Analog Devices ADV8003 Hardware Manual

ADV8003

Video Signal Processor with Motion Adaptive Deinterlacing, Scaling, Bitmap OSD, Dual HDMI Tx and Video Encoder

HARDWARE MANUAL

Rev. B

August 2013

ADV8003 Hardware Manual

TABLE OF CONTENTS

Understanding the ADV8003 Hardware Manual ............................................................................................................ 10

Description of the Hardware Manual .......................................................................................................................................... 10

Disclaimer ....................................................................................................................................................................................... 10

Trademark and Service Mark Notice ........................................................................................................................................... 10

Number Notations ......................................................................................................................................................................... 10

Register Access Conventions ........................................................................................................................................................ 10

Acronyms and Abbreviations ........................................................................................................................................................ 10

Field Function Description ........................................................................................................................................................... 13

References ........................................................................................................................................................................................ 14

1.

Introduction to the ADV8003 ................................................................................................................................. 15

1.1.

Overview .......................................................................................................................................................................... 15

1.1.1.

Digital Video Input ............................................................................................................................................................. 16

1.1.2.

Flexible Digital Core ........................................................................................................................................................... 17

1.1.3.

Video Signal Processor ....................................................................................................................................................... 17

1.1.4.

Bitmap On Screen Display ................................................................................................................................................. 18

1.1.5.

External DDR2 Memory .................................................................................................................................................... 19

1.1.6.

HDMI Transmitter.............................................................................................................................................................. 19

1.1.7.

Video Encoder ..................................................................................................................................................................... 19

1.2.

Main Features of the ADV8003 .................................................................................................................................... 19

1.2.1.

Video Signal Processor ....................................................................................................................................................... 19

1.2.1.1.

Primary VSP .......................................................................................................................................................................................... 19

1.2.1.2.

Secondary VSP ...................................................................................................................................................................................... 20

1.2.2.

OSD....................................................................................................................................................................................... 20

1.2.3.

Video Encoder ..................................................................................................................................................................... 20

1.2.4.

HDMI 1.4 Transmitter ....................................................................................................................................................... 20

1.3.

ADV8003 Functional Block Diagram .......................................................................................................................... 21

1.4.

ADV8003 Pinouts ........................................................................................................................................................... 22

1.5.

Protocol for Main I 2 C Port ............................................................................................................................................ 67

1.6.

Configuring the ADV8003 ............................................................................................................................................ 68

2.

ADV8003 Top Level Control .................................................................................................................................. 69

2.1.

ADV8003 Modes of Operation ..................................................................................................................................... 70

2.1.1.

Selecting a Mode ................................................................................................................................................................. 71

2.1.2.

Mode 1 .................................................................................................................................................................................. 71

2.1.3.

Mode 2 .................................................................................................................................................................................. 73

2.1.4.

Mode 3 .................................................................................................................................................................................. 74

2.1.5.

Mode 4 .................................................................................................................................................................................. 75

2.1.6.

Mode 5 .................................................................................................................................................................................. 76

2.1.7.

Mode 6 .................................................................................................................................................................................. 77

2.1.8.

Mode 7 .................................................................................................................................................................................. 78

2.1.9.

Mode 8 .................................................................................................................................................................................. 79

2.1.10.

Mode 9 - Bypass .................................................................................................................................................................. 80

2.1.11.

Mode 10 – Picture in Picture (PiP) (External OSD Less Than 720p).......................................................................... 81

2.1.12.

Mode 11 – PIP (External OSD Greater Than or Equal To 720p) ................................................................................. 82

2.1.13.

Mode 12 – Dual Zone OSD ............................................................................................................................................... 83

Rev. B, August 2013 2


2.1.14.

Mode 13 – OSD from HDMI RX ..................................................................................................................................... 84

2.1.15.

Mode 14 – Handling Triple Inputs ................................................................................................................................... 85

2.2.

ADV8003 Top Level Overview ..................................................................................................................................... 85

2.2.1.

Video Muxing ...................................................................................................................................................................... 85

2.2.2.

Digital Video Input ............................................................................................................................................................. 89

2.2.2.1.

Video TTL Input ................................................................................................................................................................................... 90

2.2.2.2.

EXOSD TTL Input ................................................................................................................................................................................ 90

2.2.2.3.

TTL Output ............................................................................................................................................................................................ 91

2.2.2.4.

Serial Video Rx ...................................................................................................................................................................................... 93

2.2.2.5.

Primary Input Channel ........................................................................................................................................................................ 93

2.2.2.6.

Secondary Input Channel .................................................................................................................................................................... 100

2.2.2.7.

RX Input Channel ................................................................................................................................................................................. 105

2.2.3.

Updither Configuration ..................................................................................................................................................... 106

2.2.4.

Clock Configuration ........................................................................................................................................................... 106

2.2.4.1.

PVSP Output Timing............................................................................................................................................................................ 111

2.2.4.2.

SVSP Output Timing ............................................................................................................................................................................ 111

2.2.4.3.

Frame Tracking ..................................................................................................................................................................................... 112

2.2.5.

DDR2 Interface ................................................................................................................................................................... 113

2.2.5.1.

DDR2 Configuration ............................................................................................................................................................................ 113

2.2.5.2.

DDR2 Bandwidth and Memory Selection ........................................................................................................................................ 115

2.2.5.3.

Single DDR2 Memory Configuration ................................................................................................................................................ 117

2.2.5.4.

DDR2 Loopback Test ........................................................................................................................................................................... 117

2.2.6.

I 2 C Auto Increment ............................................................................................................................................................. 118

2.2.7.

SPI Loop Through .............................................................................................................................................................. 119

2.2.8.

VBI Data Insertion ............................................................................................................................................................. 119

2.2.8.1.

Extraction Overview ............................................................................................................................................................................ 119

2.2.8.2.

Ancillary Data Extraction .................................................................................................................................................................... 120

2.2.8.3.

SPI Data Extraction .............................................................................................................................................................................. 121

2.2.8.4.

VBI Data Delay ..................................................................................................................................................................................... 121

2.2.9.

Resets .................................................................................................................................................................................... 122

2.2.10.

Image Processing Colorimetry Breakdown .................................................................................................................... 125

2.2.11.

AV-Codes ............................................................................................................................................................................. 125

2.2.12.

Color Space Conversion ..................................................................................................................................................... 130

2.2.12.1.

Primary Input Channel CSC ......................................................................................................................................................... 130

2.2.12.2.

Secondary Input Channel CSC ..................................................................................................................................................... 133

2.2.12.3.

RX Input Channel CSC .................................................................................................................................................................. 136

2.2.12.4.

HDMI Transmitter CSCs ............................................................................................................................................................... 139

2.2.13.

ADV8003 Silicon Revision ................................................................................................................................................ 142

2.2.14.

System Configuration......................................................................................................................................................... 143

3.

Video Signal Processing .......................................................................................................................................... 144

3.1.

Introduction .................................................................................................................................................................... 144

3.2.

Primary VSP .................................................................................................................................................................... 144

3.2.1.

Introduction to PVSP ......................................................................................................................................................... 144

3.2.1.1.

Autoconfiguration ................................................................................................................................................................................ 146

3.2.1.2.

Customized Input/Output Video Format Configuration ............................................................................................................... 148

3.2.1.3.

Field/Frame Buffer Number ................................................................................................................................................................ 149

3.2.1.4.

Field/Frame Buffer Address and Size ................................................................................................................................................. 149

3.2.1.5.

Frame Latency ....................................................................................................................................................................................... 151

3.2.1.6.

Game Mode ........................................................................................................................................................................................... 153



3.2.1.7.

Low Latency Mode ............................................................................................................................................................................... 154

3.2.1.8.

Freezing Output Video ......................................................................................................................................................................... 155

3.2.1.9.

Progressive Cadence Detection .......................................................................................................................................................... 155

3.2.2.

PVSP Video Input Module................................................................................................................................................. 156

3.2.2.1.

VIM Cropper ......................................................................................................................................................................................... 156

3.2.2.2.

Horizontal Down Scaler ...................................................................................................................................................................... 158

3.2.2.3.

Scaler Interpolation Mode ................................................................................................................................................................... 158

3.2.2.4.

Scaler Controls ...................................................................................................................................................................................... 159

3.2.2.5.

Pixel Packer ............................................................................................................................................................................................ 159

3.2.3.

PVSP Video Output Module ............................................................................................................................................. 160

3.2.3.1.

Pixel Unpacker ...................................................................................................................................................................................... 161

3.2.3.2.

VOM Cropper ....................................................................................................................................................................................... 161

3.2.3.3.

Motion Detection .................................................................................................................................................................................. 163

3.2.3.4.

Low Angle De-interlacing .................................................................................................................................................................... 164

3.2.3.5.

Cadence Detection ............................................................................................................................................................................... 164

3.2.3.6.

CUE Correction .................................................................................................................................................................................... 166

3.2.3.7.

Random Noise Reduction ................................................................................................................................................................... 166

3.2.3.8.

Mosquito Noise Reduction .................................................................................................................................................................. 167

3.2.3.9.

Block Noise Reduction ......................................................................................................................................................................... 168

3.2.3.10.

Sharpness Enhancement ................................................................................................................................................................ 170

3.2.3.11.

Scaler ................................................................................................................................................................................................ 170

3.2.3.12.

Panorama Mode .............................................................................................................................................................................. 172

3.2.3.13.

Output Port ...................................................................................................................................................................................... 173

3.2.3.14.

Demo Function ............................................................................................................................................................................... 177

3.2.3.15.

Progressive to Interlaced Converter............................................................................................................................................. 179

3.2.3.16.

Automatic Contrast Enhancement .............................................................................................................................................. 180

3.3.

Secondary VSP ................................................................................................................................................................ 180

3.3.1.

Introduction to SVSP ......................................................................................................................................................... 180

3.3.1.1.

Autoconfiguration ................................................................................................................................................................................ 182

3.3.1.2.

Customized Input/Output Video Format Configuration ............................................................................................................... 184

3.3.1.3.

Frame Buffer Number .......................................................................................................................................................................... 185

3.3.1.4.

Frame Buffer Address and Size ........................................................................................................................................................... 185

3.3.1.5.

Frame Latency ....................................................................................................................................................................................... 187

3.3.1.6.

Freezing Output Video ......................................................................................................................................................................... 189

3.3.2.

SVSP Video Input Module (VIM) .................................................................................................................................... 189

3.3.2.1.

VIM Cropper ......................................................................................................................................................................................... 189

3.3.2.2.

Scaler ....................................................................................................................................................................................................... 191

3.3.2.3.

Scaler Interpolation Mode ................................................................................................................................................................... 192

3.3.2.4.

VIM Miscellaneous Control ................................................................................................................................................................ 192

3.3.2.5.

Panorama Mode .................................................................................................................................................................................... 193

3.3.2.6.

Pixel Packer ............................................................................................................................................................................................ 194

3.3.3.

SVSP Video Output Module .............................................................................................................................................. 194

3.3.3.1.

Pixel Unpacker ...................................................................................................................................................................................... 195

3.3.3.2.

VOM Cropper ....................................................................................................................................................................................... 195

3.3.3.3.

Output Port ............................................................................................................................................................................................ 197

3.3.3.4.

DDR Bypass Mode ................................................................................................................................................................................ 201

3.3.3.5.

Progressive to Interlaced Converter in SVSP .................................................................................................................................... 201

3.4.

VSP Register Access Protocols ...................................................................................................................................... 202

3.4.1.

Bootup Protocol .................................................................................................................................................................. 202

3.4.2.

Reboot Protocol .................................................................................................................................................................. 203



3.4.3.

Gentle Reboot Protocol ...................................................................................................................................................... 205

3.4.4.

VOM Set Protocol ............................................................................................................................................................... 206

3.4.5.

Free Access Protocol ........................................................................................................................................................... 206

3.5.

Progressive to Interlaced Conversion .......................................................................................................................... 207

4.

On Screen Display ................................................................................................................................................... 208

4.1.

Introduction .................................................................................................................................................................... 208

4.1.1.

Features ................................................................................................................................................................................ 208

4.1.2.

OSD System Application Diagram ................................................................................................................................... 208

4.1.3.

Typical OSD Component Sizes ......................................................................................................................................... 209

4.2.

Architecture Overview ................................................................................................................................................... 209

4.2.1.

Introduction ........................................................................................................................................................................ 209

4.2.2.

Top Level Diagram ............................................................................................................................................................. 209

4.2.3.

OSD Blending ...................................................................................................................................................................... 210

4.2.4.

External Alpha Blending .................................................................................................................................................... 211

4.2.5.

OSD Core ............................................................................................................................................................................. 211

4.2.5.1.

OSD Core Region Definition .............................................................................................................................................................. 212

4.2.5.2.

OSD Color Space .................................................................................................................................................................................. 213

4.2.6.

OSD Timers ......................................................................................................................................................................... 213

4.2.7.

OSD Scaler ........................................................................................................................................................................... 217

4.2.8.

OSD Master/Slave SPI Interface ....................................................................................................................................... 217

4.2.8.1.

Overview ................................................................................................................................................................................................ 218

4.2.8.2.

SPI Slave Interface ................................................................................................................................................................................. 223

4.2.8.3.

SPI Master Interface ............................................................................................................................................................................. 225

4.2.9.

OSD Initialization ............................................................................................................................................................... 226

5.

Serial Video Receiver .............................................................................................................................................. 227

5.1.

+ 5 V Detect ..................................................................................................................................................................... 227

5.2.

TMDS Clock Activity Detection................................................................................................................................... 228

5.3.

Clock and Data Termination Control .......................................................................................................................... 229

5.4.

AV Mute Status ............................................................................................................................................................... 229

5.5.

Deep Color Mode Support ............................................................................................................................................ 229

5.6.

Video FIFO ...................................................................................................................................................................... 230

5.7.

Pixel Repetition ............................................................................................................................................................... 232

5.8.

Sync Signal Polarity Readbacks .................................................................................................................................... 233

5.9.

InfoFrame Registers ....................................................................................................................................................... 235

5.9.1.

InfoFrame Collection Mode .............................................................................................................................................. 235

5.9.2.

InfoFrame Checksum Error Flags .................................................................................................................................... 235

5.9.3.

AVI InfoFrame Registers ................................................................................................................................................... 236

5.9.4.

SPD InfoFrame Registers ................................................................................................................................................... 237

5.9.5.

MPEG Source InfoFrame Registers .................................................................................................................................. 238

5.9.6.

Vendor Specific InfoFrame Registers ............................................................................................................................... 238

5.10.

Packet Registers .............................................................................................................................................................. 239

5.10.1.

ISRC Packet Registers ......................................................................................................................................................... 239

5.10.2.

Gamut Metadata Packets ................................................................................................................................................... 241

5.11.

Customizing Packet/InfoFrame Storage Registers ..................................................................................................... 242

5.12.

HDMI Section Reset Strategy ....................................................................................................................................... 244

6.

HDMI Transmitter .................................................................................................................................................. 245



6.1.

General Controls ............................................................................................................................................................ 246

6.2.

Reset Strategy .................................................................................................................................................................. 247

6.3.

HDMI DVI Selection ..................................................................................................................................................... 248

6.4.

AV Mute ........................................................................................................................................................................... 248

6.5.

Source Product Description InfoFrame ...................................................................................................................... 249

6.6.

Spare Packets ................................................................................................................................................................... 250

6.7.

System Monitoring ......................................................................................................................................................... 252

6.7.1.

General Status and Interrupts ........................................................................................................................................... 252

6.8.

EDID/HDCP Controller Status .................................................................................................................................... 252

6.9.

EDID/HDCP Controller Error Codes ......................................................................................................................... 253

6.10.

Video Setup ..................................................................................................................................................................... 253

6.10.1.

Input Format ........................................................................................................................................................................ 253

6.10.2.

Video Mode Detection ....................................................................................................................................................... 254

6.10.3.

Pixel Repetition ................................................................................................................................................................... 255

6.10.4.

Video Related Packets and InfoFrames ............................................................................................................................ 256

6.10.5.

AVI InfoFrame .................................................................................................................................................................... 256

6.10.6.

MPEG InfoFrame ............................................................................................................................................................... 257

6.10.7.

Gamut Metadata ................................................................................................................................................................. 258

6.11.

Audio Setup ..................................................................................................................................................................... 260

6.11.1.

Audio Architecture ............................................................................................................................................................. 260

6.11.2.

Audio Configuration .......................................................................................................................................................... 261

6.11.2.1.

I2S Audio.......................................................................................................................................................................................... 263

6.11.2.2.

SPDIF Audio .................................................................................................................................................................................... 270

6.11.2.3.

DSD Audio ....................................................................................................................................................................................... 271

6.11.2.4.

HBR Audio....................................................................................................................................................................................... 271

6.11.3.

N and CTS Parameters ....................................................................................................................................................... 272

6.11.3.1.

N Parameter..................................................................................................................................................................................... 273

6.11.3.2.

CTS Parameter ................................................................................................................................................................................ 273

6.11.3.3.

Recommended N and Expected CTS Values .............................................................................................................................. 273

6.11.4.

Audio Sample Packets ........................................................................................................................................................ 275

6.11.5.

Audio InfoFrame ................................................................................................................................................................. 280

6.11.6.

ACP Packet .......................................................................................................................................................................... 280

6.11.7.

ISRC Packet ......................................................................................................................................................................... 281

6.12.

EDID Handling ............................................................................................................................................................... 283

6.12.1.

Reading the EDID ............................................................................................................................................................... 283

6.12.2.

EDID Definitions ................................................................................................................................................................ 283

6.12.3.

Additional Segments .......................................................................................................................................................... 284

6.12.4.

edid_tries Control ............................................................................................................................................................... 285

6.12.5.

EDID Reread Control......................................................................................................................................................... 285

6.13.

HDCP Handling ............................................................................................................................................................. 285

6.13.1.

One Sink and No Upstream Devices ................................................................................................................................ 285

6.13.2.

Multiple Sinks and No Upstream Devices ....................................................................................................................... 286

6.13.3.

Software Implementation .................................................................................................................................................. 288

6.13.4.

AV Mute ............................................................................................................................................................................... 290

6.14.

Audio Return Channel ................................................................................................................................................... 290

6.15.

Charge Injection Settings .............................................................................................................................................. 291

7.

Consumer Electronics Control ............................................................................................................................... 293



7.1.

Main Controls ................................................................................................................................................................. 294

7.2.

CEC Transmit Section.................................................................................................................................................... 294

7.3.

CEC Receive Section ...................................................................................................................................................... 296

7.3.1.

Logical Address Configuration ......................................................................................................................................... 296

7.3.2.

Receive Buffers .................................................................................................................................................................... 297

7.3.3.

CEC Message Reception Overview .................................................................................................................................. 300

7.4.

Antiglitch Filter Module ................................................................................................................................................ 301

7.5.

Typical Operation Flow ................................................................................................................................................. 302

7.5.1.

Initializing CEC Module .................................................................................................................................................... 302

7.5.2.

Using CEC Module as Initiator ......................................................................................................................................... 302

7.5.3.

Using CEC Module as Follower ........................................................................................................................................ 304

7.6.

Low Power CEC Message Monitoring ......................................................................................................................... 305

8.

Video Encoder ......................................................................................................................................................... 307

8.1.

Introduction .................................................................................................................................................................... 307

8.2.

Input Configuration ....................................................................................................................................................... 307

8.3.

Output Configuration .................................................................................................................................................... 310

8.4.

Additional Design Features ........................................................................................................................................... 312

8.4.1.

Output Oversampling ........................................................................................................................................................ 312

8.4.2.

Subcarrier Frequency Lock (SFL) Mode ........................................................................................................................ 313

8.4.3.

SD VCR FF/RW Synchronization ..................................................................................................................................... 313

8.4.4.

Vertical Blanking Interval .................................................................................................................................................. 314

8.4.5.

SD Subcarrier Frequency Control .................................................................................................................................... 314

8.4.5.1.

Programming the FSC ......................................................................................................................................................................... 315

8.4.6.

SD Noninterlaced Mode (240p/288p).............................................................................................................................. 315

8.4.7.

Filters .................................................................................................................................................................................... 315

8.4.7.1.

SD Filters ................................................................................................................................................................................................ 315

8.4.7.2.

ED/HD Filters ....................................................................................................................................................................................... 318

8.4.8.

ED/HD Test Pattern Generator ......................................................................................................................................... 319

8.4.9.

Color Space Conversion Matrix ........................................................................................................................................ 321

8.4.10.

ED/HD Manual CSC Matrix Adjust Feature ................................................................................................................... 321

8.4.10.1.

Programming the CSC Matrix...................................................................................................................................................... 322

8.4.11.

SD Luma and Color Scale Control ................................................................................................................................... 322

8.4.12.

SD Hue Adjust Control ...................................................................................................................................................... 324

8.4.13.

SD Brightness Detect .......................................................................................................................................................... 325

8.4.14.

SD Brightness Control ....................................................................................................................................................... 325

8.4.15.

Double Buffering ................................................................................................................................................................ 326

8.4.15.1.

ED/HD Doubling Buffering .......................................................................................................................................................... 326

8.4.15.2.

SD Doubling Buffering .................................................................................................................................................................. 326

8.4.16.

Programmable DAC Gain Control ................................................................................................................................... 327

8.4.17.

Gamma Correction ............................................................................................................................................................. 329

8.4.17.1.

ED/HD Gamma Correction ......................................................................................................................................................... 330

8.4.17.2.

SD Gamma Correction .................................................................................................................................................................. 331

8.4.18.

ED/HD Sharpness Filter and Adaptive Filter Controls.................................................................................................. 332

8.4.18.1.

ED/HD Sharpness Filter Mode ..................................................................................................................................................... 332

8.4.18.2.

ED/HD Adaptive Filters................................................................................................................................................................. 334

8.4.18.3.

ED/HD Adaptive Filter Modes ..................................................................................................................................................... 336

8.4.18.4.

ED/HD Sharpness Filter and Adaptive Filter Application Examples ...................................................................................... 337



8.4.19.

SD Digital Noise Reduction .............................................................................................................................................. 339

8.4.19.1.

Coring Gain Border ....................................................................................................................................................................... 340

8.4.19.2.

Coring Gain Data ........................................................................................................................................................................... 340

8.4.19.3.

DNR Threshold ............................................................................................................................................................................... 341

8.4.19.4.

Border Area ..................................................................................................................................................................................... 341

8.4.19.5.

Block Size Control .......................................................................................................................................................................... 342

8.4.19.6.

DNR Input Select Control ............................................................................................................................................................. 342

8.4.19.7.

DNR Mode Control ........................................................................................................................................................................ 342

8.4.19.8.

DNR Block Offset Control ............................................................................................................................................................ 343

8.4.19.9.

SD Active Video Edge Control...................................................................................................................................................... 343

8.5.

Vertical Blanking Interval.............................................................................................................................................. 345

8.6.

DAC Configurations ...................................................................................................................................................... 346

8.6.1.

Voltage Reference ................................................................................................................................................................ 346

8.6.2.

Video Output Buffer and Optional Output Filter .......................................................................................................... 346

9.

Interrupts ................................................................................................................................................................. 349

9.1.

Interrupt Pins .................................................................................................................................................................. 349

9.1.1.

Interrupt Duration .............................................................................................................................................................. 349

9.1.2.

Storing Masked Interrupts ................................................................................................................................................. 350

9.2.

Serial Video Rx Interrupts ............................................................................................................................................. 350

9.2.1.

Introduction ........................................................................................................................................................................ 350

9.2.2.

Interrupt Architecture Overview ...................................................................................................................................... 354

9.2.2.1.

Multiple Interrupt Events .................................................................................................................................................................... 355

9.2.3.

Serial Video Interrupts Validity Checking Process ........................................................................................................ 355

9.3.

VSP and OSD Section .................................................................................................................................................... 355

9.3.1.


9.4.

HDMI Tx core ................................................................................................................................................................. 356

9.4.1.

Introduction ........................................................................................................................................................................ 356

9.4.2.


9.4.3.

HDMI Tx Interrupt Polarity.............................................................................................................................................. 357

Appendix A ........................................................................................................................................................................ 358

PCB Layout Recommendations.................................................................................................................................................... 358

Analogue/Digital Video Interface Outputs ...................................................................................................................................... 358

External DDR2 Memory Requirements ........................................................................................................................................... 358

Power Supply Bypassing ..................................................................................................................................................................... 359

General Digital Inputs and Outputs ................................................................................................................................................. 360

XTAL and Load Cap Value Selection ................................................................................................................................................ 360

Encoder Component Placement ....................................................................................................................................................... 361

HDMI Transmitter Component Placement ..................................................................................................................................... 361

Power Supply Design and Sequencing.............................................................................................................................................. 361

Appendix B ........................................................................................................................................................................ 363

ADV8003 Evaluation Board Schematics ..................................................................................................................................... 363

Appendix C ....................................................................................................................................................................... 393

ADV8003 Evaluation Board Layout ............................................................................................................................................ 394

Appendix D ....................................................................................................................................................................... 402

Package Outline Drawing .............................................................................................................................................................. 402

Appendix E ........................................................................................................................................................................ 403

Unused Pin List .............................................................................................................................................................................. 403



Appendix F ........................................................................................................................................................................ 416

Pixel Input and Output Formats................................................................................................................................................... 416

List of Figures .................................................................................................................................................................... 431

List of Tables ..................................................................................................................................................................... 435

List of Equations ............................................................................................................................................................... 437

Revision History ............................................................................................................................................................... 438



UNDERSTANDING THE ADV8003 HARDWARE MANUAL

DESCRIPTION OF THE HARDWARE MANUAL

This manual provides a detailed description of the functionality and features supported by the ADV8003.

DISCLAIMER

The information contained in this document is proprietary of Analog Devices Inc. (ADI). This document must not be made available to anybody other than the intended recipient without the written permission of ADI.

The content of this document is believed to be correct. If any errors are found within this document or, if clarification is needed, contact the authors at [email protected].

TRADEMARK AND SERVICE MARK NOTICE

The Analog Devices logo is a registered trademark of Analog Devices, Inc. All other brand and product names are trademarks or service marks of their respective owners.

NUMBER NOTATIONS

Notation bit N

V[X:Y]

0xNN

0bNN

NN

Description

Bits are numbered in little endian format, that is, the least significant bit of a number is referred to as Bit 0

Bit field representation covering bit X to Y of a value or a field V

Hexadecimal (base-16) numbers are preceded by the prefix ‘0x’

Binary (base-2) numbers are preceded by the prefix ‘0b’

Decimal (base-10) are represented using no additional prefixes or suffixes

REGISTER ACCESS CONVENTIONS

Mode

R/W

R

W

Description

Memory location has read and write access.

Memory location has read access only. A read always returns 0 unless specified otherwise.

Memory location has write access only.

ACRONYMS AND ABBREVIATIONS

This is a list of common acronyms and abbreviations found in Analog Devices Hardware Manuals.

Acronym/Abbreviation Description

ACP Audio Content Protection

ACR

ADC

AFE

AGC

Ainfo

AKSV

An

ARC

AUD_IN

AVI

Aux

Bcaps

Rev. B, August 2013

Audio Clock Regeneration

Analog to Digital Converter

Analog Front End

Automatic Gain Control

HDCP register. Refer to HDCP documentation.

HDCP Transmitter Key Selection Vector. Refer to HDCP documentation.

64-bit pseudo-random value generated by HDCP cipher function of device A

Audio Return Channel

Audio Input Pin

Auxiliary Video Information

Auxiliary

HDCP register. Refer to HDCP documentation.

10


BGA Ball Grid Array

ED

ENC

EQ

FFS

FRC

HBR

HD

HDCP

DNR

DPP

DSD

DST

DUT

DVD

DVI

EAV

CVBS

DCM

DDR

DDFS

DE

DID

DLL

DMA

BKSV

BNR

CEC

CP

CSC

CSync

CTS

CUE

ISRC

I 2 S

I 2 C

KSV

LLC

LQFP

LSB

L-PCM

Mbps

MNR

HDMI

HDTV

HEAC

HEC

HPA

HPD

HSync/HS

IC

HDCP Receiver Key Selection Vector. Refer to HDCP documentation.

Block Noise Reduction

Consumer Electronics Control

Component Processor

Color Space Converter/Conversion

Composite Synchronization

Cycle Time Stamp

Color Upsampling Error

Composite Video

Decimation

Double Data Rate

Direct Digital Frequency Synthesizer

Data Enable

Data Identification Word

Delay Locked Loop

Direct Memory Access

Digital Noise Reduction

Data Preprocessor

Direct Stream Digital

Direct Stream Transfer

Device Under Test (designate the ADV8003 unless stated otherwise)

Digital Video Disc

Digital Visual Interface

End of Active Video

Enhanced Definition

Encoder

Equalizer

Field Frame Scheduler

Frame Rate Conversion/Converter

High Bit Rate

High Definition

High Bandwidth Digital Content Protection

High Bandwidth Multimedia Interface

High Definition Television

HDMI Ethernet and Audio Channels

HDMI Ethernet Channel

Hot Plug Assert

Hot Plug Detect

Horizontal Synchronization

Integrated Circuit

International Standard Recording Code

Inter IC Sound

Inter Integrated Circuit

Key Selection Vector

Line Locked Clock

Low-profile Quad Flat Package

Least Significant Bit

Linear Pulse Code Modulation

Megabit per Second

Mosquito Noise Reduction



SPI

SRM

SSPD

STDI

SVSP

TBC

TMDS

Tx

SDR

SMPTE

SNR

SOG

SOY

SPA

SPD

SPDIF

ULAI

US

VBI

VDP

VIC

VIM

VOM

VSDP

VSP

VSync/VS

PVSP

Ri’

RNR

Rx

SA

SAV

SD

SDP ms

MSB

NC

NSV

OSD

OTP

PtoI

Pj’

XTAL


MPEG Moving Picture Expert Group

Millisecond

Most Significant Bit

No Connect

Noise Shaped Video

On Screen Display

One Time Programmable

Progressive to Interlaced

HDCP Enhanced Link Verification Response. Refer to HDCP documentation.

Primary VSP

HDCP Link verification response. Refer to HDCP documentation.

Random Noise Reduction

Receiver

Slave Address

Start of Active Video

Standard Definition

Standard Definition Processor

Single Data Rate

Society of Motion Picture and Television Engineers

Signal to Noise Ratio

Sync on Green

Sync on Y

Source Physical Address

Source Production/Product Descriptor

Sony/Philips Digital Interface

Serial Peripheral Interface

System Renewability Message

Synchronization Source Polarity Detector

Standard Identification

Secondary VSP

Timebase Correction

Transition Minimized Differential Signaling

Transmitter

Ultra Low Angle Interpolation

Up Sampling

Video Blanking Interval

VBI Data Processor

Video Identification Code

Video Input Module

Video Output Module

Vendor Specific Data Block

Video Signal Processor/Processing

Vertical Synchronization

Crystal Oscillator




FIELD FUNCTION DESCRIPTION

The function of a field is described in a table preceded by the bit name, a short function description, the I 2 C map, the register location within the I 2

C map, and a detailed description of the field. Refer to Figure 1 for more details.

The detailed description consists of:

• For a readable field, the values the field can take

• For a writable field, the values the field can be set to

The name of the field. In this example the field is called deep_color_mode and is 2 bits long.

I2C location of the field in big endian format

(MSB first, LSB last)

Read/Write

Access for field deep_color_mode[1:0] , HDMI RX Map, Address 0xE20B[7:6] (Read Only)

A readback of the deep color mode information extracted from the general control packet.

Function deep_color_mode[1:0] Description

00 

01

10

11

8-bits per channel

10-bits per channel

12-bits per channel

16-bits per channel (not supported)

Detailed description of the field

Values the field can be set to or take. These values are in binary format if not preceded by ‘0x’ and in hexadecimal format if preceded by

‘0x’.

Default value indicated by 

Figure 1: Field Description Format



REFERENCES

HDMI Licensing and LLC, High-Definition Multimedia Interface, Revision 1.4a, March 4, 2010

Digital Content Protection (DCP) LLC, High-bandwidth Digital Content Protection System, Revision 1.3, December 21, 2006

CEA, CEA-861-E, A DTV Profile for Uncompressed High Speed Digital Interfaces, Revision E, September 11, 2007

ITU, ITU-R BT.656-4, Interface for Digital Component Video Signals in 525-Line and 625-Line Television Systems Operating at the 4:2:2

Level of Recommendation ITU-R BT.601, February 1998

ITU, ITU-R BT.601-5 Studio encoding parameters of digital television for standard 4:3 and widescreen 16:9 aspect ratios, December 1995

ITU, ITU-R BT.709-5 Parameter values for the HDTV standards for production and international programme exchange, April 2002

CENELEC, EN 50157, Part 1, Domestic and similar electronic equipment interconnection requirements: AV.link

CENELEC, EN 50157, Part 2-1, Domestic and similar electronic equipment interconnection requirements: AV.link





1.

INTRODUCTION TO THE ADV8003

1.1.

OVERVIEW

The ADV8003 is a video signal processor (VSP) with TTL and Serial Video inputs that can de-interlace and scale input video, generate and blend a bitmap based on-screen display (OSD) and output the blended video using one or more of the part’s outputs; dual HDMI transmitters and a 6-DAC encoder with SD and HD support.

The ADV8003 has three video inputs – the video TTL input, the EXOSD TTL input and the Serial Video receiver (Rx). The combined video TTL input and EXOSD TTL input constitute the flexible 60-bit TTL input port. The 60-bit TTL input port can be arranged in a variety of fashions to accept one input video stream (for example, a 48-bit 3 GHz input video stream from ADV7619) or two input video streams (for example, a 36-bit input video stream from ADV7844 and a 24-bit input video stream from an external OSD generator). Once the data is received, the video TTL and EXOSD TTL inputs can be connected to either the primary input channel or the secondary input channel. From these input channels, the video data can be sent to the internal video processing blocks (for example, primary VSP or secondary VSP).

The Serial Video Rx is connected to the RX input channel. The Serial Video Rx accommodates inter-chip transfer of data over an HDMI compatible interface (for example, from an HDMI (Rx) such as ADV7850 or transceiver such as ADV7623). The ADV8003 does not support EDID or DDC activity on this port.

The motion adaptive de-interlacer in the ADV8003 provides excellent edge detection and excellent ultra-low angle performance. Per-pixel motion-adaptive de-interlacing is used for natively interlaced input video (for example, a live sport broadcast) where still parts of the image are reconstructed from information on both the odd and even fields, and moving parts of the image are interpolated by an advanced interpolation algorithm. The de-interlacer can also recognize when interlaced input video originally came from progressive content (for example, 24 Hz movie content or 30 Hz documentary content) and reconstructs the original frames.

Dual video scalers allow the ADV8003 to support two different output resolutions on its outputs, for example, 1080p60 on HDMI TX1 and 720p on HDMI TX2 and the HD encoder. The primary VSP (PVSP) in the ADV8003 is capable of upscaling from 480i to 4k x 2k formats. The secondary VSP (SVSP) in the ADV8003 is used to provide a second output resolution to accommodate dual zone systems.

Also available in the ADV8003 are image enhancing features such as random noise reduction (RNR), mosquito noise reduction (MNR) and block noise reduction (BNR), detail enhancement and automatic contrast enhancement (ACE).

The ADV8003 features an internal bitmap based OSD generator capable of generating OSDs of up to 4k x 2k. External solutions can also be implemented and fed into the ADV8003 for blending with the main video. A bitmap based OSD is an advanced form of OSD display, which can add effects such as scrolling, animation and 3D depth to OSD displays. This allows customers to create advanced OSD designs to differentiate their products. Once created, OSD designs are stored in an external SPI flash memory connected to the ADV8003. The control of the OSD must be performed from the system microcontroller via SPI. OSD designs can be created using ADI’s software development tool, Blimp OSD .

The ADV8003 offers flexible configuration of its internal circuitry allowing the output of one, two or three input channels simultaneously.

Video can be output from the ADV8003 via one or both of the HDMI transmitters and the 6-DAC SD/HD video encoder. Both HDMI transmitters support the HDMI v1.4 specifications of increased resolutions, 3D video and audio return channel (ARC). The ADV8003 also integrates an HDMI v1.4 CEC controller that supports the capability discovery and control (CDC) feature. The ADV8003 supports both S/PDIF and 6-channel I 2 S audio. Its high fidelity 6-channel I 2 S can transmit either stereo or 5.1 surround audio up to 768 kHz. The

S/PDIF can carry compressed audio including Dolby Digital, DTS, and THX. Direct Stream Digital (DSD) audio signals can also be input on one of six DSD audio inputs.

The ADV8003 includes a high-speed digital-to-analog video encoder. Six high speed, Noise Shaped Video (NSV), 12-bit video DACs provide support for composite (CVBS), S-video (Y/C), and component (YPrPb/RGB) analog outputs in either SD, ED, or HD video formats up to 1080p. In addition, simultaneous SD and ED/HD formats are supported. 216 MHz (SD and ED) and 297 MHz (HD) oversampling ensures that external output filtering is not required.



The ADV8003 supports all common consumer formats as outlined in the EIA-861 specification and many common professional output formats as outlined in the VESA specification.

The part supports the I2C® and SPI protocols for communication with the system microcontroller.

Note: There are seven options within the ADV8003 family of parts, each with different capabilities but all in the same CSPBGA-425

package. These are described in Table 1 .

Part Number

ADV8003KBCZ-8

ADV8003KBCZ-8B

ADV8003KBCZ-8C

ADV8003KBCZ-7

Table 1: Available Features Within ADV8003 Family of ICs

Maximum Speed Maximum Video HDMI TX Outputs Analog Outputs VSP

3 Gbps 4k × 2k at 30 Hz (8-bit) 2 Six 12-bit DACs Yes

3 Gbps

3 Gbps

2.25 Gbps

4k × 2k at 30 Hz (8-bit)

4k × 2k at 30 Hz (8-bit)

UXGA (162 MHz)

1

2

2

No

No

Six 12-bit DACs

Yes

Yes

Yes

OSD

Yes

Yes

Yes

Yes

TTL Out

Yes

No

No

Yes

ADV8003KBCZ-7B

ADV8003KBCZ-7C

2.25 Gbps

2.25 Gbps

UXGA (162 MHz)

UXGA (162 MHz)

1

2

No

No

Yes

Yes

Yes

Yes

No

No

ADV8003KBCZ-7T 2.25 Gbps UXGA (162 MHz) 0 No Yes Yes Yes

Note that ADV8003KBCZ-8/7 functionality is described throughout this manual (figures, functional blocks, and so on). Some sections of this manual are not relevant to the ADV8003KBCZ-8B/7B, ADV8003KBCZ-8C/7C and ADV8003KBCZ-7T as they do not include those blocks. If a section is not relevant to a particular generic, this is indicated in the introduction to that section.

1.1.1.

Digital Video Input

Video data can be input into the ADV8003 in a number of ways. The flexible 60-bit TTL input port can be configured for dual video inputs (video TTL input and EXOSD TTL input), for a single video input (interleaved TTL data from an ADV7619 ) or for a single video input and an external alpha channel. The 60-bit TTL input port is extremely flexible and can be configured into a number of different

arrangements; for more information, refer to Table 95

and Table 96 . Video can also be input into the ADV8003 via the Serial Video Rx

which can be used for device to device interconnect, for example, a serial video link between the ADV7850 and the ADV8003 or a serial video link between the ADV7623 and the ADV8003. Using such front end devices located before the ADV8003 allows the audio to be extracted and processed in a DSP before being reinserted into the ADV8003.

A mux after the TTL inputs allows the video TTL input pins and the EXOSD TTL input pins to be connected to either the primary or the secondary input channel. The primary input channel features an input formatter, manually programmable CSC, updither function, ACE, contrast, brightness and saturation controls. The secondary input channel features an input formatter, manually programmable CSC and updither function. The Serial Video Rx is connected directly to the Rx input channel and features an input formatter, manually programmable CSC and updither function.



ADV8003

Secondary

Input

Channel

INPUT

FMT

DITHER

+CSC

EXOSD

60-bit

TTL

Input Video

Video 36/48

36-bit

-bit Input

Input

Primary

Input

Channel

INPUT

FMT

High Speed eed

O

148.5MHz to

300MHz

Conversion

DITHER

+CSC

+ACE

E

I Rx eo

High Speed

RX

Input

Channel

INPUT

FMT

DITHER

+CSC

Figure 2: ADV8003 Digital Video Interface

1.1.2.

Flexible Digital Core

The ADV8003 has a flexible digital core, allowing multiple options for the routing of video data. This allows the user to place the OSD in front of the video processing so the OSD will be overlaid on one or more outputs. Alternatively, video processing can be placed before the

OSD ensuring all outputs are processed to the highest quality. The digital core can also be configured so that the ADV8003 can output one or all of the inputs in various arrangements, for example, picture in picture with one input appearing as a window within another or two inputs routed to two outputs.

Several common modes of operation are defined to assist the user to quickly integrate the ADV8003 into a system. Refer to Section 2 for

more details.

1.1.3.

Video Signal Processor

The motion adaptive de-interlacer in the ADV8003 offers excellent edge detection and ultra low angle performance. The per-pixel deinterlacing algorithm used delivers excellent performance which can be seen with specialist test patterns, on facial features like eyebrows or on shirt collars. This algorithm decides on whether an area of an image is moving or not and then applies the appropriate de-interlacing approach accordingly. The de-interlacer can also determine when interlaced video originated as progressive and can reconstruct the original frames.

De-interlacer Enhance

Figure 3: ADV8003 Video Processing

The ADV8003 features dual scalers referred to as primary PVSP and SVSP. The PVSP uses a contour-based interpolation scaler which can upscale from 480i to 4k x 2k. It can also arbitrarily up and down scale between 480i and 1080p. The advanced scaling algorithm used in the ADV8003 eradicates many common problems associated with scaling video such as ringing and jagged or blurred edges. The SVSP


ADV8003 Hardware Manual can be used to provide a second lower resolution output format. The PVSP and SVSP can be connected in parallel or in series.

The ADV8003 features a number of video enhancement controls such as detail enhancement, block noise reduction, mosquito noise reduction and random noise reduction. Block and mosquito noise are related to the compression of video for transmission or encoding onto a DVD or BD disc. Random noise is related to noise picked up during the transmission of video. The automatic contrast enhancement feature offered by the ADV8003 intelligently stretches the brightness of an image to enhance the dark areas without saturating the dark areas.

Note that the dual scaler variants of the ADV8003 are the following:

• ADV8003KBCZ-8/7

• ADV8003KBCZ-8C/7C

The single scaler variants of the ADV8003 are the following:

• ADV8003KBCZ-8B/7B

• ADV8003KBCZ-7T

1.1.4.

Bitmap On Screen Display

The AD8003 incorporates an OSD core capable of generating an internal bitmap based OSD. Customers can generate elaborate OSD designs that can include bitmap images, 3D overlay and animation. Up to 256 regions in total can be created and displayed. These 256 regions are bitmap images defined during the design stage and can be characters, pictures, buttons and so on. Individual regions can be alpha blended and prioritized versus other regions.

SPI

Internal

OSD Generator

Figure 4: ADV8003 Bitmap OSD

The OSD is controlled by the host microcontroller via the ADV8003 SPI slave (serial port 1). In response to commands, the ADV8003 loads the data from the external SPI flash memory via the SPI master (serial port 2). The ADV8003 uses DDR2 memory when rendering and blending the OSD. In order to lower the load of the DDR2 memory, there is a block in the ADV8003 OSD hardware called the OSD co-processor. The OSD co-processor is responsible for handling upper level commands from the microcontroller and translating them into lower level operations for the OSD and DMA which retrieves data from the external DDR2 memories.

The OSD blend can be switched between either of the two video streams routed through the OSD blend block without disturbing the output video. This enables seamless OSD blending in dual zone systems.

Bitmap OSDs can be created and compiled using ADI’s software development tool, Blimp OSD . This allows users to create their custom

OSDs and emulate them before integrating them into their system, abstracting the design task from the underlying OSD hardware. For more details on the operation of the external OSD, design and system techniques, refer to the Blimp OSD documentation.



1.1.5.

External DDR2 Memory

Figure 5: External DDR2 Memory Interface

External DDR2 memory is required for motion adaptive de-interlacing, Frame Rate Conversion (FRC), and OSD bitmap overlay.

ADV8003 supports various memory options using one or two DDR2 memories of various sizes (1 Gb maximum). For full processing capabilities, two DDR2 memories are required which use data transfers up to 250 MHz. Refer to Section

3 for more details on the

operations using the external DDR2 memory.

1.1.6.

HDMI Transmitter

The ADV8003 features two HDMI v1.4 transmitters. The transmitters feature an audio return channel (ARC), which allows a Sony/Philips

Digital Interface (SPDIF) audio connection between the source and sink. A CEC controller and buffer help reduce design time and processor overheads. Each transmitter features an on-chip MPU with an I 2 C master to perform HDCP operations and EDID operations.

Note : The dual transmitter variants of the ADV8003 are ADV8003KBCZ-8/7 and ADV8003KBCZ-8C/7C. The single transmitter variants of the ADV8003 are ADV8003KBCZ-8B/7B. The ADV8003KBCZ-7T does not feature any HDMI transmitters.

1.1.7.

Video Encoder

The ADV8003 features a high speed digital to analog video encoder. Six high speed, NSV, 3.3 V, 12-bit video DACs provide support for worldwide composite (CVBS), S-Video (Y-C), and component (YPrPb/RGB) analog outputs in standard definition (SD), enhanced definition (ED), or high definition (HD) video formats. It is also possible to enable the ADV8003 video encoder to work in simultaneous mode where both an SD and ED/HD format are being output.

Note : The video encoder variants of the ADV8003 is ADV8003KBCZ-8/7. The variants of ADV8003 with no encoder are

ADV8003KBCZ-8B/7B, ADV8003KBCZ-8C/7C and ADV8003KBCZ-7T.

1.2.

MAIN FEATURES OF THE ADV8003

1.2.1.

Video Signal Processor

1.2.1.1.

Primary VSP

• 12-bit internal processing

• Fixed frame latency capability

• Input timing up to 1080p

• Output timing up to 4k x 2k for ADV8003KBCZ-8x derivatives

• Input/output format YCbCr at 4:4:4

• Motion adaptive de-interlacing with motion detection

• Ultra low angle interpolation on edge regions of interlaced video

• Cadence detection (any cadence detection possible)

• Progressive cadence supported

• Super resolution video scaler

• Aspect ratio conversion/panorama scaling

• Arbitrary upscaling and downscaling for both horizontal and vertical direction

• Sharpness detail and edge enhancement



• Noise reduction for random, mosquito, and block noise

• Frame Rate Conversion

• Color Upsampling Error (CUE) correction

• Progressive to interlaced (PtoI) converter

• Game mode supported

• Album mode supported

• Demo window

1.2.1.2.

Secondary VSP

• 8-bit internal processing

• Input and output timing up to 1080p

• Input and output format YCbCr at 4:4:4

• Up-scaling and down-scaling for both horizontal and vertical direction

• Aspect ratio conversion and panorama scaling

• Frame Rate Conversion

• Progressive to interlaced (PtoI) converter

1.2.2.

OSD

• Internally generated bitmap based OSD allowing overlay of bitmap images on one or more video outputs

• Dual video paths through the OSD blend block to support dual zone OSD

• Dedicated OSD scaler – allows OSDs to be rendered at a single resolution reducing external memory bandwidth

• Blending onto 3 GHz video formats for ADV8003KBCZ-8x derivatives

• Pixel-by-pixel alpha blending of OSD data on video data

• Option of externally generated OSD

• OSD can be overlaid in the main 3D video format timings

• Blimp OSD software tool and provided ANSI-C libraries cover the full design flow of any OSD

1.2.3.

Video Encoder

• Six NSV 12-bit video DACs

• Compliant with all common SMPTE formats

• Multiformat video output support o

NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support o

Composite (CVBS) and S-Video (Y/C) component/YPrPb/RGB (SD, ED and HD)

• Macrovision® Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant

• Simultaneous SD and ED/HD operation

1.2.4.

HDMI 1.4 Transmitter

• 3 GHz video output (ADV8003KBCZ-8 models only)

• Incorporates HDMI™ (v.1.4 with Deep Color, x.v.Color™) o

Content Type Bits o

CEC 1.4 controller o

ARC (Audio Return Channel) Support o

3D support

• Supports standard S/PDIF for stereo LPCM compressed audio up to 192 kHz

• Six-channel uncompressed LPCM I2S audio up to 192 kHz

• Six-channel DSD audio inputs


1.3.

ADV8003 FUNCTIONAL BLOCK DIAGRAM

ON

OSD

LLER

R

I/O, OSD, ENCODER

VSP, HDMI Tx

REGISTER MAPS

SPI

MASTER I 2 C SLAVE

HDMI Tx

VIDEO DATA

CAPTURE

HDMI Tx

VIDEO DATA

CAPTURE

AUDIO DATA CAPTURE

4:2:2 4:4:4

AND

COLOR SPACE

CONVERTER

4:2:2 4:4:4

AND

COLOR SPACE

CONVERTER

HDCP AND EDID

UNCONTROLLER

CEC

CONTROL

I 2 C

MASTER

CEC1

CEC2

DDC1_SC L

DDC1_SD A

DDC2_SC L

DDC2_SD A

HPD_TX1

HPD_TX2

HDCP

ENCRYPTION

HDCP

KEYS

TMDS

OUTPUTS

TX1_0+

TX1_0–

TX1_1+

TX1_1–

TX1_2+

TX1_2–

TX1_C+

TX1_C–

HDCP

ENCRYPTION

HDCP

KEYS

TMDS

OUTPUTS

TX2_0+

TX2_0–

TX2_1+

TX2_1–

TX2_2+

TX2_2–

TX2_C+

TX2_C–

PROGRAMMABLE

HDTV FILTERS

SHARPNESS AND

ADAPTIVE FI LTER

CONTROL

PROGRAMMABLE

LUMINANCE

FILTERS

PROGRAMMABLE

CHROMINANCE

FILTERS

ENCODER

SYNC

INSERTION

SIN/COS

MODULA-

TION/COS

VBI DATA SERVICE

INSERTION

SUBCARRIER

FREQ LOCK

12-BIT

DAC1

12-BIT

DAC2

12-BIT

DAC3

12-BIT

DAC4

12-BIT

DAC5

12-BIT

DAC6

REFERENCE

AND CABLE

DETECTION

DAC1

DAC2

DAC3

DAC4

DAC5

DAC6

21

Figure 6: ADV8003 Block Diagram

Rev. B, August 2013



1.4.

ADV8003 PINOUTS

A

B

C

D

E

1

OSD_

IN[23]/

EXT_

DIN[7]

OSD_

IN[21]/

EXT_

DIN[5]

2

OSD_

DE

OSD_

IN[22]/

EXT_

DIN[6]

OSD_

IN[19]/

EXT_

DIN[3]

OSD_

IN[16]/

EXT_

DIN[0]

OSD_

IN[20]/

EXT_

DIN[4]

OSD_

IN[17]/

EXT_

DIN[1]

OSD_

IN[13]/

VBI_SCK

OSD_

IN[14]/

VBI_MOSI

3

OSD_

CLK/

EXT_

CLK

OSD_

VS

GND

OSD_

IN[18]/

EXT_

DIN[2]

OSD_

IN[15]/

VBI_CS

4

AUD_

IN[1]

AUD_

IN[0]

AUD_

IN[4]

GND

DVDD_

IO

5

AUD_

IN[2]

AUD_

IN[3]

DSD_

CLK

6

AUD_

IN[5]

SFL

SCLK

DVDD_

IO

MCLK

7 8 9

ARC2_

OUT

MOSI1 SCK2

SCL

SDA

SCK1

CS1

GND

GND

10

CS2

INT0

INT1

11

PDN

12

GND

13

RESET XTALN PVDD2

ARC1_

OUT

MISO1 MOSI2 MISO2 ALSB XTALP PVDD1

GND

INT2

DVDD_

IO

TEST1

F

OSD_

IN[9]

OSD_

IN[10]

OSD_

IN[11]

OSD_

IN[12]

14

NC

NC

NC

NC

G

H

J

K

L

OSD_

IN[5]

OSD_

IN[6]

OSD_

IN[7]

OSD_

IN[8]

OSD_

IN[1]

OSD_

IN[2]

OSD_

IN[3]

OSD_

IN[4]

DE

VS

P[32]

HS

OSD_

HS

OSD_

IN[0]

PCLK

DVDD_

IO

DVDD_

IO

P[33] P[34] P[35]

GND

GND

GND

GND

GND

DVDD GND

GND

DVDD GND

GND DVDD

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND DVDD GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

M P[28] P[29] P[30] P[31]

N

P

R

T

P[24] P[25] P[26] P[27]

P[20] P[21] P[22] P[23]

P[16] P[17] P[18] P[19]

P[14] P[15] GND GND

GND GND GND GND GND GND GND GND


DVDD GND GND GND GND GND GND GND



15 16 17 18 19 20 21 22 23

NC

CVDD1 RX_CN RX_0N RX_1N RX_2N CVDD1 RSET1 VREF A

NC

GND RX_CP RX_0P RX_1P RX_2P GND COMP1 DAC4 B

NC

RX_

HPD

AVDD1 GND

NC

RX_5V NC

GND AVDD1 AVDD1 DAC5 DAC6

C

NC RTERM AVDD2 AVDD2 DAC1 DAC2

D

GND GND GND

GND GND GND

GND GND DVDD

GND GND

GND GND

GND

GND

GND GND GND

GND GND GND

GND GND DVDD

GND GND GND

GND GND GND

TEST2 GND COMP2 DAC3

E

RSET2 PVDD3 GND CEC1 F

ELPF1 ELPF2 GND AVDD3 G

GND GND TX1_2+ TX1_2– H

DDC1_

SDA

GND TX1_1+ TX1_1–

DDC1_

SCL

HPD_

TX1

GND

GND

TX1_0+

TX1_C+

TX1_0–

TX1_C–

R_TX1 PVDD5

HEAC_

1+

HEAC_

1–

J

K

L

M

CEC2 PVDD5 AVDD3 NC N

DDC2_

SCL

DDC2_

SDA

HPD_

TX2

GND TX2_2+ TX2_2–

GND TX2_1+ TX2_1–

GND TX2_0+ TX2_0–

P

R

T

U P[10] P[11] P[12] P[13] GND GND DVDD GND GND DVDD GND GND DVDD GND GND R_TX2 GND TX2_C+ TX2_C– U

V P[6] P[7] P[8] P[9] GND PVDD6

HEAC_

2+

HEAC_

2–

V

TEST3 PVDD6 AVDD3 NC W W

P[2] P[3] P[4] P[5]

Y

AA

P[0]

DDR_

DQ[18]

P[1]

GND

DDR_

DQS[2]

GND

GND

DDR_

DQ[23]

DVDD_

DDR

DDR_

DQS[3]

GND

DDR_

DQS[2]

DDR_

DQ[26]

DVDD_

DDR

DDR_

DQS[3]

NC/

GND

AB

DDR_

DQ[21]

DDR_

DQ[19]

DDR_

DQ[17]

DDR_

DM[2]

DDR_

DQ[30]

DDR_

DM[3]

DDR_

DQ[31]

DDR_

DQ[29]

AC

DDR_

DQ[16]

DDR_

DQ[20]

DDR_

DQ[22]

DDR_

DQ[25]

DDR_

DQ[28]

DDR_

DQ[27]

DDR_

DQ[24]

DDR_

A[9]

1 2 3 4 5 6

DDR_

A[11]

DVDD_

DDR

DDR_

A[4]

DDR_

A[8]

DVDD_

DDR

DDR_

A[2]

DDR_

A[12]

DDR_

A[6]

GND

GND

DDR_

A[3]

DDR_

A[0]

DDR_

A[5]

DDR_

A[7]

DDR_

A[1]

DDR_

A[10]

DDR_

CAS

DVDD_

DDR

DDR_

CS

DVDD_

DDR

DDR_

BA[0]

DDR_

BA[1]

DDR_

RAS

DDR_

BA[2]

DDR_

CK

DDR_

CK

DDR_

CKE

DDR_

WE

GND

GND

DDR_

VREF

DDR_

DQ[9]

DVDD_

DDR

DDR_

DQ[14]

DDR_

DQ[11]

DDR_

DQ[12]

DDR_

DQS[1]

DDR_

DQ[10]

DVDD_

DDR

DDR_

DQ[8]

DDR_

DQS[1]

DDR_

DM[1]

GND

DDR_

DM[0]

DDR_

DQ[13]

DDR_

DQ[0]

DDR_

DQ[15]

DDR_

DQ[7]

DDR_

DQ[6]

PVDD_

DDR

GND

DDR_

DQ[5]

DDR_

DQ[2]

GND

DDR_

DQS[0]

DDR_

DQS[0]

GND

DDR_

DQ[3]

DDR_

DQ[4]

DDR_

DQ[1]

19 20 21 22 23 7 8 9 10 11 12 13 14 15 16 17 18

Figure 7. ADV8003KBCZ-8 and ADV8003KBCZ-7 Pin Configuration

Y

AA

AB

AC



A4

A5

A6

A7

A8

A9

A10

A11

Table 2. ADV8003KBCZ-8 and ADV8003KBCZ-7 Pin Function Descriptions

Pin

No.

A1

A2

A3

A12

A13

A23

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

A14

A15

A16

A17

A18

A19

A20

A21

A22

B13

B14

Mnemonic

OSD_IN[23]/EXT_DIN[

7]

OSD_DE

OSD_CLK/EXT_CLK

AUD_IN[1]

AUD_IN[2]

AUD_IN[5]

ARC2_OUT

MOSI1

SCK2

CS2

RESET

XTALN

PVDD2

NC

NC

CVDD1

RX_CN

RX_0N

RX_1N

RX_2N

CVDD1

RSET1

VREF

OSD_IN[21]/EXT_DIN[

5]

OSD_IN[22]/EXT_DIN[

6]

OSD_VS

AUD_IN[0]

AUD_IN[3]

SFL

ARC1_OUT

MISO1

MOSI2

MISO2

ALSB

XTALP

PVDD1

NC

Type

OSD video input/ miscellaneous digital

Description

External OSD Video Pixel Input Port (OSD_IN[23])/Additional TTL Input for External

CCIR 656 Video Data (EXT_DIN[7]).

OSD video sync

OSD video sync

Audio input

Audio input

I

I

Data Enable for the OSD Input Port.

Pixel Clock for the OSD Input Port (OSD_CLK)/Pixel Clock for External Video Data

(EXT_CLK).

2

2

S0/DSD1 Audio Input.

S1/DSD2 Audio Input.

Audio input

Audio output

LRCLK/DSD5 Audio Input.

Audio Return Channel for HDMI Tx2.

Serial port control Master Out Slave In (Serial Port 1). Serial Port 1 is used for OSD control.

Serial port control Serial Clock (Serial Port 2). Serial Port 2 is used for the external flash ROM.

Serial port control Chip Select (Serial Port 2). Serial Port 2 is used for the external flash ROM.

Miscellaneous digital


1

Power

Reset Pin for the ADV8003.

Crystal Input.

No connect

No connect

Power

Rx input

PLL Digital Supply Voltage (1.8 V ).

Do not connect to this pin.


Comparator Supply Voltage (1.8 V).

Rx Clock Complement Input.

Rx input

Rx input

Rx input

Power

Rx Channel 0 Complement Input.




Miscellaneous

analog 1

Miscellaneous

analog 1



Resistor Current Setting for Encoder DACs: DAC1, DAC2, and DAC3. The RSET resistor should be placed as close as possible to the ADV8003.

Optional External Voltage Reference Input for DACs or Voltage Reference Output.

Place VREF voltage components as close as possible to the ADV8003.





OSD video sync

Audio input

Audio input

SFL

Audio output

Vertical Sync for the OSD Input Port.

S/PDIF/DSD0 Audio Input.

I 2 S2/DSD3 Audio Input.

Subcarrier Frequency Lock Signal (SFL).


Serial port control Master In Slave Out (Serial Port 1). Serial Port 1 is used for OSD control.

Serial port control Master Out Slave In (Serial Port 2). Serial Port 2 is used for the external flash ROM.

Serial port control Master In Slave Out (Serial Port 2). Serial Port 2 is used for the external flash ROM.

I 2 C control Sets LSB of ADV8003 I 2 C address (0x18 with LSB low, 0x1A with LSB high).

ADV8003 Crystal Input. Miscellaneous

digital 1

Power

No connect

PLL Analog Supply Voltage (1.8 V).




C3

C4

C5

C6

C7

C17

C18

C19

C20

C21

C12

C13

C14

C15

C16

C22

B17

B18

B19

B20

B21

B22

Pin

No.

B15

B16

B23

C1

C2

C8

C9

C10

C11

C23

D1

D2

D3

Mnemonic

NC

GND

RX_CP

RX_0P

RX_1P

RX_2P

GND

COMP1

DAC4

Type

No connect

GND

Rx input

Rx input

Rx input

Rx input

GND

Miscellaneous

analog 1

Analog video output

Description


Ground.

Rx Clock True Input.

Rx Channel 0 True Input.



Ground.

Compensation Pin. Connect a 2.2 nF capacitor to AVDD2.

Encoder DAC4 Output.

GND

GND

NC

NC

RX_HPD

AVDD1

GND

GND

AVDD1

AVDD1

OSD_IN[19]/EXT_DIN[

3]

OSD_IN[20]/EXT_DIN[

4]

GND

AUD_IN[4]

DSD_CLK

SCLK

SCL

SCK1

GND

INT0

PDN



GND

Audio input

Audio input





Ground.


DSD Audio Clock Input.

Audio input

I 2 C control

I 2 S Bit Clock Input.

I 2 C Clock Input. SCL is open drain; use a 4.7 kΩ resistor to connect this pin to a 3.3 V supply.

Serial port control Serial Clock (Serial Port 1). Serial Port 1 is used for OSD control.

GND Ground.

Interrupt Pin 0. When status bits change, this pin is triggered. Miscellaneous digital


GND

GND

No connect

No connect

Rx input

Power

GND

GND

Power

Power

Power-Down. This pin controls the power state of the ADV8003.

Ground.

Ground.



Hot Plug Assert Signal Output for the Rx Input.

HDMI Rx Inputs Analog Supply (3.3 V).

Ground.

Ground.



Encoder DAC5 Output. DAC5

DAC6

Analog video output

Analog video output

OSD_IN[16]/EXT_DIN[

0]

OSD_IN[17]/EXT_DIN[

1]



OSD_IN[18]/EXT_DIN[ OSD video input/









F1

F2

F3

F4

D8

D9

D10

D12

D13

D14

D15

D16

D17

D18

D19

Pin

No.

D4

D5

D6

D7

D11

D20

D21

D22

D23

E1

E2

E3

E4

E20

E21

E22

E23

Mnemonic

2]

GND

DVDD_IO

MCLK

SDA

DVDD_IO

TEST1

NC

NC

RX_5V

NC

NC

RTERM

Type miscellaneous digital

GND

Power

Description


Ground.

Digital Interface Supply (3.3 V).

Audio input

I 2 C control

MCLK for S/PDIF Input Audio.

I 2 C Data Input. SDA is open drain; use a 4.7 kΩ resistor to connect this pin to a 3.3 V supply.

Serial port control Chip Select (Serial Port 1). Serial Port 1 is used for OSD control. CS1

GND

INT1

INT2

GND Ground.

Miscellaneous digital Interrupt Pin for HDMI Transmitter Outputs. When status bits change, an interrupt is generated on this pin.

Miscellaneous digital Interrupt Pin for HDMI Receiver Input Lines. When status bits change, an interrupt is generated on this pin.

Power Digital Interface Supply (3.3 V).

Miscellaneous digital Test Pin. Float this pin.

No connect

No connect

Rx input

No connect

No connect

HDMI Rx input



5 V Detect Pin for the Rx Input.



This pin sets internal termination resistance. Use a 500 Ω resistor between this pin and GND. Place the RTERM resistor as close as possible to the ADV8003.

Analog Power Supply (3.3 V).



AVDD2

AVDD2

DAC1

DAC2

Power

Power

Analog video output

Analog video output

OSD_IN[13]/VBI_SCK OSD video input/ miscellaneous digital

OSD_IN[14]/VBI_MO

SI


OSD_IN[15]/VBI_CS

DVDD_IO

TEST2


Power

GND

COMP2

DAC3

Miscellaneous analog

GND

Miscellaneous

analog 1

Analog video output


External OSD Video Pixel Input Port (OSD_IN[13])/Serial Clock for VBI Data Serial

Port (VBI_SCK).

External OSD Video Pixel Input Port (OSD_IN[14])/Master Out Slave In for VBI Data

Serial Port (VBI_MOSI).

External OSD Video Pixel Input Port (OSD_IN[15])/Chip Select for VBI Data Serial

Port (VBI_CS).


Test Pin. Float this pin.

Ground.

Compensation Pin. Connect a 2.2 nF capacitor to AVDD2.


OSD_IN[9]

OSD_IN[10]

OSD_IN[11]

OSD_IN[12]

OSD video input

OSD video input

OSD video input


External OSD Video Pixel Input Port (OSD_IN[9]).



External OSD Video Pixel Input Port.


Mnemonic

RSET2

PVDD3

GND

CEC1

OSD_IN[5]

OSD_IN[6]

OSD_IN[7]

OSD_IN[8]

GND

GND

GND

DVDD

GND

GND

DVDD

GND

GND

GND

GND

ELPF1

G21 ELPF2

J1

J2

J3

H12

H13

H14

H15

H16

H17

H20

H21

H22

H23

G22

G23

H1

H2

H3

H4

H7

H8

H9

H10

H11

GND

GND

GND

GND

GND

GND

GND

GND

TX1_2+

TX1_2−

DE

HS

OSD_HS

GND

AVDD3

OSD_IN[1]

OSD_IN[2]

OSD_IN[3]

OSD_IN[4]

GND

GND

GND

GND

GND

Rev. B, August 2013

Pin

No.

F20

G4

G7

G8

G9

G10

G11

G12

G13

G14

G15

G16

G17

G20

F21

F22

F23

G1

G2

G3


GND

GND

GND

GND

GND

GND

GND

GND

GND

Power

OSD video input

OSD video input

OSD video input

OSD video input

GND

GND

GND

GND

HDMI Tx1

HDMI Tx1

Digital video sync

Digital video sync

Digital video sync

Type

Miscellaneous

analog 1

Power

GND

HDMI Tx1

OSD video input

OSD video input

OSD video input

OSD video input

GND

GND

GND

Power

GND

GND

Power

GND

GND

GND

GND

Miscellaneous

analog 1

Miscellaneous

analog 1

GND

Description

Resistor Current Setting for Encoder DACs: DAC4, DAC5, and DAC6. Place the RSET resistor as close as possible to the ADV8003.

PLL Supply (1.8 V).

Ground.

HDMI Tx1 Consumer Electronics Control (CEC).





Ground.

Ground.

Ground.

Digital Power Supply (1.8 V).

Ground.

Ground.


Ground.

Ground.

Ground.

Ground.

External Loop Filter for PLL 1. Connected to PVDD3.


Ground.

HDMI Analog Power Supply (1.8 V).





Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

HDMI1 Channel 2 True Output.

HDMI1 Channel 2 Complementary Output.

Data Enable for Digital Input Video.

Horizontal Sync for Digital Input Video.

Horizontal Sync for the OSD Input Port (OSD_HS).

26

L3

L4

L7

L8

L9

L10

L11

L12

L13

K21

K22

K23

L1

L2

GND

TX1_0+

TX1_0−

P[32]

P[33]

P[34]

P[35]

DVDD

GND

GND

GND

GND

GND

GND

Rev. B, August 2013

GND

TX1_1+

TX1_1−

VS

PCLK

DVDD_IO

DVDD_IO

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

DDC1_SCL

Mnemonic

OSD_IN[0]

DVDD

GND

GND

GND

GND

GND

GND

GND

GND

GND

DVDD

DDC1_SDA

J8

J9

J10

J11

J12

J13

J14

J15

J16

J17

J20

Pin

No.

J4

J7

J21

J22

J23

K1

K2

K3

K4

K7

K8

K9

K10

K11

K12

K13

K14

K15

K16

K17

K20


Type

OSD video input

Power

GND

GND

GND

GND

GND

GND

GND

GND

GND

Power

HDMI Tx1

Description



Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.


HDCP Slave Serial Data for HDMI Tx1. This pin is open drain; use a 2 kΩ resistor to connect this pin to the HDMI Tx 5 V supply.

Ground.



GND

HDMI Tx1

HDMI Tx1

Digital video sync

Digital video sync

Power

Power

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

HDMI Tx1

Vertical Sync for Digital Input Video.

Pixel Clock for Digital Input Video.



Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

HDCP Slave Serial Clock for HDMI Tx1. This pin is open drain; use a 2 kΩ resistor to connect this pin to the HDMI Tx 5 V supply.

GND

HDMI Tx1

HDMI Tx1

Ground.



Digital video input Digital Video Input Bus[35:0].




Power

GND

GND


Ground.

Ground.

GND

GND

GND

GND

Ground.

Ground.

Ground.

Ground.

27

PVDD5

HEAC_1+

HEAC_1−

P[24]

P[25]

P[26]

P[27]

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

CEC2

PVDD5

M21

M22

M23

N1

N2

N3

N4

N7

N8

N9

N10

N11

N12

N13

N14

N15

N16

N17

N20

N21

Rev. B, August 2013

Pin

No.

L14

L15

M2

M3

M4

M7

M8

M9

M10

M11

M12

L16

L17

L20

L21

L22

L23

M1

M13

M14

M15

M16

M17

M20

P[29]

P[30]

P[31]

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

R_TX1

Mnemonic

GND

GND

GND

GND

HPD_TX1

GND

TX1_C+

TX1_C−

P[28]


Type

GND

GND

GND

Description

Ground.

Ground.

Ground.

GND

HDMI Tx1

GND

HDMI Tx1

Ground.

Hot Plug Assert Signal Input for HDMI Tx1.

Ground.

HDMI1 Clock True Output.

HDMI Tx1 HDMI1 Clock Complementary Output.





GND Ground.

GND

GND

GND

GND

GND

Ground.

Ground.

Ground.

Ground.

Ground.

GND

GND

GND

GND

GND

HDMI Tx1 1

Ground.

Ground.

Ground.

Ground.

Ground.

Sets Internal Reference Currents. Place a 470 Ω resistor (1% tolerance) between this pin and ground. The external resistor should be placed as close as possible to the

ADV8003.

Power 1

HDMI Tx1

HDMI Tx1

HDMI Tx PLL Power Supply (1.8 V). This pin is a voltage regulator output. Connect a decoupling capacitor between this pin and ground.

HDMI Tx1 HEC+ from HDMI Connector.

HDMI Tx1 HEC− from HDMI Connector.





GND

GND

Ground.

Ground.

GND

GND

GND

GND

GND

Ground.

Ground.

Ground.

Ground.

Ground.

GND

GND

GND

GND

HDMI Tx2

Power 1

Ground.

Ground.

Ground.

Ground.



28

R21

R22

R23

T1

T2

T3

T4

T7

T8

GND

TX2_1+

TX2_1−

P[14]

P[15]

GND

GND

GND

GND

Rev. B, August 2013

GND

TX2_2+

TX2_2−

P[16]

P[17]

P[18]

P[19]

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

DDC2_SDA

Mnemonic

AVDD3

NC

P[20]

P[21]

P[22]

P[23]

DVDD

GND

GND

GND

GND

GND

GND

GND

GND

GND

DVDD

DDC2_SCL

P13

P14

P15

P16

P17

P8

P9

P10

P11

P12

P20

P1

P2

P3

P4

P7

Pin

No.

N22

N23

P21

P22

P23

R1

R2

R3

R4

R7

R8

R9

R10

R11

R12

R13

R14

R15

R16

R17

R20


Type

Power

No connect

Description







Power Digital Power Supply (1.8 V).

GND

GND

GND

GND

GND

Ground.

Ground.

Ground.

Ground.

Ground.

GND

GND

GND

GND

Power

HDMI Tx2

GND

HDMI Tx2

HDMI Tx2

Ground.

Ground.

Ground.

Ground.



Ground.







GND

GND

GND

GND

GND

Ground.

Ground.

Ground.

Ground.

Ground.

GND

GND

GND

GND

GND

GND

HDMI Tx2

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.


GND

HDMI Tx2

HDMI Tx2

Ground.





GND Ground.

GND

GND

GND

Ground.

Ground.

Ground.

29

U1

U2

U3

U4

U7

U8

U9

U10

T11

T12

T13

T14

T15

T16

T17

T20

T21

T22

T23

U11

U12

U13

U14

U15

U16

U17

U20

Pin

No.

T9

T10

P[10]

P[11]

P[12]

P[13]

GND

GND

DVDD

GND

GND

DVDD

GND

GND

DVDD

GND

GND

R_TX2

Mnemonic

GND

GND

GND

GND

GND

GND

GND

GND

GND

HPD_TX2

GND

TX2_0+

TX2_0−

U21

U22

U23

V1

V2

V3

V4

V20

V21

GND

TX2_C+

TX2_C−

P[6]

P[7]

P[8]

P[9]

GND

PVDD6

V22

V23

W1

W2

W3

W4

W20

HEAC_2+

HEAC_2−

P[2]

P[3]

P[4]

P[5]

TEST3

Rev. B, August 2013


Type

GND

GND

GND

GND

GND

GND

GND

GND

GND

HDMI Tx2

GND

HDMI Tx2

HDMI Tx2

Description

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.


Ground.







GND

GND

Power

GND

Ground.

Ground.


Ground.

GND

Power

GND

GND

Power

GND

GND

HDMI Tx2 1

GND

HDMI Tx2 1

HDMI Tx2 1

Ground.


Ground.

Ground.


Ground.

Ground.

Sets internal reference currents. Place a 470 Ω resistor (1% tolerance) between this pin and ground. The external resistor should be placed as close as possible to the

ADV8003.

Ground.


HDMI2 Clock Complementary Output.





GND

Power 1

Ground.


HDMI Tx2

HDMI Tx2







Miscellaneous Test Pin. Connect this pin to Ground through a 0.1 uF capacitor.

30

Pin

No. Mnemonic

AA9 DDR_A[8]

AA10 DVDD_DDR

AA11 DDR_A[2]

AA12 GND

AA13 DDR_CS

AA14 DVDD_DDR

AA15 DDR_CK

AA16 GND

AA17 DDR_DQ[11]

AA18 DVDD_DDR

AA19 DDR_DM[1]

Rev. B, August 2013

PVDD6

AVDD3

NC

P[0]

P[1]

DDR_DQS[2]

GND

DDR_DQ[23]

DVDD_DDR

DDR_DQS[3]

GND

DDR_A[11]

DVDD_DDR

DDR_A[4]

GND

DDR_CAS

DVDD_DDR

DDR_CK

GND

DDR_DQ[9]

DVDD_DDR

DDR_DQ[14]

GND

DDR_DQ[6]

PVDD_DDR

GND

DDR_DQ[18]

GND

GND

DDR_DQS[2]

DDR_DQ[26]

DVDD_DDR

DDR_DQS[3]

NC/GND

W21

Y21

Y22

Y23

AA1

AA2

AA3

Y16

Y17

Y18

Y19

Y20

AA4

AA5

AA6

AA7

AA8

W22

W23

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y8

Y9

Y10

Y11

Y12

Y13

Y14

Y15


Type digital

Power 1

Description

Power



No connect Do not connect to this pin.



DDR interface Data Strobe for DDR Data Byte[23:16].

GND Ground.

DDR interface

Power

DDR interface

GND

DDR interface

Data Line. Interface to external RAM data lines.

DDR Interface Supply (1.8 V).

Data Strobe for DDR Data Byte[31:24].

Ground.

Address Line. Interface to external RAM address lines.

Power

DDR interface

GND

DDR interface



Ground.

Column Address Strobe for DDR Memory.

Power

DDR interface


DDR Memory Clock. Interface to external DDR RAM clock lines.

GND

DDR Interface

Power

DDR interface

GND

DDR interface

Power

GND

DDR interface

GND

GND

DDR interface

DDR interface

Power

DDR interface

No connect/GND

DDR interface

Power

DDR interface

GND

DDR interface

Power

DDR interface

GND

DDR interface

Power

DDR interface

Ground.




Ground.


DDR Interface PLL Supply (1.8 V).

Ground.


Ground.

Ground.





For new ADV8003 designs, do not connect to this pin. For designs that must maintain consistency with the ADV8002, this pin can be grounded.




Ground.

DDR Chip Select. Interface to external DDR RAM chip selects.



Ground.



Data Mask for Data Lines[15:8].

31

Pin

No. Mnemonic

AA20 DDR_DM[0]

AA21 GND

AA22 GND

AA23 DDR_DQ[3]

AB1

AB2

AB3

DDR_DQ[21]

DDR_DQ[19]

DDR_DQ[17]

AB4

AB5

AB6

AB7

AB8

AB9

AB10

AB11

AB12

AB13

AB14

AB15

DDR_DM[2]

DDR_DQ[30]

DDR_DM[3]

DDR_DQ[31]

DDR_DQ[29]

DDR_A[12]

DDR_A[6]

DDR_A[3]

DDR_A[0]

DDR_BA[0]

DDR_RAS

DDR_CKE

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AC1

DDR_DQ[12]

DDR_DQS[1]

DDR_DQ[8]

DDR_DQ[13]

DDR_DQ[0]

DDR_DQ[5]

DDR_DQS[0]

DDR_DQ[4]

DDR_DQ[16]

AC2

AC3

AC4

AC5

AC6

DDR_DQ[20]

DDR_DQ[22]

DDR_DQ[25]

DDR_DQ[28]

DDR_DQ[27]

AC7

AC8

DDR_DQ[24]

DDR_A[9]

AC9 DDR_A[5]

AC10 DDR_A[7]

AC11 DDR_A[1]

AC12 DDR_A[10]

AC13 DDR_BA[1]

AC14 DDR_BA[2]

AC15 DDR_WE

AC16 DDR_VREF

AC17 DDR_DQ[10]

AC18 DDR_DQS[1]

AC19 DDR_DQ[15]

AC20 DDR_DQ[7]

AC21 DDR_DQ[2]

Rev. B, August 2013


Type

DDR interface

GND

GND

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface 1

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

Description


Ground.

Ground.














Bank Address Line. Indicates which data bank to write/read from.

Row Address Strobe for DDR Memory.

Clock Enable for External DDR Memory.


Data Strobe for DDR Data Bytes[15:8].





















Write Enable Signal for DDR RAM.

Reference Voltage for DDR RAM.






32

Pin

No. Mnemonic

AC22 DDR_DQS[0]

AC23 DDR_DQ[1]

Type

DDR interface

DDR interface

Description



1 Sensitive node. Careful layout is important. The associated circuitry should be kept as close as possible to the ADV8003.




A

B

C

D

E

1

OSD_

IN[23]/

EXT_

DIN[7]

OSD_

IN[21]/

EXT_

DIN[5]

OSD_

IN[19]/

EXT_

DIN[3]

OSD_

IN[16]/

EXT_

DIN[0]

2

OSD_

DE

3

OSD_

CLK/

EXT_

CLK

OSD_

IN[22]/

EXT_

DIN[6]

OSD_

IN[20]/

EXT_

DIN[4]

OSD_

IN[17]/

EXT_

DIN[1]

OSD_

VS

GND

OSD_

IN[18]/

EXT_

DIN[2]

OSD_

IN[13]/

VBI_SCK

OSD_

IN[14]/

VBI_MOSI

OSD_

IN[15]/

VBI_CS

4

AUD_

IN[1]

AUD_

IN[0]

AUD_

IN[4]

GND

DVDD_

IO

5

AUD_

IN[2]

AUD_

IN[3]

DSD_

CLK

6

AUD_

IN[5]

SFL

SCLK

DVDD_

IO

MCLK

7 8

TEST4 MOSI1

ARC1_

OUT

MISO1

SCL

SDA

SCK1

CS1

9

SCK2

GND

GND

10

CS2

INT0

INT1

11

PDN

12

GND

13


MOSI2 MISO2 ALSB XTALP PVDD1

GND

INT2

DVDD_

IO

TEST1

F

G

H

J

K

L

OSD_

IN[9]

OSD_

IN[10]

OSD_

IN[11]

OSD_

IN[12]

OSD_

IN[5]

OSD_

IN[6]

OSD_

IN[1]

OSD_

IN[2]

OSD_

IN[7]

OSD_

IN[3]

OSD_

IN[8]

OSD_

IN[4]

DE

VS

P[32]

HS

OSD_

HS

OSD_

IN[0]

PCLK

DVDD_

IO

DVDD_

IO

P[33] P[34] P[35]

GND

GND

DVDD

GND

DVDD

GND

GND

GND

GND

GND

GND DVDD

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

14

NC

NC

NC

NC

GND DVDD GND

GND

GND

GND

GND

M

N

P[28] P[29] P[30] P[31]

P[24] P[25] P[26] P[27]

GND

GND

GND GND GND

GND GND GND

15 22

NC CVDD1 RX_CN RX_0N RX_1N RX_2N CVDD1 NC

NC

NC

16

GND RX_CP RX_0P RX_1P RX_2P GND

NC

RX_

HPD

AVDD1 GND GND AVDD1 AVDD1 NC

NC

RX_5V NC

GND GND

GND GND

GND

GND

GND GND DVDD

GND GND

GND GND

GND GND GND GND GND GND


17

GND

GND

GND

GND

18 19 20

NC RTERM AVDD2 AVDD2

NC

TEST2 GND

GND

21

NC

GND TX1_2+ TX1_2–

H

NC PVDD5 AVDD3

23

NC

NC

NC

NC

NC

NC PVDD3 GND CEC1

ELPF1 ELPF2 GND AVDD3

DDC1_

SDA

GND TX1_1+ TX1_1–

DDC1_

SCL

HPD_

TX1

GND

GND

TX1_0+

TX1_C+

TX1_0–

TX1_C–

R_TX1 PVDD5

HEAC_

1+

HEAC_

1–

NC

A

B

C

D

E

F

G

J

K

L

M

N

DVDD GND GND GND GND GND GND GND GND GND DVDD NC GND NC NC P P[20] P[21] P[22] P[23]

R P[16] P[17] P[18] P[19] GND GND GND GND GND GND GND GND GND GND GND NC GND NC NC

P

R

T P[14] P[15] GND GND GND GND GND GND GND GND GND GND GND GND GND NC GND NC NC T

U P[10] P[11] P[12] P[13]

V P[6] P[7] P[8] P[9]

GND GND DVDD GND GND DVDD GND GND DVDD GND GND NC GND NC

GND PVDD6 NC

NC

NC

U

V

W P[2] P[3] P[4] P[5] TEST3 PVDD6 AVDD3 NC W

Y

AA

DDR_

DQ[18]

AB

P[0]

DDR_

DQ[21]

DDR_

DQ[19]

DDR_

DQ[17]

DDR_

DM[2]

DDR_

DQ[30]

DDR_

DM[3]

DDR_

DQ[31]

DDR_

DQ[29]

DDR_

A[12]

DDR_

A[6]

AC

DDR_

DQ[16]

DDR_

DQ[20]

DDR_

DQ[22]

DDR_

DQ[25]

DDR_

DQ[28]

DDR_

DQ[27]

DDR_

DQ[24]

DDR_

A[9]

1

P[1]

GND

DDR_

DQS[2]

GND

DDR_

DQ[23]

DVDD_

DDR

DDR_

DQS[3]

GND

DDR_

DQS[2]

DDR_

DQ[26]

DVDD_

DDR

DDR_

DQS[3]

GND

NC/

GND

2 3 4 5

DDR_

A[11]

DVDD_

DDR

DDR_

A[4]

DDR_

A[8]

DVDD_

DDR

DDR_

A[2]

DDR_

A[5]

DDR_

A[7]

GND

GND

DDR_

A[3]

DDR_

A[0]

DDR_

A[1]

DDR_

A[10]

DDR_

CAS

DVDD_

DDR

DDR_

CK

GND

DDR_

DQ[9]

DVDD_

DDR

DDR_

DQ[14]

GND

DDR_

CS

DVDD_

DDR

DDR_

CK

DDR_

BA[0]

DDR_

BA[1]

DDR_

RAS

DDR_

BA[2]

DDR_

WE

GND

DDR_

VREF

DDR_

DQ[11]

DVDD_

DDR

DDR_

DM[1]

DDR_

DM[0]

DDR_

CKE

DDR_

DQ[12]

DDR_

DQS[1]

DDR_

DQ[8]

DDR_

DQ[13]

DDR_

DQ[0]

DDR_

DQ[10]

DDR_

DQS[1]

DDR_

DQ[15]

DDR_

DQ[7]

19 20 6 7 8 9 10 11 12 13 14 15 16 17 18

Figure 8. ADV8003KBCZ-8B and ADV8003KBCZ-7B Pin Configuration

DDR_

DQ[6]

PVDD_

DDR

GND

GND GND

DDR_

DQ[3]

DDR_

DQ[5]

DDR_

DQS[0]

DDR_

DQ[4]

DDR_

DQ[2]

DDR_

DQS[0]

DDR_

DQ[1]

21 22 23

Y

AA

AB

AC



A4

A5

A6

A7

Table 3. ADV8003KBCZ-8B and ADV8003KBCZ-7B Pin Function Descriptions

Pin

No.

A1

A2

A3

Mnemonic

OSD_IN[23]/EXT_DIN[

7]

OSD_DE

OSD_CLK/EXT_CLK

Type


OSD video sync

OSD video sync

Description

External OSD Video Pixel Input Port (OSD_IN[23])/Additional TTL Input for

External CCIR 656 Video Data (EXT_DIN[7]).

A8

A9

A10

AUD_IN[1]

AUD_IN[2]

AUD_IN[5]

TEST4

MOSI1

SCK2

CS2

Audio input

Audio input

Audio input


Serial port control

Serial port control

Serial port control



(EXT_CLK).




Test Pin. Connect this pin to Ground through a 4.7 kΩ resistor.

Master Out Slave In (Serial Port 1). Serial Port 1 is used for OSD control.

Serial Clock (Serial Port 2). Serial Port 2 is used for the external flash ROM.

Chip Select (Serial Port 2). Serial Port 2 is used for the external flash ROM.

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

RESET

XTALN

PVDD2

NC

NC

CVDD1

RX_CN

RX_0N

RX_1N

RX_2N

CVDD1

NC

NC

OSD_IN[21]/EXT_DIN[

5]

OSD_IN[22]/EXT_DIN[

6]

OSD_VS

AUD_IN[0]

AUD_IN[3]

SFL

ARC1_OUT

MISO1

MOSI2

MISO2

ALSB

XTALP

B13

B14

PVDD1

NC

B15 NC

Rev. B, August 2013



1

Power

No connect

No connect

Power

Rx input

Rx input

Rx input

Rx input

Power

No connect

No connect



OSD video sync

Audio input

Audio input

SFL

Audio output

Serial port control

Serial port control

Serial port control

I 2 C control

Miscellaneous

digital 1

Power

No connect

No connect


Crystal Input.





















Master In Slave Out (Serial Port 1). Serial Port 1 is used for OSD control.

Master Out Slave In (Serial Port 2). Serial Port 2 is used for the external flash ROM.

Master In Slave Out (Serial Port 2). Serial Port 2 is used for the external flash ROM.

Sets LSB of ADV8003 I 2 C address (0x18 with LSB low, 0x1A with LSB high).

ADV8003 Crystal Input.




35


B18

B19

B20

B21

B22

B23

C1

Pin

No.

B16

B17

C8

C9

C10

C11

C3

C4

C5

C6

C7

C20

C21

C22

C23

D1

C12

C13

C14

C15

C16

C17

C18

C19

C2

D2

Mnemonic

GND

RX_CP

RX_0P

RX_1P

RX_2P

GND

NC

NC

OSD_IN[19]/EXT_DIN[

3]

OSD_IN[20]/EXT_DIN[

4]

GND

AUD_IN[4]

DSD_CLK

SCLK

SCL

SCK1

GND

INT0

PDN

GND

GND

NC

NC

RX_HPD

AVDD1

GND

GND

AVDD1

AVDD1

NC

NC

OSD_IN[16]/EXT_DIN[

0]

OSD_IN[17]/EXT_DIN[

1]

D3 OSD_IN[18]/EXT_DIN[

2]

D4

D5

D6

GND

DVDD_IO

MCLK

Rev. B, August 2013

Serial port control

GND



GND

GND

No connect

No connect

Rx input

Power

GND

GND

Power

Power

No connect

No connect




GND

Power

Audio input

Type

GND

Rx input

Rx input

Rx input

Rx input

GND

No connect

No connect



GND

Audio input

Audio input

Audio input

I 2 C control

Description

Ground.





Ground.







Ground.




I 2 C Clock Input. This pin is open drain; use a 4.7 kΩ resistor to connect this pin to a

3.3 V supply.

Serial Clock (Serial Port 1). Serial Port 1 is used for OSD control.

Ground.

Interrupt Pin 0. When status bits change, this pin is triggered.


Ground.

Ground.





Ground.

Ground.











Ground.



36


D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

Pin

No.

D7

Mnemonic

SDA

CS1

GND

INT1

INT2

DVDD_IO

TEST1

NC

NC

RX_5V

NC

NC

RTERM

Type

I 2 C control

Serial port control

GND



Power


No connect

No connect

Rx input

No connect

No connect

HDMI Rx input

D20

D21

D22

D23

E1

F1

F2

F3

F4

E21

E22

E23

E2

E3

E4

E20

F20

F21

F22

F23

G1

G2

G3

AVDD2

AVDD2

NC

NC

GND

NC

NC

Power

Power

No connect

No connect


OSD_IN[14]/VBI_MOS

I


OSD_IN[15]/VBI_CS OSD video input/ miscellaneous digital

DVDD_IO

TEST2

Power


GND

No connect

No connect

OSD_IN[9]

OSD_IN[10]

OSD_IN[11]

OSD_IN[12]

NC

PVDD3

GND

CEC1

OSD_IN[5]

OSD_IN[6]

OSD_IN[7]

OSD video input

OSD video input

OSD video input


No connect

Power

GND

HDMI Tx1

OSD video input

OSD video input

OSD video input

Rev. B, August 2013

Description

I 2 C Data Input. This pin is open drain; use a 4.7 kΩ resistor to connect this pin to a

3.3 V supply.

Chip Select (Serial Port 1). Serial Port 1 is used for OSD control.

Ground.

Interrupt Pin for HDMI Transmitter Outputs. When status bits change, an interrupt is generated on this pin.

Interrupt Pin for HDMI Receiver Input Lines. When status bits change, an interrupt is generated on this pin.













External OSD Video Pixel Input Port (OSD_IN[13])/Serial Clock for VBI Data Serial Port

(VBI_SCK).

External OSD Video Pixel Input Port (OSD_IN[14])/Master Out Slave In for VBI Data

Serial Port (VBI_MOSI).

External OSD Video Pixel Input Port (OSD_IN[15])/Chip Select for VBI Data Serial Port

(VBI_CS).



Ground.








PLL Supply (1.8 V).

Ground.





37

G8

G9

G10

G11

G12

G13

G14

G15

G16

G17

G20

Pin

No.

G4

G7

G21

J3

J4

J7

J8

J9

J10

J11

J12

J13

H14

H15

H16

H17

H20

H21

H22

H23

J1

J2

H4

H7

H8

H9

H10

H11

H12

H13

G22

G23

H1

H2

H3

GND

GND

GND

GND

GND

GND

TX1_2+

TX1_2−

DE

HS

OSD_HS

OSD_IN[0]

DVDD

GND

GND

GND

GND

GND

GND

GND

AVDD3

OSD_IN[1]

OSD_IN[2]

OSD_IN[3]

OSD_IN[4]

GND

GND

GND

GND

GND

GND

GND

Rev. B, August 2013

GND

DVDD

GND

GND

GND

GND

ELPF1

Mnemonic

OSD_IN[8]

GND

GND

GND

DVDD

GND

ELPF2


GND

GND

GND

GND

GND

GND

GND

GND

GND

OSD video input

OSD video input

OSD video input

OSD video input

GND

GND

GND

GND

HDMI Tx1

HDMI Tx1

Digital video sync

Digital video sync

Digital video sync

OSD video input

Power

GND

GND

GND

GND

GND

GND

Type

OSD video input

GND

GND

GND

Power

GND

GND

Power

GND

GND

GND

GND

Miscellaneous

analog 1

Miscellaneous

analog 1

GND

Power

Description


Ground.

Ground.

Ground.


Ground.

Ground.


Ground.

Ground.

Ground.

Ground.



Ground.






Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.








Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

38

Mnemonic

GND

GND

GND

DVDD

DDC1_SDA

GND

TX1_1+

TX1_1−

VS

PCLK

DVDD_IO

DVDD_IO

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

DDC1_SCL

K21

K22

K23

L1

L2

L3

L4

L7

L8

L9

L10

L11

L12

L13

L14

L15

L16

L17

L20

L21

L22

L23

GND

TX1_0+

TX1_0−

P[32]

P[33]

P[34]

P[35]

DVDD

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

HPD_TX1

GND

TX1_C+

TX1_C−

Rev. B, August 2013

Pin

No.

J14

J15

J16

J17

J20

J21

J22

J23

K1

K2

K3

K4

K7

K8

K9

K10

K11

K12

K13

K14

K15

K16

K17

K20


Type

GND

GND

GND

Power

HDMI Tx1

Description

Ground.

Ground.

Ground.



Ground. GND

HDMI Tx1

HDMI Tx1

Digital video sync

Digital video sync

Power

Power

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

HDMI Tx1

GND

HDMI Tx1

HDMI Tx1







Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.


Ground.







Power Digital Power Supply (1.8 V).

GND Ground.

GND

GND

GND

GND

Ground.

Ground.

Ground.

Ground.

GND

GND

GND

GND

GND

HDMI Tx1

GND

HDMI Tx1

HDMI Tx1

Ground.

Ground.

Ground.

Ground.

Ground.


Ground.



39

M21

N4

N7

N8

N9

N10

N11

N12

N13

N14

N15

N16

N17

N20

N21

M22

M23

N1

N2

N3

P3

P4

P7

P8

N22

N23

P1

P2

Rev. B, August 2013

PVDD5

AVDD3

NC

P[20]

P[21]

P[22]

P[23]

DVDD

GND

HEAC_1+

HEAC_1−

P[24]

P[25]

P[26]

P[27]

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

NC

PVDD5

Pin

No.

M1

M2

M3

M4

M7

M8

M9

M10

M11

M12

M13

M14

M15

M16

M17

M20

GND

GND

GND

GND

GND

GND

GND

GND

GND

R_TX1

Mnemonic

P[28]

P[29]

P[30]

P[31]

GND

GND


Type Description





GND

GND

Ground.

Ground.

GND

GND

GND

GND

GND

GND

GND

GND

GND

HDMI Tx1 1

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Power 1

HDMI Tx1

HDMI Tx1

Sets internal reference currents. Place a 470 Ω resistor (1% tolerance) between this pin and ground. The external resistor should be placed as close as possible to the

ADV8003.








GND Ground.

GND

GND

Ground.

Ground.

GND

GND

GND

GND

GND

Ground.

Ground.

Ground.

Ground.

Ground.

GND

GND

GND

No connect

Power 1

Power

No connect

Ground.

Ground.

Ground.









Power

GND


Ground.

40

GND

GND

GND

GND

GND

GND

GND

GND

NC

P[16]

P[17]

P[18]

P[19]

GND

GND

GND

GND

GND

DVDD

NC

GND

NC

NC

Mnemonic

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

NC

NC

P[14]

P[15]

GND

GND

GND

GND

GND

NC

Rev. B, August 2013

R21

R22

R23

T1

T2

T3

R10

R11

R12

R13

R14

R15

R16

R17

R20

R1

R2

R3

R4

R7

R8

R9

P11

P12

P13

P14

P15

P16

P17

P20

P21

P22

P23

T4

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T20

Pin

No.

P9

P10

Type

GND

GND

GND

GND

GND

GND

GND

GND

Power

No connect

GND

No connect

No connect

Description

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.



Ground.







GND

GND

GND

Ground.

Ground.

Ground.

GND

GND

GND

GND

GND

GND

GND

GND

No connect

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.


GND

GND

GND

GND

GND

GND

GND

GND

GND

No connect

No connect

Ground.





GND Ground.

GND

GND

GND

GND

No connect

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.


41


W21 PVDD6

W22

W23

Y1

Y2

Y3

Y4

Y5

Y6

Y7

AVDD3

NC

P[0]

P[1]

DDR_DQS[2]

GND

DDR_DQ[23]

DVDD_DDR

DDR_DQS[3]

Rev. B, August 2013

NC

NC

P[2]

P[3]

P[4]

P[5]

TEST3

DVDD

GND

GND

DVDD

GND

GND

NC

GND

NC

NC

P[6]

P[7]

P[8]

P[9]

GND

PVDD6

Mnemonic

GND

NC

NC

P[10]

P[11]

P[12]

P[13]

GND

GND

DVDD

GND

GND

V1

V2

V3

V4

V20

V21

U17

U20

U21

U22

U23

U12

U13

U14

U15

U16

U7

U8

U9

U10

U11

T23

U1

U2

U3

U4

Pin

No.

T21

T22

V22

V23

W1

W2

W3

W4

W20


Type

GND

No connect

No connect

Description

Ground.







GND

GND

Power

GND

GND

Ground.

Ground.


Ground.

Ground.

Power

GND

GND

Power

GND

GND

No connect

GND

No connect

No connect


Ground.

Ground.


Ground.

Ground.


Ground.







GND

Power 1

No connect

No connect

Ground.









Test Pin. Connect this pin to Ground through a 0.1 uF capacitor.

Power 1


Power

No connect





DDR interface Data Strobe for DDR Data Byte[23:16].

GND

DDR interface

Ground.


Power

DDR interface



42

Mnemonic

GND

DDR_A[11]

DVDD_DDR

DDR_A[4]

GND

DDR_CAS

DVDD_DDR

DDR_CK

GND

DDR_DQ[9]

DVDD_DDR

DDR_DQ[14]

GND

DDR_DQ[6]

PVDD_DDR

GND

DDR_DQ[18]

GND

GND

DDR_DQS[2]

DDR_DQ[26]

DVDD_DDR

DDR_DQS[3]

NC/GND

AA9 DDR_A[8]

AA10 DVDD_DDR

AA11 DDR_A[2]

AA12 GND

AA13 DDR_CS

AA14 DVDD_DDR

AA15 DDR_CK

AA16 GND

AA17 DDR_DQ[11]

AA18 DVDD_DDR

AA19 DDR_DM[1]

AA20 DDR_DM[0]

AA21 GND

AA22 GND

AA23 DDR_DQ[3]

AB1

AB2

DDR_DQ[21]

DDR_DQ[19]

AB3

AB4

AB5

AB6

DDR_DQ[17]

DDR_DM[2]

DDR_DQ[30]

DDR_DM[3]

AB7

AB8

DDR_DQ[31]

DDR_DQ[29]

Rev. B, August 2013

Pin

No.

Y8

Y9

Y10

Y11

Y12

Y13

Y14

Y15

Y21

Y22

Y23

AA1

AA2

AA3

Y16

Y17

Y18

Y19

Y20

AA4

AA5

AA6

AA7

AA8


Type

GND

DDR interface

Power

DDR interface

GND

DDR interface

Power

DDR interface

GND

DDR Interface

Power

DDR interface

GND

DDR interface

Power

GND

DDR interface

GND

GND

DDR interface

DDR interface

Power

DDR interface

No connect/GND

DDR interface

Power

DDR interface

GND

DDR interface

Power

DDR interface

GND

DDR interface

Power

DDR interface

DDR interface

GND

GND

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

Description

Ground.




Ground.




Ground.




Ground.



Ground.


Ground.

Ground.









Ground.




Ground.





Ground.

Ground.










43


Pin

No.

AB9

AB10

AB11

AB12

AB13

AB14

AC1

AC2

AC3

AC4

AC5

AC6

AC7

AC8

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

DDR_DQ[16]

DDR_DQ[20]

DDR_DQ[22]

DDR_DQ[25]

DDR_DQ[28]

DDR_DQ[27]

DDR_DQ[24]

DDR_A[9]

AC9 DDR_A[5]

AC10 DDR_A[7]

AC11 DDR_A[1]

AC12 DDR_A[10]

AC13 DDR_BA[1]

AC14 DDR_BA[2]

AC15 DDR_WE

Mnemonic

DDR_A[12]

DDR_A[6]

DDR_A[3]

DDR_A[0]

DDR_BA[0]

DDR_RAS

DDR_CKE

DDR_DQ[12]

DDR_DQS[1]

DDR_DQ[8]

DDR_DQ[13]

DDR_DQ[0]

DDR_DQ[5]

DDR_DQS[0]

DDR_DQ[4]

AC16 DDR_VREF

AC17 DDR_DQ[10]

AC18 DDR_DQS[1]

AC19 DDR_DQ[15]

AC20 DDR_DQ[7]

AC21 DDR_DQ[2]

AC22 DDR_DQS[0]

AC23 DDR_DQ[1]

Type

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface 1

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

Description










































A

B

C

D

E

1

OSD_

IN[23]/

EXT_

DIN[7]

OSD_

IN[21]/

EXT_

DIN[5]

OSD_

IN[19]/

EXT_

DIN[3]

OSD_

IN[16]/

EXT_

DIN[0]

2

OSD_

DE

3

OSD_

CLK/

EXT_

CLK

OSD_

IN[22]/

EXT_

DIN[6]

OSD_

IN[20]/

EXT_

DIN[4]

OSD_

IN[17]/

EXT_

DIN[1]

OSD_

VS

GND

OSD_

IN[18]/

EXT_

DIN[2]

OSD_

IN[13]/

VBI_SCK

OSD_

IN[14]/

VBI_MOSI

OSD_

IN[15]/

VBI_CS

4

AUD_

IN[1]

AUD_

IN[0]

AUD_

IN[4]

GND

DVDD_

IO

5

AUD_

IN[2]

AUD_

IN[3]

DSD_

CLK

6

AUD_

IN[5]

SFL

SCLK

DVDD_

IO

MCLK

7 8

ARC2_

OUT

MOSI1

ARC1_

OUT

MISO1

SCL

SDA

SCK1

CS1

9

SCK2

GND

GND

10

CS2

INT0

INT1

11

PDN

12

GND

13



GND

INT2

DVDD_

IO

TEST1

F

G

H

J

K

L

OSD_

IN[9]

OSD_

IN[10]

OSD_

IN[11]

OSD_

IN[12]

OSD_

IN[5]

OSD_

IN[6]

OSD_

IN[1]

OSD_

IN[2]

OSD_

IN[7]

OSD_

IN[3]

OSD_

IN[8]

OSD_

IN[4]

DE

VS

P[32]

HS

OSD_

HS

OSD_

IN[0]

PCLK

DVDD_

IO

DVDD_

IO

P[33] P[34] P[35]

GND

GND

DVDD

GND

DVDD

GND

GND

GND

GND

GND

GND DVDD

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

14

NC

NC

NC

NC

GND DVDD GND

GND

GND

GND

GND

M

N

P

R

T

P[28] P[29] P[30] P[31]

P[24] P[25] P[26] P[27]

P[20] P[21] P[22] P[23]

P[16] P[17] P[18] P[19]

P[14] P[15] GND GND

GND

GND

GND

GND

GND GND GND

GND GND GND

DVDD GND GND GND

GND GND GND

GND GND GND

15 16




17

NC

RX_5V NC

GND GND

GND GND

GND

GND

GND GND DVDD

GND GND

GND GND


GND

GND

GND

GND

GND GND GND GND GND GND DVDD

GND

GND

18 19 20

GND

21

TEST2 GND

22


NC

NC


NC

RX_

HPD



NC

NC

23

NC

NC

NC

NC

NC

NC PVDD3 GND CEC1


GND TX1_2+ TX1_2–

H

DDC1_

SDA

GND TX1_1+ TX1_1–

DDC1_

SCL

HPD_

TX1

GND

GND

TX1_0+

TX1_C+

TX1_0–

TX1_C–

R_TX1 PVDD5

HEAC_

1+

HEAC_

1–

CEC2 NC

A

B

C

D

E

F

G

J

K

L

M

N

DDC2_

SCL

DDC2_

SDA

HPD_

TX2

TX2_2+ TX2_2–

GND TX2_1+ TX2_1–

GND TX2_0+ TX2_0–

P

R

T

U

V

W

P[10] P[11] P[12] P[13]

P[6]

P[2]

P[7]

P[3]

P[8]

P[4]

P[9]

P[5]

GND GND DVDD GND GND DVDD GND GND DVDD GND GND R_TX2 GND TX2_C+ TX2_C–

U

GND PVDD6

HEAC_

2+

HEAC_

2–

V

TEST3 PVDD6 AVDD3 NC W

Y

AA

DDR_

DQ[18]

AB

P[0]

DDR_

DQ[21]

DDR_

DQ[19]

DDR_

DQ[17]

DDR_

DM[2]

DDR_

DQ[30]

DDR_

DM[3]

DDR_

DQ[31]

DDR_

DQ[29]

DDR_

A[12]

DDR_

A[6]

AC

DDR_

DQ[16]

DDR_

DQ[20]

DDR_

DQ[22]

DDR_

DQ[25]

DDR_

DQ[28]

DDR_

DQ[27]

DDR_

DQ[24]

DDR_

A[9]

1

P[1]

GND

DDR_

DQS[2]

GND

DDR_

DQ[23]

DVDD_

DDR

DDR_

DQS[3]

GND

DDR_

DQS[2]

DDR_

DQ[26]

DVDD_

DDR

DDR_

DQS[3]

GND

NC/

GND

2 3 4 5

DDR_

A[11]

DVDD_

DDR

DDR_

A[4]

DDR_

A[8]

DVDD_

DDR

DDR_

A[2]

DDR_

A[5]

DDR_

A[7]

GND

GND

DDR_

A[3]

DDR_

A[0]

DDR_

A[1]

DDR_

A[10]

DDR_

CAS

DVDD_

DDR

DDR_

CK

GND

DDR_

DQ[9]

DVDD_

DDR

DDR_

DQ[14]

GND

DDR_

CS

DVDD_

DDR

DDR_

CK

DDR_

BA[0]

DDR_

BA[1]

DDR_

RAS

DDR_

BA[2]

DDR_

WE

GND

DDR_

VREF

DDR_

DQ[11]

DVDD_

DDR

DDR_

DM[1]

DDR_

DM[0]

DDR_

CKE

DDR_

DQ[12]

DDR_

DQS[1]

DDR_

DQ[8]

DDR_

DQ[13]

DDR_

DQ[0]

DDR_

DQ[10]

DDR_

DQS[1]

DDR_

DQ[15]

DDR_

DQ[7]

19 20 6 7 8 9 10 11 12 13 14 15 16 17 18

Figure 9. ADV8003KBCZ-8C and ADV8003KBCZ-7C Pin Configuration

DDR_

DQ[6]

PVDD_

DDR

GND

GND GND

DDR_

DQ[3]

DDR_

DQ[5]

DDR_

DQS[0]

DDR_

DQ[4]

DDR_

DQ[2]

DDR_

DQS[0]

DDR_

DQ[1]

21 22 23

Y

AA

AB

AC



A4

A5

A6

A7

A8

A9

A10

Table 4. ADV8003KBCZ-8C and ADV8003KBCZ-7C Pin Function Descriptions

Pin

No.

A1

A2

A3

Mnemonic

OSD_IN[23]/EXT_DIN[7

]

OSD_DE

OSD_CLK/EXT_CLK

Type


OSD video sync

OSD video sync

Description



A11

AUD_IN[1]

AUD_IN[2]

AUD_IN[5]

ARC2_OUT

MOSI1

SCK2

CS2

RESET

Audio input

Audio input

Audio input

Audio output

Serial port control

Serial port control

Serial port control



(EXT_CLK).





Master Out Slave In (Serial Port 1). Serial Port 1 is used for OSD control.




A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

XTALN

PVDD2

NC

NC

CVDD1

RX_CN

RX_0N

RX_1N

RX_2N

CVDD1

NC

NC


]


]

OSD_VS

AUD_IN[0]

AUD_IN[3]

SFL

ARC1_OUT

MISO1

MOSI2

MISO2

ALSB

XTALP

PVDD1

NC

NC



1

Power

No connect

No connect

Power

Rx input

Rx input

Rx input

Rx input

Power

No connect

No connect



OSD video sync

Audio input

Audio input

SFL

Audio output

Serial port control

Serial port control

Serial port control

I 2 C control

Miscellaneous

digital 1

Power

No connect

No connect

Crystal Input.





















Master In Slave Out (Serial Port 1). Serial Port 1 is used for OSD control.

Master Out Slave In (Serial Port 2). Serial Port 2 is used for the external flash ROM.

Master In Slave Out (Serial Port 2). Serial Port 2 is used for the external flash ROM.

Sets LSB of ADV8003 I 2 C address (0x18 with LSB low, 0x1A with LSB high).







B18

B19

B20

B21

B22

B23

C1

Pin

No.

B16

B17

C2

C3

C4

C5

C6

C7

Mnemonic

GND

RX_CP

RX_0P

RX_1P

RX_2P

GND

NC

NC


]


]

GND

AUD_IN[4]

DSD_CLK

SCLK

SCL

Type

GND

Rx input

Rx input

Rx input

Rx input

GND

No connect

No connect



GND

Audio input

Audio input

Audio input

I 2 C control

C20

C21

C22

C23

D1

C12

C13

C14

C15

C16

C17

C18

C19

C8

C9

C10

C11

D2

D3

D4

D5

D6

SCK1

GND

INT0

PDN

GND

GND

NC

NC

RX_HPD

AVDD1

GND

GND

AVDD1

AVDD1

NC

NC


]


]


]

GND

DVDD_IO

MCLK

Rev. B, August 2013

Serial port control

GND



GND

GND

No connect

No connect

Rx input

Power

GND

GND

Power

Power

No connect

No connect




GND

Power

Audio input

Description

Ground.





Ground.







Ground.




I 2 C Clock Input. SCL is open drain; use a 4.7 kΩ resistor to connect this pin to a 3.3 V supply.


Ground.

Interrupt Pin 0. When status bits change, this pin is triggered.


Ground.

Ground.





Ground.

Ground.











Ground.



47


D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

Pin

No.

D7

Mnemonic

SDA

CS1

GND

INT1

INT2

DVDD_IO

TEST1

NC

NC

RX_5V

NC

NC

RTERM

Type

I 2 C control

Serial port control

GND



Power


No connect

No connect

Rx input

No connect

No connect

HDMI Rx input

D20

D21

D22

D23

E1

F1

F2

F3

F4

E21

E22

E23

E2

E3

E4

E20

F20

F21

F22

F23

G1

G2

G3

AVDD2

AVDD2

NC

NC

GND

NC

NC

Power

Power

No connect

No connect


OSD_IN[14]/VBI_MOS

I



DVDD_IO

TEST2

Power


GND

No connect

No connect

OSD_IN[9]

OSD_IN[10]

OSD_IN[11]

OSD_IN[12]

NC

PVDD3

GND

CEC1

OSD_IN[5]

OSD_IN[6]

OSD_IN[7]

OSD video input

OSD video input

OSD video input


No connect

Power

GND

HDMI Tx1

OSD video input

OSD video input

OSD video input

Rev. B, August 2013

Description

I 2 C Data Input. SDA is open drain; use a 4.7 kΩ resistor to connect this pin to a 3.3 V supply.

Chip Select (Serial Port 1). Serial Port 1 is used for OSD control.

Ground.

Interrupt Pin for HDMI Transmitter Outputs. When status bits change, an interrupt is generated on this pin.

Interrupt Pin for HDMI Receiver Input Lines. When status bits change, an interrupt is generated on this pin.













External OSD Video Pixel Input Port (OSD_IN[13])/Serial Clock for VBI Data Serial

Port (VBI_SCK).

External OSD Video Pixel Input Port (OSD_IN[14])/Master Out Slave In for VBI

Data Serial Port (VBI_MOSI).

External OSD Video Pixel Input Port (OSD_IN[15])/Chip Select for VBI Data Serial

Port (VBI_CS).



Ground.








PLL Supply (1.8 V).

Ground.





48

G8

G9

G10

G11

G12

G13

G14

G15

G16

G17

G20

Pin

No.

G4

G7

G21

J3

J4

J7

J8

J9

J10

J11

J12

J13

H14

H15

H16

H17

H20

H21

H22

H23

J1

J2

H4

H7

H8

H9

H10

H11

H12

H13

G22

G23

H1

H2

H3

GND

GND

GND

GND

GND

GND

TX1_2+

TX1_2−

DE

HS

OSD_HS

OSD_IN[0]

DVDD

GND

GND

GND

GND

GND

GND

GND

AVDD3

OSD_IN[1]

OSD_IN[2]

OSD_IN[3]

OSD_IN[4]

GND

GND

GND

GND

GND

GND

GND

Rev. B, August 2013

GND

DVDD

GND

GND

GND

GND

ELPF1

Mnemonic

OSD_IN[8]

GND

GND

GND

DVDD

GND

ELPF2


GND

GND

GND

GND

GND

GND

GND

GND

GND

OSD video input

OSD video input

OSD video input

OSD video input

GND

GND

GND

GND

HDMI Tx1

HDMI Tx1

Digital video sync

Digital video sync

Digital video sync

OSD video input

Power

GND

GND

GND

GND

GND

GND

Type

OSD video input

GND

GND

GND

Power

GND

GND

Power

GND

GND

GND

GND

Miscellaneous

analog 1

Miscellaneous

analog 1

GND

Power

Description


Ground.

Ground.

Ground.


Ground.

Ground.


Ground.

Ground.

Ground.

Ground.



Ground.






Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.








Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

49

Mnemonic

GND

GND

GND

DVDD

DDC1_SDA

GND

TX1_1+

TX1_1−

VS

PCLK

DVDD_IO

DVDD_IO

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

DDC1_SCL

L13

L14

L15

L16

L17

L20

L21

L22

L23

K21

K22

K23

L1

L2

L3

L4

L7

L8

L9

L10

L11

L12

GND

TX1_0+

TX1_0−

P[32]

P[33]

P[34]

P[35]

DVDD

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

HPD_TX1

GND

TX1_C+

TX1_C−

Rev. B, August 2013

Pin

No.

J14

J15

J16

J17

J20

J21

J22

J23

K1

K2

K3

K4

K7

K8

K9

K10

K11

K12

K13

K14

K15

K16

K17

K20


Type

GND

GND

GND

Power

HDMI Tx1

GND

HDMI Tx1

HDMI Tx1

Digital video sync

Digital video sync

Power

Power

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

HDMI Tx1

GND

HDMI Tx1

HDMI Tx1

Digital video input

Digital video input

Digital video input

Digital video input

Power

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

HDMI Tx1

GND

HDMI Tx1

HDMI Tx1

Description

Ground.

Ground.

Ground.



Ground.







Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.


Ground.



Digital Video Input Bus[35:0].





Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.


Ground.



50

M21

N4

N7

N8

N9

N10

N11

N12

N13

N14

N15

N16

N17

N20

N21

M22

M23

N1

N2

N3

P3

P4

P7

P8

N22

N23

P1

P2

Rev. B, August 2013

PVDD5

AVDD3

NC

P[20]

P[21]

P[22]

P[23]

DVDD

GND

HEAC_1+

HEAC_1−

P[24]

P[25]

P[26]

P[27]

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

CEC2

PVDD5

Pin

No.

M1

M2

M3

M4

M7

M8

M9

M10

M11

M12

M13

M14

M15

M16

M17

M20

GND

GND

GND

GND

GND

GND

GND

GND

GND

R_TX1

Mnemonic

P[28]

P[29]

P[30]

P[31]

GND

GND


Type

Digital video input

Digital video input

Digital video input

Digital video input

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

HDMI Tx1 1

Power 1

HDMI Tx1

HDMI Tx1

Digital video input

Digital video input

Digital video input

Digital video input

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

HDMI Tx2

Power 1

Power

No connect

Digital video input

Digital video input

Digital video input

Digital video input

Power

GND

Description





Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Sets Internal Reference Currents. Place a 470 Ω resistor (1% tolerance) between this pin and ground. The external resistor should be placed as close as possible to the

ADV8003.








Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.










Ground.

51

T3

T4

T7

T8

T9

T10

T11

T12

T13

R21

R22

R23

T1

T2

T14

T15

T16

GND

TX2_1+

TX2_1−

P[14]

P[15]

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

Rev. B, August 2013

Mnemonic

GND

GND

GND

GND

GND

GND

GND

GND

DVDD

DDC2_SCL

GND

TX2_2+

TX2_2−

P[16]

P[17]

P[18]

P[19]

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

DDC2_SDA

P11

P12

P13

P14

P15

P16

P17

P20

Pin

No.

P9

P10

P21

P22

P23

R1

R2

R3

R4

R7

R8

R9

R10

R11

R12

R13

R14

R15

R16

R17

R20


Type

GND

GND

GND

GND

GND

GND

GND

GND

Power

HDMI Tx2

GND

HDMI Tx2

HDMI Tx2

Digital video input

Digital video input

Digital video input

Digital video input

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

HDMI Tx2

GND

HDMI Tx2

HDMI Tx2

Digital video input

Digital video input

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

Description

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.



Ground.







Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.


Ground.





Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

52

U3

U4

U7

U8

U9

U10

T21

T22

T23

U1

U2

U11

U12

U13

U14

U15

U16

U17

U20

Pin

No.

T17

T20

GND

DVDD

GND

GND

DVDD

GND

GND

R_TX2

Mnemonic

GND

HPD_TX2

GND

TX2_0+

TX2_0−

P[10]

P[11]

P[12]

P[13]

GND

GND

DVDD

GND

U21

U22

U23

V1

V2

V3

V4

V20

V21

V22

V23

W1

W2

W3

W4

W20

GND

TX2_C+

TX2_C−

P[6]

P[7]

P[8]

P[9]

GND

PVDD6

HEAC_2+

HEAC_2−

P[2]

P[3]

P[4]

P[5]

TEST3

W21 PVDD6

W22

W23

Y1

Y2

AVDD3

NC

P[0]

P[1]

Y3 DDR_DQS[2]

Y4 GND

Rev. B, August 2013


Type

GND

HDMI Tx2

GND

HDMI Tx2

HDMI Tx2

Digital video input

Digital video input

Digital video input

Digital video input

GND

GND

Power

GND

GND

Power

GND

GND

Power

GND

GND

HDMI Tx2 1

GND

HDMI Tx2

HDMI Tx2

Digital video input

Digital video input

Digital video input

Digital video input

GND

Power 1

HDMI Tx2

HDMI Tx2

Digital video input

Digital video input

Digital video input

Digital video input


Power 1

Power

No connect

Digital video input

Digital video input

DDR interface

GND

Description

Ground.


Ground.







Ground.

Ground.


Ground.

Ground.


Ground.

Ground.


Ground.

Ground.

Sets internal reference currents. Place a 470 Ω resistor (1% tolerance) between this pin and ground. The external resistor should be placed as close as possible to the ADV8003.

Ground.







Ground.








Test Pin. Connect this pin to Ground through a 0.1 uF capacitor.







Ground.

53

AA9 DDR_A[8]

AA10 DVDD_DDR

AA11 DDR_A[2]

AA12 GND

AA13 DDR_CS

AA14 DVDD_DDR

AA15 DDR_CK

AA16 GND

AA17 DDR_DQ[11]

AA18 DVDD_DDR

AA19 DDR_DM[1]

AA20 DDR_DM[0]

AA21 GND

AA22 GND

AA23 DDR_DQ[3]

AB1

AB2

AB3

DDR_DQ[21]

DDR_DQ[19]

DDR_DQ[17]

AB4

AB5

DDR_DM[2]

DDR_DQ[30]

Rev. B, August 2013

Mnemonic

DDR_DQ[23]

DVDD_DDR

DDR_DQS[3]

GND

DDR_A[11]

DVDD_DDR

DDR_A[4]

GND

DDR_RAS

DVDD_DDR

DDR_CK

GND

DDR_DQ[9]

DVDD_DDR

DDR_DQ[14]

GND

DDR_DQ[6]

PVDD_DDR

GND

DDR_DQ[18]

GND

GND

DDR_DQS[2]

DDR_DQ[26]

DVDD_DDR

DDR_DQS[3]

NC/GND

Y7

Y8

Y9

Y10

Y11

Y12

Y13

Pin

No.

Y5

Y6

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8


Type

DDR interface

Power

DDR interface

GND

DDR interface

Power

DDR interface

GND

DDR interface

Power

DDR interface

GND

DDR Interface

Power

DDR interface

GND

DDR interface

Power

GND

DDR interface

GND

GND

DDR interface

DDR interface

Power

DDR interface

No connect/GND

DDR interface

Power

DDR interface

GND

DDR interface

Power

DDR interface

GND

DDR interface

Power

DDR interface

DDR interface

GND

GND

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

Description




Ground.




Ground.




Ground.




Ground.



Ground.


Ground.

Ground.









Ground.




Ground.





Ground.

Ground.







54


Pin

No.

AB6

AB7

AB8

AB9

AB10

AB11

AB12

AB13

AB14

Mnemonic

DDR_DM[3]

DDR_DQ[31]

DDR_DQ[29]

DDR_A[12]

DDR_A[6]

DDR_A[3]

DDR_A[0]

DDR_BA[0]

DDR_RAS

AC2

AC3

AC4

AC5

AC6

AC7

AC8

AC9

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AC1

AC10 DDR_A[7]

AC11 DDR_A[1]

AC12 DDR_A[10]

AC13 DDR_BA[1]

AC14 DDR_BA[2]

AC15 DDR_WE

AC16 DDR_VREF

AC17 DDR_DQ[10]

AC18 DDR_DQS[1]

AC19 DDR_DQ[15]

AC20 DDR_DQ[7]

AC21 DDR_DQ[2]

AC22 DDR_DQS[0]

AC23 DDR_DQ[1]

DDR_CKE

DDR_DQ[12]

DDR_DQS[1]

DDR_DQ[8]

DDR_DQ[13]

DDR_DQ[0]

DDR_DQ[5]

DDR_DQS[0]

DDR_DQ[4]

DDR_DQ[16]

DDR_DQ[20]

DDR_DQ[22]

DDR_DQ[25]

DDR_DQ[28]

DDR_DQ[27]

DDR_DQ[24]

DDR_A[9]

DDR_A[5]

Type

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface 1

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

Description













































A

B

C

D

E

1

OSD_

IN[23]/

EXT_

DIN[7]

OSD_

IN[21]/

EXT_

DIN[5]

OSD_

IN[19]/

EXT_

DIN[3]

OSD_

IN[16]/

EXT_

DIN[0]

2

OSD_

DE

3

OSD_

CLK/

EXT_

CLK

OSD_

IN[22]/

EXT_

DIN[6]

OSD_

IN[20]/

EXT_

DIN[4]

OSD_

IN[17]/

EXT_

DIN[1]

OSD_

VS

GND

OSD_

IN[18]/

EXT_

DIN[2]

OSD_

IN[13]/

VBI_SCK

OSD_

IN[14]/

VBI_MOSI

OSD_

IN[15]/

VBI_CS

4

TEST4

TEST8

GND

DVDD_

IO

5

TEST5

6

TEST6

7

TEST7

8

TEST9 TEST10 TEST11 MISO1

TEST12 TEST13 TEST14

DVDD_

IO

TEST15

SCL

SDA

MOSI1

SCK1

CS1

9

SCK2


GND

10

CS2

INT0

GND TEST16

11

PDN

12

GND

13


GND

INT2

DVDD_

IO

TEST1

F

G

H

J

K

L

OSD_

IN[9]

OSD_

IN[10]

OSD_

IN[11]

OSD_

IN[12]

OSD_

IN[5]

OSD_

IN[6]

OSD_

IN[1]

OSD_

IN[2]

OSD_

IN[7]

OSD_

IN[3]

OSD_

IN[8]

OSD_

IN[4]

DE

VS

P[32]

HS

OSD_

HS

OSD_

IN[0]

PCLK

DVDD_

IO

DVDD_

IO

P[33] P[34] P[35]

GND

GND

DVDD

GND

DVDD

GND

GND

GND

GND

GND

GND DVDD

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

14

NC

NC

NC

NC

GND DVDD GND

GND

GND

GND

GND

15

NC

NC

16



RX_

HPD


NC

RX_5V NC

GND GND

GND GND

GND GND DVDD

GND GND

GND GND

17

GND

GND

GND

GND

18 19 20


NC

TEST2 GND

NC PVDD3 GND

GND GND

23


NC

NC

NC

21

GND

GND

GND

22

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

A

B

C

D

E

F

G

H

J

K

L

M P[28] P[29] P[30] P[31] GND GND GND GND GND GND GND GND GND GND GND NC PVDD5 NC NC M

N

P[24] P[25] P[26] P[27] GND GND GND GND GND GND GND GND GND GND GND NC PVDD5 AVDD3 NC N

DVDD GND GND GND GND GND GND GND GND GND DVDD NC GND NC NC P P[20] P[21] P[22] P[23]

R P[16] P[17] P[18] P[19] GND GND GND GND GND GND GND GND GND GND GND NC GND NC NC

P

R

T P[14] P[15] GND GND GND GND GND GND GND GND GND GND GND GND GND NC GND NC NC T

U P[10] P[11] P[12] P[13]

V P[6] P[7] P[8] P[9]

GND GND DVDD GND GND DVDD GND GND DVDD GND GND NC GND NC

GND PVDD6 NC

NC

NC

U

V

W P[2] P[3] P[4] P[5] TEST3 PVDD6 AVDD3 NC W

Y

AA

DDR_

DQ[18]

AB

P[0]

DDR_

DQ[21]

DDR_

DQ[19]

DDR_

DQ[17]

DDR_

DM[2]

DDR_

DQ[30]

DDR_

DM[3]

DDR_

DQ[31]

DDR_

DQ[29]

DDR_

A[12]

DDR_

A[6]

AC

DDR_

DQ[16]

DDR_

DQ[20]

DDR_

DQ[22]

DDR_

DQ[25]

DDR_

DQ[28]

DDR_

DQ[27]

DDR_

DQ[24]

DDR_

A[9]

1

P[1]

GND

DDR_

DQS[2]

GND

DDR_

DQ[23]

DVDD_

DDR

DDR_

DQS[3]

GND

DDR_

DQS[2]

DDR_

DQ[26]

DVDD_

DDR

DDR_

DQS[3]

GND

NC/

GND

2 3 4 5 6 7

DDR_

A[11]

DVDD_

DDR

DDR_

A[4]

DDR_

A[8]

DVDD_

DDR

DDR_

A[2]

DDR_

A[5]

DDR_

A[7]

GND

GND

DDR_

A[3]

DDR_

A[0]

DDR_

A[1]

DDR_

A[10]

DDR_

CAS

DVDD_

DDR

DDR_

CK

GND

DDR_

DQ[9]

DVDD_

DDR

DDR_

DQ[14]

GND

DDR_

CS

DVDD_

DDR

DDR_

CK

DDR_

BA[0]

DDR_

BA[1]

DDR_

RAS

DDR_

BA[2]

DDR_

WE

GND

DDR_

VREF

DDR_

DQ[11]

DVDD_

DDR

DDR_

DM[1]

DDR_

DM[0]

DDR_

CKE

DDR_

DQ[12]

DDR_

DQS[1]

DDR_

DQ[8]

DDR_

DQ[13]

DDR_

DQ[0]

DDR_

DQ[10]

DDR_

DQS[1]

DDR_

DQ[15]

DDR_

DQ[7]

17 18 19 20 8 9 10 11 12 13 14 15 16

Figure 10. ADV8003KBCZ-7T Pin Configuration

DDR_

DQ[6]

PVDD_

DDR

GND

GND GND

DDR_

DQ[3]

DDR_

DQ[5]

DDR_

DQS[0]

DDR_

DQ[4]

DDR_

DQ[2]

DDR_

DQS[0]

DDR_

DQ[1]

21 22 23

Y

AA

AB

AC



A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

B1

Table 5. ADV8003KBCZ-7T Pin Function Descriptions

Pin

No.

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

Mnemonic


]

OSD_DE

OSD_CLK/EXT_CLK

TEST4

TEST5

TEST6

TEST7

MOSI1

SCK2

CS2

Type


OSD video sync

OSD video sync

Description




Pixel Clock for the OSD Input Port (OSD_CLK)/Pixel Clock for External Video

Data (EXT_CLK).

Miscellaneous digital Test Pin. Connect this pin to Ground through a 4.7 kΩ resistor.




Serial port control Master Out Slave In (Serial Port 1). Serial Port 1 is used for OSD control.

Serial port control

Serial port control



B2

B3

B4

B5

B6

B7

B8

B9

B10

RESET

XTALN

PVDD2

NC

NC

CVDD1

RX_CN

RX_0N

RX_1N

RX_2N

CVDD1

NC

NC


]


]

OSD_VS

TEST8

TEST9

TEST10

TEST11

MISO1

MOSI2

MISO2

B11

B12

B13

B14

B15

B16

B17

ALSB

XTALP

PVDD1

NC

NC

GND

RX_CP

B18

B19

RX_0P

RX_1P

Rev. B, August 2013

Miscellaneous digital Reset Pin for the ADV8003.

Miscellaneous digital 1

Crystal Input.

Power

No connect

No connect

Power

Rx input

Rx input

Rx input

Rx input

Power










No connect

No connect









OSD video sync Vertical Sync for the OSD Input Port.





Serial port control Master In Slave Out (Serial Port 1). Serial Port 1 is used for OSD control.

Serial port control Master Out Slave In (Serial Port 2). Serial Port 2 is used for the external flash

ROM.

Serial port control Master In Slave Out (Serial Port 2). Serial Port 2 is used for the external flash

ROM.

I 2 C control Sets LSB of ADV8003 I 2 C address (0x18 with LSB low, 0x1A with LSB high).


1


Power PLL Analog Supply Voltage (1.8 V).

No connect

No connect

GND

Rx input

Rx input

Rx input



Ground.




57


B20

B21

B22

B23

C1

C2

C3

C4

C5

C6

C7

D2

D3

D4

D5

D6

D7

C15

C16

C17

C18

C19

C20

C21

C22

C23

D1

C8

C9

C10

C11

C12

C13

C14

D8

D9

D10

D11

D12

D13

D14

D15

D16

RX_2P

GND

NC

NC


]


]

GND

TEST12

TEST13

TEST14

SCL

SCK1

GND

INT0

PDN

GND

GND

NC

NC

RX_HPD

AVDD1

GND

GND

AVDD1

AVDD1

NC

NC


]


]


]

GND

DVDD_IO

TEST15

SDA

CS1

GND

TEST16

INT2

DVDD_IO

TEST1

NC

NC

RX_5V

Rev. B, August 2013

Rx input

GND

No connect

No connect




Ground.







GND Ground.




I 2 C control I 2 C Clock Input. This pin is open drain; use a 4.7 kΩ resistor to connect this pin to a 3.3 V supply.

Serial port control

GND


Ground.

Miscellaneous digital Interrupt Pin 0. When status bits change, this pin is triggered.

Miscellaneous digital Power-Down. This pin controls the power state of the ADV8003.

GND Ground.

GND

No connect

Ground.


No connect

Rx input

Power

GND

GND




Ground.

Ground.

Power

Power

No connect

No connect








GND

Power







Ground.



I 2 C control I 2 C Data Input. This pin is open drain; use a 4.7 kΩ resistor to connect this pin to a 3.3 V supply.

Serial port control Chip Select (Serial Port 1). Serial Port 1 is used for OSD control.

GND Ground.


Miscellaneous digital Interrupt Pin for HDMI Receiver Input Lines. When status bits change, an interrupt is generated on this pin.


Miscellaneous digital Test Pin. Float this pin.

No connect

No connect

Rx input




58


D20

D21

D22

D23

E1

E2

E3

F1

F2

F3

F4

E4

E20

E21

E22

E23

G12

G13

G14

G15

G16

G17

G20

G21

G22

G23

H1

H2

H3

G2

G3

G4

G7

G8

G9

G10

G11

F20

F21

F22

F23

G1

D17

D18

D19

GND

DVDD

GND

GND

GND

GND

ELPF1

ELPF2

GND

AVDD3

OSD_IN[1]

OSD_IN[2]

OSD_IN[3]

NC

PVDD3

GND

NC

OSD_IN[5]

OSD_IN[6]

OSD_IN[7]

OSD_IN[8]

GND

GND

GND

DVDD

GND

NC

NC

RTERM

AVDD2

AVDD2

NC

NC

OSD_IN[13]/VBI_SCK

DVDD_IO

TEST2

GND

NC

NC

OSD_IN[9]

OSD_IN[10]

OSD_IN[11]

OSD_IN[12]

No connect

No connect

HDMI Rx input

Power

Power

No connect

No connect


OSD_IN[14]/VBI_MOSI OSD video input/ miscellaneous digital









External OSD Video Pixel Input Port (OSD_IN[13])/Serial Clock for VBI Data

Serial Port (VBI_SCK).

External OSD Video Pixel Input Port (OSD_IN[14])/Master Out Slave In for VBI

Data Serial Port (VBI_MOSI).

External OSD Video Pixel Input Port (OSD_IN[15])/Chip Select for VBI Data

Serial Port (VBI_CS).


Miscellaneous analog Test Pin. Float this pin.

GND Ground.

No connect

No connect



OSD video input

OSD video input

OSD video input


No connect

Power

GND

No connect






PLL Supply (1.8 V).

Ground.


External OSD Video Pixel Input Port (OSD_IN[5]). OSD video input

OSD video input

OSD video input

OSD video input

GND

GND

GND

Power

GND

GND

Power

GND

GND

GND




Ground.

Ground.

Ground.


Ground.

Ground.


Ground.

Ground.

Ground.

GND Ground.

Miscellaneous analog 1


Miscellaneous analog 1


GND Ground.

Power

OSD video input

OSD video input

OSD video input






GND

GND

GND

GND

DVDD

NC

GND

NC

NC

VS

HS

OSD_HS

OSD_IN[0]

DVDD

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

NC

NC

DE

OSD_IN[4]

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

PCLK

DVDD_IO

DVDD_IO

GND

GND

GND

GND

GND

Rev. B, August 2013

H4

H7

H8

J13

J14

J15

J16

J17

J20

J21

J22

J23

K1

J2

J3

J4

J7

J8

J9

J10

J11

J12

H20

H21

H22

H23

J1

H9

H10

H11

H12

H13

H14

H15

H16

H17

K12

K13

K14

K15

K16

K17

K2

K3

K4

K7

K8

K9

K10

K11


OSD video input

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

No connect

No connect

Digital video sync

Digital video sync

Digital video sync

OSD video input

Power

GND

GND

GND

GND

GND

GND

GND

GND

GND

Power

No connect

GND

No connect

No connect

Digital video sync

GND

GND

GND

GND

GND

GND

Digital video sync

Power

Power

GND

GND

GND

GND

GND


Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.








Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.



Ground.







Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

60

N4

N7

N8

N9

M22

M23

N1

N2

N3

NC

NC

P[24]

P[25]

P[26]

P[27]

GND

GND

GND

Rev. B, August 2013

P[28]

P[29]

P[30]

P[31]

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

NC

GND

NC

NC

GND

GND

GND

GND

GND

GND

NC

PVDD5

NC

GND

NC

NC

P[32]

P[33]

P[34]

P[35]

DVDD

GND

GND

GND

GND

K20

K21

K22

M1

M2

M3

M4

M7

M8

M9

M10

M11

L16

L17

L20

L21

L22

L23

M12

M13

M14

M15

M16

M17

M20

M21

L7

L8

L9

L10

L11

L12

L13

L14

L15

K23

L1

L2

L3

L4


No connect

GND

No connect

No connect

Digital video input

Digital video input

Digital video input

Digital video input

Power

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

No connect

GND

No connect

No connect

Digital video input

Digital video input

Digital video input

Digital video input

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

No connect

Power 1

No connect

No connect

Digital video input

Digital video input

Digital video input

Digital video input

GND

GND

GND


Ground.








Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.


Ground.







Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.


PLL Power Supply (1.8 V). This pin is a voltage regulator output. Connect a decoupling capacitor between this pin and ground.







Ground.

Ground.

Ground.

61

N10

N11

N12

N13

N14

N15

N16

N17

N20

N21

R1

R2

R3

R4

R7

R8

R9

R10

P16

P17

P20

P21

P22

P23

R11

R12

R13

R14

R15

R16

R17

R20

R21

R22

P7

P8

P9

P10

P11

P12

P13

P14

P15

N22

N23

P1

P2

P3

P4

P[16]

P[17]

P[18]

P[19]

GND

GND

GND

GND

GND

DVDD

NC

GND

NC

NC

GND

GND

GND

GND

GND

GND

GND

NC

GND

NC

AVDD3

NC

P[20]

P[21]

P[22]

P[23]

DVDD

GND

GND

GND

GND

GND

GND

GND

GND

Rev. B, August 2013

GND

GND

GND

GND

GND

GND

GND

GND

NC

PVDD5


GND

GND

GND

GND

GND

GND

GND

GND

No connect

Power 1

Power

No connect

Digital video input

Digital video input

Digital video input

Digital video input

Power

GND

GND

GND

GND

GND

GND

GND

GND

GND

Power

No connect

GND

No connect

No connect

Digital video input

Digital video input

Digital video input

Digital video input

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

No connect

GND

No connect

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.










Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.



Ground.







Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.


Ground.


62

P[11]

P[12]

P[13]

GND

GND

DVDD

GND

GND

DVDD

GND

GND

GND

GND

NC

GND

NC

NC

P[10]

NC

P[14]

P[15]

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

DVDD

GND

GND

NC

GND

NC

NC

P[6]

P[7]

P[8]

P[9]

GND

PVDD6

R23

U2

U3

U4

U7

U8

U9

U10

U11

U12

T20

T21

T22

T23

U1

T9

T10

T11

T12

T13

T14

T15

T16

T17

T1

T2

T3

T4

T7

T8

U13

U14

U15

U16

U17

U20

U21

U22

U23

V1

V2

V3

V4

V20

V21

V22

V23

W1

W2

NC

NC

P[2]

P[3]

Rev. B, August 2013


No connect

Digital video input

Digital video input

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

No connect

GND

No connect

No connect

Digital video input

Digital video input

Digital video input

Digital video input

GND

GND

Power

GND

GND

Power

GND

GND

Power

GND

GND

No connect

GND

No connect

No connect

Digital video input

Digital video input

Digital video input

Digital video input

GND

Power 1

No connect

No connect

Digital video input

Digital video input




Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.


Ground.







Ground.

Ground.


Ground.

Ground.


Ground.

Ground.


Ground.

Ground.


Ground.







Ground.






63

AA9 DDR_A[8]

AA10 DVDD_DDR

AA11 DDR_A[2]

AA12 GND

AA13 DDR_CS

AA14 DVDD_DDR

AA15 DDR_CK

AA16 GND

AA17 DDR_DQ[11]

AA18 DVDD_DDR

AA19 DDR_DM[1]

Rev. B, August 2013

P[4]

P[5]

TEST3

PVDD6

DVDD_DDR

DDR_CK

GND

DDR_DQ[9]

DVDD_DDR

DDR_DQ[14]

GND

DDR_DQ[6]

PVDD_DDR

GND

DDR_DQ[18]

GND

GND

DDR_DQS[2]

DDR_DQ[26]

DVDD_DDR

DDR_DQS[3]

NC/GND

AVDD3

NC

P[0]

P[1]

DDR_DQS[2]

GND

DDR_DQ[23]

DVDD_DDR

DDR_DQS[3]

GND

DDR_A[11]

DVDD_DDR

DDR_A[4]

GND

DDR_CAS

W3

W4

W20

W21

W22

W23

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y8

Y9

Y10

Y11

Y12

Y13

Y14

Y15

AA1

AA2

AA3

AA4

AA5

AA6

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

AA7

AA8


Digital video input

Digital video input



Miscellaneous digital Test Pin. Connect this pin to Ground through a 0.1 uF capacitor.

Power 1

Power

No connect

Digital video input

Digital video input






DDR interface

GND

DDR interface

Power

DDR interface

GND

DDR interface

Power

DDR interface

GND

DDR interface


Ground.




Ground.




Ground.


Power

DDR interface



GND

DDR Interface

Power

DDR interface

GND

DDR interface

Power

GND

DDR interface

GND

GND

DDR interface

DDR interface

Power

DDR interface

No connect/GND

DDR interface

Power

DDR interface

GND

DDR interface

Power

DDR interface

GND

DDR interface

Power

DDR interface

Ground.




Ground.



Ground.


Ground.

Ground.









Ground.




Ground.




64

AA20 DDR_DM[0]

AA21 GND

AA22 GND

AA23 DDR_DQ[3]

AB1

AB2

AB3

AB4

DDR_DQ[21]

DDR_DQ[19]

DDR_DQ[17]

DDR_DM[2]

AB5

AB6

AB7

AB8

AB9

AB10

AB11

AB12

AB13

AB14

AB15

AB16

DDR_DQ[30]

DDR_DM[3]

DDR_DQ[31]

DDR_DQ[29]

DDR_A[12]

DDR_A[6]

DDR_A[3]

DDR_A[0]

DDR_BA[0]

DDR_RAS

DDR_CKE

DDR_DQ[12]

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AC1

AC2

DDR_DQS[1]

DDR_DQ[8]

DDR_DQ[13]

DDR_DQ[0]

DDR_DQ[5]

DDR_DQS[0]

DDR_DQ[4]

DDR_DQ[16]

DDR_DQ[20]

AC3

AC4

AC5

AC6

AC7

DDR_DQ[22]

DDR_DQ[25]

DDR_DQ[28]

DDR_DQ[27]

DDR_DQ[24]

AC8

AC9

DDR_A[9]

DDR_A[5]

AC10 DDR_A[7]

AC11 DDR_A[1]

AC12 DDR_A[10]

AC13 DDR_BA[1]

AC14 DDR_BA[2]

AC15 DDR_WE

AC16 DDR_VREF

AC17 DDR_DQ[10]

AC18 DDR_DQS[1]

AC19 DDR_DQ[15]

AC20 DDR_DQ[7]

AC21 DDR_DQ[2]

AC22 DDR_DQS[0]

AC23 DDR_DQ[1]

Rev. B, August 2013

DDR interface

GND

GND

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface 1

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface

DDR interface



Ground.

Ground.
















































65





1.5.

PROTOCOL FOR MAIN I

2

C PORT

The system controller initiates a data transfer by establishing a start condition, defined by a high to low transition on SDA while SCL remains high. This transition indicates that an address/data stream will follow. All peripherals respond to the start condition and shift the next eight bits (7-bit address and R/W bit). The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition.

In the idle condition, the device monitors the SDA and SCL lines for the start condition and the correct transmitted address. The R/W bit determines the direction of the data. A logic 0 on the LSB of the first byte means that the master will write information to the peripheral. A logic 1 on the LSB of the first byte means that the master will read information from the peripheral.

The ADV8003 has a single 8-bit I as the I 2

2 C slave address. All register maps within the ADV8003 can be accessed through this I 2 through 16-bit addressing and 8-bit data registers. The ADV8003 acts as a standard slave device on the I 2

C address

C bus. It interprets the first byte

C address and the second byte and third bytes as the appropriate subaddress. The fourth byte is then considered the data for this subaddress register. This means that I 2 C writes to the part will be in the form <I 2 C Address>, <Address MSBs>, <Address LSBs>, <Data>.

For example, to write 0xFF to the encoder register map, register 0x59AF, the I 2 C writes needed are 0x1A, 0x59, 0xAF, 0xFF. The addresses

are outlined in Table 6 . Figure 11 shows the register map architecture for the ADV8003.

Table 6: ADV8003 I 2 C Address and Register Address Range for Different HW Blocks

Register Map Name I 2 C Address Register Address

IO Map 0x1A (0x18 with LSB low) 0x1A00 to 0x1BFF

Primary VSP Map

Primary VSP Map 2

Secondary VSP Map

0xE800 to 0xE8FF

0xE900 to 0xE9FF

0xE600 to 0xE6FF

Rx Main Map

Rx InfoFrame Map

Tx1 Main Map

Tx1 EDID Map

Tx1 CEC Map

Tx1 UDP Map

Tx1 Test Map

Tx2 Main Map

0xE200 to 0xE2FF

0xE300 to 0xE3FF

0xEC00 to 0xECFF

0xEE00 to 0xEEFF

0xF000 to 0xF0FF

0xF200 to 0xF2FF

0xF300 to 0xF3FF

0xF400 to 0xF4FF

Tx2 EDID Map

Tx2 CEC Map

Tx2 UDP Map

Tx2 Test Map

Encoder Map

DPLL Map

0xF600 to 0xF6FF

0xF800 to 0xF8FF

0xFA00 to 0xFAFF

0xFB00 to 0xFBFF

0xE400 to 0xE4FF

0xE000 to 0xE0FF

I

2

C

ADDRESS

0x18/0x1A

SCL

SDA

IO

MAP

0x1A00 TO

0x1BFF

0xEC00 TO

0xECFF

Tx1 MAIN

MAP

Rev. B, August 2013

PRIMARY VSP

MAP

0xE800 TO

0xE8FF

PRIMARY VSP

MAP 2

0xE900 TO

0xE9FF

SECONDARY

VSP MAP

0xE600 TO

0xE6FF

DPLL

MAP

0xE000 TO

0xE0FF

0xEE00 TO

0xEEFF

Tx1 EDID

MAP

0xF000 TO

0xF0FF

Tx1 CEC

MAP

Rx MAIN

MAP

0xE200 TO

0xE2FF

Rx INFOFRAME

MAP

0xE300 TO

0xE3FF

ENCODER

MAP

0xE400 TO

0xE4FF

0xF200 TO

0xF2FF

Tx1 UDP

MAP

0xF400 TO

0xF4FF

Tx2 MAIN

MAP

0xF600 TO

0xF6FF

Tx2 EDID

MAP

Figure 11: Register Map Architecture

67

0xF800 TO

0xF8FF

Tx2 CEC

MAP

0xFA00 TO

0xFAFF

Tx2 UDP

MAP

Tx1 TEST

MAP

0xF300 TO

0xF3FF

0xFB00 TO

0xFBFF

Tx2 TEST

MAP


It is possible to use the subaddresses auto-increment feature, which allows data to be accessed from the starting subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without having to update all the registers.

Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, these cause an immediate jump to the idle condition. During a given SCLK high period, the user should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADV8003 does not issue an acknowledge and returns to the idle condition.

If the user exceeds the highest subaddress in auto increment mode, the following actions are taken:

• In read mode, the highest subaddress register contents continue to be output until the master device issues a no acknowledge.

This indicates the end of a read. A no acknowledge condition is where the SDA line is not pulled low on the ninth pulse.

• In write mode, the data for the invalid byte is not loaded into any subaddress register. A no acknowledge is issued by the

ADV8003 and the part returns to the idle condition.

Figure 12: Bus Data Transfer

Figure 13: Read and Write Sequence

1.6.

CONFIGURING THE ADV8003

The ADV8003 requires a number of configuration settings for each mode of operation. To ensure the part is correctly configured, refer to either the recommended settings configuration script (supplied with the ADV8003 evaluation software) or the reference software driver.

Failure to follow these recommended settings will result in the part not operating to its optimum performance.



2.

ADV8003 TOP LEVEL CONTROL

Input

Muxing

& CSC o c v

VSP - YCbCr 4:4:4 Input and Output

- Deinterlacer

- Scaler

- Video enhance

OSD Core

- OSD scaler

- External OSD

- Internal OSD 36/48-

Video

Port

Conversio

CSC &

ACE

Serial

Video�

RX

& CSC

-Scaler

Figure 14: ADV8003 Simplified Block Diagram

A simplified block diagram of the ADV8003 can be seen in Figure 14 . Video can be routed through the ADV8003 in a number of ways, for

example, the OSD can be blended before the PVSP to display the OSD on all outputs, the OSD can be blended before the output to display the OSD on a single output. This has been divided into several modes of operation which are recommended by Analog Devices. These modes of operation are documented in

Section 2.1 and outline the most practical modes in which to configure the ADV8003.

The four main processing blocks of the ADV8003 are described as follows.

PVSP: This is the main scaler of the ADV8003 and contains many of the signal processing functions. This block performs motion adaptive de-interlacing as well as scaling, ACE, FRC, cadence detection, CUE correction, RNR, BNR and MNR. PVSP utilizes the external

DDR2 memory for such processes as FRC, de-interlacing and RNR. (Refer to Section 3.2

for more details on the PVSP.)

SVSP : This is the secondary scaler in the ADV8003 and is useful when providing an additional output resolution. The input to this block can only be progressive. This means an input format can only be connected to the SVSP if it is progressive or if it has been de-interlaced by

the PVSP block. (Refer to Section 3.3 for more details on the SVSP.)

OSD Blend: This block overlays the generated OSD on the incoming video signal, from the Serial Video input lines or from the video

TTL port. This is determined by an alpha factor as to how transparent the OSD will be. Depending on the source of the OSD data (from an external OSD solution or DDR2 memory), this is then synchronized with the incoming video signal. If the generated resolution is the same as the video, the OSD is simply overlaid on the video. If both are at different resolutions, the OSD scaler will first scale the OSD data

to match the incoming video. (Refer to Section 3 for more details on the OSD.)

Progressive to Interlaced: The ADV8003 has two progressive to interlaced (PtoI) blocks, one of these is included as part of the SVSP. The second is a standalone block. The function of this block is exactly as named and can be used, for example, if the user was to convert an ED

format such as 480p to a HD format such as 1080i. The PtoI block would be required as part of this conversion. (Refer to Section 3.2.3

and

Section 3.3.3

for more details on the PtoI hardware blocks.)



2.1.

ADV8003 MODES OF OPERATION

This section outlines the most practical modes in which the ADV8003 can be configured, as recommended by ADI. These modes describe

the various ways to configure the VSP block, depending on the input formats as well as the outputs required. Table 7 outlines the various

options afforded to the user in each mode. Depending on the desired output options, the appropriate mode should be chosen.

Mode 1

Mode 2

Mode 3

Mode 4

Mode 5

Mode 6

Mode 7

3

2

2

3

2

1-2

Mode 8

Mode 9 - Bypass

Mode 10 (PiP)

Mode 11 (PiP)

Mode 12 (Dual OSD) 1

Mode 13 (RX OSD) 2

Mode 14 (3 Inputs) 3

2

1

1-2

1

Table 7: ADV8003 Modes of Operation

No. of Different

Output Formats

12

Interlaced Input

Format Allowed

No. of Output

Formats with

OSD

3

3 Yes 1

Yes

No (if using SVSP)

Yes

No (if using SVSP)

No (if using SVSP)

Yes

Yes

Yes

No (if using SVSP)

No (if using SVSP)

Yes

Yes

Yes

2

2

2

2

2

3

3

1

1

1-2

1-2

0

2

Input Video

Copy-Protected

Yes

Yes

No

No

Yes

Yes

Yes

No

No

No

No

No

No

Yes

1 For modes that offer four possible output formats, this means without reconfiguring the digital core. Only three possible output formats are supported at a single time: the input format and the two converted formats.

2 The number of different output formats will be limited when using the ADV8003KBCZ-8B/7B, ADV8003KBCZ-8C/7C and ADV8003KBCZ-7T, for example, one

3 output format.

The number of output formats with OSD will be limited when using the ADV8003KBCZ-8B/7B, ADV8003KBCZ-8C/7C and ADV8003KBCZ-7T.



Note: Table 7 does not list the definitive operation of the device in each mode. For example, in mode 3, it is listed as possible to have two

different output resolutions and just have OSD on a single output. However, using the output muxing, it would also be possible to have a

single output format (1080p in this case) with OSD going to several outputs. Table 7

provides only a guideline for the ADV8003 and

should be used as such. Depending on user requirements, many of these modes could be tailored to a specific solution. Section 2.1.2 to

Section 2.1.9 describe the usable modes of operation as recommended by ADI. These modes should be studied and the appropriate one

selected for a given application.

2.1.1.

Selecting a Mode

General guidelines for selecting a mode of operation involve selecting the location of certain blocks in the VSP section. For example, mode

5 and mode 6 both use the PVSP and SVSP in parallel. However, as the SVSP can only accept progressive formats, input video to the

ADV8003 must be progressive. If interlaced, only the PVSP can be used. Therefore, a note should be kept of the input formats if selecting these in parallel mode.

The location of the OSD blend core must then be selected. This can be placed before the PVSP and both the input video and OSD can be scaled at the same time. However, depending on the application, the optimal solution may be to have both the input video and OSD scaled separately and then blended.

If blending the OSD after the PVSP, the OSD may need to be scaled to different resolutions. This can be done in two ways:

1.

The OSD bitmap images are created at higher resolutions.

2.

The OSD can be rendered at a single resolution and scaled internally in the ADV8003 using the OSD scaler.

There are limitations to both of these methods. Rendering OSDs at larger resolutions increases the system resources required to store these bitmaps. Alternatively, scaling the OSD internally in the part increases power consumption on the ADV8003.

The optimum solution to this depends on customer requirements and system capabilities. It should be chosen taking these considerations into account.

Note: For the following modes of operation, red indicates an active video path and black indicates a path is not used. If, for example, there are two red dashed lines, video may be available on one or the other but not on both.

2.1.2.

Mode 1

Mode 1 should be used if:

• Three separate output formats are required

• Additional processing (BNR, RNR, and so on) is required on the new output formats

• OSD is required on a single output format (most likely the lowest quality of the converted formats)



Figure 15: ADV8003 Mode 1 Configuration

Mode 1 places the PVSP after the input block. The output from this block is then sent to the SVSP or the PtoI converter. The OSD blend block can then be placed after the SVSP block.

In the example in Figure 15 , the input resolution is taken to be 480i. This is then passed through the PVSP where it is converted to 1080p

using motion adaptive de-interlacing. This can then be passed straight to the output, to the PtoI converter or, alternatively, to the SVSP and OSD blend. The example output formats generated using this mode are 720p (with OSD), 1080p and 1080i. The input SD format of

480i can also be passed to the SD encoder.


2.1.3.

Mode 2


• Three separate output formats are required

• Additional processing (BNR, RNR, and so on) is required on the new output formats

• OSD is required on multiple outputs

• OSD and video scaling are to be kept separate



Mode 2 places the PVSP after the input block. The output from this is sent to the OSD which is in turn sent to the SVSP or PtoI converter.

This mode is very similar to mode 4, except that the OSD position has swapped with the PVSP. The primary reason is that, in this case, the OSD data is not overlaid on the incoming video data and then scaled, but rather scaled and then overlaid. Scaling the video and OSD separately may improve the quality of the video input to the SVSP. If it is possible, it is better to scale video and OSD separately and then blend rather than scaling both together.

The example in Figure 16 takes a 480i video signal and scales this to 1080p. This is then overlaid with OSD data scaled to 1080p. This

example can generate three different output formats (720p, 1080i, and 1080p) as well as outputting the input SD standard of 480i.


2.1.4.

Mode 3


• Two separate upscaled resolutions are required

• De-interlacing is not required

• OSD is required on one resolution only (preferably the higher resolution output)



Both the PVSP and SVSP work in parallel in this mode. As the OSD is only on one data path, it will only be displayed at a single

resolution. As shown in the example in Figure 17 , the input to the SVSP must be a progressive format. Therefore, this mode can only be

used when the input is progressive. This mode allows the user to overlay the OSD on the higher resolution output(s).

It can be seen in Figure 17 that the same output formats can be generated in this mode. However, the OSD is now only generated on the

higher resolution outputs. This mode allows the user to generate two different outputs resolutions and only display OSD on one output.

Note: De-interlaced inputs can be input to the device in this mode; however the SVSP can only accept progressive input formats.

Therefore, the SVSP would be excluded from the processing in this case.


2.1.5.

Mode 4


• Three possible separate output formats are required

• Additional processing is required on the new output formats

• OSD is required on multiple output formats



Mode 4 places the OSD blend block before the PVSP. The output of the PVSP is then input to both the SVSP and the PtoI converter. The

OSD is overlaid on all output formats. In addition, high performance PVSP processing is performed on all outputs which can improve video quality at all resolutions. While blending the OSD on the incoming video, the OSD can be scaled to the necessary resolution of the incoming video using the OSD scaler.

In the example in Figure 18 , the input resolution is taken to be 480p. The OSD is downscaled, blended, and passed to the PVSP which

scales to 1080p. The advantage of configuring the ADV8003 core in this way is that by including the PVSP on multiple data path,

additional processing can be included on other outputs also. In Figure 18 , three different formats (1080p, 1080i, and 720p) can be

generated.


2.1.6.

Mode 5




• OSD is required on both output formats



Mode 5 places the OSD blend block before both the PVSP block and the SVSP block. Both the PVSP block and the SVSP work in parallel

in this mode. As the OSD is before both scalers, the OSD will be available on all the outputs. As mentioned in Section 2.1.4, the input to

the SVSP must be progressive, therefore, this mode can only be used when the input is progressive.

As can be seen in the example in Figure 19 , the output formats required are 1080p and 720p. The 1080p format is converted through the

PVSP block with the SVSP upscaling to 720p. It should be noted from Figure 19 , that when large video scalings are required, these should

be processed by the PVSP block for optimal performance.

Note: De-interlaced inputs can be input to the device in this mode; however the SVSP can only accept progressive input formats.

Therefore, the SVSP would be excluded from the processing in this case.


2.1.7.

Mode 6




• OSD is required on one resolution only (preferably the lower upscaled resolution output)



Mode 6 places the OSD blend block after the SVSP. Both the PVSP block and SVSP work in parallel in this mode. As the OSD is only on

one data path, it will only be displayed at a single resolution. As shown in the example in Figure 20 , the input to the SVSP must be a

progressive format. Therefore, this mode can only be used when the input is progressive.

It can be seen from Figure 20 that the same output formats can be generated in this mode. However, due to the change in location of the

OSD blend block, the OSD can only be generated on a single output resolution.

Note: De-interlaced inputs can be input to the device in this mode. However, the SVSP can only accept progressive input formats.

Therefore, the SVSP would be excluded from the processing in this case as would the OSD blend.


2.1.8.

Mode 7


• HDMI input video is copy protected






Mode 7 is different to other modes in that OSD is not overlaid on video data on certain outputs but rather just output on its own. In certain cases where HDMI video from an upstream IC is copy protected, video data can be output on HDMI outputs but not analog outputs. However, OSD data can still be displayed on analog output, for example, to indicate system status or to recover the system from an error-like state.

In this mode, the input format is 720p from an external video transceiver (this could also come from the Video TTL input if video is from an upstream HDMI IC) and is passed to the PVSP. This is upscaled, blended with the 1080p OSD data and sent to both HDMI transmitters. Because this may be copy protected, this cannot be passed to the analog outputs. The OSD on its own, however, can be

passed directly to these outputs. In the example in Figure 21 , the OSD is scaled down to 480p and passed to the HD encoder.


2.1.9.

Mode 8


• HDMI input video is copy protected






Mode 8 is similar to mode 7 in that OSD is not overlaid on the input video but rather output as the OSD video on its own. This may be

required when HDMI video from an upstream IC is copy protected (as in Figure 22 ), but the OSD is still required on the analog outputs.

In this mode, the input format is 720p from an external video transceiver and passed to the OSD blend. As the OSD is generated at the same resolution as the input video, they are just blended. This is then passed to the PVSP where it is upscaled and sent to both HDMI transmitters. If this data is copy protected, this cannot be passed to the analog outputs. The OSD on its own, however, can be passed

directly to these outputs. In the example in Figure 22 , the OSD is scaled down to 480p and passed through the PtoI block and sent out on

the SD encoder. The difference between mode 7 and mode 8 is very similar to the difference between modes 2 and 4. Ideally the video and

OSD should be scaled separately and then blended.


2.1.10.

Mode 9 - Bypass

Mode 9 should be used if input video is to be passed straight to the output with no video processing.



Mode 9 is used in cases where no processing is required on the input video. This can be passed directly to the output. No access to external DDR2 memory is required in this case.


2.1.11.

Mode 10 – Picture in Picture (PiP) (External OSD Less Than 720p)


• OSD data is input via the EXOSD TTL 24-bit input port

• OSD data input via the EXOSD TTL 24-bit input port is less than 720p



Mode 10 is used to support the external input of either part of or the complete OSD from another device, for example, an MCU. With support for HS, VS, DE and CLK, the external OSD input can also be used to input video data. Using mode 10, the external OSD bus can be used to support picture in picture (PiP) with two video streams.

In this mode, the input from the EXOSD TTL 24-bit input port is written into DDR2 memory and read back by the OSD core as a region of the OSD. This region is then blended with input video.



2.1.12.

Mode 11 – PIP (External OSD Greater Than or Equal To 720p)


• OSD data is input via the EXOSD TTL 24-bit input port

• OSD data input via the EXOSD TTL 24-bit input port is greater than or equal to 720p

Mode 11 is used to support the external input of either part of or the complete OSD from another device, for example, an MCU. With support for HS, VS, DE and CLK, the external OSD input can also be used to input video data. Using mode 10, the external OSD bus can be used to support picture in picture (PiP) with two video streams. The difference between mode 10 and mode 11 is the resolution of the incoming video – mode 11 can support incoming video of 720p or greater.

In this mode, the input from EXOSD TTL 24-bit input port is routed to the SVSP where it is scaled before being written into DDR2 memory. The OSD core then reads back the data as one OSD region and blends this region with input video.

Mode 11 - PiP (External OSD

≥ 720p)

720p Video



2.1.13.

Mode 12 – Dual Zone OSD

Mode 12 should be used if OSD output is required in dual zones.



Mode 12 is used to support dual zone OSD output without disturbing either video stream. Using this mode, two inputs (for example, 480p from the video TTL input port and 720p from the Serial Video Rx) can be applied to the part, processed and connected to the OSD core.

The OSD can be blended onto one or other of the two video streams and switched between the two video streams without causing any disturbance to either.



2.1.14.

Mode 13 – OSD from HDMI RX

Mode 13 should be used if the ADV8003 is being used in conjunction with a legacy standalone OSD generator with an HDMI interface.


Mode 13 is used to support OSD input from an OSD generator with an HDMI interface. Using this mode, the Serial Video Rx video is loaded into memory before being called out by the OSD core. This video can then be scaled and blended with the video on the primary video channel. It is possible to output the unblended video, the blended video or the raw OSD.


2.1.15.

Mode 14 – Handling Triple Inputs

Mode 14 should be used if three independent video streams are required on the output of the ADV8003.



Mode 14 is used to support three independent video streams. The independent video streams are input on the video TTL and EXOSD

TTL inputs and the Serial Video Rx. These video streams can then be routed through internal processing blocks (for example, PVSP or progressive to interlaced converter) or connected directly to the backend transmission blocks, for example, HDMI transmitters and encoder.

2.2.

ADV8003 TOP LEVEL OVERVIEW

This section documents the ADV8003 top level register descriptions, explaining some of the registers required to configure the part which are not section or hardware block specific. For more details on block specific settings, refer to their appropriate sections.

Note : This section details the ADV8003KBCZ-8/7. Other versions of the ADV8003 do not offer the same functionality, for example, single

scaler, single TX or no encoder. Refer to Table 1 for more information.

2.2.1.

Video Muxing

There are several blocks which make up the ADV8003 VSP, as described in Section 2. The digital core of the ADV8003 offers flexible

routing of video data, as shown in Figure 29 .



Digital Video Input

Video TTL Input

EXOSD TTL Input

48-bit TTL Input p_inp_chan_sel

Primary

Input

Channel

Video TTL Input

EXOSD TTL Input s_inp_chan_sel[0]

Secondary

Input

Channel

Serial Video RX

RX Input

Channel

Video Signal Processing

Primary Input Channel

Primary VSP

Secondary VSP

Secondary Input Channel

RX Input Channel osd_blend_inp_sel[3:0]


Primary VSP

Secondary VSP


RX Input Channel osd_blend_inp_ 2_ sel[3:0]


Primary VSP

OSD Blend 1


RX Input Channel p2i_inp_sel[3:0]


OSD Blend 1


RX Input Channel pvsp_inp_sel[3:0]


OSD Blend 1

Primary VSP

Raw OSD


RX Input Channel svsp_inp_sel[3:0]

OSD

Blend 1

OSD

Blend 2

PtoI

(Progressive to

Interlaced)

Primary

VSP

Secondary

VSP


RX Input Channel

External

OSD s_inp_chan_sel[1]

ADV8003

Figure 29: ADV8003 Digital Core Muxing

The following registers are used to configure the video routed through the ADV8003.

Video Output


Primary VSP

PtoI

OSD Blend 1

Secondary VSP


RX Input Channel

OSD Blend 2 tx1_inp_sel[3:0]


Primary VSP

PtoI

OSD Blend 1

Se condary VSP


RX Input Channel

OSD Blend 2 tx2_inp_sel[3:0]


Primary VSP

PtoI

OSD Blend 1

Secondary VSP


RX Input Channel

OSD Blend 2 hd_enc_inp_sel[3:0]


Primary VSP

PtoI

OSD Blend 1

Se condary VSP


RX Input Channel

OSD Blend 2 sd_enc_inp_sel[3:0]

HDMI

Tx1

HDMI

Tx2

HD

Encoder

SD

Encoder


ADV8003 Hardware Manual tx1_inp_sel[3:0] , IO Map, Address 0x1A03[7:4]

This signal is used to select the video source for the HDMI Tx1.

Function tx1_inp_sel[3:0] Description

0x00 

0x01

0x02

0x03

0x04

0x05

0x06

0x07

From Main TTL Input

From Primary VSP

From PtoI Converter

From Internal OSD Blend 1

From Secondary VSP/PtoI Converter

From OSD TTL Input

From RX Input

From Internal OSD Blend 2 tx2_inp_sel[3:0] , IO Map, Address 0x1A03[3:0]

This signal is used to select the video source for the HDMI Tx2.

Function tx2_inp_sel[3:0]

0x00 

0x01

0x02

0x03

0x04

0x05

0x06

0x07

Description

From Main TTL Input

From Primary VSP

From PtoI Converter



From OSD TTL Input

From RX Input

From Internal OSD Blend 2 hd_enc_inp_sel[3:0] , IO Map, Address 0x1A04[7:4]

This signal is used to select the video source for the HD encoder. When using the encoder in SD only mode, this signal must be set to the same value as sd_enc_inp_sel.

Function hd_enc_inp_sel[3:0]

0x00 

Description

From Main TTL Input

0x01

0x02

0x03

From Primary VSP

From PtoI Converter


0x04

0x05

0x06

0x07


From OSD TTL Input

From RX Input

From Internal OSD Blend 2 sd_enc_inp_sel[3:0] , IO Map, Address 0x1A04[3:0]

This signal is used to select the video source for the SD encoder. When using the encoder in SD only mode, hd_enc_inp_sel must be set to the same value as this signal.


Function sd_enc_inp_sel[3:0]

0x00 

0x01

0x02

0x03

0x04

0x05

0x06

0x07

Description

From Main TTL Input

From Primary VSP

From PtoI Converter



From OSD TTL Input

From RX Input

From Internal OSD Blend 2 svsp_inp_sel[3:0] , IO Map, Address 0x1A05[7:4]

This signal is used to select the video source for the Secondary VSP.

Function svsp_inp_sel[3:0]

0x00 

0x01

0x02

0x03

0x04

0x05

Description

From Primary Input Channel


From Primary VSP

From Internal OSD (OSD only, no blend)

From Secondary Input Channel

From RX Input pvsp_inp_sel[3:0] , IO Map, Address 0x1A05[3:0]

This signal is used to select the video source for the Primary VSP.

Function pvsp_inp_sel[3:0] Description

0x00 

0x01

0x02

0x03

From Main TTL Input


From OSD TTL Input

From RX Input p2i_inp_sel[3:0] , IO Map, Address 0x1A06[7:4]

This signal is used to select the video source for the Progressive to Interlaced converter.

Function p2i_inp_sel[3:0]

0x00 

0x01

0x02

0x03

0x04

Description

From Primary VSP


From OSD TTL Input

From RX Input

From Main TTL Input osd_blend_inp_sel[3:0] , IO Map, Address 0x1A06[3:0]

This signal is used to select the video source to the OSD Blend block.




Function osd_blend_inp_sel[3:0]

0x00 

0x01

0x02

0x03

0x04

Description

From Main TTL Input


From Primary VSP

From OSD TTL Input

From RX Input osd_blend_inp_2_sel[3:0] , IO Map, Address 0x1A08[3:0]

This signal is used to select the video to be blended on OSD channel 2.

Function osd_blend_inp_2_sel[3:

0]

Description

0x00 

0x01

0x02

0x03

0x04

From Main TTL Input


From Primary VSP

From OSD TTL Input

From RX Input

For example, when using the ADV8003 in mode 3 (described in Section 2.1.4), the following register settings are needed to configure the

video data path:

1A 1A03 34; Output of OSD blend to HDMI Tx1, Output of Secondary VSP to HDMI Tx2

1A 1A04 30; Output of OSD blend to HD encoder, SD encoder not used.

1A 1A05 00; Input to ADV8003 to both Primary and Secondary VSP.

1A 1A06 02; Progressive to Interlaced converter not used, output from Primary VSP to OSD blend.

These four register writes configure the hardware blocks in the ADV8003 in mode 3. More registers will need to be configured depending on the input and desired video standards.

2.2.2.

Digital Video Input

The ADV8003 has three means of receiving video: the video TTL input and the EXOSD TTL input which constitute the flexible 60-bit

TTL input port, and the Serial Video Rx. Each of the TTL inputs can be connected to one of the input channels – the primary input channel or the secondary input channel. The Serial Video Rx is always connected to the RX input channel. Each channel features a dedicated input formatter, color space converter (CSC) and dither block. The primary input channel also features an automatic contrast

enhancement (ACE) control. The ADV8003 input channels are illustrated in Figure 30 ,

Figure 31 and Figure 32 .

Primary Input Channel

Video TTL Input

EXOSD TTL Input

Data

Rotate

AV-Code

Detect

Up-dither CSC

Contrast

Brightness

Saturation

ACE

Primary Input

Channel Output

Video TTL Input +

EXOSD TTL Input

(OSD_IN[11:0] + P[35:0])

48-bit to

24-bit

Conversion

Figure 30: Video TTL Input Channel



Video TTL Input

EXOSD TTL Input

Secondary Input Channel

Data

Rotate

AV-Code

Detect

Up-dither CSC

Secondary Input

Channel Video Output

Data

Formatter

External OSD

Alpha Output

RX Input

Channel

Output

Figure 31: EXOSD TTL Input Channel

Serial

Video

RX

RX Input Channel

Data

Rotate

Up-dither

>1080p 12-bit data

CSC

Data

Formatter

(Receiver)

External OSD

Alpha Output

Figure 32: RX Input Channel

2.2.2.1.

Video TTL Input

The video TTL input pins are defined as follows:

• P[47:0]

• HS

• VS

• DE

• PCLK

The video TTL input pins can be connected to either the primary input channel (refer to

Section 0) or the secondary input channel (refer

to

Section 2.2.2.6).

2.2.2.2.

EXOSD TTL Input

The EXOSD TTL input pins are defined as follows:

• OSD_IN[23:16]

• OSD_IN[15]/VBI_SCK

• OSD_IN[14]/VBI_MOSI

• OSD_IN[13]/VBI_SCK

• OSD_IN[12:0]

• OSD_HS

• OSD_VS

• OSD_DE

• OSD_CLK

The EXOSD TTL input pins can be connected to either the primary input channel (refer to

Section 0) or the secondary input channel

(refer to

Section 2.2.2.6).



2.2.2.3.

TTL Output

The ADV8003 includes a TTL output port, The external OSD TTL input pins (OSD_IN[23:0]) and 12 of the TTL input pins (P35:24) can

function as TTL output pins (refer to Table 98

and Table 99 ). If all 36 TTL pins are used as outputs, this leaves only 24 pins for TTL inputs.

Appendix F describes the different pinout options available for the TTL input and output buses. HS, VS, DE and the TTL clock are output

on the following pins:

• OSD_IN[23:0]

• P[35:24]

• OSD_HS

• OSD_VS

• OSD_DE

• OSD_CLK

The video data can be output at pixel frequencies up to 162 MHz. Only single data rate video is supported on the TTL output bus – it is not possible to clock video out on the rising and falling edge of the TTL output clock.

Figure 33: TTL Output Block Diagram

The following registers are used to control the TTL outputs. ttl_ps444_in , IO Map, Address 0x1A01[0]

This bit is used to select the video type sent to the TTL output format block.

Function ttl_ps444_in

0 

1

Description

Input to TTL output block is real 444

Input to TTL output block is pseudo 444


ttl_op_format[3:0] , IO Map, Address 0x1A02[7:4]

This signal is used to specify the TTL output format.

Function ttl_op_format[3:0] Description

0000

0001

0010

0011

0100

0101

0110

8bit 422

10bit 422

12bit 422

16bit 422

20bit 422

24bit 422

24bit 444

0111 

1000

30bit 444

36bit 444 ttl_vid_out_en , IO Map, Address 0x1A02[3]

This bit is used to enable the TTL video output.

Function ttl_vid_out_en Description

0 

1

Disable TTL output

Enable TTL output ttl_out_sel[2:0] , IO Map, Address 0x1A02[2:0]

This signal is used to select the video source for the TTL video output.

Function ttl_out_sel[2:0]

0x00 

0x01

0x02

0x03

0x04

0x05

0x06

0x07

Description

From Main TTL Input

From Primary VSP

From PtoI Converter



From OSD TTL Input

From RX Input

From Internal OSD Blend 2 osd_clk_drv_str , IO Map, Address 0x1BFFH

This signal is used to control the drive strength for the video output clock signal.

Function osd_clk_drv_str

00

01

10

11

Description

Minimum

Medium low (x2)

Medium high (x3)

High (x4)



ADV8003 Hardware Manual osd_dout_drv_str , IO Map, Address 0x1BA3H

'This signal is used to control the drive strength for the video output data and sync signals.

Function osd_dout_drv_str r Description

00

01

10

11

Minimum

Medium low (x2)

Medium high (x3)

High (x4)

2.2.2.4.

Serial Video Rx

The Serial Video Rx can only be connected to the RX input channel (see

Section 2.2.2.7

).

2.2.2.5.

Primary Input Channel

The ADV8003 primary input channel incorporates an input formatter, CSC, updither block and ACE control.

The input formatter provides a number of controls to configure what data the video TTL input channel is configured for. The video TTL input channel must be connected to either the video TTL input pins, the EXOSD TTL input pins or the high speed TTL input pins using

p_inp_chan_sel[1:0] . If the primary input channel is connected to the video TTL input pins, the format and bit width of the data, for example, 2 x 8 bit buses of 4:2:2 data, must be specified using vid_format_sel[4:0] .

vid_swap_bus_ctrl[2:0] can be used to indicate which

input pins are used to carry the upper, middle and lower ranges of bits (for example, upper = D[35:25], middle = D[24:12], lower =

D[11:0] or upper = D[11:0], middle = D[35:25], lower = D[24:12]). p_inp_chan_sel[1:0] , IO Map, Address 0x1A07[1:0]

This signal is used to select the input for the Primary Input Channel.

Function p_inp_chan_sel[1:0] Description

00 

01

10

11

Video TTL input (P[35:0])

EXOSD TTL Input (OSD_IN[23:0])

48-bit TTL input (OSD_IN[11:0] and P[35:0]) for 3GHz interleaved TTL

Reserved vid_format_sel[4:0] , IO Map, Address 0x1B48[4:0]

This signal is used to select the input format for the video data.



Function vid_format_sel[4:0]

0x08 

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x10

0x11

0x12

0x13

Description

1 x 8-bit bus, SDR 4:2:2



2 x 8-bit buses, SDR 4:2:2



3 x 8-bit buses, SDR 4:4:4 (P[35:28], P[23:16], P[11:4])

3 x 10-bit buses, SDR 4:4:4 (P[35:26], P[23:14], P[11:2])


1 x 8-bit bus, DDR 4:2:2

1 x 10-bit bus DDR 4:2:2

1 x 12 bit bus, DDR 4:2:2

3 x 8 bit buses, SDR 4:4:4 (P[23:0])

2 x 3 x 8-bit interleaved buses, SDR 4:4:4




3 x 10-bit buses, SDR 4:4:4 (P[29:0])

3 x 7-bit buses, SDR 4:4:4 (for external alpha blend)

3 x 10-bit buses, SDR 4:4:4 (OSD_IN[23:0] and P[35:30]) vid_swap_bus_ctrl[2:0] , IO Map, Address 0x1B48[7:5]

This signal is used to control the video input pixel bus. The input pixel bus is 36 bits wide and is divided into three data channels: Top =

D[35:24], Middle = D[23:12] and Bottom = D[11:0]. This register allows the user to swap the order of these three data channels.

Function vid_swap_bus_ctrl[2:0]

000 

001

010

011

100

101

110

111

Description

D[35:24] D[23:12] D[11:0]

D[35:24] D[11:0] D[23:12]

D[35:24] D[23:12] D[11:0]

D[23:12] D[35:24] D[11:0]

D[11:0] D[35:24] D[23:12]

D[11:0] D[23:12] D[35:24]

D[23:12] D[11:0] D[35:24]

D[35:24] D[23:12] D[11:0]

The input formatter also has a number of controls which can be used to provide extra flexibility in terms of data processing.

Once a DDR mode is selected using

vid_format_sel[4:0] , the order of the luma and chroma data can be configured using

vid_ddr_yc_swap . In DDR modes, the luma is expected on the rising edge of the pixel clock. Setting this bit to 1 swaps the luma and

chroma samples and places the chroma sample (C) on the rising edge and the luma sample (Y) on the falling edge. Refer to Figure 34 for

more information. The edge on which each sample of DDR data is latched into the part can be specified using vid_ddr_edge_sel .

Rev. B, August 2013

Figure 34: DDR Mode, Luma and Chroma Swap

94

ADV8003 Hardware Manual vid_ddr_yc_swap , IO Map, Address 0x1B4A[0]

This bit is used to swap the Luma (Y) and Chroma (C) data in DDR modes. By default, Y is expected on the rising edge of the clock.

Function vid_ddr_yc_swap Description

0 

1

Y on rising edge of clock

C on rising edge of clock vid_ddr_edge_sel , IO Map, Address 0x1B4A[3]

This bit is used to select which edge the first sample of DDR data is latched on.

Function vid_ddr_edge_sel

0 

1

Description

Posedge data first

Negedge data first

Using the pixel clock as a reference, ADV8003 expects the Y sample on a rising edge and then a chroma sample on the falling edge. When

vid_ddr_yc_swap is set, ADV8003 expects a chroma sample on the rising edge and the Y sample on the falling edge. vid_swap_cb_cr_422

can be used to swap the order of the chroma data. By default, ADV8003 expects a sequence of Cb, Cr, Cb, Cr… When

vid_swap_cb_cr_422 is set, ADV8003 expects a sequence of Cr, Cb, Cr, Cb....

vid_swap_cb_cr_422 , IO Map, Address 0x1B49[7]

This bit is used to swap the order of the C data when decoding 4:2:2 data.

Function vid_swap_cb_cr_422

0 

1

Description

Cb/Cr decoding

Cr/Cb decoding

vid_ps444_r444_conv is used to convert from pseudo 444 video data to real 444. All processing occurs in the ADV8003 in 4:4:4 mode.

Therefore, if video input to the device is not in this format, this must be first converted to 4:4:4. Setting this bit to 1 converts video data to

4:4:4. vid_ps444_r444_conv , IO Map, Address 0x1B49[6]

This bit is used to convert 4:2:2 data to pseudo 444 or to real 444.

Function vid_ps444_r444_conv

0 

1

Description

Nothing done

Pseudo 444 to Real 444 conversion

vid_hs_pol ,

vid_vs_pol , vid_de_pol

and

vid_fld_pol configure the polarity of the input video timing signals. These must be set depending

on the polarity of the upstream IC. If active low, these register can be left at their default. If these signals from the upstream IC are active high, their polarity can be inverted. vid_hs_pol , IO Map, Address 0x1B49[3]

This bit is used to set the polarity of the input HS timing signal.



Function vid_hs_pol

0 

1

Description

Input HS polarity does not change

Input HS polarity gets inverted vid_vs_pol , IO Map, Address 0x1B49[2]

This bit is used to set the polarity of the input VS timing signal.

Function vid_vs_pol Description

0 

1

Input VS polarity does not change

Input VS polarity gets inverted vid_de_pol , IO Map, Address 0x1B49[1]

This bit is used to set the polarity of the input DE enable signal.

Function vid_de_pol Description

0 

1

Input DE polarity does not change

Input DE polarity gets inverted vid_fld_pol , IO Map, Address 0x1B49[0]

This bit is used to set the polarity of the input Field (FLD) timing signal.

Function vid_fld_pol

0 

1

Description

Input FLD polarity does not change

Input FLD polarity gets inverted

vid_hs_vs_mode is used to select the method by which the input video will be synchronized. This may be required when the ADV8003 is

used in conjunction with an MPEG decoder. MPEG decoders use embedded timing codes rather than using external HS and VS signals.

Similarly, other ADI decoders/HDMI Rxs can output video using embedded timing codes. This register should be programmed depending on the timing method of the upstream IC.

Refer to

Section 2.2.11

for more information on AV-codes.

vid_hs_vs_mode , IO Map, Address 0x1B4B[7]

This bit is used to select the method of input timing.

Function vid_hs_vs_mode Description

0

1 

Use embedded SAV/EAV codes

Use external HS/VS synchronization signals vid_av_pos_sel , IO Map, Address 0x1B4B[3]

This bit is used to select if the HS generated is consistent with EIA 861 timing or dependant on the embedded timing codes.



Function vid_av_pos_sel

0 

1

Description

Generate HS coincident with EAV code

Generate HS/VS based on 861 timing vid_av_split_code , IO Map, Address 0x1B4B[2]

This bit is used to control how AV-codes are decoded - replicated on or split across all channels.

Function vid_av_split_code Description

0 

1

Decodes AV-codes which are replicated on all channels

Decodes AV-codes which are split across all channels vid_av_codes_rep_man_en , IO Map, Address 0x1B4B[1]

This bit is used to control the enable for AV source codes. AV_codes_rep_man is used instead of the auto based on the input video format.

Function vid_av_codes_rep_man

_en

Description

0 

1

AV-codes replicated based on internal flag

Use i2c bit vid_av_codes_rep_man , IO Map, Address 0x1B4B[0]

This bit is used to specify if the AV_codes are replicated or not.

Codes replicated (4:4:4) = FF,FF,FF,00,00,00,00,00, 00,AV,AV,AV.

Codes not replicated = FF,00,00,AV.

Function vid_av_codes_rep_man

1

0 

Description

AV-codes are replicated.

AV-codes are not replicated.

The updither feature in the ADV8003 can be used to randomize quantization errors, preventing large scale patterns such as color banding in images. Refer to

Section 2.2.3

for more information on the updither block .

The updither block on the video TTL input channel can be controlled via the vid_ud_bypass_man_en

and vid_ud_bypass_man bits. By

default, the manual bypass is disabled which means that the updither block cannot be bypassed. The updither block configuration is outlined in

Section 2.2.3. The updither settings are shared for all channels (primary, secondary and RX).

vid_ud_bypass_man_en , IO Map, Address 0x1B4A[2]

This bit is used to enable the manual bypass for the up dither. Setting this bit enables the bypass to be used.

Function vid_ud_bypass_man_en Description

0 

1

Manual bypass disable

Manual bypass enable


ADV8003 Hardware Manual vid_ud_bypass_man , IO Map, Address 0x1B4A[1]

This bit is used to bypass the up dither block.

Function vid_ud_bypass_man

0 

1

Description

Disable bypass

Enable bypass

The primary input path features contrast, brightness and saturation controls. All contrast, brightness and saturation controls

( contrast[7:0] ,

brightness[7:0] , saturation[7:0] ,

blank_level_y[11:0] ,

blank_level_u[11:0] and blank_level_v[11:0] ) are doubled buffered on

VSync.

The contrast[7:0] value has a range of 0 to 1.992. Refer to Figure 35 for more information on how the contrast controls influence the video

signal.

The brightness[7:0] value has a range of -1024 to 1016. Refer to Figure 36

for more information on how the brightness controls influence the video signal.

The saturation[7:0]

value has a range 0 to 1.992. Refer to Figure 37

for more information on how the saturation controls influence the video signal. contrast[7:0] , IO Map, Address 0x1A2B[7:0]

This register is used to adjust the contrast value for Y channel. This register uses 1.7 notation.

Function contrast[7:0] Description

0x00

0x80 

0xFF

Gain of 0

Unity gain

Gain of 2 blank_level_y[11:0] , IO Map, Address 0x1A24[3:0]; Address 0x1A25[7:0]

This signal is used to adjust the blank level of y input to the vid adjust block.

Function blank_level_y[11:0] Description

0x000

0x100  y blank level sits at code 0 y blank level sits at code 256 decimal

y_in

-

* +

y_out blank_level_y contrast blank_level_y

Figure 35: Contrast Processing

98 Rev. B, August 2013

brightness[7:0] , IO Map, Address 0x1A2A[7:0]

This register is used to adjust the brightness value for Y channel. The register uses s1.6 notation.

Function brightness[7:0] Description

0x7F

0x00 

0xFF

(+127) * 8

(No adjustment) * 8

(-1) * 8

y_in

+

y_out


brightness * 8

Figure 36: Brightness Processing saturation[7:0] , IO Map, Address 0x1A29[7:0]

This register is used to adjust the saturation value for U/V channels. The register uses 1.7 notation.

Function saturation[7:0] Description

0x00

0x80 

0xFF

Gain of 0

Unity Gain

Gain of 2 blank_level_u[11:0] , IO Map, Address 0x1A26[7:0]; Address 0x1A27[7:4]

This signal is used to adjust the blank level of u input to the vid adjust block.

Function blank_level_u[11:0]

0x000

0x800 

Description u blank level sits at code 0 u blank level sits at code 2048 decimal blank_level_v[11:0] , IO Map, Address 0x1A27[3:0]; Address 0x1A28[7:0]

This signal is used to adjust the blank level of v input to the vid adjust block

Function blank_level_v[11:0]

0x000

0x800 

Description v blank level sits at code 0 v blank level sits at code 2048 decimal


-


u/v_out u/v_in

* +

blank_level_u/v saturation blank_level_u/v

Figure 37: Saturation Processing

Refer to

Section 2.2.12.1

for more information on the CSC controls for the primary input channel.

Refer to

Section 3.2.3.16

for more information on the ACE controls for the primary input channel.

2.2.2.6.

Secondary Input Channel

The ADV8003 secondary input channel incorporates an input formatter, CSC and updither block.

The input formatter provides a number of controls to configure what data the secondary input channel is configured for. The secondary

input channel must be connected to either the video TTL input pins or the EXOSD TTL input pins using s_inp_chan_sel[1:0].

If the secondary input channel is connected to the video TTL input pins, the format and bit width of the data, for example, 2 x 8 bit buses of

4:2:2 data, must be specified using exosd_format_sel[4:0] .

exosd_swap_bus_ctrl[2:0] can be used to indicate which input pins are used to

carry the upper, middle and lower ranges of bits (for example, upper = D[35:25], middle = D[24:12], lower = D[11:0]; or upper = D[11:0], middle = D[35:25], lower = D[24:12]). s_inp_chan_sel[1:0] , IO Map, Address 0x1A07[3:2]

This signal is used to select the input for the Secondary Input Channel.

Function s_inp_chan_sel[1:0]

00

01 

10

11

Description

Video TTL input (P[35:0])

EXOSD TTL Input (OSD_IN[23:0])

RX video

N/A exosd_format_sel[4:0] , IO Map, Address 0x1B68[4:0]

This signal is used to select the input format for the video data.



Function exosd_format_sel[4:0]

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C 

Description

1 x 8 bit bus 4:2:2

1 x 10 bit bus 4:2:2

1 x 12 bit bus 4:2:2

2 x 8 bit buses 4:2:2






1 x 8 bit DDR bus 4:2:2



3 x 8 bit buses 4:4:4 exosd_swap_bus_ctrl[2:0] , IO Map, Address 0x1B68[7:5]

This signal is used to control the external OSD input pixel bus. The input pixel bus is 24 bits wide and is divided into three data channels: Top = D[23:16], Middle = D[15:8] and Bottom = D[7:0]. This register allows the user to swap the order of these three data channels.

Function exosd_swap_bus_ctrl[2:

0]

Description

000 

001

010

011

100

101

110

111

D[23:16] D[15:8] D[7:0]

D[23:16] D[7:0] D[15:8]

D[23:16] D[15:8] D[7:0]

D[15:8] D[23:16] D[7:0]

D[7:0] D[23:16] D[15:8]

D[7:0] D[15:8] D[23:16]

D[15:8] D[7:0] D[23:16]

D[23:16] D[15:8] D[7:0]

The input formatter also has a number of controls which can be used to provide extra flexibility in terms of data processing.

Once a DDR mode is selected using

exosd_format_sel[4:0] , the order of the luma and chroma data can be configured using

exosd_ddr_yc_swap . In DDR modes, the luma is expected on the rising edge of the pixel clock. Setting this bit to 1 swaps the luma and

chroma samples and places the chroma sample (C) on the rising edge and the luma sample (Y) on the falling edge. Refer to Figure 34 for

more information. The edge on which each sample of DDR data is latched into the part can be specified using exosd_ddr_edge_sel .

Figure 38: DDR Mode, Luma and Chroma Swap exosd_ddr_yc_swap , IO Map, Address 0x1B6A[0]

This bit is used to swap the Luma (Y) and Chroma (C) data in DDR modes. By default, Y is expected on the rising edge of the clock.



Function exosd_ddr_yc_swap

0 

1

Description

Y on rising edge of clock

C on rising edge of clock exosd_ddr_edge_sel , IO Map, Address 0x1B6A[3]

This bit is used to select which edge the first sample of DDR data is latched on.

Function exosd_ddr_edge_sel Description

0 

1

Posedge data first

Negedge data first

Using the pixel clock as a reference, ADV8003 expects the Y sample on a rising edge and then a chroma sample on the falling edge. When

exosd_ddr_yc_swap

is set, ADV8003 expects a chroma sample on the rising edge and the Y sample on the falling edge.

exosd_swap_cb_cr_422 can be used to swap the order of the chroma data. By default, ADV8003 expects a sequence of Cb, Cr, Cb, Cr…

When exosd_swap_cb_cr_422 is set, ADV8003 expects a sequence of Cr, Cb, Cr, Cb....

exosd_swap_cb_cr_422 , IO Map, Address 0x1B69[7]

This bit is used to swap the order of the C data when decoding 4:2:2 data.

Function exosd_swap_cb_cr_422

0 

1

Description

Cb/Cr decoding

Cr/Cb decoding

exosd_ps444_r444_conv is used to convert from pseudo 444 video data to real 444. All processing occurs in the ADV8003 in 4:4:4 mode.

Therefore, if video input to the device is not in this format, it must be first converted to 4:4:4. Setting this bit to 1 converts video data to

4:4:4. exosd_ps444_r444_conv , IO Map, Address 0x1B69[6]

This bit is used to convert 4:2:2 data to pseudo 444 or to real 444.

Function exosd_ps444_r444_con v

Description

0 

1

Nothing done.

Pseudo444 to Real 444 conversion.

exosd_rev_bus is used to reverse the order of the video TTL input. By default, this is set to non reversed.

exosd_rev_bus , IO Map, Address 0x1B6B[4]

This bit is used to reverse the input video bus, i.e. D[23:0] -> D[0:23].

Function exosd_rev_bus Description

0 

1

Reverse the pin mapping on the OSD bus

Use the OSD bus as it comes from the pins

exosd_hs_pol , exosd_vs_pol and exosd_de_pol

configure the polarity of the input video timing signals. These must be set depending on


ADV8003 Hardware Manual the polarity of the upstream IC. If active low, these register can be left at their default. If these signals from the upstream IC are active high, their polarity can be inverted. exosd_hs_pol , IO Map, Address 0x1B69[0]

This bit is used to set the polarity of the input External OSD HS timing signal.

Function exosd_hs_pol

0 

1

Description

Input HS polarity doesn’t change.

Input HS polarity gets inverted. exosd_vs_pol , IO Map, Address 0x1B69[1]

This bit is used to set the polarity of the input External OSD VS timing signal.

Function exosd_vs_pol Description

0 

1

Input VS polarity doesn’t change.

Input VS polarity gets inverted. exosd_de_pol , IO Map, Address 0x1B69[2]

This bit is used to set the polarity of the input External OSD DE timing signal.

Function exosd_de_pol Description

0 

1

Input DE polarity doesn’t change.

Input DE polarity gets inverted.

exosd_hs_vs_mode is used to select the method by which the input video will be synchronized. This may be required when the ADV8003

is used in conjunction with an MPEG decoder. MPEG decoders use embedded timing codes rather than using external HS and VS signals.

Similarly, other ADI decoders/HDMI Rxs can output video using embedded timing codes. This register should be programmed depending on the timing method of the upstream IC.

Refer to

Section 2.2.11 for more information on AV-codes.

exosd_hs_vs_mode , IO Map, Address 0x1B6B[7]

This bit is used to select the method of input timing.

Function exosd_hs_vs_mode Description

0

1 

Embedded timing codes

VS/DE mode exosd_av_pos_sel , IO Map, Address 0x1B6B[3]

This bit is used to select if the HS generated is consistent with EIA 861 timing or dependant on the embedded timing codes.



Function exosd_av_pos_sel

0 

1

Description

Generate hs coincident with eav code

Generate hs/vs based on 861 timing exosd_av_split_code , IO Map, Address 0x1B6B[2]

This bit is used to control how AV-codes are decoded - replicated on or split across all channels.

Function exosd_av_split_code Description

0 

1

Replicated AV-codes on all channels

AV-codes split across all buses exosd_av_codes_rep_man_en , IO Map, Address 0x1B6B[1]

This bit is used to control the enable for AV source codes. AV_codes_rep_man is used instead of the auto based on the input video format.

Function exosd_av_codes_rep_m an_en

Description

0 

1

AV-codes replicated based on internal flag

Use i2c bit exosd_av_codes_rep_man , IO Map, Address 0x1B6B[0]

This bit is used to specify if the AV_codes are replicated or not.

Codes replicated (4:4:4) = FF,FF,FF,00,00,00,00,00, 00,AV,AV,AV.

Codes not replicated = FF,00,00,AV.

Function exosd_av_codes_rep_m an

Description

1

0 

AV-codes are replicated.

AV-codes are not replicated.

The updither feature in the ADV8003 can be used to randomize quantization error preventing large scale patterns such as color banding in images. Refer to

Section 2.2.3 for more information on the updither block

.

The updither block on the secondary input channel can be controlled via the exosd_ud_bypass_man

and exosd_ud_bypass_man_en bits.

By default, the manual bypass is disabled which means that the updither block cannot be bypassed. The updither block configuration is outlined in


exosd_ud_bypass_man_en , IO Map, Address 0x1B6A[2]


Function exosd_ud_bypass_man

_en

Description

0 

1


Manual bypass enable


ADV8003 Hardware Manual exosd_ud_bypass_man , IO Map, Address 0x1B6A[1]


Function exosd_ud_bypass_man Description

0 

1

Disable bypass

Enable bypass

Refer to

Section 2.2.12.2

for more information on the CSC controls for the secondary input channel.

2.2.2.7.

RX Input Channel

The ADV8003 RX input channel incorporates an input formatter, CSC and updither block.

The updither feature in the ADV8003 can be used to randomize quantization error preventing large scale patterns such as color banding in images. Refer to

Section 2.2.3 for more information on the updither block

.

The updither block on the RX input channel can be controlled via the rx_ud_bypass_man_en and rx_ud_bypass_man bits. By default, the

manual bypass is disabled which means that the updither block cannot be bypassed. The updither block configuration is outlined in


rx_ud_bypass_man_en , IO Map, Address 0x1B8A[2]


Function rx_ud_bypass_man_en Description

0 

1


Manual bypass enable rx_ud_bypass_man , IO Map, Address 0x1B8A[1]


Function rx_ud_bypass_man Description

0 

1

Disable bypass

Enable bypass rx_swap_bus_ctrl[2:0] , IO Map, Address 0x1B88[7:5]

This signal is used to configure the order of the input video bus.

Function rx_swap_bus_ctrl[2:0]

000 

001

010

011

100

101

110

111

Description

D[35:24] D[23:12] D[11:0]

D[35:24] D[11:0] D[23:12]

D[35:24] D[23:12] D[11:0]

D[23:12] D[35:24] D[11:0]

D[11:0] D[35:24] D[23:12]

D[11:0] D[23:12] D[35:24]

D[23:12] D[11:0] D[35:24]

D[35:24] D[23:12] D[11:0]



Refer to

Section 2.2.12.3

for more information on the CSC controls for the RX input channel.

2.2.3.

Updither Configuration

The updither block on each of the input channels can be used to increase the bit width of the incoming video. This is useful if the output video must be a certain bit depth and the input video is below this level. Updither can increase color richness and reduce the effects of quantization, rounding and truncation which may have been induced on the video data. The updither block can be used in a situation where the video input to the ADV8003 is in 8-bit form and must be converted to 10-bit or 12-bit for output.

The operation of the updither block can be seen in Figure 39 . When converting to a higher bit width, the ADV8003 updither block first

converts to a bit width of 14 and then down converts to 12- and 10-bit width.

Figure 39: Updither Operation

updither_level[1:0] is used to configure the updither algorithm level. This should be configured depending on the input and output from

the block. For example, if the input video is 8-bit data and the output is 12-bit data, this should be set to the highest level. updither_level[1:0] , IO Map, Address 0x1A0D[5:4]

This signal is used to set the sharpness of the dither block's HPF processing of the video data. The higher the value of this signal, the sharper the characteristic of the dither block's HPF.

Function updither_level[1:0]

00

11

Description

Least sharp

Sharpest

2.2.4.

Clock Configuration

This section describes the method of configuring the various clocks of the ADV8003 using the automatic controls video_in_id[7:0] ,

exosd_in_id[7:0] and rx_in_id[7:0] . These controls can be employed to automatically configure the internal clocks for the following:

• Pixel de-repetition/front-end formatter clock configuration (main and secondary TTL channels and Serial Video Rx channel)

• Timing generation for inputs with AV-codes (main and secondary TTL channels only)

• ACE configuration (main TTL channel only)

• VBI ancillary data (main TTL channel only)

In any of these modes, the video_in_id[7:0] ,

exosd_in_id[7:0] and rx_in_id[7:0] controls must be configured.


Secondary

TTL

Inputs

OSD_IN[35]

OSD_IN[0]

OSD_VS

OSD_HS

OSD_DE

Set by exosd_in_id

Main

TTL

Inputs

Set by vid_in_id

Serial

Video

RX

Set by rx_in_id

Figure 40: Configuring Input Port Clock



ADV8003 Hardware Manual video_in_id[7:0] , IO Map, Address 0x1A00[7:0]

This register is used to set the output clock frequencies from the input video formatting block used by both the HDMI RX inputs and

Video TTL input ports.

Function video_in_id[7:0] Description

0x0F

0x10

0x12

0x13

0x14

0x16

0x01

0x03

0x04

0x05

0x07

0x09

0x0B

0x0D

0x18

0x1A

0x1C

0x89

0x8A

0x8B

0x8D

0x8E

0x8F

0x90

0xFC

0xFD

0xFE 

0xFF

0x81

0x82

0x83

0x84

0x85

0x86

0x87

0x88

0x1E

0x1F

0x20

0x21

0x22

0x24

0x26

0x80

640x480p@60Hz

720x480p@60Hz

1280x720p@60Hz

1920x1080i@60Hz

720(1440)x480i@60Hz

720(1440)x240p@60Hz

(2880)x480i@60Hz

(2880)x240p@60Hz

1440x480p@60Hz

1920x1080p@60Hz

720x576p@50Hz

1280x720p@50Hz

1920x1080i@50Hz

720(1440)x576i@50Hz

720(1440)x288p@50Hz

(2880)x576i@50Hz

(2880)x288p@50Hz

1440x576p@50Hz

1920x1080p@50Hz

1920x1080p@24Hz

1920x1080p@25Hz

1920x1080p@30Hz

2880x480p@60Hz

2880x576p@50Hz

640x350@85hz

640x400@85hz

720x400@85hz

640x480@60hz

640x480@72hz

640x480@75hz

640x480@85hz

800x600@56hz

800x600@60hz

800x600@72hz

800x600@75hz

800x600@85hz

1024x768@60hz

1024x768@70hz

1024x768@75hz

1024x768@85hz

720x288p@50Hz

720x240p@60Hz

720x480i@60Hz

720x576i@50Hz


ADV8003 Hardware Manual exosd_in_id[7:0] , IO Map, Address 0x1B6C[7:0]

This register is used to specify the video_id relative to CEA 861.

Function exosd_in_id[7:0] Description

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

CEA 861 VIC 1 (480p_60 640)

CEA 861 VIC 2 (480p_60)

CEA 861 VIC 3 (480p_60)

CEA 861 VIC 4 (720p_60)

CEA 861 VIC 5 (1080i_60)

CEA 861 VIC 6 (480i_60)

CEA 861 VIC 7 (480i_60)

CEA 861 VIC 8 (240p_60)

CEA 861 VIC 9 (240p_60)

CEA 861 VIC 16 (1080p_60)

CEA 861 VIC 17 (576p_50)

CEA 861 VIC 18 (576p_50)

CEA 861 VIC 19 (720p_50)

CEA 861 VIC 20 (1080i_50)

CEA 861 VIC 21 (576i_50)

CEA 861 VIC 22 (576i_50)

CEA 861 VIC 23 (288p_50)

0x18

0x1F

0xFC

0xFD

0xFE 

0xFF

CEA 861 VIC 24 (288p_50)

CEA 861 VIC 31 (1080p_50)

CEA 861 VIC 252 (288p_50)

CEA 861 VIC 253 (240p_60)

CEA 861 VIC 254 (480i_60)

CEA 861 VIC 255 (576i_50) rx_in_id[7:0] , IO Map, Address 0x1B96[7:0]

This register is used to specify the VIC relative to CEA 861.

Function rx_in_id[7:0] Description

0x06

0x07

0x08

0x09

0x15

0x16

0x17

CEA861 VIC 6 (480i60 2x)

CEA861 VIC 7 (480i60 2x)

CEA861 VIC 8 (240p60 2x)

CEA861 VIC 9 (240p60 2x)

CEA861 VIC 21 (576i50 2x)

CEA861 VIC 22 (576i50 2x)

CEA861 VIC 23 (288p50 2x)

0x18 CEA861 VIC 24 (288p50 2x)

The ADV8003 can output a large number of video formats including many common graphics resolutions. To enable the PVSP and SVSP cores to output these frequencies, the output timing clocks must first be programmed. The output clocks for both the PVSP and SVSP are

shown in Figure 41 .



Figure 41: PVSP/SVSP Output Clock Configure

For the PVSP and SVSP, the correct clocks must be configured manually. This can be done using the DPLL period registers, which allows the user to program the sampling rate for the appropriate output format by I

Equation 1 .

2 C. The equation for calculating this I 2 C value is provided in

dpll

_

phase

_

period

≡

64

×

12

1

×

27

MHz

Equation 1: Calculating DPLL Phase Period

Once the dpll_phase_period is calculated, Equation 2 is used to calculate the dpll_clock_period.

dpll

_

clock

_

period

≡ output dpll

_

_

clock

_

period phase

_

×

2

22

period

Equation 2: Calculating DPLL Clock Period where output_clock_period is the period of the desired output sampling frequency.

For example, for HD video, the output clock sampling frequency would be 148.5 MHz. This equation returns a decimal value. Once calculated, this should be converted to hex and written to

pvsp_vid_clk_period[33:0]

and

svsp_vid_clk_period[33:0] .

Table 8 outlines

some common resolutions and their associated dpll_clock_period values.

Table 8: Example Values for dpll_clock_period

Active Resolution Frame Rate (Hz) Sampling

Frequency (MHz)

720 x 480i 29.97 13.5

720 x 480p

720 x 576i

59.94

25

27

13.5

720 x 576p

960 x 480i

960 x 576i

1280 x 720p

50

29.97

25

59.94

27

18

18

74.175

1280 x 720p

1920 x 1080i

1920 x 1080i

1920 x 1080p

1920 x 1080p

1920 x 1080i

60

29.97

30

59.94

60

25

74.25

74.175

74.25

148.35

148.5

74.25 dpll_clock_period

(Hex)

0x180000000

0x0C0000000

0x180000000

0x0C0000000

0x120000000

0x120000000

0x045E386DC

0x045D1745D

0x045E386DC

0x045D1745D

0x022F1C36E

0x022E8BA2F

0x045D1745D



Active Resolution Frame Rate (Hz) Sampling

Frequency (MHz) dpll_clock_period

(Hex)

1920 x 1080p 50 148.5 0x022E8BA2F

Depending on the sampling frequency required, the following registers need to be programmed with this DPLL clock period.

Note: To enable the DPLL to configure the correct clocks for the ADV8003, register 0x0039 must be set to 0x0A. This register must always be configured before the following registers are set. This configures the ADV8003 clock generators to generate the clocks for the

ADV8003.

2.2.4.1.

PVSP Output Timing

The following registers are programmed for the PVSP. pvsp_vid_clk_period[33:0] , IO Map, Address 0x1A3A[1:0]; Address 0x1A3B[7:0]; Address 0x1A3C[7:0]; Address 0x1A3D[7:0]; Address

0x1A3E[7:0]

This register is used to set the open_loop_period of the DPLL section. This should be programmed based on the value calculated from the given equations. pvsp_vid_clk_update , IO Map, Address 0x1A3A[4]

This bit is used to trigger the open loop period to be captured in the DPLL. A low to high transition triggers the action.

Function pvsp_vid_clk_update Description

0 

1

Do not update open_loop_period in DPLL

Update open_loop_period in DPLL

For example, the following procedure updates the PVSP DPLL clock period:

1A 1A39 0A – Put the DPLL into ADV8003 (scaler) mode

1A 1A3B XX – Configure DPLL clock period setting

1A 1A3C XX – Configure DPLL clock period setting

1A 1A3D XX – Configure DPLL clock period setting

1A 1A3E XX – Configure DPLL clock period setting

1A 1A3A 80 – Recommended setting

1A 1A3A 90 – Recommended setting

Once configured, the clock in Figure 41 is programmed for operation.

2.2.4.2.

SVSP Output Timing

The following registers are programmed for the SVSP. svsp_vid_clk_period[33:0] , IO Map, Address 0x1A3F[1:0]; Address 0x1A40[7:0]; Address 0x1A41[7:0]; Address 0x1A42[7:0]; Address

0x1A43[7:0]

This signal is used to set the open_loop_period of the DPLL section. This should be programmed based on the value calculated from the given equations.


ADV8003 Hardware Manual svsp_vid_clk_update , IO Map, Address 0x1A3F[4]

This bit is used to trigger the open loop period to be captured in the DPLL. A low to high transition triggers the action.

Function svsp_vid_clk_update Description

0 

1

Do not update open_loop_period in DPLL

Update open_loop_period in DPLL

For example, the following procedure for updating the SVSP DPLL clock period is very similar to that of the PVSP:

1A 1A39 0A – Put the DPLL into ADV8003 mode

1A 1A40 XX – Configure DPLL clock period setting




1A 1A3F 80 – Recommended setting

1A 1A3F 90 – Recommended setting

Once configured, the clock in Figure 41 is programmed for operation.

2.2.4.3.

Frame Tracking

The ADV8003 employs frame tracking on its scaler outputs. There will always be some error in the input frame rate versus the ideal frame rate. This could cause frame drops or repeats at the output. Frame tracking allows the output timing to track the input timing in such a way that eliminates frame drops and repeats while also remaining immune to discontinuities in the input. The system can be fully

frequency and phase locked using pvsp_err_sel . If phase locked is selected, there will be an integer frame latency from input to output. If

frequency locked is selected, there could be a non integer frame latency number from input to the output. Selecting phase error latency is the recommended setting. pvsp_err_sel, IO Map, Address 0x1A4EH

This bit is used to choose between phase locked loop and frequency locked loop for the Primary VSP frame tracking mode.

Function pvsp_err_sel

0 

1

Description

Phase error

Frequency error svsp_err_sel , IO Map, Address 1A4FH

This bit is used to choose between phase locked loop and frequency locked loop for the Secondary VSP frame tracking mode.

Function svsp_err_sel

0 

1

Description

Phase error

Frequency error

Frame tracking results in an integer ratio relationship between the input and output frame rates of 1:1, 2:1, 1:2, 5:2 or 2:5. For example, if scaling from 1080p30 to 720p59.94 with frame tracking enabled, the resulting output may be 720p60 due to the 1:2 relationship.

Frame rate tracking is primarily intended for cases where the input frame rate and output frame rate have a 1:1 relationship or are close to this target, that is, 59.94 Hz to 60 Hz. However, it can also be used for some standard frame rate conversion modes such as 24 Hz to 60

Hz, 25 Hz to 50 Hz, and 30 Hz to 60 Hz. The list of scaling conversions where frame tracking can be enabled is covered in Table 9 .



23.97 Hz

24 Hz

25 Hz

29.97 Hz

30 Hz

50 Hz

59.94 Hz

23.97 Hz

Yes

Yes

No

No

No

No

Yes

24 Hz

Yes

Yes

No

No

No

No

Yes

Table 9: Frame Tracking

Output Frame Rate

25 Hz 29.97 Hz 30 Hz

No

No

No

No

No

No

Yes

No

No

Yes

No

No

Yes

Yes

No

Yes

No

Yes

Yes

No

Yes

50 Hz

No

No

Yes

No

No

Yes

No

59.94 Hz

Yes

Yes

No

Yes

Yes

No

Yes

60 Hz

Yes

Yes

No

Yes

Yes

No

Yes

60 Hz Yes Yes No Yes Yes No Yes Yes

pvsp_track_en is set to enable frame tracking for the PVSP. svsp_track_en is set to enable frame tracking for the SVSP. If tracking is to be

used in frame rate conversion mode, video_in_id[7:0] ,

pvsp_autocfg_output_vid[7:0]

(PVSP) and svsp_autocfg_output_vid[7:0]

(SVSP) should also be set. pvsp_track_en , IO Map, Address 0x1A44[6]

This bit is used to enable tracking of the frequency error to reduce the number of dropped/repeated frames for the Primary VSP.

Function pvsp_track_en Description

0 

1

Do not adjust for frequency difference between input and output vertical sync

Adjust for frequency difference between input and output vertical sync svsp_track_en , IO Map, Address 0x1A44[2]

This bit is used to enable tracking of the frequency error to reduce the number of dropped/repeated frames for the Secondary VSP.

Function svsp_track_en Description

0 

1

Do not adjust for frequency difference between input and output vertical sync

Adjust for frequency difference between input and output vertical sync

2.2.5.

DDR2 Interface

The ADV8003 uses DDR2 memory to enable the de-interlacer, scaler and OSD features. The DDR2 interface on ADV8003 is designed to meet the JESD79-2F standard.

2.2.5.1.

DDR2 Configuration

The controls described in this section are used to configure the ADV8003 DDR2 memory interface.

The first three bits configure the DDR2 memory interface for the external memory configuration. The sdram_size[3:0]

sets the memory

size of the attached memory or memories. For example, if using 256 Mbit memory, sdram_size[3:0]

should be set to 0001. If using 512

Mbit memory, sdram_size[3:0]

should be set to 0010.

The word_size[3:0] and burst_length[2:0] fields

must also be configured depending on whether there are single or multiple memories

connected to the ADV8003. If there is a single DDR2 memory, word_size[3:0] and burst_length[2:0] should be set for a 32-bit word size and bursts of 8. If there are dual DDR2 memories, word_size[3:0]

and

burst_length[2:0] should be set for a 64-bit word size and bursts of

4.



ADV8003 is configured for dual 512 Mbit memories with a 64-bit word size and bursts of 4. sdram_size[3:0] , IO Map, Address 0x1A5B[7:4]

This signal is used to specify the SDRAM size. All values other than those specified here are reserved.

Function sdram_size[3:0]

0001

0010 

0011

Description individual SDRAM is 256Mbit individual SDRAM is 512Mbit individual SDRAM is 1Gbit word_size[3:0] , IO Map, Address 0x1A5C[7:4]

This signal is used to specify the word size on the user interface. The data width to the SDRAM is half of this value. All other values are reserved

Function word_size[3:0] Description

0010

0011 

32 bits

64 bits burst_length[2:0] , IO Map, Address 0x1A5D[1:0]; Address 0x1A5E[7]

This signal is used to indicate the burst length of the read/write transaction.

Function burst_length[2:0]

010 

011

Description

Burst of 4

Burst of 8.

rw_ctrl_oe sets the direction for several of the pins on the DDR2 memory interface. By default, these pins are set to input. However, when set to 1, this bit enables these pins to be outputs. Likewise, when ddr2_ck_oe is set to 1, the DDR2 clock pin becomes an output.

rw_ctrl_oe , IO Map, Address 0x1AA8[7]

This bit is used to control the output enable for external memory read/write signals (ras, cas, clock, address…).

Function rw_ctrl_oe Description

0 

1

Input

Output ddr2_ck_oe , IO Map, Address 0x1AA8[6]

This bit is used to control the output enable for external memory clock signal.

Function ddr2_ck_oe

0 

1

Description

Input

Output

The PLL clock generator for the DDR2 memory interface can be set to a user defined frequency over the range of 200 to 250MHz by

setting the plldll_sel_div[5:0] and the plldll_pre_div[1:0] I

2 C controls.



Figure 42: DDR2 PLL Architecture

Figure 42 shows the block diagram of the PLL with the relevant I memory interface clock is given in Equation 3 .

2 C controls. The formula used to determine the frequency of the DDR2

F

ddr 2 _ clk

≡

(

F

xtal_clk

)(

plldll plldll

_

_

sel pre

_

div

_

div

)

+

1

Equation 3: DDR2 Memory Interface Clock Frequency

The DDR2 clock frequency must not be changed during operation and should only be set prior to initialization of the memory interface. plldll_sel_div[5:0] , IO Map, Address 0x1AA2[5:0]

This signal is used to control the DDR2 PLL loop divider. The DDR2 clock frequency is given by: fxtal * i2c_plldll_sel_div / i2c_plldll_pre_div. plldll_pre_div[1:0] , IO Map, Address 0x1AA3[3:2]

This signal is used to control the DDR2 PLL pre divider.

2.2.5.2.

DDR2 Bandwidth and Memory Selection

The DDR2 interface on ADV8003 can be configured to work with one or two (default) DDR2 memories. Using a single DDR2 memory limits the amount of functionality. Different capabilities are possible with different memory sizes. An outline of expected limitations are

outlined in Table 11 ,

Table 10

and Table 12 .

Features

SD input

HD input

(720p)

HD input

(1080i)

HD input

(1080p)

FRC

Supported

Supported

Supported

Not supported

- VSP_3D works in bypass mode

Table 10: Indication of ADV8003 Capabilities with One DDR2 Memory

Motion OSD Dual Output (ADV8003-1 only)

Adaptive Deinterlacing

Random Noise

Reduction

Supported

N/A

Intra-field interpolation not supported

N/A

Supported

Not supported

Not supported

Not supported

Total area of all OSD regions (on screen at same time) must be <

2 * 720 * 480 pixels.

(Entire OSD can be upscaled to desired output resolution)

Supported

Supported

Supported

Support only for:

TX1 ->1080p; TX2 ->

480p/720p/1080p, as VSP_3D works in bypass mode



Features

SD input

HD input

(720p)

HD input

(1080i)

HD input

(1080p)

FRC

Supported

Supported

Supported

Supported

Table 11: Indication of ADV8003 Capabilities with Two DDR2 Memories

Motion OSD

Adaptive Deinterlacing

Random Noise

Reduction

Supported

N/A

Supported

N/A

Supported

Supported

Supported

Only supported for

8- bit processing.

Cannot be supported when

OSD enabled.

Total area of all OSD regions (on screen at same time) must be < 3 * 720 *

480 pixels.

(Entire OSD can be upscaled to desired output resolution)

FRC

SD/ED input

Table 12: Indication of ADV8003 Capabilities with Different Memory Sizes

1Gbx2 512 Mbx2 1Gbx1

Supported Supported Supported

HD input

720P60/50 Supported

1080P60/50->1080P50/60@32/24/16bit Supported

Supported

Supported

Supported

Not Supported

1080P60->1080P24@32/24bit

1080P60->1080P24@16bit

Motion Adaptive De-interlacing

SD/ED input

HD input

1080i60/50@32/24bit

1080i60/50@16bit*

Intra-field De-interlacing

SD/ED input

HD input

1080i60/50@32bit

1080i60/50@24/16bit

RNR

SD/ED input

HD input

720P60/50@32/24bit

720P60/50@16bit

1080i60/50@32/24/16bit

Supported

Supported

Supported

Supported

Supported

Supported

Supported

Supported

Supported

Supported

Supported

Supported

Supported

Supported

Supported

Supported

Supported

Supported

Supported

Supported

Not Supported

Supported

Supported

Not Supported

Supported

Supported

Not Supported

Supported

Supported

Not Supported

1080P60/50@32/24bit

1080P60/50@16bit

Game Mode

SD/ED input

HD input

Memory left for OSD (Mbytes)

Supported

Supported

Supported

Supported

Not Supported Not Supported Not Supported

Supported Supported Not Supported

Supported

Not Supported

Supported

Supported

198.25

Supported

Supported

70.25

Supported

Supported

70.25

Dual Output (ADV8003-1 only)

Supported

Supported

Supported

Supported

Supported

Not Supported

Supported

Supported

Not Supported

Supported

Not Supported

Not Supported

Not Supported

Supported

Supported

6.25

512 Mbx1

Supported

Supported

Not Supported

Not Supported

Supported

Supported

Not Supported

Supported



2.2.5.3.

Single DDR2 Memory Configuration

If using a single DDR2 memory, the number of field buffers must be reduced from seven (default) to four when performing de-interlacing and scaling on 720p, 1080i and 1080p inputs. This is achieved by enabling intra field interpolation and setting

( pvsp_ex_mem_data_format[1:0] ) to indicate 16-bit 4:2:2. Next

pvsp_frc_low_latency_mode must be enabled. Finally, the field buffers

addresses in DDR2 must be reassigned as follows:

0xE800[31:0] ( pvsp_fieldbuffer0_addr[31:0] ) = 5184000

0xE804[31:0] ( pvsp_fieldbuffer1_addr[31:0] ) = 9331200

0xE808[31:0] ( pvsp_fieldbuffer2_addr[31:0] )

= 13478400

0xE80C[31:0] ( pvsp_fieldbuffer3_addr[31:0] )

= 17625600


= 21772800


= 25920000


= 27578880

2.2.5.4.

DDR2 Loopback Test

The ADV8003 features a DDR2 loopback test block to allow testing of the ADV8003 DDR2 interface. When the loopback test block is enabled, it controls the commands sent to the DDR2 controller of the ADV8003 and generates pseudo random data and addresses using a defined protocol.

The controller first writes a programmable number of random 32-bit words to the external memory. The same number of reads are then performed from the written addresses. The readback is compared with the pseudo random data generated to check if there are any errors.

The results are available via I 2 C readback.

32-bit data 16-bit data

512Mb x16

External

DDR2 Mem

DDR2

Controller address control

Phy address control

Loopback

Test Logic 32-bit data

Figure 43: DDR2 Loopback Test Architecture

A two memory DDR2 loopback test is initialized and started via the following writes:

1A 1A5B 22 ; Recommended Write

1A 1A5F 00 ; Recommended Write

1A 1A61 06 ; Recommended Write

1A 1AA0 13 ; Recommended Write



1A 1AA3 1D ; Recommended Write





16-bit data

512M x16

External

DDR2 Mem

1A 1AA8 B4 ; Recommended Write

1A 1AFE 08 ; Recommended Write


1A E649 40 ; Recommended Write

A single memory DD2 loopback test is initialized and started via the following writes:


1A 1A5C 20 ; Recommended Write

1A 1A5E 80 ; Recommended Write

1A 1A5F 00 ; Recommended Write

1A 1A61 06 ; Recommended Write




1A 1AA3 1D ; Recommended Write




1A 1AA8 B4 ; Recommended Write

1A 1AB2 02 ; Recommended Write

1A 1AFE 08 ; Recommended Write

The result of the DDR2 loopback test is given by the lbk_test_done and lbk_test_result bits.

lbk_test_done , IO Map, Address 0x1AE1[0] (Read Only)

This bit is used to readback the DDR2 loopback test has completed.

Function lbk_test_done Description

0 

1

Test not complete

Loopback test finished lbk_test_result , IO Map, Address 0x1AE1[1] (Read Only)

This bit is used to readback the DDR2 loopback test error result.

Function lbk_test_result Description

0 

1

No error detected

Errors detected

The following are possible failures that could cause the DDR2 loopback test to fail:

• Address or control or clock open or short: all bit lines failing

• Single DQ open or short to ground or supply: single bit line failing on both positive and negative edges

• Short between DQ lines: two bit lines failing, routing in adjacent resistors of resistor pack

• DQS or DM open or short: eight DQ lines failing

• Timing transfer problem: one or more bit lines failing


2.2.6.

I 2 C Auto Increment

read_auto_inc_en is used to auto increment register addresses to allow the user to do consecutive reads from the registers on the



ADV8003. By default, this is set to 1 which means that a read from a particular address in the ADV8003 increments the read pointer to the next register map address. read_auto_inc_en , IO Map, Address 0x1AFC[0]

This register is used to auto increment I2C addresses in the device for consecutive reads.

Function read_auto_inc_en

0

1 

Description

No auto increment of I2C address for consecutive reads

Auto increment of I2C address for consecutive reads

2.2.7.

SPI Loop Through

The ADV8003 SPI ports can be put in loop through mode for programming the external SPI flash that may be connected to the ADV8003

master SPI port (if an OSD design is to be used). Refer to Section 4.2.8 for more information.

spi_loop_through , IO Map, Address 0x1AB6[5]

This bit is used to enable SPI loop through mode.

Function spi_loop_through

0 

1

Description

Regular SPI mode

SPI slave clock routed to SPI master clock output

2.2.8.

VBI Data Insertion

ADV8003 supports VBI data (such as CGMS, WSS, and CCAP) insertion into the video stream through either the ancillary data input (Y channel input of 36-bit data bus) or the SPI-compatible slave input (VBI_SCK, VBI_MOSI and VBI_CS). When using the SPI-compatible slave input for VBI insertion, a reduced set of video input formats are supported on the EXOSD TTL input due to the shared pins. The

VBI data is decoded and supplied to the encoder for output in the video data stream.

The supported VBI standards are the following:

• WSS (625i)

• CCAP (525i and 625i)

• CGMS (525i)

• CGMS (525p)

• CGMS (625p)

2.2.8.1.

Extraction Overview

VBI data can be supplied to the ADV8003 through two separate interfaces. If there is a pixel bus input from the front end decoder then the VBI data may be provided via an ancillary data stream encoded into the video data. If a pixel bus is not available, the VBI data can be

sent via the dedicated SPI interface. Refer to Figure 44 for an overview of this architecture.


External

SPI

Master sclk ss mosi

SPI

Slave y_data_in[11:4] hdmi_rx_clk vid_rx_clk

1

0

ADV8003 Hardware Manual vbi_src (1 = SPI, 0 = ANC)

Sync spi_rx_dv

1

0

1’b1 ccap_even_data ccap_even_dv ccap_odd_data

Ancillary

Data

Extractor ccap_odd_dv cgms_wss_data

Ancillary

Data

Delay ccap_out ccap_ext_out cgms_wss_out_sd

To Encoder spi_rx_dv[7:0]

1 muxed_vid_in

0 cgms_wss_dv cgms_wss_out_hd

Figure 44: VBI Data Extraction Block Diagram

2.2.8.2.

Ancillary Data Extraction

The ancillary data which is encoded in either nibble mode or byte mode is extracted from the input data stream on the Y channel and the

VBI data is retrieved. The DID and SDID from the sending device must match the value programmed in 1A 1A4A[7:0] and 1A 1A4B[7:0].

The format of the ancillary data packet is shown in Table 13 .

Byte B9 B8 B7

0

1

4

5

8

9

2

3

6

7

10

11

12

13

0

1

1

EP

EP

0

1

1

EP

EP

0

1

1

B6

0

1

1

1

1

Table 13: Output Mode Outline

B5 B4 B3 B2 B1 B0 Description

0 0 0 0 0 0

1

1

1

1

I2C_DID6[4:0]

1

1

1

1

0

1

1

0

Ancillary Data Preamble

I2C_SDID7_2[5:0]

0

0

0

0

DID Data Identification Word

SDID Secondary Data Identification

Word

ID1 User Data Word 1 EP EP 0 DC[4:0]

EP EP Padding[1:0] VBI_DATA_STD[3:0]

EP EP

LCOUNT[11:6]

EP EP

EP

EP

EP

EP

0

0

0

0

LCOUNT[5:0]

0 EF VDP_TTXT

TYPE[1:0]

VBI_WORD_1[7:4]

EP EP 0 0 VBI_WORD_1[3:0]

EP EP 0

EP EP 0

0

0

VBI_WORD_2[7:4]

VBI_WORD_2[3:0]

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

ID2 User Data Word 2








1 0 0

N-1 B8 Checksum

0 0 0 0 0 0

0

0

0

Pad, May or may not be present



2.2.8.3.

SPI Data Extraction

If there is not an input video data bus which can provide the ancillary data, it may be serialized and sent to the part via a SPI master. The

ADV8003 contains a dedicated SPI slave for receiving VBI data. The SPI interface receives serialized ancillary data bytes. All of the ancillary data packets must be encoded, including the preamble. A high to low transition on the VBI_CS line indicates the start of a new

byte. As the bytes are directly encoded ancillary data, the same decoder described in Section 2.2.8.2 for ancillary data can be used to

extract the VBI data. Only modes 0 and 3 are supported by the SPI slave and, therefore, the SPI master must use one of these modes.

2.2.8.4.

VBI Data Delay

Once the VBI data has been decoded for each of the supported standards, it is latched and delayed by the desired amount. The delay on the VBI data is measured in frames and is controllable in the range 0 ≤ delay ≤ 3 frames. The data can be delayed on either the rising or falling edge of the input VSync. The output VBI data is muxed directly with the VBI data from the encoder register map before being output by the encoder. vbi_src , IO Map, Address 0x1A4C[7]

This bit is used to choose the source of the VBI data.

Function vbi_src

0 

1

Description

VBI data from ancillary input

VBI data from SPI input ccap_odd_en , IO Map, Address 0x1A4C[3]

This bit is used to enable/disable closed caption data extraction on the odd field.

Function ccap_odd_en

0 

1

Description

Disable closed caption data extraction on odd field

Enable closed caption data extraction on odd field ccap_even_en , IO Map, Address 0x1A4C[2]

This bit is used to enable/disable closed caption data extraction on the even field.

Function ccap_even_en Description

0 

1

Disable closed caption data extraction on even field

Enable closed caption data extraction on even field cgms_anc_en , IO Map, Address 0x1A4C[1]

This bit is used to enable/disable CGMS data extraction on the even field.

Function cgms_anc_en

0 

1

Description

Disable CGMS data extraction on even field

Enable CGMS data extraction on even field wss_anc_en , IO Map, Address 0x1A4C[0]

This bit is used to enable/disable WSS data extraction on the even field.



Function wss_anc_en

0 

1

Description

Disable WSS data extraction on even field

Enable WSS data extraction on even field anc_delay[1:0] , IO Map, Address 0x1A4D[1:0]

This bit is used to set the delay on ancillary data in vsyncs. The interlaced input delay will be in fields and the progressive delay will be in frames. Decoded data is firstly transferred onto input vsync and then output vsync, this will be the base delay with a setting of 0. Every increment above this adds one input vsync delay. did_a[7:0] , IO Map, Address 0x1A4A[7:0]

This register is used to specify the value of the DID sent in the ancillary stream with VBI decoded data. sdid_a[7:0] , IO Map, Address 0x1A4B[7:0]

This register is used to specify the value of the SDID sent in the ancillary stream with VBI decoded data.

2.2.9.

Resets

This section documents the register bits used for resetting various sections of the ADV8003. These resets can be used by the system controller to reset individual sections of the device without having to reset the whole part. If the whole device needs to be reset, this can be

implemented by setting the global reset, main_reset . All these register bits are self clearing, which means that when set to 1, they are set

back to 0 after the appropriate section has been reset.

Refer to

Section 6.2 for more information on the reset strategy for the HDMI Tx.

svsp_reset , IO Map, Address 0x1AFD[7] (Self-Clearing)

This bit is used to reset the Secondary VSP.

Function svsp_reset

0 

1

Description

Default

Reset pvsp_reset , IO Map, Address 0x1AFD[6] (Self-Clearing)

This bit is used to reset the Primary VSP.

Function pvsp_reset

0 

1

Description

Default

Reset p2i_reset , IO Map, Address 0x1AFD[5] (Self-Clearing)

This bit is used to reset the Progressive to Interlaced core.


Function p2i_reset

0 

1

Description

Default

Reset ddr2_intf_reset , IO Map, Address 0x1AFD[4] (Self-Clearing)

This bit is used to reset the external DDR memory interface core.

Function ddr2_intf_reset Description

0 

1

Default

Reset spi_reset , IO Map, Address 0x1AFD[3] (Self-Clearing)

This bit is used to reset the SPI hardware, both master and slave.

Function spi_reset Description

0 

1

Default

Reset sys_clk_reset , IO Map, Address 0x1AFD[2] (Self-Clearing)

This register bit resets the clock for the digital core.

Function sys_clk_reset

0 

1

Description

Default

Reset osd_reset , IO Map, Address 0x1AFD[1] (Self-Clearing)

This bit is used to reset the OSD core and the secondary input channel.

Function osd_reset

0 

1

Description

Default

Reset inp_sdr_reset , IO Map, Address 0x1AFD[0] (Self-Clearing)

This bit is used to reset the input capture and formatting logic for the primary input channel.

Function inp_sdr_reset

0 

Description

Default

1 Reset rx_reset , IO Map, Address 0x1AFE[7] (Self-Clearing)

This bit is used to reset the Serial Video Rx core and the RX input channel.




Function rx_reset

0 

1

Description

Default

Reset enc_reset , IO Map, Address 0x1AFE[6] (Self-Clearing)

This bit is used to reset the HD and SD encoders.

Function enc_reset Description

0 

1

Default

Reset tx2_reset , IO Map, Address 0x1AFE[5] (Self-Clearing)

This bit is used to reset the HDMI TX2.

Function tx2_reset Description

0 

1

Default

Reset tx1_reset , IO Map, Address 0x1AFE[4] (Self-Clearing)

This bit is used to reset the HDMI TX1.

Function tx1_reset

0 

1

Description

Default

Reset dpll_reset , IO Map, Address 0x1AFE[2] (Self-Clearing)

This bit is used to reset the DPLL clock generator.

Function dpll_reset

0 

1

Description

Default

Reset xtal_reset , IO Map, Address 0x1AFE[0] (Self-Clearing)

This bit is used to reset all the clocks in the device and peripheral logic in the core including some CEC logic, the interrupt generator and the automatic clock selection.

Function xtal_reset Description

0 

1

Default

Reset main_reset , IO Map, Address 0x1BFF[7] (Self-Clearing)

This bit is used to initiate a global reset for the device.



Function main_reset

0 

1

Description

Default

Reset

2.2.10.

Image Processing Colorimetry Breakdown

The ADV8003 performs its image processing in the YUV format except for the internal OSD which is generated in RGB. The internally generated OSD is muxed with the external OSD (which can be in either YUV or RGB) before being input into a CSC. The CSC converts all input signals into YUV format for input into the OSD video blend block.

External OSD In

(YUV/RGB) C

S

C

OSD Video

Blend

(YUV)

De-interlacer and Cadence

Detection

(YUV)

Video

Enhancement

(YUV)

Scaling and

Frame Rate

Conversion

(YUV)

OSD

Generation

(RGB)

Motion

Detection

Random Noise

Reduction

Bitmap OSD

Controller

Scaler 1

Low Angle

Processing

Mosquito Noise

Reduction

OSD Scaler

Scaler 2

Cadence

Detection

Block Noise

Reduction

Cue

Correction

Detail

Enhancement

Frame Rate

Converter

Figure 45: ADV8003 Image Processing Colorimetry Breakdown

2.2.11.

AV-Codes

Embedded end of active video (EAV) and start of active video (SAV) timing codes are supported on the TTL inputs of the ADV8003. AVcode information is embedded into the pixel data and is transmitted using a standard 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace.

The following video formats are supported automatically for AV-code insertion.

• 480i60

• 576i50

• 240p60

• 288p50

• 480p60

• 576p50

• 720p60

• 720p50

• 1080i60

• 1080i50

• 1080p60



• 1080p50

• VGA (640x480)

• SVGA (800x600)

• XGA (1027x768

• WXGA (1280x768)

• SXGA (1280x1024)

• WXGA (1360x768)

• UXGA (1600x1200)

• WXGA(1366x768

• WUXGA (1900x1200)

A number of CEA formats are not supported automatically for AV-codes

• 1920x1080p @ 23.97/24 Hz (CEA VIC 32)

• 1920x1080p @ 25 Hz (CEA VIC 33)

• 1920x1080p @ 29.97/30 Hz (CEA VIC 34)

• 1280x720p @ 23.97/24 Hz (CEA VIC 60)

• 1280x720p @ 25 Hz (CEA VIC 61)

• 1280x720p @ 29.97/30 Hz (CEA VIC 62)

These formats can be supported following the manual configuration mode outlined in this section. de_v_beg_e_pos[6:0] , IO Map, Address 0x1A79[7:1]

This signal is used to select the DE vertical beginning position for even fields if CEA 861 timing generation is enabled and manual values selected.

Function de_v_beg_e_pos[6:0]

0xXX

Description

Assert de when lcount reaches 0xXX on even fields de_v_beg_o_pos[6:0] , IO Map, Address 0x1A79[0]; Address 0x1A7A[7:2]

This signal is used to select the DE vertical beginning position for odd fields if CEA 861 timing generation is enabled and manual values selected.

Function de_v_beg_o_pos[6:0] Description

0xXX de_h_beg_pos[9:0] , IO Map, Address 0x1A7A[1:0]; Address 0x1A7B[7:0]

This signal is used to select the DE horizontal beginning position, counting from the EAV, if CEA 861 timing generation is enabled and manual values selected.

Function de_h_beg_pos[9:0]

0xXX

Assert de when lcount reaches 0xXX on even fields

Description

Assert de when hcount reaches 0xXX hs_beg_pos[9:0] , IO Map, Address 0x1A7C[7:0]; Address 0x1A7D[7:6]

This signal is used to select the HS beginning position, counting from the EAV, if CEA 861 timing generation is enabled and manual values selected.



Function hs_beg_pos[9:0]

0xXX

Description

Assert hs when hcount reaches 0xXX hs_end_pos[9:0] , IO Map, Address 0x1A7D[5:0]; Address 0x1A7E[7:4]

This signal is used to select the HS ending position, counting from the EAV, if CEA 861 timing generation is enabled and manual values selected.

Function hs_end_pos[9:0] Description

0xXX vs_h_beg_o_pos[10:0] , IO Map, Address 0x1A7E[2:0]; Address 0x1A7F[7:0]

This signal is used to select the VS horizontal beginning position on odd fields, counting from the EAV, if CEA 861 timing generation is enabled and manual values selected.

Function vs_h_beg_o_pos[10:0]

0xXX

Release hs when hcount reaches 0xXX

Description

Assert vs when hcount reaches 0xXX on odd fields vs_h_beg_e_pos[10:0] , IO Map, Address 0x1A80[7:0]; Address 0x1A81[7:5]

This signal is used to select the VS horizontal beginning position on even fields, counting from the EAV, if CEA 861 timing generation is enabled and manual values selected.

Function vs_h_beg_e_pos[10:0] Description

0xXX Assert vs when hcount reaches 0xXX on even fields vs_v_beg_pos[5:0] , IO Map, Address 0x1A81[3:0]; Address 0x1A82[7:6]

This signal is used to select the VS vertical beginning position, if CEA 861 timing generation is enabled and manual values selected.

Function vs_v_beg_pos[5:0]

0xXX

Description

Assert vs when lcount reaches 0xXX vs_v_end_pos[5:0] , IO Map, Address 0x1A82[5:0]

This signal is used to select the VS vertical ending position, if CEA 861 timing generation is enabled and manual values selected.

Function vs_v_end_pos[5:0]

0xXX

Description

Release vs when lcount reaches 0xXX

For the secondary input channel, the controls are as follows: de_v_beg_e_pos[6:0] , IO Map, Address 0x1B8C[7:1]

This signal is used to specify the DE vertical beginning position for even fields, if CEA 861 timing generation is enable and manual values selected.



Function de_v_beg_e_pos[6:0]

0xXX

Description assert de when lcount reaches 0xXX on even fields de_v_beg_o_pos[6:0] , IO Map, Address 0x1B8C[0]; Address 0x1B8D[7:2]

This signal is used to specify the DE vertical beginning position for odd fields, if CEA 861 timing generation is enable and manual values selected.

Function de_v_beg_o_pos[6:0] Description

0xXX de_h_beg_pos[9:0] , IO Map, Address 0x1B8D[1:0]; Address 0x1B8E[7:0]

This signal is used to specify the DE horizontal beginning position, counting from the EAV, if CEA 861 timing generation is enable and manual values selected.

Function de_h_beg_pos[9:0]

0xXX assert de when lcount reaches 0xXX on even fields

Description assert de when hcount reaches 0xXX hs_beg_pos[9:0] , IO Map, Address 0x1B8F[7:0]; Address 0x1B90[7:6]

This signal is used to specify the HS beginning position, counting from the EAV, if CEA 861 timing generation is enable and manual values selected.

Function hs_beg_pos[9:0] Description

0xXX hs_end_pos[9:0] , IO Map, Address 0x1B90[5:0]; Address 0x1B91[7:4]

This signal is used to specify the HS ending position, counting from the EAV, if CEA 861 timing generation is enable and manual values selected.

Function hs_end_pos[9:0]

0xXX assert hs when hcount reaches 0xXX

Description release hs when hcount reaches 0xXX vs_h_beg_o_pos[10:0] , IO Map, Address 0x1B91[2:0]; Address 0x1B92[7:0]

This signal is used to specify the horizontal beginning position of VS for odd fields (counting from the EAV), if CEA 861 timing generation is enable and manual values selected.

Function vs_h_beg_o_pos[10:0]

0xXX

Description assert vs when hcount reaches 0xXX on odd fields vs_h_beg_e_pos[10:0] , IO Map, Address 0x1B93[7:0]; Address 0x1B94[7:5]

This signal is used to specify the horizontal beginning position of VS for even fields (counting from the EAV), if CEA 861 timing generation is enable and manual values selected.



Function vs_h_beg_e_pos[10:0]

0xXX

Description assert vs when hcount reaches 0xXX on even fields vs_v_beg_pos[5:0] , IO Map, Address 0x1B94[3:0]; Address 0x1B95[7:6]

This signal is used to specify the vertical beginning position of VS, if CEA 861 timing generation is enable and manual values selected.

Function vs_v_beg_pos[5:0] Description

0xXX assert vs when lcount reaches 0xXX vs_v_end_pos[5:0] , IO Map, Address 0x1B95[5:0]

This signal is used to specify the vertical ending position of VS, if CEA 861 timing generation is enable and manual values selected.

Function vs_v_end_pos[5:0] Description

0xXX release vs when lcount reaches 0xXX

A worked example showing how 720 (1440) x 240p can be supported using manual AV-code configuration is shown in Figure 46 . The

horizontal measurements must be the following:

de_h_beg_pos[9:0] = 276/2 = 138 = 0010001010 de_v_beg_o_pos[6:0] = 22 = 0010110 de_v_beg_e_pos[6:0] = 22 = 0010110 hs_beg_pos[9:0] = 38/2 = 19 = 0000010011

hs_end_pos[9:0] = 162/2 = 81 = 0001010001 vs_v_beg_pos[5:0] = 4 = 000100 vs_h_beg_o_pos[10:0] = 38/2 = 19 = 00000010011 vs_h_beg_e_pos[10:0] = 38/2 = 19 = 00000010011 vs_v_end_pos[5:0] = 7 = 000111


ADV8003 Hardware Manual de_h_beg_pos (276) hs_beg_pos (38) vs_h_beg_o_pos (38) vs h beg e pos (38) hs_end_pos (38 + 124 = 162) vs_v_beg_pos (4) de_v_beg_e_pos (22) vs_v_end_pos (7) de_v_beg_o_pos (22) vs_v_beg_pos (4) vs_v_end_pos (7)

Figure 46: 720(1440) x 240p @ 59.94/60Hz, CEA Formats 8 and 9

2.2.12.

Color Space Conversion

Although all processing in the ADV8003 is performed in the YCbCr color space, the part is capable of receiving video in the RGB, YUV and YCbCr color spaces. The ADV8003 provides any-to-any CSC on each of the inputs and on both of the outputs (five color space converters in all). All CSCs support formats such as RGB, YUV and YCbCr. The front end CSCs on the primary input channel, secondary input channel and RX input channel run at a maximum clock rate of 162 MHz. The back end CSCs in HDMI TX1 and HDMI TX2 operate at a maximum input clock rate of 300 MHz.

2.2.12.1.

Primary Input Channel CSC

The CSC must be manually configured for each color space conversion. The CSC on the primary input channel can be enabled using the

vid_csc_enable control. The CSC mode on the primary input channel can be configured using vid_csc_mode[1:0] . The CSC mode is used to define the fixed point position of the CSC coefficients which are located after vid_csc_mode[1:0] in the IO Map for the primary input

channel.

Reference configuration scripts to configure the primary input channel CSC are provided with the evaluation software.


ADV8003 Hardware Manual vid_csc_enable , IO Map, Address 0x1B30[7]

This bit is used to control the Primary Input Channel CSC.

Function vid_csc_enable Description

0 

1

CSC disable

CSC enable vid_csc_mode[1:0] , IO Map, Address 0x1B30[6:5]

This signal is used to specify the CSC mode for the Primary Input Channel CSC. The CSC mode sets the fixed point position of the CSC coefficients, including a4, b4, c4 and offsets.

Function vid_csc_mode[1:0]

00 

01

10

11

Description

+/- 1.0, -4096 to 4095

+/-2.0, -8192 to 8190

+/- 4.0, -16384 to 16380

+/- 4.0, -16384 to 16380

The characteristic equations for the primary input CSC are provided in Equation 4 , Equation 5 and Equation 6 .

Out _ A

=



 In _ A

∗

A 1 [ 12 :

4096

0 ]

+

In _ B

∗

A 2 [ 12 :

4096

0 ]

+

In _ C

∗

A 3 [ 12 :

4096

0 ]

+

A 4 [ 12 : 0 ]





∗

2

CSC _ scale

Equation 4: Primary Input CSC Channel A Output

Out _ B

=



 In _ A

∗

B 1 [ 12 :

4096

0 ]

+

In _ B

∗

B 2 [ 12 :

4096

0 ]

+

In _ C

∗

B 3 [ 12 :

4096

0 ]

+

B 4 [ 12 : 0 ]





∗

2

CSC _ scale

Equation 5: Primary Input CSC Channel B Output

Out _ C

=



 In _ A

∗

C 1 [ 12 :

4096

0 ]

+

In _ B

∗

C 2 [ 12 :

4096

0 ]

+

In _ C

∗

C 3 [ 12 :

4096

0 ]

+

Equation 6: Primary Input CSC Channel C Output

The CSC on the primary input channel is illustrated in Figure 47 .

C 4 [ 12 : 0 ]





∗

2 CSC

vid_csc_mode

_ scale

vid_a1 4096 vid_a4

4x

2

In_A

x

vid_a2

+ + ÷ + 2x 1

Out_A

0

In_B

x

vid_a3

In_C

x

Rev. B, August 2013

Figure 47: Primary Input Channel CSC

131


The video inputs In_A, In_B and In_C are connected by default to R, G and B. Refer to Table 14 for more information. The default routing

can be changed by adjusting the value of vid_swap_bus_ctrl[2:0] .

Table 14: Default Primary Input Channel CSC Signal Routing

Input Channel Default RGB Routing Default YCbCr Routing

In_A R Cr

In_B

In_C

G

B

Y

Cb

The A1 to A3, B1 to B3, and C1 to C3 coefficients are used to scale the primary inputs. A4, B4 and C4 are added as offsets. Floating point coefficients must be converted into 120-bit fixed decimal format then converted into binary format using twos complement for negative values and can only be programmed in the range [-1….+1] or [-4096….+4095].

The dynamic range of the CSC is [0…..1] for unipolar signals (Y, R, G, B) or [-0.5…….+0.5] for bipolar signals. Bipolar signals (Pr/Pb)

must be offset to mid range. Equations with a dynamic range larger than 1 need to be scaled appropriately using the vid_csc_mode[1:0] control. To achieve a coefficient value of 1.0 for any given coefficient, vid_csc_mode[1:0] should be set high and the coefficient should be

programmed to a value of 0.5. Otherwise, the largest value would be 4095/4096 = 0.9997. While this value could be interpreted as 1, it is

recommended to use the value of 0.5 and set the vid_csc_mode[1:0] bits for maximum accuracy.

The CSC configurations for common modes are provided in Table 15 .

Table 15: Primary Input Channel CSC Common Configuration Coefficients

Color Space

Conversion

A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4

HDTV YCbCr

(limited) to

RGB (limited)

HDTV YCbCr

(limited) to

RGB (full)

HDTV YCbCr

(limited) to

SDTV YCbCr

(limited)

HDTV YCbCr

(limited) to

SDTV YCbCr

(full)

HDTV YCbCr

(limited) to

RGB (limited)

HDTV YCbCr

(limited) to

RGB (full)

HDTV YCbCr

(full) to SDTV

YCbCr

(limited)

SDTV YCbCr

(limited) to

RGB (limited)

SDTV YCbCr

(limited) to

0x1 0x0C53 0x0800 0x0000 0x19D6 0x1C56 0x0800 0x1E88 0x0291 0x1FFF 0x0800 0x0E85 0x18BE

0x2 0x0734 0x04AD 0x0000 0x1C1B 0x1DDC 0x04AD 0x1F24 0x0135 0x0000 0x04AD 0x087C 0x1B77

0x1 0x07DD 0x0000 0x1F6C 0x005B 0x0188 0x0800 0x00CB 0x1ED6 0x1F1D 0x0000 0x07EB 0x007B

0x1 0x08EB 0x0000 0x1F58 0x1FDE 0x01C9 0x0950 0x00EC 0x1F25 0x1EFF 0x0000 0x08FA 0x031F



0x0 0x0E0D 0x0000 0x0000 0x0100 0x0000 0x0DBC 0x0000 0x0100 0x0000 0x0000 0x0E0D 0x0100

0x1 0x0AF8 0x0800 0x0000 0x1A84 0x1A6A 0x0800 0x1D50 0x0423 0x1FFC 0x0800 0x0DDE 0x1913

0x2 0x0669 0x04AC 0x0000 0x1C81 0x1CBC 0x04AD 0x1E6E 0x0220 0x1FFE 0x04AD 0x081A 0x1BA9


Color Space

Conversion


A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4

RGB (full)

SDTV YCbCr

(limited) to

HDTV YCbCr

(limited)

SDTV YCbCr

(limited) to

SDTV YCbCr

(full)

SDTV YCbCr

(limited) to

RGB (limited)

SDTV YCbCr

(limited) to

RGB (full)

SDTV YCbCr

(full) to HDTV

YCbCr

(limited)

RGB (limited) to HDTV

YCbCr

(limited)

RGB (limited) to SDTV YCbCr

(limited)

RGB (limited) to RGB (full)

RGB (full) to

HDTV YCbCr

(limited)

RGB (Full) to

SDTV YCbCr

(limited)

RGB (Full) to

RGB (limited)

0x1 0x0833 0x0000 0x0099 0x1F99 0x1E56 0x0800 0x1F13 0x014B 0x00EA 0x0000 0x0826 0x1F78

0x1 0x091B 0x0000 0x0000 0x1F6E 0x0000 0x0950 0x0000 0x1F6B 0x0000 0x0000 0x091B 0x1F6E



0x2 0x039D 0x0000 0x0043 0x0F26 0x1F44 0x036F 0x1F97 0x00D2 0x0067 0x0000 0x0397 0x004D

0x0 0x082E 0x1893 0x1F3F 0x0800 0x0367 0x0B71 0x0128 0x0000 0x1E21 0x19B2 0x082D 0x0800

0x0 0x082E 0x1926 0x1EAC 0x0800 0x04C9 0x0965 0x01D2 0x0000 0x1D3F 0x1A93 0x082E 0x0800

0x0 0x0DBC 0x0000 0x0000 0x0100 0x0000 0x0DBC 0x0000 0x0100 0x0000 0x0000 0x0DBC 0x0100

0x0 0x06FF 0x19A6 0x1F5B 0x0800 0x02E9 0x09CB 0x00FD 0x0100 0x1E66 0x1A9B 0x06FF 0x0800

0x0 0x06FF 0x1A24 0x1EDD 0x0800 0x0418 0x080A 0x018F 0x0100 0x1DA5 0x1B5C 0x06FF 0x0800

0x1 0x0950 0x0000 0x0000 0x1F6B 0x0000 0x0950 0x0000 0x1F6B 0x0000 0x0000 0x0950 0x1F6B

Identity matrix

(output = input)

0x1 0x0800 0x0000 0x0000 0x0000 0x0000 0x0800 0x0000 0x0000 0x0000 0x0000 0x0800 0x0000

2.2.12.2.

Secondary Input Channel CSC

The CSC must be manually configured for each color space conversion. The CSC on the secondary input channel can be enabled using

the exosd_csc_enable

control. The CSC mode on the secondary input channel can be configured using exosd_csc_mode[1:0] . The CSC mode is used to define the fixed point position of the CSC coefficients which are located after exosd_csc_mode[1:0] in the IO Map for the

secondary input channel.

Reference configuration scripts to configure the secondary input channel CSC are provided with the evaluation software. exosd_csc_enable , IO Map, Address 0x1B50[7]

This bit is used to enable the Secondary Input Channel CSC.



Function exosd_csc_enable

0 

1

Description

CSC disable

CSC enable exosd_csc_mode[1:0] , IO Map, Address 0x1B50[6:5]

This signal is used to specify the CSC mode for the Secondary Input Channel CSC. The CSC mode sets the fixed point position of the

CSC coefficients, including a4, b4, c4 and offsets.

Function exosd_csc_mode[1:0] Description

00 

01

10

11

+/- 1.0, -4096 to 4095

+/-2.0, -8192 to 8190

+/- 4.0, -16384 to 16380

+/- 4.0, -16384 to 16380

The characteristic equations for the secondary input CSC are provided in Equation 7 , Equation 8 and Equation 9 .

Out _ A

=



 In _ A

∗

A 1 [ 12 :

4096

0 ]

+

In _ B

∗

A 2 [ 12 :

4096

0 ]

+

In _ C

∗

A 3 [ 12 :

4096

0 ]

+

A 4 [ 12 : 0 ]





∗

2

CSC _ scale

Equation 7: Secondary Input CSC Channel A Output

Out _ B

=



 In _ A

∗

B 1 [ 12 : 0 ]

+

In _ B

∗

B 2 [ 12 : 0 ]

+

In _ C

∗

B 3 [ 12 : 0 ]

+

B 4 [ 12

4096 4096 4096

Equation 8: Secondary Input CSC Channel B Output

: 0 ]





∗

2 CSC _ scale

Out _ C

=



 In _ A

∗

C 1 [ 12 :

4096

0 ]

+

In _ B

∗

C 2 [ 12 :

4096

0 ]

+

In _ C

∗

C 3 [ 12 :

4096

0 ]

+

C

Equation 9: Secondary Input CSC Channel C Output

The CSC on the secondary input channel is illustrated in Figure 48 .

4 [ 12

4096

: 0 ]





∗

2

CSC _ scale

exosd_csc_mode exosd_a1 exosd_a4

4x

2

In_A

x

exosd_a2

+ + ÷ + 2x 1

Out_A

0

In_B

x

exosd_a3

In_C

x

Figure 48: Secondary Input Channel CSC


can be changed by adjusting the value of exosd_swap_bus_ctrl[2:0] .



Table 16: Default Secondary Input Channel CSC Signal Routing


In_A

In_B

In_C

R

G

B

Cr

Y

Cb



must be offset to mid range. Equations with a dynamic range larger than 1 need to be scaled appropriately using the exosd_csc_mode[1:0] control. To achieve a coefficient value of 1.0 for any given coefficient, exosd_csc_mode[1:0] should be set high and the coefficient should

be programmed to a value of 0.5. Otherwise, the largest value would be 4095/4096 = 0.9997. While this value could be interpreted as 1, it

is recommended to use the value of 0.5 and set the exosd_csc_mode[1:0] bits for maximum accuracy.


Table 17: Secondary Input Channel CSC Common Configuration Coefficients

Color Space

Conversion

A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4

HDTV YCbCr

(limited) to

RGB (limited)

HDTV YCbCr

(limited) to

RGB (full)

HDTV YCbCr

(limited) to

SDTV YCbCr

(limited)

HDTV YCbCr

(limited) to

SDTV YCbCr

(full)

HDTV YCbCr

(limited) to

RGB (limited)

HDTV YCbCr

(limited) to

RGB (full)

HDTV YCbCr

(full) to SDTV

YCbCr

(limited)

SDTV YCbCr

(limited) to

RGB (limited)

SDTV YCbCr

(limited) to

RGB (full)

SDTV YCbCr

(limited) to












Color Space

Conversion


A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4

HDTV YCbCr

(limited)

SDTV YCbCr

(limited) to

SDTV YCbCr

(full)

SDTV YCbCr

(limited) to

RGB (limited)

SDTV YCbCr

(limited) to

RGB (full)

SDTV YCbCr

(full) to HDTV

YCbCr

(limited)


YCbCr

(limited)


(limited)









RGB (full) to

HDTV YCbCr

(limited)

RGB (full) to

SDTV YCbCr

(limited)

RGB (full) to

RGB (limited)

Identity Matrix

(Output =

Input)




0x1 0x0800 0x0000 0x0000 0x0000 0x0000 0x0800 0x0000 0x0000 0x0000 0x0000 0x0800 0x0000

2.2.12.3.

RX Input Channel CSC

The CSC must be manually configured for each color space conversion. The CSC on the RX input channel can be enabled using the

rx_csc_enable

control. The CSC mode on the RX input channel can be configured using rx_csc_mode[1:0] . The CSC mode is used to define the fixed point position of the CSC coefficients which are located after rx_csc_mode[1:0] in the IO Map for the RX input channel.

Reference configuration scripts to configure the RX input channel CSC are provided with the evaluation software. rx_csc_enable , IO Map, Address 0x1B70[7]

This bit is used to enable the RX input channel CSC.



Function rx_csc_enable

0 

1

Description

CSC disable

CSC enable rx_csc_mode[1:0] , IO Map, Address 0x1B70[6:5]

This signal is used to specify the CSC mode for the RX input channel CSC. The CSC mode sets the fixed point position of the CSC coefficients, including a4, b4, c4 and offsets.

Function rx_csc_mode[1:0] Description

00 

01

10

11

+/- 1.0, -4096 to 4095

+/-2.0, -8192 to 8190

+/- 4.0, -16384 to 16380

+/- 4.0, -16384 to 16380

The characteristic equations for the secondary input CSC are provided in Equation 10 , Equation 11 and Equation 12 .

Out _ A

=



 In _ A

∗

A 1 [ 12 :

4096

0 ]

+

In _ B

∗

A 2 [ 12 :

4096

0 ]

+

In _ C

∗

A 3 [ 12 :

4096

0 ]

+

A 4 [ 12 : 0 ]





∗

2

CSC _ scale

Equation 10: RX Input CSC Channel A Output

Out _ B

=



 In _ A

∗

B 1 [ 12 : 0 ]

+

In _ B

∗

B 2 [ 12 : 0 ]

+

In _ C

∗

B 3 [ 12 : 0 ]

4096 4096 4096

Equation 11: RX Input CSC Channel B Output

+

Out _ C

=



 In _ A

∗

C 1 [ 12 :

4096

0 ]

+

In _ B

∗

C 2 [ 12 :

4096

0 ]

+

In _ C

∗

C 3 [ 12 :

4096

0 ]

Equation 12: RX Input CSC Channel C Output

The CSC on the RX input channel is illustrated in Figure 48 .

+

B 4 [ 12

C 4 [ 12 :

:

4096

0 ]





∗

2 CSC _ scale

0 ]





∗

2

CSC _ scale

rx_csc_mode rx_a1 rx_a4

4x

2

In_A

x

rx_a2

+ + ÷ + 2x 1

Out_A

0

In_B

x

rx_a3

In_C

x

Figure 49: RX Input Channel CSC

The video inputs In_A, In_B and In_C are connected by default to R, G and B. For more information, please see Table 18 . The default

routing can be changed by adjusting the value of rx_swap_bus_ctrl[2:0] .



Table 18: Default RX Input Channel CSC Signal Routing


In_A

In_B

In_C

R

G

B

Cr

Y

Cb



must be offset to mid range. Equations with a dynamic range larger than 1 need to be scaled appropriately using the rx_csc_mode[1:0] control. To achieve a coefficient value of 1.0 for any given coefficient, rx_csc_mode[1:0] should be set high and the coefficient should be

programmed to a value of 0.5. Otherwise, the largest value would be 4095/4096 = 0.9997. While this value could be interpreted as 1, it is

recommended to use the value of 0.5 and set the rx_csc_mode[1:0] bits for maximum accuracy.


Table 19: RX Input Channel CSC Common Configuration Coefficients

Color Space

Conversion

A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4

HDTV YCbCr

(limited) to

RGB (limited)

HDTV YCbCr

(limited) to

RGB (full)

HDTV YCbCr

(limited) to

SDTV YCbCr

(limited)

HDTV YCbCr

(limited) to

SDTV YCbCr

(full)

HDTV YCbCr

(limited) to

RGB (limited)

HDTV YCbCr

(limited) to

RGB (full)

HDTV YCbCr

(full) to SDTV

YCbCr

(limited)

SDTV YCbCr

(limited) to

RGB (limited)

SDTV YCbCr

(limited) to

RGB (full)

SDTV YCbCr

(limited) to












Color Space

Conversion


A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4

HDTV YCbCr

(limited)

SDTV YCbCr

(limited) to

SDTV YCbCr

(full)

SDTV YCbCr

(limited) to

RGB (limited)

SDTV YCbCr

(limited) to

RGB (full)

SDTV YCbCr

(full) to HDTV

YCbCr

(limited)


YCbCr

(limited)


(limited)









RGB (full) to

HDTV YCbCr

(limited)

RGB (full) to

SDTV YCbCr

(limited)

RGB (full) to

RGB (limited)

Identity matrix

(output = input)




0x1 0x0800 0x0000 0x0000 0x0000 0x0000 0x0800 0x0000 0x0000 0x0000 0x0000 0x0800 0x0000

2.2.12.4.

HDMI Transmitter CSCs

Both of the HDMI transmitters feature an any-to-any CSC. The CSC register controls for HDMI TX1 are described here; the same controls co-exist in the HDMI TX2 Main Map for the HDMI TX2 CSC.

The CSC must be manually configured for each color space conversion. The HDMI TX CSC output can be enabled using the csc_en

control. The HDMI TX CSC mode can be configured using csc_scaling_factor[1:0] . The CSC mode is used to define the fixed point position of the CSC coefficients which are located after csc_scaling_factor[1:0] in the TX Main Map.

Reference configuration scripts to configure the HDMI TX CSCs are provided with the evaluation software. csc_en , TX2 Main Map, Address 0xF418[7]

This bit is used to enable the color space converter.



Function csc_en

0 

1

Description

CSC disabled

CSC enabled csc_scaling_factor[1:0] , TX2 Main Map, Address 0xF418[6:5]

This signal is used to specify the CSC scaling factor. The CSC scaling factor sets the fixed point position of the CSC coefficients, including a4, b4, c4 and offsets.

Function csc_scaling_factor[1:0] Description

00

01

10 

11

+/- 1.0, -4096 to 4095

+/-2.0, -8192 to 8190

+/- 4.0, -16384 to 16380

+/- 4.0, -16384 to 16380

The characteristic equations for the HDMI TX CSCs are captured in Equation 13 , Equation 14 and Equation 15 .

Out _ A

=



 In _ A

∗

A 1 [ 12 :

4096

0 ]

+

In _ B

∗

A 2 [ 12 :

4096

0 ]

+

In _ C

∗

A 3 [ 12 :

4096

0 ]

+

A 4 [ 12 : 0 ]





∗

2

CSC _ scale

Equation 13: HDMI TX CSC Channel A Output

Out _ B

=



 In _ A

∗

B 1 [ 12 : 0 ]

+

In _ B

∗

B 2 [ 12 : 0 ]

+

In _ C

∗

B 3 [ 12 : 0 ]

4096 4096 4096

Equation 14: HDMI TX CSC Channel B Output

+

B 4 [ 12 : 0 ]





∗

2 CSC _ scale

Out _ C

=



 In _ A

∗

C 1 [ 12 :

4096

0 ]

+

In _ B

∗

C 2 [ 12 :

4096

0 ]

+

In _ C

∗

C 3 [ 12 :

4096

0 ]

Equation 15: HDMI TX CSC Channel C Output

The CSC in each of the HDMI TXs is illustrated in Figure 48 .

+

4096

C 4 [ 12 : 0 ]





∗

2

CSC _ scale

csc_scaling_factor csc_a1 csc_a4

4x

2

In_A

x

csc_a2

+ + ÷ + 2x 1

Out_A

0

In_B

x

csc_a3

In_C

x

Figure 50: HDMI TX CSC


cannot be changed for the HDMI TX CSCs.



Table 20: Default HDMI TX Channel CSC Signal Routing


In_A

In_B

In_C

R

G

B

Cr

Y

Cb


The dynamic range of the CSC is [0…..1] for unipolar signals (Y, R, G, B) or [-0.5…….+0.5] for bipolar signals. Bipolar signals (Pr/Pb) must be offset to mid-range. Equations with a dynamic range larger than 1 need to be scaled appropriately using the

csc_scaling_factor[1:0] control. To achieve a coefficient value of 1.0 for any given coefficient, csc_scaling_factor[1:0] should be set high

and the coefficient should be programmed to a value of 0.5. Otherwise, the largest value would be 4095/4096 = 0.9997. While this value

could be interpreted as 1, it is recommended to use the value of 0.5 and set the csc_scaling_factor[1:0] bits for maximum accuracy.


Table 21: HDMI TX CSC Common Configuration Coefficients

Color Space

Conversion

A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4

HDTV YCbCr

(limited) to

RGB (limited)

HDTV YCbCr

(limited) to

RGB (full)

HDTV YCbCr

(limited) to

SDTV YCbCr

(limited)

HDTV YCbCr

(limited) to

SDTV YCbCr

(full)

HDTV YCbCr

(limited) to

RGB (limited)

HDTV YCbCr

(limited) to

RGB (full)

HDTV YCbCr

(full) to SDTV

YCbCr

(limited)

SDTV YCbCr

(limited) to

RGB (limited)

SDTV YCbCr

(limited) to

RGB (Full)

SDTV YCbCr

(limited) to












Color Space

Conversion


A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4

HDTV YCbCr

(limited)

SDTV YCbCr

(limited) to

SDTV YCbCr

(full)

SDTV YCbCr

(limited) to

RGB (limited)

SDTV YCbCr

(limited) to

RGB (full)

SDTV YCbCr

(full) to HDTV

YCbCr

(limited)


YCbCr

(limited)


(limited)









RGB (full) to

HDTV YCbCr

(limited)

RGB (full) to

SDTV YCbCr

(limited)

RGB (full) to

RGB (limited)

Identity Matrix

(Output =

Input)




0x1 0x0800 0x0000 0x0000 0x0000 0x0000 0x0800 0x0000 0x0000 0x0000 0x0000 0x0800 0x0000

2.2.13.

ADV8003 Silicon Revision

The ADV8003 silicon revision can be determined using rb_chip_id[15:0] .

rb_chip_id[15:0] , IO Map, Address 0x1AD0[7:0]; Address 0x1AD1[7:0];

This signal is used to readback the unique silicon revision ID.

Function rb_chip_id[15:0]

0x6080

0x6081

Description

ES1 silicon

ES2 silicon



2.2.14.

System Configuration

When configuring a system featuring an HDMI Rx and ADV8003, the following sequences for HDMI Tx and encoder are recommended.

For HDMI Tx:

1.

Configure the HDMI Rx (ADV7850).

2.

Wait until the ADV8003 Serial Video Rx achieves lock.

3.

Wait 100 ms.

4.

Configure the VSP.

5.

Wait 1 field/frame.

6.

Configure the HDMI Tx.

For the encoder:

1.

Configure the HDMI Rx (ADV7850).

2.

Wait until the ADV8003 Serial Video Rx achieves lock.

3.

Wait 100 ms.

4.

Configure the VSP.

5.

Wait 250 ms.

6.

Configure the encoder.



3.

VIDEO SIGNAL PROCESSING

The dual scaler variants of the ADV8003 are the following:

• ADV8003KBCZ-8/7


The single scaler variants of the ADV8003 are the following:

• ADV8003KBCZ-8B/7B

• ADV8003KBCZ-7T

References to the SVSP apply only to the dual scaler variants.

3.1.

INTRODUCTION

The primary function of the ADV8003 is high performance video processing, such as motion adaptive de-interlacing, flexible scaling and frame rate conversion, as well as additional video processing such as noise reduction, CUE correction, and aspect ratio/panorama scaling.

This section details the registers used to control the Video Signal Processing (VSP) hardware.

The three constituent sections of the ADV8003 video processor are the PVSP, SVSP, and the PtoI converter. These hardware blocks are completely independent of each other and can be placed in various configurations within the ADV8003.

Access to an external DDR2 memory can be required for the PVSP and SVSP to operate correctly. The PVSP needs access to external

DDR2 memory in every mode except game mode. While the SVSP uses external DDR2 memory for the majority of operations, in the case of down converting from 1080p to 720p (with the same frame rate), no external memory is required and all conversions can take place in internal line memories. The PtoI converter does not need access to external DDR2 memory.

3.2.

PRIMARY VSP

3.2.1.

Introduction to PVSP

Figure 51: ADV8003 PVSP

Figure 51 shows the structure of the PVSP which comprises three sections: the Video Input Module (VIM), the Video Output Module

(VOM), and a controller referred to as the Field Frame Scheduler (FFS).

The VIM is used to capture input video data which it then writes to external DDR2 memory. The VIM is also capable of cropping input video data and performing horizontal downscaling. Before the VIM writes video data to external memory, it first packs the video into the appropriate data formats. In game mode, VIM will send packed 128-bit words to VOM directly instead of writing them into external memory.

The VOM is used to read data from external memory, format this data into 12-bit pixels, perform various functions on this data (scaling,


ADV8003 Hardware Manual de-interlacing, and so on), and then output this video from the PVSP. Many of the PVSP video processing functions are implemented in the VOM. In game mode, the VOM will use data from the VIM instead of reading data from external memory.

The FFS is used to schedule and control the interaction between the VIM, external DDR2 memory, and the VOM. Field/frame buffer scheduling, field polarity management, and FRC management are all implemented in the FFS.

The PVSP can be bypassed by setting pvsp_bypass .

pvsp_bypass , Primary VSP Map, Address 0xE829[7]

This bit is used to bypass the Primary VSP. If this bit is set to 1, the input video to the Primary VSP will be directly bypassed to the output port.

Function pvsp_bypass Description

0 

1

Not bypass Primary VSP

Bypass Primary VSP

The VIM and VOM must be enabled if using the PVSP. This can be done by enabling the pvsp_enable_vim and pvsp_enable_vom bits.

This must be done regardless of the video conversions being performed. pvsp_enable_vim , Primary VSP Map, Address 0xE828[1]

This bit is used to control the Video Input Module (VIM). If this bit is set to 1, the VIM is enabled to write packed input video data into a defined external field/frame buffer. While the Primary VSP is running, if this bit is set to 0, the output video stream will be frozen.

Function pvsp_enable_vim Description

0 

1

Disable VIM

Enable VIM pvsp_enable_vom , Primary VSP Map, Address 0xE828[2]

This bit is used to control the Video Output Module (VOM). If this bit is set to 1, the VOM is enabled to read video data from external memory, process it and then output it.

Function pvsp_enable_vom

0 

1

Description

Disable VOM

Enable VOM

Also, if using the PVSP, the FFS must be enabled using pvsp_enable_ffs . This informs the hardware of the various conversions that must

be performed. Field/frame buffers in external memory are managed by the FFS which decides which field/frame buffer should be used by the VIM to store input video data. The FFS also decides which field/frame buffer should be read back by VOM to process. In the case of interlaced video, the FFS informs the VOM if the input video is the even field or the odd field. The PVSP utilizes a frame repeat/drop mechanism to implement FRC, which is also managed by the FFS. pvsp_enable_ffs , Primary VSP Map, Address 0xE828[0]

This bit is used to control the Field Frame Scheduler (FFS). If this bit is set to 1, the FFS is enabled and the VIM and VOM are scheduled by the FFS, which means the Primary VSP is in operating mode. If this bit is set to 0, the Primary VSP is in idle mode.



Function pvsp_enable_ffs

0 

1

Description

Disable FFS/FRC

Enable FFS/FRC

3.2.1.1.

Autoconfiguration

Each block inside VIM and VOM can be automatically configured to reduce the configuration complexity. Two registers,

pvsp_autocfg_input_vid[7:0]

and pvsp_autocfg_output_vid[7:0] should be set to make the autoconfiguration work.

The 59.94/23.97 Hz timings have the same VID as the corresponding 60/24Hz timing in Figure 24 .

pvsp_autocfg_input_vid[7:0] , Primary VSP Map, Address 0xE881[7:0]

This register is used to set the input timing VIC. If this register is 0, PVSP will use values in registers of pvsp_vin_h, pvsp_vin_v, pvsp_is_i_to_p and pvsp_vin_fr to set input video.

Function pvsp_autocfg_input_vi d[7:0]

Description

0x06 

0xXX

Default: 480i@60

Input timing VID

CEA

Table 22: PVSP Supported Input Video Timing and VID

Video Timing VID

640x480p60

720x480p60

1

2 or 3 or 14 or 15 or 35 or 36

720x240p60

1280x720p60

8 or 9 or 12 or 13

4

1920x1080i60 5

720x480i60 6 or 7 or 10 or 11

1920x1080p

720x576p50

16

17 or 18 or 29 or 30 or 37 or 38

1280x720p50 19

1920x1080i50 20

720x576i50 21 or 22 or 25 or 26

720x288p50 23 or 24 or 27 or 28

1920x1080p50 31

1920x1080p24 32

1920x1080p25 33

1920x1080p30 34

1080i50-even 39

1080i100

720p100

576p100

576i100

40

41

42 or 43

44 or 45

1080i120

720p120

480p120

480i120

576p200

576i200

46

47

48 or 49

50 or 51

52 or 53

54 or 55



Video Timing

480p240

480i240

VID

56 or 57

58 or 59

VESA timing

VGA

SVGA

XGA

WXGA

SXGA

WXGA-2

UXGA

WXGA-3

200

201

202

203

204

205

206

207

WUXGA 208

Note : The PVSP does not support the CEA-861 VIC 60 and CEA-861 VIC 61 formats. pvsp_autocfg_output_vid[7:0] , Primary VSP Map, Address 0xE882[7:0]

This register is used to set the output timing VIC. If this register is 0, PVSP will use values in registers of pvsp_dp_decount, pvsp_dp_hfrontporch, pvsp_dp_hsynctime, pvsp_dp_hbackporch, pvsp_dp_activeline, pvsp_dp_vfrontporch, pvsp_dp_vsynctime, pvsp_dp_vbackporch, pvsp_dp_hpolarity, pvsp_dp_vpolarity, pvsp_vout_fr and pvsp_dp_4kx2k_mode_en to set output video.

Function pvsp_autocfg_output_v id[7:0]

Description

0x10 

0xXX

Default: 1080p@60

Output timing VID

Table 23 lists the supported output video timings and the corresponding VID. 59.94/23.97 Hz timings have the same VID as the

corresponding 60/24 Hz timing in the table.

CEA

Table 23: PVSP Supported Output Video Timing and VID


640x480p60

720x480p60

1

2 or 3 or 14 or 15 or 35 or 36

720(1440)x240p60 8 or 9

720(2880)x240p60 12 or 13

1280x720p60

1920x1080p

4

16

720x576p50

1280x720p50

720x288p50

17 or 18 or 29 or 30 or 37 or 38

19

23 or 24 or 27 or 28

1920x1080p50

1920x1080p24

1920x1080p25

1920x1080p30

720p100

576p100

720p120

480p120

576p200

480p240

4kx2k 30 Hz

31

32

33

34

41

42 or 43

47

48 or 49

52 or 53

56 or 57

112



Video Timing

4kx2k 25 Hz

VID

113

4kx2k 24 Hz 114

4kx2k 24 Hz SMPTE 115

VESA timing

VGA

SVGA

XGA

WXGA

SXGA

WXGA-2

UXGA

WXGA-3

200

201

202

203

204

205

206

207

WUXGA 208

Note : The PVSP does not support the following formats;

• 1280x720p @ 23.97/24 Hz (CEA VIC 60)

• 1280x720p @ 25 Hz (CEA VIC 61)

• 1280x720p @ 29.97/30 Hz (CEA VIC 62)

If overscan, crop or album mode is being used, the required blocks must be configured manually by enabling the corresponding enable

bits, such as pvsp_vim_crop_enable , to enable the VIM crop block.

3.2.1.2.

Customized Input/Output Video Format Configuration

If the input timing is not in the PVSP input format table, customized input format needs to be set manually.

If the input resolution has a variation with regard to standard timing (for example, if pvsp_autocfg_input_vid[7:0] is set to 2, which indicates the input resolution is 720x480, but the actual resolution is 718x478), the user can manually set pvsp_autocfg_input_vid[7:0] to

0 and set the input resolution through the following three registers. pvsp_man_input_res , Primary VSP Map, Address 0xE884[5]

This bit is used to enable the manual configuration of the input resolution.

Function pvsp_man_input_res

0 

1

Description

Disable manual configuration of input resolution

Enable manual configuration of input resolution pvsp_vin_h[10:0] , Primary VSP Map, Address 0xE82E[2:0]; Address 0xE82F[7:0]

This signal is used to set the horizontal resolution of the input video. This register's value will be used while pvsp_man_input_res is 1 or pvsp_autocfg_input_vid is 0.

Function pvsp_vin_h[10:0] Description

0x000 

0xXXX

Default

Horizontal resolution of input video pvsp_vin_v[10:0] , Primary VSP Map, Address 0xE830[2:0]; Address 0xE831[7:0]

This signal is used to set the vertical resolution of the input video. This register's value will be used while pvsp_man_input_res is 1 or pvsp_autocfg_input_vid is 0.



Function pvsp_vin_v[10:0]

0x000 

0xXXX

Description

Default

Vertical resolution of input video

Similarly, if the output timing is not in the PVSP output format table, customized output format needs to be set manually. The detailed configuration instructions are given in the PVSP VOM output port description.

3.2.1.3.

Field/Frame Buffer Number

Depending on the type of conversion that is to take place, a number of buffers must be allocated for the input/output video data.

Depending on the conversion required, this should be set in the pvsp_fieldbuf_num register . pvsp_fieldbuf_num

can be automatically set

by pvsp_autocfg_input_vid[7:0]

and

pvsp_autocfg_output_vid[7:0] .

The pvsp_fieldbuf_num register does not change when crop or album

mode is enabled.

pvsp_fieldbuf_num[2:0] , Primary VSP Map, Address 0xE829[2:0]

Sets the number of field/frame buffers.

Function pvsp_fieldbuf_num[2:0] Description

000  Default

XXX Number of field/frame buffers

3.2.1.4.

Field/Frame Buffer Address and Size

In order to store video data in external memory in the correct size fields, the buffer size of the external DDR2 memory must be programmed by the user. Configuring this manually allows the user to have very flexible control over the external DDR memory.

These programmed field buffers or frame buffers are allocated by setting the following registers: pvsp_fieldbuffer0_addr[31:0] , pvsp_fieldbuffer1_addr[31:0] , pvsp_fieldbuffer2_addr[31:0] , pvsp_fieldbuffer3_addr[31:0] , pvsp_fieldbuffer4_addr[31:0] ,

pvsp_fieldbuffer5_addr[31:0] and pvsp_fieldbuffer6_addr[31:0] .

The value programmed into each of these registers is determined by Equation 16 .

field

_

size

≡

(

active

_

video

1

+

_

width

× active

PVSP_IS_I_

_

video

TO_P

_

height

)

xbytes

_

per

_

pixel

Equation 16: Calculating External Memory Field Buffers where:

• PVSP_IS_I_TO_P indicates whether the input timing is interlaced or progressive (interlaced = 1, progressive = 0)

• bytes_per_pixel

indicates the number of bytes required to store each pixel (refer to Table 26 for more details on the number of

bytes required per pixel)

For example, for an input video resolution of 720p, Equation 16 would yield the following field size:

Field_size = ((720)x(1280))x4 = 3686400

The following values would then need to be programmed to the above registers:

pvsp_fieldbuffer0_addr[31:0] = 0 pvsp_fieldbuffer1_addr[31:0] = 38400 (3686400 in hex)



pvsp_fieldbuffer2_addr[31:0] = 70800 (7372800 in hex)

Note: The default value of the field/frame buffer is set for a 1080p input. If the maximum supported video is 1080p, there is no need to change the setting of the field/frame buffer. It is recommended to leave the setting of the buffer number and the buffer size unchanged. pvsp_fieldbuffer0_addr[31:0] , Primary VSP Map, Address 0xE800[7:0]; Address 0xE801[7:0]; Address 0xE802[7:0]; Address 0xE803[7:0]

This signal is used to set the start address of field/frame buffer 0. The software should arrange memory space properly, avoiding conflict between different buffers.

Function pvsp_fieldbuffer0_addr

[31:0]

Description

0x004F1A00 

0xXXXXXXXX

Default

Start address of field/frame buffer 0 pvsp_fieldbuffer1_addr[31:0] , Primary VSP Map, Address 0xE804[7:0]; Address 0xE805[7:0]; Address 0xE806[7:0]; Address 0xE807[7:0]



[31:0]

Description

0x00CDAA00 

0xXXXXXXXX

Default

Start address of field/frame buffer 1 pvsp_fieldbuffer2_addr[31:0] , Primary VSP Map, Address 0xE808[7:0]; Address 0xE809[7:0]; Address 0xE80A[7:0]; Address 0xE80B[7:0]



[31:0]

0x014C3A00 

0xXXXXXXXX

Description

Default

Start address of field/frame buffer 2 pvsp_fieldbuffer3_addr[31:0] , Primary VSP Map, Address 0xE80C[7:0]; Address 0xE80D[7:0]; Address 0xE80E[7:0]; Address 0xE80F[7:0]



[31:0]

Description

0x01CACA00 

0xXXXXXXXX

Default

Start address of field/frame buffer 3 pvsp_fieldbuffer4_addr[31:0] , Primary VSP Map, Address 0xE810[7:0]; Address 0xE811[7:0]; Address 0xE812[7:0]; Address 0xE813[7:0]





[31:0]

0x02495A00 

0xXXXXXXXX

Description

Default

Start address of field/frame buffer 4 pvsp_fieldbuffer5_addr[31:0] , Primary VSP Map, Address 0xE814[7:0]; Address 0xE815[7:0]; Address 0xE816[7:0]; Address

0xE817[7:0]



[31:0]

Description

0x02C7EA00 

0xXXXXXXXX

Default

Start address of field/frame buffer 5 pvsp_fieldbuffer6_addr[31:0] , Primary VSP Map, Address 0xE889[7:0]; Address 0xE88A[7:0]; Address 0xE88B[7:0]; Address 0xE88C[7:0]



[31:0]

Description

0x03073200 

0xXXXXXXXX

Default

Start address of field/frame buffer 6

3.2.1.5.

Frame Latency

Different resolutions have different frame latencies, depending on the timing combination to and from the PVSP. This is due to the

increased processing required in converting and scaling video data. Table 24 lists the frame latencies in normal mode for various

resolutions.

Input

Frame rate

50 Hz

Output

Table 24: Frame Latency in Normal Mode

Frame Rate 50 Hz 59.94/60 Hz

Timing

576i

1080i

576p/720p/1080 p

1.1~2.3

1, 2 1.1~2.3

23.97/24 Hz 25/30 Hz

480p/720p/1080p 720p/1080p

/4kx2k

1.1~2.4

720p/1080p

/4kx2k

1.1~2.4

576p

720p

1080p

0.1~1.3 0.1~1.3 0.1~1.4 0.1~1.4

59.94/60 Hz 480i

1080i

480p

720p

1080p

1.1~2.3

0.1~1.3

1.1~2.3

0.1~1.3

0.1~3.4

3

0.1~3.4

4

0.1~1.4

0.1~1.4



Input

Frame rate

23.97/24/25/30

Hz

Output Frame Rate 50 Hz

Timing 576p/720p/1080 p

720/1080p 0.1~0.8

59.94/60 Hz 23.97/24 Hz 25/30 Hz

480p/720p/1080p 720p/1080p

0.1~0.8

/4kx2k

0.1~1.3

720p/1080p

/4kx2k

0.1~1.3

1.

x.x means x.x times the input video field/frame

2.

A~B means frame latency is not a fixed value, it varies between A and B

3.

If cadence detection is disabled, this value should be 0.3~1.4 with setting pvsp_frc_change_phase_en to 0, otherwise is 0.3~3.4

4.

If progressive cadence detection is disabled, this value should be 0.3~1.4 with setting pvsp_frc_change_phase_en to 0, otherwise, it is 0.3~3.4

When crop or album mode is enabled, frame latency will be different from what is listed in Table 24 . In this case, the user can use the

following methods to measure frame latency:

pvsp_rb_frame_latency[2:0] and pvsp_rb_hsync_latency[11:0] are read only registers. Their values are real-time frame and HSync latency

between input and output video.

Frame latency may vary within a range; the pvsp_rb_max_latency[14:0] readback register indicates the maximum frame latency, while pvsp_rb_min_latency[14:0] indicates the minimum frame latency. If

pvsp_frc_latency_measure_en is set to 0,

pvsp_rb_max_latency[14:0] and pvsp_rb_min_latency[14:0] are cleared.

If asserting

pvsp_frc_latency_measure_en , the PVSP will monitor the values in pvsp_rb_frame_latency[2:0] and pvsp_rb_hsync_latency[11:0]

, then record their maximum and minimum values in pvsp_rb_max_latency[14:0] and pvsp_rb_min_latency[14:0] . Both of these signals are 15 bits wide – the highest 3 bits are the frame latency and the lowest 12 bits are the

HSync latency. Note that it will take several seconds for PVSP to find the maximum and minimum frame/HSync latency.

In a normal case (not game mode), the PVSP’s input video and output video latency are consistent. pvsp_frc_latency_measure_en , Primary VSP Map, Address 0xE8F0[6]

This bit is used to enable frame latency measuring. The results are recorded in pvsp_rb_max_latency and pvsp_rb_min_latency.

Function pvsp_frc_latency_meas ure_en

Description

0 

1

Disable frame latency measuring

Enable frame latency measuring pvsp_rb_frame_latency[2:0] , Primary VSP Map, Address 0xE870[6:4] (Read Only)

This signal is used to indicate the real time VSync latency.

Function pvsp_rb_frame_latency

[2:0]

0xXXX

Description

Number of frame latency pvsp_rb_hsync_latency[11:0] , Primary VSP Map, Address 0xE875[7:0]; Address 0xE876[7:4] (Read Only)

This signal is used to indicate the real time HSync latency.



Function pvsp_rb_hsync_latency

[11:0]

0xXXX

Description

Number of HSync latency pvsp_rb_max_latency[14:0] , Primary VSP Map, Address 0xE8F2[7:0]; Address 0xE8F3[7:1] (Read Only)

This signal is used to record the maximum frame latency.

Function pvsp_rb_max_latency[1

4:0]

0xXXX

Description

Maximum of frame latency pvsp_rb_min_latency[14:0] , Primary VSP Map, Address 0xE8F4[7:0]; Address 0xE8F5[7:1] (Read Only)

This is signal is used to record the minimum frame latency.

Function pvsp_rb_min_latency[1

4:0]

Description

0xXXX Minimum of frame latency

3.2.1.6.

Game Mode

Frame latency should be as small as possible for gaming applications. PVSP supports a game mode, which has nearly zero frame latency

(latency less than 5 lines).

To enable the game mode of PVSP, pvsp_bypass_ddr_mode should be asserted.

pvsp_bypass_ddr_mode , Primary VSP Map, Address 0xE84D[5]

This bit is used to enable game mode for the Primary VSP.

Function pvsp_bypass_ddr_mod e

Description

0 

1

Normal mode

Game mode

External memory is not used in game mode. Intra-field interpolation is used for interlaced input. Mosquito/block noise reduction and sharpness are supported in game mode, both for interlaced input and progressive input.

In game mode, the following functions are not supported:

• Frame rate change

• Motion adaptive de-interlacing (autodisabled)

• Cadence detection (autodisabled)

• Random noise reduction (autodisabled)

• CUE correction (autodisabled)

• Crop

• Album mode

The functions listed as autodisabled do not need to be manually disabled in game mode – ADV8003 will automatically disable them when game mode is enabled. Functions which are not listed as autodisabled must be manually disabled before game mode is enabled.



3.2.1.7.

Low Latency Mode

Game mode has a very small frame latency but some processing functions cannot be supported in this mode. ADV8003 provides another mode, low latency mode, which can support frame rate change, scaling, crop and album mode.

To enable low latency mode, pvsp_frc_low_latency_mode should be set to 1.

Frame latency in low latency mode is listed in Table 25 , which shows the maximum frame latency is 1.4 x frame.

Input

Frame rate

50 Hz

Output

Table 25: Frame Latency in Low Latency Mode

Frame Rate 50 Hz 59.94/60 Hz 23.97/24 Hz 25/30 Hz

Timing

576i

1080i

576p/720p/1080 p

0.3~1.3

480p/720p/1080p 720p/1080p

0.3~1.3

/4kx2k

0.3~1.4

720p/1080p

/4kx2k

0.3~1.4

576p

720p

1080p

0.3~1.3 0.3~1.3 0.3~1.4 0.3~1.4

59.94/60 Hz 480i

1080i

480p

720p

1080p

0.3~1.3

0.3~1.3

0.3~1.3

0.3~1.3

0.3~1.4

0.3~1.4

0.3~1.4

0.3~1.4

23.97/24/25/30

Hz

720/1080p 0.3~0.8 0.3~0.8 0.3~1.3 0.3~1.3

The following functions are not supported In low latency mode:

• Motion adaptive de-interlacing (autodisabled)

• Cadence detection (autodisabled)

• Random noise reduction (autodisabled)

• CUE correction (autodisabled) pvsp_frc_low_latency_mode , Primary VSP Map, Address 0xE84D[2]

This bit is used to enable low latency mode.

Function pvsp_frc_low_latency_ mode

Description

0 

1

Disable low latency mode

Enable low latency mode



3.2.1.8.

Freezing Output Video

It is possible to freeze the output video from the PVSP by disabling the VIM. This can be achieved by setting pvsp_enable_vim to 0.

3.2.1.9.

Progressive Cadence Detection

The ADV8003 PVSP supports multiple different types of cadence detection. Progressive cadence detection is another feature supported by

ADV8003 when the input video is 60 Hz and the output video is 24 Hz. An example of progressive cadence detection would involve the

ADV8003 detecting a pull-down ratio of 3:2 for 60 Hz video and reconverting this to its original film content at 24 Hz. This would allow the video to be output at 24 Hz and, therefore, be displayed at the highest image quality possible.

Conversions from slower to higher frame rates are achieved by repeating certain frames. Similarly, conversions from higher to lower frame rates are achieved by dropping some frames. Care has to be taken with repeating and dropping frames so that the quality of the video is

not impacted. A simple example of frame rate conversion is outlined in Figure 52 . This example involves converting the input video at a

rate of 24 fps to 30 fps. These two frame rates have a ratio of 4:5; for every 4 frames of input video, there must be 5 frames of output video.

This example uses a cadence detection of 3:2 pull-down which means that for every second frame of video data, an extra field of video information will be displayed.

A B C D

A A B B C C D D D

: : :

Figure 52: 2:3 Frame Rate Conversion

Progressive cadence detection can be enabled by setting register pcadence_enable to 1.

pcadence_enable , Primary VSP Map, Address 0xE84D[1]

This bit is used to enable progressive cadence detection.

Function pcadence_enable Description

0

1 

Disable progressive cadence detection

Enable progressive cadence detection



3.2.2.

PVSP Video Input Module

Figure 53: PVSP Video Input Module

3.2.2.1.

VIM Cropper

The VIM cropper block is used to define a sub window within the given input resolution. This cropped image becomes the video which is processed by the PVSP. The following registers are used to define this sub window:

•

pvsp_vim_crop_enable

•

pvsp_vim_crop_h_start[10:0]

•

pvsp_vim_crop_v_start[10:0]

•

pvsp_vim_crop_width[10:0]

•

pvsp_vim_crop_height[10:0]

To enable cropper block in VIM, pvsp_vim_crop_enable should be asserted.

pvsp_vim_crop_enable , Primary VSP Map, Address 0xE883[6]

This bit is used to enable the VIM crop.

Function pvsp_vim_crop_enable Description

0 

1

Disable VIM crop

Enable VIM crop

Figure 54 shows the correlation between this cropped image and the input video.

Rev. B, August 2013

Figure 54: VIM Crop Dimensions

156

ADV8003 Hardware Manual pvsp_vim_crop_h_start[10:0] , Primary VSP Map, Address 0xE832[2:0]; Address 0xE833[7:0]

This signal is used to set the horizontal start position of the VIM cropper.

Function pvsp_vim_crop_h_start

[10:0]

Description

0x000 

0xXXX

Default

Horizontal start position of VIM cropper input pvsp_vim_crop_v_start[10:0] , Primary VSP Map, Address 0xE834[2:0]; Address 0xE835[7:0]

This signal is used to set the vertical start position of the VIM cropper.

Function pvsp_vim_crop_v_start[

10:0]

Description

0x000 

0xXXX

Default

Vertical start position of VIM cropper input pvsp_vim_crop_width[10:0] , Primary VSP Map, Address 0xE836[2:0]; Address 0xE837[7:0]

This signal is used to set the input width of the VIM cropper.

Function pvsp_vim_crop_width[1

0:0]

Description

0x000 

0xXXX

Default

Width of VIM cropper input pvsp_vim_crop_height[10:0] , Primary VSP Map, Address 0xE838[2:0]; Address 0xE839[7:0]

This signal is used to set the input height of the VIM cropper.

Function pvsp_vim_crop_height[

10:0]

Description

0x000 

0xXXX

Default

Height of VIM cropper input

Note: The following limitations apply to the values that can be programmed in these registers:

•

0 <= pvsp_vim_crop_h_start[10:0] <= (INPUT VIDEO HORIZONTAL RESOLUTION – 1)

•

0 <= pvsp_vim_crop_v_start[10:0] <= (INPUT VIDEO VERTICAL RESOLUTION – 1)

•

( pvsp_vim_crop_h_start[10:0] + pvsp_vim_crop_width[10:0] ) <= INPUT VIDEO HORIZONTAL ACTIVE PIXELS

•

( pvsp_vim_crop_v_start[10:0] + pvsp_vim_crop_height[10:0] ) <= INPUT VIDEO VERTICAL ACTIVE PIXELS



3.2.2.2.

Horizontal Down Scaler

Although the VOM has both horizontal and vertical scalers, there is also a horizontal down scaler in the VIM. The purpose of the VIM down scaler is to save external memory bandwidth by doing horizontal downscaling before writing video data into the external memory to save memory bandwidth.

The down scaler in the VIM should only be enabled when horizontal downscaling is needed, which means that the number of horizontal output active pixels should be less than the number of horizontal input active pixels. When album mode is enabled, the specified active output video width should be the album width.

If the horizontal resolution of the PVSP output timing is less than the input timing, the horizontal down scaler can be enabled to reduce

the load on the external DDR2 memory. This horizontal down scaler input resolution is defined by the pvsp_vim_crop_width[10:0]

register and the output resolution is defined by the pvsp_vim_d_scal_out_width[10:0] register. To enable the horizontal down scaler, pvsp_vim_d_scal_enable should be set to 1.

pvsp_vim_d_scal_enable , Primary VSP Map, Address 0xE883[5]

This bit is used to enable the VIM down scaler.

Function pvsp_vim_d_scal_enabl e

Description

0 

1

Disable VIM down scaler

Enable VIM down scaler pvsp_vim_d_scal_out_width[10:0] , Primary VSP Map, Address 0xE83A[2:0]; Address 0xE83B[7:0]

This signal is used to set the output video width of the down-scaling scaler in the VIM. The input video width is set by register pvsp_vim_crop_width. If VIM crop is not enabled, pvsp_vim_crop_width is auto configured by pvsp_autocfg_input_vid, which is the same with input video's horizontal resolution.

Function pvsp_vim_d_scal_out_ width[10:0]

Description

0x000 

0xXXX

Default

Output width of VIM scalar

3.2.2.3.

Scaler Interpolation Mode

This section describes the method for scaling the input video data. The purpose of the scaler is to allow different input formats to be displayed on a screen with a fixed resolution. The VIM scaler is usually used for downscaling, for example, 1080p to be downscaled to a lower definition format such as 480p. Different scaling interpolation modes will affect scaler performance. The options for video scaling

modes are described below and are chosen using pvsp_vim_scal_type[1:0] .

Proprietary ADI Algorithm

This is a custom algorithm developed by ADI which allows improved performance in the scaling of the input video. This can reduce many common artifacts when scaling video data such as:

• Saw tooth – otherwise known as ‘jaggies’, this is an artifact that occurs when an image is zoomed in and is one of the most important criteria when evaluating scaling performance.

• Edge blurring – when zooming in, most high frequency information is lost, resulting in edges becoming blurred. The proprietary ADI algorithm keeps the edge region sharp by retaining the high frequency information.

• Ringing – also known as the Gibbs phenomenon, can be found on video due to a reduction in high frequency information. The proprietary ADI algorithm helps with the reduction of such artifacts.



Sharp/Smooth

Both the sharp/smooth options for scaler interpolation are versions of the proprietary ADI algorithm. The sharp and smooth versions allow for limited customization of the scaler function. This function can be set depending on the user preference.

Bilinear

The bilinear option uses an averaging method within a 2x2 pixel array to increase the size of the input frame. This is a cruder method of scaling than the default proprietary ADI Algorithm. In most cases, the scaler should be left at the default setting. pvsp_vim_scal_type[1:0] , Primary VSP Map, Address 0xE8E5[7:6]

This signal is used to set the VIM scaling algorithm. For up-scaling, the proprietary ADI algorithm is recommended; whereas for downscaling, the sharp setting is recommended.

Function pvsp_vim_scal_type[1:0

]

Description

00

01

10

11 


Sharp

Smooth

Bilinear

3.2.2.4.

Scaler Controls

The following register is used in the control of the VIM scaling function and should be tailored according to user requirements. pvsp_vim_scal_overshoot_ctrl[11:0] , Primary VSP Map, Address 0xE8E9[7:0]; Address 0xE8EA[7:4]

This bit is used to control the overshoot in the scaling of input video. If set to a value larger than the default setting, more overshoot is allowed.

Function pvsp_vim_scal_oversho ot_ctrl[11:0]

Description

0x080  Default

3.2.2.5.

Pixel Packer

At the back end of the VIM, the pixel packer converts input video to word packets suitable for writing to external memory. Refer to Figure

53 for more details on where the pixel packer is located in the hardware. Depending on the format of the input video, there are four

different packing formats:

• 12-bit 4:4:4 YCbCr




There is a trade off in the number of bits that can be stored. A higher number of bits means the video stored will be stored at a higher quality, however, this will reduce the available DDR2 memory bandwidth for other functions such as OSD read/write.

The data format can be set by the pvsp_ex_mem_data_format[1:0] register. This register can be set at any time, but it may take some time

(not more than 300 ms) to become valid. This delay is related to the ADV8003 taking control of the memory format change to avoid the display of garbage information. This information is important when calculating the field/frame buffer sizes, as explained in Section

3.2.1.


ADV8003 Hardware Manual pvsp_ex_mem_data_format[1:0] , Primary VSP Map, Address 0xE829[4:3]

This signal is used to set the data format in external memory.

Function pvsp_ex_mem_data_for mat[1:0]

Description

00 

01

10

11

YCbCr-12b-10b-10b

YCbCr-8b-8b-8b

YCbCr-4:2:4-12b

YCbCr-4:2:2-8b

Table 26 indicates the number of bytes required when storing a particular type of video data.

1

2

Table 26: Bytes per Pixel pvsp_ex_mem_data_format Format in Memory Bytes per Pixel

0 12 bit 4:4:4 YCbCr 4

3

8 bit 4:4:4 YCbCr

12 bit 4:2:2 YCbCr

8 bit 4:2:2 YCbCr

3

4

2

3.2.3.

PVSP Video Output Module

Figure 55 shows the structure of the PVSP VOM. The direction arrow inside Figure 55 does not capture the real processing order inside

the VOM but gives a clear overview of each processing block.

Rev. B, August 2013

Figure 55: PVSP Video Output Module

The VOM has the following main features:

• Pixel unpacker: this module reads the field/frame from external memory and unpacks memory words to video pixel information

• VOM cropper: crops the image read from external memory

• De-interlacer: converts interlaced video to progressive video

• CUE correction: filtering for Color Upsampling Error

• Noise reduction: removes random, mosquito, and block noise

• Detail and edge sharpness enhancement

160


• Scaler: scales video to target resolution

• Output port: generates output timing and output video

Register update protection is provided in the ADV8003. Refer to

Section 3.4 for more details regarding how to update the various VSP

registers. pvsp_lock_vom , Primary VSP Map, Address 0xE828[3]

This bit is used to lock the Video Output Module (VOM). If the Primary VSP is running and this bit is set to 1, the VOM will be locked to a current register setting to display the last frame. The Primary VSP registers can be configured safely in this state. All new register settings will be updated after this bit is set back to 0.

Function pvsp_lock_vom

0 

1

Description

Unlock VOM

Lock VOM

Note:

This register should be used only as part of the gentle reboot protocol. Refer to Section 3.4.3 for more details.

pvsp_update_vom , Primary VSP Map, Address 0xE828[4]

This bit is used to control the updating of the VOM. Registers in the VOM can be updated only when pvsp_update_vom is asserted. To modify registers in the VOM, pvsp_update_vom should be de-asserted. The registers can then be modified. pvsp_update_vom should then be asserted to let the VOM use the updated register value in the next frame. This procedure will guarantee the correctness of the

VOM configuration.

Function pvsp_update_vom Description

0

1 

Do not update VOM

Update VOM

Note:

Refer to Section 3.4 for more details on configuring the PVSP registers.

3.2.3.1.

Pixel Unpacker

The pixel unpacker in the VOM is very similar to that in the VIM. It is used to convert external memory words into video pixel (YCbCr) data. Pixels in external memory have the following four different data formats (the same as those set by the VIM). The VOM pixel unpacker is configured in the same way as the VIM pixel unpacker.





Data format details are described in pvsp_ex_mem_data_format[1:0] .

3.2.3.2.

VOM Cropper

The VOM cropper is similar to the VIM cropper with the exception that it uses the VOM set protocol while the VIM cropper uses the

gentle reboot protocol (refer to Section 3.4). Using the VIM cropper can reduce the external memory bandwidth required for scaling in

cases where bandwidth is a concern. If not, the VOM cropper should be used. The following registers are used to configure the VOM cropper:

•

pvsp_di_crop_enable

•

pvsp_di_crop_h_start[10:0]


•

pvsp_di_crop_v_start[10:0]

•

pvsp_di_crop_width[10:0]

•

pvsp_di_crop_height[10:0]

To enable cropper in VOM, pvsp_di_crop_enable

should be asserted. pvsp_di_crop_enable , Primary VSP Map, Address 0xE883[4]

This bit is used to enable the VOM crop.

Function pvsp_di_crop_enable Description

0 

1

Disable VOM crop

Enable VOM crop

Figure 56 shows the function of the VOM cropper.

Figure 56: VOM Crop Dimensions pvsp_di_crop_h_start[10:0] , Primary VSP Map, Address 0xE83C[2:0]; Address 0xE83D[7:0]

This signal is used to set the horizontal start position of the VOM cropper.

Function pvsp_di_crop_h_start[1

0:0]

Description

0x000 

0xXXX

Default

Horizontal start position of VOM cropper input pvsp_di_crop_v_start[10:0] , Primary VSP Map, Address 0xE83E[2:0]; Address 0xE83F[7:0]

This signal is used to set the vertical start position of the VOM cropper.

Function pvsp_di_crop_v_start[1

0:0]

Description

0x000 

0xXXX

Default

Vertical start position of VOM cropper input



ADV8003 Hardware Manual pvsp_di_crop_width[10:0] , Primary VSP Map, Address 0xE840[2:0]; Address 0xE841[7:0]

This signal is used to set the width of the VOM cropper.

Function pvsp_di_crop_width[10

:0]

Description

0x000 

0xXXX

Default

Width of VOM cropper input pvsp_di_crop_height[10:0] , Primary VSP Map, Address 0xE842[2:0]; Address 0xE843[7:0]

This signal is used to set the height of the VOM cropper.

Function pvsp_di_crop_height[1

0:0]

Description

0x000 

0xXXX

Default

Height of VOM cropper input

Note: The following restrictions apply to the values to which these registers can be set:

0 <= pvsp_di_crop_h_start[10:0] <= (HORIZONTAL RESOLUTION OUTPUT BY VIM – 1)

0 <= pvsp_di_crop_v_start[10:0] <= (VERTICAL RESOLUTION OUTPUT BY VIM – 1)

( pvsp_di_crop_h_start[10:0]

+ pvsp_di_crop_width[10:0] ) <= HORIZONTAL RESOLUTION OUTPUT BY VIM

( pvsp_di_crop_v_start[10:0] +

pvsp_di_crop_height[10:0] ) <= VERTICAL RESOLUTION OUTPUT BY VIM

3.2.3.3.

Motion Detection

The ADV8003 de-interlacer is used to convert interlaced video to progressive video. The PVSP has an extremely high quality de-interlacer algorithm which achieves excellent quality interlaced to progressive conversion. The algorithm uses motion adaptive de-interlacing technology, which includes motion detection, cadence detection, low angle detection and interpolation.

Motion detection extracts the motion information of each pixel. Based on this information, the ADV8003 chooses the most suitable form of de-interlacing. For static pixels (that is, pixels where no motion is deemed to have occurred), inter field interpolation is performed. For pixels where motion is detected, intra-field interpolation is performed. Motion detection technology is the essence of de-interlacing, so if a static pixel is detected as motion by mistake, vertical detail is lost. In contrast, if motion is detected as static by mistake, combing artifact occurs.

In order to support motion detection for interlaced inputs, two buffers in external memory are needed to store motion information. Their

addresses are defined in the pvsp_motionbuf0_addr[31:0]

and pvsp_motionbuf1_addr[31:0] registers. The size of each buffer should be

equal to the MOTION_BUF_SIZE, which can be calculated from Equation 17 .

MOTION

_

BUF

_

SIZE

(

byte

)

≡

(

active

_

input

_

video

_

width

×

4

active

_

input

_

video

_

height

)

Equation 17: Calculating Interlaced Buffers pvsp_motionbuf0_addr[31:0] , Primary VSP Map, Address 0xE818[7:0]; Address 0xE819[7:0]; Address 0xE81A[7:0]; Address 0xE81B[7:0]

This signal is used to set the start address of motion information buffer 0. Motion buffers are needed only when motion adaptive deinterlacing is enabled for interlaced input.



Function pvsp_motionbuf0_addr

[31:0]

0x00000000 

0xXXXXXXXX

Description

Default

Start address of motion buffer 0 pvsp_motionbuf1_addr[31:0] , Primary VSP Map, Address 0xE81C[7:0]; Address 0xE81D[7:0]; Address 0xE81E[7:0]; Address 0xE81F[7:0]

This signal is used to set the start address of motion information buffer 1. Motion buffers are needed only when motion adaptive deinterlacing is enabled for interlaced input.

Function pvsp_motionbuf1_addr

[31:0]

Description

0x0007E900 

0xXXXXXXXX

Default

Start address of motion buffer 1

3.2.3.4.

Low Angle De-interlacing

The ultra low angle de-interlacing interpolation algorithm (ULAI) developed by ADI performs intra field interpolation for the deinterlacing function. It is capable of determining the correct direction by examining several different directions and interpolating missing pixels based on this information. This results in higher quality low angle interpolation and reduces the effect of jaggies.

The ultra low angle interpolation function is only used for converting from interlaced to progressive formats. It can be enabled or disabled

by asserting or de-asserting register di_ulai_enable .

di_ulai_enable , Primary VSP Map, Address 0xE84C[3]

This bit is used to enable the ultra low angle de-interlacing algorithm (ULAI).

Function di_ulai_enable Description

0

1 

Disable ULAI

Enable ULAI

3.2.3.5.

Cadence Detection

The ADV8003 cadence detection can handle multiple different types of cadences, typically introduced when content originated as film

format but was converted into interlaced format for broadcast. Examples of such conversion can be seen in Figure 52 . The PVSP is able to

detect arbitrary cadences and even unknown cadence modes, with per pixel correction for combing artifacts.

There are several features of cadence detection, including the reliable detection of 2:2 cadences for PAL video and the detection of poor editing techniques often found in films converted to video standards (this may introduce artifacts). These artifacts are caused by multiple cadences in the same source as well as fast switching from film to video or between different cadences.

For an interlaced video input, cadence detection can be enabled or disabled by asserting or de-asserting di_cadence_enable . For

progressive video input, cadence detection can be enabled or disabled by asserting or de-asserting pcadence_enable .

di_cadence_enable , Primary VSP Map, Address 0xE84C[2]

This bit is used to enable cadence detection.



Function di_cadence_enable

0

1 

Description

Disable cadence detection

Enable cadence detection

The PVSP supports the following cadence types:

• 2:2

• 2:2:2:4

• 3:2

• 2:3:3:2:2

• 2:3:3:2

• 3:2:3:2:2

• 3:3

• 4:4

• 5:5

• 6:4

• 8:7

Each of these cadence types can be disabled by setting the corresponding bit in di_fd_disabled_cadence[10:0] to 1.

For conversion of 60 Hz interlaced and progressive input timing to 24 Hz progressive timing, pvsp_frc_change_phase_en should be asserted. For all other cases, pvsp_frc_change_phase_en should be disabled when using 1 external DDR2 memory.

pvsp_frc_change_phase_en , Primary VSP Map, Address 0xE84E[4]

This bit is used to lock the phase change for cadence detection.

Function pvsp_frc_change_phase

_en

Description

0

1 

Disable

Enable di_fd_disabled_cadence[10:0] , Primary VSP Map, Address 0xE8FA[7:0]; Address 0xE8FB[7:5]

This signal is used to disable corresponding cadence detection.

Function di_fd_disabled_cadenc e[10:0]

Description

0x000  Default

Table 27: Corresponding Bit for Each Cadence Type

Bit Disabled Cadence

0xE8FB[5] 2:2

0xE8FB[6] 2:2:2:4

0xE8FB[7] 3:2

0xE8FA[0] 2:3:3:2:2

0xE8FA[1] 2:3:3:2

0xE8FA[2] 3:2:3:2:2

0xE8FA[3] 3:3

0xE8FA[4] 4:4



Bit Disabled Cadence

0xE8FA[5] 5:5

0xE8FA[6] 6:4

0xE8FA[7] 8:7

3.2.3.6.

CUE Correction

Color Upsampling Error (CUE) correction is implemented using a filter which removes the jagged edges caused by the artifacts introduced by the incorrect upsampling of MPEG 2 video data in 4:2:0 format to the 4:2:2/4:4:4 formats supported by DVD players.

The CUE correction function can be enabled or disabled by di_cue_enable .

di_cue_enable , Primary VSP Map, Address 0xE84D[0]

This bit is used to enable CUE correction.

Function di_cue_enable Description

0

1 

Disable CUE correction

Enable CUE correction

3.2.3.7.

Random Noise Reduction

There are several noise reduction algorithms in the ADV8003 that help with the reduction of common sources of video noise. The random noise reduction (RNR) block reduces the random noise which may be introduced in analog broadcasting or capturing. It employs a temporal recursive algorithm to stabilize the static regions while just processing the luma channel. Users can configure the register

parameters to adjust the algorithm according to their preference. The amount level of RNR can be configured using di_rnr_level[1:0] .

RNR supports both interlaced and progressive input. It can be enabled or disabled using di_rnr_enable .

di_rnr_enable , Primary VSP Map, Address 0xE84C[4]

This bit is used to enable random noise reduction (RNR).

Function di_rnr_enable

0 

1

Description

Disable RNR

Enable RNR di_rnr_level[1:0] , Primary VSP Map, Address 0xE84F[1:0]

This signal sets the RNR level.

Function di_rnr_level[1:0]

00

01

10 

11

Description

N/A

Low

Middle

High

For the RNR feature to operate, two buffers in external memory must be allocated to store video information which will be used for noise

reduction purposes. The addresses of these two buffers can be set in the pvsp_rnrbuf0_addr[31:0] and pvsp_rnrbuf1_addr[31:0] registers.

The size of each buffer should be larger than RNR_BUF_SIZE, which can be calculated as shown in Equation 18 .



RNR

_

BUF

_

SIZE

(

byte

)

≡

active

_

input

_

video

_

width

×

active

_

input

_

video

_

height

Equation 18: Calculating RNR Buffers

Note : Using RNR will use external memory bandwidth which may impact on other features such as OSD image storage as well as deinterlacing. pvsp_rnrbuf0_addr[31:0] , Primary VSP Map, Address 0xE820[7:0]; Address 0xE821[7:0]; Address 0xE822[7:0]; Address 0xE823[7:0]

Sets the start address of random noise reduction information buffer 0. RNR buffers are needed only when random noise reduction is enabled.

Function pvsp_rnrbuf0_addr[31:

0]

Description

0x000FD200 

0xXXXXXXXX

Default

Start address of RNR buffer 0 pvsp_rnrbuf1_addr[31:0] , Primary VSP Map, Address 0xE824[7:0]; Address 0xE825[7:0]; Address 0xE826[7:0]; Address 0xE827[7:0]

Sets the start address of random noise reduction information buffer 1. RNR buffers are needed only when random noise reduction is enabled.

Function pvsp_rnrbuf1_addr[31:

0]

Description

0x002F7600 

0xXXXXXXXX

Default

Start address of RNR buffer 1

3.2.3.8.

Mosquito Noise Reduction

The second type of noise reduction algorithm implemented in the ADV8003 is the mosquito noise reduction (MNR). The MNR block selectively removes ringing artifacts introduced into highly compressed (MPEG) video data. For the best results, this block should be enabled when the input video is not being scaled, due to the fact that it is easier to identify and remove compressed artifacts at lower resolutions.

MNR can support both interlaced and progressive input video. It can be enabled or disabled by di_mnr_enable . As with the RNR block, a certain amount of control is provided to the user. This can be controlled using di_mnr_level[1:0] .

di_mnr_enable , Primary VSP Map, Address 0xE84C[5]

This bit is used to enable mosquito noise reduction (MNR).

Function di_mnr_enable

0 

Description

Disable MNR

1 Enable MNR di_mnr_level[1:0] , Primary VSP Map, Address 0xE84F[3:2]

This signal sets the MNR level.



Function di_mnr_level[1:0]

00

01

10 

11

Description

N/A

Low

Middle

High

To get better image performance, register di_mnr_th_min[3:0] can be used to set the MNR level.

di_mnr_th_min[3:0] , Primary VSP Map 2, Address 0xE917[7:4]

This signal is used to set the strength of the mosquito noise reduction (MNR). The larger the value, the stronger the MNR noise reduction.

Function di_mnr_th_min[3:0] Description

0010 

0110

Normal strength MNR

High strength MNR

3.2.3.9.

Block Noise Reduction

The block noise reduction (BNR) algorithm removes ‘blocky’ artifacts introduced into highly compressed video such as MPEG2 encoded video. For the best results, this function should be enabled when the input video is not scaled. The BNR has excellent performance for high level block artifact patterns, and it has smart block position detection.

BNR supports both interlaced and progressive input. It can be enabled or disabled using di_bnr_enable . The bnr level can be controlled by

setting di_bnr_detect_scale_line[3:0] , di_bnr_disable_local_detect ,

di_bnr_edge_offset[7:0] ,

di_bnr_global_strength_gain[3:0] , di_bnr_scale_global_hori[2:0] and di_bnr_scale_global_vert[2:0] . The corresponding value for different reduction level is given in

Table 28 .

Table 28: Corresponding Value for Block Noise Reduction Level

Register Name High Middle Low

di_bnr_detect_scale_line[3:0] di_bnr_disable_local_detect

9

0

7

1

7

1

64 32

di_bnr_edge_offset[7:0]

96

di_bnr_global_strength_gain[3:0]

12

di_bnr_scale_global_hori[2:0]

6

8

5

7

5

6 5 5

di_bnr_scale_global_vert[2:0]

di_bnr_enable , Primary VSP Map, Address 0xE84C[6]

This bit is used to enable block noise reduction (BNR).

Function di_bnr_enable Description

0 

1

Disable BNR

Enable BNR di_bnr_edge_offset[7:0] , Primary VSP Map 2, Address 0xE98D[7:0]

This signal is used to configure the BNR processing.


Function di_bnr_edge_offset[7:0] Description

0x32

0x64

0x96

Recommended setting for low level BNR

Recommended value for mid level BNR

Recommended value for high level BNR di_bnr_disable_local_detect , Primary VSP Map 2, Address 0xE987[3]

This bit is used to configure the BNR processing.

Function di_bnr_disable_local_d etect

Description

0

1 

Recommended setting for high level BNR

Recommended setting for low/mid level BNR di_bnr_scale_global_vert[2:0] , Primary VSP Map 2, Address 0xE98B[7:5]


Function di_bnr_scale_global_ve rt[2:0]

Description

0101 

0110

Recommended setting for low/mid level BNR

Recommended setting for high level BNR di_bnr_scale_global_hori[2:0] , Primary VSP Map 2, Address 0xE98B[4:2]


Function di_bnr_scale_global_ho ri[2:0]

Description

0101 

0110


Recommended setting for high level BNR di_bnr_global_strength_gain[3:0] , Primary VSP Map 2, Address 0xE988[7:4]


Function di_bnr_global_strength

_gain[3:0]

Description

1000 

1100


Recommended setting for high level BNR di_bnr_detect_scale_line[3:0] , Primary VSP Map 2, Address 0xE987[7:4]





Function di_bnr_detect_scale_lin e[3:0]

0111 

1001

3.2.3.10.

Description


Recommended setting for high level BNR

Sharpness Enhancement

The sharpness enhancement block extracts high frequency data from the de-interlaced and de-noised video frame to help simultaneously sharpen the appearance of edges and other video details, recover high frequency components and provide pictures with a natural look without adding a halo or ringing artifact. Since the sharpness works on a two dimensional pixel array before the scaler, noise will not be scaled during the scaling operation.

Detail and edge sharpness enhancement supports both interlaced and progressive inputs. It can be enabled or disabled using

di_sharpness_enable . The sharpness level can be adjusted using the signed, twos complement value in pvsp_srscal_scale_gain[11:0] . To increase the sharpness setting, the value in pvsp_srscal_scale_gain[11:0]

should be increased. To decrease the sharpness setting, the value

in pvsp_srscal_scale_gain[11:0] should be decreased.

di_sharpness_enable , Primary VSP Map, Address 0xE84C[7]

This bit is used to enable sharpness control.

Function di_sharpness_enable

0 

1

Description

Disable sharpness

Enable sharpness pvsp_srscal_scale_gain[11:0] , Primary VSP Map, Address 0xE891[7:0]; Address 0xE892[7:4]

This signal is used to control the sharpness level.

3.2.3.11.

Scaler

The last block before the VOM output is the scaler which is used to scale the input video to the desired resolution. This is very flexible and can support arbitrary resolution conversion and independently scale the input video horizontally and vertically. The ADI proprietary scaler algorithms also allow improved performance in the scaling of the input video which improves many common issues associated with scaling video data such as saw tooth, edge blurring, and ringing.

The ADV8003 scaler employs contour-based interpolation techniques to provide sharp edges and crisp details on high resolution content.

The embedded compression noise reduction will eliminate mosquito noise and block artifacts. The contour-based interpolation scaler is capable of upscaling input video formats from 480i to 4k x 2k formats (these include 4k x 2k 30 Hz/4k x 2k 25 Hz/4k x 2k 24 Hz and 4k x

2k 24 Hz SMPTE).

When the automatic scaler algorithm selection is enabled, the contour-based interpolation scaler is used for upscaling and downscaling is performed using the frequency-adaptive scaler which implements the same algorithm as the VIM down scaler. A manual selection

between the contour-based interpolation scaler and the frequency-adaptive scaler is provided by pvsp_srscal_interp_mode[1:0] .

Also, because ADV8003 provides 4kx2k timing in 8-bit precision, pvsp_srscal_8bit_en is provided to make the entire scaler operate in 8-

bit mode. This lowers the power consumed by the scaler. pvsp_srscal_interp_mode[1:0] , Primary VSP Map, Address 0xE894[7:6]

This signal is used to select the scaler algorithm employed.



Function pvsp_srscal_interp_mo de[1:0]

00 

01

10

11

Description

Automatic scaler algorithm selection

Contour-based interpolation scaler (2nd gen scaling algorithm with 4k x 2k support)

Frequency-adaptive scaler (1st gen scaling algorithm)

Bilinear scaler pvsp_srscal_8bit_en , Primary VSP Map, Address 0xE890[3]

This bit is used to set the scaler into 8-bit mode. This bit should be set when output 4K x 2K timing.

Function pvsp_srscal_8bit_en

0 

1

Description

Scaler not in 8-bit mode

Scaler in 8-bit mode

The size of the active image sent to the scaler is set by pvsp_di_crop_height[10:0] and pvsp_di_crop_width[10:0] .

The scaler output can

then be set using pvsp_scal_out_height[12:0] and pvsp_scal_out_width[12:0] by setting pvsp_man_scal_out_enable to 1, or it can set

automatically using pvsp_autocfg_input_vid[7:0]

. These registers should be set to the resolution of the output video. Refer to Figure 57 for

more details. pvsp_man_scal_out_enable , Primary VSP Map, Address 0xE883[3]

This bit is used to enable the manual setting of pvsp_scal_out_width and pvsp_scal_out_height.

Function pvsp_man_scal_out_en able

Description

0 

1

Disable manually setting M_Scaler output resolution

Enable manually setting M_Scaler output resolution pvsp_scal_out_height[12:0] , Primary VSP Map, Address 0xE846[4:0]; Address 0xE847[7:0]

This signal is used to set the output vertical resolution of scaler in the VOM.

Function pvsp_scal_out_height[1

2:0]

Description

0x000 

0xXXX

Default

Output height of VOM scaler pvsp_scal_out_width[12:0] , Primary VSP Map, Address 0xE844[4:0]; Address 0xE845[7:0]

This signal is used to set the output horizontal resolution of scaler in the VOM.

Function pvsp_scal_out_width[1

2:0]

Description

0x000 

0xXXX

Default

Output width of VOM scaler



Image before

Scaler

VSP3D_DI_CROP_HEIGHT

Scaler

VOM in Scaled Image

VSP3D_SCAL_OUT_HEIGHT

PVSP_DI_CROP_WIDTH

PVSP_SCAL_OUT_WIDTH

Figure 57: VOM Scaler Dimensions

3.2.3.12.

Panorama Mode

If the scaled video has a different aspect ratio to the original and the horizontal scaling factor is larger than the vertical, the panorama

function can be enabled using m_scaler_panorama_en .

In effect, this stretches the left- and right-most sides of the input video to fill the output resolution. This method keeps the original ratio in the centre of the screen. Figure 58 explains the panorama mode scaling feature.

Figure 58: Panorama Scaling Feature m_scaler_panorama_en , Primary VSP Map, Address 0xE850[0]

This bit enables panorama scaling for the VOM scaler.

Function m_scaler_panorama_en Description

0 

1

Disable VOM panorama

Enable VOM panorama

The position from which the output video becomes stretched is controlled using

m_scaler_panorama_pos[11:0] . This allows the user to control the width of the sides of the output image. Refer to Figure 58 for more details.

m_scaler_panorama_pos[11:0] , Primary VSP Map, Address 0xE851[3:0]; Address 0xE852[7:0]

This signal is used to define the width of the output video frame which is not stretched when panorama mode is enabled but, rather, is scaled properly. The maximum value of this register is set by: pvsp_di_crop_width * (pvsp_scal_out_width/pvsp_di_crop_height) - pvsp_scal_out_width/2.



This register sets half the width of the output frame which is to be scaled normally. By default, this register is set to 0 which means that all the input frame will be stretched. It is, therefore, recommended that this register is set by the user before enabling the panorama function.

Function m_scaler_panorama_po s[11:0]

Description

0x000 

0xXXX

Default

Width of not-stretched image

3.2.3.13.

Output Port

This section details the configuration registers for the final block of the PVSP VOM. The primary purpose of the output port is to generate

the output video timing and output the video data. Refer to Table 29 for the register settings for the common CEA video formats that are

supported by the ADV8003. The output setting can be automatically configured using the setting of pvsp_autocfg_output_vid[7:0] . If the

output configuration needs to be set manually,

pvsp_man_dp_timing_enable

must be set to 1 and pvsp_autocfg_output_vid[7:0] must be

set to 0. Refer to Figure 59 for more information.

When using manual configuration of the output timing format, pvsp_dp_4kx2k_mode_en needs to be manually enabled when outputting

4k x 2k series timings and should be disabled for other timing formats.

If a limited range of output must be provided, pvsp_data_clipping_en should be enabled. Otherwise, this register should be disabled. A

limited range indicates the output is clipped to 16-235 range for each data channel of pixel. pvsp_dp_4kx2k_mode_en , Primary VSP Map, Address 0xE869[4]

This bit is used to make the VOM display module work in 4K x 2K mode. This register's value will be used while pvsp_autocfg_output_vid is 0.

Function pvsp_dp_4kx2k_mode_ en

Description

0 

1

Not in 4K x 2K mode

In 4K x 2K mode pvsp_data_clipping_en , Primary VSP Map, Address 0xE84E[3]

This bit is used to limit the output data within range of 16 to 235.

Function pvsp_data_clipping_en

0 

1

Description

Not limit output data

Limit output data pvsp_man_dp_timing_enable , Primary VSP Map, Address 0xE883[0]

This bit is used to enable the manual setting of the display port's timing.



Function pvsp_man_dp_timing_ enable

0 

1

Description

Disable manually setting output timing

Enable manually setting output timing pvsp_dp_decount[12:0] , Primary VSP Map, Address 0xE856[4:0]; Address 0xE857[7:0]

This signal is used to set the DE duration of output timing. This register's value will be used while pvsp_autocfg_output_vid is 0.

Function pvsp_dp_decount[12:0] Description

0x000 

0xXXX

Default

Data enable count of output timing pvsp_dp_hfrontporch[11:0] , Primary VSP Map, Address 0xE858[3:0]; Address 0xE859[7:0]

This signal is used to set the horizontal front porch duration of output timing. This register's value will be used while pvsp_autocfg_output_vid is 0.

Function pvsp_dp_hfrontporch[1

1:0]

Description

0x000 

0xXXX

Default

Horizontal front porch of output timing pvsp_dp_hsynctime[11:0] , Primary VSP Map, Address 0xE85A[3:0]; Address 0xE85B[7:0]

This signal sets the HSync duration of output timing. This register's value will be used while pvsp_autocfg_output_vid is 0.

Function pvsp_dp_hsynctime[11:

0]

Description

0x000 

0xXXX

Default

HSync width of output timing pvsp_dp_hbackporch[11:0] , Primary VSP Map, Address 0xE85C[3:0]; Address 0xE85D[7:0]

This signal is used to set the horizontal back porch duration of output timing. This register's value will be used while pvsp_autocfg_output_vid is 0.

Function pvsp_dp_hbackporch[1

1:0]

Description

0x000 

0xXXX

Default

Horizontal back porch of output timing pvsp_dp_activeline[11:0] , Primary VSP Map, Address 0xE85E[3:0]; Address 0xE85F[7:0]

This signal is used to set the active line number of output timing. This register's value will be used while pvsp_autocfg_output_vid is 0.



Function pvsp_dp_activeline[11:

0]

0x000 

0xXXX

Description

Default

Active lines of output timing pvsp_dp_vfrontporch[9:0] , Primary VSP Map, Address 0xE860[1:0]; Address 0xE861[7:0]

This signal is used to set the vertical front porch duration of output timing. This register's value will be used while pvsp_autocfg_output_vid is 0.

Function pvsp_dp_vfrontporch[9

:0]

Description

0x000 

0xXXX

Default

Vertical front porch of output timing pvsp_dp_vsynctime[9:0] , Primary VSP Map, Address 0xE862[1:0]; Address 0xE863[7:0]

This signal is used to set the vertical synchronous time duration of output timing. This register's value will be used while pvsp_autocfg_output_vid is 0.

Function pvsp_dp_vsynctime[9:0

]

Description

0x000 

0xXXX

Default

VSync width of output timing pvsp_dp_vbackporch[9:0] , Primary VSP Map, Address 0xE864[1:0]; Address 0xE865[7:0]

This signal is used to set the vertical back porch duration of output timing. This register's value will be used while pvsp_autocfg_output_vid is 0.

Function pvsp_dp_vbackporch[9:

0]

Description

0x000 

0xXXX

Default

Vertical back porch of output timing pvsp_dp_vpolarity , Primary VSP Map, Address 0xE869[0]

This bit is used to set the polarity of output VSync. This register's value will be used while pvsp_autocfg_output_vid is 0.

Function pvsp_dp_vpolarity

0 

1

Description

Low

High pvsp_dp_hpolarity , Primary VSP Map, Address 0xE869[1]

This bit is used to set the polarity of output HSync. This register's value will be used while pvsp_autocfg_output_vid is 0.



Function pvsp_dp_hpolarity

0 

1

Description

Low

High

Output Timing

576p

720p50

1080p50 vga

480p

720p60

0xE8

56

0x02

0x05

0x07

0x02

0x02

0x05

0x07

0x07 decount

Table 29: Output Port Configuration Settings for Example Output Resolutions hfrontporch HSync hbackporch activeline Vfrontporch VSync vbackporch hpol vpol

0xE8

57

0xE8

58

0xE8

59

0xE8

5A

0xE8

5B

0xE8

5C

0xE8

5D

0xE8

5E

0xE8

5F

0xE8

60

0xE8

61

0xE8

62

0xE8

63

0xE8

64

0xE8

65

0xD0 0x00 0x0C 0x00 0x40 0x00 0x44 0x02 0x40 0x00 0x05 0x00 0x05 0x00 0x27 0

0xE8

69[1]

0xE8

69[0]

0

0x00 0x01 0xB8 0x00 0x28 0x00 0xDC 0x02 0xD0 0x00 0x05 0x00 0x05 0x00 0x14 1

0x80 0x02 0x10 0x00 0x2C 0x00 0x94 0x04 0x38 0x00 0x04 0x00 0x05 0x00 0x24 1

0x80 0x00 0x10 0x00 0x60 0x00 0x30 0x01 0xE0 0x00 0x0A 0x00 0x02 0x00 0x21 0

0xD0 0x00 0x10 0x00 0x3E 0x00 0x3C 0x01 0xE0 0x00 0x09 0x00 0x06 0x00 0x1E 0

0x00 0x00 0x6E 0x00 0x28 0x00 0xDC 0x02 0xD0 0x00 0x05 0x00 0x05 0x00 0x14 1

0x80 0x00 0x58 0x00 0x2C 0x00 0x94 0x04 0x38 0x00 0x04 0x00 0x05 0x00 0x24 1

0x80 0x02 0x7E 0x00 0x2C 0x00 0x94 0x04 0x38 0x00 0x04 0x00 0x05 0x00 0x24 1

1

1

1

1

1

0

0

1080p60

1080p24

The size of output images of the VOM scaler can be smaller than that defined by the parameters of the output port (that is, album mode).

The starting position for the PVSP output video can be set using pvsp_dp_video_h_start[12:0] and pvsp_dp_video_v_start[12:0] . Figure

59 shows the relationship of the VOM scaler image and the output video. In this case, the blank area around the output image is filled with

color defined by pvsp_dp_margin_color[23:0] in the YCbCr color space.

Output video from Primary VSP

PVSP_DP_VIDEO_V_START

VSP3D_DP_VIDEO_H_START

Output video from

VOM Output

VSP3D_SCAL_OUT_HEIGHT

VSP3D_DP_ACTIVELINE

PVSP_SCAL_OUT_WIDTH

PVSP_DP_DECOUNT

Figure 59: VOM Output Dimensions pvsp_dp_video_h_start[12:0] , Primary VSP Map, Address 0xE848[4:0]; Address 0xE849[7:0]

This signal is used to set the horizontal start position where the output video of the scaler is placed.

Function pvsp_dp_video_h_start

[12:0]

Description

0x000 

0xXXX

Default

Horizontal start position of VOM output pvsp_dp_video_v_start[12:0] , Primary VSP Map, Address 0xE84A[4:0]; Address 0xE84B[7:0]

This signal is used to set the vertical start position where the output video of scaler is placed.



Function pvsp_dp_video_v_start[

12:0]

0x000 

0xXXX

Description

Default

Vertical start position of VOM output pvsp_dp_margin_color[23:0] , Primary VSP Map, Address 0xE866[7:0]; Address 0xE867[7:0]; Address 0xE868[7:0]

This signal is used to set the default color in output video in YUV colorspace.

Function pvsp_dp_margin_color[

23:0]

Description

0x000000

0xXXXXXX

Default

Default color in YUV colorspace pvsp_dp_output_blank , Primary VSP Map, Address 0xE869[2]

This bit is used to force the color output of the Primary VSP. This If this bit is set to 1, the output of Primary VSP is forced to the user defined color in pvsp_dp_margin_color.

Function pvsp_dp_output_blank

0 

1

Description

Not output default color

Output default color

3.2.3.14.

Demo Function

ADV8003 supports automatically splitting the display window to demo several processing functions of ADV8003.

pvsp_demo_window_enable can be used to enable the demo function.

pvsp_demo_window_enable , Primary VSP Map, Address 0xE87E[7]

Enables demo window.

Function pvsp_demo_window_e nable

Description

0 

1

Disable demo window

Enable demo window

pvsp_demo_window_use_lower_screen

can be used to set the position of the demo window. If this bit is set to 1, the lower half display window is used for certain processing function, otherwise the upper half display window is used. pvsp_demo_window_use_lower_screen , Primary VSP Map, Address 0xE87E[6]

This bit is used to enable a demo mode on the lower half of the screen. If this bit is set to 1, the lower half display window will be used for certain processing functions, otherwise the upper half display window will be used.

Function pvsp_demo_window_us e_lower_screen

Description

0 

1

Use upper half screen as demo window

Use lower half screen as demo window


The following registers can be used to enable each corresponding demo function. pvsp_demo_window_rnr_enable , Primary VSP Map, Address 0xE87E[4]

This bit is used to enable the RNR in the demo window.

Function pvsp_demo_window_rn r_enable

Description

0 

1

Disable RNR in demo window

Enable RNR in demo window pvsp_demo_window_mnr_enable , Primary VSP Map, Address 0xE87E[3]

This bit is used to enable the MNR in the demo window.

Function pvsp_demo_window_m nr_enable

Description

0 

1

Disable MNR in demo window

Enable MNR in demo window pvsp_demo_window_bnr_enable , Primary VSP Map, Address 0xE87E[2]

This bit is used to enable the BNR in the demo window.

Function pvsp_demo_window_b nr_enable

Description

0 

1

Disable BNR in demo window

Enable BNR in demo window pvsp_demo_window_cadence_enable , Primary VSP Map, Address 0xE87E[1]

This bit is used to enable the cadence detection in the demo window.

Function pvsp_demo_window_ca dence_enable

Description

0 

1

Disable cadence detection in demo window

Enable cadence detection in demo window pvsp_demo_window_ulai_enable , Primary VSP Map, Address 0xE87E[0]

This bit is used to enable the ULAI in the demo window.

Function pvsp_demo_window_ul ai_enable

Description

0 

1

Disable ULAI in demo window

Enable ULAI in demo window pvsp_demo_window_cue_enable , Primary VSP Map, Address 0xE87F[5]

This bit is used to enable CUE correction in the demo window.




Function pvsp_demo_window_c ue_enable

0 

1

Description

Disable CUE in demo window

Enable CUE in demo window pvsp_demo_window_intra_field_enable , Primary VSP Map, Address 0xE87F[4]

This bit is used to enable the intra field interpolation in the demo window.

Function pvsp_demo_window_in tra_field_enable

Description

0 

1

Disable intra field interpolation in demo window

Enable intra field interpolation in demo window

The contour-based interpolation scaler (2 nd generation with 4k x 2k support) demo can be enabled by setting

pvsp_srscal_demo_mode_en to compare the contour-based interpolation scaler and the frequency-adaptive scaler (1

st generation) performance side by side. pvsp_srscal_demo_mode_en , Primary VSP Map, Address 0xE890[4]

This bit is used to enable scaler demo mode.

Function pvsp_srscal_demo_mod e_en

Description

0 

1

Scaler not in demo mode

Scaler in demo mode

3.2.3.15.

Progressive to Interlaced Converter

The main progressive to interlaced (PtoI) converter can be connected to many blocks, for example, Video TTL input channel, EXOSD

TTL input channel, PVSP, and so on. The block can be used for video conversion, for example, conversion of 1080p to 1080i. It drops the progressive video odd or even lines based on the field signal of the output interlaced video. It can only support 480p, 576p, and 1080p input. The associated interlaced timing signals can be generated in the independent PtoI hardware block.

By enabling m_p2i_drop_line_as_pvsp_flag , the PtoI module can drop interpolated lines to get optimal output performance.

The PtoI hardware can be enabled using m_p2i_enable .

m_p2i_enable , Secondary VSP Map, Address 0xE649[4]

This bit is used to enable the PtoI in VSP_top.

Function m_p2i_enable Description

0 

1

Disable

Enable m_p2i_drop_line_as_pvsp_flag , Secondary VSP Map, Address 0xE65B[7]

This bit is used to select an interlaced mode in game mode. If PVSP works in game mode and PVSP's input is interlaced, this bit should be set to 1 for P2I to drop interpolated lines. Otherwise, this bit should be set to 0.



The input video to the PtoI block is defined using m_p2i_vid[7:0] . Refer to Table 30 for more details on the value of this register.

m_p2i_vid[7:0] , Secondary VSP Map, Address 0xE64B[7:0]

'This register is used to set the VIC of the PtoI in VSP_top.

Function m_p2i_vid[7:0]

0x00 

Description

Default

Input Timing Format to

P2I

Table 30: VID Set to PtoI

576p 1080p50 480p 1080p60 svsp_m_p2i_vid 17 31 2 16

The PVSP PtoI does not have direct access to the data from the input pins but it can be utilized to convert a progressive input format to

interlaced using the PVSP core bypass path by setting the pvsp_bypass bit.

3.2.3.16.

Automatic Contrast Enhancement

The Automatic Contrast Enhancement (ACE) block is used to intelligently enhance the contrast of the whole picture by making dark regions darker and bright regions brighter. It is stable under scene changes as well as being robust in the presence of noise. ACE

supports both interlaced and progressive inputs and can be enabled/disabled using ace_enable .

ace_enable , IO Map, Address 0x1A30[7]

This bit is used to enable the automatic contrast enhancement (ACE) block.

Function ace_enable Description

0 

1

Bypass A.C.E.

Enable A.C.E.

3.3.

SECONDARY VSP

3.3.1.

Introduction to SVSP

Figure 60: ADV8003 SVSP

Figure 60

shows the structure of the SVSP .

The SVSP comprises of four sections; the VIM, the VOM, a controller which is the FFS, and a

PtoI converter.



The SVSP can be used to offer the option of a second output resolution to the user. The structure of the SVSP is similar to the PVSP but it is much simpler in design and does not contain all the processing elements of the PVSP. The structure of the SVSP comprises FFS, VIM, and VOM blocks.

Input to the SVSP can only be in progressive format.

The SVSP has the following features:

• Image cropping

• Scaling

• FRC

• PtoI conversion

The image cropping function is the same as that provided in the PVSP and, like the PVSP, there is an image cropper in both the VIM and the VOM of the SVSP. In the SVSP only, the VIM is capable of scaling video data. This means that the VIM of the SVSP can support vertical resolution scaling as well as horizontal resolution scaling.

The SVSP is also capable of performing FRC, which is controlled by the FFS of the SVSP. The FFS in the SVSP provides the same functionality as the FFS in the PVSP. A PtoI converter which can be used to convert the incoming video standard from progressive to interlaced is also included as part of the SVSP.

Like game mode in PVSP, SVSP can also support bypass DDR mode. Using this mode, the SVSP can convert between 1080p and 720p without using external memory. This allows the user to perform a simple conversion which does not use external memory bandwidth.

However, FRC is not supported in this case.

The SVSP can be simply bypassed by setting svsp_bypass to 1.

Note: The input to the SVSP can only be progressive video. Therefore, interlaced video must be routed through the de-interlacer in the

PVSP before being routed to the SVSP. The PVSP output can also be sent to the SVSP as a progressive input. svsp_bypass , Secondary VSP Map, Address 0xE649[6]

This bit is used to bypass the Secondary VSP.

Function svsp_bypass Description

0  Not bypass Secondary VSP

1 Bypass Secondary VSP

Similarly, if using the SVSP, the VIM and VOM must be enabled. This can be done by enabling svsp_enable_vim

and svsp_enable_vom .

svsp_enable_vim , Secondary VSP Map, Address 0xE610[6]

This bit is used to control the Video Input Module (VIM). If this bit is set to 1, the VIM is enabled to write packed input video data into the defined external frame buffer. While the Secondary VSP is running, if this bit is set to 0, the output video stream will be frozen.

Function svsp_enable_vim

0 

Description

Disable VIM

1 Enable VIM


ADV8003 Hardware Manual svsp_enable_vom , Secondary VSP Map, Address 0xE610[5]

This bit is used to control the Video Output Module (VOM). If this bit is set to 1, the VOM is enabled to read video data from external memory, process it and then output it.

Function svsp_enable_vom Description

0 

1

Disable VOM

Enable VOM

If using the SVSP, the FFS must be enabled (using svsp_enable_ffs ) so that the hardware knows the various conversions that must be

performed. The use of field/frame buffers in external memory is managed by the FFS which decides which frame buffer should be used by the VIM to store input video data. The FFS also decides which frame buffer should be read back by the VOM. The SVSP utilizes a frame repeat/drop mechanism to implement FRC, which is also managed by the FFS. svsp_enable_ffs , Secondary VSP Map, Address 0xE610[7]

This bit is used to control the Field Frame Scheduler (FFS). If this bit is set to 1, the FFS is enabled and the VIM and VOM are scheduled by the FFS, which means the Secondary VSP is in work mode. If this bit is set to 0, the Secondary VSP is in idle mode.

Function svsp_enable_ffs

0 

1

Description

Disable FFS/FRC

Enable FFS/FRC

3.3.1.1.

Autoconfiguration

Each block inside the VIM and the VOM can be automatically configured to decrease the configuration complexity. The

svsp_autocfg_input_vid[7:0]

and

svsp_autocfg_output_vid[7:0] registers should be set to make the autoconfiguration work. The

59.94/23.97 Hz timings have the same VID as the corresponding 60/24 Hz timing in Table 31 .

svsp_autocfg_input_vid[7:0] , Secondary VSP Map, Address 0xE660[7:0]

This register is used to set the input timing VIC. If this register is 0, SVSP will use values in registers of svsp_vin_h, svsp_vin_v and svsp_vin_fr to set input video.

Function svsp_autocfg_input_vid

[7:0]

Description

0x00 

0xXX

Custom input video

Input timing VIC

Rev. B, August 2013

CEA

Table 31: SVSP Supported Input Video Timing and VID


640x480p60

720x480p60

1

2 or 3 or 14 or 15 or 35 or 36

720x240p60

1280x720p60

1920x1080p

720x576p50

8 or 9 or 12 or 13

4

16

17 or 18 or 29 or 30 or 37 or 38

1280x720p50

720x288p50

19

23 or 24 or 27 or 28

1920x1080p50 31

182



1920x1080p24 32

1920x1080p25 33

1920x1080p30 34

720p100

576p100

720p120

480p120

41

42 or 43

47

48 or 49

VESA timing

576p200

480p240

VGA

SVGA

XGA

WXGA

SXGA

WXGA-2

UXGA

WXGA-3

52 or 53

56 or 57

200

201

202

203

204

205

206

207

WUXGA 208

Note : The SVSP does not support the following formats:

• 1280x720p @ 23.97/24 Hz (CEA VIC 60)

• 1280x720p @ 25 Hz (CEA VIC 61)

• 1280x720p @ 29.97/30 Hz (CEA VIC 62) svsp_autocfg_output_vid[7:0] , Secondary VSP Map, Address 0xE661[7:0]

This register is used to set the output timing VIC. If this register is 0, SVSP will use values in registers of svsp_dp_decount, svsp_dp_hfrontporch, svsp_dp_hsynctime, svsp_dp_hbackporch, svsp_dp_activeline, svsp_dp_vfrontporch, svsp_dp_vsynctime, svsp_dp_vbackporch, svsp_dp_hpolarity, svsp_dp_vpolarity and svsp_vout_fr to set output video.

Function svsp_autocfg_output_v id[7:0]

Description

0x00 

0xXX

Custom output video

Output timing VIC

Table 32 lists all the supported video timings and their VID. The 59.94/23.97 Hz timings have the same VID as the corresponding 60/24

Hz timing in the table.

CEA

Table 32: SVSP Supported Output Video Timing and VID


640x480p60 1

720x480p60 2 or 3 or 14 or 15 or 35 or 36

720(1440)x240p60 8 or 9

720(2880)x240p60 12 or 13

1280x720p60 4

1920x1080i60

720x480i60

1920x1080p

720x576p50

5

6 or 7 or 10 or 11

16

17 or 18 or 29 or 30 or 37 or 38



Video Timing

1280x720p50

1920x1080i50

720x576i50

720x288p50

1920x1080p50

1920x1080p24

1920x1080p25

1920x1080p30

720p100

576p100

720p120

480p120

576p200

480p240

VGA

VESA timing

SVGA

XGA

WXGA

SXGA

WXGA-2

UXGA

WXGA-3

201

202

203

204

205

206

207

VID

19

20

21 or 22 or 25 or 26

23 or 24 or 27 or 28

31

32

33

34

41

42 or 43

47

48 or 49

52 or 53

56 or 57

200

WUXGA 208

Note : The SVSP does not support the following formats;

• 1280x720p @ 23.97/24 Hz (CEA VIC 60)

• 1280x720p @ 25 Hz (CEA VIC 61)

• 1280x720p @ 29.97/30 Hz (CEA VIC 62)

If overscan, crop or album mode is employed, the required blocks should be configured manually by enabling the corresponding enable

bits, such as svsp_vim_crop_enable , to enable the VIM crop block.

3.3.1.2.

Customized Input/Output Video Format Configuration

If the input timing is not in the SVSP input format table, the input format needs to be set manually. If the input resolution has a variation in regard to standard timing (for example, if

svsp_autocfg_input_vid[7:0] is set to 2, which indicates the input resolution is 720x480, but the actual resolution is 718x478), the user can manually set svsp_autocfg_input_vid[7:0] to be 0 and set the input resolution through the

following three registers. svsp_man_input_res , Secondary VSP Map, Address 0xE663[4]

This bit is used to enable the manual configuration of the input resolution.

Function svsp_man_input_res

0 

1

Description

Disable manual configuration of input resolution

Enable manual configuration of input resolution svsp_vin_h[10:0] , Secondary VSP Map, Address 0xE616[7:0]; Address 0xE617[7:5]

This signal is used to set the horizontal resolution of the input video. This register's value will be used while svsp_man_input_res is 1 or svsp_autocfg_input_vid is 1.



Function svsp_vin_h[10:0]

0x000 

0xXXX

Description

Default

Horizontal resolution of input video svsp_vin_v[10:0] , Secondary VSP Map, Address 0xE618[7:0]; Address 0xE619[7:5]

This signal is used to set the vertical resolution of the input video. This register's value will be used while svsp_man_input_res is 1 or svsp_autocfg_input_vid is 1.

Function svsp_vin_v[10:0]

0x000 

0xXXX

Description

Default

Vertical resolution of input video

Similarly, if the output timing is not in the SVSP output format table, the output format needs to be set manually. The detailed configuration instruction is given in the SVSP VOM output port description.

3.3.1.3.

Frame Buffer Number

Depending on the type of conversion that is to take place, a certain number of buffers must be allocated for the input/output video data.

Depending on the conversion required, this should be set in the

svsp_fieldbuf_num[2:0] register. svsp_fieldbuf_num[2:0] can be

automatically set per svsp_autocfg_input_vid[7:0]

and

svsp_autocfg_output_vid[7:0] . The

svsp_fieldbuf_num[2:0] register will not

change when crop or album mode is enabled. svsp_fieldbuf_num[2:0] , Secondary VSP Map, Address 0xE610[2:0]

This signal is used to set the number of field/frame buffers. This signal needs to be configured while svsp_osd_mode_en is 1.

Function svsp_fieldbuf_num[2:0]

000 

Description

Default

XXX Number of field/frame buffers

3.3.1.4.

Frame Buffer Address and Size

In order to store video data in external memory in the correct size frames, the buffer size of the external DDR2 memory must be

programmed by the user. These programmed field buffers or frame buffers are allocated by setting the svsp_fieldbuffer0_addr[31:0] , svsp_fieldbuffer1_addr[31:0] , svsp_fieldbuffer2_addr[31:0] and svsp_fieldbuffer3_addr[31:0] registers.

The value programmed into each of these registers is determined in Equation 19 .

frame

_

size

=

active

_

video

_

width

×

active

_

video

_

height

×

no

_

bytes

_

per

_

pixel

Equation 19: Calculating External Memory Field Buffers

For example, for an output video resolution of 720p, Equation 19 would yield the following field size:

Field_size = ((1280)x(720))x2 = 1843200

where no_bytes_per_pixel indicates the number of bytes required to store each pixel. Refer to Table 26 for more details of the number of

bytes required to store each pixel of data.


ADV8003 Hardware Manual svsp_fieldbuffer0_addr[31:0] , Secondary VSP Map, Address 0xE600[7:0]; Address 0xE601[7:0]; Address 0xE602[7:0]; Address 0xE603[7:0]

This signal is used to set the start address of frame buffer 0. The software should arrange memory space properly, avoiding conflict between different buffers.

Function svsp_fieldbuffer0_addr[

31:0]

Description

0x00000000

0xXXXXXXXX

Default

Start address of frame buffer 0 svsp_fieldbuffer1_addr[31:0] , Secondary VSP Map, Address 0xE604[7:0]; Address 0xE605[7:0]; Address 0xE606[7:0]; Address 0xE607[7:0]



31:0]

Description

0x00000000

0xXXXXXXXX

Default

Start address of frame buffer 1 svsp_fieldbuffer2_addr[31:0] , Secondary VSP Map, Address 0xE608[7:0]; Address 0xE609[7:0]; Address 0xE60A[7:0]; Address 0xE60B[7:0]



31:0]

Description

0x00000000

0xXXXXXXXX

Default

Start address of frame buffer 2 svsp_fieldbuffer3_addr[31:0] , Secondary VSP Map, Address 0xE60C[7:0]; Address 0xE60D[7:0]; Address 0xE60E[7:0]; Address

0xE60F[7:0]



31:0]

Description

0x00000000

0xXXXXXXXX

Default

Start address of frame buffer 3 svsp_fieldbuffer4_addr[31:0] , Secondary VSP Map, Address 0xE664[7:0]; Address 0xE665[7:0]; Address 0xE666[7:0]; Address 0xE667[7:0]

This signal is used to set the start address of field/frame buffer 4. The software should arrange memory space properly, avoiding conflict between different buffers.'




31:0]

0x00000000

0xXXXXXXXX

Description

Default

Start address of frame buffer 4 svsp_fieldbuffer5_addr[31:0] , Secondary VSP Map, Address 0xE668[7:0]; Address 0xE669[7:0]; Address 0xE66A[7:0]; Address 0xE66B[7:0]



31:0]

Description

'0x00000000

0xXXXXXXXX

Default

Start address of frame buffer 5 svsp_fieldbuffer6_addr[31:0] , Secondary VSP Map, Address 0xE66C[7:0]; Address 0xE66D[7:0]; Address 0xE66E[7:0]; Address

0xE66F[7:0]



31:0]

Description

0x00000000

0xXXXXXXXX

Default

Start address of frame buffer 6

3.3.1.5.

Frame Latency

Depending on the format being input to the ADV8003 and the output required from the SVSP, different resolutions will have different frame latencies. This is due to the increased processing required on scaling different types of video data. This has a certain impact in that

the audio will have to be delayed by the same amount. Table 33 lists frame latencies in different cases for various resolutions.

Input

Frame Rate

50 Hz

Output

Table 33: Frame Latency in Normal Mode

Frame Rate 50 Hz 59.94/60 Hz

Timing

576p

720p

1080p

576p/720p/1080 p

0.1~1.3

1, 2

23.97/24 Hz 25/30 Hz

480p/720p/1080p 720p/1080p 720p/1080p

0.1~1.3 0.1~1.4 0.1~1.4

0.1~1.3 0.1~1.4 0.1~1.4 59.94/60 Hz 480p

720p

1080p

0.1~1.3

23.97/24/25/30Hz 720/1080p 0.1~0.8 0.1~0.8 0.1~1.3 0.1~1.3

1. x.x means x.x times the input video frame

2. A~B means frame latency is not a fixed value, it varies between A and B



When crop or album mode is enabled, frame latency will be different from that listed in Table 33 . In this case, the user can use the

following controls to measure frame latency: svsp_rb_frame_latency[2:0]

and

svsp_rb_hsync_latency[11:0]

are read only registers. Their values are real-time frame and HSync latency between input and output video.

Frame latency may vary within a range; the svsp_rb_max_latency[14:0]

readback register indicates the maximum frame latency, while

svsp_rb_min_latency[14:0]

indicates the minimum frame latency. If svsp_frc_latency_measure_en is set to 0, svsp_rb_max_latency[14:0]

and

svsp_rb_min_latency[14:0] are cleared. If asserting

svsp_frc_latency_measure_en , SVSP monitors values in svsp_rb_max_latency[14:0]

and

svsp_rb_min_latency[14:0] and then records the maximum and minimum values of them in the

svsp_rb_max_latency[14:0]

and svsp_rb_min_latency[14:0] registers

which are both 15 bits wide. The highest three bits are the frame latency and the lower 12 bits are the HSync latency. Users should note that it will take several seconds for the SVSP to find the maximum and minimum frame/HSync latency.

In a normal case (not game mode), the SVSP’s input video and output video latency is consistent. svsp_frc_latency_measure_en , Secondary VSP Map, Address 0xE662[2]

This bit is used to enable measuring frame/HSync latency.

Function svsp_frc_latency_meas ure_en

Description

0 

1

Disable

Enable svsp_rb_frame_latency[2:0] , Secondary VSP Map, Address 0xE6F2[7:5] (Read Only)

This signal is used to readback the realtime frame latency.

Function svsp_rb_frame_latency[

2:0]

Description

0xXXX Frame latency svsp_rb_hsync_latency[11:0] , Secondary VSP Map, Address 0xE6F3[7:0]; Address 0xE6F4[7:4] (Read Only)

This signal is used to readback the realtime HSync latency.

Function svsp_rb_hsync_latency[

11:0]

Description

0xXXX HSync latency svsp_rb_max_latency[14:0] , Secondary VSP Map, Address 0xE6F5[7:0]; Address 0xE6F6[7:1] (Read Only)

This signal is used to read back the maximum frame/HSync latency. The upper three bits are VSync latency, the lower twelve bits are

HSync latency.

Function svsp_rb_max_latency[1

4:0]

Description

0xXXX Maximum of frame latency


ADV8003 Hardware Manual svsp_rb_min_latency[14:0] , Secondary VSP Map, Address 0xE6F7[7:0]; Address 0xE6F8[7:1] (Read Only)

This signal is used to read back the minimum frame/HSync latency. The upper three bits are VSync latency, the lower twelve bits are

HSync latency.

Function svsp_rb_min_latency[1

4:0]

0xXXX

Description

Minimum of frame latency

3.3.1.6.

Freezing Output Video

Output video can be frozen by disabling the VIM by setting svsp_enable_vim to 0.

3.3.2.

SVSP Video Input Module (VIM)

Figure 61: SVSP Video Input Module

Figure 61 shows the structure of the SVSP VIM. This can be broken up into three hardware blocks. The VIM cropper can be used to crop

an input video image to a given image size. The scaler can be used to scale a video resolution to any target resolution. The pixel packer is used to pack pixels data into memory words and write them into external memory. The starting address in external memory is provided by FFS and is configured by the user using the frame buffer registers. As indicated at the start of

Section 3.3

, in order for the VIM module

to operate, it must first be enabled. This can be done using the

svsp_enable_vim bit. If the VIM is disabled by setting this register to 0, the

output video will be frozen.

3.3.2.1.

VIM Cropper

The VIM cropper block is used to define a sub window within the given input resolution. This cropped image will then become the video which will be processed by the SVSP. The following registers are used to define this sub window.

•

svsp_vim_crop_enable

•

svsp_vim_crop_h_start[10:0]

•

svsp_vim_crop_v_start[10:0]

•

svsp_vim_crop_width[10:0]

•

svsp_vim_crop_height[10:0]

To enable cropper block in VIM, svsp_vim_crop_enable

must be set to 1. svsp_vim_crop_enable , Secondary VSP Map, Address 0xE662[6]


This bit is used to enables the VIM crop.

Function svsp_vim_crop_enable Description

0 

1

Disable

Enable

Figure 62 shows the correlation between the cropped image and the input video resolution.

Input Video

SVSP_VIM_CROP_V_START

VSP2D_VIM_CROP_H_START

Cropped Image

VSP2D_VIM_CROP_HEIGHT


SVSP_VIM_CROP_WIDTH

Figure 62: VIM Crop Dimensions svsp_vim_crop_h_start[10:0] , Secondary VSP Map, Address 0xE61A[7:0]; Address 0xE61B[7:5]

This signal sets the horizontal start position of the VIM cropper.

Function svsp_vim_crop_h_start[

10:0]

Description

0x000 

0xXXX

Default

Horizontal start position of VIM cropper input svsp_vim_crop_v_start[10:0] , Secondary VSP Map, Address 0xE61C[7:0]; Address 0xE61D[7:5]

This signal sets the horizontal start position of the VIM cropper.

Function svsp_vim_crop_v_start[

10:0]

Description

0x000 

0xXXX

Default

Vertical start position of VIM cropper input svsp_vim_crop_width[10:0] , Secondary VSP Map, Address 0xE61E[7:0]; Address 0xE61F[7:5]

This signal is used to set the input width of the VIM cropper.

Function svsp_vim_crop_width[1

0:0]

Description

0x000 

0xXXX

Default

Width of VIM cropper input


ADV8003 Hardware Manual svsp_vim_crop_height[10:0] , Secondary VSP Map, Address 0xE620[7:0]; Address 0xE621[7:5]

This signal is used to set the input height of the VIM cropper.

Function svsp_vim_crop_height[

10:0]

Description

0x000 

0xXXX

Default

Height of VIM cropper input

Note: The following limitations apply to the values that can be programmed in these registers:

• Register values programmed must be even numbers

•

0 <= svsp_vim_crop_h_start[10:0] <= (INPUT VIDEO HORIZONTAL RESOLUTION – 1)

•

0 <= svsp_vim_crop_v_start[10:0] <= (INPUT VIDEO VERTICAL RESOLUTION – 1)

•

( svsp_vim_crop_h_start[10:0] + svsp_vim_crop_width[10:0] ) <= INPUT VIDEO HORIZONTAL ACTIVE PIXELS

•

( svsp_vim_crop_v_start[10:0] +

svsp_vim_crop_height[10:0] ) <= INPUT VIDEO VERTICAL ACTIVE PIXELS

3.3.2.2.

Scaler

The size of the active image being sent to the SVSP is configured using svsp_vim_crop_height[10:0]

and svsp_vim_crop_width[10:0]

as mentioned in Section

3.3.2. The output of the SVSP scaler can be set using

svsp_vim_scal_out_height[10:0] and svsp_vim_scal_out_width[10:0]

, or it can be automatically set per svsp_autocfg_output_vid[7:0] . These registers should be set to the

resolution of the output video. svsp_man_scal_out_enable , Secondary VSP Map, Address 0xE662[5]

This bit is used to enable manually setting scaler output resolution.

Function svsp_man_scal_out_en able

Description

0 

1

Disable

Enable svsp_vim_scal_out_height[10:0] , Secondary VSP Map, Address 0xE624[7:0]; Address 0xE625[7:5]

This signal is used to set the output vertical resolution of scaler in the VIM.

Function svsp_vim_scal_out_hei ght[10:0]

Description

0x000 

0xXXX

Default

Output height of VIM scaler svsp_vim_scal_out_width[10:0] , Secondary VSP Map, Address 0xE622[7:0]; Address 0xE623[7:5]

This signal is used to set the output horizontal resolution of scaler in the VIM.

Function svsp_vim_scal_out_wid th[10:0]

Description

0x000 

0xXXX

Default

Output width of VIM scaler



Image before

Scaler

VSP2D_VIM_CROP_HEIGHT

Scaler

VIM in Scaled Image

VSP2D_VIM_SCAL_OUT_HEIGHT

SVSP_VIM_CROP_WIDTH

SVSP_VIM_SCAL_OUT_WIDTH

Figure 63: VIM Scaler Dimensions

3.3.2.3.

Scaler Interpolation Mode

This section describes the method for scaling the input video data. The purpose of the scaler is to allow different input formats to be displayed on a screen with a fixed resolution. This can allow lower resolution video, for example, 480p, to be upscaled to a high definition format such as 1080p. This can improve the overall quality of a video signal when displayed on a high definition television. The four

options of video scaling are listed below and are chosen using svsp_vim_scal_type[1:0] .

Refer to

Section 3 for more information on the types of scaler algorithm

. svsp_vim_scal_type[1:0] , Secondary VSP Map, Address 0xE646[7:6]

This signal is used to set the VIM scaling algorithm. In most cases, the scaler type should be left at the default setting.

Function svsp_vim_scal_type[1:0

]

Description

00 

01

10

11


Sharp

Smooth

Bilinear

3.3.2.4.

VIM Miscellaneous Control

The following registers are used in the control of the VIM scaling function and should be tailored according to user requirements.

Anti-alias filters are provided to improve the performance of the SVSP downscaling and can be enabled using

svsp_vim_scal_anti_alias_h_en and svsp_vim_scal_anti_alias_v_en .

svsp_vim_scal_anti_alias_h_en , Secondary VSP Map, Address 0xE650[5]

This bit is used to enable the anti-aliasing filter for horizontal direction.

Function svsp_vim_scal_anti_alia s_h_en

Description

0

1 

Disable

Enable svsp_vim_scal_anti_alias_v_en , Secondary VSP Map, Address 0xE650[6]

This bit is used to enable anti-aliasing filter for vertical direction.



Function svsp_vim_scal_anti_alia s_v_en

0

1 

Description

Disable

Enable

svsp_vim_scal_type[1:0] , svsp_vim_scal_anti_alias_h_en and svsp_vim_scal_anti_alias_v_en can be manually set. These settings take

effect only when svsp_man_scaler_para_enable is set to 1, otherwise they can be automatically configured by the SVSP using

svsp_autocfg_input_vid[7:0]

and svsp_autocfg_output_vid[7:0] .

svsp_man_scaler_para_enable , Secondary VSP Map, Address 0xE662[4]

This bit is used to enable manually setting scaler parameters.

Function

Description svsp_man_scaler_para_ enable

0 

1

Disable

Enable

When a picture is zoomed in, it is possible to maintain the original high frequency content. However, maintaining this content can sometimes introduce ringing artifacts. This overshoot can be controlled by adjusting

svsp_vim_scal_overshoot_ctrl[11:0]

according to user preference. svsp_vim_scal_overshoot_ctrl[11:0] , Secondary VSP Map, Address 0xE647[7:0]; Address 0xE648[7:4]

This signal is used to control the overshoot in the scaling of input video. If set to a value larger than the default setting, more overshoot is allowed.

Function svsp_vim_scal_oversho ot_ctrl[11:0]

0x080 

Description

Default

3.3.2.5.

Panorama Mode

This feature is the same as for the PVSP. If the scaled video has a different aspect ratio to the original and the horizontal scaling factor is

larger than the vertical one, the panorama function can be enabled using svsp_vim_scal_pano_en . In effect, this stretches the left- and

right-most sides of the input video to fill the output resolution. This method keeps the original ratio in the centre of the screen. Figure 58

explains the panorama mode scaling feature. svsp_vim_scal_pano_en , Secondary VSP Map, Address 0xE650[7]

This bit is used to enable panorama scaling for the Secondary VSP.

Function svsp_vim_scal_pano_en Description

0  Disable panorama

1 Enable panorama

The position from which the output video becomes stretched is controlled using svsp_vim_scal_pano_pos[10:0] . This allows the user to

control the width of the sides of the output image. Refer to Figure 58 for more details.


ADV8003 Hardware Manual svsp_vim_scal_pano_pos[10:0] , Secondary VSP Map, Address 0xE651[7:0]; Address 0xE652[7:5]

This signal is used to define the width of the output video frame which is not stretched when panorama mode is enabled but rather scaled properly. The maximum value of this register is set by: svsp_vim_crop_width *

(svsp_vim_scal_out_height/svsp_vim_crop_height) - svsp_vim_scal_out_width/2.

This register sets half the width of the output frame which is to be scaled normally. By default, this register is set to 0 which means that all the input frame will be stretched. It is, therefore, recommended that this register is set by the user before enabling the panorama function.

Function svsp_vim_scal_pano_p os[10:0]

Description

0x000 

0xXXX

Default

Width of not-stretched image

3.3.2.6.

Pixel Packer

At the back end of the VIM, the pixel packer converts input video to word packets suitable for writing to external memory. The operation of this hardware block is similar to the pixel packer in the PVSP. The SVSP manages pixels in 8-bit precision. Pixels in external memory

have two different data formats which can be selected using svsp_ex_mem_data_format[1:0] :

• 24-bit YCbCr

• 16-bit YCbCr-4:2:2 svsp_ex_mem_data_format[1:0] , Secondary VSP Map, Address 0xE611[7:6]

This signal is used to set the data format in external memory.

Function svsp_ex_mem_data_for mat[1:0]

Description

01

11

YCbCr-8b-8b-8b

YCbCr-4:2:2-8b

3.3.3.

SVSP Video Output Module

Figure 64: SVSP Video Output Module (VOM)

Figure 64 shows the structure of the VOM in the SVSP. This is a much simpler structure than that of the VOM in the PVSP.

The SVSP VOM offers the following functions:



• Pixel unpacker: reads field/frame from external memory and unpacks memory word to video pixel information

• VOM cropper: reads cropped images from external memory

• Output port: generates output timing and output video

Register update protection is provided in the ADV8003. Refer to

Section 3.4 for more details regarding the update of the various VSP

registers. svsp_lock_vom , Secondary VSP Map, Address 0xE610[4]

This bit is used to lock the Video Output Module (VOM). If the Secondary VSP is running and this bit is set to 1, the VOM will be locked to the current register setting to display the last frame. The Secondary VSP registers can be configured safely in this state. All new register settings will be updated after this bit is set back to 0.

Function svsp_lock_vom

0 

1

Description

Unlock VOM

Lock VOM

Note : This register should be used only as part of the gentle reboot protocol. Refer to Section

3.4.3 for more details.

svsp_update_vom , Secondary VSP Map, Address 0xE610[3]

Registers related to the VOM can be updated only when this bit is set to 0. All new register settings will be updated by VOM in next frame after this bit is set back to 1.

Function svsp_update_vom

0 

1

Description

Do not update VOM

Update VOM

3.3.3.1.

Pixel Unpacker

The pixel unpacker in the VOM of the SVSP is similar to that in the VOM of the PVSP. The pixel unpacker is used to convert external memory words (128 bits) into video pixel (YCbCr-8-8-8-bit) data. Pixels in external memory can have the following two different data formats which are the same as those set by the VIM. This is configured in the same way as the VIM.

• 24-bit YCbCr

• 16-bit YCbCr 4:2:2

Data format details are described in svsp_ex_mem_data_format[1:0] .

3.3.3.2.

VOM Cropper

The VOM cropper is also very similar to the cropper in the VOM of the PVSP. The following registers are used to configure the VOM cropper.

•

svsp_vom_crop_enable

•

svsp_vom_crop_h_start[10:0]

•

svsp_vom_crop_v_start[10:0]

•

svsp_vom_crop_width[10:0]

•

svsp_vom_crop_height[10:0]

The function of the VOM cropper can be seen in Figure 65 . To enable the cropper in the SVSP VOM, svsp_vom_crop_enable

should be asserted.


svsp_vom_crop_enable , Secondary VSP Map, Address 0xE662[1]

This bit is used to enable the VOM crop.

Function svsp_vom_crop_enable

0 

1

Description

Disable

Enable

Video Image in External Memory

SVSP_VOM_CROP_V_START

VSP2D_VOM_CROP_H_START

Cropped Image

VSP2D_VOM_CROP_HEIGHT


SVSP_VOM_CROP_WIDTH

Figure 65: VOM Crop Dimensions svsp_vom_crop_h_start[10:0] , Secondary VSP Map, Address 0xE626[7:0]; Address 0xE627[7:5]

This signal is used to set the horizontal start position of the VOM cropper.

Function svsp_vom_crop_h_start

[10:0]

Description

0x000  Default

0xXXX svsp_vom_crop_v_start[10:0] , Secondary VSP Map, Address 0xE628[7:0]; Address 0xE629[7:5]

This signal is used to set the vertical start position of the VOM cropper.

Function svsp_vom_crop_v_start

[10:0]

Horizontal start position of VOM cropper

Description

0x000 

0xXXX

Default

Vertical start position of VOM cropper svsp_vom_crop_width[10:0] , Secondary VSP Map, Address 0xE62A[7:0]; Address 0xE62B[7:5]

This signal is used to set the width of the VOM cropper.



Function svsp_vom_crop_width[

10:0]

0x000 

0xXXX

Description

Default

Width of VOM cropper input svsp_vom_crop_height[10:0] , Secondary VSP Map, Address 0xE62C[7:0]; Address 0xE62D[7:5]

This signal is used to set the height of the VOM cropper.

Function svsp_vom_crop_height[

10:0]

Description

0x000 

0xXXX

Default

Height of VOM cropper input

Note: The following restrictions apply to the values at which these registers can be set:

• All registers should contain even values

•

0 <= svsp_vom_crop_h_start[10:0] <= (HORIZONTAL RESOLUTION OUTPUT BY VIM – 1)

•

0 <= svsp_vom_crop_v_start[10:0] <= (RESOLUTION OUTPUT BY VIM – 1)

•

( svsp_vom_crop_h_start[10:0] + svsp_vom_crop_width[10:0] ) <= HORIZONTAL RESOLUTION OUTPUT BY VIM

•

( svsp_vom_crop_v_start[10:0] +

svsp_vom_crop_height[10:0] ) <= VERTICAL RESOLUTION OUTPUT BY VIM

3.3.3.3.

Output Port

This section describes the configuration registers for the final block of the VOM of the SVSP. The main purpose of the output port is to generate the output video timing and output the video data. For more details regarding the various register settings for the output port for

various common video formats, refer to Table 34.

The output setting can be automatically configured using svsp_autocfg_output_vid[7:0] .

If the output configuration is to be set manually,

svsp_man_dp_timing_enable

should be set to 1. Refer to Figure 66

for more information. svsp_man_dp_timing_enable , Secondary VSP Map, Address 0xE663[7]

This bit is used to enable manually setting output timing.

Function svsp_man_dp_timing_e nable

Description

0 

1

Disable

Enable svsp_dp_decount[10:0] , Secondary VSP Map, Address 0xE632[7:0]; Address 0xE633[7:5]

This signal is used to set the DE duration of output timing. This register's value will be used while svsp_autocfg_output_vid is 0.

Function svsp_dp_decount[10:0] Description

0x000 

0xXXX

Default

Data enable count of output timing svsp_dp_hfrontporch[9:0] , Secondary VSP Map, Address 0xE634[7:0]; Address 0xE635[7:6]

This signal is used to set the horizontal front porch duration of output timing. This register's value will be used while svsp_autocfg_output_vid is 0.



Function svsp_dp_hfrontporch[9:

0]

0x000 

0xXXX

Description

Default

Horizontal front porch of output timing svsp_dp_hsynctime[9:0] , Secondary VSP Map, Address 0xE636[7:0]; Address 0xE637[7:6]

This signal is used to set the HSync duration of output timing. This register's value will be used while svsp_autocfg_output_vid is 0.

Function svsp_dp_hsynctime[9:0

]

Description

0x000 

0xXXX

Default

HSync width of output timing svsp_dp_hbackporch[9:0] , Secondary VSP Map, Address 0xE638[7:0]; Address 0xE639[7:6]

This signal is used to set the horizontal back porch duration of output timing. This register's value will be used while svsp_autocfg_output_vid is 0.

Function svsp_dp_hbackporch[9:

0]

Description

0x000 

0xXXX

Default

Horizontal back porch of output timing svsp_dp_activeline[10:0] , Secondary VSP Map, Address 0xE63A[7:0]; Address 0xE63B[7:5]

This signal is used to set the active line number of output timing. This register's value will be used while svsp_autocfg_output_vid is 0.

Function svsp_dp_activeline[10:0

]

Description

0x000 

0xXXX

Default

Active lines of output timing svsp_dp_vfrontporch[9:0] , Secondary VSP Map, Address 0xE63C[7:0]; Address 0xE63D[7:6]

This signal is used to set the vertical front porch duration of output timing. This register's value will be used while svsp_autocfg_output_vid is 0.

Function svsp_dp_vfrontporch[9:

0]

Description

0x000 

0xXXX

Default

Vertical front porch of output timing svsp_dp_vsynctime[9:0] , Secondary VSP Map, Address 0xE63E[7:0]; Address 0xE63F[7:6]

This signal is used to set the vertical synchronous time of output timing. This register's value will be used while svsp_autocfg_output_vid is 0.



Function svsp_dp_vsynctime[9:0] Description

0x000 

0xXXX

Default

VSync width of output timing svsp_dp_vbackporch[9:0] , Secondary VSP Map, Address 0xE640[7:0]; Address 0xE641[7:6]

This signal is used to set the vertical back porch duration of output timing. This register's value will be used while svsp_autocfg_output_vid is 0.

Function svsp_dp_vbackporch[9:

0]

Description

0x000 

0xXXX

Default

Vertical back porch of output timing svsp_dp_vpolarity , Secondary VSP Map, Address 0xE642[7]

This signal is used to set the polarity of output VSync. This register's value will be used while svsp_autocfg_output_vid is 0.

Function svsp_dp_vpolarity Description

0 

1

Low

High svsp_dp_hpolarity , Secondary VSP Map, Address 0xE642[6]

This signal is used to set the polarity of output HSync. This register's value will be used while svsp_autocfg_output_vid is 0.

Function svsp_dp_hpolarity

0 

1

Description

Low

High

Output Timing

576i

576p

720p50

1080i50

1080p50 vga

480i

480p

720p60

1080i60

0xE

632 decount

0xE

633

Table 34: Output Port Configuration Settings for Example Output Formats hfrontporch HSync hbackporch activeline Vfrontporch VSync vbackporch vpol hpol

0xE

634

0xE

635

0xE

636

0xE

637

0xE

638

0xE

639

0xE

63A

0xE

63B

0xE

63C

0xE

63D

0xE

63E

0xE

63F

0xE

640

0xE

641

0xE6

42[7]

0xE6

42[6]

0x5A 0x00 0x03 0x00 0x10 0x00 0x11 0x00 0x48 0x00 0x01 0x40 0x01 0x40 0x09 0xC0 0 0

0x5A 0x00 0x03 0x00 0x10 0x00 0x11 0x00 0x48 0x00 0x01 0x40 0x01 0x40 0x09 0xC0 0

0xA0 0x00 0x6E 0x00 0x0A 0x00 0x37 0x00 0x5A 0x00 0x01 0x40 0x01 0x40 0x05 0x00 1

0xF0 0x00 0x84 0x00 0x0B 0x00 0x25 0x00 0x87 0x00 0x01 0x00 0x01 0x40 0x09 0x00 1


0x50 0x00 0x04 0x00 0x18 0x00 0x0C 0x00 0x3C 0x00 0x02 0x80 0x00 0x80 0x08 0x40 0

0x5A 0x00 0x04 0x00 0x0F 0x80 0x0F 0x00 0x3C 0x00 0x02 0x40 0x01 0x80 0x07 0x80 0

0x5A 0x00 0x04 0x00 0x0F 0x80 0x0F 0x00 0x3C 0x00 0x02 0x40 0x01 0x80 0x07 0x80 0

0xA0 0x00 0x1B 0x80 0x0A 0x00 0x37 0x00 0x5A 0x00 0x01 0x40 0x01 0x40 0x05 0x00 1



0xF0 0x00 0x9F 0x80 0x0B 0x00 0x25 0x00 0x87 0x00 0x01 0x00 0x01 0x40 0x09 0x00 1

1

1

0

0

1

1

1

1

0

1

0

1080p60

1080p24

The size of the output images of the VOM scaler can be smaller than that defined by the parameters of the output port. The starting

position for the SVSP output video can be set using svsp_dp_video_h_start[10:0] and svsp_dp_video_v_start[10:0] . Figure 66 shows the

relationship of the VOM scaler image and output video. In this case, the blank area around the output image is filled with color defined by



the svsp_dp_margin_color[23:0] register in the YUV color space. This feature can be enabled using svsp_dp_output_blank .

Output video from Primary VSP

SVSP_DP_VIDEO_V_START

VSP2D_DP_VIDEO_H_START

Output video from

VOM Output

VSP2D_DI_CROP_HEIGHT

VSP2D_DP_ACTIVELINE

SVSP_SCAL_OUT_WIDTH

SVSP_DP_DECOUNT

Figure 66: VOM Output Dimensions svsp_dp_video_h_start[10:0] , Secondary VSP Map, Address 0xE62E[7:0]; Address 0xE62F[7:5]

This signal is used to set the horizontal start position where the output video of the scaler is placed.

Function

Description svsp_dp_video_h_start[

10:0]

0x000 

0xXXX

Default

Horizontal start position of output port svsp_dp_video_v_start[10:0] , Secondary VSP Map, Address 0xE630[7:0]; Address 0xE631[7:5]

This signal is used to set the vertical start position where the output video of the scaler is placed.

Function svsp_dp_video_v_start[

10:0]

Description

0x000 

0xXXX

Default

Vertical start position of output port svsp_dp_margin_color[23:0] , Secondary VSP Map, Address 0xE643[7:0]; Address 0xE644[7:0]; Address 0xE645[7:0]

This signal is used to set the default color in the output video in the YUV colorspace.

Function svsp_dp_margin_color[

23:0]

Description

0x000000

0xXXXXXX

Default

Default color in YUV colorspace svsp_dp_output_blank , Secondary VSP Map, Address 0xE642[5]

This bit is used to force the color output of the Secondary VSP. If this register is set to 1, the output of the Secondary VSP is forced to the user defined color in svsp_dp_margin_color.



Function svsp_dp_output_blank

0 

1

3.3.3.4.

DDR Bypass Mode

Description

Not output default color

Output default color

In the case where the SVSP is being used to upscale or downscale between 1080p and 720p, external DDR2 memory is not required.

Internal line buffers allow the user to convert between these two resolutions while maintaining the full external memory bandwidth for

both the PVSP and OSD. The DDR bypass mode provided in the SVSP can be manually enabled/disabled using svsp_ddr_bypass . DDR2

bypass mode can be automatically configured using

svsp_autocfg_input_vid[7:0] and

svsp_autocfg_output_vid[7:0] . If the DDR bypass

mode is to be set manually, svsp_man_set_ddr_bypass must be set to 1.

Note: This option is only available to the user when scaling between two resolutions which have the same frame rate. svsp_man_set_ddr_bypass , Secondary VSP Map, Address 0xE662[0]

This bit is used to enable manually setting DDR bypass. If this bit is set to 1, SVSP will bypass DDR while svsp_ddr_bypass is 1, or not bypass DDR while svsp_ddr_bypass is 0.

Function svsp_man_set_ddr_byp ass

Description

0 

1

Disable

Enable svsp_ddr_bypass , Secondary VSP Map, Address 0xE649[7]

This bit is used to bypass external memory. This register's value will be used while svsp_man_set_ddr_bypass is 1.

Function svsp_ddr_bypass Description

0 

1

Not bypass external memory

Bypass external memory

3.3.3.5.

Progressive to Interlaced Converter in SVSP

The PtoI converter block in the SVSP is used to convert progressive video to interlaced video. It drops odd or even lines of the progressive video based on the output interlaced video field signal. Support is limited to 480p and 576p. The associated interlaced timing signals can be generated in the PtoI hardware block.

The PtoI converter in the SVSP cannot operate in standalone mode – it must be connected to the SVSP.

The PtoI hardware can be enabled using svsp_p2i_enable .

svsp_p2i_enable , Secondary VSP Map, Address 0xE649[5]

This bit is used to enable the PtoI in Secondary VSP.

Function svsp_p2i_enable Description

0 

1

Disable

Enable



The input video to the PtoI block is defined using

svsp_p2i_vid[7:0] . For more details on the values which must be programmed into this register, refer to Table 35 .

svsp_p2i_vid[7:0] , Secondary VSP Map, Address 0xE64A[7:0]

'This register is used to set the VIC of the PtoI in Secondary VSP.

Function svsp_p2i_vid[7:0]

0x00 

Description

Default

Input Timing Format to

P2I

Table 35: VID for PtoI

576p svsp_s_p2i_vid 17

480p

2

3.4.

VSP REGISTER ACCESS PROTOCOLS

This section is used to describe the methods available to the user to update the VSP registers. The following types of register access protocols are available:

• Bootup protocol

• Reboot protocol

• Gentle reboot protocol

• VOM set protocol

• Free access protocol

These protocols are recommended to the user as best practice for updating VSP registers. The appropriate protocol should be used depending on the current status of the device. The seamless transfer of the VSP between standards can be achieved by using the bootup protocol, reboot protocol, gentle reboot protocol and VOM set protocols. If not changing VSP registers in real time, the free access protocol can be used.

3.4.1.

Bootup Protocol

The bootup protocol is used to configure the PVSP or SVSP from a reset state. All registers can be accessed using this protocol.



Figure 67: Bootup Protocol Flowchart

Figure 67 shows the process for the bootup protocol for the PVSP. This is exactly the same for the SVSP with the appropriate registers

replaced.

3.4.2.

Reboot Protocol

The reboot protocol is used to reset the PVSP and configure it again using different settings, especially different input timing or output timing. All registers can be accessed using this protocol. It should be noted that the output video will be interrupted using this protocol.



Figure 68: Reboot Protocol Flowchart

Figure 68 shows the process for the reboot protocol for the PVSP. This is exactly the same for the SVSP with the appropriate registers

replaced.



3.4.3.

Gentle Reboot Protocol

The gentle reboot is used to reboot the PVSP with different configuration settings but does not interrupt the output timing. The output video is frozen during this protocol. All registers except output video timing registers can be accessed.

Figure 69: Gentle Reboot Protocol Flowchart

Figure 69

shows the process for the gentle reboot protocol for the PVSP. This is exactly the same for the SVSP with the appropriate registers replaced.



3.4.4.

VOM Set Protocol

The VOM set protocol is used to configure the VOM. The registers in the VOM can be accessed without affecting the output video timing.

Figure 70: VOM Set Protocol Flowchart

Figure 70 shows the process for the VOM set protocol for the PVSP. This is exactly the same for the SVSP with the appropriate registers

replaced.

3.4.5.

Free Access Protocol

The free access protocol allows the user to configure all VSP registers regardless of the current configuration of the device. This can be

seen in Figure 71 .

Start

Configure register

Rev. B, August 2013

End

Figure 71: Free Access Protocol

206


3.5.

PROGRESSIVE TO INTERLACED CONVERSION

ADV8003 has two progressive to interlaced converters (P2I).

The primary P2I converter is an independent block to which the PVSP, OSD and inputs can be connected. The primary P2I converter can

convert from any progressive format to its interlaced equivalent. The input to the primary P2I converter is selected by p2i_inp_sel[3:0] .

The secondary P2I converter is connected directly to the SVSP. The secondary P2I converter cannot convert from 1080p to 1080i but can handle all other progressive to interlaced conversions. p2i_inp_sel[3:0] , IO Map, Address 0x1A06[7:4]

This signal is used to select the video source for the Progressive to Interlaced converter.

Function p2i_inp_sel[3:0] Description

0x00 

0x01

0x02

0x03

0x04

From Primary VSP


From EXOSD TTL Input

From RX Input

From Video TTL Input



4.

ON SCREEN DISPLAY

4.1.

INTRODUCTION

The On Screen Display (OSD) core in the ADV8003 allows the user to overlay a bitmap-based OSD onto one of the input video streams.

The OSD blend is capable of being performed at data rates up to 3 GHz (ADV8003KBCZ-8x derivatives). The OSD can be designed using the ADI Blimp software tool. This code generating tool may be used to design, simulate and compile the OSD which will be used in the end system application.

The Blimp OSD software tool covers the full design flow involved in delivering a complex bitmap-based OSD – from initial graphics design through to outputting the files required for integration into the system application. Blimp OSD abstracts the user from the OSD hardware so a detailed description of the OSD hardware is not provided. For more information on the OSD design flow and Blimp OSD software, refer to the Blimp OSD software tool user manual.

4.1.1.

Features

• Full design-flow covered by Blimp OSD software, user does not need to worry about the OSD hardware

• OSD maximum resolution of 4096 x 3840

• Pixel-by-pixel alpha blending

• Dual video paths through the OSD blend block to support dual zone OSD display

• Eight hardware timers which provide added functionality for OSD or system tasks

• Programmable blending effect of OSD and background video

• Programmable priority of regions

• Uniform programmable transparent color in the OSD

• OSD video input and output format: 36-bit RGB

• Support for main 3D video format timings

• High-performance scaling quality with 8-bit horizontal and vertical video scaler

• Arbitrary resolution conversion

• Support vertical/horizontal scaling order change

• Support progressive to interlaced conversion

• Anti-alias mode for downscaling

• OSD data range control

4.1.2.

OSD System Application Diagram

Figure 72 provides a typical application diagram for using the bitmap OSD. The external MCU uses the ADV8003 SPI slave (serial port 1)

interface to configure the registers in the bitmap OSD module. The ADV8003 uses its SPI master (serial port 2) interface to obtain the

OSD data (fonts, icons, and images) from an external flash memory and store it into the DDR2 memory. The OSD can then be blended onto either of the video paths through the OSD core.



Blend

Input 1

Blend

Input 2

ADV8002

Blend

Output 1

OSD

Blend

Output 2

Figure 72: Typical Application Diagram

4.1.3.

Typical OSD Component Sizes

An indication of typical OSD component sizes in provided in Table 36. This can be used to gain an approximation of the size of an OSD.

Table 36: Output Port Configuration Settings for Example Output Formats

Component Color Mode

(per pixel)

DDR2 Size

(bytes, W – width, H – height)

Label 8 bits W*H*2

Image

Listbox

Textbox

8 bits/16 bits/32 bits

32 bits

16 bits

W*H*2/4/8

W*H*8

W*H*4

Iptextbox

Histogram

Menubar

Keyboard

Progressbar

Timer

16 bits

32 bits

32 bits

32 bits

32 bits

0

W*H*4

W*H*8

W*H*8

W*H*8

W*H*8

0

4.2.

ARCHITECTURE OVERVIEW

4.2.1.

Introduction

As outlined in

Section 4.1.2, the OSD core in the ADV8003 is controlled mainly via a SPI slave interface and loads images and OSD data

into the part via a SPI master interface. Consequently, a number of the configuration registers for the OSD core are SPI registers and the code required to control these registers is automatically generated by the Blimp OSD software tool – abstracting the user away from having to understand them. For this reason, many of the SPI registers are not described in this section. For more information, refer to the Blimp

OSD software tool user manual.

4.2.2.

Top Level Diagram

Figure 73 provides a diagram of the ADV8003 OSD top level.


OSD TTL Input

Internally

OSD

Generated

Core

OSD


Figure 73: Bitmap OSD Top Level Diagram

OSD Blend: Used to overlay the OSD data with the input video.

OSD Scaler: Used to scale the OSD to the target resolution.

CSC: Used to convert the OSD core data color to the same color space as that of the input video.

OSD Core: Used to generate internal OSD data. Reads data from DDR2 memory and outputs data to FIFO.

SPI Master and SPI Slave: SPI master used to copy flash data into DDR2 memory. SPI slave used as the only means to control OSD configuration registers and memories.

4.2.3.

OSD Blending

The OSD core in the ADV8003 has two video inputs and two video outputs and is capable of blending at data rates of up to 3 GHz

(ADV8003KBCZ-8x derivatives).

The two video inputs allow two different video streams to be connected to the OSD core, for example, video TTL input channel and SVSP output. The inputs connected to the OSD core can be selected using

osd_blend_inp_sel[3:0]

and

osd_blend_inp_2_sel[3:0] . Refer to

Figure 29

for further details.

The video stream connected to OSD input 1 is output to the OSD blend 1 output and the video stream connected to OSD input 2 is output to the OSD blend 2 output.

The OSD can be blended onto either one of the two video streams connected to the OSD core, that is, there is only one source of OSD data and it must be configured to match one video stream’s format and timing at a time. The OSD can be switched between the two video streams without causing any disturbance on either output video stream. The OSD core outputs can be connected to one or more of the output blocks, for example, HDMI TX1, HDMI TX2, SD encoder and HD encoder.

The OSD is blended with the selected video stream using alpha blending. This means that each pixel of OSD has its own blending parameter which is used to blend this pixel with its corresponding background video. If the OSD data is transparent, the background video will be passed through and unadjusted.

As shown in Figure 73 , the OSD data needs to be scaled to the target resolution before getting into the blending block (refer to

Section 4.2.7). The clock and DE of the selected video stream are used to read the scaler output data. Delay is added to DATA, DE, HS and

VS for matching the delay of the OSD processing, so the OSD scaler can ensure the correct synchronization of OSD data and input video


ADV8003 Hardware Manual data.

Figure 74: OSD Scaler and Blending Top Level Diagram

4.2.4.

External Alpha Blending

The ADV8003 features an external alpha blend input which is shared with the input pixel port. The external alpha blend can only be used in conjunction with the EXOSD TTL input. This allows the option to specify an external alpha blend value for the EXOSD TTL input

channel. The options for routing the external alpha blend value are outlined in Table 97 . The external alpha blend function is enabled via

SPI.

4.2.5.

OSD Core

The OSD core generates the internal data for the OSD display. It accesses the DDR2 memory (through a DMA controller) to load the required resources.

reg_osd_enable is used to enable the OSD core on the ADV8003.

reg_osd_enable , OSD, Address 0xEE00[0]

The enable bit of OSD core.

Function reg_osd_enable

0 

1

Description

Disables OSD core

Enables OSD core

osd_reset is used to reset the whole OSD core.

osd_reset , IO, Address 0x1AFD[1]

This register bit resets the OSD core.



Function osd_reset

0 

1

Description

Default

Resets OSD core

4.2.5.1.

OSD Core Region Definition

A region defines an area on the plane, as shown in Figure 75 . The regions are derived from the OSD components defined in the

Blimp

OSD software and, therefore, contain the different elements of the OSD, for example, the text, images, icons, and so on. In other words, the regions define how the OSD pixels to be displayed are stored in DDR2 memory. The equivalence between OSD components and regions

can be found in Table 37 . A maximum of 256 regions can be displayed simultaneously on the screen.

Note : Only the regions being displayed at a given time count (and not the total on the whole OSD), so this number should be more than enough for even the most complex OSD.

OSD region

OSD plane

Background Video

Figure 75: Definition of OSD Region

Table 37: Regions Used for OSD Components

Component Number of Regions Needed in Hardware

OSDLabel

OSDImage

1

1

OSDHistogram 1

OSDKeyboard 2

OSDProgressbar 2

OSDTextbox 1

OSDMenubar

OSDListbox

OSDTimer

One region per item on each level

One region per item

0

OSDIptextbox 1

For example, if the designed OSD uses the OSD Menu bar component shown in Figure 76 , and the user is moving through the icon menu,

there will be three regions in use at the time when the selected icon is Node1 (that is, the elements from the same level, Node1, Node5 and

Node6). When the selected icon is Node3, there will be three regions in use, that is, Node2, Node3, and Node4. When the selected icon is

Node7, there will be two regions in use, that is, Node7 and Node8.

Note how the efficient translation of components to regions means that it is almost impossible to run out of regions while designing even the most complex OSD.



Figure 76: OSD Menu Bar Component

4.2.5.2.

OSD Color Space

Bitmap images as well as external OSDs are passed to the OSD core in 8-bit RGB format. However, all video processing in the ADV8003 takes place in YCbCr. The OSD core features a CSC to enable conversion of the OSD data from RGB to YCbCr. The OSD core CSC can convert into either full of limited range YCbCr.

4.2.6.

OSD Timers

ADV8003 OSD supports up to eight hardware timers. One of these timers (user-selectable in the OSD firmware) is used by the OSDTimer component of Blimp OSD , which can be inserted within any OSD design (consult the Blimp OSD manual for a detailed description of how to do this). Blimp OSD will automatically handle a number of OSD timers and will map all of them to one hardware timer. If the OSD design flow with the Blimp OSD tool is followed, the user does not need to know any low-level details about the timers. However, since they can also be used as general purpose system timers, its low-level functionality will be described in this section. Note that the HW timer being used by Blimp OSD (user-selectable as mentioned) will not be available to be used as general purpose timer.

Any of these eight timers can trigger an interrupt on the INT0 pin. This interrupt can then be handled by the MCU, and the timer which generated it can be found out by polling the timer registers.

These timers can be configured through the Timer register map. This map is only accessible through the SPI slave interface (address

0x0B). For more information on the SPI slave interface, refer to

Section 4.2.8.2. The registers used to configure the timers are described

below. sys_clock_freq[23:0] , SPI Device Address 0x0B (TIMER), Address 0x00[7:0]; Address 0x01[7:0]; Address 0x02[7:0]

System clock frequency, unit is KHz, the default value is 157.5 MHz.

Function sys_clock_freq[23:0] Description

0x02673C 

0xXXXXXX

Default

System Clock Frequency

This register is used to generate a 1 KHz pulse, which all eight timers are based on to measure a 1 ms interval. If the system clock frequency is changed, this register can be changed to guarantee the 1 KHz accuracy. It is also possible to modify this register if a smaller time interval than 1ms needs to be measured.

For example:

The default value of sys_clock_freq is 0x0278D0, that is, 162000 (162 MHz).

If it is changed to 16200, the minimum interval will be 0.1 ms.

If it is changed to 1620, the minimum interval will be 0.01ms. timer1_enable , SPI Device Address 0x0B (TIMER), Address 0x03[0]

Timer 1 Enable



Function timer1_enable

0 

1

Description

Disables

Enables

Once the timer is enabled, disabling this bit will stop the counting, and it will be resumed when enabling back this bit.

Note that the rest of the bits within this register perform the same operation as for timer1 but for the other seven timers (i.e. bit[1] controls timer2, bit[2] controls timer3, etc.); they are not included here for readability reasons. timer1_reset , SPI Device Address 0x0B (TIMER), Address 0x04[0]

Timer 1 Reset

Function timer1_reset Description

0 

1

Not reset

Reset

Enabling this reset will clear the timer_cnt and timer_irq_cnt registers.

Note that the rest of the bits within this register perform the same operation as for timer1 but for the other seven timers (that is, bit[1] controls timer2, bit[2] controls timer3, and so on); they are not included here for readability reasons. timer1_loop_mode , SPI Device Address 0x0B (TIMER), Address 0x05[0]

Timer 1 Mode Control

Function timer1_loop_mode

0 

1

Description

One time mode

Infinite mode

When working in one time mode, after the interval is reached, the timer will stop by itself, that is, there is no need to set timer_enable to disabled).

When working in infinite mode, timer_keep_result should be set to 0.

Note that the rest of the bits within this register perform the same operation as for timer1 but for the other seven timers (that is, bit[1] controls timer2, bit[2] controls timer3, and so on); they are not included here for readability reasons. timer1_keep_result , SPI Device Address 0x0B (TIMER), Address 0x06[0]

Timer 1 result control.

Function timer1_keep_result

0 

1

Description

Does not keep timer counter value after timer done

Keep timer counter value after timer done

Note that the rest of the bits within this register perform the same operation as for timer1 but for the other seven timers (that is, bit[1] controls timer2, bit[2] controls timer3, and so on); they are not included here for readability reasons.


ADV8003 Hardware Manual timer1_irq_en , SPI Device Address 0x0B (TIMER), Address 0x07[0]

Timer 1 interrupt enable.

Function timer1_irq_en Description

0 

1

Disable

Enable

Note that the rest of the bits within this register perform the same operation as for timer1 but for the other seven timers (that is, bit[1] controls timer2, bit[2] controls timer3, and so on); they are not included here for readability reasons. timer1_clr_irq , SPI Device Address 0x0B (TIMER), Address 0x08[0]

Clears the timer 1 interrupt after writing 1 to this bit. Note these are not self clearing bits, the user just needs to write 1 to this bit and it will clear the timer_flag and timer_irq_cnt registers. Even if timer_clr_irq is already set at 1, it will not clear the timer interrupt and flag until the user writes 1 to it.

Note that the rest of the bits within this register perform the same operation as for timer1 but for the other seven timers (i.e. bit[1] controls timer2, bit[2] controls timer3, etc.); they are not included here for readability reasons. timer1_flag , SPI Device Address 0x0B (TIMER), Address 0x09[0] (Read Only)

Timer 1 flag.

Function timer1_flag

0 

1

Description

Timer 1 is running

Timer 1 is done

Note that the rest of the bits within this register perform the same operation as for timer1 but for the other seven timers (that is, bit[1] controls timer2, bit[2] controls timer3, and so on); they are not included here for readability reasons. timer1_interval[31:0] , SPI Device Address 0x0B (TIMER), Address 0x0A[7:0]; Address 0x0B[7:0]; Address 0x0C[7:0]; Address 0x0D[7:0]

Timer 1 interval, unit is ms. timer2_interval[31:0] , SPI Device Address 0x0B (TIMER), Address 0x0E[7:0]; Address 0x0F[7:0]; Address 0x10[7:0]; Address 0x11[7:0]

Timer 2 interval, unit is ms. timer3_interval[31:0] , SPI Device Address 0x0B (TIMER), Address 0x12[7:0]; Address 0x13[7:0]; Address 0x14[7:0]; Address 0x15[7:0]


Timer 4 interval, unit is ms. timer5_interval[31:0] , SPI Device Address 0x0B (TIMER), Address 0x1A[7:0]; Address 0x1B[7:0]; Address 0x1C[7:0]; Address 0x1D[7:0]

Timer 5 interval, unit is ms.


ADV8003 Hardware Manual timer6_interval[31:0] , SPI Device Address 0x0B (TIMER), Address 0x1E[7:0]; Address 0x1F[7:0]; Address 0x20[7:0]; Address 0x21[7:0]



Timer 8 interval, unit is ms. timer1_cnt[31:0] , SPI Device Address 0x0B (TIMER), Address 0x2A[7:0]; Address 0x2B[7:0]; Address 0x2C[7:0]; Address 0x2D[7:0] (Read

Only)

Timer 1 value, unit is ms. timer2_cnt[31:0] , SPI Device Address 0x0B (TIMER), Address 0x2E[7:0]; Address 0x2F[7:0]; Address 0x30[7:0]; Address 0x31[7:0] (Read

Only)

Timer 2 value, unit is ms. timer3_cnt[31:0] , SPI Device Address 0x0B (TIMER), Address 0x32[7:0]; Address 0x33[7:0]; Address 0x34[7:0]; Address 0x35[7:0] (Read

Only)


Only)

Timer 4 value, unit is ms. timer5_cnt[31:0] , SPI Device Address 0x0B (TIMER), Address 0x3A[7:0]; Address 0x3B[7:0]; Address 0x3C[7:0]; Address 0x3D[7:0] (Read

Only)

Timer 5 value, unit is ms. timer6_cnt[31:0] , SPI Device Address 0x0B (TIMER), Address 0x3E[7:0]; Address 0x3F[7:0]; Address 0x40[7:0]; Address 0x41[7:0] (Read

Only)


Only)


Only)

Timer 8 value, unit is ms.


ADV8003 Hardware Manual timer1_irq_cnt[31:0] , SPI Device Address 0x0B (TIMER), Address 0x4A[7:0]; Address 0x4B[7:0]; Address 0x4C[7:0]; Address 0x4D[7:0]

(Read Only)

The number of times the timer 1 interrupt was generated. timer2_irq_cnt[31:0] , SPI Device Address 0x0B (TIMER), Address 0x4E[7:0]; Address 0x4F[7:0]; Address 0x50[7:0]; Address 0x51[7:0]

(Read Only)

The number of times the timer 2 interrupt was generated. timer3_irq_cnt[31:0] , SPI Device Address 0x0B (TIMER), Address 0x52[7:0]; Address 0x53[7:0]; Address 0x54[7:0]; Address 0x55[7:0]

(Read Only)


(Read Only)

The number of times the timer 4 interrupt was generated. timer5_irq_cnt[31:0] , SPI Device Address 0x0B (TIMER), Address 0x5A[7:0]; Address 0x5B[7:0]; Address 0x5C[7:0]; Address 0x5D[7:0]

(Read Only)

The number of times the timer 5 interrupt was generated. timer6_irq_cnt[31:0] , SPI Device Address 0x0B (TIMER), Address 0x5E[7:0]; Address 0x5F[7:0]; Address 0x60[7:0]; Address 0x61[7:0]

(Read Only)


(Read Only)


(Read Only)

The number of times the timer 8 interrupt was generated.

4.2.7.

OSD Scaler

The ADV8003 OSD core contains an arbitrary resolution conversion scaler. This scaler performs a scaling function if the OSD resolution inside the DDR2 memory is different from the output video. If the output video is interlaced, the OSD scaler can change the progressive

OSD data to interlaced data for blending. As mentioned in Section

4.2.3, the OSD scaler also guarantees the correct synchronization of

OSD data and input video data.

4.2.8.

OSD Master/Slave SPI Interface

The ADV8003 OSD requires an external DDR2 memory and some configuration done to the OSD SPI registers in order to work. OSD data can be written to the DDR2 memory on startup by the ADV8003. In addition, to dynamically configure the OSD, configuration registers need to be controlled. Note that all this configuration is taken care of by Blimp OSD and the firmware, so a detailed explanation of the DDR2 SPI interface is not provided. For this reason, this section covers only top level information (enable/disable, muxing


ADV8003 Hardware Manual configuration of the OSD through the IO Map I 2 C registers). The SPI slave hardware interface is also described in this section.

4.2.8.1.

Overview

It is possible to access the DDR2 and OSD SPI registers in one of two ways:

• The ADV8003 SPI master interface (serial port 2) can pull in resource data to DDR2 memory from an external SPI flash

memory, as shown in Figure 77 .

• The system MCU (SPI master) can write OSD data into DDR2 memory using the ADV8003 SPI slave interface (serial port 1), as

shown in Figure 78 .

Config

Register

OSD_CORE

SPI

Master

SPI

Slave

I2C

Slave

DDR2 Memory

FLASH

MEM

System

Controller(CPU)

Figure 77: Data Loaded from SPI Flash Through ADV8003 SPI Master Interface


Config

Register


OSD_CORE

SPI

Master

SPI

Slave

I2C

Slave

DDR2 Memory

FLASH

MEM

System

Controller(CPU)

Figure 78: MCU as SPI Master Sending OSD Data Through ADV8003 SPI Slave Interface

Additionally, the system MCU (SPI master) can program the external flash by looping SPI commands through the SPI slave (serial port 1) and the SPI master (serial port 2) interfaces connected in a chain. In this mode, the OSD core just passes through MOSI, SS and SCLK

signals from the MCU to the flash. Note that the system MCU is responsible for any error protection in this mode, as shown in Figure 79 .

This option can be useful during the final debug stage of the OSD, in which the OSD design could be downloaded into the system SPI flash memory through, for example, the USB or RSR232 port of the MCU.

This mode can be enabled using the spi_loop_through

mode which controls the mux shown in Figure 79 .


Config

Register


OSD_CORE

SPI

Master

SPI

Slave

I2C

Slave

DDR2 Memory

FLASH

MEM

System

Controller(CPU)

Figure 79: SPI Loopback Enabled so MCU Can Program SPI Flash

By default, the SPI ports are set in manual mode for the SPI which means the SPI pins are tristated (input). To make the SPI ports operational, the following register bits must be configured to automatic mode. spi1_cs_oe_man_en , IO Map, Address 0x1ACE[7]

This bit is used to control the output enable manual override for spi1_cs.

Function spi1_cs_oe_man_en

0

1 

Description

Auto manual override spi1_miso_oe_man_en , IO Map, Address 0x1ACE[6]

This bit is used to control the output enable manual override for spi1_miso.

Function spi1_miso_oe_man_en

0

1 

Description

Auto

Manual override spi1_mosi_oe_man_en , IO Map, Address 0x1ACE[5]

This bit is used to control the output enable manual override for spi1_mosi.

Function spi1_mosi_oe_man_en Description

0

1 

Auto

Manual override


ADV8003 Hardware Manual spi1_sclk_oe_man_en , IO Map, Address 0x1ACE[4]

This bit is used to control the output enable manual override for spi1_sclk.

Function spi1_sclk_oe_man_en Description

0

1 

Auto

Manual override spi2_cs_oe_man_en , IO Map, Address 0x1ACE[3]

This bit is used to control the output enable manual override for spi2_cs.

Function spi2_cs_oe_man_en

0

1 

Description

Auto

Manual override spi2_miso_oe_man_en , IO Map, Address 0x1ACE[2]

This bit is used to control the output enable manual override for spi2_miso.

Function spi2_miso_oe_man_en

0

1 

Description

Auto

Manual override spi2_mosi_oe_man_en , IO Map, Address 0x1ACE[1]

This bit is used to control the output enable manual override for spi2_mosi.

Function spi2_mosi_oe_man_en

0

1 

Description

Auto

Manual override spi2_sclk_oe_man_en , IO Map, Address 0x1ACE[0]

This bit is used to control the output enable manual override for spi2_sclk.

Function spi2_sclk_oe_man_en Description

0

1 

Auto

Manual override

For the majority of functions, the SPI ports can be left in automatic mode. If using the SPI ports in manual mode, the direction of the various pins can be configured using the following bits. spi1_cs_oe_man , IO Map, Address 0x1ACD[7]

This bit is used to control the output enable for spi1 chip select.


Function spi1_cs_oe_man

0 

1

Description

Input

Output spi1_miso_oe_man , IO Map, Address 0x1ACD[6]

This bit is used to control the output enable for spi1 'master in slave out'.

Function spi1_miso_oe_man Description

0 

1

Input

Output spi1_mosi_oe_man , IO Map, Address 0x1ACD[5]

This bit is used to control the output enable for spi1 'master out slave in'.

Function spi1_mosi_oe_man Description

0 

1

Input

Output spi1_sclk_oe_man , IO Map, Address 0x1ACD[4]

This bit is used to control the output enable for spi1 serial clock.

Function spi1_sclk_oe_man

0 

1

Description

Input

Output spi2_cs_oe_man , IO Map, Address 0x1ACD[3]

This bit is used to control the output enable for spi2 chip select.

Function spi2_cs_oe_man

0 

1

Description

Input

Output spi2_miso_oe_man , IO Map, Address 0x1ACD[2]

This bit is used to control the output enable for spi2 'master in slave out'.

Function spi2_miso_oe_man

0 

Description

Input

1 Output spi2_mosi_oe_man , IO Map, Address 0x1ACD[1]

This bit is used to control the output enable for spi2 'master out slave in'.




Function spi2_mosi_oe_man

0 

1

Description

Input

Output spi2_sclk_oe_man , IO Map, Address 0x1ACD[0]

This bit is used to control the output enable for spi2 serial clock.

Function spi2_sclk_oe_man Description

0 

1

Input

Output

The SPI interface can be reset using

spi_reset .

4.2.8.2.

SPI Slave Interface

The ADV8003 SPI slave interface (serial port 1) is used by the MCU to send the OSD data to the DDR2 and to configure the OSD registers. Note that the SPI functions provided within the ADI libraries will automatically take care of any SPI transfer between the MCU and ADV8003.

Hence, the information in this section is provided just so the user can configure the MCU SPI master to match the ADV8003 SPI slave interface, and get both of them to communicate properly. Apart from this setup, the user should not try to access any other SPI register map (with the exception of the timer SPI registers), since all the OSD SPI communication is handled through the provided ADI firmware.

The SPI slave can support the following modes:

• CPOL = 0, CPHA=0




Figure 80 shows the effect that these settings may have on the data.

CS1

CPOL CPHA

0 0 SCK1

1 SCK1 0

1 0 SCK1

1 1 SCK1

Device Address W/R Data in 0 Data in 1 Sub Address

MOSI1

Delay Mode

MISO1

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Dummy byte Data out 0

7 6 5 4 3 2 1 0

Data out 0 Data out 1

No Delay Mode

MISO1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Figure 80: SPI Slave Interface Timing and Data Format

The CPOL/CPHA can be configured through the I 2 C registers described below. spi_slave_cpol , IO Map, Address 0x1A14[3]



This bit is used to select the SPI slave clock polarity.

Function spi_slave_cpol Description

0

1 

Idle state, clock is low

Idle state, clock is high spi_slave_cpha , IO Map, Address 0x1A14[2]

This bit is used to select the SPI slave clock phase.

Function spi_slave_cpha

0

1 

Description

Negedge used

Posedge used

As can be seen from Figure 80 , the LSB bit of the device address sets whether the access is read or write.

The SPI subaddress is an 8-bit field and the data is also 8 bits wide with MSB sent first and LSB last.

The SPI slave readback has both delay mode and no delay mode, and it is controlled by the following SPI register. slave_delay_mode , SPI Device Address 0x0A, Address 0x85[0]

SPI slave read data MISO1 output delay mode.

Function slave_delay_mode Description

0

1 

No delay

Delay 8 clocks (8 bits dummy data)

In no delay mode, counting from the last rising edge of SCK1 (send subaddress) to the first falling edge of SCK1 (send out MISO1), there are about 10 system clock delays. Assuming the SCK1 is 50% duty cycle, only when SCK1 is slower than system clock/20 = 162 MHz/20 =

8.1 MHz, can no delay mode work normally.

If SCK1 is slower than 6 MHz, no delay mode can be set.

The ADV8003 features an analog antiglitch used to reject glitches on SCK1 (SPI slave). There are three modes of operation of this filter: bypass, 2 ns glitch rejection, and 5ns glitch rejection. The 2 ns glitch rejection mode should be used for clock frequencies between 10MHz and 40 MHz. The 5 ns glitch rejection mode should be used for clock frequencies of less than 10 MHz. spi_filter_en , IO Map, Address 0x1A2C[7]

This bit is used to enable the SPI anti glitch filter.

Function spi_filter_en

0 

1

Description

Anti glitch filter disable

Anti glitch filter enable spi_filter_sel , IO Map, Address 0x1A2C[6]

This bit is used to select the response of the SPI anti glitch filter.



Function spi_filter_sel

0 

1

4.2.8.3.

SPI Master Interface

Description

2ns glitch rejection

5ns glitch rejection

The ADV8003 SPI master interface (serial port 2) is used by the ADV8003 to read the OSD binary file (output by Blimp OSD ) from an external SPI flash memory, and to copy it to the DDR2 memory. Note that the library of functions provided by ADI will take care of this process; the information in this section is just provided so the user can find a suitable SPI flash memory which can be interfaced to the

ADV8003 SPI master interface.

The SPI master is designed to be compatible with the M25P16 and supports the FAST_READ command. The SPI master clock can be configured to support up to 80 MHz. The SPI master, similar to the slave, can support the following modes:





Figure 81 shows the effect that these settings may have on the data.

CS2

CPOL CPHA

0 0

SCK2

1

SCK2

0

1 0 SCK2

1 1

SCK2

Instruction(0x0B) 24-bit Address

Dummy Byte

MOSI2 23 22 21 ... 3 2 1 0 7 6 5 4 3 2 1 0

Data out 1 Data out 2

MISO2 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Figure 81: SPI Master Interface Timing and Data Format

The CPOL/CPHA can be configured through the following I 2 C registers. spi_master_cpol , IO Map, Address 0x1A14[1]

This bit is used to select the SPI master clock polarity.

Function spi_master_cpol Description

0 

1

Idle state, clock is low

Idle state, clock is high spi_master_cpha , IO Map, Address 0x1A14[0]

This bit is used to select the SPI master clock phase.


Function spi_master_cpha

0 

1

4.2.9.

OSD Initialization

Description

Negedge used

Posedge used

To configure ADV8003 to use the OSD, the following I 2 C writes are required:

0x1A14=0x0C: SPI mode select

0x1ACE=0x00: SPI bus enable

0x1ACC=0x10: Configure OSD HW int

Further SPI writes are required but these are controlled through the OSD.




5.

SERIAL VIDEO RECEIVER

The Serial Video Rx on the ADV8003KBCZ-8x derivatives can receive video data at rates of up to 3 GHz. This allows support for video formats ranging from SD to 4k x 2k @ 24Hz, 1080p120Hz and 1080p60 3D. The Serial Video Rx on the ADV8003KBCZ-7x derivatives can receive video data at rates of up to 2.25 GHz. This allows support for video formats ranging from SD to 1080p @ 60Hz 12-bit. It is designed for chip-to-chip connection only and, as such, does not offer any DDC lines to facilitate HDCP or EDID operations.

RX_C± PLL

Deep Colour

Conversion

To ADV8003

Digital Core

RX_0±

RX_1±

RX_2±

Sampler

Packet

Processor

Packet/

Infoframe

Memory

Figure 82: Functional Block Diagram of ADV8003 Serial Video Rx

This section outlines the various registers available to the user in the register map which is used to control the Serial Video Rx. These registers are used to configure the ADV8003 to accept input video from a device such as an HDMI transceiver (for example, ADV7623 ) or a front end device with HDMI output (for example, ADV7850 ).

5.1.

+ 5 V DETECT

The Serial Video Rx on the ADV8003 can monitor the level on the +5 V power signal pin. This +5 V signal can be used to reset the Rx section if requested. If +5 V detection is not being used, this pin should be connected to a +5 V supply. The controls for +5 V detection can be found in the following I 2 C registers. These registers are valid even when the part is not processing TMDS information. filt_5v_det_dis , HDMI RX Map, Address 0xE256[7]

This bit is a control to disable the digital glitch filter on the HDMI 5V detect signals. The filtered signals are used as interrupt flags, and also used to reset the HDMI section. The filter works from an internal ring oscillator clock and is therefore available in power-down mode. The clock frequency of the ring oscillator is 42MHz +/-10%.

Note: If the 5 V pins are not used and left unconnected, the 5 V detect circuitry should be disconnected from the HDMI reset signal by setting DIS_CABLE_DET_RST to 1. This avoids holding the HDMI section in reset.

Function filt_5v_det_dis Description

0 

1

Enabled

Disabled

Note : If the +5 V pins are not used and left unconnected, the +5 V detect circuitry should be disconnected from the Rx reset circuitry by setting

dis_cable_det_rst to 1. This avoids holding the Rx section in reset.

filt_5v_det_timer[6:0] , HDMI RX Map, Address 0xE256[6:0]

This bit is a control to set the timer for the digital glitch filter on the HDMI +5 V detect inputs. The unit of this parameter is 2 clock cycles of the ring oscillator (~ 47ns). The input must be constantly high for the duration of the timer, otherwise the filter output remains low. The output of the filter returns low as soon as any change in the +5 V power signal is detected.



Function filt_5v_det_timer[6:0]

1011000  xxxxxxx

Description

Approximately 4.2us

Time duration of +5 V deglitch filter. The unit of this parameter is 2 clock cycles of the ring oscillator (~ 47ns) dis_cable_det_rst , HDMI RX Map, Address 0xE248[6]

This bit disables the reset effects of cable detection. It should be set to 1 if the +5 V pins are unused and left unconnected.

Function dis_cable_det_rst

0 

1

Description

Resets the HDMI section if the 5 V input pin is inactive

Do not use the 5 V input pins as reset signal for the HDMI section

5.2.

TMDS CLOCK ACTIVITY DETECTION

The ADV8003 Serial Video Rx provides circuitry to monitor TMDS clock activity and also the type of data on the Rx input lines. System

software can poll these registers and configure the ADV8003 as required. rb_rx_tmds_clk_det and tmds_pll_locked can be used to

determine if there is a valid clock on the TMDS clock input and if the Serial Video Rx has locked to this. If both of these are true,

rx_hdmi_mode can be used to indicate the video data that is available on the Serial Video Rx, either DVI data or HDMI data.

rx_hdmi_mode , HDMI RX Map, Address 0xE205[7] (Read Only)

This bit is a readback to indicate whether the stream processed by the HDMI core is a DVI or an HDMI stream.

Function rx_hdmi_mode Description

0 

1

DVI mode detected

HDMI mode detected rb_rx_tmds_clk_det , IO Map, Address 0x1ADF[3] (Read Only)

This bit is used to indicate if there is a clock on the HDMI RX input lines.

Function rb_rx_tmds_clk_det

0 

1

Description

No TMDS clock detected on HDMI rx input lines

TMDS clock detected on HDMI rx input lines tmds_pll_locked , HDMI RX Map, Address 0xE204[1] (Read Only)

This is a readback bit to indicate if the TMDS PLL is locked to the TMDS clock input of the selected HDMI port.

Function tmds_pll_locked

0 

1

Description

TMDS PLL not locked

TMDS PLL is locked to the TMDS clock input of the selected HDMI port

Note: The tmds_pll_locked flag should be considered valid if a TMDS clock is input on the Serial Video Rx.


ADV8003 Hardware Manual freqtolerance[3:0] , HDMI RX Map, Address 0xE20D[3:0]

Sets the tolerance in MHz for new TMDS frequency detection. This tolerance is used for the audio mute mask mt_msk_vclk_chng and the HDMI status bit new_tmds_frq_raw.

Function freqtolerance[3:0] Description

0100  xxxx

Default tolerance in MHz for new TMDS frequency detection

Tolerance in MHz for new TMDS frequency detection

5.3.

CLOCK AND DATA TERMINATION CONTROL

The ADV8003 provides the clock_terma_disable control for TMDS clock and data termination on all Serial Video Rx input pins.

clock_terma_disable , HDMI RX Map, Address 0xE283[0]

This control is used to disable clock termination on port A. It can be used when term_auto is set to 0.

Function clock_terma_disable Description

0

1 

Enable termination port A

Disable termination port A

5.4.

AV MUTE STATUS

av_mute is used to indicate the status of the avmute bit in the general control packet. As with the TMDS clock detection bits, this register

bit can be polled by the system software and the appropriate configuration done. av_mute , HDMI RX Map, Address 0xE204[6] (Read Only)

This bit is a readback of the AVMUTE status received in the last General Control packet received.

Function av_mute

0 

1

Description

AVMUTE not set

AVMUTE set

5.5.

DEEP COLOR MODE SUPPORT

The ADV8003 supports HDMI streams with 24-bits per sample and deep color modes. The addition of a video FIFO (refer to Section 5.6

for more details) allows for the robust support of these modes.

The deep color mode information that the ADV8003 extracts from the general control packet can be read back from

deep_color_mode[1:0] . It is possible to override the deep color mode that the ADV8003 unpacks from the video data encapsulated in the

processed HDMI stream. This is achieved by configuring the override_deep_color_mode and deep_color_mode_user[1:0] controls.

deep_color_mode[1:0] , HDMI RX Map, Address 0xE20B[7:6] (Read Only)

This is a readback of the deep color mode information extracted from the general control packet.



Function deep_color_mode[1:0]

00 

01

10

11

Description

8-bits per channel

10-bits per channel

12-bits per channel

16-bits per channel (not supported) override_deep_color_mode , HDMI RX Map, Address 0xE240[6]

This bit is used to override the deep color mode

Function override_deep_color_m ode

0 

Description

1

HDMI section unpacks video data according to deep color information extracted from the

General Control packets (normal operation)

Override deep color mode extracted from General Control Packet. HDMI section unpacks video data according to the deep color mode set in DEEP_COLOR_MODE_USER[1:0] deep_color_mode_user[1:0] , HDMI RX Map, Address 0xE240[5:4]

This signal is used to manually set the deep color mode. The value set in this register is effective when

OVERRIDE_DEEP_COLOR_MODE is set to 1.

Function deep_color_mode_user

[1:0]

Description

00 

01

10

11

8 bits per channel

10 bits per channel

12 bits per channel

16 bits per channel (not supported)

Notes:

• Deep color mode can be monitored via the deepcolor_mode_chng edge sensitive interrupt in the IO Map, which indicates if the color depth of the processed stream has changed.

• The ADV8003 can be configured to trigger an interrupt when the deepcolor_mode_chng edge sensitive interrupt in the IO Map changes from 0 to 1.

5.6.

VIDEO FIFO

The ADV8003 contains a FIFO located after the TMDS decoding block (refer to Figure 83 ). Data arriving into the Serial Video Rx will be

at 1X rate for non deep color modes (8-bits per channel), and 1.25X, 1.5X, or 2X for deep color modes (30, 36 and 48 bits respectively).

Data unpacking and data rate reduction must be performed on the incoming data to provide the ADV8003 digital core with the correct data rate and data bit width. The video FIFO is used to pass data safely across the clock domains.



T M D S

C lo c k

T M D S

P L L

D iv id e r

D P L L

T M D S

C h a n n e l 0

T M D S

C h a n n e l 1

T M D S

C h a n n e l 2

+

-

+

-

T M D S C h 0

T M D S

S a m p lin g a n d

D a ta

1 0

T M D S C h 1

1 0

R e c o v e r y T M D S C h 2

1 0

T M D S

D e c o d in g

R

G

1 2

1 2

B

1 2

H S

V S

D E

F IF O

R

G

1 2

B

1 2

1 2

H S

V S

D E

Figure 83: HDMI Video FIFO

The video FIFO is designed to operate completely autonomously. It automatically resynchronizes the read and write pointers if they are about to point to the same location. However, it is also possible for the user to observe and control the FIFO operation with a number of

FIFO control and status registers described below. dcfifo_level[2:0] , HDMI RX Map, Address 0xE21C[2:0] (Read Only)

This signal is a readback to indicate the distance between the read and write pointers. Overflow and underflow will read as level 0. The ideal centered functionality will read as 0b100.

Function dcfifo_level[2:0]

000 

001

010

011

100

101

110

111

Description

FIFO has underflowed or overflowed

FIFO is about to overflow

FIFO has some margin


FIFO perfectly balanced



FIFO is about to underflow dcfifo_locked , HDMI RX Map, Address 0xE21C[3] (Read Only)

This bit is a readback to indicate if the Video FIFO is locked.

Function dcfifo_locked Description

0 

1

Video FIFO is not locked. Video FIFO had to resynchronize between previous two VSyncs

Video FIFO is locked. Video FIFO did not have to resynchronize between previous two VSyncs dcfifo_recenter , HDMI RX Map, Address 0xE25A[2] (Self-Clearing)

This bit is used as a reset to recenter the Video FIFO. This is a self clearing bit.

Function dcfifo_recenter

0 

1

Description

Video FIFO normal operation

Video FIFO to re-centre


ADV8003 Hardware Manual dcfifo_kill_dis , HDMI RX Map, Address 0xE21B[2]

This bit sets the Video FIFO output to zero if there is more than one resynchronization of the pointers within 2 FIFO cycles. This behavior can be disabled with this bit.

Function dcfifo_kill_dis Description

0 

1

FIFO output set to zero if more than one resynchronization is necessary during two FIFO cycles

FIFO output never set to zero regardless of how many resynchronizations occur dcfifo_kill_not_locked , HDMI RX Map, Address 0xE21B[3]

This bit controls whether or not the output of the Video FIFO is set to zero when the video PLL is unlocked.

Function dcfifo_kill_not_locked Description

0

1 

FIFO data is output regardless of video PLL lock status

FIFO output is zeroed if video PLL is unlocked

The DCFIFO is programmed to reset itself automatically when the video PLL transitions from unlocked to locked. Note that the video

PLL transition does not necessarily indicate that the overall system is stable. dcfifo_reset_on_lock , HDMI RX Map, Address 0xE21B[4]

This bit enables the reset/re-centering of video FIFO on video PLL unlock.

Function dcfifo_reset_on_lock Description

0

1 

Do not reset on video PLL lock

Reset FIFO on video PLL lock

5.7.

PIXEL REPETITION

In HDMI mode, video formats with TMDS rates below 25 Mpixels/s require pixel repetition in order to be transmitted over the serial video link. When the ADV8003 receives this type of video format, it discards repeated pixel data automatically, based on the pixel repetition field available in the AVI InfoFrame.

When

hdmi_pixel_repetition[3:0] is non zero, video pixel data is discarded and the pixel clock frequency is divided by

hdmi_pixel_repetition + 1. hdmi_pixel_repetition[3:0] , HDMI RX Map, Address 0xE205[3:0] (Read Only)

This is a readback signal to indicate the current HDMI pixel repetition value decoded from the AVI InfoFrame received. The HDMI Rx automatically discards repeated pixel data and divides the pixel clock frequency appropriately as per the pixel repetition value.



Function hdmi_pixel_repetition[

3:0]

0000 

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010 - 1111

Description

5x

6x

7x

8x

1x

2x

3x

4x

9x

10x

Reserved derep_n_override , HDMI RX Map, Address 0xE241[4]

This bit allows the user to override the pixel repetition factor. DEREP_N is then used instead of hdmi_pixel_repetition[3:0] to discard video pixel data from the incoming HDMI stream.

Function derep_n_override

0 

1

Description

Automatic detection and processing of pixel repeated modes using the AVI InfoFrame information

Enables manual setting of the pixel repetition factor as per DEREP_N[3:0] derep_n[3:0] , HDMI RX Map, Address 0xE241[3:0]

This signal sets the derepetition value if DEREP_N_OVERRIDE is set to 1.

Function derep_n[3:0] Description

0000  xxxx

DEREP_N+1 indicates the pixel and clock discard factor

DEREP_N+1 indicates the pixel and clock discard factor

5.8.

SYNC SIGNAL POLARITY READBACKS

These signals are used to indicate the polarity of the synchronization signals input to the Serial Video Rx input. dvi_hsync_polarity , HDMI RX Map, Address 0xE205[5] (Read Only)

This bit is a readback to indicate the polarity of the HSync encoded in the input stream.

Function dvi_hsync_polarity Description

0 

1

HSync active low

HSync active high


Data

Enable a b c d e

HSYNC a Total number of pixels per line b Active number of pixels per line c HSync front porch width in pixel unit d HSync width in pixel unit e HSync back porch width in pixel unit

Figure 84: Horizontal Timing Parameters dvi_vsync_polarity , HDMI RX Map, Address 0xE205[4] (Read Only)

This bit is a readback to indicate the polarity of the VSync encoded in the input stream.

Function dvi_vsync_polarity

0 

1

Description

VSync active low

VSync active high a b

Data

Enable


HSYNC c d e

VSYNC a d e b c

Total number of lines in field 0. Unit is in half lines.

Actives number of lines in field 0. Unit is in lines.

VSync front porch width in field 0. Unit is in half lines.

VSync pulse width in field 0. Unit is in half lines.

VSync back porch width in field 0. Unit is in half lines.

Figure 85: Vertical Parameters for Field 0

Note : Field 1 measurements should not be used for progressive video modes.



5.9.

INFOFRAME REGISTERS

In HDMI, the auxiliary data is carried across the digital link using a series of packets. The ADV8003 Serial Video Rx can automatically detect and store the following HDMI packets:

• InfoFrames

• Audio content protection

• International Standard Recording Code (ISRC)

• Gamut metadata

Section 5.9.1 explains the method through which the ADV8003 can extract and store these InfoFrames.

5.9.1.

InfoFrame Collection Mode

The ADV8003 has two modes for storing the InfoFrame packets sent from the source into the internal memory. By default, the ADV8003 only stores the InfoFrame packets received if the checksum is correct for each InfoFrame.

The ADV8003 also provides a mode to store every InfoFrame sent from the source, regardless of an InfoFrame packet checksum error.

This can be configured by setting always_store_inf to 1.

always_store_inf , HDMI RX Map, Address 0xE247[0]

This bit is used to force InfoFrames with checksum errors to be stored.

Function always_store_inf Description

0 

1

Stores data from received InfoFrames only if their checksum is correct

Always store the data from received InfoFrame regardless of their checksum

5.9.2.

InfoFrame Checksum Error Flags

To determine if a checksum error has occurred with the InfoFrame packets, the user can poll the various status bits in the IO Map. There are several interrupt flags in the IO Map which indicate the status of the various InfoFrames. Refer to

Section 9.2.2 for more details on the

Serial Video Rx interrupts.



5.9.3.

AVI InfoFrame Registers

Table 38 provides a list of readback registers for the AVI InfoFrame data. Refer to the EIA/CEA-861 specifications for a detailed

explanation of the AVI InfoFrame fields.

Table 38: AVI InfoFrame Registers

Access Type Register Name Byte Name

1

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R/W

R

0xE307

0xE308

0xE309

0xE30A

0xE30B

0xE30C

0xE30D

0xE30E

0xE30F

0xE310

0xE311

0xE312

0xE313

0xE314

InfoFrame

Map Address

0xE3E0

0xE3E1

0xE3E2

0xE300

0xE301

0xE302

0xE303

0xE304

0xE305

0xE306

0xE315

0xE316

0xE317

0xE318

0xE319

0xE31A

avi_packet_id[7:0]

avi_inf_ver avi_inf_len avi_inf_pb_0_1 avi_inf_pb_0_2 avi_inf_pb_0_3 avi_inf_pb_0_4 avi_inf_pb_0_5 avi_inf_pb_0_6 avi_inf_pb_0_7 avi_inf_pb_0_8 avi_inf_pb_0_9 avi_inf_pb_0_10 avi_inf_pb_0_11 avi_inf_pb_0_12 avi_inf_pb_0_13 avi_inf_pb_0_14 avi_inf_pb_0_15 avi_inf_pb_0_16 avi_inf_pb_0_17 avi_inf_pb_0_18 avi_inf_pb_0_19 avi_inf_pb_0_20 avi_inf_pb_0_21 avi_inf_pb_0_22 avi_inf_pb_0_23 avi_inf_pb_0_24 avi_inf_pb_0_25 avi_inf_pb_0_26 avi_inf_pb_0_27

0xE31B R avi_inf_pb_0_28 Data Byte 27

1 As defined by the EIA/CEA-861 specifications

The AVI InfoFrame registers are considered valid if the following two conditions are met:

• avi_infoframe_det is 1.

•

avi_inf_cksum_err is 0. This condition applies only if always_store_inf is set to 1.

Packet Type Value

InfoFrame version number

InfoFrame length

Checksum

Data Byte 1

Data Byte 2

Data Byte 3

Data Byte 4

Data Byte 5

Data Byte 6

Data Byte 7

Data Byte 8

Data Byte 9

Data Byte 10

Data Byte 11

Data Byte 12

Data Byte 13

Data Byte 14

Data Byte 15

Data Byte 16

Data Byte 17

Data Byte 18

Data Byte 19

Data Byte 20

Data Byte 21

Data Byte 22

Data Byte 23

Data Byte 24

Data Byte 25

Data Byte 26



5.9.4.

SPD InfoFrame Registers

Table 39 provides a list of readback registers available for the SPD InfoFrame. Refer to the EIA/CEA-861 specifications for a detailed

explanation of the SPD InfoFrame fields.

spd_packet_id[7:0]

spd_inf_ver spd_inf_len spd_inf_pb_0_1 spd_inf_pb_0_2 spd_inf_pb_0_3 spd_inf_pb_0_4 spd_inf_pb_0_5 spd_inf_pb_0_6 spd_inf_pb_0_7 spd_inf_pb_0_8 spd_inf_pb_0_9 spd_inf_pb_0_10 spd_inf_pb_0_11 spd_inf_pb_0_12 spd_inf_pb_0_13 spd_inf_pb_0_14 spd_inf_pb_0_15 spd_inf_pb_0_16 spd_inf_pb_0_17 spd_inf_pb_0_18 spd_inf_pb_0_19 spd_inf_pb_0_20 spd_inf_pb_0_21 spd_inf_pb_0_22 spd_inf_pb_0_23 spd_inf_pb_0_24 spd_inf_pb_0_25 spd_inf_pb_0_26 spd_inf_pb_0_27

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

Access

Type

R/W

R

0xE331

0xE332

0xE333

0xE334

0xE335

0xE336

0xE337

0xE338

0xE339

0xE33A

0xE33B

0xE33C

0xE33D

0xE33E

InfoFrame

Map Address

0xE3E6

0xE3E7

0xE3E8

0xE32A

0xE32B

0xE32C

0xE32D

0xE32E

0xE32F

0xE330

0xE33F

0xE340

0xE341

0xE342

0xE343

0xE344

Table 39: SPD InfoFrame Registers

Register Name Byte Name 1

0xE345 R spd_inf_pb_0_28 Data Byte 27


The Source Product Descriptor (SPD) InfoFrame registers are considered valid if the following two conditions are met:

• spd_infoframe_det is 1.

•

spd_inf_cksum_err is 0. This condition only applies if always_store_inf is set to 1.

Packet Type Value


InfoFrame length

Checksum

Data Byte 1

Data Byte 2

Data Byte 3

Data Byte 4

Data Byte 5

Data Byte 6

Data Byte 7

Data Byte 8

Data Byte 9

Data Byte 10

Data Byte 11

Data Byte 12

Data Byte 13

Data Byte 14

Data Byte 15

Data Byte 16

Data Byte 17

Data Byte 18

Data Byte 19

Data Byte 20

Data Byte 21

Data Byte 22

Data Byte 23

Data Byte 24

Data Byte 25

Data Byte 26



5.9.5.

MPEG Source InfoFrame Registers

Table 40 provides a list of readback registers available for the MPEG InfoFrame. Refer to the EIA/CEA-861 specifications for a detailed

explanation of the MPEG InfoFrame fields.

InfoFrame

Map Address

0xE3E9

0xE3EA

0xE3EB

0xE346

0xE347

0xE348

0xE349

0xE34A

0xE34B

0xE34C

0xE34D

0xE34E

0xE34F

0xE350

0xE351

0xE352

R

R

R

R

R

R

R

R

R

R

R

R

R

R

Access

Type

R/W

R

Table 40: MPEG InfoFrame Registers

Register Name Byte Name 1

ms_packet_id[7:0]

ms_inf_vers ms_inf_len ms_inf_pb_0_1 ms_inf_pb_0_2 ms_inf_pb_0_3 ms_inf_pb_0_4 ms_inf_pb_0_5 ms_inf_pb_0_6 ms_inf_pb_0_7 ms_inf_pb_0_8 ms_inf_pb_0_9 ms_inf_pb_0_10 ms_inf_pb_0_11 ms_inf_pb_0_12 ms_inf_pb_0_13

0xE353 R ms_inf_pb_0_14 Data Byte 13


• The MPEG InfoFrame registers are considered valid if the following two conditions are met: ms_infoframe_det is 1.

•

ms_inf_cksum_err is 0. This condition applies only if always_store_inf is set to 1.

Packet Type Value


InfoFrame length

Checksum

Data Byte 1

Data Byte 2

Data Byte 3

Data Byte 4

Data Byte 5

Data Byte 6

Data Byte 7

Data Byte 8

Data Byte 9

Data Byte 10

Data Byte 11

Data Byte 12

5.9.6.

Vendor Specific InfoFrame Registers

Table 41 provides a list of readback registers available for the Vendor Specific InfoFrame.

R/W

Table 41: VS InfoFrame Registers

Register Name Byte Name InfoFrame

Map Address

0xE3EC

0xE3ED

0xE3EE

0xE354

0xE355

0xE356

0xE357

0xE358

0xE359

0xE35A

0xE35B

0xE35C

0xE35D

0xE35E

R

R

R

R

R

R

R

R

R

R

R

R

R

R

vs_packet_id[7:0]

vs_inf_vers vs_inf_len vs_inf_pb_0_1 vs_inf_pb_0_2 vs_inf_pb_0_3 vs_inf_pb_0_4 vs_inf_pb_0_5 vs_inf_pb_0_6 vs_inf_pb_0_7 vs_inf_pb_0_8 vs_inf_pb_0_9 vs_inf_pb_0_10 vs_inf_pb_0_11

Packet Type Value


InfoFrame length

Checksum

Data Byte 1

Data Byte 2

Data Byte 3

Data Byte 4

Data Byte 5

Data Byte 6

Data Byte 7

Data Byte 8

Data Byte 9

Data Byte 10



InfoFrame

Map Address

0xE35F

0xE360

0xE361

0xE362

0xE363

0xE364

0xE365

0xE366

0xE367

0xE368

0xE369

0xE36A

0xE36B

0xE36C

0xE36D

0xE36E

0xE36F

R/W

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

Register Name vs_inf_pb_0_12 vs_inf_pb_0_13 vs_inf_pb_0_14 vs_inf_pb_0_15 vs_inf_pb_0_16 vs_inf_pb_0_17 vs_inf_pb_0_18 vs_inf_pb_0_19 vs_inf_pb_0_20 vs_inf_pb_0_21 vs_inf_pb_0_22 vs_inf_pb_0_23 vs_inf_pb_0_24 vs_inf_pb_0_25 vs_inf_pb_0_26 vs_inf_pb_0_27 vs_inf_pb_0_28

Byte Name

Data Byte 11

Data Byte 12

Data Byte 13

Data Byte 14

Data Byte 15

Data Byte 16

Data Byte 17

Data Byte 18

Data Byte 19

Data Byte 20

Data Byte 21

Data Byte 22

Data Byte 23

Data Byte 24

Data Byte 25

Data Byte 26

Data Byte 27

The Vendor Specific InfoFrame registers are considered valid if the following two conditions are met:

• vs_infoframe_det is 1.

•

vs_inf_cksum_err is 0. This condition applies only if always_store_inf is set to 1.

5.10.

PACKET REGISTERS

5.10.1.

ISRC Packet Registers

Table 42

and Table 43 provide lists of the readback registers available for the ISRC packets. Refer to the HDMI 1.4 specifications for a

detailed explanation of the ISRC packet fields.

R/W

Table 42: ISRC1 Packet Registers

Register Name Packet Byte No.

1

Rev. B, August 2013

0x90

0x91

0x92

0x93

0x94

0x95

0x96

0x97

InfoFrame

Map Address

0xF2

0xF3

0xF4

0x8C

0x8D

0x8E

0x8F

0x98

0x99

0x9A

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R/W

R

isrc1_packet_id[7:0]

isrc1_header1 isrc1_header2 isrc1_pb_0_1 isrc1_pb_0_2 isrc1_pb_0_3 isrc1_pb_0_4 isrc1_pb_0_5 isrc1_pb_0_6 isrc1_pb_0_7 isrc1_pb_0_8 isrc1_pb_0_9 isrc1_pb_0_10 isrc1_pb_0_11 isrc1_pb_0_12 isrc1_pb_0_13 isrc1_pb_0_14 isrc1_pb_0_15

239

PB5

PB6

PB7

PB8

PB9

PB10

PB11

PB12

PB13

PB14

Packet Type Value

HB1

HB2

PB0

PB1

PB2

PB3

PB4


InfoFrame

Map Address

0x9B

0x9C

0x9D

0x9E

0x9F

0xA0

0xA1

0xA2

0xA3

0xA4

0xA5

0xA6

R/W

R

R

R

R

R

R

R

R

R

R

R

R

Register Name isrc1_pb_0_16 isrc1_pb_0_17 isrc1_pb_0_18 isrc1_pb_0_19 isrc1_pb_0_20 isrc1_pb_0_21 isrc1_pb_0_22 isrc1_pb_0_23 isrc1_pb_0_24 isrc1_pb_0_25 isrc1_pb_0_26 isrc1_pb_0_27

Packet Byte No.

1

PB15

PB16

PB17

PB18

PB19

PB20

PB21

PB22

PB23

PB24

PB25

PB26

0xA7 R isrc1_pb_0_28 PB27

1 As defined by the HDMI 1.4 specifications

The ISRC1 packet registers are considered valid if rx_isrc1_pckt_edge_raw is set to 1. isrc1_pckt_raw , IO, Address 0x60[6] (Read Only)

This read-back indicates the raw status signal of the International Standard Recording Code 1 (ISRC1) packet detection signal. This bit resets to 0 after an HDMI packet detection reset or upon writing to isrc1_packet_id.

Function isrc1_pckt_raw Description

0 

1

No ISRC1 packets received since last HDMI packet detection reset.

ISRC1 packets received.

R/W

Table 43: ISRC2 Packet Registers


1 InfoFrame

Map Address

0xE3F5

0x E3F6

0x E3F7

0x E3A8

0x E3A9

0x E3AA

0x E3AB

0x E3AC

0x E3AD

0x E3AE

0x E3AF

0x E3B0

0x E3B1

0x E3B2

0x E3B3

0x E3B4

0x E3B5

0x E3B6

0x E3B7

R/W

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

isrc2_packet_id[7:0]

isrc2_header1 isrc2_header2 isrc2_pb_0_1 isrc2_pb_0_2 isrc2_pb_0_3 isrc2_pb_0_4 isrc2_pb_0_5 isrc2_pb_0_6 isrc2_pb_0_7 isrc2_pb_0_8 isrc2_pb_0_9 isrc2_pb_0_10 isrc2_pb_0_11 isrc2_pb_0_12 isrc2_pb_0_13 isrc2_pb_0_14 isrc2_pb_0_15 isrc2_pb_0_16

Packet Type Value

PB6

PB7

PB8

PB9

PB10

PB11

PB12

PB13

PB14

PB15

HB1

HB2

PB0

PB1

PB2

PB3

PB4

PB5


InfoFrame

Map Address

0x E3B8

0x E3B9

0x E3BA

0x E3BB

0x E3BC

0x E3BD

0x E3BE

0x E3BF

0x E3C0

0x E3C1

0x E3C2

0x E3C3


R/W

R

R

R

R

R

R

R

R

R

R

R

R

Register Name isrc2_pb_0_17 isrc2_pb_0_18 isrc2_pb_0_19 isrc2_pb_0_20 isrc2_pb_0_21 isrc2_pb_0_22 isrc2_pb_0_23 isrc2_pb_0_24 isrc2_pb_0_25 isrc2_pb_0_26 isrc2_pb_0_27 isrc2_pb_0_28

Packet Byte No.

1

PB16

PB17

PB18

PB19

PB20

PB21

PB22

PB23

PB24

PB25

PB26

PB27

The ISRC2 packet registers are considered valid if, and only if rx_isrc2_pckt_edge_raw is set to 1.

5.10.2.

Gamut Metadata Packets

Refer to the HDMI 1.3/1.4 specifications for a detailed explanation of the Gamut Metadata packet fields.

R/W

Table 44: Gamut Metadata Packet Registers


1

Rev. B, August 2013

0xE3CB

0xE3CC

0xE3CD

0xE3CE

0xE3CF

0xE3D0

0xE3D1

0xE3D2

0xE3D3

0xE3D4

0xE3D5

0xE3D6

HDMI

Map Address

0xE3F8

0xE3F9

0xE3FA

0xE3C4

0xE3C5

0xE3C6

0xE3C7

0xE3C8

0xE3C9

0xE3CA

0xE3D7

0xE3D8

0xE3D9

0xE3DA

0xE3DB

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R/W

R

gamut_packet_id[7:0]

gamut_header1 gamut_header2 gamut_mdata_pb_0_1 gamut_mdata_pb_0_2 gamut_mdata_pb_0_3 gamut_mdata_pb_0_4 gamut_mdata_pb_0_5 gamut_mdata_pb_0_6 gamut_mdata_pb_0_7 gamut_mdata_pb_0_8 gamut_mdata_pb_0_9 gamut_mdata_pb_0_10 gamut_mdata_pb_0_11 gamut_mdata_pb_0_12 gamut_mdata_pb_0_13 gamut_mdata_pb_0_14 gamut_mdata_pb_0_15 gamut_mdata_pb_0_16 gamut_mdata_pb_0_17 gamut_mdata_pb_0_18 gamut_mdata_pb_0_19 gamut_mdata_pb_0_20 gamut_mdata_pb_0_21 gamut_mdata_pb_0_22 gamut_mdata_pb_0_23 gamut_mdata_pb_0_24

241

PB13

PB14

PB15

PB16

PB17

PB18

PB7

PB8

PB9

PB10

PB11

PB12

PB2

PB3

PB4

PB5

PB6

Packet Type Value

HB1

HB2

PB0

PB1

PB19

PB20

PB21

PB22

PB23



HDMI

Map Address

0xE3DC

R/W

R

Register Name gamut_mdata_pb_0_25

Packet Byte No.

1

PB24

0xE3DD

0xE3DE

R

R gamut_mdata_pb_0_26 gamut_mdata_pb_0_27

PB25

PB26

0xE3DF R gamut_mdata_pb_0_28 PB27


The Gamut Metadata packet registers are considered valid if pkt_det_gamut is set to 1 (refer to

Section 9.2.2 for more details).

gamut_irq_next_field , HDMI RX Map, Address 0xE250[4]

This bit is used to set the new_gamut_mdata_raw interrupt to detect when new contents are applicable to the next field or to indicate that the Gamut packet is new. This is done using header information of the gamut packet.

Function gamut_irq_next_field

0 

1

Description

Interrupt flag indicates that Gamut packet is new

Interrupt flag indicates that Gamut packet is to be applied to next field

5.11.

CUSTOMIZING PACKET/INFOFRAME STORAGE REGISTERS

The packet type value of each set of packet and InfoFrame registers in the Serial Video Rx InfoFrame Map is programmable. This allows the user to configure the ADV8003 to store the payload data of any packet and InfoFrames sent by the transmitter connected on the Serial

Video Rx port.

Note : Writing to any of the following packet ID registers also clears the corresponding InfoFrame/packet detection bit. avi_packet_id[7:0] , HDMI RX Infoframe Map, Address 0xE3E0[7:0]

This siganl is a readback of the AVI InfoFrame ID.

Function avi_packet_id[7:0] Description

0xxxxxxx

1xxxxxxx

Packet type value of packet stored in InfoFrame Map, Address 0x00 to 0x1B

Packet type value of InfoFrame stored in InfoFrame Map, Address 0x00 to 0x1B spd_packet_id[7:0] , HDMI RX Infoframe Map, Address 0xE3E6[7:0]

This signal is a readback of the Source Product Descriptor InfoFrame ID

Function spd_packet_id[7:0] Description

0xxxxxxx

1xxxxxxx

Packet type value of packet stored in InfoFrame Map, Address 0x2A to 0x45

Packet type value of InfoFrame stored in InfoFrame Map, Address 0x2A to 0x45 aud_packet_id[7:0] , HDMI RX Infoframe Map, Address 0xE3E3[7:0]

This signal is a readback of the Audio InfoFrame ID.



Function aud_packet_id[7:0]

0xxxxxxx

1xxxxxxx

Description

Packet type value of packet stored in InfoFrame Map, Address 0x1C to 0x29

Packet type value of InfoFrame stored in InfoFrame Map, Address 0x1C to 0x29 ms_packet_id[7:0] , HDMI RX Infoframe Map, Address 0xE3E9[7:0]

This signal is a readback of the MPEG Source InfoFrame ID.

Function ms_packet_id[7:0] Description

0xxxxxxx

1xxxxxxx

Packet type value of packet stored in InfoFrame Map, Address 0x46 to 0x53

Packet type value of InfoFrame stored in InfoFrame Map, Address 0x46 to 0x53 vs_packet_id[7:0] , HDMI RX Infoframe Map, Address 0xE3EC[7:0]

This signal is a readback of the Vendor Specific InfoFrame ID.

Function vs_packet_id[7:0] Description

0xxxxxxx

1xxxxxxx

Packet type value of packet stored in InfoFrame Map, Address 0x54 to 0x6F

Packet type value of packet stored in InfoFrame Map, Address 0x54 to 0x6F acp_packet_id[7:0] , HDMI RX Infoframe Map, Address 0xE3EF[7:0]

This signal is a readback of the ACP Packet ID.

Function acp_packet_id[7:0]

0xxxxxxx

1xxxxxxx

Description

Packet type value of packet stored in InfoFrame Map, Address 0x70 to 0x8B

Packet type value of InfoFrame stored in InfoFrame Map, Address 0x70 to 0x8B isrc1_packet_id[7:0] , HDMI RX Infoframe Map, Address 0xE3F2[7:0]

This signal is a readback of the ISRC1 Packet ID.

Function isrc1_packet_id[7:0]

0xxxxxxx

1xxxxxxx

Description

Packet type value of packet stored in InfoFrame Map, Address 0x8C to 0xA7

Packet type value of InfoFrame stored in InfoFrame Map, Address 0x8C to 0xA7 isrc2_packet_id[7:0] , HDMI RX Infoframe Map, Address 0xE3F5[7:0]

This signal is a readback of the ISRC2 Packet ID.

Function isrc2_packet_id[7:0]

0xxxxxxx

Description

Packet type value of packet stored in InfoFrame Map, Address 0xA8 to 0xC3

1xxxxxxx Packet type value of InfoFrame stored in InfoFrame Map, Address 0xA8 to 0xC3 gamut_packet_id[7:0] , HDMI RX Infoframe Map, Address 0xE3F8[7:0]

This signal is a readback of the Gamut Metadata Packet ID.



Function gamut_packet_id[7:0]

0xxxxxxx

1xxxxxxx

Description

Packet type value of packet stored in InfoFrame Map, Address 0xC4 to 0xDF

Packet type value of InfoFrame stored in InfoFrame Map, Address 0xC4 to 0xDF

Note : The packet type values and corresponding packets should not be programmed in the packet type values registers. The general control packet (0x03) is always processed internally and cannot be stored in the packet/InfoFrame registers in the InfoFrame Map.

5.12.

HDMI SECTION RESET STRATEGY

The following reset strategy is implemented for the HDMI section:

•

Global chip reset – This means the ADV8003 Serial Video Rx core can be reset using the rx_reset

or main_reset . A global chip

reset is triggered by asserting the RESET pin to a low level. The HDMI section is reset when a global reset is triggered.

• Loss of TMDS clock or 5 V signal reset – A loss of TMDS clock or 5 V signal to the Serial Video Rx resets the entire Serial Video

Rx section. The loss of a 5 V signal condition is discarded if dis_cable_det_rst is set high.

• DVI mode reset – The packet processing block, including InfoFrame memory, is held in reset when the Serial Video Rx processes a DVI stream.



6.

HDMI TRANSMITTER

The HDMI transmitters on the ADV8003 are capable of outputting video data at up to 3 GHz (ADV8003KBCZ-8/8B/8C only) and support 3D video output, ARC, CEC and audio output.

Note that the 3 GHz transmitter variants of ADV8003 are the following:

• ADV8003KBCZ-8

• ADV8003KBCZ-8B

• ADV8003KBCZ-8C

The 2.25 GHz transmitter variants of ADV8003 are the following:

• ADV8003KBCZ-7

• ADV8003KBCZ-7B

• ADV8003KBCZ-7C

The dual transmitter variants of ADV8003 are the following:

• ADV8003KBCZ-8/7


The single transmitter variants of ADV8003 are the ADV8003KBCZ-8B/7B. The ADV8003KBCZ-7T does not feature any HDMI transmitters.

Figure 86: Functional Block Diagram of HDMI Tx Core

The ADV8003 contains two HDMI transmitters. As these two HDMI transmitters can be configured independently, there are separate

register maps for both the HDMI Tx1 and HDMI Tx2. The addresses for these register maps are listed in Table 45 .

Table 45: HDMI Transmitter Memory Addresses

Register Map Register Map Address

HDMI Tx1 Main Map 0xEC00 – 0xECFF

HDMI Tx1 EDID Map

HDMI Tx1 CEC Map

HDMI Tx1 UDP Map

HDMI Tx1 Test Map

HDMI Tx2 Main Map

0xEE00 – 0xEEFF

0xF000 – 0xF0FF

0xF200 – 0xF2FF

0xF300 – 0xF3FF

0xF400 – 0xF4FF



Register Map

HDMI Tx2 EDID Map

HDMI Tx2 CEC Map

HDMI Tx2 UDP Map

Register Map Address

0xF600 – 0xF6FF

0xF800 – 0xF8FF

0xFA00 – 0xFAFF

HDMI Tx2 Test Map 0xFB00 – 0xFBFF

It should be noted that the section on the HDMI transmitter, while referring to HDMI Tx1, also equally applies to HDMI Tx2. The same

register bits and controls as per Table 45 apply for both transmitters.

6.1.

GENERAL CONTROLS

To operate the HDMI Tx core, it is necessary to monitor the Hot Plug Detect (HPD) signal from the downstream sink and power up the

Tx core after the appropriate HPD becomes high. To power up the Tx core, system_pd must be programmed to 0 when the HPD_TX1 pin is high. The status of the HPD_TX1 pin is provided via hpd_state .

Some registers cannot be written to when the signal on the HPD_TXx input pin is low. When the level on the HPD_TX1 pin goes from high to low, some registers will be reset to their default value.

The best method to determine when the level of the signal on the HPD_TXx pin is high is to use the interrupt system. An interrupt can be

enabled to notify level change on the HPD_TXx pin (refer to Section 8 for more details regarding the ADV8003 interrupts).

The ADV8003 also features a rx_sense_state status bit which can be used to detect the presence of TMDS clock terminations from the

sink. If the ADV8003 detects a voltage level higher than 1.8 V on the clock lines of its TMDS output port, rx_sense_int is triggered and

rx_sense_state is set to 1.

The detection of TMDS clock terminations from downstream sink devices is useful to delay powering up the transmitter sections until the downstream sink devices are actually ready to receive signals. A typical implementation for a sink is to tie the transmitter 5 V power signal to HPD through a series resistor. In this case, the ADV8003 will detect a high level on HPD_TX1 (HPD_TX2 for HDMI Tx 2) regardless of whether or not the downstream sink is powered on and ready to receive a TMDS stream. For this reason, it is best to wait for both the

rx_sense_state

and hpd_state to be high before powering up the Tx core when trying to achieve minimum power consumption.

system_pd , TX2 Main Map, Address 0xF441[6]

This bit is used to power down the Tx.

Function system_pd Description

0

1 

Normal operation

Power down Tx hpd_state , TX2 Main Map, Address 0xF442[6] (Read Only)

This bit is used to read back the state of the hot plug detect.

Function hpd_state Description

0 

1

Hot Plug Detect inactive (low)

Hot Plug active (high) hpd_override[1:0] , TX2 Main Map, Address 0xF49F[5:4]

This signal is used to select the source of the internal HPD signal.



Function hpd_override[1:0]

00 

01

10

11

Description

HPD from HPD pin and CDC HPD

HPD from CDC HPD

HPD from HPD pin

HPD set to 1 rx_sense_state , TX2 Main Map, Address 0xF442[5] (Read Only)

This bit is used to readback the state of the Rx sense.

Function rx_sense_state

0 

1

Description

HDMI clock termination not detected

HDMI clock termination detected rx_sense_pd , TX2 Main Map, Address 0xF4E6[2]

This bit is used to enable the termination sense power down.

Function rx_sense_pd

0 

1

Description

Termination Sense Monitoring Enabled

Termination Sense Monitoring Disabled

Note

: rx_sense_pd should not be applied during the configuration of the HDMI Tx as it disables an oscillator required to complete the configuration of the TMDS output clock channel. It is recommended to use rx_sense_pd

when the HDMI Tx has been completely configured.

6.2.

RESET STRATEGY

The HDMI Tx, and subsections of it, can be reset in a number of ways. Table 46 , Table 47

and Table 48 describe how each of the HDMI Tx

maps are reset in response to a number of different events.

0x00 – 0x91

0x92 – 0x97

0x98 – 0xAE

0xAF – 0xBD

0xBE – 0xCF

0xD0 – 0xFE

IO Map

tx1_reset

Reset

Reset

Reset

Reset

Reset

Reset

IO Map

Table 46: HDMI Tx Main Map Reset Strategy

IO Map TX Main

Map

TX Main

Map

0x1AFC[7]

main_reset

system_pd

0xEC98[4]

0xF498[4]

Reset Reset

Reset

Reset

Reset

Reset

Reset

Reset

Reset

Event

Tx Hot Plug

Reset

Event

Reset Pin

Reset

Reset

Reset

Reset

Reset

Reset

IO Map

tx1_reset

IO Map

Table 47: HDMI Tx CEC Map Reset Strategy

IO Map TX Main

Map

TX Main

Map

0x1AFC[7]

main_reset

system_pd

0xEC98[4]

0xF498[4]

Reset Reset

Event

Tx Hot Plug

Event

Reset Pin

Reset 0x00 – 0xFF

Rev. B, August 2013

Reset

247


0x00 – 0xFF

IO Map

tx1_reset

Reset

IO Map

Table 48: HDMI Tx Packet Map Reset Strategy

IO Map TX Main

Map

TX Main

Map

0x1AFC[7]

Reset

main_reset

Reset

system_pd

0xEC98[4]

0xF498[4]

Event

Tx Hot Plug

Reset

Event

Reset Pin

Reset

6.3.

HDMI DVI SELECTION

The HDMI Tx core supports the transmission of both HDMI and DVI streams. The type of stream the ADV8003 transmits is set via

hdmi_mode_sel . In DVI transmission mode, no packets will be sent and all registers relating to packets and InfoFrames will be disregarded. The current transmission mode can be confirmed by reading hdmi_mode .

hdmi_mode_sel , TX2 Main Map, Address 0xF4AF[2]

HDMI Mode enable.

Function hdmi_mode_sel

0

1 

Description

Set DVI mode

Set HDMI mode hdmi_mode , TX2 Main Map, Address 0xF4C6[4] (Read Only)

This bit is used to readback the HDMI mode status.

Function hdmi_mode

0 

1

Description

DVI

HDMI

6.4.

AV MUTE

The AV mute status is sent to the downstream sink through the general control packet. One purpose of the AV mute is to alert the sink of a change in the TMDS clock so the sink can mute audio and video while the TMDS clock it receives is unstable. Setting AV mute also pauses HDCP encryption, so the HDCP link between the HDMI Tx and the sink is maintained while the TMDS clock is not stable. Note that AV mute is not sufficient as a means to hide protected content because the content is still sent even when AV mute is enabled.

To use AV mute:

• Enable the GCP by setting gc_pkt_en to 1

•

To set AV mute, clear clear_avmute (that is, clear_avmute

= 0) and set set_avmute (that is, set_avmute = 1)

•

To clear AV mute, clear set_avmute (that is, set_avmute

= 0) and set clear_avmute ( clear_avmute = 1)

Note that setting both set_avmute

and clear_avmute is not a valid configuration.

set_avmute , TX2 Main Map, Address 0xF44B[6]

This bit is used to control the set_avmute signal.



Function set_avmute

0 

1

Description

Set set_avmute to 0

Set set_avmute to 1 clear_avmute , TX2 Main Map, Address 0xF44B[7]

This bit is used to control the clear_avmute signal.

Function clear_avmute

0 

1

Description

Set clear_avmute to 0

Set clear_avmute to 1

6.5.

SOURCE PRODUCT DESCRIPTION INFOFRAME

The Source Product Description (SPD) InfoFrame contains the vendor name and product description. The transmission of SPD

InfoFrames is enabled by setting spd_pkt_en to 1. When this bit is set, the HDMI Tx1 section transmits one SPD packet once every two

video fields.

An application of this packet is to allow the sink to display the source information using an OSD. This information is in a 7-bit ASCII format. Refer to CEA 861 specification for more detail. spd_pkt_en , TX2 Main Map, Address 0xF440[6]

This bit is used to enable the Source Product Descriptor InfoFrame.

Function spd_pkt_en

0 

1

Description

Disabled

Enabled

Table 49: SPD InfoFrame Configuration Register

Access Type Register Name Default Value Byte Name

0xF207

0xF208

0xF209

0xF20A

0xF20B

0xF20C

0xF20D

0xF20E

0xF20F

0xF210

Packet Map

Address

0xF200

0xF201

0xF202

0xF203

0xF204

0xF205

0xF206

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W spd_hb0[7:0] spd_hb1[7:0] spd_hb2[7:0] spd_pb0[7:0] spd_pb1[7:0] spd_pb2[7:0] spd_pb3[7:0] spd_pb4[7:0] spd_pb5[7:0] spd_pb6[7:0] spd_pb7[7:0] spd_pb8[7:0] spd_pb9[7:0] spd_pb10[7:0] spd_pb11[7:0] spd_pb12[7:0] spd_pb13[7:0]

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

Header Byte 0

Header Byte 1

Header Byte 2

Data Byte 0

Data Byte 1

Data Byte 2

Data Byte 3

Data Byte 4

Data Byte 5

Data Byte 6

Data Byte 7

Data Byte 8

Data Byte 9

Data Byte 10

Data Byte 11

Data Byte 12

Data Byte 13



Packet Map

Address

0xF211

0xF212

0xF213

0xF214

0xF215

0xF216

0xF217

0xF218

0xF219

0xF21A

0xF21B

0xF21C

0xF21D

0xF21E

Access Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Register Name spd_pb14[7:0] spd_pb15[7:0] spd_pb16[7:0] spd_pb17[7:0] spd_pb18[7:0] spd_pb19[7:0] spd_pb20[7:0] spd_pb21[7:0] spd_pb22[7:0] spd_pb23[7:0] spd_pb24[7:0] spd_pb25[7:0] spd_pb26[7:0] spd_pb27[7:0]

Default Value

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

Byte Name

Data Byte 14

Data Byte 15

Data Byte 16

Data Byte 17

Data Byte 18

Data Byte 19

Data Byte 20

Data Byte 21

Data Byte 22

Data Byte 23

Data Byte 24

Data Byte 25

Data Byte 26

Data Byte 27

6.6.

SPARE PACKETS

The user may configure the ADV8003 to send any type of packets or InfoFrames via the spare packets controls and associated

configuration registers. The ADV8003 features two such spare packets that can be enabled via the spare_pkt1_en and spare_pkt0_en

controls bits. When a spare packet is enabled, the Tx transmits one these enabled spare packets once every two video fields. spare_pkt0_en , TX1 Main Map, Address 0xEC40[0]

This bit is used to enable the Spare Packet 1.

Function spare_pkt0_en Description

0 

1

Disabled

Enabled spare_pkt1_en , TX1 Main Map, Address 0xEC40[1]

This bit is used to enable the Spare Packet 2.

Function spare_pkt1_en Description

0 

1

Disabled

Enabled

Table 50: Spare Packet 0 Configuration Register

Access Type Register Name Default Value Byte Name Packet Map

Address

0xF2C0

0xF2C1

0xF202

0xF2C3

0xF2C4

0xF2C5

0xF2C6

0xF2C7

Rev. B, August 2013

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W spare1_hb0[7:0] spare1_hb1[7:0] spare1_hb2[7:0] spare1_pb0[7:0] spare1_pb1[7:0] spare1_pb2[7:0] spare1_pb3[7:0] spare1_pb4[7:0]

250

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

Header Byte 0

Header Byte 1

Header Byte 2

Data Byte 0

Data Byte 1

Data Byte 2

Data Byte 3

Data Byte 4

0xF2FF

0xF2F0

0xF2F1

0xF2F2

0xF2F3

0xF2F4

0xF2F5

0xF2F6

0xF2E7

0xF2E8

0xF2E9

0xF2EA

0xF2EB

0xF2EC

0xF2ED

0xF2EE

Packet Map

Address

0xF2E0

0xF2E1

0xF2E2

0xF2E3

0xF2E4

0xF2E5

0xF2E6

Rev. B, August 2013

0xF2CF

0xF2D0

0xF2D1

0xF2D2

0xF2D3

0xF2D4

0xF2D5

0xF2D6

Packet Map

Address

0xF2C8

0xF2C9

0xF2CA

0xF2CB

0xF2CC

0xF2CD

0xF2CE

0xF2D7

0xF2D8

0xF2D9

0xF2DA

0xF2DB

0xF2DC

0xF2DD

0xF2DE


Access Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Register Name spare2_hb0[7:0] spare2_hb1[7:0] spare2_hb2[7:0] spare2_pb0[7:0] spare2_pb1[7:0] spare2_pb2[7:0] spare2_pb3[7:0] spare2_pb4[7:0] spare2_pb5[7:0] spare2_pb6[7:0] spare2_pb7[7:0] spare2_pb8[7:0] spare2_pb9[7:0] spare2_pb10[7:0] spare2_pb11[7:0] spare2_pb12[7:0] spare2_pb13[7:0] spare2_pb14[7:0] spare2_pb15[7:0] spare2_pb16[7:0] spare2_pb17[7:0] spare2_pb18[7:0] spare2_pb19[7:0]

251

Default Value

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W spare1_pb5[7:0] spare1_pb6[7:0] spare1_pb7[7:0] spare1_pb8[7:0] spare1_pb9[7:0] spare1_pb10[7:0] spare1_pb11[7:0] spare1_pb12[7:0] spare1_pb13[7:0] spare1_pb14[7:0] spare1_pb15[7:0] spare1_pb16[7:0] spare1_pb17[7:0] spare1_pb18[7:0] spare1_pb19[7:0] spare1_pb20[7:0] spare1_pb21[7:0] spare1_pb22[7:0] spare1_pb23[7:0] spare1_pb24[7:0] spare1_pb25[7:0] spare1_pb26[7:0] spare1_pb27[7:0]

Table 51: Spare Packet 1 Configuration Register

Access Type Register Name Default Value

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

Byte Name

Header Byte 0

Header Byte 1

Header Byte 2

Data Byte 0

Data Byte 1

Data Byte 2

Data Byte 3

Data Byte 4

Data Byte 5

Data Byte 6

Data Byte 7

Data Byte 8

Data Byte 9

Data Byte 10

Data Byte 11

Data Byte 12

Data Byte 13

Data Byte 14

Data Byte 15

Data Byte 16

Data Byte 17

Data Byte 18

Data Byte 19

Byte Name

Data Byte 5

Data Byte 6

Data Byte 7

Data Byte 8

Data Byte 9

Data Byte 10

Data Byte 11

Data Byte 12

Data Byte 13

Data Byte 14

Data Byte 15

Data Byte 16

Data Byte 17

Data Byte 18

Data Byte 19

Data Byte 20

Data Byte 21

Data Byte 22

Data Byte 23

Data Byte 24

Data Byte 25

Data Byte 26

Data Byte 27


Packet Map

Address

0xF2F7

0xF2F8

0xF2F9

0xF2FA

0xF2FB

0xF2FC

0xF2FD

0xF2FE

Access Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Register Name spare2_pb20[7:0] spare2_pb21[7:0] spare2_pb22[7:0] spare2_pb23[7:0] spare2_pb24[7:0] spare2_pb25[7:0] spare2_pb26[7:0] spare2_pb27[7:0]

Default Value

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

Byte Name

Data Byte 20

Data Byte 21

Data Byte 22

Data Byte 23

Data Byte 24

Data Byte 25

Data Byte 26

Data Byte 27

6.7.

SYSTEM MONITORING

6.7.1.

General Status and Interrupts

The ADV8003 utilizes both interrupts and status bits to indicate the status of internal operations and errors in the Tx core. These interrupt

and status are listed in Table 52 , Table 53 , and Table 54

. Refer to Section 9.4 for details on the use of Tx interrupts.

Bit Name

Table 52: HDMI Tx Interrupt Bits in HDMI Tx Main Map Register 0xEC96

Bit Position Description hdcp_authenticated_int 1 (Second LSB) When set to 1 it indicates that HDCP/EDID state machine transitioned from state 3 to state 4.

Once set, it remains high until it is cleared by setting it to 1. edid_ready_int 2 When set to 1 it indicates that EDID has been read from Rx and is available in Packet Map.

Once set, it remains high until it is cleared by setting it to 1. vsync_int 5 rx_sense_int hpd_int

6

7

When set to 1 it indicates that leading edge detected on VSync input to Tx core. Once set, it remains high until it is cleared by setting it to 1.

When set to 1 it indicates that TMDS clock lines voltage has crossed 1.8 V from high to low or low to high. Once set, it remains high until it is cleared by setting it to 1.

When set to 1 it indicates that transition for high to low or low to high was detected on input HPD signal. Once set, it remains high until it is cleared by setting it to 1.

Bit Name bksv_flag_int hdcp_error_int

Table 53: HDMI Tx Interrupt Bits in Main Map Register 0xEC97

Bit Position Description

6

7

When set to 1 it indicates that the KSVs from the downstream sink have been read and available in the

Memory Map. Once set, it remains high until it is cleared by setting it to 1.

When set to 1 it indicates that the HDCP/EDID controller has reported an error. This error is available in

HDCP_CONTROLLER_ERROR. Once set, it remains high until it is cleared by setting it to 1.

Bit Name hpd_state

Table 54: Status Bits in Main Map Register 0xEC42

Bit Position Description

6

See description for hpd_state on page 246

rx_sense_state 5

See description for rx_sense_state on page 247

6.8.

EDID/HDCP CONTROLLER STATUS

The Tx core features an EDID/HDCP controller which handles EDID extraction from the downstream sink. This EDID/HDCP controller also handles HDCP authentication with downstream sink. The tasks that the Tx EDID/HDCP controller performs are described in

Section

6.12 and Section 6.13.

The current state of the Tx EDID/HDCP controller can be read from the hdcp_controller_state[3:0] status field.

hdcp_controller_state[3:0] , TX2 Main Map, Address 0xF4C8[3:0] (Read Only)



This signal is used to readback the state of the EDID/HDCP controller.

Function hdcp_controller_state[3

:0]

Description

0000 

0001

0010

0011

0100

0101

0110 - 1111

In reset (no hot plug detected)

Reading EDID

In idle state (waiting for HDCP request)

Initializing HDCP

HDCP enabled

Initializing HDCP repeater

Reserved

6.9.

EDID/HDCP CONTROLLER ERROR CODES

If an HDCP authentication occurs between the ADV8003 and the downstream sink, the ADV8003 can trigger an interrupt to notify this error to the user or the controlling CPU. The EDID/HDCP controller will then report the HDCP error code via the status field

hdcp_controller_error[3:0] . The error code is only valid when the

hdcp_error_int interrupt bit is set to 1. The last error code will remain in the HDCP/EDID controller error field even when the interrupt is cleared. hdcp_controller_error[3:0] , TX2 Main Map, Address 0xF4C8[7:4] (Read Only)

This signal is used to readback the error code when the HDCP controller error interrupt HDCP_ERROR_INT is 1.

Description

Function hdcp_controller_error[3

:0]

0000 

0001

0010

0011

0100

0101

0110

0111

1000

No error

Bad Rx BKSV

Ri mismatch

Pj mismatch

I2C error (usually no acknowledge)

Timed out waiting for downstream repeater

Maximum cascade of repeaters exceeded

SHA-1 hash check of KSV list fail

Too many devices connected to the repeater tree

6.10.

VIDEO SETUP

6.10.1.

Input Format

The HDMI Tx core of the ADV8003 receives video data from the ADV8003 digital core via a 36-bit wide bus and four synchronization signals: the pixel clock, the data enable, the horizontal and vertical synchronization signals. The HDMI Tx core always receives the video data in a 4:4:4 and SDR format from the VSP core.

It is possible to send YCrCb 4:2:2 data from the TMDS RX directly to the HDMI TX. In which case register 0xEC15 must be set appropriately in the TX main map. vfe_input_id[3:0] , TX1 Main Map, Address 0xEC15[3:0]

This signal is used to specify the video input format.



Function vfe_input_id[3:0]

0000 

0001

0101

Component

Channel

Y

Bit 12-0

Description

RGB 444 or YCbCr 444

YCbCr 422

Pseudo 422 YCbCr

Pixel

0

G/Y

0

Pixel

1

G/Y

1

Pixel

2

G/Y

2

Pixel

3

G/Y

3

Pixel

4

G/Y

4

...

...

Cb Bit 12-0 B/Cb

0

B/Cb

1

B/Cb

2

B/Cb

3

B/Cb

4

...

Cr Bit 12-0

R/Cr

0

R/Cr

1

R/Cr

2

R/Cr

3

R/Cr

4

...

Figure 87: Format of Video Data Input into HDMI Tx Core

6.10.2.

Video Mode Detection

The video mode detection feature can inform the user of the CEA-861 defined Video Identification Code (VIC) of the video being input

to the Tx core, as well as some additional formats. If a CEA 861 format is detected, the VIC is contained in vic_detected[5:0] . Some additional non CEA 861 formats are contained in aux_vic_detected[2:0] .

For some standards for which the VIC cannot be detected, the user needs to configure the following registers:

•

The aspect ratio (set via the aspect_ratio bit) is used to distinguish between CEA-861 video timing codes where the aspect ratio

is the only difference

•

For 240p and 288p modes, the number of total lines can be selected in the progressive_mode_info[1:0] field

•

The VIC detected is also affected by the pixel repetition (see Section 5.7

for more details)

The detected VIC is sent in the AVI InfoFrames unless pixel repetition is applied to the video stream transmitted by the ADV8003. When pixel repetition is applied to the video data, the VIC sent in the AVI InfoFrame may be different as the VIC is automatically determined by

the ADV8003. To override the VIC detection, the pixel repetition mode must be set to manual by setting pr_value_manual[1:0] to 0b10 or

0b11. The desired VIC is then set. The Tx core can support non CEA 861 formats, but the VIC will not be automatically detected for these formats. In this case, the VIC should manually be set to the value 0. vic_detected[5:0] , TX2 Main Map, Address 0xF43E[7:2] (Read Only)

This signal is used to readback the input video code (VIC) detected (refer to the CEA-861 specification). aux_vic_detected[2:0] , TX2 Main Map, Address 0xF43F[7:5] (Read Only)

This register returns the format of video inputs that have a resolution not defined in the CEA 861 specification.



Function aux_vic_detected[2:0]

000 

001

010

011

100

101

110

111

Description

Set by register 0x3E

240p not active

576i not active

288p not active

480i active

240p active

576i active

288p active aspect_ratio , TX2 Main Map, Address 0xF417[1]

This bit is used to set the aspect ratio of input video. This bit is used to distinguish between CEA-861D video timing codes where aspect ratio is the only difference.

Function aspect_ratio

0 

1

Description

4:3

16:9 progressive_mode_info[1:0] , TX2 Main Map, Address 0xF43F[4:3] (Read Only)

This bit is used to specify additional information for 240p or 288p input formats.

Function progressive_mode_info

[1:0]

Description

00  Reserved

01

10

11

262 total lines per frame for 240p and 312 total lines per frame for 288p

263 total lines per frame for 240p and 313 total lines per frame for 288p

Reserved for 240p and 314 total lines per frame for 288p

6.10.3.

Pixel Repetition

Pixel repetition is used in HDMI to increase the amount of blanking period available to send packets or to increase the pixel clock to meet the minimum TMDS clock rate of 25 MHz. The ADV8003 offers three choices for the user to implement pixel repetition in the Tx core.

These choices or modes are described below and can be set via pr_mode[1:0] :

Automatic mode: In automatic mode, the ADV8003 uses the audio sampling rate and the detected VIC information as parameters to decide if pixel repetition is needed to obtain sufficient blanking periods to send the audio. For an I2S input stream, the sampling rate is

always set by the user via the i2s_sf[3:0] field

.

In the case of an SPDIF stream, the source of the audio sampling rate information is set via

the audio_sampling_freq_sel bit. If the pixel repetition factor is adjusted to meet bandwidth requirements, the detected input VIC may be

different from the VIC sent to the downstream sink. The VIC of the actual video sent across the HDMI link to the downstream sink, and

which is included in the AVI InfoFrame, can be read from the vic_to_rx[5:0] field.

Manual mode: In the manual pixel repetition mode, the VIC sent in the AVI InfoFrame needs to be set. The factor between the pixel

clock input to the Tx core and the output TMDS clock frequency must be programmed in the pr_pll_manual[1:0] field. The pixel repetition value sent to the HDMI sink must be programmed in pr_value_manual[1:0] . Refer to the latest HDMI specification for more

details on valid pixel repetition formats.

Max mode: The max mode works in the same way as the automatic mode, except that it always selects the highest pixel repetition factor the Tx core is capable of. This makes the video timing independent of the audio sampling rate. This mode is not typically used.


ADV8003 Hardware Manual pr_mode[1:0] , TX2 Main Map, Address 0xF43B[6:5]

This signal is used to specify the pixel repetition mode selection. This should be set to 00 unless a non CEA-861 standard video resolution must be supported.

Function pr_mode[1:0] Description

00 

01

10

11

Auto mode

Max mode

Manual mode

Manual mode pr_pll_manual[1:0] , TX2 Main Map, Address 0xF43B[4:3]

This signal is used to specify the ratio between the input pixel clock and the TMDS output clock when manual pixel repetition is enabled.

Function pr_pll_manual[1:0] Description

00 

01

10

11 x1 x2 x4 x4 pr_value_manual[1:0] , TX2 Main Map, Address 0xF43B[2:1]

This signal is used to specify the user programmed pixel repetition sent to the downstream sink. This field is used in manual pixel repetition.

Function pr_value_manual[1:0]

00 

01

10

11

Description x1 x2 x4 x4 vic_to_rx[5:0] , TX2 Main Map, Address 0xF43D[5:0] (Read Only)

This signal is used to set the AVI InfoFrame video code (VIC) to send to the downstream sink.

Function vic_to_rx[5:0] Description xxxxxx VIC sent to the downstream sink

6.10.4.

Video Related Packets and InfoFrames

Video related packets and InfoFrames which include the AVI InfoFrame, MPEG InfoFrame and Gamut Metadata packet (GMP) are

described in Section

6.10.5, Section

6.10.6, and Section 6.10.7.

6.10.5.

AVI InfoFrame

The AVI InfoFrame is defined in the latest CEA 861 specification. The user can enable the transmission of AVI InfoFrames to the

downstream sink by setting the aviif_pkt_en bit. When the transmission of AVI InfoFrames is enabled, the Tx transmits an AVI InfoFrame once every two video fields. Table 55 provides the list of registers that can be used to configure AVI InfoFrames.


ADV8003 Hardware Manual aviif_pkt_en , TX2 Main Map, Address 0xF444[4]

This bit is used to enable the AVI InfoFrame Packet.

Function aviif_pkt_en Description

0

1 

Disable AVI InfoFrame

Enable AVI InfoFrame

Table 55: AVI InfoFrame Configuration Registers

Bit Location Access Type Default Value Field or Byte Name 1

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

0b0100

0b01101

0b00000000

0b00000000

0b00000000

0b00000000

0b0

0b0000

0b00000000

0b00000000

00000000

00000000

00000000

00000000

00000000

00000000

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[2:0]

[4:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7]

[7:4]

0xEC61

0xEC62

0xEC63

0xEC64

0xEC65

0xEC66

0xEC67

0xEC68

0xEC69

0xEC6A

0xEC6B

0xEC6C

0xEC6D

0xEC6E

0xEC59

0xEC5A

0xEC5B

0xEC5C

0xEC5D

0xEC5E

0xEC5F

0xEC60

HDMI Tx Main

Map Address

0xEC52

0xEC53

0xEC54

0xEC55

0xEC56

0xEC57

0xEC58

0xEC6F [7:0]

1 As defined in the latest CEA 861 specification

2. Only used when auto_checksum_en = 0

Data Byte 13

Data Byte 14

Data Byte 15

Data Byte 16

Data Byte 17

Data Byte 18

Data Byte 19

Data Byte 20

Data Byte 21

Data Byte 22

Data Byte 23

Data Byte 24

Data Byte 25

Data Byte 26

Data Byte 27


InfoFrame length

Checksum 2

Data Byte 1

Data Byte 2

Data Byte 3

Bit 7 of Data Byte 4

Bits [7:4] of Data Byte 5

Data Byte 6

Data Byte 7

Data Byte 8

Data Byte 9

Data Byte 10

Data Byte 11

Data Byte 12

6.10.6.

MPEG InfoFrame

The MPEG InfoFrame is defined in the latest CEA 861 specification. Currently, the specification does not recommend using this

InfoFrame. The transmission of MPEG InfoFrames can be enabled by setting the mpeg_pkt_en bit. When the transmission of MPEG

InfoFrames is enabled, the ADV8003 transmits an MPEG InfoFrame once every two video fields. Table 56 provides a list of registers that

can be used to configure MPEG InfoFrames.


ADV8003 Hardware Manual mpeg_pkt_en , TX2 Main Map, Address 0xF440[5]

This bit is used to enable the MPEG Packet.

Function mpeg_pkt_en Description

0 

1

Disabled

Enabled

0xF22F

0xF230

0xF231

0xF232

0xF233

0xF234

0xF235

0xF236

0xF237

0xF238

0xF239

0xF23A

0xF23B

0xF23C

0xF23D

0xF227

0xF228

0xF229

0xF22A

0xF22B

0xF22C

0xF22D

0xF22E

Packet Map

Address

0xF220

0xF221

0xF222

0xF223

0xF224

0xF225

0xF226

0xF23E


6.10.7.

Gamut Metadata

Table 56: MPEG InfoFrame Configuration Registers

Access Type Field Name Default Value Byte Name 1

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W mpeg_hb0[7:0] mpeg_hb1[7:0] mpeg_hb2[7:0] mpeg_pb0[7:0] mpeg_pb1[7:0] mpeg_pb2[7:0] mpeg_pb3[7:0] mpeg_pb4[7:0]

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000 mpeg_pb5[7:0] mpeg_pb6[7:0] mpeg_pb7[7:0] mpeg_pb8[7:0]

0b00000000

0b00000000

0b00000000

0b00000000 mpeg_pb9[7:0] 0b00000000 mpeg_pb10[7:0] 0b00000000 mpeg_pb11[7:0] 0b00000000 mpeg_pb12[7:0] 0b00000000 mpeg_pb13[7:0] 0b00000000 mpeg_pb14[7:0] 0b00000000 mpeg_pb15[7:0] 0b00000000 mpeg_pb16[7:0] 0b00000000 mpeg_pb17[7:0] 0b00000000 mpeg_pb18[7:0] 0b00000000 mpeg_pb19[7:0] 0b00000000 mpeg_pb20[7:0] 0b00000000 mpeg_pb21[7:0] 0b00000000 mpeg_pb22[7:0] 0b00000000 mpeg_pb23[7:0] 0b00000000 mpeg_pb24[7:0] 0b00000000 mpeg_pb25[7:0] 0b00000000 mpeg_pb26[7:0] 0b00000000 mpeg_pb27[7:0] 0b00000000

Data Byte 13

Data Byte 14

Data Byte 15

Data Byte 16

Data Byte 17

Data Byte 18

Data Byte 19

Data Byte 20

Data Byte 21

Data Byte 22

Data Byte 23

Data Byte 24

Data Byte 25

Data Byte 26

Data Byte 27

Header Byte 0

Header Byte 1

Header Byte 2

Data Byte 0

Data Byte 1

Data Byte 2

Data Byte 3

Data Byte 4

Data Byte 5

Data Byte 6

Data Byte 7

Data Byte 8

Data Byte 9

Data Byte 10

Data Byte 11

Data Byte 12

The Gamut metadata packet (GMP) contains the sources Gamut boundary description. It is defined in the latest HDMI specification.

The contents of the GMP can be set via the Packet Map registers listed in Table 57 . The user can enable the transmission of GMP to the downstream sink by setting the gm_pkt_en bit. When the transmission of GMP is enabled, the ADV8003 transmits a GMP once every two

video fields.



The ADV8003 transmits the GMP data starting 400 pixel clock cycles after the leading edge of VSync. In order to avoid corrupting the

GMP data during transmission, it is recommended that the user synchronizes all I 2 C writes to the GMP registers so that the write begins

512 pixel clock cycles after the VSync leading edge. The VSync interrupt of the ADV8003 should be used to synchronize this timing.

Figure 88 illustrates this timing requirement.

gm_pkt_en , TX2 Main Map, Address 0xF440[2]

This bit is used to enable the Gamut Metadata Packet.

Function gm_pkt_en

0 

1

Description

Disabled

Enabled

Falling edge of last DE of last field

Rising edge of first DE of next field

VSync

GMP sending window

400 pixel clocks clocks change after 512 clocks

Rev. B, August 2013

Figure 88: I 2 C Write Timing if GMP Data

Packet Map

Address

0xF2A0

0xF2A1

0xF2A2

0xF2A3

0xF2A4

0xF2A5

0xF2A6

0xF2A7

0xF2A8

0xF2A9

0xF2AA

0xF2AB

0xF2AC

0xF2AD

0xF2AE

0xF2AF

Table 57: Gamut Metadata Packet Configuration Registers

Access Type Field Name Default Value Byte Name1

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W gmp_hb0[7:0] gmp_hb1[7:0] gmp_hb2[7:0] gmp_pb0[7:0] gmp_pb1[7:0] gmp_pb2[7:0] gmp_pb3[7:0] gmp_pb4[7:0]

259

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000 gmp_pb5[7:0] gmp_pb6[7:0] gmp_pb7[7:0] gmp_pb8[7:0]

0b00000000

0b00000000

0b00000000

0b00000000 gmp_pb9[7:0] 0b00000000 gmp_pb10[7:0] 0b00000000 gmp_pb11[7:0] 0b00000000 gmp_pb12[7:0] 0b00000000

Header Byte 0

Header Byte 1

Header Byte 2

Data Byte 0

Data Byte 1

Data Byte 2

Data Byte 3

Data Byte 4

Data Byte 5

Data Byte 6

Data Byte 7

Data Byte 8

Data Byte 9

Data Byte 10

Data Byte 11

Data Byte 12


Packet Map

Address

0xF2A0

0xF2A1

0xF2A2

0xF2A3

0xF2A4

0xF2A5

0xF2A6

0xF2A7

0xF2A8

0xF2A9

0xF2AA

0xF2AB

0xF2AC

0xF2AD

0xF2AE

1 As defined in the latest HDMI specification

Access Type Field Name

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Default Value Byte Name1 gmp_pb13[7:0] 0b00000000 gmp_pb14[7:0] 0b00000000 gmp_pb15[7:0] 0b00000000 gmp_pb16[7:0] 0b00000000 gmp_pb17[7:0] 0b00000000 gmp_pb18[7:0] 0b00000000 gmp_pb19[7:0] 0b00000000 gmp_pb20[7:0] 0b00000000 gmp_pb21[7:0] 0b00000000 gmp_pb22[7:0] 0b00000000 gmp_pb23[7:0] 0b00000000 gmp_pb24[7:0] 0b00000000 gmp_pb25[7:0] 0b00000000 gmp_pb26[7:0] 0b00000000 gmp_pb27[7:0] 0b00000000

Data Byte 13

Data Byte 14

Data Byte 15

Data Byte 16

Data Byte 17

Data Byte 18

Data Byte 19

Data Byte 20

Data Byte 21

Data Byte 22

Data Byte 23

Data Byte 24

Data Byte 25

Data Byte 26

Data Byte 27

6.11.

AUDIO SETUP

6.11.1.

Audio Architecture

The ADV8003 is capable of receiving audio data in I2S, SPDIF, DSD or High Bit Rate (HBR) formats. When the input audio is captured from the audio input pins, it is then converted into audio packets for transmission over the HDMI output interface.

The ADV8003 HDMI TX1 and TX2 process audio input streams independently, the following bits select which audio format is expected on the audio pins. aud_input_mode[1:0] , IO Map, Address 0x1A08[7:6]

This signal is used to select the audio input mode.

Function aud_input_mode[1:0]

00 

01

10

11

Description

Single mode.

Dual mode; TX1 with I2S stream, TX2 with SPDIF stream.

Dual mode; TX1 with SPDIF stream, TX2 with I2S stream.

Dual mode; TX1 with SPDIF stream 1, TX2 with SPDIF stream 2.

Pin

\ aud_input_mode[1:0]

DSD_CLK

MCLK

SCLK

AUD_IN[0]

AUD_IN[1]

AUD_IN[2]

AUD_IN[3]

AUD_IN[4]

Rev. B, August 2013

Table 58: HDMI TX Supported Audio Input Modes from Audio Input Pins

0 1 2

Single Mode

Tx1 Tx2

DSD_CLK

MCLK

DSD_CLK

MCLK

Dual Mode 1

Tx1 Tx2

MCLK

MCLK

SCLK SCLK

DSD.0/SPDIF DSD.0/SPDIF

SCLK

DSD.1/I2S.0 DSD.1/I2S.0 I2S0




SPDIF

Dual Mode 2

Tx1 Tx2

MCLK

SPDIF

MCLK

SCLK

I2S0

I2S1

I2S2

I2S3

260

3

Dual Mode 3

Tx1 Tx2

MCLK

MCLK

SPDIF


AUD_IN[5] DSD.5/LRCLK DSD.5/LRCLK LRCLK LRCLK SPDIF

6.11.2.

Audio Configuration

The audio_input_sel[2:0] , audio_mode[1:0], and i2s_format[1:0]

fields must be used to configure the Tx core according to the incoming

audio input. Refer to Figure 89

to Figure 95 for more information on the audio timing formats.

audio_input_sel[2:0] , TX2 Main Map, Address 0xF40A[6:4]

This signal is used to select the input format of the audio.

Function audio_input_sel[2:0] Description

000 

001

010

011

100

I2S

SPDIF

One Bit Audio (DSD)

High Bit Rate (HBR) Audio

Reserved i2s_format[1:0] , TX2 Main Map, Address 0xF40C[1:0]

This signal is used to set the format of the I2S audio stream input to the part.

Function i2s_format[1:0] Description

00 

01

10

11

I2S

Right justified

Left justified

AES3 direct mode audio_mode[1:0] , TX2 Main Map, Address 0xF40A[3:2]

Mode Selection for Audio Select Case 1: DSD (AUDIO_SLECT = 0b010): 0x = DSD raw mode 1x = SDIF-3 mode Case 2: HBR

(AUDIO_SLECT = 0b011): 00 = 4 stream, with Bi-Phase Mark (BPM) encoding 01 = 4 stream, without BPM encoding 10 = 1 stream, with BPM encoding 11 = 1 stream, without BPM encoding

Function audio_mode[1:0]

00 

01

10

11

Description

See description

See description

See description

See description mclk_ratio[1:0] , TX2 Main Map, Address 0xF40A[1:0]

This signal is used to specify the ratio between the audio sampling frequency and the clock described using the N and CTS values.



Function mclk_ratio[1:0]

00

01 

10

11

Description

128*fs

256*fs

384*fs

512*fs mclk_en , TX2 Main Map, Address 0xF40B[5]

This bit is used to select the audio master clock that is used by the audio block.

Function mclk_en Description

0 

1

Use internally generated MCLK

Use external MCLK audio_input_sel Value audio_mode Value

Options

Table 59: Valid Configuration for audio_mode[1:0]

Corresponding Configuration

0b010 0b0x

0b1x

DSD in raw mode

DSD in SDIF-3 mode

0b011 0b00

0b01

HBR input as 4 streams, with Bi-Phase Mark (BPM) encoding

HBR input as 4 stream, without BPM encoding

0b10

0b11

HBR input as 4 stream, without BPM encoding

HBR input as 1 stream, without BPM encoding audio_input

_sel Value

0b000

0b000

0b000

0b000

0b001

0b010

0b010 audio_mode

Value

0bXX

0bXX

0bXX

0bXX

0b00

0b1X

0b1X

I2s_format

Value

0b00

0b01

0b10

0b11

0bXX

0bXX

0bXX

Table 60: Audio Input Format Summary

Input

Audio

Input

Signal

I2S[3:0]

Clock Pins Encoding ADV8003

Output Pin

SCLK,

LRCLK,

MCLK 1

Normal

Mapping

AUD_IN[4:0]

AUD_IN[5]

SCLK

MCLK

I2S[3:0]

I2S[3:0]

SCLK,

LRCLK,

MCLK 1

SCLK,

LRCLK,

MCLK 1

Normal

Normal

AUD_IN[4:0]

AUD_IN[5]

SCLK

MCLK

AUD_IN[4:0]

AUD_IN[5]

SCLK

MCLK

I2S[3:0]

SPDIF

SCLK,

LRCLK,

MCLK 1

MCLK 1

Normal

Biphase

Mark

AUD_IN[4:0]

AUD_IN[5]

SCLK

MCLK

AUD_IN[0]

MCLK

DSD[5:0] SCLK

DSD[5:0]] SCLK

Normal

SDIF-3

AUD_IN[5:0]

SCLK

AUD_IN[5:0]

SCLK

Format

Output

Packet Type

Standard

I2S

Right justified

Left justified Audio

Sample

Packet

AES3 direct Audio

Sample

Packet

IEC60958 or

IEC61937

DSD

DSD

Audio

Sample

Packet

Audio

Sample

Packet

Audio

Sample

Packet

DSD Packet

DSD Packet


ADV8003 Hardware Manual audio_input

_sel Value

0b011

0b011

0b011

0b011

0b011

0b011

0b011

0b011

0b011

0b011 audio_mode

Value

0b00

0b01

0b01

0b01

0b01

0b10

0b11

0b11

0b11

0b11

I2s_format

Value

0bXX

0b00

0b01

0b10

0b11

0bXX

0b00

0b01

0b10

0b11

Input

Audio

Input

Signal

I2S[3:0]

I2S[3:0]

I2S[3:0]

I2S[3:0]

I2S[3:0]

SPDIF

SPDIF

I2S[3:0]

I2S[3:0]

I2S[3:0]

Clock Pins Encoding ADV8003

Output Pin

Mapping

MCLK Biphase

Mark

AUD_IN[4:0]

MCLK

SCLK,

MCLK 1

Normal

SCLK, MCLK Normal

SCLK,

MCLK 1

Normal

AUD_IN[4:0]

SCLK

MCLK

AUD_IN[4:0]

SCLK

MCLK

AUD_IN[4:0]

SCLK

MCLK

SCLK,

MCLK 1

Normal

MCLK

SCLK,

MCLK

SCLK,

MCLK

1

1

Biphase

Mark

Normal

Normal

AUD_IN[4:0]

SCLK

MCLK

AUD_IN[0]

MCLK

AUD_IN[0]

SCLK

MCLK

AUD_IN[4:0]

SCLK

MCLK

SCLK,

MCLK 1

MCLK

Normal

Normal

AUD_IN[4:0]

SCLK

MCLK

AUD_IN[4:0]

MCLK

Format

IEC61937

Standard

I2S

Right justified

Standard

I2S

Right

Justified

Left

Justified

Output

Packet Type

HBR Packet

HBR Packet

HBR Packet

Left justified HBR Packet

AES3 Direct HBR Packet

IEC61937

IEC61937

HBR Packet

HBR Packet

HBR Packet

HBR Packet

HBR Packet

1 Optional signal

6.11.2.1.

I2S Audio

The ADV8003 can receive up to four stereo channels of I2S audio at up to a 192 kHz sampling rate. The number of I2S channels the Tx

processes can be selected with audioif_cc[2:0]

. The selection of the active I2S channels is done via the i2s_en[3:0] field. The audio sampling frequency of the input stream must be set appropriately via the i2s_sf[3:0] field. This value is used along with the VIC to

determine the pixel repetition factor that the Tx core applies to the video data (refer to Section

6.10.3). The value programmed in

i2s_sf[3:0] is also used to be sent across the TMDS output link in the channel status data information contained in the Audio Sample

packets.

The placement of I2S channels into the Audio Sample subpackets defined in the HDMI specification can be specified in the following fields:

• subpkt0_l_src

• subpkt0_r_src

• subpkt1_l_src

• subpkt1_r_src

• subpkt2_l_src

• subpkt2_r_src

• subpkt3_l_src

• subpkt3_r_src

When these fields are set to their default values, all I2S channels are placed in their respective position (for example, I2S0 left channel in


ADV8003 Hardware Manual channel 0 left position, I2S3 right channel in channel 3 right position, and so on) but this mapping is completely programmable if desired.

The ADV8003 can receive standard I2S, left-justified, right-justified, and direct AES3 stream formats with a sample word width between

16 bits and 24 bits. The format of the input I2S stream is set via i2s_format[1:0] while the audio sample word width is set via the

word_length[3:0] field. The ADV8003 can also receive an I2S stream in both 64-bit and 32-bit modes, so either 32- or 16-bit clock (that is,

the signal input through SCLK pin) edges or cycles per channel are valid. The ADV8003 will adapt to 32- or 64-bit modes automatically,

and the current mode can be read in the i2s_32bit_mode

field. Refer to Figure 91

to Figure 95 for timing diagrams on I2S streams input to

the ADV8003.

When the ADV8003 is configured to receive a direct AES3 stream, the stream it receives should have IEC60958-like subframes (refer to

Figure 89 ) with the stream formatted as follows:

• Data should be aligned as shown in

Figure 89 .

•

Preamble left out as shown in Figure 90 .

• Parity bit is replaced by the block start flag. The ADV8003 automatically computes the parity bit.

The channel status data collected from the audio stream input to the AUD_IN[0] pin is used in the Audio Sample packets sent by the

ADV8003 to the downstream sink. The channel status data can alternately be programmed by setting the cs_bit_override bit. When cs_bit_override is set to 1, setting audio_sampling_freq_sel allows the programming of the audio sampling frequency used for the channel

status bits while all other channel status data is extracted from the audio stream input to I2S0. The sampling frequency is set via the

i2s_sf[3:0] field.

Note:

All four stereo channels (AUD_IN[3:0]) are enabled by setting i2s_en[3:0]

to 0xF and audioif_cc[2:0] to 0x7. If one stereo channel

only is needed, the I2S audio stream data must be input to AUD_IN[0]. The i2s_en[3:0]

and audioif_cc[2:0] control fields must be set to 1.

When audio_sampling_freq_sel is set to 1, the audio sampling frequency programmed via I2S_SF is used for the determination of the

pixel repetition factor (refer to Section 5.7 for more details).

audioif_sf[2:0] , TX2 Main Map, Address 0xF474[4:2]

This signal is used to specify the Audio Sampling Frequency in the Audio InfoFrame.

000 = Case 1: Not DSD audio (Audio Select register bits 0x0A[64] ≠ 0b010) or Case 2: DSD audio (Audio Select register bits 0x0A[6:4]

= 0b010)

001 = 64x32kHz

010 = 64x44.1kHz

011 = 64x48kHz

100 = 64x88.2kHz

101 = 64x96kHz

110 = 64x176.4kHz

111 = 64x192kHz

Function audioif_sf[2:0]

000 

001

010

011

100

101

110

111

Description

See description

See description

See description

See description

See description

See description

See description

See description audioif_cc[2:0] , TX2 Main Map, Address 0xF473[2:0]

This signal is used to set the Audio Channel Count (Audio InfoFrame).



Function audioif_cc[2:0]

000 

001

010

011

100

101

110

111

Description

Refer to stream header

2 channels

3 channels

4 channels

5 channels

6 channels

7 channels

8 channels i2s_en[3:0] , TX2 Main Map, Address 0xF40C[5:2]

This signal is used to enable the I2S pins.

Function i2s_en[3:0]

0000

1111 

Description

All I2S disabled

All I2S enabled i2s_sf[3:0] , TX2 Main Map, Address 0xF415[7:4]

This signal is used to set the sampling frequency for I2S audio. This information is used both by the audio Rx and the pixel repetition.

Other values reserved.

Function

0111

1000

1001

1010

1011

1100

1101

1110

1111 i2s_sf[3:0]

0000 

0001

0010

0011

0100

0101

0110

Description

44.1kHz

Do not use

48kHz

32kHz

Do not use

Do not use

Do not use

Do not use

88.2kHz

Do not use

96kHz

Do not use

176.4kHz

Do not use

192kHz

Do not use subpkt0_l_src[2:0] , TX2 Main Map, Address 0xF40E[5:3]

This signal is used to specify the source of sub packet 0, left channel.


Function subpkt0_l_src[2:0]

000 

001

010

011

100

101

110

111

Description

I2S[0], left channel

I2S[0], right channel






I2S[3], right channel subpkt0_r_src[2:0] , TX2 Main Map, Address 0xF40E[2:0]

This signal is used to specify the source of sub packet 0, right channel.

Function subpkt0_r_src[2:0]

000

001 

010

011

100

101

110

111

Description








I2S[3], right channel subpkt1_l_src[2:0] , TX2 Main Map, Address 0xF40F[5:3]



000

001

010 

011

100

101

110

111

Description








I2S[3], right channel subpkt1_r_src[2:0] , TX2 Main Map, Address 0xF40F[2:0]


Function subpkt1_r_src[2:0] Description

000

001

010

011 

100

101

110

111











subpkt2_l_src[2:0] , TX2 Main Map, Address 0xF410[5:3]


Function subpkt2_l_src[2:0] Description

000

001

010

011

100 

101

110








111 I2S[3], right channel subpkt2_r_src[2:0] , TX2 Main Map, Address 0xF410[2:0]


Function subpkt2_r_src[2:0] Description

000

001

010

011

100

101 

110

111








I2S[3], right channel subpkt3_l_src[2:0] , TX2 Main Map, Address 0xF411[5:3]



000

001

010

011

100

101

110 

111

Description








I2S[3], right channel subpkt3_r_src[2:0] , TX2 Main Map, Address 0xF411[2:0]




Function subpkt3_r_src[2:0]

000

001

010

011

100

101

110

111 

Description








I2S[3], right channel i2s_32bit_mode , TX2 Main Map, Address 0xF442[3] (Read Only)

This bit is used to readback the I2S mode detection. It shows the number of SCLK periods per LRCLK period.

Function i2s_32bit_mode Description

0 

1

I2S 32 bit mode detected

I2S 64 bit mode detected cs_bit_override , TX2 Main Map, Address 0xF40C[6]

This bit is used to select the source of channel status bits when using I2S Mode 4.

Function cs_bit_override Description

0 

1

Use channel status bits from I2S stream

Use channel status bits programmed in I2C registers audio_sampling_freq_sel , TX2 Main Map, Address 0xF40C[7]

This bit is used to select whether the audio sampling frequency is set automatically or manually (via I2C).

Function audio_sampling_freq_s el

Description

0

1 

Use sampling frequency from I2S stream, for SPDIF stream

Use sampling frequency from I2C registers


Rev. B, August 2013

Figure 89: IEC60958 Sub Stream

268

L

S

B


LEFT

Data

23 24

M

S

B

27

V U C B 0 0 0

31

0

Validity Flag

User Data

31 Channel Status

0 Block Start Flag

Figure 90: AES3 Stream Format Input to ADV8003

RIGHT

LRCLK

SCLK

DATA

MSB LSB MSB

32 Clock Slots 32 Clock Slots

Figure 91: Timing of Standard I2S Stream Input to ADV8003

LSB

LRCLK

SCLK

DATA

LEFT RIGHT

MSB MSB MSB MSB MSB-1 LSB MSB MSB MSB MSB MSB-1

LEFT

MSB extended MSB extended


Figure 92: Timing for Right-Justified I2S Stream Input to ADV8003

RIGHT

LSB

LRCLK

SCLK

DATA

Rev. B, August 2013

MSB LSB MSB


Figure 93: Timing for Left-Justified I2S Stream Input to ADV8003

269

LSB


LRCLK

SCLK

DATA

LEFT RIGHT

LSB right

MSB left

LSB left

MSB right

LSB left

LEFT


Figure 94: Timing for I2S Stream in 32-bit Mode

RIGHT

LRCLK

SCLK

DATA

MSB LSB MSB LSB


Figure 95: Timing for I2S Stream in Left or Right-Justified and 32-bit Modes

6.11.2.2.

SPDIF Audio

The ADV8003 can receive two channel LPCM or encoded multichannel audio up to a 192 kHz sampling rate via the SPDIF input

interface. The detected sampling frequency for the SPDIF input stream can be read via the spdif_sf[3:0] field.

It is possible to set the sampling audio sampling frequency of the input SPDIF stream. This is done by setting audio_sampling_freq_sel

to

1. When audio_sampling_freq_sel is set to 1, the sampling frequency used to determine the pixel repetition factor (refer to

Section 6.11.1

)

is not extracted from the input SPDIF stream and must be programmed in the i2s_sf[3:0] field. Note that the sampling frequency that is

used in the Audio Sample packets sent to the downstream sink can be read from the spdif_sf[3:0] field.

The ADV8003 is capable of accepting SPDIF with or without an audio master clock input to through the input pin MCLK. When the

ADV8003 does not receive an audio master clock, the ADV8003 uses the bit clock input via the SCLK pin to internally generate an audio master clock and determine the CTS value. spdif_sf[3:0] , TX2 Main Map, Address 0xF404[7:4] (Read Only)

This signal is used to readback the audio sampling frequency from the SPDIF channel.



Function spdif_sf[3:0]

1000

1001

1010

1011

1100

1101

1110

1111

0000 

0001

0010

0011

0100

0101

0110

0111

6.11.2.3.

DSD Audio

Description

44.1kHz

NA

48 kHz

32kHz

NA

NA

NA

NA

88.2kHz

NA

96kHz

NA

176.4kHz

NA

192kHz

NA

The ADV8003 uses 1-bit Audio Sample packets to transmit DSD audio data across the HDMI link to the downstream sink. The ADV8003 supports up to six channels of DSD data which can be input onto six data lines clocked by the signal input to DSD_CLK.

The ADV8003 can be configured to receive a DSD stream by setting audio_input_sel[2:0] to 0b010. The mode of the DSD stream input to the ADV8003 can be set via the audio_mode[1:0]

field. The audio sampling frequency must be set via the audioif_sf[2:0] field. Note the

DSD clock input to SCLK has a frequency that is 64 times the audio sampling frequency programmed in the audioif_sf[2:0] field.

Refer to Table 60 for additional details on the DSD modes supported by the ADV8003.

Rev. B, August 2013

Table 61: Valid Configuration for audioif_sf[2:0] Address B8 (Main), Address 0x74[4:2] audio_input_sel Value audioif_sf Value Options Corresponding Configuration

≠0b010 0b000 Not DSD Audio

0b011 0b001

0b010

0b011

0b100

0b101

0b110

0b111

DSD Audio, 64x32 kHz

DSD Audio, 64x44.1 kHz






6.11.2.4.

HBR Audio

The ADV8003 uses an HBR audio packet to transmit across the TMDS link compressed audio streams conforming to IEC 61937 and with high bit rate (that is, bit rate higher than 6.144 Mbps).

The ADV8003 can be configured to receive an HBR stream by setting audio_input_sel[2:0] to 0b011. The use of one or four input stream(s) with or without biphase mark (BPM) encoding can be selected via the audio_mode[1:0] field. Note that an audio master clock

input through the pin MCLK_IN is always required for the BPM encoding modes. For HBR mode, the audio sampling frequency must be

set via the audioif_sf[2:0] field.

papb_sync can be toggled from 0 to 1 to synchronize the Pa and Pb syncword, which marks the beginning of a stream repetition with the

subpacket 0. For data bursts with a repetition period, which is a multiple of four frames, the synchronization will persist. If the data burst

does not have a repetition period of four frames, setting papb_sync is not needed but will not have any negative effects. The transition of

the bit from 0 to 1 causes the one time synchronization, so setting the bit from 1 to 0 will have no effect.

271


The mapping between the I2S input signals to the Tx core and the HBR subpackets can be via the following controls:

• subpkt0_l_src

• subpkt0_r_src

• subpkt1_l_src

• subpkt1_r_src

• subpkt2_l_src

• subpkt2_r_src

• subpkt3_l_src

• subpkt3_r_src

Note: When the HBR input stream is coming from an ADI HDMI Rx device or from the Rx section of the ADV8003, the fields listed above are set to the respective default values. Since there is no standard for chip to chip HBR transfer, different settings may be required to map the HBR stream input to the Tx core and a non ADI HDMI Rx device.

Refer to Table 60 for additional details on the HBR modes supported by the ADV8003.

papb_sync , TX2 Main Map, Address 0xF447[6]

This bit us used to synchronize the Pa and Pb syncwords with subpacket 0 for HBR audio.

Function papb_sync Description

0 

1

No function

Synchronize Pa and Pb syncwords with subpacket 0

6.11.3.

N and CTS Parameters

The audio data carried across the HDMI link to the downstream sink, which is driven by a TMDS clock only, does not retain the original audio sample clock. The task of recreating this clock at the sink is called Audio Clock Regeneration (ACR). There are varieties of ACR methods that can be implemented in an HDMI sink, each with a different set of performance characteristics. The HDMI specification does not attempt to define exactly how these mechanisms operate. It does, however, present a possible configuration and defines the data items that the HDMI source shall supply to the HDMI sink in order to allow the HDMI sink to adequately regenerate the audio clock.

The HDMI specification also defines how that data shall be generated. In many video source devices, the audio and video clocks are generated from a common clock (coherent clocks). In that situation, there exists a rational (integer divided by integer) relationship between these two clocks. The ACR architecture can take advantage of this rational relationship and can also work in an environment where there is no such relationship between these two clocks, that is, where the two clocks are truly asynchronous or where their relationship is unknown.



128 × f

S

DIVIDE

BY

N

SOURCE DEVICE

CYCLE

TIME

COUNTER

CTS

1

SINK DEVICE

VIDEO CLOCK

TMDS

CLOCK

N 1

DIVIDE

BY

CTS

MULTIPLY

BY

N

128 × f

S

N

REGISTER

N

1 N AND CTS VALUES ARE TRANSMITTED USING THE “AUDIO CLOCK REGENERATION”

PACKET. VIDEO CLOCK IS TRANSMITTED ON TMDS CLOCK CHANNEL.

Figure 96: Audio Clock Regeneration

Figure 96 illustrates the overall system architecture model used by HDMI Rxs for audio clock regeneration. The HDMI source determines

the fractional relationship between the video clock and an audio reference clock (128*fs) and passes the numerator and denominator for that fraction to the sink across the HDMI link. The sink may then recreate the audio clock from the TMDS clock by using a clock divider

and a clock multiplier. The relationship between the two clocks is shown in Equation 20 .

128

f

=

f

N

s TMDS _ CLK

CTS

Equation 20: Relationship Between Audio Reference and TMDS Clocks

The source determines the value of the numerator N as specified in the HDMI specification. Typically, this value N is used in a clock divider to generate an intermediate clock that is slower than the 128*fs clock by the factor N. The source typically determines the value of the denominator Cycle Time Stamp (CTS) by counting the number of TMDS clocks in each of the 128*fs/N clocks.

6.11.3.1.

N Parameter

N is an integer number and is calculated using Equation 21 with the recommended optimal value shown in Equation 22

which

approximately equals N for coherent audio and video clock sources. Table 62

to Table 64 can be used to determine the value of N. For non

coherent sources or sources where coherency is not known, Equation 21 , Equation 22 , and Equation 23 should be used.

128*fS/1500Hz ≤N ≤128*fS/300Hz

Equation 21: Restriction for N Value

128*fs/1000Hz

Equation 22: Optimal N Value

6.11.3.2.

CTS Parameter

The CTS value is an integer number that satisfies Equation 23 .

CTS

Average

= f

TMDS _ CLK

N

128

f

s

Equation 23: Relationship Between N and CTS

6.11.3.3.

Recommended N and Expected CTS Values

The recommended values of N for several standard pixel clocks are given in Table 62

to Table 64 .

The ADV8003 has two modes for CTS generation.



Manual mode:

Manual mode is selected by setting cts_sel to 1. In manual mode, the user can program the CTS number directly into the chip via the cts_manual[19:0] field. Manual mode is good for coherent audio and video, where the audio and video clocks are generated

from the same crystal; thus CTS should be a fixed number.

Automatic mode:

Automatic mode is selected by setting cts_sel to 0. In automatic mode, the chip computes the CTS based on the actual audio and video rates. The result can be read from the cts_internal[19:0] field. Automatic mode is good for incoherent audio or video,

where there is no simple integer ratio between the audio and video clock.

The 20-bit n value used by the Tx core of the ADV8003 can be programmed in the

n[19:0] field.

cts_sel , TX2 Main Map, Address 0xF40A[7]

This bit is used to specify whether CTS is automatically or manually set.

Function cts_sel

0 

1

Description

Automatic CTS. Use the internally generated CTS value

Manual CTS. Use the CTS programmed via CTS_MANUAL[19:0] cts_manual[19:0] , TX2 Main Map, Address 0xF407[3:0]; Address 0xF408[7:0]; Address 0xF409[7:0]

This signal is used to manually set the Cycle Time Stamp (CTS). This parameter is used with the N parameter to regenerate the audio clock in the Rx. cts_internal[19:0] , TX2 Main Map, Address 0xF404[3:0]; Address 0xF405[7:0]; Address 0xF406[7:0] (Read Only)

This signal is used to readback the automatically generated Cycle Time Stamp (CTS) parameter. This parameter is used with the N parameter to regenerate the audio clock in the Rx. n[19:0] , TX2 Main Map, Address 0xF401[3:0]; Address 0xF402[7:0]; Address 0xF403[7:0]

This signal is used to specifies the audio clock regeneration parameter N. This parameter is used with CTS to regenerate the audio clock in the Rx.

Table 62: Recommended N and Expected CTS Values for 32 kHz Audio

32 kHz

Pixel Clock (MHz) N

25.2/1.001 4576

CTS

28125

25.2

27

27 * 1.001

54

4096

4096

4096

4096

25200

27000

27027

54000

54 * 1.001

74.25/1.001

74.25

148.5/1.001

148.5

Other

4096

11648

4096

11648

4096

4096

54054

210937 – 210938

74250

421875

148500

Measured



Pixel Clock (MHz)

25.2 / 1.001

25.2

27

27 * 1.001

54

54 * 1.001

74.25 / 1.001

74.25

148.5 / 1.001

148.5

Other

Table 63: Recommended N and Expected CTS Values for 44.1 kHz and Multiples

44.1kHz 88.2 kHz

N CTS N CTS N

7007

6272

6272

31250

28000

30000

14014

12544

12544

31250

28000

30000

28028

25088

25088

6272

6272

6272

17836

6272

8918

6272

6272

30030

60000

60060

234375

82500

234375

16500

Measured

12544

12544

12544

35672

12544

17836

12544

12544

30030

60000

60060

234375

82500

234375

16500

Measured

25088

25088

25088

71344

25088

35672

25088

25088

176.4 kHz

CTS

31250

28000

30000

30030

60000

60060

234375

82500

234375

16500

Measured

Pixel Clock (MHz)

25.2 / 1.001

25.2

27

27 * 1.001

54

54 * 1.001

74.25 / 1.001

74.25

148.5 / 1.001

148.5

Other

Table 64: Recommended N and Expected CTS Values for 48 kHz and Multiples

48 kHz 96 kHz

N CTS N CTS N

6864

6144

28125

25200

13728

12288

28125

25200

27456

24576

6144

6144

6144

6144

27000

27027

54000

54054

12288

12288

12288

12288

27000

27027

54000

54054

24576

24576

24576

24576

11648

6144

5824

6144

6144

140625

74250

140625

148500

Measured

35672

12288

17836

12288

12288

140625

74250

140625

148500

Measured

46592

24576

23296

24576

24576

192 kHz

CTS

28125

25200

27000

27027

54000

54054

140625

74250

140625

148500

Measured

6.11.4.

Audio Sample Packets

By setting audioif_cc[2:0]

to a value greater then 2 (that is, 3 channel or more), the eight channel audio packet format will be used. The

I2S can be routed to different subpackets using the following fields:

• subpkt0_l_src

• subpkt0_r_src

• subpkt1_l_src

• subpkt1_r_src

• subpkt2_l_src

• subpkt2_r_src

• subpkt3_l_src

• subpkt3_r_src

The audioif_ca[7:0] must be set to a speaker mapping that corresponds to the I2S input stream to subpacket routing. Using SPDIF has a

default setting of two channels.

The audio packets use the channel status format conforming to the IEC 60958 specification. When the part is configured to receive an I2S stream, the information sent in the channel status fields is provided by the following fields:

• cr_bit

• a_info

• clk_acc

• category_code



• source_number

• word_length

• channel_status

• i2s_sf

Table 65 provides a mapping between the channel status bit encapsulated in the Audio Sample packets sent across the HDMI link to the downstream sink and corresponding ADV8003 fields located in the Tx Main register map. Note that the mapping shown in Table 65 is the

only application for I2S modes 0, 1, 2 and 3 set via the i2s_format[1:0] field.

When the part is configured to receive an SPDIF stream, the channel status information is taken from the input SPDIF stream. audioif_ca[7:0] , TX2 Main Map, Address 0xF476[7:0]

This register is used to set the speaker mapping or placement (Audio InfoFrame).

Function audioif_ca[7:0]

00000000  xxxxxxxx

Description

Default value

Speaker mapping cr_bit , TX2 Main Map, Address 0xF412[5]

This bit is used to set the channel status copyright information. Refer to the IEC 60958-3 specification.

Function cr_bit Description

0 

1

Copyright asserted

Copyright not asserted a_info[2:0] , TX2 Main Map, Address 0xF412[4:2]

This signal is used to set the channel status emphasis information. Refer to the IEC 60958-3 specification.

Function a_info[2:0] Description

000 

001

010

2 audio channels without pre-emphasis

2 audio channels with 50/15uS pre-emphasis

Reserved (for 2 audio channels with pre-emphasis)

011

100-111

Reserved (for 2 audio channels with pre-emphasis)

Reserved clk_acc[1:0] , TX2 Main Map, Address 0xF412[1:0]

This signal is used to set the channel status clock accuracy information. Refer to the IEC 60958-3 specification.



Function clk_acc[1:0]

00 

01

10

11

Description

Level II - normal accuracy +/-1000 x 10^-6

Level I - high accuracy +/- 50 x 10^-6

Level III - variable pitch shifted clock

Reserved category_code[7:0] , TX2 Main Map, Address 0xF413[7:0]

This register is used to set the channel status category code. Refer to the IEC 60958-3 specification.

Function category_code[7:0]


Description

Default value

Channel status category code source_number[3:0] , TX2 Main Map, Address 0xF414[7:4]

This signal is used to set the channel status source number.

Function source_number[3:0] Description

0000  xxxx

Default value

Channel status source number word_length[3:0] , TX2 Main Map, Address 0xF414[3:0]

This signal is used to set the channel status audio word length. Refer to the IEC 60958-3 specification.

Function word_length[3:0] Description

1000

1001

1010

1011

1100

1101

1110

1111

0000 

0001

0010

0011

0100

0101

0110

0111

Not specified

Not specified

16 bits

20 bits

18 bits

22 bits

Reserved

Reserved

19 bits

23 bits

20 bits

24 bits

17 bits

21 bits

Reserved

Reserved channel_status[1:0] , TX2 Main Map, Address 0xF412[7:6]

This signal is used to set the Channel Status bits [1:0]. Set to 0b00 as specified in IEC60958-3. Refer to IEC60958-3 specification.

Function channel_status[1:0] xx

Description

Channel status bits 0 and 1



34

35

36

37

30

31

32

33

38

39

40

41

26

27

28

29

22

23

24

25

18

19

20

21

14

15

16

17

10

11

12

13

8

9

6

7

4

5

2

3

Channel Status

Bit

0

1

Table 65: I 2 S Channel Status ADV8003 Register Map Location of Fixed Value

Channel Status Bit Name Main Map Bit Location or Fixed

Value

Main Map Bit Name or Fixed

Value

Consumer use

Audio sample word

0xEC12[6]

0xEC12[7] channel_status[0] channel_status[1]

Copyright

Emphasis

Emphasis

Emphasis

0xEC12[5]

0xEC12[2]

0xEC12[3]

0xEC12[4] cr_bit a_info[0] a_info[1] a_info[2]

Mode

Mode

Category code

Category code

Category code

Category code

Category code

Category code

0

0

0xEC13[0]

0xEC13[1]

0xEC13[2]

0xEC13[3]

0xEC13[4]

0xEC13[5]

0

0 category_code[0] category_code[1] category_code[2] category_code[3] category_code[4] category_code[5]

Category code

Category code

Source number

Source number

Source number

Source number

Channel number

Channel number

Channel number

Channel number

Sampling frequency

Sampling frequency

Sampling frequency

Sampling frequency

Clock accuracy

Clock accuracy

0xEC13[6]

0xEC13[7]

0xEC14[4]

0xEC14[5]

0xEC14[6]

0xEC14[7]

See

See

See

See

Figure 97

Figure 97

Figure 97

Figure 97

0xEC15[4]

0xEC15[5]

0xEC15[6]

0xEC15[7]

0xEC12[0]

0xEC12[1] category_code[6] category_code[7] source_number[0] source_number[1] source_number[2] source_number[3]

See

See

See

See

Figure 97

Figure 97

Figure 97

Figure 97

i2s_sf[0] i2s_sf[1] i2s_sf[2] i2s_sf[3] clk_acc[0] clk_acc[1]

Not defined

Not defined

Word length

Word length

Word length

Word length

Original sampling frequency




CGMS-A

CGMS-A

0

0

0

0

0

0

0xEC14[0]

0xEC14[1]

0

0

0xEC14[2]

0xEC14[3]

0

0

0

0

0

0 word_length[0] word_length[1]

0

0 word_length[2] word_length[3]

42-191 Not defined 0 0

Figure 97

shows how the channel number bits 20 to 23 are set, based on the layout bit and bit sample_present.spX which indicates if subpacket X contains audio samples(s). The layout bit in the Audio Sample packet header and the sample_present.spX bit are determined

based on the values programmed in the audioif_cc[2:0] field.

For example, if audioif_cc[2:0] is set to 0b001 which indicates stereo audio, the layout bit will be zero and all Audio Sample subpackets will



contain information for channels 1 and 2. If audioif_cc[2:0] is set to 0b011, indicating four channels, the layout bit will be 1;

sample_present.sp0 will be 1, sample_present.sp1 will be 1, sample_present.sp2 will be 0, and sample_present.sp2 will be 0.

Start

Audio Sample Packet Header

Layout bit

0

1

Audio Sample Packet Header sample_present.spX bit

Audio Sample Packet Header sample_present.spX bit

1

Audio Sample Subpacket X

Cl[23:20] = 2(X) + 1

Cr[23:20] = 2(X) + 2

0

1


Cl[23:20] = 1

Cr[23:20] = 2

Rev. B, August 2013


Not Present

Figure 97: Definition of Channel Status Bits 20 to 23

279


6.11.5.

Audio InfoFrame

The audio InfoFrame allows the sink to identify the characteristics of an audio stream before the channel status information is available.

The ADV8003 can be configured to transmit audio InfoFrame by setting audioif_pkt_en

to 1. When the transmission of audio InfoFrame

is enabled, the ADV8003 transmits an audio InfoFrame once every two video fields. Table 66 provides the list of registers that can be used

to configure audio InfoFrames. audioif_pkt_en , TX2 Main Map, Address 0xF444[3]

This bit is used to enable the Audio InfoFrame.

Function audioif_pkt_en Description

0

1 

Disable audio InfoFrame

Enable audio InfoFrame

HDMI Tx Main

Map Address

0xEC70

0xEC71

0xEC72

0xEC73

0xEC74

0xEC75

0xEC76

0xEC77

0xEC78

0xEC79

0xEC7A

0xEC7B

Bit Location

Table 66: Audio InfoFrame Configuration Registers

Access Type Default Value Field or Byte Name 1

[2:0]

[4:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

[7:0]

0xEC7C [7:0]


2 Only used when auto_checksum_en = 0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0b001

0b01010

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

00000000

00000000

00000000


InfoFrame length

Checksum 2

Data Byte 1

Data Byte 2

Data Byte 3

Data Byte 4

Data Byte 5

Data Byte 6

Data Byte 7

Data Byte 8

Data Byte 9

Data Byte 10

6.11.6.

ACP Packet

The Audio Content Protection (ACP) packet is used for transmitting content related information about the active audio stream. Using the

ACP packet will be defined in the license agreement of the protected audio stream.

The contents of the ACP packet can be set via the set of Packet Map registers listed in Table 67 . The user can enable the transmission of an

ACP packet to the downstream sink by setting the acp_pkt_en bit. When the transmission of ACP packets is enabled, the ADV8003

transmits an APC packets once every two video fields. acp_pkt_en , TX2 Main Map, Address 0xF440[4]

This bit is used to enable the ACP Packet.



Function acp_pkt_en

0 

1

Description

Disabled

Enabled acp_pb12[7:0] acp_pb13[7:0] acp_pb14[7:0] acp_pb15[7:0] acp_pb16[7:0] acp_pb17[7:0] acp_pb18[7:0] acp_pb19[7:0] acp_pb20[7:0] acp_pb21[7:0] acp_pb22[7:0] acp_pb23[7:0] acp_pb24[7:0] acp_pb25[7:0] acp_pb26[7:0] acp_pb27[7:0] acp_hb0[7:0] acp_hb1[7:0] acp_hb2[7:0] acp_pb0[7:0] acp_pb1[7:0] acp_pb2[7:0] acp_pb3[7:0] acp_pb4[7:0] acp_pb5[7:0] acp_pb6[7:0] acp_pb7[7:0] acp_pb8[7:0] acp_pb9[7:0] acp_pb10[7:0] acp_pb11[7:0]

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0x4F

0x50

0x51

0x52

0x53

0x54

0x55

0x56

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x57

0x58

0x59

0x5A

0x5B

0x5C

0x5D

Packet Map

Address

0x40

0x41

0x42

0x43

0x44

0x45

0x46

Table 67: ACP Packet Configuration Registers

Access Type Field Name Default Value

0x5E R/W


0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

Byte Name 1

Data Byte 12

Data Byte 13

Data Byte 14

Data Byte 15

Data Byte 16

Data Byte 17

Data Byte 18

Data Byte 19

Data Byte 20

Data Byte 21

Data Byte 22

Data Byte 23

Data Byte 24

Data Byte 25

Data Byte 26

Data Byte 27

Header Byte 0

Header Byte 1

Header Byte 2

Data Byte 0

Data Byte 1

Data Byte 2

Data Byte 3

Data Byte 4

Data Byte 5

Data Byte 6

Data Byte 7

Data Byte 8

Data Byte 9

Data Byte 10

Data Byte 11

6.11.7.

ISRC Packet

If the Supports_AI bit in the Vendor Specific Data Block (VSDB) of the sink EDID is set at 1, the International Standard Recording Code

(ISRC) packets 1 and 2 can be transmitted.

The ADV8003 can be configured to transmit ISRC packet by setting isrc_pkt_en to 1. When the transmission of an ISRC packet is enabled, the ADV8003 transmits an ISRC packet once every two video fields. Table 68 and Table 69 provide the list of registers that can be

used to configure ISRC packets.


ADV8003 Hardware Manual isrc_pkt_en , TX2 Main Map, Address 0xF440[3]

This bit is used to enable the ISRC Packet.

Function isrc_pkt_en Description

0 

1

Disabled

Enabled

Packet Map

Address

0xF260

0xF261

0xF262

0xF263

0xF264

0xF265

0xF266

0xF267

0xF268

0xF269

0xF26A

0xF26B

0xF26C

0xF26D

0xF26E

Access Type

0xF26F

0xF270

0xF271

0xF272

0xF273

0xF274

0xF275

0xF276

0xF277

0xF278

0xF279

0xF27A

0xF27B

0xF27C

0xF27D

R/W

R/W

R/W

R/W

0xF27E R/W


R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Table 68: ISRC1 Packet Configuration Registers

Field Name Default Value isrc1_hb0[7:0] isrc1_hb1[7:0] isrc1_hb2[7:0] isrc1_pb0[7:0] isrc1_pb1[7:0] isrc1_pb2[7:0] isrc1_pb3[7:0] isrc1_pb4[7:0] isrc1_pb5[7:0] isrc1_pb6[7:0] isrc1_pb7[7:0] isrc1_pb8[7:0] isrc1_pb9[7:0] isrc1_pb10[7:0] isrc1_pb11[7:0] isrc1_pb12[7:0] isrc1_pb13[7:0] isrc1_pb14[7:0] isrc1_pb15[7:0] isrc1_pb16[7:0] isrc1_pb17[7:0] isrc1_pb18[7:0] isrc1_pb19[7:0] isrc1_pb20[7:0] isrc1_pb21[7:0] isrc1_pb22[7:0] isrc1_pb23[7:0] isrc1_pb24[7:0] isrc1_pb25[7:0] isrc1_pb26[7:0] isrc1_pb27[7:0]

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

Access Type

Table 69: ISRC2 Packet Configuration Registers

Field Name Default Value Packet Map

Address

0xF280

0xF281

0xF282

0xF283

R/W

R/W

R/W

R/W isrc2_hb0[7:0] isrc2_hb1[7:0] isrc2_hb2[7:0] isrc2_pb0[7:0]

0b00000000

0b00000000

0b00000000

0b00000000


Byte Name 1

Data Byte 13

Data Byte 14

Data Byte 15

Data Byte 16

Data Byte 17

Data Byte 18

Data Byte 19

Data Byte 20

Data Byte 21

Data Byte 22

Data Byte 23

Data Byte 24

Data Byte 25

Data Byte 26

Data Byte 27

Header Byte 0

Header Byte 1

Header Byte 2

Data Byte 0

Data Byte 1

Data Byte 2

Data Byte 3

Data Byte 4

Data Byte 5

Data Byte 6

Data Byte 7

Data Byte 8

Data Byte 9

Data Byte 10

Data Byte 11

Data Byte 12

Byte Name 1

Header Byte 0

Header Byte 1

Header Byte 2

Data Byte 0


Access Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0xF29E R/W


0xF293

0xF294

0xF295

0xF296

0xF297

0xF298

0xF299

0xF29A

0xF29B

0xF29C

0xF29D

0xF28B

0xF28C

0xF28D

0xF28E

0xF28F

0xF290

0xF291

0xF292

Packet Map

Address

0xF284

0xF285

0xF286

0xF287

0xF288

0xF289

0xF28A

Field Name isrc2_pb1[7:0] isrc2_pb2[7:0] isrc2_pb3[7:0] isrc2_pb4[7:0] isrc2_pb5[7:0] isrc2_pb6[7:0] isrc2_pb7[7:0] isrc2_pb8[7:0] isrc2_pb9[7:0] isrc2_pb10[7:0] isrc2_pb11[7:0] isrc2_pb12[7:0] isrc2_pb13[7:0] isrc2_pb14[7:0] isrc2_pb15[7:0] isrc2_pb16[7:0] isrc2_pb17[7:0] isrc2_pb18[7:0] isrc2_pb19[7:0] isrc2_pb20[7:0] isrc2_pb21[7:0] isrc2_pb22[7:0] isrc2_pb23[7:0] isrc2_pb24[7:0] isrc2_pb25[7:0] isrc2_pb26[7:0] isrc2_pb27[7:0]

Default Value

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

0b00000000

Byte Name 1

Data Byte 1

Data Byte 2

Data Byte 3

Data Byte 4

Data Byte 5

Data Byte 6

Data Byte 7

Data Byte 8

Data Byte 9

Data Byte 10

Data Byte 11

Data Byte 12

Data Byte 13

Data Byte 14

Data Byte 15

Data Byte 16

Data Byte 17

Data Byte 18

Data Byte 19

Data Byte 20

Data Byte 21

Data Byte 22

Data Byte 23

Data Byte 24

Data Byte 25

Data Byte 26

Data Byte 27

6.12.

EDID HANDLING

6.12.1.

Reading the EDID

The Tx core of the ADV8003 features an EDID/HDCP controller which can read the EDID content of the downstream sink through the

DDC lines, TXDDC_SCL and TXDDC_SDA. This EDID/HDCP controller begins buffering segment 0 of the downstream sink EDID once the sink HPD is detected and the Tx core of the ADV8003 is powered up. The system can request additional segments by

programming the EDID segment pointer edid_segment[7:0] .

edid_ready_int (refer to Section

6.8

) indicates that a 256-byte EDID read

has been completed, and the EDID content can be read from the EDID Map. edid_segment[7:0] , TX2 Main Map, Address 0xF4C4[7:0]

This register is used to set the segment of the EDID read from the downstream Rx.

Function edid_segment[7:0] Description xxxxxxxx User programmed EDID segment value

6.12.2.

EDID Definitions

Extended EDID (E-EDID) supports up to 256 segments. A segment is a 256-byte segment of EDID data containing one or two 128-byte

EDID blocks. A typical HDMI sink will have only two EDID blocks and so will only use segment 0. The first EDID block is always a base



EDID structure defined in the VESA EDID specifications; the second EDID block is usually the CEA extension defined in the CEA-861 specification.

The ADV8003 has a single memory location used to store EDID and HDCP information read from the downstream sink. During HDCP repeater initialization, the EDID data read from the sink is overwritten with HDCP information which is also read from the sink. The sink

EDID is not reread after HDCP initialization. The user can request the ADV8003 to rebuffer an EDID segment by using the edid_reread

control.

6.12.3.

Additional Segments

The EDID block 0 byte number 0x7E tells how many additional EDID blocks are available. If byte 0x7E is greater than 1, additional EDID segments will need to be read. If there is more than one segment, the second block (that is, block 1) is required to be an EDID extension map. This map should be parsed according to the VESA EDID specification to determine where additional EDID blocks are stored in the sink EDID storage device such as EEPROM, RAM, and so on.

The ADV8003 is capable of accessing up to 256 segments from EDID of the sink as allowed by the EDID specification. By writing the

desired segment number to the edid_segment[7:0] field, the ADV8003 will automatically access the correct portion of the sink EDID over

the Tx DDC lines and load the 256 bytes into the EDID/HDCP memory. When the action is complete, the ADV8003 triggers the edid_ready_int interrupt

(refer to Section 6.8). The EDID data read from the sink can then be accessed from the Tx EDID Map. If the host

controller needs access to previously requested EDID information, then it can be stored in its own memory.

Figure 98 shows how to implement software to read EDID from the downstream sink using the ADV8003.

START

Wait for HPD interrupt HDP_INT

Power up Tx via

SYSTEM_PD

Wait for EDID

Ready Interrupt

EDID_READY_INT

Read EDID data from TX EDID

Map

Rev. B, August 2013

Set

EDID_SEGMENT desired Segment

YES

Parse EDID

Data

Need

Additional

Blocks?

NO

Disable EDID

Interrupt

EDID_READY_INT until next HPD

Figure 98: Reading Sink EDID Through ADV8003

Setup Audio and

Video

284


6.12.4.

edid_tries Control

edid_tries[3:0] can be used to set the number of times the Tx EDID/HDCP controller will try to read the sink EDID after a failure. Each

time an EDID read fails with an I 2

C Not Acknowledged (NACK), this value of edid_tries[3:0] is decremented. Once the edid_tries[3:0] reaches the value 0, the Tx EDID/HDCP controller will not attempt to read the EDID until edid_tries[3:0] is set to a value other than 0.

This could be used if a sink asserts high its HPD signal before the DDC bus is ready, resulting in several NACKs as the ADV8003 attempts to read the EDID. edid_tries[3:0] , TX2 Main Map, Address 0xF4C9[3:0]

This signal is used to control the number of times that the EDID read will be attempted if unsuccessful.

Function edid_tries[3:0] Description xxxx Number of time the EDID/HDCP controller attempts to read the EDID

6.12.5.

EDID Reread Control

If the EDID data from the sink is read in and the host determines that the data needs to be reread, edid_reread can be set from 0 to 1, and

the current segment set via edid_segment[7:0]

will be reread. Rereading the sink EDID may be useful, for example, if the host finds that one EDID checksum read from the sink is invalid.

Note:

It is also possible to reread the EDID from the sink by toggling the Tx core power down system_pd from 0 to 1.

edid_reread , TX2 Main Map, Address 0xF4C9[4]

This bit is used to request the EDID controller to reread the current segment if toggled from 0 to 1 for 10 times consecutively.

Function edid_reread

0 

1

Description

No action

Request EDID/HDCP controller to read EDID

6.13.

HDCP HANDLING

6.13.1.

One Sink and No Upstream Devices

The ADV8003 has a built-in controller, the Tx EDID/HDCP controller which handles HDCP transmitter states, including handling

downstream HDCP repeaters. To activate HDCP from a system level, the host controller needs to set hdcp_desired to 1 and frame_encryption_en to 1. This informs the ADV8003 that the video stream it outputs should be encrypted. The ADV8003 takes control

from there and implements all the remaining tasks defined by the HDCP 1.4 specification.

Before sending audio and video, the BKSV of the downstream sink should be compared with the revocation list which is compiled by managing System Renewability Messages (SRMs) provided on the source content (for example. DVD, Blue-ray Disc), and the

bksv_flag_int interrupt bit should be cleared. After the HDCP link is established between the ADV8003 and the downstream sink, the

system controller should monitor the status of HDCP by reading enc_on every two seconds. The Tx EDID/HDCP controller error

interrupt will activate and hdcp_error_int will be set to 1 if there is an error relating to the controller. The meaning of the error can be

determined by checking hdcp_controller_error[3:0] .

bksv_flag_int , TX1 Main Map, Address 0xEC97[6]

This bit is used to readback and control the BKSV Flag interrupt.



Function bksv_flag_int

0 

1

Description

Interrupt not active

Interrupt active. The KSVs from the downstream sink have been read and available in the

Memory Map hdcp_desired , TX2 Main Map, Address 0xF4AF[7]

This bit is used to request HDCP encryption.

Function hdcp_desired Description

0 

1

Input audio and video content not to be encrypted

Input audio and video content should be encrypted frame_encryption_en , TX2 Main Map, Address 0xF4AF[4]

This bit is used to request HDCP frame encryption.

Function frame_encryption_en

0

Description

Current video frame should not be encrypted

1  Current video frame should be encrypted bksv[39:32] , TX2 Main Map, Address 0xF4C3[7:0] (Read Only)

This register is used to readback the BKSV Byte 4 read from the downstream Rx by the HDCP controller. enc_on , TX2 Main Map, Address 0xF4B8[6] (Read Only)

This bit is used to readback the HDCP encryption status.

Function enc_on Description

0 

1

Audio and video content not being encrypted

Audio and video content being encrypted

6.13.2.

Multiple Sinks and No Upstream Devices

When connecting the ADV8003 as a source to an HDMI input of a repeater, it is necessary to read all BKSVs from downstream devices.

These BKSVs must be checked against a revocation list, which will be provided on the source content.

bksv_count[6:0]

will read 0 when the first BKSV interrupt occurs with bksv_flag_int set to 1. After the first BKSV interrupt is cleared, if

the sink connected to the ADV8003 is a repeater, a second BKSV interrupt will occur. The ADV8003 will automatically read up to 13 5-

byte BKSVs at a time and store these in the EDID memory. These BKSVs can be accessed from the EDID Map, as shown in Table 70 . The

number of additional BKSVs available stored in the EDID Map can be obtained from bksv_count[6:0] . If there are more than 13

additional BKSVs to be processed, the ADV8003 will collect the next up to 13 BKSVs from the sink, then generate another BKSV

interrupt with bksv_flag_int set to 1 when the next set is ready.


Rev. B, August 2013

8

9

7

6

3

2

1

0

Table 70: KSV Fields Accessed From EDID Map

KSV Number Field Name Register Addresses bksv0_byte_0[7:0] bksv0_byte_1[7:0] bksv0_byte_2[7:0] bksv0_byte_3[7:0] bksv0_byte_4[7:0]

0xEE00[7:0] byte 0

0xEE01[7:0] byte 1

0xEE02[7:0] byte 2

0xEE03[7:0] byte 3

0xEE04[7:0] byte 4 bksv1_byte_0[7:0] bksv1_byte_1[7:0] bksv1_byte_2[7:0] bksv1_byte_3[7:0] bksv1_byte_4[7:0] bksv2_byte_0[7:0] bksv2_byte_1[7:0] bksv2_byte_2[7:0] bksv2_byte_3[7:0] bksv2_byte_4[7:0]

0xEE05[7:0] byte 0

0xEE06[7:0] byte 1

0xEE07[7:0] byte 2

0xEE08[7:0] byte 3

0xEE09[7:0] byte 4

0xEE0A[7:0] byte 0

0xEE0B[7:0] byte 1

0xEE0C[7:0] byte 2

0xEE0D[7:0] byte 3

0xEE0E [7:0] byte 4

4

5 bksv3_byte_0[7:0] bksv3_byte_1[7:0] bksv3_byte_2[7:0] bksv3_byte_3[7:0] bksv3_byte_4[7:0] bksv4_byte_0[7:0] bksv4_byte_1[7:0] bksv4_byte_2[7:0] bksv4_byte_3[7:0] bksv4_byte_4[7:0] bksv5_byte_0[7:0] bksv5_byte_1[7:0] bksv5_byte_2[7:0] bksv5_byte_3[7:0] bksv5_byte_4[7:0] bksv6_byte_0[7:0] bksv6_byte_1[7:0] bksv6_byte_2[7:0] bksv6_byte_3[7:0] bksv6_byte_4[7:0]

0xEE0F[7:0] byte 0

0xEE10[7:0] byte 1

0xEE11[7:0] byte 2

0xEE12[7:0] byte 3

0xEE13[7:0] byte 4

0xEE14[7:0] byte 0

0xEE15[7:0] byte 1

0xEE16[7:0] byte 2

0xEE17[7:0] byte 3

0xEE18[7:0] byte 4

0xEE19[7:0] byte 0

0xEE1A[7:0] byte 1

0xEE1B[7:0] byte 2

0xEE1C[7:0] byte 3

0xEE1D[7:0] byte 4

0xEE1E[7:0] byte 0

0xEE1F[7:0] byte 1

0xEE20[7:0] byte 2

0xEE21[7:0] byte 3

0xEE22[7:0] byte 4

10 bksv7_byte_0[7:0] bksv7_byte_1[7:0] bksv7_byte_2[7:0] bksv7_byte_3[7:0] bksv7_byte_4[7:0] bksv8_byte_0[7:0] bksv8_byte_1[7:0] bksv8_byte_2[7:0] bksv8_byte_3[7:0] bksv8_byte_4[7:0] bksv9_byte_0[7:0] bksv9_byte_1[7:0] bksv9_byte_2[7:0] bksv9_byte_3[7:0] bksv9_byte_4[7:0] bksv10_byte_0[7:0] bksv10_byte_1[7:0] bksv10_byte_2[7:0] bksv10_byte_3[7:0]

0xEE23[7:0] byte 0

0xEE24[7:0] byte 1

0xEE25[7:0] byte 2

0xEE26[7:0] byte 3

0xEE27[7:0] byte 4

0xEE28[7:0] byte 0

0xEE29[7:0] byte 1

0xEE2A[7:0] byte 2

0xEE2B[7:0] byte 3

0xEE2C[7:0] byte 4

0xEE2D[7:0] byte 0

0xEE2E[7:0] byte 1

0xEE2F[7:0] byte 2

0xEE30[7:0] byte 3

0xEE31[7:0] byte 4

0xEE32[7:0] byte 0

0xEE33[7:0] byte 1

0xEE34[7:0] byte 2

0xEE35[7:0] byte 3

287



KSV Number Field Name bksv10_byte_4[7:0]

11 bksv11_byte_0[7:0] bksv11_byte_1[7:0] bksv11_byte_2[7:0] bksv11_byte_3[7:0] bksv11_byte_4[7:0]

12 bksv12_byte_0[7:0] bksv12_byte_1[7:0] bksv12_byte_2[7:0] bksv12_byte_3[7:0] bksv12_byte_4[7:0]

Register Addresses

0xEE36[7:0] byte 4

0xEE37[7:0] byte 0

0xEE38[7:0] byte 1

0xEE39[7:0] byte 2

0xEE3A[7:0] byte 3

0xEE3B[7:0] byte 4

0xEE3C[7:0] byte 0

0xEE3D[7:0] byte 1

0xEE3E[7:0] byte 2

0xEE3F[7:0] byte 3

0xEE40[7:0] byte 4

The BKVS interrupt bit bksv_flag_int set to 1 should be cleared by setting bksv_flag_int to 1 after each set of BKSVs is read. To check

when authentication is complete, the system should monitor hdcp_controller_state[3:0] and wait until this field reaches the value or state

4. At this time, the last host controller should be used to compare the BKSV list read from the sink with the revocation list. Once the host controller has verified none of the BKSVs read from the sink are revoked, the ADV8003 can be configured to send content down to the sink. bksv_count[6:0] , TX2 Main Map, Address 0xF4C7[6:0] (Read Only)

This signal is used to specify the total number of downstream HDCP devices.

Function bksv_count[6:0] xxxxxxx

Description

Total number of downstream HDCP devices

6.13.3.

Software Implementation

Figure 99 shows a block diagram of HDCP software implementation for all cases using the ADV8003 Tx HDCP/EDID controller state

machine. The necessary interactions with the ADV8003 registers and EDID memory, as well as when these interactions should take place, are illustrated in the diagram. Note that there is no need to interact with the DDC bus directly because all of the DDC functionality is controlled by the Tx HDCP/EDID controller and follows the HDCP specification 1.4.



START

Set HDCP

Request Bit

HDCP_DESIRED to 1

Wait For BKSV ready interrupt

Read BKSVs

From Registers

Tx EDID map

Clear BKSV Ready

Flag. Set

BKSV_FLAG_INT to

1

Is Sink

Repeater?

BCAPS[5]

==1

NO

Compare BKSVs with Revocation

List

Clear BKSV Ready

Flag. Set

BKSV_FLAG_INT to

1

YES

Wait For BKSV ready interrupt or

Controller State = 4

HDCP_CONTROLL

ER_STATE

Read BKSVs from EDID memeroy

If HDMI Tx is part of a repeater store BSTATUS info from EDID memory 1 st

time this state is reached

YES

Wait for Controller

State == 4

HDCP_CONTROLL

ER_STATE

Compare BKSVs with Revocation

List

If HDMI Tx is part of a repeater send DEPTH and

DEVICE_COUNT to receiver

Send Audio and

Video Across

HDMI Link

YES

Wait 2 Seconds

HDCP Link

OK?

ENCRYPTIO

N_ON == 1

Controller

State == 4?

NO

Check Number of

BKSVs available

BKSV_COUNT

Figure 99: HDCP Software Implementation

Clear HDCP

Request, return to START



6.13.4.

AV Mute

AV mute can be enabled once HDCP authentication is completed between the ADV8003 and the downstream sink. This can be used to maintain HDCP synchronization while changing video resolutions. While the KSVs for the downstream devices are being collected, an active HDCP link capable of sending encrypted video is established, but video should not be sent across the link until the KSVs have been compared with the revocation list.

It is not recommended to rely on AV mute to avoid sending audio and video during HDCP authentication. This is because AV mute does not actually mute audio or video in the Tx. It requests the function from the sink device. The best way to avoid sending unauthorized audio and video is to not send data to the Tx core of the ADV8003 until authentication between the ADV8003 and the downstream sink is complete. Another option is to black out the video data input to the Tx core and disable the audio inputs to mute the audio. Refer to

Section

6.4 for an explanation of how to enable AV mute. Refer to Section 6.11

for an explanation of how to disable the various audio

inputs.

6.14.

AUDIO RETURN CHANNEL

The ADV8003 features an Audio Return Channel (ARC) Rx in each HDMI Tx that supports the extraction of an SPDIF stream from the

ARC component of an HDMI Ethernet and Audio Channel (HEAC) signal output by a downstream sink. The ADV8003 can process the

HEAC signal output by the downstream sink in only common mode.

The ARC Rxs are powered up by default but can be powered down using the tx1_arc_powerdown and tx2_arc_powerdown bits. The ARC

pins are disabled by default and must be manually enabled to configure the ADV8003 to output ARC audio. The pins can be manually

enabled by setting both arc_pins_oe_man

and arc_pins_oe_man_en to 1. The SPDIF signal extracted by the ARC Rx can be output on the

ARC1_OUT and ARC2_OUT pins. tx1_arc_s_end_hpd and tx2_arc_s_end_hpd must both be left at the default value (1’b0) at all times – regardless of whether single-ended or common-mode ARC is being received. tx1_arc_powerdown , IO Map, Address 0x1A87[7]

This bit is used to powerdown the TX1 ARC block.

Function tx1_arc_powerdown Description

0 

1

Power up ARC

Power down ARC tx2_arc_powerdown , IO Map, Address 0x1A89[7]

This bit is used to powerdown the TX2 ARC block.

Function tx2_arc_powerdown Description

0 

1

Power up ARC

Power down ARC arc_pins_oe_man , IO Map, Address 0x1ACA[7]

This bit is used to control the output enable for ARC outputs.



Function arc_pins_oe_man

0 

1

Description

Input

Output arc_pins_oe_man_en , IO Map, Address 0x1ACB[7]

This bit is used to control the manual override for ARC outputs.

Function arc_pins_oe_man_en Description

0 

1

Auto

Manual override

To increase the noise immunity of the ADV8003 ARC Rxs, it is recommended to enable the input hysteresis block on both blocks via

tx1_arc_bias_hyst_adj and tx2_arc_bias_hyst_adj .

tx1_arc_bias_hyst_adj , IO Map, Address 0x1A88[1]

This bit is used to control the addition of hysteresis to the TX1 ARC.

Function tx1_arc_bias_hyst_adj

0 

1

Description

Normal

ADD hysteresis tx2_arc_bias_hyst_adj , IO Map, Address 0x1A8A[1]

This bit is used to control the addition of hysteresis to the TX2 ARC.

Function tx2_arc_bias_hyst_adj Description

0 

1

Normal

ADD hysteresis

6.15.

CHARGE INJECTION SETTINGS

The ADV8003 features adjustable charge injection settings to help adjust the HDMI signal rise and fall times to account for variations between different hardware implementations e.g. different board layouts, board materials, the presence of ESD devices or common-mode chokes, variations in connector type. Failure to adjust the charge injection settings may result in a system failing HDMI compliance testing due to the HDMI signal rise and fall times being too slow or fast.

The clock charge injection controls are controlled by registers 0xECE9[7:0] and 0xECF7[7:6]. These bits incorporate a series of proprietary enables and controls which enable and disable various charge injection paths. The data charge injection controls are controlled by registers 0xECEC[7:0] and 0xECF7[5:4]. These bits incorporate a series of proprietary enables and controls which enable and disable various charge injection paths.

Various charge injection options are covered in Table 71.

Clock Charge

Injection

0

0xECE9[7:0]

00000100

Table 71: Charge Injection Settings

0xECF7[7:6]

Data Charge

Injection

00 0

0xECEC[7:0]

00000100

0xECF7[5:4]

00



Clock Charge

Injection

1

1.6

2

2.6

3.2

3.6

4.2

5.2

5.8

6.4

0xECE9[7:0]

00010100

10001100

00110100

11001100

10011100

11101100

01101100

11111100

11111100

11111100

0xECF7[7:6]

01

00

10

01

00

00

00

00

10

11

Data Charge

Injection

1

1.6

2

2.6

3.2

3.6

4.2

5.2

5.8

6.4

0xECEC[7:0]

00010100

10001100

00110100

11001100

10011100

11101100

01101100

11111100

11111100

11111100

0xECF7[5:4]

01

00

10

01

00

00

00

00

10

11



7.

CONSUMER ELECTRONICS CONTROL

The Consumer Electronics Control (CEC) module features the hardware required to behave as an initiator or a follower as per the specifications for a CEC device. The CEC module contains four main sections:

• Transmit section, CEC_TX

• Receive section, CEC_RX

• Clock generator section, CEC_CLK_GEN

• Antiglitch filter section, CEC_ANTI_GLITCH

A block diagram of the CEC module is shown in Figure 100 .

CEC resetb hotplug full_resetb cec_clk cec_ clk_gen input_clk cec_tx

(initiator)

I2C registers tx_busy tx_cec_out 1 cec_out

INT

Interrupt generator cec_tx_arbitration_lost cec_tx_timeout_retry cec_tx_ready cec_rx_rdy0 cec_rx_rdy1 cec_rx_rdy2 cec_rx

(follower) rx_cec_out

0 cec_ anti_glitch cec_in

Figure 100: CEC Module Block Diagram

Note : The dual transmitter variants of ADV8003 are ADV8003KBCZ-8/7 and ADV8003KBCZ-8C/7C. The single transmitter variants of

ADV8003 are ADV8003KBCZ-8B/7B. The ADV8003KBCZ-7T does not feature any HDMI transmitters. Each HDMI transmitter features a dedicated CEC master.



7.1.

MAIN CONTROLS

This section describes the main controls for the CEC module. power_mode[1:0] , TX2 CEC Map, Address 0xF84E[1:0]

This signal is used to set the power mode of the CEC controller.

Function power_mode[1:0] Description

00 

01

10

11

Completely power down

Always active

Depends on HPD status

Depends on HPD status soft_reset , TX2 CEC Map, Address 0xF850[0]

This bit is used to reset the CEC controller.

Function soft_reset

0 

1

Description

Do not reset CEC controller

Reset CEC controller

7.2.

CEC TRANSMIT SECTION

The transmit section features the hardware required for the CEC module to act as an initiator. The host utilizes this section to transmit directly addressed messages or broadcast messages on the CEC bus. When the host wants to a send message to other CEC devices, it

writes the message to the CEC outgoing message registers (refer to Table 72 ) and the message length register. Then, the host enables the

transmission process by setting tx_enable to 1. When the message transmission is completed, or if an error occurs, the CEC transmitter

section generates an interrupt (assuming the corresponding interrupt mask bits are set accordingly).

Table 72: CEC Outgoing Message Buffer Registers

Register Name CEC Map

Address

Description tx_frame_header[7:0] 0x00 tx_frame_data0[7:0] 0x01

Header of next outgoing message

Byte 0 of next outgoing message tx_frame_data1[7:0] tx_frame_data2[7:0] tx_frame_data3[7:0] tx_frame_data4[7:0] tx_frame_data5[7:0]

0x02

0x03

0x04

0x05

0x06

Byte 1 of next outgoing message




Byte 5 of next outgoing message tx_frame_data6[7:0] tx_frame_data7[7:0] tx_frame_data8[7:0] tx_frame_data9[7:0]

0x07

0x08

0x09

0x0A tx_frame_data10[7:0] 0x0B tx_frame_data11[7:0] 0x0C tx_frame_data12[7:0] 0x0D tx_frame_data13[7:0] 0x0E tx_frame_data14[7:0] 0x0F











ADV8003 Hardware Manual tx_frame_length[4:0] , TX2 CEC Map, Address 0xF810[4:0]

This signal is used to specify the message size of the CEC message to be transmitted. This is the number of byte in the outgoing message including the header. The allowable range is 00H to 10H.

Function tx_frame_length[4:0] Description xxxxx Total number of bytes (including header byte) to be sent tx_enable , TX2 CEC Map, Address 0xF811[0]

This bit enables the TX section. When set, it initiates the start of transmission of the message in the outgoing message buffer. When the message transmission is completed this bit is automatically reset to 0. If it is manually set to 0 during a message transmission it may terminate the transmission depending on what stage of the transmission process has been reached. If the message transmission is still in the 'signal free time' stage the message transmission will be terminated. If data transmission has begun then the transmission will continue until the message is fully sent, or until an error condition occurs.

Function tx_enable

0 

1

Description

Transmission mode disabled

Transmission mode enabled and message transmission started

The ADV8003 features three status bits related to the transmission of CEC messages. The events that set these bits are mutually exclusive, that is, only one of the three events can occur during any given message transmission.

•

cec_tx_ready_int

•

cec_tx_arbitration_lost_int

•

cec_rx_ready_int[2:0]

cec_tx_ready_int , TX2 Main Map, Address 0xF497[5]

This bit is used to readback and control the CEC TX Ready interrupt.

Function cec_tx_ready_int

0 

1

Description


Interrupt active. CEC controller indicating that the TX is ready to send a message cec_tx_arbitration_lost_int , TX2 Main Map, Address 0xF497[4]

This bit is used to readback and control the CEC TX Arbitration Lost interrupt.

Function cec_tx_arbitration_lost

_int

Description

0 

1


Interrupt active. CEC controller is indicating that the TX has lost arbitration cec_tx_retry_timeout_int , TX2 Main Map, Address 0xF497[3]

This bit is used to readback and control the CEC TX Retry Timeout interrupt.



Function cec_tx_retry_timeout_i nt

0 

1

Description


Interrupt active. CEC controller is indicating that the TX retry timeout has expired tx_nack_counter[3:0] , TX2 CEC Map, Address 0xF814[3:0] (Read Only)

The signal is used to specify the number of times that the NACK error condition was encountered while trying to send the current message. This register is reset to 0b0000 when CEC_TX_ENABLE is set to 1.

Function tx_nack_counter[3:0] Description

0000 

XXXx

No error condition

Number of times NACK error condition was encountered tx_lowdrive_counter[3:0] , TX2 CEC Map, Address 0xF814[7:4] (Read Only)

This signal is used to specify the number of times that the LOWDRIVE error condition was encountered while trying to send the current message. This register is reset to 0b0000 when CEC_TX_ENABLE is set to 1.

Function tx_lowdrive_counter[3:

0]

Description

0000 

XXXx

No error condition

Number of times LOWDRIVE error condition was encountered

7.3.

CEC RECEIVE SECTION

The receive section features the hardware required for the CEC module to act as a follower. Once the CEC module is powered up via the

power_mode[1:0] bit, the CEC Rx section immediately begins monitoring the CEC bus for messages with the correct logical address(es).

When the message reception is completed, the CEC receive section generates an interrupt (assuming the corresponding interrupt mask bits are set accordingly).

The host can disable message reception while keeping the CEC module powered up by using the force_nack bit to not acknowledge

received messages. force_nack , TX2 CEC Map, Address 0xF84B[1]

This bit is used to force NO-ACK control setting. This bit forces the CEC controller to not acknowledge any received messages.

Function force_nack Description

0 

1

ACK the relevant messages

NACK all messages

7.3.1.

Logical Address Configuration

The host must set the destination logical address(es) that the CEC receive section will respond to. Up to three logical addresses can be enabled allowing support for multi function devices such as DVD recorders with TV tuners which require multiple logical addresses. The logical address(es) are set via the following registers:

logical_address2[3:0] if logical_address_mask[2:0] is set to 100 logical_address1[3:0] if logical_address_mask[2:0] is set to 010



logical_address0[3:0] if logical_address_mask[2:0] is set to 001

logical_address2[3:0] , TX2 CEC Map, Address 0xF84D[3:0]

This signal is used to specify logical address 2. This address must be enabled by setting CEC_LOGICAL_ADDRESS_MASK[2] to 1.

Function logical_address2[3:0]

1111  xxxx

Description

Default value

User specified logical address logical_address1[3:0] , TX2 CEC Map, Address 0xF84C[7:4]


Function logical_address1[3:0]

1111  xxxx

Description

Default value

User specified logical address logical_address0[3:0] , TX2 CEC Map, Address 0xF84C[3:0]


Function logical_address0[3:0] Description

1111  xxxx

Default value

User specified logical address logical_address_mask[2:0] , TX2 CEC Map, Address 0xF84B[6:4]

This signal is used to specify the logical address mask of the CEC logical devices, support up to 3 logical devices. When the bit is one, the related logical device will be enabled, and the messages whose destination address is matched with the logical address will be accepted.

Function

Description logical_address_mask[2

:0]

001 

010

100

Use logical_address0 for CEC controller



7.3.2.

Receive Buffers

The ADV8003 features three frame buffers which allow the Rx to receive up to three messages before the host processor needs to read a message out. When three messages are received, no further message reception is possible until the host reads at least one message.

For backwards compatibility with previous generation ADI CEC-enabled parts, only one frame buffer is enabled by default. In this default mode, after a message is received, the host processor must read the message out before any further message reception is possible. The

decision to use one or three messages buffers is controlled by the use_all_bufs bit.

use_all_bufs , TX2 CEC Map, Address 0xF84A[3]

This bit is used to select whether the new frames should be received in all three buffers or only one buffer.



Function use_all_bufs

0

1 

Description

Use only buffer 0 to store CEC frames (legacy mode)

Use all three buffers to store the CEC frames (non-legacy mode)

For each of the frame buffers there is a corresponding two-bit time stamp and a raw flag as described below. buf0_timestamp[1:0] , TX2 CEC Map, Address 0xF826[1:0] (Read Only)

This signal is used to readback the time stamp for the frame stored in Rx frame buffer 0. This can be used to determine which frame should be read next from the Rx frame buffers.

Function buf0_timestamp[1:0]

00 

01

10

11

Description

Invalid timestamp, no frame available in this frame buffer

Of frames currently buffered, this frame was first received

Of frames currently buffered, this frame was second received

Of frames currently buffered, this frame was third received buf1_timestamp[1:0] , TX2 CEC Map, Address 0xF826[3:2] (Read Only)


Function buf1_timestamp[1:0] Description

00 

01

10

11

Invalid timestamp, no frame is available in this frame buffer



Of frames currently buffered, this frame was third received buf2_timestamp[1:0] , TX2 CEC Map, Address 0xF826[5:4] (Read Only)


Function buf2_timestamp[1:0]

00 

01

10

11

Description

Invalid timestamp, no frame is available in this frame buffer



Of frames currently buffered, this frame was third received cec_rx_ready_int[2:0] , TX2 Main Map, Address 0xF497[2:0]

This bit is used to readback and control the CEC RX Ready interrupt.

Function cec_rx_ready_int[2:0]

000 

111

Description

CEC Ready interrupt not active

CEC Ready interrupt active. CEC controller is indicating that the RX has received a new message

When a message (other than a polling message) is received, it is loaded into the first available frame buffer (starting with buffer 0) and a two-bit time stamp is generated for that buffer. If the corresponding interrupt mask bit is set, the status bit relating to that buffer is set and


ADV8003 Hardware Manual an interrupt is generated to alert the host processor to the fact that a message was received.

When all three frame buffers are full the receive module can no longer receive CEC messages and will not acknowledge any new messages

(other than polling messages). In the case that only one frame buffer is enabled (the default condition) then only one message can be received. In this case the received message is always available in buffer 0.

The host can read the receive buffers (refer to Table 73 , Table 74

and Table 75 ) to get the messages that were addressed to the CEC Rx. The

length of each received message is available in the corresponding frame length register.

Register Name

Table 73: CEC Incoming Frame Buffer 0 Registers

CEC Map Description buf0_rx_frame_header[7:0]

Address

0x15 Header of message in frame buffer 0 buf0_rx_frame_data0[7:0] buf0_rx_frame_data1[7:0]

0x16

0x17

Byte 0 of message in frame buffer 0

Byte 1 of message in frame buffer 0 buf0_rx_frame_data2[7:0] buf0_rx_frame_data3[7:0] buf0_rx_frame_data4[7:0] buf0_rx_frame_data5[7:0]

0x18

0x19

0x1A

0x1B




Byte 5 of message in frame buffer 0 buf0_rx_frame_data6[7:0] buf0_rx_frame_data7[7:0] buf0_rx_frame_data8[7:0] buf0_rx_frame_data9[7:0] buf0_rx_frame_data10[7:0] buf0_rx_frame_data11[7:0] buf0_rx_frame_data12[7:0] buf0_rx_frame_data13[7:0] buf0_rx_frame_data14[7:0]

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24









Byte 14 of message in frame buffer 0 buf0_rx_frame_length[4:0] , TX2 CEC Map, Address 0xF825[4:0] (Read Only)

This signal is used to readback the message size of the CEC message received in frame buffer 0.

Register Name


CEC Map Description cec_buf1_rx_frame_header[7:0]

Address

0x54 Header of message in frame buffer 1 cec_buf1_rx_frame_data0[7:0] cec_buf1_rx_frame_data1[7:0]

0x55

0x56


Byte 1 of message in frame buffer 1 cec_buf1_rx_frame_data2[7:0] cec_buf1_rx_frame_data3[7:0] cec_buf1_rx_frame_data4[7:0] cec_buf1_rx_frame_data5[7:0]

0x57

0x58

0x59

0x5A




Byte 5 of message in frame buffer 1 cec_buf1_rx_frame_data6[7:0] cec_buf1_rx_frame_data7[7:0] cec_buf1_rx_frame_data8[7:0] cec_buf1_rx_frame_data9[7:0] cec_buf1_rx_frame_data10[7:0] cec_buf1_rx_frame_data11[7:0] cec_buf1_rx_frame_data12[7:0] cec_buf1_rx_frame_data13[7:0] cec_buf1_rx_frame_data14[7:0]

0x5B

0x5C

0x5D

0x5E

0x5F

0x60

0x61

0x62

0x63













Register Name


CEC Map

Address

Description cec_buf2_rx_frame_header[7:0] cec_buf2_rx_frame_data0[7:0] cec_buf2_rx_frame_data1[7:0]

0x65

0x66

0x67

Header of message in frame buffer 2


Byte 1 of message in frame buffer 2 cec_buf2_rx_frame_data2[7:0] cec_buf2_rx_frame_data3[7:0] cec_buf2_rx_frame_data4[7:0] cec_buf2_rx_frame_data5[7:0] cec_buf2_rx_frame_data6[7:0] cec_buf2_rx_frame_data7[7:0] cec_buf2_rx_frame_data8[7:0] cec_buf2_rx_frame_data9[7:0] cec_buf2_rx_frame_data10[7:0] cec_buf2_rx_frame_data11[7:0] cec_buf2_rx_frame_data12[7:0] cec_buf2_rx_frame_data13[7:0] cec_buf2_rx_frame_data14[7:0]

0x68

0x69

0x6A

0x6B

0x6C

0x6D

0x6E

0x6F

0x70

0x71

0x72

0x73

0x74















7.3.3.

CEC Message Reception Overview

This section describes how messages are received and stored when only one frame buffer is enabled (default condition).

1.

Initially the receive buffer (buffer 0) is empty.

2.

A message is received and stored in receive buffer 0, and buf0_timestamp[1:0] is set to 0b01. If the corresponding interrupt mask bit is set, cec_rx_ready_int[2:0] goes high and an interrupt is generated to alert the host processor that a message was received.

No more messages can be received until the processor reads out the received message.

3.

The host processor responds to the interrupt, or polls the buf0_timestamp[1:0] register and realizes a message was received, and reads receive buffer 0. Once the message is read the processor clears the cec_rx_ready_int[2:0]

interrupt which resets the buffer

0 timestamp to 0b00 and also clears the buffer 0 status bit (if applicable). The CEC module is now ready to receive the next incoming message.

This section describes how messages are received and stored, how the time stamps are generated, and what happens when the host reads a received message when all three frame buffers are enabled.

1.

Initially all buffers are empty and all time stamps are 0b00.

2.

A message is received and stored in receive buffer 0, and buf0_timestamp[1:0] is set to 0b01. If the corresponding interrupt mask bit is set, cec_rx_ready_int[2:0] goes high and an interrupt is generated to alert the host processor that a message was received.

3.

Another message is received and stored in receive buffer 1, and buf1_timestamp[1:0] is set to 0b10. If the corresponding interrupt mask bit is set, cec_rx_ready_int[2:0] goes high and an interrupt is generated to alert the host processor that a message

was received.

4.

The host processor responds to the interrupts, or polls the timestamps and realizes that messages were received, and reads the time stamps to determine which receive buffer to read first. The buffer with the earliest time stamp should be read first, so in this example the processor should read receive buffer 0 first. Once the message is read, the processor clears

cec_rx_ready_int[2:0] which resets the buffer 0 timestamp to 0b00 and also clears the buffer 0 status bit (if applicable).

5.

Another message is received. The Rx module checks to see which of the three buffers are available, starting with buffer 0. In this example, buffer 0 was read out already by the host processor and is available so the new message is stored in receive buffer 0. At this time the timestamp for receive buffer 1 is adjusted to 0b01 to show that it contains the first received message, and a


ADV8003 Hardware Manual timestamp of 0b10 is assigned to receive buffer 0 to show that it contains the second received message. If the corresponding

interrupt mask bit is set, cec_rx_ready_int[2:0] goes high and an interrupt is generated to alert the host processor that a message

was received.

6.

Another message is received. This message is stored in receive buffer 2 (buffer 0 and buffer 1 are full). Time stamp 0b11 is assigned to receive buffer 2 to show that it contains an unread message that was the third to be received. If the corresponding

interrupt mask bit is set, cec_rx_ready_int[2:0] goes high and an interrupt is generated to alert the host processor that a message

was received. At this time all receive buffers are full and no more messages can be received until the processor reads at least one message.

7.

The host processor responds to the interrupts, or polls the timestamps and realizes that messages were received, and reads the three time stamps. The buffer with the earliest time stamp should be read first. Therefore, receive buffer 1 is read first, followed

by receive buffer 0 and then receive buffer 2. Once the messages are read the processor clears cec_rx_ready_int[2:0] . The time

stamps for all three buffers are reset to 0b00.

7.4.

ANTIGLITCH FILTER MODULE

This module is used to remove any glitches on the CEC bus in order to make the CEC input signal cleaner before it enters the CEC

module. The glitch filter is programmable through the glitch_filter_ctrl[5:0] register. The register value specifies the minimum pulse

width that will be passed through by the module. Any pulses with narrower widths are rejected. There is a cec_glitch_filter_ctrl + 1 number of clock delays introduced by the antiglitch filter. glitch_filter_ctrl[5:0] , TX2 CEC Map, Address 0xF84F[5:0]

This signal is used to control the glitch filter. The CEC input signal is sampled by the input clock (XTAL clock). cec_glitch_filter_ctrl specifies the minimum pulse width requirement in input clock cycles. Pulses of widths less than the minimum specified width are considered glitches and will be removed.

Function glitch_filter_ctrl[5:0] Description

000000

000001

000010

000111 

111111

Disable glitch filter

Filter out pulses with width less than 1 clock cycle

Filter out pulses with width less than 2 clock cycles

...


...




7.5.

TYPICAL OPERATION FLOW

This section describes the algorithm that should be implemented in the host processor controlling the CEC module.

7.5.1.

Initializing CEC Module

Figure 101 shows the flow that can be implemented in the host processor controlling the ADV8003 in order to initialize the CEC module.

Start

Set POWER_MODE to 01

Set TX_RETRY to 3

Enable

CEC_RX_READY_INT_EN

Interrupts

Enable CEC_TX_READY_INT

Interrupt

Clear

CEC_RX_READY_INT

Enable

CEC_TX_ARBITRATION_LOST_INT

Interrupt

Enable

CEC_TX_RETRY_TIMEOUT_INT

Interrupt

Set

USE_ALL_BUFS to 1

End

Figure 101: CEC Module Initialization

7.5.2.

Using CEC Module as Initiator

Figure 102

shows the algorithm that can be implemented in the host processor controlling the ADV8003 in order to use the CEC module as an initiator.



Start

Write the outgoing CEC command into the outgoing message registers

(CEC Map Reg 0x00 to 0x0F)

Set TX_FRAME_LENGTH

According to the number of bytes in the outgoing message

Set TX_ENABLE to 1

Is

CEC_TX_READY_INT

?

YES

Clear CEC_TX_READY_INT

The last CEC message was sent without error

NO

Is

CEC_TX_ARBITRATION _LOST_INT

?

NO

Is


?

NO

YES

Clear

CEC_TX_ARBITRATION_LOST_INT

The CEC controller lost arbitration during the transmission of the last

CEC Message

YES

Clear


The last message sent by the CEC controller was NOT acknowledged by the target device within the number of tranmission attempts specified in

TX_RETRY[2:0]

End

Figure 102: Using CEC Module as Initiator



7.5.3.

Using CEC Module as Follower

Figure 103 shows the algorithm that can be implemented in the host processor controlling the ADV8003 in order to use the CEC module

as a follower.

START

(wait for interrupt)

N

CEC_RX_READY_INT

=001 ?

Y

N

CEC_RX_READY_INT

=010 ?

Y

Read

BUF0_TIMESTAMP

BUF1_TIMESTAMP

BUF2_TIMESTAMP and note the maximum value

CEC_RX_READY_INT

=100 ?

N

Y

Read the buffer associated with timestamp = 0b01



Rev. B, August 2013

Reached maximum timestamp

?

Y

N

Reached maximum timestamp

?

Y

N

Set the appropriate clear bits

CEC_RX_READY_INT corresponding to the buffers that have been read.

END

Figure 103: Using CEC Module as Follower

304


7.6.

LOW POWER CEC MESSAGE MONITORING

The ADV8003 can be programmed to monitor the CEC line for messages which contain specific, user-programmable opcodes. These are referred to as “wake_opcodes” as they allow the system to go into a low power or sleep mode and be woken up when an opcode of interest is received without the host processor having to check each received message.

The default values of the wake_opcode registers are detailed below. All of these registers can be overwritten as required by the host processor.

For each of the eight wake_opcode registers there is a corresponding raw flag, a status bit and a clear bit. If one of the wake_opcodes is received, the corresponding raw flag will go high for a brief period of time. If the appropriate interrupt mask bit is set, the status bit will go high and remain high until cleared by the clear bit, and an interrupt will also be generated. wake_opcode0[7:0] , TX2 CEC Map, Address 0xF877[7:0]

This register is used to specify the CEC_WAKE_OPCODE0. This value can be set to a CEC opcode that requires a response. On receipt of this opcode the Rx generates an interrupt that can be used to alert the system that a CEC opcode of interest has been received and requires a response.

Function wake_opcode0[7:0] Description


Power on

User specified OPCODE to respond to wake_opcode1[7:0] , TX2 CEC Map, Address 0xF878[7:0]


Function wake_opcode1[7:0]


Description

Give power status

User specified OPCODE to respond to wake_opcode2[7:0] , TX2 CEC Map, Address 0xF879[7:0]




Active source

User specified OPCODE to respond to wake_opcode3[7:0] , TX2 CEC Map, Address 0xF87A[7:0]






Description

Image view on

User specified OPCODE to respond to wake_opcode4[7:0] , TX2 CEC Map, Address 0xF87B[7:0]




Description

Text view on

User specified OPCODE to respond to wake_opcode5[7:0] , TX2 CEC Map, Address 0xF87C[7:0]




System audio mode request

User specified OPCODE to respond to wake_opcode6[7:0] , TX2 CEC Map, Address 0xF87D[7:0]




Description

Deck control

User specified OPCODE to respond to wake_opcode7[7:0] , TX2 CEC Map, Address 0xF87E[7:0]




Description

Play

User specified OPCODE to respond to



8.

VIDEO ENCODER

8.1.

INTRODUCTION

The ADV8003 encoder core consists of six high speed, Noise Shaped Video (NSV), 12-bit video DACs which provide support for composite (CVBS), S-Video (Y-C), and component (YPrPb/RGB) analog outputs in standard definition (SD), enhanced definition (ED), or high definition (HD) video formats.

Simultaneous SD and ED/HD input and output modes are supported. The ADV8003 encoder processor provides two independent signal paths for SD and ED/HD, so different video processing (filtering, color conversion, and so on) can be individually and simultaneously applied to each of the streams.

The input to the SD encoder block is always a 16/20/24-bit 4:2:2 YCbCr stream, and a 24/30/36-bit 4:4:4 YCbCr stream for ED/HD modes.

Although the encoder cannot take an RGB input stream in, it features a CSC matrix which enables the generation of RGB video signals at the component output.

The oversampling at 216 MHz (SD and ED) and 297 MHz (HD) ensures that external output filtering is not required. The block diagram

for the ADV8003 encoder core is shown in Figure 104.

ENCODER PROCESSOR

VBI DATA SERVICE

INSERTION

I2C PORT

SUBCARRIER FREQUENCY

LOCK (SFL)

24-BIT

4:2:2 YCbCr

SD VIDEO

STREAM

YCbCr

SD TEST

PATTERN

GENERATOR

YCbCr

HD TEST

PATTERN

GENERATOR

ADD

SYNC

ADD

BURST

PROGRAMMABLE

LUMINANCE

FILTER

YCrCb

TO

RGB

PROGRAMMABLE

CHROMINANCE

FILTER

SIN/COS DDS

BLOCK

16×

FILTER

16×

FILTER

14-BIT

DAC 1

14-BIT

DAC 2

14-BIT

DAC 3

14-BIT

DAC 4

14-BIT

DAC 5

14-BIT

DAC 6

DAC 1

DAC 2

DAC 3

DAC 4

DAC 5

36-BIT

4:4:4 YCbCr

EH/HD VIDEO

STREAM

PROGRAMMABLE

HDTV FILTERS

SHARPNESS AND

ADAPTIVE FILTER

CONTROL

YCbCr

TO

RGB MATRIX

4×

FILTER

DAC 6

VIDEO TIMING GENERATOR

16x/4x OVERSAMPLING

DAC PLL

Figure 104: ADV8003 Encoder Block Diagram

Note : The video encoder variants of the ADV8003 are ADV8003KBCZ-8/7. The variants of ADV8003 with no encoder are

ADV8003KBCZ-8B/7B, ADV8003KBCZ-8C/7C and ADV8003KBCZ-7T.

8.2.

INPUT CONFIGURATION

The ADV8003 encoder core is capable of supporting independent SD and ED/HD video outputs, and also both SD and ED/HD video in simultaneous mode.

The data coming either from the VSP section or directly from the ADV8003 front-end input, is input to the SD encoder through two

8/10/12-bit SDR buses; the ED/HD encoder is accessed through three 8/10/12-bit SDR buses.



ADV8003 ENCODER PROCESSOR

MUX

VIDEO FROM

INTERNAL

ADV8002

DATAPATH

16/20/24-BIT

YCbCr 4:4:4

VIDEO FROM

INTERNAL

ADV8002

DATAPATH

24/30/36-BIT

YCbCr 4:4:4

4:4:4 to 4:2:2

Conversion

SD ENCODER

HD ENCODER

14-BIT

DAC 1

14-BIT

DAC 2

14-BIT

DAC 3

14-BIT

DAC 4

14-BIT

DAC 5

14-BIT

DAC 6

DAC 4

DAC 5

DAC 6

DAC 1

DAC 2

DAC 3

Figure 105: Simplified View of ADV8003 Encoder Block

The video being routed to the SD and ED/HD encoders can be selected through the 0x0004[7:4] register (ED/HD encoder) and

0x0004[3:0] (SD encoder). Refer Section 2.2.1 for more information.

Once the desired video has been routed to the encoder, the mode of the incoming video data needs to be set using func_mode[2:0] .

func_mode[2:0] , Encoder Map, Address 0xE401[6:4]

This signal is used to select the input mode to the encoder.

Function func_mode[2:0]

000 

001

010

011

100

101

110

111

Description

SD input only

ED/HD-SDR input only

Reserved

Simultaneous SD and ED/HD-SDR

Reserved

Reserved

Reserved

Reserved

Once the input configuration to the encoder section is configured, the input standard to the SD and/or HD encoder must be selected.

Table 76 lists the possible input standards supported by the ADV8003 encoder core. Note that if using the ADV8003 de-interlacer and/or

scaler, the input standard of the encoder must be set to that of the output of the VSP section. If bypassing the VSP section, the user should set this to the standard of the external input video.

If configuring the HD encoder, the input standard must be set using hd_enc_ip_mode[4:0] .

hd_enc_ip_mode[4:0] , Encoder Map, Address 0xE430[7:3]

This signal is used to select the ED/HD output standard.



Function hd_enc_ip_mode[4:0]

01000

01001

01010

01011

01100

01101

01110

01111

00000 

00001

00010

00011

00100

00101

00110

00111

10000

10001

10011

10100

10110

Description

SMPTE293M-1996 483P 60/1.001 OR ITU-R BT.1358 483P 60/1.001

Non-standard timing mode

BTA T-1004 EDTV2 483P 60/1.001 OR ITU-R BT.1362 483P 60/1.001

ITU-R BT.1358 576P 50

ITU-R BT.1362 576P 50

SMPTE296M-2001(1) 720P 60 OR SMPTE296M-2001(2) 720P 60/1.001

SMPTE296M-2001(3) 720P 50


SMPTE296M-2001(6) 720P 25 OR


SMPTE240M-1999 1035I 30 OR SMPTE240M-1999 1035I 30/1.001

SMPTE274-1998(1) 1080P 60 OR SMPTE274-1998(2) 1080P 60/1.001

SMPTE274-1998(3) 1080P 50

SMPTE274-1998(4) 1080I 30 OR SMPTE274-1998(5) 1080I 30/1.001

SMPTE274-1998(6) 1080I 25

SMPTE274-1998(7) 1080P 30 OR SMPTE274-1998(8) 1080P 30/1.001

SMPTE274-1998(9) 1080P 25

SMPTE274-1998(10) 1080P 24 OR SMPTE274-1998(11) 1080P 24/1.001

SMPTE295-1997 1080I 25

SMPTE295-1997 1080P 50

ITU-R BT.709-5 1152I 50

For the SD encoder, the input standard can be configured using

sd_enc_ip_mode[1:0] . If using the SD encoder, the SD standard can also

be set using the automatic mode which is configured using

sd_autodetect_en . If manually setting this SD standard, the automatic mode

must be disabled.

When using the encoder in an SD-only mode, it is required that sd_enc_inp_sel[3:0] and hd_enc_inp_sel[3:0] are set to the same format.

sd_enc_ip_mode[1:0] , Encoder Map, Address 0xE480[1:0]

This signal is used to select the SD standard.

Function sd_enc_ip_mode[1:0]

00 

01

10

11

Description

NTSC

PAL B/D/G/H/I

PAL M

PAL N sd_autodetect_en , Encoder Map, Address 0xE487[5]

This bit is used to enable the encoder section to auto-detect the input standard.

Function sd_autodetect_en

1

0 

Description

Enabled

Disabled

When enabled ( sd_autodetect_en set to 1), the ADV8003 encoder core can automatically identify an NTSC or a PAL B/D/G/H/I input

stream. The ADV8003 encoder core is also configured to correctly encode the identified standard. The SD standard bits

( sd_enc_ip_mode[1:0] ) and the subcarrier frequency registers are not updated to reflect the identified standard; all registers retain their

default or user defined values. These registers should, therefore, not be used as a way of determining the decoded standard.



Table 76: Standards Directly Supported by ADV8003 Encoder Processor

Active

Resolution

I/P Frame

Rate (Hz)

Standard

720 × 240

720 × 288

P

P

59.94

50

720 × 480

720 × 576

720 × 483

I

I

P

29.97

25

59.94

ITU-R BT.601/656

ITU-R BT.601/656

SMPTE 293M

720 × 483

720 × 483

720 × 576

720 × 483

720 × 576

P

P

P

P

P

1920 × 1035 I

1920 × 1035 I

1280 × 720 P

59.94

59.94

50

59.94

50

BTA T-1004

ITU-R BT.1358

ITU-R BT.1358

ITU-R BT.1362

ITU-R BT.1362

1280 × 720

1920 × 1080

1920 × 1080

1920 × 1080

1920 × 1080

1920 × 1080

1920 × 1080

P

I

I

I

1920 × 1080 I

1920 × 1080 P

1920 × 1080 P

P

P

P

30

29.97

60, 50, 30,

25, 24

23.97,

59.94,

29.97

30, 25

29.97

25

SMPTE 240M

SMPTE 240M

SMPTE 296M

SMPTE 296M

SMPTE 274M

SMPTE 274M

SMPTE 295

50 ITU-R BT.709-5

30, 25, 24 SMPTE 274M

SMPTE 274M 23.98,

29.97

24

50

ITU-R BT.709-5

SMPTE 295

50, 59.94,

60

SMPTE 274M

I = interlaced, P = progressive.

8.3.

OUTPUT CONFIGURATION

Once the input to the encoder section has been configured, the user can configure the output of the encoder DACs. Depending on the input mode specified by the

func_mode[2:0] register

, the DAC outputs can be configured accordingly using

dac1_sel[2:0]

to

dac6_sel[2:0] .

It is important to note that if the func_mode[2:0] signal is set to simultaneous mode; then DACs 1-3 can only output the ED/HD signals

of YPbPr or RGB, and DACs 4-6 can only output the SD signals of CVBS or black burst or luma or chroma. It is possible to multiplex any of the ED/HD signals out on any of the DACs 1 to 3 in simultaneous mode. Similarly, it is possible to multiplex any of the SD signals out on any of the DACs 4 to 6. dac1_sel[2:0] , Encoder Map, Address 0xE42A[2:0]

This signal selects the data that is supplied to DAC 1.


Function dac1_sel[2:0]

4

5

6

7

0

1

2

3 

Description

CVBS or Black Burst

Luma

Chroma

Y/G

Pb/B

Pr/R

Core Bypass DAC DFT

DDS Eval DFT dac2_sel[2:0] , Encoder Map, Address 0xE42B[6:4]


Function dac2_sel[2:0] Description

4 

5

6

7

0

1

2

3

CVBS or Black Burst

Luma

Chroma

Y/G

Pb/B

Pr/R

Core Bypass DAC DFT

DDS Eval DFT dac3_sel[2:0] , Encoder Map, Address 0xE42B[2:0]



4

5 

6

7

0

1

2

3

CVBS or Black Burst

Luma

Chroma

Y/G

Pb/B

Pr/R

Core Bypass DAC DFT

DDS Eval DFT dac4_sel[2:0] , Encoder Map, Address 0xE42A[2:0]



4

5

6

7

0

1

2

3 

Description

CVBS or Black Burst

Luma

Chroma

Y/G

Pb/B

Pr/R

Core Bypass DAC DFT

DDS Eval DFT



ADV8003 Hardware Manual dac5_sel[2:0] , Encoder Map, Address 0xE429[2:0]



4

5

6

0

1 

2

3

CVBS or Black Burst

Luma

Chroma

Y/G

Pb/B

Pr/R

Core Bypass DAC DFT

7


DDS Eval DFT dac6_sel[2:0] , Encoder Map, Address 0xE42A[6:4]


4

5

6

7

0

1

2 

3

Description

CVBS or Black Burst

Luma

Chroma

Y/G

Pb/B

Pr/R

Core Bypass DAC DFT

DDS Eval DFT

8.4.

ADDITIONAL DESIGN FEATURES

This section outlines the various design features of the encoder which can be used to improve the overall video quality and the ADV8003 performance in a system. Many of these functions are optional and should be set depending on a user’s application.

8.4.1.

Output Oversampling

The ADV8003 encoder core includes two on-chip phase-locked loops (PLLs) that allow for oversampling of SD, ED, and HD video data.

Oversampling effectively increases the bandwidth of the output video data, which means that expensive analog filters are not needed at

the DAC outputs, thus resulting in reduced BOM costs. Table 77 shows the various oversampling rates supported in the ADV8003

encoder core.

Two PLLs are used for oversampling the analog output video, depending on the mode. When SD modes only are being output, PLL1 is used for output oversampling. When HD modes only are being output, PLL2 is used for output oversampling. In dual modes where both

SD and HD formats are being output, PLL1 and PLL2 are both used for SD and HD video respectively. pll_pdn , Encoder Map, Address 0xE400[1]

This bit is used to control the PLL and oversampling. This control allows the internal PLL 1 circuit to be powered down and the oversampling feature to be switched off. By default this is disabled, setting this bit to 0 enables this feature.



Function pll_pdn

0

1 

Description

PLL on

PLL off

Input Mode

Register 0xE401,

Bits[6:4]

SD only

SD only

ED only

ED only

HD only

HD only

SD and ED

SD and ED

SD and HD

SD and HD 0

ED only (at 54 MHz) 1

ED only (at 54 MHz) 0

1

0

1

0

1

0

1

0

1

Table 77: Output Oversampling Modes and Rates

PLL and Oversampling Control

Register 0xE400, Bit 1

Oversampling Mode and Rate

SD (2×)

SD (16×)

ED (1×)

ED (8×)

HD (1×)

HD (4×)

SD (2×) and ED (8×)

SD (16×) and ED (8×)

SD (2×) and HD (4×)

SD (16×) and HD (4×)

ED only (at 54 MHz) (1×)

ED only (at 54 MHz) (8×)

8.4.2.

Subcarrier Frequency Lock (SFL) Mode

The ADV8003 encoder core can be used in Subcarrier Frequency Lock (SFL) mode ( rtcen = 11). When SFL mode is enabled, the SFL pin can receive a serial digital stream from an ADI decoder (for example, ADV784x) which is used to lock the subcarrier frequency. This enables the ADV8003 encoder to stay locked to a video pixel clock which drifts over the time (this happens with poor video sources like

VCRs). Since the color subcarrier in SD modes is generated from the input pixel clock to the ADV8003, these variations on its frequency may alter the final color on the CBVS or Y/C output.

Hence, the SFL mode allows the ADV8003 encoder core to automatically alter the subcarrier frequency to compensate for these line length variations. When the part is connected to a device such as an ADV784x video decoder that outputs a digital data stream in the SFL format, the part automatically changes to the compensated subcarrier frequency on a line-by-line basis. This digital data stream is 67-bits wide, and the subcarrier is contained in Bit 0 to Bit 21. Each bit is two clock cycles long. rtcen[1:0] , Encoder Map, Address 0xE484[2:1]

This signal is used to select if the encoder is to be used in Timing Reset Mode, Subcarrier Phase Reset Mode or Subcarrier Frequency

Lock Mode. The value of these register bits along with the status of the SFL pin determine the operation.

Function rtcen[1:0] Description

00 

01

10

11

Disabled

Subcarrier phase reset mode enabled

Timing reset mode enabled

SFL mode enabled

8.4.3.

SD VCR FF/RW Synchronization

In DVD record applications where the encoder is used with a decoder, the VCR FF/RW synchronization control bit can be used for nonstandard input video. This is in fast forward or rewind modes.

In fast forward mode, the sync information at the start of a new field in the incoming video usually occurs before the correct number of


ADV8003 Hardware Manual lines/fields is reached. In rewind mode, this sync signal usually occurs after the total number of lines/fields is reached. Conventionally, this means that the output video has corrupted field signals because one signal is generated by the incoming video and another is generated when the internal line/field counters reach the end of a field.

When the VCR FF/RW sync control is enabled ( dvd_r

= 1), the line/field counters are updated according to the incoming VSync signal and when the analog output matches the incoming VSync signal. This control is available in all slave timing modes except slave mode 0. dvd_r , Encoder Map, Address 0xE482[5]

This bit is used to enable the SD VCR FF/RW sync feature.

Function dvd_r

1

0 

Description

Enabled

Disabled

8.4.4.

Vertical Blanking Interval

The ADV8003 encoder core is able to accept input data that contains VBI data (such as CGMS, WSS, VITS) in SD, ED, and HD modes.

If VBI is disabled, VBI data is not present at the output and the entire VBI is blanked. These control bits are valid in all master and slave timing modes. In order to enable this feature,

vbi_data_en is set to 1.

For the SMPTE 293M (525p) standard, VBI data can be inserted on Line 13 to Line 42 of each frame or on Line 6 to Line 43 for the ITU-R

BT.1358 (625p) standard. VBI data can be present on Line 10 to Line 20 for NTSC and on Line 7 to Line 22 for PAL. If CGMS is enabled and VBI is disabled, the CGMS data is, nevertheless, available at the output.

8.4.5.

SD Subcarrier Frequency Control

The ADV8003 encoder core is able to generate the color subcarrier used in CVBS and S-Video (Y-C) outputs from the input pixel clock.

Four 8-bit registers are used to set up the subcarrier frequency. The value of these registers is calculated using Equation 24 and Equation

25 .

Subcarrier Frequency Register =

Number of subcarrier periods in one video line

×

Number of 27 MHz clk cycles in one video line

2 32

Equation 24: SD Subcarrier Frequency Calculation where the sum is rounded to the nearest integer. For example, in NTSC mode:

Subcarrier Register Value =





 227 .

5

1716 





× 2 32 = 569408543

Equation 25: SD Subcarrier Frequency Calculation where:

Subcarrier Register Value = 569408543d = 0×21F07C1F

SD F

SC

SD F

SC

Register 0: 0x1F

Register 1: 0x7C

SD F

SC

Register 2: 0xF0

SD F

SC

Register 3: 0x21



8.4.5.1.

Programming the FSC

The subcarrier frequency register value is divided into four FSC registers, as shown in

Equation 25 . The subcarrier frequency registers

( fsc[31:0] ) must be updated sequentially, starting with Subcarrier Frequency Register 0 and ending with Subcarrier Frequency Register 3.

The reason for this is because the subcarrier frequency only updates when Subcarrier Frequency Register 3 has been updated. The SD

input standard auto detection feature (sd_autodetect_en) must be disabled. The registers to be programmed are described below.

fsc[31:0] , Encoder Map, Address 0xE48F[7:0]; Address 0xE48E[7:0]; Address 0xE48D[7:0]; Address 0xE48C[7:0]

This register is used to set the subcarrier frequency value.

Table 78 outlines the values that should be written to the subcarrier frequency registers for NTSC and PAL B/D/G/H/I.

Table 78: Typical F

SC

Values

Register Description NTSC PAL B/D/G/H/I

0xE48C F

SC

0 0x1F 0xCB

0xE48D F

SC

1

0xE48E F

SC

2

0xE48F F

SC

3

0x7C

0xF0

0x21

0x8A

0x09

0x2A

8.4.6.

SD Noninterlaced Mode (240p/288p)

The ADV8003 encoder core supports an SD noninterlaced mode. Using this mode, progressive inputs at twice the frame rate of NTSC and

PAL (240p/59.94 Hz and 288p/50 Hz respectively) can be input into the ADV8003 encoder. If the user selects the input to be 240p or 288p,

sd_non_interlaced

must be set correspondingly. Refer to Section 8.2 for more details on setting the input format.

sd_non_interlaced , Encoder Map, Address 0xE488[1]

This bit is used to enable the support of SD non-interlaced modes.

Function sd_non_interlaced Description

1

0 

Enabled

Disabled

Note: All input configurations, output configurations, and features available in NTSC and PAL modes are available in SD noninterlaced mode. For 240p/59.94 Hz input, the ADV8003 encoder core should be configured for NTSC operation. For 288p/50 Hz input, the

ADV8003 encoder core should be configured for PAL operation.

8.4.7.

Filters

The ADV8003 encoder core offers numerous filtering options for both SD and ED/HD as well as for both luma and chroma data.

8.4.7.1.

SD Filters

Table 79 provides details on the numerous available SD filters.

Rev. B, August 2013

Filter

Luma LPF NTSC

Luma LPF PAL

Luma Notch NTSC

Table 79: Internal Filter Specifications

Pass-Band Ripple (dB) 1 3 dB Bandwidth (MHz) 2

0.16

0.1

0.09

4.24

4.81

2.3/4.9/6.6

315


Filter

Luma Notch PAL

Luma SSAF

Luma CIF

Luma QCIF

Chroma 0.65 MHz

Chroma 1.0 MHz

Chroma 1.3 MHz

Chroma 2.0 MHz

Chroma 3.0 MHz

Pass-Band Ripple (dB) 1

0.1

0.04

0.127

Monotonic

Monotonic

Monotonic

0.09

0.048

Monotonic

3 dB Bandwidth (MHz) 2

3.1/5.6/6.4

6.45

3.02

1.5

0.65

1

1.395

2.2

3.2

Chroma CIF Monotonic 0.65

Chroma QCIF Monotonic 0.5

1 Pass-band ripple is the maximum fluctuation from the 0 dB response in the pass band, measured in decibels. The pass band is defined to have 0 Hz to fc (Hz) frequency limits for a low-pass filter and 0 Hz to f1 (Hz), and f2 (Hz) to infinity for a notch filter, where fc, f1, and f2 are the −3 dB points.

2 3 dB bandwidth refers to the −3 dB cutoff frequency.

The luma filter supports several different frequency responses, including two low-pass responses, two notch responses, an extended

(SSAF) response with or without gain boost attenuation, a CIF response, and a QCIF response. These can be configured using

luma_filter_sel[2:0] .

luma_filter_sel[2:0] , Encoder Map, Address 0xE480[4:2]

This signal is used to configure the luma filters for SD data.

Function luma_filter_sel[2:0]

000

001

010

011

100 

101

110

111

Description

LPF NTSC

LPF PAL

Notch NTSC

Notch PAL

SSAF Luma

Luma CIF

Luma QCIF

Reserved

If SD SSAF gain is enabled, there are 13 response options in the −4 dB to +4 dB range. The desired response can be programmed using

register 0xA2. The variation in frequency responses is shown in Figure 106 ,

Figure 107 , and Figure 108 . The registers required for enabling

and controlling the SSAF filter gain are described below.

0

–2

4

2

–4

–6

–8

–10

–12

0 1 2 3 4 5 6 7

FREQUENCY (MHz)

Figure 106: SD Luma SSAF Filter, Programmable Responses



–2

–3

–4

0

–1

2

1

0

5

4

3

–1

0 1 2 3 4

FREQUENCY (MHz)

5 6 7

Figure 107: SD Luma SSAF Filter, Programmable Gains

1

–5

0 1 2 3 4 5 6 7

FREQUENCY (MHz)

Figure 108: SD Luma SSAF Filter, Programmable Attenuation peak_en , Encoder Map, Address 0xE487[4]

This bit is used to enable the SD SSAF filter gain.

Function peak_en Description

1

0 

Enabled

Disabled peak[3:0] , Encoder Map, Address 0xE4A2[3:0]

This signal is used to configure the SD luma SSAF gain/attenuation (only applicable if subaddress 0x87, Bit 4 = 1).

Function peak[3:0]

0000 

0100

1000

Description

-4dB

...

0dB

...

+4dB

The chroma filters support several different frequency responses, including six low-pass responses, a CIF response, and a QCIF response.

These can be configured using

chroma_filter_sel[2:0] .


ADV8003 Hardware Manual chroma_filter_sel[2:0] , Encoder Map, Address 0xE480[7:5]

This signal is used to configure the chroma filters for SD data.

Function chroma_filter_sel[2:0] Description

000 

001

010

011

100

101

110

1.3MHz

0.65MHz

1MHz

2MHz

Reserved

Chroma CIF

Chroma QCIF

111 3MHz

In addition to the chroma filters listed with chroma_filter_sel[2:0] , there is an SSAF filter that is specifically designed for the color difference component outputs, Pr and Pb. This filter has a cutoff frequency of ~2.7 MHz and a gain of –40 dB at 3.8 MHz. Refer to Figure

109 for more details. To enable this filter, wide_uv_filt should be set to 1.

EXTENDED (SSAF) PrPb FILTER MODE

0

–10

–20

–30

–40

–50

–60

0 1 2 3 4

FREQUENCY (MHz)

Figure 109: PrPb SSAF Filter

5 6 wide_uv_filt , Encoder Map, Address 0xE482[0]

This bit is used to enable the SSAF filter for PrPb SD data.

Function wide_uv_filt

1 

0

Description

Enabled

Disabled

If this filter is disabled, one of the chroma filters shown in Table 79 can be selected and used for the CVBS or luma/chroma signal.

8.4.7.2.

ED/HD Filters

The ADV8003 encoder core also includes a sinc compensation filter designed to counter the effect of sinc roll-off in DAC 1, DAC 2, and

DAC 3 while operating in ED/HD mode. The benefit of the filter is illustrated in Figure 110 and Figure 111 which show the effect of the

filter when enabled and disabled. This filter is enabled by default but can be disabled using

sinc_filt_df_en .



0

–0.1

–0.2

–0.3

–0.4

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

0.5

0.4

0.3

0.2

0.1

–0.5

0 5 10 15

FREQUENCY (MHz)

20 25 30

Figure 110: ED/HD Sinc Compensation Filter Enabled

0.5

–0.5

0 5 10 15

FREQUENCY (MHz)

20 25 30

Figure 111: ED/HD Sinc Compensation Filter Disabled sinc_filt_df_en , Encoder Map, Address 0xE433[3]

This bit is used to disable the sinc compensation filter on DAC1, DAC2 and DAC3.

Function sinc_filt_df_en

0

1 

Description

Disabled

Enabled

8.4.8.

ED/HD Test Pattern Generator

ADV8003 is able to internally generate ED/HD black bar, uniform background color or hatch test patterns. It is not possible to output a color bar test pattern while EH/HD video is being routed through the encoder. This test pattern can be enabled using

hdtv_tp_en and the

test pattern used can be determined using hdtv_flat_tp . y_colour[7:0] , cr_colour[7:0] ,

and

cb_colour[7:0] are used to program the output color of the internal ED/HD test pattern generator,

whether it is the lines of the crosshatch pattern or the uniform field test pattern. They are not functional as color controls for external pixel data input. hdtv_tp_en , Encoder Map, Address 0xE431[2]

This bit is used to enable the ED/HD test pattern generator.



Function hdtv_tp_en

0 

1

Description

ED/HD test pattern off

ED/HD test pattern on

The values for the luma (Y) and the color difference (Cr and Cb) signals used to obtain white, black, and saturated primary and complementary colors conform to the ITU-R BT.601-4 standard.

Table 80 shows sample color values that can be programmed into the color registers when the output standard selection is set to EIA

770.2/EIA770.3 (Reg 0x30, Bits[1:0] = 00). hdtv_flat_tp , Encoder Map, Address 0xE431[3]

This bit is used to select the pattern used by the internal test pattern generator.

Function hdtv_flat_tp Description

0 

1

Hatch

Field/frame y_colour[7:0] , Encoder Map, Address 0xE436[7:0]

This register is used to control the ED/HD test pattern, Y level.

Function y_colour[7:0]

Default

Description

0xA0 cr_colour[7:0] , Encoder Map, Address 0xE437[7:0]

This register is used to control the ED/HD test pattern, Cr level.

Function cr_colour[7:0]

Default

Description

0x80 cb_colour[7:0] , Encoder Map, Address 0xE438[7:0]

This register is used to control the ED/HD test pattern, Cb level.

Function cb_colour[7:0] Description

Default 0x80

Rev. B, August 2013

Table 80: Sample Color Values for EIA 770.2/EIA770.3 ED/HD Output Standard Selection

Sample Color Y Value Cr Value Cb Value

White

Black

235

16

(0xEB)

(0x10)

128

128

(0x80)

(0x80)

128

128

(0x80)

(0x80)

Red

Green

Blue

Yellow

Cyan

81

145

41

210

170

(0x51)

(0x91)

(0x29)

(0xD2)

(0xAA)

240 (0xF0)

34

110

146

16

(0x22)

(0x6E)

(0x92)

(0x10)

90

54

(0x5A)

(0x36)

240 (0xF0)

16

166

(0x10)

(0xA6)

320


Sample Color

Magenta

Y Value Cr Value Cb Value

106 (0x6A) 222 (0xDE) 202 (0xCA)

8.4.9.

Color Space Conversion Matrix

The input to the encoder block on the ADV8003 should always be in a YCbCr color space. If an RGB color space is present at the input pins, the CSC on the I/O block of the ADV8003 can be used to convert it to YCbCr. It is possible, however, to convert from YCbCr to an

RGB stream in the encoder. The encoder output color space can be programmed using yuv_out .

yuv_out , Encoder Map, Address 0xE402[5]

This bit is used to select the output color space for the encoder.

Function yuv_out

0

1 

Description

RGB component outputs

YPrPb component outputs

8.4.10.

ED/HD Manual CSC Matrix Adjust Feature

The ED/HD manual CSC matrix adjust feature provides custom coefficient manipulation for the YPbPr to RGB CSC and is used in ED and

HD modes only. matrix_prog_en can be used to enable this feature.

matrix_prog_en , Encoder Map, Address 0xE402[3]

This bit is used to enable the manual mode for the ED/HD color space converter.

Function matrix_prog_en Description

0 

1

Automatic mode

Manual mode

Normally, there is no need to enable this feature because the CSC matrix automatically performs the CSC based on the input mode chosen

(ED or HD) and the output color space selected using yuv_out . If the user needs to automatically update the CSC coefficients, the

following procedure is followed.

If the user selects the RGB output color space, the ED/HD CSC matrix scaler uses the following equations:

R = GY × Y + RV × Pr

G = GY × Y − ( GU × Pb) − ( GV × Pr)

B = GY × Y + BU × Pb

Note: Subtractions in these equations are implemented in the hardware.

The following registers need to be programmed with these values:

• gy [9:0] – Reg 0xE405 [7:0], Reg 0xE403 [1:0]

• gu [9:0] – Reg 0xE406 [7:0], Reg 0xE404 [7:6]

• gv [9:0] – Reg 0xE407 [7:0], Reg 0xE404 [5:4]

• bu [9:0] – Reg 0xE408 [7:0], Reg 0xE404 [3:2]

• rv [9:0] – Reg 0xE409 [7:0], Reg 0xE404 [1:0]



On powerup, the CSC matrix is programmed with the default values shown in Table 81 .

Table 81: ED/HD Manual CSC Matrix Default Values

Register Default

0x03

0x04

0x05

0x03

0xF0

0x4E

0x06

0x07

0x0E

0x24

0x08 0x92

0x09 0x7C

When the ED/HD manual CSC matrix adjust feature is enabled, the default coefficient values in Reg 0xE403 to Reg 0xE409 are correct for the HD color space only. The color components are converted according to the following 1080i and 720p standards (SMPTE 274M,

SMPTE 296M):

R = Y + 1.575

Pr

G = Y − 0.468

Pr − 0.187

Pb

B = Y + 1.855

Pb

The conversion coefficients should be multiplied by 315 before being written to the ED/HD CSC matrix registers. This is reflected in the default values for gy = 0x13B, gu = 0x03B, gv = 0x093, bu = 0x248, and rv = 0x1F0.

If the ED/HD manual CSC matrix adjust feature is enabled and another input standard (such as ED) is used, the scale values for gy, gu, gv, bu, and rv must be adjusted according to this input standard color space. The user should consider that the color component conversion may use different scale values.

For example, SMPTE 293M uses the following conversion:

R = Y + 1.402

Pr

G = Y – 0.714

Pr – 0.344

Pb

B = Y + 1.773

Pb

The programmable CSC matrix is used for external ED/HD pixel data and is not functional when internal test patterns are enabled.

8.4.10.1.

Programming the CSC Matrix

If the user needs to manually provide the coefficients for the CSC matrix for ED/HD, this procedure is followed:

1.

Enable the ED/HD manual CSC matrix adjust feature ( matrix_prog_en ).

2.

Set the output to RGB ( yuv_out ).

3.

Disable sync on YPrPb (Reg 0xE435, Bit 2).

4.

Enable sync on RGB (optional) (Reg 0xE402, Bit 4).

The gy value controls the green signal output level, the bu value controls the blue signal output level, and the rv value controls the red signal output level.

8.4.11.

SD Luma and Color Scale Control

When enabled, the SD luma and color scale control feature can be used to scale the SD Y, Cb, and Cr output levels. This feature can be

enabled using scale_ycbcr_en . This feature affects all SD output signals, regardless of the encoder output, that is, CVBS, Y-C, YPrPb, and

RGB.


ADV8003 Hardware Manual scale_ycbcr_en , Encoder Map, Address 0xE487[0]

This bit is used to enable the SD luma and color scale control feature.

Function scale_ycbcr_en Description

1

0 

Enabled

Disabled

When enabled, three 10-bit registers (SD Y scale, SD Cb scale, and SD Cr scale) control the scaling of the SD Y, Cb, and Cr output levels.

The SD Y scale register contains the scaling factor used to scale the Y level from 0.0 to 1.5 times its initial level. The SD Cb scale and SD Cr scale registers contain the scaling factors used to scale the Cb and Cr levels from 0.0 to 2.0 times their initial levels, respectively.

The registers needed to scale the outputs are

contrast[7:0] ,

cb_scale[9:0] and cr_scale[9:0] .

contrast[7:0] , IO Map, Address 0x1A2B[7:0]

This register is used to adjust the contrast value for Y channel. This register uses 1.7 notation.

Function contrast[7:0]

0x00

0x80 

0xFF

Description

Gain of 0

Unity gain

Gain of 2 cb_scale[9:0] , Encoder Map, Address 0xE49E[7:0]; Address 0xE49C[3:2]

This signal is used to set the SD Cb scale value. cr_scale[9:0] , Encoder Map, Address 0xE49F[7:0]; Address 0xE49C[5:4]

This signal is used to set the SD Cr scale value.

To use this function, the values to be written to these 10-bit registers are calculated using the following equation:

Y, Cb, or Cr Scale Value = Scale Factor × 512

For example, if Scale Factor = 1.3

Y, Cb, or Cr Scale Value = 1.3 × 512 = 665.6

Y, Cb, or Cr Scale Value = 666 (rounded to the nearest integer)

Y, Cb, or Cr Scale Value = 1010 0110 10b

Reg 0xE49C, SD scale LSB register = 0x2A

Reg 0xE49D, SD Y scale register = 0xA6

Reg 0xE49E, SD Cb scale register = 0xA6

Reg 0xE49F, SD Cr scale register = 0xA6

Note:

It is recommended that the SD luma scale saturation feature, saturate_luma , be enabled when scaling the Y output level to avoid

excessive Y output levels. saturate_luma , Encoder Map, Address 0xE487[1]

This bit is used to enable the SD luma scale saturation.



Function saturate_luma

1

0 

8.4.12.

SD Hue Adjust Control

Description

Enabled

Disabled

When enabled, the SD hue adjust control register is used to adjust the hue on the SD composite and chroma outputs. To enable this feature,

hue_en must be programmed to 1.

hue_en , Encoder Map, Address 0xE487[2]

This bit is used to enable the hue adjust function.

Function hue_en Description

1

0 

Enabled

Disabled

Register 0xE4A0 contains the bits required to vary the hue of the video data, that is, the variance in phase of the subcarrier during active video with respect to the phase of the subcarrier during the color burst. The ADV8003 encoder provides a range of ±22.5° in increments of 0.17578125°. For normal operation (zero adjustment), this register is set to 0x80. Value 0xFF and value 0x00 represent the upper and lower limits, respectively, of the attainable adjustment in NTSC mode. Value 0xFF and value 0x01 represent the upper and lower limits, respectively, of the attainable adjustment in PAL mode.

The hue adjust value is calculated using the following equation:

Hue Adjust (°) = 0.17578125° (HCR d

− 128) where HCR d

is the hue adjust control register (decimal).

For example, to adjust the hue by +4°, write 0x97 to hue[7:0] .





 4

0 .

17578125 





+ 128 ≈ 151 d = 0 x 97 where the sum is rounded to the nearest integer.

To adjust the hue by −4°, write 0x69 to hue[7:0] .





 − 4

0 .

17578125 





+ 128 ≈ 105 d = 0 x 6 9 where the sum is rounded to the nearest integer. hue[7:0] , Encoder Map, Address 0xE4A0[7:0]

This register is used to set the SD hue adjust value.

Function hue[7:0] Description

0x00  SD hue adjust value



8.4.13.

SD Brightness Detect

The ADV8003 encoder core allows the user to monitor the brightness level of the incoming video data. This feature is used to monitor the average brightness of the incoming Y signal on a field-by-field basis. The information is read from the I 2 C and, based on this information, the color saturation, contrast, and brightness controls can be adjusted, for example, to compensate for very dark pictures.

The luma data is monitored in the active video area only. The average brightness I 2

every VSYNC signal. This can be monitored using bright_detect_val[7:0] .

C register is updated on the falling edge of bright_detect_val[7:0] , Encoder Map, Address 0xE4BA[7:0] (Read Only)

This register is used to adjust the SD brightness value. The higher the value, the higher the brightness level.

Function bright_detect_val[7:0]

0x00 

Description

Brightness value

8.4.14.

SD Brightness Control

When this feature is enabled, the SD brightness/WSS control register,

setup[6:0] , is used to control brightness by adding a programmable setup level onto the scaled Y data. To enable this feature, setup_en must be configured.

setup_en , Encoder Map, Address 0xE487[3]

This bit is used to enable the SD brightness control feature.

Function setup_en

1

0 

Description

Enabled

Disabled

For NTSC with pedestal, the setup can vary from 0 IRE to 22.5 IRE. For NTSC without pedestal and for PAL, the setup can vary from −7.5

IRE to +15 IRE. Refer to Figure 112 for more details.

The SD brightness control register is an 8-bit register. The seven LSBs of this 8-bit register are used to control the brightness level, which can be a positive or negative value.

For example, to add a +20 IRE brightness level to an NTSC signal with pedestal, the procedure is as follows:

0 × (SD Brightness Value) =

0 × (IRE Value × 2.015631) =

0 × (20 × 2.015631) = 0 × (40.31262) ≈ 0x28

To add a –7 IRE brightness level to a PAL signal, write 0x72 to setup[6:0] .

0 × (SD Brightness Value) =

0 × (IRE Value × 2.075631) =

0 × (7 × 2.015631) = 0x(14.109417) ≈ 0001110b

0001110b into twos complement = 1110010b = 0x72 setup[6:0] , Encoder Map, Address 0xE4A1[6:0]

This signal is used to specify the SD brightness value.



Function setup[6:0]

0x00 

Description

SD brightness value

Setup Level (NTSC) with Pedestal

22.5 IRE

15 IRE

7.5 IRE

15 IRE

7.5 IRE

0 IRE

0 IRE −7.5 IRE

1 Values in the range of 0x3F to 0x44 may result in an invalid output signal.

NTSC WITHOUT PEDESTAL

100 IRE

Table 82: Sample Brightness Control Values 1

Setup Level (NTSC) Without Pedestal Setup Level (PAL)

15 IRE

7.5 IRE

0 IRE

−7.5 IRE

+7.5 IRE

(

Brightness Control Value

setup[6:0] )

0x1E

0x0F

0x00

0x71

0 IRE

–7.5 IRE

NO SETUP

VALUE ADDED

POSITIVE SETUP

VALUE ADDED

NEGATIVE SETUP

VALUE ADDED

Figure 112: Examples of Brightness Control Values

8.4.15.

Double Buffering

Double buffered registers are updated once per field. Double buffering improves overall performance because modifications to register settings are not made during active video but take effect prior to the start of the active video on the next field. This can be enabled for

both SD and ED/HD using db_en and db_en_hdtv respectively.

8.4.15.1.

ED/HD Doubling Buffering db_en_hdtv , Encoder Map, Address 0xE433[7]

This bit is used to enable the double buffering on the appropriate ED/HD registers.

Function db_en_hdtv Description

0 

1

Cb after falling edge of HSync

Cr after falling edge of HSync

Double buffering can be activated on the following ED/HD functions: the ED/HD gamma A and gamma B curves and the ED/HD CGMS registers.

8.4.15.2.

SD Doubling Buffering db_en , Encoder Map, Address 0xE488[2]

This bit is used to enable double buffering on the appropriate SD registers.

Function db_en Description

1

0 

Rev. B, August 2013

Enabled

Disabled

326


Double buffering can be activated on the following SD functions: the SD gamma A and gamma B curves, SD Y scale, SD Cr scale, SD Cb scale, SD brightness, SD closed captioning, and SD Macrovision bits (Reg 0xE4E0, Bits [5:0]).

8.4.16.

Programmable DAC Gain Control

It is possible to adjust the DAC output signal gain up or down from its absolute level. This is illustrated in Figure 113 .

CASE A

GAIN PROGRAMMED IN DAC OUTPUT LEVEL

REGISTERS, SUBADDRESS 0x0A, 0x0B

700mV

300mV

CASE B

700mV

NEGATIVE GAIN PROGRAMMED IN

DAC OUTPUT LEVEL REGISTERS,

SUBADDRESS 0x0A, 0x0B

300mV

Figure 113: Programmable DAC Gain – Positive and Negative Gain

In Case A of Figure 113 , the video output signal is gained. The absolute level of the sync tip and the blanking level increase with respect to

the reference video output signal. The overall gain of the signal is increased from the reference signal.

In Case B of Figure 113 , the video output signal is reduced. The absolute level of the sync tip and the blanking level decrease with respect

to the reference video output signal. The overall gain of the signal is reduced from the reference signal.

The range of this feature is specified for ±7.5% of the nominal output from the DACs. For example, if the output current of the DAC is

4.33 mA, the DAC gain control feature can change this output current from 4.008 mA (−7.5%) to 4.658 mA (+7.5%). To enable the gain

for the relevant set of DACs, dac4to6_tuning[7:0]

and dac1to3_tuning[7:0] must be configured.

dac4to6_tuning[7:0] , Encoder Map, Address 0xE40A[7:0]

This register is used to set the gain for DACs 4-6 output voltage.



Function dac4to6_tuning[7:0]

11000000

11000001

11000010

11111111

00000000 

00000001

00000010

00111111

01000000

Description

-7.5%

-7.382%

-7.364%

…

-0.018%

0%

0.018%

0.036%

…

+7.382%

+7.5% dac1to3_tuning[7:0] , Encoder Map, Address 0xE40B[7:0]

This register is used to set the gain for DACs 1-3 output voltage.

Function dac1to3_tuning[7:0]

11000000

11000001

11000010

11111111

00000000 

00000001

00000010

00111111

01000000

Description

-7.5%

-7.382%

-7.364%

…

-0.018%

0%

0.018%

0.036%

…

+7.382%

+7.5%

The reset value of the control registers is 0x00; that is, nominal DAC current is output. Table 83 shows how the output current of the

DACs varies for a nominal 4.33 mA output current.

DAC Gain Register Value

0100 0000 (0x40)

0011 1111 (0x3F)

0011 1110 (0x3E)

…

…

0000 0010 (0x02)

0000 0001 (0x01)

0000 0000 (0x00)

1111 1111 (0xFF)

1111 1110 (0xFE)

…

…

1100 0010 (0xC2)

1100 0001 (0xC1)

1100 0000 (0xC0)

4.38

4.33

4.25

4.23

…

Table 83: DAC Gain Control

DAC Current (mA) % Gain

4.658

4.653

4.648

7.5000%

7.3820%

7.3640%

…

…

4.43

…

…

0.0360%

0.0180%

0.0000%

−0.0180%

−0.0360%

…

Note

Reset value, nominal

…

4.018

4.013

4.008

…

−7.3640%

−7.3820%

−7.5000%



8.4.17.

Gamma Correction

Generally, gamma correction is applied to compensate for the nonlinear relationship between the signal input and the output brightness level

(as perceived on a CRT). It can also be applied wherever nonlinear processing is used.

Gamma correction uses the function:

Signal

OUT

= ( Signal

IN

) γ where γ is the gamma correction factor.

Gamma correction is available for SD and ED/HD video. For both variations, there are twenty 8-bit registers, used to program the Gamma

Correction Curve A and Gamma Correction Curve B.

Gamma correction is performed on the luma data only. The user can choose one of two correction curves, Curve A or Curve B. Only one of these curves can be used at a time.

The shape of the gamma correction curve is controlled by defining the curve response at 10 different locations along the curve. By altering the response at these locations, the shape of the gamma correction curve can be modified. Between these points, linear interpolation is used to generate intermediate values. Considering that the curve has a total length of 256 points, the 10 programmable locations are at the following points: 24, 32, 48, 64, 80, 96, 128, 160, 192, and 224. The following locations are fixed and cannot be changed: 0, 16, 240, and

255.

From the curve locations, 16 to 240, the values at the programmable locations and, therefore, the response of the gamma correction curve, should be calculated to produce the following result: x

DESIRED

= (x

INPUT

) γ where: x

DESIRED

is the desired gamma corrected output. x

INPUT

is the linear input signal.

γ is the gamma correction factor.

To program the gamma correction registers, the 10 programmable curve values are calculated using Equation 26 .

γ n

=











 n

240

− 16

− 16 





γ

× ( 240 − 16 )







+ 16

Equation 26: Gamma Correction Calculation where:

γ n

is the value to be written into the gamma correction register for point n on the gamma correction curve. n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224.

γ is the gamma correction factor.

For example, setting γ = 0.5 for all programmable curve data points results in the following y n

values: y

24

= [(8/224) 0.5

× 224] + 16 = 58 y

32

= [(16/224) y

48

0.5

= [(32/224) 0.5

× 224] + 16 = 76

× 224] + 16 = 101 y

64

= [(48/224) 0.5

y

80 y

96

= [(64/224) 0.5

= [(80/224) 0.5

× 224] + 16 = 120

× 224] + 16 = 136

× 224] + 16 = 150 y

128

= [(112/224) y

160

0.5

= [(144/224) 0.5

× 224] + 16 = 174

× 224] + 16 = 195 y

192

= [(176/224) y

224

0.5

= [(208/224) 0.5

× 224] + 16 = 214

× 224] + 16 = 232



Where the sum of each equation is rounded to the nearest integer, these must then all be converted to hex.

The gamma curves in Figure 114 and Figure 115 are examples only; any user defined curve in the range from 16 to 240 is acceptable.

GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT

300

250

SIGNAL OUTPUT

200

150

0.5

100

SIGNAL INPUT

50

0

0 50 100 150 200 250

LOCATION

Figure 114: Signal Input (Ramp) and Signal Output for Gamma 0.5

300

GAMMA CORRECTION BLOCK TO A RAMP INPUT FOR

VARIOUS GAMMA VALUES

250

200

150

100

0.3

0.5

SIGN

AL

INP

UT

1.5

1.8

50

0

0 50 100 150 200 250

LOCATION

Figure 115: Signal Input (Ramp) and Selectable Output Curves

8.4.17.1.

ED/HD Gamma Correction

To enable the gamma correction curves for ED/HD standards, gamma_en_hdtv must be programmed.

gamma_en_hdtv , Encoder Map, Address 0xE435[5]

This bit is used to enable the gamma correction curves for ED/HD video data.

Function gamma_en_hdtv

0 

1

Description

Disabled

Enabled

The ED/HD gamma correction curves are provided in Table 84 and Table 85 .



Curve Type

ED/HD Gamma Curve A

ED/HD Gamma Curve A

ED/HD Gamma Curve A

ED/HD Gamma Curve A

ED/HD Gamma Curve A

ED/HD Gamma Curve A

ED/HD Gamma Curve A

ED/HD Gamma Curve A

ED/HD Gamma Curve A

ED/HD Gamma Curve A

Table 84: ED/HD Gamma Curve A

Point Register Address

(A0 – Point 24) 0xE444

(A1 – Point 32)

(A2 – Point 48)

0xE445

0xE446

(A3 – Point 64)

(A4 – Point 80)

(A5 – Point 96)

(A6 – Point 128)

0xE447

0xE448

0xE449

0xE44A

(A7 – Point 160)

(A8 – Point 192)

(A9 – Point 224)

0xE44B

0xE44C

0xE44D

Curve Type

ED/HD Gamma Curve B

Table 85: ED/HD Gamma Curve B

Point

(B0 – Point 24)

ED/HD Gamma Curve B

ED/HD Gamma Curve B

(B1 – Point 32)

(B2 – Point 48)

ED/HD Gamma Curve B

ED/HD Gamma Curve B

ED/HD Gamma Curve B

ED/HD Gamma Curve B

ED/HD Gamma Curve B

ED/HD Gamma Curve B

(B3 – Point 64)

(B4 – Point 80)

(B5 – Point 96)

(B6 – Point 128)

(B7 – Point 160)

(B8 – Point 192)

Register Address

0xE44E

0xE44F

0xE450

0xE451

0xE452

0xE453

0xE454

0xE455

0xE456

ED/HD Gamma Curve B (B9 – Point 224) 0xE457

To select between both the A and B curves for the ED/HD gamma correction, the gamma_curve_b_hdtv must be programmed.

gamma_curve_b_hdtv , Encoder Map, Address 0xE435[4]

This bit is used to select the gamma correction curves for ED/HD video data.

Function gamma_curve_b_hdtv

0 

1

Description

Gamma correction curve A

Gamma correction curve B

8.4.17.2.

SD Gamma Correction

To enable the gamma correction curves for SD standards, gamma_en

must be programmed. gamma_en , Encoder Map, Address 0xE488[6]

This bit is used to enable the gamma correction curves for SD video data.

Function gamma_en Description

1

0 

Enabled

Disabled

The SD gamma correction curves are provided in Table 86 .



Curve Type

Table 86: SD Gamma Curve A

Point

SD Gamma Curve A (A0 – Point 24)

Register Address

0xA6



0xA7

0xA8



0xA9

0xAA

SD Gamma Curve A (A5 – Point 96) 0xAB

SD Gamma Curve A (A6 – Point 128) 0xAC

SD Gamma Curve A (A7 – Point 160) 0xAD

SD Gamma Curve A (A8 – Point 192) 0xAE

SD Gamma Curve A (A9 – Point 224) 0xAF

SD Gamma Curve B (B0 – Point 24) 0xB0

SD Gamma Curve B (B1 – Point 32)




0xB1

0xB2

0xB3

0xB4






To select between both the A and B curves, gamma_curve_b must be programmed.

gamma_curve_b , Encoder Map, Address 0xE488[7]

This bit is used to select the gamma correction curves for SD video data.

Function gamma_curve_b

0 

1

Description

Gamma correction curve A

Gamma correction curve B

8.4.18.

ED/HD Sharpness Filter and Adaptive Filter Controls

There are three filter modes available on the ADV8003 encoder block: a sharpness filter mode and two adaptive filter modes.

8.4.18.1.

ED/HD Sharpness Filter Mode

To enhance or attenuate the Y signal in the frequency ranges shown in Figure 116 , the ED/HD sharpness filter must be enabled ( sharp_en set to 1) and the ED/HD adaptive filter must be disabled ( adapt_en set to 0).



INPUT

SIGNAL

STEP

0.9

0.8

0.7

0.6

0.5

1.5

1.4

1.3

1.2

1.1

1.0

SHARPNESS AND ADAPTIVE FILTER CONTROL BLOCK

1.5

1.4

1.6

1.5

1.3

1.2

1.1

1.0

1.4

1.3

0.9

1.2

0.8

0.7

1.1

0.6

FREQUENCY (MHz)

FILTER A RESPONSE (Gain Ka)

0.5

FREQUENCY (MHz)

FILTER B RESPONSE (Gain Kb)

1.0

0 2 4 6 8 10

FREQUENCY (MHz)

12

FREQUENCY RESPONSE IN SHARPNESS

FILTER MODE WITH Ka = 3 AND Kb = 7

Figure 116: ED/HD Sharpness and Adaptive Filter Control Block

To enable the ED/HD sharpness filter, the following bit must be written to. sharp_en , Encoder Map, Address 0xE431[7]

This bit is used to enable the ED/HD sharpness filter on the luma data. By default this is set to 0 which means the filter is disabled.

Function sharp_en

0 

1

Description

Disabled

Enabled

Likewise, the adaptive filter must be disabled by writing to the following bit. adapt_en , Encoder Map, Address 0xE435[7]

This bit is used to enable the ED/HD adaptive filter.

Function adapt_en

0 

1

Description

Disabled

Enabled

To select one of the 256 individual responses, the corresponding gain values, ranging from –8 to +7 for each filter, must be programmed

into the ED/HD sharpness filter gain register. These are programmed using kb[3:0]

and ka[3:0] .

kb[3:0] , Encoder Map, Address 0xE440[7:4]

This signal is used to configure the ED/HD sharpness filter gain, value B.



Function kb[3:0]

0000 

0001

0111

1000

1110

1111

Description

Gain B 0

Gain B +1

…

Gain B +7

Gain B -8

…

Gain B -2

Gain B -1 ka[3:0] , Encoder Map, Address 0xE440[3:0]

This signal is used to configure the ED/HD sharpness filter gain, value A.

Function ka[3:0]

0000 

0001

0111

1000

1110

1111

Description

Gain A 0

Gain A +1

…

Gain A +7

Gain A -8

…

Gain A -2

Gain A -1

8.4.18.2.

ED/HD Adaptive Filters

The ED/HD adaptive filter (Threshold A, Threshold B, and Threshold C) registers, the ED/HD adaptive filter (Gain 1, Gain 2, and Gain 3) registers, and the ED/HD sharpness filter gain register are used in adaptive filter mode. To activate the adaptive filter control, the ED/HD sharpness filter and the ED/HD adaptive filter must be enabled. Refer to the register tables above for enabling and disabling the sharpness and adaptive filter.

The derivative of the incoming signal is compared to the three programmable threshold values; that is the ED/HD adaptive filter

(Threshold A, Threshold B, and Threshold C) registers. These registers ( thold_a[7:0] , thold_b[7:0]

and thold_c[7:0] ) are described below.

The recommended threshold range is 16 to 235, although any value in the range of 0 to 255 can be used. thold_a[7:0] , Encoder Map, Address 0xE45B[7:0]

This register is used to set the ED/HD adaptive filter threshold A.

Function thold_a[7:0]

Default

Description

0x00 thold_b[7:0] , Encoder Map, Address 0xE45C[7:0]

This register is used to set the ED/HD adaptive filter threshold B.



Function thold_b[7:0]

Default

Description

0x00

thold_c[7:0] , Encoder Map, Address 0xE45D[7:0]

This register is used to set the ED/HD adaptive filter threshold C.

Function thold_c[7:0]

Default

Description

0x00

The edges can then be attenuated with the settings in the ED/HD adaptive filter (Gain 1, Gain 2, and Gain 3) registers. Refer to the

registers fil_resp_aa[3:0] , fil_resp_ab[3:0] , fil_resp_bb[3:0] ,

fil_resp_ca[3:0] and fil_resp_cb[3:0] for details on setting the adaptive filter

gains. fil_resp_ab[3:0] , Encoder Map, Address 0xE458[7:4]

This signal is used to set the adaptive filter gain 1 for the ED/HD standard. This is value B.

Function fil_resp_ab[3:0] Description

0000 

0001

0111

1000

1110

1111

Gain B 0

Gain B +1

...

Gain B +7

Gain B -8

...

Gain B -2

Gain B -1 fil_resp_aa[3:0] , Encoder Map, Address 0xE458[3:0]

This signal is used to set the adaptive filter gain 1 for the ED/HD standard. This is value A.

Function fil_resp_aa[3:0] Description

0000 

0001

0111

1000

1110

1111

Gain A 0

Gain A +1

...

Gain A +7

Gain A -8

...

Gain A -2

Gain A -1 fil_resp_bb[3:0] , Encoder Map, Address 0xE459[7:4]




Function fil_resp_bb[3:0]

0000 

0001

0111

1000

1110

1111

Description

Gain B 0

Gain B +1

...

Gain B +7

Gain B -8

...

Gain B -2

Gain B -1 fil_resp_cb[3:0] , Encoder Map, Address 0xE45A[7:4]


Function fil_resp_cb[3:0]

0000 

0001

0111

1000

1110

1111

Description

Gain B 0

Gain B +1

...

Gain B +7

Gain B -8

...

Gain B -2

Gain B -1 fil_resp_ca[3:0] , Encoder Map, Address 0xE45A[3:0]

This signal is used to set the adaptive filter gain 3 for the ED/HD standard. This is value A.

Function fil_resp_ca[3:0]

0000 

0001

0111

1000

1110

1111

Description

Gain A 0

Gain A +1

...

Gain A +7

Gain A -8

...

Gain A -2

Gain A -1

8.4.18.3.

ED/HD Adaptive Filter Modes

Two adaptive filter modes are available: mode A and mode B.

Mode A is used when the ED/HD adaptive filter mode control is set to 0. In this case, filter B (LPF) is used in the adaptive filter block. In addition, only the programmed values for Gain B in the ED/HD sharpness filter gain register and ED/HD adaptive filter (Gain 1, Gain 2, and Gain 3) registers are applied when needed. The Gain A values are fixed and cannot be changed.

Mode B is used when ED/HD adaptive filter mode control is set to 1. In this mode, a cascade of filter A and filter B is used. Both settings for Gain A and Gain B in the ED/HD sharpness filter gain register and ED/HD adaptive filter (Gain 1, Gain 2, and Gain 3) registers

become active when needed. The mode is selected using adapt_bc .

adapt_bc , Encoder Map, Address 0xE435[6]

This bit is used to select the adaptive filter mode.



Function adapt_bc

0 

1

Description

Mode A

Mode B

8.4.18.4.

ED/HD Sharpness Filter and Adaptive Filter Application Examples

Sharpness Filter Application

The ED/HD sharpness filter can be used to enhance or attenuate the Y video output signal. The register settings in Table 87 are used to achieve the results shown in Figure 117 . Input data is generated by an external signal source. The reference in the table can be matched

with the appropriate scope plot.

Table 87: ED/HD Sharpness Control Settings for Figure 117

Register Register Setting Reference 1

0xE400

0xE401

0xFC

0x10

0xE402

0xE430

0xE431

0x20

0x00

0x81

0xE440

0xE440

0xE440

0xE440

0xE440

0xE440

0x00

0x08

0x04

0x40

0x80

0x22 a b c d e f

1

See Figure 117.

d a

R2 1 e b

R4 R1 c f

1 R2

CH1 500mV

REF A 500mV 4.00µs 1

M 4.00µs

9.99978ms

CH1

ALL FIELDS

CH1 500mV

REF A 500mV 4.00µs 1

M 4.00µs

9.99978ms

CH1

ALL FIELDS

Figure 117: ED/ HD Sharpness Filter Control with Different Gain Settings for ED/HD Sharpness Filter Gain Values

Adaptive Filter Control Application

The register settings in Table 88

are used to obtain the results shown in Figure 119 , that is, to remove the ringing on the input Y signal, as shown in Figure 118 . Input data is generated by an external signal source.

Rev. B, August 2013

Table 88: Register Settings for Figure 119

Register Register Setting

0xE400 0xFC

0xE401 0x38

0xE402 0x20

0xE430 0x00

337

Register Register Setting

0xE431 0x81

0xE435 0x80

0xE440 0x00

0xE458 0xAC

0xE459 0x9A

0xE45A 0x88

0xE45B 0x28

0xE45C 0x3F

0xE45D 0x64


Figure 118: Input Signal to ED/HD Adaptive Filter

The effects of selecting between the two adaptive filter modes (using adapt_bc)

can be seen in Figure 119 and Figure 120.

Figure 119: Output Signal from ED/HD Adaptive Filter (Mode A)

Rev. B, August 2013

Figure 120: Output Signal from ED/HD Adaptive Filter (Mode B)

338


8.4.19.

SD Digital Noise Reduction

The ADV8003 encoder block offers a feature for digital noise reduction (DNR). DNR is applied to the Y data only. A filter block selects the high frequency, low amplitude components of the incoming signal (DNR input select). The absolute value of the filter output is compared to a programmable threshold value (DNR threshold control). Two DNR modes are available: DNR mode and DNR sharpness mode. Refer

to Figure 121 .

DNR MODE

DNR CONTROL

BLOCK SIZE CONTROL

BORDER AREA

BLOCK OFFSET

GAIN

CORING GAIN DATA

CORING GAIN BORDER

NOISE

SIGNAL PATH

INPUT FILTER

BLOCK

Y DATA

INPUT

FILTER

OUTPUT

< THRESHOLD?

FILTER OUTPUT

> THRESHOLD

MAIN SIGNAL PATH

+

–

SUBTRACT

SIGNAL IN

THRESHOLD

RANGE FROM

ORIGINAL SIGNAL

DNR OUT

DNR

SHARPNESS

MODE

DNR CONTROL

BLOCK SIZE CONTROL

BORDER AREA

BLOCK OFFSET

GAIN

NOISE

SIGNAL PATH

CORING GAIN DATA

CORING GAIN BORDER

INPUT FILTER

BLOCK

Y DATA

INPUT

FILTER

OUTPUT

> THRESHOLD?

ADD SIGNAL

ABOVE

THRESHOLD

RANGE FROM

ORIGINAL SIGNAL

FILTER OUTPUT

< THRESHOLD

+

+

MAIN SIGNAL PATH

DNR OUT

Figure 121: SD DNR Block Diagram

In DNR mode, if the absolute value of the filter output is smaller than the threshold, it is assumed to be noise. A programmable amount

(coring gain border, coring gain data) of this noise signal is subtracted from the original signal. In DNR sharpness mode, if the absolute value of the filter output is less than the programmed threshold, it is assumed to be noise. Otherwise, if the level exceeds the threshold, now identified as a valid signal, a fraction of the signal (coring gain border, coring gain data) is added to the original signal to boost high frequency components and sharpen the video image.

In MPEG systems, it is common to process the video information in blocks of 8 pixels × 8 pixels for MPEG2 systems or 16 pixels × 16 pixels for MPEG1 systems (block size control). DNR can be applied to the resulting block transition areas that are known to contain noise.

Generally, the block transition area contains two pixels. It is possible to define this area to contain four pixels (border area).

It is also possible to compensate for variable block positioning or differences in YCrCb pixel timing with the use of the DNR block offset.

The digital noise reduction registers are three 8-bit registers. They are used to control the DNR processing.

To enable the SD DNR feature, dnr_en must be programmed.

dnr_en , Encoder Map, Address 0xE481[7]

This bit is used to enable the SD Digital Noise Reduction (DNR) function.



8.4.19.1.

Function dnr_en

1

0 

Coring Gain Border

Description

Enabled

Disabled

dnr_coring_gain_a[3:0]

is the gain factor applied to border areas (refer to Figure 127 for more information on border areas). In DNR

mode, the range of gain values is 0 to -1 in decrements of 1/8. This factor is applied to the DNR filter output that lies below the set threshold range. The result is then subtracted from the original signal.

In DNR sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. This factor is applied to the DNR filter output that lies above the threshold range. The result is added to the original signal. dnr_coring_gain_a[3:0] , Encoder Map, Address 0xE4A3[7:4]

This signal is used to configure the coring gain border (in Digital Noise Reduction (DNR) mode, the values in brackets apply).

Function dnr_coring_gain_a[3:0]

0000 

0001

0010

0011

0100

0101

0110

0111

1000

Description

No gain

+1/16 [−1/8]

+2/16 [−2/8]

+3/16 [−3/8]

+4/16 [−4/8]

+5/16 [−5/8]

+6/16 [−6/8]

+7/16 [−7/8]

+8/16 [−1]

8.4.19.2.

Coring Gain Data

dnr_coring_gain_b[3:0]

is the gain factor applied to the luma data inside the MPEG pixel block. In DNR mode, the range of gain values is

0 to -1 in decrements of 1/8. This factor is applied to the DNR filter output that lies below the set threshold range. The result is then subtracted from the original signal.

In DNR sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. This factor is applied to the DNR filter output that lies

above the threshold range. The result is added to the original signal. Figure 122 explains the difference between SD DNR border gain and

data gain.

APPLY DATA

CORING GAIN

APPLY BORDER

CORING GAIN

O X X X X X X O O X X X X X X O

O X X X X X X O O X X X X X X O

OFFSET CAUSED

BY VARIATIONS IN

INPUT TIMING

DNR27 TO DNR24 = 0x01 O X X X X X X O O X X X X X X O

Figure 122: SD DNR Offset Control


ADV8003 Hardware Manual dnr_coring_gain_b[3:0] , Encoder Map, Address 0xE4A3[3:0]

This signal is used to configure the coring gain data (in Digital Noise Reduction (DNR) mode, the values in brackets apply).

Function dnr_coring_gain_b[3:0] Description

0000 

0001

0010

0011

0100

0101

0110

0111

1000

No gain

+1/16 [−1/8]

+2/16 [−2/8]

+3/16 [−3/8]

+4/16 [−4/8]

+5/16 [−5/8]

+6/16 [−6/8]

+7/16 [−7/8]

+8/16 [−1]

8.4.19.3.

DNR Threshold

dnr_threshold[5:0] is used to define the threshold value in the range of 0 to 63. The range is an absolute value.

dnr_threshold[5:0] , Encoder Map, Address 0xE4A4[5:0]

This signal is used to configure the Digital Noise Reduction (DNR) threshold.

Function dnr_threshold[5:0] Description

000000 

000001

111110

111111

0

1

...

62

63

8.4.19.4.

Border Area

When blk_border_2 is set to 1, the block transition area can be defined to consist of four pixels. If this bit is set to logic 0, the border

transition area consists of two pixels, where one pixel refers to two clock cycles at 27 MHz.

720 × 485 PIXELS

(NTSC)

TWO-PIXEL

BORDER DATA

8 × 8 PIXEL BLOCK 8 × 8 PIXEL BLOCK

Figure 123: SD DNR Border Area blk_border_2 , Encoder Map, Address 0xE4A4[6]

This bit is used to select the Digital Noise Reduction (DNR) border area.



Function blk_border_2

0 

1

8.4.19.5.

Block Size Control

Description

2 pixels

4 pixels

dnr_mpeg_1 is used to select the size of the data blocks to be processed. Setting the block size control function to 1 defines a 16 pixel × 16

pixel data block, and 0 defines an 8 pixel × 8 pixel data block, where one pixel refers to two clock cycles at 27 MHz. dnr_mpeg_1 , Encoder Map, Address 0xE4A4[7]

This bit is used to select the Digital Noise Reduction (DNR) block size.

Function dnr_mpeg_1 Description

1

0 

16 pixels

8 pixels

8.4.19.6.

DNR Input Select Control

dnr_fmode_control[2:0] is used to select the filter which is applied to the incoming Y data. The signal that lies in the pass band of the selected filter is the signal that is DNR processed. Figure 124 shows the filter responses selectable with this control.

1.0

FILTER D

0.8

FILTER C

0.6

0.4

FILTER B

0.2

FILTER A

0

0 1 2 3 4

FREQUENCY (MHz)

5

Figure 124: SD DNR Input Filter Select

6 dnr_fmode_control[2:0] , Encoder Map, Address 0xE4A5[2:0]

This signal is used to configure the Digital Noise Reduction (DNR) input filter.

Function dnr_fmode_control[2:0] Description

001

010

011

100

Filter A

Filter B

Filter C

Filter D

8.4.19.7.

DNR Mode Control

DNR works on the principle of defining low amplitude, high frequency signals as probable noise and subtracting this noise from the original signal.



In DNR mode, it is possible to subtract a fraction of the signal that lies below the set threshold, assumed to be noise, from the original

signal. The threshold is set using dnr_threshold[5:0] .

When dnr_enable_sharpness is enabled, it is possible to add a fraction of the signal that lies above the set threshold to the original signal

because this data is assumed to be valid data and not noise. The overall effect is that the signal is boosted (similar to using the extended

SSAF filter). dnr_enable_sharpness , Encoder Map, Address 0xE4A5[3]

This bit is used to select the Digital Noise Reduction (DNR) mode.

Function dnr_enable_sharpness

0 

1

Description

DNR mode

DNR sharpness mode

8.4.19.8.

DNR Block Offset Control

blk_offset[3:0] allows a shift of the data block of 15 pixels maximum. The coring gain positions are fixed. The block offset shifts the data

in steps of one pixel so that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data. blk_offset[3:0] , Encoder Map, Address 0xE4A5[7:4]

This signal is used to configure the Digital Noise Reduction (DNR) block offset.

Function blk_offset[3:0]

0000 

0001

1110

1111

Description

Zero pixel offset

One pixel offset

...

14 pixel offset

15 pixel offset

8.4.19.9.

SD Active Video Edge Control

The ADV8003 encoder core is able to control fast rising and falling signals at the start and end of active video in order to minimize ringing artifacts.

When the active video edge control feature is enabled, the first three pixels and the last three pixels of the active video on the luma

channel are scaled so that maximum transitions on these pixels are not possible. This feature is highlighted in Figure 125 .

At the start of active video, the first three pixels are multiplied by 1/8, 1/2, and 7/8, respectively. Approaching the end of active video, the

last three pixels are multiplied by 7/8, 1/2, and 1/8, respectively. All other active video pixels pass through unprocessed. Figure 126 and

Figure 127 show the difference between having this feature enabled and disabled. This feature can be enabled using slope_en .

LUMA CHANNEL WITH

ACTIVE VIDEO EDGE

DISABLED

LUMA CHANNEL WITH

ACTIVE VIDEO EDGE

ENABLED

100 IRE 100 IRE

87.5 IRE

0 IRE

50 IRE

12.5 IRE

0 IRE

Figure 125: Example of Active Video Edge Functionality



VOLTS IRE:FLT

100

0.5

50

0 0

0

F2

L135

–50

2 4 6 8 10 12

Figure 126: Example of Video Output with SD Active Video Edge Control Disabled

VOLTS IRE:FLT

100

0.5

50

0

0

–2

F2

L135

–50

0 2 4 6 8 10 12

Figure 127: Example of Video Output with SD Active Video Edge Control Enabled slope_en , Encoder Map, Address 0xE482[7]

This bit is used to enable the SD active video edge control.

Function slope_en

1

0 

Description

Enabled

Disabled

If a pattern with sharp transitions is being output through the encoder and the user does not want

slope_en to have an effect because it

softens the edges, it is possible to use

sd_under_limiter[1:0] and

sd_y_min_value to control possible ringing artifacts on the output of the

encoder. sd_under_limiter[1:0] , Encoder Map, Address 0xE489[1:0]

This signal is used to configure the SD undershoot limiter.

Function sd_under_limiter[1:0] Description

00 

01

10

11

Disabled

-11IRE

-6IRE

-1.5IRE


ADV8003 Hardware Manual sd_y_min_value , Encoder Map, Address 0xE48A[6]

This bit is used to configure the SD minimum luma value.

Function sd_y_min_value Description

0 

1

-40IRE

-7.5IRE

8.5.

VERTICAL BLANKING INTERVAL

The ADV8003 is capable of accepting input VBI data (for example, CGMS, WSS, and CCAP) in SD, ED and HD modes. If VBI is disabled,

for SD mode, see vbi_open , for HD mode, see vbi_data_en . VBI data is not present at the encoder output and the entire VBI is blanked.

These control bits are valid in all modes.

For SMPTE 293M (525p), VBI data can be inserted on Lines 13 to 42 of each frame. For ITU-R BT.1358 (625p), VBI data can be inserted on Lines 6 to 43 For NTSC, VBI data can be inserted on Lines 10 to 20. For PAL, VBI data can be inserted on Lines 7 to 22.

If CGMS is enabled and VBI is disabled, the CGMS data is available at the output. vbi_open , Encoder Map, Address 0xE483[4]

This bit is used to enable data on the Vertical Blanking Interval (VBI) to be accepted as valid data. This is valid for SD video data only.

Function vbi_open

1

0 

Description

Enabled

Disabled vbi_data_en , Encoder Map, Address 0xE483[4]

This bit is used to enable data on the Vertical Blanking Interval (VBI) to be accepted as valid data. This is valid for SD video data only.

Function vbi_data_en Description

1

0 

Enabled

Disabled



8.6.

DAC CONFIGURATIONS

The ADV8003 encoder features six DACs which all operate in low-drive mode. Low-drive mode is defined as 4.33 mA full-scale current into a 300 Ω load, R

L

.

The ADV8003 encoder has two R

SET

pins which are used to control the full-scale DAC output current and, therefore, the DAC output voltage levels; this is achieved through a resistor connected between the R

SET

pin and GND. For low-drive operation, both R

SET1

and R

SET2 must have a value of 4.12 kΩ, and R

L

must have a value of 300 Ω.

The resistors connected to the R tolerance.

SET1

and R

SET2

pins should have a 1%

The ADV8003 encoder uses two pins for compensating the DAC reference buffer, COMP1 and COMP2. A 2.2 nF capacitor should be connected from each of these pins to AVDD2.

8.6.1.

Voltage Reference

The ADV8003 contains an on-chip voltage reference that can be used as a board level voltage reference via the V

REF

ADV8003 can be used with an external voltage reference by connecting the reference source to the V

REF

pin. Alternatively, the

pin. For optimal performance, an external voltage reference such as the AD1580 is used with the ADV8003 encoder reference voltage. If an external voltage reference is not used, a 0.1 µF capacitor should be connected from the V

REF

pin to AVDD2.

8.6.2.

Video Output Buffer and Optional Output Filter

A video buffer is necessary on the DAC outputs to match the 300Ω output impedance of the ADV8003 encoder output to the 75Ω input impedance of the sink device. ADI produces a range of op amps suitable for this application, for example, the AD8061 . For more information about line driver buffering circuits, refer to the relevant op amp datasheet.

An optional reconstruction (anti-imaging) low-pass filter (LPF) may be required on the ADV8003 encoder processor DAC outputs if the part is connected to a device that requires this filtering.

The filter specifications vary with the application. The use of 16× (SD), 8× (ED), or 4× (HD) oversampling can remove the requirement

for a reconstruction filter altogether. Refer to Section 8.4.1 for more details on output oversampling.

For applications requiring an output buffer and reconstruction filter, the ADA4430-1 , ADA4411-3 , and ADA4410-6 integrated video filter buffers should be considered.

Table 89: Output Filter Requirements

Application Oversampling Cutoff Frequency (MHz) Attenuation

–50 dB at

(MHz)

SD

SD

ED

2×

16×

1×

>6.5

>6.5

>12.5

20.5

209.5

14.5

ED

HD

HD

8×

1×

4×

>12.5

>30

>30

203.5

44.25

267

10µH

DAC

OUTPUT

600 Ω 22pF 600 Ω

3

1

75 Ω

BNC

OUTPUT

4

Rev. B, August 2013

560 Ω

560 Ω

Figure 128: Example of Output Filter for SD, 16× Oversampling

346

Rev. B, August 2013

4.7µH

DAC

OUTPUT

600Ω

6.8pF

6.8pF

600Ω

3

4

1

75Ω

BNC

OUTPUT

560Ω

560Ω

Figure 129: Example of Output Filter for ED, 8× Oversampling

DAC

OUTPUT

300 Ω

3

4

1

75Ω

390nH

33pF 33pF 75

Ω

3

1

BNC

OUTPUT

4

500

Ω

500Ω

Figure 130: Example of Output Filter for HD, 4× Oversampling

CIRCUIT FREQUENCY RESPONSE

0

0

–10

–20

–30

–40

–50

–60

–70

–80

1M

GROUP DELAY (Seconds)

10M 100M

FREQUENCY (Hz)

MAGNITUDE (dB)

PHASE (Degrees)

24n

–30

21n

–60

18n

–90

–120

15n

12n

–150

–180

9n

6n

–210

3n

–240

0

1G

Figure 131: Output Filter Plot for SD, 16× Oversampling


0 480

18n

–10 400

–20

–30

–40

–50

–60

–70

–80

–90

1M


10M 100M

FREQUENCY (Hz)

MAGNITUDE (dB)

16n

320

14n

PHASE

(Degrees)

240

12n

160

10n

80

8n

0

6n

–80

4n

–160

2n

–240

1G

0

Figure 132: Output Filter Plot for ED, 8× Oversampling


347

0

–10

–20

–30

–40


PHASE

(Degrees)

200

MAGNITUDE (dB)

120


40

–40

–120

–50

1 10 100

–200

FREQUENCY (MHz)

Figure 133: Output Filter Plot for HD, 4× Oversampling




9.

INTERRUPTS

The ADV8003 has a comprehensive set of interrupt registers located in the IO Map and HDMI Main Maps of both the Serial Video Rx and HDMI transmitters. These interrupts can be used to indicate certain events in the Serial Video Rx section, OSD, and VSP, and also the

HDMI Tx.

The ADV8003 features several interrupt controllers which handle three separate interrupt signals. These three interrupt signals are available on the interrupt pins INT0, INT1, and INT2. There is one interrupt available for the Serial Video Rx inputs, which is available for use on the interrupt INT2 pin. There is a shared interrupt available for both HDMI transmitters on INT1. There is also an interrupt pin made available to be used for a number of interrupts in the OSD core. These are available on INT0.

Note : The dual transmitter variants of ADV8003 are ADV8003KBCZ-8/7 and ADV8003KBCZ-8C/7C. The single transmitter variants of

ADV8003 are ADV8003KBCZ-8B/7B. Any references to interrupts relating to HDMI Tx2 are not applicable to these parts. The

ADV8003KBCZ-7T does not feature any HDMI transmitters. Any references to interrupts relating to either HDMI Tx1 or HDMI Tx2 are not applicable to this parts.

9.1.

INTERRUPT PINS

The ADV8003 features three dedicated interrupt pins, INT0, INT1, and INT2. These pins can be configured as open drain or standard IO pads and can be configured as outputs or inputs. By default, they are set to standard TTL inputs. The following registers are used for setting these pins. int_pin_od_en[2:0] , IO Map, Address 0x1ACC[2:0]

This signal is used to control the output configuration for the interrupt signals used by the device.

Function int_pin_od_en[2:0] Description

100

010

001

RX interrupt enabled

TX interrupt enabled

OSD interrupt enabled int_pin_oe[2:0] , IO Map, Address 0x1ACC[6:4]

This signal is used to control the polarity of the interrupt signals used by the device.

Function int_pin_oe[2:0]

100

010

001

Description

RX interrupt enabled

TX interrupt enabled

OSD interrupt enabled

9.1.1.

Interrupt Duration

The interrupt duration can be programmed independently for interrupt pin INT2. When an interrupt event occurs, the interrupt pin

INT2 becomes active with a programmable duration as described in this section. intrq_dur_sel[1:0] , IO Map, Address 0x1A69[3:2]

This signal is used to set the interrupt signal duration for the HDMI RX interrupts output on pin INT2.



Function intrq_dur_sel[1:0]

00 

01

10

11

Description

4 Xtal periods

16 Xtal periods

64 Xtal periods

Active until cleared

Note: When the active until cleared interrupt duration is selected and the event that caused an interrupt ends, the interrupt persists until it is cleared or masked.

9.1.2.

Storing Masked Interrupts store_unmasked_irqs , IO Map, Address 0x1A69[7]

This bit is used to specify whether the HDMI status flags for any HDMI interrupt should be triggered regardless of whether the mask bits are set. This bit allows an HDMI interrupt to trigger and allows this interrupt to be read back through the corresponding status bit without triggering an interrupt on the interrupt pin. The status is stored until the clear bit is used to clear the status register and allows another interrupt to occur.

Function store_unmasked_irqs

0 

1

Description

Do not store triggered interrupts

Store triggered interrupts

9.2.

SERIAL VIDEO RX INTERRUPTS

9.2.1.

Introduction

This section describes the interrupt support provided for the Serial Video Rx on the ADV8003. The Serial Video Rx interrupts are OR’d together and connected to the ADV8003 INT2 pin.

The ADV8003 Serial Video Rx interrupt architecture provides the following types of bits:

• Raw bits

• Status bits

• Interrupt mask bits

• Clear bits

Raw bits are defined as being either edge-sensitive or level-sensitive. The following compares an edge-sensitive interrupt and a levelsensitive interrupt to demonstrate the difference. level_sensitive_int_raw , IO, Address 0xXX (Read Only)

This readback indicates the raw status of the level sensitive interrupt. This bit is set to one when a condition occurs and is reset to 0 when the condition is no longer apparent.

Function level_sensitive_int_raw Description

0 

1

Event/condition not currently occuring

Event/condition currently occurring


ADV8003 Hardware Manual edge_sensitive_int_raw , IO, Address 0xXX (Read Only)

This readback indicates the status of the edge sensitive interrupt. When set to 1, it indicates that an event has occured. Once set, this bit remains high until the interrupt is cleared via edge_sensitive_int_clr.

Function edge_sensitive_int_raw Description

0 

1

No event/condition occured

Event/condition occured

Level-senstivitive bit, level_sensitive_int_raw , always represents the current status of whether or not a particular event or condition is occurring e.g. if the part is receiving AVI InfoFrames. It is not a latched bit and never requires to be cleared.

Edge-sensitive bit, edge_sensitive_int_raw , indicates that a transient event or condition has occurred; it is latched and it needs to be cleared. This approach is adopted for important events which have a transient nature e.g. if the part has received a new AVI Infoframe. If edge_sensitive_int_raw did not latch and returned to 0 some time after the event occurred, the user could miss the fact that the event or condition occurred. Therefore, edge-sensitive raw bits do not truly represent the current status; instead, the represent the status of an edge event that happened in the past. To clear a latched bit, the user must set the corresponding clear bit to 1.

Figure 134 ,

Figure 135 and Figure 136 provide a graphical example of what how edge and level sensitive interrups operate.

xxx_RAW xxx_ST

Interrupt path for level sensitive Interrupts

Internal

Status Flag

SAMPLING

CHANGE

DETECTION

(Rising and

Falling edge)

HOLD UNTIL

CLEARED

APPLY

MASK

Internal

Pulse Flag xxx_CLR xxx_MB1

OR yyy_CLR yyy_MB1

SAMPLING

CHANGE

DETECTION

(Rising edge)

HOLD UNTIL

CLEARED

APPLY

MASK

Interrupt path for edge sensitive Interrupts yyy_RAW yyy_ST

Figure 134: Level and Edge-sensitive Raw, Status and Interrupt Generation

INT

Output


AVI infoFrame

Detection

Internal Flag

AVI InfoFrame

Detected

No AVI

InfoFrame

Detected

AVI_INFO_RAW

AVI_INFO_ST

AVI_INFO_CLR set to 1

AVI_INFO_CLR set to 1

Time taken by the CPU to clear

AVI_INFO_ST

Figure 135: AVI_INFO_RAW and AVI_INFO_ST Timing

Time taken by the CPU to clear

AVI_INFO_ST

New AVI InfoFrame

Detection Internal

Pulse Flag

NEW_AVI_INFO_RAW

AVI InfoFrame with new content detected

Time > 2 xtal periods

NEW_AVI_INFO_ST


NEW_AVI_INFO_CLR set to 1

Time taken by the

CPU to clear

NEW_AVI_INFO_ST

Figure 136: NEW_AVI_INFO_RAW and NEW_AVI_INFO_ST Timing

All raw bits have corresponding status bits. The status bits always work in the same manner whether the raw bit is edge or level-sensitive.

Status bits have the following characteristics:

• Enabled by setting the corresponding interrupt mask bit

• Always latched and must be cleared by the corresponding clear bit

For a given interrupt; when the interrupt mask bit is set, the interrupt status bit goes high and an interrupt is generated on the INT2 pin if the interrupt raw bit changes state. To return the interrupt status bit to low, the interrupt clear bit must be set. The status bits, interrupt mask bit and clear bits for level_sensitive_int and edge_sensitive_int are described here for completeness.


ADV8003 Hardware Manual level_sensitive_int_st , IO, Address 0xXX (Read Only)

This readback indicates the latched status of the level_sensitive_int_raw signal. This bit is only valid if enabled via the corresponding

INT1 interrupt mask bit. Once set, this bit remains high until the interrupt is cleared level_sensitive_int_clr.

Function level_sensitive_int_st Description

0 

1 level_sensitive_int_raw did not change state level_sensitive_int_raw changed state edge_sensitive_int _st , IO, Address 0xXX (Read Only)

This readback indicates the latched status for edge_sensitive_int_raw. This bit is only valid if enabled via the corresponding INT1 interrupt mask bit. Once set, this bit remains high until the interrupt is cleared via edge_sensitive_int_clr.

Function edge_sensitive_int_st

0 

1

Description edge_sensitive_int_raw not changed state edge_sensitive_int_raw changed state level_sensitive_int_clr , IO, Address 0xXX (Self-Clearing)

This control is used to clear the level_sensitive_int_st bits. This is a self clearing bit.

Function level_sensitive_int_clr Description

0 

1

No function

Clear level_sensitive_int_st edge_sensitive_int _clr , IO, Address 0xXX (Self-Clearing)

This control is used to clear the edge_sensitive_int_raw and edge_sensitive_int_st bits. This is a self clearing bit.

Function edge_sensitive_int_clr

0 

1

Description

No function

Clear edge_sensitive_int_raw and edge_sensitive_int_st level_sensitive_int_mb2 , IO, Address 0xXX[0]

This control is used to set the INT2 interrupt mask for the level_sensitive_int interrupt. When set, when the level sensitive interrupt event triggers and an interrupt is generated on INT2.

Function level_sensitive_int_mb2

0 

1

Description

Disable level_sensitive_int detection interrupt for INT2

Enable level_sensitive_int detection interrupt for INT2 edge_sensitive_int _mb2 , IO, Address 0xXX

This control is used to set the INT2 interrupt mask for the edge_sensitive_int interrupt. When set, a new edge sensitive interrupt event will cause edge_sensitive_int_st to be set and an interrupt will be generated on INT2.



Function edge_sensitive_int_mb2

0 

1

Description

Disable edge_sensitive_int detection interrupt for INT2

Enable edge_sensitive_int detection interrupt for INT2

In this section, all raw bits are classified as being triggered by either level-sensitive or edge-sensitive events, with the following understanding of the terminology.

Level-sensitive events are events that are generally either high or low and which are not expected to change rapidly. The raw bit for levelsensitive events is not latched and, therefore, always represents the true real-time status of the event in question.

Edge-sensitive events are events that only exist for an instant. The raw bits for edge-sensitive events are latched and, therefore, represent the occurrence of an edge-sensitive event that happened in the past. Raw bits for edge-sensitive events must be cleared by the corresponding clear bit.

9.2.2.

Interrupt Architecture Overview

The following is a complete list of Serial Video Rx interrupts, their mode of operation (edge or level sensitive) and a description of each interrupt.

Interrupt rx_cable_det_raw/st/mb1/clr rx_tmdspll_lck_raw/st/mbx/clr rx_tmds_clk_det_raw/st/mbx/clr rx_video_3d_raw/st/mbx/clr rx_av_mute_raw/st/mbx/clr rx_hdmi_mode_raw/st/mbx/clr rx_gen_ctl_pckt_raw/st/mbx/clr rx_gamut_mdata_ pckt_raw/st/mbx/clr rx_isrc2_pckt_raw/st/mbx/clr rx_isrc1_pckt_raw/st/mbx/clr rx_vs_info_frm_raw/st/mbx/clr rx_ms_info_frm_raw/st/mbx/clr rx_spd_info_frm_ raw/st/mbx/clr rx_avi_info_frm_raw/st/mbx/clr

Table 90: Serial Video Rx Level Sensitive Interrupts

Mode of Operation Description

Level sensitive Used to detect if the Serial Video inputs are connected to an upstream IC

Level sensitive

Level sensitive

Used to indicate if the TMDS PLL has locked to the incoming TMDS clock

Used to indicate activity on the TMDS clock line

Level sensitive

Level sensitive

Level sensitive

Level sensitive

Level sensitive

Used to indicate if the incoming video is 3D format

Used to indicate the AVMUTE value from the general control packet

Used to indicate if the incoming video is HDMI mode or DVI mode

Used to indicate if a general control packet has been detected

Used to indicate if a gamut metadata packet has been detected

Level sensitive

Level sensitive

Level sensitive

Level sensitive

Level sensitive

Level sensitive

Used to indicate if an ISRC2 packet has been detected

Used to indicate if an ISRC1 packet has been detected

Used to indicate if a vendor specific InfoFrame has been detected

Used to indicate if an MPEG source InfoFrame has been detected

Used to indicate if an SPD InfoFrame has been detected

Used to indicate if an AVI InfoFrame has been detected

Interrupt rx_vs_inf_cks_err_ edge_raw/st/mb2/clr rx_ms_inf_cks_err

_edge_ raw/st/mb2/clr

Table 91: Serial Video Rx Edge Sensitive Interrupts

Mode of Operation

Edge sensitive

Edge sensitive rx_spd_inf_cks_er r_edge_raw/st/mb2/clr rx_avi_inf_cks_err

_edge_raw/st/mb2/clr rx_deepcolor_chn g_edge_raw/st/mb2/clr

Edge sensitive

Edge sensitive

Edge sensitive rx_tmds_clk_chng

_edge_raw/st/mb2/clr

Edge sensitive rx_pkt_err_edge_ raw/st/mb2/clr Edge sensitive

Description

Used to indicate if there was an error with the vendor specific InfoFrame

Used to indicate if there was an error with the MPEG source InfoFrame

Used to indicate if there was an error with a SPD InfoFrame

Used to indicate if there was an error with the AVI InfoFrame

Used to indicate if the incoming video is deep color. The exact mode can be determined by reading the DEEP_COLOR_MODE register

Used to indicate if the incoming TMDS clock has changed frequency

Used to indicate if there was an error with any HDMI packet



Interrupt Mode of Operation rx_gamut_mdata_ pckt_edge_raw/st/mb2/clr rx_isrc2_pckt_edg eraw/st/mb2/clr rx_isrc1_pckt_edg eraw/st/mb2/clr rx_vs_info_frm_e dge_raw/st/mb2/clr rx_ms_info_frm_e dge_raw/st/mb2/clr rx_spd_info_frm_ edge_raw/st/mb2/clr rx_avi_info_frm_e dge_raw/st/mb2/clr

9.2.2.1.

Multiple Interrupt Events

Edge sensitive

Edge sensitive

Edge sensitive

Edge sensitive

Edge sensitive

Edge sensitive

Edge sensitive

Description

Used to indicate if a gamut metadata packet was detected

Used to indicate if an ISRC2 packet was detected

Used to indicate if an ISRC1 packet was detected

Used to indicate if a vendor specific InfoFrame was detected

Used to indicate if an MPEG source InfoFrame was detected

Used to indicate if a source product descriptor InfoFrame was detected

Used to indicate if an AVI InfoFrame was detected

If an interrupt event occurs, and then a second interrupt event occurs before the system controller has cleared or masked the first interrupt event, the ADV8003 does not generate a second interrupt signal. The system controller should check all unmasked interrupt status bits as more than one may be active.

9.2.3.

Serial Video Interrupts Validity Checking Process

All Serial Video interrupts have a set of conditions that must be taken into account for validation in the system firmware. When the

ADV8003 alerts the system controller with a Serial Video interrupt, the host must check that the following validity conditions for that interrupt are met before processing that interrupt. This is valid for all the interrupts described above.

• ADV8003 is configured in HMDI mode

• rx_tmds_clk_det_raw is set to 1 if the Serial Video Rx input is being used

• rx_tmdspll_lck_raw bit is set to 1

9.3.

VSP AND OSD SECTION

This section describes the interrupts provided by the ADV8003 OSD and VSP section. These interrupts are not accessed through the I2C interface as the interrupts for the Serial Video Rx and HDMI Tx are; these interrupts are accessed through the SPI interface. These interrupts are not documented in detail as they are handled transparently to the user by the Blimp OSD software tool. Interrupts from this section are output on the INT0 pin for use by the system microcontroller.

9.3.1.


The following three interrupts are required by the VSP and OSD section:

Interrupt

OSD_CFG_DONE

DMA_IRQ

DMA_RAM_IRQ

TIMER_IRQ

Table 92: VSP and OSD Interrupts

Description

Used to indicate to the system controller that the configuration within the ADV8003 RAM memories has completed

Used to indicate to the system controller that the current DMA operation has taken place

Used to indicate to the system controller that the DMA hardware block can be read from/written to by SPI

Used to indicate to the system controller that a timer has expired



Interrupt

ANIM_DONE_IRQ

Description

Used to indicate to the system controller that an animation has completed

The following controls are available to the user for indicating interrupts on the VSP and OSD interrupts. vsp_int_pol[1:0] , IO Map, Address 0x1A76[3:2]

This signal is used to control the VSP interrupt polarity.

Function vsp_int_pol[1:0] Description

00 

01

10

11

VSP interrupt is logical AND of VSP/OSD interrupts

VSP interrupt is inverted logical AND of VSP/OSD interrupts

VSP interrupt is logical OR of VSP/OSD interrupts

VSP interrupt is inverted logical OR of VSP/OSD interrupts

9.4.

HDMI TX CORE

9.4.1.

Introduction

This section describes the interrupt support provided for the HDMI Tx cores of the ADV8003. The HDMI Tx interrupts are OR’d together and connected to the ADV8003 INT1 pin.

The ADV8003 HDMI Tx interrupt architecture provides the following types of bits:

• Interrupt status/clear bits

• Interrupt mask bits

The interrupt status/clear bits are dual purpose; when an interrupt event or condition occurs, if the interrupt mask bit is set, the status bit gets latched to 1. The interrupt can only be cleared by writing a value of 1 to the status/clear bit.

The interrupts mask bits are used to selectively activate an interrupt bit on the interrupt out pin INT1. The interrupt output pin is active when one or more interrupts bits are set and their corresponding interrupt mask bit is also set. Note that any given mask bit does not affect its corresponding interrupt bit but only affects the level on the interrupt output pin INT1. The enables for all the HDMI transmitter interrupts are described below.

9.4.2.


The following is a complete list of HDMI Tx interrupts and their descriptions:

Interrupt hpd_int/ hpd_int_en rx_sense_int/ rx_sense_int_en vsync_int/ vsync_int_en

Table 93: HDMI Tx Interrupts

Description

Used to indicate the HDMI transmitter is connected to an HDMI Rx

Used to detect if an HDMI Rx is connected to the HDMI transmitter

Used to flag the falling edge on a VSync signal edid_ready_int/ edid_ready_int_en Used to indicate if the HDMI Rx EDID is ready for reading hdcp_authenticated_int/ hdcp_authenticated_int_en Used to indicate if the HDCP protocol has been authenticated ri_ready_int/ ri_ready_int_en hdcp_error_int/hdcp_error_int_en

Used to indicate if the HDCP Ri is ready

Used to indicate if a HDCP error has occurred bksv_flag_int/ bksv_flag_int_en cec_tx_ready_int/ cec_tx_ready_int_en cec_tx_arbitration_lost_int/ cec_tx_arbitration_lost_int_en

Used to indicate if the BKSV flag is set

Used to indicate that the CEC transmitter is ready

Used to indicate if the CEC master has lost arbitration

356 Rev. B, August 2013


Interrupt cec_tx_retry_timeout_int/ cec_tx_retry_timeout_int_en cec_rx_ready_int/ cec_rx_ready_int_en

Description

Used to indicate if the CEC master has failed to retransmit after the default timeout

Used to indicate if a new message is present in one of the CEC Rx buffers

9.4.3.

HDMI Tx Interrupt Polarity

This register is used to configure various logical operations which are available to the user when using the HDMI TX interrupts. tx_int_pol[1:0] , IO Map, Address 0x1A76[1:0]

This signal is used to control the TX interrupt polarity.

Function tx_int_pol[1:0] Description

00 

01

10

11

Tx interrupt is logical AND of Tx1/Tx2 interrupts

Tx interrupt is inverted logical AND of Tx1/Tx2 interrupts

Tx interrupt is logical OR of Tx1/Tx2 interrupts

Tx interrupt is inverted logical OR of Tx1/Tx2 interrupts



APPENDIX A

PCB LAYOUT RECOMMENDATIONS

The ADV8003 is a high precision, high speed, mixed signal device. It is important to have a well laid out PCB board in order to achieve the maximum performance from the part. The following sections are a guide for designing a board using the ADV8003.

Analogue/Digital Video Interface Outputs

The HDMI TMDS trace pairs must have a 100Ω differential impedance and should be routed in the shortest trace length possible to minimize the possibility of cross talk with other signals. The HDMI TMDS trace pairs must be routed on the same side of the PCB as the

ADV8003 and should not be routed through vias to any other layers. A solid plane must be maintained underneath the HDMI TMDS trace pairs for their full trace length. Any external ESD suppressors should be placed as close as possible to the HDMI connector to reduce the impact on impedance TDR measurements.

If the ADV8003KBCZ-8/8B/8C device is to support 3 GHz signals from the HDMI Txs, it is recommended the TMDS trace widths are set to 0.2 mm. The spacing of the traces, the height of the copper and the trace’s height above the ground plan should all be controlled to maintain the trace impedance with this trace width.

The encoder analog outputs must have a 75Ω characteristic impedance and should be routed in the shortest trace length possible to minimize the possibility of cross talk with other signals. To assist in reducing cross talk, ground traces can be added between adjacent encoder analog outputs. The encoder analog outputs must be routed on the same side of the PCB as the ADV8003 and should not be routed through vias to any other layers. A solid plane must be maintained underneath the encoder analog outputs for their full trace length. The termination resistors on the encoder analog outputs should be kept as close as possible to the ADV8003. Any external filtering on the encoder outputs should be placed as close as possible to the analog connectors.

External DDR2 Memory Requirements

The ADV8003 must be placed as close to and on the same side of the PCB as the external DDR2 memories. Balanced T-routing should be used for all shared connections between the ADV8003 and the external DDR2 memories. All traces should be 75Ω and impedance controlled to ensure robust timing. Traces should be routed on the same side of the PCB as the devices where possible. If this is not possible, all traces should be kept on the outer layers.

All differential signals (for example, DDR_CK and DDR_CKB) should be treated as described above. These signals should be routed in parallel and on the same side of the PCB. Match the DDR_CK trace length to DDR_CKB trace length to 20 mils (0.5 mm). Any stubs on the clock lines should be kept as short as possible to avoid signal reflections.

The following 4-byte wide data lanes should be matched to within 50 mils on the PCB layout. The precise matching of these signals is critical.

• DDR3_DM3, DDR_DQS3, DDR_DQSB3, DDR_DQ31 – DDR_DQ24




Different byte lanes are to be matched to 200 mils (5.08 mm) of each other. 47Ω series termination resistors should be placed as close to the source (ADV8003) as possible on the following signals:

• Address signals – DDR_A12-DDR_A0 and DDR_BA0-DDR_BA2

• Clock differential signals – DDR_CK and DDR_CKB (use discrete resistors for these two signals)

• Control signal – DDR_CKE and command signals – DDR_CSB, DDR_RASB, DDR_CASB, and DDR_WEB

• Data mask signals – DDR_DM3-DDR_DM0



47Ω series termination resistors should be placed in the middle of the trace on the following signals:

• Data bus signals – DDR_DQ31-DDR_DQ0

• Data strobe signals – DDR_DQS3 DDR_DQS3B-DDR_DQS0 DDR_DQS0B

The DDR2 reference voltage (DDR_VREF) should be routed as far away as possible from other signals to avoid any variations on the voltage. This trace should be wide. There should be a 100 nF decoupling cap close to the DDR2 reference voltage pins as well as the

ADV8003 reference pin.

Power Supply Bypassing

It is recommended to bypass each power supply pin with a 0.1 uF and a 10 nF capacitor where possible. The fundamental idea is to have a bypass capacitor within 0.5 cm of each power pin.

Current should flow from the power plane to the capacitor to the power pin. The power connection should not be made between the capacitor and the power pin. Generally, the best approach is to place a via underneath the 10 nF capacitor pads down to the power plane

(refer to Figure 137 ).

via to GND layer and GND pin

10nF 0.1uF

via to VDD pin VDD supply

Figure 137: Recommended Power Supply Decoupling

It is recommended to individually filter all supplies to prevent switching noise on some supplies coupling onto other more sensitive supplies. For example, DVDD consumes a significant amount of current and will also suffer significant switching noise. DVDD must be isolated from more sensitive supplies such as PVDD3, PVDD5 and PVDD6.

The DVDD and DVDD_DDR supplies should be connected to the same supply – PVDD_DDR should be filtered from DVDD to provide a noise free power supply.

It is recommended to use a single ground plane for the ADV8003. Careful attention must be paid to the layout of any internal power supply planes when traces run on adjacent layers – traces on a layer directly above or below a power supply layer must not cross between two power supply planes as this will impact the return current paths.

Table 94 shows the recommended decoupling for the ADV8003-8 parts to achieve optimum performance for 3 GHz modes from the

HDMI TX devices.



PSU

AVDD3

PVDD5

PVDD6

W22

W22 n/a

M21

M21

N21

N21 n/a

V21

V21

W21

W21 n/a

Table 94: Recommended PSU Decoupling for ADV8003-8 Parts

Ball Number Capacitance Required Placement

G23

G23

N22

N22

4 x 100nF

1 x 10nF

3 x 100nF

1 x 10nF

As close as possible to ADV8003




3 x 100nF

1 x 10nF

10uF

2 x 100nF

1 x 10nF

2 x 100nF

1 x 10nF

10uF

2 x 100nF

1 x 10nF

2 x 100nF

1 x 10nF

10uF



Place on AVDD3 trace after the EMC filter





Place on PVDD5 trace after the EMC filter





Place on PVDD5 trace after the EMC filter

General Digital Inputs and Outputs

The trace length that the digital inputs/outputs have to sink/source should be minimized. Longer traces have higher capacitance, which requires more current that can cause more internal digital noise. Shorter traces reduce the possibility of reflections. It is recommended to route traces in the shortest trace length possible and keep the number of layer transitions to a minimum.

If possible, the digital output driver capacitance loading should be limited to less than 15 pF. This can be accomplished easily by keeping traces short and by connecting the outputs to only one device. Loading the outputs with excessive capacitance increases the current transients inside the ADV8003, creating more digital noise on its power supplies.

Particular attention must be paid to the routing of clock and sync signals, for example, PCLK, OSD_CLK, HS, OSD_HS, VS, OSD_VS,

DE, OSD_DE, XTALN, and XTALP. Any noise that gets onto these signals can add jitter to the system. Therefore, the trace length should be minimized, and digital or other high frequency traces should not be run near it.

XTAL and Load Cap Value Selection

The ADV8003 requires a 27 MHz crystal. Figure 138 shows an example of a reference clock circuit for the ADV8003. Special care must be

taken when using a crystal circuit to generate the reference clock for the ADV8003. Small variations in reference clock frequency can impair the performance of the ADV8003.

X T A L

27MHz

C1 C2

47pF 47pF

Figure 138: Crystal Circuit

These guidelines are followed to ensure correct operation:

• Use the correct frequency crystal (27 MHz recommended). Tolerance should be 50 ppm or better.

• Know the C load for the crystal part number selected. The value of capacitors C1 and C2 must be matched to the C load specific crystal part number in the user’s system.

for the



To find C1 and C2, use the following formula:

C1 = C2 = 2(C load

– C stray

) - C pg where C stray is usually 2 to 3 pF, depending on board traces and C pg

(pin-to-ground-capacitance) is 4 pF for the ADV8003.

Example:

C load

= 30 pF, C1 = 50 pF, C2 = 50 pF (in this case, 47 pF is the nearest real-life cap value to 50 pF)

Encoder Component Placement

External component placement must be carefully considered – they should be kept as far away from noisy circuits as possible, as close to the ADV8003 as possible and preferably on the same layer as the ADV8003. The external loop filter (connected to PVDD3), COMP, termination resistors, V

REF

, and R

SETx

circuits must all be laid out carefully otherwise noise may couple onto the SD or HD encoder outputs.

Any external filter and buffer components connected to the encoder analog outputs should be placed close to the ADV8003 to minimize the possibility of noise cross talk between neighboring circuitry. The encoder analog output traces should be kept as short as possible to reduce the possibility of any signal integrity issues and to minimize the effect of trace capacitance on output bandwidth.

HDMI Transmitter Component Placement

External component placement must be carefully considered – they should be kept as far away as possible from noisy circuits, as close to the ADV8003 as possible and preferably on the same layer as the ADV8003. The R_TX1 and R_TX2 resistors and PVDD5 and PVDD6 power supplies must all be carefully laid out otherwise the HDMI transmitter performance, for example, HDMI compliance testing, may be reduced.

Power Supply Design and Sequencing

The ADV8003 requires only two regulators, one 3.3 V and one 1.8 V. The recommended power supply design is illustrated in Figure 139 .

If using more than one 1.8 V regulator to supply ADV8003, it must be ensured that DVDD_DDR, PVDD_DDR and DVDD are supplied by the same regulator.

The power-up sequence of the ADV8003 is as follows:

1.

Hold RESET and PDN pins low.

2.

Bring up the 3.3 V supplies (DVDD_IO, AVDD1, and AVDD2).

3.

A delay of a minimum of 20 ms is required from the point in which the 3.3 V reaches its minimum recommended value (that is,

3.14 V) before powering up the 1.8 V supplies.

4.

Bring up the 1.8 V supplies (DVDD, CVDD1, PVDD1, PVDD2, PVDD3, AVDD3, DVDD_DDR, and PVDD_DDR). These should be powered up together, that is, there should be a difference of less than 0.3 V between them.

5.

RESET may be pulled high after supplies have been powered up.

6.

A complete RESET is recommended after power up. This can be performed by the system microcontroller.


3.3V

Regulator

Filter

Filter

Filter

AVDD1

AVDD2

DVDDIO

R/C Delay

Enable

1.8V

Regulator

Filter

Filter

Filter

Filter

Filter

Filter

AVDD3

CVDD1

DVDD

DVDD_DDR

PVDD1

PVDD2

Filter

Filter

Filter

PVDD3

PVDD5

PVDD_DDR

Figure 139: Power Supply Design

ADV8003


Rev. B, August 2013

Figure 140: Power Supply Sequence

362

APPENDIX B

ADV8003 EVALUATION BOARD SCHEMATICS


Rev. B, August 2013

Figure 141: ADV8003 Schematic – Page 1

363


/HEAC+ CL DA C_GND 5V G_DET

Rev. B, August 2013


364


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APPENDIX C

ADV8003 EVALUATION BOARD LAYOUT


Figure 172: ADV8003 Layout – Page 1























APPENDIX D

PACKAGE OUTLINE DRAWING

Refer to Section

1.4.




APPENDIX E

UNUSED PIN LIST

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

Location Mnemonic

A1

Type

OSD_IN[23]/EXT_DIN[7] OSD video input/ miscellaneous digital

A2

A3

A4

A5

A6

A7

A8

OSD_DE

OSD_CLK/EXT_CLK

AUD_IN[1]

AUD_IN[2]

AUD_IN[5]

ARC2_OUT

MOSI1

OSD video sync

OSD video sync

Audio input

Audio input

Audio input

Description if Unused

Connect this pin to ground through a

4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.

Audio output Connect this pin to ground through a

4.7kΩ resistor.

Serial port control


4.7kΩ resistor.

SCK2

CS2

RESET

XTALN

PVDD2

NC

NC

CVDD1

RX_CN

RX_0N

RX_1N

RX_2N

CVDD1

RSET1

Serial port control

Serial port control



Power

No connect

No connect

Power

Rx input

Rx input

Rx input

Rx input

Power


1


4.7kΩ resistor.


4.7kΩ resistor.

This pin must be connected.


PLL Digital Supply Voltage (1.8 V

Float this pin.

Float this pin.


Float this pin.

Float this pin.

Float this pin.

Float this pin.


Float this pin.

).

A23

B1

B2

B3

B4

VREF Miscellaneous analog



OSD_VS

AUD_IN[0]

OSD video sync

Audio input

Float this pin.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.



Pin Type

Bi-directional digital IO



Digital input



Digital input

Digital input

Digital input

Digital output

Digital output

Digital output

Digital output

N/A

N/A

N/A

Digital output

Digital output

N/A

Digital input

Digital input

Digital input

Digital input

N/A

Analog input

Analog input



B13

B14

B15

B16

B17

B18

B19

B20

B21

B22


B5

B6

B7

B8

B9

B10

B11

B12

B23

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

AUD_IN[3]

SFL

ARC1_OUT

MISO1

MOSI2

MISO2

ALSB

XTALP

PVDD1

NC

NC

GND

RX_CP

RX_0P

RX_1P

RX_2P

GND

COMP1

DAC4

Rx input

GND

Miscellaneous

analog 1

Analog video output



GND

AUD_IN[4]

GND

Audio input

DSD_CLK

SCLK

SCL

SCK1

GND

INT0

PDN

GND

I

Type

Audio input

SFL


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.

Audio output Connect this pin to ground through a

4.7kΩ resistor.

Serial port control


4.7kΩ resistor.

Serial port control

Serial port control

I 2 C control


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.

This pin must be connected. Miscellaneous digital

Power

No connect

No connect

GND

Rx input

Rx input

Rx input


Float this pin.

Float this pin.

Ground.

Float this pin.

Float this pin.

Float this pin.

Audio input

Audio input

2 C control

Serial port control

GND



GND

Float this pin.

Ground.


4.7kΩ resistor.

Float this pin.


4.7kΩ resistor.


4.7kΩ resistor.

Ground.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.



4.7kΩ resistor.

Ground.


4.7kΩ resistor.


Ground.



N/A

Digital input

Digital input

Digital input

N/A

Digital input

N/A

Digital output

N/A

N/A

Pin Type

Digital input

Digital input

Digital output

Digital output

Digital output

Digital Input

Digital Input

N/A

N/A

Digital output

Digital output

N/A

Digital input

Digital input

Digital input

Digital input

N/A

Analog input

Analog output



D14

D15

D16

D17

D18

D19


C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D20

D21

D22

GND

NC

NC

RX_HPD

AVDD1

GND

GND

AVDD1

AVDD1

Type

GND

No connect

No connect

Rx input

Power

GND

GND

Power

Power


Ground.

Float this pin.

Float this pin.

Float this pin.

Serial Video Rx Inputs Analog Supply

(3.3 V).

Ground.

Ground.


(3.3 V).


(3.3 V).

Float this pin. DAC5

DAC6

Analog video output

Analog video output



Float this pin.


4.7kΩ resistor.


4.7kΩ resistor.


GND

DVDD_IO

MCLK

SDA

CS1

GND

INT1

INT2

DVDD_IO

TEST1

NC

NC

RX_5V

NC

NC

RTERM

AVDD2

AVDD2

DAC1

GND

Power

Audio input

I 2 C control

Serial port control

GND



Power


No connect

No connect

Rx input

No connect

No connect

Serial Video

Rx input


4.7kΩ resistor.

Ground.



4.7kΩ resistor.



4.7kΩ resistor.

Ground.


4.7kΩ resistor.


4.7kΩ resistor.


Float this pin.

Float this pin.

Float this pin.

Connect this pin to +5V.

Float this pin.

Float this pin.

Float this pin.

Power

Power

Encoder Analog Power Supply (3.3 V).

Encoder Analog Power Supply (3.3 V).

Analog video Float this pin.


Pin Type

N/A

Digital output

Digital output

Digital output

N/A

N/A

N/A

N/A

N/A

Analog output

Analog output




N/A

N/A

Digital input

N/A

Digital input

N/A

Digital output

Digital output

N/A

Digital output

Digital output

Digital output

Digital input

Digital input

Digital input

Analog input

N/A

N/A

Analog output



D23

E1

E2

E3

E4

E20

E21

E22

E23

Type output

DAC2

OSD_IN[13]/VBI_SCK

Analog video output


OSD_IN[14]/VBI_MOSI OSD video input/ miscellaneous digital


DVDD_IO Power

TEST2

GND

COMP2

DAC3


GND

Miscellaneous

analog 1

Analog video output

F1 OSD_IN[9]

F2

F3

F4

F20

F21

F22

F23

G1

G2

G3

G4

G7

G8

G9

G10

G11

G12

G13

G14

OSD_IN[10]

OSD_IN[11]

OSD_IN[12]

RSET2

PVDD3

GND

CEC1

OSD_IN[5]

OSD_IN[6]

OSD_IN[7]

OSD_IN[8]

GND

GND

GND

DVDD

GND

GND

DVDD

GND

OSD video input

OSD video input

OSD video input


Miscellaneous

analog 1

Power

GND

HDMI Tx1

OSD video input

OSD video input

OSD video input

OSD video input

GND

GND

GND

Power

GND

GND

Power

GND


Float this pin.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


Float this pin.

Ground.

Float this pin.

Float this pin.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.

Float this pin.

Encoder PLL Supply (1.8 V).

Ground.

Float this pin.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.

Ground.

Ground.

Ground.


Ground.

Ground.


Ground.


Pin Type

Analog output




N/A

Digital output

N/A

Analog input

Analog output





Analog input

N/A

N/A






N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

G22

G23

H1

H2

H3

H4

H7

H8

H9

H10

H11

H12

H13

H14

H15

H16

H17

H20

H21

H22

H23

J1

J2

J3

J4


G15

G16

G17

GND

GND

GND

G20 ELPF1

G21 ELPF2

J12

J13

J14

J15

J16

J7

J8

J9

J10

J11

Rev. B, August 2013

GND

GND

GND

GND

GND

DVDD

GND

GND

GND

GND

GND

AVDD3

OSD_IN[1]

OSD_IN[2]

OSD_IN[3]

OSD_IN[4]

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

TX1_2+

TX1_2−

DE

HS

OSD_HS

OSD_IN[0]


GND

GND

GND

GND

GND

Digital video sync

OSD video input

Power

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

OSD video input

GND

GND

GND

GND

Type

GND

GND

GND

Miscellaneous

analog 1

Miscellaneous

analog 1

GND

Power

OSD video input

OSD video input

OSD video input

GND

GND

GND

HDMI Tx1

HDMI Tx1

Digital video sync

Digital video sync


Ground.

Ground.

Ground.



Ground.



4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Float this pin.

Float this pin.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

407

Pin Type

N/A

N/A

N/A

N/A

N/A

N/A

N/A





N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Digital output

Digital output

Digital input

Digital input



N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

L3

L4

L12

L13

L14

L15

L16

L17

L7

L8

L9

L10

L11

L20

L21

L22

L23

M1

K2

K14

K15

K16

K17

K20

K21

K22

K23

L1

K3

K4

K7

K8

K9

K10

K11

K12

K13

L2


J17

J20

J21

DVDD

DDC1_SDA

GND

J22

J23

K1

TX1_1+

TX1_1−

VS

Rev. B, August 2013

P[34]

P[35]

GND

GND

GND

GND

GND

GND

DVDD

GND

GND

GND

GND

HPD_TX1

GND

TX1_C+

TX1_C−

P[28]

PCLK

DVDD_IO

DVDD_IO

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

DDC1_SCL

GND

TX1_0+

TX1_0−

P[32]

P[33]


Power

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

Type

Power

HDMI Tx1

GND

HDMI Tx1

HDMI Tx1

Digital video sync

Digital Video

Sync

Power

GND

HDMI Tx1

GND

HDMI Tx1

HDMI Tx1

Digital video input

Digital video input

Digital video input

Digital video input

Power

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

HDMI Tx1

GND

HDMI Tx1

HDMI Tx1

Digital video input



Float this pin.

Ground.

Float this pin.

Float this pin.


4.7kΩ resistor.


4.7kΩ resistor.



Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Float this pin.

Ground.

Float this pin.

Float this pin.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Float this pin.

Ground.

Float this pin.

Float this pin.


4.7kΩ resistor.

408

Pin Type

N/A

Digital output

N/A

Digital output

Digital output

Digital input

Digital input

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Digital output

N/A

Digital output

Digital output





N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Analog input (5V Tol)

N/A

Digital output

Digital output


P[27]

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

CEC2

PVDD5

HEAC_1+

HEAC_1−

P[24]

P[25]

P[26]

M22

M23

N1

N2

N3

N4

N12

N13

N14

N15

N16

N7

N8

N9

N10

N11

N17

N20

N21

M4

M7

M8

M9

M10

M11

M12

M13

M14

M15

M16

M17

M20

M21


M2 P[29]

M3 P[30]

P[31]

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

R_TX1

PVDD5

N22

N23

AVDD3

NC

Rev. B, August 2013


HDMI Tx1

HDMI Tx1

GND

GND

GND

GND

GND

GND

GND

GND

Digital video input

Digital video input

Digital video input

Digital video input

GND

GND

GND

HDMI Tx2

Power

Type

Digital video input

Digital video input

Digital video input

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

HDMI Tx1 1

Power

Power

No connect



4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Float this pin.

HDMI Tx PLL Power Supply (1.8 V). This pin is a voltage regulator output.

Connect a decoupling capacitor between this pin and ground.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Float this pin.




Connect this pin to ground.

409

Pin Type




N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Digital output

N/A







N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Bi-directional Analog IO (5V Tol)

N/A

N/A

Digital input

R2

R3

R4

R7

R8

R9

R10

R11

R12

R13

R14

R15

R16

R17

R20

R21

R22

R23

T1

T2

P3

P4

P12

P13

P14

P15

P16

P17

P7

P8

P9

P10

P11

P20

P21

P22

P23

R1


P1 P[20]

P2 P[21]

T3 GND

Rev. B, August 2013

P[17]

P[18]

P[19]

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

DDC2_SDA

GND

TX2_1+

TX2_1−

P[14]

P[15]

P[22]

P[23]

DVDD

GND

GND

GND

GND

GND

GND

GND

GND

GND

DVDD

DDC2_SCL

GND

TX2_2+

TX2_2−

P[16]

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

HDMI Tx2

GND

HDMI Tx2

HDMI Tx2

Digital video input

Digital video input

GND

Type

Digital video input

Digital video input

Digital video input

Digital video input

Power

GND

GND

GND

GND

GND

GND

GND

GND

GND

Power

HDMI Tx2

GND

HDMI Tx2

HDMI Tx2

Digital video input

Digital video input

Digital video input

Digital video input

GND



4.7kΩ resistor.

2


4.7kΩ resistor.

2


4.7kΩ resistor.

2


4.7kΩ resistor.

2


Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.


Float this pin.

Ground.

Float this pin.

Float this pin.


4.7kΩ resistor.

2


4.7kΩ resistor.

2


4.7kΩ resistor.

2


4.7kΩ resistor.

2

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Float this pin.

Ground.

Float this pin.

Float this pin.


4.7kΩ resistor.

2


4.7kΩ resistor.

2

Ground.

410

Pin Type

Digital input

Digital input

Digital input

Digital input

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Digital output

N/A

Digital output

Digital output

Digital input

Digital input

Digital input

Digital input

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Digital output

N/A

Digital output

Digital output

Digital input

Digital input

N/A


U2

U3

U4

U13

U14

U15

U16

U17

U20

U7

U8

U9

U10

U11

U12

U21

U22

U23

V1

V2

V3

V4

V20

V21

T15

T16

T17

T20

T21

T9

T10

T11

T12

T13

T14

T22

T23

U1


T4

T7

T8

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

HPD_TX2

GND

TX2_0+

TX2_0−

P[10]

P[11]

P[12]

P[13]

GND

GND

DVDD

GND

GND

DVDD

GND

GND

DVDD

GND

GND

R_TX2

GND

TX2_C+

TX2_C−

P[6]

P[7]

P[8]

P[9]

GND

PVDD6

Rev. B, August 2013

HDMI Tx2

HDMI Tx2

Digital video input

Digital video input

Digital video input

Digital video input

GND

GND

Power

GND

GND

Power

Type

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

HDMI Tx2

GND

GND

GND

Power

GND

GND

HDMI Tx2

GND

HDMI Tx2

HDMI Tx2

Digital video input

Digital video input

Digital video input

Digital video input

GND

Power


Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Ground.

Float this pin.

Ground.

Float this pin.

Float this pin.


4.7kΩ resistor.

2


4.7kΩ resistor.

2


4.7kΩ resistor.

2


4.7kΩ resistor.

2

Ground.

Ground.


Ground.

Ground.


Ground.

Ground.


Ground.

Ground.

Float this pin.

Ground.

Float this pin.

Float this pin.


4.7kΩ resistor.

2


4.7kΩ resistor.

2


4.7kΩ resistor.

2


4.7kΩ resistor.

2

Ground.


Connect a decoupling capacitor

411

Pin Type

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Analog input

N/A

Digital output

Digital output

Digital input

Digital input

Digital input

Digital input

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Digital output

N/A

Digital output

Digital output

Digital input

Digital input

Digital input

Digital input

N/A

N/A



V22

V23

W1

W2

W3

W4

W20

W21

HEAC_2+

HEAC_2−

P[2]

P[3]

P[4]

P[5]

TEST3

PVDD6

Y4

Y5

Y6

Y7

Y8

Y9

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

W22

W23

Y1

Y2

Y3

Y18

Y19

Y20

Y21

DVDD_DDR

DDR_DQ[14]

GND

DDR_DQ[6]

Y22

Y23

AA1

PVDD_DDR

GND

DDR_DQ[18]

Rev. B, August 2013

AVDD3

NC

P[0]

P[1]

DDR_DQS[2]

GND

DDR_DQ[23]

DVDD_DDR

DDR_DQS[3]

GND

DDR_A[11]

DVDD_DDR

DDR_A[4]

GND

DDR_CAS

DVDD_DDR

DDR_CK

GND

DDR_DQ[9]


Type

HDMI Tx2

HDMI Tx2

Digital video input

Digital video input

Digital video input

Digital video input


Power

Description if Unused between this pin and ground.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.

2


4.7kΩ resistor.

2


4.7kΩ resistor.

Float this pin.

2


4.7kΩ resistor.

2



Power

No connect


Float this pin.

Digital video input

Digital video input


4.7kΩ resistor.

2


4.7kΩ resistor.

2

DDR interface Connect this pin to ground through a

4.7kΩ resistor.

GND Ground.


4.7kΩ resistor.

Power DDR Interface Supply (1.8 V).


4.7kΩ resistor.

GND Ground.

DDR interface Float this pin.



GND Ground.




GND Ground.

DDR Interface Connect this pin to ground through a

4.7kΩ resistor.



4.7kΩ resistor.

GND Ground.


4.7kΩ resistor.

Power DDR Interface PLL Supply (1.8 V).

GND Ground.


412

Pin Type



Digital input

Digital input

Digital input

Digital input

Digital output

N/A

N/A

Digital output

Digital input

Digital input


N/A


N/A


N/A

Digital output

N/A

Digital output

N/A

Digital output

N/A

Digital output

N/A


N/A


N/A


N/A

N/A


AA2

AA3

AA4

AA5

AA6

AA7

AA8


GND

GND

DDR_DQS[2]

DDR_DQ[26]

DVDD_DDR

DDR_DQS[3]

NC/GND

AA18

AA19

AA20

AA21

AA22

AA23

AB1

AA9

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AB2

AB3

AB4

AB5

AB6

AB7

AB8 DDR_DQ[29]

AB9

AB10

AB11

AB12

AB13

AB14

AB15

DDR_A[12]

DDR_A[6]

DDR_A[3]

DDR_A[0]

DDR_BA[0]

DDR_RAS

DDR_CKE

Rev. B, August 2013

DDR_A[8]

DVDD_DDR

DDR_A[2]

GND

DDR_CS

DVDD_DDR

DDR_CK

GND

DDR_DQ[11]

DVDD_DDR

DDR_DM[1]

DDR_DM[0]

GND

GND

DDR_DQ[3]

DDR_DQ[21]

DDR_DQ[19]

DDR_DQ[17]

DDR_DM[2]

DDR_DQ[30]

DDR_DM[3]

DDR_DQ[31]


Type Description if Unused

4.7kΩ resistor.

Ground. GND

GND Ground.


4.7kΩ resistor.


4.7kΩ resistor.



4.7kΩ resistor.

No connect/GND

For New ADV8003 Designs, Float this pin. For Designs That Must Maintain

Consistency with ADV8003, this Pin can be Grounded.




GND Ground.




GND Ground.


4.7kΩ resistor.




GND

GND

Ground.

Ground.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.



4.7kΩ resistor.



4.7kΩ resistor.


4.7kΩ resistor.








413

Pin Type

N/A

N/A



N/A


N/A

Digital output

N/A

Digital output

N/A

Digital output

Digital output

N/A


N/A

Digital output

Digital output

N/A

N/A





Digital output


Digital output



Digital output

Digital output

Digital output

Digital output

Digital output

Digital output

Digital output

AC2

AC3

AC4

AC5

AC6

AC7

AC8

AC9

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AB18

AB19

AB20

AB21

AB22

AB23

AC1

AC18

AC19

AC20


AB16 DDR_DQ[12]

AB17 DDR_DQS[1]

AC21

AC22

DDR_DQ[2]

DDR_DQS[0]

AC23 DDR_DQ[1]

Rev. B, August 2013

DDR_DQ[8]

DDR_DQ[13]

DDR_DQ[0]

DDR_DQ[5]

DDR_DQS[0]

DDR_DQ[4]

DDR_DQ[16]

DDR_DQ[20]

DDR_DQ[22]

DDR_DQ[25]

DDR_DQ[28]

DDR_DQ[27]

DDR_DQ[24]

DDR_A[9]

DDR_A[5]

DDR_A[7]

DDR_A[1]

DDR_A[10]

DDR_BA[1]

DDR_BA[2]

DDR_WE

DDR_VREF

DDR_DQ[10]

DDR_DQS[1]

DDR_DQ[15]

DDR_DQ[7]


Type Description if Unused


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.









DDR interface Connect to DVDD_DDR.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.


4.7kΩ resistor.

414

Pin Type
















Digital output

Digital output

Digital output

Digital output

Digital output

Digital output

Digital output

Digital output

Digital input










2 Pull downs can be shared between 4 – 6 pins if desired



APPENDIX F

45

44

43

42

51

50

49

48

47

46

41

40

55

54

53

52

59

58

57

56

Sub

TTL

Input

PIXEL INPUT AND OUTPUT FORMATS

ADV8003

PIN NAME

OSD_IN.23 Z

OSD_IN.22 Z

OSD_IN.21 Z

OSD_IN.20 Z

OSD_IN.19 Z

OSD_IN.18 Z

OSD_IN.17 Z

OSD_IN.16 Z

OSD_IN.15 Z

OSD_IN.14 Z

OSD_IN.13 Z

OSD_IN.12 Z

OSD_IN.11 Z

OSD_IN.10 Z

OSD_IN.9

OSD_IN.8

OSD_IN.7

OSD_IN.6

OSD_IN.5

OSD_IN.4

Z

Z

Z

Z

Z

Z

8-

BIT

SDR

4:2:2

10-

BIT

SDR

4:2:2

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

12-

BIT

SDR

4:2:2

16-

BIT

SDR

4:2:2

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

20-

BIT

SDR

4:2:2

24-

BIT

SDR

4:2:2

24-

BIT

SDR

4:4:4

30-

BIT

SDR

4:4:4

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Table 95: RGB Input Formats

36-

BIT

SDR

4:4:4

8-BIT DDR

4:2:2

10-BIT DDR

4:2:2

Clock

Rise

Clock

Fall

Clock

Rise

Clock

Fall

RGB Colourspace

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

R3

R2

R1

R0

R7

R6

R5

R4

G7

G6

G5

G4

Z

Z

Z

Z

G3 G1.7

G2 G1.6

G1 G1.5

G0 G1.4

B7 G1.3

B6 G1.2

B5 G1.1

B4 G1.0

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

12-BIT DDR

4:2:2

Clock

Rise

Clock

Fall

24-

BIT

SDR

4:4:4

(a)

8-

BIT x2

SDR

4:4:4

8-

BIT x2

SDR

4:2:2

10-

BIT x2

SDR

4:2:2

12-

BIT x2

SDR

4:2:2

30-

BIT

SDR

4:4:4

21-

BIT

SDR

4:4:4

30-

BIT

SDR

4:4:4

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

R0

Z

B6

B5

R6

R5

R4

R3

R2

R1

B4

B3

G2

G1

G0

Z

G6

G5

G4

G3

G5

G4

G3

G2

R1

R0

G9

G8

G7

G6

G1

G0

R5

R4

R3

R2

R9

R8

R7

R6



12

11

10

9

17

16

15

14

13

25

24

23

22

21

20

19

18

31

30

29

28

27

26

39

38

37

36

35

34

33

32

Main

TTL

Input

8 P.8

Rev. B, August 2013

P.17

P.16

P.15

P.14

P.13

P.12

P.11

P.10

P.9

P.25

P.24

P.23

P.22

P.21

P.20

P.19

P.18

OSD_IN.3

OSD_IN.2

OSD_IN.1

OSD_IN.0

P.35

P.34

P.33

P.32

P.31

P.30

P.29

P.28

P.27

P.26

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

R1

R0

G9 G11

G8 G10

G7 G9

G6

G5

G4

G8

G7

G6

G3

G2

G1

G0

Z

Z G0

B9 B11

B8 B10

B7 B9

B6 B8

G5

G4

G3

G2

G1

R5

R4

R3

R2

R1

R0

Z

Z

Z

Z

Z

Z

Z

Z

R9 R11

R8 R10

R7 R9

R6 R8

R7

R6

R5

R4

R3

R2

Z

B7

B6

B5

B4

G1

G0

Z

Z

Z

Z

Z

G7

G6

G5

G4

G3

G2

R3

R2

R1

R0

Z

Z

Z

Z

Z

Z

R7

R6

R5

R4

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z Z

417

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

R1.1

R1.0

R7 G2.7

R6 G2.6

R5 G2.5

R4 G2.4

R3 G2.3

R2 G2.2

R1 G2.1

R0 G2.0

G7 B2.7

G6 B2.6

G5 B2.5

G4 B2.4

G3 B2.3

G2 B2.2

G1 B2.1

G0 B2.0

Z

Z

Z

Z

Z

Z

Z

Z

Z

B3 B1.7

B2 B1.6

B1 B1.5

B0 B1.4

Z B1.3

B1.2

B1.1

B1.0

R1.7

R1.6

R1.5

R1.4

R1.3

R1.2

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

G3

G2

G1

G0

Z

R0

Z

G6

G5

G4

Z

Z

R6

R5

R4

R3

R2

R1

Z

Z

Z

Z

Z

Z

Z

Z

Z

B2

B1

B0

Z

Z

G2

G1

G0

B9

B8

G7

G6

G5

G4

G3

R5

R4

R3

R2

R1

R0

G9

G8

Z

Z

R9

R8

R7

R6

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

B1

B0

Z

B9

B8

B7

B6

B5

B4

B3

B2

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z


3

2

1

7

6

5

4

0

ADV8

003

PIN

NAM

E

OSD_

DE

OSD_

VS

5

9

5

8

5

7

S ub

T

TL

In pu t

OSD_

CLK

OSD_

IN.23

OSD_

IN.22

OSD_

IN.21

5

6

OSD_

IN.20

Rev. B, August 2013

OSD_

CLK

Cb7/

Cr7,Y

7

Cb6/

Cr6,Y

6

Cb5/

Cr5,Y

5

Cb4/

Cr4,Y

4

P.7

P.6

P.5

P.4

P.3

P.2

P.1

P.0

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

B3

B2

B1

B0

Z

B5

B4

B3

B2

B1

B0

Z

Z

B7

B6

B5

B4

B3

B2

B1

B0

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

B7 R2.7

B6 R2.6

B5 R2.5

B4 R2.4

B3 R2.3

B2 R2.2

B1 R2.1

B0 R2.0

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

B7

B6

B5

B4

B3

B2

B1

B0

8-BIT

SDR

4:2:2

10-

BIT

SDR

4:2:2

OSD_

DE

OSD_

VS

OSD_

DE

OSD_

VS

12-BIT

SDR

4:2:2

OSD_D

E

OSD_V

S

OSD_

CLK

Cb9/

Cr9,Y

9

Cb8/

Cr8,Y

8

Cb7/

Cr7,Y

7

Cb6/

Cr6,Y

6

OSD_C

LK

Cb11/C r11,Y11 Y7

Cb10/C r10,Y10 Y6

Cb9/Cr

9,Y9

Cb8/Cr

8,Y8

Y5

Y4

16-

BIT

SDR

4:2:2

OSD

_DE

OSD

_VS

20-

BIT

SDR

4:2:2

OSD

_DE

OSD

_VS

OSD

_CLK

OSD

_CLK

24-

BIT

SDR

4:2:2

OSD

_DE

OSD

_VS

OSD

_CLK

Table 96: YCbCr Input Formats

24-

BIT

SDR

4:4:4

30-

BIT

SDR

4:4:4

36-

BIT

SDR

4:4:4

8-BIT DDR

4:2:2

10-BIT DDR

4:2:2

Z

Z

Z

Z

Z

Z

Z

Z

Z

Cloc k

Rise

Cloc k Fall

Cloc k

Rise

Cloc k Fall

OSD

_DE

OSD

_VS

OSD

_CL

K

YCbCr Colourspace

OSD

_DE

OSD

_VS

OSD

_CL

K

OSD

_DE

OSD

_VS

OSD

_CL

K

OSD

_DE

OSD

_VS

OSD

_CL

K

12-BIT DDR

4:2:2

Cloc k

Rise

OSD

_DE

OSD

_VS

OSD

_CL

K

Clock

Fall

OSD

_DE

OSD

_VS

OSD

_CLK

24-

BIT

SDR

4:4:4

(a)

8-

BIT x2

SDR

4:4:4

8-

BIT x2

SDR

4:2:2

10-

BIT x2

SDR

4:2:2

12-

BIT x2

SDR

4:2:2

30-

BIT

SDR

4:4:4

21-

BIT

SDR

4:4:4

OSD

_DE

OSD

_VS

OSD

_CL

K

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

OSD

_DE

OSD

_VS

OSD

_CL

K

Y9

Y8

Y7

Y6

Y11

Y10

Y9

Y8

418

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Y7

Y6

Y5

Y4

Cb7,

Cr7

Cb6,

Cr6

Cb5,

Cr5

Cb4,

Cr4

Y9

Y8

Y7

Y6

Cb9,

Cr9 Y11

Cb8,

Cr8 Y10

Cb7,

Cr7

Cb6,

Cr6

Y9

Y8

Cb11

,Cr11 Cr7

Cb10

,Cr10 Cr6

Cb9,

Cr9

Cb8,

Cr8

Cr5

Cr4

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Cr6

Cr5

Cr4

Cr3

B6

B5

B4

B3

B2

B1

B0

Z

30-

BIT

SDR

4:4:4

OSD

_DE

OSD

_VS

OSD

_CL

K

Cr9

Cr8

Cr7

Cr6

Z

Z

Z

Z

Z

Z

Z

Z


5

3

5

2

5

5

5

4

5

1

3

9

3

8

4

6

4

5

4

2

4

1

4

4

4

3

4

0

5

0

4

9

4

8

4

7

3

7

Rev. B, August 2013

OSD_

IN.15

OSD_

IN.14

OSD_

IN.13

OSD_

IN.12

OSD_

IN.11

OSD_

IN.10

OSD_

IN.9

OSD_

IN.8

OSD_

IN.7

OSD_

IN.6

OSD_

IN.5

OSD_

IN.4

OSD_

IN.3

OSD_

IN.2

OSD_

IN.1

OSD_

IN.19

OSD_

IN.18

OSD_

IN.17

OSD_

IN.16

Cb3/

Cr3,Y

3

Cb2/

Cr2,Y

2

Cb1/

Cr1,Y

1

Cb0/

Cr0,Y

0

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Cb5/

Cr5,Y

5

Cb4/

Cr4,Y

4

Cb3/

Cr3,Y

3

Cb2/

Cr2,Y

2

Cb1/

Cr1,Y

1

Cb0/

Cr0,Y

0

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Cb7/Cr

7,Y7

Cb6/Cr

6,Y6

Cb5/Cr

5,Y5

Cb4/Cr

4,Y4

Cb3/Cr

3,Y3

Cb2/Cr

2,Y2

Cb1/Cr

1,Y1

Cb0/Cr

0,Y0

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Y3

Y2

Y1

Y0

Z

Y5

Y4

Y3

Y2

Y1

Y7

Y6

Y5

Y4

Y3

Z

Z

Z

Cb7,

Cr7

Cb6,

Cr6

Cb5,

Cr5

Cb4,

Cr4

Cb3,

Cr3

Cb2,

Cr2

Cb1,

Cr1

Cb0,

Cr0

Z

Z

Z Z

Y2

Y1

Y0

Cb11

,Cr11

Cb10

,Cr10

Cb9,

Cr9

Cb8,

Cr8

Cb7,

Cr7

Cb6,

Cr6

Cb5,

Cr5

Cb4,

Cr4

Cb3,

Cr3

Cb2,

Cr2

Cb1,

Cr1

Y0

Z

Z

Cb9,

Cr9

Cb8,

Cr8

Cb7,

Cr7

Cb6,

Cr6

Cb5,

Cr5

Cb4,

Cr4

Cb3,

Cr3

Cb2,

Cr2

Cb1,

Cr1

Cb0,

Cr0

419

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Y3

Y2

Y1

Y0

Cb3,

Cr3

Cb2,

Cr2

Cb1,

Cr1

Cb0,

Cr0

Z Z

Y5

Y4

Y3

Y2

Y1

Cb1,

Cr1

Cb0,

Cr0

Z

Z

Cb5,

Cr5

Cb4,

Cr4

Cb3,

Cr3

Cb2,

Cr2

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Y0

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Y7

Y6

Y5

Y4

Y3

Cb7,

Cr7

Cb6,

Cr6

Cb5,

Cr5

Cb4,

Cr4

Cb3,

Cr3

Cb2,

Cr2

Cb1,

Cr1

Cb0,

Cr0

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Y2

Y1

Y0

Z

Z

Z

Z

Cr3

Cr2

Cr1

Cr0

Y7

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Cb7

Cb6

Cb5

Cb4

Cb3

Cb2

Cb1

Z

Z

Z

Z

Z

Z

Z

Z

Z

Y1.7

Y1.6

Z

Y1.7

Y1.6

Z

Y1.9

Y1.8

Z

Y1.1

1

Y1.1

0

Y1.5 Y1.5 Y1.7 Y1.9

Y1.4 Y1.4 Y1.6 Y1.8

Y1.3 Y1.3 Y1.5 Y1.7

Y1.2 Y1.2 Y1.4 Y1.6

Y1.1 Y1.1 Y1.3 Y1.5

Y1.0 Y1.0 Y1.2 Y1.4

Cb1.

7

Cb1.

6

Cb1.

5

Z

Z

Z

Y1.1

Y1.0

Z

Y1.3

Y1.2

Y1.1

Z

Z

Z

Z

Z

Cr2

Cr1

Cr0

Z

Y6

Cr5

Cr4

Cr3

Cr2

Cr1

Y1

Y0

Z

Cb6

Cb5

Cb4

Cb3

Y5

Y4

Y3

Y2

Cb2 Cb9

Cb1 Cb8

Cb0 Cb7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Cr0

Y9

Y8

Y7

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z


2

0

1

9

2

2

2

1

3

3

3

0

2

9

3

2

3

1

2

6

2

5

2

8

2

7

2

4

3

6

3

5

3

4

TL

In pu t

M ai n

T

2

3

OSD_

IN.0

P.35

P.34

P.33

P.32

P.31

P.30

P.29

P.28

P.27

P.26

P.25

P.24

P.23

1

8

P.22

P.21

P.20

P.19

P.18

Z

Z

Z

Z

Z

Z

Z

Z

Z

Cb7/

Cr7,Y

7

Cb6/

Cr6,Y

6

Cb5/

Cr5,Y

5

Cb4/

Cr4,Y

4

Cb3/

Cr3,Y

3

Cb2/

Cr2,Y

2

Z

Z

Z

Z

Rev. B, August 2013

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Cb9/

Cr9,Y

9

Cb8/

Cr8,Y

8

Cb7/

Cr7,Y

7

Cb6/

Cr6,Y

6

Cb5/

Cr5,Y

5

Cb4/

Cr4,Y

4

Z

Z

Z

Z

Z Z

Cb11/C r11,Y11 Y7

Cb10/C r10,Y10 Y6

Cb9/Cr

9,Y9 Y5

Cb8/Cr

8,Y8

Cb7/Cr

7,Y7

Cb6/Cr

6,Y6

Z

Z

Z

Z

Y4

Y3

Y2

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Y9

Y8

Y7

Y6

Y5

Cb0,

Cr0

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z Z Z

Cr7 Cr9 Cr11

Cr6 Cr8 Cr10

Cr5 Cr7 Cr9

Cr4 Cr6 Cr8

Cr3 Cr5 Cr7

Cr2 Cr4 Cr6

Cr1 Cr3 Cr5

Cr0 Cr2 Cr4

Z Cr1 Cr3

Z

Z

Z

Cr0

Z

Z

Cr2

Cr1

Cr0

Y11

Y10

Y9

Y8

Y7

Y7

Y6

Y5

Y4

Y3

Y7

Y6

Y5

Y4

Y9

Y8

Y7

Y6

Y5

Y4

Y3

Y2

Z

Z

Z

Z

Z

Cb7,

Cr7

Cb6,

Cr6

Cb5,

Cr5

Cb4,

Cr4

Cb3,

Cr3

Z

Z

Z

Z

Z

Z

Z

Z

Cb2,

Cr2

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Y9 Y11 Y7

Y8 Y10 Y6

Y4 Y6

420

Y2

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Y9

Y8

Y7

Y6

Y5

Cb7,

Cr7

Cb6,

Cr6

Cb5,

Cr5

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Cb9,

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Cr9 Y11

Cb8,

Cr8 Y10

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Cb11

,Cr11 Cr7

Cb10

Cb0

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

,Cr10 Cr6

Cb1.

4

Cb1.

3

Cb1.

2

Cb1.

1

Cb1.

0

Z

Cb.7

Cb.6

Cb.5

Cb.4

Z

Cb.9

Cb.8

Cb.7

Cb.6

Y1.0

Cb.1

1

Cb.1

0

Cb.9

Cb.8

Cr1.7 Cb.3 Cb.5 Cb.7




Cr1.3

Z

Cb.1 Cb.3

Cr1.2 Cb.0 Cb.2

Z

Cr1.1 Cb.1

Z Z

Cr1.0 Cb.0

Z Z

Y2.7 Y2.7 Y2.9

Y2.1

1

Y2.6 Y2.6 Y2.8

Y2.1

0

Y9

Y8

Y7

Cb9,

Cr9

Cb8,

Cr8

Cb7,

Cr7

Cr5

Cr4

Cr3

Y2.5 Y2.5 Y2.7 Y2.9

Y2.4

Y2.3

Y2.4

Y2.3

Y2.6

Y2.5

Y2.8

Y2.7

Z

Z

Z

Z

Z

Z

Z

Cr9

Cr8

Cr7

Cr6

Cr5

Cr4

Cr3 Cr6

Cr2 Cr5

Cr1 Cr4

Cr0 Cr3

Y9

Z

Z

Z

Z

Cr2

Z

Z

Z

Z

Z

Z

Z

Z

Z

Cb4,

Cr4 Y6

Cb6,

Cr6 Cr2

Y2.2 Y2.2 Y2.4 Y2.6

Y8 Cr1

Cb6

Cb5

Cb4

Cb3

Z

Z

Z

Z

Z

Cb2

Cb1

Cb0

Z

Z

Z

Z

Z

Z

Z Y4


7

6

9

8

1

5

1

4

1

3

1

2

1

1

1

0

3

2

5

4

1

1

7

1

6

0

P.17

P.16

Cb1/

Cr1,Y

1

Cb0/

Cr0,Y

0

P.15

P.14

P.13

P.12

P.7

P.6

P.5

P.4

P.11

P.10

P.9

P.8

P.3

P.2

P.1

P.0

VID_

DE

VID_

HS

Z

Z

VID_

DE

VID_

HS

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

VID_

Rev. B, August 2013

VID_

Cb3/

Cr3,Y

3

Cb2/

Cr2,Y

2

Cb1/

Cr1,Y

1

Cb0/

Cr0,Y

0

Cb5/Cr

5,Y5

Cb4/Cr

4,Y4

Cb3/Cr

3,Y3

Y1

Y0

Z

Y3

Y2

Y1

Y5

Y4

Y3

Y1

Y0

Z

Y3

Y2

Y1

Y5

Y4

Y3

Y1

Y0

Z

Cb1,

Cr1

Cb0,

Cr0

Z

Y3

Y2

Y1

Cb3,

Cr3

Cb2,

Cr2

Cb1,

Cr1

Y5

Y4

Y3

Cb5,

Cr5

Cb4,

Cr4

Cb3,

Cr3

Cr1

Cr0

Y7

Y2.1 Y2.1 Y2.3 Y2.5

Y2.0 Y2.0 Y2.2 Y2.4

Cb2.

7

Z

Y2.1 Y2.3

Y7

Y6

Y5

Cr0

Z

Y6

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Cb2/Cr

2,Y2

Cb1/Cr

1,Y1

Cb0/Cr

0,Y0

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z Z

VID_

DE VID_DE

VID_

HS VID_HS

Z

Z

Z

Cb3,

Cr3

Cb2,

Cr2

Cb1,

Cr1

Cb0,

Cr0

Cb7,

Cr7

Cb6,

Cr6

Cb5,

Cr5

Cb4,

Cr4

Z

Z

Z

Z

VID_

DE

VID_

HS

Y0

Z

Z

Cb5,

Cr5

Cb4,

Cr4

Cb3,

Cr3

Cb2,

Cr2

Cb1,

Cr1

Cb9,

Cr9

Cb8,

Cr8

Cb7,

Cr7

Cb6,

Cr6

Cb0,

Cr0

Z

Z

VID_

DE

VID_

HS

Y2

Y1

Z

Z

Y0

Z

Y2

Y1

Cb2,

Cr2

Cb1,

Cr1

Cb0,

Cr0

VID_

DE

VID_

HS

Y0 Z Z Y0

Cb11

,Cr11 Cb7 Cb9

Cb10

,Cr10 Cb6 Cb8

Cb1

1

Cb1

0

Cb9,

Cr9 Cb5 Cb7 Cb9

Cb8,

Cr8 Cb4 Cb6 Cb8

Cb7,

Cr7 Cb3 Cb5 Cb7

Cb6,

Cr6 Cb2 Cb4 Cb6

Cb5,

Cr5 Cb1 Cb3 Cb5

Cb4,

Cr4 Cb0 Cb2 Cb4

Cb3,

Cr3 Z Cb1 Cb3

Z

Z

Z

VID_

DE

VID_

HS

Cb0

Z

Z

VID_

DE

VID_

HS

Cb2

Cb1

Cb0

VID_

DE

VID_

HS

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

VID_

DE

VID_

HS

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

VID_

DE

VID_

HS

Y0

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

VID_

DE

VID_

HS

Cb0,

Cr0

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

VID_

DE

VID_

HS

Y2

Y1

Y0

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

VID_

DE

VID_

HS

Cb2,

Cr2

Cb1,

Cr1

Cb0,

Cr0

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

VID_

DE

VID_

HS

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Cb7

Cb6

Cb5

Cb4

Cb3

Cb2

Cb1

Cb0

VID_

DE

VID_

HS

Cb2.

6

Cr2.

2

Cr2.

1

Cr2.

0

VID_

DE

VID_

HS

Cb2.

5

Cb2.

4

Cr2.

7

Cr2.

6

Cr2.

5

Cr2.

4

Cr2.

3

Cb2.

3

Cb2.

2

Cb2.

1

Cb2.

0

Z

Z

Z

Cr.7 Cr.9

Cr.6 Cr.8

Cr.5 Cr.7 Cr.9

Cr.4 Cr.6 Cr.8

Cr.3 Cr.5 Cr.7

Cr.2 Cr.4 Cr.6

Cr.1 Cr.3 Cr.5

Cr.0 Cr.2 Cr.4

Z

Z

Z

Z

VID_

DE

VID_

HS

Y2.0 Y2.2

Z

Z

Y2.1

Y2.0

Cr.1

1

Cr.1

0

Cr.1 Cr.3

Cr.0 Cr.2

Z

Z

VID_

DE

VID_

HS

Cr.1

Cr.0

VID_

DE

VID_

HS

Y4

Y3

Y2

Y1

Y0

Cb9

Cb8

Y5

Cb7 Cb6

Cb6 Cb5

Cb5 Cb4

Cb4 Cb3

Cb3 Cb2

Cb2 Cb1

Cb1 Cb0

Cb0

VID_

DE

VID_

HS

Y4

Y3

Y2

Y1

Y0

Z

Z

VID_

DE

VID_

HS

VID_ VID_VS VID_ VID_ VID_ VID_ VID_ VID_ VID_ VID_ VID_ VID_ VID_ VID_ VID_ VID_ VID_ VID_ VID_ VID_ VID_

421

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z


VS

VID_

CLK

VS

VID_

CLK

VS

VID_

CLK

VID_CL

K

VS

VID_

CLK

VS

VID_

CLK

VS

VID_

CLK

VS

VID_

CLK

VS

VID_

CLK

VS

VID_

CLK

VS

VID_

CLK

VS

VID_

CLK

VS

VID_

CLK

VS

VID_

CLK

VS

VID_

CLK

VS

VID_

CLK

VS

VID_

CLK

VS

VID_

CLK

VS

VID_

CLK

VS

VID_

CLK

VS

VID_

CLK

VS

VID_

CLK

VS

VID_

CLK Z

Alpha Format

OSD_DE

OSD_VS

OSD_CLK

OSD_IN.23

OSD_IN.22

OSD_IN.21

OSD_IN.20

OSD_IN.19

OSD_IN.18

OSD_IN.17

OSD_IN.16

OSD_IN.15

OSD_IN.14

OSD_IN.13

OSD_IN.12

OSD_IN.11

OSD_IN.10

OSD_IN.9

OSD_IN.8

OSD_IN.7

OSD_IN.6

OSD_IN.5

Rev. B, August 2013

Z

Z

Z

0x0

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

0x2

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

0x1

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

422

Z

Z

Z

0x4

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

0x3

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Table 97: Alpha Blending Input Formats

0x5 0x6 0x7 0x8

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

0x9

Z

Z

Z

Z

Z

Z

Z

Z

A6

Z

Z

Z

Z

Z

Z

Z

Z

A7

Z

Z

Z

Z

0xB

A6

A5

A4

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

A7

Z

Z

Z

0xA

Z

A7

A6

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

0xD

A6

A5

A4

A3

A2

Z

Z

A1

A0

Z

Z

Z

Z

Z

Z

Z

Z

Z

A7

Z

Z

Z

0xC

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

A7

A6

A5

A4

A3

A2

A1

A0

Z

Z

Z

Z

0xE

Z

Z

Z

Z

Z

Z

Z

A7

A6

A5

Z

Z

Z

Z

Z

Z

Z

Z

Z

P.28

P.27

P.26

P.25

P.24

P.23

P.22

P.21

P.20

P.19

P.18

P.17

P.16

P.35

P.34

P.33

P.32

P.31

P.30

P.29

P.15

P.14

P.13

P.12

P.11

P.10

P.9

P.8

OSD_IN.4

OSD_IN.3

OSD_IN.2

OSD_IN.1

OSD_IN.0

Rev. B, August 2013

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

A3

A2

A1

A0

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

A0

Z

Z

A3

A2

A1

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

423

Z

Z

A4

Z

Z

A7

A6

A5

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

A0

Z

Z

A3

A2

A1

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

A7

A6

A5

A4

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

A7

A6

A5

A4

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

A4

Z

Z

A7

A6

A5

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

A3

A2

A1

A0

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

A7

A6

A5

Z

Z

Z

Z

A4

A3

A2

A1

A0

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

A7

A6

A5

A4

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

A0

Z

Z

Z

Z

Z

Z

A7

A6

A5

A4

A3

A2

A1

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

A5

A4

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

A5

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

A3

A2

A1

A0


Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

A4

A3

A2

A1

A0

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

P.3

P.2

P.1

P.0

P.7

P.6

P.5

P.4

VID_DE

VID_HS

VID_VS

VID_CLK

A7

A6

A5

A4

Z

Z

Z

Z

Z

Z

Z

Z

A7

A6

A5

A4

Z

Z

Z

Z

Z

Z

Z

Z

A3

A2

A1

A0

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

A3

A2

A1

A0

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

A3

A2

A1

A0

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z


Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z


Rev. B, August 2013

ADV8003 PIN

NAME

OSD_DE

OSD_VS

OSD_HS

OSD_CLK

OSD_IN.23

OSD_IN.23

OSD_IN.21

OSD_IN.20

OSD_IN.19

OSD_IN.18

OSD_IN.17

OSD_IN.16

OSD_IN.15

OSD_IN.14

OSD_IN.13

OSD_IN.12

OSD_IN.11

OSD_IN.10

OSD_IN.9

OSD_IN.8

OSD_IN.7

OSD_IN.6

OSD_IN.5

OSD_IN.4

OSD_IN.3

OSD_IN.2

OSD_IN.1

OSD_IN.0

P.35

425

Table 98: RGB TTL Output Formats

24-BIT SDR 4:4:4 30-BIT SDR 4:4:4 36-BIT SDR 4:4:4

DE_OUT

G4

G3

G2

G1

G0

R0

G7

G6

G5

VS_OUT

HS_OUT

CLK_OUT

R7

R6

R5

R4

R3

R2

R1

B3

B2

B1

B0

B7

B6

B5

B4

Z

DE_OUT

R4

R3

R2

R1

R0

G11

G10

G9

G8

VS_OUT

HS_OUT

CLK_OUT

R11

R10

R9

R8

R7

R6

R5

G3

G2

G1

G0

G7

G6

G5

G4

B11

DE_OUT

G8

G7

G6

G5

G4

R2

R1

R0

G9

VS_OUT

HS_OUT

CLK_OUT

R9

R8

R7

R6

R5

R4

R3

B9

B8

B7

B6

G3

G2

G1

G0

B5


Rev. B, August 2013

P.11

P.10

P.9

P.8

P.7

P.6

P.5

P.4

P.20

P.19

P.18

P.17

P.16

P.15

P.14

P.13

P.12

P.27

P.26

P.25

P.24

P.23

P.22

P.21

P.34

P.33

P.32

P.31

P.30

P.29

P.28

P.3

426

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

B3

B2

B1

B0

Z

Z

Z

B10

B9

B8

B7

B6

B5

B4

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

B4

B3

B2

B1

B0

Z

Z


P.2

P.1

P.0

Z

Z

Z

Z

Z

Z

Z

Z

Z



Rev. B, August 2013

ADV8003 PIN

NAME

OSD_DE

OSD_VS

OSD_HS

OSD_CLK

OSD_IN.23

OSD_IN.22

OSD_IN.21

OSD_IN.20

OSD_IN.19

OSD_IN.18

OSD_IN.17

OSD_IN.16

OSD_IN.15

OSD_IN.14

OSD_IN.13

OSD_IN.12

OSD_IN.11

OSD_IN.10

OSD_IN.9

OSD_IN.8

OSD_IN.7

OSD_IN.6

OSD_IN.5

OSD_IN.4

OSD_IN.3

OSD_IN.2

OSD_IN.1

OSD_IN.0

DE_OUT

VS_OUT

HS_OUT

CLK_OUT

Z

Cb7,Cr7

Cb6,Cr6

Cb5,Cr5

Cb4,Cr4

Cb3,Cr3

Cb2,Cr2

Cb1,Cr1

Cb0,Cr0

Z

Z

Z

Z

Y3

Y2

Y1

Y0

Z

Z

Z

Y7

Y6

Y5

Y4

428

Table 99: YCrCb TTL Output Formats

16-BIT SDR 4:2:2 20-BIT SDR 4:2:2 24-BIT SDR 4:2:2 24-BIT SDR 4:4:4 30-BIT SDR 4:4:4 36-BIT SDR 4:4:4

DE_OUT

VS_OUT

HS_OUT

CLK_OUT

Z

Cb9,Cr9

Cb8,Cr8

Cb7,Cr7

Cb6,Cr6

Cb5,Cr5

Cb4,Cr4

Cb3,Cr3

Cb2,Cr2

Cb1,Cr1

Cb0,Cr0

Z

Z

Y5

Y4

Y3

Y2

Y9

Y8

Y7

Y6

Y1

Y0

Z

YCbCr Colorspace

DE_OUT DE_OUT

VS_OUT

HS_OUT

CLK_OUT

VS_OUT

HS_OUT

CLK_OUT

Y0

Cb11,Cr11

Cb10,Cr10

Cb9,Cr9

Cb8,Cr8

Cb7,Cr7

Cb6,Cr6

Cb5,Cr5

Cb4,Cr4

Cb3,Cr3

Cb2,Cr2

Cb1,Cr1

Cb0,Cr0

Y11

Y10

Y9

Y8

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Cb7

Cb6

Cb5

Cb4

Cb3

Cb2

Cb1

Cb0

Y4

Y3

Y2

Y1

Cr7

Cr6

Cr5

Cr4

Cr3

Cr2

Cr1

Cr0

Y7

Y6

Y5

DE_OUT

VS_OUT

HS_OUT

CLK_OUT

Cb9

Cb8

Cb7

Cb6

Y4

Y3

Y2

Y1

Y0

Y8

Y7

Y6

Y5

Cr9

Cr8

Cr7

Cr6

Cr5

Cr4

Cr3

Cr2

Cr1

Cr0

Y9

DE_OUT

VS_OUT

HS_OUT

CLK_OUT

Cr0

Y11

Y10

Y9

Y8

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Cr11

Cr10

Cr9

Cr8

Cr7

Cr6

Cr5

Cr4

Cr3

Cr2

Cr1


Rev. B, August 2013

P.12

P.11

P.10

P.9

P.8

P.7

P.6

P.5

P.4

P.3

P.19

P.18

P.17

P.16

P.15

P.14

P.13

P.27

P.26

P.25

P.24

P.23

P.22

P.21

P.20

P.35

P.34

P.33

P.32

P.31

P.30

P.29

P.28

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

429

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Cb3

Cb2

Cb1

Cb0

Cb11

Cb10

Cb9

Cb8

Cb7

Cb6

Cb5

Cb4

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Cb5

Cb4

Cb3

Cb2

Cb1

Cb0

Z

Z


P.2

P.1

P.0

VID_DE

VID_HS

VID_VS

VID_CLK

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z

Z




LIST OF FIGURES

Figure 1: Field Description Format ................................................................................................................................................................................ 13

Figure 2: ADV8003 Digital Video Interface .................................................................................................................................................................. 17

Figure 3: ADV8003 Video Processing ............................................................................................................................................................................ 17

Figure 4: ADV8003 Bitmap OSD .................................................................................................................................................................................... 18

Figure 5: External DDR2 Memory Interface ................................................................................................................................................................. 19

Figure 6: ADV8003 Block Diagram ............................................................................................................................................................................... 21

Figure 7. ADV8003KBCZ-8 and ADV8003KBCZ-7 Pin Configuration .................................................................................................................. 22

Figure 8. ADV8003KBCZ-8B and ADV8003KBCZ-7B Pin Configuration ............................................................................................................. 34

Figure 9. ADV8003KBCZ-8C and ADV8003KBCZ-7C Pin Configuration ............................................................................................................ 45

Figure 10. ADV8003KBCZ-7T Pin Configuration ...................................................................................................................................................... 56

Figure 11: Register Map Architecture ............................................................................................................................................................................ 67

Figure 12: Bus Data Transfer ........................................................................................................................................................................................... 68

Figure 13: Read and Write Sequence ............................................................................................................................................................................. 68

Figure 14: ADV8003 Simplified Block Diagram .......................................................................................................................................................... 69

Figure 15: ADV8003 Mode 1 Configuration ................................................................................................................................................................ 72









Figure 24: ADV8003 Mode 10 Configuration .............................................................................................................................................................. 81





Figure 29: ADV8003 Digital Core Muxing ................................................................................................................................................................... 86

Figure 30: Video TTL Input Channel ............................................................................................................................................................................. 89

Figure 31: EXOSD TTL Input Channel ......................................................................................................................................................................... 90

Figure 32: RX Input Channel .......................................................................................................................................................................................... 90

Figure 33: TTL Output Block Diagram ......................................................................................................................................................................... 91

Figure 34: DDR Mode, Luma and Chroma Swap......................................................................................................................................................... 94

Figure 35: Contrast Processing ....................................................................................................................................................................................... 98

Figure 36: Brightness Processing .................................................................................................................................................................................... 99

Figure 37: Saturation Processing .................................................................................................................................................................................. 100

Figure 38: DDR Mode, Luma and Chroma Swap....................................................................................................................................................... 101

Figure 39: Updither Operation ..................................................................................................................................................................................... 106

Figure 40: Configuring Input Port Clock .................................................................................................................................................................... 107

Figure 41: PVSP/SVSP Output Clock Configure........................................................................................................................................................ 110

Figure 42: DDR2 PLL Architecture .............................................................................................................................................................................. 115

Figure 43: DDR2 Loopback Test Architecture ............................................................................................................................................................ 117

Figure 44: VBI Data Extraction Block Diagram ......................................................................................................................................................... 120

Figure 45: ADV8003 Image Processing Colorimetry Breakdown ........................................................................................................................... 125

Figure 46: 720(1440) x 240p @ 59.94/60Hz, CEA Formats 8 and 9 ......................................................................................................................... 130

Figure 47: Primary Input Channel CSC ...................................................................................................................................................................... 131

Figure 48: Secondary Input Channel CSC .................................................................................................................................................................. 134

Figure 49: RX Input Channel CSC ............................................................................................................................................................................... 137

Figure 50: HDMI TX CSC ............................................................................................................................................................................................. 140

Figure 51: ADV8003 PVSP ............................................................................................................................................................................................ 144



Figure 52: 2:3 Frame Rate Conversion ......................................................................................................................................................................... 155

Figure 53: PVSP Video Input Module .......................................................................................................................................................................... 156

Figure 54: VIM Crop Dimensions ................................................................................................................................................................................ 156

Figure 55: PVSP Video Output Module ....................................................................................................................................................................... 160

Figure 56: VOM Crop Dimensions .............................................................................................................................................................................. 162

Figure 57: VOM Scaler Dimensions ............................................................................................................................................................................. 172

Figure 58: Panorama Scaling Feature ........................................................................................................................................................................... 172

Figure 59: VOM Output Dimensions .......................................................................................................................................................................... 176

Figure 60: ADV8003 SVSP ............................................................................................................................................................................................ 180

Figure 61: SVSP Video Input Module .......................................................................................................................................................................... 189

Figure 62: VIM Crop Dimensions ................................................................................................................................................................................ 190

Figure 63: VIM Scaler Dimensions .............................................................................................................................................................................. 192

Figure 64: SVSP Video Output Module (VOM) ......................................................................................................................................................... 194

Figure 65: VOM Crop Dimensions .............................................................................................................................................................................. 196

Figure 66: VOM Output Dimensions .......................................................................................................................................................................... 200

Figure 67: Bootup Protocol Flowchart ......................................................................................................................................................................... 203

Figure 68: Reboot Protocol Flowchart ......................................................................................................................................................................... 204

Figure 69: Gentle Reboot Protocol Flowchart ............................................................................................................................................................ 205

Figure 70: VOM Set Protocol Flowchart ..................................................................................................................................................................... 206

Figure 71: Free Access Protocol .................................................................................................................................................................................... 206

Figure 72: Typical Application Diagram ...................................................................................................................................................................... 209

Figure 73: Bitmap OSD Top Level Diagram................................................................................................................................................................ 210

Figure 74: OSD Scaler and Blending Top Level Diagram ......................................................................................................................................... 211

Figure 75: Definition of OSD Region ........................................................................................................................................................................... 212

Figure 76: OSD Menu Bar Component ....................................................................................................................................................................... 213

Figure 77: Data Loaded from SPI Flash Through ADV8003 SPI Master Interface ............................................................................................... 218

Figure 78: MCU as SPI Master Sending OSD Data Through ADV8003 SPI Slave Interface ............................................................................... 219

Figure 79: SPI Loopback Enabled so MCU Can Program SPI Flash ....................................................................................................................... 220

Figure 80: SPI Slave Interface Timing and Data Format ........................................................................................................................................... 223

Figure 81: SPI Master Interface Timing and Data Format ........................................................................................................................................ 225

Figure 82: Functional Block Diagram of ADV8003 Serial Video Rx ....................................................................................................................... 227

Figure 83: HDMI Video FIFO....................................................................................................................................................................................... 231

Figure 84: Horizontal Timing Parameters ................................................................................................................................................................... 234

Figure 85: Vertical Parameters for Field 0 ................................................................................................................................................................... 234

Figure 86: Functional Block Diagram of HDMI Tx Core ......................................................................................................................................... 245

Figure 87: Format of Video Data Input into HDMI Tx Core ................................................................................................................................... 254

Figure 88: I 2 C Write Timing if GMP Data ................................................................................................................................................................... 259

Figure 89: IEC60958 Sub Stream .................................................................................................................................................................................. 268

Figure 90: AES3 Stream Format Input to ADV8003 .................................................................................................................................................. 269

Figure 91: Timing of Standard I2S Stream Input to ADV8003 ................................................................................................................................ 269

Figure 92: Timing for Right-Justified I2S Stream Input to ADV8003 ..................................................................................................................... 269

Figure 93: Timing for Left-Justified I2S Stream Input to ADV8003 ........................................................................................................................ 269

Figure 94: Timing for I2S Stream in 32-bit Mode ...................................................................................................................................................... 270

Figure 95: Timing for I2S Stream in Left or Right-Justified and 32-bit Modes ..................................................................................................... 270

Figure 96: Audio Clock Regeneration .......................................................................................................................................................................... 273

Figure 97: Definition of Channel Status Bits 20 to 23................................................................................................................................................ 279

Figure 98: Reading Sink EDID Through ADV8003................................................................................................................................................... 284

Figure 99: HDCP Software Implementation ............................................................................................................................................................... 289

Figure 100: CEC Module Block Diagram .................................................................................................................................................................... 293

Figure 101: CEC Module Initialization ........................................................................................................................................................................ 302

Figure 102: Using CEC Module as Initiator ................................................................................................................................................................ 303

Figure 103: Using CEC Module as Follower ............................................................................................................................................................... 304

Figure 104: ADV8003 Encoder Block Diagram ......................................................................................................................................................... 307



Figure 105: Simplified View of ADV8003 Encoder Block......................................................................................................................................... 308

Figure 106: SD Luma SSAF Filter, Programmable Responses .................................................................................................................................. 316

Figure 107: SD Luma SSAF Filter, Programmable Gains .......................................................................................................................................... 317

Figure 108: SD Luma SSAF Filter, Programmable Attenuation ............................................................................................................................... 317

Figure 109: PrPb SSAF Filter ......................................................................................................................................................................................... 318

Figure 110: ED/HD Sinc Compensation Filter Enabled ............................................................................................................................................ 319

Figure 111: ED/HD Sinc Compensation Filter Disabled ........................................................................................................................................... 319

Figure 112: Examples of Brightness Control Values .................................................................................................................................................. 326

Figure 113: Programmable DAC Gain – Positive and Negative Gain ..................................................................................................................... 327

Figure 114: Signal Input (Ramp) and Signal Output for Gamma 0.5 ...................................................................................................................... 330

Figure 115: Signal Input (Ramp) and Selectable Output Curves ............................................................................................................................. 330

Figure 116: ED/HD Sharpness and Adaptive Filter Control Block .......................................................................................................................... 333

Figure 117: ED/ HD Sharpness Filter Control with Different Gain Settings for ED/HD Sharpness Filter Gain Values .................................. 337

Figure 118: Input Signal to ED/HD Adaptive Filter ................................................................................................................................................... 338

Figure 119: Output Signal from ED/HD Adaptive Filter (Mode A) ........................................................................................................................ 338

Figure 120: Output Signal from ED/HD Adaptive Filter (Mode B) ........................................................................................................................ 338

Figure 121: SD DNR Block Diagram ........................................................................................................................................................................... 339

Figure 122: SD DNR Offset Control ............................................................................................................................................................................ 340

Figure 123: SD DNR Border Area ................................................................................................................................................................................ 341

Figure 124: SD DNR Input Filter Select ....................................................................................................................................................................... 342

Figure 125: Example of Active Video Edge Functionality ......................................................................................................................................... 343

Figure 126: Example of Video Output with SD Active Video Edge Control Disabled .......................................................................................... 344

Figure 127: Example of Video Output with SD Active Video Edge Control Enabled ........................................................................................... 344

Figure 128: Example of Output Filter for SD, 16× Oversampling ............................................................................................................................ 346

Figure 129: Example of Output Filter for ED, 8× Oversampling ............................................................................................................................. 347

Figure 130: Example of Output Filter for HD, 4× Oversampling ............................................................................................................................ 347

Figure 131: Output Filter Plot for SD, 16× Oversampling ........................................................................................................................................ 347

Figure 132: Output Filter Plot for ED, 8× Oversampling .......................................................................................................................................... 347

Figure 133: Output Filter Plot for HD, 4× Oversampling ......................................................................................................................................... 348

Figure 134: Level and Edge-sensitive Raw, Status and Interrupt Generation ......................................................................................................... 351

Figure 135: AVI_INFO_RAW and AVI_INFO_ST Timing ...................................................................................................................................... 352

Figure 136: NEW_AVI_INFO_RAW and NEW_AVI_INFO_ST Timing ............................................................................................................. 352

Figure 137: Recommended Power Supply Decoupling ............................................................................................................................................. 359

Figure 138: Crystal Circuit ............................................................................................................................................................................................ 360

Figure 139: Power Supply Design ................................................................................................................................................................................. 362

Figure 140: Power Supply Sequence ............................................................................................................................................................................. 362

Figure 141: ADV8003 Schematic – Page 1 .................................................................................................................................................................. 363









Figure 150: ADV8003 Schematic – Page 10 ................................................................................................................................................................ 371
























Figure 172: ADV8003 Layout – Page 1 ........................................................................................................................................................................ 394










LIST OF TABLES

Table 1: Available Features Within ADV8003 Family of ICs ...................................................................................................................................... 16

Table 6: ADV8003 I 2 C Address and Register Address Range for Different HW Blocks ......................................................................................... 67

Table 7: ADV8003 Modes of Operation ........................................................................................................................................................................ 70

Table 8: Example Values for dpll_clock_period.......................................................................................................................................................... 110

Table 9: Frame Tracking ................................................................................................................................................................................................. 113

Table 10: Indication of ADV8003 Capabilities with One DDR2 Memory.............................................................................................................. 115

Table 11: Indication of ADV8003 Capabilities with Two DDR2 Memories ........................................................................................................... 116

Table 12: Indication of ADV8003 Capabilities with Different Memory Sizes ........................................................................................................ 116

Table 13: Output Mode Outline .................................................................................................................................................................................... 120

Table 22: PVSP Supported Input Video Timing and VID ......................................................................................................................................... 146

Table 23: PVSP Supported Output Video Timing and VID ...................................................................................................................................... 147

Table 24: Frame Latency in Normal Mode .................................................................................................................................................................. 151

Table 25: Frame Latency in Low Latency Mode ......................................................................................................................................................... 154

Table 26: Bytes per Pixel ................................................................................................................................................................................................ 160

Table 27: Corresponding Bit for Each Cadence Type ................................................................................................................................................ 165

Table 28: Corresponding Value for Block Noise Reduction Level ........................................................................................................................... 168

Table 29: Output Port Configuration Settings for Example Output Resolutions .................................................................................................. 176

Table 30: VID Set to PtoI ............................................................................................................................................................................................... 180

Table 31: SVSP Supported Input Video Timing and VID ......................................................................................................................................... 182

Table 32: SVSP Supported Output Video Timing and VID ...................................................................................................................................... 183

Table 33: Frame Latency in Normal Mode .................................................................................................................................................................. 187

Table 34: Output Port Configuration Settings for Example Output Formats ........................................................................................................ 199

Table 35: VID for PtoI .................................................................................................................................................................................................... 202

Table 36: Output Port Configuration Settings for Example Output Formats ........................................................................................................ 209

Table 37: Regions Used for OSD Components ........................................................................................................................................................... 212

Table 38: AVI InfoFrame Registers ............................................................................................................................................................................... 236

Table 39: SPD InfoFrame Registers .............................................................................................................................................................................. 237

Table 40: MPEG InfoFrame Registers .......................................................................................................................................................................... 238

Table 41: VS InfoFrame Registers ................................................................................................................................................................................. 238

Table 42: ISRC1 Packet Registers .................................................................................................................................................................................. 239

Table 43: ISRC2 Packet Registers .................................................................................................................................................................................. 240

Table 44: Gamut Metadata Packet Registers ............................................................................................................................................................... 241

Table 45: HDMI Transmitter Memory Addresses ...................................................................................................................................................... 245

Table 46: HDMI Tx Main Map Reset Strategy............................................................................................................................................................ 247

Table 47: HDMI Tx CEC Map Reset Strategy ............................................................................................................................................................. 247

Table 48: HDMI Tx Packet Map Reset Strategy ......................................................................................................................................................... 248

Table 49: SPD InfoFrame Configuration Register ...................................................................................................................................................... 249

Table 50: Spare Packet 0 Configuration Register........................................................................................................................................................ 250

Table 51: Spare Packet 1 Configuration Register........................................................................................................................................................ 251

Table 52: HDMI Tx Interrupt Bits in HDMI Tx Main Map Register 0xEC96 ....................................................................................................... 252

Table 53: HDMI Tx Interrupt Bits in Main Map Register 0xEC97 .......................................................................................................................... 252

Table 54: Status Bits in Main Map Register 0xEC42 .................................................................................................................................................. 252

Table 55: AVI InfoFrame Configuration Registers ..................................................................................................................................................... 257

Table 56: MPEG InfoFrame Configuration Registers ................................................................................................................................................ 258

Table 57: Gamut Metadata Packet Configuration Registers ..................................................................................................................................... 259

Table 58: HDMI TX Supported Audio Input Modes from Audio Input Pins......................................................................................................... 260

Table 59: Valid Configuration for audio_mode[1:0] ................................................................................................................................................. 262

Table 60: Audio Input Format Summary ..................................................................................................................................................................... 262

Table 61: Valid Configuration for audioif_sf[2:0] Address B8 (Main), Address 0x74[4:2] .................................................................................. 271

Table 62: Recommended N and Expected CTS Values for 32 kHz Audio .............................................................................................................. 274

Table 63: Recommended N and Expected CTS Values for 44.1 kHz and Multiples ............................................................................................. 275



Table 64: Recommended N and Expected CTS Values for 48 kHz and Multiples ................................................................................................ 275

Table 65: I 2 S Channel Status ADV8003 Register Map Location of Fixed Value ..................................................................................................... 278

Table 66: Audio InfoFrame Configuration Registers ................................................................................................................................................. 280

Table 67: ACP Packet Configuration Registers ........................................................................................................................................................... 281

Table 68: ISRC1 Packet Configuration Registers ....................................................................................................................................................... 282

Table 69: ISRC2 Packet Configuration Registers ....................................................................................................................................................... 282

Table 70: KSV Fields Accessed From EDID Map ....................................................................................................................................................... 287

Table 71: Charge Injection Settings .............................................................................................................................................................................. 291

Table 72: CEC Outgoing Message Buffer Registers .................................................................................................................................................... 294

Table 73: CEC Incoming Frame Buffer 0 Registers .................................................................................................................................................... 299



Table 76: Standards Directly Supported by ADV8003 Encoder Processor ............................................................................................................. 310

Table 77: Output Oversampling Modes and Rates ..................................................................................................................................................... 313

Table 78: Typical F

SC

Values ........................................................................................................................................................................................... 315

Table 79: Internal Filter Specifications ......................................................................................................................................................................... 315

Table 80: Sample Color Values for EIA 770.2/EIA770.3 ED/HD Output Standard Selection .............................................................................. 320

Table 81: ED/HD Manual CSC Matrix Default Values .............................................................................................................................................. 322

Table 82: Sample Brightness Control Values 1 .............................................................................................................................................................. 326

Table 83: DAC Gain Control ......................................................................................................................................................................................... 328

Table 84: ED/HD Gamma Curve A .............................................................................................................................................................................. 331

Table 85: ED/HD Gamma Curve B .............................................................................................................................................................................. 331

Table 86: SD Gamma Curve A ...................................................................................................................................................................................... 332

Table 87: ED/HD Sharpness Control Settings for Figure 117 ................................................................................................................................... 337

Table 88: Register Settings for Figure 119 .................................................................................................................................................................... 337

Table 89: Output Filter Requirements .......................................................................................................................................................................... 346

Table 90: Serial Video Rx Level Sensitive Interrupts.................................................................................................................................................. 354

Table 91: Serial Video Rx Edge Sensitive Interrupts .................................................................................................................................................. 354

Table 92: VSP and OSD Interrupts ............................................................................................................................................................................... 355

Table 93: HDMI Tx Interrupts ...................................................................................................................................................................................... 356

Table 94: Recommended PSU Decoupling for ADV8003-8 Parts ........................................................................................................................... 360

Table 95: RGB Input Formats ........................................................................................................................................................................................ 416

Table 96: YCbCr Input Formats .................................................................................................................................................................................... 418

Table 97: Alpha Blending Input Formats ..................................................................................................................................................................... 422

Table 98: RGB TTL Output Formats ............................................................................................................................................................................ 425

Table 99: YCrCb TTL Output Formats ........................................................................................................................................................................ 428



LIST OF EQUATIONS

Equation 1: Calculating DPLL Phase Period .............................................................................................................................................................. 110

Equation 2: Calculating DPLL Clock Period .............................................................................................................................................................. 110

Equation 3: DDR2 Memory Interface Clock Frequency ........................................................................................................................................... 115

Equation 4: Primary Input CSC Channel A Output .................................................................................................................................................. 131

Equation 5: Primary Input CSC Channel B Output .................................................................................................................................................. 131

Equation 6: Primary Input CSC Channel C Output .................................................................................................................................................. 131

Equation 7: Secondary Input CSC Channel A Output .............................................................................................................................................. 134

Equation 8: Secondary Input CSC Channel B Output .............................................................................................................................................. 134

Equation 9: Secondary Input CSC Channel C Output .............................................................................................................................................. 134

Equation 10: RX Input CSC Channel A Output ......................................................................................................................................................... 137

Equation 11: RX Input CSC Channel B Output ......................................................................................................................................................... 137

Equation 12: RX Input CSC Channel C Output ......................................................................................................................................................... 137

Equation 13: HDMI TX CSC Channel A Output ....................................................................................................................................................... 140

Equation 14: HDMI TX CSC Channel B Output ....................................................................................................................................................... 140

Equation 15: HDMI TX CSC Channel C Output ...................................................................................................................................................... 140

Equation 16: Calculating External Memory Field Buffers ........................................................................................................................................ 149

Equation 17: Calculating Interlaced Buffers ............................................................................................................................................................... 163

Equation 18: Calculating RNR Buffers ........................................................................................................................................................................ 167

Equation 19: Calculating External Memory Field Buffers ........................................................................................................................................ 185

Equation 20: Relationship Between Audio Reference and TMDS Clocks .............................................................................................................. 273

Equation 21: Restriction for N Value ........................................................................................................................................................................... 273

Equation 22: Optimal N Value ...................................................................................................................................................................................... 273

Equation 23: Relationship Between N and CTS ......................................................................................................................................................... 273

Equation 24: SD Subcarrier Frequency Calculation .................................................................................................................................................. 314

Equation 25: SD Subcarrier Frequency Calculation .................................................................................................................................................. 314

Equation 26: Gamma Correction Calculation ............................................................................................................................................................ 329


REVISION HISTORY

04/13 – Rev. A to Rev. B

Removed ADI Confidential from footer.

04/13 – Rev. 0 to Rev. A

Removed the descriptionof the Subcarrier Phase Reset and Timing Reset Modes.

Removed mention of non-standard timing mode under Table 76

Removed Section 6.11.2 Audio from Serial Video Rx.

Corrected the I2C readbacks for the Chip ID registers to 0x1AD0 and 0x1AD1 in section 2.2.13

Corrected Figure 25 to read 720P EXOSD input.

Updated Appendix F to replace OSD_P with OSD_IN, which is consistant with the rest of the document.

Updated Appendix F to replace VID_P with P, which is consistant with the rest of the document.

Added a description of the vfe_input_id[3:0] control.

10/13 – Pr.2 to Rev. 0

Functional block diagram updated

Pinout diagrams updated

Unused pin list updated

Pixel mapping updated

Interrupts section updated

Charge injections section added

ARC clarified

DDR2 Interface clarified

10/12 – Pr. 1 to Pr. 2

ADV8003 pin outs updated

2.2.2.3 Section added

2.2.4.3 Updated

2.2.11 Modes which require manual configuration added

2.2.11 Example added

2.2.13 Silicon revision updated

2.2.14 New section on system configuration sequencing added

3 CEA modes not supported by the PVSP clarified

4 CEA modes not supported by the SVSP clarified

6.2 New Section detailing HDMI Tx reset strategy

6.13 Audio Return Channel confirmed as only working in common mode

Tables 47, 48 and 49 added

8.3 Updated

Appendix A Layout recommendations updated

Table 90 Added

Appendix E Updated

Appendix F Pin mapping updated

01/12 – Pr. 0 to Pr. 1

TMDS RX/HDMI Compatible Rx updated to Serial Video Rx

1.1. OVERVIEW updated

1.1.1. Digital Video Input updated

Updated functional block diagram

R_TX1 and R_TX2 resistors updated in pin list

2. ADV8003 TOP LEVEL CONTROL updated

Figure 11: ADV8003 Simplified Block Diagram updated

2.1.1. Selecting a Mode updated



Modes 1 - 12 updated

Modes 13 and 14 added svsp_inp_sel updated

2.1.14. Mode 13 – Added

2.1.15. Mode 14 – Added

Figure 24: ADV8003 Digital Core Muxing - updated

Figure 25:Main TTL Input Channel - updated

2.2.2. Digital Video Input updated vid_format_sel updated

2.2.2.1. Video TTL Input added

2.2.2.2. EXOSD TTL Input added

2.2.2.3. TMDS RX Input added

2.2.2.1. Main TTL Input Channel update and changed to 2.2.2.4

2.2.2.2. OSD TTL Input Channel updated and changed to 2.2.2.5

2.2.2.3. RX Input Channel updated and changed to 2.2.2.6

2.2.4. Clock Configuration updated

2.2.5.1. DDR2 Configuration updated

Table 7: Indication of ADV8003 Capabilities with 2 DDR2 Memories updated

Table 8: Indication of ADV8003 Capabilities with 1 DDR2 Memory updated

2.2.8. VBI Data Insertion updated

Figure 36: ADV8003 Image Processing Colorimetry Breakdown updated

2.2.11. AV-Codes added

2.2.12. Color Space Conversion added

2.2.13. Silicon ID added

Table 12: Supported Input Video Timing and VID updated

Table 13: Supported Output Video Timing and VID updated

3.2.1.6. Game Mode updated

3.2.2.3. Scaler Interpolation Mode updated

3.2.3. Primary VSP Video Output Module updated

3.2.3.9. Block Noise Reduction updated

3.2.3.10. Sharpness Enhancement updated

3.2.3.11. Scaler updated

3.2.3.14. Demo Function updated

3.2.3.15. Progressive to Interlaced Converter for the Primary VSP updated

3.2.3.16. Automatic Contrast Enhancement updated

3.3.1. Introduction to SVSP updated

Table 21: Supported Input Video Timing and VID updated

Table 22: Supported Output Video Timing and VID updated

3.3.3.3. Output Port updated

3.3.3.4. DDR Bypass Mode updated

3.3.3.5. Progressive to Interlaced Converter in SVSP updated

3.5. PROGRESSIVE TO INTERLACED CONVERSION updated

Figure 59: Bitmap OSD Top Level Diagram updated

4.2.4. External Alpha Blending updated

4.2.6. OSD Timers updated

4.2.8.2. SPI Slave Interface updated

4.2.9. OSD Initialization updated

5. TMDS RX updated

5.6. VIDEO FIFO updated

Table 35: HDMI Transmitter Memory Addresses updated

6.10.2. Audio from the TMDS RX updated

6.10.3.1. I2S Audio updated

6.10.3.2. SPDIF Audio updated



8.2. INPUT CONFIGURATION updated

Figure 91: Simplified View of ADV8003 Encoder Block updated

8.4.6. SD Noninterlaced Mode (240p/288p) updated

8.4.9. Color Space Conversion Matrix updated

9.2. RX SECTION updated

9.3. VSP AND OSD SECTION updated

9.4. TX CORE updated

HDMI Transmitter Component Placement updated

Table 77: YCbCr Input Formats updated

10/11 – Pr. 0

Initial version

