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ADV8003 Hardware Manual
Register Map
HDMI Tx2 EDID Map
HDMI Tx2 CEC Map
HDMI Tx2 UDP Map
Register Map Address
0xF600 – 0xF6FF
0xF800 – 0xF8FF
0xFA00 – 0xFAFF
HDMI Tx2 Test Map 0xFB00 – 0xFBFF
It should be noted that the section on the HDMI transmitter, while referring to HDMI Tx1, also equally applies to HDMI Tx2. The same
register bits and controls as per Table 45 apply for both transmitters.
6.1.
GENERAL CONTROLS
To operate the HDMI Tx core, it is necessary to monitor the Hot Plug Detect (HPD) signal from the downstream sink and power up the
Some registers cannot be written to when the signal on the HPD_TXx input pin is low. When the level on the HPD_TX1 pin goes from high to low, some registers will be reset to their default value.
The best method to determine when the level of the signal on the HPD_TXx pin is high is to use the interrupt system. An interrupt can be
sink. If the ADV8003 detects a voltage level higher than 1.8 V on the clock lines of its TMDS output port, rx_sense_int is triggered and
The detection of TMDS clock terminations from downstream sink devices is useful to delay powering up the transmitter sections until the downstream sink devices are actually ready to receive signals. A typical implementation for a sink is to tie the transmitter 5 V power signal to HPD through a series resistor. In this case, the ADV8003 will detect a high level on HPD_TX1 (HPD_TX2 for HDMI Tx 2) regardless of whether or not the downstream sink is powered on and ready to receive a TMDS stream. For this reason, it is best to wait for both the
system_pd , TX2 Main Map, Address 0xF441[6]
This bit is used to power down the Tx.
Function system_pd Description
0
1
Normal operation
Power down Tx hpd_state , TX2 Main Map, Address 0xF442[6] (Read Only)
This bit is used to read back the state of the hot plug detect.
Function hpd_state Description
0
1
Hot Plug Detect inactive (low)
Hot Plug active (high) hpd_override[1:0] , TX2 Main Map, Address 0xF49F[5:4]
This signal is used to select the source of the internal HPD signal.
Rev. B, August 2013 246
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Table of contents
- 2 TABLE OF CONTENTS
- 2 Understanding the ADV8003 Hardware Manual 10
- 2 1. Introduction to the ADV8003 15
- 2 2. ADV8003 Top Level Control 69
- 3 3. Video Signal Processing 144
- 5 4. On Screen Display 208
- 5 5. Serial Video Receiver 227
- 5 6. HDMI Transmitter 245
- 6 7. Consumer Electronics Control 293
- 7 8. Video Encoder 307
- 8 9. Interrupts 349
- 8 Appendix A 358
- 8 Appendix B 363
- 8 Appendix C 393
- 8 Appendix D 402
- 8 Appendix E 403
- 9 Appendix F 416
- 9 List of Figures 431
- 9 List of Tables 435
- 9 List of Equations 437
- 9 Revision History 438
- 9 Understanding the ADV8003 Hardware Manual
- 10 Description of the Hardware Manual
- 10 Disclaimer
- 10 Trademark and Service Mark Notice
- 10 Number Notations
- 10 Register Access Conventions
- 10 Acronyms and Abbreviations
- 13 Field Function Description
- 14 References
- 15 Introduction to the ADV8003
- 15 Overview
- 19 Main Features of the ADV8003
- 21 ADV8003 Functional Block Diagram
- 22 ADV8003 Pinouts
- 67 Protocol for Main I2C Port
- 68 Configuring the ADV8003
- 69 ADV8003 Top Level Control
- 70 ADV8003 Modes of Operation
- 85 ADV8003 Top Level Overview
- 144 Video Signal Processing
- 144 Introduction
- 144 Primary VSP
- 180 Secondary VSP
- 202 VSP Register Access Protocols
- 207 Progressive to Interlaced Conversion
- 208 On Screen Display
- 208 Introduction
- 209 Architecture Overview
- 227 Serial Video Receiver
- 227 + 5 V Detect
- 228 TMDS Clock Activity Detection
- 229 Clock and Data Termination Control
- 229 AV Mute Status
- 229 Deep Color Mode Support
- 230 Video FIFO
- 232 Pixel Repetition
- 233 Sync Signal Polarity Readbacks
- 235 InfoFrame Registers
- 239 Packet Registers
- 242 Customizing Packet/InfoFrame Storage Registers
- 244 HDMI Section Reset Strategy
- 245 HDMI Transmitter
- 246 General Controls
- 247 Reset Strategy
- 248 HDMI DVI Selection
- 248 AV Mute
- 249 Source Product Description InfoFrame
- 250 Spare Packets
- 252 System Monitoring
- 252 EDID/HDCP Controller Status
- 253 EDID/HDCP Controller Error Codes
- 253 Video Setup
- 260 Audio Setup
- 283 EDID Handling
- 285 HDCP Handling
- 290 Audio Return Channel
- 291 Charge Injection Settings
- 293 Consumer Electronics Control
- 294 Main Controls
- 294 CEC Transmit Section
- 296 CEC Receive Section
- 301 Antiglitch Filter Module
- 302 Typical Operation Flow
- 305 Low Power CEC Message Monitoring
- 307 Video Encoder
- 307 Introduction
- 307 Input Configuration
- 310 Output Configuration
- 312 Additional Design Features
- 345 Vertical Blanking Interval
- 346 DAC Configurations
- 349 Interrupts
- 349 Interrupt Pins
- 350 Serial Video Rx Interrupts
- 355 VSP and OSD Section
- 356 HDMI Tx core
- 358 Appendix A
- 358 PCB Layout Recommendations
- 363 Appendix B
- 363 ADV8003 Evaluation Board Schematics
- 394 Appendix C
- 394 ADV8003 Evaluation Board Layout
- 402 Appendix D
- 402 Package Outline Drawing
- 403 Appendix E
- 403 Unused Pin List
- 416 Appendix F
- 416 Pixel Input and Output Formats
- 431 List of Figures
- 435 List of Tables
- 437 List of Equations
- 438 Revision History