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ADV8003 Hardware Manual
InfoFrame
Map Address
0xE35F
0xE360
0xE361
0xE362
0xE363
0xE364
0xE365
0xE366
0xE367
0xE368
0xE369
0xE36A
0xE36B
0xE36C
0xE36D
0xE36E
0xE36F
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Register Name vs_inf_pb_0_12 vs_inf_pb_0_13 vs_inf_pb_0_14 vs_inf_pb_0_15 vs_inf_pb_0_16 vs_inf_pb_0_17 vs_inf_pb_0_18 vs_inf_pb_0_19 vs_inf_pb_0_20 vs_inf_pb_0_21 vs_inf_pb_0_22 vs_inf_pb_0_23 vs_inf_pb_0_24 vs_inf_pb_0_25 vs_inf_pb_0_26 vs_inf_pb_0_27 vs_inf_pb_0_28
Byte Name
Data Byte 11
Data Byte 12
Data Byte 13
Data Byte 14
Data Byte 15
Data Byte 16
Data Byte 17
Data Byte 18
Data Byte 19
Data Byte 20
Data Byte 21
Data Byte 22
Data Byte 23
Data Byte 24
Data Byte 25
Data Byte 26
Data Byte 27
The Vendor Specific InfoFrame registers are considered valid if the following two conditions are met:
• vs_infoframe_det is 1.
•
vs_inf_cksum_err is 0. This condition applies only if always_store_inf is set to 1.
5.10.
PACKET REGISTERS
5.10.1.
ISRC Packet Registers
detailed explanation of the ISRC packet fields.
R/W
Table 42: ISRC1 Packet Registers
Register Name Packet Byte No.
1
Rev. B, August 2013
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
InfoFrame
Map Address
0xF2
0xF3
0xF4
0x8C
0x8D
0x8E
0x8F
0x98
0x99
0x9A
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R
isrc1_header1 isrc1_header2 isrc1_pb_0_1 isrc1_pb_0_2 isrc1_pb_0_3 isrc1_pb_0_4 isrc1_pb_0_5 isrc1_pb_0_6 isrc1_pb_0_7 isrc1_pb_0_8 isrc1_pb_0_9 isrc1_pb_0_10 isrc1_pb_0_11 isrc1_pb_0_12 isrc1_pb_0_13 isrc1_pb_0_14 isrc1_pb_0_15
239
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
Packet Type Value
HB1
HB2
PB0
PB1
PB2
PB3
PB4
ADV8003 Hardware Manual
InfoFrame
Map Address
0x9B
0x9C
0x9D
0x9E
0x9F
0xA0
0xA1
0xA2
0xA3
0xA4
0xA5
0xA6
R/W
R
R
R
R
R
R
R
R
R
R
R
R
Register Name isrc1_pb_0_16 isrc1_pb_0_17 isrc1_pb_0_18 isrc1_pb_0_19 isrc1_pb_0_20 isrc1_pb_0_21 isrc1_pb_0_22 isrc1_pb_0_23 isrc1_pb_0_24 isrc1_pb_0_25 isrc1_pb_0_26 isrc1_pb_0_27
Packet Byte No.
1
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
0xA7 R isrc1_pb_0_28 PB27
1 As defined by the HDMI 1.4 specifications
The ISRC1 packet registers are considered valid if rx_isrc1_pckt_edge_raw is set to 1. isrc1_pckt_raw , IO, Address 0x60[6] (Read Only)
This read-back indicates the raw status signal of the International Standard Recording Code 1 (ISRC1) packet detection signal. This bit resets to 0 after an HDMI packet detection reset or upon writing to isrc1_packet_id.
Function isrc1_pckt_raw Description
0
1
No ISRC1 packets received since last HDMI packet detection reset.
ISRC1 packets received.
R/W
Table 43: ISRC2 Packet Registers
Register Name Packet Byte No.
1 InfoFrame
Map Address
0xE3F5
0x E3F6
0x E3F7
0x E3A8
0x E3A9
0x E3AA
0x E3AB
0x E3AC
0x E3AD
0x E3AE
0x E3AF
0x E3B0
0x E3B1
0x E3B2
0x E3B3
0x E3B4
0x E3B5
0x E3B6
0x E3B7
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
isrc2_header1 isrc2_header2 isrc2_pb_0_1 isrc2_pb_0_2 isrc2_pb_0_3 isrc2_pb_0_4 isrc2_pb_0_5 isrc2_pb_0_6 isrc2_pb_0_7 isrc2_pb_0_8 isrc2_pb_0_9 isrc2_pb_0_10 isrc2_pb_0_11 isrc2_pb_0_12 isrc2_pb_0_13 isrc2_pb_0_14 isrc2_pb_0_15 isrc2_pb_0_16
Packet Type Value
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
HB1
HB2
PB0
PB1
PB2
PB3
PB4
PB5
Rev. B, August 2013 240
InfoFrame
Map Address
0x E3B8
0x E3B9
0x E3BA
0x E3BB
0x E3BC
0x E3BD
0x E3BE
0x E3BF
0x E3C0
0x E3C1
0x E3C2
0x E3C3
1 As defined by the HDMI 1.4 specifications
R/W
R
R
R
R
R
R
R
R
R
R
R
R
Register Name isrc2_pb_0_17 isrc2_pb_0_18 isrc2_pb_0_19 isrc2_pb_0_20 isrc2_pb_0_21 isrc2_pb_0_22 isrc2_pb_0_23 isrc2_pb_0_24 isrc2_pb_0_25 isrc2_pb_0_26 isrc2_pb_0_27 isrc2_pb_0_28
Packet Byte No.
1
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
The ISRC2 packet registers are considered valid if, and only if rx_isrc2_pckt_edge_raw is set to 1.
5.10.2.
Gamut Metadata Packets
Refer to the HDMI 1.3/1.4 specifications for a detailed explanation of the Gamut Metadata packet fields.
R/W
Table 44: Gamut Metadata Packet Registers
Register Name Packet Byte No.
1
Rev. B, August 2013
0xE3CB
0xE3CC
0xE3CD
0xE3CE
0xE3CF
0xE3D0
0xE3D1
0xE3D2
0xE3D3
0xE3D4
0xE3D5
0xE3D6
HDMI
Map Address
0xE3F8
0xE3F9
0xE3FA
0xE3C4
0xE3C5
0xE3C6
0xE3C7
0xE3C8
0xE3C9
0xE3CA
0xE3D7
0xE3D8
0xE3D9
0xE3DA
0xE3DB
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R
gamut_header1 gamut_header2 gamut_mdata_pb_0_1 gamut_mdata_pb_0_2 gamut_mdata_pb_0_3 gamut_mdata_pb_0_4 gamut_mdata_pb_0_5 gamut_mdata_pb_0_6 gamut_mdata_pb_0_7 gamut_mdata_pb_0_8 gamut_mdata_pb_0_9 gamut_mdata_pb_0_10 gamut_mdata_pb_0_11 gamut_mdata_pb_0_12 gamut_mdata_pb_0_13 gamut_mdata_pb_0_14 gamut_mdata_pb_0_15 gamut_mdata_pb_0_16 gamut_mdata_pb_0_17 gamut_mdata_pb_0_18 gamut_mdata_pb_0_19 gamut_mdata_pb_0_20 gamut_mdata_pb_0_21 gamut_mdata_pb_0_22 gamut_mdata_pb_0_23 gamut_mdata_pb_0_24
241
PB13
PB14
PB15
PB16
PB17
PB18
PB7
PB8
PB9
PB10
PB11
PB12
PB2
PB3
PB4
PB5
PB6
Packet Type Value
HB1
HB2
PB0
PB1
PB19
PB20
PB21
PB22
PB23
ADV8003 Hardware Manual
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