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RM0313 Reference manual STM32F37xx and STM32F38xx advanced ARM-based 32-bit MCUs
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RM0313 Reference manual STM32F37xx and STM32F38xx advanced ARM-based 32-bit MCUs Introduction This reference manual targets application developers. It provides complete information on how to use the STM32F373Cx/Rx/Vx and STM32F383Cx/Rx/Vx microcontroller memory and peripherals. The STM32F373Cx/Rx/Vx and STM32F383Cx/Rx/Vx will be referred to as STM32F37xx/STM32F38xx throughout the document, unless otherwise specified. The STM32F37xx/STM32F38xx is a family of microcontrollers with different memory sizes, packages and peripherals. For ordering information, mechanical and electrical device characteristics please refer to the STM32F37xx/STM32F38xx datasheet. For information on the ARM Cortex™-M4 core with FPU, please refer to the STM32F3xx/STM32F4xx programming manual (PM0214). Related documents • STM32F37xx/STM32F38xx datasheet available from your nearest ST sales office. • STM32F3xx/F4xx Cortex™-M4 programming manual (PM0214) available from http://www.st.com. December 2013 DocID022448 Rev 2 1/897 www.st.com Contents RM0313 Contents 1 2 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.1 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.2 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.3 Peripheral availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 System architecture and memory overview . . . . . . . . . . . . . . . . . . . . . 37 2.1 2.2 2.3 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.1.1 S0: I-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.1.2 S1: D-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.1.3 S2: S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.1.4 S3, S4: DMA-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.1.5 BusMatrix-S (5M5S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.2.2 Memory map and register boundary addresses . . . . . . . . . . . . . . . . . . 41 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.3.1 3 2.4 Bit banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.5 Flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.6 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.1 Flash main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.2 Flash memory functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.3 2/897 Parity check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2.1 Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.2.2 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.2.3 Flash program and erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.3.1 Read protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.3.2 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.3.3 Option byte block write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.4 Flash interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.5 Flash register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 DocID022448 Rev 2 RM0313 Contents 3.6 3.5.1 Flash access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . . . 61 3.5.2 Flash key register (FLASH_KEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.5.3 Flash option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . . 62 3.5.4 Flash status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.5.5 Flash control register (FLASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.5.6 Flash address register (FLASH_AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.5.7 Option byte register (FLASH_OBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.5.8 Write protection register (FLASH_WRPR) . . . . . . . . . . . . . . . . . . . . . . . 66 Flash register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4 Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . 71 6 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.2 CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.3 CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.4 Polynomial programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.5 CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.5.1 Data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.5.2 Independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.5.3 Control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.5.4 Initial CRC value (CRC_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.5.5 CRC polynomial (CRC_POL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.5.6 CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.1 6.2 6.3 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.1.1 Independent A/D and D/A converter supply and reference voltage . . . . 79 6.1.2 Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.1.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.2.1 Power on reset (POR)/power down reset (PDR) . . . . . . . . . . . . . . . . . . 81 6.2.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.2.3 External NPOR signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.1 Slowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 DocID022448 Rev 2 3/897 26 Contents RM0313 6.4 7 Peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3.3 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3.4 Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.3.5 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.6 Auto-wakeup from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Power control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.4.1 Power control register (PWR_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.4.2 Power control/status register (PWR_CSR) . . . . . . . . . . . . . . . . . . . . . . 93 6.4.3 PWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.1 7.2 4/897 6.3.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.1.1 Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.1.2 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.1.3 RTC domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.2.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.2.2 HSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.2.3 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.2.4 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.2.5 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.2.6 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.2.7 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.2.8 ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.2.9 SDADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.2.10 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.2.11 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.2.12 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.2.13 Internal/external clock measurement using TIM14 . . . . . . . . . . . . . . . 107 7.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7.4 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.4.1 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.4.2 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 111 7.4.3 Clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 7.4.4 APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 117 7.4.5 APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . . . . . 119 7.4.6 AHB peripheral clock enable register (RCC_AHBENR) . . . . . . . . . . . 121 DocID022448 Rev 2 RM0313 8 Contents 7.4.7 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 123 7.4.8 APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . . . . . . 125 7.4.9 Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . 128 7.4.10 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 7.4.11 AHB peripheral reset register (RCC_AHBRSTR) . . . . . . . . . . . . . . . . 132 7.4.12 Clock configuration register 2 (RCC_CFGR2) . . . . . . . . . . . . . . . . . . . 134 7.4.13 Clock configuration register 3 (RCC_CFGR3) . . . . . . . . . . . . . . . . . . . 135 7.4.14 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 8.2 GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 8.3 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 8.4 8.3.1 General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 8.3.2 I/O pin alternate function multiplexer and mapping . . . . . . . . . . . . . . . 142 8.3.3 I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 8.3.4 I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 8.3.5 I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 8.3.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 8.3.7 I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 8.3.8 External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 8.3.9 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 8.3.10 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 8.3.11 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 8.3.12 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 8.3.13 Using the HSE or LSE oscillator pins as GPIOs . . . . . . . . . . . . . . . . . 147 8.3.14 Using the GPIO pins in the RTC supply domain . . . . . . . . . . . . . . . . . 147 GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 8.4.1 GPIO port mode register (GPIOx_MODER) (x = A..F) . . . . . . . . . . . . 148 8.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A..F) . . . . . . . 148 8.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 8.4.5 GPIO port input data register (GPIOx_IDR) (x = A..F) . . . . . . . . . . . . 150 8.4.6 GPIO port output data register (GPIOx_ODR) (x = A..F) . . . . . . . . . . 151 8.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..F) . . . . . . . . . 151 DocID022448 Rev 2 5/897 26 Contents 9 RM0313 8.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A..E) . . . . . 153 8.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A..F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 8.4.11 GPIO port bit reset register (GPIOx_BRR) (x = A..F) . . . . . . . . . . . . . 154 8.4.12 GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 SYSCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 9.1.1 SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . . . . . . . . . 157 9.1.2 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 9.1.3 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 9.1.4 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 9.1.5 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 9.1.6 SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . . . . . . . . . 161 9.1.7 SYSCFG register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 164 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 10.2 DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 10.3 DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 10.4 DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 10.5 6/897 GPIO port configuration lock register (GPIOx_LCKR) (x = A, B, and D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 157 9.1 10 8.4.8 10.4.1 DMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 10.4.2 Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 10.4.3 DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 10.4.4 Programmable data width, data alignment and endians . . . . . . . . . . . 168 10.4.5 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 10.4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 10.4.7 DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 10.5.1 DMA interrupt status register (DMA_ISR) . . . . . . . . . . . . . . . . . . . . . . 176 10.5.2 DMA interrupt flag clear register (DMA_IFCR) . . . . . . . . . . . . . . . . . . 177 10.5.3 DMA channel x configuration register (DMA_CCRx) (x = 1..7, where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 DocID022448 Rev 2 RM0313 11 Contents DMA channel x number of data register (DMA_CNDTRx) (x = 1..7, where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 10.5.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..7, where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 10.5.6 DMA channel x memory address register (DMA_CMARx) (x = 1..7, where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 10.5.7 DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 11.1 11.2 11.3 12 10.5.4 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 184 11.1.1 NVIC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 11.1.2 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 11.1.3 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Extended interrupts and events controller (EXTI) . . . . . . . . . . . . . . . . . 187 11.2.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 11.2.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 11.2.3 Wakeup event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 11.2.4 Asynchronous Internal Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 11.2.5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 11.2.6 External and internal interrupt/event line mapping . . . . . . . . . . . . . . . 191 EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 11.3.1 Interrupt mask register (EXTI_IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 11.3.2 Event mask register (EXTI_EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 11.3.3 Rising trigger selection register (EXTI_RTSR) . . . . . . . . . . . . . . . . . . 194 11.3.4 Falling trigger selection register (EXTI_FTSR) . . . . . . . . . . . . . . . . . . 194 11.3.5 Software interrupt event register (EXTI_SWIER) . . . . . . . . . . . . . . . . . 195 11.3.6 Pending register (EXTI_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 11.3.7 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 12.1 ADC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 12.2 ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 12.3 ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 12.3.1 ADC on-off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 12.3.2 ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 12.3.3 Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 12.3.4 Single conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 DocID022448 Rev 2 7/897 26 Contents RM0313 12.3.5 Continuous conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 12.3.6 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 12.3.7 Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 12.3.8 Scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 12.3.9 Injected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 12.3.10 Discontinuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 12.4 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 12.5 Data alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 12.6 Channel-by-channel programmable sample time . . . . . . . . . . . . . . . . . . 206 12.7 Conversion on external trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 12.8 DMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 12.9 Temperature sensor and internal reference voltage . . . . . . . . . . . . . . . . 207 12.10 Battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 12.11 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 12.12 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 12.12.1 ADC status register (ADC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 12.12.2 ADC control register 1 (ADC_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 12.12.3 ADC control register 2 (ADC_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 12.12.4 ADC sample time register 1 (ADC_SMPR1) . . . . . . . . . . . . . . . . . . . . 215 12.12.5 ADC sample time register 2 (ADC_SMPR2) . . . . . . . . . . . . . . . . . . . . 216 12.12.6 ADC injected channel data offset register x (ADC_JOFRx)(x=1..4) . . 216 12.12.7 ADC watchdog high threshold register (ADC_HTR) . . . . . . . . . . . . . . 217 12.12.8 ADC watchdog low threshold register (ADC_LTR) . . . . . . . . . . . . . . . 217 12.12.9 ADC regular sequence register 1 (ADC_SQR1) . . . . . . . . . . . . . . . . . 218 12.12.10 ADC regular sequence register 2 (ADC_SQR2) . . . . . . . . . . . . . . . . . 219 12.12.11 ADC regular sequence register 3 (ADC_SQR3) . . . . . . . . . . . . . . . . . 220 12.12.12 ADC injected sequence register (ADC_JSQR) . . . . . . . . . . . . . . . . . . 221 12.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . . . . . . . . . . . 222 12.12.14 ADC regular data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . 222 12.12.15 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 13 8/897 Sigma-delta analog-to-digital converter (SDADC) . . . . . . . . . . . . . . . 225 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 13.2 SDADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 13.3 SDADC pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 13.4 SDADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 DocID022448 Rev 2 RM0313 Contents 13.5 SDADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 13.5.1 SDADC on-off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 13.5.2 Power down and Standby low power modes . . . . . . . . . . . . . . . . . . . . 229 13.5.3 SDADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 13.5.4 Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 13.5.5 Differential and single-ended modes . . . . . . . . . . . . . . . . . . . . . . . . . . 230 13.5.6 Configuring the analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 13.5.7 Launching calibration and determining the offset values . . . . . . . . . . . 234 13.5.8 Launching conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 13.5.9 Continuous and fast continuous modes . . . . . . . . . . . . . . . . . . . . . . . . 235 13.5.10 Request precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 13.5.11 Launching conversions with deterministic timing . . . . . . . . . . . . . . . . . 237 13.5.12 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 13.5.13 Analog input signal ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 13.5.14 Input impedance of SDADC analog input and VREFSD reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 13.6 SDADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 13.6.1 Register write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 13.6.2 SDADC control register 1 (SDADC_CR1) . . . . . . . . . . . . . . . . . . . . . . 241 13.6.3 SDADC control register 2 (SDADC_CR2) . . . . . . . . . . . . . . . . . . . . . . 244 13.6.4 SDADC interrupt and status register (SDADC_ISR) . . . . . . . . . . . . . . 247 13.6.5 SDADC interrupt and status clear register (SDADC_CLRISR) . . . . . . 249 13.6.6 SDADC injected channel group selection register (SDADC_JCHGR) . 250 13.6.7 SDADC configuration 0 register (SDADC_CONF0R) . . . . . . . . . . . . . 251 13.6.8 SDADC configuration 1 register (SDADC_CONF1R) . . . . . . . . . . . . . 252 13.6.9 SDADC configuration 2 register (SDADC_CONF2R) . . . . . . . . . . . . . 253 13.6.10 SDADC channel configuration register 1 (SDADC_CONFCHR1) . . . . 254 13.6.11 SDADC channel configuration register 2 (SDADC_CONFCHR2) . . . . 254 13.6.12 SDADC data register for injected group (SDADC_JDATAR) . . . . . . . . 255 13.6.13 SDADC data register for the regular channel (SDADC_RDATAR) . . . . 256 13.6.14 SDADC1 and SDADC2 injected data register (SDADC_JDATA12R) . . 257 13.6.15 SDADC1 and SDADC2 regular data register (SDADC_RDATA12R) . . 258 13.6.16 SDADC1 and SDADC3 injected data register (SDADC_JDATA13R) . . 259 13.6.17 SDADC1 and SDADC3 regular data register (SDADC_RDATA13R) . . 260 13.6.18 SDADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 14 Digital-to-analog converter (DAC1 and DAC2) . . . . . . . . . . . . . . . . . . 263 DocID022448 Rev 2 9/897 26 Contents RM0313 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 14.2 DAC1/2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 14.3 Single mode functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 14.4 10/897 14.3.1 DAC channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 14.3.2 DAC output buffer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 14.3.3 DAC data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 14.3.4 DAC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 14.3.5 DAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 14.3.6 DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Dual mode functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 14.4.1 DAC channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 14.4.2 DAC output buffer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 14.4.3 DAC data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 14.4.4 DAC channel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 14.4.5 Description of dual conversion modes . . . . . . . . . . . . . . . . . . . . . . . . . 270 14.4.6 DAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 14.4.7 DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 14.5 Noise generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 14.6 Triangle-wave generation 14.7 DMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 14.8 DAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 14.8.1 DAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 14.8.2 DAC software trigger register (DAC_SWTRIGR) . . . . . . . . . . . . . . . . . 281 14.8.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 14.8.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 14.8.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 14.8.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 14.8.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 14.8.8 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 14.8.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 DocID022448 Rev 2 RM0313 Contents 14.8.10 DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 14.8.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 14.8.12 DAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . . 285 14.8.13 DAC channel2 data output register (DAC_DOR2) . . . . . . . . . . . . . . . . 285 14.8.14 DAC status register (DAC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 14.8.15 DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 15 Comparator (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 15.1 COMP introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 15.2 COMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 15.3 COMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 15.4 15.5 16 15.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 15.3.2 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 15.3.3 Comparator inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 15.3.4 Interrupt and wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 15.4.1 Comparator LOCK mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 15.4.2 Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 COMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 15.5.1 COMP control and status register (COMP_CSR) . . . . . . . . . . . . . . . . 293 15.5.2 COMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 General-purpose timers (TIM2 to TIM5, TIM19) . . . . . . . . . . . . . . . . . 297 16.1 Ito TIM5/TIM19 ntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 16.2 TIM2 to TIM5/TIM19 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 16.3 TIM2 to TIM5/TIM19 functional description . . . . . . . . . . . . . . . . . . . . . . 298 16.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 16.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 16.3.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 16.3.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 16.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 16.3.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 16.3.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 16.3.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 16.3.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 DocID022448 Rev 2 11/897 26 Contents RM0313 16.3.10 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 16.3.11 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 324 16.3.12 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 16.3.13 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 16.3.14 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 328 16.3.15 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 16.3.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 16.4 TIM2 to TIM5/TIM19 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 16.4.1 TIMx control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 337 16.4.2 TIMx control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 339 16.4.3 TIMx slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . . . 340 16.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . 342 16.4.5 TIMx status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 16.4.6 TIMx event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . 345 16.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . 346 16.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . . . 349 16.4.9 TIMx capture/compare enable register (TIMx_CCER) . . . . . . . . . . . . . 350 16.4.10 TIMx counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 16.4.11 TIMx prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 16.4.12 TIMx auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 352 16.4.13 TIMx capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . . . . 353 16.4.14 TIMx capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . . . . 353 16.4.15 TIMx capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . . . . . . 354 16.4.16 TIMx capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . . . . . . 354 16.4.17 TIMx DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . . . . . . 355 16.4.18 TIMx DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . . . . . . 355 16.4.19 TIM2 option register (TIM2_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 16.4.20 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 17 General-purpose timers (TIM12/13/14) . . . . . . . . . . . . . . . . . . . . . . . . 360 17.1 TIM12/13/14 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 17.2 TIM12/13/14 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 17.2.1 12/897 TIM12 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 17.3 TIM13/TIM14 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 17.4 TIM12/13/14 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 17.4.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 17.4.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 DocID022448 Rev 2 RM0313 Contents 17.4.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 17.4.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 17.4.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 17.4.6 PWM input mode (only for TIM12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 17.4.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 17.4.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 17.4.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 17.4.10 One-pulse mode (only for TIM12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 17.4.11 TIM12 external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . . . 379 17.4.12 Timer synchronization (TIM12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 17.4.13 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 17.5 TIM12 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 17.5.1 TIM12 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . 383 17.5.2 TIM12 slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . . 384 17.5.3 TIM12 Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . . . . 385 17.5.4 TIM12 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 17.5.5 TIM12 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . 388 17.5.6 TIM12 capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . 389 17.5.7 TIM12 capture/compare enable register (TIMx_CCER) . . . . . . . . . . . 392 17.5.8 TIM12 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 17.5.9 TIM12 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 17.5.10 TIM12 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . 393 17.5.11 TIM12 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . . . 394 17.5.12 TIM12 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . . . 394 17.5.13 TIM12 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 17.6 TIM13/14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 17.6.1 TIM13/14 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . 397 17.6.2 TIM13/14 Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . 398 17.6.3 TIM13/14 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . 398 17.6.4 TIM13/14 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . 399 17.6.5 TIM13/14 capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 17.6.6 TIM13/14 capture/compare enable register (TIMx_CCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 17.6.7 TIM13/14 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 17.6.8 TIM13/14 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 17.6.9 TIM13/14 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . 404 DocID022448 Rev 2 13/897 26 Contents RM0313 17.6.10 TIM13/14 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . 405 17.6.11 TIM14 option register (TIM14_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 17.6.12 TIM13/14 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 18 General-purpose timers (TIM15/16/17) . . . . . . . . . . . . . . . . . . . . . . . . 408 18.1 TIM15/16/17 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 18.2 TIM15 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 18.3 TIM16 and TIM17 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 18.4 TIM15/16/17 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 18.4.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 18.4.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 18.4.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 18.4.4 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 18.4.5 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 18.4.6 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 18.4.7 PWM input mode (only for TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 18.4.8 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 18.4.9 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 18.4.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 18.4.11 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 428 18.4.12 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 18.4.13 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 18.4.14 TIM15 and external trigger synchronization (only for TIM15) . . . . . . . 436 18.4.15 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 18.4.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 18.5 TIM15 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 18.5.1 TIM15 control register 1 (TIM15_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 439 18.5.2 TIM15 control register 2 (TIM15_CR2) . . . . . . . . . . . . . . . . . . . . . . . . 440 18.5.3 TIM15 slave mode control register (TIM15_SMCR) . . . . . . . . . . . . . . 442 18.5.4 TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . . . . . . . . . . 444 18.5.5 TIM15 status register (TIM15_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 18.5.6 TIM15 event generation register (TIM15_EGR) . . . . . . . . . . . . . . . . . . 446 18.5.7 TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . . . . . 447 18.5.8 TIM15 capture/compare enable register (TIM15_CCER) . . . . . . . . . . 450 18.5.9 TIM15 counter (TIM15_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 18.5.10 TIM15 prescaler (TIM15_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 18.5.11 TIM15 auto-reload register (TIM15_ARR) . . . . . . . . . . . . . . . . . . . . . . 453 14/897 DocID022448 Rev 2 RM0313 Contents 18.5.12 TIM15 repetition counter register (TIM15_RCR) . . . . . . . . . . . . . . . . . 454 18.5.13 TIM15 capture/compare register 1 (TIM15_CCR1) . . . . . . . . . . . . . . . 454 18.5.14 TIM15 capture/compare register 2 (TIM15_CCR2) . . . . . . . . . . . . . . . 455 18.5.15 TIM15 break and dead-time register (TIM15_BDTR) . . . . . . . . . . . . . 455 18.5.16 TIM15 DMA control register (TIM15_DCR) . . . . . . . . . . . . . . . . . . . . . 457 18.5.17 TIM15 DMA address for full transfer (TIM15_DMAR) . . . . . . . . . . . . . 458 18.5.18 TIM15 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 18.6 TIM16&TIM17 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 18.6.1 TIM16&TIM17 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . 461 18.6.2 TIM16&TIM17 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . 462 18.6.3 TIM16&TIM17 DMA/interrupt enable register (TIMx_DIER) . . . . . . . . 464 18.6.4 TIM16&TIM17 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . 465 18.6.5 TIM16&TIM17 event generation register (TIMx_EGR) . . . . . . . . . . . . 466 18.6.6 TIM16&TIM17 capture/compare mode register 1 (TIMx_CCMR1) . . . 467 18.6.7 TIM16&TIM17 capture/compare enable register (TIMx_CCER) . . . . . 470 18.6.8 TIM16&TIM17 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . 473 18.6.9 TIM16&TIM17 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . 473 18.6.10 TIM16&TIM17 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . 473 18.6.11 TIM16&TIM17 repetition counter register (TIMx_RCR) . . . . . . . . . . . . 474 18.6.12 TIM16&TIM17 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . 474 18.6.13 TIM16&TIM17 break and dead-time register (TIMx_BDTR) . . . . . . . . 475 18.6.14 TIM16&TIM17 DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . 476 18.6.15 TIM16&TIM17 DMA address for full transfer (TIMx_DMAR) . . . . . . . . 477 18.6.16 TIM16&TIM17 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 19 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 19.1 20 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 Basic timers (TIM6/7/18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 20.2 TIM6/7/18 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 20.3 TIM6/7/18 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 20.4 20.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 20.3.2 Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 20.3.3 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 20.3.4 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 TIM6/7/18 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 DocID022448 Rev 2 15/897 26 Contents 21 RM0313 16/897 TIM6/7/18 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . 488 20.4.2 TIM6/7/18 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . 490 20.4.3 TIM6/7/18 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . 490 20.4.4 TIM6/7/18 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . 491 20.4.5 TIM6/7/18 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . 491 20.4.6 TIM6/7/18 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 20.4.7 TIM6/7/18 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 20.4.8 TIM6/7/18 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . 492 20.4.9 TIM6/7/18 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 21.2 IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 21.3 IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 21.4 22 20.4.1 21.3.1 Window option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 21.3.2 Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 21.3.3 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 21.3.4 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 21.4.1 Key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 21.4.2 Prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 21.4.3 Reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 21.4.4 Status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 21.4.5 Window register (IWDG_WINR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 21.4.6 IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . 502 22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 22.2 WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 22.3 WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 22.4 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . 504 22.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 22.6 WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 22.6.1 Control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 22.6.2 Configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . 506 22.6.3 Status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 DocID022448 Rev 2 RM0313 Contents 22.6.4 23 WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 23.2 RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 23.3 RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 23.3.1 RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 23.3.2 GPIOs controlled by the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 23.3.3 Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 23.3.4 Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 23.3.5 Programmable alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 23.3.6 Periodic auto-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 23.3.7 RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 23.3.8 Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 23.3.9 Resetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 23.3.10 RTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 23.3.11 RTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 23.3.12 RTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 23.3.13 Time-stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 23.3.14 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 23.3.15 Calibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 23.3.16 Alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 23.4 RTC low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 23.5 RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 23.6 RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 23.6.1 RTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 23.6.2 RTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 23.6.3 RTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 23.6.4 RTC initialization and status register (RTC_ISR) . . . . . . . . . . . . . . . . . 531 23.6.5 RTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . . 534 23.6.6 RTC wakeup timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . . . 535 23.6.7 RTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . . 536 23.6.8 RTC alarm B register (RTC_ALRMBR) . . . . . . . . . . . . . . . . . . . . . . . . 537 23.6.9 RTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . . 538 23.6.10 RTC sub second register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . . 539 23.6.11 RTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . . 540 DocID022448 Rev 2 17/897 26 Contents RM0313 23.6.12 RTC timestamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . . 541 23.6.13 RTC timestamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . . 542 23.6.14 RTC time-stamp sub second register (RTC_TSSSR) . . . . . . . . . . . . . 543 23.6.15 RTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . . 544 23.6.16 RTC tamper and alternate function configuration register (RTC_TAFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 23.6.17 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . . . . . . . . 548 23.6.18 RTC alarm B sub second register (RTC_ALRMBSSR) . . . . . . . . . . . . 549 23.6.19 RTC backup registers (RTC_BKPxR) . . . . . . . . . . . . . . . . . . . . . . . . . 550 23.6.20 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551 24 Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . 553 24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 24.2 I2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 24.3 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 24.4 I2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 24.4.1 I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 24.4.2 I2C clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 24.4.3 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 24.4.4 I2C initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 24.4.5 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562 24.4.6 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563 24.4.7 I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 24.4.8 I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 24.4.9 I2Cx_TIMINGR register configuration examples . . . . . . . . . . . . . . . . . 585 24.4.10 SMBus specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 24.4.11 SMBus initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589 24.4.12 SMBus: I2Cx_TIMEOUTR register configuration examples . . . . . . . . 591 24.4.13 SMBus slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 24.4.14 Wakeup from STOP on address match . . . . . . . . . . . . . . . . . . . . . . . . 599 24.4.15 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 24.4.16 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 24.4.17 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 24.5 I2C low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 24.6 I2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 24.7 I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 24.7.1 18/897 Control register 1 (I2Cx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 DocID022448 Rev 2 RM0313 Contents 24.7.2 Control register 2 (I2Cx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 24.7.3 Own address 1 register (I2Cx_OAR1) . . . . . . . . . . . . . . . . . . . . . . . . . 609 24.7.4 Own address 2 register (I2Cx_OAR2) . . . . . . . . . . . . . . . . . . . . . . . . . 610 24.7.5 Timing register (I2Cx_TIMINGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 24.7.6 Timeout register (I2Cx_TIMEOUTR) . . . . . . . . . . . . . . . . . . . . . . . . . . 612 24.7.7 Interrupt and Status register (I2Cx_ISR) . . . . . . . . . . . . . . . . . . . . . . . 613 24.7.8 Interrupt clear register (I2Cx_ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 24.7.9 PEC register (I2Cx_PECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 24.7.10 Receive data register (I2Cx_RXDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 617 24.7.11 Transmit data register (I2Cx_TXDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 617 24.7.12 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 25 Universal synchronous asynchronous receiver transmitter (USART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 25.1 USART introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 25.2 USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 25.3 USART extended features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 25.4 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622 25.5 USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622 25.5.1 USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 25.5.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626 25.5.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628 25.5.4 Baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634 25.5.5 Tolerance of the USART receiver to clock deviation . . . . . . . . . . . . . . 636 25.5.6 Auto baud rate detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 25.5.7 Multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638 25.5.8 ModBus communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640 25.5.9 Parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640 25.5.10 LIN (local interconnection network) mode . . . . . . . . . . . . . . . . . . . . . . 641 25.5.11 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644 25.5.12 Single-wire half-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . 646 25.5.13 Smartcard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647 25.5.14 IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 25.5.15 Continuous communication using DMA . . . . . . . . . . . . . . . . . . . . . . . . 654 25.5.16 Hardware flow control and RS485 Driver Enable . . . . . . . . . . . . . . . . 656 25.5.17 Wakeup from Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658 25.6 USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 DocID022448 Rev 2 19/897 26 Contents RM0313 25.7 USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661 25.7.1 Control register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661 25.7.2 Control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665 25.7.3 Control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669 25.7.4 Baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 25.7.5 Guard time and prescaler register (USART_GTPR) . . . . . . . . . . . . . . 672 25.7.6 Receiver timeout register (USART_RTOR) . . . . . . . . . . . . . . . . . . . . . 673 25.7.7 Request register (USART_RQR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675 25.7.8 Interrupt & status register (USART_ISR) . . . . . . . . . . . . . . . . . . . . . . . 676 25.7.9 Interrupt flag clear register (USART_ICR) . . . . . . . . . . . . . . . . . . . . . . 680 25.7.10 Receive data register (USART_RDR) . . . . . . . . . . . . . . . . . . . . . . . . . 682 25.7.11 Transmit data register (USART_TDR) . . . . . . . . . . . . . . . . . . . . . . . . . 683 25.7.12 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684 26 Serial peripheral interface/ inter-IC sound (SPI/I2S) . . . . . . . . . . . . . 685 26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 26.1.1 SPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 26.1.2 SPI extended features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 26.1.3 I2S features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 26.2 SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 26.3 SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 26.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 26.3.2 Communications between one master and one slave . . . . . . . . . . . . . 688 26.3.3 Standard multi-slave communication . . . . . . . . . . . . . . . . . . . . . . . . . . 690 26.3.4 Slave select (NSS) pin management . . . . . . . . . . . . . . . . . . . . . . . . . . 691 26.3.5 Communication formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 26.3.6 Configuration of SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695 26.3.7 Procedure for enabling SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696 26.3.8 Data transmission and reception procedures . . . . . . . . . . . . . . . . . . . 696 26.3.9 SPI status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706 26.3.10 SPI error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707 26.4 26.5 20/897 SPI special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 26.4.1 NSS pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 26.4.2 TI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 26.4.3 CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709 SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 DocID022448 Rev 2 RM0313 Contents 26.6 26.7 I2S functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 26.6.1 I2S general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 26.6.2 Supported audio protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713 26.6.3 Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719 26.6.4 I2S master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722 26.6.5 I2S slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724 26.6.6 I2S status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 26.6.7 I2S error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727 26.6.8 I2S interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727 26.6.9 DMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 SPI and I2S registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729 26.7.1 SPI control register 1 (SPIx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729 26.7.2 SPI control register 2 (SPIx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731 26.7.3 SPI status register (SPIx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734 26.7.4 SPI data register (SPIx_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 26.7.5 SPI CRC polynomial register (SPIx_CRCPR) . . . . . . . . . . . . . . . . . . . 736 26.7.6 SPI Rx CRC register (SPIx_RXCRCR) . . . . . . . . . . . . . . . . . . . . . . . . 737 26.7.7 SPI Tx CRC register (SPIx_TXCRCR) . . . . . . . . . . . . . . . . . . . . . . . . 737 26.7.8 SPIx_I2S configuration register (SPIx_I2SCFGR) . . . . . . . . . . . . . . . . 738 26.7.9 SPIx_I2S prescaler register (SPIx_I2SPR) . . . . . . . . . . . . . . . . . . . . . 740 26.7.10 SPI/I2S register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 27 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 27.2 TSC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 27.3 TSC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 27.3.1 TSC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 27.3.2 Surface charge transfer acquisition overview . . . . . . . . . . . . . . . . . . . 743 27.3.3 Reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 27.3.4 Charge transfer acquisition sequence . . . . . . . . . . . . . . . . . . . . . . . . . 746 27.3.5 Spread spectrum feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 27.3.6 Max count error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 27.3.7 Sampling capacitor I/O and channel I/O mode selection . . . . . . . . . . . 748 27.3.8 Acquisition mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 27.3.9 I/O hysteresis and analog switch control . . . . . . . . . . . . . . . . . . . . . . . 749 27.3.10 Capacitive sensing GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 DocID022448 Rev 2 21/897 26 Contents RM0313 27.4 TSC low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 27.5 TSC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 27.6 TSC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 27.6.1 TSC control register (TSC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 27.6.2 TSC interrupt enable register (TSC_IER) . . . . . . . . . . . . . . . . . . . . . . 753 27.6.3 TSC interrupt clear register (TSC_ICR) . . . . . . . . . . . . . . . . . . . . . . . . 754 27.6.4 TSC interrupt status register (TSC_ISR) . . . . . . . . . . . . . . . . . . . . . . . 754 27.6.5 TSC I/O hysteresis control register (TSC_IOHCR) . . . . . . . . . . . . . . . 756 27.6.6 TSC I/O analog switch control register (TSC_IOASCR) . . . . . . . . . . . 756 27.6.7 TSC I/O sampling control register (TSC_IOSCR) . . . . . . . . . . . . . . . . 757 27.6.8 TSC I/O channel control register (TSC_IOCCR) . . . . . . . . . . . . . . . . . 757 27.6.9 TSC I/O group control status register (TSC_IOGCSR) . . . . . . . . . . . . 758 27.6.10 TSC I/O group x counter register (TSC_IOGxCR) (x = 1..8) . . . . . . . . 758 27.6.11 TSC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 28 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761 28.1 bxCAN introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761 28.2 bxCAN main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761 28.3 bxCAN general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 28.4 28.5 22/897 28.3.1 CAN 2.0B active core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 28.3.2 Control, status and configuration registers . . . . . . . . . . . . . . . . . . . . . 762 28.3.3 Tx mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 28.3.4 Acceptance filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 bxCAN operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 28.4.1 Initialization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 28.4.2 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 28.4.3 Sleep mode (low power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 28.5.1 Silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 28.5.2 Loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 28.5.3 Loop back combined with silent mode . . . . . . . . . . . . . . . . . . . . . . . . . 766 28.6 STM32F37xx/STM32F38xx in Debug mode . . . . . . . . . . . . . . . . . . . . . 767 28.7 bxCAN functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767 28.7.1 Transmission handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767 28.7.2 Time triggered communication mode . . . . . . . . . . . . . . . . . . . . . . . . . 769 28.7.3 Reception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769 DocID022448 Rev 2 RM0313 29 Contents 28.7.4 Identifier filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770 28.7.5 Message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 28.7.6 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776 28.7.7 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776 28.8 bxCAN interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779 28.9 CAN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780 28.9.1 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780 28.9.2 CAN control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780 28.9.3 CAN mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791 28.9.4 CAN filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798 28.9.5 bxCAN register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802 Universal serial bus full-speed device interface (USB) . . . . . . . . . . . 806 29.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806 29.2 USB main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806 29.3 USB functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807 29.3.1 29.4 29.5 30 Description of USB blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808 Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809 29.4.1 Generic USB device programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 809 29.4.2 System and power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 29.4.3 Double-buffered endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814 29.4.4 Isochronous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817 29.4.5 Suspend/Resume events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818 USB registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820 29.5.1 Common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820 29.5.2 Endpoint-specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826 29.5.3 Buffer descriptor table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831 29.5.4 USB register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834 HDMI-CEC controller (HDMI-CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836 30.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836 30.2 HDMI-CEC controller main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836 30.3 HDMI-CEC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837 30.3.1 HDMI-CEC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837 30.3.2 Message description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838 30.3.3 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838 DocID022448 Rev 2 23/897 26 Contents RM0313 30.4 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839 30.4.1 30.5 31 Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841 30.5.1 Bit error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841 30.5.2 Message error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841 30.5.3 Bit Rising Error (BRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841 30.5.4 Short Bit Period Error (SBPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842 30.5.5 Long Bit Period Error (LBPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842 30.5.6 Transmission Error Detection (TXERR) . . . . . . . . . . . . . . . . . . . . . . . . 844 30.6 HDMI-CEC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845 30.7 HDMI-CEC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846 30.7.1 CEC control register (CEC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846 30.7.2 CEC configuration register (CEC_CFGR) . . . . . . . . . . . . . . . . . . . . . . 847 30.7.3 CEC Tx data register (CEC_TXDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 850 30.7.4 CEC Rx Data Register (CEC_RXDR) . . . . . . . . . . . . . . . . . . . . . . . . . 850 30.7.5 CEC Interrupt and Status Register (CEC_ISR) . . . . . . . . . . . . . . . . . . 850 30.7.6 CEC interrupt enable register (CEC_IER) . . . . . . . . . . . . . . . . . . . . . . 852 30.7.7 HDMI-CEC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854 Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855 31.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855 31.2 Reference ARM documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857 31.3 SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . 857 31.3.1 31.4 Mechanism to select the JTAG-DP or the SW-DP . . . . . . . . . . . . . . . . 858 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858 31.4.1 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858 31.4.2 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858 31.4.3 Internal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . . 859 31.4.4 Using serial wire and releasing the unused debug pins as GPIOs . . . 860 31.5 STM32F37xx and STM32F38xx JTAG TAP connection . . . . . . . . . . . . . 860 31.6 ID codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861 31.7 24/897 SFT option bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840 31.6.1 MCU device ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862 31.6.2 Boundary scan TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862 31.6.3 Cortex-M4 with FPU TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862 31.6.4 Cortex-M4 with FPU JEDEC-106 ID code . . . . . . . . . . . . . . . . . . . . . . 863 JTAG debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863 DocID022448 Rev 2 RM0313 Contents 31.8 31.9 SW debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865 31.8.1 SW protocol introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865 31.8.2 SW protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865 31.8.3 SW-DP state machine (reset, idle states, ID code) . . . . . . . . . . . . . . . 866 31.8.4 DP and AP read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866 31.8.5 SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867 31.8.6 SW-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867 AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868 31.10 Core debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869 31.11 Capability of the debugger host to connect under system reset . . . . . . 869 31.12 FPB (Flash patch breakpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870 31.13 DWT (data watchpoint trigger) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870 31.14 ITM (instrumentation trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . . 870 31.14.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870 31.14.2 Time stamp packets, synchronization and overflow packets . . . . . . . . 871 31.15 ETM (Embedded trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872 31.15.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872 31.15.2 Signal protocol, packet types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873 31.15.3 Main ETM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873 31.15.4 Configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873 31.16 MCU debug component (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 874 31.16.1 Debug support for low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 874 31.16.2 Debug support for timers, watchdog, bxCAN and I2C . . . . . . . . . . . . . 874 31.16.3 Debug MCU configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874 31.16.4 Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . . . . . . . 877 31.16.5 Debug MCU APB2 freeze register (DBGMCU_APB2_FZ) . . . . . . . . . 879 31.17 TPIU (trace port interface unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879 31.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879 31.17.2 TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880 31.17.3 TPUI formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882 31.17.4 TPUI frame synchronization packets . . . . . . . . . . . . . . . . . . . . . . . . . . 882 31.17.5 Transmission of the synchronization frame packet . . . . . . . . . . . . . . . 882 31.17.6 Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883 31.17.7 Asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883 31.17.8 TRACECLKIN connection inside the STM32F37xx and STM32F38xx 883 DocID022448 Rev 2 25/897 26 Contents RM0313 31.17.9 TPIU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884 31.17.10 Example of configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885 31.18 DBG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885 32 Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887 32.1 33 Memory size data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889 33.1 34 26/897 Unique device ID register (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887 Flash size data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893 DocID022448 Rev 2 RM0313 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. STM32F37xx/STM32F38xx peripheral register boundary addresses. . . . . . . . . . . . . . . . . 41 Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Flash module organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Flash memory read protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Access status versus protection level and execution modes . . . . . . . . . . . . . . . . . . . . . . . 59 Flash interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Flash interface - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Option byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Option byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Description of the option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 CRC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Sleep-now . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Sleep-on-exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 PWR register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 SYSCFG register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Programmable data width & endian behavior (when bits PINC = MINC = 1) . . . . . . . . . . 168 DMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Summary of DMA1 requests for each channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Summary of DMA2 requests for each channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 List of vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Extended interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . 197 ADC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 External trigger for regular channels for ADC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 External trigger for injected channels for ADC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 ADC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 SDADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 DAC1/2 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 External triggers (DAC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 External triggers (DAC2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 External triggers (DAC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 DAC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 COMP register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 TIM2 to TIM5/TIM19 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 DocID022448 Rev 2 27/897 29 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 90. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. 28/897 RM0313 Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 TIM12 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 TIM13/14 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 Output control bits for complementary OCx and OCxN channels with break feature . . . . 452 TIM15 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 Output control bits for complementary OCx and OCxN channels with break feature . . . . 472 TIM16&TIM17 register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 TIM6/7/18 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 RTC pin PC13 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 LSE pin PC14 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 LSE pin PC15 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 Effect of low power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551 STM32F37xx/STM32F38xx I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 Comparison of analog vs. digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 I2C-SMBUS specification data setup and hold times . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 I2C Configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 I2C-SMBUS specification clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 Examples of timings settings for fI2CCLK = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 Examples of timings settings for fI2CCLK = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 Examples of timings settings for fI2CCLK = 48 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 SMBus timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 SMBUS with PEC configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 Examples of TIMEOUTA settings for various I2CCLK frequencies (max tTIMEOUT = 25 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591 Examples of TIMEOUTB settings for various I2CCLK frequencies . . . . . . . . . . . . . . . . . 592 Examples of TIMEOUTA settings for various I2CCLK frequencies (max tIDLE = 50 µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622 Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633 Error calculation for programmed baud rates at fCK = 72 MHz for oversampling by 16 and by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 Tolerance of the USART receiver when BRR[3:0] = 0000 . . . . . . . . . . . . . . . . . . . . . . . . 636 Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684 SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 Audio-frequency precision using standard 8 MHz HSE . . . . . . . . . . . . . . . . . . . . . . . . . . 721 Audio-frequency precision using standard 8 MHz HSE . . . . . . . . . . . . . . . . . . . . . . . . . . 722 I2S interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 Acquisition sequence summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 DocID022448 Rev 2 RM0313 Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. Table 134. Table 135. Table 136. Table 137. Table 138. Table 139. Table 140. Table 141. Table 142. Table 143. Table 144. Table 145. Table 146. Table 147. Table 148. List of tables Spread spectrum deviation versus AHB clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . 747 I/O state depending on its mode and IODEF bit value . . . . . . . . . . . . . . . . . . . . . . . . . . . 748 Capacitive sensing GPIOs available on STM32F37xx/STM32F38xx devices . . . . . . . . . 750 Effect of low power modes on TSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 TSC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 Transmit mailbox mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775 Receive mailbox mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775 bxCAN register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802 Double-buffering buffer flag definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815 Bulk double-buffering memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816 Isochronous memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817 Resume event detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819 Reception status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829 Endpoint type encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830 Endpoint kind meaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830 Transmission status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830 Definition of allocated buffer memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834 USB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834 HDMI pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837 Error handling timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843 TXERR timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844 HDMI-CEC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845 HDMI-CEC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859 JTAG debug port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863 32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . . . 864 Packet request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865 ACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866 DATA transfer (33 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866 SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867 Cortex-M4 with FPU AHB-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868 Core debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869 Main ITM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871 Main ETM registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873 Asynchronous TRACE pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880 Synchronous TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880 Flexible TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881 Important TPIU registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884 DBG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893 DocID022448 Rev 2 29/897 29 List of figures RM0313 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. 30/897 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Programming procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Flash memory Page Erase procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Flash memory Mass Erase procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 PVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Clock tree part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Clock tree part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 HSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Frequency measurement with TIM14 in capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Basic structure of an I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Basic structure of a five-volt tolerant I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 High impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 DMA1 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 DMA2 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 EXTI extended interrupt/event block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Extended interrupt/event GPIO mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Single ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Injected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Calibration timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Right alignment of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Left alignment of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Temperature sensor and VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . 208 SDADC clock block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Single SDADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Switch configuration in single-ended mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Switch configuration in differential mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Switch configuration in mixed mode (example 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Switch configuration in mixed mode (example 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Equivalent input circuit for input channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Equivalent input circuit for VREFSD input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 DAC1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 DAC2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Data registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Timing diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . . . 267 Data registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Data registers in dual DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 DAC LFSR register calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 DocID022448 Rev 2 RM0313 Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93. Figure 94. Figure 95. Figure 96. Figure 97. Figure 98. Figure 99. List of figures DAC conversion (SW trigger enabled) with LFSR wave generation. . . . . . . . . . . . . . . . . 275 DAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 DAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 276 Comparator 1 and 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 Comparator hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 299 Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 300 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 303 Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 303 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Counter timing diagram, Update event when repetition counter is not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 308 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 309 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 310 Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 310 Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 311 TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 315 Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 316 PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 Example of one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 327 Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 327 Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 331 Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 Gating timer y with OC1REF of timer x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 Gating timer y with Enable of timer x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 Triggering timer y with update of timer x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Triggering timer y with Enable of timer x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Triggering timer x and y with timer x TI1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 DocID022448 Rev 2 31/897 35 List of figures Figure 100. Figure 101. Figure 102. Figure 103. Figure 104. Figure 105. Figure 106. Figure 107. Figure 108. Figure 109. Figure 110. Figure 111. Figure 112. Figure 113. Figure 114. Figure 115. Figure 116. Figure 117. Figure 118. Figure 119. Figure 120. Figure 121. Figure 122. Figure 123. Figure 124. Figure 125. Figure 126. Figure 127. Figure 128. Figure 129. Figure 130. Figure 131. Figure 132. Figure 133. Figure 134. Figure 135. Figure 136. Figure 137. Figure 138. Figure 139. Figure 140. Figure 141. Figure 142. Figure 143. Figure 144. Figure 145. Figure 146. Figure 147. 32/897 RM0313 General-purpose timer block diagram (TIM12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 General-purpose timer block diagram (TIM13/14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 364 Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 365 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 370 TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 372 Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 373 PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 Example of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 TIM15 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 TIM16 and TIM17 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 413 Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 413 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 419 Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 420 TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 422 Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 423 Output stage of capture/compare channel (channel 2 for TIM15) . . . . . . . . . . . . . . . . . . 423 PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 430 Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 430 Output behavior in response to a break.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 DocID022448 Rev 2 RM0313 Figure 148. Figure 149. Figure 150. Figure 151. Figure 152. Figure 153. Figure 154. Figure 155. Figure 156. Figure 157. Figure 158. Figure 159. Figure 160. Figure 161. Figure 162. Figure 163. Figure 164. Figure 165. Figure 166. Figure 167. Figure 168. Figure 169. Figure 170. Figure 171. Figure 172. Figure 173. Figure 174. Figure 175. Figure 176. Figure 177. Figure 178. Figure 179. Figure 180. Figure 181. Figure 182. Figure 183. Figure 184. Figure 185. Figure 186. Figure 187. Figure 188. Figure 189. Figure 190. Figure 191. Figure 192. Figure 193. Figure 194. Figure 195. Figure 196. Figure 197. List of figures Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 IR internal hardware connections with TIM16 and TIM17. . . . . . . . . . . . . . . . . . . . . . . . . 480 Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 483 Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 483 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 488 Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 I2C initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562 Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563 Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 Slave initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=0. . . . . . . . . . . . . 569 Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=1. . . . . . . . . . . . . 569 Transfer bus diagrams for I2C slave transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 Transfer sequence flowchart for slave receiver with NOSTRETCH=0 . . . . . . . . . . . . . . . 571 Transfer sequence flowchart for slave receiver with NOSTRETCH=1 . . . . . . . . . . . . . . . 572 Transfer bus diagrams for I2C slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 Master clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 Master initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 10-bit address read access with HEAD10R=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 10-bit address read access with HEAD10R=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 Transfer sequence flowchart for I2C master transmitter for N<=255 bytes . . . . . . . . . . . 578 Transfer sequence flowchart for I2C master transmitter for N>255 bytes . . . . . . . . . . . . 579 Transfer bus diagrams for I2C master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 Transfer sequence flowchart for I2C master receiver for N<=255 bytes . . . . . . . . . . . . . 582 Transfer sequence flowchart for I2C master receiver for N >255 bytes . . . . . . . . . . . . . . 583 Transfer bus diagrams for I2C master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584 Timeout intervals for tLOW:SEXT, tLOW:MEXT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589 Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC. . . . . . . . . . . . 593 Transfer bus diagrams for SMBus slave transmitter (SBC=1) . . . . . . . . . . . . . . . . . . . . . 593 Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC . . . . . . . . . . . . . 595 Bus transfer diagrams for SMBus slave receiver (SBC=1) . . . . . . . . . . . . . . . . . . . . . . . 596 Bus transfer diagrams for SMBus master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 Bus transfer diagrams for SMBus master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 I2C interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 DocID022448 Rev 2 33/897 35 List of figures Figure 198. Figure 199. Figure 200. Figure 201. Figure 202. Figure 203. Figure 204. Figure 205. Figure 206. Figure 207. Figure 208. Figure 209. Figure 210. Figure 211. Figure 212. Figure 213. Figure 214. Figure 215. Figure 216. Figure 217. Figure 218. Figure 219. Figure 220. Figure 221. Figure 222. Figure 223. Figure 224. Figure 225. Figure 226. Figure 227. Figure 228. Figure 229. Figure 230. Figure 231. Figure 232. Figure 233. Figure 234. Figure 235. Figure 236. Figure 237. Figure 238. Figure 239. Figure 240. Figure 241. Figure 242. Figure 243. Figure 244. Figure 245. Figure 246. Figure 247. 34/897 RM0313 USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624 Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626 TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628 Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629 Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640 Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . . 643 Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . . 644 USART example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645 USART data clock timing diagram (M=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645 USART data clock timing diagram (M=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646 RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646 ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647 Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 IrDA SIR ENDEC- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 IrDA data modulation (3/16) -Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 USART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660 SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 Full-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688 Half-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689 Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690 Master and three independent slaves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691 Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692 Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694 Data alignment when data length is not equal to 8-bit or 16-bit . . . . . . . . . . . . . . . . . . . . 695 Packing data in FIFO for transmission and reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699 Master full duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702 Slave full duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 Master full duplex communication with CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704 Master full duplex communication in packed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 NSSP pulse generation in Motorola SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 TI mode transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709 I2S block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 I2S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0). . . . . . . . . . . . . . . . . 714 I2S Philips standard waveforms (24-bit frame with CPOL = 0) . . . . . . . . . . . . . . . . . . . . . 714 Transmitting 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715 Receiving 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715 I2S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715 Example of 16-bit data frame extended to 32-bit channel frame . . . . . . . . . . . . . . . . . . . 715 MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . . . . . . . . . . . . . . . 716 MSB justified 24-bit frame length with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716 MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . . 716 DocID022448 Rev 2 RM0313 List of figures Figure 248. Figure 249. Figure 250. Figure 251. Figure 252. Figure 253. Figure 254. Figure 255. Figure 256. Figure 257. Figure 258. Figure 259. Figure 260. Figure 261. Figure 262. Figure 263. Figure 264. Figure 265. Figure 266. Figure 267. Figure 268. Figure 269. Figure 270. Figure 271. Figure 272. Figure 273. Figure 274. Figure 275. Figure 276. Figure 277. Figure 278. Figure 279. Figure 280. Figure 281. Figure 282. Figure 283. Figure 284. Figure 285. Figure 286. Figure 287. Figure 288. Figure 289. Figure 290. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . 717 LSB justified 24-bit frame length with CPOL = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717 Operations required to transmit 0x3478AE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717 Operations required to receive 0x3478AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . . 718 Example of 16-bit data frame extended to 32-bit channel frame . . . . . . . . . . . . . . . . . . . 718 PCM standard waveforms (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719 PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . . . . . . . . . . . . . . 719 Audio sampling frequency definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 I2S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 TSC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 Surface charge transfer analog I/O group structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 Sampling capacitor voltage variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 Charge transfer acquisition sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746 Spread spectrum variation principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 CAN network topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 bxCAN operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 bxCAN in silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 bxCAN in loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 bxCAN in combined mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767 Transmit mailbox states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768 Receive FIFO states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769 Filter bank scale configuration - register organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 772 Example of filter numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773 Filtering mechanism - example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 CAN error state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 CAN frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778 Event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779 Can mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791 USB peripheral block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807 Packet buffer areas with examples of buffer description table locations . . . . . . . . . . . . . 811 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837 Message structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838 Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838 Bit timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839 Signal free time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839 Arbitration phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840 SFT of three nominal bit periods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840 Error bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841 Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842 TXERR detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844 Block diagram of STM32F37xx/STM32F38xx MCU and Cortex-M4 with FPU-level debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856 Figure 291. SWJ debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857 Figure 292. JTAG TAP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861 Figure 293. TPIU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880 DocID022448 Rev 2 35/897 35 Documentation conventions RM0313 1 Documentation conventions 1.1 List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) Software can read and write to these bits. read-only (r) Software can only read these bits. write-only (w) Software can only write to this bit. Reading the bit returns the reset value. read/clear (rc_w1) Software can read as well as clear this bit by writing 1. Writing ‘0’ has no effect on the bit value. read/clear (rc_w0) Software can read as well as clear this bit by writing 0. Writing ‘1’ has no effect on the bit value. read/clear by read (rc_r) Software can read this bit. Reading this bit automatically clears it to ‘0’. Writing ‘0’ has no effect on the bit value. read/set (rs) Software can read as well as set this bit. Writing ‘0’ has no effect on the bit value. Reserved (Res.) Reserved bit, must be kept at reset value. 1.2 Glossary This section gives a brief definition of acronyms and abbreviations used in this document: 1.3 • The Cortex-M4 with FPU core integrates one debug port: SWD debug port (SWD-DP) provides a 2-pin (clock and data) interface based on the Serial Wire Debug (SWD) protocol. Please refer to the Cortex-M4 with FPU technical reference manual. • Word: data of 32-bit length. • Half-word: data of 16-bit length. • Byte: data of 8-bit length. • IAP (in-application programming): IAP is the ability to re-program the Flash memory of a microcontroller while the user program is running. • ICP (in-circuit programming): ICP is the ability to program the Flash memory of a microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the device is mounted on the user application board. • Option bytes: product configuration bits stored in the Flash memory. • OBL: option byte loader. • AHB: advanced high-performance bus. Peripheral availability For peripheral availability and number across all sales types, please refer to the particular device datasheet. 36/897 DocID022448 Rev 2 RM0313 System architecture and memory overview 2 System architecture and memory overview 2.1 System architecture The main system consists of: • • Five masters: – Cortex-M4 with FPU core I-bus – Cortex-M4 with FPU core D-bus – Cortex-M4 with FPU core S-bus – GP-DMA1 and GP-DMA2 (general-purpose DMAs) Five slaves: – Internal SRAM – Internal Flash memory (ICODE and DCODE) – AHB to APBx (APB1 or APB2), which connect all the APB peripherals – AHB dedicated to GPIO ports These are interconnected using a multilayer AHB bus architecture as shown in Figure 1: Figure 1. System architecture 3BUS $-! $-! $-! $-! 3 3 $BUS 3 !2#ORTEX- 3 )BUS 3 "USMATRIX3 BIT+" &LASHMEMORY &,)4& - - - - )#/$% $#/$% - !("DEDICATEDTO'0)/PORTS 2##43##2#AND !("TO!0"AND!0" +"32!-36 2.1.1 S0: I-bus This bus connects the Instruction bus of the Cortex-M4 with FPU core to the BusMatrix. This bus is used by the core to fetch instructions. The target of this bus is a memory area (Flash and SRAM) containing the code. DocID022448 Rev 2 37/897 38 System architecture and memory overview 2.1.2 RM0313 S1: D-bus This bus connects the Data bus of the Cortex-M4 with FPU core to the BusMatrix. This bus is used by the core for literal load and debug access. The target of this bus is a memory area (Flash and SRAM) containing the code or data. 2.1.3 S2: S-bus This bus connects the system bus of the Cortex-M4 with FPU core to the BusMatrix. This bus is used to access data located in peripheral or SRAM area. Instructions can also be fetched on this bus even if it less efficient than the ICode bus. The targets of this bus are the 32-Kbyte SRAM, the AHB2APB bridges, the AHB I/O port. 2.1.4 S3, S4: DMA-bus This bus connects the AHB master interface of the DMAs to the BusMatrix which manages the access of different Masters to Flash memory, SRAM and AHB peripherals. 2.1.5 BusMatrix-S (5M5S) The BusMatrix manages the access arbitration between Masters (core system bus, GPDMAs). The arbitration scheme uses a Round Robin algorithm. The BusMatrix is composed of 5 slaves (FLASH ITF, SRAM, AHB2APB bridges and AHB I/O ports) and 5 masters (CPU System, DCODE and ICODE buses, DMA1 and DMA2 bus). The following subsections describe all the peripherals connected to the AHB subsystem. AHB/APB bridges The two AHB/APB bridges provide full synchronous connections between the AHB and the 2 APB buses. APB1 is limited to 36 MHz, APB2 operates at full speed(72 MHz). Refer to Section 2.2.2: Memory map and register boundary addresses on page 41 for the address mapping of the peripherals connected to this bridge. After each device reset, all peripheral clocks are disabled (except for the SRAM and FLITF). Before using a peripheral you have to enable its clock in the RCC_AHBENR, RCC_APB2ENR or RCC_APB1ENR register. Note: 38/897 When a 16- or 8-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector. DocID022448 Rev 2 RM0313 2.2 Memory organization 2.2.1 Introduction Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant. The addressable memory space is divided into 8 main blocks, each of 512 MB. DocID022448 Rev 2 39/897 44 RM0313 Figure 2. Memory map [)))))))) [)) $+% [ [( [( &RUWH[ 0,QWHUQDO 3HULSKHUDOV UHVHUYHG [& [)) ")# [ UHVHUYHG [$ [ [))))))) "1# 2SWLRQE\WHV [ [ 6\VWHPPHPRU\ UHVHUYHG [ "1# [ [ UHVHUYHG [ 3HULSKHUDOV )ODVKPHPRU\ [ 65$0 Y UHVHUYHG &2'( 'MBTITZTUFNNFNPSZ PS43".EFQFOEJOHPO #005DPOGJHVSBUJPO [ [ 5HVHUYHG 069 40/897 DocID022448 Rev 2 RM0313 All the memory areas that are not allocated to on-chip memories and peripherals are considered “Reserved”). For the detailed mapping of available memory and register areas, please refer to the Memory map and register boundary addresses chapter and peripheral chapters. 2.2.2 Memory map and register boundary addresses See the datasheet corresponding to your device for a comprehensive diagram of the memory map. The following table gives the boundary addresses of the peripherals available in the devices. Table 1. STM32F37xx/STM32F38xx peripheral register boundary addresses Bus AHB2 AHB Boundary address Size Peripheral Peripheral register map 0xE000 0000 - 0xE010 0000 1MB Cortex-M4 with FPU internal peripherals 0x4800 1800 - 0x5FFF FFFF ~384 MB Reserved 0x4800 1400 - 0x4800 17FF 1KB GPIOF Section 8.4.11 on page 154 0x4800 1000 - 0x4800 13FF 1KB GPIOE Section 8.4.11 on page 154 0x4800 0C00 - 0x4800 0FFF 1KB GPIOD Section 8.4.11 on page 154 0x4800 0800 - 0x4800 0BFF 1KB GPIOC Section 8.4.11 on page 154 0x4800 0400 - 0x4800 07FF 1KB GPIOB Section 8.4.11 on page 154 0x4800 0000 - 0x4800 03FF 1KB GPIOA Section 8.4.11 on page 154 0x4002 4400 - 0x47FF FFFF ~128 MB Reserved 0x4002 4000 - 0x4002 43FF 1 KB TSC 0x4002 3400 - 0x4002 3FFF 3 KB Reserved 0x4002 3000 - 0x4002 33FF 1 KB CRC 0x4002 2400 - 0x4002 2FFF 3 KB Reserved 0x4002 2000 - 0x4002 23FF 1 KB FLASH memory interface 0x4002 1400 - 0x4002 1FFF 3 KB Reserved 0x4002 1000 - 0x4002 13FF 1 KB RCC 0x4002 0800- 0x4002 0FFF 2 KB Reserved 0x4002 0400 - 0x4002 07FF 1 KB DMA2 Section 10.5.7 on page 182 0x4002 0000 - 0x4002 03FF 1 KB DMA1 Section 10.5.7 on page 182 0x4001 6C00 - 0x4001 FFFF 37 KB Reserved DocID022448 Rev 2 Section 27.6.11 on page 759 Section 5.5.6 on page 76 Section 3.6 on page 66 Section 7.4.14 on page 137 41/897 44 RM0313 Table 1. STM32F37xx/STM32F38xx peripheral register boundary addresses (continued) Bus Boundary address Size Peripheral Peripheral register map 0x4001 6800 - 0x4001 6BFF 1 KB SDADC3 Section 13.6.18 on page 261 0x4001 6400 - 0x4001 67FF 1 KB SDADC2 Section 13.6.18 on page 261 0x4001 6000 - 0x4001 63FF 1 KB SDADC1 Section 13.6.18 on page 261 0x4001 5C00 - 0x4001 5FFF 1 KB TIM19 Section 16.4.20 on page 357 0x4001 5800 - 0x4001 5BFF 1 KB DBGMCU Section 31.18: DBG register map on page 885 0x4001 4C00 - 0x4001 57FF 4 KB Reserved 0x4001 4800 - 0x4001 4BFF 1 KB TIM17 Section 18.6.16 on page 478 0x4001 4400 - 0x4001 47FF 1 KB TIM16 Section 18.6.16 on page 478 APB2 0x4001 4000 - 0x4001 43FF 1 KB TIM15 Section 18.5.18 on page 459 0x4001 3C00 - 0x4001 3FFF 1 KB Reserved 0x4001 3800 - 0x4001 3BFF 1 KB USART1 0x4001 3400 - 0x4001 37FF 1 KB Reserved 0x4001 3000 - 0x4001 33FF 1 KB SPI1/I2S1 0x4001 2800 - 0x4001 2FFF 1 KB Reserved 0x4001 2400 - 0x4001 27FF 1 KB ADC 0x4001 0800 - 0x4001 23FF 7 KB Reserved 0x4001 0400 - 0x4001 07FF 1 KB EXTI Section 11.3.7 on page 197 0x4001 0000 - 0x4001 03FF 1 KB SYSCFG Section 9.1.7 on page 163 0x4000 A000 - 0x4000 FFFF 32 KB Reserved 42/897 DocID022448 Rev 2 Section 25.7.12 on page 684 Section 26.7.10 on page 741 Section 12.12.15 on page 223 RM0313 Table 1. STM32F37xx/STM32F38xx peripheral register boundary addresses (continued) Bus Boundary address Size Peripheral 0x4000 9C00 - 0x4000 9FFF 1 KB TIM18 Section 20.4.9 on page 493 0x4000 9800 - 0x4000 9BFF 1 KB DAC2 Section 14.8.15 on page 287 0x4000 8000 - 0x4000 97FF 8 KB Reserved 0x4000 7C00 - 0x4000 7FFF 1 KB COMP Section 15.5.2 on page 296 0x4000 7800 - 0x4000 7BFF 1 KB CEC Section 30.7.7 on page 854 0x4000 7400 - 0x4000 77FF 1 KB DAC1 Section 14.8.15 on page 287 0x4000 7000 - 0x4000 73FF 1 KB PWR Section 6.4.3 on page 95 0x4000 6800 - 0x4000 6FFF 2 KB Reserved 0x4000 6400 - 0x4000 67FF 1 KB CAN 0x4000 6200 - 0x4000 63FF 1 KB Reserved 0x4000 6000 - 0x4000 61FF 0.5 KB APB1 APB1 Peripheral register map Section 28.9.5 on page 802 USB packet (stored in SRAM) Section 29.5.4 on page 834 0x4000 5C00 - 0x4000 5FFF 1 KB USB FS Section 29.5.4 on page 834 0x4000 5800 - 0x4000 5BFF 1 KB I2C2 Section 24.7 on page 604 0x4000 5400 - 0x4000 57FF 1 KB I2C1 Section 24.7 on page 604 0x4000 4C00 - 0x4000 53FF 2 KB Reserved 0x4000 4800 - 0x4000 4BFF 1 KB USART3 Section 25.7.12 on page 684 0x4000 4400 - 0x4000 47FF 1 KB USART2 Section 25.7.12 on page 684 0x4000 4000 - 0x4000 43FF 1 KB Reserved 0x4000 3C00 - 0x4000 3FFF 1 KB SPI3/I2S3 Section 26.7.10 on page 741 0x4000 3800 - 0x4000 3BFF 1 KB SPI2/I2S2 Section 26.7.10 on page 741 0x4000 3400 - 0x4000 37FF 1 KB Reserved 0x4000 3000 - 0x4000 33FF 1 KB IWDG Section 21.4.6 on page 501 0x4000 2C00 - 0x4000 2FFF 1 KB WWDG Section 22.6.4 on page 507 0x4000 2800 - 0x4000 2BFF 1 KB RTC Section 23.6.20 on page 551 0x4000 2400 - 0x4000 27FF 1 KB Reserved 0x4000 2000 - 0x4000 23FF 1 KB TIM14 Section 18.4.12 on page 438 0x4000 1C00 - 0x4000 1FFF 1 KB TIM13 Section 18.4.12 on page 438 0x4000 1800 - 0x4000 1BFF 1 KB TIM12 Section 18.4.12 on page 438 0x4000 1400 - 0x4000 17FF 1 KB TIM7 Section 18.4.12 on page 438 0x4000 1000 - 0x4000 13FF 1 KB TIM6 Section 20.4.9 on page 525 0x4000 0C00 - 0x4000 0FFF 1 KB TIM5 Section 20.4.9 on page 525 0x4000 0800 - 0x4000 0BFF 1 KB TIM4 Section 20.4.9 on page 525 0x4000 0400 - 0x4000 07FF 1 KB TIM3 Section 20.4.9 on page 525 0x4000 0000 - 0x4000 03FF 1 KB TIM2 Section 20.4.9 on page 525 0x2000 8000 - 3FFF FFFF ~512 MB Reserved DocID022448 Rev 2 43/897 44 RM0313 Table 1. STM32F37xx/STM32F38xx peripheral register boundary addresses (continued) Bus Boundary address 0x2000 0000 - 0x2000 7FFF 44/897 Size Peripheral 32 KB SRAM 0x1FFF FC00 - 0x1FFF FFFF 1 KB Reserved 0x1FFF F800 - 0x1FFF FBFF 1 KB Option bytes 0x1FFF D800 - 0x1FFF F7FF 8 KB System memory 0x0801 0000 - 0x1FFF EBFF ~384 MB Reserved 0x0800 0000 - 0x0803 FFFF 256 KB Main Flash memory 0x0001 0000 - 0x07FF FFFF 128 MB Reserved 0x0000 000 - 0x0000 FFFF 64 KB Main Flash memory, system memory or SRAM depending on BOOT configuration DocID022448 Rev 2 Peripheral register map RM0313 2.3 Embedded SRAM The STM32F37xx/STM32F38xx features 32 Kbytes of static SRAM. It can be accessed as bytes, half-words (16 bits) or full words (32 bits). This memory can be addressed at maximum system clock frequency without wait state and thus by both CPU and DMA. 2.3.1 Parity check The data bus width is 36 bits because 4 bits are available for parity check (1 bit per byte) in order to increase memory robustness, as required for instance by Class B or SIL norms. The parity bits are computed and stored when writing into the SRAM. Then, they are automatically checked when reading. If one bit fails, an NMI is generated. The same error can also be linked to the BRK_IN Break input of TIMER1, with the SRAM_PARITY_LOCK control bit in the SYSCFG configuration register 2 (SYSCFG_CFGR2). The SRAM Parity Error flag (SRAM_PEF) is available in the SYSCFG configuration register 2 (SYSCFG_CFGR2). 2.4 Bit banding The Cortex-M4 memory map includes two bit-band regions. These regions map each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a word in the alias region has the same effect as a read-modify-write operation on the targeted bit in the bit-band region. In the STM32F37xx/STM32F38xx both peripheral registers and SRAM are mapped in a bitband region. This allows single bit-band write and read operations to be performed. The operations are only available for Cortex-M4 accesses, not from other bus masters (e.g. DMA). A mapping formula shows how to reference each word in the alias region to a corresponding bit in the bit-band region. The mapping formula is: bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4) where: bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit. bit_band_base is the starting address of the alias region byte_offset is the number of the byte in the bit-band region that contains the targeted bit bit_number is the bit position (0-7) of the targeted bit. Example: The following example shows how to map bit 2 of the byte located at SRAM address 0x20000300 in the alias region: 0x22006008 = 0x22000000 + (0x300*32) + (2*4). Writing to address 0x22006008 has the same effect as a read-modify-write operation on bit 2 of the byte at SRAM address 0x20000300. Reading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the byte at SRAM address 0x20000300 (0x01: bit set; 0x00: bit reset). DocID022448 Rev 2 45/897 70 RM0313 For more information on Bit-Banding, please refer to the Cortex-M4 Technical Reference Manual. 2.5 Flash memory overview The Flash memory is composed of two distinct physical areas: • The main Flash memory block. It contains the application program and user data if necessary. • The information block. It is composed of two parts: – Option bytes for hardware and memory protection user configuration. – System memory which contains the proprietary bootloader code. Please, refer to Section 3: Embedded Flash memory for more details. Flash memory instructions and data access are performed through the AHB bus. The prefetch block is used for instruction fetches through the ICode bus. Arbitration is performed in the Flash memory interface, and priority is given to data access on the DCode bus. It also implements the logic necessary to carry out the Flash memory operations (Program/Erase) controlled through the Flash registers. 2.6 Boot configuration In the STM32F37xx/STM32F38xx, three different boot modes can be selected through the BOOT0 pin and nBOOT1 bit in the User option byte, as shown in the following table: Table 2. Boot modes Boot mode selection Boot mode Aliasing BOOT1 (inverted nBOOT1) BOOT0 x 0 Main Flash memory Main flash memory is selected as boot space 0 1 System memory System memory is selected as boot space 1 1 Embedded SRAM Embedded SRAM (on the DCode bus) is selected as boot space The values on both BOOT0 pin and nBOOT1 option bit are latched on the 4th rising edge of SYSCLK after a reset. It is up to the user to set the nBOOT1 and BOOT0 to select the required boot mode. The BOOT0 pin and nBOOT1 option bit are also resampled when exiting from Standby mode. Consequently they must be kept in the required Boot mode configuration in Standby mode. After this startup delay has elapsed, the CPU fetches the top-of-stack value from address 0x0000 0000, then starts code execution from the boot memory at 0x0000 0004. Depending on the selected boot mode, main Flash memory, system memory or SRAM is accessible as follows: • 46/897 Boot from main Flash memory: the main Flash memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space (0x0800 DocID022448 Rev 2 RM0313 0000). In other words, the Flash memory contents can be accessed starting from address 0x0000 0000 or 0x0800 0000. • Boot from system memory: the system memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space (0x1FFF D800). • Boot from the embedded SRAM: the SRAM is aliased in the boot memory space (0x0000 0000), but it is still accessible from its original memory space (0x2000 0000). Embedded bootloader The embedded bootloader is located in the System memory, programmed by ST during production. It is used to reprogram the Flash memory through USART1 or USART2 or USB (DFU: device firmware upgrade). DocID022448 Rev 2 47/897 70 Embedded Flash memory RM0313 3 Embedded Flash memory 3.1 Flash main features • Up to 256 Kbytes of Flash memory • Memory organization: – Main memory block: 32 Kbits × 64 bits – Information block: 1280 × 64 bits Flash memory interface (FLITF) features: • Read interface with prefetch buffer (2 × 64-bit words) • Option byte loader • Flash program/Erase operation • Read/Write protection • Low power mode 3.2 Flash memory functional description 3.2.1 Flash memory organization The Flash memory is organized as 64-bit wide memory cells that can be used for storing both code and data constants. The memory organization is based on a main memory block containing 128 pages of 2 Kbyte and an information block as shown in Table 3. Table 3. Flash module organization Flash area Main memory 48/897 Flash memory addresses Size (bytes) Name 0x0800 0000 - 0x0800 07FF 2K Page 0 0x0800 0800 - 0x0800 0FFF 2K Page 1 0x0800 1000 - 0x0800 17FF 2K Page 2 0x0800 1800 - 0x0800 1FFF 2K Page 3 . . . . . . . . . . . . . . . .. . . . . . . . . . 0x0803 F800 - 0x0803 FFFF 2K Page 127 DocID022448 Rev 2 RM0313 Embedded Flash memory Table 3. Flash module organization (continued) Flash area Information block Flash memory interface registers Flash memory addresses Size (bytes) Name 0x1FFF D800 - 0x1FFF F7FF 8K System memory 0x1FFF F800 - 0x1FFF F80F 16 Option bytes 0x4002 2000 - 0x4002 2003 4 FLASH_ACR 0x4002 2004 - 0x4002 2007 4 FLASH_KEYR 0x4002 2008 - 0x4002 200B 4 FLASH_OPTKEYR 0x4002 200C - 0x4002 200F 4 FLASH_SR 0x4002 2010 - 0x4002 2013 4 FLASH_CR 0x4002 2014 - 0x4002 2017 4 FLASH_AR 0x4002 2018 - 0x4002 201B 4 Reserved 0x4002 201C - 0x4002 201F 4 FLASH_OBR 0x4002 2020 - 0x4002 2023 4 FLASH_WRPR The information block is divided into two parts: 3.2.2 • System memory is used to boot the device in System memory boot mode. The area is reserved for use by STMicroelectronics and contains the bootloader which is used to reprogram the Flash memory through one of the following interfaces: USART1, USART2 or USB (DFU). It is programmed by ST when the device is manufactured, and protected against spurious write/erase operations. For further details, please refer to the AN2606. • Option bytes Read operations The embedded Flash module can be addressed directly, as a common memory space. Any data read operation accesses the content of the Flash module through dedicated read senses and provides the requested data. The read interface consists of a read controller on one side to access the Flash memory and an AHB interface on the other side to interface with the CPU. The main task of the read interface is to generate the control signals to read from the Flash memory and to prefetch the blocks required by the CPU. The prefetch block is only used for instruction fetches over the ICode bus. The Literal pool is accessed over the DCode bus. Since these two buses have the same Flash memory as target, DCode bus accesses have priority over prefetch accesses. Read accesses can be performed with the following options managed through the Flash access control register (FLASH_ACR): • Instruction fetch: Prefetch buffer enabled for a faster CPU execution. • Latency: number of wait states for a correct read operation (from 0 to 2) DocID022448 Rev 2 49/897 70 Embedded Flash memory RM0313 Instruction fetch The Cortex-M4 with FPU fetches the instruction over the ICode bus and the literal pool (constant/data) over the DCode bus. The prefetch block aims at increasing the efficiency of ICode bus accesses. Prefetch buffer The prefetch controller decides to access the Flash memory depending on the available space in the prefetch buffer. The controller initiates a read request when there is at least one block free in the prefetch buffer. After reset, the state of the prefetch buffer is on. The prefetch buffer is usually switched on/off during the initialization routine, while the microcontroller is running on the internal 8 MHz RC (HSI) oscillator. Prefetch controller The prefetch controller decides to access the Flash memory depending on the available space in the prefetch buffer. The Controller initiates a read request when there is at least one block free in the prefetch buffer. After reset, the state of the prefetch buffer is on. The prefetch buffer should be switched on/off only when SYSCLK is lower than 24 MHz and no prescaler is applied on the AHB clock (SYSCLK must be equal to HCLK). The prefetch buffer is usually switched on/off during the initialization routine, while the microcontroller is running on the internal 8 MHz RC (HSI) oscillator. Note: The prefetch buffer must be kept on (FLASH_ACR[4]=’1’) when using a prescaler different from 1 on the AHB clock. Access latency In order to maintain the control signals to read the Flash memory, the ratio of the prefetch controller clock period to the access time of the Flash memory has to be programmed in the Flash access control register with the LATENCY[2:0] bits. This value gives the number of cycles needed to maintain the control signals of the Flash memory and correctly read the required data. After reset, the value is zero and only one cycle without additional wait states is required to access the Flash memory. DCode interface The DCode interface consists of a simple AHB interface on the CPU side and a request generator to the Arbiter of the Flash access controller. The DCode accesses have priority over prefetch accesses. This interface uses the Access Time Tuner block of the prefetch buffer. Flash Access controller Mainly, this block is a simple arbiter between the read requests of the prefetch/ICode and DCode interfaces. DCode interface requests have priority over other requests. 50/897 DocID022448 Rev 2 RM0313 3.2.3 Embedded Flash memory Flash program and erase operations The STM32F37xx/STM32F38xx embedded Flash memory can be programmed using incircuit programming or in-application programming. The in-circuit programming (ICP) method is used to update the entire contents of the Flash memory, using the JTAG, SWD protocol or the bootloader to load the user application into the microcontroller. ICP offers quick and efficient design iterations and eliminates unnecessary package handling or socketing of devices. In contrast to the ICP method, in-application programming (IAP) can use any communication interface supported by the microcontroller (I/Os, USB, CAN, UART, I2C, SPI, etc.) to download programming data into memory. IAP allows the user to re-program the Flash memory while the application is running. Nevertheless, part of the application has to have been previously programmed in the Flash memory using ICP. The program and erase operations are managed through the following seven Flash registers: • Key register (FLASH_KEYR) • Option byte key register (FLASH_OPTKEYR) • Flash control register (FLASH_CR) • Flash status register (FLASH_SR) • Flash address register (FLASH_AR) • Option byte register (FLASH_OBR) • Write protection register (FLASH_WRPR) An on going Flash memory operation will not block the CPU as long as the CPU does not access the Flash memory. On the contrary, during a program/erase operation to the Flash memory, any attempt to read the Flash memory will stall the bus. The read operation will proceed correctly once the program/erase operation has completed. This means that code or data fetches cannot be made while a program/erase operation is ongoing. For program and erase operations on the Flash memory (write/erase), the internal RC oscillator (HSI) must be ON. Unlocking the Flash memory After reset, the FPEC (Flash memory program/erase controller) is protected against unwanted write or erase operations. The FLASH_CR register is not accessible in write mode, except for the OBL_LAUNCH bit, used to reload the OBL. An unlocking sequence should be written to the FLASH_KEYR register to open the access to the FLASH_CR register. This sequence consists of two write operations into FLASH_KEYR register: 1. Write KEY1 = 0x45670123 2. Write KEY2 = 0xCDEF89AB Any wrong sequence locks up the FPEC and the FLASH_CR register until the next reset. In the case of a wrong key sequence, a bus error is detected and a Hard Fault interrupt is generated. This is done after the first write cycle if KEY1 does not match, or during the second write cycle if KEY1 has been correctly written but KEY2 does not match. DocID022448 Rev 2 51/897 70 Embedded Flash memory RM0313 The FPEC and the FLASH_CR register can be locked again by user software by writing the LOCK bit in the FLASH_CR register to 1. Main Flash memory programming The main Flash memory can be programmed 16 bits at a time. The program operation is started when the CPU writes a half-word into a main Flash memory address with the PG bit of the FLASH_CR register set. Any attempt to write data that are not half-word long will result in a bus error generating a Hard Fault interrupt. Figure 3. Programming procedure Read FLASH_CR_LOCK Yes FLASH_CR_LOCK =1 Perform unlock sequency No Write FLASH_CR_PG to 1 Perform half-word write at the desired address FLASH_SR_BSY =1 Yes No Check the programmed value by reading the programmed address ai14307b The Flash memory interface preliminarily reads the value at the addressed main Flash memory location and checks that it has been erased. If not, the program operation is skipped and a warning is issued by the PGERR bit in FLASH_SR register (the only exception to this is when 0x0000 is programmed. In this case, the location is correctly programmed to 0x0000 and the PGERR bit is not set). If the addressed main Flash memory location is write-protected by the FLASH_WRPR register, the program operation is skipped and a warning is issued by the WRPRTERR bit in the FLASH_SR register. The end of the program operation is indicated by the EOP bit in the FLASH_SR register. The main Flash memory programming sequence in standard mode is as follows: 52/897 DocID022448 Rev 2 RM0313 Note: Embedded Flash memory 1. Check that no main Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register. 2. Set the PG bit in the FLASH_CR register. 3. Perform the data write (half-word) at the desired address. 4. Wait until the BSY bit is reset in the FLASH_SR register. 5. Check the EOP flag in the FLASH_SR register (it is set when the programming operation has succeeded), and then clear it by software. The registers are not accessible in write mode when the BSY bit of the FLASH_SR register is set. Flash memory erase The Flash memory can be erased page by page or completely (Mass Erase). Page Erase To erase a page, the procedure below should be followed: Note: 1. Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_CR register. 2. Set the PER bit in the FLASH_CR register 3. Program the FLASH_AR register to select a page to erase 4. Set the STRT bit in the FLASH_CR register (see below note) 5. Wait for the BSY bit to be reset 6. Check the EOP flag in the FLASH_SR register (it is set when the erase operation has succeed), and then clear it by software. 7. Clear the EOP flag. The software should start checking if the BSY bit equals ‘0’ at least one CPU cycle after setting the STRT bit. DocID022448 Rev 2 53/897 70 Embedded Flash memory RM0313 Figure 4. Flash memory Page Erase procedure 2EAD&,!3(?#2?,/#+ 9ES &,!3(?#2?,/#+ 0ERFORMUNLOCKSEQUENCY .O 7RITE&,!3(?#2?0%2TO 7RITEINTO&!2ANADDRESS WITHINTHEPAGETOERASE 7RITE&,!3(?#2?3424TO &,!3(?32?"39 .O 9ES #HECK%/0FLAGIN&,!3(?32 ANDTHENCLEARITBYSOFTWARE AID Mass Erase The Mass Erase command can be used to completely erase the user pages of the Flash memory. The information block is unaffected by this procedure. The following sequence is recommended: Note: 54/897 1. Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register 2. Set the MER bit in the FLASH_CR register 3. Set the STRT bit in the FLASH_CR register (see below note) 4. Wait for the BSY bit to be reset 5. Check the EOP flag in the FLASH_SR register (it is set when the erase operation has succeed), and then clear it by software. 6. Clear the EOP flag. The software should start checking if the BSY bit equals ‘0’ at least one CPU cycle after setting the STRT bit. DocID022448 Rev 2 RM0313 Embedded Flash memory Figure 5. Flash memory Mass Erase procedure 2EAD&,!3(?#2?,/#+ &,!3(?#2?,/#+ 9ES 0ERFORMUNLOCKSEQUENCY .O 7RITEINTO&,!3(?#2?-%2 TO 7RITE&,!3(?#2?3424TO &,!3(?32?"39 .O 9ES #HECK%/0FLAGIN&,!3(?32 ANDTHENCLEARITBYSOFTWARE AIC Option byte programming The option bytes are programmed differently from normal user addresses. The number of option bytes is limited to 8 (4 for write protection, 1 for readout protection, 1 for hardware configuration, and 2 for data storage). After unlocking the FPEC, the user has to authorize the programming of the option bytes by writing the same set of KEYS (KEY1 and KEY2) to the FLASH_OPTKEYR register (refer to Unlocking the Flash memory for key values). Then, the OPTWRE bit in the FLASH_CR register will be set by hardware and the user has to set the OPTPG bit in the FLASH_CR register and perform a half-word write operation at the desired Flash address. The value of the addressed option byte is first read to check it is really erased. If not, the program operation is skipped and a warning is issued by the WRPRTERR bit in the FLASH_SR register. The end of the program operation is indicated by the EOP bit in the FLASH_SR register. The LSB value is automatically complemented into the MSB before the programming operation starts. This guarantees that the option byte and its complement are always correct. The sequence is as follows: DocID022448 Rev 2 55/897 70 Embedded Flash memory RM0313 1. Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register. 2. Unlock the OPTWRE bit in the FLASH_CR register. 3. Set the OPTPG bit in the FLASH_CR register 4. Write the data (half-word) to the desired address 5. Wait for the BSY bit to be reset. 6. Read the programmed value and verify. When the Flash memory read protection option is changed from protected to unprotected, a Mass Erase of the main Flash memory is performed before reprogramming the read protection option. If the user wants to change an option other than the read protection option, then the mass erase is not performed. The erased state of the read protection option byte protects the Flash memory. Erase procedure The option byte erase sequence (OPTERASE) is as follows: 56/897 1. Check that no Flash memory operation is ongoing by reading the BSY bit in the FLASH_SR register 2. Unlock the OPTWRE bit in the FLASH_CR register 3. Set the OPTER bit in the FLASH_CR register 4. Set the STRT bit in the FLASH_CR register and wait a few cycles before the BSY bit is set 5. Wait for BSY to reset 6. Read the erased option bytes and verify DocID022448 Rev 2 RM0313 3.3 Embedded Flash memory Memory protection The user area of the Flash memory can be protected against read by untrusted code. The pages of the Flash memory can also be protected against unwanted write due to loss of program counter contexts. The write-protection granularity is one sector (four pages). 3.3.1 Read protection The read protection is activated by setting the RDP option byte and then, by applying a system reset to reload the new RDP option byte. Note: If the read protection is set while the debugger is still connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset. There are three levels of read protection from no protection (level 0) to maximum protection or no debug (level 2). The Flash memory is protected when the RDP option byte and its complement contain the pair of values shown in Table 4. Table 4. Flash memory read protection status RDP byte value RDP complement value Read protection level 0xAA 0x55 Level 0 (ST production configuration) Any value except 0xAA or 0xCC Any value (not necessarily complementary) except 0x55 and 0x33 Level 1 0xCC 0x33 Level 2 The System memory area is read accessible whatever the protection level. It is never accessible for program/erase operation Level 0: no protection Read, program and erase operations into the main memory Flash area are possible. The option bytes are also accessible by all operations. DocID022448 Rev 2 57/897 70 Embedded Flash memory RM0313 Level 1: Read protection This is the default protection level when RDP option byte is erased. It is defined as well when RDP value is at any value different from 0xAA and 0xCC, or even if the complement is not correct. • User mode: Code executing in user mode can access main memory Flash and option bytes with all operations. • Debug, boot RAM and bootloader modes: In debug mode or when code is running from boot RAM or bootloader, the main Flash memory and the backup registers (RTC_BKPxR in the RTC) are totally inaccessible. In these modes, even a simple read access generates a bus error and a Hard Fault interrupt. The main memory is program/erase protected to prevent malicious or unauthorized users from reprogramming any of the user code with a dump routine. Any attempted program/erase operation sets the PGERR flag of Flash status register (FLASH_SR). When the RDP is reprogrammed to the value 0xAA to move back to Level 0, a mass erase of main memory Flash is performed and the backup registers (RTC_BKPxR in the RTC) are reset. Level 2: No debug In this level, the protection level 1 is guaranteed. In addition, the Cortex-M4 with FPU debug capabilities are disabled. Consequently, the debug port, the boot from RAM (boot RAM mode) and the boot from System memory (bootloader mode) are no more available. In user execution mode, all operations are allowed on the Main Flash memory. On the contrary, only read and program operations can be performed on the option bytes. Option bytes cannot be erases. Moreover, the RDP bytes cannot be programmed. Thus, the level 2 cannot be removed at all: it is an irreversible operation. When attempting to program the RDP byte, the protection error flag WRPRTERR is set in the Flash_SR register and an interrupt can be generated. Note: The debug feature is also disabled under reset. STMicroelectronics is not able to perform analysis on defective parts on which the level 2 protection has been set. 58/897 DocID022448 Rev 2 RM0313 Embedded Flash memory Table 5. Access status versus protection level and execution modes Area Main Flash memory System memory (2) Option bytes Backup registers Read protection level (RDP) Debug/ BootFromRam/ BootFromLoader User execution Read Write Erase Read Write Erase 1 Yes Yes Yes No No No(3) 2 Yes Yes Yes N/A(1) N/A(1) N/A(1) 1 Yes No No Yes No No 2 Yes No No NA(1) N/A(1) N/A(1) 1 Yes Yes(3) Yes No No Yes 2 Yes Yes(4) No 1 Yes Yes N/A 2 Yes Yes N/A N/A N/A(1) No No No(5) N/A(1) N/A(1) N/A(1) N/A (1) (1) 1. When the protection level 2 is active, the Debug port, the boot from RAM and the boot from system memory are disabled. 2. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode. 3. The main Flash memory is erased when the RDP option byte is programmed with all level protections disabled (0xAA). 4. All option bytes can be programmed, except the RDP byte. 5. The backup registers are erased only when RDP changes from level 1 to level 0. Changing read protection level It is easy to move from level 0 to level 1 by changing the value of the RDP byte to any value (except 0xCC). By programming the 0xCC value in the RDP byte, it is possible to go to level 2 either directly from level 0 or from level 1. On the contrary, the change to level 0 (no protection) is not possible without a main Flash memory Mass Erase operation. This Mass Erase is generated as soon as 0xAA is programmed in the RDP byte. Note: When the Mass Erase command is used, the backup registers (RTC_BKPxR in the RTC) are also reset. To validate the protection level change, the option bytes must be reloaded through the OBL_LAUNCH bit in Flash control register. 3.3.2 Write protection The write protection is implemented with a granularity of 2 pages. It is activated by configuring the WRP[1:0] option bytes, and then by reloading them by setting the OBL_LAUNCH bit in the FLASH_CR register. If a program or an erase operation is performed on a protected sector, the Flash memory returns a WRPRTERR protection error flag in the Flash memory Status Register (FLASH_SR). DocID022448 Rev 2 59/897 70 Embedded Flash memory RM0313 Write unprotection To disable the write protection, two application cases are provided: • • 3.3.3 Case 1: Read protection disabled after the write unprotection: – Erase the entire option byte area by using the OPTER bit in the Flash memory control register (FLASH_CR). – Program the code 0xAA in the RDP byte to unprotect the memory. This operation forces a Mass Erase of the main Flash memory. – Set the OBL_LAUNCH bit in the Flash control register (FLASH_CR) to reload the option bytes (and the new WRP[3:0] bytes), and to disable the write protection. Case 2: Read protection maintained active after the write unprotection, useful for inapplication programming with a user bootloader: – Erase the entire option byte area by using the OPTER bit in the Flash memory control register (FLASH_CR). – Set the OBL_LAUNCH bit in the Flash control register (FLASH_CR) to reload the option bytes (and the new WRP[3:0] bytes), and to disable the write protection. Option byte block write protection The option bytes are always read-accessible and write-protected by default. To gain write access (Program/Erase) to the option bytes, a sequence of keys (same as for lock) has to be written into the OPTKEYR. A correct sequence of keys gives write access to the option bytes and this is indicated by OPTWRE in the FLASH_CR register being set. Write access can be disabled by resetting the bit through software. 3.4 Flash interrupts Table 6. Flash interrupt request Interrupt event End of operation Write protection error Programming error 60/897 Event flag Enable control bit EOP EOPIE WRPRTERR ERRIE PGERR ERRIE DocID022448 Rev 2 RM0313 Embedded Flash memory 3.5 Flash register description The Flash memory registers have to be accessed by 32-bit words (half-word and byte accesses are not allowed). 3.5.1 Flash access control register (FLASH_ACR) Address offset: 0x00 Reset value: 0x0000 0030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. PRFT BS PRFT BE Res. r rw Res. Res. Res. Res. Res. Res. Res. Res. Res. LATENCY[2:0] rw rw rw Bits 31:6 Reserved, must be kept at reset value. Bit 5 PRFTBS: Prefetch buffer status This bit provides the status of the prefetch buffer. 0: Prefetch buffer is disabled 1: Prefetch buffer is enabled Bit 4 PRFTBE: Prefetch buffer enable 0: Prefetch is disabled 1: Prefetch is enabled Bits 3:2 Reserved, must be kept at reset value. Bits 1:0 LATENCY[2:0]: Latency These bits represent the ratio of the SYSCLK (system clock) period to the Flash access time. 000: Zero wait state, if 0 < SYSCLK≤ 24 MHz 001: One wait state, if 24 MHz < SYSCLK ≤ 48 MHz 010: Two wait sates, if 48 < SYSCLK ≤72 MHz 3.5.2 Flash key register (FLASH_KEYR) Address offset: 0x04 Reset value: xxxx xxxx 31 30 29 28 27 26 25 24 w w w w w w w w 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 w w w w w w w w 7 6 5 4 3 2 1 0 w w w w w w w FKEYR[31:16] FKEYR[15:0] w Note: w w w w w w w w These bits are all write-only and return a 0 when read. Bits 31:0 FKEYR: Flash key These bits represent the keys to unlock the Flash. DocID022448 Rev 2 61/897 70 Embedded Flash memory 3.5.3 RM0313 Flash option key register (FLASH_OPTKEYR) Address offset: 0x08 Reset value: xxxx xxxx All the register bits are write-only and return a 0 when read. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OPTKEYR[31:16] w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w w w w w w w w w w w w w w OPTKEYR[15:0] Bits 31:0 3.5.4 w w OPTKEYR: Option byte key These bits represent the keys to unlock the OPTWRE. Flash status register (FLASH_SR) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EOP WRPRT ERR Res. PG ERR Res. BSY rw rw Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw r Bits 31:6 Reserved, must be kept at reset value. Bit 5 EOP: End of operation Set by hardware when a Flash operation (programming / erase) is completed. Reset by writing a 1 Note: EOP is asserted at the end of each successful program or erase operation Bit 4 WRPRTERR: Write protection error Set by hardware when programming a write-protected address of the Flash memory. Reset by writing 1. Bit 3 Reserved, must be kept at reset value. Bit 2 PGERR: Programming error Set by hardware when an address to be programmed contains a value different from '0xFFFF' before programming. Reset by writing 1. Note: The STRT bit in the FLASH_CR register should be reset before starting a programming operation. Bit 1 Reserved, must be kept at reset value Bit 0 BSY: Busy This indicates that a Flash operation is in progress. This is set on the beginning of a Flash operation and reset when the operation finishes or when an error occurs. 62/897 DocID022448 Rev 2 RM0313 3.5.5 Embedded Flash memory Flash control register (FLASH_CR) Address offset: 0x10 Reset value: 0x0000 0080 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. ERRIE OPTWR E Res. LOCK STRT OPTER OPT PG Res. MER PER PG rw rw rw rw rw rw rw rw rw Res. Res. OBL_L AUNC EOPIE H rw rw Bits 31:14 Reserved, must be kept at reset value. Bit 13 OBL_LAUNCH: Force option byte loading When set to 1, this bit forces the option byte reloading. 0: Inactive 1: Active Bit 12 EOPIE: End of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_SR register goes to 1. 0: Interrupt generation disabled 1: Interrupt generation enabled Bit 11 Reserved, must be kept at reset value Bit 10 ERRIE: Error interrupt enable This bit enables the interrupt generation on an error when PGERR / WRPRTERR are set in the FLASH_SR register. 0: Interrupt generation disabled 1: Interrupt generation enabled Bit 9 OPTWRE: Option bytes write enable When set, the option bytes can be programmed. This bit is set on writing the correct key sequence to the FLASH_OPTKEYR register. This bit can be reset by software Bit 8 Reserved, must be kept at reset value. Bit 7 LOCK: Lock Write to 1 only. When it is set, it indicates that the Flash is locked. This bit is reset by hardware after detecting the unlock sequence. In the event of unsuccessful unlock operation, this bit remains set until the next reset. Bit 6 STRT: Start This bit triggers an ERASE operation when set. This bit is set only by software and reset when the BSY bit is reset. Bit 5 OPTER: Option byte erase Option byte erase chosen. Bit 4 OPTPG: Option byte programming Option byte programming chosen. DocID022448 Rev 2 63/897 70 Embedded Flash memory RM0313 Bit 3 Reserved, must be kept at reset value. Bit 2 MER: Mass erase Erase of all user pages chosen. Bit 1 PER: Page erase Page Erase chosen. Bit 0 PG: Programming Flash programming chosen. 3.5.6 Flash address register (FLASH_AR) Address offset: 0x14 Reset value: 0x0000 0000 This register is updated by hardware with the currently/last used address. For Page Erase operations, this should be updated by software to indicate the chosen page. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FAR[31:16] w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w w w w w w w FAR[15:0] w w w w w w w w w Bits 31:0 FAR: Flash Address Chooses the address to program when programming is selected, or a page to erase when Page Erase is selected. Note: Write access to this register is blocked when the BSY bit in the FLASH_SR register is set. 64/897 DocID022448 Rev 2 RM0313 Embedded Flash memory 3.5.7 Option byte register (FLASH_OBR) Address offset 0x1C Reset value: 0xXXXXXX0X It contains the level protection notifications, error during load of option bytes and user options. r r r r r r r r r r r r Res. r Res. SRAM_PE SDADC12_VDD_MONITOR r 5 4 3 2 1 0 OPTERR r 6 LEVEL1_PROT r 7 LEVEL2_PROT r WDG_SW r 8 nRST_STOP r nBOOT1 r VDDA_MON r Data0 Data1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 r 9 nRST_STDBY The reset value of this register depends on the value programmed in the option byte and the OPTERR bit reset value depends on the comparison of the option byte and its complement during the option byte loading phase. r r r Bits 31:24 Data1 Bits 23:16 Data0 Bits 15:8 OBR: User Option Byte Bit 15: SDADC12_VDD_MONITOR Bit 14: SRAM_PE Bit 13: VDDA_MON Bit 12: nBOOT1 Bit 11: Reserved, must be kept at reset value. Bit 10: nRST_STDBY Bit 9: nRST_STOP Bit 8: WDG_SW Bits 7:3 Reserved, must be kept at reset value. Bit 2 LEVEL2_PROT: Level 2 Read protection status When set, this indicates that the Flash memory is level 2 read-protected. It is set only if LEVEL1_PROT is set. Note: This bit is read-only. Bit 1 LEVEL1_PROT: Level 1 Read protection status When set, this indicates that the Flash memory is level 1 read-protected. Note: This bit is read-only. Bit 0 OPTERR: Option byte Load error When set, this indicates that the loaded option byte and its complement do not match. The corresponding byte and its complement are read as 0xFF in the FLASH_OBR or FLASH_WRPR register. Note: This bit is read-only. DocID022448 Rev 2 65/897 70 Embedded Flash memory 3.5.8 RM0313 Write protection register (FLASH_WRPR) Address offset: 0x20 Reset value: 0xFFFF FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WRP[31:16] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r r r r WRP[15:0] r r Bits 31:0 WRP: Write protect This register contains the write-protection option bytes loaded by the OBL. These bits are read-only. 3.6 Flash register map x x x x x x x x x x x x x x FLASH_OPTKE YR x x x x 66/897 0 Res. x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x FLASH_SR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PGERR Res. BSY 0 0 0 0 0 PG 0 PER 0 0 MER 1 0 Res. OPTPG 0 OPTER 0 0 STRT 0 0 LOCK 0 0 Res. 0 OPTWRE 0 Res. 0 ERRIE Reset value EOPIE FLASH_AR OBL_LAUNCH Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FLASH_CR WRPRTERR x EOP Reset Value Res. OPTKEYR[31:0] Reset value 0x014 0 FKEYR[31:0] Reset value 0x010 0 Res. 0x00C Reset value 1 Res. 0x008 FLASH_KEYR 1 LATENC Y [2:0] Res. 0x004 PRFTBE Res. Reset value PRFTBS Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FLASH_ACR Res. 0x000 Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 7. Flash interface - register map and reset values 0 0 0 0 0 0 FAR[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DocID022448 Rev 2 0 0 0 0 0 RM0313 Embedded Flash memory 1 1 1 1 1 1 FLASH_WRPR Reset value 1 1 1 1 1 1 1 1 1 1 1 1 Res. 1 Res. 1 OPTERR 1 LEVEL1_PROT 1 LEVEL2_PROT 1 WDG_SW 1 nRST_STOP 1 nRST_STDBY 1 SRAM_PE 1 nBOOT1 0x020 1 VDDA_MON Reset value SDADC12_VDD_MONITOR FLASH_OBR Data0 0x01C Register Data1 Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 7. Flash interface - register map and reset values (continued) 0 1 0 1 1 1 WRP[31:0] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Refer to Section 2.2.2 on page 41 for the register boundary addresses. DocID022448 Rev 2 67/897 70 Option byte description 4 RM0313 Option byte description There are eight option bytes. They are configured by the end user depending on the application requirements. As a configuration example, the watchdog may be selected in hardware or software mode. A 32-bit word is split up as follows in the option bytes. Table 8. Option byte format 31-24 23-16 15 -8 7-0 Complemented option byte 1 Option byte 1 Complemented option byte 0 Option byte 0 The organization of these bytes inside the information block is as shown in Table 9. The option bytes can be read from the memory locations listed in Table 9 or from the Option byte register (FLASH_OBR). Note: The new programmed option bytes (user, read/write protection) are loaded after a system reset. Table 9. Option byte organization 68/897 Address [31:24] [23:16] [15:8] [7:0] 0x1FFF F800 nUSER USER nRDP RDP 0x1FFF F804 nData1 Data1 nData0 Data0 0x1FFF F808 nWRP1 WRP1 nWRP0 WRP0 0x1FFF F80C nWRP3 WRP3 nWRP2 WRP2 DocID022448 Rev 2 RM0313 Option byte description Table 10. Description of the option bytes Flash memory address Option bytes 0x1FFF F800 Bits [31:24] nUSER Bits [23:16] USER: User option byte (stored in FLASH_OBR[15:8]) This byte is used to configure the following features: - Select the watchdog event: Hardware or software - Reset event when entering Stop mode - Reset event when entering Standby mode Bit 23: SDADC12_VDD MONITOR 0: SDADC12_VDD power supply supervisor disabled. 1: SDADC12_VDD power supply supervisor enabled Bit 22: SRAM_PE The SRAM hardware parity check is disabled by default. This bit allows the user to enable the SRAM hardware parity check. 0: Parity check enabled. 1: Parity check disabled. Bit 21: VDDA_MON This bit selects the analog monitoring on the VDDA power source: 0: VDDA power supply supervisor disabled. 1: VDDA power supply supervisor enabled. Bit 20: nBOOT1 Together with the BOOT0 pin, this bit selects Boot mode from the main Flash memory, SRAM or System memory. Refer to Section 2.6: Boot configuration. Bit 19: Reserved, must be kept at reset. Bit 18: nRST_STDBY 0: Reset generated when entering Standby mode. 1: No reset generated. Bit 17: nRST_STOP 0: Reset generated when entering Stop mode 1: No reset generated Bit 16: WDG_SW 0: Hardware watchdog 1: Software watchdog Bits [15:8]: nRDP Bits [7:0]: RDP: Read protection option byte The value of this byte defines the Flash memory protection level 0xAA: Level 0 0xXX (except 0xAA and 0xCC): Level 1 0xCC: Level 2 The protection levels 1 and 2 are stored in the Flash_OBR Flash option register (LEVEL1_PROT and LEVEL2_PROT status flags respectively). 0x1FFF F804 Datax: Two bytes for user data storage. These addresses can be programmed using the option byte programming procedure. Bits [31:24]: nData1 Bits [23:16]: Data1 (stored in FLASH_OBR[31:24]) Bits [15:8]: nData0 Bits [7:0]: Data0 (stored in FLASH_OBR[23:16]) DocID022448 Rev 2 69/897 70 Option byte description RM0313 Table 10. Description of the option bytes (continued) Flash memory address Option bytes 0x1FFF F808 WRPx: Flash memory write protection option bytes Bits [31:24]: nWRP1 Bits [23:16]: WRP1 (stored in FLASH_WRPR[15:8]) Bits [15:8]: nWRP0 Bits [7:0]: WRP0 (stored in FLASH_WRPR[7:0]) 0: Write protection active 1 0: Write protection not active Refer to Section 3.3.2: Write protection for more details. 0x1FFF F80C WRPx: Flash memory write protection option bytes Bits [31:24]: nWRP3 Bits [23:16]: WRP3 (stored in FLASH_WRPR[31:24]) Bits [15:8]: nWRP2 Bits [7:0]: WRP2 (stored in FLASH_WRPR[23:16]) One bit of the user option bytes WRPx is used to protect 2 pages of 2 Kbytes in the main memory block. 0: Write protection active 1: Write protection not active In total, 4 user option bytes are used to protect the whole main Flash memory. WRP0: Write-protects pages 0 to 15 WRP1: Write-protects pages 16 to 31 WRP2: Write-protects pages 32 to 47 WRP3: bits 0-6 write-protect pages 48 to 61, bit 7 write-protects pages 62 to 127. On every system reset, the option byte loader (OBL) reads the information block and stores the data into the Option byte register (FLASH_OBR) and the Write protection register (FLASH_WRPR). Each option byte also has its complement in the information block. During option loading, by verifying the option bit and its complement, it is possible to check that the loading has correctly taken place. If this is not the case, an option byte error (OPTERR) is generated. When a comparison error occurs, the corresponding option byte is forced to 0xFF. The comparator is disabled when the option byte and its complement are both equal to 0xFF (Electrical Erase state). 70/897 DocID022448 Rev 2 RM0313 Cyclic redundancy check calculation unit (CRC) 5 Cyclic redundancy check calculation unit (CRC) 5.1 Introduction The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the functional safety standards, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link time and stored at a given memory location. 5.2 CRC main features • Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7 X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2+ X +1 • Alternatively uses a fully programmable polynomial with programmable size (7, 8, 16, 32 bits) • Handles 8-,16-, 32-bit data size • Programmable CRC initial value • Single input/output 32-bit data register • Input buffer to avoid bus stall during calculation • CRC computation done in 4 AHB clock cycles (HCLK) for 32-bit data • General-purpose 8-bit register (can be used for temporary storage) • Reversibility option on I/O data DocID022448 Rev 2 71/897 76 Cyclic redundancy check calculation unit (CRC) 5.3 RM0313 CRC functional description Figure 6. CRC calculation unit block diagram $+%EXV ELWUHDGDFFHVV 'DWDUHJLVWHURXWSXW &5&FRPSXWDWLRQ ELWZULWHDFFHVV 'DWDUHJLVWHULQSXW 069 The CRC calculation unit has a single 32-bit read/write data register (CRC_DR). It is used to input new data (write access), and holds the result of the previous CRC calculation (read access). Each write operation to the data register creates a combination of the previous CRC value (stored in CRC_DR) and the new one. CRC computation is done on the whole 32-bit data word or byte by byte depending on the format of the data being written. The CRC_DR register can be accessed by word, right-aligned half-word and right-aligned byte. For the other registers only 32-bit access is allowed. The duration of the computation depends on data width: • 4 AHB clock cycles for 32-bit • 2 AHB clock cycles for 16-bit • 1 AHB clock cycles for 8-bit An input buffer allows to immediately write a second data without waiting for any wait states due to the previous CRC calculation. The data size can be dynamically adjusted to minimize the number of write accesses for a given number of bytes. For instance, a CRC for 5 bytes can be computed with a word write followed by a byte write. The input data can be reversed, to manage the various endianness schemes. The reversing operation can be performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits in the CRC_CR register. For example: input data 0x1A2B3C4D is used for CRC calculation as: 0x58D43CB2 with bit-reversal done by byte 0xD458B23C with bit-reversal done by half-word 0xB23CD458 with bit-reversal done on the full word The output data can also be reversed by setting the REV_OUT bit in the CRC_CR register. The operation is done at bit level: for example, output data 0x11223344 is converted into 0x22CC4488. 72/897 DocID022448 Rev 2 RM0313 Cyclic redundancy check calculation unit (CRC) The CRC calculator can be initialized to a programmable value using the RESET control bit in the CRC_CR register (the default value is 0xFFFFFFFF). The initial CRC value can be programmed with the CRC_INIT register. The CRC_DR register is automatically initialized upon CRC_INIT register write access. The CRC_IDR register can be used to hold a temporary value related to CRC calculation. It is not affected by the RESET bit in the CRC_CR register. 5.4 Polynomial programmability The polynomial coefficients are fully programmable through the CRC_POL register, and the polynomial size can be configured to be 7, 8, 16 or 32 bits by programming the POLYSIZE[1:0] bits in the CRC_CR register. If the CRC data is less than 32-bit, its value can be read from the least significant bits of the CRC_DR register. To obtain a reliable CRC calculation, the change on-fly of the polynomial value or size can not be perform during a CRC calculation. As a result, if a CRC calculation is ongoing, the application must either reset it or perform a CRC_DR read before changing the polynomial. The default polynomial value is the CRC-32 (Ethernet) polynomial: 0x4C11DB7. 5.5 CRC registers 5.5.1 Data register (CRC_DR) Address offset: 0x00 Reset value: 0xFFFF FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 DR[31:16] rw 15 14 13 12 11 10 9 8 7 DR[15:0] rw Bits 31:0 DR[31:0]: Data register bits This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value. DocID022448 Rev 2 73/897 76 Cyclic redundancy check calculation unit (CRC) 5.5.2 RM0313 Independent data register (CRC_IDR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. IDR[7:0] rw Bits 31:8 Reserved, must be kept cleared. Bits 7:0 IDR[7:0]: General-purpose 8-bit data register bits These bits can be used as a temporary storage location for one byte. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register 5.5.3 Control register (CRC_CR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. REV_ OUT Res. Res. RESET Res. Res. Res. Res. Res. Res. Res. rw REV_IN[1:0] rw rw Bits 31:8 Reserved, must be kept cleared. Bit 7 REV_OUT: Reverse output data This bit controls the reversal of the bit order of the output data. 0: Bit order not affected 1: Bit-reversed output format Bits 6:5 REV_IN[1:0]: Reverse input data These bits control the reversal of the bit order of the input data 00: Bit order not affected 01: Bit reversal done by byte 10: Bit reversal done by half-word 11: Bit reversal done by word 74/897 DocID022448 Rev 2 POLYSIZE[1:0] rw rw rs RM0313 Cyclic redundancy check calculation unit (CRC) Bits 4:3 POLYSIZE[1:0]: Polynomial size These bits control the size of the polynomial. 00: 32 bit polynomial 01: 16 bit polynomial 10: 8 bit polynomial 11: 7 bit polynomial Bits 2:1 Reserved, must be kept cleared. Bit 0 RESET: RESET bit This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware 5.5.4 Initial CRC value (CRC_INIT) Address offset: 0x10 Reset value: 0xFFFF FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 22 21 20 19 18 17 16 6 5 4 3 2 1 0 CRC_INIT[31:16] rw 15 14 13 12 11 10 9 8 7 CRC_INI[15:0] rw Bits 31:0 CRC_INIT: Programmable initial CRC value This register is used to write the CRC initial value. 5.5.5 CRC polynomial (CRC_POL) Address offset: 0x14 Reset value: 0x04C11DB7 31 30 29 28 27 26 25 24 23 POL[31:16] rw 15 14 13 12 11 10 9 8 7 POL[15:0] rw Bits 31:0 POL[31:0]: Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32-bits, the least significant bits have to be used to program the correct value. DocID022448 Rev 2 75/897 76 Cyclic redundancy check calculation unit (CRC) 5.5.6 RM0313 CRC register map Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 11. CRC register map and reset values CRC_DR DR[31:0] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CRC_IDR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CRC_CR 0 Res. 0x08 Reset value 0x10 CRC_INIT Reset value 0x14 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 CRC_INIT[31:0] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CRC_POL Polynomial coefficients Reset value 0x04C11DB7 1 Refer to Section 2.2.2 for the register boundary addresses. 76/897 1 IDR[7:0] REV_OUT 0x04 1 Res. 1 RESET 1 Res. 1 POLYSIZE[1:0] 1 REV_IN[1:0] Reset value Res. 0x00 DocID022448 Rev 2 1 1 1 1 1 1 1 RM0313 Power control (PWR) 6 Power control (PWR) 6.1 Power supplies An internal regulator is embedded in the STM32F37xx devices. • The internal regulator is enabled in the STM32F37xx MCUs: The STM32F37xx devices require 2.0 V - 3.6 V operating supply voltage (VDD) and 2.0 V - 3.6 V analog supply voltage (VDDA). The embedded regulator is used to supply the internal 1.8 V digital power. • The internal regulator is disabled in the STM32F38xx MCUs: The STM32F38xx devices require1.8 V +/- 8 % operating voltage supply (VDD) and 1.65 V - 3.6 V analog voltage supply (VDDA). The embedded regulator is OFF and VDD directly supplies the regulator output. The real-time clock (RTC) and backup registers can be powered from the VBAT voltage when the main VDD supply is powered off. Figure 7. Power supply overview 9''$GRPDLQ 670)[[ 6$$! 633! 6$$3$ 6$$3$ 6333$ 9''$GRPDLQ 6$$! !$CONVERTER $!# 3$!$#S 4EMPSENSOR 2ESETBLOCK 0,, 633! 6$$3$ 6$$3$ 6333$ !$CONVERTER $!# 3$!$#S 4EMPSENSOR 2ESETBLOCK 0,, 9GRPDLQ 9GRPDLQ 9''GRPDLQ 9''GRPDLQ #ORE )/RING 633 6$$ 670)[[ 3TANDBYCIRCUITRY WAKEUPLOGIC)7$' 6OLTAGEREGULATOR -EMORIES $IGITAL 6$$ PERIPHERALS #ORE )/RING 633 6$$ 3TANDBYCIRCUITRY WAKEUPLOGIC)7$' -EMORIES $IGITAL PERIPHERALS ,OWVOLTAGEREGULATOR %DFNXSGRPDLQ 6"!4 ,3%CRYSTAL+(ZOSC 2##"$#2REGISTER 24#AND"+0REGISTERS %DFNXSGRPDLQ 6"!4 ,3%CRYSTAL+(ZOSC 2##"$#2REGISTER 24#AND"+0REGISTERS -36 DocID022448 Rev 2 77/897 95 Power control (PWR) RM0313 Supply voltages • VDD, VSS = 2.0 to 3.6 V: external power supply for I/Os (except I/Os related to SDADCs) and core. These supply voltages are provided externally through VDD and VSS pins. VDD = 2.0 to 3.6 V (STM32F37xx devices) or 1.8 V ± 8 % (STM32F38xx devices). In case of the 1.8 V mode external supply, VDD directly supplies the regulator output which directly drives the VDD18 domain.VDD must always be kept lower or equal to VDDA. • VDD18 = 1.65 to 1.95 V (VDD18 domain): power supply for digital core, SRAM and Flash memory. VDD18 is either internally generated through an internal voltage regulator (STM32F37xx devices) or can be provided directly from the external VDD pin when the regulator is bypassed (STM32F38xx devices). • VDDA, VSSA= 2.4 to 3.6 V (ADC/DAC ON) or 1.65 to 3.6 V (both ADC/DAC OFF): external power supply for ADC, DAC, comparators, temperature sensor, PLL, HSI 8 MHz oscillator, and LSI 40 kHz oscillator. It is forbidden to have VDDA < VDD - 0.4 V. A external Schottky diode must be placed between VDD and VDDA to guarantee this condition is met. • VBAT= 1.65 to 3.6 V Backup power supply for RTC, LSE oscillator, PC13 to PC15 and backup registers when VDD is not present. When VDD supply is present, the internal power switch switches the backup power to VDD. During fast VDD startup, if VDD+0.6 >VBAT, there is a 2 ms period of time during which the current can flow from VDD to VBAT pin. In STM32F38xx devices, VBAT must be connected to VDD (no battery backup). If VBAT is not used, it must be connected to VDD. • VDDSD12= 2.2 to 3.6 V: external power supply for SDADC1/2, PB2, PB10, and PE7 to PE15 I/O pins (I/O pin ground is internally connected to VSS). VDDSD12 must always be kept lower or equal to VDDA. If VDDSD12 is not used, it must be connected to VDDA. • VDDSD3= 2.2 to 3.6 V: external power supply for SDADC3, PB14 to PB15 and PD8 to PD15 I/O pins (I/O pin ground is internally connected to VSS). VDDSD3 must always be kept lower or equal to VDDA. If VDDSD3 is not used, it must be connected to VDDA. • VSSSD: analog ground pin for SDADC1/2/3. VSSSD must be connected to ground. Note: PB0 and PB1 pins are powered from VDD power supply. However, PB0 and PB1 are also sharing SDADC1 analog inputs. Therefore the maximum voltage connected to these pins when they are not used as analog inputs must be less than the minimum of VDD and VDDSD12 supply voltages to avoid current injection into VDD and VDDSD12. When PB0 and PB1 are configured in analog input mode (MODERy[1:0] = 11, see Section 8.4.1: GPIO port mode register (GPIOx_MODER) (x = A..F)), the maximum voltage must be less than VDDSD12. If VDD is higher than VDDSD12, it is forbidden to use PB0 and PB1 in digital output mode to avoid current injection from VDD supply into VDDSD12 supply through shared analog inputs. 78/897 DocID022448 Rev 2 RM0313 Power control (PWR) Reference voltages • VREF+, VREF− = 2.2 to 3.6 V VREF+ and VREF−correspond to the reference voltage for ADC and DAC peripherals. They define the ADC and DAC input range. VREF+ must always be kept lower or equal to VDDA. If VREF+ is not used, it must be connected to VDDA and VREF− must be connected to VSSA. VREF− must be connected to ground. • VREFSD+, VREFSD- = 1.1 to 3.6 V VREFSD+ and VREFSD- correspond to the reference voltage for SDADCx converters. They define the input conversion range for all SDADCx converters. If SDADCx is configured in external reference voltage mode, the external voltage reference source must be connected to these pins. If the external reference voltage is not enabled, then the selected SDADC internal reference voltage source (VREFINT, SDADC_VDD) is present on VREFSD+. A 10 nF+1 μF capacitor must be placed between VREFSD+ and VREFSD- for decoupling purposes. VREFSD+ must be lower than SDADC power supply: VREFSD+ < min(VDDSD12, VDDSD3). VREFSD- must be connected to ground. 6.1.1 Independent A/D and D/A converter supply and reference voltage To improve conversion accuracy, the ADC and the DAC have an independent power supply which can be separately filtered and shielded from noise on the PCB. • The ADC and DAC voltage supply input is available on a separate VDDA pin. • An isolated supply ground connection is provided on pin VSSA. • The SDADC voltage supply is available on separate VDDSDx pins. • An isolated SDADC supply ground connection is provided on pin VSSSD. The VDDA supply/reference voltage can be equal or higher than VDD. The VDDSD12 and VDDSD3 can be different from VDD, VDDA and from one another, considering they are inside the allowed working range and must always be lower than VDDA. When VDDSD3 is different, it must start before or at the same time as VDDSD12. When a single supply is used, VDDA, VDDSD12 and VDDSD3 can be externally connected to VDD, through the external filtering circuit in order to ensure a noise free analog supply/reference voltage. When VDDA is different from VDD, it must always be higher or equal to VDD. In order to ensure this condition, also during power-up/power-down transitions, an external Schottky diode may be used between VDD and VDDA. VDDSD12 and VDDSD3 can also be different, higher or lower than VDD and lower or equal to VDDA. DocID022448 Rev 2 79/897 95 Power control (PWR) 6.1.2 RM0313 Battery backup domain To retain the content of the backup registers and supply the RTC function when VDD is turned off, VBAT pin can be connected to an optional standby voltage supplied by a battery or by another source. The battery backup feature is not available on STM32F38xx microcontrollers (VDD = 1.8 V ± 8%). When the device operates in this mode, VBAT pin must be connected to VDD. The VBAT pin powers the RTC unit, the LSE oscillator and the PC13 to PC15 I/Os, allowing the RTC to operate even when the main digital supply (VDD) is turned off. The switch to the VBAT supply is controlled by the Power Down Reset embedded in the Reset block. Warning: During tRSTTEMPO (temporization at VDD startup) or after a PDR is detected, the power switch between VBAT and VDD remains connected to VBAT. During the startup phase, if VDD is established in less than tRSTTEMPO (Refer to the datasheet for the value of tRSTTEMPO) and VDD > VBAT + 0.6 V, a current may be injected into VBAT through an internal diode connected between VDD and the power switch (VBAT). If the power supply/battery connected to the VBAT pin cannot support this current injection, it is strongly recommended to connect an external low-drop diode between this power supply and the VBAT pin. If no external battery is used in the application, it is recommended to connect VBAT externally to VDD with a 100 nF external ceramic decoupling capacitor (for more details refer to AN4206). When the backup domain is supplied by VDD (analog switch connected to VDD), the following functions are available: Note: • PC14 and PC15 can be used as either GPIO or LSE pins • PC13 can be used as GPIO, TAMPER pin, RTC Calibration Clock, RTC Alarm or second output (refer to Section 23.6.19: RTC backup registers (RTC_BKPxR) on page 550) Due to the fact that the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is restricted: the speed has to be limited to 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED). When the backup domain is supplied by VBAT (analog switch connected to VBAT because VDD is not present), the following functions are available: 80/897 • PC14 and PC15 can be used as LSE pins only • PC13 can be used as TAMPER pin, RTC Alarm or Second output (refer to section).Section 23.6.15: RTC calibration register (RTC_CALR) on page 544 DocID022448 Rev 2 RM0313 6.1.3 Power control (PWR) Voltage regulator The voltage regulator is always enabled after Reset. It works in three different modes depending on the application modes. • In Run mode, the regulator supplies full power to the 1.8 V domain (core, memories and digital peripherals). • In Stop mode the regulator supplies low-power to the 1.8 V domain, preserving contents of registers and SRAM. This mode is automatically disabled when the USART, CEC, or I2C peripheral requires a clock in Stop mode. • In Standby Mode, the regulator is powered off. The contents of the registers and SRAM are lost except for the Standby circuitry and the Backup Domain. STM32F38xx microcontrollers The internal voltage regulator is bypassed in STM32F38xx devices (unlike the STM32F37xx where the voltage regulator is functional). In this case, the microcontroller must be powered from a nominal VDD = 1.8 V ± 8% voltage. In STM32F38xx microcontrollers, the external NPOR input pin replaces the internal POR signal. The external NPOR pin must be controlled by the application (released after all supply voltages are stabilized) and be connected to VDDA through a pull-up resistor. This pin replaces PB2 GPIO pin. 6.2 Power supply supervisor 6.2.1 Power on reset (POR)/power down reset (PDR) The device has an integrated power-on reset (POR) and power-down reset (PDR) circuits which are always active and ensure proper operation above a threshold of 2 V. The device remains in Reset mode when the monitored supply voltage is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. • The POR monitors only the VDD supply voltage. During startup phase, VDDA must arrive first and be higher than or equal to VDD. • The PDR monitors both VDD and VDDA supply voltages. However, if the application is designed with VDDA higher than or equal to VDD, the VDDA power supply supervisor can be disabled (by programming a dedicated VDDA_MONITOR option bit) to reduce the power consumption. For more details on the power on /power down reset threshold, refer to the electrical characteristics section in the datasheet. DocID022448 Rev 2 81/897 95 Power control (PWR) RM0313 Figure 8. Power on reset/power down reset waveform 6$$6$$! 0$2 M6 HYSTERESIS 0$2 4EMPORIZATION T2344%-0/ 2ESET -36 VDDSD12 monitoring VDDSD12 supply is monitored comparing it with the internal reference voltage (VREFINT). At startup, the supply voltage monitoring defaults to be active. It can then be disabled through the SDADC12_VDD_MONITOR option bit. Assuming VDDA and VDD are instantaneously available at startup, the system waits for VDDSD12 to exceed VREFINT voltage before releasing the reset. VDDSD3 is not monitored, so even if VDDSD12 is usually higher or lower than VDDSD3, the application has to make sure that VDDSD3 is set up before VDDSD12. Constrains on VDDSDx versus VREFSD voltage When the reference voltage for SDADC converters (VREFSD+) is selected from SDADC power supply (REFV[1:0] bits of SDADC_CR1 register set to 11), the reference is provided by converters analog supplies (VDDSD12 and VDDSD3) and VDDSD12 must be at the same voltage level as VDDSD3. Note: There is one exception if SDADC1 and SDADC2 converters are disabled and SDADC3 is enabled (through ENSDx bits in PWR_CR register and ADON bit in SDADC_CR2 register). In this case, VDDSD12 can be lower than VDDSD3 and the reference voltage can be provided by VDDSD3. In STM32F38xx devices (VDD=1.8 V+/8%), VDDSD12 monitoring is OFF like the other supply voltage monitoring systems. This means that the application should take care of monitoring it externally and of releasing the external power on NPOR reset pin after powerup and when all supply voltages are stable. 82/897 DocID022448 Rev 2 RM0313 6.2.2 Power control (PWR) Programmable voltage detector (PVD) You can use the PVD to monitor the VDD power supply by comparing it to a threshold selected by the PLS[2:0] bits in the Power control register (PWR_CR). The PVD is enabled by setting the PVDE bit. A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate if VDD is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The PVD output interrupt can be generated when VDD drops below the PVD threshold and/or when VDD rises above the PVD threshold depending on EXTI line16 rising/falling edge configuration. As an example the service routine could perform emergency shutdown tasks. Figure 9. PVD thresholds 6$$ 06$THRESHOLD M6 HYSTERESIS 06$OUTPUT -36 Note: In STM32F38xx devices (VDD = 1.8 V ± 8 %), the POR, PDR and PVD features are not available. The Power-on reset signal is applied on the NPOR pin. See details in the following section. 6.2.3 External NPOR signal In STM32F38xx devices (powered from 1.8 V ± 8 %), the POR, PDR and PVD features are not available and the application must provide the reset signal to the external NPOR pin. The NPOR signal is active low, and must be driven to VSS when the VDDA is applied. Then, when VDD is stable, it can be released (high impedance) and the internal pull-up will hold this input to VDDA. The NPOR signal can also be controlled by using an open-drain driver circuitry. In STM32F38xx devices, PB2 I/O is not available and is replaced by the NPOR functionality. DocID022448 Rev 2 83/897 95 Power control (PWR) 6.3 RM0313 Low-power modes By default, the microcontroller is in Run mode after a system or a power Reset. Several lowpower modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event. It is up to the user to select the mode that gives the best compromise between low-power consumption, short startup time and available wakeup sources. The device features three low-power modes: • Sleep mode (CPU clock off, all peripherals including Cortex-M4 with FPU core peripherals like NVIC, SysTick, etc. are kept running) • Stop mode (all clocks are stopped) • Standby mode (1.8 V domain powered-off) In addition, the power consumption in Run mode can be reduced by one of the following means: • Slowing down the system clocks • Gating the clocks to the APB and AHB peripherals when they are unused. Table 12. Low-power mode summary Mode name Sleep (Sleep now or Sleep-on -exit) Stop Standby Entry wakeup WFI Any interrupt WFE Wakeup event Any EXTI line (configured in the EXTI registers) PDDS and LPDS bits + SLEEPDEEP Specific communication bit + WFI or WFE peripherals on reception events (CEC, USART, I2C) PDDS bit + SLEEPDEEP bit + WFI or WFE Effect on 1.8 V domain clocks CPU clock OFF no effect on other clocks or analog clock sources All 1.8V domain clocks OFF WKUP pin rising edge, RTC alarm, external reset in NRST pin, IWDG reset Effect on VDD domain clocks None HSI and HSE oscillators OFF Voltage regulator ON ON or in lowpower mode (depends on Power control register (PWR_CR))(1) OFF 1. In STM32F38xx devices, Standby mode is not available. Stop mode is still available, but it is meaningless to distinguish between voltage regulator in Low power mode and voltage regulator in Run mode, because the regulator is not used and VDD is applied externally to the regulator output. 6.3.1 Slowing down system clocks In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down peripherals before entering Sleep mode. For more details refer to Section 7.4.2: Clock configuration register (RCC_CFGR). 84/897 DocID022448 Rev 2 RM0313 6.3.2 Power control (PWR) Peripheral clock gating In Run mode, the HCLK and PCLK for individual peripherals and memories can be stopped at any time to reduce power consumption. To further reduce power consumption in Sleep mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions. Peripheral clock gating is controlled by the AHB peripheral clock enable register (RCC_AHBENR) 6.3.3 Sleep mode Entering Sleep mode The Sleep mode is entered by executing the WFI (Wait For Interrupt) or WFE (Wait for Event) instructions. Two options are available to select the Sleep mode entry mechanism, depending on the SLEEPONEXIT bit in the Cortex-M4 with FPU System Control register: • Sleep-now: if the SLEEPONEXIT bit is cleared, the MCU enters Sleep mode as soon as WFI or WFE instruction is executed. • Sleep-on-exit: if the SLEEPONEXIT bit is set, the MCU enters Sleep mode as soon as it exits the lowest priority ISR. In the Sleep mode, all I/O pins keep the same state as in the Run mode. Refer to Table 13 and Table 14 for details on how to enter Sleep mode. Exiting Sleep mode If the WFI instruction is used to enter Sleep mode, any peripheral interrupt acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device from Sleep mode. If the WFE instruction is used to enter Sleep mode, the MCU exits Sleep mode as soon as an event occurs. The wakeup event can be generated either by: • enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the Cortex-M4 with FPU System Control register. When the MCU resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. • or configuring an external or internal EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set. This mode offers the lowest wakeup time as no time is wasted in interrupt entry/exit. Refer to Table 13 and Table 14 for more details on how to exit Sleep mode. DocID022448 Rev 2 85/897 95 Power control (PWR) RM0313 Table 13. Sleep-now Sleep-now mode Description Mode entry WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP = 0 and – SLEEPONEXIT = 0 Refer to the Cortex-M4 with FPU System Control register. Mode exit If WFI was used for entry: Interrupt: Refer to Table 28: List of vectors If WFE was used for entry Wakeup event: Refer to Section 11.2.3: Wakeup event management Wakeup latency None Table 14. Sleep-on-exit Sleep-on-exit 6.3.4 Description Mode entry WFI (wait for interrupt) while: – SLEEPDEEP = 0 and – SLEEPONEXIT = 1 Refer to the Cortex-M4 with FPU System Control register. Mode exit Interrupt: refer to Table 28: List of vectors. Wakeup latency None Stop mode The Stop mode is based on the Cortex-M4 with FPU deepsleep mode combined with peripheral clock gating. The voltage regulator can be configured either in normal or lowpower mode in STM32F37xx devices. In STM32F38xx, it is meaningless to distinguish between voltage regulator in low power mode and voltage regulator in Run mode, because the regulator is not used and VDD is applied externally to the regulator output.. In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC oscillators are disabled, SRAM and register contents are preserved. The I2C, CEC, and USART peripherals are an exception since they require a given kernel clock in Stop mode. In this case, when this specific clock request is ON, the power controller automatically forces the regulator to be ON as well, to prevent the device to operate in lowpower mode since the regulator would not sustain the current required by the peripherals. In the Stop mode, all I/O pins keep the same state as in Run mode. Entering Stop mode Refer to Table 15 for details on how to enter the Stop mode. To further reduce power consumption in Stop mode, the internal voltage regulator can be put in low-power mode. This is configured by the LPDS bit of the Power control register (PWR_CR). If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory access is finished. 86/897 DocID022448 Rev 2 RM0313 Power control (PWR) If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB access is finished. In Stop mode, the following features can be selected by programming individual control bits: • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a Reset. See Section 21.3: IWDG functional description in Section 21: Independent watchdog (IWDG). • real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR) • Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status register (RCC_CSR). • External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the Backup domain control register (RCC_BDCR). The SDADC, ADC or DAC can also consume power during the Stop mode, unless they are disabled before entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit in the DAC_CR register must both be written to 0. Note: If the application needs to disable the external oscillator (external clock) before entering Stop mode, the system clock source must be first switched to HSI and then clear the HSEON bit. Otherwise, if before entering Stop mode the HSEON bit is kept at 1, the security system (CSS) feature must be enabled to detect any external oscillator (external clock) failure and avoid a malfunction when entering Stop mode. Exiting Stop mode Refer to Table 15 for more details on how to exit Stop mode. When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock. When the voltage regulator operates in low-power mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced. DocID022448 Rev 2 87/897 95 Power control (PWR) RM0313 Table 15. Stop mode Stop mode 6.3.5 Description Mode entry WFI (Wait for Interrupt) or WFE (Wait for Event) while: – Set SLEEPDEEP bit in Cortex-M4 with FPU System Control register – Clear PDDS bit in Power Control register (PWR_CR) – Select the voltage regulator mode by configuring LPDS bit in PWR_CR Note: To enter Stop mode, all EXTI Line pending bits (in Pending register (EXTI_PR)), all peripherals interrupt pending bits and RTC Alarm flag must be reset. Otherwise, the Stop mode entry procedure is ignored and program execution continues. Mode exit If WFI was used for entry: – Any EXTI Line configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC). – Some specific communication peripherals (CEC, USART, I2C) interrupts, when programmed in wakeup mode (the peripheral must be programmed in wakeup mode and the corresponding interrupt vector must be enabled in the NVIC). Refer to Table 28: List of vectors. If WFE was used for entry: Any EXTI Line configured in event mode. Refer to Section 11.2.3: Wakeup event management Wakeup latency HSI RC wakeup time + regulator wakeup time from Low-power mode Standby mode The Standby mode allows to achieve the lowest power consumption. It is based on the Cortex-M4 with FPU deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also switched off. SRAM and register contents are lost except for registers in the Backup domain (see Figure 7). Caution: In the STM32F38x devices, the Standby mode is not available. Entering Standby mode Refer to Table 16 for more details on how to enter Standby mode. In Standby mode, the following features can be selected by programming individual control bits: 88/897 • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a reset. See Section 21.3: IWDG functional description in Section 21: Independent watchdog (IWDG). • real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR) • Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status register (RCC_CSR). • External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the Backup domain control register (RCC_BDCR) DocID022448 Rev 2 RM0313 Power control (PWR) Exiting Standby mode The microcontroller exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin or the rising edge of an RTC alarm occurs (see Figure 166: RTC block diagram). All registers are reset after wakeup from Standby except for Power control/status register (PWR_CSR). After waking up from Standby mode, program execution restarts in the same way as after a Reset (boot pins sampling, vector reset is fetched, etc.). The SBF status flag in the Power control/status register (PWR_CSR) indicates that the MCU was in Standby mode. Refer to Table 16 for more details on how to exit Standby mode. Table 16. Standby mode Standby mode Description Mode entry WFI (Wait for Interrupt) or WFE (Wait for Event) while: – Set SLEEPDEEP in Cortex-M4 with FPU System Control register – Set PDDS bit in Power Control register (PWR_CR) – Clear WUF bit in Power Control/Status register (PWR_CSR) Mode exit WKUP pin rising edge, RTC alarm event’s rising edge, external Reset in NRST pin, IWDG Reset. Wakeup latency Reset phase I/O states in Standby mode In Standby mode, all I/O pins are high impedance except: • Reset pad (still available) • TAMPER pin if configured for tamper or calibration out • WKUP pin, if enabled Debug mode By default, the debug connection is lost if the application puts the MCU in Stop or Standby mode while the debug features are used. This is due to the fact that the Cortex-M4 with FPU core is no longer clocked. However, by setting some configuration bits in the DBGMCU_CR register, the software can be debugged even when using the low-power modes extensively.For more details, refer to Section 31.16.1: Debug support for low-power modes. 6.3.6 Auto-wakeup from low-power mode The RTC can be used to wakeup the MCU from low-power mode without depending on an external interrupt (Auto-wakeup mode). The RTC provides a programmable time base for waking up from Stop or Standby mode at regular intervals. For this purpose, two of the three DocID022448 Rev 2 89/897 95 Power control (PWR) RM0313 alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR): • Low-power 32.768 kHz external crystal oscillator (LSE OSC). This clock source provides a precise time base with very low-power consumption (less than 1µA added consumption in typical conditions) • Low-power internal RC Oscillator (LSI RC) This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This internal RC Oscillator is designed to add minimum power consumption. To wakeup from Stop mode with an RTC alarm event, it is necessary to: • Configure the EXTI Line 17 to be sensitive to rising edge • Configure the RTC to generate the RTC alarm To wakeup from Standby mode, there is no need to configure the EXTI Line 17. 90/897 DocID022448 Rev 2 RM0313 Power control (PWR) 6.4 Power control registers The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 6.4.1 Power control register (PWR_CR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by wakeup from Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. ENSD 3 ENSD 2 ENSD 1 DBP PVDE CSBF CWUF PDDS LPDS rw rw rw rw rw rc_w1 rc_w1 rw rw Bits 31:12 PLS[2:0] rw rw rw Reserved, must be kept at reset value. Bit 11 ENSD3: Enable SDADC3. This bit is set and cleared by software. 0: SDADC3 disabled. SDADC3 is in power down mode. 1: SD3 is enabled. Bit 10 ENSD2: Enable SDADC2. This bit is set and cleared by software. 0: SDADC2 disabled. SDADC2 is in power down mode. 1: SD2 is enabled. Bit 9 ENSD1: Enable SDADC1. This bit is set and cleared by software. 0: SDADC1 disabled. SDADC1 is in power down mode. 1: SD1 is enabled. Bit 8 DBP: Disable backup domain write protection. In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers. 0: Access to RTC and Backup registers disabled 1: Access to RTC and Backup registers enabled Note: If the HSE divided by 128 is used as the RTC clock, this bit must remain set to 1. DocID022448 Rev 2 91/897 95 Power control (PWR) RM0313 Bits 7:5 PLS[2:0]: PVD level selection. These bits are written by software to select the voltage threshold detected by the Power Voltage Detector. Note: 000: 2.2V 001: 2.3V 010: 2.4V 011: 2.5V 100: 2.6V 101: 2.7V 110: 2.8V 111: 2.9V Note: Refer to the electrical characteristics of the datasheet for more details. Note: Once the PVD_LOCK is enabled (for CLASS B protection) the PLS[2:0] bits cannot be programmed anymore. Bit 4 PVDE: Power voltage detector enable. This bit is set and cleared by software. 0: PVD disabled 1: PVD enabled Bit 3 CSBF: Clear standby flag. This bit is always read as 0. 0: No effect 1: Clear the SBF Standby Flag (write). Bit 2 CWUF: Clear wakeup flag. This bit is always read as 0. 0: No effect 1: Clear the WUF Wakeup Flag after 2 System clock cycles. (write) Bit 1 PDDS: Power down deepsleep. This bit is set and cleared by software. It works together with the LPDS bit. 0: Enter Stop mode when the CPU enters Deepsleep. The regulator status depends on the LPDS bit. 1: Enter Standby mode when the CPU enters Deepsleep. Bit 0 LPDS: Low-power deepsleep. This bit is set and cleared by software. It works together with the PDDS bit. 0: Voltage regulator on during Stop mode 1: Voltage regulator in low-power mode during Stop mode 92/897 DocID022448 Rev 2 RM0313 Power control (PWR) 6.4.2 Power control/status register (PWR_CSR) Address offset: 0x04 Reset value: 0x0000 0000 (not reset by wakeup from Standby mode) Additional APB cycles are needed to read this register versus a standard APB read. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. EWUP 3 EWUP 2 EWUP 1 Res. Res. Res. Res. VREFI NTRD YF PVDO SBF WUF rw rw rw r r r r Bits 31:11 Reserved, must be kept at reset value. Bit 10 EWUP3: Enable WKUP3 pin This bit is set and cleared by software. 0: WKUP3 pin is used for general purpose I/O. An event on the WKUP3 pin does not wakeup the device from Standby mode. 1: WKUP3 pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP3 pin wakes-up the system from Standby mode). Note: This bit is reset by a system Reset. Bit 9 EWUP2: Enable WKUP2 pin This bit is set and cleared by software. 0: WKUP2 pin is used for general purpose I/O. An event on the WKUP2 pin does not wakeup the device from Standby mode. 1: WKUP2 pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP2 pin wakes-up the system from Standby mode). Note: This bit is reset by a system Reset. Bit 8 EWUP1: Enable WKUP1 pin This bit is set and cleared by software. 0: WKUP1 pin is used for general purpose I/O. An event on the WKUP1 pin does not wakeup the device from Standby mode. 1: WKUP1 pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP1 pin wakes-up the system from Standby mode). Note: This bit is reset by a system Reset. Bits 7:4 Reserved, must be kept at reset value. DocID022448 Rev 2 93/897 95 Power control (PWR) RM0313 Bit 3 VREFINTRDY: VREFINT reference voltage ready. This bit is cleared and set by hardware. This bit indicates the state of the internal reference voltage VREFINT. It is set when VREFINT is ready. It is reset during stabilization of VREFINT. Note: This flag is useful only for the STM32F38xx product when working with external NPOR pin. In the STM32F37xx product, the internal POR waits for the VREFINT stabilization before releasing the reset. Bit 2 PVDO: PVD output This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit. 0: VDD is higher than the PVD threshold selected with the PLS[2:0] bits. 1: VDD is lower than the PVD threshold selected with the PLS[2:0] bits. Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after Standby or reset until the PVDE bit is set. Once the PVD is enabled and configured in the PWR_CR register, PVDO can be used to generate an interrupt through the Extended Interrupt/event controller. Once the PVD_LOCK is enabled (for CLASS B protection) PVDO cannot be disabled anymore. Bit 1 SBF: Standby flag This bit is set by hardware and cleared only by a POR/PDR (power on reset/power down reset) or by setting the CSBF bit in the Power control register (PWR_CR) 0: Device has not been in Standby mode 1: Device has been in Standby mode Bit 0 WUF: Wakeup flag This bit is set by hardware and cleared by a system reset or by setting the CWUF bit in the Power control register (PWR_CR). 0: No wakeup event occurred 1: A wakeup event was received from the WKUP pin or from the RTC alarm Note: An additional wakeup event is detected if the WKUP pin is enabled (by setting the EWUP bit) when the WKUP pin level is already high. 94/897 DocID022448 Rev 2 RM0313 6.4.3 Power control (PWR) PWR register map The following table summarizes the PWR registers. Res. Res. LPDS Res. 0 PDDS EWUP1 0 0 0 0 0 SBF EWUP2 0 0 WUF 0 CSBF 0 CWUF 0 PVDO 0 PVDE DBP 0 Res. ENSD1 0 VREFINTRDYF ENSD2 0 EWUP3 Res. Res. Res. Res. ENSD3 Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PWR_CSR Res. 0x004 Res. Reset value PLS[2:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PWR_CR Res. 0x000 Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 17. PWR register map and reset values 0 0 0 0 Refer to Section 2.2.2 on page 41 for the register boundary addresses. DocID022448 Rev 2 95/897 95 Reset and clock control (RCC) RM0313 7 Reset and clock control (RCC) 7.1 Reset There are three types of reset, defined as system reset, power reset and RTC domain reset. 7.1.1 Power reset A power reset is generated when one of the following events occurs: 1. Power-on/power-down reset (POR/PDR reset) 2. When exiting Standby mode A power reset sets all registers to their reset values except the RTC domain (Figure 7 on page 77). In STM32F38xx devices, the POR/PDR reset is not functional and the Standby mode is not available. Power reset must be provided from an external NPOR pin (active low and released by the application when all supply voltages are stabilized). 7.1.2 System reset A system reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the RTC domain (see Figure 7 on page 77). A system reset is generated when one of the following events occurs: 1. A low level on the NRST pin (external reset) 2. Window watchdog event (WWDG reset) 3. Independent watchdog event (IWDG reset) 4. A software reset (SW reset) (see Software reset) 5. Low-power management reset (see Low-power management reset) 6. Option byte loader reset (see Option byte loader reset) 7. A power reset The reset source can be identified by checking the reset flags in the Control/Status register, RCC_CSR (see Section 7.4.10: Control/status register (RCC_CSR)). These sources act on the NRST pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at address 0x0000_0004 in the memory map. The system reset signal provided to the device is output on the NRST pin. The pulse generator guarantees a minimum reset pulse duration of 20 µs for each internal reset source. In case of an external reset, the reset pulse is generated while the NRST pin is asserted low. 96/897 DocID022448 Rev 2 RM0313 Reset and clock control (RCC) Figure 10. Simplified diagram of the reset circuit 9 '' 5 38 ([WHUQDO UHVHW )LOWHU 1567 3XOVH JHQHUDWRU PLQV 6\VWHPUHVHW ::'*UHVHW ,:'*UHVHW 3RZHUUHVHW 6RIWZDUHUHVHW /RZSRZHUPDQDJHPHQWUHVHW 2SWLRQE\WHORDGHUUHVHW ([LWIURP6WDQGE\PRGH 069 Software reset The SYSRESETREQ bit in Cortex-M4 with FPU Application Interrupt and Reset Control Register must be set to force a software reset on the device. Refer to the Cortex™-M0 technical reference manual for more details. Low-power management reset There are two ways to generate a low-power management reset: 1. Reset generated when entering Standby mode: This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby mode. 2. Reset when entering Stop mode: This type of reset is enabled by resetting nRST_STOP bit in User Option Bytes. In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering Stop mode. For further information on the User Option Bytes, refer to Section 4: Option bytes. Option byte loader reset The option byte loader reset is generated when the OBL_LAUNCH bit (bit 13) is set in the FLASH_CR register. This bit is used to launch the option byte loading by software. 7.1.3 RTC domain reset The RTC domain has two specific resets that affect only the RTC domain (Figure 7 on page 77). An RTC domain reset only affects the LSE oscillator, the RTC, the Backup registers and the RCC Backup domain control register (RCC_BDCR). It is generated when one of the following events occurs. 1. Software reset, triggered by setting the BDRST bit in the Backup domain control register (RCC_BDCR). 2. VDD power-up if VBAT has been disconnected when it was low. DocID022448 Rev 2 97/897 138 Reset and clock control (RCC) RM0313 The Backup registers are also reset when one of the following events occurs: 7.2 1. RTC tamper detection event. 2. Change of the read out protection from level 1 to level 0. Clocks Three different clock sources can be used to drive the system clock (SYSCLK): • HSI 8 MHZ RC oscillator clock • HSE oscillator clock • PLL clock The devices have the following additional clock sources: • 40 kHz low speed internal RC (LSI RC) which drives the independent watchdog and optionally the RTC used for Auto-wakeup from Stop/Standby mode. • 32.768 kHz low speed external crystal (LSE crystal) which optionally drives the realtime clock (RTCCLK) Each clock source can be switched on or off independently when it is not used, to optimize power consumption. Several prescalers allow to configure the frequency of the AHB, the high speed APB (APB2) and the low speed APB (APB1) domains. The AHB and the high speed APB domains maximum frequency is 72 MHz, while the low speed APB domain maximum frequency is 36 MHz. The Cortex system timer is always clocked by the AHB clock divided by 8 or directly by the AHB clock (through Cortex Systick configuration bits). 98/897 DocID022448 Rev 2 RM0313 Reset and clock control (RCC) All the peripheral clocks are derived from their bus clock (HCLK or PCLK) except: • The Flash memory programming interface clock (FLITFCLK) which is always the HSI clock. • The option byte loader clock which is always the HSI clock • The ADC clock is the high speed APB clock (APB2) divided by 2, 4, 6 or 8. • The USART1/2/3 clock which is derived (selected by software) from one of the four following sources: • – system clock – HSI clock – LSE clock – APB clock (PCLK) The I2C1/2 clock which is derived (selected by software) from one of the two following sources: – system clock – HSI clock • The CEC clock which is derived from the HSI clock divided by 244 or from the LSE clock. • The I2S clock which is always the system clock. • The RTC clock which is derived from the LSE, LSI or from the HSE clock divided by 32. • The IWDG clock which is always the LSI clock. • The timer clock frequencies are twice the frequency of the APB domain to which they are connected. Nevertheless, if the APB prescaler is 1, the timer clock frequency is the same as the frequency of the APB domain to which it is connected. The RCC feeds the Cortex System Timer (SysTick) external clock with the AHB clock (HCLK) divided by 8. The SysTick can work either with this clock or directly with the Cortex clock (HCLK), configurable in the SysTick Control and Status Register. DocID022448 Rev 2 99/897 138 Reset and clock control (RCC) RM0313 Figure 11. Clock tree part 1 ,3)2# ,3)TEMPO 7ATCHDOG ,3 ,3)/3# ,3%TEMPO 24#!75 CK?LSE -#/ CK?LSI #+?-)&( CK?HSI?CEC CK?HSI?USART CK?HSI?IC 2#-(Z #+?072 / #+?#05 #+?-)&2# (3)TEMPO (3%/3# CK?HSI CK?HSE (3%TEMPO 35(',9 CK?PLL 6 !(" 02%3# 0,, 8 LEVELSHIFTERS #+?4)-393 #+?&#,+ !0" 02%3# !0" 02%3# !$# 02%3# CK?PLLIN -(ZCLOCK DETECTOR (3%PRESENTORNOT CLOCKSOURCE CONTROL 53!24%.!.$./4DEEPSLEEP/2 #,+2%1?53!24!.$ CK?HSI?USART 53!2437/2 CK?LSE #+?53!24 #+?)330) #+?)330) #+?)330) #+?!0" #+?)# CK?HSI?IC CK?LSE #+?#%# CK?HSI?CEC #+?4)-X!0" IF!0"PRESCX ELSEX #+?4)-X!0" IF!0"PRESCX ELSEX #+?!0" #+?!$# -36 100/897 DocID022448 Rev 2 RM0313 Reset and clock control (RCC) Figure 12. Clock tree part 2 CK?HSI?USAR T CK?LSE CK?SYSTEM !0"PRESCOUTCLOCK #+?53!24 #+?53!24 #+?53" 53"02%3# #+?3$!$# CK?VCO CK?PLL / 3 $! $ # 0 2 % 3 # -36 1. For full details about the internal and external clock source characteristics, please refer to the “Electrical characteristics” section in your device datasheet. 7.2.1 HSE clock The high speed external clock signal (HSE) can be generated from two possible clock sources: • HSE external crystal/ceramic resonator • HSE user external clock The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected oscillator. DocID022448 Rev 2 101/897 138 Reset and clock control (RCC) RM0313 Figure 13. HSE/ LSE clock sources Clock source Hardware configuration 26&B,1 26&B287 External clock *3,2 ([WHUQDO VRXUFH 06Y9 26&B,1 Crystal/Ceramic resonators &/ 26&B287 /RDG FDSDFLWRUV &/ 06Y9 External crystal/ceramic resonator (HSE crystal) The 4 to 32 MHz external oscillator has the advantage of producing a very accurate rate on the main clock. The associated hardware configuration is shown in Figure 13. Refer to the electrical characteristics section of the datasheet for more details. The HSERDY flag in the Clock control register (RCC_CR) indicates if the HSE oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR). The HSE crystal can be switched on and off using the HSEON bit in the Clock control register (RCC_CR). Caution: To switch ON the HSE oscillator, 512 HSE clock pulses need to be seen by an internal stabilization counter after the HSEON bit is set. Even in the case that no crystal or resonator is connected to the device, excessive external noise on the OSC_IN pin may still lead the oscillator to start. Once the oscillator is started, it needs another 6 HSE clock pulses to complete a switching OFF sequence. If for any reason the oscillations are no more present on the OSC_IN pin, the oscillator cannot be switched OFF, locking the OSC pins from any other use and introducing unwanted power consumption. To avoid such situation, it is strongly recommended to always enable the Clock Security System (CSS) which is able to switch OFF the oscillator even in this case. External source (HSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to 32 MHz. You select this mode by setting the HSEBYP and HSEON bits in the Clock control register (RCC_CR). The external clock signal (square, sinus or triangle) with ~40-60% duty cycle depending on the frequency (refer to the datasheet) has to drive the OSC_IN pin while the OSC_OUT pin can be used as GPIO. See Figure 13. 102/897 DocID022448 Rev 2 RM0313 7.2.2 Reset and clock control (RCC) HSI clock The HSI clock signal is generated from an internal 8 MHz RC Oscillator and can be used directly as a system clock or divided by 2 to be used as PLL input. The HSI RC oscillator has the advantage of providing a clock source at low cost (no external components). It also has a faster startup time than the HSE crystal oscillator however, even with calibration the frequency is less accurate than an external crystal oscillator or ceramic resonator. Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at TA=25°C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Clock control register (RCC_CR). If the application is subject to voltage or temperature variations this may affect the RC oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0] bits in the Clock control register (RCC_CR). For more details on how to measure the HSI frequency variation please refer to Section 7.2.13: Internal/external clock measurement using TIM14 on page 107. The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI RC is stable or not. At startup, the HSI RC output clock is not released until this bit is set by hardware. The HSI RC can be switched on and off using the HSION bit in the Clock control register (RCC_CR). The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 7.2.7: Clock security system (CSS) on page 105. 7.2.3 PLL The internal PLL can be used to multiply the HSI or HSE output clock frequency. Refer to Figure 11 and Clock control register (RCC_CR). The PLL configuration (selection of the input clock, and multiplication factor) must be done before enabling the PLL. Once the PLL is enabled, these parameters cannot be changed. To modify the PLL configuration, proceed as follows: 1. Disable the PLL by setting PLLON to 0. 2. Wait until PLLRDY is cleared. The PLL is now fully stopped. 3. Change the desired parameter. 4. Enable the PLL again by setting PLLON to 1. An interrupt can be generated when the PLL is ready, if enabled in the Clock interrupt register (RCC_CIR). The PLL output frequency must be set in the range 16-72 MHz. 7.2.4 LSE clock The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the advantage of providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions. DocID022448 Rev 2 103/897 138 Reset and clock control (RCC) RM0313 The LSE crystal is switched on and off using the LSEON bit in Backup domain control register (RCC_BDCR). The crystal oscillator driving strength can be changed at runtime using the LSEDRV[1:0] bits in the Backup domain control register (RCC_BDCR) to obtain the best compromise between robustness and short start-up time on one side and low power-consumption on the other. The LSERDY flag in the Backup domain control register (RCC_BDCR) indicates whether the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR). Caution: To switch ON the LSE oscillator, 4096 LSE clock pulses need to be seen by an internal stabilization counter after the LSEON bit is set. Even in the case that no crystal or resonator is connected to the device, excessive external noise on the OSC32_IN pin may still lead the oscillator to start. Once the oscillator is started, it needs another 6 LSE clock pulses to complete a switching OFF sequence. If for any reason the oscillations are no more present on the OSC_IN pin, the oscillator cannot be switched OFF, locking the OSC32 pins from any other use and introducing unwanted power consumption. The only way to recover such situation is to perform the Backup domain reset by software. External source (LSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to 1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the Backup domain control register (RCC_BDCR). The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin can be used as GPIO. See Figure 13. 7.2.5 LSI clock The LSI RC acts as a low-power clock source that can be kept running in Stop and Standby mode for the independent window watchdog (IWDG) and RTC. The clock frequency is around 40 kHz (between 30 kHz and 60 kHz). For more details, refer to the electrical characteristics section of the datasheets. The LSI RC can be switched on and off using the LSION bit in the Control/status register (RCC_CSR). The LSIRDY flag in the Control/status register (RCC_CSR) indicates if the LSI oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR). 7.2.6 System clock (SYSCLK) selection Three different clock sources can be used to drive the system clock (SYSCLK): • HSI oscillator • HSE oscillator • PLL After a system reset, the HSI oscillator is selected as system clock. When a clock source is used directly or through the PLL as a system clock, it is not possible to stop it. A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source becomes ready. Status bits in the 104/897 DocID022448 Rev 2 RM0313 Reset and clock control (RCC) Clock control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently used as a system clock. 7.2.7 Clock security system (CSS) Clock Security System can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped. If a failure is detected on the HSE clock, the HSE oscillator is automatically disabled, a clock failure event is sent to the break input of the TIM15/TIM16/TIM17 timers and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex-M4 with FPU NMI (Non-Maskable Interrupt) exception vector. Note: Once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is automatically generated. The NMI will be executed indefinitely unless the CSS interrupt pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt by setting the CSSC bit in the Clock interrupt register (RCC_CIR). If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is used as PLL input clock, and the PLL clock is used as system clock), a detected failure causes a switch of the system clock to the HSI oscillator and the disabling of the HSE oscillator. If the HSE clock (divided or not) is the clock entry of the PLL used as system clock when the failure occurs, the PLL is disabled too. 7.2.8 ADC clock The ADC clock is derived from the APB2 high speed clock divided by 2,4,6,8 (duty cycle 50%). 7.2.9 SDADC clock The SDADC clock source is derived from the system clock divided by a selectable divider with a 50% duty cycle. Possible division factors are 2, 4, 6, 8, 10, 12, 14, 16, 20, 24, 28, 32, 36, 40, 44, and 48. The SDADC clock is automatically stopped in deepsleep mode. The maximum and minimum operating frequencies of the SDAC are 6 MHz and 500 kHz, respectively. 7.2.10 RTC clock The RTCCLK clock source can be either the HSE/32, LSE or LSI clocks. This is selected by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR). This selection cannot be modified without resetting the Backup domain. The system must be always configured in a way that the PCLK frequency is greater than or equal to the RTCCLK frequency for proper operation of the RTC. DocID022448 Rev 2 105/897 138 Reset and clock control (RCC) RM0313 The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. Consequently: • If LSE is selected as RTC clock: – • If LSI is selected as the RTC clock: – • The RTC state is not guaranteed if the VDD supply is powered off. If the HSE clock divided by 32 is used as the RTC clock: – 7.2.11 The RTC continues to work even if the VDD supply is switched off, provided the VBAT supply is maintained. The RTC state is not guaranteed if the VDD supply is powered off or if the internal voltage regulator is powered off (removing power from the 1.8 V domain). Watchdog clock If the Independent watchdog (IWDG) is started by either hardware option or software access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator temporization, the clock is provided to the IWDG. 7.2.12 Clock-out capability The microcontroller clock output (MCO) capability allows the clock to be output onto the external MCO pin. The configuration registers of the corresponding GPIO port must be programmed in alternate function mode. One of 5 clock signals can be selected as the MCO clock. • LSI • LSE • SYSCLK • HSI • HSE • PLL clock divided by 2 The selection is controlled by the MCO[2:0] bits of the Clock configuration register (RCC_CFGR). 106/897 DocID022448 Rev 2 RM0313 7.2.13 Reset and clock control (RCC) Internal/external clock measurement using TIM14 It is possible to indirectly measure the frequency of all on-board clock sources by mean of the TIM14 channel 1 input capture. As represented on Figure 14. Figure 14. Frequency measurement with TIM14 in capture mode 7,0 7,B503>@ *3,2 57&&/. +6( 0&2 7, 069 The input capture channel of the Timer 14 can be a GPIO line or an internal clock of the MCU. This selection is performed through the TI1_RMP [1:0] bits in the TIM14_OR register. The possibilities available are the following ones. • TIM14 Channel1 is connected to the GPIO. Refer to the alternate function mapping in the device datasheets. • TIM14 Channel1 is connected to the RTCCLK. • TIM14 Channel1 is connected to the HSE/32 Clock. • TIM14 Channel1 is connected to the microcontroller clock output (MCO). Refer to section Section 7.2.12: Clock-out capability for MCO clock configuration. Calibration of the HSI The primary purpose of connecting the LSE, through the MCO multiplexer, to the channel 1 input capture is to be able to precisely measure the HSI system clocks (for this, the HSI should be used as the system clock source). The number of HSI clock counts between consecutive edges of the LSE signal provides a measure of the internal clock period. Taking advantage of the high precision of LSE crystals (typically a few tens of ppm’s), it is possible to determine the internal clock frequency with the same resolution, and trim the source to compensate for manufacturing-process- and/or temperature- and voltage-related frequency deviations. The HSI oscillator has dedicated user-accessible calibration bits for this purpose. The basic concept consists in providing a relative measurement (e.g. the HSI/LSE ratio): the precision is therefore closely related to the ratio between the two clock sources. The higher the ratio is, the better the measurement will be. If LSE is not available, HSE/32 will be the better option in order to reach the most precise calibration possible. Calibration of the LSI The calibration of the LSI will follow the same pattern that for the HSI, but changing the reference clock. It will be necessary to connect LSI clock to the channel 1 input capture of the TIM14. Then define the HSE as system clock source, the number of its clock counts DocID022448 Rev 2 107/897 138 Reset and clock control (RCC) RM0313 between consecutive edges of the LSI signal provides a measure of the internal low speed clock period. The basic concept consists in providing a relative measurement (e.g. the HSE/LSI ratio): the precision is therefore closely related to the ratio between the two clock sources. The higher the ratio is, the better the measurement will be. 7.3 Low power modes APB peripheral clocks and DMA clock can be disabled by software. Sleep mode stops the CPU clock. The memory interface clocks (Flash and RAM interfaces) can be stopped by software during sleep mode. The AHB to APB bridge clocks are disabled by hardware during Sleep mode when all the clocks of the peripherals connected to them are disabled. Stop mode stops all the clocks in the V18 domain and disables the PLL and the HSI, and HSE oscillators. HDMI CEC, USART1/2/3, and I2C1/2 have the capability to enable the HSI oscillator even when the MCU is in Stop mode (if HSI is selected as the clock source for that peripheral). HDMI CEC and USART1/2/3 can also be driven by the LSE oscillator when the system is in Stop mode (if LSE is selected as clock source for that peripheral) and the LSE oscillator is enabled (LSEON) but they do not have the capability to turn on the LSE oscillator. Standby mode stops all the clocks in the V18 domain and disables the PLL and the HSI, and HSE oscillators. The CPU’s deepsleep mode can be overridden for debugging by setting the DBG_STOP or DBG_STANDBY bits in the DBGMCU_CR register. When waking up from deepsleep after an interrupt (Stop mode) or reset (Standby mode), the HSI oscillator is selected as system clock. If a Flash programming operation is on going, deepsleep mode entry is delayed until the Flash interface access is finished. If an access to the APB domain is ongoing, deepsleep mode entry is delayed until the APB access is finished. 108/897 DocID022448 Rev 2 RM0313 Reset and clock control (RCC) 7.4 RCC registers Refer to Section 1.1 on page 36 for a list of abbreviations used in register descriptions. 7.4.1 Clock control register (RCC_CR) Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. PLL RDY PLLON Res. Res. Res. Res. CSS ON HSE BYP HSE RDY HSE ON r rw rw rw r rw 9 8 3 2 1 0 Res. HSI RDY HSION r rw 15 14 13 12 11 10 7 6 HSICAL[7:0] r r r r r Bits 31:26 5 4 HSITRIM[4:0] r r r rw rw rw rw rw Reserved, must be kept at reset value. Bit 25 PLLRDY: PLL clock ready flag Set by hardware to indicate that the PLL is locked. 0: PLL unlocked 1: PLL locked Bit 24 PLLON: PLL enable Set and cleared by software to enable PLL. Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the PLL clock is used as system clock or is selected to become the system clock. 0: PLL OFF 1: PLL ON Bits 23:20 Reserved, must be kept at reset value. Bit 19 CSSON: Clock security system enable Set and cleared by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. 0: Clock detector OFF 1: Clock detector ON (Clock detector ON if the HSE oscillator is ready, OFF if not). Bit 18 HSEBYP: HSE crystal oscillator bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. 0: HSE crystal oscillator not bypassed 1: HSE crystal oscillator bypassed with external clock DocID022448 Rev 2 109/897 138 Reset and clock control (RCC) RM0313 Bit 17 HSERDY: HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. This bit needs 6 cycles of the HSE oscillator clock to fall down after HSEON reset. 0: HSE oscillator not ready 1: HSE oscillator ready Bit 16 HSEON: HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. 0: HSE oscillator OFF 1: HSE oscillator ON Bits 15:8 HSICAL[7:0]: HSI clock calibration These bits are initialized automatically at startup. Bits 7:3 HSITRIM[4:0]: HSI clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI. The default value is 16, which, when added to the HSICAL value, should trim the HSI to 8 MHz ± 1%. The trimming step (Fhsitrim) is around 40 kHz between two consecutive HSICAL steps. Bit 2 Reserved, must be kept at reset value. Bit 1 HSIRDY: HSI clock ready flag Set by hardware to indicate that HSI oscillator is stable. After the HSION bit is cleared, HSIRDY goes low after 6 HSI oscillator clock cycles. 0: HSI oscillator not ready 1: HSI oscillator ready Bit 0 HSION: HSI clock enable Set and cleared by software. Set by hardware to force the HSI oscillator ON when leaving Stop or Standby mode or in case of failure of the HSE crystal oscillator used directly or indirectly as system clock. This bit cannot be reset if the HSI is used directly or indirectly as system clock or is selected to become the system clock. 0: HSI oscillator OFF 1: HSI oscillator ON 110/897 DocID022448 Rev 2 RM0313 Reset and clock control (RCC) 7.4.2 Clock configuration register (RCC_CFGR) Address offset: 0x04 Reset value: 0x0000 0000 Access: 0 ≤ wait state ≤ 2, word, half-word and byte access 1 or 2 wait states inserted only if the access occurs during clock source switch. 31 30 29 28 27 26 SDPRE[4:0] 25 24 MCO[2:0] rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 ADCPRE[1:0] rw rw PPRE2[2:0] rw rw 23 22 Res. USBP RE rw rw rw 20 rw 18 PLLMUL[3:0] 17 16 PLL XTPRE PLL SRC rw rw rw rw rw rw 6 5 4 3 2 1 0 HPRE[3:0] rw 19 rw 7 PPRE1[2:0] 21 rw DocID022448 Rev 2 rw SWS[1:0] rw r r SW[1:0] rw rw 111/897 138 Reset and clock control (RCC) RM0313 Bits 31:27 SDPRE[4:0]: SDADC prescaler These bits are set and reset by software to control AHB clocks division factor. 0xxxx: system clock divided by 2 10000: system clock divided by 2 10001: system clock divided by 4 10010: system clock divided by 6 10011: system clock divided by 8 10100: system clock divided by 10 10101: system clock divided by 12 10110: system clock divided by 14 10111: system clock divided by 16 11000: system clock divided by 20 11001: system clock divided by 24 11010: system clock divided by 28 11011: system clock divided by 32 11100: system clock divided by 36 11101: system clock divided by 40 11110: system clock divided by 44 11111: system clock divided by 48 Bits 26:24 MCO[2:0]: Microcontroller clock output Set and cleared by software. 000: MCO output disabled, no clock on MCO 001: Reserved 010: LSI clock selected 011: LSE clock selected 100: System clock (SYSCLK) selected 101: HSI clock selected 110: HSE clock selected 111: PLL clock divided by 2 selected Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. Bits 23 Reserved, must be kept at reset value. Bit 22 USBPRE: USB prescaler This bit is set and reset by software to generate the 48 MHz USB clock. They must be valid before enabling USB clocks. 0: PLL clock is divided by 1,5 1: PLL clock is not divided 112/897 DocID022448 Rev 2 RM0313 Reset and clock control (RCC) Bits 21:18 PLLMUL[3:0]: PLL multiplication factor These bits are written by software to define the PLL multiplication factor. These bits can be written only when PLL is disabled. Caution: The PLL output frequency must not exceed 72 MHz. 0000: PLL input clock x 2 0001: PLL input clock x 3 0010: PLL input clock x 4 0011: PLL input clock x 5 0100: PLL input clock x 6 0101: PLL input clock x 7 0110: PLL input clock x 8 0111: PLL input clock x 9 1000: PLL input clock x 10 1001: PLL input clock x 11 1010: PLL input clock x 12 1011: PLL input clock x 13 1100: PLL input clock x 14 1101: PLL input clock x 15 1110: PLL input clock x 16 1111: PLL input clock x 16 Bit 17 PLLXTPRE: HSE divider for PLL input clock This bits is set and cleared by software to select the HSE division factor for the PLL. It can be written only when the PLL is disabled. 0000: HSE input to PLL not divided 0001: HSE input to PLL divided by 2 Note: This bit is the same as the LSB of PREDIV in Clock configuration register 2 (RCC_CFGR2) (for compatibility with other STM32 products) Bit 16 PLLSRC: PLL entry clock source Set and cleared by software to select PLL clock source. This bit can be written only when PLL is disabled. 0: HSI/2 selected as PLL input clock 1: HSE/PREDIV selected as PLL input clock (refer to Section 7.4.12: Clock configuration register 2 (RCC_CFGR2) on page 134 Bits 15:14 ADCPRE[1:0]: ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. 00: PCLK divided by 2 01: PCLK divided by 4 10: PCLK divided by 6 11: PCLK divided by 8 Bits 13:11 PPRE2[2:0]: APB high speed prescaler (APB2) These bits are set and reset by software to control the high speed APB clock division factor. 0xx: AHB clock not divided 100: AHB clock divided by 2 101: AHB clock divided by 4 110: AHB clock divided by 8 111: AHB clock divided by 16 DocID022448 Rev 2 113/897 138 Reset and clock control (RCC) RM0313 Bits 10:8 PPRE1[2:0]: APB low speed prescaler (APB1) These bits are set and cleared by software to control the low speed APB clock division factor. 0xx: APB1 clock not divided 100: APB1 divided by 2 101: APB1 divided by 4 110: APB1 divided by 8 111: APB1 divided by 16 Bits 7:4 HPRE[3:0]: AHB prescaler Set and cleared by software to control the division factor of the AHB clock. 0xxx: SYSCLK not divided 1000: SYSCLK divided by 2 1001: SYSCLK divided by 4 1010: SYSCLK divided by 8 1011: SYSCLK divided by 16 1100: SYSCLK divided by 64 1101: SYSCLK divided by 128 1110: SYSCLK divided by 256 1111: SYSCLK divided by 512 Note: The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB clock. Refer to section Read operations on page 49 for more details. Bits 3:2 SWS[1:0]: System clock switch status Set and cleared by hardware to indicate which clock source is used as system clock. 00: HSI oscillator used as system clock 01: HSE oscillator used as system clock 10: PLL used as system clock 11: not applicable Bits 1:0 SW[1:0]: System clock switch Set and cleared by software to select SYSCLK source. Cleared by hardware to force HSI selection when leaving Stop and Standby mode or in case of failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security System is enabled). 00: HSI selected as system clock 01: HSE selected as system clock 10: PLL selected as system clock 11: not allowed 114/897 DocID022448 Rev 2 RM0313 Reset and clock control (RCC) 7.4.3 Clock interrupt register (RCC_CIR) Address offset: 0x08 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. CSSC Res. Res. PLL RDYC HSE RDYC HSI RDYC LSE RDYC LSI RDYC w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. PLL RDYIE HSE RDYIE HSI RDYIE LSE RDYIE LSI RDYIE CSSF Res. Res. PLL RDYF HSE RDYF HSI RDYF LSE RDYF LSI RDYF rw rw rw rw rw r r r r r r w Bits 31:24 Reserved, must be kept at reset value. Bit 23 CSSC: Clock security system interrupt clear This bit is set by software to clear the CSSF flag. 0: No effect 1: Clear CSSF flag Bit 22 Reserved, must be kept at reset value. Bit 21 Reserved, must be kept at reset value. Bit 20 PLLRDYC: PLL ready interrupt clear This bit is set by software to clear the PLLRDYF flag. 0: No effect 1: Clear PLLRDYF flag Bit 19 HSERDYC: HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag. 0: No effect 1: Clear HSERDYF flag Bit 18 HSIRDYC: HSI ready interrupt clear This bit is set software to clear the HSIRDYF flag. 0: No effect 1: Clear HSIRDYF flag Bit 17 LSERDYC: LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag. 0: No effect 1: LSERDYF cleared Bit 16 LSIRDYC: LSI ready interrupt clear This bit is set by software to clear the LSIRDYF flag. 0: No effect 1: LSIRDYF cleared Bits 15:13 Reserved, must be kept at reset value. DocID022448 Rev 2 115/897 138 Reset and clock control (RCC) RM0313 Bit 12 PLLRDYIE: PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL lock. 0: PLL lock interrupt disabled 1: PLL lock interrupt enabled Bit 11 HSERDYIE: HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization. 0: HSE ready interrupt disabled 1: HSE ready interrupt enabled Bit 10 HSIRDYIE: HSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization. 0: HSI ready interrupt disabled 1: HSI ready interrupt enabled Bit 9 LSERDYIE: LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization. 0: LSE ready interrupt disabled 1: LSE ready interrupt enabled Bit 8 LSIRDYIE: LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization. 0: LSI ready interrupt disabled 1: LSI ready interrupt enabled Bit 7 CSSF: Clock security system interrupt flag Set by hardware when a failure is detected in the HSE oscillator. Cleared by software setting the CSSC bit. 0: No clock security interrupt caused by HSE clock failure 1: Clock security interrupt caused by HSE clock failure Bit 6:5 Reserved, must be kept at reset value. Bit 4 PLLRDYF: PLL ready interrupt flag Set by hardware when the PLL locks and PLLRDYDIE is set. Cleared by software setting the PLLRDYC bit. 0: No clock ready interrupt caused by PLL lock 1: Clock ready interrupt caused by PLL lock Bit 3 HSERDYF: HSE ready interrupt flag Set by hardware when the HSE clock becomes stable and HSERDYDIE is set. Cleared by software setting the HSERDYC bit. 0: No clock ready interrupt caused by the HSE oscillator 1: Clock ready interrupt caused by the HSE oscillator 116/897 DocID022448 Rev 2 RM0313 Reset and clock control (RCC) Bit 2 HSIRDYF: HSI ready interrupt flag Set by hardware when the HSI clock becomes stable and HSIRDYDIE is set in a response to setting the HSION (refer to Clock control register (RCC_CR)). When HSION is not set but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Cleared by software setting the HSIRDYC bit. 0: No clock ready interrupt caused by the HSI oscillator 1: Clock ready interrupt caused by the HSI oscillator Bit 1 LSERDYF: LSE ready interrupt flag Set by hardware when the LSE clock becomes stable and LSERDYDIE is set. Cleared by software setting the LSERDYC bit. 0: No clock ready interrupt caused by the LSE oscillator 1: Clock ready interrupt caused by the LSE oscillator Bit 0 LSIRDYF: LSI ready interrupt flag Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set. Cleared by software setting the LSIRDYC bit. 0: No clock ready interrupt caused by the LSI oscillator 1: Clock ready interrupt caused by the LSI oscillator 7.4.4 APB2 peripheral reset register (RCC_APB2RSTR) Address offset: 0x0C Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. SDAD3 RST SDAD2 RST SDAD1 RST Res. Res. Res. Res. TIM19 RST TIM17 RST TIM16 RST TIM15 RST rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. USART1 RST Res. SPI1 RST Res. Res. ADC RST Res. Res. Res. Res. Res. Res. Res. Res. SYS CFG RST rw rw Bits 31:27 rw rw Reserved, must be kept at reset value. Bit 26 SDAD3RST: SDADC3 (Sigma delta ADC 3) reset This bit is set and reset by software. 0: does not reset the SDADC3 1: resets the SDADC3 Bit 25 SDAD2RST: SDADC2 (Sigma delta ADC 2) reset This bit is set and reset by software. 0: does not reset the SDADC2 1: resets the SDADC2 DocID022448 Rev 2 117/897 138 Reset and clock control (RCC) RM0313 Bit 24 SDAD1RST: SDADC1 (Sigma delta ADC 1) reset This bit is set and reset by software. 0: does not reset the SDADC1 1: resets the SDADC1 Bits 22:20 Reserved, must be kept at reset value. Bit 19 TIM19RST: TIM19 timer reset Set and cleared by software. 0: No effect 1: Reset TIM19 timer Bit 18 TIM17RST: TIM17 timer reset Set and cleared by software. 0: No effect 1: Reset TIM17 timer Bit 17 TIM16RST: TIM16 timer reset Set and cleared by software. 0: No effect 1: Reset TIM16 timer Bit 16 TIM15RST: TIM15 timer reset Set and cleared by software. 0: No effect 1: Reset TIM15 timer Bit 15 Reserved, must be kept at reset value. Bit 14 USART1RST: USART1 reset Set and cleared by software. 0: No effect 1: Reset USART1 Bit 13 Reserved, must be kept at reset value. Bit 12 SPI1RST: SPI1 reset Set and cleared by software. 0: No effect 1: Reset SPI1 Bit 11:10 Reserved, must be kept at reset value. Bit 9 ADCRST: ADC interface reset Set and cleared by software. 0: No effect 1: Reset ADC interface Bits 8:1 Bit 0 118/897 Reserved, must be kept at reset value. SYSCFGRST: SYSCFG reset Set and cleared by software. 0: No effect 1: Reset all SYSCFG registers except for SYSCFG_CFGR2 DocID022448 Rev 2 RM0313 7.4.5 Reset and clock control (RCC) APB1 peripheral reset register (RCC_APB1RSTR) Address offset: 0x10 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. CECR ST DAC1 RST PWR RST Res. DAC2 RST CAN RST Res. USB RST I2C2 RST I2C1 RST Res. Res. USART3 RST USART 2RST Res. rw rw rw rw rw rw rw rw rw rw 13 12 11 Res. WWD GRST 15 14 SPI3 RST SPI2 RST rw rw Res. rw 10 9 8 7 6 5 4 3 2 1 0 Res. TIM18 RST TIM14 RST TIM13 RST TIM12 RST TIM7 RST TIM6 RST TIM5 RST TIM4 RST TIM3 RST TIM2 RST rw rw rw rw rw rw rw rw rw rw Bit 31 Reserved, must be kept at reset value. Bit 30 CECRST HDMI CEC reset Set and cleared by software. 0: No effect 1: Reset HDMI CEC Bit 29 DAC1RST: DAC1 interface reset Set and cleared by software. 0: No effect 1: Reset DAC1 interface Bit 28 PWRRST: Power interface reset Set and cleared by software. 0: No effect 1: Reset power interface Bit 27 Reserved, must be kept at reset value. Bit 26 DAC2RST: DAC2 interface reset Set and cleared by software. 0: No effect 1: Reset DAC2 interface Bit 25 CANRST: CAN interface reset Set and cleared by software. 0: No effect 1: Reset CAN interface Bit 24 Reserved, must be kept at reset value. Bit 23 USBRST: USB interface reset Set and cleared by software. 0: No effect 1: Reset USB interface DocID022448 Rev 2 119/897 138 Reset and clock control (RCC) RM0313 Bit 22 I2C2RST: I2C2 reset Set and cleared by software. 0: No effect 1: Reset I2C2 Bit 21 I2C1RST: I2C1 reset Set and cleared by software. 0: No effect 1: Reset I2C1 Bits 20:19 Reserved, must be kept at reset value. Bit 18 USART3RST: USART3 reset Set and cleared by software. 0: No effect 1: Reset USART3 Bit 17 USART2RST: USART2 reset Set and cleared by software. 0: No effect 1: Reset USART2 Bit 16 Reserved, must be kept at reset value. Bit 15 SPI3RST: SPI3 reset Set and cleared by software. 0: No effect 1: Reset SPI3 Bit 14 SPI2RST: SPI2 reset Set and cleared by software. 0: No effect 1: Reset SPI2 Bits 13:12 Reserved, must be kept at reset value. Bit 11 WWDGRST: Window watchdog reset Set and cleared by software. 0: No effect 1: Reset window watchdog Bit 10 Reserved, must be kept at reset value. Bit 9 TIM18RST: TIM18 timer reset Set and cleared by software. 0: No effect 1: Reset TIM18 Bit 8 TIM14RST: TIM14 timer reset Set and cleared by software. 0: No effect 1: Reset TIM14 Bit 7 TIM13RST: TIM13 timer reset Set and cleared by software. 0: No effect 1: Reset TIM13 120/897 DocID022448 Rev 2 RM0313 Reset and clock control (RCC) Bit 6 TIM12RST: TIM12 timer reset Set and cleared by software. 0: No effect 1: Reset TIM12 Bit 5 TIM7RST: TIM7 timer reset Set and cleared by software. 0: No effect 1: Reset TIM7 Bit 4 TIM6RST: TIM6 timer reset Set and cleared by software. 0: No effect 1: Reset TIM6 Bit 3 TIM5RST: TIM5 timer reset Set and cleared by software. 0: No effect 1: Reset TIM5 Bit 2 TIM4RST: TIM4 timer reset Set and cleared by software. 0: No effect 1: Reset TIM4 Bit 1 TIM3RST: TIM3 timer reset Set and cleared by software. 0: No effect 1: Reset TIM3 Bit 0 TIM2RST: TIM2 timer reset Set and cleared by software. 0: No effect 1: Reset TIM2 7.4.6 AHB peripheral clock enable register (RCC_AHBENR) Address offset: 0x14 Reset value: 0x0000 0014 Access: no wait state, word, half-word and byte access Note: When the peripheral clock is not active, the peripheral register values may not be readable by software and the returned value is always 0x0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. TSCEN Res. IOPFE N IOPE EN IOPD EN IOPC EN IOPB EN IOPA EN Res. rw rw rw rw rw rw 7 6 5 4 3 2 1 0 Res. CRCE N Res. FLITF EN Res. SRAM EN DMA2 EN DMA EN rw rw rw rw 15 Res. 14 Res. 13 Res. 12 Res. 11 Res. 10 Res. 9 8 Res. Res. rw DocID022448 Rev 2 rw 121/897 138 Reset and clock control (RCC) RM0313 Bits 31:25 Reserved, must be kept at reset value. Bit 24 TSCEN: Touch sensing controller clock enable Set and cleared by software. 0: TSC clock disabled 1: TSC clock enabled Bit 23 Reserved, must be kept at reset value. Bit 22 IOPFEN: I/O port F clock enable Set and cleared by software. 0: I/O port F clock disabled 1: I/O port F clock enabled Bit 21 IOPEEN: I/O port E clock enable Set and cleared by software. 0: I/O port E clock disabled 1: I/O port E clock enabled Bit 20 IOPDEN: I/O port D clock enable Set and cleared by software. 0: I/O port D clock disabled 1: I/O port D clock enabled Bit 19 IOPCEN: I/O port C clock enable Set and cleared by software. 0: I/O port C clock disabled 1: I/O port C clock enabled Bit 18 IOPBEN: I/O port B clock enable Set and cleared by software. 0: I/O port B clock disabled 1: I/O port B clock enabled Bit 17 IOPAEN: I/O port A clock enable Set and cleared by software. 0: I/O port A clock disabled 1: I/O port A clock enabled Bits 16:7 Reserved, must be kept at reset value. Bit 6 CRCEN: CRC clock enable Set and cleared by software. 0: CRC clock disabled 1: CRC clock enabled Bit 5 Reserved, must be kept at reset value. Bit 4 FLITFEN: FLITF clock enable Set and cleared by software to disable/enable FLITF clock during Sleep mode. 0: FLITF clock disabled during Sleep mode 1: FLITF clock enabled during Sleep mode Bit 3 Reserved, must be kept at reset value. 122/897 DocID022448 Rev 2 RM0313 Reset and clock control (RCC) Bit 2 SRAMEN: SRAM interface clock enable Set and cleared by software to disable/enable SRAM interface clock during Sleep mode. 0: SRAM interface clock disabled during Sleep mode. 1: SRAM interface clock enabled during Sleep mode Bit 1 DMA2EN: DMA2 clock enable Set and cleared by software. 0: DMA2 clock disabled 1: DMA2 clock enabled Bit 0 DMAEN: DMA clock enable Set and cleared by software. 0: DMA clock disabled 1: DMA clock enabled 7.4.7 APB2 peripheral clock enable register (RCC_APB2ENR) Address: 0x18 Reset value: 0x0000 0000 Access: word, half-word and byte access No wait states, except if the access occurs while an access to a peripheral in the APB domain is on going. In this case, wait states are inserted until the access to APB peripheral is finished. When the peripheral clock is not active, the peripheral register values may not be readable by software and the returned value is always 0x0. Note: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. SDAD C3EN SDAD C2EN SDAD C1EN Res. DBGM CUEN Res. Res. TIM19 EN TIM17 EN TIM16 EN TIM15 EN rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. USAR T1EN Res. SPI1 EN Res. Res. ADC EN Res. Res. Res. Res. Res. Res. Res. Res. SYS CFG EN rw rw rw rw Bits 31:27 Reserved, must be kept at reset value. Bit 26 SDADC3: SDADC3 (Sigma Delta ADC 3) clock enable Set and reset by software. 0: SDADC3 clock disabled 1: SDADC3 clock enabled Bit 25 SDADC2: SDADC2 (Sigma Delta ADC 2) clock enable Set and reset by software. 0: SDADC2 clock disabled 1: SDADC2 clock enabled DocID022448 Rev 2 123/897 138 Reset and clock control (RCC) RM0313 Bit 24 SDADC1: SDADC1 (Sigma Delta ADC 1) clock enable Set and reset by software. 0: SDADC1 clock disabled 1: SDADC1 clock enabled Bit 23:22 Reserved, must be kept at reset value. Bits 21:20 Reserved, must be kept at reset value. Bit 19 TIM19EN: TIM19 timer clock enable Set and cleared by software. 0: TIM19 timer clock disabled 1: TIM19 timer clock enabled Bit 18 TIM17EN: TIM17 timer clock enable Set and cleared by software. 0: TIM17 timer clock disabled 1: TIM17 timer clock enabled Bit 17 TIM16EN: TIM16 timer clock enable Set and cleared by software. 0: TIM16 timer clock disabled 1: TIM16 timer clock enabled Bit 16 TIM15EN: TIM15 timer clock enable Set and cleared by software. 0: TIM15 timer clock disabled 1: TIM15 timer clock enabled Bit 15 Reserved, must be kept at reset value. Bit 14 USART1EN: USART1clock enable Set and cleared by software. 0: USART1clock disabled 1: USART1clock enabled Bit 13 Reserved, must be kept at reset value. Bit 12 SPI1EN: SPI1 clock enable Set and cleared by software. 0: SPI1 clock disabled 1: SPI1 clock enabled Bit 11 Reserved, must be kept at reset value. Bit 10 Reserved, must be kept at reset value. Bit 9 ADCEN: ADC interface clock enable Set and cleared by software. 0: ADC interface disabled 1: ADC interface clock enabled Bits 8:1 Reserved, must be kept at reset value. Bit 0 SYSCFGEN: SYSCFG clock enable Set and cleared by software. 0: SYSCFG clock disabled 1: SYSCFG clock enabled 124/897 DocID022448 Rev 2 RM0313 7.4.8 Reset and clock control (RCC) APB1 peripheral clock enable register (RCC_APB1ENR) Address: 0x1C Reset value: 0x0000 0000 Access: word, half-word and byte access No wait state, except if the access occurs while an access to a peripheral on APB1 domain is on going. In this case, wait states are inserted until this access to APB1 peripheral is finished. When the peripheral clock is not active, the peripheral register values may not be readable by software and the returned value is always 0x0. Note: 31 30 29 28 27 26 25 24 23 22 21 20 19 Res. CEC EN DAC1 EN PWR EN Res. DAC2 EN CAN EN Res. USB EN I2C2 EN I2C1 EN Res. Res. rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPI3 EN SPI2 EN Res. Res. WWD GEN Res. TIM18 EN TIM14 EN TIM13 EN TIM12 EN TIM7 EN TIM6 EN TIM5 EN TIM4 EN TIM3 EN TIM2 EN rw rw rw rw rw rw rw rw rw rw rw rw rw 18 17 16 USART3 USART2 EN EN Res. Bit 31 Reserved, must be kept at reset value. Bit 30 CECEN: HDMI CEC interface clock enable Set and cleared by software. 0: HDMI CEC clock disabled 1: HDMI CEC clock enabled Bit 29 DAC1EN: DAC1 interface clock enable Set and cleared by software. 0: DAC1 interface clock disabled 1: DAC1 interface clock enabled Bit 28 PWREN: Power interface clock enable Set and cleared by software. 0: Power interface clock disabled 1: Power interface clock enabled Bit 27 Reserved, must be kept at reset value. Bit 26 DAC2EN: DAC2 interface clock enable Set and cleared by software. 0: DAC2 interface clock disabled 1: DAC2 interface clock enabled Bit 25 CANEN: CAN interface clock enable Set and cleared by software. 0: CAN interface clock disabled 1: CAN interface clock enabled Bit 24 Reserved, must be kept at reset value. DocID022448 Rev 2 125/897 138 Reset and clock control (RCC) RM0313 Bit 23 USBEN: USB interface clock enable Set and cleared by software. 0: USB interface clock disabled 1: USB interface clock enabled Bit 22 I2C2EN: I2C2 clock enable Set and cleared by software. 0: I2C2 clock disabled 1: I2C2 clock enabled Bit 21 I2C1EN: I2C1 clock enable Set and cleared by software. 0: I2C1 clock disabled 1: I2C1 clock enabled Bits 20:18 Reserved, must be kept at reset value. Bit 17 USART2EN: USART2 clock enable Set and cleared by software. 0: USART2 clock disabled 1: USART2 clock enabled Bit 16 Reserved, must be kept at reset value. Bit 15 SPI3EN: SPI3 clock enable Set and cleared by software. 0: SPI3 clock disabled 1: SPI3 clock enabled Bit 14 SPI2EN: SPI2 clock enable Set and cleared by software. 0: SPI2 clock disabled 1: SPI2 clock enabled Bits 13:12 Reserved, must be kept at reset value. Bit 11 WWDGEN: Window watchdog clock enable Set and cleared by software. 0: Window watchdog clock disabled 1: Window watchdog clock enabled Bit 10 Reserved, must be kept at reset value. Bit 9 TIM18EN: TIM18 timer clock enable Set and cleared by software. 0: TIM18 clock disabled 1: TIM18 clock enabled Bit 8 TIM14EN: TIM14 timer clock enable Set and cleared by software. 0: TIM14 clock disabled 1: TIM14 clock enabled Bit 7 TIM13EN: TIM13 timer clock enable Set and cleared by software. 0: TIM13 clock disabled 1: TIM13 clock enabled 126/897 DocID022448 Rev 2 RM0313 Reset and clock control (RCC) Bit 6 TIM12EN: TIM12 timer clock enable Set and cleared by software. 0: TIM12 clock disabled 1: TIM12 clock enabled Bit 5 TIM7EN: TIM7 timer clock enable Set and cleared by software. 0: TIM7 clock disabled 1: TIM7 clock enabled Bit 4 TIM6EN: TIM6 timer clock enable Set and cleared by software. 0: TIM6 clock disabled 1: TIM6 clock enabled Bit 3 TIM5EN: TIM5 timer clock enable Set and cleared by software. 0: TIM5 clock disabled 1: TIM5 clock enabled Bit 2 TIM4EN: TIM4 timer clock enable Set and cleared by software. 0: TIM4 clock disabled 1: TIM4 clock enabled Bit 1 TIM3EN: TIM3 timer clock enable Set and cleared by software. 0: TIM3 clock disabled 1: TIM3 clock enabled Bit 0 TIM2EN: TIM2 timer clock enable Set and cleared by software. 0: TIM2 clock disabled 1: TIM2 clock enabled DocID022448 Rev 2 127/897 138 Reset and clock control (RCC) 7.4.9 RM0313 Backup domain control register (RCC_BDCR) Address offset: 0x20 Reset value: 0x0000 0000, reset by Backup domain Reset. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register. Note: The LSEON, LSEBYP, RTCSEL and RTCEN bits of the Backup domain control register (RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are writeprotected and the DBP bit in the Power control register (PWR_CR) has to be set before these can be modified. Refer to Section 6.1.2 on page 80 for further information. These bits are only reset after a Backup domain Reset (see Section 7.1.3: Backup domain reset). Any internal or external Reset will not have any effect on these bits. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BDRST rw 15 14 13 12 11 10 RTC EN Res. Res. Res. Res. Res. rw 9 8 RTCSEL[1:0] rw 7 6 5 Res. Res. Res. rw 4 3 LSEDRV[1:0] rw rw 2 1 0 LSE BYP LSE RDY LSEON rw r rw Bits 31:17 Reserved, must be kept at reset value. Bit 16 BDRST: Backup domain software reset Set and cleared by software. 0: Reset not activated 1: Resets the entire Backup domain Bit 15 RTCEN: RTC clock enable Set and cleared by software. 0: RTC clock disabled 1: RTC clock enabled Bits 14:10 Reserved, must be kept at reset value. Bits 9:8 RTCSEL[1:0]: RTC clock source selection Set by software to select the clock source for the RTC. Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit can be used to reset them. 00: No clock 01: LSE oscillator clock used as RTC clock 10: LSI oscillator clock used as RTC clock 11: HSE oscillator clock divided by 32 used as RTC clock Bits 7:5 Reserved, must be kept at reset value. 128/897 DocID022448 Rev 2 RM0313 Reset and clock control (RCC) Bits 3:3 LSEDRV LSE oscillator drive capability Set and reset by software to modulate the LSE oscillator’s drive capability. A reset of the backup domain restores the default value. 00: ‘Xtal mode’ lower driving capability 01: ‘Xtal mode’ medium low driving capability 10: ‘Xtal mode’ medium high driving capability 11: ‘Xtal mode’ higher driving capability (reset value) Note: The oscillator is in Xtal mode when it is not in bypass mode. Bit 2 LSEBYP: LSE oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled. 0: LSE oscillator not bypassed 1: LSE oscillator bypassed Bit 1 LSERDY: LSE oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after 6 external lowspeed oscillator clock cycles. 0: LSE oscillator not ready 1: LSE oscillator ready Bit 0 LSEON: LSE oscillator enable Set and cleared by software. 0: LSE oscillator OFF 1: LSE oscillator ON DocID022448 Rev 2 129/897 138 Reset and clock control (RCC) 7.4.10 RM0313 Control/status register (RCC_CSR) Address: 0x24 Reset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LPWR RSTF WWDG RSTF I WDG RSTF SFT RSTF POR RSTF PIN RSTF OB LRSTF RMVF Res. Res. Res. Res. Res. Res. Res. Res. rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LSI RDY LSION r rw Bit 31 LPWRRSTF: Low-power reset flag Set by hardware when a Low-power management reset occurs. Cleared by writing to the RMVF bit. 0: No Low-power management reset occurred 1: Low-power management reset occurred For further information on Low-power management reset, refer to Low-power management reset. Bit 30 WWDGRSTF: Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by writing to the RMVF bit. 0: No window watchdog reset occurred 1: Window watchdog reset occurred Bit 29 IWDGRSTF: Independent window watchdog reset flag Set by hardware when an independent watchdog reset from VDD domain occurs. Cleared by writing to the RMVF bit. 0: No watchdog reset occurred 1: Watchdog reset occurred Bit 28 SFTRSTF: Software reset flag Set by hardware when a software reset occurs. Cleared by writing to the RMVF bit. 0: No software reset occurred 1: Software reset occurred Bit 27 PORRSTF: POR/PDR reset flag Set by hardware when a POR/PDR reset occurs. Cleared by writing to the RMVF bit. 0: No POR/PDR reset occurred 1: POR/PDR reset occurred 130/897 DocID022448 Rev 2 RM0313 Reset and clock control (RCC) Bit 26 PINRSTF: PIN reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by writing to the RMVF bit. 0: No reset from NRST pin occurred 1: Reset from NRST pin occurred Bit 25 OBLRSTF: Option byte loader reset flag Set by hardware when a reset from the OBL occurs. Cleared by writing to the RMVF bit. 0: No reset from OBL occurred 1: Reset from OBL occurred Bit 24 RMVF: Remove reset flag Set by software to clear the reset flags. 0: No effect 1: Clear the reset flags Bits 23:2 Reserved, must be kept at reset value. Bit 1 LSIRDY: LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. 0: LSI oscillator not ready 1: LSI oscillator ready Bit 0 LSION: LSI oscillator enable Set and cleared by software. 0: LSI oscillator OFF 1: LSI oscillator ON DocID022448 Rev 2 131/897 138 Reset and clock control (RCC) 7.4.11 RM0313 AHB peripheral reset register (RCC_AHBRSTR) Address: 0x28 Reset value: 0x0000 0000 Access: no wait states, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. TSC RST Res. IOPF RST IOPE RST IOPD RST IOPC RST IOPB RST IOPA RST Res. rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:25 Reserved, must be kept at reset value. Bit 24 TSCRST: Touch sensing controller reset Set and cleared by software. 0: No effect 1: Reset TSC Bit 23 Reserved, must be kept at reset value. Bit 22 IOPFRST: I/O port F reset Set and cleared by software. 0: No effect 1: Reset I/O port F Bit 21 IOPERST: I/O port E reset Set and cleared by software. 0: No effect 1: Reset I/O port E Bit 20 IOPDRST: I/O port D reset Set and cleared by software. 0: No effect 1: Reset I/O port D Bit 19 IOPCRST: I/O port C reset Set and cleared by software. 0: No effect 1: Reset I/O port C 132/897 DocID022448 Rev 2 RM0313 Reset and clock control (RCC) Bit 18 IOPBRST: I/O port B reset Set and cleared by software. 0: No effect 1: Reset I/O port B Bit 17 IOPARST: I/O port A reset Set and cleared by software. 0: No effect 1: Reset I/O port A Bits 16:0 Reserved, must be kept at reset value. DocID022448 Rev 2 133/897 138 Reset and clock control (RCC) 7.4.12 RM0313 Clock configuration register 2 (RCC_CFGR2) Address: 0x2C Reset value: 0x0000 0000 Access: no wait states, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PREDIV[3:0] rw rw rw rw Bits 31:4 Reserved, must be kept at reset value. Bits 3:0 PREDIV[3:0] PREDIV division factor These bits are set and cleared by software to select PREDIV1 division factor. They can be written only when the PLL is disabled. Note: Bit 0 is the same bit as bit17 in Clock configuration register (RCC_CFGR), so modifying bit17 Clock configuration register (RCC_CFGR) also modifies bit 0 in Clock configuration register 2 (RCC_CFGR2) (for compatibility with other STM32 products) 0000: HSE input to PLL not divided 0001: HSE input to PLL divided by 2 0010: HSE input to PLL divided by 3 0011: HSE input to PLL divided by 4 0100: HSE input to PLL divided by 5 0101: HSE input to PLL divided by 6 0110: HSE input to PLL divided by 7 0111: HSE input to PLL divided by 8 1000: HSE input to PLL divided by 9 1001: HSE input to PLL divided by 10 1010: HSE input to PLL divided by 11 1011: HSE input to PLL divided by 12 1100: HSE input to PLL divided by 13 1101: HSE input to PLL divided by 14 1110: HSE input to PLL divided by 15 1111: HSE input to PLL divided by 16 134/897 DocID022448 Rev 2 RM0313 Reset and clock control (RCC) 7.4.13 Clock configuration register 3 (RCC_CFGR3) Address: 0x30 Reset value: 0x0000 0000 Access: no wait states, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. CEC SW I2C2 SW I2C1 SW Res. Res. rw rw rw USART3SW[1:0] 17 16 USART2SW[1:0] USART1SW[1:0] rw rw Bits 31:20 Reserved, must be kept at reset value. Bits 19:18 USART3SW[1:0]: USART3 clock source selection This bit is set and cleared by software to select the USART3 clock source. 00: PCLK selected as USART3 clock source (default) 01: System clock (SYSCLK) selected as USART3 clock 10: LSE clock selected as USART3 clock 11: HSI clock selected as USART3 clock Bits 17:16 USART2SW[1:0]: USART2 clock source selection This bit is set and cleared by software to select the USART2 clock source. 00: PCLK selected as USART2 clock source (default) 01: System clock (SYSCLK) selected as USART2 clock 10: LSE clock selected as USART2 clock 11: HSI clock selected as USART2 clock Bits 15:7 Reserved, must be kept at reset value. Bit 6 CECSW: HDMI CEC clock source selection This bit is set and cleared by software to select the CEC clock source. 0: HSI clock, divided by 244, selected as CEC clock (default) 1: LSE clock selected as CEC clock Bit 5 I2C2SW: I2C2 clock source selection This bit is set and cleared by software to select the I2C2 clock source. 0: HSI clock selected as I2C2 clock source (default) 1: System clock (SYSCLK) selected as I2C2 clock DocID022448 Rev 2 135/897 138 Reset and clock control (RCC) RM0313 Bit 4 I2C1SW: I2C1 clock source selection This bit is set and cleared by software to select the I2C1 clock source. 0: HSI clock selected as I2C1 clock source (default) 1: System clock (SYSCLK) selected as I2C1 clock Bits 3:2 Reserved, must be kept at reset value. Bits 1:0 USART1SW[1:0]: USART1 clock source selection This bit is set and cleared by software to select the USART1 clock source. 00: PCLK selected as USART1 clock source (default) 01: System clock (SYSCLK) selected as USART1 clock 10: LSE clock selected as USART1 clock 11: HSI clock selected as USART1 clock 136/897 DocID022448 Rev 2 0x20 RCC_BDCR 0 0 0 0 DocID022448 Rev 2 0 0 0 0 TIM18EN TIM14EN TIM13EN 0 0 0 0 RTC SEL [1:0] 0 0 0 0 TIM5EN TIM4EN TIM3EN TIM2EN 0 0 0 0 LSE DRV [1:0] LSERDY LSEON TIM2RST 0 1 0 0 0 0 0 DMAEN 0 1 0 0 SYSCFGEN TIM3RST 0 DMA2EN TIM4RST 0 Res. TIM5RST 0 Res. HSIRDYF LSERDYF LSIRDYF 0 0 0 0 0 Res. SYSCFGRST 0 HSERDYF 0 Res. 0 Res. 0 Res. HSION Res. HSIRDY HPRE[3:0] SRAMEN 0 PLLRDYF 0 Res. HSITRIM[4:0] Res. TM6RST 0 FLITFEN Res. 0 Res. 0 LSEBYP 0 0 Res. Res. Res. 0 TIM6EN TIM7RST 0 Res. 0 0 Res. 0 TIM7EN CSSF 0 Res. 0 Res. TIM12RST 0 CRCEN LSIRDYIE 0 Res. PPRE [2:0] 1 Res. TIM13RST 0 Res. 0 TIM12EN TIM14RST 0 Res. 0 Res. HSIRDYIE 0 LSERDYIE 0 ADCRST 0 HSERDYIE 0 Res. 0 Res. 0 Res. HSICAL[7:0] Res. 0 Res. 0 TIM18RST Res. WWDGRST 0 Res. Res. Res. 0 PLLRDYIE 0 SPI1RST PPRE2 [2:0] ADCEN Res. Res. Res. 0 Res. Res. WWDGEN Res. Res. USART1RST 0 Res. Res. Res. SPI2RST Res. Res. PLLSRC Res. HSEBYP HSERDY Res. CSSON 0 Res. 0 SPI1EN Res. USART1EN 0 Res. Res. SPI2EN HSEON PLLXTPRE LSIRDYC Res. TIM15RST SPI3RST 0 0 Res. 0 0 Res. 0 0 Res. Res. 0 Res. 0 0 Res. 0 SPI3EN TIM16RST 0 TIM17RST 0 TIM19RST HSIRDYC 0 LSERDYC 0 0 0 USART2RST 0 HSERDYC 0 Res. 0 PLLRDYC 0 Res. Res. 0 Res. Res. PLL ON USBPRE Res. 0 Res. CSSC Res. PLL RDY 0 0 0 USART3RST Res. Res. ADC PRE [1:0] 0 Res. IOPAEN TIM15 EN IOPBEN Res. Res. PLLMUL[3:0 0 Res. Res. Res. Res. 0 0 Res. 0 TIM16 EN 0 TIM17 EN 0 USART2EN 0 USART3EN IOPCEN 0 TIM19 EN 0 Res. IOPDEN 0 Res. Res. Res. Res. Res. Res. Res. 0 0 BDRST 0 Res. 0 Res. I2C1RST IOPEEN 0 Res. 0 Res. 0 0 Res. 0 I2C1EN 0 Res. 0 Res. 0 I2C2RST 0 IOPFEN 0 Res. Reset value 0 Res. 0 I2C2EN Reset value Res. SDAD1RST RCC_CIR Res. 0 USBRST 0 Res. 0 TSCEN 0 Res. SDADC1EN SDAD2RST 0 Res. MCO [2:0] USBEN CANRST 0 Res. SDAD3RST 0 Res. 0 Res. SDADC2EN 0 CANEN DAC2RST 0 Res. Res. Res. Res. 0 Res. SDADC3EN 0 DAC2EN Reset value 0 Res. 0 Res. Res. Reset value Res. 0 Res. PWRRST Res. Res. Res. SDPRE[4:0] Res. 0 Res. DAC1RST 0 Res. Res. Res. Res. Reset value RTCEN Reset value PWREN Reset value CECRST Reset value Res. RCC_APB1EN R 0 Res. 0x1C RCC_APB2EN R DAC1EN 0x18 RCC_AHBENR 0 Res. Reset value Res. 0x14 RCC_APB1RS TR Res. 0x010 RCC_APB2RS TR Res. 0x0C RCC_CFGR Res. 0x08 Res. 0x04 RCC_CR Res. 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register CECEN Offset Res. 7.4.14 Res. RM0313 Reset and clock control (RCC) RCC register map The following table gives the RCC register map and the reset values. Table 18. RCC register map and reset values 0 1 1 SWS [1:0] SW [1:0] 0 0 0 0 137/897 138 0x30 138/897 RCC_CFGR3 Reset value 0 0 0 DocID022448 Rev 2 Refer to Section 2.2.2 on page 41 for the register boundary addresses. I2C1SW 0 0 0 0 USART1SW[1:0] 0 Res. I2S2SW Reset value Res. CECSW 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PREDIV[3:0] LSIRDY LSION 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. R e s. Res. IOPA RST 0 Res. IOPB RST 0 Res. IOPC RST 0 Res. IOPD RST 0 Res. IOPE RST 0 R e s. Res. Res. Res. Res. Res. Res. IOPF RST Res. RMVF TSC RST 0 Res. USART2SW[1:0] USART3SW[1:0] Res. Res. Res. 0 Res. Reset value Res. 0 Res. PINRSTF OBLRSTF 0 Res. SFTRSTF PORRSTF 1 Res. Res. Res. 1 Res. Res. Res. Res. 0 Res. Res. Res. Res. IWDGRSTF 0 Res. Res. LPWRSTF WWDGRSTF 0 Res. Res. Res. 0 Res. RCC_CFGR2 Res. RCC_AHBRST R Res. 0x2C Reset value Res. 0x28 RCC_CSR Res. 0x24 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. Reset and clock control (RCC) RM0313 Table 18. RCC register map and reset values (continued) 0 0 0 0 RM0313 General-purpose I/Os (GPIO) 8 General-purpose I/Os (GPIO) 8.1 Introduction Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection registers (GPIOx_AFRH and GPIOx_AFRL). 8.2 8.3 GPIO main features • Output states: push-pull or open drain + pull-up/down • Output data from output data register (GPIOx_ODR) or peripheral (alternate function output) • Speed selection for each I/O • Input states: floating, pull-up/down, analog • Input data to input data register (GPIOx_IDR) or peripheral (alternate function input) • Bit set and reset register (GPIOx_ BSRR) for bitwise write access to GPIOx_ODR • Locking mechanism (GPIOx_LCKR) provided to freeze the port A, B and D I/O port configuration . • Analog function • Alternate function selection registers • Fast toggle capable of changing every one AHB clock cycle • Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several peripheral functions GPIO functional description Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in several modes: • Input floating • Input pull-up • Input-pull-down • Analog • Output open-drain with pull-up or pull-down capability • Output push-pull with pull-up or pull-down capability • Alternate function push-pull with pull-up or pull-down capability • Alternate function open-drain with pull-up or pull-down capability Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR and GPIOx_BRR registers is to allow atomic read/modify accesses to any of the GPIOx_ODR DocID022448 Rev 2 139/897 156 General-purpose I/Os (GPIO) RM0313 registers. In this way, there is no risk of an IRQ occurring between the read and the modify access. Figure 15 and Figure 16 show the basic structures of a standard and a 5 V tolerant I/O port bit, respectively. Table 20 gives the possible port bit configurations. Figure 15. Basic structure of an I/O port bit !NALOG 4OONCHIP PERIPHERAL !LTERNATEFUNCTIONINPUT )NPUTDATAREGISTER TRIGGER ONOFF 0ROTECTION DIODE 0ULL UP )NPUTDRIVER )/PIN /UTPUTDRIVER 6$$ ONOFF 0ROTECTION DIODE 0ULL DOWN 0-/3 633 /UTPUT CONTROL 633 .-/3 2EADWRITE &ROMONCHIP PERIPHERAL 6$$ 6$$ /UTPUTDATAREGISTER "ITSETRESETREGISTERS 2EAD 7RITE ONOFF 633 !LTERNATEFUNCTIONOUTPUT 0USHPULL OPENDRAINOR DISABLED !NALOG AI Figure 16. Basic structure of a five-volt tolerant I/O port bit !NALOG 4OONCHIP PERIPHERAL )NPUTDATAREGISTER !LTERNATEFUNCTIONINPUT 2EADWRITE &ROMONCHIP PERIPHERAL /UTPUTDATAREGISTER 7RITE "ITSETRESETREGISTERS 2EAD ONOFF 6$$ 44,3CHMITT TRIGGER ONOFF 0ULL UP 6$$?&4 0ROTECTION DIODE )NPUTDRIVER )/PIN /UTPUTDRIVER 6$$ ONOFF 0-/3 /UTPUT CONTROL 0ULL DOWN 633 0ROTECTION DIODE 633 .-/3 633 !LTERNATEFUNCTIONOUTPUT 0USHPULL OPENDRAINOR DISABLED !NALOG AIB 1. VDD_FT is a potential specific to five-volt tolerant I/Os and different from VDD. 140/897 DocID022448 Rev 2 RM0313 General-purpose I/Os (GPIO) Table 19. Port bit configuration table(1) MODER(i) [1:0] 01 10 00 11 OTYPER(i) OSPEEDR(i) [B:A] PUPDR(i) [1:0] I/O configuration 0 0 0 GP output PP 0 0 1 GP output PP + PU 0 1 0 GP output PP + PD 1 1 Reserved 0 0 GP output OD 1 0 1 GP output OD + PU 1 1 0 GP output OD + PD 1 1 1 Reserved (GP output OD) 0 0 0 AF PP 0 0 1 AF PP + PU 0 1 0 AF PP + PD 1 1 Reserved 0 0 AF OD 1 0 1 AF OD + PU 1 1 0 AF OD + PD 1 1 1 Reserved 0 SPEED [B:A] 1 0 SPEED [B:A] 1 x x x 0 0 Input Floating x x x 0 1 Input PU x x x 1 0 Input PD x x x 1 1 Reserved (input floating) x x x 0 0 Input/output x x x 0 1 x x x 1 0 x x x 1 1 Analog Reserved 1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate function. 8.3.1 General-purpose I/O (GPIO) During and just after reset, the alternate functions are not active and the I/O ports are configured in input floating mode. The debug pins are in AF pull-up/pull-down after reset: • PA15: JTDI in pull-up • PA14: JTCK in pull-down • PA13: JTMS in pull-up • PB4: NJTRST in pull-up DocID022448 Rev 2 141/897 156 General-purpose I/Os (GPIO) RM0313 When the pin is configured as output, the value written to the output data register (GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull mode or open-drain mode (only the low level is driven, high level is HI-Z). The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB clock cycle. All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or not depending on the value in the GPIOx_PUPDR register. 8.3.2 I/O pin alternate function multiplexer and mapping The device I/O pins are connected to onboard peripherals/modules through a multiplexer that allows only one peripheral’s alternate function (AF) connected to an I/O pin at a time. In this way, there can be no conflict between peripherals available on the same I/O pin. Each I/O pin has a multiplexer with up to sixteen alternate function inputs (AF0 to AF15) that can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to 15) registers: • After reset all I/Os are connected to alternate function 0 (AF0) • The specific alternate function assignments for each pin are detailed in the device datasheet. In addition to this flexible I/O multiplexing architecture, each peripheral has alternate functions mapped onto different I/O pins to optimize the number of peripherals available in smaller packages. To use an I/O in a given configuration, you have to proceed as follows: • Debug function: after each device reset these pins are assigned as alternate function pins immediately usable by the debugger host • GPIO: configure the desired I/O as output, input or analog in the GPIOx_MODER register. • Peripheral alternate function: • • – Connect the I/O to the desired AFx in one of the GPIOx_AFRL or GPIOx_AFRH register. – Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER, GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively. – Configure the desired I/O as an alternate function in the GPIOx_MODER register. Additional functions: – For the ADC and DACs, configure the desired I/O in analog mode in the GPIOx_MODER register and configure the required function in the ADC or DAC registers. – For the additional functions like RTC, WKUPx and oscillators, configure the required function in the related RTC, PWR and RCC registers. These functions have priority over the configuration in the standard GPIO registers. EVENTOUT You can configure the I/O pin used to output the Cortex-M4 with FPU EVENTOUT signal by connecting it to AF15. Note: EVENTOUT is not mapped onto the following I/O pins: PC13, PC14, PC15, PF0, and PF1. Please refer to the “Alternate function mapping” table in the device datasheet for the detailed mapping of the alternate function I/O pins. 142/897 DocID022448 Rev 2 RM0313 8.3.3 General-purpose I/Os (GPIO) I/O port control registers Each of the GPIO ports has four 32-bit memory-mapped control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The GPIOx_MODER register is used to select the I/O mode (input, output, AF, analog). The GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (pushpull or open-drain) and speed. The GPIOx_PUPDR register is used to select the pullup/pull-down whatever the I/O direction. 8.3.4 I/O port data registers Each GPIO has two 16-bit memory-mapped data registers: input and output data registers (GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write accessible. The data input through the I/O are stored into the input data register (GPIOx_IDR), a read-only register. See Section 8.4.5: GPIO port input data register (GPIOx_IDR) (x = A..F) and Section 8.4.6: GPIO port output data register (GPIOx_ODR) (x = A..F) for the register descriptions. 8.3.5 I/O data bitwise handling The bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to set and reset each individual bit in the output data register (GPIOx_ODR). The bit set reset register has twice the size of GPIOx_ODR. To each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BS(i) and BR(i). When written to 1, bit BS(i) sets the corresponding ODR(i) bit. When written to 1, bit BR(i) resets the ODR(i) corresponding bit. Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set action takes priority. Using the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a “one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always be accessed directly. The GPIOx_BSRR register provides a way of performing atomic bitwise handling. There is no need for the software to disable interrupts when programming the GPIOx_ODR at bit level: it is possible to modify one or more bits in a single atomic AHB write access. 8.3.6 GPIO locking mechanism It is possible to freeze the GPIO control registers by applying a specific write sequence to the GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must be the same). When the LOCK sequence has been applied to a port bit, the value of the port bit can no longer be modified until the next reset. Each GPIOx_LCKR bit freezes the corresponding bit in the control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. DocID022448 Rev 2 143/897 156 General-purpose I/Os (GPIO) RM0313 The LOCK sequence (refer to Section 8.4.8: GPIO port configuration lock register (GPIOx_LCKR) (x = A, B, and D)) can only be performed using a word (32-bit long) access to the GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same time as the [15:0] bits. For more details please refer to LCKR register description in Section 8.4.8: GPIO port configuration lock register (GPIOx_LCKR) (x = A, B, and D). 8.3.7 I/O alternate function input/output Two registers are provided to select one of the alternate function inputs/outputs available for each I/O. With these registers, you can connect an alternate function to some other pin as required by your application. This means that a number of possible peripheral functions are multiplexed on each GPIO using the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can thus select any one of the possible functions for each I/O. The AF selection signal being common to the alternate function input and alternate function output, a single channel is selected for the alternate function input/output of one I/O. To know which functions are multiplexed on each GPIO pin, refer to the device datasheet. 8.3.8 External interrupt/wakeup lines All ports have external interrupt capability. To use external interrupt lines, the port must be configured in input mode, refer to the Extended interrupts and events controller (EXTI) and to the Wakeup event management section. 8.3.9 Input configuration When the I/O port is programmed as input: • The output buffer is disabled • The Schmitt trigger input is activated • The pull-up and pull-down resistors are activated depending on the value in the GPIOx_PUPDR register • The data present on the I/O pin are sampled into the input data register every AHB clock cycle • A read access to the input data register provides the I/O state Figure 17 shows the input configuration of the I/O port bit. 144/897 DocID022448 Rev 2 RM0313 General-purpose I/Os (GPIO) )NPUTDATAREGISTER Figure 17. Input floating/pull up/pull down configurations 2EADWRITE /UTPUTDATAREGISTER 7RITE "ITSETRESETREGISTERS 2EAD ON 44,3CHMITT TRIGGER 6$$ ONOFF 6$$ PROTECTION DIODE PULL UP INPUTDRIVER )/PIN ONOFF OUTPUTDRIVER PULL DOWN 633 PROTECTION DIODE 633 AIB 8.3.10 Output configuration When the I/O port is programmed as output: • The output buffer is enabled: – Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register leaves the port in Hi-Z (the P-MOS is never activated) – Push-pull mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register activates the P-MOS • The Schmitt trigger input is activated • The pull-up and pull-down resistors are activated depending on the value in the GPIOx_PUPDR register • The data present on the I/O pin are sampled into the input data register every AHB clock cycle • A read access to the input data register gets the I/O state • A read access to the output data register gets the last written value Figure 18 shows the output configuration of the I/O port bit. DocID022448 Rev 2 145/897 156 General-purpose I/Os (GPIO) RM0313 )NPUTDATAREGISTER Figure 18. Output configuration 7RITE 2EADWRITE ON 6$$ 6$$ 44,3CHMITT TRIGGER ONOFF )NPUTDRIVER /UTPUTDATAREGISTER "ITSETRESETREGISTERS 2EAD PROTECTION DIODE PULL UP /UTPUTDRIVER 6$$ )/PIN ONOFF 0-/3 /UTPUT CONTROL PROTECTION DIODE PULL DOWN 633 633 .-/3 0USHPULLOR 633 /PENDRAIN AIB 8.3.11 Alternate function configuration When the I/O port is programmed as alternate function: • The output buffer can be configured in open-drain or push-pull mode • The output buffer is driven by the signals coming from the peripheral (transmitter enable and data) • The Schmitt trigger input is activated • The weak pull-up and pull-down resistors are activated or not depending on the value in the GPIOx_PUPDR register • The data present on the I/O pin are sampled into the input data register every AHB clock cycle • A read access to the input data register gets the I/O state Figure 19 shows the Alternate function configuration of the I/O port bit. Figure 19. Alternate function configuration !LTERNATEFUNCTIONINPUT 2EADWRITE &ROMONCHIP PERIPHERAL 6$$ 6$$ 44,3CHMITT TRIGGER ONOFF PROTECTION DIODE 0ULL UP )NPUTDRIVER /UTPUTDATAREGISTER "ITSETRESETREGISTERS 2EAD 7RITE ON )NPUTDATAREGISTER 4OONCHIP PERIPHERAL )/PIN /UTPUTDRIVER ONOFF 6$$ 0-/3 /UTPUT CONTROL PROTECTION DIODE 0ULL DOWN 633 633 .-/3 633 PUSHPULLOR OPENDRAIN !LTERNATEFUNCTIONOUTPUT AIB 146/897 DocID022448 Rev 2 RM0313 8.3.12 General-purpose I/Os (GPIO) Analog configuration When the I/O port is programmed as analog configuration: Note: • The output buffer is disabled • The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0). • The weak pull-up and pull-down resistors are disabled by hardware • Read access to the input data register gets the value “0” In the analog configuration, the I/O pins cannot be 5 Volt tolerant. Figure 20 shows the high-impedance, analog-input configuration of the I/O port bit. Figure 20. High impedance-analog configuration )NPUTDATAREGISTER !NALOG 4OONCHIP PERIPHERAL 2EADWRITE &ROMONCHIP PERIPHERAL 8.3.13 /UTPUTDATAREGISTER 7RITE "ITSETRESETREGISTERS 2EAD OFF 6$$ 44,3CHMITT TRIGGER PROTECTION DIODE )NPUTDRIVER )/PIN PROTECTION DIODE 633 !NALOG AI Using the HSE or LSE oscillator pins as GPIOs When the HSE or LSE oscillator is switched OFF (default state after reset), the related oscillator pins can be used as normal GPIOs. When the HSE or LSE oscillator is switched ON (by setting the HSEON or LSEON bit in the RCC_CSR register) the oscillator takes control of its associated pins and the GPIO configuration of these pins has no effect. When the oscillator is configured in a user external clock mode, only the OSC_IN or OSC32_IN pin is reserved for clock input and the OSC_OUT or OSC32_OUT pin can still be used as normal GPIO. 8.3.14 Using the GPIO pins in the RTC supply domain The PC13/PC14/PC15 GPIO functionality is lost when the core supply domain is powered off (when the device enters Standby mode). In this case, if their GPIO configuration is not bypassed by the RTC configuration, these pins are set in an analog input mode. For details about I/O control by the RTC, refer to Section 23.3: RTC functional description on page 510. DocID022448 Rev 2 147/897 156 General-purpose I/Os (GPIO) 8.4 RM0313 GPIO registers This section gives a detailed description of the GPIO registers. For a summary of register bits, register address offsets and reset values, refer to Table 20. The peripheral registers can be written in word, half word or byte mode. 8.4.1 GPIO port mode register (GPIOx_MODER) (x = A..F) Address offset: 0x00 Reset values: 31 30 • 0xA800 0000 for port A • 0x0000 0280 for port B • 0x0000 0000 for other ports 29 MODER15[1:0] 28 MODER14[1:0] 27 26 MODER13[1:0] 25 24 MODER12[1:0] 23 22 MODER11[1:0] 21 20 MODER10[1:0] 19 18 MODER9[1:0] 17 16 MODER8[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MODER7[1:0] rw rw MODER6[1:0] rw rw MODER5[1:0] rw rw MODER4[1:0] rw rw MODER3[1:0] rw rw MODER2[1:0] rw rw MODER1[1:0] rw rw MODER0[1:0] rw rw Bits 2y+1:2y MODERy[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode. 00: Input mode (reset state) 01: General purpose output mode 10: Alternate function mode 11: Analog mode 8.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A..F) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OT15 OT14 OT13 OT12 OT11 OT10 OT9 OT8 OT7 OT6 OT5 OT4 OT3 OT2 OT1 OT0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 OTy: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type. 0: Output push-pull (reset state) 1: Output open-drain 148/897 DocID022448 Rev 2 RM0313 General-purpose I/Os (GPIO) 8.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..F) Address offset: 0x08 Reset value: 31 30 OSPEEDR15 [1:0] • 0x0C00 0000 for port A • 0x0000 00C0 for port B • 0x0000 0000 for other ports 29 28 OSPEEDR14 [1:0] 27 26 OSPEEDR13 [1:0] 25 24 OSPEEDR12 [1:0] 23 22 OSPEEDR11 [1:0] 21 20 OSPEEDR10 [1:0] 19 18 17 16 OSPEEDR9 [1:0] OSPEEDR8 [1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OSPEEDR7 [1:0] OSPEEDR6 [1:0] OSPEEDR5 [1:0] OSPEEDR4 [1:0] OSPEEDR3 [1:0] OSPEEDR2 [1:0] OSPEEDR1 [1:0] OSPEEDR0 [1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 2y+1:2y OSPEEDRy[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. x0: Low speed 01: Medium speed 11: High speed Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed. DocID022448 Rev 2 149/897 156 General-purpose I/Os (GPIO) 8.4.4 RM0313 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..F) Address offset: 0x0C Reset values: 31 30 • 0x6400 0000 for port A • 0x0000 0100 for port B • 0x0C00 0000 for other ports 29 PUPDR15[1:0] 28 PUPDR14[1:0] 27 26 PUPDR13[1:0] 25 24 PUPDR12[1:0] 23 22 PUPDR11[1:0] 21 20 19 PUPDR10[1:0] 18 PUPDR9[1:0] 17 16 PUPDR8[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PUPDR7[1:0] rw rw PUPDR6[1:0] rw rw PUPDR5[1:0] rw rw PUPDR4[1:0] rw rw PUPDR3[1:0] rw rw PUPDR2[1:0] rw PUPDR1[1:0] rw rw rw PUPDR0[1:0] rw rw Bits 2y+1:2y PUPDRy[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down 00: No pull-up, pull-down 01: Pull-up 10: Pull-down 11: Reserved 8.4.5 GPIO port input data register (GPIOx_IDR) (x = A..F) Address offset: 0x10 Reset value: 0x0000 XXXX (where X means undefined) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IDR15 IDR14 IDR13 IDR12 IDR11 IDR10 IDR9 IDR8 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 r r r r r r r r r r r r r r r r Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 IDR: Port input data These bits are read-only. They contain the input value of the corresponding I/O port. 150/897 DocID022448 Rev 2 RM0313 General-purpose I/Os (GPIO) 8.4.6 GPIO port output data register (GPIOx_ODR) (x = A..F) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ODR9 ODR8 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 rw rw rw rw rw rw rw rw rw rw ODR15 ODR14 ODR13 ODR12 ODR11 ODR10 rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 ODR: Port output data These bits can be read and written by software. Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F). 8.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..F) Address offset: 0x18 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BS15 BS14 BS13 BS12 BS11 BS10 BS9 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 BS0 w w w w w w w w w w w w w w w w Bits 31:16 BRy: Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. 0: No action on the corresponding ODRx bit 1: Resets the corresponding ODRx bit Note: If both BSx and BRx are set, BSx has priority. Bits 15:0 BSy: Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000. 0: No action on the corresponding ODRx bit 1: Sets the corresponding ODRx bit 8.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A, B, and D) This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the DocID022448 Rev 2 151/897 156 General-purpose I/Os (GPIO) RM0313 LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next reset. Note: A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). Address offset: 0x1C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LCKK rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:17 Reserved, must be kept at reset value. Bit 16 LCKK: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. 0: Port configuration lock key not active 1: Port configuration lock key active. The GPIOx_LCKR register is locked until an MCU reset occurs. LOCK key write sequence: WR LCKR[16] = ‘1’ + LCKR[15:0] WR LCKR[16] = ‘0’ + LCKR[15:0] WR LCKR[16] = ‘1’ + LCKR[15:0] RD LCKR RD LCKR[16] = ‘1’ (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return ‘1’ until the next CPU reset. Bits 15:0 LCKy: Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is ‘0. 0: Port configuration not locked 1: Port configuration locked 152/897 DocID022448 Rev 2 RM0313 General-purpose I/Os (GPIO) 8.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A..E) Address offset: 0x20 Reset value: 0x0000 0000 31 30 29 28 27 AFR7[3:0] 26 25 24 23 22 AFR6[3:0] 21 20 19 AFR5[3:0] 18 17 16 AFR4[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw AFR3[3:0] rw AFR2[3:0] rw AFR1[3:0] rw AFR0[3:0] rw rw 17 16 Bits 31:0 AFRy[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFRy selection: 0000: AF0 0001: AF1 0010: AF2 0011: AF3 0100: AF4 0101: AF5 0110: AF6 0111: AF7 8.4.10 1000: AF8 (Ports A, B and D only) 1001: AF9 (Ports A, B and D only) 1010: AF10 (Ports A, B and D only) 1011: AF11 (Ports A, B and D only) 1100: AF12 (Ports A, B and D only) 1101: AF13 (Ports A, B and D only) 1110: AF14 (Ports A, B and D only) 1111: AF15 (Ports A, B and D only) GPIO alternate function high register (GPIOx_AFRH) (x = A..F) Address offset: 0x24 Reset value: 0x0000 0000 31 30 rw rw 15 14 29 28 27 rw rw rw rw 13 12 11 10 AFR15[3:0] rw rw 25 24 23 22 rw rw rw rw 9 8 7 6 AFR14[3:0] AFR11[3:0] rw 26 rw rw rw 20 19 18 rw rw rw rw rw rw 5 4 3 2 1 0 AFR13[3:0] AFR10[3:0] rw 21 AFR12[3:0] AFR9[3:0] rw rw rw rw AFR8[3:0] rw rw rw rw rw Bits 31:0 AFRy[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFRy selection: 0000: AF0 0001: AF1 0010: AF2 0011: AF3 0100: AF4 0101: AF5 0110: AF6 0111: AF7 1000: AF8 (Ports A, B and D only) 1001: AF9 (Ports A, B and D only) 1010: AF10 (Ports A, B and D only) 1011: AF11 (Ports A, B and D only) 1100: AF12 (Ports A, B and D only) 1101: AF13 (Ports A, B and D only) 1110: AF14 (Ports A, B and D only) 1111: AF15 (Ports A, B and D only) DocID022448 Rev 2 153/897 156 General-purpose I/Os (GPIO) 8.4.11 RM0313 GPIO port bit reset register (GPIOx_BRR) (x = A..F) Address offset: 0x28 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 w w w w w w w w w w w w w w w w Bits 31:16 Reserved Bits 15:0 BRy: Port x Reset bit y (y= 0 .. 15) These bits are write-only. A read to these bits returns the value 0x0000 0: No action on the corresponding ODRx bit 1: Reset the corresponding ODRx bit 154/897 DocID022448 Rev 2 0x08 0x08 0x0C Reset value GPIOB_OSPEEDR Reset value GPIOx_OSPEEDR (where x = C..F) Reset value GPIOA_PUPDR Reset value 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOx_OTYPER (where x = A..F) Reset value 0 0 0 0 0 0 0 0 DocID022448 Rev 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OT1 OT0 0 0 0 0 0 0 0 0 0 0 0 0 OSPEEDR0[1:0] MODER0[1:0] 0 MODER1[1:0] 0 OSPEEDR0[1:0] MODER1[1:0] 0 OSPEEDR0[1:0] OT2 0 PUPDR0[1:0] OT3 OSPEEDR1[1:0] 0 MODER2[1:0] 0 OSPEEDR1[1:0] MODER2[1:0] 0 OSPEEDR1[1:0] OT4 0 PUPDR1[1:0] OT5 OSPEEDR2[1:0] 1 MODER3[1:0] 0 OSPEEDR2[1:0] MODER3[1:0] 0 OSPEEDR2[1:0] OT6 0 PUPDR2[1:0] OT7 OSPEEDR3[1:0] 1 MODER4[1:0] 0 OSPEEDR3[1:0] MODER4[1:0] 0 OSPEEDR3[1:0] OT8 0 PUPDR3[1:0] OT9 OSPEEDR4[1:0] 0 OSPEEDR4[1:0] 0 MODER5[1:0] 0 OSPEEDR4[1:0] MODER5[1:0] 0 PUPDR4[1:0] OT11 OT10 OSPEEDR5[1:0] 0 MODER6[1:0] 0 OSPEEDR5[1:0] MODER6[1:0] 0 OSPEEDR5[1:0] OT12 0 PUPDR5[1:0] OT13 OSPEEDR6[1:0] 0 OSPEEDR6[1:0] 0 MODER7[1:0] 0 OSPEEDR6[1:0] MODER7[1:0] 0 PUPDR6[1:0] OT14 0 OT15 MODER8[1:0] 0 OSPEEDR7[1:0] MODER8[1:0] 0 OSPEEDR7[1:0] 0 Res. 0 OSPEEDR7[1:0] 0 Res. 0 PUPDR7[1:0] OSPEEDR8[1:0] 0 MODER9[1:0] 0 OSPEEDR8[1:0] MODER9[1:0] 0 OSPEEDR8[1:0] 0 Res. 0 PUPDR8[1:0] 0 Res. MODER10[1:0] 0 OSPEEDR9[1:0] MODER10[1:0] 0 OSPEEDR9[1:0] 0 Res. 0 OSPEEDR9[1:0] 0 Res. 0 PUPDR9[1:0] OSPEEDR10[1:0] 0 MODER11[1:0] 0 OSPEEDR10[1:0] MODER11[1:0] 0 OSPEEDR10[1:0] 0 Res. 0 PUPDR10[1:0] 0 Res. MODER12[1:0] 0 OSPEEDR11[1:0] MODER12[1:0] 0 OSPEEDR11[1:0] 0 Res. 0 OSPEEDR11[1:0] 0 Res. 0 PUPDR11[1:0] OSPEEDR12[1:0] 0 MODER13[1:0] 0 OSPEEDR12[1:0] MODER13[1:0] 1 OSPEEDR12[1:0] 0 Res. 0 PUPDR12[1:0] 0 Res. MODER14[1:0] 0 OSPEEDR13[1:0] MODER14[1:0] 0 OSPEEDR13[1:0] 0 Res. 1 OSPEEDR13[1:0] 0 Res. MODER15[1:0] 0 PUPDR13[1:0] GPIOA_OSPEEDR OSPEEDR14[1:0] GPIOx_MODER (where x = C..F) 0 OSPEEDR14[1:0] Reset value OSPEEDR14[1:0] 0x08 GPIOB_MODER MODER15[1:0] Reset value PUPDR14[1:0] 0x04 Reset value Res. 0x00 Res. 0x00 0 0 0 0 MODER0[1:0] MODER0[1:0] MODER1[1:0] MODER2[1:0] MODER3[1:0] MODER4[1:0] MODER5[1:0] MODER6[1:0] MODER7[1:0] MODER8[1:0] MODER9[1:0] MODER10[1:0] MODER11[1:0] MODER12[1:0] MODER13[1:0] MODER14[1:0] MODER15[1:0] GPIOA_MODER OSPEEDR15[1:0] 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register OSPEEDR15[1:0] Offset OSPEEDR15[1:0] 8.4.12 PUPDR15[1:0] RM0313 General-purpose I/Os (GPIO) GPIO register map The following table gives the GPIO register map and reset values. Table 20. GPIO register map and reset values 0 0 0 0 0 0 155/897 156 156/897 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BR1 BR0 Res. 0 BR2 Res. 0 BR3 Res. 0 BR4 Res. 0 GPIOx_BRR (where x = A..F) BR5 Res. AFR10[3:0] BR6 Res. AFR11[3:0] BR7 Res. AFR12[3:0] BR8 Res. AFR13[3:0] BR9 Res. AFR14[3:0] BR11 Reset value AFR15[3:0] Reset value BR10 Res. 0x24 GPIOx_AFRH (where x = A..F) BR12 Res. 0x20 GPIOx_AFRL (where x = A..F) BR13 0x1C BR14 0 BR15 BR1 0 Res. 0 0 0 AFR7[3:0] 0 0 0 0 AFR6[3:0] 0 0 0 0 AFR5[3:0] 0 0 0 BS15 BS14 BS13 BS12 BS11 BS10 BS9 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 BS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0 0 0 LCK14 AFR4[3:0] 0 0 DocID022448 Rev 2 ODR14 ODR13 ODR12 ODR11 ODR10 ODR9 ODR8 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 0 0 0 0x10 Res. Res. Res. Res. IDR0 0 IDR1 0 IDR2 0 IDR3 0 IDR4 0 IDR5 0 IDR6 0 IDR7 0 IDR8 0 IDR9 0 IDR11 0 IDR10 0 IDR12 0 IDR13 0 IDR14 0 IDR15 Reset value ODR15 0 Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Refer to Section 2.2.2 for the register boundary addresses. AFR3[3:0] 0 0 0 0 0 0 1 0 AFR2[3:0] 0 0 0 0 0 0 0 0 AFR1[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AFR9[3:0] 0 PUPDR0[1:0] 0 PUPDR1[1:0] 0 PUPDR2[1:0] 0 PUPDR3[1:0] 0 PUPDR4[1:0] 0 PUPDR5[1:0] 0 PUPDR6[1:0] PUPDR7[1:0] PUPDR8[1:0] PUPDR9[1:0] PUPDR10[1:0] 0 Res. Res. 0 Res. 0 BR0 0 PUPDR11[1:0] 0 LCKK LCK15 0 Res. 0 Res. 0 Res. 0 Res. 0 PUPDR12[1:0] 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 1 PUPDR13[1:0] 0 Res. 1 Res. 0 Res. 0 Res. 0 Res. 0 PUPDR14[1:0] 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Reset value GPIOx_IDR (where x = A..F) Res. 0 Res. GPIOx_PUPDR (where x = C..F) PUPDR15[1:0] 0x0C Res. Reset value Res. PUPDR0[1:0] PUPDR1[1:0] PUPDR2[1:0] PUPDR3[1:0] PUPDR4[1:0] PUPDR5[1:0] PUPDR6[1:0] PUPDR7[1:0] PUPDR8[1:0] PUPDR9[1:0] PUPDR10[1:0] PUPDR11[1:0] PUPDR12[1:0] PUPDR13[1:0] PUPDR14[1:0] PUPDR15[1:0] GPIOB_PUPDR Res. 0 Res. BR2 0 Res. BR3 0 Res. BR4 0 Res. BR5 0 Res. BR6 0 Res. BR7 0 Res. BR8 0 Res. BR9 0 Res. 0 Res. BR11 BR10 0 Res. BR12 0 Res. BR13 0 Res. Reset value GPIOx_LCKR (where x = A, B, D) Res. 0x28 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. BR14 Reset value 0x18 GPIOx_BSRR (where x = A..F) BR15 Reset value GPIOx_ODR (where x = A..F) Res. Reset value 0x14 Res. 0x0C Res. Offset Res. General-purpose I/Os (GPIO) RM0313 Table 20. GPIO register map and reset values (continued) 0 0 0 0 0 x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AFR0[3:0] 0 AFR8[3:0] RM0313 9 System configuration controller (SYSCFG) System configuration controller (SYSCFG) The devices feature a set of configuration registers. The main purposes of the system configuration controller are the following: • Enabling/disabling I2C Fast Mode Plus on some I/O ports • Remapping some DMA trigger sources from TIM16 and TIM17, USART1, and ADC to different DMA channels • Remapping the memory located at the beginning of the code area • Managing the external interrupt line connection to the GPIOs • Managing robustness feature 9.1 SYSCFG registers 9.1.1 SYSCFG configuration register 1 (SYSCFG_CFGR1) This register is used for specific configurations on memory remap. Two bits are used to configure the type of memory accessible at address 0x0000 0000. These bits are used to select the physical remap by software and so, bypass the BOOT pins. After reset these bits take the value selected by the BOOT pin (BOOT0) and by the option bite (nBOOT1). Address offset: 0x00 Reset value: 0x0000 000X (X is the memory mode selected by the BOOT0 pin and nBOOT1 option bit) ) 31 30 29 28 27 26 FPU_IT[5:0] rw rw rw rw rw rw 15 14 13 12 11 10 TIM17_ DMA_ RMP TIM16_ DMA_ RMP rw rw TIM18_ TIM7 TIM6 DAC2_ _DAC1_ _DAC1_ OUT1_ OUT2_ OUT1_ DMA_RMP DMA_RMP DMA_RMP rw rw 25 24 23 22 21 20 19 18 17 16 Res. VBAT_ MON Re s. Re s. I2C2_ FM+ I2C1_ FM+ I2C_ PB9_ FM+ I2C_ PB8_ FM+ I2C_ PB7_ FM+ I2C_ PB6_ FM+ rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 Res. Re s. Re s. Res. Res. Res. Res. rw 9 Res. Res. MEM_MODE rw DocID022448 Rev 2 rw 157/897 163 System configuration controller (SYSCFG) RM0313 Bits 31:26 FPU_IT[5:0]: Interrupt enable bits from FPU. 5: Inexact Interrupt enable (interrupt disabled at reset) 4: Input denormal Interrupt enable 3: Overflow Interrupt enable 2: Underflow Interrupt enable 1: Divide-by-zero Interrupt enable 0: Invalid operation Interrupt enable Bit 25 Reserved, must be kept at reset value. Bit 24 VBAT_MON: VBAT monitoring enable This bit is set and cleared by software. When it is set, it enables the power switch to deliver VBAT voltage on ADC channel 18 input. Bits 23:22 Reserved, must be kept at reset value. Bit 21 I2C2_FM+: I2C2 Fast Mode Plus (FM+) driving capability activation bit, whatever the AFI/AFO mapping. This bit is set and cleared by software. When it is set, the FM+ mode is enabled on I2C2 pins selected through IOPORT control registers AF selection bits. This bit is OR-ed with I2C_PBx_FM+ bits. Bit 20 I2C1_FM+: I2C1 Fast Mode Plus (FM+) driving capability activation bit, whatever the AFI/AFO mapping. This bit is set and cleared by software. When it is set, the FM+ mode is enabled on I2C1 pins selected through IOPORT control registers AF selection bits. This bit is OR-ed with I2C_PBx_FM+ bits. Bits 19:16 I2C_PBx_FM+: Fast Mode Plus (FM+) driving capability activation bits. These bits are set and cleared by software. Each bit enables I2C FM+ mode for PB6, PB7, PB8, and PB9 I/Os. 0: PBx pin operates in standard mode. 1: I2C FM+ mode enabled on PBx pin, and the Speed control is bypassed. Bit 15 TIM18_DAC2_OUT1_DMA_RMP: TIM18 and DAC2_OUT1 DMA request remapping bit This bit is set and cleared by software. It controls the remapping of TIM18 and DAC2_OUT1 DMA request. 0: No remap (TIM18 and DAC2_OUT1 DMA requests mapped on DMA2 channel 5) 1: Remap (TIM18 and DAC2_OUT1 DMA requests mapped on DMA1 channel 5) Bit 14 TIM7_DAC1_OUT2_DMA_RMP: TIM7 and DAC1_OUT2 DMA request remapping bit This bit is set and cleared by software. It controls the remapping of TIM7 and DAC1_OUT2 DMA request. 0: No remap (TIM7 and DAC1_OUT2 DMA requests mapped on DMA2 channel 4) 1: Remap (TIM7 and DAC1_OUT2 DMA requests mapped on DMA1 channel 4) Bit 13 TIM6_DAC1_OUT1_DMA_RMP: TIM6 and DAC1_OUT1 DMA request remapping bit This bit is set and cleared by software. It controls the remapping of TIM6 and DAC1_OUT1 DMA request. 0: No remap (TIM7 and DAC1_OUT1 DMA requests mapped on DMA2 channel 3) 1: Remap (TIM7 and DAC1_OUT1 DMA requests mapped on DMA1 channel 3) Bit 12 TIM17_DMA_RMP: TIM17 DMA request remapping bit This bit is set and cleared by software. It controls the remapping of TIM17 DMA request. 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1) 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) 158/897 DocID022448 Rev 2 RM0313 System configuration controller (SYSCFG) Bit 11 TIM16_DMA_RMP: TIM16 DMA request remapping bit This bit is set and cleared by software. It controls the remapping of TIM16 DMA request. 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3) 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) Bits 10:2 Reserved, must be kept at reset value. Bits 1:0 MEM_MODE: Memory mapping selection bits This bit is set and cleared by software. It controls the memory internal mapping at address 0x0000 0000. After reset these bits take on the memory mapping selected by BOOT0 pin and nBOOT1 option bit. x0: Main Flash memory mapped at 0x0000 0000 01: System Flash memory mapped at 0x0000 0000 11: Embedded SRAM mapped at 0x0000 0000 9.1.2 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) Address offset: 0x08 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI3[3:0] rw rw rw EXTI2[3:0] rw rw rw EXTI1[3:0] rw rw rw rw rw EXTI0[3:0] rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 EXTIx[3:0]: EXTI x configuration bits (x = 0 to 3) These bits are written by software to select the source input for the EXTIx external interrupt. x000: PA[x] pin x001: PB[x] pin x010: PC[x] pin x011: PD[x] pin x100: PE[x] pin x101: PF[x] pin (x = 0 to 2) other configurations: reserved Note: Some of the I/O pins mentioned in the above register may not be available on small packages. DocID022448 Rev 2 159/897 163 System configuration controller (SYSCFG) 9.1.3 RM0313 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) Address offset: 0x0C Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI7[3:0] rw rw rw EXTI6[3:0] rw rw rw EXTI5[3:0] rw rw rw rw rw EXTI4[3:0] rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 EXTIx[3:0]: EXTI x configuration bits (x = 4 to 7) These bits are written by software to select the source input for the EXTIx external interrupt. x000: PA[x] pin x001: PB[x] pin x010: PC[x] pin x011: PD[x] pin x100: PE[x] pin x101: PF[x] pin (x = 4, 6, 7) other configurations: reserved Note: Some of the I/O pins mentioned in the above register may not be available on small packages. 9.1.4 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) Address offset: 0x10 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI11[3:0] rw 160/897 rw rw EXTI10[3:0] rw rw rw rw EXTI9[3:0] rw rw rw DocID022448 Rev 2 rw EXTI8[3:0] rw rw rw rw rw RM0313 System configuration controller (SYSCFG) Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 EXTIx[3:0]: EXTI x configuration bits (x = 8 to 11) These bits are written by software to select the source input for the EXTIx external interrupt. x000: PA[x] pin x001: PB[x] pin (x= 8 to 10) x010: PC[x] pin x011: PD[x] pin x100: PE[x] pin x101: PF[x] pin (x = 9, 10) other configurations: reserved Note: Some of the I/O pins mentioned in the above register may not be available on small packages. 9.1.5 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) Address offset: 0x14 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 EXTI15[3:0] rw rw rw EXTI14[3:0] rw rw rw rw EXTI13[3:0] rw rw rw rw EXTI12[3:0] rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 EXTIx[3:0]: EXTI x configuration bits (x = 12 to 15) These bits are written by software to select the source input for the EXTIx external interrupt. x000: PA[x] pin x001: PB[x] pin (x= 14, 15) x010: PC[x] pin x011: PD[x] pin x100: PE[x] pin other configurations: reserved Note: Some of the I/O pins mentioned in the above register may not be available on small packages. 9.1.6 SYSCFG configuration register 2 (SYSCFG_CFGR2) Address offset: 0x18 System reset value: 0x0000 DocID022448 Rev 2 161/897 163 System configuration controller (SYSCFG) RM0313 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. SRAM_ PEF Res. Res. rc_w1 Res. Res. Res. SRAM_ PVD_ LOCUP PARITY LOCK _LOCK _LOCK rw rw rw Bits 31:9 Reserved, must be kept at reset value Bit 8 SRAM_PEF: SRAM parity flag This bit is set by hardware when an SRAM parity error is detected. It is cleared by software by writing ‘1’. 0: No SRAM parity error detected 1: SRAM parity error detected Bits 7:3 Reserved, must be kept at reset value Bit 2 PVD_LOCK: PVD lock enable bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the PVD connection to TIM15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR register. 0: PVD interrupt disconnected from TIM15/16/17 Break input. PVDE and PLS[2:0] bits can be programmed by the application. 1: PVD interrupt connected to TIM15/16/17 Break input, PVDE and PLS[2:0] bits are read only. Bit 1 SRAM_PARITY_LOCK: SRAM parity lock bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM parity error signal connection to TIM15/16/17 Break input. 0: SRAM parity error disconnected from TIM15/16/17 Break input 1: SRAM parity error connected to TIM15/16/17 Break input Bit 0 LOCKUP_LOCK: Cortex-M4F LOCKUP enable bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the connection of Cortex-M4F LOCKUP (Hardfault) output to TIM15/16/17 Break input. 0: Cortex-M4F LOCKUP output disconnected from TIM15/16/17 Break input 1: Cortex-M4F LOCKUP output connected to TIM15/16/17 Break input 162/897 DocID022448 Rev 2 RM0313 9.1.7 System configuration controller (SYSCFG) SYSCFG register maps The following table gives the SYSCFG register map and the reset values. 0 0 0 0 0 EXTI11[3:0] EXTI10[3:0] 0 0 0 0 MEM_MODE Res. Res. Res. Res. 0 0 EXTI9[3:0] 0 0 0 0 EXTI8[3:0] 0 0 EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCUP_LOCK 0 SRAM_PARITY_LOCK 0 PVD_LOCK 0 EXTI4[3:0] Res. 0 0 Res. 0 0 Res. 0 0 Res. 0 EXTI5[3:0] 0 Res. 0 0 SRAM_PEF 0 0 Res. 0 0 Res. 0 0 Res. 0 Res. TIM16_DMA_RMP EXTI6[3:0] 0 Res. TIM17_DMA_RMP Res. TIM6_DAC1_OUT1_DMA_RMP 0 0 EXTI0[3:0] Res. Reset value 0 0 EXTI1[3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SYSCFG_CFGR2 Res. 0x18 Res. Reset value 0 EXTI2[3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SYSCFG_EXTIC R4 Res. 0x14 Res. Reset value 0 X X Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x10 0 EXTI7[3:0] 0 Res. Reset value SYSCFG_EXTIC R3 0 Res. TIM7_DAC1_OUT2_DMA_RMP Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SYSCFG_EXTIC R2 Res. 0x0C 0 Res. Reset value EXTI3[3:0] Res. I2C_PB6_FM+ TIM18_DAC2_OUT1_DMA_RMP 0 I2C_PB7_FM+ 0 0 Res. 0 I2C_PB8_FM+ 0 0 Res. 0 0 Res. Res. 0 I2C_PB9_FM+ 0 Res. Res. I2C1_FM+ Res. 0 Res. Res. 0 Res. 0 I2C2_FM+ 0 Res. 0 Res. 0 VBAT_MON Res. 0 Res. 0 Res. Reset value SYSCFG_EXTIC R1 Res. FPU_IT[5:0] Res. 0x08 SYSCFG_CFGR1 Res. 0x00 Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 21. SYSCFG register map and reset values 0 0 0 0 Refer to Section 2.2.2 on page 41 for the register boundary addresses. DocID022448 Rev 2 163/897 163 Direct memory access controller (DMA) RM0313 10 Direct memory access controller (DMA) 10.1 Introduction Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations. The two DMA controllers have 12 channels in total, each dedicated to managing memory access requests from one or more peripherals. Each has an arbiter for handling the priority between DMA requests. 10.2 164/897 DMA main features • 12 independently configurable channels (requests) • Each channel is connected to dedicated hardware DMA requests, software trigger is also supported on each channel. This configuration is done by software. • Priorities between requests from channels of one DMA are software programmable (4 levels consisting of very high, high, medium, low) or hardware in case of equality (request 1 has priority over request 2, etc.) • Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size. • Support for circular buffer management • 3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error) logically ORed together in a single interrupt request for each channel • Memory-to-memory transfer • Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers • Access to Flash, SRAM, APB and AHB peripherals as source and destination • Programmable number of data to be transferred: up to 65536 DocID022448 Rev 2 RM0313 Direct memory access controller (DMA) The block diagram is shown in the following figure. Figure 21. DMA block diagram ,&RGH )ODVK )/,7) '&RGH &RUWH[0 6\VWHP &K '0$ &K 65$0 %XVPDWUL[ '0$ $+%6\VWHPEXV %ULGJH &K '0$ %ULGJH $UELWHU '0$UHTXHVW $+%6ODYH '0$ &K '0$UHTXHVW &K 7,0 7,0 7,0 7,0 7,0 7,0 7,0 7,0 7,0 7,0 $3% 63, 63, 86$57 86$57 ,& ,& 86% &$1 '$& '$& &K '0$UHTXHVW $UELWHU $3% $'& 63, 86$57 7,0 7,0 7,0 7,0 6'$'& 6'$'& 6'$'& $+%6ODYH 5HVHWFORFNFRQWURO 5&& 069 10.3 DMA implementation This manual describes the full set of features implemented in DMA1. DMA2 supports a smaller number of channels, but is otherwise identical to DMA1. Table 22. DMA implementation Feature Number of DMA channels DocID022448 Rev 2 DMA1 DMA2 7 5 165/897 183 Direct memory access controller (DMA) 10.4 RM0313 DMA functional description The DMA controller performs direct memory transfer by sharing the system bus with the Cortex-M4 with FPU core. The DMA request may stop the CPU access to the system bus for some bus cycles, when the CPU and DMA are targeting the same destination (memory or peripheral). The bus matrix implements round-robin scheduling, thus ensuring at least half of the system bus bandwidth (both to memory and peripheral) for the CPU. 10.4.1 DMA transactions After an event, the peripheral sends a request signal to the DMA Controller. The DMA controller serves the request depending on the channel priorities. As soon as the DMA Controller accesses the peripheral, an Acknowledge is sent to the peripheral by the DMA Controller. The peripheral releases its request as soon as it gets the Acknowledge from the DMA Controller. Once the request is deasserted by the peripheral, the DMA Controller release the Acknowledge. If there are more requests, the peripheral can initiate the next transaction. In summary, each DMA transfer consists of three operations: 10.4.2 • The loading of data from the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. The start address used for the first transfer is the base peripheral/memory address programmed in the DMA_CPARx or DMA_CMARx register • The storage of the data loaded to the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. The start address used for the first transfer is the base peripheral/memory address programmed in the DMA_CPARx or DMA_CMARx register • The post-decrementing of the DMA_CNDTRx register, which contains the number of transactions that have still to be performed. Arbiter The arbiter manages the channel requests based on their priority and launches the peripheral/memory access sequences. The priorities are managed in two stages: • • 166/897 Software: each channel priority can be configured in the DMA_CCRx register. There are four levels: – Very high priority – High priority – Medium priority – Low priority Hardware: if 2 requests have the same software priority level, the channel with the lowest number will get priority versus the channel with the highest number. For example, channel 2 gets priority over channel 4. DocID022448 Rev 2 RM0313 10.4.3 Direct memory access controller (DMA) DMA channels Each channel can handle DMA transfer between a peripheral register located at a fixed address and a memory address. The amount of data to be transferred (up to 65535) is programmable. The register which contains the amount of data items to be transferred is decremented after each transaction. Programmable data sizes Transfer data sizes of the peripheral and memory are fully programmable through the PSIZE and MSIZE bits in the DMA_CCRx register. Pointer incrementation Peripheral and memory pointers can optionally be automatically post-incremented after each transaction depending on the PINC and MINC bits in the DMA_CCRx register. If incremented mode is enabled, the address of the next transfer will be the address of the previous one incremented by 1, 2 or 4 depending on the chosen data size. The first transfer address is the one programmed in the DMA_CPARx/DMA_CMARx registers. During transfer operations, these registers keep the initially programmed value. The current transfer addresses (in the current internal peripheral/memory address register) are not accessible by software. If the channel is configured in noncircular mode, no DMA request is served after the last transfer (that is once the number of data items to be transferred has reached zero). In order to reload a new number of data items to be transferred into the DMA_CNDTRx register, the DMA channel must be disabled. Note: If a DMA channel is disabled, the DMA registers are not reset. The DMA channel registers (DMA_CCRx, DMA_CPARx and DMA_CMARx) retain the initial values programmed during the channel configuration phase. In circular mode, after the last transfer, the DMA_CNDTRx register is automatically reloaded with the initially programmed value. The current internal address registers are reloaded with the base address values from the DMA_CPARx/DMA_CMARx registers. Channel configuration procedure The following sequence should be followed to configure a DMA channelx (where x is the channel number). 1. Set the peripheral register address in the DMA_CPARx register. The data will be moved from/ to this address to/ from the memory after the peripheral event. 2. Set the memory address in the DMA_CMARx register. The data will be written to or read from this memory after the peripheral event. 3. Configure the total number of data to be transferred in the DMA_CNDTRx register. After each peripheral event, this value will be decremented. 4. Configure the channel priority using the PL[1:0] bits in the DMA_CCRx register 5. Configure data transfer direction, circular mode, peripheral & memory incremented mode, peripheral & memory data size, and interrupt after half and/or full transfer in the DMA_CCRx register 6. Activate the channel by setting the ENABLE bit in the DMA_CCRx register. As soon as the channel is enabled, it can serve any DMA request from the peripheral connected on the channel. DocID022448 Rev 2 167/897 183 Direct memory access controller (DMA) RM0313 Once half of the bytes are transferred, the half-transfer flag (HTIF) is set and an interrupt is generated if the Half-Transfer Interrupt Enable bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag (TCIF) is set and an interrupt is generated if the Transfer Complete Interrupt Enable bit (TCIE) is set. Circular mode Circular mode is available to handle circular buffers and continuous data flows (e.g. ADC scan mode). This feature can be enabled using the CIRC bit in the DMA_CCRx register. When circular mode is activated, the number of data to be transferred is automatically reloaded with the initial value programmed during the channel configuration phase, and the DMA requests continue to be served. Memory-to-memory mode The DMA channels can also work without being triggered by a request from a peripheral. This mode is called Memory to Memory mode. If the MEM2MEM bit in the DMA_CCRx register is set, then the channel initiates transfers as soon as it is enabled by software by setting the Enable bit (EN) in the DMA_CCRx register. The transfer stops once the DMA_CNDTRx register reaches zero. Memory to Memory mode may not be used at the same time as Circular mode. 10.4.4 Programmable data width, data alignment and endians When PSIZE and MSIZE are not equal, the DMA performs some data alignments as described in Table 23: Programmable data width & endian behavior (when bits PINC = MINC = 1). Table 23. Programmable data width & endian behavior (when bits PINC = MINC = 1) Number Source of data Destination port items to port width width transfer (NDT) Source content: address / data Transfer operations Destination content: address / data 8 8 4 @0x0 / B0 @0x1 / B1 @0x2 / B2 @0x3 / B3 1: READ B0[7:0] @0x0 then WRITE B0[7:0] @0x0 2: READ B1[7:0] @0x1 then WRITE B1[7:0] @0x1 3: READ B2[7:0] @0x2 then WRITE B2[7:0] @0x2 4: READ B3[7:0] @0x3 then WRITE B3[7:0] @0x3 @0x0 / B0 @0x1 / B1 @0x2 / B2 @0x3 / B3 8 16 4 @0x0 / B0 @0x1 / B1 @0x2 / B2 @0x3 / B3 1: READ B0[7:0] @0x0 then WRITE 00B0[15:0] @0x0 2: READ B1[7:0] @0x1 then WRITE 00B1[15:0] @0x2 3: READ B3[7:0] @0x2 then WRITE 00B2[15:0] @0x4 4: READ B4[7:0] @0x3 then WRITE 00B3[15:0] @0x6 @0x0 / 00B0 @0x2 / 00B1 @0x4 / 00B2 @0x6 / 00B3 8 32 4 @0x0 / B0 @0x1 / B1 @0x2 / B2 @0x3 / B3 1: READ B0[7:0] @0x0 then WRITE 000000B0[31:0] @0x0 2: READ B1[7:0] @0x1 then WRITE 000000B1[31:0] @0x4 3: READ B3[7:0] @0x2 then WRITE 000000B2[31:0] @0x8 4: READ B4[7:0] @0x3 then WRITE 000000B3[31:0] @0xC @0x0 / 000000B0 @0x4 / 000000B1 @0x8 / 000000B2 @0xC / 000000B3 16 8 4 @0x0 / B1B0 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 1: READ B1B0[15:0] @0x0 then WRITE B0[7:0] @0x0 2: READ B3B2[15:0] @0x2 then WRITE B2[7:0] @0x1 3: READ B5B4[15:0] @0x4 then WRITE B4[7:0] @0x2 4: READ B7B6[15:0] @0x6 then WRITE B6[7:0] @0x3 @0x0 / B0 @0x1 / B2 @0x2 / B4 @0x3 / B6 16 16 4 @0x0 / B1B0 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 1: READ B1B0[15:0] @0x0 then WRITE B1B0[15:0] @0x0 2: READ B3B2[15:0] @0x2 then WRITE B3B2[15:0] @0x2 3: READ B5B4[15:0] @0x4 then WRITE B5B4[15:0] @0x4 4: READ B7B6[15:0] @0x6 then WRITE B7B6[15:0] @0x6 @0x0 / B1B0 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 16 32 4 @0x0 / B1B0 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 1: READ B1B0[15:0] @0x0 then WRITE 0000B1B0[31:0] @0x0 2: READ B3B2[15:0] @0x2 then WRITE 0000B3B2[31:0] @0x4 3: READ B5B4[15:0] @0x4 then WRITE 0000B5B4[31:0] @0x8 4: READ B7B6[15:0] @0x6 then WRITE 0000B7B6[31:0] @0xC @0x0 / 0000B1B0 @0x4 / 0000B3B2 @0x8 / 0000B5B4 @0xC / 0000B7B6 168/897 DocID022448 Rev 2 RM0313 Direct memory access controller (DMA) Table 23. Programmable data width & endian behavior (when bits PINC = MINC = 1) (continued) Number Source of data Destination port items to port width width transfer (NDT) Source content: address / data Transfer operations Destination content: address / data 32 8 4 @0x0 / B3B2B1B0 @0x4 / B7B6B5B4 @0x8 / BBBAB9B8 @0xC / BFBEBDBC 1: READ B3B2B1B0[31:0] @0x0 then WRITE B0[7:0] @0x0 2: READ B7B6B5B4[31:0] @0x4 then WRITE B4[7:0] @0x1 3: READ BBBAB9B8[31:0] @0x8 then WRITE B8[7:0] @0x2 4: READ BFBEBDBC[31:0] @0xC then WRITE BC[7:0] @0x3 @0x0 / B0 @0x1 / B4 @0x2 / B8 @0x3 / BC 32 16 4 @0x0 / B3B2B1B0 @0x4 / B7B6B5B4 @0x8 / BBBAB9B8 @0xC / BFBEBDBC 1: READ B3B2B1B0[31:0] @0x0 then WRITE B1B0[15:0] @0x0 2: READ B7B6B5B4[31:0] @0x4 then WRITE B5B4[15:0] @0x2 3: READ BBBAB9B8[31:0] @0x8 then WRITE B9B8[15:0] @0x4 4: READ BFBEBDBC[31:0] @0xC then WRITE BDBC[15:0] @0x6 @0x0 / B1B0 @0x2 / B5B4 @0x4 / B9B8 @0x6 / BDBC 4 @0x0 / B3B2B1B0 @0x4 / B7B6B5B4 @0x8 / BBBAB9B8 @0xC / BFBEBDBC @0x0 / B3B2B1B0 1: READ B3B2B1B0[31:0] @0x0 then WRITE B3B2B1B0[31:0] @0x0 @0x4 / B7B6B5B4 2: READ B7B6B5B4[31:0] @0x4 then WRITE B7B6B5B4[31:0] @0x4 @0x8 / BBBAB9B8 3: READ BBBAB9B8[31:0] @0x8 then WRITE BBBAB9B8[31:0] @0x8 @0xC / 4: READ BFBEBDBC[31:0] @0xC then WRITE BFBEBDBC[31:0] @0xC BFBEBDBC 32 32 Addressing an AHB peripheral that does not support byte or halfword write operations When the DMA initiates an AHB byte or halfword write operation, the data are duplicated on the unused lanes of the HWDATA[31:0] bus. So when the used AHB slave peripheral does not support byte or halfword write operations (when HSIZE is not used by the peripheral) and does not generate any error, the DMA writes the 32 HWDATA bits as shown in the two examples below: • To write the halfword “0xABCD”, the DMA sets the HWDATA bus to “0xABCDABCD” with HSIZE = HalfWord • To write the byte “0xAB”, the DMA sets the HWDATA bus to “0xABABABAB” with HSIZE = Byte Assuming that the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take the HSIZE data into account, it will transform any AHB byte or halfword operation into a 32-bit APB operation in the following manner: • an AHB byte write operation of the data “0xB0” to 0x0 (or to 0x1, 0x2 or 0x3) will be converted to an APB word write operation of the data “0xB0B0B0B0” to 0x0 • an AHB halfword write operation of the data “0xB1B0” to 0x0 (or to 0x2) will be converted to an APB word write operation of the data “0xB1B0B1B0” to 0x0 For instance, if you want to write the APB backup registers (16-bit registers aligned to a 32bit address boundary), you must configure the memory source size (MSIZE) to “16-bit” and the peripheral destination size (PSIZE) to “32-bit”. 10.4.5 Error management A DMA transfer error can be generated by reading from or writing to a reserved address space. When a DMA transfer error occurs during a DMA read or a write access, the faulty channel is automatically disabled through a hardware clear of its EN bit in the corresponding Channel configuration register (DMA_CCRx). The channel's transfer error interrupt flag (TEIF) in the DMA_IFR register is set and an interrupt is generated if the transfer error interrupt enable bit (TEIE) in the DMA_CCRx register is set. DocID022448 Rev 2 169/897 183 Direct memory access controller (DMA) 10.4.6 RM0313 Interrupts An interrupt can be produced on a Half-transfer, Transfer complete or Transfer error for each DMA channel. Separate interrupt enable bits are available for flexibility. Table 24. DMA interrupt requests Interrupt event 170/897 Event flag Enable control bit Half-transfer HTIF HTIE Transfer complete TCIF TCIE Transfer error TEIF TEIE DocID022448 Rev 2 RM0313 10.4.7 Direct memory access controller (DMA) DMA request mapping DMA1 controller The hardware requests from the peripherals (TIMx, ADC1, DACx, SPIx, I2Cx, and USARTx) are simply logically ORed before entering the DMA1. This means that on one channel, only one request must be enabled at a time. Refer to Figure 22: DMA1 request mapping. The peripheral DMA1 requests can be independently activated/de-activated by programming the DMA1 control bit in the registers of the corresponding peripheral. DocID022448 Rev 2 171/897 183 Direct memory access controller (DMA) RM0313 Figure 22. DMA1 request mapping 3HULSKHUDOUHTXHVWVLJQDOV '0$ )L[HGKDUGZDUHSULRULW\ +LJKSULRULW\ $'& 7,0B&+ 7,0B&+ 7,0B&+ 7,0B83 7,0B&+ 7,0B83 63,B5; 86$57B7; 7,0B83 7,0B&+ 7,0B&+ 63,B7; 86$57B5; 7,0B&+ 7,0B83 7,0B83 7,0B&+ 7,0B83 7,0B&+ 63,B5; 86$57B7; ,&B7; 7,0B&+ 7,0B83 7,0B83 86$57B5; ,&B7; 7,0B&+ 7,0B75,* 7,0B&+ 7,0B83 +:UHTXHVW 6:WULJJHU 0(00(0ELW +:UHTXHVW &KDQQHO 6:WULJJHU 0(00(0ELW +:UHTXHVW ,QWHUQDO '0$ UHTXHVW &KDQQHO 6:WULJJHU 0(00(0ELW +:UHTXHVW 63,B7; 86$57B5; ,&B5; 7,0B&+ 7,0B&+ 7,0B83 7,0B&+ 7,0B83 7,0B75,* 7,0B&20 &KDQQHO &KDQQHO 6:WULJJHU 0(00(0ELW +:UHTXHVW &KDQQHO 6:WULJJHU 0(00(0ELW +:UHTXHVW &KDQQHO 6:WULJJHU 0(00(0ELW 86$57B7; ,&B5; 7,0B&+ 7,0B&+ 7,0B83 7,0B&+ 7,0B83 +:UHTXHVW 6:WULJJHU 0(00(0ELW &KDQQHO /RZSULRULW\ 069 1. DMA request mapped on this DMA channel only if the corresponding remapping bit is cleared in the SYSCFG_CFGR1 register. For more details, please refer to Section 9.1.1: SYSCFG configuration register 1 (SYSCFG_CFGR1) on page 157. 172/897 DocID022448 Rev 2 RM0313 Direct memory access controller (DMA) Table 25 lists the DMA1 requests for each channel. Table 25. Summary of DMA1 requests for each channel Peripherals Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 ADC1 SPI ADC1 SPI1_RX SP1_TX SPI2_RX SPI2_TX USART USART3_ TX USART3_RX USART1_T X I2C TIM2 I2C2_TX TIM2_CH3 TIM3 TIM4 TIM2_UP TIM3_CH3 Channel 7 USART1_RX USART2_RX USART2_TX I2C2_RX I2C1_TX TIM3_CH4 TIM3_UP I2C1_RX TIM2_CH2 TIM2_CH4 TIM2_CH1 TIM4_CH1 TIM6 / DAC channel 1 Channel 6 TIM3_CH1 TIM3_TRIG TIM4_CH2 TIM4_CH3 TIM4_UP TIM6_UP DAC1_CH1 TIM7 / DAC channel 2 TIM7_UP DAC1_CH2 TIM18 / DAC channel 3 TIM18_UP DAC2_CH1 TIM15 TIM15_CH1 TIM15_UP TIM15_TRIG TIM15_COM TIM16_CH1 TIM16_UP TIM16 TIM17 TIM17_CH1 TIM17_UP TIM19 TIM19_CH3 TIM19_CH1 TIM19_CH4 TIM16_CH1 TIM16_UP TIM17_CH1 TIM17_UP TIM19_CH2 TIM19_UP DMA2 controller The hardware requests from the peripherals (TIMx, SDADCx, DAC and SPI) are simply logically ORed before entering the DMA2. This means that on one channel, only one request must be enabled at a time. Refer to Figure 23: DMA2 request mapping. The peripheral DMA2 requests can be independently activated/de-activated by programming the DMA2 control bit in the registers of the corresponding peripheral. DocID022448 Rev 2 173/897 183 Direct memory access controller (DMA) RM0313 Figure 23. DMA2 request mapping 3HULSKHUDOUHTXHVWVLJQDOV '0$ )L[HGKDUGZDUHSULRULW\ +LJKSULRULW\ 63,B5; 7,0B&+ 7,0B75,* 63,B7; 7,0B&+ 7,0B83 6'$'& 7,0B83 +:UHTXHVW &KDQQHO 6:WULJJHU 0(00(0ELW +:UHTXHVW &KDQQHO 6:WULJJHU 0(00(0ELW +:UHTXHVW ,QWHUQDO '0$ UHTXHVW &KDQQHO 6:WULJJHU 0(00(0ELW +:UHTXHVW 6'$'& 7,0B&+ 7,0B83 &KDQQHO 6:WULJJHU 0(00(0ELW 6'$'& 7,0B&+ 7,0B83 +:UHTXHVW &KDQQHO 6:WULJJHU 0(00(0ELW /RZSULRULW\ 069 1. DMA request mapped on this DMA channel only if the corresponding remapping bit is cleared in the SYSCFG_CFGR1 register. For more details, please refer to Section 9.1.1: SYSCFG configuration register 1 (SYSCFG_CFGR1) on page 157. 174/897 DocID022448 Rev 2 RM0313 Direct memory access controller (DMA) Table 26 lists the DMA2 requests for each channel. Table 26. Summary of DMA2 requests for each channel Peripherals Channel 1 Channel 2 SPI SPI3_RX SPI3_TX TIM5 TIM5_CH4 TIM5_TRIG TIM5_CH3 TIM5_UP SDADC TIM6 / DAC channel 1 Channel 3 Channel 4 Channel 5 SDADC1 SDADC2 SDADC3 TIM5_CH2 TIM5_CH1 TIM6_UP DAC1_CH1 TIM7 / DAC channel 2 TIM7_UP DAC1_CH2 TIM18 / DAC channel 3 TIM18_UP DAC2_CH1 DocID022448 Rev 2 175/897 183 Direct memory access controller (DMA) 10.5 RM0313 DMA registers Refer to Section 1.1 on page 36 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by bytes (8-bit), half-words (16-bit) or words (32bit). 10.5.1 DMA interrupt status register (DMA_ISR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. TEIF7 HTIF7 TCIF7 GIF7 TEIF6 HTIF6 TCIF6 GIF6 TEIF5 HTIF5 TCIF5 GIF5 r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEIF4 HTIF4 TCIF4 GIF4 TEIF3 HTIF3 TCIF3 GIF3 TEIF2 HTIF2 TCIF2 GIF2 TEIF1 HTIF1 TCIF1 GIF1 r r r r r r r r r r r r r r r r Bits 31:28 Reserved, must be kept at reset value. Bits 27, 23, 19, 15, TEIFx: Channel x transfer error flag (x = 1 ..7) 11, 7, 3 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer error (TE) on channel x 1: A transfer error (TE) occurred on channel x Bits 26, 22, 18, 14, HTIFx: Channel x half transfer flag (x = 1 ..7) 10, 6, 2 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No half transfer (HT) event on channel x 1: A half transfer (HT) event occurred on channel x Bits 25, 21, 17, 13, TCIFx: Channel x transfer complete flag (x = 1 ..7) 9, 5, 1 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer complete (TC) event on channel x 1: A transfer complete (TC) event occurred on channel x Bits 24, 20, 16, 12, GIFx: Channel x global interrupt flag (x = 1 ..7) 8, 4, 0 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No TE, HT or TC event on channel x 1: A TE, HT or TC event occurred on channel x 176/897 DocID022448 Rev 2 RM0313 Direct memory access controller (DMA) 10.5.2 DMA interrupt flag clear register (DMA_IFCR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 CHTIF CTCIF7 7 23 22 21 20 19 18 17 16 Res. Res. Res. Res. CTEIF 7 w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CTEIF 4 CHTIF 4 CTCIF 4 CGIF4 CTEIF 3 w w w w w CHTIF CTCIF3 3 w w CGIF7 CGIF3 w CTEIF6 CHTIF6 CTCIF6 CGIF6 CTEIF2 CHTIF2 CTCIF2 CGIF2 w w w w CTEIF5 CHTIF5 CTCIF5 CTEIF1 CHTIF1 CTCIF1 w w w CGIF5 CGIF1 w Bits 31:28 Reserved, must be kept at reset value. Bits 27, 23, 19, 15, CTEIFx: Channel x transfer error clear (x = 1 ..7) 11, 7, 3 This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TEIF flag in the DMA_ISR register Bits 26, 22, 18, 14, CHTIFx: Channel x half transfer clear (x = 1 ..7) 10, 6, 2 This bit is set and cleared by software. 0: No effect 1: Clears the corresponding HTIF flag in the DMA_ISR register Bits 25, 21, 17, 13, CTCIFx: Channel x transfer complete clear (x = 1 ..7) 9, 5, 1 This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TCIF flag in the DMA_ISR register Bits 24, 20, 16, 12, CGIFx: Channel x global interrupt clear (x = 1 ..7) 8, 4, 0 This bit is set and cleared by software. 0: No effect 1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register DocID022448 Rev 2 177/897 183 Direct memory access controller (DMA) 10.5.3 RM0313 DMA channel x configuration register (DMA_CCRx) (x = 1..7, where x = channel number) Address offset: 0x08 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. MEM2 MEM MINC PINC CIRC DIR TEIE HTIE TCIE EN rw rw rw rw rw rw rw rw rw PL[1:0] rw rw MSIZE[1:0] PSIZE[1:0] rw rw rw rw Bits 31:15 Reserved, must be kept at reset value. Bit 14 MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled Bits 13:12 PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high Bits 11:10 MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits 11: Reserved Bits 9:8 PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits 11: Reserved Bit 7 MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled Bit 6 PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled 178/897 DocID022448 Rev 2 RM0313 Direct memory access controller (DMA) Bit 5 CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled Bit 4 DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory Bit 3 TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled Bit 2 HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled Bit 1 TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled Bit 0 EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled DocID022448 Rev 2 179/897 183 Direct memory access controller (DMA) 10.5.4 RM0313 DMA channel x number of data register (DMA_CNDTRx) (x = 1..7, where x = channel number) Address offset: 0x0C + 0d20 × (channel number – 1) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw NDT[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not. 10.5.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..7, where x = channel number) Address offset: 0x10 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 This register must not be written when the channel is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PA [31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw PA [15:0] rw Bits 31:0 PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address. 180/897 DocID022448 Rev 2 RM0313 Direct memory access controller (DMA) 10.5.6 DMA channel x memory address register (DMA_CMARx) (x = 1..7, where x = channel number) Address offset: 0x14 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 This register must not be written when the channel is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MA [31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw MA [15:0] rw Bits 31:0 MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address. DocID022448 Rev 2 181/897 183 Direct memory access controller (DMA) 10.5.7 RM0313 DMA register map The following table gives the DMA register map and the reset values. TCIF1 GIF1 CGIF7 CTEIF6 CHTIF6 CTCIF6 CGIF6 CTEIF5 CHTIF5 CTCIF5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCIE EN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN 0 TCIE 0 HTIE 0 TEIE 0 DIR PL [1:0] 0 0 0 0 0 0 0 NDT[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HTIE TCIE EN 0 TEIE 0 DIR 0 PINC 0 Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEM2MEM MINC PINC CIRC DIR TEIE HTIE TCIE EN NDT[15:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 PL [1:0] CIRC 0 PSIZE [1:0] 0 0 0 0 0 0 0 0 0 0 0 0 PA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DocID022448 Rev 2 PL [1:0] 0 0 0 PSIZE [1:0] 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 M SIZE [1:0] MA[31:0] Reset value 182/897 HTIE 0 M SIZE [1:0] 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. DMA_CCR4 TEIE 0 MINC 0 Res. 0 Res. 0x44 DIR 0 MEM2MEM 0 DMA_CMAR3 Reset value 0 MA[31:0] Res. 0x3C 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 DMA_CPAR3 Reset value 0 PINC 0 Reset value 0x38 0 Res. 0 Res. DMA_CNDTR3 0 0 Reset value 0x34 0 0 0 Res. DMA_CCR3 0 PA[31:0] Res. 0x30 0 0 CIRC 0 DMA_CMAR2 Reset value 0 0 0 Res. 0x28 0 PSIZE [1:0] 0 DMA_CPAR2 Reset value 0 0 M SIZE [1:0] 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Reset value 0x24 0 MA[31:0] Res. DMA_CNDTR2 0 0 Reset value 0x20 0 MINC 0 Res. DMA_CCR2 0 MEM2MEM 0 Res. 0x1C 0 DMA_CMAR1 Reset value 0 0 NDT[15:0] 0 Res. 0x14 Reset value 0 0 0 PA[31:0] Res. 0x10 0 0 Res. Reset value DMA_CPAR1 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CNDTR1 Res. 0x0C 0 Res. Reset value PL [1:0] 0 PINC 0 CIRC 0 PSIZE [1:0] 0 M SIZE [1:0] 0 Res. 0 CGIF1 HTIF1 CTCIF7 0 CTCIF1 CHTIF7 0 CHTIF1 GIF2 TEIF1 0 CTEIF1 TCIF2 0 CGIF2 HTIF2 0 CTCIF2 0 CHTIF2 GIF3 TEIF2 0 CTEIF2 0 MINC TCIF3 0 CGIF3 HTIF3 0 CTCIF3 0 CHTIF3 GIF4 TEIF3 0 CTEIF3 TCIF4 0 CGIF4 HTIF4 0 CTCIF4 0 CHTIF4 0 MEM2MEM GIF5 TEIF4 0 CTEIF4 0 Res. TCIF5 0 CGIF5 HTIF5 0 Res. 0 Res. GIF6 TEIF5 0 Res. TCIF6 0 Res. HTIF6 0 Res. 0 Res. GIF7 TEIF6 0 Res. TCIF7 0 Res. HTIF7 0 Res. 0 Res. TEIF7 Res. Res. Res. DMA_CCR1 Res. 0x08 Res. Reset value 0 CTEIF7 Res. Res. DMA_IFCR Res. 0x04 Res. Reset value Res. Res. DMA_ISR Res. 0x00 Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Refer to Section 2.2.2 on page 41 for the register boundary addresses. Table 27. DMA register map and reset values 0 RM0313 Direct memory access controller (DMA) Res. Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x08C 0x090 PINC CIRC DIR TEIE HTIE TCIE EN PSIZE [1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CIRC DIR TEIE HTIE TCIE EN PSIZE [1:0] 0 PINC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEM2MEM MINC 0 0 0 PA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CMAR6 Reset value 0 Res. Reset value 0 NDT[15:0] 0 DMA_CPAR6 PL [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CNDTR6 0 0 0 MA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value CIRC DIR TEIE HTIE TCIE EN PSIZE [1:0] 0 PINC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CMAR7 Reset value 0 NDT[15:0] 0 DMA_CPAR7 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CNDTR7 0 PL [1:0] M SIZE [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CCR7 Res. Reserved Reset value 0x088 0 0 Reset value 0x084 0 0 M SIZE [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CCR6 0x07C 0x080 0 Reserved Res. 0x078 0 MA[31:0] Reset value 0x074 0 0 Reset value 0x070 0 MINC 0 0x068 0x06C 0 MEM2MEM 0 DMA_CMAR5 Reset value 0 NDT[15:0] 0 Res. 0x64 Reset value 0 PA[31:0] Res. 0x60 0 Res. Reset value DMA_CPAR5 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CNDTR5 Res. 0x5C 0 Res. Reset value PL [1:0] M SIZE [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CCR5 Res. Reserved Res. 0x54 0x58 0 MINC 0 DMA_CMAR4 Res. 0x50 Reset value 0 PA[31:0] Res. 0x4C 0 DMA_CPAR4 MEM2MEM Reset value NDT[15:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CNDTR4 Res. 0x48 Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 27. DMA register map and reset values (continued) 0 0 MA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved DocID022448 Rev 2 183/897 183 Interrupts and events RM0313 11 Interrupts and events 11.1 Nested vectored interrupt controller (NVIC) 11.1.1 NVIC main features • 1 non-maskable interrupt line (NMI) • 64 maskable interrupt channels • 16 programmable priority levels (2 bits of interrupt priority are used) • Low-latency exception and interrupt handling • Power management control • Implementation of System Control Registers The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to PM0214 programming manual. 11.1.2 SysTick calibration value register The SysTick calibration value is set to 9000, which gives a reference time base of 1 ms with the SysTick clock set to 9 MHz (max fHCLK/8). 11.1.3 Interrupt and exception vectors Table 28 is the vector table for STM32F37xx/STM32F38xx devices. 184/897 Priority Position Table 28. List of vectors Type of priority - - -3 Acronym Description Address - Reserved 0x0000 0000 fixed Reset Reset 0x0000 0004 -2 fixed NMI Non maskable interrupt. The RCC Clock Security System (CSS) is linked to the NMI vector. 0x0000 0008 -1 fixed HardFault Hardware fault 0x0000 000C 0 fixed MemManage MPU fault 0x0000 0010 1 settable BusFault Prefetch fault or memory access error 0x0000 0014 2 settable UsageFault Undefined instruction or illegal state 0x0000 0018 DocID022448 Rev 2 RM0313 Interrupts and events Priority Position Table 28. List of vectors (continued) Type of priority 3 settable SVCall System service call via SWI instruction 0x0000 002C 4 settable DebugMonitor Debug monitor 0x0000 0030 5 settable PendSV Pendable request for system service 0x0000 0038 6 settable SysTick System tick timer 0x0000 003C 0 7 settable WWDG Window Watchdog interrupt 0x0000 0040 1 8 settable PVD Power voltage detector through EXTI line detection interrupt 0x0000 0044 2 9 settable TAMP Tamper and timestamp through EXTI19 line 0x0000 0048 3 10 settable RTC_WKUP RTC 0x0000 004C 4 11 settable FLASH Flash global interrupt 0x0000 0050 5 12 settable RCC RCC global interrupt 0x0000 0054 6 13 settable EXTI0 EXTI Line 0 interrupt 0x0000 0058 7 14 settable EXTI1 EXTI Line 1 interrupt 0x0000 005C 8 15 settable EXTI2_TS EXTI Line 2 and routing interface interrupt 0x0000 0060 9 16 settable EXTI3 EXTI Line 3 interrupt 0x0000 0064 10 17 settable EXTI4 EXTI Line 4 interrupt 0x0000 0068 11 18 settable DMA1_CH1 DMA1 channel 1 interrupt 0x0000 006C 12 19 settable DMA1_CH2 DMA1 channel 2 interrupt 0x0000 0070 13 20 settable DMA1_CH3 DMA1 channel 3 interrupt 0x0000 0074 14 21 settable DMA1_CH4 DMA1 channel 4 interrupt 0x0000 0078 15 22 settable DMA1_CH5 DMA1 channel 5 interrupt 0x0000 007C 16 23 settable DMA1_CH6 DMA1 channel 6 interrupt 0x0000 0080 17 24 settable DMA1_CH7 DMA1 channel 7 interrupt 0x0000 0084 18 25 settable ADC1 ADC1 interrupt 0x0000 0088 19 26 settable CAN TX CAN_TX interrupt 0x0000 008C 20 27 settable CAN RXD CAN_RXD interrupt 0x0000 0090 21 28 settable CAN RXI CAN_RXI interrupt 0x0000 0094 22 29 settable CAN SCE CAN_SCE interrupt 0x0000 0098 Acronym Description DocID022448 Rev 2 Address 185/897 197 Interrupts and events RM0313 Position Priority Table 28. List of vectors (continued) Type of priority 23 30 settable EXTI5_9 EXTI Line[9:5] interrupts 0x0000 009C 24 31 settable TIM15 Timer 15 global interrupt 0x0000 00A0 25 32 settable TIM16 Timer 16 global interrupt 0x0000 00A4 26 33 settable TIM17 Timer 17 global interrupt 0x0000 00A8 27 34 settable TIM18_DAC2 Timer 18 global interrupt/DAC2 underrun interrupt 0x0000 00AC 28 35 settable TIM2 Timer 2 global interrupt 0x0000 00B0 29 36 settable TIM3 Timer 3 global interrupt 0x0000 00B4 30 37 settable TIM4 Timer 4 global interrupt 0x0000 00B8 31 38 settable I2C1_EV I2C1_EV global interrupt/EXTI Line[3:2] interrupts 0x0000 00BC 32 39 settable I2C1_ER I2C1_ER 0x0000 00C0 33 40 settable I2C2_EV I2C2_EV global interrupt/EXTI Line[4:2] interrupts 0x0000 00C4 34 41 settable I2C2_ER I2C2_ER 0x0000 00C8 35 42 settable SPI1 SPI1 global interrupt 0x0000 00CC 36 43 settable SPI2 SPI2 global interrupt 0x0000 00D0 37 44 settable USART1 USART1 global interrupt/EXTI25 (USART1 wakeup event) 0x0000 00D4 38 45 settable USART2 USART2 global interrupt/EXTI26 (USART2 wakeup event) 0x0000 00D8 39 46 settable USART3 USART3 global interrupt/EXTI28 (USART3 wakeup event) 0x0000 00DC 40 47 settable EXTI15_10 EXTI Line[15:10] interrupts 0x0000 00E0 41 48 settable RTC_ALARM_IT RTC alarm interrupt 0x0000 00E4 42 49 settable CEC CEC interrupt 0x0000 00E8 43 50 settable TIM12 Timer 12 global interrupt 0x0000 00EC 44 51 settable TIM13 Timer 13 global interrupt 0x0000 00F0 45 52 settable TIM14 Timer 14 global interrupt 0x0000 00F4 Acronym Description 46- 53Reserved 49 56 186/897 Address 0x0000 00F80x0000 0104 50 57 settable TIM5 Timer 5 global interrupt 0x0000 0108 51 58 settable SPI3 SPI3 global interrupt 0x0000 010C DocID022448 Rev 2 RM0313 Interrupts and events Priority Position Table 28. List of vectors (continued) Type of priority Acronym Description 52- 59Reserved 53 60 0x0000 01100x0000 0114 54 61 settable TIM6_DAC1 Timer 6 global interrupt/DAC1 underrun interrupt 0x0000 0118 55 62 settable TIM7 Timer 7 global interrupt 0x0000 011C 56 63 settable DMA2_CH1 DMA2 channel 1 interrupt 0x0000 0120 57 64 settable DMA2_CH2 DMA2 channel 2 interrupt 0x0000 0124 58 65 settable DMA2_CH3 DMA2 channel 3 interrupt 0x0000 0128 59 66 settable DMA2_CH4 DMA2 channel 4 interrupt 0x0000 012C 60 67 settable DMA2_CH5 DMA2 channel 5 interrupt 0x0000 0130 61 68 settable SDADC1 ADC sigma delta 1 (SDADC1) global interrupt 0x0000 0134 62 69 settable SDADC2 ADC sigma delta 2 (SDADC2) global interrupt 0x0000 0138 63 70 settable SDADC3 ADC sigma delta 1 (SDADC3) global interrupt 0x0000 013C 64 71 settable COMP1_2 Comparator 1/comparator 2 global interrupts (EXTI21/EXTI22) 0x0000 0140 65- 72Reserved 73 80 0x0000 01440x0000 0164 74 81 settable USB_HP USB high priority interrupt 0x0000 0168 75 82 settable USB_LP USB low priority interrupt 0x0000 016C 76 83 settable USB_WAKEUP USB wakeup interrupt 0x0000 0170 77 84 Reserved 78 85 settable 0x0000 0174 TIM19 Timer 19 global interrupt 79- 86Reserved 80 87 81 11.2 Address 88 settable 0x0000 0178 0x0000 017C0x0000 0180 FPU Floating point unit interrupt 0x0000 0184 Extended interrupts and events controller (EXTI) The extended interrupts and events controller (EXTI) manages the external and internal asynchronous events/interrupts and generates the event request to the CPU/Interrupt Controller and a wake-up request to the Power Manager. DocID022448 Rev 2 187/897 197 Interrupts and events RM0313 The EXTI allows the management of up to 29 external/internal event line (21 external event lines and 8 internal event lines). The active edge of each external interrupt line can be chosen independently, whilst for internal interrupt the active edge is always the rising one. An interrupt could be left pending: in case of an external one, a status register is instantiated and indicates the source of the interrupt; an event is always a simple pulse and it’s used for triggering the core Wake-up. For internal interrupts, the pending status is assured by the generating IP, so no need for a specific flag. Each input line can be masked independently for interrupt or event generation, in addition the internal lines are sampled only in STOP mode. This controller allows also to emulate the (only) external events by software, multiplexed with the corresponding hardware event line, by writing to a dedicated register. 11.2.1 Main features The EXTI main features are the following: 11.2.2 • support generation of up to 29 event/interrupt requests; • Independent configuration of each line as an external or an internal event requests; • Independent mask on each event/interrupt line • Automatic disable of internal lines when system is not in STOP mode • Independent trigger for external event/interrupt line • Dedicated status bit for external interrupt line; • Emulation for all the external event requests. Block diagram The extended interrupt/event block diagram is shown in Figure 24. 188/897 DocID022448 Rev 2 RM0313 Interrupts and events Figure 24. EXTI extended interrupt/event block diagram !-"!!0"BUS 0#,+ 0ERIPHERALINTERFACE 0ENDING REQUEST REGISTER 4O.6)#INTERRUPT CONTROLLER )NTERRUPT MASK REGISTER 3OFTWARE INTERRUPT EVENT 2EGISTER 2ISING TRIGGER SELECTION REGSITER &ALLING TRIGGER SELECTION REGSITER 0ULSE GENERATOR %DGEDETECT CIRCUIT )NPUT LINE %VENT MASK REGISTER -36 11.2.3 Wakeup event management The STM32F37xx/STM32F38xx is able to handle external or internal events in order to wake up the core (WFE). The wakeup event can be generated either by: 11.2.4 • enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the Cortex-M4 with FPU System Control register. When the MCU resumes from WFE, the EXTI peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. • or by configuring an external or internal EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set. Asynchronous Internal Interrupts Some communication peripherals (UART, I2C, CEC) are able to generate events when the system is in run mode and also when the system is in stop mode allowing to wake up the system from stop mode. To accomplish this, the peripheral is asked to generate both a synchronized (to the system clock, e.g. APB clock) and an asynchronous version of the event. DocID022448 Rev 2 189/897 197 Interrupts and events 11.2.5 RM0313 Functional description For the external interrupt lines, to generate the interrupt, the interrupt line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the interrupt request by writing a ‘1’ to the corresponding bit in the interrupt mask register. When the selected edge occurs on the external interrupt line, an interrupt request is generated. The pending bit corresponding to the interrupt line is also set. This request is reset by writing a ‘1’ in the pending register. For the internal interrupt lines, the active edge is always the rising edge, the interrupt is enabled by default in the interrupt mask register and there is no corresponding pending bit in the pending register. To generate the event, the event line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the event request by writing a ‘1’ to the corresponding bit in the event mask register. When the selected edge occurs on the event line, an event pulse is generated. The pending bit corresponding to the event line is not set. For the external lines, an interrupt/event request can also be generated by software by writing a ‘1’ in the software interrupt/event register. Note: The interrupts or events associated to the internal lines can be triggered only when the system is in STOP mode. If the system is still running, no interrupt/event is generated. Hardware interrupt selection To configure a line as interrupt source, use the following procedure: • Configure the corresponding mask bit in the EXTI_IMR register. • Configure the Trigger Selection bits of the Interrupt line (EXTI_RTSR and EXTI_FTSR) • Configure the enable and mask bits that control the NVIC IRQ channel mapped to the EXTI so that an interrupt coming from one of the EXTI line can be correctly acknowledged. Hardware event selection To configure a line as event source, use the following procedure: • Configure the corresponding mask bit in the EXTI_EMR register. • Configure the Trigger Selection bits of the Event line (EXTI_RTSR and EXTI_FTSR) Software interrupt/event selection Any of the external lines can be configured as software interrupt/event lines. The following is the procedure to generate a software interrupt. 190/897 • Configure the corresponding mask bit (EXTI_IMR, EXTI_EMR) • Set the required bit of the software interrupt register (EXTI_SWIER) DocID022448 Rev 2 RM0313 11.2.6 Interrupts and events External and internal interrupt/event line mapping In the STM32F37xx/STM32F38xx, 29 interrupt/event lines are available: 8 lines are internal (including the reserved ones) and the remaining 21 lines are external. The GPIOs are connected to the 16 external interrupt/event lines in the following manner: Figure 25. Extended interrupt/event GPIO mapping %84);=BITSINTHE393#&'?%84)#2REGISTER 0! 0" 0# 0$ 0% 0& %84) %84);=BITSINTHE393#&'?%84)#2REGISTER 0! 0" 0# 0$ 0% 0& %84) %84);=BITSINTHE393#&'?%84)#2REGISTER 0! 0" 0# 0$ 0% 0& %84) -36 DocID022448 Rev 2 191/897 197 Interrupts and events RM0313 The remaining lines are connected as follow: Note: 192/897 • EXTI line 16 is connected to the PVD output • EXTI line 17 is connected to the RTC Alarm event • EXTI line 18 is connected to USB FS wakeup event • EXTI line 19 is connected to RTC tamper and Timestamps • EXTI line 20 is connected to RTC wakeup • EXTI line 21 is connected to Comparator 1 output • EXTI line 22 is connected to Comparator 2 output • EXTI line 23 is connected to I2C1 wakeup • EXTI line 24 is connected to I2C2 wakeup • EXTI line 25 is connected to USART1 wakeup • EXTI line 26 is connected to USART2 wakeup • EXTI line 27 is connected to CEC wakeup • EXTI line 28 is connected to USART3 wakeup. EXTI lines 18, 20, 23, 24, 25, 26, 27, and 28 are internal. DocID022448 Rev 2 RM0313 Interrupts and events 11.3 EXTI registers Refer to Section 1.1 on page 36 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 11.3.1 Interrupt mask register (EXTI_IMR) Address offset: 0x00 Reset value: 0x1F80 0000 (See note below) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. MR28 MR27 MR26 MR25 MR24 MR23 MR22 MR21 MR20 MR19 MR18 MR17 MR16 rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:29 Reserved, must be kept at reset value (0). Bits 28:0 MRx: Interrupt Mask on external/internal line x 0: Interrupt request from Line x is masked 1: Interrupt request from Line x is not masked Note: The reset value for the internal lines (23, 24, 25, 26, 27 and 28) is set to ‘1’ in order to enable the interrupt by default. 11.3.2 Event mask register (EXTI_EMR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. MR28 MR27 MR26 MR25 MR24 MR23 MR22 MR21 MR20 MR19 MR18 MR17 MR16 rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:29 Reserved, must be kept at reset value (0). Bits 28:0 MRx: Event mask on external/internal line x 0: Event request from Line x is masked 1: Event request from Line x is not masked DocID022448 Rev 2 193/897 197 Interrupts and events 11.3.3 RM0313 Rising trigger selection register (EXTI_RTSR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TR19 Res. TR17 TR16 rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:20 Reserved, must be kept at reset value. Bit 19 TR19: Rising trigger event configuration bit of line 19 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line. Bits 18 Reserved, must be kept at reset value. Bits 17:0 TRx: Rising trigger event configuration bit of line x (x = 17 to 0) 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line. Note: The external wakeup lines are edge triggered. No glitches must be generated on these lines. If a rising edge on an external interrupt line occurs during a write operation to the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition. 11.3.4 Falling trigger selection register (EXTI_FTSR) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TR19 Res. TR17 TR16 rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:20 Reserved, must be kept at reset value. Bit 19 TR19: Falling trigger event configuration bit of line 19 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line. Bits 18 Reserved, must be kept at reset value. Bits 17:0 TRx: Falling trigger event configuration bit of line x (x = 17 to 0) 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line. 194/897 DocID022448 Rev 2 RM0313 Interrupts and events Note: The external wakeup lines are edge triggered. No glitches must be generated on these lines. If a falling edge on an external interrupt line occurs during a write operation to the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition. 11.3.5 Software interrupt event register (EXTI_SWIER) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 SWIER 19 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 18 Res. rw SWIER SWIER SWIER SWIER SWIER SWIER SWIER 15 14 13 12 11 10 9 rw rw rw rw rw rw rw 3 2 17 16 SWIER SWIER 17 16 rw rw 1 0 SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw Bits 31:20 Reserved, must be kept at reset value. Bits 19 SWIER19: Software interrupt on line 19 If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation. This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a 1 into the bit). Bits 18 Reserved, must be kept at reset value. Bits 17:0 SWIERx: Software interrupt on line x (x = 17 to 0) If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation. This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a 1 into the bit). 11.3.6 Pending register (EXTI_PR) Address offset: 0x14 Reset value: undefined 31 30 29 28 27 26 25 24 23 22 21 20 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19 18 PR19 Res. rc_w1 17 16 PR17 PR16 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PR15 PR14 PR13 PR12 PR11 PR10 PR9 PR8 PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 DocID022448 Rev 2 195/897 197 Interrupts and events RM0313 Bits 31:20 Reserved, must be kept at reset value. Bits 19 PR19: Pending bit on line 19 0: No trigger request occurred 1: selected trigger request occurred This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit. Bits 18 Reserved, must be kept at reset value. Bits 19:0 PRx: Pending bit on line x (x = 17 to 0) 0: No trigger request occurred 1: selected trigger request occurred This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a 1 into the bit. 196/897 DocID022448 Rev 2 RM0313 11.3.7 Interrupts and events EXTI register map The following table gives the EXTI register map and the reset values. Res. 1 1 1 1 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. 0 0 0 Res. 0 Res. 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TR[17:0] 0 0 0 0 0 0 Res. 0 0 0 TR[17:0] 0 0 0 0 0 Res. 0 0 0 0 SWIER[17:0] 0 0 0 0 0 0 0 0 Res. PR19 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EXTI_PR Res. 0x14 0 0 0 Res. Reset value SWIER19 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EXTI_SWIER Res. 0x10 0 0 0 Res. Reset value TR19 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. EXTI_FTSR 0 TR19 0 Reset value 0x0C 0 MR[28:0] Res. Res. Res. EXTI_RTSR Res. Reset value 0x08 1 Res. EXTI_EMR Res. 0x04 1 Res. Reset value MR[28:0] Res. EXTI_IMR Res. 0x00 Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 29. Extended interrupt/event controller register map and reset values 0 0 PR[17:0] 0 0 0 0 0 0 0 0 0 0 Refer toSection 2.2.2 on page 41 for the register boundary addresses. DocID022448 Rev 2 197/897 197 Analog-to-digital converter (ADC) RM0313 12 Analog-to-digital converter (ADC) 12.1 ADC introduction The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 18 multiplexed channels allowing it measure signals from 16 external and three internal sources. A/D conversion of the various channels can be performed in single, continuous, scan or discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit data register. The analog watchdog feature allows the application to detect if the input voltage goes outside the user-defined high or low thresholds. The ADC input clock is generated from the PCLK2 clock divided by a prescaler (refer to Table 11). 12.2 ADC main features • 12-bit resolution • Interrupt generation at End of Conversion, End of Injected conversion and Analog watchdog event • Single and continuous conversion modes • Scan mode for automatic conversion of channel 0 to channel ‘n’ • Self-calibration • Data alignment with in-built data coherency • Channel by channel programmable sampling time • External trigger option for both regular and injected conversion • Discontinuous mode • ADC conversion time: – 1 µs at 56 MHz (1.17 µs at 72 MHz) • ADC supply requirement: 2.4 V to 3.6 V • ADC input range: VREF- ≤VIN ≤VREF+ • DMA request generation during regular channel conversion The block diagram of the ADC is shown in Figure 26. Note: 198/897 VREF-,if available (depending on package), must be tied to VSSA. DocID022448 Rev 2 RM0313 ADC functional description Figure 26 shows a single ADC block diagram and Table 30 gives the ADC pin description. Figure 26. Single ADC block diagram )ODJV ,QWHUUXSW HQDEOHELWV (QGRIFRQYHUVLRQ (QGRILQMHFWHGFRQYHUVLRQ $QDORJZDWFKGRJHYHQW (2& (2&,( -(2& -(2&,( $:' $:',( $'&,QWHUUXSWWR19,& $QDORJZDWFKGRJ &RPSDUHUHVXOW +LJK7KUHVKROGELWV /RZ7KUHVKROGELWV ,QMHFWHGGDWDUHJLVWHUV [ELWV 95() 966$ 95() 5HJXODUGDWDUHJLVWHU ELWV 9''$ $QDORJ 08; '0$UHTXHVW $GGUHVV'DWDEXV 12.3 Analog-to-digital converter (ADC) $'&[B,1 $'&[B,1 *3,2 3RUWV XSWR XSWR $'&[B,1 ,QMHFWHG FKDQQHOV $QDORJWRGLJLWDO FRQYHUWHU $'&&/. 5HJXODU FKDQQHOV 7HPSVHQVRU 9 5(),17 9 %$7 )URP$'&SUHVFDOHU -(;76(/>@ELWV 7,0B&& 7,0B&& 7,0B75*2 7,0B&& 7,0B&& 7,0B75*2 -(;75,* ELW 6WDUWWULJJHU LQMHFWHGJURXS (;7,B (;75,* ELW (;76(/>@ELWV 7,0B75*2 7,0B&& 7,0B&& 7,0B&& 7,0B75*2 7,0B&& 6WDUWWULJJHU UHJXODUJURXS (;7,B 069 DocID022448 Rev 2 199/897 224 Analog-to-digital converter (ADC) RM0313 Table 30. ADC pins Name Signal type Remarks VREF+ Input, analog reference positive The higher/positive reference voltage for the ADC, 2.4 V ≤VREF+ ≤VDDA VDDA(1) Input, analog supply Analog power supply equal to VDD and 2.4 V ≤VDDA ≤3.6 V VREF- Input, analog reference negative The lower/negative reference voltage for the ADC, VREF- = VSSA VSSA(1) Input, analog supply ground Ground for analog power supply equal to VSS ADC_IN[15:0] Analog signals Up to 16 external analog channels plus three internal: VBAT, temperature sensor, and VREFINT(2) 1. VDDA and VSSA have to be connected to VDD and VSS, respectively. 2. For full details about the ADC I/O pins, please refer to the “Pinouts and pin descriptions” section of the corresponding device datasheet. 12.3.1 ADC on-off control The ADC can be powered-on by setting the ADON bit in the ADC_CR2 register. When the ADON bit is set for the first time, it wakes up the ADC from Power Down mode. Conversion starts when ADON bit is set for a second time by software after ADC power-up time (tSTAB). You can stop conversion and put the ADC in power down mode by resetting the ADON bit. In this mode the ADC consumes almost no power (only a few µA). 12.3.2 ADC clock The ADCCLK clock provided by the Clock Controller is synchronous with the PCLK2 (APB2 clock). The RCC controller has a dedicated programmable prescaler for the ADC clock (refer to Section 6: Reset and clock control (RCC) for more details. 12.3.3 Channel selection There are 16 multiplexed channels. It is possible to organize the conversions in two groups: regular and injected. A group consists of a sequence of conversions which can be done on any channel and in any order. For instance, it is possible to do the conversion in the following order: Ch3, Ch8, Ch2, Ch2, Ch0, Ch2, Ch2, Ch15. • The regular group is composed of up to 16 conversions. The regular channels and their order in the conversion sequence must be selected in the ADC_SQRx registers. The total number of conversions in the regular group must be written in the L[3:0] bits in the ADC_SQR1 register. • The injected group is composed of up to 4 conversions. The injected channels and their order in the conversion sequence must be selected in the ADC_JSQR register. The total number of conversions in the injected group must be written in the L[1:0] bits in the ADC_JSQR register. If the ADC_SQRx or ADC_JSQR registers are modified during a conversion, the current conversion is reset and a new start pulse is sent to the ADC to convert the new chosen group. 200/897 DocID022448 Rev 2 RM0313 Analog-to-digital converter (ADC) Temperature sensor/VREFINT/VBAT internal channels The Temperature sensor is connected to channel ADC_IN16, the internal reference voltage VREFINT is connected to ADC_IN17, and the VBAT is connected to ADC_IN18. These two internal channels can be selected and converted as injected or regular channels. 12.3.4 Single conversion mode In Single conversion mode the ADC does one conversion. This mode is started either by setting the ADON bit in the ADC_CR2 register (for a regular channel only) or by external trigger (for a regular or injected channel), while the CONT bit is 0. Once the conversion of the selected channel is complete: • • If a regular channel was converted: – The converted data is stored in the 16-bit ADC_DR register – The EOC (End Of Conversion) flag is set – and an interrupt is generated if the EOCIE is set. If an injected channel was converted: – The converted data is stored in the 16-bit ADC_DRJ1 register – The JEOC (End Of Conversion Injected) flag is set – and an interrupt is generated if the JEOCIE bit is set. The ADC is then stopped. 12.3.5 Continuous conversion mode In continuous conversion mode ADC starts another conversion as soon as it finishes one. This mode is started either by external trigger or by setting the ADON bit in the ADC_CR2 register, while the CONT bit is 1. After each conversion: • • 12.3.6 If a regular channel was converted: – The converted data is stored in the 16-bit ADC_DR register – The EOC (End Of Conversion) flag is set – An interrupt is generated if the EOCIE is set. If an injected channel was converted: – The converted data is stored in the 16-bit ADC_DRJ1 register – The JEOC (End Of Conversion Injected) flag is set – An interrupt is generated if the JEOCIE bit is set. Timing diagram As shown in Figure 27, the ADC needs a stabilization time of tSTAB before it starts converting accurately. After the start of ADC conversion and after 14 clock cycles, the EOC flag is set and the 16-bit ADC Data register contains the result of the conversion. DocID022448 Rev 2 201/897 224 Analog-to-digital converter (ADC) RM0313 Figure 27. Timing diagram $'&B&/. 6(7$'21 $'&SRZHURQ 6WDUWVWFRQYHUVLRQ 6WDUWQH[WFRQYHUVLRQ $'&FRQYHUVLRQ $'& W67$% 1H[W$'&FRQYHUVLRQ &RQYHUVLRQWLPH 7RWDOFRQYWLPH (2& 6RIWZDUHUHVHWV(2&ELW 069 12.3.7 Analog watchdog The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is below a low threshold or above a high threshold. These thresholds are programmed in the 12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can be enabled by using the AWDIE bit in the ADC_CR1 register. The threshold value is independent of the alignment selected by the ALIGN bit in the ADC_CR2 register. The comparison is done before the alignment (see Section 12.5). The analog watchdog can be enabled on one or more channels by configuring the ADC_CR1 register as shown in Table 31. Figure 28. Analog watchdog guarded area $QDORJYROWDJH +LJKWKUHVKROG +75 *XDUGHGDUHD /75 /RZWKUHVKROG 069 Table 31. Analog watchdog channel selection Channels to be guarded by analog watchdog AWDSGL bit AWDEN bit JAWDEN bit None x 0 0 All injected channels 0 0 1 All regular channels 0 1 0 All regular and injected channels 0 1 1 Single(1) injected channel 1 0 1 (1) 202/897 ADC_CR1 register control bits (x = don’t care) Single regular channel 1 1 0 Single(1) regular or injected channel 1 1 1 DocID022448 Rev 2 RM0313 Analog-to-digital converter (ADC) 1. Selected by AWDCH[4:0] bits 12.3.8 Scan mode This mode is used to scan a group of analog channels. Scan mode can be selected by setting the SCAN bit in the ADC_CR1 register. Once this bit is set, ADC scans all the channels selected in the ADC_SQRx registers (for regular channels) or in the ADC_JSQR (for injected channels). A single conversion is performed for each channel of the group. After each end of conversion the next channel of the group is converted automatically. If the CONT bit is set, conversion does not stop at the last selected group channel but continues again from the first selected group channel. When using scan mode, DMA bit must be set and the direct memory access controller is used to transfer the converted data of regular group channels to SRAM after each update of the ADC_DR register. The injected channel converted data is always stored in the ADC_JDRx registers. 12.3.9 Injected channel management Triggered injection To use triggered injection, the JAUTO bit must be cleared and SCAN bit must be set in the ADC_CR1 register. Note: 1. Start conversion of a group of regular channels either by external trigger or by setting the ADON bit in the ADC_CR2 register. 2. If an external injected trigger occurs during the regular group channel conversion, the current conversion is reset and the injected channel sequence is converted in Scan once mode. 3. Then, the regular group channel conversion is resumed from the last interrupted regular conversion. If a regular event occurs during an injected conversion, it doesn’t interrupt it but the regular sequence is executed at the end of the injected sequence. Figure 29 shows the timing diagram. When using triggered injection, one must ensure that the interval between trigger events is longer than the injection sequence. For instance, if the sequence length is 28 ADC clock cycles (that is two conversions with a 1.5 clock-period sampling time), the minimum interval between triggers must be 29 ADC clock cycles. Auto-injection If the JAUTO bit is set, then the injected group channels are automatically converted after the regular group channels. This can be used to convert a sequence of up to 20 conversions programmed in the ADC_SQRx and ADC_JSQR registers. In this mode, external trigger on injected channels must be disabled. If the CONT bit is also set in addition to the JAUTO bit, regular channels followed by injected channels are continuously converted. For ADC clock prescalers ranging from 4 to 8, a delay of 1 ADC clock period is automatically inserted when switching from regular to injected sequence (respectively injected to regular). When the ADC clock prescaler is set to 2, the delay is 2 ADC clock periods. Note: It is not possible to use both auto-injected and discontinuous modes simultaneously. DocID022448 Rev 2 203/897 224 Analog-to-digital converter (ADC) RM0313 Figure 29. Injected conversion latency $'&FORFN ,QMHYHQW 5HVHW$'& 62& 0D[ODWHQF\ 069 1. The maximum latency value can be found in the electrical characteristics of the STM32F101xx and STM32F103xx datasheets. 12.3.10 Discontinuous mode Regular group This mode is enabled by setting the DISCEN bit in the ADC_CR1 register. It can be used to convert a short sequence of n conversions (n <=8) which is a part of the sequence of conversions selected in the ADC_SQRx registers. The value of n is specified by writing to the DISCNUM[2:0] bits in the ADC_CR1 register. When an external trigger occurs, it starts the next n conversions selected in the ADC_SQRx registers until all the conversions in the sequence are done. The total sequence length is defined by the L[3:0] bits in the ADC_SQR1 register. Example: n = 3, channels to be converted = 0, 1, 2, 3, 6, 7, 9, 10 1st trigger: sequence converted 0, 1, 2; an EOC event is generated at each conversion 2nd trigger: sequence converted 3, 6, 7; an EOC event is generated at each conversion 3rd trigger: sequence converted 9, 10; an EOC event is generated at each conversion 4th trigger: sequence converted 0, 1, 2; an EOC event is generated at each conversion Note: When a regular group is converted in discontinuous mode, no rollover will occur. When all sub groups are converted, the next trigger starts conversion of the first sub-group. In the example above, the 4th trigger reconverts the 1st sub-group channels 0, 1 and 2. Injected group This mode is enabled by setting the JDISCEN bit in the ADC_CR1 register. It can be used to convert the sequence selected in the ADC_JSQR register, channel by channel, after an external trigger event. When an external trigger occurs, it starts the next channel conversions selected in the ADC_JSQR registers until all the conversions in the sequence are done. The total sequence length is defined by the JL[1:0] bits in the ADC_JSQR register. Example: n = 1, channels to be converted = 1, 2, 3 1st trigger: channel 1 converted 2nd trigger: channel 2 converted 204/897 DocID022448 Rev 2 RM0313 Analog-to-digital converter (ADC) 3rd trigger: channel 3 converted and EOC and JEOC events generated 4th trigger: channel 1 Note: When all injected channels are converted, the next trigger starts the conversion of the first injected channel. In the example above, the 4th trigger reconverts the 1st injected channel 1. It is not possible to use both auto-injected and discontinuous modes simultaneously. The user must avoid setting discontinuous mode for both regular and injected groups together. Discontinuous mode must be enabled only for one group conversion. 12.4 Calibration The ADC has an built-in self calibration mode. Calibration significantly reduces accuracy errors due to internal capacitor bank variations. During calibration, an error-correction code (digital word) is calculated for each capacitor, and during all subsequent conversions, the error contribution of each capacitor is removed using this code. Calibration is started by setting the CAL bit in the ADC_CR2 register. Once calibration is over, the CAL bit is reset by hardware and normal conversion can be performed. It is recommended to calibrate the ADC once at power-on. The calibration codes are stored in the ADC_DR as soon as the calibration phase ends. Note: It is recommended to perform a calibration after each power-up. Before starting a calibration the ADC must have been in power-off state (ADON bit = ‘0’) for at least two ADC clock cycles. Figure 30. Calibration timing diagram &/. &DOLEUDWLRQUHVHWE\KDUGZDUH &$/ &DOLEUDWLRQRQJRLQJ W &$/ 1RUPDO$'&FRQYHUVLRQ $'& FRQYHUVLRQ 069 12.5 Data alignment ALIGN bit in the ADC_CR2 register selects the alignment of data stored after conversion. Data can be left or right aligned as shown in Figure 31. and Figure 32. The injected group channels converted data value is decreased by the user-defined offset written in the ADC_JOFRx registers so the result can be a negative value. The SEXT bit is the extended sign value. For regular group channels no offset is subtracted so only twelve bits are significant. DocID022448 Rev 2 205/897 224 Analog-to-digital converter (ADC) RM0313 Figure 31. Right alignment of data ,QMHFWHGJURXS 6(;7 6(;7 6(;7 6(;7 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 5HJXODUJURXS ' 069 Figure 32. Left alignment of data ,QMHFWHGJURXS 6(;7 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 5HJXODUJURXS ' ' ' ' ' ' ' 069 12.6 Channel-by-channel programmable sample time ADC samples the input voltage for a number of ADC_CLK cycles which can be modified using the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can be sampled with a different sample time. The total conversion time is calculated as follows: Tconv = Sampling time + 12.5 cycles Example: With an ADCCLK = 12 MHz and a sampling time of 1.5 cycles: Tconv = 1.5 + 12.5 = 14 cycles = µs 12.7 Conversion on external trigger Conversion can be triggered by an external event (e.g. timer capture, EXTI line). If the EXTTRIG control bit is set then external events are able to trigger a conversion. The EXTSEL[2:0] and JEXTSEL[2:0] control bits allow the application to select decide which out of 8 possible events can trigger conversion for the regular and injected groups. Note: 206/897 When an external trigger is selected for ADC regular or injected conversion, only the rising edge of the signal can start the conversion. DocID022448 Rev 2 RM0313 Analog-to-digital converter (ADC) Table 32. External trigger for regular channels for ADC1 Source Type EXTSEL[2:0] TIM19_TRGO 000 TIM19_CC3 001 TIM19_CC4 TIM2_CC2 event Internal signal from on-chip timers 010 011 TIM3_TRGO event 100 TIM4_CC4 event 101 EXTI line 11 External pin 110 SWSTART Software control bit 111 Table 33. External trigger for injected channels for ADC1 Source Connection type JEXTSEL[2:0] TIM19_CC1 000 TIM19_CC2 001 TIM2_TRGO event TIM2_CC1 event Internal signal from on-chip timers 010 011 TIM3_CC4 event 100 TIM4_TRGO event 101 EXTI line 15 External pin 110 JSWSTART Software control bit 111 The software source trigger events can be generated by setting a bit in a register (SWSTART and JSWSTART in ADC_CR2). A regular group conversion can be interrupted by an injected trigger. 12.8 DMA request Since converted regular channels value are stored in a unique data register, it is necessary to use DMA for conversion of more than one regular channel. This avoids the loss of data already stored in the ADC_DR register. Only the end of conversion of a regular channel generates a DMA request, which allows the transfer of its converted data from the ADC_DR register to the destination location selected by the user. 12.9 Temperature sensor and internal reference voltage The temperature sensor can be used to measure the ambient temperature (TA) of the device. The temperature sensor is internally connected to the ADC_IN16 input channel DocID022448 Rev 2 207/897 224 Analog-to-digital converter (ADC) RM0313 which is used to convert the sensor output voltage into a digital value. The recommended sampling time for the temperature sensor is 17.1 µs. The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and Comparators. VREFINT is internally connected to the ADC_IN17 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode. Figure 33 shows the block diagram of the temperature sensor. When not in use, this sensor can be put in power down mode. Note: The TSVREFE bit must be set to enable both internal channels: ADC_IN16 (temperature sensor) and ADC_IN17 (VREFINT) conversion. The temperature sensor output voltage changes linearly with temperature. The offset of this line varies from chip to chip due to process variation (up to 45 °C from one chip to another). The internal temperature sensor is more suited for applications that detect temperature variations instead of absolute temperatures. If accurate temperature readings are needed, an external temperature sensor part should be used. During the manufacturing process, the calibration data of the temperature sensor and the internal voltage reference are stored in the system memory area. The user application can then read them and use them to improve the accuracy of the temperature sensor or the internal reference. Refer to the datasheet for additional information. Figure 33. Temperature sensor and VREFINT channel block diagram 7HPSHUDWXUH VHQVRU 96(16( $'&B,1 $'& ,QWHUQDO SRZHUEORFN 95(),17 $'&B,1 $GGUHVV'DWDEXV 7695()(FRQWUROELW 06Y9 Reading the temperature To use the sensor: 208/897 DocID022448 Rev 2 RM0313 Analog-to-digital converter (ADC) 1. Select the ADC_IN16 input channel. 2. Select a sample time of 17.1 µs 3. Set the TSVREFE bit in the ADC control register 2 (ADC_CR2) to wake up the temperature sensor from power down mode. 4. Start the ADC conversion by setting the ADON bit (or by external trigger). 5. Read the resulting VSENSE data in the ADC data register 6. Obtain the temperature using the following formula: Temperature (in °C) = {(V25 - VSENSE) / Avg_Slope} + 25. Where, V25 = VSENSE value for 25° C and Avg_Slope = Average Slope for curve between Temperature vs. VSENSE (given in mV/° C or µV/ °C). Refer to the Electrical characteristics section for the actual values of V25 and Avg_Slope. Note: The sensor has a startup time after waking from power down mode before it can output VSENSE at the correct level. The ADC also has a startup time after power-on, so to minimize the delay, the ADON and TSVREFE bits should be set at the same time. 12.10 Battery voltage monitoring The VBATEN bit in the SYSCFG_CTRL register allows the backup battery voltage on the VBAT pin to be measured. As the VBAT voltage can be higher than VDDA, to ensure the correct operation of the ADC, the VBAT pin is internally connected to a bridge divider by 2. This bridge is automatically enabled when VBATEN is set, to connect VBAT/2 to the ADC1_IN18 input channel. Consequently, the converted digital value is half the VBAT voltage. To prevent any unwanted consumption on the battery, it is recommended to enable the bridge divider only when needed, for ADC conversion. 12.11 ADC interrupts An interrupt can be produced on end of conversion for regular and injected groups and when the analog watchdog status bit is set. Separate interrupt enable bits are available for flexibility. Two other flags are present in the ADC_SR register, but there is no interrupt associated with them: • JSTRT (Start of conversion for injected group channels) • STRT (Start of conversion for regular group channels) Table 34. ADC interrupts Interrupt event Event flag Enable Control bit End of conversion regular group EOC EOCIE End of conversion injected group JEOC JEOCIE Analog watchdog status bit is set AWD AWDIE DocID022448 Rev 2 209/897 224 Analog-to-digital converter (ADC) 12.12 RM0313 ADC registers Refer to Section 1.1 on page 36 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 12.12.1 ADC status register (ADC_SR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 STRT JSTRT JEOC EOC AWD rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Res. 15 14 13 12 11 10 9 8 7 Res. Bits 31:5 Reserved, must be kept at reset value. Bit 4 STRT: Regular channel Start flag This bit is set by hardware when regular channel conversion starts. It is cleared by software. 0: No regular channel conversion started 1: Regular channel conversion has started Bit 3 JSTRT: Injected channel Start flag This bit is set by hardware when injected channel group conversion starts. It is cleared by software. 0: No injected group conversion started 1: Injected group conversion has started Bit 2 JEOC: Injected channel end of conversion This bit is set by hardware at the end of all injected group channel conversion. It is cleared by software. 0: Conversion is not complete 1: Conversion complete Bit 1 EOC: End of conversion This bit is set by hardware at the end of a group channel conversion (regular or injected). It is cleared by software or by reading the ADC_DR. 0: Conversion is not complete 1: Conversion complete Bit 0 AWD: Analog watchdog flag This bit is set by hardware when the converted voltage crosses the values programmed in the ADC_LTR and ADC_HTR registers. It is cleared by software. 0: No Analog watchdog event occurred 1: Analog watchdog event occurred 210/897 DocID022448 Rev 2 RM0313 Analog-to-digital converter (ADC) 12.12.2 ADC control register 1 (ADC_CR1) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. 15 14 13 DISCNUM[2:0] rw rw rw 23 22 AWDE N JAWDE N rw rw 21 20 19 18 17 16 2 1 0 rw rw Res. 12 11 10 9 8 7 6 5 JDISC EN DISC EN JAUT O AWD SGL SCAN JEOC IE AWDIE EOCIE rw rw rw rw rw rw rw rw 4 3 AWDCH[4:0] rw rw rw Bits 31:24 Reserved, must be kept at reset value. Bit 23 AWDEN: Analog watchdog enable on regular channels This bit is set/reset by software. 0: Analog watchdog disabled on regular channels 1: Analog watchdog enabled on regular channels Bit 22 JAWDEN: Analog watchdog enable on injected channels This bit is set/reset by software. 0: Analog watchdog disabled on injected channels 1: Analog watchdog enabled on injected channels Bits 21:16 Reserved, must be kept at reset value. Bits 15:13 DISCNUM[2:0]: Discontinuous mode channel count These bits are written by software to define the number of regular channels to be converted in discontinuous mode, after receiving an external trigger. 000: 1 channel 001: 2 channels ....... 111: 8 channels Bit 12 JDISCEN: Discontinuous mode on injected channels This bit set and cleared by software to enable/disable discontinuous mode on injected group channels 0: Discontinuous mode on injected channels disabled 1: Discontinuous mode on injected channels enabled Bit 11 DISCEN: Discontinuous mode on regular channels This bit set and cleared by software to enable/disable Discontinuous mode on regular channels. 0: Discontinuous mode on regular channels disabled 1: Discontinuous mode on regular channels enabled Bit 10 JAUTO: Automatic Injected Group conversion This bit set and cleared by software to enable/disable automatic injected group conversion after regular group conversion. 0: Automatic injected group conversion disabled 1: Automatic injected group conversion enabled DocID022448 Rev 2 211/897 224 Analog-to-digital converter (ADC) RM0313 Bit 9 AWDSGL: Enable the watchdog on a single channel in scan mode This bit set and cleared by software to enable/disable the analog watchdog on the channel identified by the AWDCH[4:0] bits. 0: Analog watchdog enabled on all channels 1: Analog watchdog enabled on a single channel Bit 8 SCAN: Scan mode This bit is set and cleared by software to enable/disable Scan mode. In Scan mode, the inputs selected through the ADC_SQRx or ADC_JSQRx registers are converted. 0: Scan mode disabled 1: Scan mode enabled Note: An EOC or JEOC interrupt is generated only on the end of conversion of the last channel if the corresponding EOCIE or JEOCIE bit is set Bit 7 JEOCIE: Interrupt enable for injected channels This bit is set and cleared by software to enable/disable the end of conversion interrupt for injected channels. 0: JEOC interrupt disabled 1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set. Bit 6 AWDIE: Analog watchdog interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. 0: Analog watchdog interrupt disabled 1: Analog watchdog interrupt enabled Bit 5 EOCIE: Interrupt enable for EOC This bit is set and cleared by software to enable/disable the End of Conversion interrupt. 0: EOC interrupt disabled 1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set. Bits 4:0 AWDCH[4:0]: Analog watchdog channel select bits These bits are set and cleared by software. They select the input channel to be guarded by the Analog watchdog. 00000: ADC analog Channel0 00001: ADC analog Channel1 .... 01111: ADC analog Channel15 10000: ADC analog Channel16 10001: ADC analog Channel17 10010: ADC analog Channel18 Other values reserved. Note: ADC1 analog Channel16, Channel17 and Channel 18 are internally connected to the temperature sensor, to VREFINT and to VBAT/2 respectively. 212/897 DocID022448 Rev 2 RM0313 Analog-to-digital converter (ADC) 12.12.3 ADC control register 2 (ADC_CR2) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. 15 14 JEXTT RIG rw 13 12 JEXTSEL[2:0] rw rw Bits 31:24 rw 23 22 21 20 19 TSVRE SWSTA JSWST EXTTR FE RT ART IG 11 10 9 8 ALIGN Res. DMA rw Res. rw 18 17 16 EXTSEL[2:0] Res. rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 RST CAL CAL CONT ADON rw rw rw rw Res. Reserved, must be kept at reset value. Bit 23 TSVREFE: Temperature sensor and VREFINT enable This bit is set and cleared by software to enable/disable the temperature sensor and VREFINT channel. 0: Temperature sensor and VREFINT channel disabled 1: Temperature sensor and VREFINT channel enabled Bit 22 SWSTART: Start conversion of regular channels This bit is set by software to start conversion and cleared by hardware as soon as conversion starts. It starts a conversion of a group of regular channels if SWSTART is selected as trigger event by the EXTSEL[2:0] bits. 0: Reset state 1: Starts conversion of regular channels Bit 21 JSWSTART: Start conversion of injected channels This bit is set by software and cleared by software or by hardware as soon as the conversion starts. It starts a conversion of a group of injected channels (if JSWSTART is selected as trigger event by the JEXTSEL[2:0] bits. 0: Reset state 1: Starts conversion of injected channels Bit 20 EXTTRIG: External trigger conversion mode for regular channels This bit is set and cleared by software to enable/disable the external trigger used to start conversion of a regular channel group. 0: Conversion on external event disabled 1: Conversion on external event enabled Bits 19:17 EXTSEL[2:0]: External event select for regular group These bits select the external event used to trigger the start of conversion of a regular group: 000: Timer 19 TRGO event 001: Timer 19 CC3 event 010: Timer 19 CC4 event 011: Timer 2 CC2 event 100: Timer 3 TRGO event 101: Timer 4 CC4 event 110: EXTI line 11 111: SWSTART Bit 16 Reserved, must be kept at reset value. DocID022448 Rev 2 213/897 224 Analog-to-digital converter (ADC) RM0313 Bit 15 JEXTTRIG: External trigger conversion mode for injected channels This bit is set and cleared by software to enable/disable the external trigger used to start conversion of an injected channel group. 0: Conversion on external event disabled 1: Conversion on external event enabled Bits 14:12 JEXTSEL[2:0]: External event select for injected group These bits select the external event used to trigger the start of conversion of an injected group: 000: Timer 19 CC1 event 001: Timer 19 CC2 event 010: Timer 2 TRGO event 011: Timer 2 CC1 event 100: Timer 3 CC4 event 101: Timer 4 TRGO event 110: EXTI line15 111: JSWSTART Bit 11 ALIGN: Data alignment This bit is set and cleared by software. Refer to Figure 31.and Figure 32. 0: Right Alignment 1: Left Alignment Bits 10:9 Reserved, must be kept at reset value. Bit 8 DMA: Direct memory access mode This bit is set and cleared by software. Refer to the DMA controller chapter for more details. 0: DMA mode disabled 1: DMA mode enabled Bits 7:4 Reserved, must be kept at reset value. Bit 3 RSTCAL: Reset calibration This bit is set by software and cleared by hardware. It is cleared after the calibration registers are initialized. 0: Calibration register initialized. 1: Initialize calibration register. Note: If RSTCAL is set when conversion is ongoing, additional cycles are required to clear the calibration registers. 214/897 DocID022448 Rev 2 RM0313 Analog-to-digital converter (ADC) Bit 2 CAL: A/D Calibration This bit is set by software to start the calibration. It is reset by hardware after calibration is complete. 0: Calibration completed 1: Enable calibration Bit 1 CONT: Continuous conversion This bit is set and cleared by software. If set conversion takes place continuously till this bit is reset. 0: Single conversion mode 1: Continuous conversion mode Bit 0 ADON: A/D converter ON / OFF This bit is set and cleared by software. If this bit holds a value of zero and a 1 is written to it then it wakes up the ADC from Power Down state. Conversion starts when this bit holds a value of 1 and a 1 is written to it. The application should allow a delay of tSTAB between power up and start of conversion. Refer to Figure 27. 0: Disable ADC conversion/calibration and go to power down mode. 1: Enable ADC and to start conversion Note: If any other bit in this register apart from ADON is changed at the same time, then conversion is not triggered. This is to prevent triggering an erroneous conversion. 12.12.4 ADC sample time register 1 (ADC_SMPR1) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 14 SMP 15[0] rw 13 12 11 SMP14[2:0] rw rw 25 24 23 SMP18[2:0] Res. 15 26 rw 21 20 19 18 SMP16[2:0] 17 16 SMP15[2:1] rw rw rw rw rw rw rw rw rw rw rw 10 9 8 7 6 5 4 3 2 1 0 SMP13[2:0] rw 22 SMP17[2:0] rw SMP12[2:0] rw rw rw SMP11[2:0] rw rw rw SMP10[2:0] rw rw rw rw Bits 31:24 Reserved, must be kept at reset value. Bits 23:0 SMPx[2:0]: Channel x Sample time selection These bits are written by software to select the sample time individually for each channel. During sample cycles channel selection bits must remain unchanged. 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles ADC1 analog Channel16, Channel 17 and Channel18 are internally connected to the temperature sensor, to VREFINT and to VBAT/2 respectively. DocID022448 Rev 2 215/897 224 Analog-to-digital converter (ADC) 12.12.5 RM0313 ADC sample time register 2 (ADC_SMPR2) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 Res. Res. 15 14 SMP 5[0] rw 28 27 26 SMP9[2:0] 24 23 22 21 20 SMP7[2:0] 19 18 SMP6[2:0] 17 16 SMP5[2:1] rw rw rw rw rw rw rw rw rw rw rw rw rw rw 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SMP4[2:0] rw 25 SMP8[2:0] rw SMP3[2:0] rw rw rw SMP2[2:0] rw rw rw SMP1[2:0] rw rw rw SMP0[2:0] rw rw rw rw Bits 31:30 Reserved, must be kept at reset value. Bits 29:0 SMPx[2:0]: Channel x Sample time selection These bits are written by software to select the sample time individually for each channel. During sample cycles channel selection bits must remain unchanged. 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles ADC1 analog Channel16 and Channel 17 are internally connected to the temperature sensor and to VREFINT, respectively. 12.12.6 ADC injected channel data offset register x (ADC_JOFRx)(x=1..4) Address offset: 0x14-0x20 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 rw rw rw rw rw Res. Res. Bits 31:12 7 JOFFSETx[11:0] rw rw rw rw rw rw rw Reserved, must be kept at reset value. Bits 11:0 JOFFSETx[11:0]: Data offset for injected channel x These bits are written by software to define the offset to be subtracted from the raw converted data when converting injected channels. The conversion result can be read from in the ADC_JDRx registers. 216/897 DocID022448 Rev 2 RM0313 Analog-to-digital converter (ADC) 12.12.7 ADC watchdog high threshold register (ADC_HTR) Address offset: 0x24 Reset value: 0x0000 0FFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 rw rw rw rw rw Res. 15 14 13 12 11 10 9 8 7 HT[11:0] Res. rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 HT[11:0]: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. 12.12.8 ADC watchdog low threshold register (ADC_LTR) Address offset: 0x28 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 rw rw rw rw rw Res. 15 14 13 Res. 12 11 10 9 8 7 LT[11:0] rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 LT[11:0]: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. DocID022448 Rev 2 217/897 224 Analog-to-digital converter (ADC) 12.12.9 RM0313 ADC regular sequence register 1 (ADC_SQR1) Address offset: 0x2C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 14 13 rw rw SQ16[0] rw 12 11 10 9 8 rw rw rw rw SQ15[4:0] rw 22 21 20 19 L[3:0] Res. 15 23 18 17 16 SQ16[4:1] rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw SQ14[4:0] rw SQ13[4:0] rw Bits 31:24 Reserved, must be kept at reset value. Bits 23:20 L[3:0]: Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. 0000: 1 conversion 0001: 2 conversions ..... 1111: 16 conversions Bits 19:15 SQ16[4:0]: 16th conversion in regular sequence These bits are written by software with the channel number (0..17) assigned as the 16th in the conversion sequence. Bits 14:10 SQ15[4:0]: 15th conversion in regular sequence Bits 9:5 SQ14[4:0]: 14th conversion in regular sequence Bits 4:0 SQ13[4:0]: 13th conversion in regular sequence 218/897 DocID022448 Rev 2 RM0313 Analog-to-digital converter (ADC) 12.12.10 ADC regular sequence register 2 (ADC_SQR2) Address offset: 0x30 Reset value: 0x0000 0000 31 30 28 rw rw 13 12 14 SQ10 [0] rw 27 26 25 24 23 rw rw rw rw rw 11 10 9 8 7 SQ12[4:0] Res. 15 29 rw Bits 31:30 rw 21 20 19 18 rw rw rw rw rw rw rw 6 5 4 3 2 1 0 rw rw SQ11[4:0] SQ9[4:0] rw 22 rw rw rw rw 16 SQ10[4:1] SQ8[4:0] rw 17 SQ7[4:0] rw rw rw rw rw Reserved, must be kept at reset value. Bits 29:26 SQ12[4:0]: 12th conversion in regular sequence These bits are written by software with the channel number (0..17) assigned as the 12th in the sequence to be converted. Bits 24:20 SQ11[4:0]: 11th conversion in regular sequence Bits 19:15 SQ10[4:0]: 10th conversion in regular sequence Bits 14:10 SQ9[4:0]: 9th conversion in regular sequence Bits 9:5 SQ8[4:0]: 8th conversion in regular sequence Bits 4:0 SQ7[4:0]: 7th conversion in regular sequence DocID022448 Rev 2 219/897 224 Analog-to-digital converter (ADC) RM0313 12.12.11 ADC regular sequence register 3 (ADC_SQR3) Address offset: 0x34 Reset value: 0x0000 0000 31 30 28 rw rw 13 12 14 SQ4 [0] rw 27 26 25 24 23 rw rw rw rw rw 11 10 9 8 7 SQ6[4:0] Res. 15 29 rw Bits 31:30 rw 21 20 19 18 rw rw rw rw rw rw rw 6 5 4 3 2 1 0 rw rw SQ5[4:0] SQ3[4:0] rw 22 rw rw rw rw 16 SQ4[4:1] SQ2[4:0] rw 17 SQ1[4:0] rw rw rw rw rw Reserved, must be kept at reset value. Bits 29:25 SQ6[4:0]: 6th conversion in regular sequence These bits are written by software with the channel number (0..17) assigned as the 6th in the sequence to be converted. Bits 24:20 SQ5[4:0]: 5th conversion in regular sequence Bits 19:15 SQ4[4:0]: 4th conversion in regular sequence Bits 14:10 SQ3[4:0]: 3rd conversion in regular sequence Bits 9:5 SQ2[4:0]: 2nd conversion in regular sequence Bits 4:0 SQ1[4:0]: 1st conversion in regular sequence 220/897 DocID022448 Rev 2 RM0313 Analog-to-digital converter (ADC) 12.12.12 ADC injected sequence register (ADC_JSQR) Address offset: 0x38 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 14 13 JSQ4[0] rw 12 11 10 9 8 JSQ3[4:0] rw rw Bits 31:22 rw 20 19 18 rw rw rw rw rw rw 5 4 3 2 1 0 rw rw JL[1:0] Res. 15 21 7 6 rw rw rw rw 16 JSQ4[4:1] JSQ2[4:0] rw 17 JSQ1[4:0] rw rw rw rw rw Reserved, must be kept at reset value. Bits 21:20 JL[1:0]: Injected sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence. 00: 1 conversion 01: 2 conversions 10: 3 conversions 11: 4 conversions Bits 19:15 JSQ4[4:0]: 4th conversion in injected sequence (when JL[1:0] = 3)(1) These bits are written by software with the channel number (0..17) assigned as the 4th in the sequence to be converted. Note: Unlike a regular conversion sequence, if JL[1:0] length is less than four, the channels are converted in a sequence starting from (4-JL). Example: ADC_JSQR[21:0] = 10 00011 00011 00111 00010 means that a scan conversion will convert the following channel sequence: 7, 3, 3. (not 2, 7, 3) Bits 14:10 JSQ3[4:0]: 3rd conversion in injected sequence (when JL[1:0] = 3) Bits 9:5 JSQ2[4:0]: 2nd conversion in injected sequence (when JL[1:0] = 3) Bits 4:0 JSQ1[4:0]: 1st conversion in injected sequence (when JL[1:0] = 3) 1. When JL=3 (4 injected conversions in the sequencer), the ADC converts the channels in this order: JSQ1[4:0] >> JSQ2[4:0] >> JSQ3[4:0] >> JSQ4[4:0] When JL=2 (3 injected conversions in the sequencer), the ADC converts the channels in this order: JSQ2[4:0] >> JSQ3[4:0] >> JSQ4[4:0] When JL=1 (2 injected conversions in the sequencer), the ADC converts the channels in this order: JSQ3[4:0] >> JSQ4[4:0] When JL=0 (1 injected conversion in the sequencer), the ADC converts only JSQ4[4:0] channel DocID022448 Rev 2 221/897 224 Analog-to-digital converter (ADC) RM0313 12.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4) Address offset: 0x3C - 0x48 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 r r r r r r r Res. 7 JDATA[15:0] r r r Bits 31:16 r r r r r r Reserved, must be kept at reset value. Bits 15:0 JDATA[15:0]: Injected data These bits are read only. They contain the conversion result from injected channel x. The data is left or right-aligned as shown in Figure 31 and Figure 32. 12.12.14 ADC regular data register (ADC_DR) Address offset: 0x4C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 r r r r r r r Res. 7 DATA[15:0] r r r r r r r r r Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 DATA[15:0]: Regular data These bits are read only. They contain the conversion result from the regular channels. The data is left or right-aligned as shown in Figure 31 and Figure 32. 222/897 DocID022448 Rev 2 0x2C ADC_SQR1 Reset value 0 0 0 0 L[3:0] 0 0 0 0 DocID022448 Rev 2 0 SQ16[4:0] 0 0 Res. Res. Res. Res. Res. Res. Res. Res. SCAN JEOC IE AWDIE EOCIE 0 0 0 0 0 0 JEXTSE L[2:0] Res. Res. Res. Res. Res. 0 DMA Res. AWD SGL Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. ADC_JOFR1 JAUTO 0 0 Res. 0 DISCEN 0 0 ALIGN 0 JDISCEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Sample time bits SMPx_x 0 0 Reset value Reset value Reset value Reset value Reset value Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ15[4:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JOFFSET2[11:0] 0 JOFFSET3[11:0] 0 JOFFSET4[11:0] 0 HT[11:0] 0 LT[11:0] 0 0 ADON JOFFSET1[11:0] CONT 0 0 CAL 0 JSTRT JEOC EOC AWD Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 Res. STRT Reset value RSTCAL 0 Res. Res. Sample time bits SMPx_x 0 0 Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. DISC NUM [2:0] JEXTTRIG 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. EXTTRIG 0 Res. 0 Res. JSWSTART 0 Res. 0 Res. SWSTART 0 Res. Res. 0 Res. TSVREFE EXTSEL [2:0] Res. Res. Res. 0 Res. JAWDEN ADC_CR2 Res. Res. Res. 0 Res. 0 Res. Res. 0 Res. AWDEN 0 Res. 0 Res. Reset value 0 Res. Res. Res. 0 Res. 0 Res. Res. Res. 0 Res. ADC_SMPR2 Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. 0 Res. ADC_SMPR1 Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Reset value Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. ADC_LTR 0 Res. 0x28 ADC_HTR 0 Res. 0x24 ADC_JOFR4 Res. 0x20 ADC_JOFR3 0 Res. 0x1C ADC_JOFR2 0 Res. 0x18 ADC_SR Res. 0x14 Register Res. 0x10 Res. Reset value Res. 0x0C Res. 0x08 Res. 0x04 ADC_CR1 Res. 0x00 Res. Offset Res. RM0313 Analog-to-digital converter (ADC) 12.12.15 ADC register map The following table summarizes the ADC registers. Table 35. ADC register map and reset values 0 0 0 0 0 AWDCH[4:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ14[4:0] SQ13[4:0] 0 0 0 0 0 223/897 224 Analog-to-digital converter (ADC) RM0313 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ1[4:0] 0 0 JSQ2[4:0] 0 0 0 0 0 0 JSQ1[4:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATA[15:0] 0 0 0 0 0 0 0 0 0 JDATA[15:0] 0 0 0 0 0 0 0 0 0 JDATA[15:0] 0 0 0 0 0 0 0 0 0 Regular DATA[15:0] 0 DocID022448 Rev 2 0 SQ2[4:0] 0 0 0 0 0 0 0 Refer to Section 2.2.2 on page 41 for the register boundary addresses. 224/897 0 SQ7[4:0] JDATA[15:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ADC_DR 0 0 Res. Reset value 0x4C 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ADC_JDR4 0 JSQ3[4:0] 0 Res. Reset value 0x48 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ADC_JDR3 0 0 Res. Reset value 0x44 0 SQ8[4:0] SQ3[4:0] 0 Res. ADC_JDR2 0 JSQ4[4:0] Reset value 0x40 SQ9[4:0] SQ4[4:0] Res. 0 0 Res. 0 Res. 0 Res. 0 Res. Res. Res. ADC_JDR1 0 Res. 0 Reset value 0x3C 0 SQ5[4:0] Res. SQ6[4:0] 0 JL[1:0] 0 SQ10[4:0] Res. 0 Res. ADC_JSQR Res. 0x38 Res. Reset value 0 SQ11[4:0] Res. ADC_SQR3 Res. 0x34 0 Res. Reset value SQ12[4:0] Res. Res. ADC_SQR2 Res. 0x30 Register 31 Offset Res. Table 35. ADC register map and reset values (continued) 0 0 0 RM0313 Sigma-delta analog-to-digital converter (SDADC) 13 Sigma-delta analog-to-digital converter (SDADC) 13.1 Introduction The SDADC module is a high-performance and low-power sigma-delta analog-to-digital converter, featuring 16-bit resolution and 9 differential analog channels with selectable gains. The conversion speed is up to 16.6 ksps (kilo-samples per second) for each SDADC when converting multiple channels and up to 50 ksps per SDADC if only one channel conversion is used. There are two conversion modes: single conversion mode and continuous mode, capable of automatically scanning any number of channels. The data can be automatically stored in a system RAM buffer, reducing the software overhead. A flexible timer triggering system can be used to control the start of conversion of the three SDADCs. This timing control is capable of triggering simultaneous conversions or inserting a programmable delay between the SDADCs. Reference voltage for SDADC can be selected from external reference pins, internal 1.2/1.8V reference or SDADC analog power supply. Four power modes are supported: Normal, Slow, Standby and Power down. In Standby mode, references stay powered on to reduce the startup time. DocID022448 Rev 2 225/897 262 Sigma-delta analog-to-digital converter (SDADC) 13.2 SDADC main features • 16-bit sigma-delta architecture • 5 differential input pairs, or 9 single-ended inputs, or a combination • High-performance data throughput: – 16.6 ksps input sampling rate when multiplexing between different channels – 50 ksps input sampling rate for single-channel operation • Self-calibration • 7 gain settings from 0.5x to 32x • Full-scale single-ended conversion mode referenced to ground in addition to differential mode • Each channel can choose between 3 user-defined configurations, where each configuration specifies: – • Analog gain at the input of the channel – Conversion mode: differential vs. full-scale single-ended referenced to ground – Calibration offset Selectable reference voltage which determines the input signal range and digital endof-scale: – Internal VDDSDx: VREF = analog supply, 2.4 V-3.6 V (2.2 V-3.6 V in Slow mode) – Internal bandgap: VREF = 1.2 V – Internal bandgap: VREF = 1.8 V – External: VREF = 1.1 V to analog supply • Continuous conversion • Start-of-conversion synchronization with – Software trigger – Internal timers – External events – start-of-conversion of another (first) SDADC • “Regular” conversions can be requested at any time or even in continuous mode without having any impact on the timing of “injected” conversions • Two’s-complement output format • DMA may be used to read the conversion data • End of conversion, overrun, and end of calibration interrupts • 3 low power modes (refer to the datasheet for the current consumption values): • 226/897 RM0313 – Slow mode where the device operates from a reduced clock frequency – Standby mode – Power down mode All three SDADCs can share up to 23 input pins which may be configured in any combination of single-ended (up to 21) or differential inputs (up to 11). DocID022448 Rev 2 RM0313 13.3 Sigma-delta analog-to-digital converter (SDADC) SDADC pins Table 36. ADC pins Name 13.4 Signal Type Remarks When the external reference is selected (REFV=00), this pin must be driven externally to a voltage between 1.1 V and VDDSDx. When an internal reference is selected (REFV is 01, 10, or 11), this pin must have an external capacitance connected to VREFSD-. VREFSD+ Input or In/Out, positive analog reference VREFSD- Input, negative This pin, when present, must be driven to the same voltage analog reference level as VSSSD. VDDSDx Input, analog supply Analog power supply. Must be greater than 2.4 V (or 2.2 V in Slow mode) and less than 3.6 V. VSSSD Input, analog supply ground Analog ground power supply. SDADCx_AIN[8:0]P Analog input Positive differential analog inputs for the 9 channels. SDADCx_AIN[8:0]M Analog input Negative differential analog inputs for the 9 channels. SDADC clock The clock source for SDADC is derived from the system clock. This clock is divided by a selectable divider with 50% duty cycle. Any of the following division ratios can be selected: 2, 4, 6, 8,10,12,14,16, 20, 24, 28, 32, 36, 40, 44, 48. The SDADC clock is automatically stopped in deepsleep mode. The maximum operating frequency of the SDAC is 6 MHz. Its minimum operating frequency is 500 kHz. A detailed diagram of SDADC clock is given in Section 7.2.9: SDADC clock on page 105 Figure 34. SDADC clock block diagram (SDADC enable) and (not deepsleep) System clock Total division ratio: 2, 4,6,8,10,12,16, 20,24, 28,32,36, 40,44, 48 CK_SDAD MS30230V1 DocID022448 Rev 2 227/897 262 Sigma-delta analog-to-digital converter (SDADC) 13.5 RM0313 SDADC functional description Figure 35. Single SDADC block diagram FNBVGDG IURP5&& -(2&) -(2&,( -295) -295,( 5(2&) 5(2&,( 5295) 5295,( (2&$/) (2&$/,( 0+]RU0+]PLQN+] 9''6'[ EDQGJDS 5()9 6/2:&. 6'$'& ,QWHUUXSW 95()6' 6'$'& FORFN *DLQ FN VH]U FRQILJXUDWLRQ VHOHFWRU 5'$7$>@ 56:67$57 56<1& 56:67$57 -6<1& -67$57 /RJLFLPSOHPHQWHG RQO\LQ6'$'&DQG 6'$'& -6:67$57 -(;7(1 -(;76(/ 7,0[ 6'$'&B&21)5 6'$'&B&21)5 6'$'&B&21)5 &21)&+>@ &21)&+>@ &21)&+>@ 5HJXODUFKDQQHO 5&+>@ VWDUW FRQILJXUDWLRQ FKDQQHO VHOHFWRU ,QMHFWHGFKDQQHOV -&+*>@ -'$7$>@ Ȉ¨ -67$57 6'B$'&[B$,13 6'B$'&[B$,10 YUHI VORZ 7,0\ 6'B$'&[B$,13 6'B$'&[B$,10 RIIVHW 6'B$'&[B$,13 6'B$'&[B$,10 -36 13.5.1 SDADC on-off control The SDADC is enabled by setting the ADON bit in the SDADC_CR2 register. After the SDADC is powered on, it needs 100 µs to stabilize before it can start a conversion or launch calibration (unless PDI=1, see next section). An action requested in the meantime will be automatically started as soon as stabilization is complete. The end of stabilization is signalled by bit STABIP in the SDAC_ISR register. Clearing ADON stops any conversion which may be in progress and puts the SDADC in power down mode. 228/897 DocID022448 Rev 2 RM0313 13.5.2 Sigma-delta analog-to-digital converter (SDADC) Power down and Standby low power modes In order to reduce consumption, the SDADC can be automatically put into either Standby mode or power down mode when it is idle. “Idle” is defined as when RCIP=0, JCIP=0, and CALIBIP=0. Setting PDI in the SDADC_CR1 register causes the SDADC to enter power down mode when idle, where it consumes about 10 µA instead of up to 1.2 mA (see datasheet for exact values). Whenever exiting power down mode, a period of 100 µs is needed for stabilization. During stabilization, a conversion may be requested, but it will not start until stabilization is complete (STABIP=0). Similarly, setting SBI in the SDADC_CR1 register puts the SDADC in Standby mode when idle, where it consumes a maximum of about 200 µA. Whenever exiting Standby mode conversions, a period of 50 µs is required for stabilization. While the SDADC is stabilizing, the stabilization in progress status bit, STABIP, in SDADC_ISR is set to ‘1’. When enforcing the stabilization times, the SDADC measures these durations assuming that the prescaler outputs a clock at 6 MHz. This means that the 100 µs period after power on is defined as 600 SDADC clock cycles (or 150 if SLOWCK=1, where the SDADC frequency should be 1.5 MHz), and the 50 µs period after exiting Standby mode is defined as 300 SDADC clock cycles (or 75 if SLOWCK=1). When SBI=1, if a conversion or calibration is requested within the first 50 µs after ADON is activated, a stabilization period of 100 µs (rather than 50 µs) is observed starting from the moment that the conversion or calibration is requested. 13.5.3 SDADC clock The SDADC clock, which is used to drive the analog logic, is generated by the RCC block. When not in Slow mode, its prescaler should be configured so that the SDADC can run at its maximum frequency of 6 MHz. The minimum operating frequency of the SDADC is 500 kHz. Slow mode Setting the SLOWCK bit in the SDADC_CR1 register puts the SDADC in Slow mode. When SLOWCK=1, the analog consumes less and is able to operate down to a voltage of 2.2 V, but the frequency of the SDADC clock must be reduced to 1.5 MHz. The minimum frequency is still 500 kHz in Slow mode. 13.5.4 Channel selection There are 9 multiplexed channels which can be selected for conversion using the injected channel group and using the regular channel. The injected channel group is a selection of any or all of the 9 channels. JCHG[8:0] in the SDADC_JCHGR register selects the channels of the injected group, where JCHG[i]=1 means that channel i is selected. Injected conversions are always executed in scan mode, which means that each of the selected channels are converted in series. The highest channel (channel 8, if selected) is converted first, followed immediately by the next lower channel until all the channels selected by JCHG[8:0] have been converted. DocID022448 Rev 2 229/897 262 Sigma-delta analog-to-digital converter (SDADC) RM0313 Injected conversions can be launched by software or by a trigger. They are never interrupted by regular conversions. The regular channel is a selection of just one of the 9 channels. RCH[3:0] in the SDADC_CR2 register indicates the selected channel. Regular conversions can be launched only by software (not by a trigger). A sequence of continuous regular conversions is temporarily interrupted when a injected conversion is requested. 13.5.5 Differential and single-ended modes Each SDADC channel has 2 differential inputs (positive and negative: SDADCx_AIN[n]P, SDADCx_AIN[n]M). Configuring of those inputs to pins connection can be obtained several measurement modes. Differential mode: Simple mode where both - positive and negative inputs - are connected to external pins. The output signal is positive or negative depending on the connected signal polarity. The corresponding SE[1:0] bits must be set to “00” (see Section 13.5.6: Configuring the analog inputs) to select this mode. In additional to this differential mode, conversions may be performed in one of two singleended modes. When in single-ended mode, the negative input is set to 0 V internally, leaving the corresponding pin for the negative input (SDADCx_AIN[n]M) free to be used for other purposes. The signal to be measured is applied to the positive input. Single-ended offset mode: The corresponding SE[1:0] bits must be set to “01” (see Section 13.5.6: Configuring the analog inputs) to select this mode.The output signal is always positive, thus excluding the negative half of the dynamic range. In this mode, the signal to noise ratio (SNR) is degraded by 6 dB. Single-ended zero reference mode: The corresponding SE[1:0] bits must be set to “11” (see Section 13.5.6: Configuring the analog inputs) to select this mode. This mode injects an offset of half scale to the SDADC thus maintaining the full positive/negative dynamic range like in differential mode. In this mode, the offset is dependent on gain variations. 230/897 DocID022448 Rev 2 RM0313 Sigma-delta analog-to-digital converter (SDADC) Examples of possible modes Figure 36. Switch configuration in single-ended mode &+VLQJ 3$' $,13 $,10 &+VLQJ 3$' $,13 $,10 &+VLQJ 3$' $,13 $,10 &+VLQJ 3$' $,13 $,10 &+VLQJ 3$' $,13 $,10 &+VLQJ 3$' $,13 $,10 &+VLQJ 3$' $,13 $,10 &+VLQJ 3$' $,13 $,10 &+VLQJ 3$' $,13 $,10 3$' 5()0 06Y9 • All analog switches on the left are open. • All analog switches on the right are closed. • CH8 to CH0 are used in single-ended mode. • REFM is used. • PAD 9 is not used. DocID022448 Rev 2 231/897 262 Sigma-delta analog-to-digital converter (SDADC) RM0313 Figure 37. Switch configuration in differential mode &+GLII &+GLII 3$' $,13 $,10 3$' $,13 $,10 3$' $,13 $,10 3$' $,13 $,10 3$' $,13 $,10 3$' $,13 $,10 3$' $,13 $,10 3$' $,13 $,10 3$' $,13 $,10 &+GLII &+GLII &+GLII 3$' 5()0 06Y9 232/897 • All analog switches on the left are closed. • All analog switches on the right are open. • CH8, CH6, CH4, CH2, and CH0 are in differential mode. • CH7, CH5, CH3 and CH1 are not used. • REFM is not used. DocID022448 Rev 2 RM0313 Sigma-delta analog-to-digital converter (SDADC) Figure 38. Switch configuration in mixed mode (example 1) 3$' $,13 $,10 3$' $,13 $,10 &+VLQJ 3$' $,13 $,10 &+VLQJ 3$' $,13 $,10 3$' $,13 $,10 3$' $,13 $,10 3$' $,13 $,10 3$' $,13 $,10 3$' $,13 $,10 &+GLII &+GLII &+GLII &+VLQJ 3$' 5()0 06Y9 • CH8, CH4 and CH2 are used as differential. • CH6, CH5 and CH0 are used in single-ended mode. • REFM is used. • PAD 9 is not used. DocID022448 Rev 2 233/897 262 Sigma-delta analog-to-digital converter (SDADC) RM0313 Figure 39. Switch configuration in mixed mode (example 2) &+VLQJ 3$' $,13 $,10 3$' $,13 $,10 3$' $,13 $,10 3$' $,13 $,10 3$' $,13 $,10 3$' $,13 $,10 &+VLQJ 3$' $,13 $,10 &+VLQJ 3$' $,13 $,10 3$' $,13 $,10 &+GLII &+GLII &+GLII 3$' 5()0 06Y9 13.5.6 • CH6, CH4 and CH0 are used as differential. • CH8, CH2 and CH1 are used in single-ended mode. • REFM is used. • PAD 1 is not used. Configuring the analog inputs The following parameters must be configured for the analog inputs: • Gain. There are 5 analog gain settings (1/2x, 1x, 2x, 4x, 8x) and 2 digital gain settings (16x, 32x). • Single-ended modes (SE) (see Section 13.5.5: Differential and single-ended modes). • Common mode. The common mode setting (VSSSD, VDDSDx, or VDDSDx/2) is used only in the determination of the offset during the calibration sequence. • Offset. The 12-bit offset is applied to the conversion results. This value varies from part to part and also depends on the common mode, on the SE setting, and on the gain if SE=11. This value can be determined automatically during the calibration sequence or it can be written by software. Three distinct configurations can be specified using the SDADC_CONF0R, SDADC_CONF1R, and SDADC_CONF2R registers. Each SDADC_CONFxR register contains the fields GAINx[2:0], COMMONx[1:0], SE[1:0], and OFFSETx[11:0]. Each individual input can select one of the three configurations, by way of the SDADC_CONFCHR1 and SDADC_CONFCHR2 registers. 13.5.7 Launching calibration and determining the offset values Calibration can be used to determine the offset values of the configurations defined in each of the three SDADC_CONFxR registers. OFFSETx[11:0] is determined based on GAINx[2:0], COMMONx[1:0], and SEx[1:0] (where x is 0, 1, or 2). 234/897 DocID022448 Rev 2 RM0313 Sigma-delta analog-to-digital converter (SDADC) During the offset calibration positive and negative SDADC inputs are shorted internally and connected to common voltage given by COMMONx[1:0] setting. GAINx[2:0] is applied and then is performed a conversion which determines the OFFSETx[11:0] value (12-bit signed value). The calibration sequence consists of the following steps: 13.5.8 • The SDADC_CONFxR registers must be written. If only 1 distinct configuration is used, then it must be defined in the SDADC_CONF0R register. If only 2 distinct configurations are used, then they must be defined in the SDADC_CONF0R and SDADC_CONF1R registers. • The SDADC_CR2 register is written: – “00” written to CALIBCNT[1:0] if only OFFSET0 is to be determined, “01” for both OFFSET0 and OFFSET1, or “10” to determine all three offset values, – ‘1’ must be written to STARTCALIB to launch calibration. • The calibration sequence then executes, taking 30720 ADC cycles (5.12 ms at 6 MHz) for each offset calculation. Thus, all three offsets are calculated, the entire sequence lasts 15.36 ms at 6 MHz. • The offset values are automatically stored in the corresponding OFFSETx[11:0] fields. Launching conversions Injected conversions can be launched using the following methods: • Software: writing ‘1’ to the JSWSTART bit in the SDADC_CR2 register. • Trigger: the JEXTSEL[2:0] bits select the trigger signal while the JEXTEN bit activates the trigger and selects the active edge at the same time. • Synchronous with SDADC1: for SDADC2 or SDADC3, an injected conversion is automatically launched when an action in SDADC1 causes its own injected conversion sequence to start. Each injected conversion in SDADC2 or SDADC3 is always executed according its local configuration settings (JDS, JCONT, JCHG, etc.). Each time an injected conversion is launched, all of the selected channels in the injected group are converted sequentially, starting with the lowest channel (channel 0, if selected). Only one injected conversion can be pending or ongoing at a given time. Thus, any request to launch an injected conversion is ignored if another request for an injected conversion has already been issued but not yet completed. Regular conversions can be launched using the following methods: • Software: by writing ‘1’ to RSWSTART in the SDADC_CR2 register. • Synchronous with SDADC1: for SDADC2 or SDADC3, a regular conversion is automatically launched when an action in SDADC1 causes its own regular conversion sequence to start. Each regular conversion in SDADC2 or SDADC3 is always executed according its local configuration settings (RCONT, RCH, etc.). Only one regular conversion can be pending or ongoing at a given time. Thus, any request to launch a regular conversion is ignored if another request for an regular conversion has already been issued but not yet completed. 13.5.9 Continuous and fast continuous modes Setting the JCONT bit in the SDADC_CR2 register causes injected conversions launched by software to execute in continuous mode. If software writes ‘1’ to the JCONT bit at the DocID022448 Rev 2 235/897 262 Sigma-delta analog-to-digital converter (SDADC) RM0313 same time as it writes ‘1’ to the JSWSTART bit, the same scan sequence is performed repeatedly, always starting over at the highest channel after the lowest channel is finished. Similarly, setting the RCONT bit causes regular conversions to execute in continuous mode. RCONT=1 means that the channel selected by the RCH[3:0] bits is converted repeatedly after ‘1’ is written to the RSWSTART bit. The sequence of injected conversions executing in continuous mode can be stopped by writing ‘0’ to the JCONT bit. After clearing the JCONT bit, only the on-going conversion will be completed; the scan sequence is interrupted, and thus the final conversion will not be the last (lowest) selected channel unless it was the one being converted when the JCONT bit was cleared. Similarly, writing ‘0’ to the RCONT bit stops continuous regular conversions, allowing only the currently executing conversion to complete. If just a single channel is selected in continuous mode (either by executing a regular conversion or by executing a injected conversion with only one channel selected), the sampling rate can be increased three fold by setting the FAST bit in the SDADC_CR2 register. The conversion of each channel normally requires 360 SDADC clock cycles (60 µs at 6 MHz). In fast continuous mode (FAST=1), the first conversion takes still 360 SDADC clocks, but then each subsequent conversion finishes in 120 SDADC clocks. 13.5.10 Request precedence In summary, the calibration sequence has the highest precedence, followed by injected conversions, while regular conversions have the lowest priority. However, an individual conversion which is already in progress is never interrupted by the request for another action. Also, a request is ignored if a like action is already pending or in progress. Finally, no action can start before stabilization has finished. The following text gives examples and more details. Injected conversions can not be launched if another injected conversion is pending or already in progress: any request to launch a injected conversion (either by JSWSTART or by a trigger) is ignored when the bit JCIP (in the SDADC_ISR register) is ‘1’. Similarly, regular conversions can not be launched if another regular conversion is pending or already in progress: any request to launch a regular conversion (using RSWSTART) is ignored when the RCIP bit in the SDADC_ISR register is ‘1’. However, if a injected conversion is requested while a regular conversion is already in progress (or vice-versa), the injected conversion is launched as soon as the regular conversion is finished (or vice-versa, assuming that the injected scans sequence is finished and JCONT=0). Injected conversions have precedence over regular conversions in that a injected conversion can temporarily interrupt a sequence of continuous regular conversions (after the current conversion finishes). When the sequence of injected conversions finishes (at the end of the scan sequence or by writing ‘0’ to the JCONT bit in the case of continuous injected conversion mode), the continuous regular conversions start again if the RCONT bit is still set. Precedence matters also when actions are initiated by the same write to SDADC, or if multiple actions are pending at the end of an other action. For example, suppose that while stabilization is in process (STABIP=1), a single write operation to SDADC_CR2 writes ‘1’ to both the RSWSTART and STARTCALIB bits, requesting a regular conversion as well as a calibration sequence. Then a trigger event occurs which requests an injected conversion, 236/897 DocID022448 Rev 2 RM0313 Sigma-delta analog-to-digital converter (SDADC) still during stabilization. When stabilization finishes, precedence dictates that the calibration sequence will execute first, followed by the injected scan sequence, and then finally the regular conversion is performed. 13.5.11 Launching conversions with deterministic timing In applications where certain conversions must be launched at precise intervals, it is a problem if these conversions get delayed by another conversion which is already in progress. This issue can be resolved by setting the JDS (delay start of injected conversions) bit in the SDADC_CR2 register. When JDS=1, the start of each injected conversion is delayed by 500 cycles, during which time no new regular conversions may be launched. Since no conversion can take longer than 360 cycles once it is started, there is guaranteed to be no regular conversions which are in progress at the end of the delay. Note that if PDI=1 (power down mode when idle) and SLOWCK=0 (when the SDADC clock frequency can be as high as 6 MHz), the delay is increased from 500 cycles to 600 cycles since the SDADC needs that many cycles to stabilize as it wakes from power down mode. In this manner, applications can launch regular conversions at any time without affecting the timing of the injected conversions. If continuous regular conversions are executing, they will restart automatically after the injected conversions are complete. 13.5.12 Reference voltage The reference voltage, common to all three sigma-delta ADCs (SDADC1, SDADC2, and SDADC3), is always seen on the VREF pin • When REFV (SDADC_CR1) is “00” (its default value), the VREF pin must be driven externally to a voltage between 1.1V and VDDA. • When REFV=01, the VREF pin is forced internally to the 1.2V bandgap voltage and must be connected externally to a capacitance coupled to VREFM if present, or VSSA otherwise. • When REFV=10, the VREF pin is forced internally to the 1.8V bandgap voltage and must be connected externally to a capacitance coupled to VREFM if present, or VSSA otherwise. • When REFV=11, the VREF pin is forced internally to VDDSDx. It must be externally connected to a capacitance coupled to VREFSD-. – If SDADC1 or SDADC2 are enabled through ENSD1 or ENSD2 bits in PWR_CR register then VDDSD1/2 must be at the same voltage level as VDDSD3. – If SDADC1 and SDADC2 are disabled through ENSD1 and ENSD2 bits in PWR_CR register then VDDSD12 can be lower than VDDSD3. The REFV[1:0] control bits are available only in the register set of SDADC1. For applications which do not use the SDADC, the VREFSD+ pin must not be left floating. The VREFSD+ pin must be tied to VDD, or software must set REFV to “11”. The VREFSDpin must always be grounded. The selected reference voltage is always present on the VREFSD+ pin. This pin must be decoupled by a capacitor (1 µF recommended). If VDDSDx is selected through the reference voltage selection bits (REFV=”11” in SDADC_CR1 register), the application must first configure REFV and then wait for at least 2 ms before enabling the SDADC (ADON=1 DocID022448 Rev 2 237/897 262 Sigma-delta analog-to-digital converter (SDADC) RM0313 in SDADC_CR2 register). The 1 µF decoupling capacitor must be fully charged before enabling the SDADC. The voltage on VREFSD+ pin must meet the following conditions: 13.5.13 • It must always be less than VDDSD3 (in particular when no SDADC is used). • it must be always less than VDDSD12 if SDADC1 or SDADC2 is enabled through ENSD1 or ENSD2 bits in PWR_CR register. Analog input signal ranges The input analog voltage on input channel pins (SDADCx_AIN[8:0]P, SDADCx_AIN[8:0]M) must be in the SDADC power supply range (VSSSD, VDDSDx) for all selected measurement modes and gains. The input analog voltage range corresponding to full-scale SDADC output data range depends on the measurement mode (Section 13.5.5: Differential and single-ended modes), on the selected channel gain, and on the selected reference voltage (configured through REFV[1:0] bits): • In differential mode, the full-scale differential voltage, VIN, ranges between SDADCx_AIN[8:0]P and SDADCx_AIN[8:0]M: – VREFSD VREFSD V IN = ----------------------------- to -------------------------2 × gain 2 × gain • In single ended offset mode, the full-scale differential voltage, VIN, ranges between SDADCx_AIN[8:0]P and VSSA: VREFSD V IN = V SSA to -------------------------2 × gain • In single ended zero reference mode, the full-scale differential voltage, VIN, ranges between SDADCx_AIN[8:0]P and VSSA: VREFSD V IN = V SSA to -------------------------gain where VREFSD = VREFSD+ - VREFSD-. 13.5.14 Input impedance of SDADC analog input and VREFSD reference voltage Input impedance of SDADC depends from the selected SDADC clock, selected gain and if conversion is in progress. The input equivalent circuit is on the following figure. 238/897 DocID022448 Rev 2 RM0313 Sigma-delta analog-to-digital converter (SDADC) Figure 40. Equivalent input circuit for input channel FKFON FKFON 6'$'&[B$,1[3 & S)S)JDLQ FKFON] FKFON] 6'$'&[B$,1[1 FKFON & S)S)JDLQ 069 Note: Gain can be from 0.5x to 8x (16x and 32x are digital gains) Both chclk and chclkz are 0 when the channel is not active (not sampled) and both switch with opposite phases when the channel is active. The average impedance during the channel conversion is: 1 R in = -------------------------------2 ⋅ F clk ⋅ C Input equivalent circuit for external reference voltage (VREFSD) input is shown in the next Figure. Figure 41. Equivalent input circuit for VREFSD input #+?3$!$ 6REFBUFFER 62%&3$ CLK #P& CLKZ CLKZ 62%&3$ CLK #P& -36 DocID022448 Rev 2 239/897 262 Sigma-delta analog-to-digital converter (SDADC) The average impedance of external VREFSD+ input during SDADC operation is: 1 R in = --------------------F clk ⋅ C 240/897 DocID022448 Rev 2 RM0313 RM0313 13.6 Sigma-delta analog-to-digital converter (SDADC) SDADC registers Refer to Section 1.1 on page 36 for a list of abbreviations used in register descriptions. 13.6.1 Register write protection INITRDY=0 ADON=1 and JCIP=1 RCIP=1 CALIBIP=1 ADON=1 RSYNC ro JSYNC ro PDI/SBI ro SLOWCK ro REFV ro(1) FAST ro RSWSTART ignored(2) JSWSTART (2) ignored JEXTEN ro JEXTSEL ro JDS ro STARTCALIB ignored(2) CALIBCNT ro SDADC_JCHGR rwnz rwnz SDADC_CONFxR ro SDADC_CONFCHRx ro ignored ignored ignored rwnz rwnz rwnz 1. REFV can be modified only when all of the SDADC modules are disabled (ADON=0 for all SDADCs). 2. The “START” bits are ignored when INIT=1 (as soon as initialization mode is requested). All bits can be modified when ADON=0. Table legend ro = read only rwnz = read and write-non-zero (writes of all-zero values are ignored) blank = read and write (no protection) 13.6.2 SDADC control register 1 (SDADC_CR1) Address offset: 0x00 Reset value: 0x0000 0000 DocID022448 Rev 2 241/897 262 Sigma-delta analog-to-digital converter (SDADC) RM0313 31 30 29 28 27 26 25 24 23 22 21 20 19 18 INIT Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 RSYNC JSYN C Res. PDI SBI SLOW CK Res. Res. Res. ROVRI E rw rw rw rw rw rw REFV[1:0] rw rw rw 17 16 RDMAE JDMAE N N rw rw 1 0 REOCI EOCAL JOVRIE JEOCIE E IE rw rw rw rw Bit 31 INIT: Initialization mode request 0: Initialization mode is disabled and many control and configuration registers are read only 1: Initialization mode has been requested and firmware must wait for INITRDY to become ‘1’ to write to the control and configuration registers When INIT=1, all requests to launch conversions (software, trigger, synchronized) or calibration are ignored. Bits 30:17 Reserved, must be kept at reset value. Bit 17 RDMAEN: DMA channel enabled to read data for the regular channel 0: The DMA channel is not enabled to read regular data 1: The DMA channel is enabled to read regular data RDMAEN must not be ‘1’ if JDMAEN=1. Bit 16 JDMAEN: DMA channel enabled to read data for the injected channel group 0: The DMA channel is not enabled to read injected data 1: The DMA channel is enabled to read injected data JDMAEN must not be ‘1’ if RDMAEN=1. Bit 15 RSYNC: Launch regular conversion synchronously with SDADC1 0: Do not launch a regular conversion synchronously with SDADC1 1: Launch a regular conversion in this SDADC at the same moment that a regular conversion is launched in SDADC1 This bit can be modified only when INITRDY=1 (SDADC_ISR) or ADON=0 (SDADC_CR2). Bit 14 JSYNC: Launch a injected conversion synchronously with SDADC1 0: Do not launch injected conversion synchronously with SDADC1 1: Launch an injected conversion in this SDADC at the same moment that an injected conversion is launched in SDADC1 This bit can be modified only when INITRDY=1 (SDADC_ISR) or ADON=0 (SDADC_CR2). Bit 13 Reserved, must be kept at reset value. Bit 12 PDI: Enter power down mode when idle 0: Do not enter power down mode when the SDADC is idle 1: Enter Power down when idle When the SDADC is in power down mode due to PDI=1 and a conversion is requested, the SDADC takes 100µs to stabilize before launching the conversion. This bit can be modified only when ADON=0 (SDADC_CR2). 242/897 DocID022448 Rev 2 RM0313 Sigma-delta analog-to-digital converter (SDADC) Bit 11 SBI: Enter Standby mode when idle 0: Do not put the SDADC in Standby mode when it is idle 1: Put the SDADC in Standby mode when it is idle When the SDADC is in Standby mode and a conversion is requested, the SDADC takes 50µs to stabilize before launching the conversion. Software must not write ‘1’ to SBI at the same time that it writes ‘1’ to PDI. This bit can be modified only when ADON=0 (SDADC_CR2). Bit 10 SLOWCK: Slow clock mode enable 0: Disable Slow mode 1: Enable Slow mode (where the SDADC clock frequency should be only 1.5MHz) allowing a lower level of current consumption as well as operation at a lower minimum voltage This bit may be written only when ADON=0 (SDADC_CR2). Bits 9:8 REFV[1:0]: Reference voltage selection 00: External reference where the VREF pin must be forced externally 01: Internal reference where the reference voltage is forced to the 1.2V bandgap voltage internally and the VREF pin must be connected externally to a capacitance coupled to VSSA 10: Internal reference where the reference voltage is forced to the 1.8V bandgap voltage internally and the VREF pin must be connected externally to a capacitance coupled to VSSA 11: Internal reference where the reference voltage is forced internally to VDDSDx and the VREFSD+ pin must be externally connected to a capacitance coupled to VREFSD-. See Section : Constrains on VDDSDx versus VREFSD voltage). These bits are available only in the register set of SDADC1 and may be written only when ADON=0 (SDADC_CR2) for all SDADC modules. Bit 7:5 Reserved, must be kept at reset value. Bit 4 ROVRIE: Regular data overrun interrupt enable 0: Regular data overrun interrupt disabled 1: Regular data overrun interrupt enabled Please see explanation of ROVRF in SDADC_ISR. Bit 3 REOCIE: Regular end of conversion interrupt enable 0: Regular end of conversion interrupt disabled 1: Regular end of conversion interrupt enabled Refer to the description of the REOCF bit in the SDADC_ISR register. Bit 2 JOVRIE: Injected data overrun interrupt enable 0: Injected data overrun interrupt disabled 1: Injected data overrun interrupt enabled Refer to the description of the JOVRF bit in the SDADC_ISR register. Bit 1 JEOCIE: Injected end of conversion interrupt enable 0: Injected end of conversion interrupt disabled 1: Injected end of conversion interrupt enabled Refer to the description of the JEOCF bit in the SDADC_ISR register. Bit 0 EOCALIE: End of calibration interrupt enable 0: End of calibration interrupt disabled 1: End of calibration interrupt enabled Refer to the description of the EOCALF bit in the SDADC_ISR register. DocID022448 Rev 2 243/897 262 Sigma-delta analog-to-digital converter (SDADC) 13.6.3 RM0313 SDADC control register 2 (SDADC_CR2) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. FAST 15 14 13 12 11 10 9 Res. Res. JSW STAR T JEXTEN[1:0] rc_w1 rw rw rw 22 RSW RCONT START 21 20 Res. Res. 19 18 17 16 RCH[3:0] rw rc_w1 rw rw rw rw rw 8 7 6 5 4 3 2 1 0 Res. JDS JCONT START CALIB Res. rw rw rc_w1 JEXTSEL[2:0] rw 23 rw CALIBCNT[1:0] rw ADON rw rw Bits 31:25 Reserved, must be kept at reset value. Bit 24 FAST: Fast conversion mode selection 0: Fast conversion mode disabled 1: Fast conversion mode enabled When converting a single channel in continuous mode, having enabled fast mode causes each conversion (except for the first) to execute 3 times faster (taking 120 SDADC cycles rather than 360). This bit has no effect for conversions which are not continuous. This bit can be modified only when INITRDY=1 (SDADC_ISR) or ADON=0 (SDADC_CR2). Bit 23 RSWSTART: Software start of a conversion on the regular channel 0: Writing ‘0’ has no effect 1: Writing ‘1’ makes a request to start a conversion on the regular channel and causes RCIP to become ‘1’. If RCIP=1 already or if INIT=1, writing to RSWSTART has no effect This bit is always read as ‘0’. Bit 22 RCONT: Continuous mode selection for regular conversions 0: The regular channel is converted just once for each conversion request 1: The regular channel is converted repeatedly after each conversion request Writing ‘0’ to this bit while a continuous regular conversion is already in progress stops continuous mode after the conversion already in progress is finished. Setting this bit to ‘1’ has no effect on any regular conversion which is pending or already in progress. Bits 21:20 Reserved, must be kept at reset value. Bits 19:16 RCH[3:0]: Regular channel selection 0: Channel 0 is selected as regular channel 1: Channel 1 is selected as regular channel ... 8: Channel 8 is selected as regular channel 9-15: Reserved, these values are forbidden Writing these bits when RCIP=1 takes effect when the next regular conversion begins. This is especially useful in continuous mode (when RCONT=1). It affects also regular conversions which are pending (due to stabilization or due to an ongoing injected conversion). 244/897 DocID022448 Rev 2 RM0313 Sigma-delta analog-to-digital converter (SDADC) Bit 15 JSWSTART: Start a conversion of the injected group of channels 0: Writing ‘0’ has no effect. 1: Writing ‘1’ makes a request to convert the channels in the injected conversion group, causing JCIP to become ‘1’ at the same time. If JCIP=1 already or if INIT=1, then writing to JSWSTART has no effect. This bit is always read as ‘0’. Bits 14:13 JEXTEN[1:0]: Trigger enable and trigger edge selection for injected conversions 00: Trigger detection is disabled 01: Each rising edge on the selected trigger makes a request to launch a injected conversion 10: Each falling edge on the selected trigger makes a request to launch a injected conversion 11: Both rising edges and falling edges on the selected trigger make requests to launch injected conversions This bit can be modified only when INITRDY=1 (SDADC_ISR) or ADON=0 (SDADC_CR2). Bit 12:11 Reserved, must be kept at reset value. Bits 10:8 JEXTSEL[2:0]: Trigger signal selection for launching injected conversions 0x0-0x7: Trigger inputs selected by following table. This bit can be modified only when INITRDY=1 (SDADC_ISR) or ADON=0 (SDADC_CR2). 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 SDADC1 TIM13_CH1 TIM14_CH1 TIM15_CH2 TIM3_CH1 TIM4_CH1 TIM19_CH2 EXTI15 EXTI11 SDADC2 TIM17_CH1 TIM12_CH1 TIM2_CH3 TIM3_CH2 TIM4_CH2 TIM19_CH3 EXTI15 EXTI11 SDADC3 TIM16_CH1 TIM12_CH2 TIM2_CH4 TIM3_CH3 TIM4_CH3 TIM19_CH4 EXTI15 EXTI11 Bit 7 Reserved, must be kept at reset value. Bit 6 JDS: Delay start of injected conversions. 0: Injected conversions begin as soon as possible after the request 1: After a request for a injected conversion is made, the SDADC waits a fixed interval before launching the conversion, allowing time for any regular conversions which is already in progress to finish, and thus assuring that the timing of the launch is deterministic. The delay is 500 ADC clocks, unless PDI=1 and SLOWCK=0, in which case the delay is 600 ADC clocks. This bit can be modified only when INITRDY=1 (SDADC_ISR) or ADON=0 (SDADC_CR2). Bit 5 JCONT: Continuous mode selection for injected conversions 0: The series of conversions which converts each selected channel (the scan sequence) is executed just once for each conversion request 1: The series of conversions for the injected group channels is repeated continuously, starting over with the highest selected channel each time the lowest selected channel finishes its conversion Writing ‘0’ to this bit while a continuous injected conversion is already in progress stops continuous mode after the conversion already in progress is finished. If an injected conversions is pending or is already in progress when this bit changes to ‘1’, it does not become continuous. DocID022448 Rev 2 245/897 262 Sigma-delta analog-to-digital converter (SDADC) RM0313 Bit 4 STARTCALIB: Start calibration 0: Writing ‘0’ has no effect 1: Writing ‘1’ makes a request to start the calibration sequence, causing CALIBIP to become ‘1’ at the same time After the request is made, the calibration starts as soon as any ongoing activity (stabilization or a conversion) is finished, or immediately if the SDADC is stabilized and idle. Writing this bit when CALIBIP=1 or when INIT=1 has no effect. This bit is always read as ‘0’. Bit 3 Reserved, must be kept at reset value. Bits 2:1 CALIBCNT[1:0]: Number of calibration sequences to be performed (number of valid configurations) 0: One calibration sequence will be performed to calculate OFFSET0[11:0] 1: Two calibration sequences will be performed to calculate OFFSET0[11:0] and OFFSET1[11:0] 2: Three calibration sequences will be performed to calculate OFFSET0[11:0], OFFSET1[11:0], and OFFSET2[11:0] 3: Reserved, must not use this value This bit can be modified only when INITRDY=1 (SDADC_ISR) or ADON=0 (SDADC_CR2). Bit 0 ADON: SDADC enable 0: All SDADC functions are disabled. Power down mode is entered, and the flags and the data are cleared 1: SDADC is enabled. When PDI=0, the SDADC exits power down mode and the 100us of stabilization are observed starting at the moment that ADON is set to ‘1’. 246/897 DocID022448 Rev 2 RM0313 Sigma-delta analog-to-digital converter (SDADC) 13.6.4 SDADC interrupt and status register (SDADC_ISR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INITR DY Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STABI P RCIP JCIP CALIBI P Res. Res. Res. Res. Res. Res. Res. r r r r r ROVRF REOCF JOVRF JEOCF r r r EOCAL F r r Bit 31 INITRDY: Initialization mode is ready 0: The SDADC is not in initialization mode. 1: The SDADC is in initialization mode Many control and configuration registers (see their descriptions) can be modified only when INITRDY=1. Hardware clears this bit as soon as INIT (SDADC_CR1) is cleared. Hardware sets this bit after the INIT bit is set. If a conversion or calibration is pending or ongoing when INIT is cleared, INITRDY stays at ‘0’ until all operations have complete. Otherwise, INITRDY becomes ‘1’ about two SDADC clock cycles after INIT is set. Bits 30:16 Reserved, must be kept at reset value. Bit 15 STABIP: Stabilization in progress status 0: The SDADC is either stabilized or it is in power down mode or Standby mode 1: The SDADC is currently in the process of stabilization, after waking up from either power down mode or Standby mode A request to start the calibration sequence or to start a conversion can be issued while STABIP=1, with the actions automatically delayed until after stabilization is complete. Bit 14 RCIP: Regular conversion in progress status 0: No request to convert the regular channel has been issued 1: The conversion of the regular channel is in progress or a request for a regular conversion is pending A request to start a regular conversion is ignored when RCIP=1. Bit 13 JCIP: Injected conversion in progress status 0: No request to convert the injected channel group (neither by software nor by trigger) has been issued 1: The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to ‘1’ being written to JSWSTART or to a trigger detection A request to start a injected conversion is ignored when JCIP=1. Bit 12 CALIBIP: Calibration in progress status 0: No calibration request has been issued 1: Calibration is in progress or a request to start calibration is pending A request to start calibration is ignored when CALIBIP=1. Bits 11:5 Reserved, must be kept at reset value. DocID022448 Rev 2 247/897 262 Sigma-delta analog-to-digital converter (SDADC) RM0313 Bit 4 ROVRF: Regular conversion overrun flag 0: No regular conversion overrun has occurred 1: A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already ‘1’. RDATAR is not affected by overruns This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the SDADC_CLRISR register. Bit 3 REOCF: End of regular conversion flag 0: No regular conversion has completed 1: A regular conversion has completed and its data may be read This bit is set by hardware. It is cleared when software reads SDADC_RDATAR. Bit 2 JOVRF: Injected conversion overrun flag 0: No injected conversion overrun has occurred 1: A injected conversion overrun has occurred, which means that a injected conversion finished while JEOCF was already ‘1’. JDATAR is not affected by overruns This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the SDADC_CLRISR register. Bit 1 JEOCF: End of injected conversion flag 0: No injected conversion has completed 1: A injected conversion has completed and its data may be read This bit is set by hardware. It is cleared when software reads SDADC_JDATAR. Bit 0 EOCALF: End of calibration flag 0: No calibration sequence has completed 1: Calibration has completed and the offsets have been updated This bit is set by hardware. It can be cleared by software using the CLREOCALF bit in SDADC_CLRISR. Note: For each of the flag bits (ROVRF, REOCF, JOVRF, JEOCF, and EOCALF), an interrupt can be enabled by setting the corresponding bit in the SDADC_CR1 register. If an interrupt is requested, the flag must be cleared before exiting the interrupt service routine. All the bits of SDADC_ISR except INITRDY are cleared automatically when ADON=0. 248/897 DocID022448 Rev 2 RM0313 13.6.5 Sigma-delta analog-to-digital converter (SDADC) SDADC interrupt and status clear register (SDADC_CLRISR) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CLR ROVR F Res. CLR JOVRF Res. CLR EOCA LF rc_w1 rc_w1 rc_w1 Bits 31:5 Reserved, must be kept at reset value. Bit 4 CLRROVRF: Clear the regular conversion overrun flag 0: Writing ‘0’ has no effect 1: Writing ‘1’ clears the ROVRF bit in the SDADC_ISR register Bit 3 Reserved, must be kept at reset value. Bit 2 CLRJOVRF: Clear the injected conversion overrun flag 0: Writing ‘0’ has no effect 1: Writing ‘1’ clears the JOVRF bit in the SDADC_ISR register Bit 1 Reserved, must be kept at reset value. Bit 0 Note: CLREOCALF: Clear the end of calibration flag 0: Writing ‘0’ has no effect 1: Writing ‘1’ clears the EOCALF bit in the SDADC_ISR register The bits of SDADC_CLRISR are always read as ‘0’. DocID022448 Rev 2 249/897 262 Sigma-delta analog-to-digital converter (SDADC) 13.6.6 RM0313 SDADC injected channel group selection register (SDADC_JCHGR) Address offset: 0x14 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. rw rw rw rw JCHG[8:0] rw rw rw rw rw Bits 31:9 Reserved, must be kept at reset value. Bits 8:0 JCHG[8:0]: Injected channel group selection 0: If JCHG[i]=0, then channel i is not part of the injected group (where, 0 <= i <= 8) 1: If JCHG[i]=1, then channel i is part of the injected group (where, 0 <= i <= 8) A injected conversion operates always in scan mode, which means that each of selected channels are converted, one after another. The highest channel (channel 8, if selected) is converted first and the sequence ends at the lowest selected channel. If JCONT=1, this series of conversions is performed continuously. If JCONT=1, FAST=1, and there is only one channel selected in the injected group, then each of the conversions (besides the first) finishes in only 120 SDADC cycles (rather than 360). This field can be modified while an injected conversion is in progress and it will take effect for the next group conversion. Writing JCHG also affects injected conversions which are pending (due to stabilization or due to the delay caused by JDS=1). At least one channel must always be selected for the injected group. Writes causing all JCHG bits to be zero are ignored. 250/897 DocID022448 Rev 2 RM0313 13.6.7 Sigma-delta analog-to-digital converter (SDADC) SDADC configuration 0 register (SDADC_CONF0R) This register specifies the parameters for configuration 0. If CONFCHi[1:0]=’00’, then each conversion of channel “i” will use the configuration settings specified in this register. Address offset: 0x20 Reset value: 0x0000 0000 31 30 COMMON0[1:0 ] 29 28 Res. Res. rw rw 15 14 13 12 Res. Res. Res. Res. 27 26 SE0[1:0] rw rw 11 10 25 24 23 Res. Res. Res. 9 8 7 22 21 20 GAIN0[2:0] 19 18 17 16 Res. Res. Res. Res. rw rw rw 6 5 4 3 2 1 0 rw rw rw rw rw OFFSET0[11:0] rw rw rw rw rw rw rw Bits 31:30 COMMON0[1:0]: Common mode for configuration 0 00: Ground 01: VCM (VDD/2) 10: VDD 11: Reserved, must not use this value This value is used only during calibration, i.e., when determining the offset. It has no direct effect on the conversions. Bits 29:28 Reserved, must be kept at reset value. Bits 27:26 SE0[1:0]: Single-ended mode for configuration 0 00: Conversions are executed in differential mode 01: Conversions are executed in single-ended offset mode 10: Reserved, do not use this setting 11: Conversions are executed in single-ended zero-volt reference mode When this field is non-zero, the corresponding negative differential analog input, SDADCx_AINxM, is connected internally to VSSA so that its pin can be used for other functions. Bits 25:23 Reserved, must be kept at reset value. Bits 22:20 GAIN0[2:0]: Gain setting for configuration 0 000: 1x gain 001: 2x gain 010: 4x gain 011: 8x gain 100: 16x gain 101: 32x gain 111: 0.5x gain Bits 19:12 Reserved, must be kept at reset value. Bits 11:0 OFFSET0[11:0]: Twelve-bit calibration offset for configuration 0 For channels which select configuration 0, OFFSET0 is applied to the results of each conversion. This value is automatically set during calibration. Note: This register can be modified only when INITRDY=1 (SDADC_ISR) or ADON=0 (SDADC_CR2). DocID022448 Rev 2 251/897 262 Sigma-delta analog-to-digital converter (SDADC) 13.6.8 RM0313 SDADC configuration 1 register (SDADC_CONF1R) This register specifies the parameters for configuration 1. If CONFCHi[1:0]=’01’, then each conversion of channel “i” will use the configuration settings specified in this register. Address offset: 0x24 Reset value: 0x0000 0000 31 30 COMMON1 [1:0] 29 28 Res. Res. rw rw 15 14 13 12 Res. Res. Res. Res. 27 26 SE1[1:0] rw rw 11 10 25 24 23 Res. Res. Res. 9 8 7 22 21 20 GAIN1[2:0] 19 18 17 16 Res. Res. Res. Res. rw rw rw 6 5 4 3 2 1 0 rw rw rw rw rw OFFSET1[11:0] rw rw rw rw rw rw rw Bits 31:30 COMMON1[1:0]: Common mode for configuration 1 00: Ground 01: VCM (VDD/2) 10: VDD 11: Reserved, must not use this value This value is used only during calibration, i.e., when determining the offset. It has no direct effect on the conversions. Bits 29:28 Reserved, must be kept at reset value. Bits 27:26 SE1[1:0]: Single-ended mode for configuration 1 00: Conversions are executed in differential mode 01: Conversions are executed in single-ended offset mode 10: Reserved, do not use this setting 11: Conversions are executed in single-ended zero-volt reference mode When this field is non-zero, the corresponding negative differential analog input, INNx, is connected internally to VSSA so that its pin can be used for other functions. Bits 25:23 Reserved, must be kept at reset value. Bits 22:20 GAIN1[2:0]: Gain setting for configuration 1 000: 1x gain 001: 2x gain 010: 4x gain 011: 8x gain 100: 16x gain 101: 32x gain 111: 0.5x gain Bits 19:12 Reserved, must be kept at reset value. Bits 11:0 OFFSET1[11:0]: Twelve-bit calibration offset for configuration 1 For channels which select configuration 1, OFFSET1 is applied to the results of each conversion. This value is automatically set during calibration if CALIBCNT (SDADC_CR2) has a value greater than or equal to 1. Note: This register can be modified only when INITRDY=1 (SDADC_ISR) or ADON=0 (SDADC_CR2). 252/897 DocID022448 Rev 2 RM0313 13.6.9 Sigma-delta analog-to-digital converter (SDADC) SDADC configuration 2 register (SDADC_CONF2R) This register specifies the parameters for configuration 2. If CONFCHi[1:0]=’10’, then each conversion of channel “i” will use the configuration settings specified in this register. Address offset: 0x28 Reset value: 0x0000 0000 31 30 COMMON2 [1:0] 29 28 Res. Res. rw rw 15 14 13 12 Res. Res. Res. Res. 27 26 SE2[1:0] rw rw 11 10 25 24 23 Res. Res. Res. 9 8 7 22 21 20 GAIN2[2:0] 19 18 17 16 Res. Res. Res. Res. rw rw rw 6 5 4 3 2 1 0 rw rw rw rw rw OFFSET2[11:0] rw rw rw rw rw rw rw Bits 31:30 COMMON2[1:0]: Common mode for configuration 2 00: VSSSD 01: VDDSDx/2 10: VDDSDx 11: Reserved, this value is forbidden This value is used only during calibration, i.e., when determining the offset. It has no direct effect on the conversions. Bits 29:28 Reserved, must be kept at reset value. Bits 27:26 SE2[1:0]: Single-ended mode for configuration 2 00: Conversions are executed in differential mode 01: Conversions are executed in single-ended offset mode 10: Reserved, do not use this setting 11: Conversions are executed in single-ended zero-volt reference mode When this field is non-zero, the corresponding negative differential analog input, INNx, is connected internally to VSSA so that its pin can be used for other functions. Bits 25:23 Reserved, must be kept at reset value. Bits 22:20 GAIN2[2:0]: Gain setting for configuration 2 000: 1x gain 001: 2x gain 010: 4x gain 011: 8x gain 100: 16x gain 101: 32x gain 111: 0.5x gain Bits 19:12 Reserved, must be kept at reset value. Bits 11:0 OFFSET2[11:0]: Twelve-bit calibration offset for configuration 2 For channels which select configuration 2, OFFSET2 is applied to the results of each conversion. This value is automatically set during calibration if CALIBCNT (SDADC_CR2) has a value greater than or equal to 2. Note: This register can be modified only when INITRDY=1 (SDADC_ISR) or ADON=0 (SDADC_CR2). DocID022448 Rev 2 253/897 262 Sigma-delta analog-to-digital converter (SDADC) 13.6.10 RM0313 SDADC channel configuration register 1 (SDADC_CONFCHR1) This register specifies which configurations are to be used by channels 0-7. Address offset: 0x40 Reset value: 0x0000 0000 31 30 Res. Res. 15 14 Res. Res. 29 28 CONFCH7[1:0] rw rw 13 12 CONFCH3[1:0] rw 27 26 Res. Res. 11 10 Res. Res. 25 24 CONFCH6[1:0] rw rw 9 8 CONFCH2[1:0] rw rw 23 22 Res. Res. 7 6 Res. Res. rw 21 20 CONFCH5[1:0] rw rw 5 4 CONFCH1[1:0] rw 19 18 Res. Res. 3 2 Res. Res. rw 17 16 CONFCH4[1:0] rw rw 1 0 CONFCH0[1:0] rw rw CONFCHi[1:0]: Channel i configuration 00: Channel i uses the configuration specified in SDADC_CONF0R 01: Channel i uses the configuration specified in SDADC_CONF1R 10: Channel i uses the configuration specified in SDADC_CONF2R 11: Reserved, must not use this value Note: This register can be modified only when INITRDY=1 (SDADC_ISR) or ADON=0 (SDADC_CR2). 13.6.11 SDADC channel configuration register 2 (SDADC_CONFCHR2) This register specifies which configuration is to be used by channel 8. Address offset: 0x44 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. CONFCH8[1:0] rw Bits 31:2 Reserved, must be kept at reset value. Bits 1:0 CONFCH8[1:0]: Channel 8 configuration 00: Channel 8 uses the configuration specified in SDADC_CONF0R 01: Channel 8 uses the configuration specified in SDADC_CONF1R 10: Channel 8 uses the configuration specified in SDADC_CONF2R 11: Reserved, must not use this value Note: This register can be modified only when INITRDY=1 (SDADC_ISR) or ADON=0 (SDADC_CR2). 254/897 DocID022448 Rev 2 rw RM0313 Sigma-delta analog-to-digital converter (SDADC) 13.6.12 SDADC data register for injected group (SDADC_JDATAR) This register contains the data resulting from the recently completed conversion of a channel in the injected group. Address offset: 0x60 Reset value: 0x0000 0000 31 30 29 28 Res. Res. Res. Res. 15 14 13 12 27 26 25 24 JDATACH[3:0] r r r r 11 10 9 8 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 1 0 r r r r r r r JDATA[15:0] r r r r r r r r r Bits 31:28 Reserved, must be kept at reset value. Bits 27:24 JDATACH[3:0]: Injected channel most recently converted When each conversion of a channel in the injected group finishes, JDATACH[3:0] is updated to indicate which channel was converted. This field is valid when JEOCF=1, and is set to zero when JEOCF is cleared. Thus, when JEOCF=1, JDATA[15:0] holds the data that corresponds to the channel indicated by JDATACH[3:0]. Bits 23:16 Reserved, must be kept at reset value. Bits 15:0 JDATA[15:0]: Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears both this field as well as the corresponding JEOCF. Note: DMA may be used to read the data from this register. Half-word accesses may be used to read only the conversion data. Note: This register is cleared as soon as it is read. Reading this register also clears JEOCF in SDADC_ISR. Thus, firmware must not read this register if DMA is activated to read data from this register. DocID022448 Rev 2 255/897 262 Sigma-delta analog-to-digital converter (SDADC) 13.6.13 RM0313 SDADC data register for the regular channel (SDADC_RDATAR) This register contains the data resulting from the recently completed conversion of the regular channel. Address offset: 0x64 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r RDATA[15:0] r r r r r r r r r Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 RDATA[15:0]: Regular channel conversion data When each regular conversion finishes, its data is stored in this register. The data is valid when REOCF=1. Reading this register clears both this field as well as the corresponding JEOCF. Note: 256/897 This register is cleared as soon as it is read. Reading this register also clears REOCF in SDADC_ISR. DocID022448 Rev 2 RM0313 Sigma-delta analog-to-digital converter (SDADC) 13.6.14 SDADC1 and SDADC2 injected data register (SDADC_JDATA12R) This register contains the data resulting from the recently completed conversions of injected channels of SDADC1 and SDADC2. The data is a mirror image of the data in the corresponding SDADC_JDATAR registers. This register is available only in the set of registers for SDADC1 and must not be accessed unless the JSYNC bit of SDADC2 is set. Address offset: 0x70 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 JDATA2[15:0] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r JDATA1[15:0] r r r r r r r r r Bits 31:16 JDATA2[15:0]: Injected group conversion data for SDADC2 When each conversion of a channel in the injected group of SDADC2 finishes, its resulting data is stored in this field. The data is valid only when JEOCF of SDADC2 is set. Reading this register clears both this field as well as the corresponding JEOCF. Bits 15:0 JDATA1[15:0]: Injected group conversion data for SDADC1 When each conversion of a channel in the injected group of SDADC1 finishes, its resulting data is stored in this field. The data is valid only when JEOCF of SDADC1 is set. Reading this register clears both this field as well as the corresponding JEOCF. Note: DMA may be used to read the data from this register, in which case 32-bit word accesses must be used. Note: This register is cleared as soon as it is read. Reading this register also clears JEOCF in the corresponding two SDADC_ISR registers. Thus, firmware must not read this register nor the SDADC_JDATA registers of SDADC1 and SDADC2 if DMA is activated to read data from this register. DocID022448 Rev 2 257/897 262 Sigma-delta analog-to-digital converter (SDADC) 13.6.15 RM0313 SDADC1 and SDADC2 regular data register (SDADC_RDATA12R) This register contains the data resulting from the recently completed conversions of regular channels of SDADC1 and SDADC2. The data is a mirror image of the data in the corresponding SDADC_RDATAR registers. This register is available only in the set of registers for SDADC1 and must not be accessed unless the RSYNC bit of SDADC2 is set. Address offset: 0x74 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RDATA2[15:0] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r RDATA1[15:0] r r r r r r r r r Bits 31:16 RDATA2[15:0]: Regular conversion data for SDADC2 When each conversion of the regular channel of SDADC2 finishes, its resulting data is stored in this field. The data is valid only when REOCF of SDADC2 is set. Reading this register clears both this field as well as the corresponding REOCF. Bits 15:0 RDATA1[15:0]: Regular conversion data for SDADC1 When each conversion of the regular channel of SDADC1 finishes, its resulting data is stored in this field. The data is valid only when REOCF of SDADC1 is set. Reading this register clears both this field as well as the corresponding REOCF. Note: DMA may be used to read the data from this register, in which case 32-bit word accesses must be used. Note: This register is cleared as soon as it is read. Reading this register also clears REOCF in the corresponding two SDADC_ISR registers. Thus, firmware must not read this register nor the SDADC_RDATA registers of SDADC1 and SDADC2 if DMA is activated to read data from this register. 258/897 DocID022448 Rev 2 RM0313 Sigma-delta analog-to-digital converter (SDADC) 13.6.16 SDADC1 and SDADC3 injected data register (SDADC_JDATA13R) This register contains the data resulting from the recently completed conversions of injected channels of SDADC1 and SDADC3. The data is a mirror image of the data in the corresponding SDADC_JDATAR registers. This register is available only in the set of registers for SDADC1 and must not be accessed unless the JSYNC bit of SDADC3 is set. Address offset: 0x78 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 JDATA3[15:0] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r JDATA1[15:0] r r r r r r r r r Bits 31:16 JDATA3[15:0]: Injected group conversion data for SDADC3 When each conversion of a channel in the injected group of SDADC3 finishes, its resulting data is stored in this field. The data is valid only when JEOCF of SDADC3 is set. Reading this register clears both this field as well as the corresponding JEOCF. Bits 15:0 JDATA1[15:0]: Injected group conversion data for SDADC1 When each conversion of a channel in the injected group of SDADC1 finishes, its resulting data is stored in this field. The data is valid only when JEOCF of SDADC1 is set. Reading this register clears both this field as well as the corresponding JEOCF. Note: DMA may be used to read the data from this register, in which case 32-bit word accesses must be used. Note: This register is cleared as soon as it is read. Reading this register also clears JEOCF in the corresponding two SDADC_ISR registers. Thus, firmware must not read this register nor the SDADC_JDATA registers of SDADC1 and SDADC3 if DMA is activated to read data from this register. DocID022448 Rev 2 259/897 262 Sigma-delta analog-to-digital converter (SDADC) 13.6.17 RM0313 SDADC1 and SDADC3 regular data register (SDADC_RDATA13R) This register contains the data resulting from the recently completed conversions of regular channels of SDADC1 and SDADC3. The data is a mirror image of the data in the corresponding SDADC_RDATAR registers. This register is available only in the set of registers for SDADC1 and must not be accessed unless the RSYNC bit of SDADC3 is set. Address offset: 0x7C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RDATA3[15:0] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r RDATA1[15:0] r r r r r r r r r Bits 31:16 RDATA3[15:0]: Regular conversion data for SDADC3 When each conversion of the regular channel of SDADC3 finishes, its resulting data is stored in this field. The data is valid only when REOCF of SDADC3 is set. Reading this register clears both this field as well as the corresponding REOCF. Bits 15:0 RDATA1[15:0]: Regular conversion data for SDADC1 When each conversion of the regular channel of SDADC1 finishes, its resulting data is stored in this field. The data is valid only when REOCF of SDADC1 is set. Reading this register clears both this field as well as the corresponding REOCF. Note: DMA may be used to read the data from this register, in which case 32-bit word accesses must be used. Note: This register is cleared as soon as it is read. Reading this register also clears REOCF in the corresponding two SDADC_ISR registers. Thus, firmware must not read this register nor the SDADC_RDATA registers of SDADC1 and SDADC3 if DMA is activated to read data from this register. 260/897 DocID022448 Rev 2 0x28 0x2C 0x3C Reset value 0 COM SDADC_CONF MON 2R 2 [1:0] 0 0 SE2 [1:0] 0 0 0 GAIN2 [2:0] 0 0 DocID022448 Rev 2 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0 0 0 0 REOCF JOVRF JEOCF EOCALF 0 0 0 0 0 Res. CLRJOVRF Res. CLREOCALF JOVRIE JEOCIE EOCALIE 0 0 0 0 0 0 0 0 0 ADON CALIB CNT [1:0] REOCIE 0 Res. Res. Res. ROVRIE STARTCALIB 0 ROVRF JCONT 0 Res. Res. REFV[1:0](2) SBI Res. SLOWCK 0 CLRROVRF Res. JDS Res. 0 Res. Res. JEXTSEL [3:0] Res. JSYNC (1) Res. JDMAEN RSYNC (1) 0 Res. Res. Res. JEXTEN JSWSTART RDMAEN Res. Res. Res. Res. 0 Res. Res. 0 Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. 0 Res. 0 Res. JCIP CALIBIP 0 0 Res. RCIP 0 Res. STABIP 0 Res. Res. Res. Res. 0 Res. Res. Res. Res. 0 Res. Res. Res. Res. RCONT Res. Res. RSWSTART Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. FAST Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. INIT Res. Res. 0 Res. Res. Res. Res. Res. Res. 0x1C Res. Res. Res. Res. Res. 0x18 Res. Res. Res. Res. Res. Res. Res. Res. 0 0 Res. 0 0 0 Res. GAIN1 [2:0] 0 Res. 0 0 Res. 0 Res. 0 GAIN0 [2:0] RCH [3:0] Res. Res. Res. Res. Res. Res. 0x10 0 Res. 0 0 Res. 0 SE1 [1:0] 0 Res. COM SDADC_CONF MON 1R 1 [1:0] 0 0 Res. 0 0 Res. Reset value 0 SE0 [1:0] Res. Reset value Res. Reset value Res. COM SDADC_CONF MON 0R 0 [1:0] Res. SDADC_JCHG R Res. SDADC_CLRI SR Res. 0 Res. Reset value Res. SDADC_ISR Res. 0x24 SDADC_CR2 Res. 0x20 0 Res. 0x14 Reset value Res. 0x0C SDADC_CR1 Res. 0x08 INITRDY 0x04 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. 0x00 Res. Offset Res. 13.6.18 Res. RM0313 Sigma-delta analog-to-digital converter (SDADC) SDADC register map The following table summarizes the ADC registers. Table 37. SDADC register map and reset values 0 0 0 0 0 Res. JCHG[8:0] OFFSET0[11:0] OFFSET1[11:0] OFFSET2[11:0] 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Res. 261/897 262 Sigma-delta analog-to-digital converter (SDADC) RM0313 Res. Res. CON F CH8 [1:0] Res. 0 Res. Res. Res. 0 Reset value 0x48 0x5C Res. Res. Res. Res. Res. Res. Res. Res. Res. SDADC_ JDATA12R (2) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x80 0xBC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JDATA1[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 RDATA3[15:0] 0 0 RDATA1[15:0] JDATA3[15:0] SDADC_ RDATA13R (2) Reset value 0 0 0 0 RDATA1[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. 1. Not available in SDADC1. 2. Available only in SDADC1. Refer to Section 2.2.2 on page 41 for the register boundary addresses. 262/897 0 JDATA1[15:0] RDATA2[15:0] SDADC_ JDATA13R (2) Reset value 0x7C 0 JDATA2[15:0] SDADC_ RDATA12R (2) Reset value 0x78 0 Res. Reset value 0x74 0 RDATA[15:0] 0 0x68 0x6C 0 Res. Res. Res. Res. Res. Res. Res. Reset value 0x70 0 JDATA[15:0] 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. SDADC_RDAT AR JDATACH [3:0] Res. Res. SDADC_JDAT AR Reset value 0x64 0 Res. Res. 0x60 CON F CH0 [1:0] Res. Res. Res. CON F CH1 [1:0] 0 Res. Res. Res. 0 Res. Res. Res. CON F CH2 [1:0] 0 Res. Res. Res. 0 Res. Res. Res. CON F CH3 [1:0] 0 Res. Res. Res. 0 Res. Res. Res. CON F CH4 [1:0] 0 Res. Res. Res. 0 Res. Res. Res. CON F CH5 [1:0] 0 Res. Res. Res. 0 Res. Res. Res. CON F CH6 [1:0] 0 Res. 0 Res. SDADC_ CONFCHR2 Res. 0x44 0 Res. Reset value CON F CH7 [1:0] Res. SDADC_ CONFCHR1 Res. 0x40 Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 37. SDADC register map and reset values (continued) DocID022448 Rev 2 0 0 RM0313 Digital-to-analog converter (DAC1 and DAC2) 14 Digital-to-analog converter (DAC1 and DAC2) 14.1 Introduction The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned. An input reference voltage, VDDA (shared with ADC) is available. The output can optionally be buffered for higher current drive. 14.2 DAC1/2 main features The devices integrate three 12-bit DAC channels: • DAC1 integrates two DAC channels: – DAC1 channel 1 which output is DAC1_OUT1 – DAC1 channel 2 which output is DAC1_OUT2 The two channels can be used independently or simultaneously when both channels are grouped together for synchronous update operations (dual mode). • DAC2 integrates only one channel, DAC2 channel 1 which output is DAC2_OUT1 . The DAC main features are the following: • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave generation • Triangular-wave generation • Independent or simultaneous conversions (dual mode only) • DMA capability for each channel • DMA underrun error detection • External triggers for conversion • Programmable internal buffer • Input voltage reference, VDDA Figure 42 and Figure 43 show the block diagram of a DAC1 and DAC2 channels and Table 38 gives the pin description. DocID022448 Rev 2 263/897 288 Digital-to-analog converter (DAC1 and DAC2) RM0313 Figure 42. DAC1 block diagram '$&FRQWUROUHJLVWHU 6:75,*[ 7,0B75*2 7,0B75*2 7,0B75*2 7,0B75*2 7,0B75*2 7,0B75*2 7ULJJHUVHOHFWRU[ 76(/[>@ ELWV '0$(1[ (;7,B '0$UHTXHVW[ '+5[ ELW &RQWUROORJLF[ /)65[ WULDQJOH[ 7(1[ 0$03[>@ELWV :$9([>@ELWV ELW %2)) '25[ ELW 9''$ 966$ 'LJLWDOWRDQDORJ FRQYHUWHU[ '$&B287[ 95 () 069 264/897 DocID022448 Rev 2 RM0313 Digital-to-analog converter (DAC1 and DAC2) Figure 43. DAC2 block diagram '$&FRQWUROUHJLVWHU 3742)'X 4)-?42'/ 4)-?42'/ 4)-?42'/ 4)-?42'/ 4)-?42'/ 4)-?42'/ 7ULJJHUVHOHFWRU[ 76(/[>@ '0$(1[ %84)? '0$UHTXHVW[ '+5[ &RQWUROORJLF[ ELW /)65[ WULDQJOH[ 7(1[ 0$03[>@ELWV :$9([>@ELWV "/&& ELW '25[ ELW 9''$ '$&B287 'LJLWDOWRDQDORJ FRQYHUWHU[ 966$ 95() -36 Table 38. DAC1/2 pins Name Note: Signal type Remarks VREF+ Input, analog reference positive The higher/positive reference voltage for the DAC, 1.8 V ≤ VREF+ ≤ VDDA VDDA Input, analog supply Analog power supply VSSA Input, analog supply ground Ground for analog power supply DAC1_OUT1 Analog output signal DACx channel y analog output Once the DACx channel y is enabled, the corresponding GPIO pin (PA4 or PA5) is automatically connected to the analog converter output (DACx_OUTy). In order to avoid parasitic consumption, the PA4 or PA5 pin should first be configured to analog (AIN). DocID022448 Rev 2 265/897 288 Digital-to-analog converter (DAC1 and DAC2) RM0313 14.3 Single mode functional description 14.3.1 DAC channel enable The DAC channel can be powered on by setting the EN1 bit in the DAC_CR register. The DAC channel is then enabled after a startup time tWAKEUP. Note: The ENx bit enables the analog DAC Channelx macrocell only. The DAC Channelx digital interface is enabled even if the ENx bit is reset. 14.3.2 DAC output buffer enable The DAC integrates an output buffer that can be used to reduce the output impedance, and to drive external loads directly without having to add an external operational amplifier. The DAC channel output buffer can be enabled and disabled using the BOFF1 bit in the DAC_CR register. 14.3.3 DAC data format Depending on the selected configuration mode, the data have to be written into the specified register as described below: • There are three possibilities: – 8-bit right alignment: the software has to load data into the DAC_DHR8Rx [7:0] bits (stored into the DHRx[11:4] bits) – 12-bit left alignment: the software has to load data into the DAC_DHR12Lx [15:4] bits (stored into the DHRx[11:0] bits) – 12-bit right alignment: the software has to load data into the DAC_DHR12Rx [11:0] bits (stored into the DHRx[11:0] bits) Depending on the loaded DAC_DHRyyyx register, the data written by the user is shifted and stored into the corresponding DHRx (data holding registerx, which are internal non-memorymapped registers). The DHRx register is then loaded into the DORx register either automatically, by software trigger or by an external event trigger. Figure 44. Data registers in single DAC channel mode 31 24 15 7 0 8-bit right aligned 12-bit left aligned 12-bit right aligned ai14710 14.3.4 DAC conversion The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must be performed by loading the DAC_DHRx register (write to DAC_DHR8Rx, DAC_DHR12Lx, DAC_DHR12Rx). Data stored in the DAC_DHRx register are automatically transferred to the DAC_DORx register after one APB1 clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR register is reset). However, when a hardware trigger is selected (TENx bit in DAC_CR 266/897 DocID022448 Rev 2 RM0313 Digital-to-analog converter (DAC1 and DAC2) register is set) and a trigger occurs, the transfer is performed three PCLK1 clock cycles later. When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage becomes available after a time tSETTLING that depends on the power supply voltage and the analog output load. Figure 45. Timing diagram for conversion with trigger disabled TEN = 0 APB1_CLK DHR 0x1AC Output voltage available on DAC_OUT pin 0x1AC DOR tSETTLING ai14711b 14.3.5 DAC output voltage Digital inputs are converted to output voltages on a linear conversion between 0 and VDDA. The analog output voltages on each DAC channel pin are determined by the following equation: DOR DACoutput = V DDA × -------------4095 14.3.6 DAC trigger selection If the TENx control bit is set, conversion can then be triggered by an external event (timer counter, external interrupt line). The TSELx[2:0] control bits determine which out of 8 possible events will trigger conversion as shown in Table 40. Table 39. External triggers (DAC1) Source Type TSEL[2:0] Timer 6 TRGO event 000 Timer 3 TRGO event 001 Timer 7 TRGO event Timer 5 TRGO event Internal signal from on-chip timers 010 011 Timer 2 TRGO event 100 Timer 4 TRGO event 101 EXTI line9 External pin 110 SWTRIG Software control bit 111 DocID022448 Rev 2 267/897 288 Digital-to-analog converter (DAC1 and DAC2) RM0313 Table 40. External triggers (DAC2) Source Type TSEL[2:0] Timer 6 TRGO event 000 Timer 3 TRGO event 001 Timer 7 TRGO event Timer 18 TRGO event Internal signal from on-chip timers 010 011 Timer 2 TRGO event 100 Timer 4 TRGO event 101 EXTI line9 External pin 110 SWTRIG Software control bit 111 Each time a DAC interface detects a rising edge on the selected timer TRGO output, or on the selected external interrupt line 9, the last data stored into the DAC_DHRx register are transferred into the DAC_DORx register. The DAC_DORx register is updated three APB1 cycles after the trigger occurs. If the software trigger is selected, the conversion starts once the SWTRIG bit is set. SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the DAC_DHRx register contents. Note: TSELx[2:0] bit cannot be changed when the ENx bit is set. When software trigger is selected, the transfer from the DAC_DHRx register to the DAC_DORx register takes only one APB1 clock cycle. 14.4 Dual mode functional description 14.4.1 DAC channel enable Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR register. The DAC channel is then enabled after a startup time tWAKEUP. Note: The ENx bit enables the analog DAC Channelx macrocell only. The DAC Channelx digital interface is enabled even if the ENx bit is reset. 14.4.2 DAC output buffer enable The DAC integrates two output buffers that can be used to reduce the output impedance, and to drive external loads directly without having to add an external operational amplifier. Each DAC channel output buffer can be enabled and disabled using the corresponding BOFFx bit in the DAC_CR register. 268/897 DocID022448 Rev 2 RM0313 14.4.3 Digital-to-analog converter (DAC1 and DAC2) DAC data format Depending on the selected configuration mode, the data have to be written into the specified register as described below: • Single DAC channel mode There are three possibilities: – 8-bit right alignment: the software has to load data into the DAC_DHR8Rx [7:0] bits (stored into the DHRx[11:4] bits) – 12-bit left alignment: the software has to load data into the DAC_DHR12Lx [15:4] bits (stored into the DHRx[11:0] bits) – 12-bit right alignment: the software has to load data into the DAC_DHR12Rx [11:0] bits (stored into the DHRx[11:0] bits) Depending on the loaded DAC_DHRyyyx register, the data written by the user is shifted and stored into the corresponding DHRx (data holding registerx, which are internal non-memorymapped registers). The DHRx register is then loaded into the DORx register either automatically, by software trigger or by an external event trigger. Figure 46. Data registers in single DAC channel mode 31 24 15 7 0 8-bit right aligned 12-bit left aligned 12-bit right aligned ai14710 • Dual DAC channel mode, there are three possibilities: – 8-bit right alignment: data for DAC channel1 to be loaded in the DAC_DHR8RD [7:0] bits (stored in the DHR1[11:4] bits) and data for DAC channel2 to be loaded in the DAC_DHR8RD [15:8] bits (stored in the DHR2[11:4] bits) – 12-bit left alignment: data for DAC channel1 to be loaded into the DAC_DHR12LD [15:4] bits (stored into the DHR1[11:0] bits) and data for DAC channel2 to be loaded into the DAC_DHR12LD [31:20] bits (stored in the DHR2[11:0] bits) – 12-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR12RD [11:0] bits (stored in the DHR1[11:0] bits) and data for DAC channel2 to be loaded into the DAC_DHR12LD [27:16] bits (stored in the DHR2[11:0] bits) Depending on the loaded DAC_DHRyyyD register, the data written by the user is shifted and stored in DHR1 and DHR2 (data holding registers, which are internal non-memorymapped registers). The DHR1 and DHR2 registers are then loaded into the DOR1 and DOR2 registers, respectively, either automatically, by software trigger or by an external event trigger. DocID022448 Rev 2 269/897 288 Digital-to-analog converter (DAC1 and DAC2) RM0313 Figure 47. Data registers in dual DAC channel mode 31 24 15 7 0 8-bit right aligned 12-bit left aligned 12-bit right aligned ai14709 14.4.4 DAC channel conversion The DAC channel conversion in dual mode is performed in the same way as in single mode (refer to Section 14.3.4) except that the data have to be loaded by writing to DAC_DHR8Rx, DAC_DHR12Lx, DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12LD or DAC_DHR12RD. 14.4.5 Description of dual conversion modes To efficiently use the bus bandwidth in applications that require the two DAC channels at the same time, three dual registers are implemented: DHR8RD, DHR12RD and DHR12LD. A unique register access is then required to drive both DAC channels at the same time. Eleven possible conversion modes are possible using the two DAC channels and these dual registers. All the conversion modes can nevertheless be obtained using separate DHRx registers if needed. All modes are described in the paragraphs below. Independent trigger without wave generation To configure the DAC in this conversion mode, the following sequence is required: 1. Set the two DAC channel trigger enable bits TEN1 and TEN2 2. Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits 3. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a DAC channel1 trigger arrives, the DHR1 register is transferred into DAC_DOR1 (three APB1 clock cycles later). When a DAC channel2 trigger arrives, the DHR2 register is transferred into DAC_DOR2 (three APB1 clock cycles later). Independent trigger with single LFSR generation To configure the DAC in this conversion mode, the following sequence is required: 270/897 1. Set the two DAC channel trigger enable bits TEN1 and TEN2 2. Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits 3. Configure the two DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask value in the MAMPx[3:0] bits 4. Load the dual DAC channel data into the desired DHR register (DHR12RD, DHR12LD or DHR8RD) DocID022448 Rev 2 RM0313 Digital-to-analog converter (DAC1 and DAC2) When a DAC channel1 trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). Then the LFSR1 counter is updated. When a DAC channel2 trigger arrives, the LFSR2 counter, with the same mask, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). Then the LFSR2 counter is updated. Independent trigger with different LFSR generation To configure the DAC in this conversion mode, the following sequence is required: 1. Set the two DAC channel trigger enable bits TEN1 and TEN2 2. Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits 3. Configure the two DAC channel WAVEx[1:0] bits as “01” and set different LFSR masks values in the MAMP1[3:0] and MAMP2[3:0] bits 4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a DAC channel1 trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). Then the LFSR1 counter is updated. When a DAC channel2 trigger arrives, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). Then the LFSR2 counter is updated. Independent trigger with single triangle generation To configure the DAC in this conversion mode, the following sequence is required: 1. Set the two DAC channel trigger enable bits TEN1 and TEN2 2. Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits 3. Configure the two DAC channel WAVEx[1:0] bits as “1x” and the same maximum amplitude value in the MAMPx[3:0] bits 4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with the same triangle amplitude, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then updated. When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with the same triangle amplitude, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then updated. Independent trigger with different triangle generation To configure the DAC in this conversion mode, the following sequence is required: DocID022448 Rev 2 271/897 288 Digital-to-analog converter (DAC1 and DAC2) RM0313 1. Set the two DAC channel trigger enable bits TEN1 and TEN2 2. Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits 3. Configure the two DAC channel WAVEx[1:0] bits as “1x” and set different maximum amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits 4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then updated. When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with a triangle amplitude configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then updated. Simultaneous software start To configure the DAC in this conversion mode, the following sequence is required: 1. Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) In this configuration, one APB1 clock cycle later, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and DAC_DOR2, respectively. Simultaneous trigger without wave generation To configure the DAC in this conversion mode, the following sequence is required: 1. Set the two DAC channel trigger enable bits TEN1 and TEN2 2. Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits 3. Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a trigger arrives, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and DAC_DOR2, respectively (after three APB1 clock cycles). Simultaneous trigger with single LFSR generation To configure the DAC in this conversion mode, the following sequence is required: 1. Set the two DAC channel trigger enable bits TEN1 and TEN2 2. Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits 3. Configure the two DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask value in the MAMPx[3:0] bits 4. Load the dual DAC channel data to the desired DHR register (DHR12RD, DHR12LD or DHR8RD) When a trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The LFSR1 counter is then updated. At the same time, the LFSR2 counter, with the same mask, 272/897 DocID022448 Rev 2 RM0313 Digital-to-analog converter (DAC1 and DAC2) is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The LFSR2 counter is then updated. Simultaneous trigger with different LFSR generation To configure the DAC in this conversion mode, the following sequence is required: 1. Set the two DAC channel trigger enable bits TEN1 and TEN2 2. Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits 3. Configure the two DAC channel WAVEx[1:0] bits as “01” and set different LFSR mask values using the MAMP1[3:0] and MAMP2[3:0] bits 4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The LFSR1 counter is then updated. At the same time, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The LFSR2 counter is then updated. Simultaneous trigger with single triangle generation To configure the DAC in this conversion mode, the following sequence is required: 1. Set the two DAC channel trigger enable bits TEN1 and TEN2 2. Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits 3. Configure the two DAC channel WAVEx[1:0] bits as “1x” and the same maximum amplitude value using the MAMPx[3:0] bits 4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a trigger arrives, the DAC channel1 triangle counter, with the same triangle amplitude, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then updated. At the same time, the DAC channel2 triangle counter, with the same triangle amplitude, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then updated. Simultaneous trigger with different triangle generation To configure the DAC in this conversion mode, the following sequence is required: 1. Set the two DAC channel trigger enable bits TEN1 and TEN2 2. Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits 3. Configure the two DAC channel WAVEx[1:0] bits as “1x” and set different maximum amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits 4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DocID022448 Rev 2 273/897 288 Digital-to-analog converter (DAC1 and DAC2) RM0313 DAC_DOR1 (three APB1 clock cycles later). Then the DAC channel1 triangle counter is updated. At the same time, the DAC channel2 triangle counter, with a triangle amplitude configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). Then the DAC channel2 triangle counter is updated. 14.4.6 DAC output voltage Digital inputs are converted to output voltages on a linear conversion between 0 and VDDA. The analog output voltages on each DAC channel pin are determined by the following equation: DOR DACoutput = V DDA × -------------4095 14.4.7 DAC trigger selection If the TENx control bit is set, conversion can then be triggered by an external event (timer counter, external interrupt line). The TSELx[2:0] control bits determine which out of 8 possible events will trigger conversion as shown in table below. Table 41. External triggers (DAC1) Source Type TSEL[2:0] Timer 6 TRGO event 000 Timer 3 TRGO event 001 Timer 7 TRGO event Timer 5 TRGO event Internal signal from on-chip timers 010 011 Timer 2 TRGO event 100 Timer 4 TRGO event 101 EXTI line9 External pin 110 SWTRIG Software control bit 111 Each time a DAC interface detects a rising edge on the selected timer TRGO output, or on the selected external interrupt line 9, the last data stored into the DAC_DHRx register are transferred into the DAC_DORx register. The DAC_DORx register is updated three APB1 cycles after the trigger occurs. If the software trigger is selected, the conversion starts once the SWTRIG bit is set. SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the DAC_DHRx register contents. Note: TSELx[2:0] bit cannot be changed when the ENx bit is set. When software trigger is selected, the transfer from the DAC_DHRx register to the DAC_DORx register takes only one APB1 clock cycle. 14.5 Noise generation In order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift register) is available. DAC noise generation is selected by setting WAVEx[1:0] to “01”. The 274/897 DocID022448 Rev 2 RM0313 Digital-to-analog converter (DAC1 and DAC2) preloaded value in LFSR is 0xAAA. This register is updated three APB1 clock cycles after each trigger event, following a specific calculation algorithm. Figure 48. DAC LFSR register calculation algorithm XOR X6 X 12 11 10 9 8 7 6 X4 5 4 X0 X 3 2 1 0 12 NOR ai14713b The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this value is then stored into the DAC_DORx register. If LFSR is 0x0000, a ‘1 is injected into it (antilock-up mechanism). It is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits. Figure 49. DAC conversion (SW trigger enabled) with LFSR wave generation APB1_CLK DHR DOR 0x00 0xAAA 0xD55 SWTRIG ai14714 Note: The DAC trigger must be enabled for noise generation by setting the TENx bit in the DAC_CR register. DocID022448 Rev 2 275/897 288 Digital-to-analog converter (DAC1 and DAC2) 14.6 RM0313 Triangle-wave generation It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal. DAC triangle-wave generation is selected by setting WAVEx[1:0] to “10”. The amplitude is configured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter is incremented three APB1 clock cycles after each trigger event. The value of this counter is then added to the DAC_DHRx register without overflow and the sum is stored into the DAC_DORx register. The triangle counter is incremented as long as it is less than the maximum amplitude defined by the MAMPx[3:0] bits. Once the configured amplitude is reached, the counter is decremented down to 0, then incremented again and so on. It is possible to reset triangle wave generation by resetting the WAVEx[1:0] bits. Figure 50. DAC triangle wave generation N TIO EN EM CR N TIO TA )N EN EM CR TA $E -!-0X;=MAXAMPLITUDE $!#?$(2XBASEVALUE $!#?$(2XBASEVALUE AIC Figure 51. DAC conversion (SW trigger enabled) with triangle wave generation APB1_CLK DHR DOR 0xABE 0xABE 0xABF 0xAC0 SWTRIG ai14714 Note: The DAC trigger must be enabled for triangle generation by setting the TENx bit in the DAC_CR register. The MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot be changed. 14.7 DMA request Each DAC channel has a DMA capability. Two DMA channels are used to service DAC channel DMA requests. A DAC DMA request is generated when an external trigger (but not a software trigger) occurs while the DMAENx bit is set. The value of the DAC_DHRx register is then transferred to the DAC_DORx register. 276/897 DocID022448 Rev 2 RM0313 Digital-to-analog converter (DAC1 and DAC2) In dual mode, if both DMAENx bits are set, two DMA requests are generated. If only one DMA request is needed, you should set only the corresponding DMAENx bit. In this way, the application can manage both DAC channels in dual mode by using one DMA request and a unique DMA channel. DMA underrun The DAC DMA request is not queued so that if a second external trigger arrives before the acknowledgement for the first external trigger is received (first request), then no new request is issued and the DMA channelx underrun flag DMAUDRx in the DAC_SR register is set, reporting the error condition. DMA data transfers are then disabled and no further DMA request is treated. The DAC channelx continues to convert old data. The software should clear the DMAUDRx flag by writing “1”, clear the DMAEN bit of the used DMA stream and re-initialize both DMA and DAC channelx to restart the transfer correctly. The software should modify the DAC trigger conversion frequency or lighten the DMA workload to avoid a new DMA. Finally, the DAC conversion can be resumed by enabling both DMA data transfer and conversion trigger. For each DAC channel, an interrupt is also generated if the corresponding DMAUDRIEx bit in the DAC_CR register is enabled. 14.8 DAC registers Refer to Section 1.1 on page 36 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 14.8.1 DAC control register (DAC_CR) Address offset: 0x00 Reset value: 0x0000 0000 31 Res. 15 Res. 30 29 28 Res. DMAU DRIE2 DMA EN2 rw rw rw rw rw rw rw rw rw rw 11 10 9 8 7 6 5 4 14 13 12 Res. DMAU DRIE1 DMA EN1 rw rw 27 26 25 24 MAMP2[3:0] rw rw 22 21 WAVE2[1:0] MAMP1[3:0] rw 23 rw rw DocID022448 Rev 2 19 18 17 16 TEN2 BOFF2 EN2 rw rw rw rw 3 2 1 0 TEN1 BOFF1 EN1 rw rw rw TSEL2[2:0] WAVE1[1:0] rw 20 TSEL1[2:0] rw rw rw 277/897 288 Digital-to-analog converter (DAC1 and DAC2) RM0313 Bits 31:30 Reserved, must be kept at reset value. Bit 29 DMAUDRIE2: DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software. 0: DAC channel2 DMA underrun interrupt disabled 1: DAC channel2 DMA underrun interrupt enabled Note: This bit is available in dual mode only. It is reserved in single mode. Bit 28 DMAEN2: DAC channel2 DMA enable This bit is set and cleared by software. 0: DAC channel2 DMA mode disabled 1: DAC channel2 DMA mode enabled Note: This bit is available in dual mode only. It is reserved in single mode. Bits 27:24 MAMP2[3:0]: DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1 0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15 0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31 0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63 0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127 0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255 1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511 1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023 1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047 ≥1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 Note: These bits are available in dual mode only. They are reserved in single mode. Bits 23:22 WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 00: wave generation disabled 01: Noise wave generation enabled 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) These bits are available in dual mode only. They are reserved in single mode. Bits 21:19 TSEL2[2:0]: DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 000: Timer 6 TRGO event 001: Timer 3 TRGO event 010: Timer 7 TRGO event 011: Timer 5 TRGO event 100: Timer 2 TRGO event 101: Timer 4 TRGO event 110: EXTI line9 111: Software trigger Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled). These bits are available in dual mode only. They are reserved in single mode. 278/897 DocID022448 Rev 2 RM0313 Digital-to-analog converter (DAC1 and DAC2) Bit 18 TEN2: DAC channel2 trigger enable This bit is set and cleared by software to enable/disable DAC channel2 trigger 0: DAC channel2 trigger disabled and data written into the DAC_DHRx register are transferred one APB1 clock cycle later to the DAC_DOR2 register 1: DAC channel2 trigger enabled and data from the DAC_DHRx register are transferred three APB1 clock cycles later to the DAC_DOR2 register Note: When software trigger is selected, the transfer from the DAC_DHRx register to the DAC_DOR2 register takes only one APB1 clock cycle. Note: This bit is available in dual mode only. It is reserved in single mode. Bit 17 BOFF2: DAC channel2 output buffer disable This bit is set and cleared by software to enable/disable DAC channel2 output buffer. 0: DAC channel2 output buffer enabled 1: DAC channel2 output buffer disabled Note: This bit is available in dual mode only. It is reserved in single mode. Bit 16 EN2: DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2. 0: DAC channel2 disabled 1: DAC channel2 enabled Note: This bit is available in dual mode only. It is reserved in single mode. Bits 15:14 Reserved, must be kept at reset value. Bit 13 DMAUDRIE1: DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software. 0: DAC channel1 DMA Underrun Interrupt disabled 1: DAC channel1 DMA Underrun Interrupt enabled Bit 12 DMAEN1: DAC channel1 DMA enable This bit is set and cleared by software. 0: DAC channel1 DMA mode disabled 1: DAC channel1 DMA mode enabled Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1 0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15 0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31 0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63 0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127 0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255 1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511 1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023 1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047 ≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 DocID022448 Rev 2 279/897 288 Digital-to-analog converter (DAC1 and DAC2) RM0313 Bits 7:6 WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. 00: Wave generation disabled 01: Noise wave generation enabled 1x: Triangle wave generation enabled Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). Bits 5:3 TSEL1[2:0]: DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. 000: Timer 6 TRGO event 001: Timer 3 TRGO event 010: Timer 7 TRGO event 011: Timer 5 TRGO event (for DAC1), Timer 18 TRGO event (for DAC2) 100: Timer 2 TRGO event 101: Timer 4 TRGO event 110: EXTI line9 111: Software trigger Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). Bit 2 TEN1: DAC channel1 trigger enable This bit is set and cleared by software to enable/disable DAC channel1 trigger. 0: DAC channel1 trigger disabled and data written into the DAC_DHRx register are transferred one APB1 clock cycle later to the DAC_DOR1 register 1: DAC channel1 trigger enabled and data from the DAC_DHRx register are transferred three APB1 clock cycles later to the DAC_DOR1 register Note: When software trigger is selected, the transfer from the DAC_DHRx register to the DAC_DOR1 register takes only one APB1 clock cycle. Bit 1 BOFF1: DAC channel1 output buffer disable This bit is set and cleared by software to enable/disable DAC channel1 output buffer. 0: DAC channel1 output buffer enabled 1: DAC channel1 output buffer disabled Bit 0 EN1: DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1. 0: DAC channel1 disabled 1: DAC channel1 enabled 280/897 DocID022448 Rev 2 RM0313 Digital-to-analog converter (DAC1 and DAC2) 14.8.2 DAC software trigger register (DAC_SWTRIGR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 0 SWTRIG2 SWTRIG1 w w Bits 31:2 Reserved, must be kept at reset value. Bit 1 SWTRIG2: DAC channel2 software trigger This bit is set and cleared by software to enable/disable the software trigger. 0: Software trigger disabled 1: Software trigger enabled Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register. This bit is available in dual mode only. It is reserved in single mode. Bit 0 SWTRIG1: DAC channel1 software trigger This bit is set and cleared by software to enable/disable the software trigger. 0: Software trigger disabled 1: Software trigger enabled Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register. 14.8.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. rw rw rw rw rw rw rw rw rw rw DACC1DHR[11:0] rw rw Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. DocID022448 Rev 2 281/897 288 Digital-to-analog converter (DAC1 and DAC2) 14.8.4 RM0313 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 DACC1DHR[11:0] rw rw rw rw rw rw rw rw rw rw rw 3 2 1 0 Res. Res. Res. Res. rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. Bits 3:0 Reserved, must be kept at reset value. 14.8.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 1 0 rw rw rw 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. DACC1DHR[7:0] rw rw rw rw rw Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. 14.8.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw 15 14 13 12 Res. Res. Res. Res. DACC2DHR[11:0] rw 282/897 rw rw rw rw rw DocID022448 Rev 2 rw RM0313 Digital-to-analog converter (DAC1 and DAC2) Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. 14.8.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) Address offset: 0x18 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 DACC2DHR[11:0] rw rw rw rw rw rw rw rw rw rw rw 3 2 1 0 Res. Res. Res. Res. rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:4 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2. Bits 3:0 Reserved, must be kept at reset value. 14.8.8 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) Address offset: 0x1C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. rw rw rw rw rw rw DACC2DHR[7:0] rw rw Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. DocID022448 Rev 2 283/897 288 Digital-to-analog converter (DAC1 and DAC2) 14.8.9 RM0313 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) Address offset: 0x20 Reset value: 0x0000 0000 31 30 29 28 Res. Res. Res. Res. 15 14 13 12 Res. Res. Res. Res. 27 26 25 24 23 22 21 20 19 18 17 16 DACC2DHR[11:0] rw rw rw rw rw rw rw rw rw rw rw rw 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw DACC1DHR[11:0] rw rw rw rw rw rw rw Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. Bits 15:12 Reserved, must be kept at reset value. Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. 14.8.10 DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) Address offset: 0x24 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 DACC2DHR[11:0] rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 rw rw rw rw rw rw rw rw rw rw DACC1DHR[11:0] rw rw 19 18 17 16 Res. Res. Res. Res. 3 2 1 0 Res. Res. Res. Res. Bits 31:20 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. Bits 19:16 Reserved, must be kept at reset value. Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. Bits 3:0 Reserved, must be kept at reset value. 284/897 DocID022448 Rev 2 RM0313 Digital-to-analog converter (DAC1 and DAC2) 14.8.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) Address offset: 0x28 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw DACC2DHR[7:0] rw rw rw rw DACC1DHR[7:0] rw rw rw rw rw rw rw rw rw Bits 31:168 Reserved, must be kept at reset value. Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. 14.8.12 DAC channel1 data output register (DAC_DOR1) Address offset: 0x2C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. r r r r r r r r r r DACC1DOR[11:0] r r Bits 31:12 Reserved, must be kept at reset value. Bit 11:0 DACC1DOR[11:0]: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1. 14.8.13 DAC channel2 data output register (DAC_DOR2) Address offset: 0x30 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r 15 14 13 12 Res. Res. Res. Res. DACC2DOR[11:0] r r r r r DocID022448 Rev 2 r r 285/897 288 Digital-to-analog converter (DAC1 and DAC2) RM0313 Bits 31:12 Reserved, must be kept at reset value. Bit 11:0 DACC2DOR[11:0]: DAC channel2 data output These bits are read-only, they contain data output for DAC channel2. 14.8.14 DAC status register (DAC_SR) Address offset: 0x34 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. DMAUDR2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. DMAUDR1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rc_w1 Bits 31:30 Reserved, must be kept at reset value. Bit 29 DMAUDR2: DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 0: No DMA underrun error condition occurred for DAC channel2 1: DMA underrun error condition occurred for DAC channel2 (the currently selected trigger is driving DAC channel2 conversion at a frequency higher than the DMA service capability rate) Note: This bit is available in dual mode only. It is reserved in single mode. Bits 28:14 Reserved, must be kept at reset value. Bit 13 DMAUDR1: DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 0: No DMA underrun error condition occurred for DAC channel1 1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate) Bits 12:0 Reserved, must be kept at reset value. 286/897 DocID022448 Rev 2 0x30 DAC_DOR2 Reset value DocID022448 Rev 2 0 0 0 0 Res. Reset value 0 0 0 Res. 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Reset value Res. 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0 Reset value 0 0 0 0 0 Res. Res. Res. 0 DACC1DHR[11:0] 0 0 0 0 0 0 0 0 0 0 DACC1DHR[7:0] 0 0 DACC2DHR[7:0] 0 0 0 0 0 0 0 0 0 DACC2DHR[11:0] DACC2DHR[11:0] 0 0 0 0 0 0 DACC1DHR[11:0] 0 0 0 0 0 0 0 Res. 0 Res. 0 0 0 0 Res. 0 0 Res. 0 0 0 0 0 0 0 0 0 Res. 0 Res. 0 DACC2DHR[7:0] 0 DACC1DHR[11:0] Res. 0 Res. 0 Res. 0 Res. 0 0 0 0 0 0 0 0 0 DACC1DHR[7:0] 0 DACC1DOR[11:0] 0 DACC2DOR[11:0] Res. Reset value 0 Res. 0 Res. 0 Res. 0 Res. Reset value Res. Res. Res. Res. Reset value Res. Res. Res. EN2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMAEN1 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EN1 0 Reset value SWTRIG1 TEN1 BOFF1 0 SWTRIG2 0 Res. TSEL1[2:0] WAVE1[1:0] MAMP1[3:0]. DMAUDRIE1 Res. Res. TSEL2[2:0] WAVE2[1:0] 0 Res. Res. Res. 0 Res. Res. 0 Res. Res. TEN2 BOFF2 0 Res. Res. Res. Res. 0 Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. DMAEN2 0 MAMP2[3:0] DMAUDRIE2 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. DACC2DHR[11:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. 0 Res. Res. DAC_ DHR8RD Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. DACC2DHR[11:0] Res. 0 Res. 0 Res. Res. Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. 0 Res. 0 Res. Res. Res. 0 Res. 0 Res. Res. 0 Res. DAC_DOR1 Res. DAC_ DHR12LD 0 Res. 0x2C 0 Res. 0 Res. Reset value Res. 0 Res. DAC_ DHR12RD Res. Reset value Res. 0x28 DAC_ DHR8R2 Res. 0x24 DAC_ DHR12L2 Res. 0x20 DAC_ DHR12R2 Res. 0x1C DAC_ DHR8R1 Res. Reset value Res. 0x18 DAC_ DHR12L1 Res. 0x14 DAC_ DHR12R1 Res. 0x10 DAC_ SWTRIGR Res. DAC_CR Res. 0x0C Res. 0x08 Res. 0x00 Res. 0x04 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register name Res. Offset Res. 14.8.15 Res. RM0313 Digital-to-analog converter (DAC1 and DAC2) DAC register map Table 42 summarizes the DAC registers. Table 42. DAC register map and reset values 0 0 DACC1DHR[11:0] 0 0 0 0 0 0 0 0 0 0 0 0 287/897 288 Digital-to-analog converter (DAC1 and DAC2) RM0313 Reset value 0 0 Refer to Section 2.2.2 for the register boundary addresses. 288/897 DocID022448 Rev 2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMAUDR1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMAUDR2 DAC_SR 0x34 Res. Register name Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 42. DAC register map (continued)and reset values (continued) RM0313 Comparator (COMP) 15 Comparator (COMP) 15.1 COMP introduction The STM32F37xx/STM32F38xx embedstwo general purpose comparators COMP1 and COMP2,that can be used either as standalone devices (all terminal are available on I/Os) or combined with the timers. They can be used for a variety of functions including: 15.2 • Wake-up from low-power mode triggered by an analog signal, • Analog signal conditioning, • Cycle-by-cycle current control loop when combined with the DAC and a PWM output from a timer. COMP main features • Rail-to-rail comparators • Each comparator has configurable positive and negative inputs used for flexible voltage selection: – 3 I/O pins – DAC1 – Internal reference voltage and three submultiple values (1/4, 1/2, 3/4) provided by scaler (buffered voltage divider). • Programmable hysteresis • Programmable speed and consumption • The outputs can be redirected to an I/O or to multiple timer inputs for triggering: – Capture events – OCref_clr events (for cycle-by-cycle current control) – Break events for fast PWM shutdowns • COMP1 and COMP2 comparators can be combined in a window comparator. • The two comparators can be combined in a window comparator • Each comparator has interrupt generation capability with wake-up from Sleep and Stop modes (through the EXTI controller) DocID022448 Rev 2 289/897 296 Comparator (COMP) RM0313 15.3 COMP functional description 15.3.1 General description The block diagram of the comparators is shown in Figure 52: Comparator 1 and 2 block diagram. Figure 52. Comparator 1 and 2 block diagram #/-0?/54 0! #/-0?).0 #/-0INTERRUPTREQUEST TO%84) #/-0 #/-0?).0! 0!$!#?/54 0!$!#?/54 0!$!#?/54 62%&).4 62%&).4 62%&).4 62%&).4 0! 0! 0!$!#?/54 0!$!#?/54 0!$!#?/54 62%&).4 62%&).4 62%&).4 62%&).4 0OLARITY SELECTION 4)-?)# 4)-?/#REF?CLR 4)-?"+). 4)-?)# 4)-?/#REF?CLR 4)-?)# 4)-?/#REF?CLR #/-0?/54 #/-0?).0 7INDOW MODE 0!0!0!0" 0!0!0!0" #/-0INTERRUPTREQUEST TO%84) #/-0 0OLARITY SELECTION #/-0?).- 4)-?)# 4)-?/#REF?CLR 4)-?"+). 4)-?)# 4)-?/#REF?CLR 4)-?)# 4)-?/#REF?CLR -36 15.3.2 Clock The COMP clock provided by the clock controller is synchronous with the PCLK (APB1 clock). There is no clock enable control bit provided in the RCC controller. Note: Important: The polarity selection logic and the output redirection to the port works independently from the PCLK clock. This allows the comparator to work even in Stop mode. 15.3.3 Comparator inputs and outputs The I/Os used as comparators inputs must be configured in analog mode in the GPIOs registers. The comparator output can be connected to the I/Os using the alternate function channel given in “Alternate function mapping” table in the datasheet. The output can also be internally redirected to a variety of timer input for the following purposes: 290/897 DocID022448 Rev 2 RM0313 Comparator (COMP) • Emergency shut-down of PWM signals, using BKIN • Cycle-by-cycle current control, using OCref_clr inputs • Input capture for timing measures It is possible to have the comparator output simultaneously redirected internally and externally. 15.3.4 Interrupt and wakeup The comparator outputs are internally connected to the Extended interrupts and events controller. Each comparator has its own EXTI line and can generate either interrupts or events. The same mechanism is used to exit from low power modes. Refer to Interrupt and events section for more details. 15.4 Power mode The comparator power consumption versus propagation delay can be adjusted to have the optimum trade-off for a given application.The bits COMPxMODE[1:0] in COMP_CSR register can be programmed as follows: 15.4.1 • 00: High speed / full power • 01: Medium speed / medium power • 10: Low speed / low power • 11: Very-low speed / ultra-low power Comparator LOCK mechanism The comparators can be used for safety purposes, such as over-current or thermal protection. For applications having specific functional safety requirements, it is necessary to insure that the comparator programming cannot be altered in case of spurious register access or program counter corruption. For this purpose, the comparator control and status registers can be write-protected (readonly). Once the programming is completed, using bits 30:16 and 15:0 of COMP_CSR, the COMPxLOCK bit must be set to 1. This causes the whole COMP_CSR register to become read-only, including the COMPxLOCK bit. The write protection can only be reset by a MCU reset. 15.4.2 Hysteresis The comparator includes a programmable hysteresis to avoid spurious output transitions in case of noisy signals. The hysteresis can be disabled if it is not needed (for instance when exiting from low power mode) to be able to force the hysteresis value using external components. DocID022448 Rev 2 291/897 296 Comparator (COMP) RM0313 Figure 53. Comparator hysteresis ).0 ).).-6 HYS T #/-0?/54 -36 292/897 DocID022448 Rev 2 RM0313 Comparator (COMP) 15.5 COMP registers 15.5.1 COMP control and status register (COMP_CSR) Address offset: 0x1C Reset value: 0x0000 0000 31 30 COMP COMP 2LOCK 2OUT 29 28 COMP2HYST [1:0] 27 COMP 2POL 26 25 24 COMP2OUTSEL[2:0] 23 WNDW EN 22 21 20 COMP2INSEL[2:0] 19 18 COMP2MODE [1:0] rwo r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 COMP COMP 1LOCK 1OUT rwo r COMP1HYST [1:0] rw/r rw/r COMP 1POL rw/r COMP1OUTSEL[2:0] rw/r rw/r Res. rw/r COMP1INSEL[2:0] rw/r rw/r rw/r COMP1MODE [1:0] rw/r rw/r 17 16 Res. COMP2 EN rw/r 1 0 COMP1 COMP1 _INP_D EN AC rw/r rw/r Bit 31 COMP2LOCK: Comparator 2 lock This bit is write-once. It is set by software. It can only be cleared by a system reset. It allows to have all control bits of comparator 2 as read-only. 0: COMP_CSR[31:16] bits are read-write. 1: COMP_CSR[31:16] bits are read-only. Bit 30 COMP2OUT: Comparator 2 output This read-only bit is a copy of comparator 2 output state. 0: Output is low (non-inverting input below inverting input). 1: Output is high (non-inverting input above inverting input). Bits 29:28 COMP2HYST[1:0] Comparator 2 hysteresis These bits control the hysteresis level. 00: No hysteresis 01: Low hysteresis 10: Medium hysteresis 11: High hysteresis Please refer to the electrical characteristics for the hysteresis values. Bit 27 COMP2POL: Comparator 2 output polarity This bit is used to invert the comparator 2 output. 0: Output is not inverted 1: Output is inverted Bits 26:24 COMP2OUTSEL[2:0]: Comparator 2 output selection These bits select the destination of the comparator output. 000: No selection 001: Timer 16 break input 010: Timer 4 Input capture 1 011: Timer 4 OCrefclear input 100: Timer 2 input capture 4 101: Timer 2 OCrefclear input 110: Timer 3 input capture 1 111: Timer 3 OCrefclear input DocID022448 Rev 2 293/897 296 Comparator (COMP) RM0313 Bit 23 WNDWEN: Window mode enable This bit connects the non-inverting input of COMP2 to COMP1’s non-inverting input, which is simultaneously disconnected from PA3. 0: Window mode disabled 1: Window mode enabled Bits 22:20 COMP2INSEL[2:0]: Comparator 2 inverting input selection These bits allows to select the source connected to the inverting input of the comparator 2. 000: 1/4 of Vrefint 001: 1/2 of Vrefint 010: 3/4 of Vrefint 011: Vrefint 100: DAC1_OUT1 output (and PA4 output) 101: Input from PA5 (and DAC1_OUT2 output) 110: Input from PA2 111: Input from PA6 (and DAC2_OUT1 output) Bits 19:18 COMP2MODE[1:0]: Comparator 2 mode These bits control the operating mode of the comparator2 and allows to adjust the speed/consumption. 00: High speed/ 01: Medium speed 10: Low power 11: Ultra-low power Bit 17 Reserved, must be kept at reset value. Bit 16 COMP2EN: Comparator 2 enable This bit switches ON/OFF the comparator2. 0: Comparator 2 disabled 1: Comparator 2 enabled Bit 15 COMP1LOCK: Comparator 1 lock This bit is write-once. It is set by software. It can only be cleared by a system reset. It allows to have all control bits of comparator 1 as read-only. 0: COMP_CSR[15:0] bits are read-write. 1: COMP_CSR[15:0] bits are read-only. Bit 14 COMP1OUT: Comparator 1 output This read-only bit is a copy of comparator 1 output state. 0: Output is low (non-inverting input below inverting input). 1: Output is high (non-inverting input above inverting input). Bits 13:12 COMP1HYST[1:0] Comparator 1 hysteresis These bits are controlling the hysteresis level. 00: No hysteresis 01: Low hysteresis 10: Medium hysteresis 11: High hysteresis Please refer to the electrical characteristics for the hysteresis values. Bit 11 COMP1POL: Comparator 1 output polarity This bit is used to invert the comparator 1 output. 0: output is not inverted 1: output is inverted 294/897 DocID022448 Rev 2 RM0313 Comparator (COMP) Bits 10:8 COMP1OUTSEL[2:0]: Comparator 1 output selection These bits selects the destination of the comparator 1 output. 000: no selection 001: Timer 15 break input 010: Timer 3 Input capture 1 011: Timer 3 OCrefclear input 100: Timer 2 input capture 4 101: Timer 2 OCrefclear input 110: Timer 5 input capture 4 111: Timer 5 OCrefclear input Bit 7 Reserved, must be kept at reset value. Bits 6:4 COMP1INSEL[2:0]: Comparator 1 inverting input selection These bits select the source connected to the inverting input of the comparator 1. 000: 1/4 of Vrefint 001: 1/2 of Vrefint 010: 3/4 of Vrefint 011: Vrefint 100: DAC1_OUT1output (and PA4) 101: Input from PA5 (and DAC1_OUT2 output) 110: Input from PA0 111: Input from PA6 (and DAC2_OUT1 output) Bits 3:2 COMP1MODE[1:0]: Comparator 1 mode These bits control the operating mode of the comparator1 and allows to adjust the speed/consumption. 00: Ultra-low power 01: Low power 10: Medium speed 11: High speed Bit 1 COMP1_INP_DAC: Comparator 1 non-inverting input connection to DAC output. This bit closes a switch between comparator 1 non-inverting input on PA0 and PA4 (DAC) I/O. 0: Switch open 1: Switch closed Note: This switch is solely intended to redirect signals onto high impedance input, such as COMP1 non-inverting input (highly resistive switch). Bit 0 COMP1EN: Comparator 1 enable This bit switches COMP1 ON/OFF. 0: Comparator 1 disabled 1: Comparator 1 enabled DocID022448 Rev 2 295/897 296 Comparator (COMP) 15.5.2 RM0313 COMP register map The following table summarizes the comparator registers. 0 0 0 0 0 0 0 0 0 0 0 0 0 Refer to Section 2.2.2 on page 41 for the register boundary addresses. 296/897 DocID022448 Rev 2 COMP1MODE[1:0] COMP1INSEL[2:0] Res. 0 COMP1OUTSEL[2:0] 0 COMP1POL 0 COMP1HYST[1:0] Res. COMP2INSEL[2:0] 0 0 0 0 0 0 COMP1EN 0 COMP1_INP_DAC 0 WNDWEN COMP2POL 0 COMP1OUT 0 COMP1LOCK 0 COMP2EN 0 COMP2MODE[1:0] Reset value COMP2OUTSEL[2:0] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COMP_CSR 0x1C COMP2HYST[1:0] Register COMP2OUT Offset COMP register map and reset values COMP2LOCK Table 43. 0 0 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) 16 General-purpose timers (TIM2 to TIM5, TIM19) 16.1 Ito TIM5/TIM19 ntroduction The general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers. The timer are completely independent, and do not share any resources. They can be synchronized together as described in Section 16.3.15. 16.2 TIM2 to TIM5/TIM19 main features General-purpose TIMx timer features include: • 16-bit (TIM3, TIM4, and TIM19) or 32-bit (TIM2 and TIM5) up, down, up/down autoreload counter. • 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65535. • Up to 4 independent channels for: – Input capture – Output compare – PWM generation (Edge- and Center-aligned modes) – One-pulse mode output • Synchronization circuit to control the timer with external signals and to interconnect several timers. • Interrupt/DMA generation on the following events: – Update: counter overflow/underflow, counter initialization (by software or internal/external trigger) – Trigger event (counter start, stop, initialization or count by internal/external trigger) – Input capture – Output compare • Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning purposes • Trigger input for external clock or cycle-by-cycle current management DocID022448 Rev 2 297/897 359 General-purpose timers (TIM2 to TIM5, TIM19) RM0313 Figure 54. General-purpose timer block diagram ,QWHUQDOFORFN&.B,17 7,0[&/.IURP5&& (75) (75 7,0[B(75 7ULJJHU FRQWUROOHU 75*2 3RODULW\VHOHFWLRQHGJH (753 ,QSXWILOWHU GHWHFWRUSUHVFDOHU ,75 ,75 ,75 ,75 WRRWKHUWLPHUV WR'$&$'& 7*, ,75 75& 75*, 6ODYH FRQWUROOHU 5HVHWHQDEOHXSFRXQW PRGH 7,)B(' (QFRGHU LQWHUIDFH 7,)3 7,)3 8 $XWRUHORDGUHJLVWHU 8, 6WRSFOHDURUXSGRZQ &.B36& ;25 7, 7,0[B&+ 7,0[B&+ ,QSXWILOWHU HGJHGHWHFWRU 7, ,QSXWILOWHU HGJHGHWHFWRU 7, ,QSXWILOWHU HGJHGHWHFWRU 7,)3 7,)3 ,& 36& &.B&17 SUHVFDOHU &&, 8 3UHVFDOHU 75& 7,)3 7,)3 75& ,&36 &&, ,& 3UHVFDOHU 7,0[B&+ 7, 7,0[B&+ ,QSXWILOWHU HGJHGHWHFWRU ,& 3UHVFDOHU 75& 7,)3 7,)3 8 &17FRXQWHU &&, &DSWXUH&RPSDUHUHJLVWHU 2&5() &DSWXUH&RPSDUHUHJLVWHU 2&5() ,&36 &DSWXUH&RPSDUHUHJLVWHU 2&5() &&, 3UHVFDOHU ,&36 2XWSXW 2& FRQWURO 7,0[B&+ 2XWSXW 2& FRQWURO 7,0[B&+ 2XWSXW 2& FRQWURO 7,0[B&+ &&, 8 ,& 7,0[B&+ &&, 8 ,&36 2XWSXW 2& FRQWURO &&, 8 &&, 7,)3 7,)3 &DSWXUH&RPSDUHUHJLVWHU 2&5() 75& (75) 1RWHV 5HJ 3UHORDGUHJLVWHUVWUDQVIHUUHG WRDFWLYHUHJLVWHUVRQ8HYHQW DFFRUGLQJWRFRQWUROELW (YHQW ,QWHUUXSW'0$RXWSXW 069 16.3 TIM2 to TIM5/TIM19 functional description 16.3.1 Time-base unit The main block of the programmable timer is a 16-bit/32-bit counter with its related autoreload register. The counter can count up, down or both up and down but also down or both up and down. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running. 298/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) The time-base unit includes: • Counter Register (TIMx_CNT) • Prescaler Register (TIMx_PSC): • Auto-Reload Register (TIMx_ARR) The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration. The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling). Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN. Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit/32-bit register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event. Figure 55 and Figure 16.3.2 give some examples of the counter behavior when the prescaler ratio is changed on the fly: Figure 55. Counter timing diagram with prescaler division change from 1 to 2 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 DocID022448 Rev 2 299/897 359 General-purpose timers (TIM2 to TIM5, TIM19) RM0313 Figure 56. Counter timing diagram with prescaler division change from 1 to 4 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 16.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An Update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller). The UEV event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register) • The auto-reload shadow register is updated with the preload value (TIMx_ARR) The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. 300/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) Figure 57. Counter timing diagram, internal clock divided by 1 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 58. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 DocID022448 Rev 2 301/897 359 General-purpose timers (TIM2 to TIM5, TIM19) RM0313 Figure 59. Counter timing diagram, internal clock divided by 4 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 60. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 302/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) Figure 61. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )) :ULWHDQHZYDOXHLQ7,0[B$55 069 Figure 62. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) ) ) ) &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU ) $XWRUHORDGVKDGRZ UHJLVWHU ) :ULWHDQHZYDOXHLQ7,0[B$55 DocID022448 Rev 2 069 303/897 359 General-purpose timers (TIM2 to TIM5, TIM19) RM0313 Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. An Update event can be generate at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0. However, the counter restarts from the current auto-reload value, whereas the counter of the prescaler restarts from 0 (but the prescale rate doesn’t change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register). • The auto-reload active register is updated with the preload value (content of the TIMx_ARR register). Note that the auto-reload is updated before the counter is reloaded, so that the next period is the expected one. The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 63. Counter timing diagram, internal clock divided by 1 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHUXQGHUIORZ FQWBXGI 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 304/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) Figure 64. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 65. Counter timing diagram, internal clock divided by 4 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 DocID022448 Rev 2 305/897 359 General-purpose timers (TIM2 to TIM5, TIM19) RM0313 Figure 66. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHUXQGHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 67. Counter timing diagram, Update event when repetition counter is not used &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHUXQGHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )) :ULWHDQHZYDOXHLQ7,0[B$55 069 306/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) – 1, generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. Then it restarts counting from 0. Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to '00'. The Output compare interrupt flag of channels configured in output is set when: the counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3, CMS = "11"). In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated by hardware and gives the current direction of the counter. The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. In this case, the counter restarts counting from 0, as well as the counter of the prescaler. The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter continues counting up and down, based on the current auto-reload value. In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupt when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register). • The auto-reload active register is updated with the preload value (content of the TIMx_ARR register). Note that if the update source is a counter overflow, the autoreload is updated before the counter is reloaded, so that the next period is the expected one (the counter is loaded with the new value). The following figures show some examples of the counter behavior for different clock frequencies. DocID022448 Rev 2 307/897 359 General-purpose timers (TIM2 to TIM5, TIM19) RM0313 Figure 68. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 1. Here, center-aligned mode 1 is used (for more details refer to Section 16.4.1: TIMx control register 1 (TIMx_CR1) on page 337). Figure 69. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 308/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) Figure 70. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 1RWH+HUHFHQWHUBDOLJQHGPRGHRULVXSGDWHGZLWKDQ8,)RQRYHUIORZ 069 1. Center-aligned mode 2 or 3 is used with an UIF on overflow. Figure 71. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHUXQGHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 DocID022448 Rev 2 309/897 359 General-purpose timers (TIM2 to TIM5, TIM19) RM0313 Figure 72. Counter timing diagram, Update event with ARPE=1 (counter underflow) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )' :ULWHDQHZYDOXHLQ7,0[B$55 $XWRUHORDGDFWLYH UHJLVWHU )' 069 Figure 73. Counter timing diagram, Update event with ARPE=1 (counter overflow) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& ) &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )' :ULWHDQHZYDOXHLQ7,0[B$55 $XWRUHORDGDFWLYH )' UHJLVWHU 069 310/897 DocID022448 Rev 2 RM0313 16.3.3 General-purpose timers (TIM2 to TIM5, TIM19) Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin (TIx) • External clock mode2: external trigger input (ETR) • Internal trigger inputs (ITRx): using one timer as prescaler for another timer. Refer to : Using one timer as prescaler for another on page 331 for more details. Internal clock source (CK_INT) If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT. Figure 74 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. Figure 74. Control circuit in normal mode, internal clock divided by 1 ,QWHUQDOFORFN &(1 &17B(1 8* &17B,1,7 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 069 External clock source mode 1 This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at each rising or falling edge on a selected input. DocID022448 Rev 2 311/897 359 General-purpose timers (TIM2 to TIM5, TIM19) RM0313 Figure 75. TI2 external clock connection example 7,0[B60&5 76>@ RU 7,) 7,) ,75[ 7,B(' 7, )LOWHU (GJH GHWHFWRU 7,)B5LVLQJ 7,)B)DOOLQJ 7,)3 7,)3 (75) RU RU [[ 75*, (75) &.B,17 ,&)>@ &&3 7,0[B&&05 7,0[B&&(5 LQWHUQDOFORFN (QFRGHU PRGH ([WHUQDOFORFN PRGH ([WHUQDOFORFN PRGH &.B36& ,QWHUQDOFORFN PRGH (&( 606>@ 7,0[B60&5 069 For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Note: 1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the TIMx_CCMR1 register. 2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. 3. Select rising edge polarity by writing CC2P=0 and CC2NP=0 in the TIMx_CCER register. 4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register. 5. Select TI2 as the input source by writing TS=110 in the TIMx_SMCR register. 6. Enable the counter by writing CEN=1 in the TIMx_CR1 register. When a rising edge occurs on TI2, the counter counts once and the TIF flag is set. The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input. 312/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) Figure 76. Control circuit in external clock mode 1 7, &17B(1 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 7,) :ULWH7,) 069 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. Figure 77 gives an overview of the external trigger input block. Figure 77. External trigger input block RU 7,) 7,) (75 RU RU 75*, (75SLQ 'LYLGHU (753 I'76 )LOWHU GRZQFRXQWHU (75) &.B,17 (73 (736>@ (7)>@ 7,0[B60&5 7,0[B60&5 7,0[B60&5 LQWHUQDOFORFN (QFRGHU PRGH ([WHUQDOFORFN PRGH ([WHUQDOFORFN PRGH &.B36& ,QWHUQDOFORFN PRGH (&( 606>@ 7,0[B60&5 069 For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure: DocID022448 Rev 2 313/897 359 General-purpose timers (TIM2 to TIM5, TIM19) RM0313 1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. 2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register 3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register 4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register. 5. Enable the counter by writing CEN=1 in the TIMx_CR1 register. The counter counts once each 2 ETR rising edges. The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal. Figure 78. Control circuit in external clock mode 2 I &.B,17 &17B(1 (75 (753 (75) &RXQWHUFORFN &.B,17 &.B36& &RXQWHUUHJLVWHU 069 16.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). The following figure gives an overview of one Capture/Compare channel. The input stage samples the corresponding TIx input to generate a filtered signal TIxF. Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS). 314/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) Figure 79. Capture/compare channel (example: channel 1 input stage) 7,)B(' 7RWKHVODYHPRGHFRQWUROOHU 7, 7,)B5LVLQJ )LOWHU 7,) GRZQFRXQWHU I'76 (GJH GHWHFWRU 7,)B)DOOLQJ 7,)3 7,)3 &&3&&13 ,&)>@ 75& 7,0[B&&(5 7,0[B&&05 7,)B5LVLQJ IURPFKDQQHO 7,)B)DOOLQJ IURPFKDQQHO IURPVODYHPRGH FRQWUROOHU ,&36 'LYLGHU ,& &&6>@ ,&36>@ &&( 7,0[B&&05 7,0[B&&(5 069 The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. Figure 80. Capture/compare channel 1 main circuit $3%%XV 5HDG&&5+ 6 5HDG&&5/ KLJK UHDGBLQBSURJUHVV &&6>@ ,&36 ZULWHBLQBSURJUHVV 5 5 ,QSXW PRGH 6 ZULWH&&5+ &DSWXUHFRPSDUHSUHORDGUHJLVWHU FRPSDUHBWUDQVIHU FDSWXUHBWUDQVIHU &&6>@ ORZ LIELW 0&8SHULSKHUDOLQWHUIDFH 2XWSXW PRGH &17!&&5 &RXQWHU &&* &&6>@ 8(9 &RPSDUDWRU &&( &&6>@ 2&3( &DSWXUHFRPSDUHVKDGRZUHJLVWHU &DSWXUH ZULWH&&5/ IURPWLPH EDVHXQLW 2&3( 7,0[B&&05 &17 &&5 7,0[B(*5 069 DocID022448 Rev 2 315/897 359 General-purpose timers (TIM2 to TIM5, TIM19) RM0313 Figure 81. Output stage of capture/compare channel (channel 1) 7,0[B60&5 2&&6 2&5()B&/5 (75) 7RWKHPDVWHU PRGHFRQWUROOHU RFUHIBFOUBLQW &17!&&5 2XWSXW PRGH &17 &&5 FRQWUROOHU 2&5() 2XWSXW HQDEOH FLUFXLW 2& &&3 7,0[B&&(5 2&0>@ &&( 7,0B&&(5 7,0[B&&05 069 The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register. In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter. 16.3.5 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to 0 or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to 0. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure: 316/897 1. Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00, the channel is configured in input and the TIMx_CCR1 register becomes read-only. 2. Program the input filter duration you need with respect to the signal you connect to the timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s imagine that, when toggling, the input signal is not stable during at must 5 internal clock cycles. We must program a filter duration longer than these 5 clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the new level have been DocID022448 Rev 2 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. 3. Select the edge of the active transition on the TI1 channel by writing the CC1P and CC1NP bits to 00 in the TIMx_CCER register (rising edge in this case). 4. Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to 00 in the TIMx_CCMR1 register). 5. Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER register. 6. If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the TIMx_DIER register. When an input capture occurs: • The TIMx_CCR1 register gets the value of the counter on the active transition. • CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared. • An interrupt is generated depending on the CC1IE bit. • A DMA request is generated depending on the CC1DE bit. In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data. Note: IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register. 16.3.6 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. • One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode. For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): DocID022448 Rev 2 317/897 359 General-purpose timers (TIM2 to TIM5, TIM19) RM0313 1. Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected). 2. Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P to ‘0’ and the CC1NP bit to ‘0’ (active on rising edge). 3. Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (TI1 selected). 4. Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P bit to ‘1’ and the CC2NP bit to ’0’(active on falling edge). 5. Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register (TI1FP1 selected). 6. Configure the slave mode controller in reset mode: write the SMS bits to 100 in the TIMx_SMCR register. 7. Enable the captures: write the CC1E and CC2E bits to ‘1 in the TIMx_CCER register. Figure 82. PWM input mode timing 7, 7,0[B&17 7,0[B&&5 7,0[B&&5 ,&FDSWXUH ,&FDSWXUH UHVHWFRXQWHU ,&FDSWXUH SXOVHZLGWK PHDVXUHPHQW ,&FDSWXUH SHULRG PHDVXUHPHQW DL 16.3.7 Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (OCxREF/OCx) to its active level, you just need to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCxREF is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. e.g.: CCxP=0 (OCx active high) => OCx is forced to high level. OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx register. Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the Output Compare Mode section. 318/897 DocID022448 Rev 2 RM0313 16.3.8 General-purpose timers (TIM2 to TIM5, TIM19) Output compare mode This function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function: • Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match. • Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register). • Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the TIMx_DIER register). • Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request selection). The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register. In output compare mode, the update event UEV has no effect on OCxREF and OCx output. The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One-pulse mode). Procedure: 1. Select the counter clock (internal, external, prescaler). 2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers. 3. Set the CCxIE and/or CCxDE bits if an interrupt and/or a DMA request is to be generated. 4. Select the output mode. For example, you must write OCxM=011, OCxPE=0, CCxP=0 and CCxE=1 to toggle OCx output pin when CNT matches CCRx, CCRx preload is not used, OCx is enabled and active high. 5. Enable the counter by setting the CEN bit in the TIMx_CR1 register. The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 83. DocID022448 Rev 2 319/897 359 General-purpose timers (TIM2 to TIM5, TIM19) RM0313 Figure 83. Output compare mode, toggle on OC1. :ULWH%KLQWKH&&5UHJLVWHU 7,0B&17 % $ % % $ 7,0B&&5 % RFUHI 2& 0DWFKGHWHFWHGRQ&&5 ,QWHUUXSWJHQHUDWHGLIHQDEOHG 069 16.3.9 PWM mode Pulse width modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register. The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing 110 (PWM mode 1) or ‘111 (PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. You must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register. As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register. OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by the CCxE bit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more details. In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CCRx≤TIMx_CNT or TIMx_CNT≤TIMx_CCRx (depending on the direction of the counter). However, to comply with the OCREF_CLR functionality (OCREF can be cleared by an external event through the ETR signal until the next PWM period), the OCREF signal is asserted only: • When the result of the comparison changes, or • When the output compare mode (OCxM bits in TIMx_CCMRx register) switches from the “frozen” configuration (no comparison, OCxM=‘000) to one of the PWM modes (OCxM=‘110 or ‘111). This forces the PWM by software while the timer is running. 320/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register. PWM edge-aligned mode Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Section : Upcounting mode on page 300. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <TIMx_CCRx else it becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1. If the compare value is 0 then OCxREF is held at ‘0. Figure 84 shows some edge-aligned PWM waveforms in an example where TIMx_ARR=8. Figure 84. Edge-aligned PWM waveforms (ARR=8) &&5[ &RXQWHUUHJLVWHU 2&;5() &&[,) 2&;5() &&5[ &&[,) 2&;5() µ¶ &&5[! &&[,) 2&;5() µ¶ &&5[ &&[,) 069 Downcounting configuration Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to Section : Downcounting mode on page 304. In PWM mode 1, the reference signal OCxREF is low as long as TIMx_CNT>TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, then OCxREF is held at ‘1. 0% PWM is not possible in this mode. PWM center-aligned mode Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from ‘00 (all the remaining configurations having the same effect on the OCxREF/OCx signals). DocID022448 Rev 2 321/897 359 General-purpose timers (TIM2 to TIM5, TIM19) RM0313 The compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to Section : Center-aligned mode (up/down counting) on page 307. Figure 85 shows some center-aligned PWM waveforms in an example where: • TIMx_ARR=8, • PWM mode is the PWM mode 1, • The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register. Figure 85. Center-aligned PWM waveforms (ARR=8) &RXQWHUUHJLVWHU 2&[5() &&5[ &06 &06 &06 &&[,) 2&[5() &&5[ &06 RU &&[,) 2&[5() µ¶ &&5[ &&[,) 2&[5() &&5[! µ¶ &06 &06 &06 &&[,) 2&[5() &&5[ &&[,) &06 &06 &06 µ¶ &06 &06 &06 $,E Hints on using center-aligned mode: • 322/897 When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit DocID022448 Rev 2 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. • • – The direction is not updated if you write a value in the counter that is greater than the auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter was counting up, it continues to count up. – The direction is updated if you write 0 or write the TIMx_ARR value in the counter but no Update Event UEV is generated. The safest way to use center-aligned mode is to generate an update by software (setting the UG bit in the TIMx_EGR register) just before starting the counter and not to write the counter while it is running. One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. You select One-pulse mode by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV. A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be: • In upcounting: CNT<CCRx≤ARR (in particular, 0<CCRx), • In downcounting: CNT>CCRx. Figure 86. Example of one-pulse mode. 7, 2&5() 2& 7,0B$55 &RXQWHU 16.3.10 Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results. In particular: 7,0B&&5 W'(/$< W38/6( W 069 DocID022448 Rev 2 323/897 359 General-purpose timers (TIM2 to TIM5, TIM19) RM0313 For example you may want to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin. Let’s use TI2FP2 as trigger 1: • Map TI2FP2 on TI2 by writing IC2S=01 in the TIMx_CCMR1 register. • TI2FP2 must detect a rising edge, write CC2P=0 and CC2NP=’0’ in the TIMx_CCER register. • Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=110 in the TIMx_SMCR register. • TI2FP2 is used to start the counter by writing SMS to ‘110 in the TIMx_SMCR register (trigger mode). The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The tDELAY is defined by the value written in the TIMx_CCR1 register. • The tPULSE is defined by the difference between the auto-reload value and the compare value (TIMx_ARR - TIMx_CCR1). • Let’s say you want to build a waveform with a transition from ‘0 to ‘1 when a compare match occurs and a transition from ‘1 to ‘0 when the counter reaches the auto-reload value. To do this you enable PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1 register. You can optionally enable the preload registers by writing OC1PE=1 in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to write the compare value in the TIMx_CCR1 register, the auto-reload value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2. CC1P is written to ‘0 in this example. In our example, the DIR and CMS bits in the TIMx_CR1 register should be low. You only want 1 pulse (Single mode), so you write '1 in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the Repetitive Mode is selected. Particular case: OCx fast enable: In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay tDELAY min we can get. If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the TIMx_CCMRx register. Then OCxRef (and OCx) is forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode. 16.3.11 324/897 Clearing the OCxREF signal on an external event 1. The external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR register are cleared to 00. 2. The external clock mode 2 must be disabled: bit ECE in the TIMx_SMCR register is cleared to 0. 3. The external trigger polarity (ETP) and the external trigger filter (ETF) can be configured according to the application’s needs. DocID022448 Rev 2 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) Figure 87 shows the behavior of the OCxREF signal when the ETRF input becomes high, for both values of the OCxCE enable bit. In this example, the timer TIMx is programmed in PWM mode. Figure 87. Clearing TIMx OCxREF &&5[ &RXQWHU&17 (75) 2&[5() 2&[&( µ¶ 2&[5() 2&[&( µ¶ 2&[5()B&/5 EHFRPHVKLJK 2&[5()B&/5 VWLOOKLJK 069 1. In case of a PWM with a 100% duty cycle (if CCRx>ARR), OCxREF is enabled again at the next counter overflow. 16.3.12 Encoder interface mode To select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if it is counting on both TI1 and TI2 edges. Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER register. CC1NP and CC2NP must be kept cleared. When needed, you can program the input filter as well. The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to Table 44. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2 after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted, TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in TIMx_CR1 register written to ‘1). The sequence of transitions of the two inputs is evaluated and generates count pulses as well as the direction signal. Depending on the sequence the counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever the counter is counting on TI1 only, TI2 only or both TI1 and TI2. Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value in the TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So you must DocID022448 Rev 2 325/897 359 General-purpose timers (TIM2 to TIM5, TIM19) RM0313 configure TIMx_ARR before starting. In the same way, the capture, compare, prescaler, trigger output features continue to work as normal. In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s position. The count direction correspond to the rotation direction of the connected sensor. The table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the same time. Table 44. Counting direction versus encoder signals Level on opposite signal (TI1FP1 for TI2, TI2FP2 for TI1) Rising Falling Rising Falling Counting on TI1 only High Down Up No Count No Count Low Up Down No Count No Count Counting on TI2 only High No Count No Count Up Down Low No Count No Count Down Up Counting on TI1 and TI2 High Down Up Up Down Low Up Down Down Up Active edge TI1FP1 signal TI2FP2 signal An external incremental encoder can be connected directly to the MCU without external interface logic. However, comparators are normally be used to convert the encoder’s differential outputs to digital signals. This greatly increases noise immunity. The third encoder output which indicate the mechanical zero position, may be connected to an external interrupt input and trigger a counter reset. Figure 88 gives an example of counter operation, showing count signal generation and direction control. It also shows how input jitter is compensated where both edges are selected. This might occur if the sensor is positioned near to one of the switching points. For this example we assume that the configuration is the following: 326/897 • CC1S= 01 (TIMx_CCMR1 register, TI1FP1 mapped on TI1) • CC2S= 01 (TIMx_CCMR2 register, TI2FP2 mapped on TI2) • CC1P=0, CC1NP = ‘0’ (TIMx_CCER register, TI1FP1 noninverted, TI1FP1=TI1) • CC2P=0, CC2NP = ‘0’ (TIMx_CCER register, TI2FP2 noninverted, TI2FP2=TI2) • SMS= 011 (TIMx_SMCR register, both inputs are active on both rising and falling edges) • CEN= 1 (TIMx_CR1 register, Counter is enabled) DocID022448 Rev 2 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) Figure 88. Example of counter operation in encoder interface mode IRUZDUG MLWWHU EDFNZDUG MLWWHU IRUZDUG 7, 7, &RXQWHU XS GRZQ XS 069 Figure 89 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=1). Figure 89. Example of encoder interface mode with TI1FP1 polarity inverted IRUZDUG MLWWHU EDFNZDUG MLWWHU IRUZDUG 7, 7, &RXQWHU GRZQ XS GRZQ 069 The timer, when configured in Encoder Interface mode provides information on the sensor’s current position. You can obtain dynamic information (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode. The output of the encoder which indicates the mechanical zero can be used for this purpose. Depending on the time between two events, the counter can also be read at regular times. You can do this by latching the counter value into a third input capture register if available (then the capture signal must be periodic and can be generated by another timer). when available, it is also possible to read its value through a DMA request generated by a Real-Time clock. 16.3.13 Timer input XOR function The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3. The XOR output can be used with all the timer input functions such as trigger or input capture. DocID022448 Rev 2 327/897 359 General-purpose timers (TIM2 to TIM5, TIM19) 16.3.14 RM0313 Timers and external trigger synchronization The TIMx Timers can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated. In the following example, the upcounter is cleared in response to a rising edge on TI1 input: • Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect rising edges only). • Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. • Start the counter by writing CEN=1 in the TIMx_CR1 register. The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register). The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input. Figure 90. Control circuit in reset mode 7, 8* &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) 069 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: 328/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) 1. Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write CC1P=1 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect low level only). 2. Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. 3. Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the counter doesn’t start if CEN=0, whatever is the trigger input level). The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops. The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input. Figure 91. Control circuit in gated mode 7, FQWBHQ &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) :ULWH7,) 069 1. The configuration “CCxP=CCxNP=1” (detection of both rising and falling edges) does not have any effect in gated mode because gated mode acts on a level and not on an edge. Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: 1. Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. CC2S bits are selecting the input capture source only, CC2S=01 in TIMx_CCMR1 register. Write CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low level only). 2. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI2 as the input source by writing TS=110 in TIMx_SMCR register. DocID022448 Rev 2 329/897 359 General-purpose timers (TIM2 to TIM5, TIM19) RM0313 When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set. The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input. Figure 92. Control circuit in trigger mode 7, FQWBHQ &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) 069 Slave mode: External Clock mode 2 + trigger mode The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock input, and another input can be selected as trigger input when operating in reset mode, gated mode or trigger mode. It is recommended not to select ETR as TRGI through the TS bits of TIMx_SMCR register. In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs: 1. 2. 3. Configure the external trigger input circuit by programming the TIMx_SMCR register as follows: – ETF = 0000: no filter – ETPS=00: prescaler disabled – ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock mode 2. Configure the channel 1 as follows, to detect rising edges on TI: – IC1F=0000: no filter. – The capture prescaler is not used for triggering and does not need to be configured. – CC1S=01in TIMx_CCMR1 register to select only the input capture source – CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect rising edge only). Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on ETR rising edges. The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization circuit on ETRP input. 330/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) Figure 93. Control circuit in external clock mode 2 + trigger mode 7, &(1&17B(1 (75 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 7,) 069 16.3.15 Timer synchronization The TIMx timers are linked together internally for timer synchronization or chaining. When one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of another Timer configured in Slave Mode. Figure 94: Master/Slave timer example presents an overview of the trigger selection and the master mode selection blocks. Using one timer as prescaler for another Figure 94. Master/Slave timer example 7,0[ 7,0\ &ORFN 76 006 606 8(9 3UHVFDOHU &RXQWHU 0DVWHU 75*2 PRGH FRQWURO ,75 6ODYH &.B36& PRGH FRQWURO 3UHVFDOHU &RXQWHU ,QSXW WULJJHU VHOHFWLRQ 069 For example, you can configure Timer x to act as a prescaler for Timer y. Refer to Figure 94. To do this: DocID022448 Rev 2 331/897 359 General-purpose timers (TIM2 to TIM5, TIM19) Note: RM0313 1. Configure Timer x in master mode so that it outputs a periodic trigger signal on each update event UEV. If you write MMS=010 in the TIMx_CR2 register, a rising edge is output on TRGO1 each time an update event is generated. 2. To connect the TRGO1 output of Timer x to Timer y, Timer y must be configured in slave mode using ITR1 as internal trigger. You select this through the TS bits in the TIMy_SMCR register (writing TS=000). 3. Then you put the slave mode controller in external clock mode 1 (write SMS=111 in the TIMy_SMCR register). This causes Timer y to be clocked by the rising edge of the periodic Timer x trigger signal (which correspond to the timer x counter overflow). 4. Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1 register). If OCx is selected on Timer x as trigger output (MMS=1xx), its rising edge is used to clock the counter of timer y. Using one timer to enable another timer In this example, we control the enable of Timer y with the output compare 1 of Timer x. Refer to Figure 94 for connections. Timer y counts on the divided internal clock only when OC1REF of Timer x is high. Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT (fCK_CNT = fCK_INT/3). Note: 1. Configure Timer x master mode to send its Output Compare 1 Reference (OC1REF) signal as trigger output (MMS=100 in the TIMx_CR2 register). 2. Configure the Timer x OC1REF waveform (TIMx_CCMR1 register). 3. Configure Timer y to get the input trigger from Timer x (TS=000 in the TIMy_SMCR register). 4. Configure Timer y in gated mode (SMS=101 in TIMy_SMCR register). 5. Enable Timer y by writing ‘1 in the CEN bit (TIMy_CR1 register). 6. Start Timer x by writing ‘1 in the CEN bit (TIMx_CR1 register). The counter 2 clock is not synchronized with counter 1, this mode only affects the Timer y counter enable signal. Figure 95. Gating timer y with OC1REF of timer x &.B,17 7,0(5[2&5() 7,0(5[&17 )& 7,0(5\&17 )' )( )) 7,0(5\7,) :ULWH7,) 069 In the example in Figure 95, the Timer y counter and prescaler are not initialized before being started. So they start counting from their current value. It is possible to start from a given value by resetting both timers before starting Timer x. You can then write any value 332/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) you want in the timer counters. The timers can easily be reset by software using the UG bit in the TIMx_EGR registers. In the next example, we synchronize Timer x and Timer y. Timer x is the master and starts from 0. Timer y is the slave and starts from 0xE7. The prescaler ratio is the same for both timers. Timer y stops when Timer x is disabled by writing ‘0 to the CEN bit in the TIMy_CR1 register: 1. Configure Timer x master mode to send its Output Compare 1 Reference (OC1REF) signal as trigger output (MMS=100 in the TIMx_CR2 register). 2. Configure the Timer x OC1REF waveform (TIMx_CCMR1 register). 3. Configure Timer y to get the input trigger from Timer x (TS=000 in the TIMy_SMCR register). 4. Configure Timer y in gated mode (SMS=101 in TIMy_SMCR register). 5. Reset Timer x by writing ‘1 in UG bit (TIMx_EGR register). 6. Reset Timer y by writing ‘1 in UG bit (TIMy_EGR register). 7. Initialize Timer y to 0xE7 by writing ‘0xE7’ in the timer y counter (TIMy_CNTL). 8. Enable Timer y by writing ‘1 in the CEN bit (TIMy_CR1 register). 9. Start Timer x by writing ‘1 in the CEN bit (TIMx_CR1 register). 10. Stop Timer x by writing ‘0 in the CEN bit (TIMx_CR1 register). Figure 96. Gating timer y with Enable of timer x &.B,17 7,0(5[&(1 &17B(1 7,0(5[&17B,1,7 7,0(5[&17 7,0(5\&17 $% ( ( ( 7,0(5\&17B,1,7 7,0(5\ZULWH&17 7,0(5\7,) :ULWH7,) 069 Using one timer to start another timer In this example, we set the enable of Timer y with the update event of Timer x. Refer to Figure 94 for connections. Timer y starts counting from its current value (which can be nonzero) on the divided internal clock as soon as the update event is generated by Timer x. When Timer y receives the trigger signal its CEN bit is automatically set and the counter counts until we write ‘0 to the CEN bit in the TIM2_CR1 register. Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT (fCK_CNT = fCK_INT/3). DocID022448 Rev 2 333/897 359 General-purpose timers (TIM2 to TIM5, TIM19) RM0313 1. Configure Timer x master mode to send its Update Event (UEV) as trigger output (MMS=010 in the TIMx_CR2 register). 2. Configure the Timer x period (TIMx_ARR registers). 3. Configure Timer y to get the input trigger from Timer x (TS=000 in the TIM2_SMCR register). 4. Configure Timer y in trigger mode (SMS=110 in TIM2_SMCR register). 5. Start Timer x by writing ‘1 in the CEN bit (TIMx_CR1 register). Figure 97. Triggering timer y with update of timer x &.B,17 7,0(5[8(9 7,0(5[&17 )' )( )) 7,0(5\&17 7,0(5\&(1 &17B(1 7,0(5\7,) :ULWH7,) 069 As in the previous example, you can initialize both counters before starting counting. Figure 98 shows the behavior with the same configuration as in Figure 97 but in trigger mode instead of gated mode (SMS=110 in the TIMy_SMCR register). Figure 98. Triggering timer y with Enable of timer x &.B,17 7,0(5[&(1 &17B(1 7,0(5[&17B,1,7 7,0(5[&17 7,0(5\&17 &' ( ( ( ($ 7,0(5\&17B,1,7 7,0(5\ ZULWH&17 7,0(5\7,) :ULWH7,) 069 334/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) Using one timer as prescaler for another timer For example, you can configure Timer x to act as a prescaler for Timer y. Refer to Figure 94 for connections. To do this: 1. Configure Timer x master mode to send its Update Event (UEV) as trigger output (MMS=010 in the TIMx_CR2 register). then it outputs a periodic signal on each counter overflow. 2. Configure the Timer x period (TIMx_ARR registers). 3. Configure Timer y to get the input trigger from Timer x (TS=000 in the TIM2_SMCR register). 4. Configure Timer y in external clock mode 1 (SMS=111 in TIM2_SMCR register). 5. Start Timer y by writing ‘1 in the CEN bit (TIMy_CR1 register). 6. Start Timer x by writing ‘1 in the CEN bit (TIMx_CR1 register). Starting 2 timers synchronously in response to an external trigger In this example, we set the enable of timer x when its TI1 input rises, and the enable of Timer y with the enable of Timer x. Refer to Figure 94 for connections. To ensure the counters are aligned, Timer x must be configured in Master/Slave mode (slave with respect to TI1, master with respect to Timer y): 1. Configure Timer x master mode to send its Enable as trigger output (MMS=001 in the TIMx_CR2 register). 2. Configure Timer x slave mode to get the input trigger from TI1 (TS=100 in the TIMx_SMCR register). 3. Configure Timer x in trigger mode (SMS=110 in the TIMx_SMCR register). 4. Configure the Timer x in Master/Slave mode by writing MSM=1 (TIMx_SMCR register). 5. Configure Timer y to get the input trigger from Timer x (TS=000 in the TIM2_SMCR register). 6. Configure Timer y in trigger mode (SMS=110 in the TIM2_SMCR register). When a rising edge occurs on TI1 (Timer x), both counters starts counting synchronously on the internal clock and both TIF flags are set. Note: In this example both timers are initialized before starting (by setting their respective UG bits). Both counters starts from 0, but you can easily insert an offset between them by writing any of the counter registers (TIMx_CNT). You can see that the master/slave mode insert a delay between CNT_EN and CK_PSC on timer x. DocID022448 Rev 2 335/897 359 General-purpose timers (TIM2 to TIM5, TIM19) RM0313 Figure 99. Triggering timer x and y with timer x TI1 input &.B,17 7,0(5[7, 7,0(5[&(1 &17B(1 7,0(5[&.B36& 7,0(5[&17 7,0(5[7,) 7,0(5\&(1 &17B(1 7,0(5\&.B36& 7,0(5\&17 7,0(5\7,) 069 16.3.16 Debug mode When the microcontroller enters debug mode (Cortex-M4 with FPU core - halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBGMCU module. For more details, refer to Section 31.16.2: Debug support for timers, watchdog, bxCAN and I2C. 336/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) 16.4 TIM2 to TIM5/TIM19 registers Refer to Section 1.1 on page 36 for a list of abbreviations used in register descriptions. The 32-bit peripheral registers have to be written by words (32 bits). All other peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 16.4.1 TIMx control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 15 14 13 12 Res. 11 10 9 8 CKD[1:0] rw 7 6 ARPE rw rw 5 CMS rw rw 4 3 2 1 0 DIR OPM URS UDIS CEN rw rw rw rw rw Bits 15:10 Reserved, must be kept at reset value. Bits 9:8 CKD: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx), 00: tDTS = tCK_INT 01: tDTS = 2 × tCK_INT 10: tDTS = 4 × tCK_INT 11: Reserved Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered 1: TIMx_ARR register is buffered Bits 6:5 CMS: Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down. Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) Bit 4 DIR: Direction 0: Counter used as upcounter 1: Counter used as downcounter Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. Bit 3 OPM: One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) DocID022448 Rev 2 337/897 359 General-purpose timers (TIM2 to TIM5, TIM19) RM0313 Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled. Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. 338/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) 16.4.2 TIMx control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 15 14 13 12 11 Res. 10 9 8 7 6 TI1S rw 5 4 MMS[2:0] rw rw 3 CCDS rw rw 2 1 0 Res. Bits 15:8 Reserved, must be kept at reset value. Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) Bits 6:4 MMS: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). 010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO) 100: Compare - OC1REF signal is used as trigger output (TRGO) 101: Compare - OC2REF signal is used as trigger output (TRGO) 110: Compare - OC3REF signal is used as trigger output (TRGO) 111: Compare - OC4REF signal is used as trigger output (TRGO) Bit 3 CCDS: Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs Bits 2:0 Reserved, must be kept at reset value. DocID022448 Rev 2 339/897 359 General-purpose timers (TIM2 to TIM5, TIM19) 16.4.3 RM0313 TIMx slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 15 14 ETP ECE 13 rw rw 12 11 ETPS[1:0] rw rw 10 9 8 ETF[3:0] rw rw 7 6 MSM rw rw rw 5 4 TS[2:0] rw rw rw 3 Res. 2 1 0 SMS[2:0] rw rw rw Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is noninverted, active at high level or rising edge 1: ETR is inverted, active at low level or falling edge Bit 14 ECE: External clock enable This bit enables External clock mode 2. 0: External clock mode 2 disabled 1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=111). 2: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 111). 3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. Bits 13:12 ETPS: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 00: Prescaler OFF 01: ETRP frequency divided by 2 10: ETRP frequency divided by 4 11: ETRP frequency divided by 8 Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS 0001: fSAMPLING=fCK_INT, N=2 0010: fSAMPLING=fCK_INT, N=4 0011: fSAMPLING=fCK_INT, N=8 0100: fSAMPLING=fDTS/2, N=6 0101: fSAMPLING=fDTS/2, N=8 0110: fSAMPLING=fDTS/4, N=6 0111: fSAMPLING=fDTS/4, N=8 1000: fSAMPLING=fDTS/8, N=6 1001: fSAMPLING=fDTS/8, N=8 1010: fSAMPLING=fDTS/16, N=5 1011: fSAMPLING=fDTS/16, N=6 1100: fSAMPLING=fDTS/16, N=8 1101: fSAMPLING=fDTS/32, N=5 1110: fSAMPLING=fDTS/32, N=6 1111: fSAMPLING=fDTS/32, N=8 340/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) Bit 7 MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. Bits 6:4 TS: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0). 001: Internal Trigger 1 (ITR1). 010: Internal Trigger 2 (ITR2). 011: Internal Trigger 3 (ITR3). 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2) 111: External Trigger input (ETRF) See Table 2: TIM2 internal trigger connection on page 403 for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. Bit 3 Reserved, must be kept at ‘1’. Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. 000: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. 001: Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. 010: Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. 011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. DocID022448 Rev 2 341/897 359 General-purpose timers (TIM2 to TIM5, TIM19) RM0313 Table 45. TIMx internal trigger connection 16.4.4 Slave TIM ITR0 (TS = 000) ITR1 (TS = 001) ITR2 (TS = 010) ITR3 (TS = 011) TIM2 TIM19 TIM15 TIM3 TIM14 TIM3 TIM19 TIM2 TIM5 TIM14 TIM4 TIM19 TIM2 TIM3 TIM15 TIM5 TIM2 TIM3 TIM4 TIM15 TIM19 TIM2 TIM3 TIM15 TIM16 TIMx DMA/Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 15 Res. 14 TDE rw 13 Res Bit 15 12 11 10 9 8 CC4DE CC3DE CC2DE CC1DE rw rw rw rw UDE rw 7 Res. 6 TIE rw Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled. 1: Trigger DMA request enabled. Bit 13 Reserved, always read as 0 Bit 12 CC4DE: Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled. 1: CC4 DMA request enabled. Bit 11 CC3DE: Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled. 1: CC3 DMA request enabled. Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled. 1: CC2 DMA request enabled. Bit 9 CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled. 1: CC1 DMA request enabled. Bit 8 UDE: Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled. Bit 7 Reserved, must be kept at reset value. Bit 6 TIE: Trigger interrupt enable 0: Trigger interrupt disabled. 1: Trigger interrupt enabled. Bit 5 342/897 Reserved, must be kept at reset value. DocID022448 Rev 2 5 Res 4 3 2 1 0 CC4IE CC3IE CC2IE CC1IE UIE rw rw rw rw rw RM0313 General-purpose timers (TIM2 to TIM5, TIM19) Bit 4 CC4IE: Capture/Compare 4 interrupt enable 0: CC4 interrupt disabled. 1: CC4 interrupt enabled. Bit 3 CC3IE: Capture/Compare 3 interrupt enable 0: CC3 interrupt disabled 1: CC3 interrupt enabled Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled 1: CC2 interrupt enabled Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled 16.4.5 TIMx status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 15 14 13 12 11 10 9 8 CC4OF CC3OF CC2OF CC1OF Res. rc_w0 Bit 15:13 rc_w0 rc_w0 rc_w0 7 Res. 6 TIF rc_w0 5 Res. 4 3 2 1 0 CC4IF CC3IF CC2IF CC1IF UIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Reserved, must be kept at reset value. Bit 12 CC4OF: Capture/Compare 4 overcapture flag refer to CC1OF description Bit 11 CC3OF: Capture/Compare 3 overcapture flag refer to CC1OF description Bit 10 CC2OF: Capture/compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0. 0: No overcapture has been detected 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set Bits 8:7 Reserved, must be kept at reset value. Bit 6 TIF: Trigger interrupt flag This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 0: No trigger event occurred 1: Trigger interrupt pending Bit 5 Reserved, must be kept at reset value. DocID022448 Rev 2 343/897 359 General-purpose timers (TIM2 to TIM5, TIM19) RM0313 Bit 4 CC4IF: Capture/Compare 4 interrupt flag refer to CC1IF description Bit 3 CC3IF: Capture/Compare 3 interrupt flag refer to CC1IF description Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). It is cleared by software. 0: No match 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in upcounting and up/down-counting modes) or underflow (in downcounting mode) If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1 register. 0: No input capture occurred 1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected on IC1 which matches the selected polarity) Bit 0 UIF: Update interrupt flag ″ This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: ″ At overflow or underflow (for TIM2 to TIM5 and TIM19) and if UDIS=0 in the TIMx_CR1 register. ″ When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register. 344/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) 16.4.6 TIMx event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 TG Res. w 5 Res. 4 3 2 1 0 CC4G CC3G CC2G CC1G UG w w w w w Bits 15:7 Reserved, must be kept at reset value. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. Bit 5 Reserved, must be kept at reset value. Bit 4 CC4G: Capture/compare 4 generation refer to CC1G description Bit 3 CC3G: Capture/compare 3 generation refer to CC1G description Bit 2 CC2G: Capture/compare 2 generation refer to CC1G description Bit 1 CC1G: Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting). DocID022448 Rev 2 345/897 359 General-purpose timers (TIM2 to TIM5, TIM19) 16.4.7 RM0313 TIMx capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So you must take care that the same bit can have a different meaning for the input stage and for the output stage. 15 14 OC2CE 13 12 OC2M[2:0] IC2F[3:0] rw rw rw 11 10 OC2PE OC2FE IC2PSC[1:0] rw rw rw 9 8 CC2S[1:0] rw 7 6 OC1CE rw 5 4 OC1M[2:0] IC1F[3:0] rw rw rw 3 2 OC1PE OC1FE IC1PSC[1:0] rw rw rw 1 0 CC1S[1:0] rw rw Output compare mode Bit 15 OC2CE: Output compare 2 clear enable Bits 14:12 OC2M[2:0]: Output compare 2 mode Bit 11 OC2PE: Output compare 2 preload enable Bit 10 OC2FE: Output compare 2 fast enable Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). Bit 7 OC1CE: Output compare 1 clear enable OC1CE: Output Compare 1 Clear Enable 0: OC1Ref is not affected by the ETRF input 1: OC1Ref is cleared as soon as a High level is detected on ETRF input 346/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. 000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base). 001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 100: Force inactive level - OC1REF is forced low. 101: Force active level - OC1REF is forced high. 110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=1). 111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output). 2: In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Bit 3 OC1PE: Output compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output). 2: The PWM mode can be used without validating the preload register only in onepulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. Bit 2 OC1FE: Output compare 1 fast enable This bit is used to accelerate the effect of an event on the trigger in input on the CC output. 0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. 1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output. 01: CC1 channel is configured as input, IC1 is mapped on TI1. 10: CC1 channel is configured as input, IC1 is mapped on TI2. 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). DocID022448 Rev 2 347/897 359 General-purpose timers (TIM2 to TIM5, TIM19) RM0313 Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output. 01: CC2 channel is configured as input, IC2 is mapped on TI2. 10: CC2 channel is configured as input, IC2 is mapped on TI1. 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). Bits 7:4 IC1F: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS1000: fSAMPLING=fDTS/8, N=6 0001: fSAMPLING=fCK_INT, N=21001: fSAMPLING=fDTS/8, N=8 0010: fSAMPLING=fCK_INT, N=41010: fSAMPLING=fDTS/16, N=5 0011: fSAMPLING=fCK_INT, N=81011: fSAMPLING=fDTS/16, N=6 0100: fSAMPLING=fDTS/2, N=61100: fSAMPLING=fDTS/16, N=8 0101: fSAMPLING=fDTS/2, N=81101: fSAMPLING=fDTS/32, N=5 0110: fSAMPLING=fDTS/4, N=61110: fSAMPLING=fDTS/32, N=6 0111: fSAMPLING=fDTS/4, N=81111: fSAMPLING=fDTS/32, N=8 Note: In current silicon revision, fDTS is replaced in the formula by CK_INT when ICxF[3:0]= 1, 2 or 3. Bits 3:2 IC1PSC: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=0 (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 348/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) 16.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. 15 14 OC4CE 13 12 OC4M[2:0] IC4F[3:0] rw rw rw 11 10 OC4PE OC4FE IC4PSC[1:0] rw rw rw 9 8 CC4S[1:0] rw 7 6 OC3CE rw 5 4 OC3M[2:0] IC3F[3:0] rw rw rw 3 2 OC3PE OC3FE IC3PSC[1:0] rw rw rw 1 0 CC3S[1:0] rw rw Output compare mode Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode Bit 11 OC4PE: Output compare 4 preload enable Bit 10 OC4FE: Output compare 4 fast enable Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). Bit 7 OC3CE: Output compare 3 clear enable Bits 6:4 OC3M: Output compare 3 mode Bit 3 OC3PE: Output compare 3 preload enable Bit 2 OC3FE: Output compare 3 fast enable Bits 1:0 CC3S: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). DocID022448 Rev 2 349/897 359 General-purpose timers (TIM2 to TIM5, TIM19) RM0313 Input capture mode Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). Bits 7:4 IC3F: Input capture 3 filter Bits 3:2 IC3PSC: Input capture 3 prescaler Bits 1:0 CC3S: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). 16.4.9 TIMx capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 15 CC4NP rw 14 Res. 13 12 11 CC4P CC4E CC3NP rw rw rw 10 Res. 9 8 7 CC3P CC3E CC2NP rw rw rw 6 Res. Bit 15 CC4NP: Capture/Compare 4 output Polarity. Refer to CC1NP description Bit 14 Reserved, must be kept at reset value. Bit 13 CC4P: Capture/Compare 4 output Polarity. refer to CC1P description Bit 12 CC4E: Capture/Compare 4 output enable. refer to CC1E description Bit 11 CC3NP: Capture/Compare 3 output Polarity. refer to CC1NP description Bit 10 Reserved, must be kept at reset value. Bit 9 CC3P: Capture/Compare 3 output Polarity. refer to CC1P description Bit 8 CC3E: Capture/Compare 3 output enable. refer to CC1E description 350/897 DocID022448 Rev 2 5 4 3 CC2P CC2E CC1NP rw rw rw 2 Res. 1 0 CC1P CC1E rw rw RM0313 General-purpose timers (TIM2 to TIM5, TIM19) Bit 7 CC2NP: Capture/Compare 2 output Polarity. refer to CC1NP description Bit 6 Reserved, must be kept at reset value. Bit 5 CC2P: Capture/Compare 2 output Polarity. refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable. refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 output Polarity. CC1 channel configured as output: CC1NP must be kept cleared in this case. CC1 channel configured as input: This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P description. Bit 2 Reserved, must be kept at reset value. Bit 1 CC1P: Capture/Compare 1 output Polarity. CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations. 00: noninverted/rising edge Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode). 01: inverted/falling edge Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is inverted (trigger in gated mode, encoder mode). 10: reserved, do not use this configuration. 11: noninverted/both edges Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This configuration must not be used for encoder mode. Bit 0 CC1E: Capture/Compare 1 output enable. CC1 channel configured as output: 0: Off - OC1 is not active 1: On - OC1 signal is output on the corresponding output pin CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not. 0: Capture disabled 1: Capture enabled Table 46. Output control bit for standard OCx channels CCxE bit OCx output state 0 Output Disabled (OCx=0, OCx_EN=0) 1 OCx=OCxREF + Polarity, OCx_EN=1 DocID022448 Rev 2 351/897 359 General-purpose timers (TIM2 to TIM5, TIM19) RM0313 Note: The state of the external I/O pins connected to the standard OCx channels depends on the OCx channel state and the GPIO registers. 16.4.10 TIMx counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CNT[31:16] (depending on timers) rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CNT[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 CNT[31:16]: High counter value (on TIM2 and TIM5). Bits 15:0 CNT[15:0]: Low counter value 16.4.11 TIMx prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw PSC[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event. 16.4.12 TIMx auto-reload register (TIMx_ARR) Address offset: 0x2C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ARR[31:16] (depending on timers) rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw ARR[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 ARR[31:16]: High auto-reload value (on TIM2 and TIM5). Bits 15:0 352/897 ARR[15:0]: Low Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 16.3.1: Time-base unit on page 298 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. DocID022448 Rev 2 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) 16.4.13 TIMx capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CCR1[31:16] (depending on timers) rw rw rw rw rw rw rw 15 14 13 12 11 10 9 rw rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CCR1[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 CCR1[31:16]: High Capture/Compare 1 value (on TIM2 and TIM5). Bits 15:0 CCR1[15:0]: Low Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). 16.4.14 TIMx capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 0000 31 30 29 28 27 26 25 rw rw rw rw rw rw rw 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 CCR2[31:16] (depending on timers) rw rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CCR2[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 CCR2[31:16]: High Capture/Compare 2 value (on TIM2 and TIM5). Bits 15:0 CCR2[15:0]: Low Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). DocID022448 Rev 2 353/897 359 General-purpose timers (TIM2 to TIM5, TIM19) 16.4.15 RM0313 TIMx capture/compare register 3 (TIMx_CCR3) Address offset: 0x3C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CCR3[31:16] (depending on timers) rw rw rw rw rw rw rw 15 14 13 12 11 10 9 rw rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CCR3[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 CCR3[31:16]: High Capture/Compare 3 value (on TIM2 and TIM5). Bits 15:0 CCR3[15:0]: Low Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. If channel CC3is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). 16.4.16 TIMx capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CCR4[31:16] (depending on timers) rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw CCR4[15:0] rw rw Bits 31:16 CCR4[31:16]: High Capture/Compare 4 value (on TIM2 and TIM5). Bits 15:0 CCR4[15:0]: Low Capture/Compare value 1. if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. 2. if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register): CCR4 is the counter value transferred by the last input capture 4 event (IC4). 354/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) 16.4.17 TIMx DMA control register (TIMx_DCR) Address offset: 0x48 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 DBL[4:0] Res. rw rw rw rw 6 5 3 2 1 0 rw rw DBA[4:0] Res. rw 4 rw rw rw Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). 00000: 1 transfer, 00001: 2 transfers, 00010: 3 transfers, ... 10001: 18 transfers. Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 DBA[4:0]: DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2, 00010: TIMx_SMCR, ... Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. 16.4.18 TIMx DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DMAB[15:0] rw rw Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). Example of how to use the DMA burst feature In this example the timer DMA burst feature is used to update the contents of the CCRx registers (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers. DocID022448 Rev 2 355/897 359 General-purpose timers (TIM2 to TIM5, TIM19) RM0313 This is done in the following steps: 1. Note: 356/897 Configure the corresponding DMA channel as follows: – DMA channel peripheral address is the DMAR register address – DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers. – Number of data to transfer = 3 (See note below). – Circular mode disabled. 2. Configure the DCR register by configuring the DBA and DBL bit fields as follows: DBL = 3 transfers, DBA = 0xE. 3. Enable the TIMx update DMA request (set the UDE bit in the DIER register). 4. Enable TIMx 5. Enable the DMA channel This example is for the case where every CCRx register to be updated once. If every CCRx register is to be updated twice for example, the number of data to transfer should be 6. Let's take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and data6. The data is transferred to the CCRx registers as follows: on the first update DMA request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is transferred to CCR3 and data6 is transferred to CCR4. DocID022448 Rev 2 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) 16.4.19 TIM2 option register (TIM2_OR) Address offset: 0x50 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 ITR1_RMP Res. rw 4 3 2 1 0 Res. rw Bits 15:12 Reserved, must be kept at reset value. Bits 11:10 ITR1_RMP: Internal trigger 1 remap Set and cleared by software. 00: TIM8_TRGOUT 01: PTP trigger output is connected to TIM2_ITR1 10: OTG FS SOF is connected to the TIM2_ITR1 input 11: OTG HS SOF is connected to the TIM2_ITR1 input Bits 9:0 Reserved, must be kept at reset value. 16.4.20 TIMx register map TIMx registers are mapped as described in the table below: URS UDIS CEN 0 0 0 Res. Res. Res. 0 0 0 CC1IF UIF 0 0 0 0 0 0 UG 0 0 0 0 0 Res. Res. CC2IF 0 CC1G 0 CC2G 0 CC3IF 0 CC3G 0 CC4IF 0 CC4G UIE Res. 0 CC1IE 0 SMS[2:0] CC2IE 0 CC4IE TS[2:0] 0 DocID022448 Rev 2 0 TIF MSM UDE 0 Res. Res. 0 Res. 0 Res. CC1DE CC1OF Res. Res. Res. 0 Res. CC2DE 0 CC2OF 0 Res. CC3DE 0 CC3OF 0 Res. CC4DE 0 CC4OF 0 Res. COMDE 0 DIR 0 OPM CCDS 0 0 0 Res. 0 TIE ARPE 0 Res. Res. 0 0 TG Reset value TI1S Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_EGR 0 0 Reset value 0x14 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_SR 0 0 Reset value 0x10 MMS[2:0 ] 0 TDE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_DIER Res. 0x0C Res. Reset value ETF[3:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_SMCR 0 ETP S [1:0] Reset value 0x08 0 ECE 0 ETP Res. 0 CMS [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_CR2 Res. 0x04 Res. Reset value CKD [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_CR1 Res. 0x00 Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 47. TIM2 to TIM5/TIM19 register map and reset values 357/897 359 General-purpose timers (TIM2 to TIM5, TIM19) RM0313 0 0 0 0 0 0 0 0 0 0 TIMx_PSC 358/897 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 OC3CE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OC3M [2:0] 0 0 0 OC1PE OC1FE 0 0 0 CC3 S [1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC3P CC3E CC2NP Res. Res. CC3 S [1:0] Res. IC3 PSC [1:0] CC4E IC3F[3:0] CC1 S [1:0] CC3NP CC4 S [1:0] 0 IC1 PSC [1:0] Res. IC4 PSC [1:0] 0 0 OC3FE OC4FE CC4 S [1:0] 0 0 OC3PE OC2FE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARR[31:16] (TIM2 and TIM5 only, reserved on the other timers) 0 OC1CE OC2PE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSC[15:0] 0 0 0 0 0 ARR[15:0] 0 0 0 0 0 0 0 CCR1[31:16] (TIM2 and TIM5 only, reserved on the other timers) TIMx_CCR1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR1[15:0] 0 0 0 0 0 0 0 CCR2[31:16] (TIM2 and TIM5 only, reserved on the other timers) TIMx_CCR2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR3[15:0] 0 0 0 0 0 0 0 CCR4[31:16] (TIM2 and TIM5 only, reserved on the other timers) TIMx_CCR4 0 CCR2[15:0] CCR3[31:16] (TIM2 and TIM5 only, reserved on the other timers) TIMx_CCR3 Reset value 0x44 0 IC1F[3:0] 0 Res. Reset value 0x40 CC2 S [1:0] 0 CC1E 0 Reset value 0x3C IC2 PSC [1:0] 0 CC1P 0 0 0 CC2E 0 0 0 CC1NP 0 Reset value 0x38 CC4NP Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 TIMx_ARR 0 CC1 S [1:0] CC2P Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0x30 0x34 0 OC4PE O24CE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Reset value 0 0 OC1M [2:0] CNT[15:0] Reset value 0x2C 0 0 CNT[31:16] (TIM2 and TIM5 only, reserved on the other timers) TIMx_CNT Res. 0x28 0 IC4F[3:0] 0 Res. 0x24 0 CC2 S [1:0] CC4P Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 0 OC4M [2:0] 0 0 Res. TIMx_CCER 0 0 Reset value 0x20 OC2CE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 TIMx_CCMR2 Input Capture mode 0 IC2F[3:0] Reset value Reset value OC2M [2:0] 0 TIMx_CCMR2 Output Compare mode Res. 0x1C Res. TIMx_CCMR1 Input Capture mode 0 Res. Reset value Res. 0x18 Res. TIMx_CCMR1 Output Compare mode Res. Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 47. TIM2 to TIM5/TIM19 register map and reset values (continued) 0 0 0 0 CCR4[15:0] 0 Res. DocID022448 Rev 2 0 0 0 0 0 0 0 0 0 0 RM0313 General-purpose timers (TIM2 to TIM5, TIM19) Reset value Res. 0 0 0 0 0 0 0 0 Res. Res. Res. 0 Res. 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. ITR1 _RM P 0 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x50 0 DBA[4:0] DMAB[15:0] 0 Res. Reset value TIM2_OR 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_DMAR Res. 0x4C DBL[4:0] 0 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_DCR Res. 0x48 Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 47. TIM2 to TIM5/TIM19 register map and reset values (continued) 0 Refer to Table 1 on page 43 for the register boundary addresses. DocID022448 Rev 2 359/897 359 General-purpose timers (TIM12/13/14) RM0313 17 General-purpose timers (TIM12/13/14) 17.1 TIM12/13/14 introduction The TIM12/13/14 general-purpose timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers. The TIM12/13/14 timers are completely independent, and do not share any resources. They can be synchronized together as described in Section 17.4.12. 17.2 TIM12/13/14 main features 17.2.1 TIM12 main features The features of the TIM12 general-purpose timer include: • 16-bit auto-reload upcounter (in medium density devices) • 16-bit programmable prescaler used to divide the counter clock frequency by any factor between 1 and 65535 (can be changed “on the fly”) • Up to 2 independent channels for: – Input capture – Output compare – PWM generation (edge-aligned mode) – One-pulse mode output • Synchronization circuit to control the timer with external signals and to interconnect several timers together • Interrupt generation on the following events: – 360/897 Update: counter overflow, counter initialization (by software or internal trigger) – Trigger event (counter start, stop, initialization or count by internal trigger) – Input capture – Output compare DocID022448 Rev 2 RM0313 General-purpose timers (TIM12/13/14) Figure 100. General-purpose timer block diagram (TIM12) ,QWHUQDOFORFN&.B,17 7ULJJHU FRQWUROOHU ,75 ,75 ,75 ,75 7*, ,75 75& 7,)B(' 75*, 6ODYH FRQWUROOHU 5HVHWHQDEOHXSFRXQW PRGH 7,)3 7,)3 8 $XWRUHORDGUHJLVWHU 6WRS&OHDU &.B36& 7, 7,0[B&+ 7, 7,0[B&+ ,QSXWILOWHU HGJHGHWHFWRU ,QSXWILOWHU HGJHGHWHFWRU 7,)3 7,)3 ,& 36& &.B&17 SUHVFDOHU &&, 8 3UHVFDOHU 75& 7,)3 7,)3 75& ,&36 &&, ,& 3UHVFDOHU 8 &17FRXQWHU &&, &DSWXUH&RPSDUHUHJLVWHU 2&5() 2XWSXW FRQWURO 2& 7,0[B&+ &&, 8 ,&36 8, &DSWXUH&RPSDUHUHJLVWHU 2&5() 2XWSXW 2& FRQWURO 7,0[B&+ 1RWHV 5HJ 3UHORDGUHJLVWHUVWUDQVIHUUHG WRDFWLYHUHJLVWHUVRQ8HYHQW DFFRUGLQJWRFRQWUROELW (YHQW ,QWHUUXSW DL DocID022448 Rev 2 361/897 479 General-purpose timers (TIM12/13/14) 17.3 RM0313 TIM13/TIM14 main features The features of general-purpose timers TIM13/TIM14 include: • 16-bit auto-reload upcounter • 16-bit programmable prescaler used to divide the counter clock frequency by any factor between 1 and 65535 (can be changed “on the fly”) • independent channel for: • – Input capture – Output compare – PWM generation (edge-aligned mode) Interrupt generation on the following events: – Update: counter overflow, counter initialization (by software) – Input capture – Output compare Figure 101. General-purpose timer block diagram (TIM13/14) ,QWHUQDOFORFN&.B,17 7ULJJHU &RQWUROOHU $XWRUHORDGUHJLVWHU 8 8, 6WRSFOHDU &.B36& 7,0[B&+ 7, ,QSXWILOWHU HGJHVHOHFWRU 7,)3 36& SUHVFDOHU &.B&17 3UHVFDOHU ,&36 8 &17FRXQWHU &, &&, 8 ,& (QDEOH FRXQWHU &DSWXUHFRPSDUHUHJLVWHU 2&5() 2XWSXW FRQWURO 2& 7,0[B&+ 1RWHV 5HJ 3UHORDGUHJLVWHUVWUDQVIHUUHG WRDFWLYHUHJLVWHUVRQ8HYHQW DFFRUGLQJWRFRQWUROELW (YHQW DLG ,QWHUUXSW'0$RXWSXW 362/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM12/13/14) 17.4 TIM12/13/14 functional description 17.4.1 Time-base unit The main block of the timer is a 16-bit counter with its related auto-reload register. The counters counts up. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running. The time-base unit includes: • Counter register (TIMx_CNT) • Prescaler register (TIMx_PSC) • Auto-reload register (TIMx_ARR) The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detailed for each configuration. The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling). Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 register. Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event. Figure 103 and Figure 104 give some examples of the counter behavior when the prescaler ratio is changed on the fly. DocID022448 Rev 2 363/897 479 General-purpose timers (TIM12/13/14) RM0313 Figure 102. Counter timing diagram with prescaler division change from 1 to 2 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 364/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM12/13/14) Figure 103. Counter timing diagram with prescaler division change from 1 to 4 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 17.4.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller on TIM12) also generates an update event. The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. DocID022448 Rev 2 365/897 479 General-purpose timers (TIM12/13/14) RM0313 When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The auto-reload shadow register is updated with the preload value (TIMx_ARR), • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register). The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 104. Counter timing diagram, internal clock divided by 1 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 366/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM12/13/14) Figure 105. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 106. Counter timing diagram, internal clock divided by 4 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 DocID022448 Rev 2 367/897 479 General-purpose timers (TIM12/13/14) RM0313 Figure 107. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 108. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )) :ULWHDQHZYDOXHLQ7,0[B$55 069 368/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM12/13/14) Figure 109. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) ) ) ) &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU ) $XWRUHORDGVKDGRZ UHJLVWHU ) :ULWHDQHZYDOXHLQ7,0[B$55 17.4.3 069 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1 (for TIM12): external input pin (TIx) • Internal trigger inputs (ITRx) (for TIM12): connecting the trigger output from another timer. Refer to Section : Using one timer as prescaler for another for more details. Internal clock source (CK_INT) The internal clock source is the default clock source for TIM13/TIM14. For TIM12, the internal clock source is selected when the slave mode controller is disabled (SMS=’000’). The CEN bit in the TIMx_CR1 register and the UG bit in the TIMx_EGR register are then used as control bits and can be changed only by software (except for UG which remains cleared). As soon as the CEN bit is programmed to 1, the prescaler is clocked by the internal clock CK_INT. Figure 110 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. DocID022448 Rev 2 369/897 479 General-purpose timers (TIM12/13/14) RM0313 Figure 110. Control circuit in normal mode, internal clock divided by 1 ,QWHUQDOFORFN &(1 &17B(1 8* &17B,1,7 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 069 External clock source mode 1(TIM12) This mode is selected when SMS=’111’ in the TIMx_SMCR register. The counter can count at each rising or falling edge on a selected input. Figure 111. TI2 external clock connection example 7,0[B60&5 76>@ RU 7,) 7,) ,75[ 7,B(' 7, )LOWHU (GJH GHWHFWRU 7,)B5LVLQJ 7,)B)DOOLQJ 7,)3 7,)3 RU RU [[ 75*, &&3 7,0[B&&05 7,0[B&&(5 ([WHUQDOFORFN PRGH &.B36& &.B,17 ,&)>@ (QFRGHU PRGH LQWHUQDOFORFN ,QWHUQDOFORFN PRGH 606>@ 7,0[B60&5 069 For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: 370/897 DocID022448 Rev 2 RM0313 Note: General-purpose timers (TIM12/13/14) 1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register. 2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=’0000’). 3. Select the rising edge polarity by writing CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER register. 4. Configure the timer in external clock mode 1 by writing SMS=’111’ in the TIMx_SMCR register. 5. Select TI2 as the trigger input source by writing TS=’110’ in the TIMx_SMCR register. 6. Enable the counter by writing CEN=’1’ in the TIMx_CR1 register. The capture prescaler is not used for triggering, so you don’t need to configure it. When a rising edge occurs on TI2, the counter counts once and the TIF flag is set. The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input. Figure 112. Control circuit in external clock mode 1 7, &17B(1 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 7,) :ULWH7,) 069 17.4.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). Figure 113 to Figure 115 give an overview of one capture/compare channel. The input stage samples the corresponding TIx input to generate a filtered signal TIxF. Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS). DocID022448 Rev 2 371/897 479 General-purpose timers (TIM12/13/14) RM0313 Figure 113. Capture/compare channel (example: channel 1 input stage) 7,)B(' 7RWKHVODYHPRGHFRQWUROOHU 7, )LOWHU 7,) GRZQFRXQWHU I'76 7,)B5LVLQJ (GJH GHWHFWRU 7,)B)DOOLQJ 7,)3 7,)3 &&3&&13 ,&)>@ 7,0[B&&(5 7,0[B&&05 7,)B5LVLQJ IURPFKDQQHO 7,)B)DOOLQJ IURPFKDQQHO ,& 75& IURPVODYHPRGH FRQWUROOHU ,&36 'LYLGHU &&6>@ ,&36>@ &&( 7,0[B&&05 7,0[B&&(5 069 The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. Figure 114. Capture/compare channel 1 main circuit $3%%XV 5HDG&&5+ 6 5HDG&&5/ KLJK UHDGBLQBSURJUHVV &&6>@ ,&36 ZULWHBLQBSURJUHVV ,QSXW PRGH 6 ZULWH&&5+ &DSWXUHFRPSDUHSUHORDGUHJLVWHU 5 5 FRPSDUHBWUDQVIHU FDSWXUHBWUDQVIHU &&6>@ ORZ LIELW 0&8SHULSKHUDOLQWHUIDFH 2XWSXW PRGH &17!&&5 &RXQWHU &&* &&6>@ 8(9 &RPSDUDWRU &&( &&6>@ 2&3( &DSWXUHFRPSDUHVKDGRZUHJLVWHU &DSWXUH ZULWH&&5/ IURPWLPH EDVHXQLW 2&3( 7,0B&&05 &17 &&5 7,0B(*5 069 372/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM12/13/14) Figure 115. Output stage of capture/compare channel (channel 1) 7RWKHPDVWHU PRGHFRQWUROOHU &17!&&5 2XWSXW PRGH &17 &&5 FRQWUROOHU 2&B5() 2XWSXW HQDEOH FLUFXLW 2& &&3 7,0[B&&(5 2&0>@ &&( 7,0[B&&(5 7,0[B&&05 DL The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register. In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter. 17.4.5 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to ‘0’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure: 1. Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to ‘01’ in the TIMx_CCMR1 register. As soon as CC1S becomes different from ‘00’, the channel is configured in input mode and the TIMx_CCR1 register becomes readonly. 2. Program the input filter duration you need with respect to the signal you connect to the timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s imagine that, when toggling, the input signal is not stable during at must 5 internal clock cycles. We must program a filter duration longer than these 5 clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the new level have been DocID022448 Rev 2 373/897 479 General-purpose timers (TIM12/13/14) RM0313 detected (sampled at fDTS frequency). Then write IC1F bits to ‘0011’ in the TIMx_CCMR1 register. 3. Select the edge of the active transition on the TI1 channel by programming CC1P and CC1NP bits to ‘00’ in the TIMx_CCER register (rising edge in this case). 4. Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the TIMx_CCMR1 register). 5. Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER register. 6. If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register. When an input capture occurs: • The TIMx_CCR1 register gets the value of the counter on the active transition. • CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared. • An interrupt is generated depending on the CC1IE bit. In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data. Note: IC interrupt requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register. 17.4.6 PWM input mode (only for TIM12) This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. • One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode. For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): 374/897 1. Select the active input for TIMx_CCR1: write the CC1S bits to ‘01’ in the TIMx_CCMR1 register (TI1 selected). 2. Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): program the CC1P and CC1NP bits to ‘00’ (active on rising edge). 3. Select the active input for TIMx_CCR2: write the CC2S bits to ‘10’ in the TIMx_CCMR1 register (TI1 selected). 4. Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): program the CC2P and CC2NP bits to ‘11’ (active on falling edge). 5. Select the valid trigger input: write the TS bits to ‘101’ in the TIMx_SMCR register (TI1FP1 selected). 6. Configure the slave mode controller in reset mode: write the SMS bits to ‘100’ in the TIMx_SMCR register. 7. Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register. DocID022448 Rev 2 RM0313 General-purpose timers (TIM12/13/14) Figure 116. PWM input mode timing 7, 7,0[B&17 7,0[B&&5 7,0[B&&5 ,&FDSWXUH ,&FDSWXUH UHVHWFRXQWHU ,&FDSWXUH SXOVHZLGWK PHDVXUHPHQW ,&FDSWXUH SHULRG PHDVXUHPHQW DL 1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only TI1FP1 and TI2FP2 are connected to the slave mode controller. 17.4.7 Forced output mode In output mode (CCxS bits = ‘00’ in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (OCXREF/OCx) to its active level, you just need to write ‘101’ in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. For example: CCxP=’0’ (OCx active high) => OCx is forced to high level. The OCxREF signal can be forced low by writing the OCxM bits to ‘100’ in the TIMx_CCMRx register. Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt requests can be sent accordingly. This is described in the output compare mode section below. 17.4.8 Output compare mode This function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function: 1. Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCXM=’000’), be set active (OCxM=’001’), be set inactive (OCxM=’010’) or can toggle (OCxM=’011’) on match. 2. Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register). 3. Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the TIMx_DIER register). DocID022448 Rev 2 375/897 479 General-purpose timers (TIM12/13/14) RM0313 The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register. In output compare mode, the update event UEV has no effect on OCxREF and OCx output. The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One-pulse mode). Procedure: 1. Select the counter clock (internal, external, prescaler). 2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers. 3. Set the CCxIE bit if an interrupt request is to be generated. 4. Select the output mode. For example: 5. – Write OCxM = ‘011’ to toggle OCx output pin when CNT matches CCRx – Write OCxPE = ‘0’ to disable preload register – Write CCxP = ‘0’ to select active high polarity – Write CCxE = ‘1’ to enable the output Enable the counter by setting the CEN bit in the TIMx_CR1 register. The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 117. Figure 117. Output compare mode, toggle on OC1 :ULWH%KLQWKH&&5UHJLVWHU 7,0B&17 7,0B&&5 % $ % % % $ RFUHI 2& 0DWFKGHWHFWHGRQ&&5 ,QWHUUXSWJHQHUDWHGLIHQDEOHG 069 17.4.9 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register. 376/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM12/13/14) The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. You must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register. As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register. The OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. The OCx output is enabled by the CCxE bit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more details. In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CNT ≤TIMx_CCRx. The timer is able to generate PWM in edge-aligned mode only since the counter is upcounting. PWM edge-aligned mode In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 118 shows some edgealigned PWM waveforms in an example where TIMx_ARR=8. Figure 118. Edge-aligned PWM waveforms (ARR=8) &RXQWHUUHJLVWHU &&5[ 2&;5() &&[,) 2&;5() &&5[ &&[,) 2&;5() µ¶ &&5[! &&[,) 2&;5() µ¶ &&5[ &&[,) 069 DocID022448 Rev 2 377/897 479 General-purpose timers (TIM12/13/14) 17.4.10 RM0313 One-pulse mode (only for TIM12) One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. You select One-pulse mode by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV. A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be as follows: CNT < CCRx≤ ARR (in particular, 0 < CCRx) Figure 119. Example of one pulse mode 7, 2&5() 2& &RXQWHU 7,0B$55 7,0B&&5 W'(/$< W38/6( W 069 For example you may want to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin. Use TI2FP2 as trigger 1: 378/897 1. Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register. 2. TI2FP2 must detect a rising edge, write CC2P=’0’ and CC2NP = ‘0’ in the TIMx_CCER register. 3. Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in the TIMx_SMCR register. 4. TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register (trigger mode). DocID022448 Rev 2 RM0313 General-purpose timers (TIM12/13/14) The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The tDELAY is defined by the value written in the TIMx_CCR1 register. • The tPULSE is defined by the difference between the auto-reload value and the compare value (TIMx_ARR - TIMx_CCR1). • Let’s say you want to build a waveform with a transition from ‘0’ to ‘1’ when a compare match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload value. To do this you enable PWM mode 2 by writing OC1M=’111’ in the TIMx_CCMR1 register. You can optionally enable the preload registers by writing OC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to write the compare value in the TIMx_CCR1 register, the auto-reload value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2. CC1P is written to ‘0’ in this example. You only want 1 pulse (Single mode), so you write '1 in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the Repetitive Mode is selected. Particular case: OCx fast enable In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay tDELAY min we can get. If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode. 17.4.11 TIM12 external trigger synchronization The TIM12 timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated. In the following example, the upcounter is cleared in response to a rising edge on TI1 input: 1. Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=’0000’). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S = ‘01’ in the TIMx_CCMR1 register. Program CC1P and CC1NP to ‘00’ in TIMx_CCER register to validate the polarity (and detect rising edges only). 2. Configure the timer in reset mode by writing SMS=’100’ in TIMx_SMCR register. Select TI1 as the input source by writing TS=’101’ in TIMx_SMCR register. 3. Start the counter by writing CEN=’1’ in the TIMx_CR1 register. DocID022448 Rev 2 379/897 479 General-purpose timers (TIM12/13/14) RM0313 The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request can be sent if enabled (depending on the TIE bit in TIMx_DIER register). The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input. Figure 120. Control circuit in reset mode 7, 8* &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) 069 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: 1. Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=’0000’). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S=’01’ in TIMx_CCMR1 register. Program CC1P=’1’ and CC1NP= ‘0’ in TIMx_CCER register to validate the polarity (and detect low level only). 2. Configure the timer in gated mode by writing SMS=’101’ in TIMx_SMCR register. Select TI1 as the input source by writing TS=’101’ in TIMx_SMCR register. 3. Enable the counter by writing CEN=’1’ in the TIMx_CR1 register (in gated mode, the counter doesn’t start if CEN=’0’, whatever is the trigger input level). The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops. The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input. 380/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM12/13/14) Figure 121. Control circuit in gated mode 7, FQWBHQ &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) :ULWH7,) 069 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: 1. Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=’0000’). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC2S bits are configured to select the input capture source only, CC2S=’01’ in TIMx_CCMR1 register. Program CC2P=’1’ and CC2NP=’0’ in TIMx_CCER register to validate the polarity (and detect low level only). 2. Configure the timer in trigger mode by writing SMS=’110’ in TIMx_SMCR register. Select TI2 as the input source by writing TS=’110’ in TIMx_SMCR register. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set. The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input. Figure 122. Control circuit in trigger mode 7, FQWBHQ &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) 069 DocID022448 Rev 2 381/897 479 General-purpose timers (TIM12/13/14) 17.4.12 RM0313 Timer synchronization (TIM12) The TIM timers are linked together internally for timer synchronization or chaining. Refer to Section 16.3.15: Timer synchronization on page 331 for details. 17.4.13 Debug mode When the microcontroller enters debug mode (Cortex-M4 with FPU core halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBG module. For more details, refer to Section 31.16.2: Debug support for timers, watchdog, bxCAN and I2C. 382/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM12/13/14) 17.5 TIM12 registers Refer to Section 1.1 on page 36 for a list of abbreviations used in register descriptions. The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 17.5.1 TIM12 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 15 14 13 12 Res. 11 10 9 8 CKD[1:0] rw 7 ARPE rw rw 6 5 Res. 4 3 2 1 0 OPM URS UDIS CEN rw rw rw rw Bits 15:10 Reserved, must be kept at reset value. Bits 9:8 CKD: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx), 00: tDTS = tCK_INT 01: tDTS = 2 × tCK_INT 10: tDTS = 4 × tCK_INT 11: Reserved Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered. 1: TIMx_ARR register is buffered. Bits 6:4 Reserved, must be kept at reset value. Bit 3 OPM: One-pulse mode 0: Counter is not stopped on the update event 1: Counter stops counting on the next update event (clearing the CEN bit). Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt if enabled: – Counter overflow – Setting the UG bit 1: Only counter overflow generates an update interrupt if enabled. Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable update event (UEV) generation. 0: UEV enabled. An UEV is generated by one of the following events: – Counter overflow – Setting the UG bit Buffered registers are then loaded with their preload values. 1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled CEN is cleared automatically in one-pulse mode, when an update event occurs. DocID022448 Rev 2 383/897 479 General-purpose timers (TIM12/13/14) 17.5.2 RM0313 TIM12 slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 15 14 13 12 11 Res. 10 9 8 7 6 MSM rw 5 4 TS[2:0] rw rw rw 3 Res. 2 1 0 SMS[2:0] rw rw rw Bits 15:8 Reserved, must be kept at reset value. Bit 7 MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful in order to synchronize several timers on a single external event. Bits 6:4 TS: Trigger selection This bitfield selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0) 001: Internal Trigger 1 (ITR1) 010: Internal Trigger 2 (ITR2) 011: Internal Trigger 3 (ITR3) 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2) 111: Reserved. See Table 77: TIMx Internal trigger connectionTO BE CHECKED on page 444for more details on the meaning of ITRx for each timer. Note: These bits must be changed only when they are not used (e.g. when SMS=’000’) to avoid wrong edge detections at the transition. Bit 3 Reserved, must be kept at reset value. Bits 2:0 SMS: Slave mode selection When external signals are selected, the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input control register and Control register descriptions. 000: Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock 001: Reserved 010: Reserved 011: Reserved 100: Reset mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers 101: Gated mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Counter starts and stops are both controlled 110: Trigger mode - The counter starts on a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled 111: External clock mode 1 - Rising edges of the selected trigger (TRGI) clock the counter Note: The Gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the Gated mode checks the level of the trigger signal. 384/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM12/13/14) Table 48. TIMx Internal trigger connection(1) Slave TIM ITR0 (TS = 000) ITR1 (TS = 001) ITR2 (TS = 010) ITR3 (TS = 011) TIM12 TIM4 TIM5 TIM13 TIM14 1. When a timer is not present in the product, the corresponding trigger ITRx is not available. 17.5.3 TIM12 Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 Res. Bit 15:7 6 TIE rw 5 4 Res. 3 2 1 0 CC2IE CC1IE UIE rw rw rw Reserved, must be kept at reset value. Bit 6 TIE: Trigger interrupt enable 0: Trigger interrupt disabled. 1: Trigger interrupt enabled. Bit 5:3 Reserved, must be kept at reset value. Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled. 1: CC2 interrupt enabled. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled. 1: CC1 interrupt enabled. Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled. DocID022448 Rev 2 385/897 479 General-purpose timers (TIM12/13/14) 17.5.4 RM0313 TIM12 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 15 14 13 Res. Bit 15:11 12 11 10 9 8 CC2OF CC1OF rc_w0 rc_w0 7 Res. 6 TIF rc_w0 5 4 Res. 3 2 1 0 CC2IF CC1IF UIF rc_w0 rc_w0 rc_w0 Reserved, must be kept at reset value. Bit 10 CC2OF: Capture/compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected. 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set Bits 8:7 Reserved, must be kept at reset value. Bit 6 TIF: Trigger interrupt flag This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 0: No trigger event occurred. 1: Trigger interrupt pending. Bit 5:3 386/897 Reserved, must be kept at reset value. DocID022448 Rev 2 RM0313 General-purpose timers (TIM12/13/14) Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value. It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow. If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1 register. 0: No input capture occurred. 1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1 which matches the selected polarity). Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: – At overflow and if UDIS=’0’ in the TIMx_CR1 register. – When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register. – When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register. DocID022448 Rev 2 387/897 479 General-purpose timers (TIM12/13/14) 17.5.5 RM0313 TIM12 event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 TG Res. w 5 4 Res. 3 2 1 0 CC2G CC1G UG w w w Bits 15:7 Reserved, must be kept at reset value. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in the TIMx_SR register. Related interrupt can occur if enabled Bits 5:3 Reserved, must be kept at reset value. Bit 2 CC2G: Capture/compare 2 generation refer to CC1G description Bit 1 CC1G: Capture/compare 1 generation This bit is set by software to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: the CC1IF flag is set, the corresponding interrupt is sent if enabled. If channel CC1 is configured as input: The current counter value is captured in the TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initializes the counter and generates an update of the registers. The prescaler counter is also cleared and the prescaler ratio is not affected. The counter is cleared. 388/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM12/13/14) 17.5.6 TIM12 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits in this register have different functions in input and output modes. For a given bit, OCxx describes its function when the channel is configured in output mode, ICxx describes its function when the channel is configured in input mode. So you must take care that the same bit can have different meanings for the input stage and the output stage. 15 14 Res. rw rw 13 12 11 10 OC2M[2:0] OC2PE OC2FE IC2F[3:0] IC2PSC[1:0] rw rw rw rw 9 8 CC2S[1:0] rw rw 7 6 Res. rw rw 5 4 3 2 OC1M[2:0] OC1PE OC1FE IC1F[3:0] IC1PSC[1:0] rw rw rw rw 1 0 CC1S[1:0] rw rw Output compare mode Bit 15 Reserved, must be kept at reset value. Bits 14:12 OC2M[2:0]: Output compare 2 mode Bit 11 OC2PE: Output compare 2 preload enable Bit 10 OC2FE: Output compare 2 fast enable Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register Note: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). Bit 7 Reserved, must be kept at reset value. DocID022448 Rev 2 389/897 479 General-purpose timers (TIM12/13/14) RM0313 Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas the active levels of OC1 and OC1N depend on the CC1P and CC1NP bits, respectively. 000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base). 001: Set channel 1 to active level on match. The OC1REF signal is forced high when the TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1). 010: Set channel 1 to inactive level on match. The OC1REF signal is forced low when the TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1). 011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1 100: Force inactive level - OC1REF is forced low 101: Force active level - OC1REF is forced high 110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else it is inactive. In downcounting, channel 1 is inactive (OC1REF=‘0) as long as TIMx_CNT>TIMx_CCR1, else it is active (OC1REF=’1’) 111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else it is active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else it is inactive. Note: In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Bit 3 OC1PE: Output compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken into account immediately 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded into the active register at each update event Note: The PWM mode can be used without validating the preload register only in one-pulse mode (OPM bit set in the TIMx_CR1 register). Else the behavior is not guaranteed. Bit 2 OC1FE: Output compare 1 fast enable This bit is used to accelerate the effect of an event on the trigger in input on the CC output. 0: CC1 behaves normally depending on the counter and CCR1 values even when the trigger is ON. The minimum delay to activate the CC1 output when an edge occurs on the trigger input is 5 clock cycles 1: An active edge on the trigger input acts like a compare match on the CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode. Bits 1:0 CC1S: Capture/Compare 1 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) Note: The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 390/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM12/13/14) Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) Note: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). Bits 7:4 IC1F: Input capture 1 filter This bitfield defines the frequency used to sample the TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS1000: fSAMPLING=fDTS/8, N=6 0001: fSAMPLING=fCK_INT, N=21001: fSAMPLING=fDTS/8, N=8 0010: fSAMPLING=fCK_INT, N=41010: fSAMPLING=fDTS/16, N=5 0011: fSAMPLING=fCK_INT, N=8 1011: fSAMPLING=fDTS/16, N=6 0100: fSAMPLING=fDTS/2, N=61100: fSAMPLING=fDTS/16, N=8 0101: fSAMPLING=fDTS/2, N=81101: fSAMPLING=fDTS/32, N=5 0110: fSAMPLING=fDTS/4, N=61110: fSAMPLING=fDTS/32, N=6 0111: fSAMPLING=fDTS/4, N=81111: fSAMPLING=fDTS/32, N=8 Note: In the current silicon revision, fDTS is replaced in the formula by CK_INT when ICxF[3:0]= 1, 2 or 3. Bits 3:2 IC1PSC: Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events Bits 1:0 CC1S: Capture/Compare 1 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). DocID022448 Rev 2 391/897 479 General-purpose timers (TIM12/13/14) 17.5.7 RM0313 TIM12 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 15 14 13 12 11 Res. 10 9 8 7 CC2NP rw 6 Res. 5 4 3 CC2P CC2E CC1NP rw rw rw 2 Res. 1 0 CC1P CC1E rw rw Bits 15:8 Reserved, must be kept at reset value. Bit 7 CC2NP: Capture/Compare 2 output Polarity refer to CC1NP description Bits 6 Reserved, must be kept at reset value. Bit 5 CC2P: Capture/Compare 2 output Polarity refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 complementary output Polarity CC1 channel configured as output: CC1NP must be kept cleared CC1 channel configured as input: CC1NP is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity (refer to CC1P description). Bits 2 Reserved, must be kept at reset value. Bit 1 CC1P: Capture/Compare 1 output Polarity. CC1 channel configured as output: 0: OC1 active high. 1: OC1 active low. CC1 channel configured as input: CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations. 00: noninverted/rising edge Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode). 01: inverted/falling edge Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is inverted (trigger in gated mode, encoder mode). 10: reserved, do not use this configuration. Note: 11: noninverted/both edges Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This configuration must not be used for encoder mode. Bit 0 CC1E: Capture/Compare 1 output enable. CC1 channel configured as output: 0: Off - OC1 is not active. 1: On - OC1 signal is output on the corresponding output pin. CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not. 0: Capture disabled. 1: Capture enabled. 392/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM12/13/14) Table 49. Output control bit for standard OCx channels CCxE bit OCx output state 0 Output disabled (OCx=’0’, OCx_EN=’0’) 1 OCx=OCxREF + Polarity, OCx_EN=’1’ Note: The states of the external I/O pins connected to the standard OCx channels depend on the state of the OCx channel and on the GPIO registers. 17.5.8 TIM12 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CNT[15:0] rw rw rw rw rw rw rw rw Bits 15:0 CNT[15:0]: Counter value 17.5.9 TIM12 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 15 14 13 12 11 10 9 8 PSC[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded into the active prescaler register at each update event. 17.5.10 TIM12 auto-reload register (TIMx_ARR) Address offset: 0x2C Reset value: 0x0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw ARR[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 ARR[15:0]: Auto-reload value ARR is the value to be loaded into the actual auto-reload register. Refer to the Section 17.4.1: Time-base unit on page 363 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. DocID022448 Rev 2 393/897 479 General-purpose timers (TIM12/13/14) 17.5.11 RM0313 TIM12 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CCR1[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded into the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (OC1PE bit). Else the preload value is copied into the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the TIMx_CNT counter and signaled on the OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). 17.5.12 TIM12 capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CCR2[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded into the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (OC2PE bit). Else the preload value is copied into the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the TIMx_CNT counter and signalled on the OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). 394/897 DocID022448 Rev 2 0x28 TIMx_PSC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Reset value DocID022448 Rev 2 0 0 0 Res. Res. 0 0 0 0 0 0 IC2F[3:0] 0 0 0 0 0 0 0 0 0 0 IC2 PSC [1:0] CC2 S [1:0] Reset value 0 0 Reset value 0 0 0 0 0 0 0 0 IC1F[3:0] CC1G UG 0 CC2G 0 0 0 0 OC1FE OC1M [2:0] 0 0 0 0 0 0 CNT[15:0] PSC[15:0] 0 0 0 0 0 0 0 0 0 UIF 0 CC1IF CC2IE CC1IE UIE 0 CC2IF Res. Res. 0 Res. 0 Res. Res. OPM URS UDIS CEN 0 0 Res. Res. Res. Res. Res. Res. ARPE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 0 Res. TS[2:0] OC1PE Res. Res. 0 TIE Res. MSM 0 Res. Res. Res. TIF Reset value TG 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 IC1 PSC [1:0] CC1 S [1:0] 0 0 0 CC1E 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value MMS[2:0] Res. CC2 S [1:0] Res. Res. CC1OF Res. Res. CC2OF 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 CC1P OC2FE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. OC2PE 0 0 CC1NP 0 0 CC2E 0 CKD [1:0] CC2P Reset value OC2M [2:0] 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value CC2NP 0 Res. Res. 0 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x1C Res. Res. Res. Res. Res. Res. Res. Res. TIMx_CNT Res. 0x24 Res. TIMx_CCER Res. 0x20 Res. TIMx_CCMR1 Input Capture mode Res. TIMx_CCMR1 Output Compare mode Res. TIMx_EGR Res. 0x14 Res. TIMx_SR Res. 0x10 Res. TIMx_DIER Res. 0x0C Res. TIMx_SMCR Res. 0x08 Res. TIMx_CR2 Res. 0x04 Res. 0x00 Res. TIMx_CR1 Res. 0x18 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. 17.5.13 Res. RM0313 General-purpose timers (TIM12/13/14) TIM12 register map TIM12 registers are mapped as 16-bit addressable registers as described below: Table 50. TIM12 register map and reset values SMS[2:0] 0 0 0 0 0 0 0 0 0 CC1 S [1:0] 0 0 0 0 0 0 0 0 0 0 0 0 395/897 479 General-purpose timers (TIM12/13/14) RM0313 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_ARR 0x2C Res. Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 50. TIM12 register map and reset values (continued) Reset value ARR[15:0] 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_CCR1 0x34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR2[15:0] 0 0x3C to 0x4C 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_CCR2 0x38 CCR1[15:0] 0 Res. Reset value 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_CCR2 Res. Res. 0x38 Reset value CCR2[15:0] 0 0 0 0 0 0 Refer to Table 2 on page 40 for the register boundary addresses. 396/897 0 Res. Res. 0x30 0 DocID022448 Rev 2 0 0 0 0 RM0313 General-purpose timers (TIM12/13/14) 17.6 TIM13/14 registers The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 17.6.1 TIM13/14 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 15 14 13 12 11 10 Res. 9 8 CKD[1:0] rw 7 ARPE rw rw 6 5 4 Res. 3 2 1 0 URS UDIS CEN rw rw rw Bits 15:10 Reserved, must be kept at reset value. Bits 9:8 CKD: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx), 00: tDTS = tCK_INT 01: tDTS = 2 × tCK_INT 10: tDTS = 4 × tCK_INT 11: Reserved Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered 1: TIMx_ARR register is buffered Bits 6:3 Reserved, must be kept at reset value. Bit 2 URS: Update request source This bit is set and cleared by software to select the update interrupt (UEV) sources. 0: Any of the following events generate an UEV if enabled: – Counter overflow – Setting the UG bit 1: Only counter overflow generates an UEV if enabled. Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable update interrupt (UEV) event generation. 0: UEV enabled. An UEV is generated by one of the following events: – Counter overflow – Setting the UG bit. Buffered registers are then loaded with their preload values. 1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled DocID022448 Rev 2 397/897 479 General-purpose timers (TIM12/13/14) 17.6.2 RM0313 TIM13/14 Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Res. Bits 15:2 1 0 CC1IE UIE rw rw Reserved, must be kept at reset value. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled 17.6.3 TIM13/14 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 15 14 13 12 Res. Bit 15:10 11 10 9 8 7 CC1OF rc_w0 6 5 Res. 4 3 2 1 0 CC1IF UIF rc_w0 rc_w0 Reserved, must be kept at reset value. Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected. 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set 398/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM12/13/14) Bits 8:2 Reserved, must be kept at reset value. Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value. It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow. If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1 register. 0: No input capture occurred. 1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1 which matches the selected polarity). Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: – At overflow and if UDIS=’0’ in the TIMx_CR1 register. – When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register. 17.6.4 TIM13/14 event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 Res. 6 5 4 3 2 1 0 CC1G UG w w Bits 15:2 Reserved, must be kept at reset value. Bit 1 CC1G: Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared. DocID022448 Rev 2 399/897 479 General-purpose timers (TIM12/13/14) 17.6.5 RM0313 TIM13/14 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So you must take care that the same bit can have a different meaning for the input stage and for the output stage. 15 14 13 12 11 10 9 8 7 6 Res. Res. 5 4 OC1M[2:0] IC1F[3:0] rw rw rw 3 2 OC1PE OC1FE IC1PSC[1:0] rw rw rw 1 0 CC1S[1:0] rw rw Output compare mode Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas OC1 active level depends on CC1P bit. 000: Frozen. The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. 001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 011: Toggle - OC1REF toggles when TIMx_CNT = TIMx_CCR1. 100: Force inactive level - OC1REF is forced low. 101: Force active level - OC1REF is forced high. 110: PWM mode 1 - Channel 1 is active as long as TIMx_CNT < TIMx_CCR1 else inactive. 111: PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT < TIMx_CCR1 else active. Note: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison changes or when the output compare mode switches from frozen to PWM mode. 400/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM12/13/14) Bit 3 OC1PE: Output compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. Bit 2 OC1FE: Output compare 1 fast enable This bit is used to accelerate the effect of an event on the trigger in input on the CC output. 0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. 1: An active edge on the trigger input acts like a compare match on CC1 output. OC is then set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode. Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output. 01: CC1 channel is configured as input, IC1 is mapped on TI1. 10: Reserved 11: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). Input capture mode Bits 15:8 Reserved, must be kept at reset value. DocID022448 Rev 2 401/897 479 General-purpose timers (TIM12/13/14) RM0313 Bits 7:4 IC1F: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS1000: fSAMPLING=fDTS/8, N=6 0001: fSAMPLING=fCK_INT, N=21001: fSAMPLING=fDTS/8, N=8 0010: fSAMPLING=fCK_INT, N=41010: fSAMPLING=fDTS/16, N=5 0011: fSAMPLING=fCK_INT, N=81011: fSAMPLING=fDTS/16, N=6 0100: fSAMPLING=fDTS/2, N=61100: fSAMPLING=fDTS/16, N=8 0101: fSAMPLING=fDTS/2, N=81101: fSAMPLING=fDTS/32, N=5 0110: fSAMPLING=fDTS/4, N=61110: fSAMPLING=fDTS/32, N=6 0111: fSAMPLING=fDTS/4, N=81111: fSAMPLING=fDTS/32, N=8 Note: In current silicon revision, fDTS is replaced in the formula by CK_INT when ICxF[3:0]= 1, 2 or 3. Bits 3:2 IC1PSC: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 402/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM12/13/14) 17.6.6 TIM13/14 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 CC1NP Res. rw 2 Res. 1 0 CC1P CC1E rw rw Bits 15:4 Reserved, must be kept at reset value. Bit 3 CC1NP: Capture/Compare 1 complementary output Polarity. CC1 channel configured as output: CC1NP must be kept cleared. CC1 channel configured as input: CC1NP bit is used in conjunction with CC1P to define TI1FP1 polarity (refer to CC1P description). Bit 2 Reserved, must be kept at reset value. Bit 1 CC1P: Capture/Compare 1 output Polarity. CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: The CC1P bit selects TI1FP1 and TI2FP1 polarity for trigger or capture operations. 00: noninverted/rising edge Circuit is sensitive to TI1FP1 rising edge (capture mode), TI1FP1 is not inverted. 01: inverted/falling edge Circuit is sensitive to TI1FP1 falling edge (capture mode), TI1FP1 is inverted. 10: reserved, do not use this configuration. 11: noninverted/both edges Circuit is sensitive to both TI1FP1 rising and falling edges (capture mode), TI1FP1 is not inverted. Bit 0 CC1E: Capture/Compare 1 output enable. CC1 channel configured as output: 0: Off - OC1 is not active 1: On - OC1 signal is output on the corresponding output pin CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not. 0: Capture disabled 1: Capture enabled Table 51. Output control bit for standard OCx channels CCxE bit Note: OCx output state 0 Output Disabled (OCx=’0’, OCx_EN=’0’) 1 OCx=OCxREF + Polarity, OCx_EN=’1’ The state of the external I/O pins connected to the standard OCx channels depends on the OCx channel state and the GPIO registers. DocID022448 Rev 2 403/897 479 General-purpose timers (TIM12/13/14) 17.6.7 RM0313 TIM13/14 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CNT[15:0] rw rw rw rw rw rw rw rw Bits 15:0 CNT[15:0]: Counter value 17.6.8 TIM13/14 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw rw PSC[15:0] rw Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event. 17.6.9 TIM13/14 auto-reload register (TIMx_ARR) Address offset: 0x2C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw ARR[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 ARR[15:0]: Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to Section 17.4.1: Time-base unit on page 363 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. 404/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM12/13/14) 17.6.10 TIM13/14 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CCR1[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). DocID022448 Rev 2 405/897 479 General-purpose timers (TIM12/13/14) 17.6.11 RM0313 TIM14 option register (TIM14_OR) Address offset: 0x38 Reset value: 0x0000 15 Res. 14 Res. 13 Res. 12 Res. 11 10 Res. Res. 9 8 Res. 7 Res. 6 Res. 5 Res. 4 Res. 3 Res. 2 Res. 1 0 TI1_ RMP[1:0] Res. rw Bits 15:2 Reserved, must be kept at reset value. Bit 1:0 TI1_RMP[1:0]: Timer Input 1 remap Set and cleared by software. 00: TIM14 Channel1 is connected to the GPIO. Refer to the Alternate function mapping table in the device datasheets. 01: the RTC_CLK is connected to the TIM14_CH1 input for calibration purposes 10: TIM14_CH1 input is connected to HSE/32 clock 11: TIM14_CH1 input is connected to MCO clock. 17.6.12 TIM13/14 register map TIMx registers are mapped as 16-bit addressable registers as described in the tables below: UDIS CEN Res. URS 0 0 0 Res. Res. Res. 0 Res. ARPE TIMx_SMCR 0 Res. 0x08 0 Res. Res. Reset value CKD [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_CR1 0x00 Res. Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 52. TIM13/14 register map and reset values Not Available 406/897 DocID022448 Rev 2 CC1IE UIE UIF Res. Res. Res. Res. Res. 0 CC1IF Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 UG Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_EGR 0x14 0 Res. Reset value CC1OF Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_SR 0x10 Res. Reset value CC1G Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_DIER 0x0C Res. Reset value 0 0 0x38 TIM14_OR 0x3C to 0x4C Reset value DocID022448 Rev 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI1_ RMP[1:0] Reset value Res. Reset value Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. 0x30 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 IC1F[3:0] Reset value OC1PE OC1FE 0 IC1 PSC [1:0] CC1 S [1:0] 0 0 0 0 0 0 CC1E Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OC1M [2:0] CC1P 0 Res. 0 Res. Reset value CC1NP 0 Res. Res. 0 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x1C Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_CCR1 Res. 0x34 Res. TIMx_ARR Res. 0x2C Res. TIMx_PSC Res. 0x28 Res. TIMx_CNT Res. 0x24 Res. TIMx_CCER Res. 0x20 Res. TIMx_CCMR1 Input capture mode Res. TIMx_CCMR1 Output compare mode Res. 0x18 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. RM0313 General-purpose timers (TIM12/13/14) Table 52. TIM13/14 register map and reset values (continued) CC1 S [1:0] 0 0 0 0 0 0 CNT[15:0] PSC[15:0] ARR[15:0] Res. CCR1[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. 407/897 479 General-purpose timers (TIM15/16/17) RM0313 18 General-purpose timers (TIM15/16/17) 18.1 TIM15/16/17 introduction The TIM15/16/17 timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers. The TIM15/16/17 timers are completely independent, and do not share any resources. The TIM15 can be synchronized with other timers. 18.2 TIM15 main features TIM15 includes the following features: 408/897 • 16-bit auto-reload upcounter • 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65535 • Up to 2 independent channels for: – Input capture – Output compare – PWM generation (edge mode) – One-pulse mode output • Complementary outputs with programmable dead-time (for channel 1 only) • Synchronization circuit to control the timer with external signals and to interconnect several timers together • Repetition counter to update the timer registers only after a given number of cycles of the counter • Break input to put the timer’s output signals in the reset state or a known state • Interrupt/DMA generation on the following events: – Update: counter overflow, counter initialization (by software or internal/external trigger) – Input capture – Output compare – Break input (interrupt request) DocID022448 Rev 2 RM0313 18.3 General-purpose timers (TIM15/16/17) TIM16 and TIM17 main features The TIM16 and TIM17 timers include the following features: • 16-bit auto-reload upcounter • 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65535 • One channel for: – Input capture – Output compare – PWM generation (edge-aligned mode) – One-pulse mode output • Complementary outputs with programmable dead-time • Repetition counter to update the timer registers only after a given number of cycles of the counter • Break input to put the timer’s output signals in the reset state or a known state • Interrupt/DMA generation on the following events: – Update: counter overflow – Trigger event (counter start, stop, initialization or count by internal/external trigger) – Input capture – Output compare – Break input DocID022448 Rev 2 409/897 479 General-purpose timers (TIM15/16/17) RM0313 Figure 123. TIM15 block diagram ,QWHUQDOFORFN&.B,17 &.B7,0IURP5&& ,75 ,75 ,75 ,75 7ULJJHU FRQWUROOHU 7*, ,75 75& 7,)B(' 75*, 75*2 WRRWKHUWLPHUV 6ODYH FRQWUROOHU 5HVHWHQDEOHXSFRXQW PRGH 7,)3 7,)3 5(3UHJLVWHU 8 8, $XWRUHORDGUHJLVWHU 5HSHWLWLRQ FRXQWHU 6WRSFOHDURUXSGRZQ &.B36& 7, 7,0[B&+ 7, 7,0[B&+ 7,0[B%.,1 %5. ,QSXWILOWHU HGJHGHWHFWRU ,QSXWILOWHU HGJHGHWHFWRU 7,)3 7,)3 ,& 36& &.B&17 SUHVFDOHU &&, 8 3UHVFDOHU 75& 7,)3 7,)3 75& 3RODULW\VHOHFWLRQ ,&36 &&, ,& 3UHVFDOHU &17FRXQWHU &&, &DSWXUH&RPSDUHUHJLVWHU '7*UHJLVWHUV 2&5() '7* &&, 8 ,&36 8 &DSWXUH&RPSDUHUHJLVWHU 2&5() 7,0[B&+ 2XWSXW 2& FRQWURO 7,0[B&+1 2&1 2XWSXW 2& 7,0[B&+ FRQWURO %, &ORFNIDLOXUHHYHQWIURPFORFNFRQWUROOHU &66&ORFN6HFXULW\6\VWHP 1RWHV 5HJ 3UHORDGUHJLVWHUVWUDQVIHUUHG WRDFWLYHUHJLVWHUVRQ8HYHQW DFFRUGLQJWRFRQWUROELW (YHQW ,QWHUUXSW'0$RXWSXW DL 410/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM15/16/17) Figure 124. TIM16 and TIM17 block diagram ,QWHUQDOFORFN&.B,17 &RXQWHU(QDEOH&(1 5(3UHJLVWHU $XWRUHORDGUHJLVWHU 8 8, 5HSHWLWLRQ FRXQWHU 6WRSFOHDURUXSGRZQ &.B36& 7,0[B&+ 7, ,QSXWILOWHU HGJHVHOHFWRU 7,)3 36& SUHVFDOHU &.B&17 &17FRXQWHU &, 3UHVFDOHU ,&36 '7*UHJLVWHUV &&, 8 ,& 8 &DSWXUHFRPSDUHUHJLVWHU 2&5() 7,0[B&+ '7* 2XWSXW 2& FRQWURO 7,0[B&+1 2&1 7,0[B%.,1 %5. 3RODULW\VHOHFWLRQ %, &ORFNIDLOXUHHYHQWIURPFORFNFRQWUROOHU 1RWHV 5HJ 3UHORDGUHJLVWHUVWUDQVIHUUHG WRDFWLYHUHJLVWHUVRQ8HYHQW DFFRUGLQJWRFRQWUROELW (YHQW ,QWHUUXSW'0$RXWSXW 069 DocID022448 Rev 2 411/897 479 General-purpose timers (TIM15/16/17) RM0313 18.4 TIM15/16/17 functional description 18.4.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running. The time-base unit includes: • Counter register (TIMx_CNT) • Prescaler register (TIMx_PSC) • Auto-reload register (TIMx_ARR) • Repetition counter register (TIMx_RCR) The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detailed for each configuration. The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling). Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 register. Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event. Figure 103 and Figure 104 give some examples of the counter behavior when the prescaler ratio is changed on the fly: 412/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM15/16/17) Figure 125. Counter timing diagram with prescaler division change from 1 to 2 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 Figure 126. Counter timing diagram with prescaler division change from 1 to 4 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 DocID022448 Rev 2 413/897 479 General-purpose timers (TIM15/16/17) 18.4.2 RM0313 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR). Else the update event is generated at each counter overflow. Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The repetition counter is reloaded with the content of TIMx_RCR register, • The auto-reload shadow register is updated with the preload value (TIMx_ARR), • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register). The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. 414/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM15/16/17) Figure 127. Counter timing diagram, internal clock divided by 1 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 128. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 DocID022448 Rev 2 415/897 479 General-purpose timers (TIM15/16/17) RM0313 Figure 129. Counter timing diagram, internal clock divided by 4 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 130. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 416/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM15/16/17) Figure 131. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )) :ULWHDQHZYDOXHLQ7,0[B$55 069 Figure 132. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) ) ) ) &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU ) $XWRUHORDGVKDGRZ UHJLVWHU ) :ULWHDQHZYDOXHLQ7,0[B$55 DocID022448 Rev 2 069 417/897 479 General-purpose timers (TIM15/16/17) 18.4.3 RM0313 Repetition counter Section 17.4.1: Time-base unit describes how the update event (UEV) is generated with respect to the counter overflows/underflows. It is actually generated only when the repetition counter has reached zero. This can be useful when generating PWM signals. This means that data are transferred from the preload registers to the shadow registers (TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx capture/compare registers in compare mode) every N counter overflows or underflows, where N is the value in the TIMx_RCR repetition counter register. The repetition counter is decremented at each counter overflow in upcounting mode. The repetition counter is an auto-reload type; the repetition rate is maintained as defined by the TIMx_RCR register value (refer to Figure 133). When the update event is generated by software (by setting the UG bit in TIMx_EGR register) or by hardware through the slave mode controller, it occurs immediately whatever the value of the repetition counter is and the repetition counter is reloaded with the content of the TIMx_RCR register. 418/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM15/16/17) Figure 133. Update rate examples depending on mode and TIMx_RCR register settings (GJHDOLJQHGPRGH 8SFRXQWLQJ &RXQWHU 7,0[B&17 7,0[B5&5 8(9 7,0[B5&5 8(9 7,0[B5&5 8(9 7,0[B5&5 8(9 7,0[B5&5 DQG UHV\QFKURQL]DWLRQ8(9 E\6: 8(9 8SGDWH(YHQWSUHORDGUHJLVWHUVWUDQVIHUUHGWRDFWLYHUHJLVWHUV DQGXSGDWHLQWHUUXSWJHQHUDWHG 069 18.4.4 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin (only for TIM15) • Internal trigger inputs (ITRx) (only for TIM15): using one timer as the prescaler for another timer, for example, you can configure TIM2 to act as a prescaler for TIM15. Refer to Using one timer as prescaler for another for more details. Internal clock source (CK_INT) For TIM15, if the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT. DocID022448 Rev 2 419/897 479 General-purpose timers (TIM15/16/17) RM0313 Figure 110 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. Figure 134. Control circuit in normal mode, internal clock divided by 1 ,QWHUQDOFORFN &(1 &17B(1 8* &17B,1,7 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 069 External clock source mode 1 This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at each rising or falling edge on a selected input. Figure 135. TI2 external clock connection example 7,0[B60&5 76>@ RU 7,) 7,) ,75[ 7,B(' 7, )LOWHU (GJH GHWHFWRU 7,)B5LVLQJ 7,)B)DOOLQJ 7,)3 7,)3 RU RU [[ 75*, &&3 7,0[B&&05 7,0[B&&(5 ([WHUQDOFORFN PRGH &.B36& &.B,17 ,&)>@ (QFRGHU PRGH LQWHUQDOFORFN ,QWHUQDOFORFN PRGH 606>@ 7,0[B60&5 069 For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: 420/897 DocID022448 Rev 2 RM0313 Note: General-purpose timers (TIM15/16/17) 1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register. 2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000). 3. Select rising edge polarity by writing CC2P=0 in the TIMx_CCER register. 4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register. 5. Select TI2 as the trigger input source by writing TS=110 in the TIMx_SMCR register. 6. Enable the counter by writing CEN=1 in the TIMx_CR1 register. The capture prescaler is not used for triggering, so you don’t need to configure it. When a rising edge occurs on TI2, the counter counts once and the TIF flag is set. The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input. Figure 136. Control circuit in external clock mode 1 7, &17B(1 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 7,) :ULWH7,) 069 18.4.5 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). Figure 113 to Figure 140 give an overview of one Capture/Compare channel. The input stage samples the corresponding TIx input to generate a filtered signal TIxF. Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS). DocID022448 Rev 2 421/897 479 General-purpose timers (TIM15/16/17) RM0313 Figure 137. Capture/compare channel (example: channel 1 input stage) 7,)B(' 7RWKHVODYHPRGHFRQWUROOHU 7, )LOWHU 7,) GRZQFRXQWHU I'76 7,)B5LVLQJ (GJH GHWHFWRU 7,)B)DOOLQJ 7,)3 7,)3 &&3&&13 ,&)>@ 75& 7,0[B&&(5 7,0[B&&05 7,)B5LVLQJ IURPFKDQQHO 7,)B)DOOLQJ IURPFKDQQHO ,& IURPVODYHPRGH FRQWUROOHU ,&36 'LYLGHU &&6>@ ,&36>@ &&( 7,0[B&&05 7,0[B&&(5 069 The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. Figure 138. Capture/compare channel 1 main circuit $3%%XV 5HDG&&5+ 6 5HDG&&5/ KLJK UHDGBLQBSURJUHVV &&6>@ ,&36 ZULWHBLQBSURJUHVV ,QSXW PRGH 6 ZULWH&&5+ &DSWXUHFRPSDUHSUHORDGUHJLVWHU 5 5 FRPSDUHBWUDQVIHU FDSWXUHBWUDQVIHU &&6>@ ORZ LIELW 0&8SHULSKHUDOLQWHUIDFH 2XWSXW PRGH &17!&&5 &RXQWHU &&* &&6>@ 8(9 &RPSDUDWRU &&( &&6>@ 2&3( &DSWXUHFRPSDUHVKDGRZUHJLVWHU &DSWXUH ZULWH&&5/ IURPWLPH EDVHXQLW 2&3( 7,0B&&05 &17 &&5 7,0B(*5 069 422/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM15/16/17) Figure 139. Output stage of capture/compare channel (channel 1) µ¶ 2&5()& &17!&&5 2XWSXW PRGH &17 &&5 FRQWUROOHU 2&B'7 'HDGWLPH JHQHUDWRU 2&5() [ 2XWSXW HQDEOH FLUFXLW 2& 2XWSXW HQDEOH FLUFXLW 2&1 &&3 7,0B&&(5 2&1B'7 µ¶ [ &&1( &&( 7,0[B&&(5 2&&( 2&0>@ '7*>@ &&1( &&( &&13 02( 266, 2665 7,0[B&&05 7,0[B%'75 7,0[B&&(5 7,0[B&&(5 7,0[B%'75 069 Figure 140. Output stage of capture/compare channel (channel 2 for TIM15) 7RWKHPDVWHU PRGHFRQWUROOHU &17!&&5 &17 &&5 2XWSXW PRGH FRQWUROOHU 2&5() 2XWSXW HQDEOH FLUFXLW 2& &&3 7,0B&&(5 2&0>@ &&( 7,0B&&(5 02( 266, 7,0B%'75 7,0B&&05 2,6 7,0B&5 DL The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register. In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter. DocID022448 Rev 2 423/897 479 General-purpose timers (TIM15/16/17) 18.4.6 RM0313 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to ‘0’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure: 1. Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00, the channel is configured in input and the TIMx_CCR1 register becomes read-only. 2. Program the input filter duration you need with respect to the signal you connect to the timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s imagine that, when toggling, the input signal is not stable during at must 5 internal clock cycles. We must program a filter duration longer than these 5 clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the new level have been detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. 3. Select the edge of the active transition on the TI1 channel by writing CC1P bit to 0 in the TIMx_CCER register (rising edge in this case). 4. Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the TIMx_CCMR1 register). 5. Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER register. 6. If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the TIMx_DIER register. When an input capture occurs: • The TIMx_CCR1 register gets the value of the counter on the active transition. • CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared. • An interrupt is generated depending on the CC1IE bit. • A DMA request is generated depending on the CC1DE bit. In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data. Note: 424/897 IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register. DocID022448 Rev 2 RM0313 18.4.7 General-purpose timers (TIM15/16/17) PWM input mode (only for TIM15) This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. • One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode. For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): 1. Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected). 2. Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P bit to ‘0’ (active on rising edge). 3. Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (TI1 selected). 4. Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P bit to ‘1’ (active on falling edge). 5. Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register (TI1FP1 selected). 6. Configure the slave mode controller in reset mode: write the SMS bits to 100 in the TIMx_SMCR register. 7. Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register. Figure 141. PWM input mode timing 7, 7,0[B&17 7,0[B&&5 7,0[B&&5 ,&FDSWXUH ,&FDSWXUH UHVHWFRXQWHU ,&FDSWXUH SXOVHZLGWK PHDVXUHPHQW ,&FDSWXUH SHULRG PHDVXUHPHQW DL 1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only TI1FP1 and TI2FP2 are connected to the slave mode controller. 18.4.8 Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. DocID022448 Rev 2 425/897 479 General-purpose timers (TIM15/16/17) RM0313 To force an output compare signal (OCXREF/OCx) to its active level, you just need to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. For example: CCxP=0 (OCx active high) => OCx is forced to high level. The OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx register. Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the output compare mode section below. 18.4.9 Output compare mode This function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function: 1. Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match. 2. Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register). 3. Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the TIMx_DIER register). 4. Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request selection). The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register. In output compare mode, the update event UEV has no effect on OCxREF and OCx output. The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One-pulse mode). Procedure: 1. Select the counter clock (internal, external, prescaler). 2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers. 3. Set the CCxIE bit if an interrupt request is to be generated. 4. 5. Select the output mode. For example: – Write OCxM = 011 to toggle OCx output pin when CNT matches CCRx – Write OCxPE = 0 to disable preload register – Write CCxP = 0 to select active high polarity – Write CCxE = 1 to enable the output Enable the counter by setting the CEN bit in the TIMx_CR1 register. The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 117. 426/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM15/16/17) Figure 142. Output compare mode, toggle on OC1 :ULWH%KLQWKH&&5UHJLVWHU 7,0B&17 7,0B&&5 % $ % % % $ RFUHI 2& 0DWFKGHWHFWHGRQ&&5 ,QWHUUXSWJHQHUDWHGLIHQDEOHG 069 18.4.10 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register. The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. You must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register. As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register. OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by a combination of the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers). Refer to the TIMx_CCER register description for more details. In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CCRx ≤TIMx_CNT or TIMx_CNT ≤TIMx_CCRx (depending on the direction of the counter). The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register. DocID022448 Rev 2 427/897 479 General-purpose timers (TIM15/16/17) RM0313 PWM edge-aligned mode • Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the Upcounting mode on page 365. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 118 shows some edge-aligned PWM waveforms in an example where TIMx_ARR=8. Figure 143. Edge-aligned PWM waveforms (ARR=8) &&5[ &RXQWHUUHJLVWHU 2&;5() &&[,) 2&;5() &&5[ &&[,) 2&;5() µ¶ &&5[! &&[,) 2&;5() µ¶ &&5[ &&[,) 069 • Downcounting configuration Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to the Repetition counter on page 418 In PWM mode 1, the reference signal OCxRef is low as long as TIMx_CNT > TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, then OCxREF is held at ‘1’. 0% PWM is not possible in this mode. 18.4.11 Complementary outputs and dead-time insertion The TIM15/16/17 general-purpose timers can output one complementary signal and manage the switching-off and switching-on of the outputs. 428/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM15/16/17) This time is generally known as dead-time and you have to adjust it depending on the devices you have connected to the outputs and their characteristics (intrinsic delays of levelshifters, delays due to power switches...) You can select the polarity of the outputs (main output OCx or complementary OCxN) independently for each output. This is done by writing to the CCxP and CCxNP bits in the TIMx_CCER register. The complementary signals OCx and OCxN are activated by a combination of several control bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx, OISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers. Refer to Table 54: Output control bits for complementary OCx and OCxN channels with break feature on page 452 for more details. In particular, the dead-time is activated when switching to the IDLE state (MOE falling down to 0). Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the break circuit is present. There is one 10-bit dead-time generator for each channel. From a reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are active high: • The OCx output signal is the same as the reference signal except for the rising edge, which is delayed relative to the reference rising edge. • The OCxN output signal is the opposite of the reference signal except for the rising edge, which is delayed relative to the reference falling edge. If the delay is greater than the width of the active output (OCx or OCxN) then the corresponding pulse is not generated. The following figures show the relationships between the output signals of the dead-time generator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1, CCxE=1 and CCxNE=1 in these examples) Figure 144. Complementary output with dead-time insertion. 2&[5() 2&[ GHOD\ 2&[1 GHOD\ 069 DocID022448 Rev 2 429/897 479 General-purpose timers (TIM15/16/17) RM0313 Figure 145. Dead-time waveforms with delay greater than the negative pulse. 2&[5() 2&[ GHOD\ 2&[1 069 Figure 146. Dead-time waveforms with delay greater than the positive pulse. 2&[5() 2&[ 2&[1 GHOD\ 069 The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 18.5.15: TIM15 break and dead-time register (TIM15_BDTR) on page 455 for delay calculation. Re-directing OCxREF to OCx or OCxN In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER register. This allows you to send a specific waveform (such as PWM or static active level) on one output while the complementary remains at its inactive level. Other alternative possibilities are to have both outputs at inactive level or both outputs active and complementary with dead-time. Note: 430/897 When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes active when OCxREF is high whereas OCxN is complemented and becomes active when OCxREF is low. DocID022448 Rev 2 RM0313 18.4.12 General-purpose timers (TIM15/16/17) Using the break function When using the break function, the output enable signals and inactive levels are modified according to additional control bits (MOE, OSSI and OSSR bits in the TIMx_BDTR register, OISx and OISxN bits in the TIMx_CR2 register). In any case, the OCx and OCxN outputs cannot be set both to active level at a given time. Refer to Table 54: Output control bits for complementary OCx and OCxN channels with break feature on page 452 for more details. The break source can be either the break input pin or a clock failure event, generated by the Clock Security System (CSS), from the Reset Clock Controller. For further information on the Clock Security System, refer to Section 7.2.7: Clock security system (CSS). When exiting from reset, the break circuit is disabled and the MOE bit is low. You can enable the break function by setting the BKE bit in the TIMx_BDTR register. The break input polarity can be selected by configuring the BKP bit in the same register. BKE and BKP can be modified at the same time. When the BKE and BKP bits are written, a delay of 1 APB clock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1 APB clock period to correctly read back the bit after the write operation. Because MOE falling edge can be asynchronous, a resynchronization circuit has been inserted between the actual signal (acting on the outputs) and the synchronous control bit (accessed in the TIMx_BDTR register). It results in some delays between the asynchronous and the synchronous signals. In particular, if you write MOE to 1 whereas it was low, you must insert a delay (dummy instruction) before reading it correctly. This is because you write the asynchronous signal and read the synchronous signal. When a break occurs (selected level on the break input): • The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or in reset state (selected by the OSSI bit). This feature functions even if the MCU oscillator is off. • Each output channel is driven with the level programmed in the OISx bit in the TIMx_CR2 register as soon as MOE=0. If OSSI=0 then the timer releases the enable output else the enable output remains high. • When complementary outputs are used: – The outputs are first put in reset state inactive state (depending on the polarity). This is done asynchronously so that it works even if no clock is provided to the timer. – If the timer clock is still present, then the dead-time generator is reactivated in order to drive the outputs with the level programmed in the OISx and OISxN bits after a dead-time. Even in this case, OCx and OCxN cannot be driven to their active level together. Note that because of the resynchronization on MOE, the dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles). – If OSSI=0 then the timer releases the enable outputs else the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high. • The break status flag (BIF bit in the TIMx_SR register) is set. An interrupt can be generated if the BIE bit in the TIMx_DIER register is set. A DMA request can be sent if the BDE bit in the TIMx_DIER register is set. • If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again at the next update event UEV. This can be used to perform a regulation, for instance. Else, MOE remains low until you write it to ‘1’ again. In this case, it can be used for security and you can connect the break input to an alarm from power drivers, thermal sensors or any security components. DocID022448 Rev 2 431/897 479 General-purpose timers (TIM15/16/17) Note: RM0313 The break inputs is acting on level. Thus, the MOE cannot be set while the break input is active (neither automatically nor by software). In the meantime, the status flag BIF cannot be cleared. The break can be generated by the BRK input which has a programmable polarity and an enable bit BKE in the TIMx_BDTR Register. In addition to the break input and the output management, a write protection has been implemented inside the break circuit to safeguard the application. It allows you to freeze the configuration of several parameters (dead-time duration, OCx/OCxN polarities and state when disabled, OCxM configurations, break enable and polarity). You can choose from 3 levels of protection selected by the LOCK bits in the TIMx_BDTR register. Refer to Section 18.5.15: TIM15 break and dead-time register (TIM15_BDTR) on page 455. The LOCK bits can be written only once after an MCU reset. The Figure 147 shows an example of behavior of the outputs in response to a break. 432/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM15/16/17) Figure 147. Output behavior in response to a break. %5($.02( 2&[5() 2&[ 2&[1QRWLPSOHPHQWHG&&[3 2,6[ 2&[ 2&[1QRWLPSOHPHQWHG&&[3 2,6[ 2&[ 2&[1QRWLPSOHPHQWHG&&[3 2,6[ 2&[ 2&[1QRWLPSOHPHQWHG&&[3 2,6[ 2&[ GHOD\ GHOD\ 2&[1 &&[( &&[3 2,6[ &&[1( &&[13 2,6[1 GHOD\ 2&[ GHOD\ GHOD\ 2&[1 &&[( &&[3 2,6[ &&[1( &&[13 2,6[1 GHOD\ 2&[ 2&[1 &&[( &&[3 2,6[ &&[1( &&[13 2,6[1 GHOD\ 2&[ 2&[1 &&[( &&[3 2,6[ &&[1( &&[13 2,6[1 GHOD\ 2&[ 2&[1 &&[( &&[3 &&[1( &&[13 2,6[ 2,6[1 RU2,6[ 2,6[1 069 DocID022448 Rev 2 433/897 479 General-purpose timers (TIM15/16/17) 18.4.13 RM0313 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. You select One-pulse mode by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV. A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be: • In upcounting: CNT < CCRx ≤ ARR (in particular, 0 < CCRx) • In downcounting: CNT > CCRx Figure 148. Example of one pulse mode. TI2 OC1REF Counter OC1 TIMx_ARR TIMx_CCR1 0 tDELAY tPULSE t For example you may want to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin. Let’s use TI2FP2 as trigger 1: 1. 434/897 Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register. 2. TI2FP2 must detect a rising edge, write CC2P=’0’ in the TIMx_CCER register. 3. Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in the TIMx_SMCR register. 4. TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register (trigger mode). DocID022448 Rev 2 RM0313 General-purpose timers (TIM15/16/17) The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The tDELAY is defined by the value written in the TIMx_CCR1 register. • The tPULSE is defined by the difference between the auto-reload value and the compare value (TIMx_ARR - TIMx_CCR1). • Let’s say you want to build a waveform with a transition from ‘0’ to ‘1’ when a compare match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload value. To do this you enable PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1 register. You can optionally enable the preload registers by writing OC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to write the compare value in the TIMx_CCR1 register, the auto-reload value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2. CC1P is written to ‘0’ in this example. In our example, the DIR and CMS bits in the TIMx_CR1 register should be low. You only want 1 pulse, so you write ‘1’ in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). Particular case: OCx fast enable In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay tDELAY min we can get. If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode. DocID022448 Rev 2 435/897 479 General-purpose timers (TIM15/16/17) 18.4.14 RM0313 TIM15 and external trigger synchronization (only for TIM15) The TIM15 timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated. In the following example, the upcounter is cleared in response to a rising edge on TI1 input: 1. Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write CC1P=0 in TIMx_CCER register to validate the polarity (and detect rising edges only). 2. Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. 3. Start the counter by writing CEN=1 in the TIMx_CR1 register. The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register). The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input. Figure 149. Control circuit in reset mode 7, 8* &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) 069 436/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM15/16/17) Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: 1. Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write CC1P=1 in TIMx_CCER register to validate the polarity (and detect low level only). 2. Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. 3. Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the counter doesn’t start if CEN=0, whatever is the trigger input level). The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops. The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input. Figure 150. Control circuit in gated mode 7, FQWBHQ &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) :ULWH7,) 069 DocID022448 Rev 2 437/897 479 General-purpose timers (TIM15/16/17) RM0313 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: 1. Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC2S bits are configured to select the input capture source only, CC2S=01 in TIMx_CCMR1 register. Write CC2P=1 in TIMx_CCER register to validate the polarity (and detect low level only). 2. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI2 as the input source by writing TS=110 in TIMx_SMCR register. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set. The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input. Figure 151. Control circuit in trigger mode 7, FQWBHQ &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) 069 18.4.15 Timer synchronization The TIM timers are linked together internally for timer synchronization or chaining. Refer to Section 16.3.15: Timer synchronization on page 331 for details. 18.4.16 Debug mode When the microcontroller enters debug mode (Cortex-M4 with FPU core halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBG module. For more details, refer to Section 31.16.2: Debug support for timers, watchdog, bxCAN and I2C. 438/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM15/16/17) 18.5 TIM15 registers Refer to Section 1.1 on page 36 for a list of abbreviations used in register descriptions. The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 18.5.1 TIM15 control register 1 (TIM15_CR1) Address offset: 0x00 Reset value: 0x0000 15 14 13 12 Res. Bits 15:10 11 10 9 8 CKD[1:0] rw rw 7 ARPE rw 6 5 Res. 4 3 2 1 0 OPM URS UDIS CEN rw rw rw rw Reserved, must be kept at reset value. Bits 9:8 CKD[1:0]: Clock division This bitfield indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS) used by the dead-time generators and the digital filters (TIx) 00: tDTS = tCK_INT 01: tDTS = 2*tCK_INT 10: tDTS = 4*tCK_INT 11: Reserved, do not program this value Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered 1: TIMx_ARR register is buffered Bits 6:4 Reserved, must be kept at reset value. Bit 3 OPM: One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) DocID022448 Rev 2 439/897 479 General-purpose timers (TIM15/16/17) RM0313 Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt if enabled. These events can be: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt if enabled Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 18.5.2 TIM15 control register 2 (TIM15_CR2) Address offset: 0x04 Reset value: 0x0000 15 14 13 Res. Bit 15:11 12 11 10 9 8 OIS2 OIS1N OIS1 rw rw rw 7 Res. 6 5 4 MMS[2:0] rw rw rw 3 2 CCDS CCUS rw rw 1 Res. 0 CCPC rw Reserved, must be kept at reset value. Bit 10 OIS2: Output idle state 2 (OC2 output) 0: OC2=0 when MOE=0 1: OC2=1 when MOE=0 Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in the TIMx_BKR register). Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BKR register). Bit 8 OIS1: Output Idle state 1 (OC1 output) 0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BKR register). 440/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM15/16/17) Bit 7 Reserved, must be kept at reset value. Bits 6:4 MMS[1:0]: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). 010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO). 100: Compare - OC1REF signal is used as trigger output (TRGO). 101: Compare - OC2REF signal is used as trigger output (TRGO). Bit 3 CCDS: Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs Bit 2 CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI. Note: This bit acts only on channels that have a complementary output. Bit 1 Reserved, must be kept at reset value. Bit 0 CCPC: Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set. Note: This bit acts only on channels that have a complementary output. DocID022448 Rev 2 441/897 479 General-purpose timers (TIM15/16/17) 18.5.3 RM0313 TIM15 slave mode control register (TIM15_SMCR) Address offset: 0x08 Reset value: 0x0000 15 14 13 12 11 Res. Bits 15:8 10 9 8 7 6 MSM rw 5 4 TS[2:0] rw rw rw 3 Res. 2 1 0 SMS[2:0] rw rw rw Reserved, must be kept at reset value. Bit 7 MSM: Master/slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. Bits 6:4 TS[2:0]: Trigger selection This bitfield selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0) 001: Internal Trigger 1 (ITR1) 010: Internal Trigger 2 (ITR2) 011: Internal Trigger 3 (ITR3) 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2) See Table 53: TIMx Internal trigger connection on page 443 for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. Bit 3 Reserved, must be kept at reset value. Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. 000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal clock. 001: Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. 010: Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. 011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. 442/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM15/16/17) Table 53. TIMx Internal trigger connection Slave TIM ITR0 (TS = 000)(1) ITR1 (TS = 001)(1) ITR2 (TS = 010) ITR3 (TS = 011) TIM15 TIM2 TIM3 TIM16 TIM17 1. ITR0 and ITR1 triggers available only in high density value line devices. DocID022448 Rev 2 443/897 479 General-purpose timers (TIM15/16/17) 18.5.4 RM0313 TIM15 DMA/interrupt enable register (TIM15_DIER) Address offset: 0x0C Reset value: 0x0000 15 Res. 14 13 TDE 12 Res. rw Bit 15 11 10 9 CC2DE CC1DE rw rw 8 7 6 5 UDE BIE TIE COMIE rw rw rw rw Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled 1: Trigger DMA request enabled Bits 13:11 Reserved, must be kept at reset value. Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled 1: CC2 DMA request enabled Bit 9 CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled 1: CC1 DMA request enabled Bit 8 UDE: Update DMA request enable 0: Update DMA request disabled 1: Update DMA request enabled Bit 7 BIE: Break interrupt enable 0: Break interrupt disabled 1: Break interrupt enabled Bit 6 TIE: Trigger interrupt enable 0: Trigger interrupt disabled 1: Trigger interrupt enabled Bit 5 COMIE: COM interrupt enable 0: COM interrupt disabled 1: COM interrupt enabled Bits 4:3 Reserved, must be kept at reset value. Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled 1: CC2 interrupt enabled Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled 444/897 DocID022448 Rev 2 4 3 Res. 2 1 0 CC2IE CC1IE UIE rw rw rw RM0313 General-purpose timers (TIM15/16/17) 18.5.5 TIM15 status register (TIM15_SR) Address offset: 0x10 Reset value: 0x0000 15 14 13 Res. Bits 15:11 12 11 10 9 8 CC2OF CC1OF rc_w0 rc_w0 Res. 7 6 5 BIF TIF COMIF rc_w0 rc_w0 4 3 Res. 2 1 0 CC2IF CC1IF UIF rc_w0 rc_w0 rc_w0 Reserved, must be kept at reset value. Bit 10 CC2OF: Capture/Compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set Bit 8 Reserved, must be kept at reset value. Bit 7 BIF: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 0: No break event occurred 1: An active level has been detected on the break input Bit 6 TIF: Trigger interrupt flag This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is cleared by software. 0: No trigger event occurred 1: Trigger interrupt pending Bit 5 COMIF: COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE, CCxNE, OCxM– have been updated). It is cleared by software. 0: No COM event occurred 1: COM interrupt pending Bits 5:3 Reserved, must be kept at reset value. DocID022448 Rev 2 445/897 479 General-purpose timers (TIM15/16/17) RM0313 Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in upcounting and up/down-counting modes) or underflow (in downcounting mode) If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1 register. 0: No input capture occurred 1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected on IC1 which matches the selected polarity) Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: – At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. – When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. – When CNT is reinitialized by a trigger event (refer to Section 18.5.3: TIM15 slave mode control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register. 18.5.6 TIM15 event generation register (TIM15_EGR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 Res. Bits 15:8 10 9 8 7 6 5 BG TG COMG w w rw 4 3 Res. 2 1 0 CC2G CC1G UG w w w Reserved, must be kept at reset value. Bit 7 BG: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled 446/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM15/16/17) Bit 5 COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits Note: This bit acts only on channels that have a complementary output. Bits 4:3 Reserved, must be kept at reset value. Bit 2 CC2G: Capture/Compare 2 generation refer to CC1G description Bit 1 CC1G: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action. 1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting). 18.5.7 TIM15 capture/compare mode register 1 (TIM15_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So you must take care that the same bit can have a different meaning for the input stage and for the output stage. 15 14 Res. 13 12 OC2M[2:0] IC2F[3:0] rw rw rw 11 10 OC2 PE OC2 FE 9 8 CC2S[1:0] 7 6 Res. rw rw 4 OC1M[2:0] IC2PSC[1:0] rw 5 IC1F[3:0] rw rw rw rw DocID022448 Rev 2 rw 3 2 OC1 PE OC1 FE 1 0 CC1S[1:0] IC1PSC[1:0] rw rw rw rw rw 447/897 479 General-purpose timers (TIM15/16/17) RM0313 Output compare mode: Bit 15 Reserved, must be kept at reset value. Bits 14:12 OC2M[2:0]: Output Compare 2 mode Bit 11 OC2PE: Output Compare 2 preload enable Bit 10 OC2FE: Output Compare 2 fast enable Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output. 01: CC2 channel is configured as input, IC2 is mapped on TI2. 10: CC2 channel is configured as input, IC2 is mapped on TI1. 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER). Bit 7 Reserved, must be kept at reset value. Bits 6:4 OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. 000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. 001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 100: Force inactive level - OC1REF is forced low. 101: Force active level - OC1REF is forced high. 110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’). 111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). 2: In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. 448/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM15/16/17) Bit 3 OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). 2: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. Bit 2 OC1FE: Output Compare 1 fast enable This bit is used to accelerate the effect of an event on the trigger in input on the CC output. 0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. 1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output. 01: CC1 channel is configured as input, IC1 is mapped on TI1. 10: CC1 channel is configured as input, IC1 is mapped on TI2. 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER). Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER). DocID022448 Rev 2 449/897 479 General-purpose timers (TIM15/16/17) RM0313 Bits 7:4 IC1F[3:0]: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS 0001: fSAMPLING=fCK_INT, N=2 0010: fSAMPLING=fCK_INT, N=4 0011: fSAMPLING=fCK_INT, N=8 0100: fSAMPLING=fDTS/2, N=6 0101: fSAMPLING=fDTS/2, N=8 0110: fSAMPLING=fDTS/4, N=6 0111: fSAMPLING=fDTS/4, N=8 1000: fSAMPLING=fDTS/8, N=6 1001: fSAMPLING=fDTS/8, N=8 1010: fSAMPLING=fDTS/16, N=5 1011: fSAMPLING=fDTS/16, N=6 1100: fSAMPLING=fDTS/16, N=8 1101: fSAMPLING=fDTS/32, N=5 1110: fSAMPLING=fDTS/32, N=6 1111: fSAMPLING=fDTS/32, N=8 Bits 3:2 IC1PSC: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events Bits 1:0 CC1S: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER). 18.5.8 TIM15 capture/compare enable register (TIM15_CCER) Address offset: 0x20 Reset value: 0x0000 15 14 13 12 11 Res. Bits 15:8 10 9 8 7 CC1NP rw 6 Res. 5 4 CC2P CC2E rw rw Reserved, must be kept at reset value. Bit 7 CC2NP: Capture/Compare 2 complementary output polarity refer to CC1NP description Bit 6 Reserved, must be kept at reset value. Bit 5 CC2P: Capture/Compare 2 output polarity refer to CC1P description 450/897 DocID022448 Rev 2 3 2 CC1NP CC1NE rw rw 1 0 CC1P CC1E rw rw RM0313 General-purpose timers (TIM15/16/17) Bit 4 CC2E: Capture/Compare 2 output enable refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 complementary output polarity 0: OC1N active high 1: OC1N active low Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output). Bit 2 CC1NE: Capture/Compare 1 complementary output enable 0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. 1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. Bit 1 CC1P: Capture/Compare 1 output polarity CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: The CC1NP/CC1P bits select the polarity of TI1FP1 and TI2FP1 for trigger or capture operations. 00: noninverted/rising edge: circuit is sensitive to TIxFP1's rising edge (capture, trigger in reset or trigger mode), TIxFP1 is not inverted (trigger in gated mode). 01: inverted/falling edge: circuit is sensitive to TIxFP1's falling edge (capture, trigger in reset, or trigger mode), TIxFP1 is inverted (trigger in gated mode). 10: reserved, do not use this configuration. 11: noninverted/both edges: circuit is sensitive to both the rising and falling edges of TIxFP1 (capture, trigger in reset or trigger mode), TIxFP1 is not inverted (trigger in gated mode). Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). Bit 0 CC1E: Capture/Compare 1 output enable CC1 channel configured as output: 0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. 1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not. 0: Capture disabled 1: Capture enabled DocID022448 Rev 2 451/897 479 General-purpose timers (TIM15/16/17) RM0313 Table 54. Output control bits for complementary OCx and OCxN channels with break feature Output states(1) Control bits MOE bit 1 0 OSSI bit OSSR bit CCxE bit CCxNE bit 0 0 0 Output Disabled (not driven by the timer) OCx=0, OCx_EN=0 Output Disabled (not driven by the timer) OCxN=0, OCxN_EN=0 0 0 1 Output Disabled (not driven by the timer) OCx=0, OCx_EN=0 OCxREF + Polarity OCxN=OCxREF xor CCxNP, OCxN_EN=1 Output Disabled (not driven by the timer) OCxN=0, OCxN_EN=0 OCx output state OCxN output state 0 1 0 OCxREF + Polarity OCx=OCxREF xor CCxP, OCx_EN=1 0 1 1 OCREF + Polarity + deadtime OCx_EN=1 Complementary to OCREF (not OCREF) + Polarity + dead-time OCxN_EN=1 1 0 0 Output Disabled (not driven by the timer) OCx=CCxP, OCx_EN=0 Output Disabled (not driven by the timer) OCxN=CCxNP, OCxN_EN=0 1 0 1 Off-State (output enabled with inactive state) OCx=CCxP, OCx_EN=1 OCxREF + Polarity OCxN=OCxREF xor CCxNP, OCxN_EN=1 1 1 0 OCxREF + Polarity OCx=OCxREF xor CCxP, OCx_EN=1 Off-State (output enabled with inactive state) OCxN=CCxNP, OCxN_EN=1 1 1 1 OCREF + Polarity + deadtime OCx_EN=1 Complementary to OCREF (not OCREF) + Polarity + dead-time OCxN_EN=1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 1 0 1 1 1 X 1 X Output Disabled (not driven by the timer) Asynchronously: OCx=CCxP, OCx_EN=0, OCxN=CCxNP, OCxN_EN=0 Then if the clock is present: OCx=OISx and OCxN=OISxN after a dead-time, assuming that OISx and OISxN do not correspond to OCX and OCxN both in active state. Off-State (output enabled with inactive state) Asynchronously: OCx=CCxP, OCx_EN=1, OCxN=CCxNP, OCxN_EN=1 Then if the clock is present: OCx=OISx and OCxN=OISxN after a dead-time, assuming that OISx and OISxN do not correspond to OCX and OCxN both in active state 1. When both outputs of a channel are not used (CCxE = CCxNE = 0), the OISx, OISxN, CCxP and CCxNP bits must be kept cleared. Note: 452/897 The state of the external I/O pins connected to the complementary OCx and OCxN channels depends on the OCx and OCxN channel state and the GPIO and AFIO registers. DocID022448 Rev 2 RM0313 General-purpose timers (TIM15/16/17) 18.5.9 TIM15 counter (TIM15_CNT) Address offset: 0x24 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CNT[15:0] rw rw rw Bits 15:0 18.5.10 rw rw rw rw rw CNT[15:0]: Counter value TIM15 prescaler (TIM15_PSC) Address offset: 0x28 Reset value: 0x0000 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw rw PSC[15:0] rw Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”). 18.5.11 TIM15 auto-reload register (TIM15_ARR) Address offset: 0x2C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw ARR[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 ARR[15:0]: Prescaler value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 17.4.1: Time-base unit on page 363 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. DocID022448 Rev 2 453/897 479 General-purpose timers (TIM15/16/17) 18.5.12 RM0313 TIM15 repetition counter register (TIM15_RCR) Address offset: 0x30 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw REP[7:0] Res. rw rw rw rw rw Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode. 18.5.13 TIM15 capture/compare register 1 (TIM15_CCR1) Address offset: 0x34 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CCR1[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). 454/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM15/16/17) 18.5.14 TIM15 capture/compare register 2 (TIM15_CCR2) Address offset: 0x38 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CCR2[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). 18.5.15 TIM15 break and dead-time register (TIM15_BDTR) Address offset: 0x44 Reset value: 0x0000 15 14 13 12 11 10 MOE AOE BKP BKE OSSR OSSI rw rw rw rw rw rw Note: 9 8 7 6 5 LOCK[1:0] rw rw 4 3 2 1 0 rw rw rw DTG[7:0] rw rw rw rw rw As the bits AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. DocID022448 Rev 2 455/897 479 General-purpose timers (TIM15/16/17) RM0313 Bit 15 MOE: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. 0: OC and OCN outputs are disabled or forced to idle state 1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register) See OC/OCN enable description for more details (Section 18.5.8: TIM15 capture/compare enable register (TIM15_CCER) on page 450). Bit 14 AOE: Automatic output enable 0: MOE can be set only by software 1: MOE can be set by software or automatically at the next update event (if the break input is not be active) Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 13 BKP: Break polarity 0: Break input BRK is active low 1: Break input BRK is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. Bit 12 BKE: Break enable 0: Break inputs (BRK and CCS clock failure event) disabled 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. Bit 11 OSSR: Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (Section 18.5.8: TIM15 capture/compare enable register (TIM15_CCER) on page 450). 0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) 1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1. Then, OC/OCN enable output signal=1 Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). 456/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM15/16/17) Bit 10 OSSI: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (Section 18.5.8: TIM15 capture/compare enable register (TIM15_CCER) on page 450). 0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) 1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1) Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). Bits 9:8 LOCK[1:0]: Lock configuration These bits offer a write protection against software errors. 00: LOCK OFF - No bit is write protected 01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written 10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. 11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. Bits 7:0 DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 18.5.16 TIM15 DMA control register (TIM15_DCR) Address offset: 0x48 Reset value: 0x0000 15 14 13 12 11 Res. Res. 10 9 8 DBL[4:0] rw rw rw 7 6 5 4 3 Res. rw rw Res. DocID022448 Rev 2 2 1 0 rw rw DBA[4:0] rw rw rw 457/897 479 General-purpose timers (TIM15/16/17) RM0313 Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). 00000: 1 transfer, 00001: 2 transfers, 00010: 3 transfers, ... 10001: 18 transfers. Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 DBA[4:0]: DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2, 00010: TIMx_SMCR, ... 18.5.17 TIM15 DMA address for full transfer (TIM15_DMAR) Address offset: 0x4C Reset value: 0x0000 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DMAB[15:0] rw rw Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 458/897 DocID022448 Rev 2 0x28 TIM15_PSC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIM15_CNT Res. 0x24 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIM15_CCER Res. 0x20 Res. Reset value Reset value DocID022448 Rev 2 0 0 0 0 Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC2 PSC [1:0] CC2 S [1:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT[15:0] 0 0 0 PSC[15:0] 0 CC1E CC2 S [1:0] Res. 0 0 0 0 0 0 0 IC1F[3:0] UG 0 CC1G OC1M [2:0] CC2IF CC1IF UIF 0 0 0 0 0 CC1IE UIE Res. 0 CC2IE OPM URS UDIS CEN 0 0 0 CCDS CCUS Res. CCPC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 Res. TS[2:0] CC2G Res. 0 0 0 0 OC1FE 0 Res. Res. 0 Res. TI1S 0 0 Res. ARPE OIS1 0 MSM Res. OIS1N OIS2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MMS[2:0 ] OC1PE 0 Res. COMIE 0 COMIF 0 COMG TIE 0 TIF BIE 0 TG UDE 0 BIF Res. 0 BG Reset value Res. Res. Res. CC1DE CC1OF 0 CC2DE CC2OF Res. 0 Res. Reset value CC1P IC2F[3:0] Res. Res. Res. Reset value CC1NE 0 OC2FE OC2M [2:0] OC2PE Res. 0 0 CC2E 0 Res. Res. TDE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIM15_CR2 Res. 0 Res. 0 CC1NP 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value CC2P Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CKD [1:0] 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value CC2NP 0 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIM15_CCMR 1 Input Capture mode Res. TIM15_CCMR 1 Output Compare mode Res. TIM15_EGR Res. 0x14 Res. TIM15_SR Res. 0x10 Res. TIM15_DIER Res. 0x0C Res. TIM15_SMCR Res. 0x08 Res. 0x04 Res. 0x00 Res. TIM15_CR1 Res. 0x18 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. 18.5.18 Res. RM0313 General-purpose timers (TIM15/16/17) TIM15 register map TIM15 registers are mapped as 16-bit addressable registers as described in the table below: Table 55. TIM15 register map and reset values SMS[2:0] 0 0 0 0 0 0 0 CC1 S [1:0] 0 0 0 0 IC1 PSC [1:0] CC1 S [1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 459/897 479 460/897 0x4C TIM15_DMAR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIM15_DCR Res. 0x48 Reset value DocID022448 Rev 2 AOE BKP BKE OSSR OSSI Reset value LOC K [1:0] 0 0 0 0 0 0 0 Res. 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBL[4:0] 0 Refer to Section 2.2.2 on page 41 for the register boundary addresses. 0 0 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value MOE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x44 Res. TIM15_BDTR Res. TIM15_CCR2 Res. 0x38 Res. TIM15_CCR1 Res. 0x34 Res. TIM15_RCR Res. 0x30 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIM15_ARR Res. 0x2C Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. General-purpose timers (TIM15/16/17) RM0313 Table 55. TIM15 register map and reset values (continued) ARR[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR1[15:0] CCR2[15:0] DT[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REP[7:0] DBA[4:0] DMAB[15:0] 0 0 0 0 0 0 0 0 0 0 RM0313 General-purpose timers (TIM15/16/17) 18.6 TIM16&TIM17 registers Refer to Section 1.1 on page 36 for a list of abbreviations used in register descriptions. The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 18.6.1 TIM16&TIM17 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 15 14 13 12 Res. 11 10 9 8 CKD[1:0] rw 7 ARPE rw rw 6 5 Res. 4 3 2 1 0 OPM URS UDIS CEN rw rw rw rw Bits 15:10 Reserved, must be kept at reset value. Bits 9:8 CKD[1:0]: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx), 00: tDTS=tCK_INT 01: tDTS=2*tCK_INT 10: tDTS=4*tCK_INT 11: Reserved, do not program this value Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered 1: TIMx_ARR register is buffered Bits 6:4 Reserved, must be kept at reset value. Bit 3 OPM: One pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) DocID022448 Rev 2 461/897 479 General-purpose timers (TIM15/16/17) RM0313 Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled. Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled 18.6.2 TIM16&TIM17 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 15 14 13 12 Res. Bits 15:10 11 10 9 8 OIS1N OIS1 rw rw 7 6 5 Res. 4 3 2 CCDS CCUS rw rw 1 Res. 0 CCPC rw Reserved, must be kept at reset value. Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BKR register). Bit 8 OIS1: Output Idle state 1 (OC1 output) 0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BKR register). Bits 7:4 Reserved, must be kept at reset value. Bit 3 CCDS: Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs 462/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM15/16/17) Bit 2 CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI. Note: This bit acts only on channels that have a complementary output. Bit 1 Reserved, must be kept at reset value. Bit 0 CCPC: Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set. Note: This bit acts only on channels that have a complementary output. DocID022448 Rev 2 463/897 479 General-purpose timers (TIM15/16/17) 18.6.3 RM0313 TIM16&TIM17 DMA/interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 15 Res. 14 Res. 13 12 11 Res. 10 9 8 7 CC1DE UDE BIE rw rw rw 6 Res Bit 15 Reserved, must be kept at reset value. Bit 14 Reserved, always read as 0. Bits 13:10 Reserved, must be kept at reset value. Bit 9 CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled 1: CC1 DMA request enabled Bit 8 UDE: Update DMA request enable 0: Update DMA request disabled 1: Update DMA request enabled Bit 7 BIE: Break interrupt enable 0: Break interrupt disabled 1: Break interrupt enabled Bit 6 Reserved, always read as 0. Bit 5 COMIE: COM interrupt enable 0: COM interrupt disabled 1: COM interrupt enabled Bits 4:2 Reserved, must be kept at reset value. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled 464/897 DocID022448 Rev 2 5 COMIE rw 4 3 Res. 2 1 0 CC1IE UIE rw rw RM0313 General-purpose timers (TIM15/16/17) 18.6.4 TIM16&TIM17 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 15 14 13 12 Res. 11 10 9 8 CC1OF rc_w0 Res. 7 BIF rc_w0 6 Res 5 COMIF rc_w0 4 3 Res. 2 1 0 CC1IF UIF rc_w0 rc_w0 Bits 15:10 Reserved, must be kept at reset value. Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set Bit 8 Reserved, must be kept at reset value. Bit 7 BIF: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 0: No break event occurred 1: An active level has been detected on the break input Bit 6 Reserved, always read as 0. Bit 5 COMIF: COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE, CCxNE, OCxM– have been updated). It is cleared by software. 0: No COM event occurred 1: COM interrupt pending DocID022448 Rev 2 465/897 479 General-purpose timers (TIM15/16/17) RM0313 Bits 4:2 Reserved, must be kept at reset value. Bit 1 CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in upcounting and up/down-counting modes) or underflow (in downcounting mode) If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1 register. 0: No input capture occurred 1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected on IC1 which matches the selected polarity) Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: – At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. – When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. 18.6.5 TIM16&TIM17 event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 BG Res. w 6 Res 5 COMG w 4 3 Res. 2 1 0 CC1G UG w w Bits 15:8 Reserved, must be kept at reset value. Bit 7 BG: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action. 1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. Bit 6 Reserved, always read as 0. Bit 5 COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits Note: This bit acts only on channels that have a complementary output. 466/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM15/16/17) Bits 4:2 Reserved, must be kept at reset value. Bit 1 CC1G: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action. 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action. 1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting). 18.6.6 TIM16&TIM17 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So you must take care that the same bit can have a different meaning for the input stage and for the output stage. 15 14 13 12 11 10 9 8 7 6 Res. 5 4 OC1M[2:0] Res. IC1F[3:0] rw rw DocID022448 Rev 2 rw 3 2 OC1PE OC1FE IC1PSC[1:0] rw rw rw 1 0 CC1S[1:0] rw rw 467/897 479 General-purpose timers (TIM15/16/17) RM0313 Output compare mode: Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. 000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. 001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 100: Force inactive level - OC1REF is forced low. 101: Force active level - OC1REF is forced high. 110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’). 111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). 2: In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. 468/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM15/16/17) Bit 3 OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). 2: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. Bit 2 OC1FE: Output Compare 1 fast enable This bit is used to accelerate the effect of an event on the trigger in input on the CC output. 0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. 1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode. Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER). DocID022448 Rev 2 469/897 479 General-purpose timers (TIM15/16/17) RM0313 Input capture mode Bits 15:8 Reserved, must be kept at reset value. Bits 7:4 IC1F[3:0]: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS 0001: fSAMPLING=fCK_INT, N=2 0010: fSAMPLING=fCK_INT, N=4 0011: fSAMPLING=fCK_INT, N=8 0100: fSAMPLING=fDTS/2, N= 0101: fSAMPLING=fDTS/2, N=8 0110: fSAMPLING=fDTS/4, N=6 0111: fSAMPLING=fDTS/4, N=8 1000: fSAMPLING=fDTS/8, N=6 1001: fSAMPLING=fDTS/8, N=8 1010: fSAMPLING=fDTS/16, N=5 1011: fSAMPLING=fDTS/16, N=6 1100: fSAMPLING=fDTS/16, N=8 1101: fSAMPLING=fDTS/32, N=5 1110: fSAMPLING=fDTS/32, N=6 1111: fSAMPLING=fDTS/32, N=8 Bits 3:2 IC1PSC: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input. 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events Bits 1:0 CC1S: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER). 18.6.7 TIM16&TIM17 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 5 4 3 2 CC1NP CC1NE Res. 470/897 6 rw DocID022448 Rev 2 rw 1 0 CC1P CC1E rw rw RM0313 General-purpose timers (TIM15/16/17) Bits 15:4 Reserved, must be kept at reset value. Bit 3 CC1NP: Capture/Compare 1 complementary output polarity 0: OC1N active high 1: OC1N active low Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output). Bit 2 CC1NE: Capture/Compare 1 complementary output enable 0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. 1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. Bit 1 CC1P: Capture/Compare 1 output polarity CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: The CC1NP/CC1P bits select the polarity of TI1FP1 and TI2FP1 for capture operation. 00: Non-inverted/rising edge: circuit is sensitive to TIxFP1's rising edge TIxFP1 is not inverted. 01: Inverted/falling edge: circuit is sensitive to TIxFP1's falling edge, TIxFP1 is inverted. 10: Reserved, do not use this configuration. 11: Non-inverted/both edges: circuit is sensitive to both the rising and falling edges of TIxFP1, TIxFP1 is not inverted. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) Bit 0 CC1E: Capture/Compare 1 output enable CC1 channel configured as output: 0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. 1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not. 0: Capture disabled 1: Capture enabled DocID022448 Rev 2 471/897 479 General-purpose timers (TIM15/16/17) RM0313 Table 56. Output control bits for complementary OCx and OCxN channels with break feature Output states(1) Control bits MOE OSSI OSSR CCxE CCxNE bit bit bit bit bit 1 0 OCx output state OCxN output state 0 0 0 Output Disabled (not driven by the timer) OCx=0, OCx_EN=0 Output Disabled (not driven by the timer) OCxN=0, OCxN_EN=0 0 0 1 Output Disabled (not driven by the timer) OCx=0, OCx_EN=0 OCxREF + Polarity OCxN=OCxREF xor CCxNP, OCxN_EN=1 Output Disabled (not driven by the timer) OCxN=0, OCxN_EN=0 0 1 0 OCxREF + Polarity OCx=OCxREF xor CCxP, OCx_EN=1 0 1 1 OCREF + Polarity + deadtime OCx_EN=1 Complementary to OCREF (not OCREF) + Polarity + dead-time OCxN_EN=1 1 0 0 Output Disabled (not driven by the timer) OCx=CCxP, OCx_EN=0 Output Disabled (not driven by the timer) OCxN=CCxNP, OCxN_EN=0 1 0 1 Off-State (output enabled with inactive state) OCx=CCxP, OCx_EN=1 OCxREF + Polarity OCxN=OCxREF xor CCxNP, OCxN_EN=1 1 1 0 OCxREF + Polarity OCx=OCxREF xor CCxP, OCx_EN=1 Off-State (output enabled with inactive state) OCxN=CCxNP, OCxN_EN=1 1 1 1 OCREF + Polarity + deadtime OCx_EN=1 Complementary to OCREF (not OCREF) + Polarity + dead-time OCxN_EN=1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 1 0 1 1 1 X 1 X Output Disabled (not driven by the timer) Asynchronously: OCx=CCxP, OCx_EN=0, OCxN=CCxNP, OCxN_EN=0 Then if the clock is present: OCx=OISx and OCxN=OISxN after a dead-time, assuming that OISx and OISxN do not correspond to OCX and OCxN both in active state. Off-State (output enabled with inactive state) Asynchronously: OCx=CCxP, OCx_EN=1, OCxN=CCxNP, OCxN_EN=1 Then if the clock is present: OCx=OISx and OCxN=OISxN after a dead-time, assuming that OISx and OISxN do not correspond to OCX and OCxN both in active state 1. When both outputs of a channel are not used (CCxE = CCxNE = 0), the OISx, OISxN, CCxP and CCxNP bits must be kept cleared. 472/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM15/16/17) Note: The state of the external I/O pins connected to the complementary OCx and OCxN channels depends on the OCx and OCxN channel state and the GPIO and AFIO registers. 18.6.8 TIM16&TIM17 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CNT[15:0] rw rw rw Bits 15:0 18.6.9 rw rw rw rw rw rw CNT[15:0]: Counter value TIM16&TIM17 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 PSC[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”). 18.6.10 TIM16&TIM17 auto-reload register (TIMx_ARR) Address offset: 0x2C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw ARR[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 ARR[15:0]: Prescaler value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 17.4.1: Time-base unit on page 363 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. DocID022448 Rev 2 473/897 479 General-purpose timers (TIM15/16/17) 18.6.11 RM0313 TIM16&TIM17 repetition counter register (TIMx_RCR) Address offset: 0x30 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw REP[7:0] Res. rw rw rw rw rw Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode. 18.6.12 TIM16&TIM17 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CCR1[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). 474/897 DocID022448 Rev 2 RM0313 General-purpose timers (TIM15/16/17) 18.6.13 TIM16&TIM17 break and dead-time register (TIMx_BDTR) Address offset: 0x44 Reset value: 0x0000 15 14 13 12 11 10 MOE AOE BKP BKE OSSR OSSI rw rw rw rw rw rw Note: 9 8 7 6 5 LOCK[1:0] rw rw 4 3 2 1 0 rw rw rw DTG[7:0] rw rw rw rw rw As the bits AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. Bit 15 MOE: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. 0: OC and OCN outputs are disabled or forced to idle state 1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register) See OC/OCN enable description for more details (Section 18.5.8: TIM15 capture/compare enable register (TIM15_CCER) on page 450). Bit 14 AOE: Automatic output enable 0: MOE can be set only by software 1: MOE can be set by software or automatically at the next update event (if the break input is not be active) Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Bit 13 BKP: Break polarity 0: Break input BRK is active low 1: Break input BRK is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. Bit 12 BKE: Break enable 0: Break inputs (BRK and CCS clock failure event) disabled 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. Bit 11 OSSR: Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (Section 18.5.8: TIM15 capture/compare enable register (TIM15_CCER) on page 450). 0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) 1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1. Then, OC/OCN enable output signal=1 Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). DocID022448 Rev 2 475/897 479 General-purpose timers (TIM15/16/17) RM0313 Bit 10 OSSI: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (Section 18.5.8: TIM15 capture/compare enable register (TIM15_CCER) on page 450). 0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) 1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1) Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). Bits 9:8 LOCK[1:0]: Lock configuration These bits offer a write protection against software errors. 00: LOCK OFF - No bit is write protected 01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written. 10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. 11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. Bits 7:0 DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 18.6.14 TIM16&TIM17 DMA control register (TIMx_DCR) Address offset: 0x48 Reset value: 0x0000 15 14 Res. 476/897 13 12 11 10 9 8 DBL[4:0] rw rw rw rw rw 7 6 Res. DocID022448 Rev 2 5 4 3 2 1 0 rw rw DBA[4:0] rw rw rw RM0313 General-purpose timers (TIM15/16/17) Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). 00000: 1 transfer, 00001: 2 transfers, 00010: 3 transfers, ... 10001: 18 transfers. Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 DBA[4:0]: DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2, 00010: TIMx_SMCR, ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. 18.6.15 TIM16&TIM17 DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DMAB[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write access to the DMAR register accesses the register located at the address: “(TIMx_CR1 address) + DBA + (DMA index)” in which: TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is the offset automatically controlled by the DMA transfer, depending on the length of the transfer DBL in the TIMx_DCR register. Example of how to use the DMA burst feature In this example the timer DMA burst feature is used to update the contents of the CCRx registers (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers. This is done in the following steps: DocID022448 Rev 2 477/897 479 General-purpose timers (TIM15/16/17) 1. RM0313 Configure the corresponding DMA channel as follows: – DMA channel peripheral address is the DMAR register address – DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers. – Number of data to transfer = 3 (See note below). – Circular mode disabled. 2. Configure the DCR register by configuring the DBA and DBL bit fields as follows: DBL = 3 transfers, DBA = 0xE. 3. Enable the TIMx update DMA request (set the UDE bit in the DIER register). 4. Enable TIMx 5. Enable the DMA channel Note: This example is for the case where every CCRx register to be updated once. If every CCRx register is to be updated twice for example, the number of data to transfer should be 6. Let's take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and data6. The data is transferred to the CCRx registers as follows: on the first update DMA request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is transferred to CCR3 and data6 is transferred to CCR4. 18.6.16 TIM16&TIM17 register map TIM16&TIM17 registers are mapped as 16-bit addressable registers as described in the table below: 478/897 URS UDIS CEN Res. CCPC UIE UIF 0 0 0 UG CCUS CC1IE Res. Res. Res. Res. 0 CC1IF 0 Res. COMG Res. BG Res. 0 0 CC1G Res. OPM CCDS Res. 0 Res. Res. Res. Res. 0 Res. Res. 0 Res. TI1S 0 Res. OIS1 0 BIE 0 UDE 0 BIF 0 Res. 0 Res. Res. Res. Res. Res. Res. 0 0 0 DocID022448 Rev 2 Res. ARPE Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_EGR Res. 0x14 0 0 0 Res. Reset value 0 OIS1N Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_SR Res. 0x10 Res. Reset value 0 MMS[2:0 ] CC1DE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_DIER Res. 0x0C Res. Reset value 0 CC1OF Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_CR2 Res. 0 Res. 0 Res. Reset value Res. 0x04 CKD [1:0] TIMx_CR1 Res. 0x00 Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 57. TIM16&TIM17 register map and reset values 0 0 0x4C TIMx_DMAR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_DCR Res. 0x48 Reset value DocID022448 Rev 2 BKP BKE OSSR OSSI LOC K [1:0] 0 0 0 0 0 0 0 Res. Reset value AOE 0 0 0 0 0 Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0 0 DBL[4:0] 0 0 0 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC1F[3:0] Reset value CCR1[15:0] DT[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OC1PE OC1FE 0 IC1 PSC [1:0] CC1 S [1:0] 0 0 0 0 0 CC1E 0 CC1P 0 CC1NE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OC1M [2:0] CC1NP Reset value Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Reset value 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value MOE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_BDTR Res. 0x44 TIMx_CCR1 Res. 0x34 TIMx_RCR Res. 0x30 TIMx_ARR Res. 0x2C TIMx_PSC Res. 0x28 TIMx_CNT Res. 0x24 TIMx_CCER Res. 0x20 Res. TIMx_CCMR1 Input Capture mode Res. TIMx_CCMR1 Output Compare mode Res. 0x18 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. RM0313 General-purpose timers (TIM15/16/17) Table 57. TIM16&TIM17 register map and reset values (continued) CC1 S [1:0] 0 0 0 0 0 0 0 0 0 CNT[15:0] PSC[15:0] ARR[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REP[7:0] DBA[4:0] DMAB[15:0] 0 0 0 0 0 0 0 0 0 0 Refer to Section 2.2.2 on page 41 for the register boundary addresses. 479/897 479 Infrared interface (IRTIM) 19 RM0313 Infrared interface (IRTIM) An infrared interface (IRTIM) for remote control is available on the device. It can be used with an infrared LED to perform remote control functions. It uses internal connections with TIM16 and TIM17 as shown in Figure 152. To generate the infrared remote control signals, the IR interface must be enabled and TIM16 channel 1 (TIM16_OC1) and TIM17 channel 1 (TIM17_OC1) must be properly configured to generate correct waveforms. The infrared receiver can be implemented easily through a basic input capture mode. Figure 152. IR internal hardware connections with TIM16 and TIM17 4)-?#( )24)- )2?/54 4)-?#( -36 19.1 Main features All standard IR pulse modulation modes can be obtained by programming the two timer output compare channels. TIM16 is used to generate the high frequency carrier signal, while TIM17 generates the modulation envelope. The infrared function is output on the IR_OUT pin. The activation of this function is done through the GPIOx_AFRx register by enabling the related alternate function bit. The high sink LED driver capability (only available on the PB9 pin) can be activated through the I2C_PB9_FM+ bit in the SYS_CTRL register and used to sink the high current needed to directly control an infrared LED. 480/897 DocID022448 Rev 2 RM0313 Basic timers (TIM6/7/18) 20 Basic timers (TIM6/7/18) 20.1 Introduction The basic timers TIM6,TIM7, and TIM18 consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used as generic timers for time-base generation but they are also specifically used to drive the digital-to-analog converter (DAC). In fact, the timers are internally connected to the DAC and are able to drive it through their trigger outputs. The timers are completely independent, and do not share any resources. 20.2 TIM6/7/18 main features Basic timer (TIM6/TIM7/TIM18) features include: • 16-bit auto-reload upcounter • 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65536 • Synchronization circuit to trigger the DAC • Interrupt/DMA generation on the update event: counter overflow Figure 153. Basic timer block diagram 7ULJJHU FRQWUROOHU ,QWHUQDOFORFN&.B,17 7,0[&/.IURP5&& &RQWURO &.B&17 5HVHWHQDEOH&RXQW 8, 6WRSFOHDURUXS 36& SUHVFDOHU WR'$& $XWRUHORDGUHJLVWHU 8 &.B36& 75*2 8 &17FRXQWHU 1RWHV 5HJ 3UHORDGUHJLVWHUVWUDQVIHUUHG WRDFWLYHUHJLVWHUVRQ8HYHQW DFFRUGLQJWRFRQWUROELW (YHQW ,QWHUUXSW'0$RXWSXW 069 DocID022448 Rev 2 481/897 493 Basic timers (TIM6/7/18) RM0313 20.3 TIM6/7/18 functional description 20.3.1 Time-base unit The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running. The time-base unit includes: • Counter Register (TIMx_CNT) • Prescaler Register (TIMx_PSC) • Auto-Reload Register (TIMx_ARR) The auto-reload register is preloaded. The preload register is accessed each time an attempt is made to write or read the auto-reload register. The contents of the preload register are transferred into the shadow register permanently or at each update event UEV, depending on the auto-reload preload enable bit (ARPE) in the TIMx_CR1 register. The update event is sent when the counter reaches the overflow value and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration. The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in the TIMx_CR1 register is set. Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN. Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as the TIMx_PSC control register is buffered. The new prescaler ratio is taken into account at the next update event. Figure 154 and Figure 155 give some examples of the counter behavior when the prescaler ratio is changed on the fly. 482/897 DocID022448 Rev 2 RM0313 Basic timers (TIM6/7/18) Figure 154. Counter timing diagram with prescaler division change from 1 to 2 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 Figure 155. Counter timing diagram with prescaler division change from 1 to 4 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 DocID022448 Rev 2 483/897 493 Basic timers (TIM6/7/18) 20.3.2 RM0313 Counting mode The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An update event can be generate at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller). The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This avoids updating the shadow registers while writing new values into the preload registers. In this way, no update event occurs until the UDIS bit has been written to 0, however, the counter and the prescaler counter both restart from 0 (but the prescale rate does not change). In addition, if the URS (update request selection) bit in the TIMx_CR1 register is set, setting the UG bit generates an update event UEV, but the UIF flag is not set (so no interrupt or DMA request is sent). When an update event occurs, all the registers are updated and the update flag (UIF bit in the TIMx_SR register) is set (depending on the URS bit): • The buffer of the prescaler is reloaded with the preload value (contents of the TIMx_PSC register) • The auto-reload shadow register is updated with the preload value (TIMx_ARR) The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR = 0x36. Figure 156. Counter timing diagram, internal clock divided by 1 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 484/897 DocID022448 Rev 2 RM0313 Basic timers (TIM6/7/18) Figure 157. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 158. Counter timing diagram, internal clock divided by 4 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 DocID022448 Rev 2 485/897 493 Basic timers (TIM6/7/18) RM0313 Figure 159. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 160. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )) :ULWHDQHZYDOXHLQ7,0[B$55 069 486/897 DocID022448 Rev 2 RM0313 Basic timers (TIM6/7/18) Figure 161. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) ) ) ) &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU ) $XWRUHORDGVKDGRZ UHJLVWHU ) :ULWHDQHZYDOXHLQ7,0[B$55 20.3.3 069 Clock source The counter clock is provided by the Internal clock (CK_INT) source. The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except for UG that remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT. Figure 162 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. DocID022448 Rev 2 487/897 493 Basic timers (TIM6/7/18) RM0313 Figure 162. Control circuit in normal mode, internal clock divided by 1 ,QWHUQDOFORFN &(1 &17B(1 8* &17B,1,7 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 069 20.3.4 Debug mode When the microcontroller enters the debug mode (Cortex-M4 with FPU core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP configuration bit in the DBG module. For more details, refer to Section 31.16.2: Debug support for timers, watchdog, bxCAN and I2C. 20.4 TIM6/7/18 registers Refer to Section 1.1: List of abbreviations for registers for a list of abbreviations used in register descriptions. The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 20.4.1 TIM6/7/18 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 15 14 13 12 11 Res. 10 9 8 7 ARPE rw Bits 15:8 Reserved, must be kept at reset value. Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered. 1: TIMx_ARR register is buffered. Bits 6:4 Reserved, must be kept at reset value. 488/897 DocID022448 Rev 2 6 5 Res. 4 3 2 1 0 OPM URS UDIS CEN rw rw rw rw RM0313 Basic timers (TIM6/7/18) Bit 3 OPM: One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the CEN bit). Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt or DMA request if enabled. These events can be: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled. Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. DocID022448 Rev 2 489/897 493 Basic timers (TIM6/7/18) 20.4.2 RM0313 TIM6/7/18 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 MMS[2:0] Res. rw rw 1 0 Res. rw Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 MMS: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). 010: Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. Bits 3:0 Reserved, must be kept at reset value. 20.4.3 TIM6/7/18 DMA/Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 UDE Res. rw Bit 15:9 Reserved, must be kept at reset value. Bit 8 UDE: Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled. Bit 7:1 Reserved, must be kept at reset value. Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled. 490/897 DocID022448 Rev 2 6 5 4 Res. 3 2 1 0 UIE rw RM0313 Basic timers (TIM6/7/18) 20.4.4 TIM6/7/18 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UIF Res. rc_w0 Bits 15:1 Reserved, must be kept at reset value. Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: – At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. – When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register. 20.4.5 TIM6/7/18 event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UG Res. w Bits 15:1 Reserved, must be kept at reset value. Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action. 1: Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected). 20.4.6 TIM6/7/18 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CNT[15:0] rw rw Bits 15:0 rw rw rw rw rw rw rw CNT[15:0]: Counter value DocID022448 Rev 2 491/897 493 Basic timers (TIM6/7/18) 20.4.7 RM0313 TIM6/7/18 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw PSC[15:0] rw Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded into the active prescaler register at each update event. 20.4.8 TIM6/7/18 auto-reload register (TIMx_ARR) Address offset: 0x2C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw ARR[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 ARR[15:0]: Auto-reload value ARR is the value to be loaded into the actual auto-reload register. Refer to Section 20.3.1: Time-base unit on page 482 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. 492/897 DocID022448 Rev 2 0x2C TIMx_ARR 0x1C Res. 0x20 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x18 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Reset value Reset value DocID022448 Rev 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value Reset value UIF Res. Res. 0 UG Res. Res. Res. Res. Res. Res. UIE URS UDIS CEN OPM Res. Res. Res. ARPE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. 0 Res. 0 Res. Res. 0 Res. MMS[2:0 ] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Reset value Res. Res. UDE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x08 Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_PSC Res. 0x28 TIMx_CNT Res. 0x24 TIMx_EGR Res. 0x14 TIMx_SR Res. 0x10 TIMx_DIER Res. 0x0C TIMx_CR2 Res. 0x04 TIMx_CR1 Res. 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. 20.4.9 Res. RM0313 Basic timers (TIM6/7/18) TIM6/7/18 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 58. TIM6/7/18 register map and reset values 0 0 0 0 0 0 CNT[15:0] PSC[15:0] ARR[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Refer to Table 1 on page 43 for the register boundary addresses. 493/897 493 Independent watchdog (IWDG) RM0313 21 Independent watchdog (IWDG) 21.1 Introduction The devices feature an embedded watchdog peripheral which offers a combination of high safety level, timing accuracy and flexibility of use. The Independent watchdog peripheral serves to detect and resolve malfunctions due to software failure, and to trigger system reset when the counter reaches a given timeout value. The independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (LSI) and thus stays active even if the main clock fails. The IWDG is best suited to applications which require the watchdog to run as a totally independent process outside the main application, but have lower timing accuracy constraints. For further information on the window watchdog, refer to Section 22 on page 502. 21.2 IWDG main features • 21.3 Free-running downcounter • Clocked from an independent RC oscillator (can operate in Standby and Stop modes) • Conditional Reset – Reset (if watchdog activated) when the downcounter value becomes less than 000h – Reset (if watchdog activated) if the downcounter is reloaded outside the window IWDG functional description Figure 163 shows the functional blocks of the independent watchdog module. When the independent watchdog is started by writing the value 0x0000 CCCC in the Key register (IWDG_KR), the counter starts counting down from the reset value of 0xFFF. When it reaches the end of count value (0x000) a reset signal is generated (IWDG reset). Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, the IWDG_RLR value is reloaded in the counter and the watchdog reset is prevented. 21.3.1 Window option The IWDG can also work as a window watchdog by setting the appropriate window in the IWDG_WINR register. If the reload operation is performed while the counter is greater than the value stored in the window register (IWDG_WINR), then a reset is provided. The default value of the IWDG_WINR is 0x0000 0FFF, so if it is not updated, the window option is disabled. As soon as the window value is changed, a reload operation is performed in order to reset the downcounter to the IWDG_RLR value and ease the cycle number calculation to generate the next reload. 494/897 DocID022448 Rev 2 RM0313 Independent watchdog (IWDG) Configuring the IWDG when the window option is enabled Note: 1. Enable the IWDG by writing 0x0000 CCCC in the IWDG_KR register. 2. Enable register access by writing 0x0000 5555 in the IWDG_KR register. 3. Write the IWDG prescaler by programming IWDG_PR from 0 to 7. 4. Write the reload register (IWDG_RLR). 5. Wait for the registers to be updated (IWDG_SR = 0x0000 0000). 6. Write to the window register IWDG_WINR. This automatically refreshes the counter value IWDG_RLR. Writing the window value allows to refresh the Counter value by the RLR when IWDG_SR to set to 0x0000 0000. Configuring the IWDG when the window option is disabled When the window option it is not used, the IWDG can be configured as follows: 1. 21.3.2 Enable register access by writing 0x0000 5555 in the IWDG_KR register. 2. Write the IWDG prescaler by programming IWDG_PR from 0 to 7. 3. Write the reload register (IWDG_RLR). 4. Wait for the registers to be updated (IWDG_SR = 0x0000 0000). 5. Refresh the counter value with IWDG_RLR (IWDG_KR = 0x0000 AAAA). 6. Enable the IWDG by writing 0x0000 CCCC in the IWDG_KR. Hardware watchdog If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and generates a reset unless the Key register is written by the software before the counter reaches end of count or if the downcounter is reloaded inside the window. 21.3.3 Register access protection Write access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers is protected. To modify them, you must first write the code 0x0000 5555 in the IWDG_KR register. A write access to this register with a different value will break the sequence and register access will be protected again. This implies that it is the case of the reload operation (writing 0x0000 AAAA). A status register is available to indicate that an update of the prescaler or the down-counter reload value or the window value is on going. 21.3.4 Debug mode When the microcontroller enters debug mode (core halted), the IWDG counter either continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in DBG module. DocID022448 Rev 2 495/897 501 Independent watchdog (IWDG) RM0313 Figure 163. Independent watchdog block diagram #/2% 0RESCALERREGISTER )7$'?02 3TATUSREGISTER )7$'?32 2ELOADREGISTER )7$'?2,2 +EYREGISTER )7$'?+2 BITRELOADVALUE BIT ,3) K(Z PRESCALER )7$'RESET BITDOWNCOUNTER 6$$VOLTAGEDOMAIN -36 Note: The watchdog function is implemented in the CORE voltage domain that is still functional in Stop and Standby modes. 21.4 IWDG registers Refer to Section 1.1 on page 36 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 21.4.1 Key register (IWDG_KR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w w w w w w w w w w w w w w w KEY[15:0] w Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 KEY[15:0]: Key value (write only, read 0x0000) These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. Writing the key value 0x5555 to enables access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers (see Section 21.3.3) Writing the key value CCCCh starts the watchdog (except if the hardware watchdog option is selected) 496/897 DocID022448 Rev 2 RM0313 Independent watchdog (IWDG) 21.4.2 Prescaler register (IWDG_PR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PR[2:0] rw rw rw Bits 31:3 Reserved, must be kept at reset value. Bits 2:0 PR[2:0]: Prescaler divider These bits are write access protected seeSection 21.3.3. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in order to be able to change the prescaler divider. 000: divider /4 001: divider /8 010: divider /16 011: divider /32 100: divider /64 101: divider /128 110: divider /256 111: divider /256 Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the IWDG_SR register is reset. DocID022448 Rev 2 497/897 501 Independent watchdog (IWDG) 21.4.3 RM0313 Reload register (IWDG_RLR) Address offset: 0x08 Reset value: 0x0000 0FFF (reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw 15 14 13 12 Res. Res. Res. Res. RL[11:0] rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bits11:0 RL[11:0]: Watchdog counter reload value These bits are write access protected see Section 21.3.3. They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the IWDG_KR register. The watchdog counter counts down from this value. The timeout period is a function of this value and the clock prescaler. Refer to the datasheet for the timout information. The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing on this register. For this reason the value read from this register is valid only when the RVU bit in the IWDG_SR register is reset. 498/897 DocID022448 Rev 2 RM0313 Independent watchdog (IWDG) 21.4.4 Status register (IWDG_SR) Address offset: 0x0C Reset value: 0x0000 0000 (not reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WVU RVU PVU r r r Bits 31:3 Reserved, must be kept at reset value. Bit 2 WVU: Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Window value can be updated only when WVU bit is reset. This bit is generated only if generic “window” = 1 Bit 1 RVU: Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Reload value can be updated only when RVU bit is reset. Bit 0 PVU: Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Prescaler value can be updated only when PVU bit is reset. DocID022448 Rev 2 499/897 501 Independent watchdog (IWDG) 21.4.5 RM0313 Window register (IWDG_WINR) Address offset: 0x10 Reset value: 0x0000 0FFF (reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw 15 14 13 12 Res. Res. Res. Res. WIN[11:0] rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bits11:0 WIN[11:0]: Watchdog counter window value These bits are write access protected see Section 21.3.3. These bits contain the high limit of the window value to be compared to the downcounter. To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 The WVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the WVU bit in the IWDG_SR register is reset. Note: 500/897 If several reload, prescaler, or window values are used by the application, it is mandatory to wait until RVU bit is reset before changing the reload value, to wait until PVU bit is reset before changing the prescaler value, and to wait until WVU bit is reset before changing the window value. However, after updating the prescaler and/or the reload/window value it is not necessary to wait until RVU or PVU or WVU is reset before continuing code execution except in case of low-power mode entry. DocID022448 Rev 2 0x0C 0x10 Reset value DocID022448 Rev 2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Reset value 1 1 1 1 1 WIN[11:0] 1 1 1 1 PVU 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 RVU 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 WVU 1 Res. 1 Res. 1 Res. 1 Res. Res. Res. 1 Res. Res. Res. 1 Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Reset value Res. IWDG_WINR Res. IWDG_SR Res. IWDG_RLR Res. 0x08 Res. 0x04 IWDG_PR Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IWDG_KR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Register Res. 0x00 Res. Offset Res. 21.4.6 Res. RM0313 Independent watchdog (IWDG) IWDG register map The following table gives the IWDG register map and reset values. Table 59. IWDG register map and reset values KEY[15:0] 0 PR[2:0] 0 0 0 0 0 RL[11:0] 0 0 0 1 1 1 Refer to Table 1 on page 43 for the register boundary addresses. 501/897 501 System window watchdog (WWDG) RM0313 22 System window watchdog (WWDG) 22.1 Introduction The system window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the downcounter before the T6 bit becomes cleared. An MCU reset is also generated if the 7-bit downcounter value (in the control register) is refreshed before the downcounter has reached the window register value. This implies that the counter must be refreshed in a limited window. The WWDG clock is prescaled from the APB1 clock and has a configurable time-window that can be programmed to detect abnormally late or early application behavior. The WWDG is best suited for applications which require the watchdog to react within an accurate timing window. 22.2 WWDG main features • Programmable free-running downcounter • Conditional reset • 22.3 – Reset (if watchdog activated) when the downcounter value becomes less than 0x40 – Reset (if watchdog activated) if the downcounter is reloaded outside the window (see Figure 165) Early wakeup interrupt (EWI): triggered (if enabled and the watchdog activated) when the downcounter is equal to 0x40. WWDG functional description If the watchdog is activated (the WDGA bit is set in the WWDG_CR register) and when the 7-bit downcounter (T[6:0] bits) rolls over from 0x40 to 0x3F (T6 becomes cleared), it initiates a reset. If the software reloads the counter while the counter is greater than the value stored in the window register, then a reset is generated. 502/897 DocID022448 Rev 2 RM0313 System window watchdog (WWDG) Figure 164. Watchdog block diagram Watchdog configuration register (WWDG_CFR) RESET - comparator = 1 when T6:0 > W6:0 W6 W5 W4 W3 W2 W1 W0 CMP Write WWDG_CR Watchdog control register (WWDG_CR) WDGA T6 T5 T4 T3 T2 T1 T0 6-bit downcounter (CNT) PCLK (from RCC clock controller) WDG prescaler (WDGTB) The application program must write in the WWDG_CR register at regular intervals during normal operation to prevent an MCU reset. This operation must occur only when the counter value is lower than the window register value. The value to be stored in the WWDG_CR register must be between 0xFF and 0xC0: Enabling the watchdog The watchdog is always disabled after a reset. It is enabled by setting the WDGA bit in the WWDG_CR register, then it cannot be disabled again except by a reset. Controlling the downcounter This downcounter is free-running: It counts down even if the watchdog is disabled. When the watchdog is enabled, the T6 bit must be set to prevent generating an immediate reset. The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. The timing varies between a minimum and a maximum value due to the unknown status of the prescaler when writing to the WWDG_CR register (see Figure 165).The Configuration register (WWDG_CFR) contains the high limit of the window: To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x3F. Figure 165 describes the window watchdog process. Note: The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). Advanced watchdog interrupt feature The Early Wakeup Interrupt (EWI) can be used if specific safety operations or data logging must be performed before the actual reset is generated. The EWI interrupt is enabled by setting the EWI bit in the WWDG_CFR register. When the downcounter reaches the value 0x40, an EWI interrupt is generated and the corresponding interrupt service routine (ISR) can be used to trigger specific actions (such as communications or data logging), before resetting the device. In some applications, the EWI interrupt can be used to manage a software system check and/or system recovery/graceful degradation, without generating a WWDG reset. In this DocID022448 Rev 2 503/897 507 System window watchdog (WWDG) RM0313 case, the corresponding interrupt service routine (ISR) should reload the WWDG counter to avoid the WWDG reset, then trigger the required actions. The EWI interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register. Note: When the EWI interrupt cannot be served, e.g. due to a system lock in a higher priority task, the WWDG reset will eventually be generated. 22.4 How to program the watchdog timeout You can use the formula in Figure 165 to calculate the WWDG timeout. Warning: When writing to the WWDG_CR register, always write 1 in the T6 bit to avoid generating an immediate reset. Figure 165. Window watchdog timing diagram 4;=#.4DOWNCOUNTER 7;= X& 2EFRESHNOTALLOWED 2EFRESHALLOWED 4IME 4BIT 2%3%4 AIB The formula to calculate the timeout value is given by: WDGTB t WWDG = tPCLK1 × 4096 × 2 × ( t [ 5:0 ] + 1 ) ( ms ) where: tWWDG: WWDG timeout tPCLK: APB1 clock period measured in ms Refer to the datasheet for the minimum and maximum values of the TWWDG. 504/897 DocID022448 Rev 2 RM0313 System window watchdog (WWDG) 22.5 Debug mode When the microcontroller enters debug mode (Cortex-M4 with FPU core halted), the WWDG counter either continues to work normally or stops, depending on DBG_WWDG_STOP configuration bit in DBG module. For more details, refer to Section 31.16.2: Debug support for timers, watchdog, bxCAN and I2C. 22.6 WWDG registers Refer to Section 1.1 on page 36 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 22.6.1 Control register (WWDG_CR) Address offset: 0x00 Reset value: 0x0000 007F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. WDGA T[6:0] rs rw Bits 31:8 Reserved, must be kept at reset value. Bit 7 WDGA: Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter. It is decremented every (4096 x 2WDGTB) PCLK cycles. A reset is produced when it rolls over from 0x40 to 0x3F (T6 becomes cleared). DocID022448 Rev 2 505/897 507 System window watchdog (WWDG) 22.6.2 RM0313 Configuration register (WWDG_CFR) Address offset: 0x04 Reset value: 0x0000 007F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 Res. Res. Res. Res. Res. Res. EWI WDGTB[1:0] W[6:0] rs rw rw Bit 31:10 Reserved, must be kept at reset value. Bit 9 EWI: Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset. Bits 8:7 WDGTB[1:0]: Timer base The time base of the prescaler can be modified as follows: 00: CK Counter Clock (PCLK div 4096) div 1 01: CK Counter Clock (PCLK div 4096) div 2 10: CK Counter Clock (PCLK div 4096) div 4 11: CK Counter Clock (PCLK div 4096) div 8 Bits 6:0 W[6:0]: 7-bit window value These bits contain the window value to be compared to the downcounter. 22.6.3 Status register (WWDG_SR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EWIF rc_w0 Bit 31:1 Reserved, must be kept at reset value. Bit 0 EWIF: Early wakeup interrupt flag This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing ‘0. A write of ‘1 has no effect. This bit is also set if the interrupt is not enabled. 506/897 DocID022448 Rev 2 0x08 WWDG_SR DocID022448 Rev 2 Reset value WDGTB1 WDGTB0 0 0 0 1 1 1 1 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EWI Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WWDG_CFR Res. 0x04 Res. Reset value 0 1 1 1 1 W[6:0] 1 1 1 1 Res. 1 EWIF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WWDG_CR WDGA Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Register Res. 0x00 Res. Offset Res. 22.6.4 Res. RM0313 System window watchdog (WWDG) WWDG register map The following table gives the WWDG register map and reset values. Table 60. WWDG register map and reset values T[6:0] 0 Refer to Section 2.2.2 for the register boundary addresses. 507/897 507 Real-time clock (RTC) RM0313 23 Real-time clock (RTC) 23.1 Introduction The RTC provides an automatic wakeup to manage all low power modes. The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a timeof-day clock/calendar with programmable alarm interrupts. The RTC includes also a periodic programmable wakeup flag with interrupt capability. Two 32-bit registers contain the seconds, minutes, hours (12- or 24-hour format), day (day of week), date (day of month), month, and year, expressed in binary coded decimal format (BCD). The sub-seconds value is also available in binary format. Compensations for 28-, 29- (leap year), 30-, and 31-day months are performed automatically. Daylight saving time compensation can also be performed. Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date. A digital calibration feature is available to compensate for any deviation in crystal oscillator accuracy. After Backup domain reset, all RTC registers are protected against possible parasitic write accesses. As long as the supply voltage remains in the operating range, the RTC never stops, regardless of the device status (Run mode, low power mode or under reset). 508/897 DocID022448 Rev 2 RM0313 23.2 Real-time clock (RTC) RTC main features The RTC unit main features are the following (see Figure 166: RTC block diagram): • Calendar with subseconds, seconds, minutes, hours (12 or 24 format), day (day of week), date (day of month), month, and year. • Daylight saving compensation programmable by software. • Programmable alarm with interrupt function. The alarm can be triggered by any combination of the calendar fields. • Automatic wakeup unit generating a periodic flag that triggers an automatic wakeup interrupt. • Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. • Accurate synchronization with an external clock using the subsecond shift feature. • Digital calibration circuit (periodic counter correction): 0.95 ppm accuracy, obtained in a calibration window of several seconds • Time-stamp function for event saving • Tamper detection event with configurable filter and internal pull-up • Maskable interrupts/events: • – Alarm A – Alarm B – Wakeup interrupt – Time-stamp – Tamper detection Backup registers. DocID022448 Rev 2 509/897 552 Real-time clock (RTC) RM0313 23.3 RTC functional description 23.3.1 RTC block diagram Figure 166. RTC block diagram Z dͺ dDWϯ Ă ĐŬƵƉƌĞŐŝƐƚĞƌƐ ĂŶĚZ dƚĂŵƉĞƌ ĐŽŶƚƌŽůƌĞŐŝƐƚĞƌƐ Z dͺ dDWϮ Z dͺ dDWϭ dDWdž& Z dͺd^ dŝŵĞƐƚĂŵƉ ƌĞŐŝƐƚĞƌƐ Z dͺZ&/E d^& >^;ϯϮ͘ϳϲϴ,njͿ ,^ͬϯϮ Z d>< >^/ Z dͺ>Z ^ŵŽŽƚŚ ĐĂůŝď ƌĂƚŝŽŶ Z dͺWZZ ƐLJŶĐŚƌŽŶŽƵƐ ϳͲďŝƚƉƌĞƐĐĂůĞƌ ;ĚĞ ĨĂƵůƚсϭϮϴͿ ĐŬͺĂƉƌĞ ;ĚĞ ĨĂƵůƚϮϱϲ,njͿ Z dͺWZZ ^LJŶĐŚƌŽŶŽƵƐ ϭϱͲďŝƚƉƌĞƐĐĂůĞƌ ;ĚĞ ĨĂƵůƚсϮϱϲͿ ĐŬͺƐƉƌĞ ;ĚĞ ĨĂƵůƚϭ,njͿ ĂůĞŶĚĂƌ ^ŚĂĚŽǁƌĞŐŝƐƚĞƌƐ ZdͺdZ͕ ZdͺZ ^ŚĂĚŽǁƌĞŐŝƐƚĞƌ Zdͺ^^Z th<^>ϭ͗Ϭ WƌĞƐĐĂůĞƌ ϭ͕Ϯ͕ϰ͕ϴ͕ϭϲ ϭ,nj ϱϭϮ,nj Z dͺ>/ Z dͺ>ZD KƵƚƉƵƚ ĐŽŶƚƌŽů Z dͺKhd ZdͺthdZ thd& ϭϲͲďŝƚǁĂŬĞƵƉ ĂƵƚŽƌĞůŽĂĚƚŝŵĞƌ K^>ϭ͗Ϭ ůĂ ƌŵ Z dͺ>ZDZ Z dͺ>ZD^^Z >Z& с ůĂ ƌŵ Z dͺ>ZDZ Z dͺ>ZD^^Z с >Z& D^ϯϬϮϭϲsϯ 510/897 DocID022448 Rev 2 RM0313 Real-time clock (RTC) The RTC includes: • Two alarms • Three tamper events • 32 x 32-bit backup registers – • • 23.3.2 The backup registers (RTC_BKPxR) are implemented in the backup domain that remains powered-on by VBAT when the VDD power is switched off. Alternate function outputs: RTC_OUT which selects one of the following two outputs: – RTC_CALIB: 512 Hz or 1Hz clock output (with an LSE frequency of 32.768 kHz). This output is enabled by setting the COE[23] bit in the RTC_CR register. – RTC_ALARM: This output is enabled by configuring the OSEL[1:0] bits in the RTC_CR register which select the Alarm A, Alarm B or Wakeup outputs. Alternate function inputs: – RTC_TS: timestamp event – RTC_TAMP1: tamper1 event detection – RTC_TAMP2: tamper2 event detection – RTC_TAMP3: tamper3 event detection – RTC_REFIN: 50 or 60 Hz reference clock input GPIOs controlled by the RTC RTC_OUT, RTC_TS and RTC_TAMP1 are mapped on the same pin (PC13). The selection of the RTC_ALARM output is performed through the RTC_TAFCR register as follows: the PC13VALUE bit is used to select whether the RTC_ALARM output is configured in push-pull or open drain mode. When PC13 is not used as RTC alternate function, it can be forced in output push-pull mode by setting the PC13MODE bit in the RTC_TAFCR. The output data value is then given by the PC13VALUE bit. In this case, PC13 output push-pull state and data are preserved in Standby mode. The output mechanism follows the priority order shown in Table 61. When PC14 and PC15 are not used as LSE oscillator, they can be forced in output push-pull mode by setting the PC14MODE and PC15MODE bits in the RTC_TAFCR register respectively. The output data values are then given by PC14VALUE and PC15VALUE. In this case, the PC14 and PC15 output push-pull states and data values are preserved in Standby mode. The output mechanism follows the priority order shown in Table 62 and Table 63. Table 61. RTC pin PC13 configuration(1) Pin configuration and function RTC_ALARM output enabled RTC_CALIB output enabled RTC_TAMP1 input enabled RTC_TS input enabled PC13MODE bit PC13VALUE bit RTC_ALARM output OD 1 Don’t care Don’t care Don’t care Don’t care 0 RTC_ALARM output PP 1 Don’t care Don’t care Don’t care Don’t care 1 DocID022448 Rev 2 511/897 552 Real-time clock (RTC) RM0313 Table 61. RTC pin PC13 configuration(1) (continued) Pin configuration and function RTC_ALARM output enabled RTC_CALIB output enabled RTC_TAMP1 input enabled RTC_TS input enabled PC13MODE bit PC13VALUE bit RTC_CALIB output PP 0 1 Don’t care Don’t care Don’t care Don’t care RTC_TAMP1 input floating 0 0 1 0 Don’t care Don’t care RTC_TS and RTC_TAMP1 input floating 0 0 1 1 Don’t care Don’t care RTC_TS input floating 0 0 0 1 Don’t care Don’t care Output PP forced 0 0 0 0 1 PC13 output data value Wakeup pin or Standard GPIO 0 0 0 0 0 Don’t care 1. OD: open drain; PP: push-pull. Table 62. LSE pin PC14 configuration (1) Pin configuration and function LSEON bit in RCC_BDCR register LSEBYP bit in RCC_BDCR register PC14MODE bit PC14VALUE bit LSE oscillator 1 0 Don’t care Don’t care LSE bypass 1 1 Don’t care Don’t care Output PP forced 0 Don’t care 1 PC14 output data value Standard GPIO 0 Don’t care 0 Don’t care 1. OD: open drain; PP: push-pull. Table 63. LSE pin PC15 configuration (1) Pin configuration and function LSEON bit in RCC_BDCR register LSEBYP bit in RCC_BDCR register PC15MODE bit PC15VALUE bit 1 0 Don’t care Don’t care 1 1 0 Don’t care 1 PC15 output data value 0 Don’t care 0 Don’t care LSE oscillator Output PP forced Standard GPIO 1. OD: open drain; PP: push-pull. 512/897 DocID022448 Rev 2 RM0313 23.3.3 Real-time clock (RTC) Clock and prescalers The RTC clock source (RTCCLK) is selected through the clock controller among the LSE clock, the LSI oscillator clock, and the HSE clock. For more information on the RTC clock source configuration, refer to the Reset and clock control (RCC) section. A programmable prescaler stage generates a 1 Hz clock which is used to update the calendar. To minimize power consumption, the prescaler is split into 2 programmable prescalers (see Figure 166: RTC block diagram): Note: • A 7-bit asynchronous prescaler configured through the PREDIV_A bits of the RTC_PRER register. • A 15-bit synchronous prescaler configured through the PREDIV_S bits of the RTC_PRER register. When both prescalers are used, it is recommended to configure the asynchronous prescaler to a high value to minimize consumption. The asynchronous prescaler division factor is set to 128, and the synchronous division factor to 256, to obtain an internal clock frequency of 1 Hz (ck_spre) with an LSE frequency of 32.768 kHz. The minimum division factor is 1 and the maximum division factor is 222. This corresponds to a maximum input frequency of around 4 MHz. fck_apre is given by the following formula: f RTCCLK f CK_APRE = --------------------------------------PREDIV_A + 1 The ck_apre clock is used to clock the binary RTC_SSR subseconds downcounter. When it reaches 0, RTC_SSR is reloaded with the content of PREDIV_S. fck_spre is given by the following formula: f RTCCLK f CK_SPRE = ----------------------------------------------------------------------------------------------( PREDIV_S + 1 ) × ( PREDIV_A + 1 ) The ck_spre clock can be used either to update the calendar or as timebase for the 16-bit wakeup auto-reload timer. To obtain short timeout periods, the 16-bit wakeup auto-reload timer can also run with the RTCCLK divided by the programmable 4-bit asynchronous prescaler (see Section 23.3.6: Periodic auto-wakeup for details). 23.3.4 Real-time clock and calendar The RTC calendar time and date registers are accessed through shadow registers which are synchronized with PCLK (APB clock). They can also be accessed directly in order to avoid waiting for the synchronization duration. • RTC_SSR for the subseconds • RTC_TR for the time • RTC_DR for the date Every two RTCCLK periods, the current calendar value is copied into the shadow registers, and the RSF bit of RTC_ISR register is set (see Section 23.6.4). The copy is not performed DocID022448 Rev 2 513/897 552 Real-time clock (RTC) RM0313 in Stop and Standby mode. When exiting these modes, the shadow registers are updated after up to 2 RTCCLK periods. When the application reads the calendar registers, it accesses the content of the shadow registers. It is possible to make a direct access to the calendar registers by setting the BYPSHAD control bit in the RTC_CR register. By default, this bit is cleared, and the user accesses the shadow registers. When reading the RTC_SSR, RTC_TR or RTC_DR registers in BYPSHAD=0 mode, the frequency of the APB clock (fAPB) must be at least 7 times the frequency of the RTC clock (fRTCCLK). The shadow registers are reset by system reset. 23.3.5 Programmable alarms The RTC unit provides programmable alarm: Alarm A and Alarm B. The description below is given for Alarm A, but can be translated in the same way for Alarm B. The programmable alarm function is enabled through the ALRAE bit in the RTC_CR register. The ALRAF is set to 1 if the calendar subseconds, seconds, minutes, hours, date or day match the values programmed in the alarm registers RTC_ALRMASSR and RTC_ALRMAR. Each calendar field can be independently selected through the MSKx bits of the RTC_ALRMAR register, and through the MASKSSx bits of the RTC_ALRMASSR register. The alarm interrupt is enabled through the ALRAIE bit in the RTC_CR register. Caution: If the seconds field is selected (MSK0 bit reset in RTC_ALRMAR), the synchronous prescaler division factor set in the RTC_PRER register must be at least 3 to ensure correct behavior. Alarm A and Alarm B (if enabled by bits OSEL[0:1] in RTC_CR register) can be routed to the RTC_ALARM output. RTC_ALARM output polarity can be configured through bit POL the RTC_CR register. 23.3.6 Periodic auto-wakeup The periodic wakeup flag is generated by a 16-bit programmable auto-reload down-counter. The wakeup timer range can be extended to 17 bits. The wakeup function is enabled through the WUTE bit in the RTC_CR register. The wakeup timer clock input can be: • RTC clock (RTCCLK) divided by 2, 4, 8, or 16. When RTCCLK is LSE(32.768kHz), this allows to configure the wakeup interrupt period from 122 µs to 32 s, with a resolution down to 61µs. • ck_spre (usually 1 Hz internal clock) When ck_spre frequency is 1Hz, this allows to achieve a wakeup time from 1 s to around 36 hours with one-second resolution. This large programmable time range is divided in 2 parts: 514/897 – from 1s to 18 hours when WUCKSEL [2:1] = 10 – and from around 18h to 36h when WUCKSEL[2:1] = 11. In this last case 216 is added to the 16-bit counter current value.When the initialization sequence is complete (see Programming the wakeup timer on page 516), the timer starts counting down.When the wakeup function is enabled, the down-counting remains active in low power modes. In addition, when it reaches 0, the WUTF flag is set in DocID022448 Rev 2 RM0313 Real-time clock (RTC) the RTC_ISR register, and the wakeup counter is automatically reloaded with its reload value (RTC_WUTR register value). The WUTF flag must then be cleared by software. When the periodic wakeup interrupt is enabled by setting the WUTIE bit in the RTC_CR2 register, it can exit the device from low power modes. The periodic wakeup flag can be routed to the RTC_ALARM output provided it has been enabled through bits OSEL[0:1] of RTC_CR register. RTC_ALARM output polarity can be configured through the POL bit in the RTC_CR register. System reset, as well as low power modes (Sleep, Stop and Standby) have no influence on the wakeup timer. 23.3.7 RTC initialization and configuration RTC register access The RTC registers are 32-bit registers. The APB interface introduces 2 wait-states in RTC register accesses except on read accesses to calendar shadow registers when BYPSHAD=0. RTC register write protection After system reset, the RTC registers are protected against parasitic write access by clearing the DBP bit in the PWR_CR register (refer to the power control section). DBP bit must be set in order to enable RTC registers write access. After Backup domain reset, all the RTC registers are write-protected. Writing to the RTC registers is enabled by writing a key into the Write Protection register, RTC_WPR. The following steps are required to unlock the write protection on all the RTC registers except for RTC_TAFCR, RTC_BKPxR and RTC_ISR[13:8]. 1. Write ‘0xCA’ into the RTC_WPR register. 2. Write ‘0x53’ into the RTC_WPR register. Writing a wrong key reactivates the write protection. The protection mechanism is not affected by system reset. Calendar initialization and configuration To program the initial time and date calendar values, including the time format and the prescaler configuration, the following sequence is required: 1. Set INIT bit to 1 in the RTC_ISR register to enter initialization mode. In this mode, the calendar counter is stopped and its value can be updated. 2. Poll INITF bit of in the RTC_ISR register. The initialization phase mode is entered when INITF is set to 1. It takes around 2 RTCCLK clock cycles (due to clock synchronization). 3. To generate a 1 Hz clock for the calendar counter, program both the prescaler factors in RTC_PRER register. 4. Load the initial time and date values in the shadow registers (RTC_TR and RTC_DR), and configure the time format (12 or 24 hours) through the FMT bit in the RTC_CR register. 5. Exit the initialization mode by clearing the INIT bit. The actual calendar counter value is then automatically loaded and the counting restarts after 4 RTCCLK clock cycles. DocID022448 Rev 2 515/897 552 Real-time clock (RTC) RM0313 When the initialization sequence is complete, the calendar starts counting. Note: After a system reset, the application can read the INITS flag in the RTC_ISR register to check if the calendar has been initialized or not. If this flag equals 0, the calendar has not been initialized since the year field is set at its Backup domain reset default value (0x00). To read the calendar after initialization, the software must first check that the RSF flag is set in the RTC_ISR register. Daylight saving time The daylight saving time management is performed through bits SUB1H, ADD1H, and BKP of the RTC_CR register. Using SUB1H or ADD1H, the software can subtract or add one hour to the calendar in one single operation without going through the initialization procedure. In addition, the software can use the BKP bit to memorize this operation. Programming the alarm A similar procedure must be followed to program or update the programmable alarms. The procedure below is given for Alarm A but can be translated in the same way for Alarm B. Note: 1. Clear ALRAE in RTC_CR to disable Alarm A. 2. Program the Alarm A registers (RTC_ALRMASSR/RTC_ALRMAR). 3. Set ALRAE in the RTC_CR register to enable Alarm A again. Each change of the RTC_CR register is taken into account after around 2 RTCCLK clock cycles due to clock synchronization. Programming the wakeup timer The following sequence is required to configure or change the wakeup timer auto-reload value (WUT[15:0] in RTC_WUTR): 23.3.8 1. Clear WUTE in RTC_CR to disable the wakeup timer. 2. Poll WUTWF until it is set in RTC_ISR to make sure the access to wakeup auto-reload counter and to WUCKSEL[2:0] bits is allowed. It takes around 2 RTCCLK clock cycles (due to clock synchronization). 3. Program the wakeup auto-reload value WUT[15:0], and the wakeup clock selection (WUCKSEL[2:0] bits in RTC_CR).Set WUTE in RTC_CR to enable the timer again. The wakeup timer restarts down-counting. Reading the calendar When BYPSHAD control bit is cleared in the RTC_CR register To read the RTC calendar registers (RTC_SSR, RTC_TR and RTC_DR) properly, the APB1 clock frequency (fPCLK) must be equal to or greater than seven times the fRTCCLK RTC clock frequency. This ensures a secure behavior of the synchronization mechanism. If the APB1 clock frequency is less than seven times the RTC clock frequency, the software must read the calendar time and date registers twice. If the second read of the RTC_TR gives the same result as the first read, this ensures that the data is correct. Otherwise a third read access must be done. In any case the APB1 clock frequency must never be lower than the RTC clock frequency. 516/897 DocID022448 Rev 2 RM0313 Real-time clock (RTC) The RSF bit is set in RTC_ISR register each time the calendar registers are copied into the RTC_SSR, RTC_TR and RTC_DR shadow registers. The copy is performed every two RTCCLK cycles. To ensure consistency between the 3 values, reading either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read. In case the software makes read accesses to the calendar in a time interval smaller than 2 RTCCLK periods: RSF must be cleared by software after the first calendar read, and then the software must wait until RSF is set before reading again the RTC_SSR, RTC_TR and RTC_DR registers. After waking up from low power mode (Stop or Standby), RSF must be cleared by software. The software must then wait until it is set again before reading the RTC_SSR, RTC_TR and RTC_DR registers. The RSF bit must be cleared after wakeup and not before entering low power mode. After a system reset, the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers. Indeed, a system reset resets the shadow registers to their default values. After an initialization (refer to Calendar initialization and configuration on page 515): the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers. After synchronization (refer to Section 23.3.10: RTC synchronization): the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers. When the BYPSHAD control bit is set in the RTC_CR register (bypass shadow registers) Reading the calendar registers gives the values from the calendar counters directly, thus eliminating the need to wait for the RSF bit to be set. This is especially useful after exiting from low power modes (STOP or Standby), since the shadow registers are not updated during these modes. When the BYPSHAD bit is set to 1, the results of the different registers might not be coherent with each other if an RTCCLK edge occurs between two read accesses to the registers. Additionally, the value of one of the registers may be incorrect if an RTCCLK edge occurs during the read operation. The software must read all the registers twice, and then compare the results to confirm that the data is coherent and correct. Alternatively, the software can just compare the two results of the least-significant calendar register. Note: While BYPSHAD=1, instructions which read the calendar registers require one extra APB cycle to complete. 23.3.9 Resetting the RTC The calendar shadow registers (RTC_SSR, RTC_TR and RTC_DR) and some bits of the RTC status register (RTC_ISR) are reset to their default values by all available system reset sources. On the contrary, the following registers are reset to their default values by a Backup domain reset and are not affected by a system reset: the RTC current calendar registers, the RTC control register (RTC_CR), the prescaler register (RTC_PRER), the RTC calibration register (RTC_CALR), the RTC shift register (RTC_SHIFTR), the RTC timestamp registers (RTC_TSSSR, RTC_TSTR and RTC_TSDR), the RTC tamper and alternate function configuration register (RTC_TAFCR), the RTC backup registers (RTC_BKPxR), the wakeup DocID022448 Rev 2 517/897 552 Real-time clock (RTC) RM0313 timer register (RTC_WUTR), the Alarm A and Alarm B registers (RTC_ALRMASSR/RTC_ALRMAR and RTC_ALRMBSSR/RTC_ALRMBR). In addition, the RTC keeps on running under system reset if the reset source is different from the Backup domain reset one. When a Backup domain reset occurs, the RTC is stopped and all the RTC registers are set to their reset values. 23.3.10 RTC synchronization The RTC can be synchronized to a remote clock with a high degree of precision. After reading the sub-second field (RTC_SSR or RTC_TSSSR), a calculation can be made of the precise offset between the times being maintained by the remote clock and the RTC. The RTC can then be adjusted to eliminate this offset by “shifting” its clock by a fraction of a second using RTC_SHIFTR. RTC_SSR contains the value of the synchronous prescaler’s counter. This allows one to calculate the exact time being maintained by the RTC down to a resolution of 1 / (PREDIV_S + 1) seconds. As a consequence, the resolution can be improved by increasing the synchronous prescaler value (PREDIV_S[14:0]. The maximum resolution allowed (30.52 μs with a 32768 Hz clock) is obtained with PREDIV_S set to 0x7FFF. However, increasing PREDIV_S means that PREDIV_A must be decreased in order to maintain the synchronous prescaler’s output at 1 Hz. In this way, the frequency of the asynchronous prescaler’s output increases, which may increase the RTC dynamic consumption. The RTC can be finely adjusted using the RTC shift control register (RTC_SHIFTR). Writing to RTC_SHIFTR can shift (either delay or advance) the clock by up to a second with a resolution of 1 / (PREDIV_S + 1) seconds. The shift operation consists of adding the SUBFS[14:0] value to the synchronous prescaler counter SS[15:0]: this will delay the clock. If at the same time the ADD1S bit is set, this results in adding one second and at the same time subtracting a fraction of second, so this will advance the clock. Caution: Before initiating a shift operation, the user must check that SS[15] = 0 in order to ensure that no overflow will occur. As soon as a shift operation is initiated by a write to the RTC_SHIFTR register, the SHPF flag is set by hardware to indicate that a shift operation is pending. This bit is cleared by hardware as soon as the shift operation has completed. Caution: This synchronization feature is not compatible with the reference clock detection feature: firmware must not write to RTC_SHIFTR when REFCKON=1. 23.3.11 RTC reference clock detection The update of the RTC calendar can be synchronized to a reference clock, RTC_REFIN, which is usually the mains frequency (50 or 60 Hz). The precision of the RTC_REFIN reference clock should be higher than the 32.768 kHz LSE clock. When the RTC_REFIN detection is enabled (REFCKON bit of RTC_CR set to 1), the calendar is still clocked by the LSE, and RTC_REFIN is used to compensate for the imprecision of the calendar update frequency (1 Hz). Each 1 Hz clock edge is compared to the nearest RTC_REFIN clock edge (if one is found within a given time window). In most cases, the two clock edges are properly aligned. When the 1 Hz clock becomes misaligned due to the imprecision of the LSE clock, the RTC shifts 518/897 DocID022448 Rev 2 RM0313 Real-time clock (RTC) the 1 Hz clock a bit so that future 1 Hz clock edges are aligned. Thanks to this mechanism, the calendar becomes as precise as the reference clock. The RTC detects if the reference clock source is present by using the 256 Hz clock (ck_apre) generated from the 32.768 kHz quartz. The detection is performed during a time window around each of the calendar updates (every 1 s). The window equals 7 ck_apre periods when detecting the first reference clock edge. A smaller window of 3 ck_apre periods is used for subsequent calendar updates. Each time the reference clock is detected in the window, the asynchronous prescaler which outputs the ck_apre clock is forced to reload. This has no effect when the reference clock and the 1 Hz clock are aligned because the prescaler is being reloaded at the same moment. When the clocks are not aligned, the reload shifts future 1 Hz clock edges a little for them to be aligned with the reference clock. If the reference clock halts (no reference clock edge occurred during the 3 ck_apre window), the calendar is updated continuously based solely on the LSE clock. The RTC then waits for the reference clock using a large 7 ck_apre period detection window centered on the ck_spre edge. When the RTC_REFIN detection is enabled, PREDIV_A and PREDIV_S must be set to their default values: • PREDIV_A = 0x007F • PREVID_S = 0x00FF Note: RTC_REFIN clock detection is not available in Standby mode. 23.3.12 RTC smooth digital calibration The RTC frequency can be digitally calibrated with a resolution of about 0.954 ppm with a range from -487.1 ppm to +488.5 ppm. The correction of the frequency is performed using series of small adjustments (adding and/or subtracting individual RTCCLK pulses). These adjustments are fairly well distributed so that the RTC is well calibrated even when observed over short durations of time. The smooth digital calibration is performed during a cycle of about 220 RTCCLK pulses, or 32 seconds when the input frequency is 32768 Hz. The smooth calibration register (RTC_CALR) specifies the number of RTCCLK clock cycles to be masked during the 32-second cycle: • Setting the bit CALM[0] to 1 causes exactly one pulse to be masked during the 32- second cycle. • Setting CALM[1] to 1 causes two additional cycles to be masked • Setting SMC[2] to 1 causes four additional cycles to be masked • and so on up to SMC[8] set to 1 which causes 256 clocks to be masked. While CALM allows the RTC frequency to be reduced by up to 487.1 ppm with fine resolution, the bit CALP can be used to increase the frequency by 488.5 ppm. Setting CALP to ‘1’ effectively inserts an extra RTCCLK pulse every 211 RTCCLK cycles, which means that 512 clocks are added during every 32-second cycle. Using CALM together with CALP, an offset ranging from -511 to +512 RTCCLK cycles can be added during the 32-second cycle, which translates to a calibration range of -487.1 ppm to +488.5 ppm with a resolution of about 0.954 ppm. DocID022448 Rev 2 519/897 552 Real-time clock (RTC) RM0313 The formula to calculate the effective calibrated frequency (FCAL) given the input frequency (FRTCCLK) is as follows: FCAL = FRTCCLK x [ 1 + (CALP x 512 - CALM) / (220 + CALM - CALP x 512) ] Calibration when PREDIV_A<3 The CALP bit can not be set to 1 when the asynchronous prescaler value (PREDIV_A bits in RTC_PRER register) is less than 3. If CALP was already set to 1 and PREDIV_A bits are set to a value less than 3, CALP is ignored and the calibration operates as if CALP was equal to 0. To perform a calibration with PREDIV_A less than 3, the synchronous prescaler value (PREDIV_S) should be reduced so that each second is accelerated by 8 RTCCLK clock cycles, which is equivalent to adding 256 clock cycles every 32 seconds. As a result, between 255 and 256 clock pulses (corresponding to a calibration range from 243.3 to 244.1 ppm) can effectively be added during each 32-second cycle using only the CALM bits. With a nominal RTCCLK frequency of 32768 Hz, when PREDIV_A equals 1 (division factor of 2), PREDIV_S should be set to 16379 rather than 16383 (4 less). The only other interesting case is when PREDIV_A equals 0, PREDIV_S should be set to 32759 rather than 32767 (8 less). If PREDIV_S is reduced in this way, the formula given the effective frequency of the calibrated input clock is as follows: FCAL = FRTCCLK x [ 1 + (256 - CALM) / (220 + CALM - 256) ] In this case, CALM[7:0] equals 0x100 (the midpoint of the CALM range) is the correct setting if RTCCLK is exactly 32768.00 Hz. Verifying the RTC calibration RTC precision is ensured by measuring the precise frequency of RTCCLK and calculating the correct CALM value and CALP values. An optional 1 Hz output is provided to allow applications to measure and verify the RTC precision. Measuring the precise frequency of the RTC over a limited interval can result in a measurement error of up to 2 RTCCLK clock cycles over the measurement period, depending on how the digital calibration cycle is aligned with the measurement period. However, this measurement error can be eliminated if the measurement period is the same length as the calibration cycle period. In this case, the only error observed is the error due to the resolution of the digital calibration. • By default, the calibration cycle period is 32 seconds. Using this mode and measuring the accuracy of the 1 Hz output over exactly 32 seconds guarantees that the measure is within 0.477 ppm (0.5 RTCCLK cycles over 32 seconds, due to the limitation of the calibration resolution). • CALW16 bit of the RTC_CALR register can be set to 1 to force a 16- second calibration cycle period. In this case, the RTC precision can be measured during 16 seconds with a maximum error of 0.954 ppm (0.5 RTCCLK cycles over 16 seconds). However, since the calibration 520/897 DocID022448 Rev 2 RM0313 Real-time clock (RTC) resolution is reduced, the long term RTC precision is also reduced to 0.954 ppm: CALM[0] bit is stuck at 0 when CALW16 is set to 1. • CALW8 bit of the RTC_CALR register can be set to 1 to force a 8- second calibration cycle period. In this case, the RTC precision can be measured during 8 seconds with a maximum error of 1.907 ppm (0.5 RTCCLK cycles over 8s). The long term RTC precision is also reduced to 1.907 ppm: CALM[1:0] bits are stuck at 00 when CALW8 is set to 1. Re-calibration on-the-fly The calibration register (RTC_CALR) can be updated on-the-fly while RTC_ISR/INITF=0, by using the follow process: 23.3.13 1. Poll the RTC_ISR/RECALPF (re-calibration pending flag). 2. If it is set to 0, write a new value to RTC_CALR, if necessary. RECALPF is then automatically set to 1 3. Within three ck_apre cycles after the write operation to RTC_CALR, the new calibration settings take effect. Time-stamp function Time-stamp is enabled by setting the TSE bit of RTC_CR register to 1. The calendar is saved in the time-stamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR) when a time-stamp event is detected on the RTC_TS pin. When a time-stamp event occurs, the time-stamp flag bit (TSF) in RTC_ISR register is set. By setting the TSIE bit in the RTC_CR register, an interrupt is generated when a time-stamp event occurs. If a new time-stamp event is detected while the time-stamp flag (TSF) is already set, the time-stamp overflow flag (TSOVF) flag is set and the time-stamp registers (RTC_TSTR and RTC_TSDR) maintain the results of the previous event. Note: TSF is set 2 ck_apre cycles after the time-stamp event occurs due to synchronization process. There is no delay in the setting of TSOVF. This means that if two time-stamp events are close together, TSOVF can be seen as '1' while TSF is still '0'. As a consequence, it is recommended to poll TSOVF only after TSF has been set. Caution: If a time-stamp event occurs immediately after the TSF bit is supposed to be cleared, then both TSF and TSOVF bits are set.To avoid masking a time-stamp event occurring at the same moment, the application must not write ‘0’ into TSF bit unless it has already read it to ‘1’. Optionally, a tamper event can cause a time-stamp to be recorded. See the description of the TAMPTS control bit in Section 23.6.14: RTC time-stamp sub second register (RTC_TSSSR). 23.3.14 Tamper detection The RTC_TAMPx input events can be configured either for edge detection, or for level detection with filtering. DocID022448 Rev 2 521/897 552 Real-time clock (RTC) RM0313 The tamper detection can be configured for the following purposes: • erase the RTC backup registers • generate an interrupt, capable to wakeup from Stop and Standby modes RTC backup registers The backup registers (RTC_BKPxR) are not reset by system reset, or when the device wakes up from Standby mode. The backup registers are reset when a tamper detection event occurs (see Section 23.6.19: RTC backup registers (RTC_BKPxR) and Tamper detection initialization on page 522, or when the readout protection of the flash is changed from level 1 to level 0). Tamper detection initialization Each input can be enabled by setting the corresponding TAMPxE bits to 1 in the RTC_TAFCR register. Each RTC_TAMPx tamper detection input is associated with a flag TAMPxF in the RTC_ISR register. The TAMPxF flag is asserted after the tamper event on the pin, with the latency provided below: • 3 ck_apre cycles when TAMPFLT differs from 0x0 (Level detection with filtering) • 3 ck_apre cycles when TAMPTS=1 (Timestamp on tamper event) • No latency when TAMPFLT=0x0 (Edge detection) and TAMPTS=0 A new tamper occuring on the same pin during this period and as long as TAMPxF is set cannot be detected. By setting the TAMPIE bit in the RTC_TAFCR register, an interrupt is generated when a tamper detection event occurs. Timestamp on tamper event With TAMPTS set to ‘1’, any tamper event causes a timestamp to occur. In this case, either the TSF bit or the TSOVF bit are set in RTC_ISR, in the same manner as if a normal timestamp event occurs. The affected tamper flag register TAMPxF is set at the same time that TSF or TSOVF is set. Edge detection on tamper inputs If the TAMPFLT bits are “00”, the RTC_TAMPx pins generate tamper detection events when either a rising edge or a falling edge is observed depending on the corresponding TAMPxTRG bit. The internal pull-up resistors on the RTC_TAMPx inputs are deactivated when edge detection is selected. Caution: To avoid losing tamper detection events, the signal used for edge detection is logically ANDed with the corresponding TAMPxE bit in order to detect a tamper detection event in case it occurs before the RTC_TAMPx pin is enabled. • 522/897 When TAMPxTRG = 0: if the RTC_TAMPx alternate function is already high before tamper detection is enabled (TAMPxE bit set to 1), a tamper event is detected as soon DocID022448 Rev 2 RM0313 Real-time clock (RTC) as the RTC_TAMPx input is enabled, even if there was no rising edge on the RTC_TAMPx input after TAMPxE was set. • When TAMPxTRG = 1: if the RTC_TAMPx alternate function is already low before tamper detection is enabled, a tamper event is detected as soon as the RTC_TAMPx input is enabled (even if there was no falling edge on the RTC_TAMPx input after TAMPxE was set. After a tamper event has been detected and cleared, the RTC_TAMPx alternate function should be disabled and then re-enabled (TAMPxE set to 1) before re-programming the backup registers (RTC_BKPxR). This prevents the application from writing to the backup registers while the RTC_TAMPx input value still indicates a tamper detection. This is equivalent to a level detection on the RTC_TAMPx alternate function input. Note: Tamper detection is still active when VDD power is switched off. To avoid unwanted resetting of the backup registers, the pin to which the RTC_TAMPx alternate function is mapped should be externally tied to the correct level. Level detection with filtering on RTC_TAMPx inputs Level detection with filtering is performed by setting TAMPFLT to a non-zero value. A tamper detection event is generated when either 2, 4, or 8 (depending on TAMPFLT) consecutive samples are observed at the level designated by the TAMPxTRG bits. The RTC_TAMPx inputs are pre-charged through the I/O internal pull-up resistance before its state is sampled, unless disabled by setting TAMPPUDIS to 1,The duration of the precharge is determined by the TAMPPRCH bits, allowing for larger capacitances on the RTC_TAMPx inputs. The trade-off between tamper detection latency and power consumption through the pull-up can be optimized by using TAMPFREQ to determine the frequency of the sampling for level detection. Note: Refer to the datasheets for the electrical characteristics of the pull-up resistors. 23.3.15 Calibration clock output When the COE bit is set to 1 in the RTC_CR register, a reference clock is provided on the RTC_CALIB device output. If the COSEL bit in the RTC_CR register is reset and PREDIV_A = 0x7F, the RTC_CALIB frequency is fRTCCLK/64. This corresponds to a calibration output at 512 Hz for an RTCCLK frequency at 32.768 kHz. The RTC_CALIB duty cycle is irregular: there is a light jitter on falling edges. It is therefore recommended to use rising edges. When COSEL is set and “PREDIV_S+1” is a non-zero multiple of 256 (i.e: PREDIV_S[7:0] = 0xFF), the RTC_CALIB frequency is fRTCCLK/(256 * (PREDIV_A+1)). This corresponds to a calibration output at 1 Hz for prescaler default values (PREDIV_A = Ox7F, PREDIV_S = 0xFF), with an RTCCLK frequency at 32.768 kHz. 23.3.16 Alarm output The OSEL[1:0] control bits in the RTC_CR register are used to activate the alarm alternate function output RTC_ALARM, and to select the function which is output. These functions reflect the contents of the corresponding flags in the RTC_ISR register. The polarity of the output is determined by the POL control bit in RTC_CR so that the opposite of the selected flag bit is output when POL is set to 1. DocID022448 Rev 2 523/897 552 Real-time clock (RTC) RM0313 Alarm alternate function output The RTC_ALARM pin can be configured in output open drain or output push-pull using the control bit ALARMOUTTYPE in the RTC_TAFCR register. Note: Once the RTC_ALARM output is enabled, it has priority over RTC_CALIB (COE bit is don't care and must be kept cleared). When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is automatically configured in output alternate function. 23.4 RTC low power modes Table 64. Effect of low power modes on RTC Mode Description Sleep No effect RTC interrupts cause the device to exit the Sleep mode. Stop The RTC remains active when the RTC clock source is LSE or LSI. RTC alarm, RTC tamper event, RTC timestamp event, and RTC Wakeup cause the device to exit the Stop mode. The RTC remains active when the RTC clock source is LSE or LSI. RTC alarm, RTC Standby tamper event, RTC timestamp event, and RTC Wakeup cause the device to exit the Standby mode. 23.5 RTC interrupts All RTC interrupts are connected to the EXTI controller. Refer to the External and internal interrupt/event line mapping section. To enable the RTC Alarm interrupt, the following sequence is required: 1. Configure and enable the EXTI line corresponding to the RTC Alarm event in interrupt mode and select the rising edge sensitivity. 2. Configure and enable the RTC_ALARM IRQ channel in the NVIC. 3. Configure the RTC to generate RTC alarms. To enable the RTC Tamper interrupt, the following sequence is required: 1. Configure and enable the EXTI line corresponding to the RTC Tamper event in interrupt mode and select the rising edge sensitivity. 2. Configure and Enable the RTC_TAMP_STAMP IRQ channel in the NVIC. 3. Configure the RTC to detect the RTC tamper event. To enable the RTC TimeStamp interrupt, the following sequence is required: 1. Configure and enable the EXTI line corresponding to the RTC TimeStamp event in interrupt mode and select the rising edge sensitivity. 2. Configure and Enable the RTC_TAMP_STAMP IRQ channel in the NVIC. 3. Configure the RTC to detect the RTC time-stamp event. To enable the Wakeup timer interrupt, the following sequence is required: 524/897 DocID022448 Rev 2 RM0313 Real-time clock (RTC) 1. Configure and enable the EXTI line corresponding to the Wakeup timer even in interrupt mode and select the rising edge sensitivity. 2. Configure and Enable the RTC_WKUP IRQ channel in the NVIC. 3. Configure the RTC to detect the RTC Wakeup timer event. Table 65. Interrupt control bits Interrupt event Event flag Enable control bit Exit from Sleep mode Exit from Stop mode Exit from Standby mode Alarm A ALRAF ALRAIE yes yes(1) yes(1) Alarm B ALRBF ALRBIE yes yes(1) yes(1) RTC_TS input (timestamp) TSF TSIE yes yes(1) yes(1) RTC_TAMP1 input detection TAMP1F TAMPIE yes yes(1) yes(1) RTC_TAMP2 input detection TAMP2F TAMPIE yes yes(1) yes(1) RTC_TAMP3 input detection TAMP3F TAMPIE yes yes(1) yes(1) Wakeup timer interrupt WUTF WUTIE yes yes(1) yes(1) 1. Wakeup from STOP and Standby modes is possible only when the RTC clock source is LSE or LSI. 23.6 RTC registers Refer to Section 1.1 on page 36 of the reference manual for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by words (32-bit). DocID022448 Rev 2 525/897 552 Real-time clock (RTC) 23.6.1 RM0313 RTC time register (RTC_TR) The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page 515 and Reading the calendar on page 516. This register is write protected. The write access procedure is described in RTC register write protection on page 515. Address offset: 0x00 Backup domain reset value: 0x0000 0000 System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1. 31 30 29 28 27 26 25 24 23 22 Res. Res. Res. Res. Res. Res. Res. Res. Res. PM 15 14 13 12 11 10 9 8 7 rw rw rw Res. MNT[2:0] rw rw MNU[3:0] rw 19 18 17 16 HU[3:0] rw rw rw rw rw rw 6 5 4 3 2 1 0 rw rw rw rw rw ST[2:0] rw Bits 31-23 Reserved, must be kept at reset value Bit 22 PM: AM/PM notation 0: AM or 24-hour format 1: PM Bits 21:20 HT[1:0]: Hour tens in BCD format Bit 19:16 HU[3:0]: Hour units in BCD format Bit 15 Reserved, must be kept at reset value. Bits 14:12 MNT[2:0]: Minute tens in BCD format Bit 11:8 MNU[3:0]: Minute units in BCD format Bit 7 Reserved, must be kept at reset value. Bits 6:4 ST[2:0]: Second tens in BCD format Bit 3:0 SU[3:0]: Second units in BCD format 526/897 20 HT[1:0] rw Res. rw 21 DocID022448 Rev 2 rw SU[3:0] RM0313 Real-time clock (RTC) 23.6.2 RTC date register (RTC_DR) The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page 515 and Reading the calendar on page 516. This register is write protected. The write access procedure is described in RTC register write protection on page 515. Address offset: 0x04 Backup domain reset value: 0x0000 2101 System reset: 0x0000 2101 when BYPSHAD = 0. Not affected when BYPSHAD = 1. 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 rw rw rw rw WDU[2:0] rw rw MT rw rw MU[3:0] 23 22 21 20 19 18 YT[3:0] 17 16 YU[3:0] rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 Res. Res. rw rw rw rw rw DT[1:0] rw DU[3:0] Bits 31:24 Reserved, must be kept at reset value Bits 23:20 YT[3:0]: Year tens in BCD format Bits 19:16 YU[3:0]: Year units in BCD format Bits 15:13 WDU[2:0]: Week day units 000: forbidden 001: Monday ... 111: Sunday Bit 12 MT: Month tens in BCD format Bits 11:8 MU: Month units in BCD format Bits 7:6 Reserved, must be kept at reset value. Bits 5:4 DT[1:0]: Date tens in BCD format Bits 3:0 DU[3:0]: Date units in BCD format DocID022448 Rev 2 527/897 552 Real-time clock (RTC) 23.6.3 RM0313 RTC control register (RTC_CR) Address offset: 0x08 Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 27 26 25 24 23 Res. Res. Res. Res. Res. Res. Res. Res. COE 15 14 13 12 11 10 9 8 TSIE WUTIE ALRBIE ALRAIE rw rw rw rw TSE WUTE rw rw ALRBE ALRAE rw 22 21 OSEL[1:0] 20 19 18 POL COSEL BKP 17 16 SUB1H ADD1H rw rw rw rw rw rw w w 7 6 5 4 3 2 1 0 Res. rw FMT rw BYPS REFCKON TSEDGE HAD rw rw rw WUCKSEL[2:0] rw rw rw Bits 31:24 Reserved, must be kept at reset value. Bit 23 COE: Calibration output enable This bit enables the RTC_CALIB output 0: Calibration output disabled 1: Calibration output enabled Bits 22:21 OSEL[1:0]: Output selection These bits are used to select the flag to be routed to RTC_ALARM output 00: Output disabled 01: Alarm A output enabled 10: Alarm B output enabled 11: Wakeup output enabled Bit 20 POL: Output polarity This bit is used to configure the polarity of RTC_ALARM output 0: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) 1: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]). Bit 19 COSEL: Calibration output selection When COE=1, this bit selects which signal is output on RTC_CALIB. 0: Calibration output is 512 Hz 1: Calibration output is 1 Hz These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A=127 and PREDIV_S=255). Refer to Section 23.3.15: Calibration clock output Bit 18 BKP: Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not. Bit 17 SUB1H: Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0. 0: No effect 1: Subtracts 1 hour to the current time. This can be used for winter time change. 528/897 DocID022448 Rev 2 RM0313 Real-time clock (RTC) Bit 16 ADD1H: Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. 0: No effect 1: Adds 1 hour to the current time. This can be used for summer time change Bit 15 TSIE: Time-stamp interrupt enable 0: Time-stamp Interrupt disable 1: Time-stamp Interrupt enable Bit 14 WUTIE: Wakeup timer interrupt enable 0: Wakeup timer interrupt disabled 1: Wakeup timer interrupt enabled Bit 13 ALRBIE: Alarm B interrupt enable 0: Alarm B Interrupt disable 1: Alarm B Interrupt enable Bit 12 ALRAIE: Alarm A interrupt enable 0: Alarm A interrupt disabled 1: Alarm A interrupt enabled Bit 11 TSE: timestamp enable 0: timestamp disable 1: timestamp enable Bit 10 WUTE: Wakeup timer enable 0: Wakeup timer disabled 1: Wakeup timer enabled Bit 9 ALRBE: Alarm B enable 0: Alarm B disabled 1: Alarm B enabled Bit 8 ALRAE: Alarm A enable 0: Alarm A disabled 1: Alarm A enabled Bit 7 Reserved, must be kept at reset value. Bit 6 FMT: Hour format 0: 24 hour/day format 1: AM/PM hour format Bit 5 BYPSHAD: Bypass the shadow registers 0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles. 1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters. Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to ‘1’. DocID022448 Rev 2 529/897 552 Real-time clock (RTC) RM0313 Bit 4 REFCKON: RTC_REFIN reference clock detection enable (50 or 60 Hz) 0: RTC_REFIN detection disabled 1: RTC_REFIN detection enabled Note: PREDIV_S must be 0x00FF. Bit 3 TSEDGE: Time-stamp event active edge 0: RTC_TS input rising edge generates a time-stamp event 1: RTC_TS input falling edge generates a time-stamp event TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting. Bits 2:0 WUCKSEL[2:0]: Wakeup clock selection 000: RTC/16 clock is selected 001: RTC/8 clock is selected 010: RTC/4 clock is selected 011: RTC/2 clock is selected 10x: ck_spre (usually 1 Hz) clock is selected 11x: ck_spre (usually 1 Hz) clock is selected and 216 is added to the WUT counter value (see note below) Note: Bits 7, 6 and 4 of this register can be written in initialization mode only (RTC_ISR/INITF = 1). WUT = Wakeup unit counter value. WUT = (0x0000 to 0xFFFF) + 0x10000 added when WUCKSEL[2:1 = 11]. Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1. It is recommended not to change the hour during the calendar hour increment as it could mask the incrementation of the calendar hour. ADD1H and SUB1H changes are effective in the next second. This register is write protected. The write access procedure is described in RTC register write protection on page 515. 530/897 DocID022448 Rev 2 RM0313 Real-time clock (RTC) 23.6.4 RTC initialization and status register (RTC_ISR) This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure is described in RTC register write protection on page 515. Address offset: 0x0C Backup domain reset value: 0x0000 0007 System reset: not affected except INIT, INITF, and RSF bits which are cleared to ‘0’ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RECALPF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSF WUTF ALRB F ALRAF INIT INITF RSF INITS SHPF WUT WF ALRB WF ALRAWF rc_w0 rc_w0 rc_w0 rc_w0 rw r rc_w0 r r r r r r TAMP TAMP2F TAMP1F TSOVF 3F rc_w0 rc_w0 rc_w0 rc_w0 Bits 31:17 Reserved, must be kept at reset value Bit 16 RECALPF: Recalibration pending Flag The RECALPF status flag is automatically set to ‘1’ when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to ‘0’. Refer to Re-calibration on-the-fly. Bit 15 TAMP3F: RTC_TAMP3 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP3 input. It is cleared by software writing 0 Bit 14 TAMP2F: RTC_TAMP2 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP2 input. It is cleared by software writing 0 Bit 13 TAMP1F: RTC_TAMP1 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP1 input. It is cleared by software writing 0 Bit 12 TSOVF: Time-stamp overflow flag This flag is set by hardware when a time-stamp event occurs while TSF is already set. This flag is cleared by software by writing 0. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared. Bit 11 TSF: Time-stamp flag This flag is set by hardware when a time-stamp event occurs. This flag is cleared by software by writing 0. Bit 10 WUTF: Wakeup timer flag This flag is set by hardware when the wakeup auto-reload counter reaches 0. This flag is cleared by software by writing 0. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. DocID022448 Rev 2 531/897 552 Real-time clock (RTC) RM0313 Bit 9 ALRBF: Alarm B flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR). This flag is cleared by software by writing 0. Bit 8 ALRAF: Alarm A flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR). This flag is cleared by software by writing 0. Bit 7 INIT: Initialization mode 0: Free running mode 1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. Bit 6 INITF: Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. 0: Calendar registers update is not allowed 1: Calendar registers update is allowed. Bit 5 RSF: Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow register mode (BYPSHAD=1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode. 0: Calendar shadow registers not yet synchronized 1: Calendar shadow registers synchronized Bit 4 INITS: Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state). 0: Calendar has not been initialized 1: Calendar has been initialized Bit 3 SHPF: Shift operation pending 0: No shift operation is pending 1: A shift operation is pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect. 532/897 DocID022448 Rev 2 RM0313 Real-time clock (RTC) Bit 2 WUTWF: Wakeup timer write flag This bit is set by hardware when the wakeup timer values can be changed, after the WUTE bit has been set to 0 in RTC_CR. 0: Wakeup timer configuration update not allowed 1: Wakeup timer configuration update allowed. Bit 1 ALRBWF: Alarm B write flag This bit is set by hardware when Alarm B values can be changed, after the ALRBE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode. 0: Alarm B update not allowed 1: Alarm B update allowed Bit 0 ALRAWF: Alarm A write flag This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode. 0: Alarm A update not allowed 1: Alarm A update allowed Note: The bits ALRAF, ALRBF, WUTF and TSF are cleared 2 APB clock cycles after programming them to 0. DocID022448 Rev 2 533/897 552 Real-time clock (RTC) 23.6.5 RM0313 RTC prescaler register (RTC_PRER) This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page 515. This register is write protected. The write access procedure is described in RTC register write protection on page 515. Address offset: 0x10 Backup domain reset value: 0x007F 00FF System reset: not affected 31 30 29 28 27 26 25 24 23 Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 rw rw rw rw rw rw rw Res. 22 21 19 18 17 16 PREDIV_A[6:0] rw rw rw rw rw rw rw 6 5 4 3 2 1 0 rw rw rw rw rw rw rw PREDIV_S[14:0] rw Bits 31:23 Reserved, must be kept at reset value Bits 22:16 PREDIV_A[6:0]: Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) Bit 15 Reserved, must be kept at reset value. Bits 14:0 PREDIV_S[14:0]: Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1) 534/897 20 DocID022448 Rev 2 RM0313 Real-time clock (RTC) 23.6.6 RTC wakeup timer register (RTC_WUTR) This register can be written only when WUTWF is set to 1 in RTC_ISR. This register is write protected. The write access procedure is described in RTC register write protection on page 515. Address offset: 0x14 Backup domain reset value: 0x0000 FFFF System reset: not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw WUT[15:0] rw Bits 31:16 Reserved, must be kept at reset value Bits 15:0 WUT[15:0]: Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden. DocID022448 Rev 2 535/897 552 Real-time clock (RTC) 23.6.7 RM0313 RTC alarm A register (RTC_ALRMAR) This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page 515. Address offset: 0x1C Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 MSK4 WDSEL 29 28 27 DT[1:0] 26 25 24 DU[3:0] 23 22 MSK3 PM 21 20 19 18 HT[1:0] 17 16 HU[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw MSK2 rw MNT[2:0] rw rw MNU[3:0] rw rw rw MSK1 rw rw rw ST[2:0] rw rw Bit 31 MSK4: Alarm A date mask 0: Alarm A set if the date/day match 1: Date/day don’t care in Alarm A comparison Bit 30 WDSEL: Week day selection 0: DU[3:0] represents the date units 1: DU[3:0] represents the week day. DT[1:0] is don’t care. Bits 29:28 DT[1:0]: Date tens in BCD format. Bits 27:24 DU[3:0]: Date units or day in BCD format. Bit 23 MSK3: Alarm A hours mask 0: Alarm A set if the hours match 1: Hours don’t care in Alarm A comparison Bit 22 PM: AM/PM notation 0: AM or 24-hour format 1: PM Bits 21:20 HT[1:0]: Hour tens in BCD format. Bits 19:16 HU[3:0]: Hour units in BCD format. Bit 15 MSK2: Alarm A minutes mask 0: Alarm A set if the minutes match 1: Minutes don’t care in Alarm A comparison Bits 14:12 MNT[2:0]: Minute tens in BCD format. Bits 11:8 MNU[3:0]: Minute units in BCD format. Bit 7 MSK1: Alarm A seconds mask 0: Alarm A set if the seconds match 1: Seconds don’t care in Alarm A comparison Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. 536/897 DocID022448 Rev 2 SU[3:0] rw rw rw RM0313 Real-time clock (RTC) 23.6.8 RTC alarm B register (RTC_ALRMBR) This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page 515. Address offset: 0x20 Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 MSK4 WDSEL 29 28 27 DT[1:0] 26 25 24 DU[3:0] 23 22 MSK3 PM 21 20 19 18 HT[1:0] 17 16 HU[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw MSK2 rw MNT[2:0] rw rw MNU[3:0] rw rw rw rw MSK1 rw rw ST[2:0] rw rw SU[3:0] rw rw rw Bit 31 MSK4: Alarm B date mask 0: Alarm B set if the date and day match 1: Date and day don’t care in Alarm B comparison Bit 30 WDSEL: Week day selection 0: DU[3:0] represents the date units 1: DU[3:0] represents the week day. DT[1:0] is don’t care. Bits 29:28 DT[1:0]: Date tens in BCD format Bits 27:24 DU[3:0]: Date units or day in BCD format Bit 23 MSK3: Alarm B hours mask 0: Alarm B set if the hours match 1: Hours don’t care in Alarm B comparison Bit 22 PM: AM/PM notation 0: AM or 24-hour format 1: PM Bits 21:20 HT[1:0]: Hour tens in BCD format Bits 19:16 HU[3:0]: Hour units in BCD format Bit 15 MSK2: Alarm B minutes mask 0: Alarm B set if the minutes match 1: Minutes don’t care in Alarm B comparison Bits 14:12 MNT[2:0]: Minute tens in BCD format Bits 11:8 MNU[3:0]: Minute units in BCD format Bit 7 MSK1: Alarm B seconds mask 0: Alarm B set if the seconds match 1: Seconds don’t care in Alarm B comparison Bits 6:4 ST[2:0]: Second tens in BCD format Bits 3:0 SU[3:0]: Second units in BCD format DocID022448 Rev 2 537/897 552 Real-time clock (RTC) 23.6.9 RM0313 RTC write protection register (RTC_WPR) Address offset: 0x24 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 1 0 w w w w 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. Res. KEY w w w w Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 KEY: Write protection key This byte is written by software. Reading this byte always returns 0x00. Refer to RTC register write protection for a description of how to unlock RTC register write protection. 538/897 DocID022448 Rev 2 RM0313 Real-time clock (RTC) 23.6.10 RTC sub second register (RTC_SSR) Address offset: 0x28 Backup domain reset value: 0x0000 0000 System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r SS[15:0] r r r r r r r r r Bits31:16 Reserved, must be kept at reset value Bits 15:0 SS: Sub second value SS[15:0] is the value in the synchronous prescaler’s counter. The fraction of a second is given by the formula below: Second fraction = ( PREDIV_S - SS ) / ( PREDIV_S + 1 ) Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR. DocID022448 Rev 2 539/897 552 Real-time clock (RTC) 23.6.11 RM0313 RTC shift control register (RTC_SHIFTR) This register is write protected. The write access procedure is described in RTC register write protection on page 515. Address offset: 0x2C Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADD1S Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w w w w w w w w 15 Res. SUBFS[14:0] w w w w w w w w Bit 31 ADD1S: Add one second 0: No effect 1: Add one second to the clock/calendar This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation. Bits 30:15 Reserved, must be kept at reset value Bits 14:0 SUBFS: Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). The value which is written to SUBFS is added to the synchronous prescaler’s counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / ( PREDIV_S + 1 ) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = ( 1 - ( SUBFS / ( PREDIV_S + 1 ) ) ) . Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF=1 to be sure that the shadow registers have been updated with the shifted time. 540/897 DocID022448 Rev 2 RM0313 Real-time clock (RTC) 23.6.12 RTC timestamp time register (RTC_TSTR) The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset. Address offset: 0x30 Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 27 26 25 24 23 22 Res. Res. Res. Res. Res. Res. Res. Res. Res. PM r 15 14 Res. 13 12 11 MNT[2:0] r r 10 9 8 MNU[3:0] r r r 7 6 Res. r r 21 20 19 18 HT[1:0] r r r r 5 4 3 2 ST[2:0] r r 17 16 HU[3:0] r r 1 0 r r SU[3:0] r r r Bits 31:23 Reserved, must be kept at reset value Bit 22 PM: AM/PM notation 0: AM or 24-hour format 1: PM Bits 21:20 HT[1:0]: Hour tens in BCD format. Bits 19:16 HU[3:0]: Hour units in BCD format. Bit 15 Reserved, must be kept at reset value Bits 14:12 MNT[2:0]: Minute tens in BCD format. Bits 11:8 MNU[3:0]: Minute units in BCD format. Bit 7 Reserved, must be kept at reset value Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. DocID022448 Rev 2 541/897 552 Real-time clock (RTC) 23.6.13 RM0313 RTC timestamp date register (RTC_TSDR) The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset. Address offset: 0x34 Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. r r 15 WDU[1:0] r r MT r r MU[3:0] r r r r Bits 31:16 Reserved, must be kept at reset value Bits 15:13 WDU[1:0]: Week day units Bit 12 MT: Month tens in BCD format Bits 11:8 MU[3:0]: Month units in BCD format Bits 7:6 Reserved, must be kept at reset value Bits 5:4 DT[1:0]: Date tens in BCD format Bit 3:0 DU[3:0]: Date units in BCD format 542/897 DocID022448 Rev 2 DT[1:0] r DU[3:0] r r r RM0313 Real-time clock (RTC) 23.6.14 RTC time-stamp sub second register (RTC_TSSSR) The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the RTC_ISR/TSF bit is reset. Address offset: 0x38 Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r SS[15:0] r r r r r r r r r Bits 31:16 Reserved, must be kept at reset value Bits 15:0 SS: Sub second value SS[15:0] is the value of the synchronous prescaler’s counter when the timestamp event occurred. DocID022448 Rev 2 543/897 552 Real-time clock (RTC) 23.6.15 RM0313 RTC calibration register (RTC_CALR) This register is write protected. The write access procedure is described in RTC register write protection on page 515. Address offset: 0x3C Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CALP CALW8 CALW 16 Res. Res. Res. Res. rw rw rw rw rw rw rw CALM[8:0] rw rw rw rw rw Bit 31:16 Reserved, must be kept at reset value Bit 15 CALP: Increase frequency of RTC by 488.5 ppm 0: No RTCCLK pulses are added. 1: One RTCCLK pulse is effectively inserted every 211 pulses (frequency increased by 488.5 ppm). This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 * CALP) - CALM. Refer to Section 23.3.12: RTC smooth digital calibration. Bit 14 CALW8: Use an 8-second calibration cycle period When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected. Note: CALM[1:0] are stuck at “00” when CALW8=’1’. Refer to Section 23.3.12: RTC smooth digital calibration. Bit 13 CALW16: Use a 16-second calibration cycle period When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1. Note: CALM[0] is stuck at ‘0’ when CALW16=’1’. Refer to Section 23.3.12: RTC smooth digital calibration. Bits 12:9 Reserved, must be kept at reset value Bits 8:0 CALM[8:0]: Calibration minus The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See Section 23.3.12: RTC smooth digital calibration on page 519. 544/897 DocID022448 Rev 2 RM0313 Real-time clock (RTC) 23.6.16 RTC tamper and alternate function configuration register (RTC_TAFCR) Address offset: 0x40 Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 TAMPP UDIS rw TAMPPRCH [1:0] rw rw TAMPFLT[1:0] rw rw TAMPFREQ[2:0] rw rw rw 23 22 21 20 19 PC15 PC15 PC14 PC14 PC13 MODE VALUE MODE VALUE MODE 18 17 16 PC13 VALUE Res. Res. 1 0 rw rw rw rw rw rw 7 6 5 4 3 2 TAMPT TAMP3 TAMP3 TAMP2 TAMP2 S -TRG E TRG E rw rw rw rw rw TAMPIE rw TAMP1 TAMP1 TRG E rw rw Bit 31:24 Reserved, must be kept at reset value. Bit 23 PC15MODE: PC15 mode 0: PC15 is controlled by the GPIO configuration registers. Consequently PC15 is floating in Standby mode. 1: PC15 is forced to push-pull output if LSE is disabled. Bit 22 PC15VALUE: PC15 value If the LSE is disabled and PC15MODE = 1, PC15VALUE configures the PC15 output data. Bit 21 PC14MODE: PC14 mode 0: PC14 is controlled by the GPIO configuration registers. Consequently PC14 is floating in Standby mode. 1: PC14 is forced to push-pull output if LSE is disabled. Bit 20 PC14VALUE: PC14 value If the LSE is disabled and PC14MODE = 1, PC14VALUE configures the PC14 output data. Bit 19 PC13MODE: PC13 mode 0: PC13 is controlled by the GPIO configuration registers. Consequently PC13 is floating in Standby mode. 1: PC13 is forced to push-pull output if all RTC alternate functions are disabled. Bit 18 PC13VALUE: RTC_ALARM output type/PC13 value If PC13 is used to output RTC_ALARM, PC13VALUE configures the output configuration: 0: RTC_ALARM is an open-drain output 1: RTC_ALARM is a push-pull output If all RTC alternate functions are disabled and PC13MODE = 1, PC13VALUE configures the PC13 output data. Bits 17:16 Reserved, must be kept at reset value. Bit 15 TAMPPUDIS: RTC_TAMPx pull-up disable This bit determines if each of the RTC_TAMPx pins are pre-charged before each sample. 0: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) 1: Disable precharge of RTC_TAMPx pins. DocID022448 Rev 2 545/897 552 Real-time clock (RTC) RM0313 Bits 14:13 TAMPPRCH[1:0]: RTC_TAMPx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the RTC_TAMPx inputs. 0x0: 1 RTCCLK cycle 0x1: 2 RTCCLK cycles 0x2: 4 RTCCLK cycles 0x3: 8 RTCCLK cycles Bits 12:11 TAMPFLT[1:0]: RTC_TAMPx filter count These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a Tamper event. TAMPFLT is valid for each of the RTC_TAMPx inputs. 0x0: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input). 0x1: Tamper event is activated after 2 consecutive samples at the active level. 0x2: Tamper event is activated after 4 consecutive samples at the active level. 0x3: Tamper event is activated after 8 consecutive samples at the active level. Bits 10:8 TAMPFREQ[2:0]: Tamper sampling frequency Determines the frequency at which each of the RTC_TAMPx inputs are sampled. 0x0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) 0x1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) 0x2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) 0x3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) 0x4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) 0x5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) 0x6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) 0x7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) Bit 7 TAMPTS: Activate timestamp on tamper detection event 0: Tamper detection event does not cause a timestamp to be saved 1: Save timestamp on tamper detection event TAMPTS is valid even if TSE=0 in the RTC_CR register. Bit 6 TAMP3TRG: Active level for RTC_TAMP3 input if TAMPFLT != 00: 0: RTC_TAMP3 input staying low triggers a tamper detection event. 1: RTC_TAMP3 input staying high triggers a tamper detection event. if TAMPFLT = 00: 0: RTC_TAMP3 input rising edge triggers a tamper detection event. 1: RTC_TAMP3input falling edge triggers a tamper detection event. Bit 5 TAMP3E: RTC_TAMP3 detection enable 0: RTC_TAMP3 input detection disabled 1: RTC_TAMP3 input detection enabled Bit 4 TAMP2TRG: Active level for RTC_TAMP2 input if TAMPFLT != 00: 0: RTC_TAMP2 input staying low triggers a tamper detection event. 1: RTC_TAMP2 input staying high triggers a tamper detection event. if TAMPFLT = 00: 0: RTC_TAMP2 input rising edge triggers a tamper detection event. 1: RTC_TAMP2 input falling edge triggers a tamper detection event. 546/897 DocID022448 Rev 2 RM0313 Real-time clock (RTC) Bit 3 TAMP2E: RTC_TAMP2 input detection enable 0: RTC_TAMP2 detection disabled 1: RTC_TAMP2 detection enabled Bit 2 TAMPIE: Tamper interrupt enable 0: Tamper interrupt disabled 1: Tamper interrupt enabled. Bit 1 TAMP1TRG: Active level for RTC_TAMP1 input If TAMPFLT != 00 0: RTC_TAMP1 input staying low triggers a tamper detection event. 1: RTC_TAMP1 input staying high triggers a tamper detection event. if TAMPFLT = 00: 0: RTC_TAMP1 input rising edge triggers a tamper detection event. 1: RTC_TAMP1 input falling edge triggers a tamper detection event. Bit 0 TAMP1E: RTC_TAMP1 input detection enable 0: RTC_TAMP1 detection disabled 1: RTC_TAMP1 detection enabled Caution: When TAMPFLT = 0, TAMP1E must be reset when TAMP1TRG is changed to avoid spuriously setting TAMP1F. DocID022448 Rev 2 547/897 552 Real-time clock (RTC) 23.6.17 RM0313 RTC alarm A sub second register (RTC_ALRMASSR) This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page 515 Address offset: 0x44 Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 Res. Res. Res. Res. 27 26 25 24 rw rw rw rw 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw MASKSS[3:0] Res. 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 1 0 rw rw rw rw w rw rw SS[14:0] rw Bits 31:28 Reserved, must be kept at reset value. Bits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit 0: No comparison on sub seconds for Alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). 1: SS[14:1] are don’t care in Alarm A comparison. Only SS[0] is compared. 2: SS[14:2] are don’t care in Alarm A comparison. Only SS[1:0] are compared. 3: SS[14:3] are don’t care in Alarm A comparison. Only SS[2:0] are compared. ... 12: SS[14:12] are don’t care in Alarm A comparison. SS[11:0] are compared. 13: SS[14:13] are don’t care in Alarm A comparison. SS[12:0] are compared. 14: SS[14] is don’t care in Alarm A comparison. SS[13:0] are compared. 15: All 15 SS bits are compared and must match to activate alarm. The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. Bits23:15 Reserved, must be kept at reset value. Bits 14:0 SS[14:0]: Sub seconds value This value is compared with the contents of the synchronous prescaler’s counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. 548/897 DocID022448 Rev 2 RM0313 Real-time clock (RTC) 23.6.18 RTC alarm B sub second register (RTC_ALRMBSSR) This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode. This register is write protected.The write access procedure is described in Section : RTC register write protection. Address offset: 0x48 Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 Res. Res. Res. Res. 27 26 25 24 rw rw rw rw 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw MASKSS[3:0] Res. 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 1 0 rw rw rw rw w rw rw SS[14:0] rw Bits 31:28 Reserved, must be kept at reset value. Bits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit 0x0: No comparison on sub seconds for Alarm B. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). 0x1: SS[14:1] are don’t care in Alarm B comparison. Only SS[0] is compared. 0x2: SS[14:2] are don’t care in Alarm B comparison. Only SS[1:0] are compared. 0x3: SS[14:3] are don’t care in Alarm B comparison. Only SS[2:0] are compared. ... 0xC: SS[14:12] are don’t care in Alarm B comparison. SS[11:0] are compared. 0xD: SS[14:13] are don’t care in Alarm B comparison. SS[12:0] are compared. 0xE: SS[14] is don’t care in Alarm B comparison. SS[13:0] are compared. 0xF: All 15 SS bits are compared and must match to activate alarm. The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. Bits 23:15 Reserved, must be kept at reset value. Bits 14:0 SS[14:0]: Sub seconds value This value is compared with the contents of the synchronous prescaler’s counter to determine if Alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared. DocID022448 Rev 2 549/897 552 Real-time clock (RTC) 23.6.19 RM0313 RTC backup registers (RTC_BKPxR) Address offset: 0x50 to 0xCC Backup domain reset value: 0x0000 0000 System reset: not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BKP[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw w rw rw BKP[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 BKP[31:0] The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled. 550/897 DocID022448 Rev 2 RM0313 Real-time clock (RTC) 23.6.20 RTC register map ALRAF 0 0 0 1 1 1 1 1 1 1 Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 PM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC_WPR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 DU[3:0] 0 0 0 0 0 HT [1:0] 0 0 0 0 HU[3:0] MNT[2:0] 0 0 0 MNU[3:0] 0 MNT[2:0] 0 0 0 MNU[3:0] Res. 0 0 0 0 0 Res. Res. Res. Res. WDU[1:0] 0 MT 0 0 Res. 0 0 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reset value 1 ST[2:0] 0 0 0 SU[3:0] 0 ST[2:0] 0 0 0 0 0 0 SU[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MU[3:0] 0 0 0 0 0 0 0 0 0 0 0 ST[2:0] 0 0 0 0 SU[3:0] 0 DT [1:0] 0 0 0 DU[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 SS[15:0] 0 DocID022448 Rev 2 1 KEY Res. 0 Res. Res. Res. Res. 0 MNT[2:0] Res. HT[1:0] 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 MNU[3:0] Res. PM 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 Res. RTC_TSSSR 0 SUBFS[14:0] 0 Reset value 0x38 0 Res. Res. Res. Res. Res. HU[3:0] 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RTC_TSDR Res. Reset value 0x34 Res. Res. Res. Res. Res. Res. Res. Res. RTC_TSTR 0 0 Res. 0 Res. ADD1S Reset value Res. RTC_SHIFTR Res. 0x30 0 WUCKS EL[2:0] SS[15:0] 0 Res. Reset value 0x2C 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RTC_SSR 0 0 Res. Reset value 0x28 0 MSK2 DT [1:0] 0 HU[3:0] MSK2 0 1 0 MSK1 MSK3 Reset value 0 MSK2 RTC_ALRMBR 0 PM 0 MSK3 0 Res. 1 Res. 1 Res. 1 MSK4 1 WDSEL 1 MSK4 1 WDSEL 1 Reset value HT [1:0] 0 WUT[15:0] RTC_ALRMAR DU[3:0] 0 PREDIV_S[14:0] 1 DT [1:0] 0 ALRAWF WUTF ALRBF 0 0 ALRBWF TSF 0 0 TSEDGE TSOVF 0 DU[3:0] SHPF TAMP1F 0 0 WUT WF 0 0 BYPSHAD 0 DT [1:0] 0 REFCKON 0 0 RSF 0 0 INITS ALRAE 0 Res. 0x24 Res. WUTE ALRBE 0 Res. 0x20 Res. TSE 0 0 SU[3:0] FMT ALRAIE 0 Res. ALRBIE 0 Reset value 0x1C 1 0 Res. Res. Res. Res. Res. Res. Res. Res. RTC_WUTR Res. 0x14 Res. Reset value 0 PREDIV_A[6:0] 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RTC_PRER 0 0 Reset value 0x10 0 TSIE 0 MU[3:0] WUTIE 1 0 .TAMP2F 0 0 ADD1H 0 0 Res. 0 WDU[2:0] 0 TAMP3F 0 0 0 BKP 0 0 0 SUB1H POL COSEL 0 0 0 ST[2:0] INITF Res. 0 MNU[3:0] INIT 0 Res. 0 Res. OSE L [1:0] 0 Res. 0 Res. COE 0 0 MNT[2:0] MT 0 YU[3:0] Res. Res. Res. Res. Res. Res. Res. RTC_ISR Res. 0x0C Res. Reset value 0 Res. Res. Res. Res. Res. Res. Res. RTC_CR Res. 0x08 0 HU[3:0] YT[3:0] 0 Res. Reset value HT [1:0] Res. Res. Res. Res. Res. Res. Res. RTC_DR Res. 0x04 0 Res. Reset value PM Res. Res. Res. Res. Res. Res. Res. RTC_TR Res. 0x00 Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 66. RTC register map and reset values 0 0 0 0 0 0 0 0 0 551/897 552 Real-time clock (RTC) RM0313 Reset value 0 0 0 Reset value 0 TAMP1E 0 .TAMPIE 0 TAMP1TRG 0 .TAMP2E 0 TAMP3E 0 0 TAMP2-TRG Res. Res. Res. CALW8 CALW16 Res. CALP Res. 0 0 0 0 0 0 Res. Res. Res. 0 0 TAMPTS Res. Res. 0 0 TAMP3-TRG Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS[14:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKP[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKP[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Refer to Section 2.2.2 for the register boundary addresses. 552/897 TAMPFREQ[2:0] Res. Res. 0 0 SS[14:0] 0 Res. TAMPFLT[1:0] Res. 0 CALM[8:0] 0 TAMPPRCH[1:0] PC13VALUE Res. 0 0 to RTC_BKP31R Reset value 0 0 RTC_BKP0R 0x50 to 0xCC 0 Res. PC13VALUE 0 Res. PC14MODE 0 Res. PC14VALUE 0 Res. PC15MODE 0 Res. PC15MODE 0 Res. 0 0 Res. 0 MASKSS [3:0] Res. Res. Res. RTC_ ALRMASSR 0 Res. Reset value 0x48 MASKSS [3:0] Res. Res. RTC_ ALRMASSR Res. 0x44 Res. Reset value Res. Res. Res. Res. Res. Res. Res. RTC_TAFCR Res. 0x40 Res. Reset value TAMPPUDIS Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RTC_ CALR Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x3C Register Res. Offset Res. Table 66. RTC register map and reset values (continued) DocID022448 Rev 2 Inter-integrated circuit (I2C) interface RM0313 24 Inter-integrated circuit (I2C) interface 24.1 Introduction The I2C (inter-integrated circuit) bus interface handles communications between the microcontroller and the serial I2C bus. It provides multimaster capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports standard speed mode, Fast Mode and Fast Mode Plus. It is also SMBus (system management bus) and PMBus (power management bus) compatible. DMA can be used to reduce CPU overload. 24.2 I2C main features • I2C bus specification rev03 compatibility: – Slave and master modes – Multimaster capability – Standard mode (up to 100 kHz) – Fast Mode (up to 400 kHz) – Fast Mode Plus (up to 1 MHz) – 7-bit and 10-bit addressing mode – Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) – All 7-bit addresses acknowledge mode – General call – Programmable setup and hold times – Easy to use event management – Optional clock stretching – Software reset • 1-byte buffer with DMA capability • Programmable analog and digital noise filters DocID022448 Rev 2 553/897 619 Inter-integrated circuit (I2C) interface RM0313 The following additional features are also available depending on the product implementation (see Section 24.3: I2C implementation): • SMBus specification rev 2.0 compatibility: – 24.3 Hardware PEC (Packet Error Checking) generation and verification with ACK control – Command and data acknowledge control – Address resolution protocol (ARP) support – Host and Device support – SMBus alert – Timeouts and idle condition detection • PMBus rev 1.1 standard compatibility • Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming • Wakeup from Stop on address match. I2C implementation This manual describes the full set of features implemented in I2C1. In the STM32F37xx/STM32F38xx devices both I2C1 and I2C2 are identical and implement the full set of features as shown in the following table. Table 67. STM32F37xx/STM32F38xx I2C implementation I2C features(1) I2C1 I2C2 Independent clock X X SMBus X X Wakeup from Stop X X 20 mA output drive for FM+ mode X X 1. X = supported. 24.4 I2C functional description In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa. The interrupts are enabled or disabled by software. The interface is connected to the I2C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected with a standard (up to 100 kHz), Fast Mode (up to 400 kHz) or Fast Mode Plus (up to 1 MHz) I2C bus. This interface can also be connected to a SMBus with the data pin (SDA) and clock pin (SCL). If SMBus feature is supported: the additional optional SMBus Alert pin (SMBA) is also available. 554/897 DocID022448 Rev 2 Inter-integrated circuit (I2C) interface RM0313 24.4.1 I2C block diagram The block diagram of the I2C interface is shown in Figure 167. Figure 167. I2C block diagram 6<6&/. ,&&/. )URPV\VWHPFRQILJXUDWLRQ FRQWUROOHU6<6&)* )0GULYH +6, 'DWDFRQWURO 6KLIWUHJLVWHU 5&&B,&6: IURPUHVHWDQG FORFN FRQWUROOHU 'LJLWDO QRLVH ILOWHU :83(1 $QDORJ QRLVH ILOWHU *3,2 ORJLF ,&B6'$ 60%86 3(& JHQHUDWLRQ FKHFN :DNHXS RQ DGGUHVV PDWFK )URPV\VWHPFRQILJXUDWLRQ FRQWUROOHU6<6&)* )0GULYH &ORFNFRQWURO 0DVWHUFORFN JHQHUDWLRQ 6ODYHFORFN VWUHWFKLQJ 'LJLWDO QRLVH ILOWHU $QDORJ QRLVH ILOWHU *3,2 ORJLF ,&B6&/ 60%XV 7LPHRXW FKHFN 60%XV$OHUW FRQWURO VWDWXV 3&/. ,&B60%$ 5HJLVWHUV $3%EXV 069 The I2C is clocked by an independent clock source which allows to the I2C to operate independently from the PCLK frequency. This independent clock source can be selected for either of the following two clock sources: • HSI: high speed internal oscillator (default value) • SYSCLK: system clock Refer to Section 7: Reset and clock control (RCC) for more details. I2C I/Os support 20 mA output current drive for Fast Mode Plus operation. This is enabled by setting the driving capability control bits for SCL and SDA in the Section 10.1.1: SYSCFG configuration register 1 (SYSCFG_CFGR1). DocID022448 Rev 2 555/897 619 Inter-integrated circuit (I2C) interface 24.4.2 RM0313 I2C clock requirements The I2C kernel is clocked by I2CCLK. The I2CCLK period tI2CCLK must respect the following conditions: tI2CCLK < (tLOW - tfilters ) / 4 and tI2CCLK < tHIGH with: tLOW: SCL low time and tHIGH : SCL high time tfilters: when enabled, sum of the delays brough
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