Nuvoton TRM ISD91200 Technical Reference Manual

ISD91200 Series Technical Reference Manual

ISD ARM

®

Cortex

®

-M0 SoC

ISD91200 Series

Technical Reference Manual

The information described in this document is the exclusive intellectual property of

Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.

Nuvoton is providing this document only for reference purposes of ISD ARM® Cortex®-M0 microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions.

All data and specifications are subject to change without notice.

For additional information or questions, please contact: Nuvoton Technology Corporation.

Release Date: Sep 16, 2019

Revision 2.4 - 1 -


Table of Contents-

TABLE OF CONTENTS- .................................................................................................................. 2

1 GENERAL DESCRIPTION ..................................................................................................... 9

2 FEATURES ........................................................................................................................... 10

3 PART INFORMATION AND PIN CONFIGURATION ........................................................... 14

3.1

Pin Configuration ........................................................................................................ 14

3.2

Pin Description ........................................................................................................... 15

4 BLOCK DIAGRAM ................................................................................................................ 20

5 FUNCTIONAL DESCRIPTION .............................................................................................. 21

5.1

ARM

®

Cortex™-M0 core ............................................................................................ 21

5.2

System Manager ........................................................................................................ 23

5.2.1

Overview ......................................................................................................................... 23

5.2.2

System Reset .................................................................................................................. 23

5.2.3

System Power Distribution .............................................................................................. 24

5.2.4

System Memory Map ...................................................................................................... 25

5.2.5

System Manager Control Registers ................................................................................ 27

5.2.6

System Timer (SysTick) .................................................................................................. 51

5.2.7

Nested Vectored Interrupt Controller (NVIC)................................................................... 55

5.2.8

System Control Registers ............................................................................................. 101

5.3

Clock Controller and Power Management Unit (PMU) ............................................ 109

5.3.1

Clock Generator ............................................................................................................ 109

5.3.2

System Clock & SysTick Clock ..................................................................................... 110

5.3.3

Peripheral Clocks .......................................................................................................... 111

5.3.4

Power Management ...................................................................................................... 111

5.3.5

Register Map ................................................................................................................. 113

5.3.6

Register Description ...................................................................................................... 114

5.4

General Purpose I/O ................................................................................................ 131

5.4.1

Overview and Features ................................................................................................. 131

5.4.2

GPIO I/O Modes ........................................................................................................... 131

5.4.3

GPIO Control Register Map .......................................................................................... 133

5.4.4


5.5

Brownout Detection and Temperature Alarm ........................................................... 144

5.5.1

Brownout Register Map ................................................................................................ 144

5.5.2

Brownout Register Description ...................................................................................... 145

5.6

I2C Serial Interface Controller (Master/Slave) ......................................................... 148

5.6.1

Introduction ................................................................................................................... 148

5.6.2

Modes of Operation ...................................................................................................... 152

5.6.3

Data Transfer Flow in Five Operating Modes ................................................................ 153

5.6.4

I2C Protocol Registers .................................................................................................. 159

5.6.5

Register Mapping .......................................................................................................... 162

5.6.6


5.7

PWM Generator and Capture Timer ........................................................................ 170

5.7.1

Introduction ................................................................................................................... 170

5.7.2

Features ........................................................................................................................ 170

5.7.3

PWM Generator Architecture ........................................................................................ 172

- 2 -


Revision 2.4


5.7.4

PWM-Timer Operation .................................................................................................. 172

5.7.5

PWM Double Buffering, Auto-reload and One-shot Operation ...................................... 174

5.7.6

Modulate Duty Cycle ..................................................................................................... 174

5.7.7

Dead-Zone Generator ................................................................................................... 175

5.7.8

Capture Timer Operation .............................................................................................. 176

5.7.9

PWM-Timer Interrupt Architecture ................................................................................ 177

5.7.10

PWM-Timer Initialization Procedure ............................................................................ 177

5.7.11

PWM-Timer Stop Procedure ....................................................................................... 177

5.7.12

Capture Start Procedure ............................................................................................. 178

5.7.13

Register Map ............................................................................................................... 179

5.7.14

Register Description .................................................................................................... 181

5.8

Real Time Clock (RTC) Overview ........................................................................... 198

5.8.1

RTC Features ............................................................................................................... 198

5.8.2

RTC Block Diagram ...................................................................................................... 199

5.8.3

RTC Function Description ............................................................................................. 199

5.8.4

Register Map ................................................................................................................. 202

5.8.5


5.9

Serial 0 Peripheral Interface (SPI0) Controller ......................................................... 216

5.9.1

Overview ....................................................................................................................... 216

5.9.2

Features ........................................................................................................................ 216

5.9.3

SPI0 Block Diagram ...................................................................................................... 216

5.9.4

SPI0 Function Descriptions ........................................................................................... 217

5.9.5

SPI Timing Diagram ...................................................................................................... 227

5.9.6

SPI Configuration Examples ......................................................................................... 230

5.9.7

Register Map ................................................................................................................. 232

5.9.8


5.10

Serial 1 Peripheral Interface (SPI1) Controller ......................................................... 248

5.10.1

Overview ..................................................................................................................... 248

5.10.2

Features ...................................................................................................................... 248

5.10.3

SPI1 Block Diagram .................................................................................................... 248

5.10.4

SPI1 Function Descriptions ......................................................................................... 249

5.10.5

SPI Timing Diagram .................................................................................................... 255

5.10.6

SPI Configuration Examples ....................................................................................... 258

5.10.7

Register Map ............................................................................................................... 260

5.10.8


5.11

Timer Controller ........................................................................................................ 272

5.11.1

General Timer Controller............................................................................................. 272

5.11.2

Features ...................................................................................................................... 272

5.11.3

Timer Controller Block Diagram .................................................................................. 272

5.11.4

Register Map ............................................................................................................... 273

5.11.5


5.12

Watchdog Timer ....................................................................................................... 279

5.12.1

Register Map ............................................................................................................... 281

5.12.2


5.13

UART Interface Controller ........................................................................................ 284

5.13.1

Overview ..................................................................................................................... 284

5.13.2

Features of UART controller ....................................................................................... 286

- 3 -


Revision 2.4


5.13.3

Block Diagram ............................................................................................................. 287

5.13.4

IrDA Mode ................................................................................................................... 289

5.13.5

LIN (Local Interconnection Network) mode ................................................................. 291

5.13.6

Register Map ............................................................................................................... 292

5.13.7


5.14

I2S Audio PCM Controller ........................................................................................ 312

5.14.1

Overview ..................................................................................................................... 312

5.14.2

Features ...................................................................................................................... 312

5.14.3

I2S Block Diagram ...................................................................................................... 313

5.14.4

I2S Operation .............................................................................................................. 314

5.14.5

FIFO operation ............................................................................................................ 315

5.14.6

Register Map ............................................................................................................... 316

5.14.7


5.15

PDMA Controller ...................................................................................................... 328

5.15.1

Overview ..................................................................................................................... 328

5.15.2

Features ...................................................................................................................... 328

5.15.3

Block Diagram ............................................................................................................. 328

5.15.4

Function Description ................................................................................................... 329

5.15.5

Register Map ............................................................................................................... 330

5.15.6


5.16

Volume Control ......................................................................................................... 350

5.16.1

Overview and feature .................................................................................................. 350

5.16.2

Volume Control Register Map ..................................................................................... 350

5.16.3

Volume Control register Description ........................................................................... 351

6 FLASH MEMORY CONTROLLER (FMC)........................................................................... 354

6.1

Overview ................................................................................................................... 354

6.2

Features ................................................................................................................... 354

6.3

Flash Memory Controller Block Diagram ................................................................. 355

6.4

Flash Memory Organization ..................................................................................... 356

6.5

Boot Selection .......................................................................................................... 356

6.6

Data Flash (DATAF) ................................................................................................. 357

6.7

User Configuration (CONFIG) .................................................................................. 358

6.8

In-System Programming (ISP) ................................................................................. 360

6.8.1

ISP Procedure ............................................................................................................... 360

6.9

Register Map ............................................................................................................ 363

6.10

Register Description ................................................................................................. 364

7 ANALOG SIGNAL PATH BLOCKS ..................................................................................... 371

7.1

Sigma- Delta Analog-to-Digital Converter (SDADC) ................................................ 371

7.1.1

Functional Description .................................................................................................. 371

7.1.2

Features ........................................................................................................................ 371

7.1.3

Block Diagram ............................................................................................................... 371

7.1.4

Operation ...................................................................................................................... 372

7.1.5

ADC Register Map ........................................................................................................ 377

7.1.6

ADC Register Description ............................................................................................. 378

7.2

Audio Class D Speaker Driver (DPWM) ................................................................... 387

- 4 -


Revision 2.4


7.2.1

Functional Description .................................................................................................. 388

7.2.2

Features ........................................................................................................................ 388

7.2.3

Block Diagram ............................................................................................................... 388

7.2.4

Operation ...................................................................................................................... 388

7.2.5

DPWM Register Map .................................................................................................... 391

7.2.6

DPWM Register Description ......................................................................................... 392

7.3

Analog Functional Blocks ......................................................................................... 398

7.3.1

Overview ....................................................................................................................... 398

7.3.2

Features ........................................................................................................................ 398

7.3.3

Register Map ................................................................................................................. 398

7.3.4

VMID Reference Voltage Generation ............................................................................ 399

7.3.5

LDO Power Domain Control.......................................................................................... 400

7.3.6

Microphone Bias ........................................................................................................... 402

7.3.7

Oscillator Frequency Measurement and Control ........................................................... 403

7.4

Automatic Level Control (ALC) ................................................................................. 409

7.4.1


7.4.2

Register Map ................................................................................................................. 413

7.4.3


7.5

Capacitive Sensing Scan (CSCAN) and Operational Amplifiers .............................. 420

7.5.1


7.5.2

Features ........................................................................................................................ 420

7.5.3

Operation ...................................................................................................................... 420

7.5.4

Operational Amplifier .................................................................................................... 420

7.5.5

Comparator ................................................................................................................... 423

7.5.6

Register Map ................................................................................................................. 423

7.5.7


7.6

Biquad Filter (BIQ) .................................................................................................... 432

7.6.1


7.6.2

Register Map ................................................................................................................. 433

7.6.3


7.7

Successive Approximation Analog-to-Digital Convertor (SARADC) ........................ 440

7.7.1


7.7.2

Block Diagram ............................................................................................................... 441

7.7.3

Function description ...................................................................................................... 441

7.7.4

Register Map ................................................................................................................. 447

7.7.5

Register description ...................................................................................................... 448

8 APPLICATION DIAGRAM ................................................................................................... 458

9 PACKAGE DIMENSIONS ................................................................................................... 459

9.1

64L LQFP (7x7x1.4mm footprint 2.0mm) ................................................................. 459

9.2

QFN 32L 4X4 mm2, Thickness: 0.8mm (Max), Pitch: 0.40mm ................................ 460

10 ORDERING INFORMATION ............................................................................................... 461

11 REVISION HISTORY .......................................................................................................... 462

IMPORTANT NOTICE ................................................................................................................. 463

- 5 -


Revision 2.4


Figure of Contents-

Figure 4-1 ISD91200 Block Diagram ............................................................................................. 20

Figure 5-1 Functional Block Diagram ............................................................................................. 21

Figure 5-2 ISD91200 Power Distribution Diagram ......................................................................... 24

Figure 5-3 Clock generator block diagram ................................................................................... 109

Figure 5-4 System Clock Block Diagram ..................................................................................... 110

Figure 5-5 SysTick Clock Control Block Diagram ........................................................................ 110

Figure 5-6 Output Mode: Push-Pull Output .................................................................................. 131

Figure 5-7 Open-Drain Output ..................................................................................................... 132

Figure 5-8 Quasi-bidirectional GPIO Mode .................................................................................. 132

Figure 5-9 I2C Bus Timing ........................................................................................................... 149

Figure 5-10 I2C Protocol .............................................................................................................. 150

Figure 5-11 Master Transmits Data to Slave ............................................................................... 150

Figure 5-12 Master Reads Data from Slave................................................................................. 150

Figure 5-13 START and STOP condition ..................................................................................... 151

Figure 5-14 Bit Transfer on the I2C bus ....................................................................................... 151

Figure 5-15 Acknowledge on the I2C bus .................................................................................... 152

Figure 5-16 Legend for the following four figures ........................................................................ 153

Figure 5-17 Master Transmitter Mode.......................................................................................... 154

Figure 5-18 Master Receiver Mode .............................................................................................. 155

Figure 5-19 Slave Transmitter Mode ............................................................................................ 156

Figure 5-20 Slave Receiver Mode ................................................................................................ 157

Figure 5-21 GC Mode................................................................................................................... 158

Figure 5-22 I2C Data Shift Direction ............................................................................................ 160

Figure 5-23 I2C Time-out Count Block Diagram .......................................................................... 161

Figure 5-24 PWM Generator Clock Source Control ..................................................................... 172

Figure 5-25 PWM Generator Architecture Diagram ..................................................................... 172

Figure 5-26 PWM Generation Timing .......................................................................................... 173

Figure 5-27 PWM-Timer Operation Timing .................................................................................. 173

Figure 5-28 PWM Double Buffering. ............................................................................................ 174

Figure 5-29 PWM Controller Duty Cycle Modulation (PERIOD = 150). ....................................... 174

Figure 5-30 Paired-PWM Output with Dead Zone Generation Operation ................................... 175

Figure 5-31 Capture Operation Timing ........................................................................................ 176

Figure 5-32 PWM-Timer Interrupt Architecture Diagram ............................................................. 177

Figure 5-33 RTC Block Diagram .................................................................................................. 199

Figure 5-34 SPI Block Diagram .................................................................................................... 216

Figure 5-35 SPI Master Mode Application Block Diagram ........................................................... 217

- 6 -


Revision 2.4


Figure 5-36 SPI Slave Mode Application Block Diagram ............................................................. 217

Figure 5-37 Word Sleep Suspend Mode ...................................................................................... 219

Figure 5-38 Byte Re-Ordering Transfer ....................................................................................... 219

Figure 5-39 Byte Order in Memory ............................................................................................... 220


Figure 5-41 2-Bit Mode System Architecture ............................................................................... 223

Figure 5-42 2-Bit Mode (Slave Mode) .......................................................................................... 223

Figure 5-43 Bit Sequence of Dual Output Mode .......................................................................... 224

Figure 5-44 Bit Sequence of Dual Input Mode ............................................................................. 224

Figure 5-45 Quad Mode System Architecture .............................................................................. 225

Figure 5-46 Bit Sequence of Quad Output Mode ......................................................................... 225

Figure 5-47 FIFO Mode Block Diagram ....................................................................................... 226

Figure 5-48 SPI Timing in Master Mode ...................................................................................... 228

Figure 5-49 SPI Timing in Master Mode (Alternate Phase of SPICLK) ...................................... 228

Figure 5-50 SPI Timing in Slave Mode ....................................................................................... 229

Figure 5-51 SPI Timing in Slave Mode (Alternate Phase of SPICLK) ........................................ 229

Figure 5-52 SPI Block Diagram .................................................................................................... 248

Figure 5-53 SPI Master Mode Application Block Diagram ........................................................... 249

Figure 5-54 SPI Slave Mode Application Block Diagram ............................................................. 250

Figure 5-55 Two Transactions in One Transfer (Burst Mode) ..................................................... 251

Figure 5-56 Word Sleep Suspend Mode ...................................................................................... 251

Figure 5-57 Byte Re-Ordering Transfer ....................................................................................... 252



Figure 5-60 Byte Suspend Mode ................................................................................................. 253

Figure 5-61 Two Bits Transfer Mode ............................................................................................ 254

Figure 5-62 Variable Serial Clock Frequency .............................................................................. 255

Figure 5-63 SPI Timing in Master Mode ...................................................................................... 255

Figure 5-64 SPI Timing in Master Mode (Alternate Phase of SPICLK) ...................................... 256

Figure 5-65 SPI Timing in Slave Mode ....................................................................................... 256

Figure 5-66 SPI Timing in Slave Mode (Alternate Phase of SPICLK) ........................................ 257

Figure 5-67 Timer Controller Block Diagram ............................................................................... 272

Figure 5-68 Clock Source of Timer Controller ............................................................................. 273

Figure 5-69 Watchdog Timer Clock Control ................................................................................. 279

Figure 5-70 Watchdog Timer Block Diagram ............................................................................... 280

Figure 5-71 UART Clock Control Diagram ................................................................................... 287

Figure 5-72 UART Block Diagram ................................................................................................ 287

Figure 5-73 Auto Flow Control Block Diagram ............................................................................. 288

- 7 -


Revision 2.4


Figure 5-74 IrDA Block Diagram .................................................................................................. 289

Figure 5-75 IrDA Tx/Rx Timing Diagram ...................................................................................... 290

Figure 5-76 Structure of LIN Frame ............................................................................................. 291

Figure 5-77 I2S Clock Control Diagram ....................................................................................... 313

Figure 5-78 I2S Controller Block Diagram ................................................................................... 313

Figure 5-79 I2S Bus Timing Diagram (Format =0) ....................................................................... 314

Figure 5-80 MSB Justified Timing Diagram (Format=1) .............................................................. 314

Figure 5-81 FIFO contents for various I2S modes ....................................................................... 315

Figure 5-82 PDMA Controller Block Diagram .............................................................................. 328

Figure 6-1 Flash Memory Control Block Diagram ........................................................................ 355

Figure 6-2 Flash Memory Organization........................................................................................ 356

Figure 6-3 Flash Memory Structure ............................................................................................. 357

Figure 6-4 ISP Operation Timing ................................................................................................. 360

Figure 6-5 Boot Sequence and ISP Procedure ............................................................................ 361

Figure 7-1 ADC Signal Path Block Diagram ................................................................................ 371

Figure 7-2 SDADC Controller Interrupt ........................................................................................ 376

Figure 7-3 DPWM Block Diagram ................................................................................................ 388

Figure 7-4 VMID Reference Generation ...................................................................................... 399

Figure 7-5 LDO Power Domain .................................................................................................... 400

Figure 7-6 Oscillator Frequency Measurement Block Diagram ................................................... 403

Figure 7-8: ALC Response Graph ............................................................................................... 409

Figure 7-9: ALC Normal Mode Operation ................................................................................... 410

Figure 7-10: ALC Hold Time ....................................................................................................... 410

Figure 7-11: ALC Limiter Mode Operations ................................................................................ 411

Figure 7-12: ALC Operation with Noise Gate disabled ............................................................... 412

Figure 7-13: ALC Operation with Noise Gate Enabled ............................................................... 412

Figure 7-14 Operational Amplifier 0 Switch Control ..................................................................... 421

Figure 7-15 Operational Amplifier 1 Switch Control ..................................................................... 422

Figure 7-16 Operational Amplifier bias Switch Control ................................................................ 422

Figure 7-17 Comparator Switch Control....................................................................................... 423

Figure 7-18 SARADC Block Diagram .......................................................................................... 441

Figure 7-19 SARADC Clock Generator........................................................................................ 442

Figure 7-20 Single Mode Conversion Timing Diagram ................................................................ 443

Figure 7-21 Single-Cycle Scan on Enabled Channels Timing Diagram ...................................... 444

Figure 7-22 Continuous Scan on Enabled Channels Timing Diagram ........................................ 445

Figure 7-23 A/D Conversion Result Monitor Logics Diagram ...................................................... 446

Figure 7-24 A/D Controller Interrupt ............................................................................................. 446

Figure 7-25 Conversion Result Mapping Diagram of Single-end Input ....................................... 449

- 8 -


Revision 2.4


1 GENERAL DESCRIPTION

The ISD91200 series is a system-on-chip product optimized for low power, audio record and playback with an embedded ARM® Cortex™-M0 32-bit microcontroller core.

The ISD91200 device embeds a Cortex™-M0 core running up to 50 MHz with 64K/128Kbyte of nonvolatile flash memory and 12K-byte of embedded SRAM. It also comes equipped with a variety of peripheral devices, such as Timers, Watchdog Timer (WDT), Real-time Clock (RTC), Peripheral Direct

Memory Access (PDMA), a variety of serial interfaces (UART, SPI/SSP, I

2

C, I

2

S), PWM modulators,

GPIO, LDO, SDADC, SARADC, DPWM, Low Voltage Detector and Brown-out detector.

The ISD91200 comes equipped with a rich set of power saving modes including a Deep Power Down

(DPD) mode drawing less than 1

µ

A. A micro-power 10KHz oscillator can periodically wake up the device from deep power down to check for other events. A Standby Power Down (SPD) mode can maintain a real time clock function at less than 5

µ

A.

For audio functionality the ISD91200 includes a Sigma-Delta ADC with 91dB SNR performance coupled with a Programmable Gain Amplifier (PGA with 0-6/12dB gain) and volume control (36dB to -

108dB) in digital domain to enable direct connection of a microphone. Audio output is provided by a

Differential Class D amplifier (DPWM) that can deliver 0.5W of power to an 8

Ω speaker.

The ISD91200 provides 16 analog enabled general purpose IO pins (GPIO). These pins can be configured to connect to an analog comparator, can be configured as analog current sources or can be routed to the SDADC for analog conversion. They can also be used as a relaxation oscillator to perform capacitive touch sensing.

- 9 -


Revision 2.4


2 FEATURES

•

Core

– ARM® Cortex™-M0 core running up to 50 MHz for normal speed.

– One 24-bit System tick timer for operating system support.

– Supports a variety of low power sleep and power down modes.

– Single-cycle 32-bit hardware multiplier.

– NVIC (Nested Vector Interrupt Controller) for 32 interrupt inputs, each with 4-levels of priority.

– Serial Wire Debug (SWD) supports with 2 watchpoints/4 breakpoints.

•

Power Management

– Wide operating voltage range from 1.8V to 5.5V.

– Power management Unit (PMU) providing four levels of power controls.

– Deep Power Down (DPD) mode with sub micro-amp leakage (<2µA).

– Wakeup from Deep Power Down via dedicated WAKEUP pin or timed operation from internal low power 10KHz oscillator.

– Standby current in SPD mode with limited RAM (256byte SBRAM) retention and RTC operation <5µA.

– Standby current in STOP mode with full SRAM retention <10 µA.

– Wakeup from Standby can be from any GPIO interrupt, RTC or BOD.

– Sleep mode with minimal dynamic power consumption.

– 3V LDO for operation of external 3V devices such as serial flash.

•

Flash EPROM Memory

– 64K/128K bytes Flash EPROM for program code and data storage.

– Mini-cache to maintain near zero-wait state memory access.

– Support In-system program (ISP) and In-circuit program (ICP) application code update

– 512 byte page erase for flash.

– Configurable boundary to delineate code and data flash.

– Support 2 wire In-circuit Programming (ICP) update from SWD ICE interface

•

SRAM Memory

– 12K bytes embedded SRAM.

•

Clock Control

– High speed and low speed oscillators providing flexible selection for different applications. No external components necessary.

– Built-in trimmable oscillator with range of 16-50MHz. Factory trimmed HIRC within 1% to settings of 49.152MHz and 32.768MHz. User trimmable with in-built frequency measurement block (OSCFM) using reference clock of 32kHz crystal or external reference source.

– Ultra-low power (<1uA) 10KHz oscillator for watchdog and wakeup from power-down or sleep operation.

– External 32kHz crystal input for RTC function and low power system operation.

– External 12 MHz crystal input for precise timing operation.

•

GPIO

– Four I/O modes:



Quasi bi-direction





Push-Pull output

Open-Drain output

 Input only with high impendence

– Schmitt trigger input selectable.

– I/O pin can be configured as interrupt source with edge/level setting.

– Supports Driver and Sink IO mode.

– Capacitive Touch: 16

– Maximal 32 GPIO

- 10 -


Revision 2.4


•

Audio Analog to Digital converter

– Sigma Delta ADC with configurable decimation filter and 16 bit output.

– 90dB Signal-to-Noise (SNR) performance.

– Programmable gain amplifier with 32 steps from -12 to 35.25dB in 0.75dB steps.

– Boost gain stage of 26dB, giving maximum total gain of 61dB.

– Input selectable from dedicated MIC pins or analog enabled GPIO.

– Programmable biquad filter to support multiple sample rates from 8-32kHz.

– DMA support for minimal CPU intervention.

•

Differential Audio PWM Output (DPWM)

– Direct connection of speaker

– 0.5W drive capability into 8

Ω load.

– Configurable up-sampling to support sample rates from 8-48kHz.

– Programmable volume control from -108dB to +36dB in 0.5 dB step

– Programmable biquad filter to support multiple sample rates from 8-48kHz

– DMA support for minimal CPU intervention.

•

Timers

– Two timers with 8-bit pre-scaler and 24-bit resolution.

– Counter auto reload.

•

Watch Dog Timer

– Default ON/OFF by configuration setting

– Multiple clock sources

– 8 selectable time out period from micro seconds to seconds (depending on clock source)

– WDT can wake up power down/sleep.

– Interrupt or reset selectable on watchdog time-out.

•

RTC

– Real Time Clock counter (second, minute, hour) and calendar counter (day, month, year)

– Alarm registers (second, minute, hour, day, month, year)

– Selectable 12-hour or 24-hour mode

– Automatic leap year recognition

– Time tick and alarm interrupts.

– Device wake up function.

– Supports software compensation of crystal frequency by compensation register (FCR)

•

PWM/Capture

– Four 16-bit PWM generators provide four single ended PWM outputs or two complementary paired PWM outputs.

– The PWM generator equipped with a clock source selector, a clock divider, an 8-bit pre-scaler and Dead-Zone generator for complementary paired PWM.

– PWM interrupt synchronous to PWM period.

– 16-bit digital Capture timers (shared with PWM timers) provide rising/falling capture inputs.

– Support Capture interrupt

•

UART

– Up to two uart controller

– UART ports with flow control (TX, RX, CTS and RTS)

– 8-byte FIFO.

– Support IrDA (SIR) and LIN function

– Programmable baud-rate generator up to 1/16 of system clock.

•

SPI

– Up to two SPI controller

– SPI Clock up to 25 MHz.

– SPI data rate in Quad mode up to 100 Mbps

– Support MICROWIRE/SPI master/slave mode (SSP)

- 11 -


Revision 2.4


– Full duplex synchronous serial data transfer

– Variable length of transfer data from 1 to 4 bytes

– MSB or LSB first data transfer

– 2 slave/device select lines when used in master mode.

– DMA support.( 64bit (16x4) data FIFO)

– Quad/Dual SPI support.

•

I2C

– Master/Slave up to 1Mbit/s

– Bidirectional data transfer between masters and slaves

– Multi-master bus (no central master).

– Arbitration between simultaneously transmitting masters without corruption of serial data on the bus

– Serial clock synchronization allows devices with different bit rates to communicate via one serial bus.

– Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer.

– Programmable clock allowing versatile rate control.

– Supports multiple address recognition (four slave address with mask option)

– Supports wake-up by address recognition (for 1st slave address only)

•

I

2

S

– Interface with external audio CODEC.

– Operate as either master or slave.

– Capable of handling 8, 16, 24 and 32 bit word sizes

– Mono and stereo audio data supported

– I

2

S and MSB justified data format supported

– Two 8 word FIFO data buffers are provided, one for transmit and one for receive

– Generates interrupt requests when buffer levels cross a programmable boundary

– Supports DMA requests, for transmit and receive

•

SARADC

– 12-bit SAR ADC with 700K SPS

– Up to 12-ch single-end input

– Single scan/single cycle scan/continuous scan

– Each channel with individual result register

– Scan on enabled channels

– Threshold voltage detection

– Conversion start by software programming or external input

– Supports PDMA mode

•

Low Voltage Reset

– Threshold voltage typical level: 1.6V

•

Brown-out detector

– Supports 16-level brown-out setting.

– Supports time-multiplex operation to minimize power consumption.

– Supports Brownout Interrupt and Reset option

•

Built in Low Dropout Voltage Regulator (LDO)

– Capable of delivering 30mA load current.

– Configurable 8 output voltage selections from 1.5V – 3.3V.

– LDO output powers IO ring for GPIOA<7:0> and can supply power to external SPI Flash.

– Can be bypassed and voltage domain supplied directly from system power.

•

Additional Features

- 12 -


Revision 2.4


– Digital Microphone interface.

•

Standby current in STOP mode with SRAM retention <=10µA at 25°C.

•

Operating Temperature: -40C~85C

•

Package:

– All Green package (RoHS)



LQFP 64-pin

- 13 -


Revision 2.4


3 PART INFORMATION AND PIN CONFIGURATION

3.1 Pin Configuration

NC

NC

NC

VCCA

VCCLDO

VLDOx

GPIOA<0>

GPIOA<1>

GPIOA<2>

GPIOA<3>

GPIOA<4>

GPIOA<5>

GPIOA<6>

GPIOA<7>

VSS

NC

7

8

5

6

3

4

1

2

9

10

11

12

13

14

15

16

I 91200

39

38

37

36

35

34

33

48

47

46

45

44

43

42

41

40

GPIOB<6>

GPIOB<5>

GPIOB<4>

GPIOB<3>

GPIOB<2>

GPIOB<1>

GPIOB<0>

VCC

NC

VDDL/ VREG

GPIOA<11>

GPIOA<10>

RESETB

ICE_ CLK

ICE_ DAT

NC

Fig 3-1 ISD912XX LQFP 64 pin

- 14 -


Revision 2.4


3.2 Pin Description

The ISD91200 is a low pin count device where many pins are configurable to alternative functions. All

General Purpose Input/Output (GPIO) pins can be configured to alternate functions as described in the table below.

Pin No.

LQFP

64

Pin Name Pin Type Alt CFG Description

1 NC

2 NC

3 NC

4 VCCA

5 VCCLDO

6 VLDOx

7

8

9

10

11

12

13

PA.0

SPI0_MISO1

SPI0_SSB1

I2S0_FS

PA.1

SPI0_MOSI0

I2S0_BCLK

PA.2

SPI0_SCLK0

DMIC_DAT

I2S0_SDI

PA.3

SPI0_SSB0

SARADC_TRIG

I2S0_SDO

PA.4

SPI0_MISO0

UART0_TX

SPI1_MOSI

PA.5

SPI0_MOSI1

UART0_RX

SP1_SCLK

PA.6

UART0_TX

I2C0_SDA

I

O

I/O

O

O

I/O

I/O

I

I

I/O

O

I/O

O

O

I/O

I/O

O

I/O

O

I/O

O

I

I/O

I/O

O

I/O

P

P

P

Analog power supply.

Power supply for LDO, should be connected to VCCD.

LDO regulator output. if used, a 1μF decoupling capacitor must be placed. If not used then tie to VCCD.

0 General purpose input/output pin; Port A, bit 0

1 2 nd

Master In, Slave Out for SPI0 interface

2 Slave Select Bar 1 for SPI0 interface

3 Frame Sync Clock for I2S interface


1 1 st

Master Out, Slave In for SPI0 interface

3 Bit Clock for I2S interface


1 Serial Clock for SPI 0interface

2 DMIC data

3 Serial Data Input for I2S interface



2 SARADC Trigger

3 Serial Data Output for I2S interface


1 Master In, Slave Out channel 0 for SPI interface

2 Transmit channel of UART 0

3 Master Out, Slave In for SPI1 interface


1 2 nd


2 Receive channel of UART 0

3 Serial Clock for SPI1 interface



2 Serial Data, I2C interface

- 15 -


Revision 2.4


Pin No.

LQFP

64

Pin Name

14

15

SPI1_SSB

PA.7

UART0_RX

I2C0_SCL

SPI1_MISO

VSSD

16 NC

17

NC

18

NC

19

VCCSPK

20 SPKP

21

VSSSPK

22

VSSSPK

23

SPKN

24 VCCSPK

25

26

27

28

29

30

NC

PA.8

I2C0_SDA

UART1_TX

UART0_RTS

PA.9

I2C0_SCL

UART1_RX

UART0_CTS

I2C0_SCL

PA.12

PWM0CH2

XI12M

PA.13

PWM0CH3

XO12M

I2C0_SCL

PA.14

UART1_TX

DMIC_CLK

XI32K

Pin Type Alt CFG Description

P

O

P

O

I/O

I

I/O

I

P

P

O

P

I/O

I/O

I

I

I/O

I/O

O

O

I/O

I/O

O

I

I/O

O

O

I/O

I/O

O

IO

I

3 Slave Select Bar for SPI1 interface



2 Serial Clock, I2C interface

3 Master In, Slave Out for SPI1 interface

Digital Ground.

Power Supply for PWM Speaker Driver

Positive Speaker Driver Output

Ground for PWM Speaker Driver

Ground for PWM Speaker Driver

Positive Speaker Driver Output

Power Supply for PWM Speaker Driver




3 UART 0 Request to Send Output.




3 UART 0 Clear to Send Input.



1 PWM0CH2 Output.

2 12MHz Crystal Oscillator Input. Max Voltage 1.8V


1 PWM0CH3 Output.

2 12MHz Crystal Oscillator Output




2 DMIC clock

3 32.768kHz Crystal Oscillator Input. Max Voltage 1.8V

- 16 -


Revision 2.4


Pin No.

LQFP

64

Pin Name

31

PA.15

UART1_RX

MCLK

XO32K

32 NC

33

NC

34

ICE_DAT

35 ICE_CLK

36

37

38

39

RESETN

PA.10

PWM0CH0

TM0

DPWM_P

PA.11

PWM0CH1

TM1

DPWM_N

VREG

40

NC

41 VCCD

42

43

44

45

PB.0

SPI1_MOSI

CS0

A0P

PB.1

SP1_SCLK

CS1

A0N

PB.2

SPI1_SSB

CS2

A0E

SAR11

PB.3

SPI1_MISO

CS3


I

I/O

O

I

O

I/O

O

I

O

P

P

I/O

I

O

O

I/O

O

I/O

O

AI

AI

I/O

AI

AO

AI

I/O

I

AI

I/O

AI

AI

I/O

O



2 Master clock output for synchronizing external device

3 32.768kHz Crystal Oscillator Output

Serial Wire Debug port clock pin. Has internal weak pull-up.

Serial Wire Debug port data pin. Has internal weak pull-up.

External reset input. Pull this pin low to reset device to initial state. Has internal weak pull-up.


1 PWM0CH0 Output.

2 External input to Timer 0

3 Audio PWM positive


1 PWM0CH1 Output.

2 External input to Timer 1

3 Audio PWM negative

L ogic regulator output decoupling pin. A 1μF capacitor returning to

VSSD must be placed on this pin.

0

Main Digital Supply for Chip. Supplies all IO except analog, Speaker

Driver

General purpose input/output pin, analog capable; Port B, bit 0.

Triggers external interrupt 0 (EINT0/IRQ2)


Touch scan channel 0

Operational Amplifier 0 positive input

0

General purpose input/output pin, analog capable; Port B, bit 1.

Triggers external interrupt 1 (EINT1/IRQ3)



Operational Amplifier 0 negative input

0 General purpose input/output pin, analog capable; Port B, bit 2

1 Slave Select Bar for SPI1 interface


Operational Amplifier 0 output

SARADC channel 11




- 17 -


Revision 2.4


Pin No.

LQFP

64

Pin Name

46

47

48

49

50

PB.7

I2S0_SDO

CS7

C1N

SAR9

PB.8

I2C0_SDA

I2S0_FS

UART1_RTS

CS8

C2P

SAR0

PB.9

I2C0_SCL

I2S0_BCLK

51

UART1_CTS

CS9

SAR1

PB.10

CMP1

52

I2S0_SDI

UART1_TX

CS10

SAR2

53 PB.11

A1P

PB.4

I2S0_FS

CS4

A1N

PB.5

I2S0_BCLK

CS5

A1E

SAR10

PB.6

I2S0_SDI

CS6

CNP

SAR8


AI

AI

I/O

I/O

I/O

I

AI

AI

I/O

O

I

O

AI

AI

I/O

AI

I/O

O

AI

AI

AI

I/O

I/O

I/O

O

AI

I/O

I/O

AI

AO

AI

I/O

I

AI

AI

AI

I/O

I/O

AI

AO

Operational Amplifier 1 positive input




Operational Amplifier 1 negative input




Operational Amplifier 1 output

SARADC channel 10




Comparator 1 positive input and comparator 2 negtive input

SARADC channel 8




Comparator 1 negtive input

SARADC channel 9

0 General purpose input/output pin, analog capable; Port B, bit 8.



3 UART 1 Request to Send Output.


Comparator 2 positive input

SARADC channel 0

0 General purpose input/output pin, analog capable; Port B, bit 9.



3 UART 1 Clear to Send Input.


SARADC channel 1


1 Compare 1 Output




SARADC channel 2


- 18 -


Revision 2.4


Pin No.

LQFP

64

Pin Name Pin Type Alt CFG Description

54

55

56

57

58

CS13

SAR5

PB.14

SPI0_SCLK0

SPI1_SSB

DMIC_CLK

CS14

SAR6

PB.15

SPI0_SSB0

SPI1_MISO

MCLK

CS15

CMP2

I2S0_SDO

UART1_RX

CS11

SAR3

PB.12

SPI0_MISO0

SPI1_MOSI

DMIC_DAT

CS12

SAR4

PB.13

SPI0_MOSI0

SPI1_SCLK

SARADC_TRIG

SAR7

VSSA

I/O

I/O

I/O

I

AI

AI

I/O

I/O

I/O

O

O

I

AI

AI

I

AI

AI

I/O

I/O

O

O

AI

AI

I/O

O

I/O

O

AI

AI

AP

1 Compare 2 Output




SARADC channel 3


1 1 st

Master In, Slave Out for SPI0 interface


3 DMIC data


SARADC channel 4


1 1 st



3 SARADC Trigger


SARADC channel 5


1 1 st

Serial Clock for SPI0 interface


3 DMIC clock


SARADC channel 6




3 Master clock output for synchronizing external device


SARADC channel 7

Ground for analog circuitry.

59 VMID O Mid rail reference. Connect 4.7µF to VSSA.

60 MICP

61 VSS_SARADC

62

MICN

AI

AP

AI

SDADC positive input

SARADC ground

SDADC negative input

63

NC

64

MICBIAS O Microphone bias output.

Note:

1.

Pin Type I=Digital Input, O=Digital Output; AI=Analog Input; AO=Analog Output; P=Power Pin; AP=Analog Power

- 19 -


Revision 2.4

4 BLOCK DIAGRAM


Figure 4-1 ISD91200 Block Diagram

- 20 -


Revision 2.4


5 FUNCTIONAL DESCRIPTION

5.1 ARM

®

Cortex™-M0 core

The Cortex™-M0 processor is a multistage, 32-bit RISC processor. It has an AMBA AHB-Lite interface and includes an NVIC component. It also has hardware debug functionality. The processor can execute Thumb code and is compatible with other Cortex-M profile processor.

Figure 5-1 shows the functional blocks of processor.

Interrupts

Cortex-M0 components

Cortex-M0 processor

Nested

Vectored

Interrupt

Controller

(NVIC)

Wakeup

Interrupt

Controller

(WIC)

Cortex-M0

Processor core

Bus matrix

Debug

Breakpoint and

Watchpoint unit

Debugger interface

Debug

Access Port

(DAP)

AHB-Lite interface Serial Wire debug port

Figure 5-1 Functional Block Diagram

The implemented device provides:

•

A low gate count processor that features:

– The ARMv6-M Thumb® instruction set.

– Thumb-2 technology.

– ARMv6-M compliant 24-bit SysTick timer.

– A 32-bit hardware multiplier.

– The system interface supports little-endian data accesses.

– The ability to have deterministic, fixed-latency, interrupt handling.

– Load/store-multiples that can be abandoned and restarted to facilitate rapid interrupt handling.

– C Application Binary Interface compliant exception model.

This is the ARMv6-M, C Application Binary Interface (C-ABI) compliant exception model that enables the use of pure C functions as interrupt handlers.

– Low power sleep-mode entry using Wait For Interrupt (WFI), Wait For Event (WFE) instructions, or the return from interrupt sleep-on-exit feature.

•

NVIC that features:

– 32 external interrupt inputs, each with four levels of priority.

– Dedicated non-Maskable Interrupt (NMI) input.

– Support for both level-sensitive and pulse-sensitive interrupt lines

– Wake-up Interrupt Controller (WIC), providing ultra-low power sleep mode support.

•

Debug support

– Four hardware breakpoints.

- 21 -


Revision 2.4


– Two watchpoints.

– Program Counter Sampling Register (PCSR) for non-intrusive code profiling.

– Single step and vector catch capabilities.

•

Bus interfaces:

– Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration to all system peripherals and memory.

– Single 32-bit slave port that supports the DAP (Debug Access Port).

- 22 -


Revision 2.4


5.2 System Manager

5.2.1 Overview

The following functions are included in system manager section

 System Memory Map

 System Timer (SysTick)

 Nested Vectored Interrupt Controller (NVIC)

 System management registers for product ID

 System management registers for chip and module functional reset and multi-function pin control

 Brown-Out and chip miscellaneous Control Register

 Combined peripheral interrupt source identify

5.2.2 System Reset

The system reset includes one of the list below event occurs. For these reset event flags can be read by SYS_RSTSTS register.

 The Power-On Reset

 The low level on the RESETN pin

 Watchdog Time Out Reset

 Low Voltage Reset

 Cortex-M0 MCU Reset

 PMU Reset – for details of wakeup events, also examine CLK_PWRCTL register.

 SWD Debug interface.

A power-on reset (POR) will occur if the main external supply rail ramps from 0V or the voltage of the main supply drops below reset threshold. A low voltage reset monitors the regulated core logic (1.5V) supply and will assert if the voltage on this rail drops below reliable logic threshold.

- 23 -


Revision 2.4


5.2.3 System Power Distribution

The ISD91200 implements several power domains:

 Analog power from VCCA and VSSA provides the power for analog module operation.

 Digital power from VCCD and VSSD supplies the power to the IO ring and the internal regulator which provides 1.5V power for digital operation.

 VCCLDO supplies the LDO regulator whose output is available on pin VLDOx. This supply powers the IO ring for GPIOA<7:0>.

 An internal Standby reference (SB REG) generates a 1.5V rail to part of the logic including the IO ring, Standby RAM and RTC during standby mode for low power operation.

The outputs of internal voltage regulators; VREG and VDDB, require external decoupling capacitors which should be located close to the corresponding pin. The following diagram shows the power distribution of this device.

VCCA

VSSA

XO32K

XI32K

SD ADC

Speaker

Driver

IO Cell

SAR ADC

Analog Comparator

N573FXX

Power Distribution

RAM

OPA

Brownout

Detector

FLASH

RTC

32 K

OSC

SB

RAM

Digital

Logic

1.5 V Standby Supply

SB

REG

10 KHz

Osc.

POR15

POR50

BUFFER

3.3V

5 V to 3.3 V

LDO

50 MHz

Osc.

1.5V Main Supply

1.5V

LDO

CSCAN IO cell

GPIOA<7:0>

VDDB

1uF

VDDBS

VREG

4.7uF

GPIOA<15:8>

GPIOB<15:0>

Note: GPIOA11 is

DPD wakeup pin

Active in Standby Power Down Mode

Active in Deep and Standby Power Down Mode

Figure 5-2 ISD91200 Power Distribution Diagram

- 24 -


Revision 2.4


5.2.4 System Memory Map

The ISD91200 provides 4G-byte address space. The memory locations assigned to each on-chip

module is shown in Table 5-1. The detailed register definition, memory space, and programming

detailed will be described in the following sections for each on-chip module. The ISD91200 supports little-endian data format.

Table 5-1 Address Space Assignments for On-Chip Modules

Modules Reference Address Space

Flash & SRAM Memory Space

0x0000_0000 – 0x0002_33FF

0x2000_0000 – 0x2000_2FFF

Token

FLASH_BA

SRAM_BA

AHB Modules Space (0x5000_0000 – 0x501F_FFFF)

0x5000_0000 – 0x5000_01FF

0x5000_0200 – 0x5000_02FF

SYS_BA

CLK_BA

0x5000_0300 – 0x5000_03FF

0x5000_0400 – 0x5000_04FF

0x5000_4000 – 0x5000_7FFF

0x5000_8000 – 0x5000_BFFF

0x5000_C000 – 0x5000_FFFF

INT_BA

Reserved

GPIO_BA

PDMA_BA

FMC_BA

APB1 Modules Space (0x4000_0000 ~ 0x400F_FFFF)

0x4000_4000 – 0x4000_7FFF

0x4000_8000 – 0x4000_BFFF

WDT_BA

RTC_BA

0x4001_0000 – 0x4001_3FFF

0x4002_0000 – 0x4002_3FFF

0x4003_0000 – 0x4003_3FFF

0x4003_8000 – 0x4003_FFFF

TIMER0_BA

I2C_BA

SPI0_BA

SPI1_BA

0x4004_0000 – 0x4004_3FFF

0x4005_0000 – 0x4005_3FFF

0x4005_8000 – 0x4005_FFF

0x4006_0000 – 0x4006_3FFF

PWM_BA

UART0_BA

UART1_BA

SARADC_BA

0x4007_0000 – 0x4007_3FFF

0x4008_0000 – 0x4008_3FFF

0x4008_4000 – 0x4008_7FFF

0x400A_0000 - 0x400A_FFFF

0x400B_0000 - 0x400B_009F

0x400B_0090 – 0x400B_009F

DPWM_BA

ANA_BA

BOD_BA

I2S_BA

BIQ_BA

ALC_BA

FLASH Memory Space (141KB)

SRAM Memory Space (12KB)

System Global Control Registers

Clock Control Registers

Interrupt Multiplexer Control Registers

GPIO Control Registers

SRAM_APB DMA Control Registers

Flash Memory Control Registers

Watch-Dog Timer Control Registers

Real Time Clock (RTC) Control Register

Timer0/Timer1 Control Registers

I2C Interface Control Registers

SPI0 Serial Interface Control Registers

SPI1 Serial Interface Control Registers

PWM0/1 Control Registers

UART0 Control Registers

UART1 Control Registers

SARADC Controller Registers

Differential Audio PWM Speaker Driver

Analog Block Control Registers

Brown Out Detector Control Registers

I2S Interface Control registers

Biquad Filter Control Registers

Analog Block Control Registers

5.2.5

5.3.5

5.2.7.5

5.4.3

5.15.5

6.9

7.2.5

7.3.3

5.5.1

5.14.6

7.6.2.1

7.4.2

5.12.1

5.8.4

5.11.4

5.6.5

5.9.7

5.10.7

5.7.13

5.13.6

5.13.6

7.7.4

- 25 -


Revision 2.4


0x400B_00A0 - 0x400B_00AF

0x400D_0000 – 0x400D_3FFF

0x400E_0000 – 0x400E_FFFF

0x400F_0000 – 0x400F_7FFF

VOLCTRL_BA

CSCAN_BA

SDADC_BA

SBRAM_BA

System Control Space (0xE000_E000 ~ 0xE000_EFFF)

0xE000_E010 – 0xE000_E0FF SYSTICK_BA

0xE000_E100 – 0xE000_ECFF

0xE000_ED00 – 0xE000_ED8F

SCS_BA

SYSINFO_BA

Volume Control Registers

CAP SENSE Control Registers

Analog-Digital-Converter (ADC) Registers

Standby RAM Block Address space

5.16.2

7.5.6

7.1.5

System Timer Control Registers

5.2.6.1

External Interrupt Controller Control Registers

5.2.7.4

System Control Registers

5.2.8

- 26 -


Revision 2.4


5.2.5 System Manager Control Registers

R/W Description Register Offset

SYS Base Address:

SYS_BA = 0x5000_0000

SYS_PDID SYS_BA+0x00

SYS_RSTSTS SYS_BA+0x04

SYS_BA+0x08 SYS_IPRST0

SYS_IPRST1 SYS_BA+0x0C

SYS_GPSMTEN

SYS_GPA_MFP

SYS_BA+0x30

SYS_BA+0x38

R

R/W

R/W

R/W

R/W

R/W

Product ID

System Reset Source Register

IP Reset Control Resister0

IP Reset Control Resister1

Reset Value

0xXXXX_XXXX

0x0000_0XXX

0x0000_0000

0x0000_0000

GPIOA/B input type control register 0xFFFF_0000

GPIOA multiple alternate functions control register 0x0000_0000

SYS_GPB_MFP

SYS_WKCTL

SYS_REGLCTL

SYS_BA+0x3C

SYS_BA+0x54

R/W

R/W

GPIOB multiple alternate functions control register 0x0000_0000

WAKEUP pin control register 0x0000_0006

SYS_BA+0x100 R/W Register Lock Control 0x0000_0000

SYS_IRCTCTL SYS_BA+0x110 R/W Oscillator Frequency Adjustment control register

10kHz Oscillator (LIRC) Trim Register

0xXXXX_XXXX

0xXXXX_XXXX SYS_OSC10KTRIM SYS_BA+0x114 R/W

SYS_OSCTRIM0 SYS_BA+0x118 R/W Internal oscillator trim register 0

0xXXXX_XXXX

SYS_OSCTRIM1 SYS_BA+0x11C R/W Internal oscillator trim register 1 0xXXXX_XXXX

SYS_OSCTRIM2 SYS_BA+0x120 R/W Internal oscillator trim register 2

0xXXXX_XXXX

SYS_XTALTRIM SYS_BA+0x124 R/W External Crystal oscillator trim register

0xXXXX_XXXX

Reserved SYS_BA+0x128 R/W System reserved, keep POR value

0xXXXX_XXXX

Note: In BSP register structure, the prefix is structure name, and register be no prefix, for example

SYS_ is the prefix, SYS_XTALTRIM will be SYS->XTALTRIM

- 27 -


Revision 2.4


Product Identifier Register (SYS_PDID)

This register provides specific read-only information for software to identify this chip.

Register Offset R/W Description

SYS_PDID

31

SYS_BA+0x00 R

30 29

Product ID

26 25

23

15

7

22

14

6

21

13

5

28

PDID[31:24]

27

20 19

12

PDID[23:16]

11

PDID[15:8]

4 3

PDID[7:0]

18

10

2

17

9

1

Reset Value

0xXXXX_XXXX

24

16

8

0

Table 5-2 System Product Identifier Register (SYS_PDID, address 0x5000_0000) Bit Description.

Bits Description

PDID

Product Identifier

Chip identifier for ISD91200 series.

[31:0]

- 28 -


Revision 2.4


System Reset Source Register (SYS_RSTSTS)

This register provides specific information for software to identify this chip’s reset source from last operation.


SYS_BA+0x04 R/W System Reset Source Register

Reset Value

0x0000_0XXX SYS_RSTSTS

31 30 29 28 27 26 25 24

Reserved

23 22 21 20 19 18 17 16

Reserved

15

7

CPURF

14

6

PMURSTF

13

Reserved

5

SYSRF

12

4

Reserved

11

3

LVRF

10

PORF

2

WDTRF

9

DPDRSTF

1

PADRF

8

WKRSTF

0

CORERSTF

Table 5-3 System Reset Source Register (SYS_RSTSTS, address 0x5000_0004) Bit Description.

Bits

[31:11]

Description

Reserved

[10]

[9]

[8]

PORF

DPDRSTF

WKRSTF

Reserved.

Power on Reset Flag

The PORF flag is set by hardware if device has powered up from a power on reset condition or standby power down.

0=No detected.

1= A power on Reset has occurred.

This bit is cleared by writing 1 to itself. Writing 1 to this bit will clear bits PORF,

DPDRSTF, and WKRSTF

Deep Power Down Reset Flag

The DPDRSTF flag is set by hardware if device has powered up due to the DPD timer function.

0=No detected.

1= A power on was triggered by DPD timer.


DPDRSTF, and WKRSTF

Wakeup Pin Reset Flag

The WKRSTF flag is set by hardware if device has powered up from deep power down (DPD) due to action of the WAKEUP pin.

0=No detected.

1= A power on was triggered by WAKEUP pin.


DPDRSTF, and WKRSTF

- 29 -


Revision 2.4

[0]

[5]

[4]

[3]

[7]

[6]

[2]

[1]

CPURF

PMURSTF

SYSRF

Reserved

LVRF

WDTRF

PADRF

CORERSTF


Reset Source From CPU

The CPURF flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) with a “1” to reset Cortex-M0 CPU kernel and Flash memory controller (FMC).

0= No reset from CPU.

1= The Cortex-M0 CPU kernel and FMC has been reset by software setting

CPURST to 1.

This bit is cleared by writing 1 to itself.

Reset Source From PMU

The PMURSTF flag is set if the PMU.

0= No reset from PMU.

1= PMU reset the system from a power down/standby event.


Reset Source From MCU

The SYSRF flag is set if the previous reset source originates from the Cortex_M0 kernel.

0= No reset from MCU.

1= The Cortex_M0 MCU issued a reset signal to reset the system by software writing

1 to bit SYSRESTREQ(SYSINFO_AIRCTL[2], Application Interrupt and Reset

Control Register) in system control registers of Cortex_M0 kernel.


Reserved.

Low Voltage Reset Flag

The LVRF flag is set if pervious reset source originates from the LVR module.

0 = No reset from LVR

1 = The LVR module issued the reset signal to reset the system.


Reset Source From WDT

The WDTRF flag is set if pervious reset source originates from the Watch-Dog module.

0 = No reset from Watch-Dog.

1 = The Watch-Dog module issued the reset signal to reset the system.


The RSTS_PAD Flag Is If Pervious Reset Source Originates From the /RESET

Pin

0 = No reset from Pin /RESET.

1 = Pin /RESET had issued the reset signal to reset the system.


Reset Source From CORE

The CORERSTF flag is set if the core has been reset. Possible sources of reset are a Power-On Reset (POR), RESETn Pin Reset or PMU reset.

0 = No reset from CORE.

1 = Core was reset by hardware block.


- 30 -


Revision 2.4


IP Reset Control Register1(SYS_IPRST0)


SYS_IPRST0 SYS_BA+0x08 R/W IP Reset Control Resister0

Reset Value

0x0000_0000

7 6 5

Reserved

4 3 2

PDMARST

1

CPURST

0

CHIPRST

Bits

[31:3]

[2]

[1]

[0]

Table 5-4 IP Reset Control Register 1 (SYS_IPRST0 address 0x5000_0008) Bit Description.

Description

Reserved

PDMARST

CPURST

CHIPRST

Reserved.

PDMA Controller Reset

Set “1” will generate a reset signal to the PDMA Block. User needs to set this bit to

“0” to release from the reset state

0= Normal operation.

1= PDMA IP reset.

CPU Kernel One Shot Reset

Setting this bit will reset the CPU kernel and Flash Memory Controller(FMC), this bit will automatically return to “0” after the 2 clock cycles

This bit is a protected bit, to program first issue the unlock sequence

0= Normal.

1= Reset CPU.

CHIP One Shot Reset

Set this bit will reset the whole chip, this bit will automatically return to “0” after the 2 clock cycles.

CHIPRST has same behavior as POR reset, all the chip modules are reset and the chip configuration settings from flash are reloaded.

This bit is a protected bit, to program first issue the unlock sequence

0= Normal.

1= Reset CHIP.

- 31 -


Revision 2.4


IP Reset Control Register1 (SYS_IPRST1)

Setting these bits “1” will generate an asynchronous reset signal to the corresponding peripheral block.

The user needs to set bit to “0” to release block from the reset state.


SYS_BA+0x0C R/W IP Reset Control Resister1

Reset Value

0x0000_0000 SYS_IPRST1

31

Reserved

23

15

Reserved

7

TMR1RST

30

ANARST

22

Reserved

14

Reserved

6

TMR0RST

29

I2S0RST

21

13

DPWMRST

5

Reserved

28 27

SDADCRST SARADCRST

20 19

PWM0RST

12

SPI0RST

4

Reserved

Reserved

11

SPI1RST

3

Reserved

26

18

BIQRST

10

Reserved

2

Reserved

25

Reserved

17

24

16

UART1RST UART0RST

9 8

Reserved I2C0RST

1

Reserved

0

Reserved

Table 5-5 IP Reset Control Register 1 (SYS_IPRST1 address 0x5000_000C) Bit Description.

Bits

[31]

Description

Reserved

[30]

[29]

[28]

[27]

[26:21]

[20]

[19]

[18]

ANARST

I2S0RST

SDADCRST

SARADCRST

Reserved

PWM0RST

Reserved

BIQRST

Analog Block Control Reset

0=Normal Operation.

1=Reset.

I2S Controller Reset

0=Normal Operation.

1=Reset.

SDADC Controller Reset

0=Normal Operation.

1=Reset.

SAR ADC Controller Reset,

0 =Normal Operation.

1 = Reset,.

PWM0 Controller Reset

0=Normal Operation.

1=Reset.

Reserved

Biquad Filter Block Reset

0=Normal Operation.

1=Reset.

- 32 -


Revision 2.4

[17]

[16]

[15:14]

[13]

[12]

[11]

[10:9]

[8]

[7]

[6]

[5:0]

UART1RST

UART0RST

Reserved

DPWMRST

SPI0 RST

SPI1 RST

Reserved

I2C0RST

TMR1RST

TMR0RST

Reserved


UART1 Controller Reset

0=Normal Operation.

1=Reset.

UART0 Controller Reset

0=Normal Operation.

1=Reset.

DPWM Speaker Driver Reset

0=Normal Operation.

1=Reset.

SPI0 Controller Reset

0=Normal Operation.

1=Reset.

SPI1 Controller Reset

0=Normal Operation.

1=Reset.

I2C0 Controller Reset

0=Normal Operation.

1=Reset.

Timer1 Controller Reset

0=Normal Operation.

1=Reset.

Timer0 Controller Reset

0=Normal Operation.

1=Reset.

- 33 -


Revision 2.4


GPIOA Input Type Control Register (SYS_GPSMTEN)


SYS_GPSMTEN SYS_BA+0x30 R/W GPIOA/B input type control register

31

HSGPBG3

23

HSGPAG3

15

7

30

SSGPBG3

22

SSGPAG3

14

6

29

HSGPBG2

21

HSGPAG2

13

5

28

SSGPBG2

20

SSGPAG2

12

Reserved

27

HSGPBG1

19

HSGPAG1

11

4 3

Reserved

26

SSGPBG1

18

SSGPAG1

10

2

Bits

[31]

[30]

[29]

[28]

[27]

25

HSGPBG0

17

HSGPAG0

9

1

Reset Value

0xFFFF_0000

24

SSGPBG0

16

SSGPAG0

8

0

Table 5-6 GPIOA Input Type Control Register (SYS_PASMTEN address 0x5000_0030)

Description

HSSGPBG3

SSGPBG3

HSSGPBG2

SSGPBG2

HSSGPBG1

this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is

Enabled and Whether High or Low Slew Rate Is Selected for Output Dr.

Each bit controls a group of four GPIO pins

1 = GPIOB 15/14/13/12 Output high slew rate.

0 = GPIOB 15/14/13/12 Output low slew rate .




1 = GPIOB 15/14/13/12 input Schmitt Trigger enabled.

0 = GPIOB 15/14/13/12 input CMOS enabled.
















- 34 -


Revision 2.4

[26]

[25]

[24]

[23]

[22]

[21]

[20]

[19]

[18]

SSGPBG1

HSSGPBG0

SSGPBG0

HSSGPAG3

SSGPAG3

HSSGPAG2

SSGPAG2

HSSGPAG1

SSGPAG1




















1 = GPIOA 15/14/13/12 Output high slew rate.

0 = GPIOA 15/14/13/12 Output low slew rate .




1 = GPIOA 15/14/13/12 input Schmitt Trigger enabled.

0 = GPIOA 15/14/13/12 input CMOS enabled.





















- 35 -


Revision 2.4

[17]

[16]

[15:0]

HSSGPAG0

SSGPAG0

Reserved












Reserved.

- 36 -


Revision 2.4


GPIO Alternative Function Control Register (SYS_GPA_MFP, SYS_GPB_MFP)

Each GPIO pin can take on multiple alternate functions depending on the setting of this register. Each pin has two bits of alternate function control. Set to 00 the pin is a standard GPIO pin whose attributes

are defined by the GPIO control registers (See Section 0). Set to other values the pin is assigned to a

peripheral as outlined in table below.


SYS_GPA_MFP SYS_BA+0x38 R/W GPIOA multiple alternate functions control register

Reset Value

0x0000_0000

31 30 29 28 27 26 25 24

PA15MFP PA14MFP PA13MFP PA12MFP

23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8


7 6 5 4 3 2 1


Bits

[31:30]

[29:28]

[27:26]

[25:24]

Table 5-7 GPIOA Alternate Function Register (SYS_GPA_MFP address 0x5000_0038)

Description

PA15MFP

PA14MFP

PA13MFP

PA12MFP

Alternate Function Setting for PA15MFP

00 = GPIO.

01 = UART1_RX.

10 = MCLK.

11 = X32KO.


00 = GPIO.

01 = UART1_TX.

10 = DMIC_CLK.

11 = X32KI.


00 = GPIO.

01 = PWM0CH3.

10 = X12MO.

11 = I2C0_SCL.


00 = GPIO.

01 = PWM0CH2.

10 = X12MI.

11 = I2C0_SDA.

0

- 37 -


Revision 2.4

[23:22]

[21:20]

[19:18]

[17:16]

[15:14]

[13:12]

[11:10]

[9:8]

[7:6]

PA11MFP

PA10MFP

PA9MFP

PA8MFP

PA7MFP

PA6MFP

PA5MFP

PA4MFP

PA3MFP



00 = GPIO.

01 = PWM0CH1.

10 = TM1.

11 = DPWM_M.


00 = GPIO.

01 = PWM0CH0.

10 = TM0.

11 = DPWM_P.


00 = GPIO.

01 = I2C0_SCL.

10 = UART1_RX.

11 = UART0_CTSn.


00 = GPIO.

01 = I2C0_SDA.

10 = UART1_TX.

11 = UART0_RTSn.


00 = GPIO.

01 = UART0_RX.

10 = I2C0_SCL.

11 = SPI1_MISO.


00 = GPIO.

01 = UART0_TX.

10 = I2C0_SDA.

11 = SPI1_SSB.


00 = GPIO.

01 = SPI0_MOSI1.

10 = UART0_RX.

11 = SPI1_SCLK.


00 = GPIO.

01 = SPI0_MISO0.

10 = UART0_TX.

11 = SPI1_MOSI


00 = GPIO.

01 = SPI0_SSB0.

10 = SARADC_TRIG.

11 = I2S0_SDO.

- 38 -


Revision 2.4


[5:4]

[3:2]

[1:0]

PA2MFP

PA1MFP

PA0MFP


00 = GPIO.

01 = SPI0_SCLK0.

10 = DMIC_DAT.

11 = I2S0_SDI


00 = GPIO.

01 = SPI0_MOSI0.

11 = I2S0_BCLK.


00 = GPIO.

01 = SPI0_MISO1.

11 = I2S0_FS.


SYS_GPB_MFP SYS_BA+0x3C R/W GPIOB multiple alternate functions control register

31

PB15MFP

30

23 22

PB11MFP

15 14

PB7MFP

7 6

PB3MFP

29

PB14MFP

28

21 20

PB10MFP

13 12

PB6MFP

5 4

PB2MFP

27

PB13MFP

26

19 18

PB9MFP

11 10

PB5MFP

3 2

PB1MFP

Reset Value

0x0000_0000

25

PB12MFP

24

17 16

PB8MFP

9 8

PB4MFP

1 0

PB0MFP

Bits

[31:30]

[29:28]

Table 5-8 GPIOB Alternate Function Register (SYS_GPB_MFP address 0x5000_003C)

Description

PB15MFP

PB14MFP

Alternate Function Setting for PB15MFP

00 = GPIO.

01 = SPI0_SSB0

10 = SPI1_MISO.

11 = MCLK.


00 = GPIO.

01 = SPI0_SCLK0.

10 = SPI1_SSB.

11 = DMIC_CLK.

- 39 -


Revision 2.4

[15:14]

[13:12]

[11:10]

[9:8]

[7:6]

[27:26]

[25:24]

[23:22]

[21:20]

[19:18]

[17:16]

PB13MFP

PB12MFP

PB11MFP

PB10MFP

PB9MFP

PB8MFP

PB7MFP

PB6MFP

PB5MFP

PB4MFP

PB3MFP



00 = GPIO.

01 = SPI0_MOSI0.

10 = SPI1_SCLK.

11 = SARADC_TRIG.


00 = GPIO.

01 = SP0_MISO1.

10 = SPI1_MOSI.

11 = DMIC_DAT.


00 = GPIO.

10 = I2S0_SDO.

11 = UART1_RX.


00 = GPIO.

10 = I2S0_SDI.

11 = UART1_TX.


00 = GPIO.

01 = I2C0_SCL.

10 = I2S0_BCLK.

11 = UART1_CTsn.


00 = GPIO.

01 = I2C0_SDA

10 = I2S0_FS.

11 = UART1_RSTn.


00 = GPIO.

01 = I2S0_SDO.


00 = GPIO.

01 = I2S0_SDI.


00 = GPIO.

01 = I2S0_BCLK.


00 = GPIO.

01 = I2S0_FS.


00 = GPIO.

01 = SPI1_MISO.

- 40 -


Revision 2.4


[5:4]

[3:2]

[1:0]

GPIO

GPIOA0

GPIOA1

PB2MFP

PB1MFP


00 = GPIO.

01 = SPI1_SSB.


00 = GPIO.

01 = SPI1_SCLK.

PB0MFP


00 = GPIO.

01 = SPI1_MOSI.

Table 5-9 GPIOA Alternate Function Register (GPA_ALT address 0x5000_0038)

Power

Domain

VDD33

VDD33

GPAn=01

Type Function

SPI0_HOLD0

(MISO1)

IO

SPI0_MOSI0 O

GPAn =10

Function Type

GPAn =11

Function

I2S0_FS

I2S0_BCLK

Type

IO

IO

GPIOA2 VDD33

VDD33

SPI0_SCLK0

SPI0_SSB0

O

IO

DMIC_DAT I

SARADC_TRIG I

I2S0_SDI

I2S0_SDO

I

O GPIOA3

GPIOA4 VDD33 UART0_TX O SPI1_MOSI O

GPIOA5

GPIOA6

GPIOA7

VDD33

VDD33

VDD33

SPI0_MISO0 IO

SPI0_WP0

(MOSI1)

IO

UART0_TX O

UART0_RX I

UART0_RX

I2C0_SDA

I2C0_SCL

I

IO

IO

SPI1_SCLK

SPI1_SSB

SPI1_MISO

O

IO

I

GPIOA8

GPIOA9

VCCD

VCCD

GPIOA10 VCCD

GPIOA11 VCCD

GPIOA12 VCCD

GPIOA13 VCCD

GPIOA14 VCCD

I2C0_SDA

I2C0_SCL

PWM0CH0

PWM0CH1

PWM0CH2

PWM0CH3

UART1_TX

IO

IO

O

O

O

O

O

UART1_TX

UART1_RX

TM0

TM1

X12MI

X12MO

DMIC_CLK

I

I

O

I

I

O

IO

UART0_RTSn O

UART0_CTSn I

DPWM_P

DPWM_M

O

O

I2C0_SDA

I2C0_SCL

X32KI

IO

IO

I

GPIOA15 VCCD UART1_RX IO MCLK O X32KO O

Table 5-10 GPIOB Alternate Function Register (SYS_GPB_MFP address 0x5000_003C)

GPIO

GPBn=01 GPBn =10 GPBn =11

Power

Domain

Function Type Function Type Function Type

Analog Functions

- 41 -


Revision 2.4


GPIOB0 VCCD SPI1_MOSI O

GPIOB1 VCCD SPI1_SCLK O

GPIOB2 VCCD SPI1_SSB IO

GPIOB3 VCCD SPI1_MISO I

GPIOB4 VCCD I2S0_FS IO

GPIOB5 VCCD I2S0_BCLK IO

GPIOB6 VCCD I2S0_SDI I

GPIOB7 VCCD I2S0_SDO O

GPIOB8 VCCD I2C0_SDA

GPIOB9 VCCD I2C0_SCL

GPIOB10 VCCD CMP1 O

GPIOB11 VCCD CMP2 O

GPIOB12 VCCD SPI0_MISO1 I

GPIOB13 VCCD SPI0_MOSI0 O

GPIOB14 VCCD SPI0_SCLK0 O

GPIOB15 VCCD SPI0_SSB0 O

I2S0_FS IO

I2S0_BCLK IO

I2S0_SDI I

I2S0_SDO O

SPI1_MOSI O

SPI1_SCLK O

SPI1_SSB IO

SPI1_MISO I

UART1_RSTn IO

UART1_CTsn IO

UART1_TX I

UART1_RX I

DMIC_DAT I

SARADC_TRIG O

DMIC_CLK

MCLK

O

O

CS0

CS1

CS2

CS3

A0P

A0N

A0E SAR11

A1P

CS4

CS5

CS6

CS7

CS8

CS9

CS10

A1N

A1E SAR10

CNP SAR8

C1N SAR9

C2P SAR0

SAR1

SAR2

CS11

CS12

CS13

CS14

CS15

SAR3

SAR4

SAR5

SAR6

SAR7

- 42 -


Revision 2.4


Protected Register Lock Key Register (SYS_REGLCTL)

Certain critical system control registers are protected against inadvertent write operations which may disturb chip operation. These system control registers are locked after power on reset until the user specifically issues an unlock sequence to open the lock. The unlock sequence is to write to

SYS_REGLCTL the data 0x59, 0x16, 0x88. Any different sequence, data or a write to any other address will abort the unlock sequence.

MDK provides the defined function UNLOCKREG(x); which will execute this sequence.

The status of the lock can be determined by reading SYS_REGLCTL bit0: “1” is unlocked, “0” is locked. Once unlocked, user can update protected register values. To lock registers again, write any data to SYS_REGLCTL.

This register is write accessible for writing key values and read accessible to determine REGLCTL status.

Register Offset R/W Description Reset Value

0x0000_0000 SYS_REGLCTL SYS_BA+0x100 R/W Register Lock Control

7 6 5 4

Reserved

3 2 1 0

REGLCTL

Bits

[31:1]

[0]

Table 5-11 Protected Register Lock Key Register (SYS_REGLCTL address 0x5000_0100).

Description

Reserved

REGLCTL

Reserved.

Protected Register Unlock Register

0 = Protected registers are locked. Any write to the target register is ignored.

1 = Protected registers are unlocked.

- 43 -


Revision 2.4


Oscillator Trim Control Register (SYS_IRCTCTL)

The master oscillator of the ISD91200 has an adjustable frequency and can be controlled by the

SYS_IRCTCTL register. This register contains the current scillator frequency trim value, which depends upon the setting of register CLK_CLKSEL0.HIRCFSEL register. If this register is 0,

SYS_OSCTRIM0 trim is active, if 1 then

SYS_OSCTRIM1 is active, if 2 then

SYS_OSCTRIM2

.

Upon power on reset this register is loaded from flash memory with factory stored values to give oscillator frequencies of 49.152MHz for

SYS_OSCTRIM0

, 32.768MHz for

SYS_OSCTRIM1 and no factory trimming for SYS_OSCTRIM2 (customer need to set a workable value before change to use)

. If users wish to change the default frequency, it is possible to do so by setting this register. A write to FREQ will change the active SYS_OSCTRIMn register, or writing active

SYS_OSCTRIMn.TRIM (n=0,1,2) will change the FREQ.

This register is a protected register, to write to register first issue the unlock sequence


SYS_IRCTCTL SYS_BA+0x110 R/W Oscillator Frequency Adjustment control register

31

23

15

RANGE

7

30

22

14

6

29

21

13

5

28 27

20

Reserved

19

Reserved

12

Reserved

4

11

3

FREQ

26

18

10

2

25

17

9

1

Reset Value

0xXXXX_XXXX

FREQ

24

16

8

0

Table 5-12 Oscillator Frequency Adjust Control Register (SYS_IRCTCTL, address 0x5000_0110).

Bits

[31:16]

Description

Reserved

[15]

[14:10]

[9:0]

RANGE

Reserved

FREQ

1: Low Frequency mode of oscillator active (2MHz).

0: High frequency mode (20-50MHz)

Current oscillator frequency trim value. (based on CLK_CLKSEL0.HIRCFSEL)

- 44 -


Revision 2.4


10kHz Oscillator Trim Register (SYS_OSC10KTRIM)


SYS_OSC10KTRIM SYS_BA+0x114 R/W 10kHz Oscillator (LIRC) Trim Register

31

TRMCLK

23

Reserved

15

30

22

14

29

Reserved

21

13

28

20

12

27

19

TRIM

11

26

18

10

Reserved

25

17

9

TRIM

7 6 5 4 3 2 1

TRIM

Reset Value

0xXXXX_XXXX

24

16

8

0

Bits

[31]

[30:28]

[27:23]

[22:0]

Description

TRMCLK

Reserved

Reserved

TRIM

Must be toggled to( from 0 => 1 => 0) load a new OSC10K_TRIM

23bit trim for LIRC.

- 45 -


Revision 2.4


Oscillator Trim 0 Control Register (SYS_OSCTRIM0)

Register Offset R/W Description

SYS_OSCTRIM0

SYS_BA+0x118

R/W

Internal oscillator trim register 0

31

EN2MHZ

23

15

7

30

22

14

6

29

21

13

5

28

20

27

Reserved

19

Reserved

12 11

TRIM

4 3

TRIM

26

18

10

2

25

17

9

1

Reset Value

0xXXXX_XXXX

Table 5-13 Oscillator Frequency Adjust Control Register (OSCTRIM0, address

0x5000_0118).

24

16

8

0

Bits Description

[31]

[30:16]

[15:0]

EN2MHZ

Reserved

TRIM



Reserved

16bit sign extended representation of 10bit trim.

- 46 -


Revision 2.4




SYS_OSCTRIM1

SYS_BA+0x11C

R/W


31

EN2MHZ

23

15

7

30

22

14

6

29

21

13

5

28

20

27

Reserved

19

Reserved

12 11

TRIM

4 3

TRIM

26

18

10

2

25

17

9

1

Reset Value

0xXXXX_XXXX

Table 5-14 Oscillator Frequency Adjust Control Register (OSCTRIM1, address

0x5000_011C).

24

16

8

0


[31]

[30:16]

[15:0]

EN2MHZ

Reserved

TRIM



Reserved

16bit sign extended representation of 10bit trim.

- 47 -


Revision 2.4




SYS_OSCTRIM2

SYS_BA+0x120

R/W


31

EN2MHZ

23

15

7

30

22

14

6

29

21

13

5

28

20

27

Reserved

19

Reserved

12 11

TRIM

4 3

TRIM

26

18

10

2

25

17

9

1

Reset Value

0xXXXX_XXXX

24

16

8

0

Table 5-15 Oscillator Frequency Adjust Control Register (OSCTRIM, address 0x5000_0120).


[31]

[30:16]

EN2MHZ



Reserved

16bit sign extended representation of 10bit trim. [15:0]

Reserved

TRIM

- 48 -


Revision 2.4


[16]

[15:10]

[9]

[8:6]

[5:3]

[2:0]

XTAL32K Oscillator Control Register (SYS_XTALTRIM)


SYS_XTALTRIM

SYS_BA+0x124

R/W

External Crystal oscillator trim register

31

23

15

7

Reserved

30

22

14

6

29 28

21

13

Reserved

20

Reserved

12

5

Reserved

4

Reserved

27

19

11

3

26

18

10

2

Table 5-16 Xtal Trim

Bits

[31:26]

[25:24]

[23:17]

Description

Reserved

XGS

Reserved

SELXT

Reserved

LOWPWR

Reserved

Reserved

Reserved

HXT Gain Select

HXT select external clock

0: Disable

1: Enable

1: low power mode. 0: normal mode.

Leave at default. Do not modify



Reset Value

0xXXXX_XXXX

25 24

17

9

LOWPWR

1

Reserved

XGS

16

SELXT

8

Reserved

0

- 49 -


Revision 2.4


Reserved

Register Offset

Reserved

SYS_BA+0x128

31 30 29

R/W Description

R/W

System reserved, keep POR value

28 27

Reserved

23 22 21 20 19

Reserved

15 14 13 12 11

Reserved

7 6 5 4 3

Reserved

26

18

10

2

Table 5-17 Factory Default

Bits

[31:0]

Description

Reserved

25

17

9

1

Reset Value

0xXXXX_XXXX

This register is loaded with trim from manufacturing – do not modify.

24

16

8

0

- 50 -


Revision 2.4


5.2.6 System Timer (SysTick)

The Cortex-M0 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit, clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example:

 An RTOS tick timer which fires at a programmable rate (for example 100Hz) and invokes a

SysTick routine.

 A high speed alarm timer using Core clock.

 A variable rate alarm or signal timer – the duration range dependent on the reference clock used and the dynamic range of the counter.

 A simple counter. Software can use this to measure time to completion and time used.

 An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field in the control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop.

When enabled, the timer will count down from the value in the SysTick Current Value Register

(SYST_CVR) to zero, reload (wrap) to the value in the SysTick Reload Value Register (SYST_RVR) on the next clock edge, then decrement on subsequent clocks. When the counter transitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.

The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to zero before enabling the feature. This ensures the timer will count from the SYST_RVR value rather than an arbitrary value when it is enabled.

If the SYST_RVR is zero, the timer will be maintained with a current value of zero after it is reloaded with this value. This mechanism can be used to disable the feature independently from the timer enable bit.

In DEEPSLEEP and power down modes, the SysTick timer is disabled so cannot be used to wake up the device.

For more detailed information, please refer to the documents “ ARM® Cortex™-M0 Technical

Reference Manual” and “ ARM® v6-M Architecture Reference Manual”.

5.2.6.1 System Timer Control Register Map

R : read only, W : write only, R/W : both read and write, W&C : Write 1 clear


SYSTICK Base Address:

SYSTICK_BA = 0xE000_E000

SYST_CSR

SYST_RVR

SYSTICK_BA+0x10 R/W

SYSTICK_BA+0x14 R/W

SysTick Control and Status Register

SysTick Reload value Register

SYST_CVR SYSTICK_BA+0x18 R/W SysTick Current value Register

0x0000_0000

0xXXXX_XXXX

0xXXXX_XXXX

Note: In BSP register structure, the prefix is structure name, and register will be no prefix, for example

SYSTICK_ is the prefix, SYSTICK_CSR will be SYSTICK->CSR

5.2.6.2 System Timer Control Register Description

- 51 -


Revision 2.4


Register

SysTick Control and Status （ SYST_CSR ）

Offset R/W Description

SYSTICK_BA+0x10 R/W SysTick Control and Status Register SYST_CSR

31

23

15

7

Table 5-18 SysTick Control and Status Register (SYST_CSR, address 0xE000_E010)

30 29 28 27 26 25

22

14

6

21

13

Reserved

20

Reserved

12

19

11

Reserved

4 3

18

10

17

9

5

Reserved

2

CLKSRC

1

TICKINT

Reset Value

0x0000_0000

24

16

COUNTFLAG

8

0

ENABLE


[31:17] Reserved

[16]

[15:3]

[2]

[1]

[0]

COUNTFLAG

Reserved

CLKSRC

TICKINT

ENABLE

Reserved

Count Flag

Returns 1 if timer counted to 0 since last time this register was read.

0= Cleared on read or by a write to the Current Value register.

1= Set by a count transition from 1 to 0.

Reserved

Clock Source

0= Core clock unused.

1= Core clock used for SysTick, this bit will read as 1 and ignore writes.

Enables SysTick Exception Request

0 = Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred.

1 = Counting down to 0 will cause SysTick exception to be pended. Clearing the

SysTick Current Value register by a register write in software will not cause

SysTick to be pended.

ENABLE

0 = The counter is disabled

1 = The counter will operate in a multi-shot manner.

- 52 -


Revision 2.4


Register

SysTick Reload Value Register （ SYST_RVR ）


SYSTICK_BA+0x14 R/W SysTick Reload value Register SYST_RVR

31

23

15

7

Table 5-19 SysTick Reload Value Register (SYST_RVR, address 0xE000_E014)

30 29 28 27 26 25

22

14

6

21

13

5

Reserved

20 19

RELOAD[23:16]

12

RELOAD[15:8]

11

4 3

RELOAD[7:0]

18

10

2

17

9

1


[31:24] Reserved

[23:0] RELOAD

Reset Value

0xXXXX_XXXX

24

16

8

0

Reserved

SysTick Reload

Value to load into the Current Value register when the counter reaches 0.

To generate a multi-shot timer with a period of N processor clock cycles, use a

RELOAD value of N-1. For example, if the SysTick interrupt is required every 200 clock pulses, set RELOAD to 199.

- 53 -


Revision 2.4


Register

SysTick Current Value Register （ SYST_CVR ）


SYSTICK_BA+0x18 R/W SysTick Current value Register SYST_CVR

31

23

15

7

Table 5-20 SysTick Current Value Register (SYST_CVR, address 0xE000_E018)

30 29 28 27 26 25

22

14

6

21

13

5

Reserved

20 19

CURRENT [23:16]

12 11

CURRENT [15:8]

4

CURRENT[7:0]

3

18

10

2

17

9

1


[31:24] Reserved

[23:0] CURRENT

Reset Value

0xXXXX_XXXX

24

16

8

0

Reserved

Current Counter Value

This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0 and also clear the COUNTFLAG bit.

- 54 -


Revision 2.4


5.2.7 Nested Vectored Interrupt Controller (NVIC)

Cortex-M0 includes an interrupt controller the “Nested Vectored Interrupt Controller (NVIC)”. It is closely coupled to the processor kernel and provides following features:

 Nested and Vectored interrupt support

 Automatic processor state saving and restoration

 Dynamic priority changing

 Reduced and deterministic interrupt latency

The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler

Mode”. This NVIC architecture supports 32 (IRQ [31:0]) discrete interrupts with 4 levels of priority. All of the interrupts and most of the system exceptions can be configured to different priority levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the current running one’s priority. If the priority of the new interrupt is higher than the current one, the new interrupt handler will override the current handler.

When any interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched from a vector table in memory. There is no need to determine which interrupt is accepted and branch to the starting address of the corresponding ISR by software. While the starting address is fetched,

NVIC will also automatically save processor state including the registers “PC, PSR, LR, R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the above mentioned registers from the stack and resume normal execution. This provides a high speed and deterministic time to process any interrupt request.

The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the overhead of state saving and restoration and therefore reduces delay time in switching to a pending

ISR at the end of the current ISR. The NVIC also supports “Late Arrival” which improves the efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will give priority to the higher one without delay penalty. This aids real-time, high priority, interrupt capability.

For more detailed information, please refer to the documents “ARM® Cortex™-M0 Technical

Reference Manual” and “ “ARM® v6-M Architecture Reference Manual” .

5.2.7.1 Exception Model and System Interrupt Map

The following table lists the exception model supported by ISD91200 series. Software can set four levels of priority on certain exceptions as well as on all interrupts. The highest user-configurable priority is denoted as “0” and the lowest priority is denoted as “3”. The default priority of all the userconfigurable interrupts is “0”. Note that priority “0” is treated as the fourth priority on the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”.

- 55 -


Revision 2.4


Exception Name

Table 5-21 Exception Model

Vector Number Priority

Reset

NMI

Hard Fault

Reserved

SVCall

Reserved

PendSV

SysTick

Interrupt (IRQ0 ~ IRQ31)

1

2

3

4 ~ 10

11

12 ~ 13

14

15

16 ~ 47

Table 5-22 System Interrupt Map

-3

-2

-1

N/A

Configurable

N/A

Configurable

Configurable

Configurable

Vector

Number

Interrupt Number

(Bit in Interrupt

Registers)

0 ~ 15

16

17

18

19

20

21

22

23

24

1

2

-

0

3

4

5

6

7

8

Interrupt

Name

Source IP Interrupt description

- - System exceptions

BOD_IRQn

WDT_IRQn

Brown-Out

WDT

EINT0_IRQn GPIO

Brownout low voltage detector interrupt

Watch Dog Timer interrupt

External signal interrupt from PB.0 pin

EINT1_IRQn GPIO External signal interrupt from PB.1 pin

External signal interrupt from PA[15:0] / PB[7:2] GPAB_IRQn GPIO

ALC_IRQn ALC

PWM0_IRQn PWM0

Automatic Level Control Interrupt

PWM0 channel 0/1/2/3 interrupt

Reserved

TMR0_IRQn TMR0 Timer 0 interrupt

- 56 -


Revision 2.4


33

34

35

36

37

38

39

40

41

42

43

25

26

27

28

29

30

31

32

44

17

18

19

20

21

22

23

24

25

26

27

9

10

11

12

13

14

15

16

28

TMR1_IRQn

Reserved

UART1_IRQn

UART0_IRQn

SPI1_IRQn

SPI0_IRQn

DPWM_IRQn

Reserved

Reserved

I2C0_IRQn

Reserved

Reserved

CMP_IRQn

Reserved

Reserved

Reserved

SARADC_IRQn

PDMA_IRQn

I2S0_IRQn

CAPS_IRQn

TMR1

UART1

UART0

SPI1

Timer 1 interrupt

UART1interrupt

UART0 interrupt

SPI1 interrupt

SPI0

DPWM

SPI0 interrupt

DPWM interrupt

I2C0

CMP

I2C0 interrupt

CMP interrupt

SARADC SARADC interrupt

PDMA PDMA interrupt

I2S

ANA

I2S0 interrupt

Capacitive Touch Sensing Relaxation Oscillator

Interrupt

SDADC Audio ADC interrupt

RTC Real time clock interrupt

45

46

47

29

30

31

ADC_INT

Reserved

RTC_INT

5.2.7.2 Vector Table

When an interrupt is accepted, the processor will automatically fetch the starting address of the interrupt service routine (ISR) from the vector table in memory. For ARMv6-M, the vector table base address is fixed in flash at 0x00000000. The vector table contains the initialization value for the stack pointer on reset, and the entry point addresses for all exception handlers. The vector number on previous page defines the order of entries in the vector table.

Vector Table Word

Offset

0

Vector Number

Description

SP_main - The Main stack pointer

Exception Entry Pointer using that Vector Number

Table 5-23 Vector Table Format

- 57 -


Revision 2.4


5.2.7.3 Operation Description

NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-Enable or

Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading back the current enabled state of the corresponding interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become Pending, however, the interrupt will not activate. If an interrupt is Active when it is disabled, it remains in its Active state until cleared by reset or an exception return. Clearing the enable bit prevents new activations of the associated interrupt.

NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading back the current pended state of the corresponding interrupts. The Clear-Pending Register has no effect on the execution status of an Active interrupt.

NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register supporting four interrupts).

The general registers associated with the NVIC are all accessible from a block of memory in the

System Control Space and will be described in next section.

- 58 -


Revision 2.4


5.2.7.4 NVIC Control Registers



SCS Base Address:

SCS_BA = 0xE000_E100

NVIC_ISER SCS_BA+0x000 R/W IRQ0 ~ IRQ31 Set-Enable Control Register

NVIC_ICER SCS_BA+0x080 R/W IRQ0 ~ IRQ31 Clear-Enable Control Register

NVIC_ISPR

NVIC_ICPR

NVIC_IPR0

NVIC_IPR1

NVIC_IPR2

NVIC_IPR3

NVIC_IPR4

SCS_BA+0x100

SCS_BA+0x180

SCS_BA+0x300

SCS_BA+0x304

SCS_BA+0x308

SCS_BA+0x30C

SCS_BA+0x310

R/W

R/W

R/W

R/W

R/W

R/W

R/W

IRQ0 ~ IRQ31 Set-Pending Control Register

IRQ0 ~ IRQ31 Clear-Pending Control Register

IRQ0 ~ IRQ3 Priority Control Register





Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

NVIC_IPR5

NVIC_IPR6

SCS_BA+0x314

SCS_BA+0x318

R/W

R/W



0x0000_0000

0x0000_0000

NVIC_IPR7 SCS_BA+0x31C R/W IRQ28 ~ IRQ31 Priority Control Register 0x0000_0000


NVIC_ is the prefix, NVIC_ISER will be NVIC->ISER

- 59 -


Revision 2.4


IRQ0 ~ IRQ31 Set-Enable Control Register （ NVIC_ISER ）


NVIC_ISER SCS_BA+0x000 R/W IRQ0 ~ IRQ31 Set-Enable Control Register 0x0000_0000

If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.

Table 5-24 Interrupt Set-Enable Control Register (ISER, address 0xE000_E100) Bit Description


[31:0] SETENA

Set-enable Control

Enable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).

Writing 1 will enable the associated interrupt.

Writing 0 has no effect.

The register reads back the current enable state.

- 60 -


Revision 2.4


IRQ0 ~ IRQ31 Clear-Enable Control Register (NVIC_ICER ）


NVIC_ICER SCS_BA+0x080 R/W IRQ0 ~ IRQ31 Clear-Enable Control Register 0x0000_0000

Table 5-25 Interrupt Clear-Enable Control Register (ICER, address 0xE000_E180) Bit Description


[31:0] CLRENA

Clear-enable Control

Disable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).

Writing 1 will disable the associated interrupt.


The register reads back with the current enable state.

- 61 -


Revision 2.4


IRQ0 ~ IRQ31 Set-Pending Control Register （ NVIC_ISPR ）


NVIC_ISPR SCS_BA+0x100 R/W IRQ0 ~ IRQ31 Set-Pending Control Register 0x0000_0000

Table 5-26 Interrupt Set-Pending Control Register (ISPR, address 0xE000_E200)


[31:0] SETPEND

Set-pending Control

Writing 1 to a bit forces pending state of the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).


The register reads back with the current pending state.

- 62 -


Revision 2.4


IRQ0 ~ IRQ31 Clear-Pending Control Register （ NVIC_ICPR ）


NVIC_ICPR SCS_BA+0x180 R/W IRQ0 ~ IRQ31 Clear-Pending Control Register 0x0000_0000

Table 5-27 Interrupt Clear-Pending Control Register (ICPR, address 0xE000_E280)


[31:0] CLRPEND

Clear-pending Control

Writing 1 to a bit to clear the pending state of associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).


The register reads back with the current pending state.

- 63 -


Revision 2.4


IRQ0 ~ IRQ3 Interrupt Priority Register （ NVIC_IPR0 ）


NVIC_IPR0

31

PRI_3

SCS_BA+0x300 R/W IRQ0 ~ IRQ3 Priority Control Register

30 29 28 27

Reserved

26

23 22 21 20 19 18

PRI_2 Reserved

15 14 13 12 11 10

PRI_1 Reserved

7 6 5 4 3 2

PRI_0 Reserved

25

17

9

1

Table 5-28 Interrupt Priority Register (IPR0, address 0xE000_E400)

Reset Value

0x0000_0000

24

16

8

0


[31:30]

[23:22]

[15:14]

[7:6]

PRI_3

PRI_2

PRI_1

PRI_0

Priority of IRQ3

“0” denotes the highest priority and “3” denotes lowest priority







- 64 -


Revision 2.4




NVIC_IPR1

31

PRI_7


30 29 28 27

Reserved

26

23 22 21 20 19 18

PRI_6 Reserved

15 14 13 12 11 10

PRI_5 Reserved

7 6 5 4 3 2

PRI_4 Reserved

25

17

9

1


Reset Value

0x0000_0000

24

16

8

0


[31:30]

[23:22]

[15:14]

[7:6]

PRI_7

PRI_6

PRI_5

PRI_4









- 65 -


Revision 2.4




NVIC_IPR2

31

PRI_11


30 29 28 27

Reserved

26

23 22 21 20 19 18

PRI_10 Reserved

15 14 13 12 11 10

PRI_9 Reserved

7 6 5 4 3 2

PRI_8 Reserved

25

17

9

1


Reset Value

0x0000_0000

24

16

8

0


[31:30]

[23:22]

[15:14]

[7:6]

PRI_11

PRI_10

PRI_9

PRI_8









- 66 -


Revision 2.4




NVIC_IPR3

31

PRI_15

SCS_BA+0x30C R/W IRQ12 ~ IRQ15 Priority Control Register

30 29 28 27

Reserved

26

23 22 21 20 19 18

PRI_14 Reserved

15 14 13 12 11 10

PRI_13 Reserved

7 6 5 4 3 2

PRI_12 Reserved

25

17

9

1

Table 5-31 Interrupt Priority Register (IPR3, address 0xE000_E40C)

Reset Value

0x0000_0000

24

16

8

0


[31:30]

[23:22]

[15:14]

[7:6]

PRI_15

PRI_14

PRI_13

PRI_12









- 67 -


Revision 2.4




NVIC_IPR4

31

PRI_19


30 29 28 27

Reserved

26

23 22 21 20 19 18

PRI_18 Reserved

15 14 13 12 11 10

PRI_17 Reserved

7 6 5 4 3 2

PRI_16 Reserved

25

17

9

1


Reset Value

0x0000_0000

24

16

8

0


[31:30]

[23:22]

[15:14]

[7:6]

PRI_19

PRI_18

PRI_17

PRI_16









- 68 -


Revision 2.4




NVIC_IPR5

31

PRI_23


30 29 28 27

Reserved

26

23 22 21 20 19 18

PRI_22 Reserved

15 14 13 12 11 10

PRI_21 Reserved

7 6 5 4 3 2

PRI_20 Reserved

25

17

9

1


Reset Value

0x0000_0000

24

16

8

0


[31:30]

[23:22]

[15:14]

[7:6]

PRI_23

PRI_22

PRI_21

PRI_20









- 69 -


Revision 2.4




NVIC_IPR6

31

PRI_27


30 29 28 27

Reserved

26

23 22 21 20 19 18

PRI_26 Reserved

15 14 13 12 11 10

PRI_25 Reserved

7 6 5 4 3 2

PRI_24 Reserved

25

17

9

1


Reset Value

0x0000_0000

24

16

8

0


[31:30]

[23:22]

[15:14]

[7:6]

PRI_27

PRI_26

PRI_25

PRI_24









- 70 -


Revision 2.4




NVIC_IPR7

31

PRI_31

SCS_BA+0x31C R/W IRQ28 ~ IRQ31 Priority Control Register

30 29 28 27

Reserved

26

23 22 21 20 19 18

PRI_30 Reserved

15 14 13 12 11 10

PRI_29 Reserved

7 6 5 4 3 2

PRI_28 Reserved

25

17

9

1

Table 5-35 Interrupt Priority Register (IPR7, address 0xE000_E41C)

Reset Value

0x0000_0000

24

16

8

0


[31:30]

[23:22]

[15:14]

[7:6]

PRI_31

PRI_30

PRI_29

PRI_28









- 71 -


Revision 2.4


5.2.7.5 Interrupt Source Control Registers

Along with the interrupt control registers associated with the NVIC, the ISD91200 also implements some specific control registers to facilitate the interrupt functions, including “interrupt source identify”, ”NMI source selection” and “interrupt test mode”. They are described as below.



INT Base Address:

INT_BA = 0x5000_0300

IRQ0_SRC INT_BA+0x00 R IRQ0 (BOD) Interrupt Source Identity Register 0xXXXX_XXXX

INT_BA+0x04

INT_BA+0x08

INT_BA+0x0C

INT_BA+0x10

INT_BA+0x14

INT_BA+0x18

INT_BA+0x1C

INT_BA+0x20

INT_BA+0x24

INT_BA+0x28

INT_BA+0x2C

INT_BA+0x30

INT_BA+0x34

INT_BA+0x38

INT_BA+0x3C

INT_BA+0x40

INT_BA+0x44

INT_BA+0x48

INT_BA+0x4C

INT_BA+0x50

INT_BA+0x54

INT_BA+0x58

IRQ1_SRC

IRQ2_SRC

IRQ3_SRC

IRQ4_SRC

IRQ5_SRC

IRQ6_SRC

IRQ7_SRC

IRQ8_SRC

IRQ9_SRC

IRQ10_SRC

IRQ11_SRC

IRQ12_SRC

IRQ13_SRC

IRQ14_SRC

IRQ15_SRC

IRQ16_SRC

IRQ17_SRC

IRQ18_SRC

IRQ19_SRC

IRQ20_SRC

IRQ21_SRC

IRQ22_SRC

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

IRQ1 (WDT) Interrupt Source Identity Register

IRQ2 (EINT0) Interrupt Source Identity Register


IRQ4 (GPA/B) Interrupt Source Identity Register

IRQ5 (ALC) Interrupt Source Identity Register

IRQ6 (PWM0) Interrupt Source Identity Register

IRQ7 (Reserved) Interrupt Source Identity Register

IRQ8 (TMR0) Interrupt Source Identity Register



IRQ11 (UART1) Interrupt Source Identity Register


IRQ13 (SPI1) Interrupt Source Identity Register


IRQ15 (DPWM) Interrupt Source Identity Register



IRQ18 (I2C0) Interrupt Source Identity Register



IRQ21 (CMP) Interrupt Source Identity Register

IRQ22 (MAC ) Interrupt Source Identity Register

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

- 72 -


Revision 2.4


IRQ23_SRC

IRQ24_SRC

IRQ25_SRC

IRQ26_SRC

IRQ27_SRC

IRQ28_SRC

IRQ29_SRC

IRQ30_SRC

IRQ31_SRC

NMI_SEL

INT_BA+0x5C

INT_BA+0x60

INT_BA+0x64

INT_BA+0x68

INT_BA+0x6C

INT_BA+0x70

INT_BA+0x74

INT_BA+0x78

INT_BA+0x7C

INT_BA+0x80

R

R

R

R

R

R

R

R

R

R/W



IRQ25 (SARADC) Interrupt Source Identity Register

IRQ26 (PDMA) Interrupt Source Identity Register

IRQ27 (I2S0) Interrupt Source Identity Register

IRQ28 (CAPS) Interrupt Source Identity Register

IRQ29 (ADC) Interrupt Source Identity Register


IRQ31 (RTC) Interrupt Source Identity Register

NMI Source Interrupt Select Control Register

MCU_IRQ INT_BA+0x84 R/W MCU IRQ Number Identify Register

Note: In BSP register structure, INT_ is structure name, for example INT->MCU_IRQ.

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0x0000_0000

0x0000_0000

- 73 -


Revision 2.4


Register

IRQ0(BOD) Interrupt Source Identify Register (IRQ0_SRC)


INT_BA+0x00 R IRQ0 (BOD) Interrupt Source Identity Register IRQ0_SRC

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5

Reserved

4 3 2


[2:0] INT_SRC

Interrupt Source Identity

Bit2: 0

Bit1: 0

Bit0: BOD_INT

25

17

9

1

INT_SRC[2:0]

Reset Value

0xXXXX_XXXX

24

16

8

0

- 74 -


Revision 2.4


Register

IRQ1(WDT) Interrupt Source Identify Register (IRQ1_SRC)


INT_BA+0x04 R IRQ1 (WDT) Interrupt Source Identity Register IRQ1_SRC

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5

Reserved

4 3 2


[2:0] INT_SRC


Bit2: 0

Bit1: 0

Bit0: WDT_INT

25

17

9

1

INT_SRC[2:0]

Reset Value

0xXXXX_XXXX

24

16

8

0

- 75 -


Revision 2.4


Register

IRQ2(ENIT0) Interrupt Source Identify Register (IRQ2_SRC)


INT_BA+0x08 R IRQ2 (EINT0) Interrupt Source Identity Register IRQ2_SRC

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5

Reserved

4 3 2


25

17

9

1

INT_SRC[2:0]

Reset Value

0xXXXX_XXXX

24

16

8

0

[2:0] INT_SRC


Bit2: 0

Bit1: 0

Bit0: INT0_INT

- 76 -


Revision 2.4


Register

IRQ3(ENIT1) Interrupt Source Identify Register (IRQ3_SRC)


INT_BA+0x0C R IRQ3 (EINT1) Interrupt Source Identity Register IRQ3_SRC

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5

Reserved

4 3 2


25

17

9

1

INT_SRC[2:0]

Reset Value

0xXXXX_XXXX

24

16

8

0

[2:0] INT_SRC


Bit2: 0

Bit1: 0

Bit0: INT0_INT

- 77 -


Revision 2.4


Register

IRQ4(GPA/B) Interrupt Source Identify Register (IRQ4_SRC)


INT_BA+0x10 R IRQ4 (GPA/B) Interrupt Source Identity Register IRQ4_SRC

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5

Reserved

4 3 2


25

17

9

1

INT_SRC[2:0]

Reset Value

0xXXXX_XXXX

24

16

8

0

[2:0] INT_SRC


Bit2: 0

Bit1: GPB_INT

Bit0: GPA_INT

- 78 -


Revision 2.4


Register

IRQ5(ALC) Interrupt Source Identify Register (IRQ5_SRC)


INT_BA+0x14 R IRQ5 (ALC) Interrupt Source Identity Register IRQ5_SRC

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5

Reserved

4 3 2


[2:0] INT_SRC


Bit2: 0

Bit1: 0

Bit0: ALC_INT

25

17

9

1

INT_SRC[2:0]

Reset Value

0xXXXX_XXXX

24

16

8

0

- 79 -


Revision 2.4


Register

IRQ6(PWM0) Interrupt Source Identify Register (IRQ6_SRC)


INT_BA+0x18 R IRQ6 (PWM0) Interrupt Source Identity Register IRQ6_SRC

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5

Reserved

4 3 2


25

17

9

1

INT_SRC[2:0]

Reset Value

0xXXXX_XXXX

24

16

8

0

[2:0] INT_SRC


Bit2: 0

Bit1: 0

Bit0: PWM_INT

- 80 -


Revision 2.4


Register

IRQ8(TMR0) Interrupt Source Identify Register (IRQ8_SRC)


INT_BA+0x20 R IRQ8 (TMR0) Interrupt Source Identity Register IRQ8_SRC

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5

Reserved

4 3 2


25

17

9

1

INT_SRC[2:0]

Reset Value

0xXXXX_XXXX

24

16

8

0

[2:0] INT_SRC


Bit2: 0

Bit1: 0

Bit0: TMR0_INT

- 81 -


Revision 2.4


Register

IRQ9(TMR1) Interrupt Source Identify Register (IRQ9_SRC)


INT_BA+0x24 R IRQ9 (TMR1) Interrupt Source Identity Register IRQ9_SRC

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5

Reserved

4 3 2


25

17

9

1

INT_SRC[2:0]

Reset Value

0xXXXX_XXXX

24

16

8

0

[2:0] INT_SRC


Bit2: 0

Bit1: 0

Bit0: TMR1_INT

- 82 -


Revision 2.4


IRQ11(UART1) Interrupt Source Identify Register (IRQ11_SRC)


IRQ11_SRC INT_BA+0x2C R IRQ11 (UART1) Interrupt Source Identity Register

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5

Reserved

4 3 2

25

17

9

1

INTSRC[2:0]

Reset Value

0xXXXX_XXXX

24

16

8

0

Bits

[31:3]

Description

Reserved

[2:0] INTSRC


Bit2: 0

Bit1: 0

Bit0: UART1 INT

- 83 -


Revision 2.4


Register

IRQ12(UART0) Interrupt Source Identify Register (IRQ12_SRC)


INT_BA+0x30 R IRQ12 (UART0) Interrupt Source Identity Register IRQ12_SRC

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5

Reserved

4 3 2

25

17

9

1

INT_SRC[2:0]

Reset Value

0xXXXX_XXXX

24

16

8

0


[2:0] INT_SRC


Bit2: 0

Bit1: 0

Bit0: UART0_INT

- 84 -


Revision 2.4


IRQ13(SPI1) Interrupt Source Identify Register (IRQ13_SRC)


IRQ13_SRC INT_BA+0x34 R IRQ13 (SPI1) Interrupt Source Identity Register

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5

Reserved

4 3 2

25

17

9

1

INT_SRC[2:0]

Reset Value

0xXXXX_XXXX

24

16

8

0

Bits

[31:3]

Description

Reserved

[2:0] INT_SRC


Bit2: 0

Bit1: 0

Bit0: SPI1 INT

- 85 -


Revision 2.4


Register

IRQ14(SPI0) Interrupt Source Identify Register (IRQ14_SRC)


INT_BA+0x38 R IRQ14 (SPI0) Interrupt Source Identity Register IRQ14_SRC

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5

Reserved

4 3 2


25

17

9

1

INT_SRC[2:0]

Reset Value

0xXXXX_XXXX

24

16

8

0

[2:0] INT_SRC


Bit2: 0

Bit1: 0

Bit0: SPI0_INT

- 86 -


Revision 2.4


IRQ15(DPWM) Interrupt Source Identify Register (IRQ15_SRC)


IRQ15_SRC INT_BA+0x3C R IRQ15 (DPWM) Interrupt Source Identity Register

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5

Reserved

4 3 2

25

17

9

1

INT_SRC[2:0]

Reset Value

0xXXXX_XXXX

24

16

8

0

Bits

[31:3]

Description

Reserved

[2:0] INT_SRC


Bit2: 0

Bit1:

Bit0: DPWM INT

- 87 -


Revision 2.4


Register

IRQ18(I2C0) Interrupt Source Identify Register (IRQ18_SRC)


INT_BA+0x48 R IRQ18 (I2C0) Interrupt Source Identity Register IRQ18_SRC

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5

Reserved

4 3 2


[2:0] INT_SRC


Bit2: 0

Bit1: 0

Bit0: I2C0_INT

25

17

9

1

INT_SRC[2:0]

Reset Value

0xXXXX_XXXX

24

16

8

0

- 88 -


Revision 2.4


Register

IRQ21(CMP) Interrupt Source Identify Register (IRQ21_SRC)


INT_BA+0x54 R IRQ21 (CMP) Interrupt Source Identity Register IRQ21_SRC

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5

Reserved

4 3 2


25

17

9

1

INT_SRC[2:0]

Reset Value

0xXXXX_XXXX

24

16

8

0

[2:0] INT_SRC


Bit2: 0

Bit1: 0

Bit0: CMP INT

- 89 -


Revision 2.4


IRQ22(MAC) Interrupt Source Identify Register (IRQ22_SRC)


IRQ22_SRC INT_BA+0x58 R IRQ22 (MAC ) Interrupt Source Identity Register

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5

Reserved

4 3 2

25

17

9

1

INT_SRC[2:0]

Reset Value

0xXXXX_XXXX

24

16

8

0

Bits

[31:3]

Description

Reserved

[2:0] INT_SRC


Bit2: 0

Bit1: 0

Bit0: MAC INT

- 90 -


Revision 2.4


Register

IRQ25(SARADC) Interrupt Source Identify Register (IRQ25_SRC)


INT_BA+0x64 R IRQ25 (SARADC) Interrupt Source Identity Register IRQ25_SRC

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5

Reserved

4 3 2

25

17

9

1

INT_SRC[2:0]

Reset Value

0xXXXX_XXXX

24

16

8

0


[2:0] INT_SRC


Bit2: 0

Bit1: 0

Bit0: SARADC INT

- 91 -


Revision 2.4


Register

IRQ26(PDMA) Interrupt Source Identify Register (IRQ26_SRC)


INT_BA+0x68 R IRQ26 (PDMA) Interrupt Source Identity Register IRQ26_SRC

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5

Reserved

4 3 2

25

17

9

1

INT_SRC[2:0]

Reset Value

0xXXXX_XXXX

24

16

8

0


[2:0] INT_SRC


Bit2: 0

Bit1: 0

Bit0: PDMA_INT

- 92 -


Revision 2.4


Register

IRQ27(I2S0) Interrupt Source Identify Register (IRQ27_SRC)


INT_BA+0x6C R IRQ27 (I2S0) Interrupt Source Identity Register IRQ27_SRC

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5

Reserved

4 3 2


[2:0] INT_SRC


Bit2: 0

Bit1: 0

Bit0: I2S_INT

25

17

9

1

INT_SRC[2:0]

Reset Value

0xXXXX_XXXX

24

16

8

0

- 93 -


Revision 2.4


Register

IRQ28(CAPS) Interrupt Source Identify Register (IRQ28_SRC)


INT_BA+0x70 R IRQ28 (CAPS) Interrupt Source Identity Register IRQ28_SRC

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5

Reserved

4 3 2

25

17

9

1

INT_SRC[2:0]

Reset Value

0xXXXX_XXXX

24

16

8

0


[2:0] INT_SRC


Bit2: 0

Bit1: 0

Bit0: CAPS_INT

- 94 -


Revision 2.4


Register

IRQ29(ADC) Interrupt Source Identify Register (IRQ29_SRC)


INT_BA+0x74 R IRQ29 (ADC) Interrupt Source Identity Register IRQ29_SRC

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5

Reserved

4 3 2


[2:0] INT_SRC


Bit2: 0

Bit1: 0

Bit0: ADC_INT

25

17

9

1

INT_SRC[2:0]

Reset Value

0xXXXX_XXXX

24

16

8

0

- 95 -


Revision 2.4


Register

IRQ31(RTC) Interrupt Source Identify Register (IRQ31_SRC)


INT_BA+0x7C R IRQ31 (RTC) Interrupt Source Identity Register IRQ31_SRC

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5

Reserved

4 3 2


[2:0] INT_SRC


Bit2: 0

Bit1: 0

Bit0: RTC_INT

25

17

9

1

INT_SRC[2:0]

Reset Value

0xXXXX_XXXX

24

16

8

0

- 96 -


Revision 2.4


Register

NMI Interrupt Source Select Control Register (NMI_SEL)


INT_BA+0x80 R/W NMI Source Interrupt Select Control Register NMI_SEL

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7

IRQ_TM

6

Reserved

5 4 3 2

NMI_SEL[4:0]

Description Bits

[31:7] Reserved Reserved

[7]

[4:0]

IRQ_TM

NMI_SEL

25

17

9

1

Reset Value

0x0000_0000

24

16

8

0

IRQ Test Mode

If set to 1 then peripheral IRQ signals (0-31) are replaced by the value in the

MCU_IRQ register. This is a protected register to program first issue the unlock sequence.

NMI Source Interrupt Select

The NMI interrupt to Cortex-M0 can be selected from one of the interrupt[31:0]

The NMI_SEL bit[4:0] used to select the NMI interrupt source

- 97 -


Revision 2.4


Register

MCU Interrupt Request Source Test Mode Register (MCU_IRQ)


MCU_IRQ INT_BA+0x84 R/W MCU IRQ Number Identify Register

31

RTC

23

Reserved

15

DPWM

30

Reserved

22

MAC

14

SPI0

7 6

Reserved PWM0

29

SDADC

21

CMP

13

SPI1

5

ALC

28

CAPS

20

27

I2S0

19

Reserved Reserved

12 11

UART0 UART1

4

GPAB

3

EINT1

26

PDMA

18

I2C0

10

Reserved

2

EINT0


[31]

[30]

[29]

[28]

[27]

[26]

[25]

RTC

Reserved

SDADC

CAPS

I2S

PDMA

SARADC

Reset Value

0x0000_0000

25

SARADC

17

24

Reserved

16

Reserved Reserved

9 8

TMR1 TMR0

1

WDT

IRQ31 (RTC) Interrupt Source Identity Register

0: No effect.

1: clear the interrupt

IRQ30 (RESERVED) Interrupt Source Identity Register

IRQ29 (SDADC) Interrupt Source Identity Register

0: No effect.


IRQ28 (CAPS) Interrupt Source Identity Register

0: No effect.


IRQ27 (I2S0) Interrupt Source Identity Register

0: No effect.


IRQ26 (PDMA) Interrupt Source Identity Register

0: No effect.


IRQ25 (SARADC) Interrupt Source Identity Register

0: No effect.


0

BOD

- 98 -


Revision 2.4

[13]

[12]

[11]

[10]

[9]

[18]

[17]

[16]

[15]

[21]

[20]

[19]

[14]

[24]

[23]

[22]

Reserved

Reserved

MAC

CMP

Reserved

Reserved

I2C

Reserved

Reserved

DPWM

SPI0

SPI1

UART0

UART1

Reserved

TMR1




IRQ22 (MAC ) Interrupt Source Identity Register

0: No effect.


IRQ21 (CMP) Interrupt Source Identity Register

0: No effect.




IRQ18 (I2C0) Interrupt Source Identity Register

0: No effect.




IRQ15 (DPWM) Interrupt Source Identity Register

0: No effect.



0: No effect.



0: No effect.



0: No effect.



0: No effect.



RQ9 (TMR1) Interrupt Source Identity Register

0: No effect.


- 99 -


Revision 2.4

[5]

[4]

[8]

[7]

[6]

[3]

[2]

[1]

[0]

TMR0

Reserved

PWM

ALC

GPAB

EINT1

EINT0

WDT

BOD



0: No effect.



IRQ6 (PWM0) Interrupt Source Identity Register

0: No effect.


IRQ5 (ALC) Interrupt Source Identity Register

0: No effect.


IRQ4 (GPA/B) Interrupt Source Identity Register

0: No effect.



0: No effect.



0: No effect.


IRQ1 (WDT) Interrupt Source Identity Register

0: No effect.


IRQ0 (BOD) Interrupt Source Identity Register

0: No effect.


- 100 -


Revision 2.4


5.2.8 System Control Registers

Key control and status features of Coterx-M0 are managed centrally in a System Control Block within the System Control Registers.

For more detailed information, please refer to the documents “ARM® Cortex™-M0 Technical

Reference Manual” and “ARM® v6-M Architecture Reference Manual” .


Register Offset

SYSINFO Base Address:

SYSINFO_BA = 0xE000_ED00

SYSINFO_CPUID SYSINFO_BA+0x000

SYSINFO_ICSR SYSINFO_BA+0x004

SYSINFO_AIRCTL SYSINFO_BA+0x00C

SYSINFO_SCR SYSINFO_BA+0x010

R/W Description Reset Value

R CPUID Base Register 0x410C_C200

R/W Interrupt Control State Register 0x0000_0000

R/W Application Interrupt and Reset Control Register 0xFA05_0000

R/W System Control Register 0x0000_0000

SYSINFO_SHPR2 SYSINFO_BA+0x01C R/W System Handler Priority Register 2 0x0000_0000

SYSINFO_SHPR3 SYSINFO_BA+0x020 R/W System Handler Priority Register 3 0x0000_0000


SYSINFO_ is the prefix, SYSINFO_SHPR3 will be SYSINFO->SHPR3

- 101 -


Revision 2.4


CPUID Base Register (SYSINFO_CPUID)


SYSINFO_CPUID SYSINFO_BA+0x000 R CPUID Base Register

31 30 29

23 22 21

28

IMPCODE

27

20 19

Reserved

15

7

14 13 12 11

PARTNO[11:4]

4 3 6

PARTNO[3:0]

5


[31:24]

[23:20]

[19:16]

[15:4]

[3:0]

IMPCODE

Reserved

PART

PARTNO

REVISION

Implementer Code Assigned by ARM

ARM = 0x41.

Reserved.

ARMv6-m Parts

Reads as 0xC for ARMv6-M parts

Part Number

Reads as 0xC20.

Revision

Reads as 0x0

26

18

10

2

PART

REVISION

25

17

9

1

Reset Value

0x410C_C200

24

16

8

0

- 102 -


Revision 2.4


Interrupt Control State Register (SYSINFO_ICSR)


SYSINFO_ICSR SYSINFO_BA+0x004 R/W Interrupt Control State Register

31

NMIPNSET

23

ISRPREEM

15

7

30 29

14

Reserved

22

ISRPEND

21

Reserved

13

6

VTPEND[3:0]

5

28

PPSVISET

20

12

4

27 26 25

PPSVICLR PSTKISET PSTKICLR

19 17 18

VTPNDING[8:4]

11 9

3

10

Reserved

2 1

VTACT[7:0]

Reset Value

0x0000_0000

24

Reserved

16

8

VTACT[8]

0


[31]

[20:29]

[28]

[27]

[26]

[25]

[23]

[22]

[21]

[20:12]

[11:9]

NMIPNSET

Reserved

PPSVISET

PPSVICLR

PSTKISET

PSTKICLR

ISRPREEM

ISRPEND

Reserved

VTPEND

Reserved

NMI Pending Set Control

Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. Reads back with current state (1 if Pending, 0 if not).

Set a Pending PendSV Interrupt

This is normally used to request a context switch. Reads back with current state (1 if Pending,

0 if not).

Clear a Pending PendSV Interrupt

Write 1 to clear a pending PendSV interrupt.

Set a Pending SYST

Reads back with current state (1 if Pending, 0 if not).

Clear a Pending SYST

Write 1 to clear a pending SYST.

ISR Preemptive

If set, a pending exception will be serviced on exit from the debug halt state.

ISR Pending

Indicates if an external configurable (NVIC generated) interrupt is pending.

Vector Pending

Indicates the exception number for the highest priority pending exception. The pending state includes the effect of memory-mapped enable and mask registers. It does not include the

PRIMASK special-purpose register qualifier. A value of zero indicates no pending exceptions.

- 103 -


Revision 2.4

[8:0] VTACT


Vector Active

0: Thread mode

Value > 1: the exception number for the current executing exception.

- 104 -


Revision 2.4


Application Interrupt and Reset Control Register (SYSINFO_AIRCTL)


SYSINFO_AIRCTL SYSINFO_BA+0x00C R/W Application Interrupt and Reset Control Register

31

23

15

ENDIANES

7

30

22

14

6

29

21

13

5

Reserved

28 27

VTKEY

20 19

12

4

VTKEY

11

Reserved

3

26

18

10

2

SRSTREQ

25

17

9

1

CLRACTVT

Reset Value

0xFA05_0000

24

16

8

0

Reserved


[31:16]

[15]

[14:3]

[2]

[1]

VTKEY

ENDIANES

Reserved

SRSTREQ

CLRACTVT

Reserved

Vector Key

The value 0x05FA must be written to this register, otherwise a write to register is UNPREDICTABLE.

Endianness

Read Only. Reads 0 indicating little endian machine.

System Reset Request

0 = do not request a reset.

1 = request reset.

Writing 1 to this bit asserts a signal to request a reset by the external system.

Clear All Active Vector

Clears all active state information for fixed and configurable exceptions.

0= do not clear state information.

1= clear state information.

The effect of writing a 1 to this bit if the processor is not halted in Debug, is

UNPREDICTABLE.

[0]

- 105 -


Revision 2.4


System Control Register (SYSINFO_SCR)


SYSINFO_SCR SYSINFO_BA+0x010 R/W System Control Register

31

23

15

7

30

22

14

6

Reserved

29

21

13

5

28 27

Reserved

20 19

Reserved

12 11

Reserved

4 3

SEVNONPN Reserved

26

18

10

25

17

9

Reset Value

0x0000_0000

24

16

8

2 1 0

SLPDEEP SLPONEXC Reserved

Bits

[31:5]

Description

Reserved

[4]

[2]

[1]

SEVNONPN

SLPDEEP

SLPONEXC

Reserved

Send Event on Pending Bit

0 = only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded.

1 = enabled events and all interrupts, including disabled interrupts, can wake-up the processor.

When enabled, interrupt transitions from Inactive to Pending are included in the list of wakeup events for the WFE instruction.

When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.

The processor also wakes up on execution of an SEV instruction.

Controls Whether the Processor Uses Sleep or Deep Sleep As Its Low Power

Mode

0 = sleep.

1 = deep sleep.

The SLPDEEP flag is also used in conjunction with CLK_PWRCTL register to enter deeper power-down states than purely core sleep states.

Sleep on Exception

When set to 1, the core can enter a sleep state on an exception return to Thread mode. This is the mode and exception level entered at reset, the base level of execution. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.

[0]

- 106 -


Revision 2.4


System Handler Priority Register2 (SYSINFO_SHPR2)


SYSINFO_SHPR2 SYSINFO_BA+0x01C R/W System Handler Priority Register 2

31 30 29 28 27 26

PRI11 Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5 4 3 2

Reserved


[31:30] PRI11

Reserved

25

17

9

1

Priority of System Handler 11 – SVCall


[29:0]

Reset Value

0x0000_0000

24

16

8

0

- 107 -


Revision 2.4


System Handler Priority Register3 (SYSINFO_SHPR3)


SYSINFO_SHPR3 SYSINFO_BA+0x020 R/W System Handler Priority Register 3

31 30 29 28 27 26

PRI15 Reserved

23 22 21 20 19 18

PRI14 Reserved

15 14 13 12 11 10

Reserved

7 6 5 4 3 2

Reserved


[31:30]

[29:24]

[23:22]

PRI15

Reserved

PRI14

Reserved

25

17

9

1

Priority of System Handler 15 – SYST


Priority of System Handler 14 – PendSV


[21:0]

Reset Value

0x0000_0000

24

16

8

0

- 108 -


Revision 2.4


5.3 Clock Controller and Power Management Unit (PMU)

The clock controller generates the clock sources for the whole device, including all AMBA interface modules and all peripheral clocks. Clock gating is provided on all peripheral clocks to minimize power consumption. The Power Management Unit (PMU) implements power control functions which can place the device into various power saving modes. The device will enter these various modes by requesting a power mode then requesting the Cortex-M0 to execute the WFI or the WFE instruction.

5.3.1 Clock Generator

The clock generator consists of 4 sources listed below:

•

An internal programmable high frequency oscillator (HIRC) factory trimmed to provide frequencies of 49.152MHz and 32.768MHz to 1% accuracy.

•

An external 32kHz crystal oscillator (LXT)

•

An internal low power 10 kHz oscillator (LIRC)

•

An external 12MHz crystal oscillator (HXT)

CLK_PWRCTL.HXTEN

XI12M

HXT

HXT

(CLK12M)

XO12M

CLK_PWRCTL.LXTEN

XI32K

XTL32K

XO32K

CLK_CLKSEL0.HIRCFSEL

CLK_PWRCTL.HIRCEN

LXT

(CLK32K)

HIRC

HIRC

(49.152MHz)

SYSCLK->PWRCTL.LIRCEN

LIRC

LIRC

CLK10K

Figure 5-3 Clock generator block diagram

- 109 -


Revision 2.4


5.3.2 System Clock & SysTick Clock

The system clock has 4 clock sources from clock generator block. The clock source switch depends on the register HCLKSEL (CLK_CLKSEL0[2:0]). The clock is then divided by HCLKDIV+1 to produce the master clock for the device.

Figure 5-4 System Clock Block Diagram

The SysTick clock (STCLK) has five clock sources. The clock source switch depends on the setting of the register STCLKSEL (CLK_CLKSEL0[5:3]).

Figure 5-5 SysTick Clock Control Block Diagram

- 110 -


Revision 2.4


5.3.3 Peripheral Clocks

Each peripheral has a selectable clock gate. The register CLK_APBCLK0 determines whether the clock is active for each peripheral. In addition, the CLK_SLEEPCTL register determines whether these clocks remain on during M0 sleep mode. Certain peripheral clocks have selectable sources these are controlled by the CLK_CLKSEL1 & CLK_CLKSEL2 register.

5.3.4 Power Management

The ISD91200 is equipped with a Power Management Unit (PMU) that implements a variety of power saving modes. There are five levels of power control with increasing functionality (and power consumption):

•

Level0 : Deep Power Down (DPD)

•

Level1 : Standby Power Down (SPD)

•

Level2: STOP

•

Level3 : Deep Sleep

•

Level4 : Sleep

•

Level5 : Normal Operation

Within each of these levels there are further options to optimize power consumption.

5.3.4.1 Level0: Deep Power Down (DPD)

Deep Power Down (DPD) is the lowest power state the device can obtain. In this state there is no power provided to the logic domain and power consumption is only from the higher voltage chip supply domain. All logic state in the Cortex-M0 is lost as is contents of all RAM. All IO pins of the device are in a high impedance state. On a release from DPD the Cortex-M0 boots as if from a power-on reset.

There are certain registers that can be interrogated to allow software to determine that previous state was a DPD state.

In DPD there are three ways to wake up the device:

1. A high to low transition on the WAKEUP pin.

2. A timed wakeup where the LIRC is configured active and reaches a certain count.

3. A power cycle of main chip supply triggering a POR event.

To assist software in determining previous state of device before a DPD, a one-byte register is available CLK_DPDSTATE [7:0] that can be loaded with a value to be preserved before issuing a DPD request.

To configure the device for DPD the user sets the following options:

•

CLK_PWRCTL.WKPINEN: If set to ‘1’ then the WAKEUP pin is disabled and will not wake up the chip.

•

CLK_PWRCTL.LIRCDPDEN: If set to ‘1’ then the LIRC will power down in DPD. No timed wakeup is possible.

•

CLK_WAKE10K.SELWKTMR: Each bit in this register will trigger a wakeup event after a certain number of LIRC cycles.

When a WAKEUP event occurs the PMU will start the Cortex-M0 processor and execute the reset vector. The condition that generated the WAKEUP event can be interrogated by reading the registers

CLK_PWRCTL.WKPINWKF, CLK_PWRCTL.TMRWKF and CLK_PWRCTL.PORWKF.

To enter the DPD state the user must set the register bit CLK_PWRCTL.DPDEN then execute a WFI or WFE instruction. Note that when debug interface is active, device will not enter DPD. Also once device enters DPD the debug interface will be inactive. It is possible that user could write code that makes it impossible to activate the debug interface and reprogram device, for instance if device re-

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Revision 2.4

ISD91200 Series Technical Reference Manual enters DPD mode with insufficient time to allow an ICE tool to activate the SWD debug port. Especially during development it is recommended that some checks are placed in the boot sequence to prevent device going to power down. A register bit, CLK_DBGPD.DISPDREQ is included for this purpose that will disable power down features. A check such as: void Reset_Handler(void){

/* check ICE_CLK and ICE_DAT to disable power down to the chip */ if (CLK_DBGPD.ICECLKST == 0 && CLK_DBGPD.ICEDATST == 0)

CLK_DBGPD.DISPDREQ = 1;

}

__main();

Can check the SWD pin state on boot and prevent power down from occurring.

5.3.4.2 Level1: Standby Power Down (SPD) mode.

Standby Power Down mode is the lowest power state that some logic operation can be performed. In this mode power is removed from the majority of the core logic, including the Cortex-M0 and main

RAM. A low power standby reference is enabled however that supplies power to a subset of logic including the IO ring, GPIO control, RTC module, 32kHz Crystal Oscillator, Brownout Detector and a

256Byte Standby RAM.

In Standby mode there are three ways to wake up the device:

1. An interrupt from the GPIO block, for instance a pin transition.

2. An interrupt from the RTC module, for instance an alarm or timer event.


When a wake up event occurs the PMU will start the Cortex-M0 processor and execute the reset vector. Software can determine whether the device woke up from SPD by interrogating the register bit

CLK_PWRSTSF.SPDF.

To enter the SPD state the user must set the register bit CLK_PWRCTL.SPDEN then execute a WFI or WFE instruction. Note that when debug interface is active, device will not enter SPD. Also once device enters SPD the debug interface will be inactive.

5.3.4.3 Level2:STOP mode (special characteristic).

STOP mode is the lowest power state that some logic operation can be performed with full SRAM retention. In this mode power is removed from the majority of the core logic, including the Cortex-M0.

A low power standby reference is enabled however that supplies power to a subset of logic including the IO ring, GPIO control, RTC module, LXT 32kHz Crystal Oscillator (if enabled), Brownout Detector,

LIRC 10kHz Oscillator, and SRAM.

In STOP mode there are three ways to wake up the device:

4. An interrupt from the GPIO block, for instance a pin transition.

5. An interrupt from the RTC module, for instance an alarm or timer event.


When a wake up event occurs the PMU will start the Cortex-M0 processor and execute the next instrument. Software can determine whether the device woke up from STOP by interrogating the register bit CLK_PWRSTSF.STOPF.

To enter the STOP state the user must set the register bit CLK_PWRCTL.STOPEN then execute a

WFI or WFE instruction. Note that when debug interface is active, device will not enter STOP. Also once device enters STOP the debug interface will be inactive.

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Revision 2.4


5.3.4.4 Level3: Deep Sleep mode.

The Deep Sleep mode is the lowest power state where the Cortex-M0 and all logic state are preserved. In Deep Sleep mode the HIRC oscillator is shut down and a low speed oscillator is selected, if LXT is active this source is selected, if not then LIRC is enabled and selected. All clocks to the Cortex-M0 core are gated eliminating dynamic power in the core. Clocks to peripheral are gated according to the CLK_SLEEPCTL register, note however that HCLK is operating at a low frequency and HIRC is not available. Deep Sleep mode is entered by setting System Control register bit 2:

SYSINFO_SCR |= (1UL << 2) and executing a WFI/WFE instruction. Software can determine whether the device woke up from Deep Sleep by interrogating the register bit CLK_PWRSTSF.DSF.

5.3.4.5 Level4: Sleep mode.

The Sleep mode gates all clocks to the Cortex-M0 eliminating dynamic power in the core. In addition, clocks to peripherals are gated according to the CLK_SLEEPCTL register. The mode is entered by executing a WFI/WFE instruction and is released when an event occurs. Peripheral functions, including PDMA can be continued while in Sleep mode. Using this mode power consumption can be minimized while waiting for events such as a PDMA operation collecting data from the ADC, once

PDMA has finished the core can be woken up to process the data

5.3.5 Register Map

R: read only, W: write only, R/W: both read and write


CLK Base Address:

CLK_BA = 0x5000_0200

CLK_PWRCTL CLK_BA + 0x00 R/W System Power Control Register

CLK_AHBCLK CLK_BA + 0x04 R/W AHB Device Clock Enable Control Register

Reset Value

CLK_APBCLK0 CLK_BA + 0x08 R/W

CLK_DPDSTATE CLK_BA + 0x0C R/W

CLK_CLKSEL0

CLK_CLKSEL1

CLK_CLKDIV0

CLK_BA + 0x10

CLK_BA + 0x14

R/W

R/W

CLK_CLKSEL2

CLK_SLEEPCTL

CLK_BA + 0x18 R/W

CLK_BA + 0x1C R/W

CLK_BA + 0x20 R/W

CLK_PWRSTSF

CLK_DBGPD

CLK_BA + 0x24

CLK_BA + 0x28

R/W

R/W

APB Device Clock Enable Control Register

Deep Power Down State Register

Clock Source Select Control Register 0


Clock Divider Number Register


Sleep Clock Source Select Register

Power State Flag Register

Debug Port Power Down Disable Register

0xXX00_000D

0x0000_0005

0x0000_0001

0x0000_XX00

0x0000_0038

0xF000_7703

0x0000_1010

0x0000_0000

0xFFFF_FFFF

0x0000_0000

0x0000_00XX

CLK_WAKE10K CLK_BA + 0x2C R/W Deep Power Down 10K Wakeup Timer 0x0000_0001

Note: In BSP register structure, the prefix is structure name, and register be no prefix, for example

CLK_ is the prefix, CLK_WAKE10K will be CLK->WAKE10K

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Revision 2.4


5.3.6 Register Description

System Power Control Register （ CLK_PWRCTL ）

This is a protected register, to write to register, first issue the unlock sequence.


CLK_PWRCTL CLK_BA + 0x00 R/W System Power Control Register 0xXX00_000D

Table 5-36 System Power Control Register （ CLK_PWRCTL, address 0x5000_0200 ）

31 28

23

15

Reserved

7

30 29

Reserved

22

6

Reserved

21

Reserved

14 13

IOSTATE RELEASEIO

5

20

12

HOLDIO

4

HXTEN

27

WKPUEN

19

26

PORWKF

18

FLASHEN

11

DPDEN

10

SPDEN

3

LIRCEN

2

HIRCEN

25 24

TMRWKF WKPINWKF

17 16

LIRCDPDEN WKPINEN

9 8

STOPEN Reserved

1

LXTEN

0

Reserved

Table 5-37 System Power Control Register (CLK_PWRCTL, address 0x5000_0200) Bit Description.

Bits

[31:27]

Description

Reserved

[27]

[26]

[25]

[24]

[23:20]

WKPUEN

PORWKF

TMRWKF

WKPINWKF

Reserved

Reserved.

Wakeup Pin Pull-up Control

This signal is latched in deep power down and preserved.

0 = pull-up enable.

1 = tri-state (default).

POR Wakeup Flag

Read Only. This flag indicates that wakeup of device was requested with a power-on reset. Flag is cleared when DPD mode is entered.

Timer Wakeup Flag

Read Only. This flag indicates that wakeup of device was requested with TIMER count of the 10khz oscillator. Flag is cleared when DPD mode is entered.

Pin Wakeup Flag

Read Only. This flag indicates that wakeup of device was requested with a high to low transition of the WAKEUP pin. Flag is cleared when DPD mode is entered.

Reserved

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Revision 2.4

[3]

[2]

[16]

[15]

[14]

[13]

[12]

[11]

[10]

[9]

[8:5]

[4]

[1]

[0]

[19:18]

[17]

FLASHEN

LIRCDPDEN

WKPINEN

Reserved

IOSTATE

RELEASEIO

HOLDIO

DPDEN

SPDEN

STOPEN

Reserved

HXTEN

LIRCEN

HIRCEN

LXTEN

Reserved


Flash ROM Control Enable/Disable

Bit [19]: for Stop mode operation

Bit [18]: for Sleep mode operation

1: Turn off flash

0: Normal

Note: It takes 10us to turn on the flash to normal

OSC10k Enabled Control

Determines whether OSC10k is enabled in DPD mode. If OSC10k is disabled, device cannot wake from DPD with SELWKTMR delay.

0 = enabled.

1 = disabled.

Wakeup Pin Enabled Control

Determines whether WAKEUP pin is enabled in DPD mode.

0 = enabled.

1 = disabled.

Reserved.

‘1’: IO held from SPD ‘0’: IO released.

Write ‘1’ to this bit to release IO state after exiting SPD if hold request was made with the HOLD_IO bit.

When entering SPD mode, IO state is automatically held If this bit is set to ‘1’ then this sate upon resuming full power mode will be hold until the RELEASE_IO bit is written ‘1’

Deep Power Down (DPD) Bit

Set to ‘1’ and issue WFI/WFE instruction to enter DPD mode.

Standby Power Down (SPD) Bit

Set to ‘1’ and issue WFI/WFE instruction to enter SPD mode.

Stop

Set to ‘1’ and issue WFI/WFE instruction to enter STOP mode.

Reserved.

HXT Oscillator Enable Bit

0 = disable (default).

1 = enable.

LIRC Oscillator Enable Bit

0 = disable.

1 = enable (default).

HIRC Oscillator Enable Bit

0 = disable.

1 = enable (default).

External 32.768 KHz Crystal Enable Bit

0 = disable (default).

1 = enable.

Reserved.

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Revision 2.4


AHB Device Clock Enable Control Register （ CLK_AHBCLK ）

These register bits are used to enable/disable the clock source for AHB (Advanced High-Performance

Bus) blocks. This is a protected register, to write to register, first issue the unlock sequence .


0x0000_0005 CLK_AHBCLK CLK_BA + 0x04 R/W AHB Device Clock Enable Control Register

7 6 5

Reserved

4 3 2 1 0

ISPCKEN PDMACKEN HCLKEN

Bits

[31:3]

[2]

[1]

[0]

Table 5-38 AHB Device Clock Enable Register (CLK_AHBCLK, address 0x5000_0204) Bit

Description.

Description

Reserved

ISPCKEN

PDMACKEN

HCLKEN

Reserved.

Flash ISP Controller Clock Enable Control

0 = To disable the Flash ISP engine clock.

1 = To enable the Flash ISP engine clock.

PDMA Controller Clock Enable Control

0 = To disable the PDMA engine clock.

1 = To enable the PDMA engine clock.

CPU Clock Enable (HCLK)

Must be left as 1 for normal operation.

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Revision 2.4


APB Device Clock Enable Control Register （ CLK_APBCLK0 ）

These register bits are used to enable/disable clocks for APB (Advanced Peripheral Bus) peripherals.

To enable the clocks write ‘1’ to the appropriate bit. To reduce power consumption and disable the peripheral, write ‘0’ to the appropriate bit.


CLK_APBCLK0 CLK_BA + 0x08 R/W APB Device Clock Enable Control Register

Reset Value

0x0000_0001

31

Reserved

23

30

ANACKEN

22

29 28

I2S0CKEN SDADCCKEN

21 20

27

Reserved

26

Reserved

25 24

19 18 17 16

Reserved PWM0CH23C

KEN

13

PWM0CH01C

KEN

12

Reserved

15 14 11

UART1CKEN Reserved DPWMCKEN SPI0CKEN SPI1CKEN

BIQALCKEN SARADCKEN UART0CKEN

10

Reserved

9 8

I2C0CKEN

4 3 2 1 7 6 5

TMR1CKEN TMR0CKEN RTCCKEN

0

WDTCKEN

Table 5-39 APB Device Clock Enable Control Register (CLK_APBCLK0, address 0x5000_0208) Bit

Description.

Bits

[31]

Description

Reserved

[30]

[29]

[28]

[27:22]

[21]

[20]

[19]

ANACKEN

I2S0CKEN

SDADCCKEN

Reserved

PWM0CH23CKEN

PWM0CH01CKEN

Reserved

Analog Block Clock Enable Control

0=Disable.

1=Enable.

I2S Clock Enable Control

0=Disable.

1=Enable.

Delta-Sigma Analog-digital-converter (ADC) Enable Control

0=Disable.

1=Enable.

PWM0CH2 and PWM0CH3 Block Clock Enable Control

0=Disable.

1=Enable.

PWM0CH0 and PWM0CH1 Block Clock Enable Control

0=Disable.

1=Enable.

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Revision 2.4

[16]

[15]

[14]

[13]

[12]

[18]

[17]

[7]

[6]

[11]

[10:9]

[8]

[5]

[4:1]

[0]


BIQALCKEN

SARADCKEN

UART0CKEN

UART1CKEN

Reserved

DPWMCKEN

SPI0CKEN

SPI1CKEN

Reserved

I2C0CKEN

TMR1CKEN

TMR0CKEN

RTCCKEN

Reserved

WDTCKEN

BIQ and ALC Clock Enable Control

0=Disable.

1=Enable.

SAR Analog-digital-converter (ADC) Clock Enable Control

0=Disable.

1=Enable.

UART0 Clock Enable Control

0=Disable.

1=Enable.

UART1 Clock Enable Control

0=Disable.

1=Enable.

Differential PWM Speaker Driver Clock Enable Control

0=Disable.

1=Enable.

SPI0 Clock Enable Control

0=Disable.

1=Enable.

SPI1 Clock Enable Control

0=Disable

1=Enable

I2C0 Clock Enable Control

0=Disable.

1=Enable.

Timer1 Clock Enable Control

0=Disable.

1=Enable.

Timer0 Clock Enable Control

0=Disable.

1=Enable.

Real-time-clock APB Interface Clock Control

0=Disable.

1=Enable.

Watchdog Clock Enable Control

0=Disable.

1=Enable.

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Revision 2.4


DPD State Register （ CLK_DPDSTATE ）

The Deep Power Down State register is a user settable register that is preserved during Deep Power

Down (DPD). Software can use this register to store a single byte during a DPD event. The

DPDSTSRD register reads back the current state of the CLK_DPDSTATE register. To write to this register, set desired value in the DPDSTSWR register, this value will be latched in to the

CLK_DPDSTATE register on next DPD event.


R/W Deep Power Down State Register

Reset Value

0x0000_XX00 CLK_DPDSTATE CLK_BA + 0x0C

31 30 29 26 25 24

23

15

7

22

14

6

21

13

5

28 27

Reserved

20 19

Reserved

12

DPDSTSRD

11

4

DPDSTSWR

3

18

10

2

17

9

1

16

8

0

Table 5-40 DPD State Register (CLK_DPDSTATE, address 0x5000_020C) Bit Description.

Bits

[31:16]

Description

Reserved

[15:8]

[7:0]

DPDSTSRD

DPDSTSWR

DPD State Read Back

Read back of CLK_DPDSTATE register. This register was preserved from last DPD event .

DPD State Write Register

Read back of CLK_DPDSTATE register. This register was preserved from last DPD event .

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Revision 2.4


Clock Source Select Control Register 0 （ CLK_CLKSEL0 ）


CLK_CLKSEL0 CLK_BA + 0x10 R/W Clock Source Select Control Register 0

7

HIRCFSEL

6 5 4

STCLKSEL

3 2

Bits

[31:6]

[7:6]

[5:3]

[2:0]

1

HCLKSEL

Reset Value

0x0000_0038

0

Table 5-41 Clock Source Select Register 0 (CLK_CLKSEL0, address 0x5000_0210

Description

Reserved

HIRCFSEL

STCLKSEL

HCLKSEL

High Frequency RC Oscilltor Frequency Select Register.

These bits are protected, to write to bits first perform the unlock sequence.

00 = Trim for 49.152MHz selected.

01 = Trim for 32.768MHz selected.

10 = Trim for reserved.

MCU Cortex_M0 SYST Clock Source Select


000 = clock source from LIRC.

001 = clock source from LXT.

010 = clock source from LIRC divided by 2.

011 = clock source from HIRC divided by 2.

1xx = clock source from HCLK÷2 (Default).

Note that to use STCLKSEL as source of SysTic timer the CLKSRC bit of

SYST_CSR must be set to 0.

HCLK Clock Source Select

Ensure that related clock sources (pre-select and new-select) are enabled before updating register.


000 = clock source from HIRC. (deafult)



011 = clock source from HXT.

Others = Reserved.

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Revision 2.4



Clock multiplexors are a glitch free design to ensure smooth transitions between asynchronous clock sources. As such, both the current clock source and the target clock source must be enabled for switching to occur. Beware when switching from a low speed clock to a high speed clock that low speed clock remains on for at least one period before disabling.


CLK_CLKSEL1 CLK_BA + 0x14 R/W Clock Source Select Control Register 1

31 30

PWM0CH23SEL

23 22

15

Reserved

7

Reserved

14

6

29 28

PWM0CH01SEL

21 20

27

19

Reserved

26

18

13

TMR1SEL

5

DPWMSEL

12

4

Reserved

11

Reserved

3

ADCSEL

10

2

Reset Value

0xF000_7703

25 24

SARADCSEL

17 16

9

TMR0SEL

1

WDTSEL

8

0

Table 5-42 Clock Source Select Register 1 (CLK_CLKSEL1, address 0x5000_0214)


[31:30]

[29:28]

[27:26]

[25:24]

[23:15]

PWM0CH23SEL

PWM0CH01SEL

Reserved

SARADCSEL

Reserved

PWM0CH23 Clock Source Select

PWM0 CH2 and CH3 uses the same clock source, and pre-scaler



10 = clock source from HCLK.

11 = clock source from HIRC.(default)

PWM0CH01 Clock Source Select

PWM0 CH0 and CH1 uses the same clock source, and pre-scaler



10 = clock source from HCLK.

11 = clock source from HIRC.(default)

SAR ADC Clock Source Select

00 = clock source from HCLK (default)


10 = clock source from HIRC.


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Revision 2.4

[14:12]

[11]

[10:8]

[7:6]

[5:4]

[3:2]

[1:0]

TMR1SEL

Reserved

TMR0SEL

Reserved

DPWMSEL

SDADCSEL

WDTSEL


TIMER1 Clock Source Select




011 = clock source from external pin (GPIOA[11]).

1xx = clock source from HCLK.(default)

TIMER0 Clock Source Select




011 = clock source from external pin (GPIOA[10]).

1xx = clock source from internal HCLK.(default)

Differential Speaker Driver PWM Clock Source Select

00 = clock source from HCLK/(DPWMDIV+1). (default)

01 = clock source from HXT

1x = Reserved .

SD ADC Clock Source Select (output is MCLK after clock enable)

00 = clock source from HCLK/(SDADCDIV+1). (default)

01 = clock source from HXT

1x = Reserved .

WDT Clock Source Select



10 = clock source from HCLK/2048 clock.

11 = clock source from LIRC.(default)

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Revision 2.4


Clock Divider Register (CLK_CLKDIV0)


CLK_CLKDIV0 CLK_BA + 0x18 R/W Clock Divider Number Register

31

23

15

30

22

14

29

21

13

28

SARADCDIV

27

20 19

12

SDADCDIV

11

DPWMDIV

7 6 5 4 3

BIQDIV

26

18

10

2

UARTDIV

HCLKDIV

25

17

9

1

Reset Value

0x0000_1010

24

16

8

0

Table 5-43 Clock Divider Register (CLK_CLKDIV0, address 0x5000_0218) Bit Description.


[31:24]

[23:16]

[15:12]

[11:8]

[7:4]

[3:0]

SARADCDIV

SDADCDIV

DPWMDIV

UARTDIV

BIQDIV

HCLKDIV

SARADC Clock Divide Number From ADC Clock Source

The SARADC clock frequency = (ADC clock source frequency ) / ( SARADCDIV + 1).

SDADC Clock Divide Number From ADC Clock Source

The SDADC clock frequency = (SDADC clock source frequency ) / ( SDADCDIV + 1)

DPWM Clock Divide Number From HCLK Clock Source

The HCLK clock frequency = (System clock source frequency) / ( DPWMDIV + 1).

UART Clock Divide Number From UART Clock Source

The UART clock frequency = (UART clock source frequency ) / ( UARTDIV + 1).

BIQ Clock Divide Number From HCLK Clock Source

The HCLK clock frequency = (System clock source frequency) / ( BIQDIV + 1).

Suggestion: BIQ_N =1, if HCLK is 49MHz.

HCLK Clock Divide Number From HCLK Clock Source

The HCLK clock frequency = (System clock source frequency) / ( HCLKDIV + 1).

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Revision 2.4



Before changing clock source, ensure that related clock sources (pre-select and new-select) are enabled.


CLK_CLKSEL2 CLK_BA + 0x1C R/W Clock Source Select Control Register 2

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved UART1DIV

25

17

9

7 6 5 4 3 2 1

Reserved

0x0000_0000

I2S0SEL

24

16

8

0

Table 5-44 Clock Source Select Control Register 2 (CLK_CLKSEL2, address 0x5000_021C).

Bits

[32:12]

Description

Reserved

[11:8]

[7:2]

[1:0]

UART1DIV

Reserved

I2S0SEL

Reserved.

UART1 Clock Divide Number From UART Clock Source

The UART clock frequency = (UART clock source frequency ) / ( UART1DIV + 1).

I2S0 Clock Source Select

00 = clock source from internal 10kHz oscillator.(default)

01 = clock source from external 32kHz crystal clock.

10 = clock source from HCLK


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Revision 2.4


Sleep Clock Enable Control Register （ CLK_SLEEPCTL ）

These register bits are used to enable/disable clocks during sleep mode. It works in conjunction with

CLK_AHBCLK and CLK_APBCLK0 clock register to determine whether a clock source remains active during CPU Sleep mode. For a clock to be active in Sleep mode, the appropriate clock must be enabled in the CLK_AHBCLK or CLK_APBCLK0 register and the bit must also be enabled in the

CLK_SLEEPCTL register. In other words, to disable a clock in Sleep mode, write ‘0’ to the appropriate bit in CLK_SLEEPCTL.


CLK_SLEEPCTL CLK_BA + 0x20 R/W Sleep Clock Source Select Register 0xFFFF_FFFF

31

Reserved

30

ANACKEN

29 28 27

I2SCKEN SDADCCKEN Reserved

26

Reserved

25

Reserved

24

Reserved

23

Reserved

15

22 21 20

Reserved PWM0CH23C

14

KEN

13

PWM0CH01C

KEN

12

19

Reserved

11

UART1CKEN Reserved DPWMCKEN SPI0CKEN SPI1CKEN

18 17

BQALCKEN SARADCCKE

10

Reserved

N

9

Reserved

16

UART0CKEN

8

I2C0CKEN

7 6 5 4

TMR1CKEN TMR0CKEN RTCCKEN WDTCKEN

3

Reserved

2 1 0

ISPCKEN PDMACKEN HCLKCKEN

Bits

[31]

[30]

[29]

[28]

[27]

[26]

[25:22]

[21]

[20]

Table 5-45 Sleep Clock Enable Control Register (CLK_SLEEPCTL, address 0x5000_0220).

Description

Reserved

ANACKEN

I2SCKEN

SDADCCKEN

Reserved

Reserved

Reserved

PWM0CH23CKEN

PWM0CH01CKEN

Analog Block Sleep Clock Enable Control

0=Disable.

1=Enable.

I2S Sleep Clock Enable Control

0=Disable.

1=Enable.

Delta-Sigma Analog-digital-converter (ADC) Sleep Clock Enable Control

0=Disable.

1=Enable.

PWM0CH2 and PWM0CH3 Block Sleep Clock Enable Control

0=Disable.

1=Enable.

PWM0CH0 and PWM0CH1 Block Sleep Clock Enable Control

0=Disable.

1=Enable.

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Revision 2.4

[7]

[6]

[12]

[11]

[10:9]

[8]

[16]

[15]

[14]

[13]

[19]

[18]

[17]

[5]

[4]

[2]


Reserved

BIQALCKEN

SARADCCKEN

UART0CKEN

UART1CKEN

Reserved

DPWMCKEN

SPI0CKEN

SPI1CHEN

Reserved

I2C0CKEN

TMR1CKEN

TMR0CKEN

RTCCKEN

WDTCKEN

ISPCKEN

BIQ and ALCSleep Clock Enable Control

0=Disable.

1=Enable.

SARADC Sleep Clock Enable Control

0=Disable.

1=Enable.

UART0 Sleep Clock Enable Control

0=Disable.

1=Enable.

UART1 Sleep Clock Enable Control

0=Disable.

1=Enable.

Differential PWM Speaker Driver Sleep Clock Enable Control

0=Disable.

1=Enable.

SPI0 Sleep Clock Enable Control

0=Disable.

1=Enable.

SPI1 Sleep Clock Enable Control

0=Disable.

1=Enable.

I2C0 Sleep Clock Enable Control

0=Disable.

1=Enable.

Timer1 Sleep Clock Enable Control

0=Disable.

1=Enable.

Timer0 Sleep Clock Enable Control

0=Disable.

1=Enable.

Real-time- Sleep Clock APB Interface Clock Control

0=Disable.

1=Enable.

Watchdog Sleep Clock Enable Control

0=Disable.

1=Enable.

Flash ISP Controller Sleep Clock Enable Control

0=Disable.

1=Enable.

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Revision 2.4

[1]

[0]


PDMACKEN

HCLKCKEN

PDMA Controller Sleep Clock Enable Control

0=Disable.

1=Enable.

CPU Clock Sleep Enable (HCLK)

Must be left as ‘1’ for normal operation.

0=Disable.

1=Enable.

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Revision 2.4


Power State Flag Register (CLK_PWRSTSF)


CLK_PWRSTSF CLK_BA + 0x24 R/W Power State Flag Register

7 6 5

Reserved

4 3 2

SPDF

1

STOPF

Reset Value

0x0000_0000

0

DSF

Table 5-46 Power State Flag Register (CLK_PWRSTSF, address 0x5000_0224) Bit Description.

Bits

[31:3]

Description

Reserved

[2]

[1]

[0]

SPDF

STOPF

DSF

Powered Down Flag

This flag is set if core logic was powered down to Standby (SPD). Write ‘1’ to clear flag.

Stop Flag

This flag is set if core logic was stopped but not powered down. Write ‘1’ to clear flag.

Deep Sleep Flag

This flag is set if core logic was placed in Deep Sleep mode. Write ‘1’ to clear flag.

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Revision 2.4


Debug Power Down Register (CLK_DBGPD)


CLK_BA + 0x28 R/W Debug Port Power Down Disable Register CLK_DBGPD

7 6

ICEDATST ICECLKST

5 4 3

Reserved

2 1

Reset Value

0x0000_00XX

0

DISPDREQ

Table 5-47 Debug Power Down Register (CLK_DBGPD, address 0x5000_0228) Bit Description.


[7]

[6]

[5:1]

[0]

ICEDATST

ICECLKST

Reserved

DISPDREQ

ICEDATST Pin State

Read Only. Current state of ICE_DAT pin.

ICECLKST Pin State

Read Only. Current state of ICE_CLK pin.

Disable Power Down

0 = Enable power down requests.

1 = Disable power down requests.

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Revision 2.4


Deep Power Down 10K Wakeup Timer (CLK_WAKE10K)


CLK_WAKE10K CLK_BA + 0x2C R/W Deep Power Down 10K Wakeup Timer

31 30

WAKE10KEN Reserved

23 22

15

7

Reserved

14

6

29

21

13

5

28 27 26

20

WKTMRSTS

19

WKTMRSTS

18

12

4

SELWKTMR

11

SELWKTMR

10

3 2

25

17

9

1

Reset Value

0x0000_0001

24

16

8

0

Table 5-48 Deep Power Down 10K Wakeup Timer (CLK_WAKE10K, address 0x5000_022C)

Bit Description.


[31]

[30]

[29:16]

[15:14]

[13:0]

WAKE10KEN

Reserved

WKTMRSTS

Reserved

SELWKTMR

Enable WAKE from DPD on 10kHz timer

Reserved

Current Wakeup Timer Setting

Read-Only. Read back of the current WAKEUP timer setting. This value is updated with SELWKTMR upon entering DPD mode.

Reserved

Select Wakeup Timer

WAKEUP after 64* (SELWKTMR+1) OSC10k clocks (6.4 * (SELWKTMR+1) ms)

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Revision 2.4


5.4 General Purpose I/O

5.4.1 Overview and Features

Up to 32 General Purpose I/O pins are available on the ISD91200 series. These are shared peripheral special function pins under control of the alternate configuration registers. These 32 pins are arranged in 2 ports named with GPIOA, and GPIOB. Each one of the 32 pins is independent and has corresponding register bits to control the pin mode function and data.

The I/O type of each GPIO pin can be independently configured as an input, output, open-drain or in a quasi-bidirectional mode. Upon chip reset, all GPIO pins are configured in quasi-bidirectional mode and port data register resets high.

When device is in deep power down (DPD) mode, all GPIO pins become high impedance.

GPIO can generate interrupt signals to the core as either level sensitive or edge sensitive inputs. Edge sensitive inputs can also be de-bounced.

In quasi-bidirectional mode, each GPIO pin has a weak pull-up resistor which is approximately

110K

Ω

~300K

Ω

for V

DD from 5.0V to 2.4V.

Each pin can generate and interrupt exception to the Cortex M0 core. GPIOB[0] and GPIOB[1] can

generate interrupts to system interrupt number IRQ2 and IRQ3 respectively (see Table 5-21). All other

GPIO generate and exception to interrupt number IRQ4.

5.4.2 GPIO I/O Modes

The I/O mode of each GPIO pin is controlled by the register Px.

(x=A or B). Each pin has two bits of control giving four possible states:

5.4.2.1 Input Mode

For Px_MODE n = 00b the GPIO x port [ n ] pin is in Input Mode. The GPIO pin is in a tri-state (high impedance) condition without output drive capability. The Px_PIN value reflects the status of the corresponding port pins.

5.4.2.2 Output Mode

For Px_MODE n = 01b the GPIO x port [ n ] pin is in Output Mode. The GPIO pin supports a digital output function with current source/sink capability. The bit value in the corresponding bit [n] of P x_ DOUT is driven to the pin.

VDD

P

Port Pin[n]

DOUT[n]

N

PIN[n]

Figure 5-6 Output Mode: Push-Pull Output

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Revision 2.4


5.4.2.3 Open-Drain Mode

For Px_MODE n = 10b the GPIO x port [ n ] pin is in Open-Drain mode. The GPIO pin supports a digital output function but only with sink current capability, an additional pull-up resister is needed for defining a high state. If the bit value in the corresponding bit [n] of Px_DOUT is “0”, pin is driven low. If the bit value in the corresponding bit [n] of Px_DOUT is “1”, the pin state is defined by the external load on the pin.

Port Pin

Port Latch

Data

N

Input Data

Figure 5-7 Open-Drain Output

5.4.2.4 Quasi-bidirectional Mode Explanation

For Px_MODE n = 11b the GPIO x port [ n ] pin is in Quasi-bidirectional mode and the I/O pin supports digital output and input function where the source current is only between 30-200uA.Before input function is performed the corresponding bit in Px_DOUT must be set to 1. The quasi-bidirectional output is common on the 80C51 and most of its derivatives. If the bit value in the corresponding bit [n] of Px_DOUT is “0”, the pin will drive a “low” output to the pin. If the bit value in the corresponding bit [n] of Px_DOUT is “1”, the pin will check the pin value. If pin value is high, no action is taken. If pin state is low, then pin will drive a strong high for2 clock cycles. After this the pin has an internal pull-up resistor connected. Note that the source current capability in quasi-bidirectional mode is approximately200uA to

30uA for VDD form 5.0V to 2.4V.

VDD

2 CPU

Clock Delay

P

Strong

P Very

Weak

P

Weak

Port Pin

Port Latch

Data

N

Input Data

Figure 5-8 Quasi-bidirectional GPIO Mode

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Revision 2.4


5.4.3 GPIO Control Register Map


Register Offset

GPIO Base Address:

GPIO_BA = 0x5000_4000

PA_MODE GPIO_BA+0x000

PA_DINOFF GPIO_BA+0x004

PA_DOUT

PA_DATMSK

PA_PIN

PA_DBEN

PA_INTTYPE

PA_INTEN

PA_INTSRC

PB_MODE

PB_DINOFF

PB_DOUT

PB_DATMSK

PB_PIN

PB_DBEN

PB_INTTYPE

PB_INTEN

PB_INTSRC

GPIO_BA+0x008

GPIO_BA+0x00C

GPIO_BA+0x010

GPIO_BA+0x014

GPIO_BA+0x018

GPIO_BA+0x01C

GPIO_BA+0x020

GPIO_BA+0x040

GPIO_BA+0x044

GPIO_BA+0x048

GPIO_BA+0x04C

GPIO_BA+0x050

GPIO_BA+0x054

GPIO_BA+0x058

GPIO_BA+0x05C

GPIO_BA+0x060

R/W Description

R/W GPIO Port A Pin I/O Mode Control

R/W GPIO Port A Pin Input Disable

R/W GPIO Port A Data Output Value

R/W GPIO Port A Data Output Write Mask

R GPIO Port A Pin Value

R/W GPIO Port A De-bounce Enable

R/W GPIO Port A Interrupt Trigger Type

R/W GPIO Port A Interrupt Enable

R/W GPIO Port A Interrupt Source Flag

R/W GPIO Port B Pin I/O Mode Control

R/W GPIO Port B Pin Input Disable

R/W GPIO Port B Data Output Value

R/W GPIO Port B Data Output Write Mask

R GPIO Port B Pin Value

R/W GPIO Port B De-bounce Enable

R/W GPIO Port B Interrupt Trigger Type

R/W GPIO Port B Interrupt Enable

R/W GPIO Port B Interrupt Source Flag

Reset Value

0xFFFF_FFFF

0x0000_0000

0x0000_FFFF

0xXXXX_0000

0x0000_XXXX

0xXXXX_0000

0xXXXX_0000

0x0000_0000

0x0000_0000

0xFFFF_FFFF

0x0000_0000

0x0000_FFFF

0xXXXX_0000

0x0000_XXXX

0xXXXX_0000

0xXXXX_0000

0x0000_0000

0x0000_0000

DBCTL GPIO_BA+0x180 R/W Interrupt De-bounce Control 0x0000_0020

Note: In BSP register structure, GPIO is the structure name. Register is no prefix PA_ or PB_.

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Revision 2.4



GPIO Port [A/B] I/O Mode Control (Px_MODE)


PA_MODE GPIO_BA+0x000 R/W GPIO Port A Pin I/O Mode Control

PB_MODE GPIO_BA+0x040 R/W GPIO Port B Pin I/O Mode Control

31

23

15

7

MODE15

MODE11

MODE7

MODE3

30

22

14

6

Table 5-49 GPIO Mode Control Register

29 28 27 26

MODE14 MODE13

21 20 19 18

MODE10 MODE9

13 12 11 10

MODE6 MODE5

5 4 3 2

MODE2 MODE1


[2n+1 :2n] n=0,1..15

MODEn

Px I/O Pin[n] Mode Control

Determine each I/O type of GPIOx pins

00 = GPIO port [n] pin is in INPUT mode.

01 = GPIO port [n] pin is in OUTPUT mode.

10 = GPIO port [n] pin is in Open-Drain mode.

11 = GPIO port [n] pin is in Quasi-bidirectional mode.

Reset Value

0xFFFF_FFFF

0xFFFF_FFFF

25

MODE12

24

17 16

MODE8

9 8

MODE4

1 0

MODE0

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Revision 2.4


GPIO Port [A/B] Input Disable (Px_DINOFF)


PA_DINOFF GPIO_BA+0x004 R/W GPIO Port A Pin Input Disable

PB_DINOFF GPIO_BA+0x044 R/W GPIO Port B Pin Input Disable

31

23

15

7

30

22

14

6

Table 5-50 GPIO Input Disable Register

29 26

21

13

5

28 27

DINOFF [31:24]

20 19

DINOFF [23:16]

12 11

Reserved

4 3

Reserved

18

10

2


[31:16] DINOFF

Reserved

GPIOx Pin[n] OFF Digital Input Path Enable

0 = Enable IO digital input path (Default).

1 = Disable IO digital input path (low leakage mode).

Reserved. [15:0]

25

17

9

1

Reset Value

0x0000_0000

0x0000_0000

24

16

8

0

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Revision 2.4


GPIO Port [A/B] Data Output Value (Px_DOUT)


PA_DOUT GPIO_BA+0x008 R/W GPIO Port A Data Output Value

PB_DOUT GPIO_BA+0x048 R/W GPIO Port B Data Output Value

31

23

15

7

30

22

14

6

Table 5-51 GPIO Data Output Register (Px_DOUT)

29 26

21

13

5

28 27

Reserved

20 19

Reserved

12

DOUT[15:8]

11

4 3

DOUT[7:0]

18

10

2

Bits

[31:16]

Description

Reserved

[15:0] DOUT

25

17

9

1

Reset Value

0x0000_FFFF

0x0000_FFFF

24

16

8

0

Reserved.

Px Pin[n] Output Value

Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode.

1 = GPIO port [A/B] Pin[n] will drive High if the corresponding output mode bit is set.

0 = GPIO port [A/B] Pin[n] will drive Low if the corresponding output mode bit is set.

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Revision 2.4


GPIO Port [A/B] Data Output Write Mask (Px _DATMSK)


PA_DATMSK GPIO_BA+0x00C R/W GPIO Port A Data Output Write Mask

PB_DATMSK GPIO_BA+0x04C R/W GPIO Port B Data Output Write Mask

31

23

15

7

Table 5-52 GPIO Data Output Write Mask Register (Px_DATMSK)

30 29 26 25

22

14

6

21

13

5

28 27

Reserved

20 19

Reserved

12 11

DATMSK[15:8]

4

DATMSK[7:0]

3

18

10

2

17

9

1

Reset Value

0xXXXX_0000

0xXXXX_0000

24

16

8

0

Bits

[31:16]

Description

Reserved

[15:0] DATMSK

Reserved.

Port [A/B] Data Output Write Mask

These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DATMSK bit[n] to “1”, the corresponding DOUTn bit is writing protected.

0 = The corresponding Px_DOUT[n] bit can be updated.

1 = The corresponding Px_DOUT[n] bit is read only.

- 137 -


Revision 2.4


GPIO Port [A/B] Pin Value (Px _PIN)


PA_PIN GPIO_BA+0x010 R GPIO Port A Pin Value

PB_PIN GPIO_BA+0x050 R GPIO Port B Pin Value

31

23

15

7

30

22

14

6

Table 5-53 GPIO PIN Value Register (Px_PIN)

29 28 27 26

Reserved

21 20 19 18

Reserved

13 12 11 10

PIN[15:8]

5 4 3 2

PIN[7:0]

Bits

[31:16]

Description

Reserved

[15:0] PIN

25

17

9

1

Reset Value

0x0000_XXXX

0x0000_XXXX

24

16

8

0

Reserved.

Port [A/B] Pin Values

The value read from each of these bit reflects the actual status of the respective

GPIO pin

- 138 -


Revision 2.4


GPIO Port [A/B] De-bounce Enable (Px _DBEN)


PA_DBEN GPIO_BA+0x014 R/W GPIO Port A De-bounce Enable

PB_DBEN GPIO_BA+0x054 R/W GPIO Port B De-bounce Enable

31

23

15

7

30

22

14

6

Table 5-54 GPIO Debounce Enable Register (Px_DBEN)

29 26

21

13

5

28 27

Reserved

20 19

Reserved

12

DBEN[15:8]

11

4 3

DBEN[7:0]

18

10

2

25

17

9

1

Bits

[31:16]

Description

Reserved

[15:0] DBEN

Reset Value

0xXXXX_0000

0xXXXX_0000

24

16

8

0

Reserved.

Port [A/B] De-bounce Enable Control

DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the

GPIO_DBCTL register.

The DBEN[n] is used for “edge-trigger” interrupt only; it is ignored for “level trigger” interrupt

0 = The bit[n] de-bounce function is disabled.

1 = The bit[n] de-bounce function is enabled.

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Revision 2.4


GPIO Port [A/B] Interrupt Mode Control (Px _INTTYPE)


PA_INTTYPE GPIO_BA+0x018 R/W GPIO Port A Interrupt Trigger Type

PB_INTTYPE GPIO_BA+0x058 R/W GPIO Port B Interrupt Trigger Type

31

23

15

7

30

22

14

6

Table 5-55 GPIO Interrupt Mode Control (Px_INTTYPE)

29 26

21

13

5

28 27

Reserved

20 19

Reserved

12

TYPE[15:8]

11

4 3

TYPE[7:0]

18

10

2

25

17

9

1

Bits

[31:16]

Description

Reserved

[15:0] TYPE

Reset Value

0xXXXX_0000

0xXXXX_0000

24

16

8

0

Reserved.

Port [A/B] Edge or Level Detection Interrupt Trigger Type

TYPE[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt

0 = Edge triggered interrupt.

1 = Level triggered interrupt.

If level triggered interrupt is selected, then only one level can be selected in the

Px_INTEN register. If both levels are set no interrupt will occur

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Revision 2.4


GPIO Port [A/B] Interrupt Enable Control (Px _INTEN)


PA_INTEN GPIO_BA+0x01C R/W GPIO Port A Interrupt Enable

PB_INTEN GPIO_BA+0x05C R/W GPIO Port B Interrupt Enable

31

23

15

7

30

Table 5-56 GPIO Interrupt Enable Control Register (Px_INTEN)

29 26 25

22

14

6

21

13

5

28

RHIEN[15:8]

27

20 19

12

RHIEN[7:0]

11

FLIEN[15:8]

4 3

FLIEN[7:0]

18

10

2

17

9

1


[31:16]

[15:0]

RHIEN

FLIEN

Reset Value

0x0000_0000

0x0000_0000

24

16

8

0

Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High

RHIEN[n] is used to enable the rising/high interrupt for each of the corresponding

GPIO pins. It also enables the pin wakeup function.

If the interrupt is configured in level trigger mode, a level “high” will generate an interrupt.

If the interrupt is configured in edge trigger mode, a state change from “low-to-high” will generate an interrupt.

GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.

0 = Disable GPIOx[n] for level-high or low-to-high interrupt.

1 = Enable GPIOx[n] for level-high or low-to-high interrupt.

Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low

FLIEN[n] is used to enable the falling/low interrupt for each of the corresponding

GPIO pins. It also enables the pin wakeup function.

If the interrupt is configured in level trigger mode, a level “low” will generate an interrupt.

If the interrupt is configured in edge trigger mode, a state change from “high-to-low” will generate an interrupt.

GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.

0 = Disable GPIOx[n] for low-level or high-to-low interrupt.

1 = Enable GPIOx[n] for low-level or high-to-low interrupt.

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Revision 2.4


GPIO Port [A/B] Interrupt Source Flag(Px _INTSRC)


PA_INTSRC GPIO_BA+0x020 R/W GPIO Port A Interrupt Source Flag

PB_INTSRC GPIO_BA+0x060 R/W GPIO Port B Interrupt Source Flag

15

7

14

6

Table 5-57 GPIO Interrupt Source Flag Register (Px_INTSRC)

13 10 9

5

12 11

INTSRC[15:8]

4

INTSRC[7:0]

3 2 1

Bits

[31:16]

Description

Reserved

[15:0] INTSRC

Reserved.

Port [A/B] Interrupt Source Flag

Read :

1 = Indicates GPIOx[n] generated an interrupt.

0 = No interrupt from GPIOx[n].

Write :

1 = Clear the corresponding pending interrupt.

0 = No action.

Reset Value

0x0000_0000

0x0000_0000

8

0

- 142 -


Revision 2.4


Interrupt De-bounce Control (GPIO_DBCTL )


GPIO_BA+0x180 R/W Interrupt De-bounce Control DBCTL

Table 5-58 GPIO Interrupt De-bounce Control Register (GPIO_DBCTL )

Reset Value

0x0000_0020

7

Reserved

6 5

ICLKON

4

DBCLKSRC

3 2

DBCLKSEL

1 0

Bits

[31:6]

Description

Reserved

[5]

[4]

[3:0]

ICLKON

DBCLKSRC

DBCLKSEL

Reserved.

Interrupt Clock on Mode

Set this bit “0” will gate the clock to the interrupt generation circuit if the GPIOx[n] interrupt is disabled.

0 = disable the clock if the GPIOx[n] interrupt is disabled.

1 = Interrupt generation clock always active.

De-bounce Counter Clock Source Select

0 = De-bounce counter clock source is HCLK.

1 = De-bounce counter clock source is the internal 16 kHz clock.

De-bounce Sampling Cycle Selection

For edge level interrupt GPIO state is sampled every 2^(DBCLKSEL) de-bounce clocks. For example if DBCLKSRC = 6, then interrupt is sampled every 2^6 = 64 debounce clocks. If DBCLKSRC is 10kHz oscillator this would be a 64ms de-bounce.

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Revision 2.4


5.5 Brownout Detection and Temperature Alarm

The ISD91200 is equipped with a Brown-Out voltage detector. The Brown-Out detector features a configurable trigger level and can be configured by flash to be active upon reset. The Brown-Out detector also has a power saving mode where detection can be set up to be active for a configurable on and off time.

BOD operation require that the OSC10k low power oscillator is enabled (CLK_PWRCTL.LIRCDPDEN =

0).

5.5.1 Brownout Register Map


R/W Description Register

BOD Base Address:

BOD_BA = 0x4008_4000

Offset

BOD_BODSEL BOD_BA+0x00

BOD_BODCTL BOD_BA+0x04

BOD_BODDTMR BOD_BA+0x10

R/W Brown Out Detector Select Register

R/W Brown Out Detector Enable Register

R/W Brown Out Detector Timer Register

Reset Value

0x0000_0000

0x000X_000X

0x0003_03E3

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Revision 2.4


5.5.2 Brownout Register Description

This register is initialized by user flash configuration bits config0[22:18].

Brown-Out Detector Select Register (BOD_BODSEL)


BOD_BODSEL BOD_BA+0x00 R/W Brown Out Detector Select Register 0x0000_0000

Table 5-59 Brownout Detector Select Register (BOD_BODSEL, address 0x4008_4000)

7 6

Reserved

5 4

BODHYS

3 2

BODVL

1 0

Bits

[31:5]

Description

Reserved

[4]

[3:0]

BODHYS

BODVL

Reserved.

BOD Hysteresis

0 = Hysteresis Disabled.

1 = Enable Hysteresis of BOD detection.

BOD Voltage Level

1111b = 4.6V.

1110b = 4.2V.

1101b = 3.9V.

1100b = 3.7V.

1011b = 3.6V.

1010b = 3.4V.

1001b = 3.1V.

1000b = 3.0V.

0111b= 2.8V

0110b = 2.6V.

0101b = 2.4V.

0100b = 2.2V.

0011b = 2.1V.

0010b = 2.0V.

0001b = 1.9V.

0000b = 1.8V.

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Revision 2.4


Brown-Out Detector Enable Register (BOD_BODCTL)

This register is initialized by user flash configuration bit config0[23]. If config0[23]=1, then reset value of

BOD_BODCTL is 0x7. The effect of this is to generate a NMI interrupt (default NMI interrupt is BOD interrupt) if BOD circuit detects a voltage below 2.1V. The NMI ISR can be defined by the user to respond to this low voltage level.

Register

BOD_BODCTL

Offset

BOD_BA+0x04

R/W Description

R/W Brown Out Detector Enable Register

Table 5-60 Detector Enable Register (BOD_BODCTL, address 0x4008_4004)

Reset Value

0x000X_000X

31 30 29 26 25 24

23 22

28

Reserved

27

20 19

15 14

21

Reserved

13

18 17

10

LVR_FILTER

9

16

LVR_EN

8

7

Reserved

6 5

BODRST

12 11

Reserved

4

BODOUT

3

BODIF

2

BODINTEN

1

BODEN

0

Bits

[31:5]

Description

Reserved

[18:17]

[16]

[15:6]

[5]

[4]

[3]

LVR_FILTER

LVR_EN

Reserved

BODRST

BODOUT

BODIF

Reserved.

00 = LVR output will be filtered by 1 HCLK.

01 = LVR output will be filtered by 2 HCLK



Default value is 00.

Low Voltage Reset (LVR) Enable (Initialized & Protected Bit)

The LVR function resets the chip when the input power voltage is lower than LVR trip point. Default value is set by flash controller as inverse of CLVR config0[27].

0 = Disable LVR function.

1 = Enable LVR function.

BOD Reset

1: Reset device when BOD is triggered.

Output of BOD Detection Block

This signal can be monitored to determine the current state of the BOD comparator.

BODOUT = 1 implies that VCC is less than BODVL.

Current Status of Interrupt

Latched whenever a BOD event occurs and IE=1. Write ‘1’ to clear.

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Revision 2.4

[2]

[1:0]

BODINTEN

BODEN


BOD Interrupt Enable

0= Disable BOD Interrupt.

1= Enable BOD Interrupt.

BOD Enable

1xb = Enable continuous BOD detection.

01b = Enable time multiplexed BOD detection. See BOD_BODDTMR register.

00b = Disable BOD Detection.

- 147 -


Revision 2.4


Detection Time Multiplex Register (BOD_BODDTMR)

The BOD detector can be set up to take periodic samples of the supply voltage to minimize power consumption. The circuit can be configured and used in Standby Power Down (SPD) mode and can wake up the device if a BOD is event detected. The detection timer uses the OSC10k oscillator as time base so this oscillator must be active for timer operation. When active the BOD circuit requires ~165uA.

With default timer settings, average current reduces to 500nA

165uA*DURTON/(DURTON+DURTOFF).

Register

BOD_BODDTMR

Offset

BOD_BA+0x10

R/W Description

R/W Brown Out Detector Timer Register

Reset Value

0x0003_03E3

Table 5-61 Detection Time Multiplex Register (BOD_BODDTMR, address 0x4008_4010)

31 30 29 28 27 26 25

Reserved

23

15

22

14

Reserved

21

13

20 19 18 17

DURTON[3:0]

10 9

7 6 5

12 11

DURTOFF[15:8]

4 3

DURTOFF[7:0]

2 1

Bits

[31:20]

Description

Reserved

[19:16]

[15:0]

DURTON

DURTOFF

Reserved.

Time BOD Detector Is Active

(DURTON+1) * 100us. Minimum value is 1. (default is 400us)

Time BOD Detector Is Off

(DURTOFF+1)*100us . Minimum value is 7. (default is 99.6ms)

24

16

8

0

5.6 I2C Serial Interface Controller (Master/Slave)

5.6.1 Introduction

I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. Serial, 8-bit oriented, bi-directional data transfers can be made up 1.0 Mbps.

Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a byte-bybyte basis. Each data byte is 8 bits long. There is one SCL clock pulse for each data bit with the MSB being transmitted first. An acknowledge bit follows each transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only during the low period of SCL and must be held stable during the high period of SCL. A transition on the SDA line while SCL is high is interpreted as a command (START or STOP).

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Revision 2.4


STOP START

Repeated

START STOP

SDA t

BUF t

LOW t r t f

SCL t

HD;STA t

HIGH t

HD;DAT t

SU;DAT t

SU;STA t

SU;STO

Figure 5-9 I2C Bus Timing

The device’s on-chip I2C logic provides the serial interface that meets the I2C bus standard mode specification. The I2C port handles byte transfers autonomously. To enable this port, the bit I2CEN in

I2C_CTL should be set to '1'. The I2C H/W interfaces to the I2C bus via two pins: I2C_SDA and

I2C_SCL.See Table 5-10 for alternate GPIO pin functions. Pull up resistor is needed for these pins for

I2C operation as these are open drain pins.

The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus. The main features of the bus are:

 Master/Slave up to 1Mbit/s

 Bidirectional data transfer between masters and slaves

 Multi-master bus (no central master)

 Arbitration between simultaneously transmitting masters without corruption of serial data on the bus

 Serial clock synchronization allows devices with different bit rates to communicate via one serial bus

 Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer

 Built-in a 14-bit time-out counter will request the I2C interrupt if the I2C bus hangs up and timerout counter overflows.

 External pull-up are needed for high output

 Programmable clocks allow versatile rate control

 Supports 7-bit addressing mode

 I2C-bus controllers support multiple address recognition ( Four slave address with mask option)

5.6.1.1 I

2

C Protocol

Normally, a standard communication consists of four parts:

1) START or Repeated START signal generation

2) Slave address transfer

3) Data transfer

4) STOP signal generation

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Revision 2.4


SCL

1 2 7 8 9 1 2 3 - 7 8 9

P

SDA

S or

Sr

A6

MSB

A5 A4 - A1 A0 R/W

LSB

ACK D7

MSB

D6 D5 - D1 D0

LSB

NACK

ACK

Figure 5-10 I2C Protocol

5.6.1.2 Data transfer on the I2C-bus

A master-transmitter always begins by addressing a slave receiver with a 7-bit address. For a transaction where the master-transmitter is sending data to the slave, the transfer direction is not changed, master is always transmitting and slave acknowledges the data.

P or

Sr

Sr

S SLAVE ADDRESS R/W A DATA A DATA A/A P data transfer

(n bytes + acknowledge)

'0'(write) from master to slave from slave to master

A = acknowledge (SDA low)

A = not acknowledge (SDA high)

S = START condition

P = STOP condition

Figure 5-11 Master Transmits Data to Slave

For a master to read data from a slave, master addresses slave with the R/W bit set to ‘1’, immediately after the first byte (address) is acknowledged by the slave the transfer direction is changed and slave sends data to the master and master acknowledges the data transfer.

S SLAVE ADDRESS R/W A DATA A DATA A P data transfer

(n bytes + acknowledge)

'1'(read)

Figure 5-12 Master Reads Data from Slave

5.6.1.3 START or Repeated START signal

When the bus is free/idle, meaning no master device is engaging the bus (both SCL and SDA lines are high), a master can initiate a transfer by sending a START signal. A START signal, usually referred to as the S-bit, is defined as a HIGH to LOW transition on the SDA line while SCL is HIGH. The START signal denotes the beginning of a new data transfer.

A Repeated START (Sr) is a START signal without first generating a STOP signal. The master uses this method to communicate with another slave or the same slave in a different transfer direction (e.g. from writing to a device to reading from a device) without releasing the bus.

STOP signal

The master can terminate the communication by generating a STOP signal. A STOP signal, usually referred to as the P-bit, is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH.

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Revision 2.4


SCL

SDA

START condition STOP condition

Figure 5-13 START and STOP condition

5.6.1.4 Slave Address Transfer

The first byte of data transferred by the master immediately after the START signal is the slave address. This is a 7-bits calling address followed by a RW bit. The RW bit signals the slave the data transfer direction. No two slaves in the system can have the same address. Only the slave with an address that matches the one transmitted by the master will respond by returning an acknowledge bit by pulling the SDA low at the 9th SCL clock cycle.

5.6.1.5 Data Transfer

Once successful slave addressing has been achieved, the data transfer can proceed on a byte-by-byte basis in the direction specified by the RW bit sent by the master. Each transferred byte is followed by an acknowledge bit on the 9th SCL clock cycle. If the slave signals a Not Acknowledge (NACK), the master can generate a STOP signal to abort the data transfer or generate a Repeated START signal and start a new transfer cycle.

If the master, as the receiving device, does Not Acknowledge (NACK) the slave, the slave releases the

SDA line for the master to generate a STOP or Repeated START signal.

SCL

SDA data line stable; data valid change of data allowed

Figure 5-14 Bit Transfer on the I2C bus

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Revision 2.4

ISD91200 Series Technical Reference Manual clock pulse for acknowledgement

9

SCL FROM

MASTER

1 2 8

DATA OUTPUT BY

TRANSMITTER not acknowledge

DATA OUTPUT BY

RECEIVER

S

START condition acknowledge

Figure 5-15 Acknowledge on the I2C bus

5.6.2 Modes of Operation

The on-chip I2C ports support five operation modes, Master transmitter, Master receiver, Slave transmitter, Slave receiver, and GC call.

In a given application, I2C port may operate as a master or as a slave. In the slave mode, the I2C port hardware looks for its own slave address and the general call address. If one of these addresses is detected, and if the slave is willing to receive or transmit data from/to master(by setting the AA bit), an acknowledge pulse will be transmitted out on the 9th clock. An interrupt is requested on both master and slave devices if interrupt is enabled. When the microcontroller wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted. If bus arbitration is lost in the master mode, I2C port switches to the slave mode immediately and can detect its own slave address in the same serial transfer.

5.6.2.1 Master Transmitter Mode

Serial data output through SDA while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. In this case the data direction bit (R/W) will be logic 0, and it is represented by “W” in the flow diagrams. Thus the first byte transmitted is SLA+W. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received. START and STOP conditions are output to indicate the beginning and the end of a serial transfer.

5.6.2.2 Master Receiver Mode

In this case the data direction bit (R/W) will be logic 1, and it is represented by “R” in the flow diagrams.

Thus the first byte transmitted is SLA+R. Serial data is received via SDA while SCL outputs the serial clock. Serial data is received 8 bits at a time. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are output to indicate the beginning and end of a serial transfer.

5.6.2.3 Slave Receiver Mode

Serial data and the serial clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit.

5.6.2.4 Slave Transmitter Mode

The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted via SDA while the serial clock is input through SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer.

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Revision 2.4


5.6.3 Data Transfer Flow in Five Operating Modes

The five operating modes are: Master/Transmitter, Master/Receiver, Slave/Transmitter, Slave/Receiver and GC Call. Bits STA, STO and AA in I2C_CTL register will determine the next state of the SIO hardware after SI flag is cleared. Upon completion of the new action, a new status code will be updated and the SI flag will be set. If the I2C interrupt control bit INTEN (I2C_CTL[7]) is set, appropriate action or software branch of the new status code can be performed in the Interrupt service routine.

Data transfers in each mode are shown in the following figures.

*** Legend for the following five figures:

Last state

Last action is done

Next setting in I2CON

Expected next action

08H

A START has been transmitted.

(STA,STO,SI,AA)=(0,0,0,X)

SLA+W will be transmitted;

ACK bit will be received.

Software's access to I2DAT with respect to "Expected next action":

(1) Data byte will be transmitted:

Software should load the data byte (to be transmitted) into I2DAT before new I2CON setting is done.

(2) SLA+W (R) will be transmitted:

Software should load the SLA+W/R (to be transmitted) into I2DAT before new I2CON setting is done.

(3) Data byte will be received:

Software can read the received data byte from I2DAT while a new state is entered.

New state next action is done

18H

SLA+W has been transmitted;

ACK has been received.

Figure 5-16 Legend for the following four figures

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Revision 2.4


From Slave Mode (C)

Set STA to generate a START.

08H





18H



or

20H


NOT ACK bit will be received.

From Master/Receiver (B)


Data byte will be transmitted;

ACK will be received.


A repeated START will be transmitted;

28H

Data byte in S1DAT has been transmitted;


or

30H


NOT ACK has been received.

10H

A repeated START has been transmitted.


A STOP will be transmitted;

STO flag will be reset.


A STOP followed by a START will be transmitted;


Send a STOP

Send a STOP followed by a START


SLA+R will be transmitted;

ACK bit will be transmitted;

SIO1 will be switched to MST/REC mode.

38H

Arbitration lost in SLA+R/W or

Data byte.

To Master/Receiver (A)


I2C bus will be release;

Not address SLV mode will be entered.


A START will be transmitted when the bus becomes free.

Enter NAslave

Send a START when bus becomes free

Figure 5-17 Master Transmitter Mode

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Revision 2.4


Set STA to generate a START.

08H


From Slave Mode (C)

From Master/Transmitter (A)




48H

SLA+R has been transmitted;


40H

SLA+R has been transmitted;


(STA,STO,SI,AA)=(0,0,1,0)

Data byte will be received;

NOT ACK will be returned.

58H

Data byte has been received;

NOT ACK has been returned.



ACK will be returned.

50H


ACK has been returned.


A STOP followed by a START will be transmitted;


Send a STOP followed by a START


A STOP will be transmitted;


Send a STOP

38H

Arbitration lost in NOT ACK bit.


A START will be transmitted; when the bus becomes free


A repeated START will be transmitted;

10H

A repeated START has been transmitted.



ACK bit will be transmitted;

SIO1 will be switched to MST/REC mode.


I2C bus will be release;

Not address SLV mode will be entered.

To Master/Transmitter (B)


Enter NAslave

Figure 5-18 Master Receiver Mode

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Revision 2.4


Set AA

A8H

Own SLA+R has been received;

ACK has been return.

or

B0H

Arbitration lost SLA+R/W as master;

Own SLA+R has been received;



Last data byte will be transmitted;





C8H

Last data byte in S1DAT has been transmitted;


C0H

Data byte or Last data byte in S1DAT has been transmitted;


B8H




Last data will be transmitted;


A0H

A STOP or repeated START has been received while still addressed as SLV/TRX.





Switch to not address SLV mode;

Own SLA will be recognized;



Switch to not addressed SLV mode;

No recognition of own SLA;

A START will be transmitted when the becomes free.



Own SLA will be recognized.



No recognition of own SLA.

Enter NAslave


To Master Mode (C)

Figure 5-19 Slave Transmitter Mode

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Revision 2.4


Set AA

60H

Own SLA+W has been received;


or

68H

Arbitration lost SLA+R/W as master;

Own SLA+W has been received;





88H

Previously addressed with own SLA address;





80H

Previously addressed with own SLA address;

Data has been received;



Data will be received;


A0H

A STOP or repeated START has been received while still addressed as SLV/REC.



















To Master Mode (C)

Figure 5-20 Slave Receiver Mode

Enter NAslave

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Revision 2.4


Set AA

70H

Reception of the general call address and one or more data bytes;


or

78H

Arbitration lost SLA+R/W as master; and address as SLA by general call;


(STA,STO,SI,AA)=(X,0,1,0)



98H

Previously addressed with General Call;






90H

Previously addressed with General Call;

Data has been received;





A0H

A STOP or repeated START has been received while still addressed as

SLV/REC.


















Enter NAslave


To Master Mode (C)

Figure 5-21 GC Mode

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Revision 2.4


5.6.4 I2C Protocol Registers

The CPU interfaces to the SIO port through the following thirteen special function registers: I2C_CTL

(control register), I2C_STATUS (status register), I2C_DAT (data register), I2C_ADDRn (address registers, n=0~3), I2C_ADDRMSKn (address mask registers, n=0~3), I2C_CLKDIV (clock rate register) and I2C_TOCTL (Time-out counter register). Bits 31~ bit 8 of these I2C special function registers are reserved. These bits do not have any functions and are all zero if read back.

When I2C port is enabled by setting I2CEN (I2C_CTL[6]) to high, the internal states will be controlled by

I2C_CTL and I2C logic hardware. Once a new status code is generated and stored in I2C_STATUS, the I2C Interrupt Flag bit SI (I2C_CTL[3]) will be set automatically. If the Enable Interrupt bit INTEN

(I2C_CTL[7]) is set high at this time, the I2C interrupt will be generated. The bit field I2C_STATUS[7:3] stores the internal state code, the lowest 3 bits of I2C_STATUS are always zero and the contents are stable until SI is cleared by software. The base address of the I2C peripheral on theISD91200 is

0x4002_0000.

5.6.4.1 Address Registers (I2C_ADDR)

I2C port is equipped with four slave address registers I2C_ADDRn (n=0~3). The contents of the register are irrelevant when I2C is in master mode. In the slave mode, the bit field I2C_ADDRn[7:1] must be loaded with the MCU’s own slave address. The I2C hardware will react if the contents of I2C_ADDR are matched with the received slave address.

The I2C ports support the “General Call” function. If the GC bit (I2C_ADDRn[0]) is set the I2C port hardware will respond to General Call address (00H). Clear GC bit to disable general call function.

When GC bit is set, the I2C is in Slave mode, it can be received the general call address by 00H after

Master send general call address to I2C bus, then it will follow status of GC mode. If it is in master mode, the AA bit (I2C_CTL[2], Assert Acknowledge control bit) must be cleared when it will send general call address of 00H to I2C bus.

I2C-bus controllers support multiple address recognition with four address mask registers I2ADRMn

(n=0~3). When the bit in the address mask register is set to one, it means the received corresponding address bit is don’t-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.

5.6.4.2 Data Register (I2C_DAT)

This register contains a byte of serial data to be transmitted or a byte which has just been received. The

CPU can read from or write to this 8-bit (I2C_DAT[7:0]) directly addressable SFR while it is not in the process of shifting a byte. This occurs when SIO is in a defined state and the serial interrupt flag (SI) is set. Data in I2C_DAT[7:0] remains stable as long as SI bit is set. While data is being shifted out, data on the bus is simultaneously being shifted in; I2C_DAT[7:0] always contains the last data byte present on the bus. Thus, in the event of arbitration lost, the transition from master transmitter to slave receiver is made with the correct data in I2C_DAT[7:0].

I2C_DAT[7:0] and the acknowledge bit form a 9-bit shift register, the acknowledge bit is controlled by the SIO hardware and cannot be accessed by the CPU. Serial data is shifted through the acknowledge bit into I2C_DAT[7:0] on the rising edges of serial clock pulses on the SCL line. When a byte has been shifted into I2C_DAT[7:0], the serial data is available in I2C_DAT[7:0], and the acknowledge bit (ACK or

NACK) is returned by the control logic during the ninth clock pulse. Serial data is shifted out from

I2C_DAT[7:0] on the falling edges of SCL clock pulses, and is shifted into I2C_DAT[7:0] on the rising edges of SCL clock pulses.

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Revision 2.4


I2C Data Register:

DATA.7 DATA.6 DATA.5 DATA.4 DATA.3 DATA.2 DATA.1 DATA.0

shifting direction

Figure 5-22 I2C Data Shift Direction

5.6.4.3 Control Register (I2C_CTL)

The CPU can read from and write to this 8-bit field of I2C_CTL[7:0]. Two bits are affected by hardware: the SI bit is set when the I2C hardware requests a serial interrupt, and the STO bit is cleared when a

STOP condition is present on the bus. The STO bit is also cleared when I2CEN = "0".

INTEN Enable Interrupt.

I2CEN

STA

STO

Set to enable I2C serial function block. When I2CEN=1 the I2C serial function is enabled.

I2C START Control Bit. Setting STA to logic 1 enters master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.

I2C STOP Control Bit. In master mode, setting STO transmits a STOP condition to the bus.

The I2C hardware will check the bus condition and if a STOP condition is detected this flag will be cleared by hardware. In a slave mode, setting STO resets I2C hardware to the defined “not addressed” slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.

SI

AA

I2C Interrupt Flag. When a new SIO state is present in the I2C_STATUS register, the SI flag is set by hardware, and if bit INTEN (I2C_CTL[7]) is set, the I2C interrupt is requested.

SI must be cleared by software. Clear SI is by writing one to this bit.

Assert Acknowledge Control Bit. When AA=1 prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when:

1.) A slave is acknowledging the address sent from master,

2.) A receiver device is acknowledging the data sent by a transmitter.

When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.

5.6.4.4 Status Register (I2C_STATUS)

I2C_STATUS[7:0] is an 8-bit read-only register. The three least significant bits are always 0. The bit field I2C_STATUS[7:3] contains the status code. There are 26 possible status codes. When

I2C_STATUS[7:0] contains F8H, no serial interrupt is requested. All other I2C_STATUS[7:3] values correspond to defined SIO states. When each of these states is entered, a status interrupt is requested

(SI = 1). A valid status code is present in I2C_STATUS[7:3] one machine cycle after SI is set by hardware and is still present one machine cycle after SI has been reset by software.

In addition, state 00H stands for a Bus Error. A Bus Error occurs when a START or STOP condition is present at an illegal position in the format frame. Examples of illegal positions are during the serial transfer of an address byte, a data byte or an acknowledge bit. To recover I2C from bus error, STO should be set and SI should be clear to enter not addressed slave mode. Then clear STO to release bus and to wait new communication. I2C bus cannot recognize stop condition during this action when bus error occurs.

5.6.4.5 I2C Clock Baud Rate Bits (I2C_CLKDIV)

The data baud rate of I2C is determined by I2C_CLKDIV[7:0] register when SIO is in a master mode. It is not important when SIO is in a slave mode. In the slave modes, SIO will automatically synchronize

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Revision 2.4

ISD91200 Series Technical Reference Manual with any clock frequency up to 1M Hz from master I2C device.

Data Baud Rate of I2C = PCLK /(4x(I2C_CLKDIV[7:0]+1)). If PCLK=16MHz, the I2C_CLKDIV[7:0] = 40

(28H), data baud rate of I2C = 16MHz/(4x(40 +1)) = 97.5Kbits/sec.

5.6.4.6 The I2C Time-out Counter Register (I2C_TOCTL)

There is a 14-bit time-out counter which can be configured to deal with an I2C bus hang-up. If the timeout counter is enabled, the counter starts up-counting until it overflows (TOIF=1) and generates I2C interrupt to CPU or stops counting by clearing TOCEN to 0. When time-out counter is enabled, setting flag SI to high will reset counter. Counter will re-start after SI is cleared. If the I2C bus hangs up,

counter will overflow and generate a CPU interrupt. Refer to Figure 5-23 I2C Time-out Count Block

Diagram for the 14-bit time-out counter. User can clear TOIF by writing one to this bit.

Pclk

1/4

DIV4

0

1

Enabl e

I2CEN

TOCEN

14-bit Counter

Clear Counter

TOIF

SI

SI

Figure 5-23 I2C Time-out Count Block Diagram

To I2C Interrupt

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Revision 2.4


5.6.5 Register Mapping

R : read only, W : write only, R/W : both read and write

Register Offset

I2C Base Address:

I2C_BA = 0x4002_0000

I2C_CTL

R/W Description

I2C_BA+0x00 R/W I2C Control Register

I2C_ADDR0 I2C_BA+0x04 R/W I2C Slave address Register0

I2C_BA+0x08 R/W I2C DATA Register I2C_DAT

I2C_STATUS I2C_BA+0x0C R I2C Status Register

I2C_CLKDIV

I2C_TOCTL

I2C_BA+0x10 R/W I2C clock divided Register

I2C_BA+0x14 R/W I2C Time out control Register

I2C_ADDR1

I2C_ADDR2

I2C_BA+0x18 R/W I2C Slave address Register1

I2C_BA+0x1C R/W I2C Slave address Register2

I2C_ADDR3 I2C_BA+0x20 R/W I2C Slave address Register3

I2C_ADDRMSK0 I2C_BA+0x24 R/W I2C Slave address Mask Register0


I2C_ADDRMSK2 I2C_BA+0x2C R/W I2C Slave address Mask Register2


Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_00F8

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

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Revision 2.4



I2C CONTROL REGISTER (I2C_CTL)


I2C_CTL I2C_BA+0x00 R/W I2C Control Register

Bits

[31:8]

7

INTEN

6

I2CEN

Description

Reserved

5

STA

4

STO

[7]

[6]

[5]

[4]

[3]

[2]

[1:0]

INTEN

I2CEN

STA

STO

SI

AA

Reserved

3

SI

2

AA

1

Reset Value

0x0000_0000

Reserved

0

Reserved.

Enable Interrupt

0 = Disable interrupt.

1 = Enable interrupt CPU.

I2C Controller Enable Bit

0 = Disable.

1 = Enable.

Set to enable I2C serial function block.

I2C START Control Bit

Setting STA to logic 1 will enter master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.

I2C STOP Control Bit

In master mode, set STO to transmit a STOP condition to bus. I2C hardware will check the bus condition, when a STOP condition is detected this bit will be cleared by hardware automatically. In slave mode, setting STO resets I2C hardware to the defined “not addressed” slave mode. This means it is NO LONGER in the slave receiver mode able receive data from the master transmit device.

I2C Interrupt Flag

When a new SIO state is present in the I2C_STATUS register, the SI flag is set by hardware, and if bit INTEN (I2C_CTL[7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing one to this bit.

Assert Acknowledge Control Bit

When AA=1 prior to address or data received, an acknowledge (ACK - low level to

SDA) will be returned during the acknowledge clock pulse on the SCL line when:.

1. A slave is acknowledging the address sent from master,

2. The receiver devices are acknowledging the data sent by transmitter.

When AA = 0 prior to address or data received, a Not acknowledged (high level to

SDA) will be returned during the acknowledge clock pulse on the SCL line.

Reserved.

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Revision 2.4


I2C DATA REGISTER (I2C_DAT)


I2C_BA+0x08 R/W I2C DATA Register I2C_DAT

7 6 5 4

DAT[7:0]

3

Bits

[31:8]

Description

Reserved

[7:0] DAT

2 1

Reset Value

0x0000_0000

0

Reserved.

I2C Data Register

During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.

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Revision 2.4


I2C STATUS REGISTER (I2C_STATUS )

Register

I2C_STATUS


I2C_BA+0x0C R I2C Status Register

7 6 5 4

STATUS[7:0]

3

Bits

[31:8]

Description

Reserved

[7:0] STATUS

2 1

Reset Value

0x0000_00F8

0

Reserved.

I2C Status Register

The status register of I2C:

The three least significant bits are always 0. The five most significant bits contain the status code. There are 26 possible status codes. When I2C_STATUS contains F8H, no serial interrupt is requested. All other I2C_STATUS values correspond to defined

I2C states. When each of these states is entered, a status interrupt is requested (SI

= 1). A valid status code is present in I2C_STATUS one PCLK cycle after SI is set by hardware and is still present one PCLK cycle after SI has been reset by software. In addition, states 00H stands for a Bus Error. A Bus Error occurs when a START or

STOP condition is present at an illegal position in the frame. Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.

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Revision 2.4


I2C DATA BAUD RATE CONTROL REGISTER (I2C_CLKDIV)

Register

I2C_CLKDIV


I2C_BA+0x10 R/W I2C clock divided Register

7 6 5 4

DIVIDER[7:0]

3 2

Bits

[31:8]

Description

Reserved

[7:0] DIVIDER

1

Reset Value

0x0000_0000

0

Reserved.

I2C Clock Divided Register

The I2C clock rate bits: Data Baud Rate of I2C = PCLK /(4x(I2C_CLKDIV+1)).

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Revision 2.4


I2C TIME-OUT COUNTER REGISTER (I2C_TOCTL)

Register

I2C_TOCTL


I2C_BA+0x14 R/W I2C Time out control Register

7 6 5

Reserved

4 3

Bits

[31:3]

Description

Reserved

[2]

[1]

[0]

TOCEN

TOCDIV4

TOIF

2

TOCEN

1

TOCDIV4

Reset Value

0x0000_0000

0

TOIF

Reserved.

Time-out Counter Control Bit

0 = Disable.

1 = Enable.

When enabled, the 14 bit time-out counter will start counting when SI is clear.

Setting flag SI to high will reset counter and re-start up counting after SI is cleared.

Time-out Counter Input Clock Divide by 4

0 = Disable.

1 = Enable.

When enabled, the time-out clock is PCLK/4.

Time-out Flag

0 = No time-out.

1 = Time-out flag is set by H/W. It can interrupt CPU. Write 1 to clear..

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Revision 2.4


I2C SLAVE ADDRESS REGISTER (I2CADDRx)

Register

I2C_ADDR0



I2C_ADDR1

I2C_ADDR2

I2C_ADDR3

7


I2C_BA+0x1C R/W I2C Slave address Register2


6 5 4

ADDR[7:1]

3

Bits

[31:8]

Description

Reserved

[7:1]

[0]

ADDR

GC

2 1

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0

GC

Reserved.

I2C Address Register

The content of this register is irrelevant when I2C is in master mode. In the slave mode, the seven most significant bits must be loaded with the MCU’s own address.

The I2C hardware will react if any of the addresses are matched.

General Call Function

0 = Disable General Call Function.

1 = Enable General Call Function.

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Revision 2.4


I2C SLAVE ADDRESS MASK REGISTER (I2CADMx)



Reset Value

0x0000_0000


I2C_ADDRMSK2 I2C_BA+0x2C R/W I2C Slave address Mask Register2

0x0000_0000

0x0000_0000

[7:1]

[0]


7 6 5 4

ADDRMSK

3

Bits

[31:8]

Description

Reserved

ADDRMSK

Reserved

2 1

0x0000_0000

0

Reserved

Reserved.

I2C Address Mask Register

0 = Mask disable.

1 = Mask enable (the received corresponding address bit is don’t care.).

I2C bus controllers support multiple-address recognition with four address mask registers. Bits in this field mask the ADDRx registers masking bits from the address comparison.

Reserved.

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Revision 2.4


5.7 PWM Generator and Capture Timer

5.7.1 Introduction

The ISD91200 has two PWM generators which can be configured as 4 independent PWM outputs,

PWM0CH0, PWM0CH1, PWM0CH2 and PWM0CH3, or as a complementary PWM pairs with programmable dead-zone generator. Each PWM Generator has an 8-bit pre-scaler, a clock divider providing 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16), two PWM Timers including two clock selectors, two 16-bit PWM down-counters for PWM period control, two 16-bit comparators for PWM duty control and one dead-zone generator. The PWM Generator provides PWM interrupt flags which are set by hardware when the corresponding PWM period down counter reaches zero. Each PWM interrupt source, with its corresponding enable bit, can generate a PWM interrupt request to the CPU. The PWM generator can be configured in one-shot mode to produce only one PWM cycle signal or continuous mode to output a periodic PWM waveform.

When PWM_CTL.DTEN01 is set, PWM0CH0 and PWM0CH1 perform complementary paired PWM function; the paired PWM timing, period, duty and dead-time are determined by PWM0 timer and Dead-

zone generator0. Refer to Figure 5-25 PWM Generator Architecture Diagram for the architecture of

PWM Timers.

To prevent PWM driving glitches to an output pin, the 16-bit period down-counter and 16-bit comparator are implemented with a double buffer. When user writes data to the counter/comparator registers, the updated value will not be load into the 16-bit down-counter/comparator until the down-counter reaches zero.

When the 16-bit period down-counter reaches zero, the interrupt request is generated. If PWM timer is configured in continuous mode, when the down counter reaches zero, it is reloaded with PWM Counter

Register automatically and begins decrementing again. If the PWM timer is configured in one-shot mode, the down counter will stop and generate a single interrupt request when it reaches zero.

The value of PWM counter comparator is used for pulse width modulation. The counter control logic inverts the output level when down-counter value matches the value of compare register.

The alternate function of the PWM-timer is as a digital input capture timer. If Capture function is enabled the PWM output pin is switched as a capture input pin. The Capture0 and PWM0CH0 share one timer which is included in PWM0CH0; and the Capture1 and PWM0CH1 share PWM0CH1 timer.

User must setup the PWM-timer before enabling the Capture feature. After the capture feature is enabled, the count is latched to the Capture Rising Latch Register (RCAPDAT) when input channel has a rising transition and latched to Capture Falling Latch Register (PWM_FCAPDATx) when input channel has a falling transition. Capture channel 0 interrupt is programmable by setting

PWM_CAPCTL01.CRLIEN0[1] (Rising latch Interrupt enable) and PWM_CAPCTL01.CFLIEN0[2]]

(Falling latch Interrupt enable) to determine the condition of interrupt occurrence. Capture channel 1 has the same feature by setting PWM_CAPCTL01.CRLIEN1[17] and PWM_CAPCTL01.CFLIEN1[18].

Whenever Capture issues interrupt, the PWM counter will also be reloaded.

5.7.2 Features

5.7.2.1 PWM function features:

 PWM Generator, incorporating an 8-bit pre-scaler, clock divider, two PWM-timers (down counters), a dead-zone generator and two PWM outputs.

 Up to 4 PWM channels or two paired PWM channel.

 16 bits resolution.

 PWM Interrupt request synchronous with PWM period.

 Single-shot or Continuous mode PWM.

 Dead-Zone generator.

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Revision 2.4


5.7.2.2 Capture Function Features:

 Timing control logic shared with PWM Generators.

 2 Capture input channels shared with 2 PWM output channels.

 Each channel supports a rising latch register (RCAPDAT), a falling latch register

(PWM_FCAPDATx) and Capture interrupt flag (CAPIFx)

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Revision 2.4


5.7.3 PWM Generator Architecture

The following figures illustrate the architecture of the PWM.

PWM0CH01SEL

(CLK_CLKSEL1[29:28])

PWM0CH01EN(CLK_APBCLK0[20])

PWM0CH01_CLK CLK48M

HCLK

CLK32K

CLK10K

11

10

01

00

Figure 5-24 PWM Generator Clock Source Control

CSR0(CSR[2:0])

DZI01

CNR0, CMR0,

PCR

Dead Zone

Generator 0

PWM0CH01_CLK

(from clock controller)

8-bit

Prescaler

PPR.CP01

Clock

Divider

1

1/2

1/4

1/8

1/16

1

1/2

1/4

1/8

1/16

100

000

001

010

011

1

1/2

1/4

1/8

1/16

100

000

001

010

011

CSR1(CSR[6:4])

PWM-

Timer0

Logic

1

0

PWMIE0 PWMIF0

CH0INV

DZEN01

CNR1, CMR1,

PCR

PWM-

Timer1

Logic

PWMIE1 PWMIF1

CH1INV

1

0

1

0

1

0

POE.PWM0

POE.PWM1

PA.12/PWM0

PA.13/PWM1

Figure 5-25 PWM Generator Architecture Diagram

5.7.4 PWM-Timer Operation

The PWM period and duty control are configured by the PWM down-counter register

(PWMx_PERIODx) and PWM comparator register (PWMx_CMPDATx). Formulas for calculating the

pulse width modulation are shown below and demonstrated in Figure 5-26 PWM Generation Timing.

Note that the corresponding GPIO pins must be configured as the alternate function before PWM function is enabled.

 PWM frequency = PWM0CH01_CLK/(prescale+1)*(clock divider)/(PERIOD+1);

 Duty cycle = (CMP+1)/(PERIOD+1).

 CMP >= PERIOD: PWM output is always high.

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Revision 2.4


 CMP < PERIOD: PWM low width= (PERIOD-CMP) unit

1

; PWM high width=(CMP+1) unit.

 CMP = 0: PWM low width = (PERIOD) unit; PWM high width=1 unit

Note: 1. Unit = one PWM clock cycle.

Initialize

PWM

Start Update new CMRx

CMRx+1

CNRx

+

-

PWM-Timer

Comparator

Output

CMRx

CNRx

PWM

Ouput

CNR+1

CMR+1

Note: x= 0~1.

Figure 5-26 PWM Generation Timing

The procedure to operate the PWM generator is shown in Figure 5-27 PWM-Timer Operation Timing.

First initialize the PWM settings. At the same time ensure that GPIO are configured to PWM function.

Next step is to enable PWM channel. After this, if PERIOD or CMP register is written by software, it is double buffered until the next counter reload, at which time the registers are updated to new values.

Comparator

(CMR)

1 1 0

PWM down-counter

3 3 2 1 0 4 3 2 1 0 4

PWM-Timer output

CMR = 1

CNR = 3

Auto reload = 1

(CHxMOD=1)

(Write initial setting)

Set ChxEN=1

(PWM-Timer starts running)

CMR = 0

CNR = 4

(S/W write new value)

Auto-load

(H/W update value)

(PWMIFx is set by H/W)

Figure 5-27 PWM-Timer Operation Timing

Auto-load

(PWMIFx is set by H/W)

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Revision 2.4


5.7.5 PWM Double Buffering, Auto-reload and One-shot Operation

The ISD91200 series PWM Timers are double buffered, the reload value is updated at the start of next period without affecting current timer operation. The PWM counter reset value can be written into

PWM_PERIOD0~1 and current PWM counter value can be read from PWM_CNT0~1.

The bit CNTMODEx in PWM Control Register (PWM_CTL) determines whether PWMx operates in auto-reload or one-shot mode. If CNTMODEx is set to one, the auto-reload operation loads PERIODx to PWM counter when PWM counter reaches zero. If PERIODx is set to zero, PWM counter will halt when PWM counter counts to zero. If CNTMODEx is set as zero, counter will stop immediately.

Write

CNR=150

CMR=50

Start

Write

CNR=199

CMR=49

Write

CNR=99

CMR=0

Write

CNR=0

CMR=XX

Stop

PWM

Waveform

51 50 1 write a nonzero number to prescaler & setup clock dividor

151 200 100

Figure 5-28 PWM Double Buffering.

5.7.6 Modulate Duty Cycle

The double buffering allows CMP to be written at any point in current cycle. The loaded value will take

effect from next cycle. This is demonstrated in Figure 5-29 PWM Controller Duty Cycle Modulation

(PERIOD = 150).

101 51 1

Write

CMR=100

CNR=150

Write

CMR=50

Write

CMR=0

1 PWM cycle = 151 1 PWM cycle = 151 1 PWM cycle = 151

Figure 5-29 PWM Controller Duty Cycle Modulation (PERIOD = 150).

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Revision 2.4


5.7.7 Dead-Zone Generator

The ISD91200 PWM generator includes a Dead Zone generator. This is used to ensure neither PWM output is active simultaneously for power device protection. The function generates a programmable time gap between rising PWM outputs. The user can program PPRx.DZI to determine the Dead Zone

interval. The Dead Zone generator behavior is demonstrated in Figure 5-30 Paired-PWM Output with

Dead Zone Generation Operation.

PWM-Timer

Output 0

PWM-Timer

Inversed output

1

Dead-Zone

Generator output 0

Dead-Zone

Generator output 1

Dead zone interval

Figure 5-30 Paired-PWM Output with Dead Zone Generation Operation

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Revision 2.4


5.7.8 Capture Timer Operation

Instead of using the PWM generator to output a modulated signal, it can be configured as a capture timer to measure a modulated input. Capture channel 0 and PWM0CH0 share one timer and Capture channel 1 and PWM0CH1 share another timer. The capture timer latches PWM-counter to RCAPDAT when input channel has a rising transition and latches PWM-counter to PWM_FCAPDATx when input channel has a falling transition. Capture channel 0 interrupt is programmable by setting

PWM_CAPCTL01[1] (Rising latch Interrupt enable) and PWM_CAPCTL01[2] (Falling latch Interrupt enable) to decide the condition of interrupt occurrence. Capture channel 1 has the same feature by setting PWM_CAPCTL01[17] and PWM_CAPCTL01[18]. Whenever the Capture module issues a capture interrupt, the corresponding PWM counter will be reloaded with PERIODx at this moment. Note that the corresponding GPIO pins must be configured as their alternate function before Capture function is enabled.

PWM Counter

Capture Input x

3 2 1 8 7 6 5

Reload

(If CNRx = 8)

8 7 6 5 4

Reload

No reload due to no CAPIFx

CAPCHxEN

CFLRx

CRLRx

1

5

7

CFL_IEx

CRL_IEx

Clear by S/W

CAPIFx

Set by H/W

Set by H/W Clear by S/W

CFLRIx

Set by H/W Clear by S/W

CRLRIx

Note: X=0~1

Figure 5-31 Capture Operation Timing

Figure 5-31 Capture Operation Timing demonstrates the case where PERIOD = 8:

1. The PWM counter will be reloaded with PERIODx=8 when a capture interrupt flag (CAPIFx) is set by a transition on the capture input.

2. The channel low pulse width is given by (PERIOD- RCAPDAT).

3. The channel high pulse width is given by (PERIOD - FCAPDAT).

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Revision 2.4


5.7.9 PWM-Timer Interrupt Architecture

There are two PWM interrupts, PWM0_INT, PWM1_INT, which are multiplexed into PWM0_IRQ. PWM

0 and Capture 0 share one interrupt, PWM1 and Capture 1 share the same interrupt. Figure 5-32 PWM-

Timer Interrupt Architecture Diagram demonstrates the architecture of PWM-Timer interrupts.

PWMIF0

CAPIF0

PWMIF1

CAPIF1

PWM0_INT

PWM1_INT

PWMA_IRQ

Figure 5-32 PWM-Timer Interrupt Architecture Diagram

5.7.10 PWM-Timer Initialization Procedure

The following procedure is recommended for starting a PWM generator.

1. Setup clock selector (PWM_CLKDIV)

2. Setup prescaler (PWM_CLKPSC)

3. Setup inverter on/off, dead zone generator on/off, auto-reload/one-shot mode and Stop PWMtimer (PWM_CTL)

4. Setup comparator register (PWM_CMPDAT)to set PWM duty cycle.

5. Setup PWM down-counter register (PWM_PERIOD) to set PWM period.

6. Setup interrupt enable register (PWM_INTEN)

7. Setup PWM output enable (PWM_POEN)

8. Setup the corresponding GPIO pins to PWM function (SYS_GPA_MFP)

9. Enable PWM timer start (Set CNTENx = 1 in PWM_CTL)

5.7.11 PWM-Timer Stop Procedure

•

Method 1:

Set 16-bit down counter (PWMx_PERIODx) as 0, and monitor PWMx_CNTx (current value of 16-bit down-counter). When PWMx_CNTx reaches to 0, disable PWM-Timer (CNTENx in PWMx_CTL).

(Recommended)

•

Method 2:

Set 16-bit down counter (PWMx_PERIODx) as 0. When interrupt request occurs, disable PWM-Timer

(CNTENx in PWMx_CTL). (Recommended)

•

Method 3:

Disable PWM-Timer directly (CNTENx in PWMx_CTL). (Not recommended)

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Revision 2.4


•

4.

5.

6.

7.

5.7.12 Capture Start Procedure

1. Setup clock selector (PWM_CLKDIV)

2. Setup prescaler (PWM_CLKPSC)

3. Setup channel enable, rising/falling interrupt enable and input signal inverter on/off

(PWM_CAPCTL01, PWM_CAPCTL23)

Setup PWM down-counter (PERIOD)

Set Capture Input Enable Register (PWM_CAPINEN)

Setup the corresponding GPIO pins to PWM function (SYS_GPA_MFP)

Enable PWM timer start running (Set CNTENx = 1 in PWM_CTL)

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Revision 2.4





PWM_CLKPSC

Offset

PWM Base Address:

PWM_BA = 0x4004_0000

PWM_BA+0x000

PWM_CLKDIV

PWM_BA+0x004

PWM_CTL PWM_BA+0x008

PWM_PERIOD0 PWM_BA+0x00C

PWM_CMPDAT0 PWM_BA+0x010

PWM_CNT0 PWM_BA+0x014

PWM_PERIOD1 PWM_BA+0x018

PWM_CMPDAT1 PWM_BA+0x01C

PWM_CNT1

PWM_BA+0x020



PWM_CNT2 PWM_BA+0x02C



PWM_CNT3 PWM_BA+0x038

PWM_INTEN

PWM_BA+0x040

PWM_INTSTS PWM_BA+0x044

PWM_CAPCTL01

PWM_BA+0x050

PWM_CAPCTL23

PWM_RCAPDAT0

PWM_FCAPDAT0

PWM_RCAPDAT1

PWM_BA+0x054

PWM_BA+0x058

PWM_BA+0x05C

PWM_BA+0x060

R/W PWM Prescaler Register

R/W PWM Clock Select Register

R/W PWM Control Register

R/W PWM Counter Register 0

R/W PWM Comparator Register 0

R PWM Data Register 0










R/W PWM Interrupt Enable Register

R/W PWM Interrupt Flag Register

R/W Capture Control Register For Pair Of PWM0CH0

And PWM0CH1

R/W Capture Control Register For Pair Of PWM0CH2

And PWM0CH3

R Capture Rising Latch Register (Channel 0)

R Capture Falling Latch Register (Channel 0)


PWM_FCAPDAT1

PWM_RCAPDAT2

PWM_BA+0x064

PWM_BA+0x068



PWM_FCAPDAT2

PWM_RCAPDAT3

PWM_BA+0x06C

PWM_BA+0x070



Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

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Revision 2.4


PWM_FCAPDAT3

PWM_CAPINEN

PWM_POEN

PWM_BA+0x074

PWM_BA+0x078

PWM_BA+0x07C


R/W Capture Input Enable Register

R/W PWM0 Output Enable Register for CH0~CH3

0x0000_0000

0x0000_0000

0x0000_0000

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Revision 2.4



PWM Pre-Scale Register (PWM_CLKPSC)


PWM_CLKPSC PWM_BA+0x000 R/W PWM Prescaler Register

31

23

15

7

30

22

14

6

29

21

13

5

28 27

DTCNT23

20 19

DTCNT01

12

CLKPSC23

11

4 3

CLKPSC01

Bits

[31:24]

[23:16]

[15:8]

[7:0]

26

18

10

2

25

17

9

1

Reset Value

0x0000_0000

Table 5-62 PWM Pre-Scaler Register (PWM_CLKPSC, address 0x4004_0000).

Description

DTCNT23

DTCNT01

CLKPSC23

CLKPSC01

Dead Zone Interval Register for Pair of PWM0CH2 and PWM0CH3

These 8 bits determine dead zone length.

The unit time of dead zone length is that from clock selector 0.

Dead Zone Interval Register for Pair of PWM0CH0 and PWM0CH1

These 8 bits determine dead zone length.

The unit time of dead zone length is that from clock selector 0.

Clock Pre-scaler for Pair of PWM0CH2 and PWM0CH3

Clock input is divided by (CLKPSC23 + 1)

If CLKPSC23 = 0, then the pre-scaler output clock will be stopped.

This implies PWM counter 2 and 3 will also be stopped.

Clock Pre-scaler Pair of PWM0CH0 and PWM0CH1

Clock input is divided by (CLKPSC01 + 1)

If CLKPSC01 = 0, then the pre-scaler output clock will be stopped.

This implies PWM counter 0 and 1 will also be stopped.

24

16

8

0

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Revision 2.4


PWM Clock Select Register (PWM_CLKDIV)


PWM_CLKDIV PWM_BA+0x004 R/W PWM Clock Select Register

15

Reserved

7

Reserved

14

6

13

CLKDIV3

5

CLKDIV1

12

4

11

Reserved

3

Reserved

Bits

[31:15]

[14:12]

[11]

[10:8]

[7]

[6:4]

[3]

[2:0]

10

2

9

CLKDIV2

1

CLKDIV0

Reset Value

0x0000_0000

Table 5-63 PWM Clock Select Register (PWM_CLKDIV, address 0x4004_0004).

Description

Reserved

CLKDIV3

Reserved

CLKDIV2

Reserved

CLKDIV1

Reserved

CLKDIV0

Reserved.

Timer 3 Clock Source Selection

(Table is as CLKDIV0)

Reserved.



Reserved.



Reserved.


Value : Input clock divided by

0 : 2

1 : 4

2 : 8

3 : 16

4 : 1

8

0

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Revision 2.4


PWM Control Register (PWM_CTL)

Register

PWM_CTL


PWM_BA+0x008 R/W PWM Control Register

31 30 29

Reserved

23 22 21

Reserved

15 14 13

7

Reserved

6

Reserved

5

DTEN23

28

20

12

4

DTEN01

27

CNTMODE3

19

CNTMODE2

11

CNTMODE1

3

CNTMODE0

Bits

[31:28]

[27]

[26]

[25]

[24]

[23:20]

[19]

[18]

[16]

26

PINV3

18

PINV2

10

PINV1

2

PINV0

25

Reserved

17

Reserved

9

Reserved

1

Reserved

Reset Value

0x0000_0000

Table 5-64 PWM Control Register (PWM_CTL, address 0x4004_008).

Description

Reserved

CNTMODE3

PINV3

Reserved

CNTEN3

Reserved

CNTMODE2

PINV2

CNTEN2

Reserved.

PWM-timer 3 Auto-reload/One-shot Mode

0 = One-Shot Mode.

1 = Auto-load Mode.

Note: A rising transition of this bit will cause PWM_PERIOD3 and PWM_CMPDAT3 to be cleared.

PWM-timer 3 Output Inverter ON/OFF

0 = Inverter OFF.

1 = Inverter ON.

Reserved.

PWM-timer 3 Enable/Disable Start Run

0 = Stop PWM-Timer 3.

1 = Enable PWM-Timer 3 Start/Run.

Reserved.


0 = One-Shot Mode.

1 = Auto-load Mode.



0 = Inverter OFF.

1 = Inverter ON.




24

CNTEN3

16

CNTEN2

8

CNTEN1

0

CNTEN0

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Revision 2.4

[2]

[1]

[0]

[10]

[9]

[8]

[7:6]

[5]

[15:12]

[11]

[4]

[3]

PINV1

Reserved

CNTEN1

Reserved

DTEN23

Reserved

CNTMODE1

DTEN01

CNTMODE0

PINV0

Reserved

CNTEN0


Reserved.


0 = One-Shot Mode.

1 = Auto-load Mode.



0 = Inverter OFF.

1 = Inverter ON.

Reserved.




Reserved.

Dead-zone 23 Generator Enable/Disable Pair of PWM0CH2 and PWM0CH3

0 = Disable.

1 = Enable.

Note: When Dead-Zone Generator is enabled, the pair of PWM0CH2 and

PWM0CH3 become a complementary pair.

Dead-zone 01 Generator Enable/Disable Pair of PWM0CH0 and PWM0CH1

0 = Disable.

1 = Enable.

Note: When Dead-Zone Generator is enabled, the pair of PWM0CH0 and

PWM0CH1 become a complementary pair.


0 = One-Shot Mode.

1 = Auto-reload Mode.



0 = Inverter OFF.

1 = Inverter ON.

Reserved.


0 = Stop PWM-Timer 0 Running.


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Revision 2.4


PWM Counter Register 1-0 (PWM_PERIOD1-0)


PWM_PERIOD0 PWM_BA+0x00C R/W PWM Counter Register 0

Reset Value

0x0000_0000

PWM_PERIOD1 PWM_BA+0x018 R/W PWM Counter Register 1


0x0000_0000

0x0000_0000


31

23

15

7

30

22

14

6

29

21

13

5

28 27

Reserved

20 19

Reserved

12 11

PERIOD [15:8]

4 3

PERIOD [7:0]

26

18

10

2

25

17

9

1

0x0000_0000

Table 5-65 PWM Counter Register (PWM_PERIODx, address 0x4004_00C+C*x).

24

16

8

0

Bits

[31:16]

Description

Reserved

[15:0] PERIOD

Reserved.

PWM Counter/Timer Reload Value

PERIOD determines the PWM period.

PWM frequency = PWM0CHx_CLK/(prescale+1)*(clock divider)/(PERIOD+1);.

Duty ratio = (CMP+1)/(PERIOD+1).

CMP > = PERIOD: PWM output is always high.

CMP < PERIOD: PWM low width = (PERIOD-CMP) unit; PWM high width =

(CMP+1) unit.

CMP = 0: PWM low width = (PERIOD) unit; PWM high width = 1 unit.

(Unit = one PWM clock cycle).

Note:

Any write to PERIOD will take effect in next PWM cycle.

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Revision 2.4


PWM Comparator Register 1-0 (PWM_CMPDAT)


PWM_CMPDAT0 PWM_BA+0x010 R/W PWM Comparator Register 0

Reset Value

0x0000_0000

PWM_CMPDAT1 PWM_BA+0x01C R/W PWM Comparator Register 1


0x0000_0000

0x0000_0000


31 30 29 28 27

Reserved

23 22 21 20 19

Reserved

15 14 13 12 11

CMP[15:8]

7 6 5 4 3

CMP[7:0]

26

18

10

2

25

17

9

1

0x0000_0000

24

16

8

0

Table 5-66 PWM Comparator Register (PWM_CMPDATx, address 0x4004_0010 + C*x).

Bits

[31:16]

Description

Reserved

[15:0] CMP

Reserved.

PWM Comparator Register

CMP determines the PWM duty cycle.

PWM frequency = PWM0CHx_CLK/(prescale+1)*(clock divider)/(PERIOD+1);.

Duty Cycle = (CMP+1)/(PERIOD+1).

CMP > = PERIOD: PWM output is always high.

CMP < PERIOD: PWM low width = (PERIOD-CMP) unit; PWM high width =

(CMP+1) unit.

CMP = 0: PWM low width = (PERIOD) unit; PWM high width = 1 unit.

(Unit = one PWM clock cycle).

Note: Any write to CMP will take effect in next PWM cycle.

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Revision 2.4


PWM Data Register 1-0 (PWM_CNT)

Register

PWM_CNT0


PWM_BA+0x014 R PWM Data Register 0

PWM_CNT1

PWM_CNT2

PWM_CNT3

15

7

PWM_BA+0x020 R

PWM_BA+0x02C R

PWM_BA+0x038 R

14

6

13

5

PWM Data Register 1

PWM Data Register 2

PWM Data Register 3

12

CNT[15:8]

11

4 3

CNT[7:0]

Bits

[31:16]

[15:0]

10

2

9

1

Table 5-67 PWM Data Register (PWM_CNTx, address 0x4004_0014 + C*x).

Description

Reserved

CNT

Reserved.

PWM Data Register

Reports the current value of the 16-bit down counter.

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

8

0

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Revision 2.4


PWM Interrupt Enable Register (PWM_INTEN)

Register

PWM_INTEN


PWM_BA+0x040 R/W PWM Interrupt Enable Register

7 6

Reserved

5 4 3

PIEN3

Bits

[31:4]

[3]

[2]

[1]

[0]

2

PIEN2

1

PIEN1

Reset Value

0x0000_0000

Table 5-68 PWM Interrupt Enable Register (PWM_INTEN, address 0x4004_0040).

Description

Reserved

PIEN3

PIEN2

PIEN1

PIEN0

Reserved.

PWM Timer 3 Interrupt Enable

0 = Disable.

1 = Enable.


0 = Disable.

1 = Enable.


0 = Disable.

1 = Enable.


0 = Disable.

1 = Enable.

0

PIEN0

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Revision 2.4


PWM Interrupt Flag Register (PWM_INTSTS)

Register

PWM_INTSTS


PWM_BA+0x044 R/W PWM Interrupt Flag Register

7 6

Reserved

5 4 3

PIF3

2

PIF2

1

PIF1

Reset Value

0x0000_0000

Table 5-69 PWM Interrupt Flag Register (PWM_INTSTS, address 0x4004_0044).

0

PIF0

Bits

[31:4]

Description

Reserved Reserved.

[3]

[2]

[1]

PIF3

PIF2

PIF1

PWM Timer 3 Interrupt Flag

Flag is set by hardware when PWM0CH3 down counter reaches zero, software can clear this bit by writing ‘1’ to it.





[0] PIF0



Note: User can clear each interrupt flag by writing a one to corresponding bit in PWM_INTSTS.

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Revision 2.4


Capture Control Register (PWM_CAPCTL01)


PWM_CAPCTL01 PWM_BA+0x050 R/W Capture Control Register For Pair Of PWM0CH0 And

PWM0CH1

31 30 29 26

23

CFLIF1

15

7

CFLIF0

22

CRLIF1

14

6

CRLIF0

21

Reserved

13

5

Reserved

28 27

Reserved

20

CAPIF1

12

19

CAPEN1

Reserved

11

4

CAPIF0

3

CAPEN0

18

CFLIEN1

10

2

CFLIEN0

25

17

CRLIEN1

9

1

CRLIEN0

Reset Value

0x0000_0000

24

16

CAPINV1

8

0

CAPINV0

Table 5-70 Capture Control Register (PWM0_CAPCTL01, address 0x4004_0050).

Bits

[31:24]

Description

Reserved

[23]

[22]

[20]

[19]

[18]

[17]

CFLIF1

CRLIF1

CAPIF1

CAPEN1

CFLIEN1

CRLIEN1

Reserved.

PWM_FCAPDAT1 Latched Indicator Bit

When input channel 1 has a falling transition, PWM_FCAPDAT1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.

PWM_RCAPDAT1 Latched Indicator Bit

When input channel 1 has a rising transition, PWM_RCAPDAT1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.

Capture1 Interrupt Indication Flag

If channel 1 rising latch interrupt is enabled (CRLIEN1 = 1), a rising transition at input channel 1 will result in CAPIF1 to high; Similarly, a falling transition will cause

CAPIF1 to be set high if channel 1 falling latch interrupt is enabled (CFLIEN1 = 1).

This flag is cleared by software writing a ‘1’ to it.

Capture Channel 1 Transition Enable/Disable

0 = Disable capture function on channel 1.

1 = Enable capture function on channel 1.

When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition.

When disabled, Capture function is inactive as is interrupt.

Channel 1 Falling Latch Interrupt Enable

0 = Disable falling edge latch interrupt.

1 = Enable falling edge latch interrupt.

When enabled, capture block generates an interrupt on falling edge of input.

Channel 1 Rising Latch Interrupt Enable

0 = Disable rising edge latch interrupt.

1 = Enable rising edge latch interrupt.

When enabled, capture block generates an interrupt on rising edge of input.

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Revision 2.4

[0]

[16]

[15:8]

[7]

[6]

[4]

[3]

[2]

[1]

CAPINV1

Reserved

CFLIF0

CRLIF0

CAPIF0

CAPEN0

CFLIEN0

CRLIEN0

CAPINV0


Channel 1 Inverter ON/OFF

0 = Inverter OFF.

1 = Inverter ON. Reverse the input signal from GPIO before Capture timer

Reserved.














Channel 0 Falling Latch Interrupt Enable ON/OFF

0 = Disable falling latch interrupt.

1 = Enable falling latch interrupt.


Channel 0 Rising Latch Interrupt Enable ON/OFF

0 = Disable rising latch interrupt.

1 = Enable rising latch interrupt.



0 = Inverter OFF.


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Revision 2.4


Capture Control Register (PWM_CAPCTL23)


PWM_CAPCTL23 PWM_BA+0x054 R/W Capture Control Register For Pair Of PWM0CH2 And

PWM0CH3

31 30 29 26

23

CFLIF3

15

7

CFLIF2

22

CRLIF3

14

6

CRLIF2

21

Reserved

13

5

Reserved

28 27

Reserved

20

CAPIF3

12

19

CAPEN3

Reserved

11

4

CAPIF2

3

CAPEN2

18

CFLIEN3

10

2

CFLIEN2

25

17

CRLIEN3

9

1

CRLIEN2

Reset Value

0x0000_0000

24

16

CAPINV3

8

0

CAPINV2

Table 5-71 Capture Control Register (PWM_CAPCTL23, address 0x4004_0050).

Bits

[31:24]

Description

Reserved

[23]

[22]

[21]

[20]

[19]

[18]

CFLIF3

CRLIF3

Reserved

CAPIF3

CAPEN3

CFLIEN3

Reserved.





Reserved.










Channel 3 Falling Latch Interrupt Enable

0 = Disable falling edge latch interrupt.

1 = Enable falling edge latch interrupt.


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Revision 2.4

[0]

[6]

[5]

[4]

[17]

[16]

[15:8]

[7]

[3]

[2]

[1]

CRLIEN3

CAPINV3

Reserved

CFLIF2

CRLIF2

Reserved

CAPIF2

CAPEN2

CFLIEN2

CRLIEN2

CAPINV2


Channel 3 Rising Latch Interrupt Enable

0 = Disable rising edge latch interrupt.

1 = Enable rising edge latch interrupt.



0 = Inverter OFF.


Reserved.





Reserved.










Channel 2 Falling Latch Interrupt Enable ON/OFF

0 = Disable falling latch interrupt.

1 = Enable falling latch interrupt.


Channel 2 Rising Latch Interrupt Enable ON/OFF

0 = Disable rising latch interrupt.

1 = Enable rising latch interrupt.



0 = Inverter OFF.


- 193 -


Revision 2.4


Capture Rising Latch Register n (PWM_RCAPDATn)


PWM_RCAPDAT0 PWM_BA+0x058 R Capture Rising Latch Register (Channel 0)

PWM_RCAPDAT1 PWM_BA+0x060 R



Capture Rising Latch Register (Channel 1)



Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

15

7

14

6

13

5

12 11

RCAPDAT[15:8]

4 3

RCAPDAT[7:0]

10

2

9

1

8

0

Bits

[31:16]

[15:0]

Table 5-72 Capture Rising Latch Register (PWM_RCAPDATx, address 0x4004_0058 +C*x).

Description

Reserved

RCAPDAT

Reserved.

Capture Rising Latch Register

In Capture mode, this register is latched with the value of the PWM counter on a rising edge of the input signal.

- 194 -


Revision 2.4


Capture Falling Latch Register n(PWM_FCAPDATn)


PWM_FCAPDAT0 PWM_BA+0x05C R Capture Falling Latch Register (Channel 0)

Reset Value

0x0000_0000

PWM_FCAPDAT1 PWM_BA+0x064 R

PWM_FCAPDAT2 PWM_BA+0x06C R

PWM_FCAPDAT3 PWM_BA+0x074 R

Capture Falling Latch Register (Channel 1)



0x0000_0000

0x0000_0000

0x0000_0000

15

7

14

6

13

5

12 11

FCAPDAT[15:8]

4 3

FCAPDAT[7:0]

10

2

9

1

8

0

Table 5-73 Capture Falling Latch Register (PWM_FCAPDATx, address 0x4004_005C + C*x).

Bits

[31:16]

Description

Reserved

[15:0] FCAPDAT

Reserved.

Capture Falling Latch Register

In Capture mode, this register is latched with the value of the PWM counter on a falling edge of the input signal.

- 195 -


Revision 2.4


Capture Input Enable Register (PWM_CAPINEN)


PWM_CAPINEN PWM_BA+0x078 R/W Capture Input Enable Register

7 6 5 4 3

Reserved

Bits

[31:4]

[3:0]

2

CAPINEN[3:0]

1

Reset Value

0x0000_0000

0

Table 5-74 Capture Input Enable Register (PWM_CAPINEN, address 0x4004_0078).

Description

Reserved

CAPINEN

Reserved.

Capture Input Enable Register

0 : OFF (GPA[13:12], GPB[15:14] pin input disconnected from Capture block)

1 : ON (GPA[13:12] , GPB[15:14] pin, if in PWM alternative function, will be configured as an input and fed to capture function)

CAPINEN[3:0]

Bit [3][2][1][0]

Bit xxx1 : Capture channel 0 is from GPA [12]

Bit xx1x : Capture channel 1 is from GPA [13]

Bit x1xx : Capture channel 2 is from GPB [14]

Bit 1xxx : Capture channel 3 is from GPB [15]

- 196 -


Revision 2.4


PWM Output Enable Register (PWM_POEN)

Register

PWM_POEN


PWM_BA+0x07C R/W PWM0 Output Enable Register for CH0~CH3

7 6

Reserved

5 4 3

POEN3

2

POEN2

Bits

[31:4]

[3]

[2]

[1]

[0]

1

POEN1

Reset Value

0x0000_0000

0

POEN0

Table 5-75 PWM Output Enable (PWM_POEN, address 0x4004_007C).

Description

Reserved

POEN3

POEN2

POEN1

POEN0

Reserved.

PWM0CH3 Output Enable Register

0 = Disable PWM0CH3 output to pin.

1 = Enable PWM0CH3 output to pin.

Note: The corresponding GPIO pin also must be switched to PWM function (refer to

SYS_GPA_MFP)





SYS_GPA_MFP)





SYS_GPA_MFP)



1 = Enable PWM0CH 0 output to pin.


SYS_GPA_MFP)

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Revision 2.4


5.8 Real Time Clock (RTC)

Overview

Real Time Clock (RTC) unit provides real time clock, calendar and alarm functions. The clock source of the RTC is an external 32.768 kHz crystal connected at pins XI32K and XO32K or from an external

32.768 kHz oscillator output fed to pin XI32K. The RTC unit provides the time (second, minute, hour) in

Time Load Register (RTC_TIME) as well as calendar (day, month, year) in Calendar Load Register

(RTC_CAL). The data is expressed in BCD (Binary Coded Decimal) format. The unit offers an alarm function whereby the user can preset the alarm time in the Time Alarm Register (RTC_TALM) and alarm calendar in Calendar Alarm Register (RTC_CALM).

The RTC unit supports periodic Time-Tick and Alarm-Match interrupts. The periodic interrupt has 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second which are selected by

RTC_TICK.TTR. When RTC counter in RTC_TIME and RTC_CAL is equal to alarm setting registers

RTC_TALM and RTC_CALM, the alarm interrupt flag (RTC_INTSTS.ALMIF) is set and the alarm interrupt is requested if the alarm interrupt is enabled (RTC_INTEN.ALMIEN=1). The RTC Time Tick and Alarm Match can wake the CPU from sleep mode or Standby Power-Down (SPD) mode if the

Wakeup CPU function is enabled (RTC_TICK.TWKEN=1).

5.8.1 RTC Features

 Consists of a time counter (second, minute, hour) and calendar counter (day, month, year).

 Alarm register (second, minute, hour, day, month, year).

 12-hour or 24-hour mode is selectable.

 Automatic leap year compensation.

 Day of week counter.

 Frequency compensate register (FCR).

 All time and calendar registers are expressed in BCD code.

 Support periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and

1 second.

 Support RTC Time-Tick and Alarm-Match interrupt

 Support CPU wakeup from sleep or standby power-down mode.

- 198 -


Revision 2.4


5.8.2 RTC Block Diagram

Time Alarm

Register (TAR)

Calendar Alarm

Register (CAR)

Compare

Operation

ALMIEN(INTEN[0])

ALMIF(INTSTS[0]) Alarm

Interrupt

Leap Year Indicator (LIP)

TSSR.24Hr/12Hr

Day of Week

(DWR)

Initiation/Enable

(INIR/AER)

Clock Source

32776 ~32761

Time Load

Register (TLR)

Calendar Load

Register (CLR)

RTC Time Counter

Control Unit

Frequency

Compensation

Wakeup CPU from

Power-down mode

(sec)

1/128 change

1/64 change

1/32 change

1/16 change

1/8 change

1/4 change

1/2 change

1 change

011

010

001

000

111

110

101

100

TWKEN(TICK[3])

TICKIEN(INTEN[1])

TICKIF(INTSTS[1])

Periodic

Interrupt

RTC_TICK[2:0]

Frequency

Compensation

Register (FCR)

Figure 5-33 RTC Block Diagram

5.8.3 RTC Function Description

5.8.3.1 Access to RTC register

Due to clock frequency difference between RTC clock and system clock, when the user writes new data to any one of the RTC registers, the register will not be updated until 2 RTC clock periods later (60us).

The programmer should take this into consideration for determining access sequence between

RTC_CLKFMT, RTC_TALM and RTC_TIME.

In addition, the RTC block does not check whether written data is out of bounds for a valid BCD time or calendar load. RTC does not check validity of RTC_WEEKDAY and RTC_CAL write either.

5.8.3.2 RTC Initiation

When RTC block is powered on, programmer must write 0xA5EB1357 to RTC_INIT register to reset all logic. RTC_INIT acts as a hardware reset circuit. Once RTC_INIT has been set to0xA5EB1357, internal reset operation begins. When reset operation is finished, RTC_INIT[0] is set by hardware and RTC is ready for operation.

5.8.3.3 RTC Read/Write Enable

Register RTC_RWEN[15:0] serves as the RTC read/write password to protect RTC registers.

RTC_RWEN[15:0] have to be set to 0xA965 to enable access. Once set, it will take effect 512 RTC clocks later (about 15ms). Programmer can read RTC enabled status flag in RTC_RWEN.ENF to check whether RTC is access enabled. Access is automatically cleared after 200ms.

5.8.3.4 Frequency Compensation

The RTC Frequency Compensation Register (RTC_FREQADJ)allows software to configure digital compensation to the 32768Hz clock input. The RTC_FREQADJ allows compensation of a clock input in the range from 32761Hz to 32776Hz. If desired, RTC clock can be measured during manufacture from a GPIO pin and compensation value calculated and stored in flash memory for retrieval when the product is first powered on. Following are compensation examples for a higher or lower measured frequency clock input.

- 199 -


Revision 2.4


Table 5-76 RTC Frequency Compensation Example

Example 1:

Frequency Counter Measurement : 32773.65Hz ( > 32768 Hz)

Integer Part: 32773 = 0x8005

RTC_FREQADJ. INTEGER= (32773 – 32761) = 12 = 0x0C

Fractional Part: 0.65 X 60 = 39 = 0x27

RTC_FREQADJ. FRACTION= 0x27

Example 2

Frequency counter measurement : 32765.27Hz ( < 32768 Hz)

Integer part: 32765 = 0x7ffd

RTC_FREQADJ.INTEGER = (32765 – 32761) = 4 = 0x04

Fractional part: 0.27 x 60 = 16.2 = 0x10

RTC_FREQADJ.FRACTION = 0x10

5.8.3.5 Time and Calendar counter

RTC_TIME and RTC_CAL are used to load the time and calendar. RTC_TALM and RTC_CALM are used to set the alarm. They are all represented by a BCD format, see register descriptions for digit assignments.

5.8.3.6 12/24 hour Time Scale Selection

RTC can be selected to report time in either a 12 or 24hour time scale. If 12 hour mode is selected then

AM/PM indication is provided by the hour digit being >=2, see register description RTC_CLKFMT for details. The 12/24 hour time scale selection depends on RTC_CLKFMT.24HEN.

5.8.3.7 Day of the week counter

The RTC unit provides day of week in Day of the Week Register (RTC_WEEKDAY). The value is defined from 0 to 6 to represent Sunday to Saturday respectively.

5.8.3.8 Periodic Time Tick Interrupt

The periodic interrupt has 8 period option 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second which are selected by RTC_TICK.TICKSEL[2:0]. When periodic time tick interrupt is enabled by setting

RTC_INTEN.TICKEN to 1, the Periodic Time Tick Interrupt is requested as selected by RTC_TICK register.

5.8.3.9 Alarm Time Interrupt

When RTC counter in RTC_TIME and RTC_CAL is equal to alarm setting in RTC_TALM and

RTC_CALM the alarm interrupt flag (RTC_INTSTS.ALMIF) is set. If alarm interrupt is enabled

(RTC_INTEN.ALMIEN=1) the alarm interrupt is also requested.

5.8.3.10 Additional Notes

1. RTC_TALM, RTC_CALM, RTC_TIME and RTC_CAL registers are all BCD counter.

2. Programmer has to make sure that values loaded are reasonable. For example, some invalid

RTC_CAL values would be 201a (year), 13 (month), 00 (day).

3. Reset state :

Register

RTC_RWEN

RTC_CAL

RTC_TIME

RTC_CALM

Reset State

0

05/1/1 (year/month/day)

00:00:00 (hour : minute : second)

00/00/00 (year/month/day)

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Revision 2.4


RTC_TALM

RTC_CLKFMT

RTC_WEEKDAY

RTC_INTEN

00:00:00 (hour : minute : second)

1 (24 hr. mode)

6 (Saturday)

RTC_INTSTS

RTC_LEAPYEAR

RTC_TICK

0

0

0

0

PWRTOUT 5555

4. In RTC_TIME and RTC_TALM, only 2 BCD digits are used to express “year”. It is assumed that 2

BCD digits of xY denote 20xY, but not 19xY or 21xY.

- 201 -


Revision 2.4



R : read only, W : write only, R/W : both read and write, C : Only value 0 can be written

R/W Description Reset Value Register Offset

RTC Base Address:

RTC_BA = 0x4000_8000

RTC_INIT RTC_BA+0x000

RTC_RWEN RTC_BA+0x004

RTC_BA+0x008 RTC_FREQADJ

RTC_TIME RTC_BA+0x00C

R/W RTC Initialization Register

R/W RTC Access Enable Register

R/W RTC Frequency Compensation Register

R/W Time Load Register

0x0000_0000

0x0000_0000

0x0000_0700

0x0000_0000

RTC_CAL

RTC_CLKFMT

RTC_WEEKDAY

RTC_TALM

RTC_CALM

RTC_LEAPYEAR

RTC_INTEN

RTC_INTSTS

RTC_TICK

RTC_BA+0x010

RTC_BA+0x014

RTC_BA+0x018

RTC_BA+0x01C

RTC_BA+0x020

RTC_BA+0x024

RTC_BA+0x028

RTC_BA+0x02C

RTC_BA+0x030

R/W Calendar Load Register

R/W Time Scale Selection Register

R/W Day of the Week Register

R/W Time Alarm Register

R/W Calendar Alarm Register

R Leap year Indicator Register

R/W RTC Interrupt Enable Register

R/W RTC Interrupt Indicator Register

R/W RTC Time Tick Register

0x0000_0000

0x0000_0001

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

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Revision 2.4



RTC Initiation Register (RTC_INIT)


RTC_INIT

31

RTC_BA+0x000 R/W RTC Initialization Register

30 29 28 27

INIT

23 22 21 20 19

INIT

15 14 13 12 11

INIT

7 6 5 4

INIT

3

Bits

[31:1]

[0]

26

18

10

2

25

17

9

1

Reset Value

0x0000_0000

24

16

8

0

ATVSTS

Table 5-77 RTC Initialization Register (RTC_INIT, address 0x4000_8000).

Description

INIT

ATVSTS

RTC Initialization

After a power-on reset (POR) RTC block should be initialized by writing

0xA5EB1357 to INIT. This will force a hardware reset then release all logic and counters.

RTC Active Status (Read Only)

0: RTC is in reset state

1: RTC is in normal active state.

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Revision 2.4


RTC Access Enable Register (RTC_RWEN)

Register

RTC_RWEN


RTC_BA+0x004 R/W RTC Access Enable Register

23

15

7

22

14

6

21

13

5

20 19

Reserved

12

RWEN

11

4 3

RWEN

Bits

[31:17]

[16]

[15:0]

18

10

2

17

9

1

Reset Value

0x0000_0000

16

RWENF

8

0

Table 5-78 RTC Access Enable Register (RTC_RWEN, address 0x4000_8004).

Description

Reserved Reserved.

RWENF

RWEN

RTC Register Access Enable Flag (Read Only)

1 = RTC register read/write enable.

0 = RTC register read/write disable.

This bit will be set after RWEN[15:0] register is set to 0xA965, it will clear automatically in 512 RTC clock cycles or RWEN[15:0] ! = 0xA965. The effect of RTC_RWEN.RWENF is as the below.

Table 5-79 RTC_RWEN.RWENF Register Access Effect.

Register : RWENF = 1 : RWENF = 0.

RTC_INIT : R/W : R/W

RTC_FREQADJ : R/W : -

RTC_TIME : R/W : R

RTC_CAL : R/W : R

RTC_CLKFMT : R/W : R/W

RTC_WEEKDAY : R/W : R

RTC_TALM : R/W : -

RTC_CALM : R/W : -

RTC_LEAPYEAR : R : R

RTC_INTEN : R/W : R/W

RTC_INTSTS : R/W : R/W

RTC_TICK : R/W : -

RTC Register Access Enable Password (Write Only)

0xA965 = Enable RTC acces..s

Others = Disable RTC acces..s

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Revision 2.4


RTC Frequency Compensation Register (RTC_FREQADJ)


RTC_FREQADJ RTC_BA+0x008 R/W RTC Frequency Compensation Register

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved INTEGER

25

17

9

7 6 5 4 3 2 1

Reserved FRACTION

Reset Value

0x0000_0700

24

16

8

0

Table 5-80 RTC Frequency Compensation Register (RTC_FREQADJ, address 0x4000_8008).


Reserved [31:12]

[11:8] INTEGER

Reserved.

Integer Part

Register should contain the value (INT(F actual

) – 32761)

Ex: Integer part of detected value = 32772,.

RTC_FREQADJ.INTEGER = 32772-32761 = 11 (..1011b)

The range between 32761 and 32776

Reserved. [7:6] Reserved

[5:0] FRACTION

Fractional Part

Formula = (fraction part of detected value) x 60.

Refer to Table 5-76 RTC Frequency Compensation Example

f

or the examples.

Note: This register can be read back after the RTC enable is active.

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Revision 2.4


RTC Time Load Register (RTC_TIME)

This register is Read Only until access enable password is written to RTC_RWEN register. The register returns the current time.

Register

RTC_TIME


RTC_BA+0x00C R/W Time Load Register

Reset Value

0x0000_0000

23 22

Reserved

15

Reserved

7

Reserved

14

6

21 20

13

TENMIN

5

TENHR

TENSEC

12

4

19

11

3

18

10

2

HR

MIN

SEC

17

9

1

Table 5-81 RTC Time Load Register (RTC_TIME, address 0x4000_800C).

Bits

[31:22]

[21:20]

[19:16]

[15]

[14:12]

[11:8]

[7]

Description

Reserved

TENHR

HR

Reserved

TENMIN

MIN

Reserved

TENSEC

Reserved.

10 Hour Time Digit (0~3)

1 Hour Time Digit (0~9)

Reserved.

10 Min Time Digit (0~5)

1 Min Time Digit (0~9)

Reserved.

[6:4] 10 Sec Time Digit (0~5)

[3:0] SEC 1 Sec Time Digit (0~9)

Note:

1.

RTC_TIME is a BCD counter and RTC will not check loaded data for validity.

2.

Valid range is listed in the parenthesis.

16

8

0

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Revision 2.4


[11:8]

[7:6]

[5:4]

[3:0]

Bits

[31:24]

[23:20]

[19:16]

[15:13]

[12]

RTC Calendar Load Register (RTC_CAL)

This register is Read Only until access enable password is written to RTC_RWEN register. The register returns the current date.


RTC_BA+0x010 R/W Calendar Load Register RTC_CAL

31 30 29 28 27

Reserved

23

15

7

22 21

TENYEAR

14

Reserved

13

6 5

Reserved TENDAY

20

12

TENMON

4

19

11

3

26

18

10

2

YEAR

MON

DAY

25

17

9

1

Reset Value

0x0000_0000

24

16

8

0

Table 5-82 RTC Calendar Load Register (RTC_CAL, address 0x4000_80010).

Description

Reserved

TENYEAR

YEAR

Reserved

TENMON

MON

Reserved

TENDAY

DAY

Reserved.

10-Year Calendar Digit (0~9)

1-Year Calendar Digit (0~9)

Reserved.

10-Month Calendar Digit (0~1)

1-Month Calendar Digit (0~9)

Reserved.

10-Day Calendar Digit (0~3)

1-Day Calendar Digit (0~9)

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Revision 2.4


RTC Time Scale Selection Register (RTC_CLKFMT)


RTC_CLKFMT RTC_BA+0x014 R/W Time Scale Selection Register

Reset Value

0x0000_0001

Table 5-83 RTC Time Scale Selection Register (RTC_CLKFMT, address 0x4000_8014).

7 6 5 4

Reserved

3 2 1 0

24HEN

Bits

[31:1]

Description

Reserved

[0] 24HEN

Reserved.

24-hour / 12-hour Mode Selection

Determines whether RTC_TIME and RTC_TALM are in 24-hour mode or 12-hour mode

1 = select 24-hour time scale.

0 = select 12-hour time scale with AM and PM indication.

The range of 24-hour time scale is between 0 and 23.

12-hour time scale:

01(AM01), 02(AM02), 03(AM03), 04(AM04), 05(AM05), 06(AM06)

07(AM07), 08(AM08), 09(AM09), 10(AM10), 11(AM11), 12(AM12)

21(PM01), 22(PM02), 23(PM03), 24(PM04), 25(PM05), 26(PM06)

27(PM07), 28(PM08), 29(PM09), 30(PM10), 31(PM11), 32(PM12)

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Revision 2.4


RTC Day of the Week Register (RTC_WEEKDAY)


RTC_WEEKDAY RTC_BA+0x018 R/W Day of the Week Register

7 6 5

Reserved

4 3 2 1

WEEKDAY

Reset Value

0x0000_0000

Table 5-84 RTC Day of Week Register (RTC_WEEKDAY, address 0x4000_8018).

0

Bits

[31:3]

Description

Reserved

[2:0] WEEKDAY

Reserved.

Day of the Week Register

0 (Sunday), 1 (Monday), 2 (Tuesday), 3 (Wednesday)

4 (Thursday), 5 (Friday), 6 (Saturday)

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Revision 2.4


RTC Time Alarm Register (RTC_TALM)

Register

RTC_TALM


RTC_BA+0x01C R/W Time Alarm Register

31 30 29 28 27

Reserved

23

7

Reserved

22

Reserved

15

Reserved

14

6

21

5

TENSEC

20

13

TENMIN

TENHR

12

4

19

11

3

26

18

10

2

HR

MIN

SEC

25

17

9

1

Reset Value

0x0000_0000

Table 5-85 RTC Time Alarm Register (RTC_TALM, address 0x4000_801C).

24

16

8

0

Bits

[31:22]

[21:20]

[19:16]

[15]

[14:12]

[11:8]

[7]

Description

Reserved

TENHR

HR

Reserved

TENMIN

MIN

Reserved

Reserved.

10 Hour Time Digit of Alarm Setting (0~3)

2

1 Hour Time Digit of Alarm Setting (0~9)

Reserved.

10 Min Time Digit of Alarm Setting (0~5)

1 Min Time Digit of Alarm Setting (0~9)

Reserved.

[6:4] TENSEC 10 Sec Time Digit of Alarm Setting (0~5)

[3:0] SEC 1 Sec Time Digit of Alarm Setting (0~9)

Note:

1.

RTC_TALM is a BCD digit counter and RTC will not check validity of loaded data. Valid range is listed in the parenthesis.

2.

This register can be read back after the RTC unit is active.

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Revision 2.4


RTC Calendar Alarm Register (RTC_CALM)

Register

RTC_CALM


RTC_BA+0x020 R/W Calendar Alarm Register

31 30 29 28 27

Reserved

23

15

7

22 21

TENYEAR

14

Reserved

6

13

5

Reserved TENDAY

20

12

TENMON

4

19

11

3

26

18

10

2

YEAR

MON

DAY

25

17

9

1

Reset Value

0x0000_0000

Table 5-86 RTC Calendar Alarm Register (RTC_CALM, address 0x4000_8020).

24

16

8

0

Bits

[31:24]

[23:20]

[19:16]

[15:13]

[12]

[11:8]

[7]

Description

Reserved

TENYEAR

YEAR

Reserved

TENMON

MON

Reserved

Reserved.

10-Year Calendar Digit of Alarm Setting (0~9)

1-Year Calendar Digit of Alarm Setting (0~9)

Reserved.

10-Month Calendar Digit of Alarm Setting (0~1)

1-Month Calendar Digit of Alarm Setting (0~9)

Reserved.

[5:4] TENDAY 10-Day Calendar Digit of Alarm Setting (0~3)

[3:0] DAY 1-Day Calendar Digit of Alarm Setting (0~9)

Note:

1.

RTC_TIME is a BCD digit counter and RTC will not check validity loaded data, valid range is listed in the parenthesis.

2.

This register can be read back after the RTC unit is active.

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Revision 2.4


RTC Leap year Indication Register (RTC_LEAPYEAR)


RTC_LEAPYEAR RTC_BA+0x024 R Leap year Indicator Register

7 6 5 4

Reserved

3 2 1

Reset Value

0x0000_0000

0

LEAPYEAR

Table 5-87 RTC Leap Year Indicator Register (RTC_LEAPYEAR, address 0x4000_8024).

Bits

[31:1]

Description

Reserved

[0] LEAPYEAR

Reserved.

Leap Year Indication Register (Read Only)

0 = Current year is not a leap year.

1 = Current year is leap year.

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Revision 2.4


RTC Interrupt Enable Register (RTC_INTEN)

Register

RTC_INTEN


RTC_BA+0x028 R/W RTC Interrupt Enable Register

7 6 5 4 3

Reserved

2 1

TICKIEN

Reset Value

0x0000_0000

0

ALMIEN

Table 5-88 RTC Interrupt Enable Register (RTC_INTEN, address 0x4000_8028).

Bits

[31:2]

Description

Reserved

[1]

[0]

TICKIEN

ALMIEN

Reserved.

Time-tick Interrupt and Wakeup-by-tick Enable

1 = RTC Time-Tick Interrupt is enabled.

0 = RTC Time-Tick Interrupt is disabled.

Alarm Interrupt Enable

1 = RTC Alarm Interrupt is enabled.

0 = RTC Alarm Interrupt is disabled.

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Revision 2.4


RTC Interrupt Indication Register (RTC_INTSTS)

Register

RTC_INTSTS


RTC_BA+0x02C R/W RTC Interrupt Indicator Register

7 6 5 4 3

Reserved

2 1

TICKIF

Reset Value

0x0000_0000

0

ALMIF

Table 5-89 RTC Interrupt Indication Register (RTC_INTSTS, address 0x4000_802C).

Bits

[31:2]

Description

Reserved

[1]

[0]

TICKIF

ALMIF

Reserved.

RTC Time-tick Interrupt Flag

When RTC Time-Tick Interrupt is enabled (RTC_INTEN.TICKIF=1), RTC unit will set

TIF high at the rate selected by RTC_TICK[2:0]. This bit cleared/acknowledged by writing 1 to it.

0= Indicates no Time-Tick Interrupt condition.

1= Indicates RTC Time-Tick Interrupt generated.

RTC Alarm Interrupt Flag

When RTC Alarm Interrupt is enabled (RTC_INTEN.ALMIF=1), RTC unit will set

ALMIF to high once the RTC real time counters RTC_TIME and RTC_CAL reach the alarm setting time registers RTC_TALM and RTC_CALM. This bit cleared/acknowledged by writing 1 to it.

0= Indicates no Alarm Interrupt condition.

1= Indicates RTC Alarm Interrupt generated.

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Revision 2.4


RTC Time-Tick Register (RTC_TICK)

Register

RTC_TICK


RTC_BA+0x030 R/W RTC Time Tick Register

7 6

Reserved

5 4 3

TWKEN

2 1

TICKSEL

Table 5-90 RTC Time-Tick Register (RTC_TICK, address 0x4000_8030).

Reset Value

0x0000_0000

0

Bits

[31:4]

Description

Reserved

[3]

[2:0]

TWKEN

TICKSEL

Reserved.

RTC Timer Wakeup CPU Function Enable Bit

If TWKE is set before CPU is in power-down mode, when a RTC Time-Tick or Alarm

Match occurs, CPU will wake up.

0= Disable Wakeup CPU function.

1= Enable the Wakeup function.

Time Tick Period Select

The RTC time tick period for Periodic Time-Tick Interrupt request.

Time Tick (second) : 1 / (2^TTR)

Note: This register can be read back after the RTC is active.

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Revision 2.4


5.9 Serial 0 Peripheral Interface (SPI0) Controller

5.9.1 Overview

The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol which operates in full duplex mode. Devices communicate in master/slave mode with 4-wire bi-directional interface. The ISD91200 series contains an SPI controller performing a serial-to-parallel conversion of data received from an external device, and a parallel-to-serial conversion of data transmitted to an external device. The SPI0 controller can be set as a master with up to 2 slave select (SSB) address lines to access two slave devices; it also can be set as a slave controlled by an off-chip master device.

In addition the SPI0 interface supports Dual and Quad IO as is common on serial flash memories, where data is transferred 2 or 4 bits per clock period.

5.9.2 Features

 Supports master or slave mode operation.

 Supports one or two channels of serial data.

 8 word FIFO on transmit and receive.

 MSB or LSB first transfer.

 2 device/slave select lines in master mode, single device/slave select line in slave mode.

 Byte or word Sleep Suspend Mode.

 PDMA access support.

5.9.3 SPI0 Block Diagram

APB

IF

(32-bits)

PDMA

Control

Clock Generator

Status/Control

Register

Core Logic

TX FIFO/

TX Bufer/

Shifter

RX FIFO/

RX Bufer/

Shifter

PIO

SPI0_SCLK

SPI0_SSB0

SPI0_SSB1

SPI0_MOSI0

SPI0_MOSI1

SPI0_MISO0

SPI0_MISO1

Figure 5-34 SPI0 Block Diagram

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Revision 2.4


5.9.4 SPI0 Function Descriptions

5.9.4.1 SPI Engine Clock and SPI Serial Clock

The SPI controller derives its clock source from the system HCLK as determined by the CLKSEL1 register. The frequency of the SPI master clock is determined by the divisor ratio SPI0_CLKDIV.

In Master mode, the output frequency of the SPI serial clock output pin is equal to the SPI engine clock rate. In general, the SPI serial clock is denoted as SPI clock. In Slave mode, the SPI serial clock is provided by an off-chip master device. The SPI engine clock rate of slave device must be faster than the SPI serial clock rate of the master device. The frequency of SPI engine clock cannot be faster than the APB clock rate regardless of Master or Slave mode.

5.9.4.2 Master/Slave Mode

This SPI0 controller can be configured as in master or slave mode by setting the SLAVE bit

(SPI0_CTL.SLAVE). In master mode the ISD91200 generates SCLK and SSB signals to access one or more slave devices. In slave mode the ISD91200 monitors SCLK and SSB signals to respond to data transactions from an off-chip master. The signal directions are summarized in the application block diagrams.

SCLK

MISO

ISD91200

SPI Controller

Master

MOSI

SSB0

SSB1

SCLK

MISO

MOSI

SS

Slave 0

SCLK

MISO

MOSI

SS

Slave 1

Figure 5-35 SPI Master Mode Application Block Diagram

SCLK

MISO

ISD91200

SPI Controller

Slave

MOSI

SSB0

SSB1

SCLK

MISO

MOSI

SS

Master

Figure 5-36 SPI Slave Mode Application Block Diagram

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Revision 2.4


5.9.4.3 Slave Select

In master mode, the SPI controller can address up to two off-chip slave devices through the slave select output pins SPI0_SSB0 and SPI0_SSB1. Only one slave can be addressed at any one time. If more slave address lines are required, GPIO pins can be manually configured to provide additional

SSB lines. In slave mode, the off-chip master device drives the slave select signal SPI0_SSB0 to address the SPI controller. The slave select signal can be programmed to be active low or active high via the SPI0_SSCTL.SSACTPOL bit. In addition the SPI0_SSCTL.SSLTRIG bit defines whether the slave select signals are level triggered or edge triggered. The selection of trigger condition depends on what type of peripheral slave/master device is connected.

5.9.4.4 Automatic Slave Select

In master mode, if the bit SPI0_SSCTL.ASS is set, the slave select signals will be generated automatically and output to SPI0_SSB0 and SPI0_SSB1 pins according to registers

SPI0_SSCTL.SS[0] and SPI0_SSCTL.SS[1]. In this mode, SPI0 controller will assert SSB when transaction is triggered and de-assert when data transfer is finished. If the SPI0_SSCTL.ASS bit is cleared, the slave select output signals are asserted and de-asserted by manual setting and clearing the related bits in the SPI0_SSCTL.SS[1:0] register. The active level of the slave select output signals is specified by the SPI0_SSCTL.SSACTPOL bit.

In Master mode, if the value of SUSPITV[3:0] is less than 3 and AUTOSS is enabled, the slave select signal will be kept in active state between two successive transactions.

In Slave mode, to recognize the inactive state of the slave select signal, the inactive period of the slave select signal must be larger than or equal to 3 engine clock periods between two successive transactions.

5.9.4.5 Serial Clock

In master mode, writing a divisor into the SPI0_CLKDIV.DIVIDER register will program the output frequency of serial clock to the SPI0_SCLK output port. In slave mode, the off-chip master device drives the serial clock through the SPI0_SCLK.

5.9.4.6 Clock Polarity

The SPI0_CTL.CLKPOL bit defines the serial clock idle state in master mode. If CLKPOL = 1, the output SPI0_SCLK is high in idle state. If CLKPOL=0,it is low in idle state.

5.9.4.7 Transmit/Receive Bit Length

The bit length of a transfer word is defined in SPI0_CTL.DWIDTH bit field. It is set to define the length of a transfer word and can be up to 32 bits in length. DWIDTH=0x0 enables 32bit word length.

5.9.4.8 LSB First

The SPI0_CTL.LSB bit defines the bit order of data transmission. If LSB=0 then MSB of transfer word is sent first in time. If LSB=1 then LSB of transfer word is sent first in time. If REORDER is active, then the LSB=1 causes the bit order of each byte to be reversed, not the bit order of the short or word transmission.

For transmission, if DWIDTH is a byte multiple and LSB=1 , bytes are always reordered.

LSB is not valid and must be set to 0 for DUAL or QUAD SPI transactions.

5.9.4.9 Transmit Edge

The SPI0_CTL.TXNEG bit determines whether transmit data is changed on the positive or negative edge of the SPI0_SCLK serial clock. If TXNEG=0 then transmitted data will change state on the rising edge of SPI0_SCLK. If TXNEG=1 then transmitted data will change state on the falling edge of

SPI0_SCLK.

5.9.4.10 Receive Edge

The SPI0_CTL.RXNEG bit determines whether data is received at either the negative edge or positive

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Revision 2.4

ISD91200 Series Technical Reference Manual edge of serial clock SPI0_SCLK. If RXNEG=1 then data is clocked in on the falling edge of SPI0_SCLK.

If RXNEG=0 data is clocked in on the rising edge of SPI0_SCLK. Note that RXNEG should be the inverse of TXNEG for standard SPI operation.

5.9.4.11 Word Suspend

The four bit field SUSPITV (SPI0_CTL[7:4]) provides a configurable suspend interval of 0.5 ~ 15.5 SPI clock periods, between two successive transaction words in Master mode. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value of SUSPITV is 0x3 (3.5 SPI clock cycles).

.

Word

Sleep

CLKP=0

SPICLK

CLKP=1

MISO

MOSI

MSB

Tx0[31]

MSB

Rx0[31]

Tx0[30]

Rx0[30]

Tx0[0]

Rx0[0]

Tx1[31]

Rx1[31]

Tx1[30]

Rx1[30]

LSB

Tx1[0]

LSB

Rx1[0]

1st Transfer Word

2nd Transfer Word

Figure 5-37 Word Sleep Suspend Mode

5.9.4.12 Byte Reorder

APB access to the SPI controller is via the 32bit wide TX and RX registers. When the transfer is set as

MSB first (SPI0_CTL.LSB = 0) and the SPI0_CTL.REORDER bit is set, the data stored in the TX buffer and RX buffer will be rearranged such that the least significant physical byte is processed first. For

DWIDTH =0 (32 bits transfer), the sequence of transmitted/received data will be BYTE0, BYTE1,

BYTE2, and then BYTE3. If DWIDTH is set to 24-bits, the sequence will be BYTE0, BYTE1, and

BYTE2. For Quad and Dual SPI transactions, REORDER is only valid for receive operation. For transmit in Dual/Quad modes, REORDER must be set to 0.

SPI->TX[0]/SPI->RX[0]

MSB first

Byte3 Byte2 Byte1 Byte0

[31:24] [23:16] [15:8] [7:0]

LSB = 0 (MSB first)

REORDER = 1

MSB first

TX/RX Buffer

Byte0 Byte1 Byte2 Byte3

DWIDTH = 32 bits

MSB first

N/A Byte0 Byte1 Byte2


MSB first

N/A N/A Byte0 Byte1


REODRER = 0

MSB first

TX/RX Buffer



MSB first



MSB first



Time

Figure 5-38 Byte Re-Ordering Transfer

Byte ordering can be a confusing issue when converting from arrays of data processed by the CPU for

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Revision 2.4

ISD91200 Series Technical Reference Manual transmission out the SPI port. The CortexM0 stores data in a little endian format; that is the LSB of a multi-byte word or half-word are stored first in memory. Consider how the CortexM0 stores the following arrays in memory:

1. unsigned char ucSPI_DATA[]={0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08};

2. unsigned int uiSPI_DATA[]={0x01020304, 0x05060708}; unsigned char ucSPI_DATA[]={0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08}; unsigned int uiSPI_DATA[]={0x01020304, 0x05060708};

RAM Address RAM Contents

0x20000014

0x20000010

0x2000000c uiSPI_DATA[]

→ 0x20000008

0x20000004 ucSPI_DATA[]

→ 0x20000000

0x08

0x04

0x05

0x01

0x07

0x03

0x06

0x02

0x06

0x02

0x07

0x03

0x05

0x01

0x08

0x04

APB Data Bus [7:0] [15:8] [23:16] [31:24]

Figure 5-39 Byte Order in Memory

It can be seen from that byte order for an array of bytes is different than that of an array of words. Now consider if this data were to be sent to the SPI port; the user could:

1. Set DWIDTH=8 and send data byte-by-byte SPI0_TX = ucSPI_DATA[i++]

2. Set DWIDTH=32 and send word-by-word SPI0_TX = uiSPI_DATA[i++]

Both of these would result in the byte stream {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08} being sent.

It would be common that a byte array of data is constructed but user, for efficiency, wishes to transfer data to SPI via word transfers. Consider the situation of where a int pointer points to the byte data array.

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Revision 2.4

ISD91200 Series Technical Reference Manual unsigned char ucSPI_DATA[]={0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08}; unsigned int *uiSPI_DATA = (unsigned int *)ucSPI_DATA[];

RAM Address RAM Contents uiSPI_DATA[]

→

0x20000014

0x20000010

Byte0

Byte0

0x08

0x2000000c

0x20000008


→ 0x20000000

0x04

0x05

0x01

Byte1

Byte1

0x07

0x03

0x06

0x02

Byte2

Byte2

0x06

0x02

0x07

0x03

Byte3

Byte3

0x05

0x01

0x08

0x04

APB Data Bus [7:0] [15:8] [23:16] [31:24]


Now if we set DWIDTH=32 and sent word-by-word SPI0_TX[0] = uiSPI_DATA[i++], the order transmitted would be {0x04, 0x03, 0x02, 0x01, 0x08, 0x07, 0x06, 0x05}. However if we set

REORDER=1, we would reverse this order to the desired stream: {0x01, 0x02, 0x03, 0x04, 0x05, 0x06,

0x07, 0x08}.

5.9.4.13 Interrupt

 SPI unit transfer interrupt

As the SPI controller finishes a unit transfer, the unit transfer interrupt flag UNITIF (SPI0_STATUS[1]) will be set to 1. The unit transfer interrupt event will generate an interrupt to CPU if the unit transfer interrupt enable bit UNITIEN (SPI0_CTL[17]) is set. The unit transfer interrupt flag is cleared by writing

1 to it.

 SPI slave select interrupt

In slave mode, there are slave select active and in-active interrupt flag, SSACTIF and SSINAIF, will be set to 1 when the SPIEN and SLAVE bits were set to 1 and slave senses the slave select signal active or inactive. The SPI controller will issue an interrupt if the SSINAIEN or SSACTIEN,

SPI0_SSCTL[13:12], are set to 1.

 Slave Time-out interrupt

In Slave mode, there is slave time-out function for user to know that there is serial clock input but one transaction doesn’t finish over the period of SLVTOCNT basing on engine clock.

When the Slave select is active and the value of SLVTOCNT is not 0, the Slave time-out counter in the

SPI controller logic will start after the serial clock input. This counter will be clear after one transaction done or the SLVTOCNT is set to 0. If the value of the time-out counter greater or equal than the value of SLVTOCNT before one transaction done, the slave time-out event occurs and the SLVTOIF,

SPI0_STATUS[5], will be set to 1. The SPI controller will issue an interrupt if the SLVTOIEN,

SPI0_SSCR[5], is set to 1.

 Slave Error 0 interrupt

In Slave mode, if the transmit/ receive bit count mismatch with the DWIDTH when the slave select line goes to inactive state, the Slave mode error 0, SLVBEIF, SPI0_STATUS[6], will be set to 1. The SPI controller will issue an interrupt if the SLVBCEIEN, SPI0_SSCR[8], is set to 1.

Note: 1. In Slave transmit mode, if there is bit length transmit error (bit count mismatch), the user shall set the TXRST bit and write the transmit datum again to restart the next transaction.

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Revision 2.4


2. If the slave select active but there is no any serial clock input, the SLVBEIF also active when the slave select goes to inactive state.

 Slave Under-run and Slave Error 1 interrupts

In Slave mode, if there is no any data is written to the SPI0_TX register, the under-run event, TXUFIF

(SPI0_STATUS[19]) will active when the slave select active and the serial clock input this controller.

The SPI controller will issue an interrupt if the SLVUDRIEN is set to 1.

Under the previous condition, the Slave mode error 1, SLVURIF, SPI0_STATUS[7], will be set to 1 when SS goes to inactive state and transmit under-run occurs. The SPI controller will issue an interrupt if the SLVUDRIEN, SPI0_SSCR[9], is set to 1.

Note: In SLV3WIRE mode, the slave select bus active all the time so that the user shall polling the

TXUFIF bit to know if there is transmit under-run event or not.

 Receive Over-run interrupt

In Slave mode, if the receive FIFO buffer contains 8 unread data, the RXFULL flag will be set to 1 and the RXOVIF will be set 1 if there is more serial data is received from SPIMOSI and the RXOVIF will be set to 1 and follow-up data will be dropped. The SPI controller will issue an interrupt if the RXOVIEN,

SPI0_FIFOCTL[5], set to 1.

 Receive FIFO time-out interrupt

In FIFO mode, there is a time-out function to inform user. If there is a received data in the FIFO and it is not read by software over 64 SPI engine clock periods in Master mode or over 576 SPI engine clock periods in Slave mode, it will send a time-out interrupt to the system if the time-out interrupt enable bit,

RXTOIEN, SPI0_FIFOCTL[4], is set to 1.

 Transmit FIFO interrupt

In FIFO mode, if the valid data count of the transmit FIFO buffer is less than or equal to the setting value of TXTH, the transmit FIFO interrupt flag will be set to 1. The SPI controller will generate a transmit FIFO interrupt to the system if the transmit FIFO interrupt enable bit, SPI0_FIFOCTL[3], is set to 1.

 Receive FIFO interrupt

In FIFO mode, if the valid data count of the receive FIFO buffer is larger than the setting value of RXTH, the receive FIFO interrupt flag will be set to 1. The SPI controller will generate a receive FIFO interrupt to the system if the receive FIFO interrupt enable bit, SPI0_FIFOCTL[2], is set to 1.

5.9.4.14 3-Wire Mode

When the SLV3WIRE bit is set by software to enable the Slave 3-wire mode, the SPI controller can work with no slave select signal in Slave mode. The SLV3WIRE bit only takes effect in Slave mode.

Only three pins, SPICLK, SPI0_MISO, and SPI0_MOSI, are required to communicate with a SPI master. The SPISS pin can be configured as a GPIO. When the SLV3WIRE bit is set to 1, the SPI slave will be ready to transmit/receive data after the SPIEN bit is set to 1.

5.9.4.15 2-Bit Mode

The SPI controller supports 2-bit Transfer mode when setting the TWOBIT bit (SPI0_CTL[16]) to 1. In

2-bit mode, the SPI controller performs full duplex data transfer. In other words, the 2-bit serial data can be transmitted and received simultaneously.

For example, in Master mode, the first data written to the TX FIFO will be transmitted through

SPI0_MOSI0 and the second data written to the TX FIFO will be transmitted through the SPI0_MOSI1 pin. After transmission, the first read of RX FIFO will result in the data received from SPI0_MISO0 pin and the second read the data received from SPI0_MISO1 pin.

In Slave mode, the first two data stored in the TX FIFO will be transmitted through the SPI0_MISO0 and

SPI0_MISO1 pin respectively. Concurrently, the RX FIFO will store the data received from the

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SPI0_MOSI0 and SPI0_MOSI1 pin, same as Master mode.

SPICLKx

MISOx[1:0]

MOSIx[1:0]

SPI Controller

Master

SPISSx0

SPISSx1

SCLK

MISOx[0]

MOSIx[0]

MISO

Slave 0

MOSI

SS

SCLK

MISOx[1]

MOSIx[1]

MISO

Slave 1

MOSI

SS

Figure 5-41 2-Bit Mode System Architecture

SPI_SS

SS_LVL=1

SS_LVL=0

CLKP=0

SPI_CLK

CLKP=1

SPI_MISO0

SPI_MOSI0

SPI_MISO1

MSB

TX0[31]

TX0[30]

MSB

RX0[31]

RX0[30]

MSB

TX1[31]

TX1[30]

TX0[16] TX0[15] TX0[14]

RX0[16] RX0[15] RX0[14]

TX1[16] TX1[15] TX1[14]

LSB

TX0[0]

LSB

RX0[0]

LSB

TX1[0]

SPI_MOSI1

MSB

RX1[31]

RX1[30] RX1[16] RX1[15] RX1[14]

LSB

RX1[0]

Figure 5-42 2-Bit Mode (Slave Mode)

5.9.4.16 Dual/Quad I/O Mode

The SPI controller supports dual and quad I/O transfer when setting the DUALIOEN bit or the

QUADIOEN bit (SPI0_CTL[21], SPI0_CTL[22]) to 1. Many SPI Serial Flash devices support Dual/ Quad

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I/O transfer. The QDIODIR bit (SPI0_CTL[20]) is used to define the direction of the transfer data. When the QDIODIR bit is set to 1, the controller will send the data to external device. When the QDIODIR bit is set to 0, the controller will read the data from the external device. This function supports transfers of

8, 16, 24, and 32-bits.

The Dual/Quad I/O mode is not supported in the Slave 3-wire mode. The byte REORDER function is only available in receive mode for Dual/Quad transactions.

For Dual I/O mode, if both the DUALIOEN and QDIODIR bits are set as 1, the SPI0_MOSI0 is the even bit data output and the SPI0_MISO0 will be set as the odd bit data output. If the DUALIOEN is set as 1 and QDIODIR is set as 0, both the SPI0_MISO0 and SPI0_MOSI0 will be set as data input ports.

SPI_SS

SPI_CLK

SPI_MOSI

SPI_MISO

7 6 5 4 3 2 1 0

Master output

Slave input

Master input

Slave output

6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

Output

7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1

Output

DUAL_IO_EN

QD_IO_DIR

Figure 5-43 Bit Sequence of Dual Output Mode

SPI_SS

SPI_CLK

SPI_MOSI

SPI_MISO

7 6 5 4 3 2 1 0

Master output

Slave input

6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

Input

7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1

Input

Master input

Slave output

DUAL_IO_EN

QD_IO_DIR

Figure 5-44 Bit Sequence of Dual Input Mode

For Quad I/O mode, if both the QUADIOEN and QDIODIR bits are set as 1, the SPI0_MOSI0 and

SPI0_MOSI1 are the even bit data output and the SPI0_MISO0 and SPI0_MISO1 will be set as the odd bit data output. If the QUADIOEN is set as 1 and QDIODIR is set as 0, both the SPI0_MISO0,

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SPI0_MISO1, SPI0_MOSI0 and SPI0_MOSI1 will be set as data input ports.

SPICLKx

MISOx[1:0]

MOSIx[1:0]

SPI Controller

Master

SPISSx0

SPISSx1

SCLK

MISOx[0]

MOSIx[0]

MISO

Quad

HOLDB

MOSI

SpiFlash

WP

SS

MISOx[1]

MOSIx[1]

Figure 5-45 Quad Mode System Architecture

SPI_SS

SPI_CLK

SPI_MOSI0

CS

CLK

DI (IO

0

)

SPI_MISO0

SPI_MOSI1

SPI_MISO1

7 6 5 4 3 2 1 0

Master output

Slave input

Master input

Slave output

4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0

Output

5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1

Output

6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2

Output

7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3

Output

DO (IO

1

)

WP (IO

2

)

HOLD (IO

3

)

QUAD_IO_EN

QD_IO_DIR

Figure 5-46 Bit Sequence of Quad Output Mode

5.9.4.17 4-Level FIFO Buffer

The SPI controller is equipped with eight 32-bit wide transmit and receive FIFO buffers.

The transmit FIFO buffer is an 4-level depth, 32-bit wide, first-in, first-out register buffer. 4 words of data can be written to the transmit FIFO buffer in advance through software by writing the SPI0_TX register. The data stored in the transmit FIFO buffer will be read and sent out by the transmission control logic. If the 8-level transmit FIFO buffer is full, the TXFULL bit will be set to 1. When the SPI

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ISD91200 Series Technical Reference Manual transmission logic unit draws out the last datum of the transmit FIFO buffer, so that the 4-level transmit

FIFO buffer is empty, the TXEMPTY bit will be set to 1. Notice that the TXEMPTY flag is set to 1 while the last transaction is still in progress. In Master mode, both the BUSY bit (SPI0_STATUS[0]) and

TXEMPTY bit should be checked by software to make sure whether the SPI is idle or not.

The received FIFO buffer is also an 4-level depth, 32-bit wide, first-in, first-out register buffer. The receive control logic will store the received data to this buffer. The FIFO buffer data can be read from

SPI0_RX register by software. There are FIFO related status bits, like RXEMPTY and RXFULL, to indicate the current status of FIFO buffer.

The transmitting and receiving threshold can be set through software by setting the TXTH,

SPI0_FIFOCTL[29:28], and RXTH, SPI0_FIFOCTL[25:24], settings. When the count of valid data stored in transmit FIFO buffer is less than or equal to TXTH setting, the TXTHIF, SPI0_STATUS[18], bit will be set to 1. When the count of valid data stored in receive FIFO buffer is larger than RXTH setting, the RXTHIF, SPI0_STATUS[10], bit will be set to 1.

Write

SPI_TX Buffer

MOSI Pin in Master Mode or

MISO Pin in Slave Mode

1

2

n

APB

MISO Pin in Master Mode or

MOSI Pin in Slave Mode

Receive buffer n

Receive buffer 1 1

2

n

Read

SPI_RX Buffer

Figure 5-47 FIFO Mode Block Diagram

In Master mode, the first datum is written to the SPI0_TX register, the TXEMPTY flag will be cleared to

0. The transmission immediately starts as long as the transmit FIFO buffer is not empty. User can write the next data into SPI0_TX register immediately. The SPI controller will insert a suspend interval between two successive transactions and the period of suspend interval is decided by the setting of

SUSPITV (SPI0_CTL [7:4]). User can write data into SPI0_TX register as long as the TXFULL flag is 0.

The subsequent transactions will be triggered automatically if the transmitted data are updated in time.

If the SPI0_TX register is not updated after data transfer is done, the transfer will stop.

In Master mode, during receive operation, the serial data is received from SPI0_MISO0/1 pin and stored to receive FIFO buffer. The RXEMPTY flag will be cleared to 0 while the receive FIFO buffer contains unread data. The received data can be read by software from SPI0_RX register as long as the

RXEMPTY flag is 0. If the receive FIFO buffer contains 8 unread data, the RXFULL flag will be set to 1.

The SPI controller will stop receiving data until the SPI0_RX register is read by software.

In Slave mode, during transmission operation, when data is written to the SPI0_TX register by software, the data will be loaded into transmit FIFO buffer and the TXEMPTY flag will be set to 0. The

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ISD91200 Series Technical Reference Manual transmission will start when the slave device receives clock signal from master. Data can be written to

SPI0_TX register as long as the TXFULL flag is 0. After all data have been drawn out by the SPI transmission logic unit and the SPI0_TX register is not updated by software, the TXEMPTY flag will be set to 1.

If there is no any data is written to the SPI0_TX register, the under-run event, TXUFIF

(SPI0_STATUS[19]) will active when the slave select active and the serial clock input this controller.

Under the previous condition, the Slave mode error 1, SLVURIF, SPI0_STATUS[7], will be set to 1 when SS goes to inactive state and transmit under-run occurs.

In Slave mode, during receiving operation, the serial data is received from SPI0_MOSI0/1 pin and stored to SPI0_RX register. The reception mechanism is similar to Master mode reception operation. If the receive FIFO buffer contains 8 unread data, the RXFULL flag will be set to 1 and the RXOVIF will be set 1 if there is more serial data is received from SPIMOSI and follow-up data will be dropped. If the receive bit counter mismatch with the DWIDTH when the slave select line goes to inactive state, the

Slave mode error 0, SLVBEIF, SPI0_STATUS[6], will be set to 1.

When the Slave select is active and the value of SLVTOCNT is not 0, the Slave time-out counter in the

SPI controller logic will start after the serial clock input. This counter will be clear after one transaction done or the SLVTOCNT is set to 0. If the value of the time-out counter greater or equal than the value of SLVTOCNT before one transaction done, the slave time-out event occurs abd the SLVTOIF,

SPI0_STATUS[5], will be set to 1.

A receive time-out function is built-in in this controller. When the receive FIFO is not empty and no read operation in receive FIFO over 64 SPI clock period in Master mode or over 576 SPI engine clock period in Slave mode, the receive time-out occurs and the SLVTOIF be set to 1. When the receive FIFO is read by user, the time-out status will be cleared automatically.

5.9.4.18 DMA Receive Mode

The SPI controller supports DMA access to the transmit and receive FIFOs. When the DMA transmit interface is active, DMA sub-system fills the TX FIFO to trigger SPI interface. When only DMA receive function is required, an additional mode is provided to inform the SPI system of the number of transfers desired so that SPI system can read ahead of DMA requests. When SPI0_CTL. RXTCNTEN is set, the register SPI0_RXTSNCNT holds the number of SPI transactions (total number of bytes is determined by SPI0_CTL.DWIDTH value).

5.9.5 SPI Timing Diagram

In master/slave mode, the device address/slave select (SPI0_SSB0/1) signal can be configured as active low or active high by the SPI0_SSCTL.SSACTPOL bit.

The serial clock phase and polarity is controlled by CLKPOL, RXNEG and TXNEG bits. The bit length of a transfer word is configured by the DWIDTH parameter. Whether data transmission is MSB first or

LSB first is controlled by the SPI0_CTL.LSB bit. Four examples of SPI timing diagrams for master/slave operations and the related settings are shown as below.

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SPI_SS

SS_LVL=1

SS_LVL=0

SPICLK

CLKP=0

CLKP=1

MOSI

MISO

MSB

Tx0[7]

MSB

Rx0[7]

Tx0[6] Tx0[5]

Rx0[6] Rx0[5]

Tx0[4] Tx0[3]

Rx0[4] Rx0[3]

Tx0[2] Tx0[1]

Rx0[2] Rx0[1]

LSB

Tx0[0]

LSB

Rx0[0]

Master Mode: CNTRL[SLVAE]=0, CNTRL[LSB]=0, CNTRL[Tx_NUM]=0x0, CNTRL[Tx_BIT_LEN]=0x08

1. CNTRL[CLKP]=0, CNTRL[Tx_NEG]=1, CNTRL[Rx_NEG]=0 or

2. CNTRL[CLKP]=1, CNTRL[Tx_NEG]=0, CNTRL[Rx_NEG]=1

Figure 5-48 SPI Timing in Master Mode

SPI_SS

SS_LVL=1

SS_LVL=0

SPICLK

CLKP=0

CLKP=1

MOSI

MISO

LSB

Tx0[0]

LSB

Rx0[0]

Tx0[1] Tx0[2]

Rx0[1] Rx0[2]

Tx0[3] Tx0[4]

Rx0[3] Rx0[4]

Tx0[5]

Rx0[5]

Tx0[6]

Rx0[6]

MSB

Tx0[7]

MSB

Rx0[7]

Master Mode: CNTRL[SLVAE]=0, CNTRL[LSB]=1, CNTRL[Tx_NUM]=0x0, CNTRL[Tx_BIT_LEN]=0x08



Figure 5-49 SPI Timing in Master Mode (Alternate Phase of SPICLK)

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SPI_SS

SS_LVL=1

SS_LVL=0

SPICLK

CLKP=0

CLKP=1

MISO

MOSI

MSB

Tx0[7]

MSB

Rx0[7]

Tx0[6]

Rx0[6]

Tx0[0] Tx1[7] Tx1[6]

Rx0[0] Rx1[7] Rx1[6]

LSB

Tx1[0]

LSB

Rx1[0]

Slave Mode: CNTRL[SLVAE]=1, CNTRL[LSB]=0, CNTRL[Tx_NUM]=0x01, CNTRL[Tx_BIT_LEN]=0x08



Figure 5-50 SPI Timing in Slave Mode

SPI_SS

SS_LVL=1

SS_LVL=0

SPICLK

CLKP=0

CLKP=1

MISO

MOSI

LSB

Tx0[0]

LSB

Rx0[0]

Tx0[1]

Rx0[1]

Tx0[7] Tx1[0]

Rx0[7] Rx1[0]

Tx1[6]

Rx1[6]

MSB

Tx1[7]

MSB

Rx1[7]

Slave Mode: CNTRL[SLVAE]=1, CNTRL[LSB]=1, CNTRL[Tx_NUM]=0x01, CNTRL[Tx_BIT_LEN]=0x08



Figure 5-51 SPI Timing in Slave Mode (Alternate Phase of SPICLK)

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5.9.6 SPI Configuration Examples

 Example 1, SPI controller is set as a master to access an off-chip slave device with following specifications:

 Data bit latched on positive edge of serial clock

 Data bit driven on negative edge of serial clock

 Data be transferred from MSB first

 SCLK low in idle state

 Only one byte data be transmitted/received in a transfer

 Slave select signal is active low

 SCLK frequency is 10MHz

To configure the SPI0 interface to the above specifications perform the following steps:

1) Write a divisor into the SPI0_CLKDIV register to determine the output frequency of serial clock.

2) Configure the SPI0_SSCTL register to address device. For example to manually address, set

SPI0_SSCTL.ASS=0, SPI0_SSCTL.SSACTPOL =0 for active low SS. When software wishes to address device it will set SPI0_SSCTL.SS=1 to output an active SS on SPI0_SSB0 pin.

3) Configure the SPI0_CTL register. Set SPI0_CTL.SLAVE=0 for master mode, set

SPI0_CTL.CLKPOL=0 for SCLK polarity normally low, set SPI0_CTL.TXNEG=1 so that data changes on falling edge of SCLK, set SPI0_CTL.RXNEG=0 so that data is latched into device on positive edge of SCLK, set SPI0_CTL.DWIDTH=4 and SPI0_CTL.TX_NUM=0 for a single byte transfer and finally set SPI0_CTL.LSB=0 for MSB first transfer.

4) If manually selecting slave device set SPI0_SSCTL.SS=1.

5) To transmit one byte of data, write data to SPI0_TX register. If only doing a receive, write a dummy byte to SPI0_TX register.

6) Enable the SPI0_CTL.SPIEN bit to start the data transfer over the SPI interface.

7) Wait for SPI transfer to finish. Can be interrupt driven (if the interrupt enable SPI0_CTL.UNITIEN bit is set) or by polling the UNITIF bit which will be cleared to 0 by hardware automatically at end of transmission.

8) Read out the received one byte data from SPI0_RX

9) Go to 5) to continue another data transfer or set SPI0_SSCTL.SS=0 to deactivate the off-chip slave devices.

 Example 2, SPI controller is set as a slave device that controlled by an off-chip master device with the following characteristics:



 Data be transferred from LSB first

 SCLK high in idle state


 Slave select signal is active high level trigger

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To configure the SPI interface to the above specifications perform the following steps:

1) Configure the SPI0_SSCTL register. SPI0_SSCTL.SSACTPOL=1 for active high slave select,

SPI0_SSCTL.SS_LTRIG=1 for level sensitive trigger.

2) Configure the SPI0_CTL register. Set SPI0_CTL.SLAVE=1 for slave mode, set

SPI0_CTL.CLKPOL=1 for SCLK polarity idle high, set SPI0_CTL.TXNEG=1 so that data changes on falling edge of SCLK, set SPI0_CTL.RXNEG=0 so that data is latched into device on positive edge of SCLK, set SPI0_CTL.DWIDTH=4 and SPI0_CTL.TX_NUM=0 for a single byte transfer and finally set SPI0_CTL.LSB=1 for LSB first transfer.

3) If SPI slave is to transmit one byte of data to the off-chip master device, write first byte to TX register. If no data to be transmitted write a dummy byte.

4) Enable the SPIEN bit to wait for the slave select trigger input and serial clock input from the off-chip master device to start the data transfer at the SPI interface.

5) Wait for SPI transfer to finish. Can be interrupt driven (if the interrupt enable SPI0_CTL.UNITIEN bit is set) or by polling the UNITIF bit which will be cleared to 0 by hardware automatically at end of transmission.

6) Read out the received data from RX register.

7) Go to 3) to continue another data transfer or disable the GO_BUSY bit to stop data transfer.

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Description Register Offset

SPI Base Address:

SPI0_BA = 0x4003_0000

SPI0_CTL SPI0_BA + 0x00

SPI0_CLKDIV SPI0_BA + 0x04

SPI0_BA + 0x08 SPI0_SSCTL

SPI0_PDMACTL SPI0_BA + 0x0C

R/W

R/W

R/W

R/W

R/W

Control and Status Register

Clock Divider Register (Master Only)

Slave Select Register

SPI PDMA Control Register

SPI0_FIFOCTL

SPI0_STATUS

SPI0_BA + 0x10

SPI0_BA + 0x14

SPI0_RXTSNCNT SPI0_BA + 0x18

SPI0_TX SPI0_BA + 0x20

SPI0_RX SPI0_BA + 0x30

SPI0_BA + 0x50 SPI0_VERNUM

R

R

R/W

R/W

R/W

W

FIFO Control/Status Register

Status Register

Receive Transaction Count Register

FIFO Data Transmit Register

FIFO Data Receive Register

IP Version Number Register

Reset Value

0x0000_0034

0x0000_0000

0x0000_0000

0x0000_0000

0x4400_0000

0x0005_0110

0x0000_0000

0x0000_0000

0x0000_0000

0x0201_0001

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SPI Control and Status Register (SPI0_CTL)


SPI0_BA + 0x00 R/W Control and Status Register SPI0_CTL

31 30 29 27

23 22 21

RXTCNTEN QUADIOEN DUALIOEN

15 14

7

Reserved

6

13

LSB

5

SUSPITV

28

Reserved

20

QDIODIR

12

4

19

REORDER

11

3

CLKPOL

26

18

SLAVE

10

DWIDTH

2

TXNEG

25

17

UNITIEN

9

1

RXNEG

Reset Value

0x0000_0034

24

RXMODEEN

16

TWOBIT

8

Table 5-91 SPI Control and Status Register (SPI0_CTL, address 0x4003_0000)

0

SPIEN

Bits

[31:25]

Description

Reserved

[24]

[23]

[22]

[21]

[20]

RXMODEEN

RXTCNTEN

QUADIOEN

DUALIOEN

QDIODIR

Reserved.

FIFO Receive Mode Enable

0 = Disable function.

1 = Enable FIFO receive mode. In this mode SPI transactions will be continuously performed while RXFULL is not active. To stop transactions, set RXMODEEN to 0.

DMA Receive Transaction Count Enable

0 = Disable function.

1 = Enable transaction counter for DMA receive only mode. SPI will perform the number of transfers specified in the SPI0_RXTSNCNT register, allowing the SPI interface to read ahead of DMA controller.

Quad I/O Mode Enable

0 = Quad I/O mode Disabled.

1 = Quad I/O mode Enabled.

Dual I/O Mode Enable

0 = Dual I/O mode Disabled.

1 = Dual I/O mode Enabled.

Quad or Dual I/O Mode Direction Control

0 = Quad or Dual Input mode.

1 = Quad or Dual Output mode.

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Revision 2.4

[18]

[17]

[19]

[16]

[15:14]

[13]

[12:8]

REORDER

SLAVE

UNITIEN

TWOBIT

Reserved

LSB

DWIDTH


Byte Reorder Function Enable

0 = Byte reorder function Disabled.

1 = Byte reorder function Enabled. A byte suspend interval will be inserted between each byte. The period of the byte suspend interval depends on the setting of

SUSPITV.

Note:

Byte reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.

REORDER is only available for Receive mode in DUAL and QUAD transactions.

For DUAL and QUAD transactions with REORDER, SUSPITV must be set to 0.

Master Slave Mode Control

0 = Master mode.

1 = Slave mode.

Unit Transfer Interrupt Enable

0 = Disable SPI Unit Transfer Interrupt.

1 = Enable SPI Unit Transfer Interrupt to CPU.

Two Bits Transfer Mode

0 = Disable two-bit transfer mode.

1 = Enable two-bit transfer mode.

When 2-bit mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data. As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.

Reserved.

LSB First

0 = The MSB is transmitted/received first (which bit in TX and RX FIFO depends on the DWIDTH field).

1 = The LSB is sent first on the line (bit 0 of TX FIFO]), and the first bit received from the line will be put in the LSB position in the SPIn_RX FIFO (bit 0 SPIn_RX).

Note:

For DUAL and QUAD transactions with LSB must be set to 0.

DWIDTH – Data Word Bit Length

This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted.

DWIDTH = 0x01 … 1 bit.

DWIDTH = 0x02 … 2 bits.

……

DWIDTH = 0x1f … 31 bits.

DWIDTH = 0x00 … 32 bits.

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Revision 2.4

[3]

[2]

[1]

[7:4]

[0]

SUSPITV

CLKPOL

TXNEG

RXNEG

SPIEN


Suspend Interval (Master Only)

The four bits provide configurable suspend interval between two successive transmit/receive transactions in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.

SUSPITV is available for standard SPI transactions, it must be set to 0 for DUAL and

QUAD mode transactions.

(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle

Example:

SUSPITV = 0x0 … 0.5 SPICLK clock cycle.

SUSPITV = 0x1 … 1.5 SPICLK clock cycle.

……

SUSPITV = 0xE … 14.5 SPICLK clock cycle.

SUSPITV = 0xF … 15.5 SPICLK clock cycle.

Note:

For DUAL and QUAD transactions with SUSPITV must be set to 0.

Clock Polarity

0 = SCLK idle low.

1 = SCLK idle high.

Transmit at Negative Edge

0 = The transmitted data output signal is changed at the rising edge of SCLK.

1 = The transmitted data output signal is changed at the falling edge of SCLK.

Receive at Negative Edge

0 = The received data input signal is latched at the rising edge of SCLK.

1 = The received data input signal is latched at the falling edge of SCLK.

SPI Transfer Enable

0 = Disable SPI Transfer.

1 = Enable SPI Transfer.

In Master mode, the transfer will start when there is data in the FIFO buffer after this is set to 1. In Slave mode, the device is ready to receive data when this bit is set to

1.

Note:

All configuration should be set before writing 1 to this SPIEN bit. (e.g.: TXNEG,

RXNEG, DWIDTH, LSB, CLKP, and so on).

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SPI Divider Register (SPI0_CLKDIV)


SPI0_BA + 0x04 R/W Clock Divider Register (Master Only) SPI0_CLKDIV

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5 4 3 2

DIVIDER

25

17

9

1

Reset Value

0x0000_0000

Table 5-92 SPI Clock Divider Register (SPI0_CLKDIV, address 0x4003_0004)

24

16

8

0

Bits

[31:8]

Description

Reserved

[7:0] DIVIDER

Reserved.

Clock Divider Register

The value in this field is the frequency divider for generating the SPI engine clock,Fspi_sclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation.

Fspi_sclk = Fspi_clockSRC / (DIVIDER+1). where

Fspi_clockSRC is the SPI engine clock source, which is defined in the clock control,

CLKSEL1 register.

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Revision 2.4


SPI Slave Select Register (SPI0_SSCTL)


SPI0_BA + 0x08 R/W Slave Select Register SPI0_SSCTL

31 30 29

23 22

15 14

Reserved

7 6

Reserved SLVTORST

21

13

SSINAIEN

5

SLVTOIEN

Reset Value

0x0000_0000

28 27

SLVTOCNT[15:8]

20 19

SLVTOCNT[7:0]

12

SSACTIEN

4

26

18

11

Reserved

10

3 2

SLV3WIRE AUTOSS SSACTPOL

25

17

24

16

9 8

SLVUDRIEN SLVBCEIEN

1 0

SS

Table 5-93 SPI Slave Select Register (SPI0_SSCTL, address 0x4003_0008)


[31:16]

[15:14]

[13]

[12]

[11:10]

[9]

[8]

[7]

[6]

[5]

SLVTOCNT

Reserved

SSINAIEN

SSACTIEN

Reserved

SLVUDRIEN

SLVBCEIEN

Reserved

SLVTORST

SLVTOIEN

Slave Mode Time-out Period

In Slave mode, these bits indicate the time out period when there is serial clock input during slave select active. The clock source of the time out counter is Slave engine clock.

If the value is 0, it indicates the slave mode time-out function is disabled.

Reserved.

Slave Select Inactive Interrupt Enable

0 = Slave select inactive interrupt Disable.

1 = Slave select inactive interrupt Enable.

Slave Select Active Interrupt Enable

0 = Slave select active interrupt Disable.

1 = Slave select active interrupt Enable.

Reserved.

Slave Mode Error 1 Interrupt Enable

0 = Slave mode error 1 interrupt Disable.

1 = Slave mode error 1 interrupt Enable.

Slave Mode Error 0 Interrupt Enable

0 = Slave mode error 0 interrupt Disable.

1 = Slave mode error 0 interrupt Enable.

Reserved.

Slave Mode Time-out FIFO Clear

0 = Function disabled.

1 = Both the FIFO clear function, TXRST and RXRST, are activated automatically when there is a slave mode time-out event.

Slave Mode Time-out Interrupt Enable

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Revision 2.4

[4]

[3]

[2]

[1:0]


SLV3WIRE

AUTOSS

SSACTPOL

SS

0 = Slave mode time-out interrupt Disabled.

1 = Slave mode time-out interrupt Enabled.

Slave 3-wire Mode Enable

This is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface consisting of SPI0_CLK, SPI0_MISO, and SPI0_MOSI.

0 = 4-wire bi-directional interface.

1 = 3-wire bi-directional interface.

Automatic Slave Select Function Enable (Master Only)

0 = If this bit is cleared, slave select signals will be asserted/de-asserted by setting/clearing the corresponding bits of SPI0_SSCTL[1:0].

1 = If this bit is set, SPI0_SS0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI0_SSCTL[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished.

Slave Select Active Level

This bit defines the active status of slave select signal (SPI0_SS0/1).

0 = The slave select signal SPI0_SS0/1 is active on low-level/falling-edge.

1 = The slave select signal SPI0_SS0/1 is active on high-level/rising-edge.

Slave Select Control Bits (Master Only)

If AUTOSS bit is cleared, writing 1 to any bit of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.

If the AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPI0_SS0/1 line at inactive state; writing 1 to any bit location of this field will select appropriate SPI0_SS0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time.

The active state of SPI0_SS0/1 is specified in SSACTPOL.

Note: SPI0_SS0 is defined as the slave select input in Slave mode.

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Revision 2.4


SPI DMA Control Register (SPI0_PDMACTL)


SPI0_PDMACT

L

SPI0_BA + 0x0C R/W SPI PDMA Control Register 0x0000_0000

Table 5-94 SPI0_PDMACTL Control Register (address SPI0_BA + 0x0C)

7 6 5

Reserved

4 3 2

PDMARST

1

RXPDMAEN

0

TXPDMAEN

Bits

[31:3]

Description

Reserved

[2]

[1]

[0]

PDMARST

RXPDMAEN

TXPDMAEN

Reserved.

PDMA Reset

0 = No effect.

1 = Reset the PDMA control logic of the SPI controller. This bit will be cleared to

0 automatically.

Receive PDMA Enable

Setting this bit to 1 will start the receive PDMA process. The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. This bit will be cleared to 0 by hardware automatically after PDMA transfer is done.

Transmit DMA Enable

Setting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.

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Revision 2.4


SPI FIFO Control Register (SPI0_FIFOCTL)


0x4400_0000 SPI0_FIFOCTL SPI0_BA + 0x10 R/W FIFO Control/Status Register

Table 5-95 SPI FIFO Control Register SPI0_FIFOCTL (address SPI0_BA + 0x10)

25 31 30 29 28 27 26

23

15

Reserved

22

14

21

13

7 6 5

TXUDFIEN TXUDFPOL RXOVIEN

TXTH Reserved

20 19

Reserved

12 11

Reserved

4

RXTOIEN

3

TXTHIEN

18

10

2

RXTHIEN

17

9

1

TXRST

RXTH

24

16

8

0

RXRST

Bits

[31:30]

Description

Reserved

[29:28]

[27:26]

[25:24]

[23:8]

[7]

[6]

TXTH

Reserved

RXTH

Reserved

TXUDFIEN

TXUDFPOL

Reserved.

Transmit FIFO Threshold

If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.

00: 1 word will transmit




Reserved.

Receive FIFO Threshold

If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the

RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.





Reserved.

Slave Transmit Under Run Interrupt Enable

0 = Slave Transmit FIFO under-run interrupt Disabled.

1 = Slave Transmit FIFO under-run interrupt Enabled.

Transmit Under-run Data Out

0 = The SPI data out is 0 if there is transmit under-run event in Slave mode.

1 = The SPI data out is 1 if there is transmit under-run event in Slave mode.

Note: The under run event is active after the serial clock input and the hardware synchronous, so that the first 1~3 bit (depending on the relation between system clock and the engine clock) data out will be the last transaction data.

Note: If the frequency of system clock approach the engine clock, they may be a 3-bit time

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Revision 2.4

[5] RXOVIEN

[4] RXTOIEN

[3] TXTHIEN

[2] RXTHIEN

[1] TXRST

[0] RXRST

ISD91200 Series Technical Reference Manual to report the transmit under-run data out.

Receive FIFO Overrun Interrupt Enable

0 = Receive FIFO overrun interrupt Disabled.

1 = Receive FIFO overrun interrupt Enabled.

Slave Receive Time-out Interrupt Enable

0 = Receive time-out interrupt Disabled.

1 = Receive time-out interrupt Enabled.

Transmit FIFO Threshold Interrupt Enable

0 = TX FIFO threshold interrupt Disabled.

1 = TX FIFO threshold interrupt Enabled.

Receive FIFO Threshold Interrupt Enable

0 = RX FIFO threshold interrupt Disabled.

1 = RX FIFO threshold interrupt Enabled.

Clear Transmit FIFO Buffer

0 = No effect.

1 = Clear transmit FIFO buffer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clocks + 3 SPI engine clock after it is set to 1.

Note: If there is slave receive time out event, the TXRST will be set 1 when the

SPI0_SSCTL.SLVTORST, is enabled.

Clear Receive FIFO Buffer

0 = No effect.

1 = Clear receive FIFO buffer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clocks + 3 SPI engine clock after it is set to 1.

Note: If there is slave receive time out event, the RXRST will be set 1 when the

SPI0_SSCTL.SLVTORST, is enabled.

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Revision 2.4


SPI Status Register (SPI0_STATUS)


SPI0_STATU

S

SPI0_BA + 0x14 R/W Status Register 0x0005_0110

Table 5-96 SPI Status Register SPI0_STATUS (address SPI0_BA + 0x14)

31 28 27 24

23

TXRXRST

15

SPIENSTS

7

SLVURIF

30 29

22

TXCNT

21

Reserved

14 13

Reserved

6

SLVBEIF

5

SLVTOIF

20

12

RXTOIF

4

SSLINE

19

TXUFIF

11

RXOVIF

3

SSINAIF

26 25

18

TXTHIF

RXCNT

17

TXFULL

10

RXTHIF

9

RXFULL

2

SSACTIF

1

UNITIF

16

TXEMPTY

8

RXEMPTY

0

BUSY


[31:28] TXCNT

[27:24] RXCNT

[23] TXRXRST

[22:20] Reserved

[19]

[18]

[17]

[16]

TXUFIF

TXTHIF

TXFULL

TXEMPTY

Transmit FIFO Data Count (Read Only)

This bit field indicates the valid data count of transmit FIFO buffer.

Receive FIFO Data Count (Read Only)

This bit field indicates the valid data count of receive FIFO buffer.

FIFO CLR Status (Read Only)

0 = Done the FIFO buffer clear function of TXRST and RXRST.

1 = Doing the FIFO buffer clear function of TXRST or RXRST.

Note: Both the TXRST, RXRST, need 3 system clock + 3 engine clocks, the status of this bit allows the user to monitor whether the clear function is busy or done.

Reserved.

Slave Transmit FIFO Under-run Interrupt Status (Read Only)

When the transmit FIFO buffer is empty and further serial clock pulses occur, data transmitted will be the value of the last transmitted bit and this under-run bit will be set.

Note: This bit will be cleared by writing 1 to itself.

Transmit FIFO Threshold Interrupt Status (Read Only)

0 = The valid data count of the transmit FIFO buffer is larger than the setting value of

TXTH.

1 = The valid data count of the transmit FIFO buffer is less than or equal to the setting value of TXTH.

Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI controller will generate a SPI interrupt request.

Transmit FIFO Buffer Full Indicator (Read Only)

0 = Transmit FIFO buffer is not full.

1 = Transmit FIFO buffer is full.

Transmit FIFO Buffer Empty Indicator (Read Only)

0 = Transmit FIFO buffer is not empty.

1 = Transmit FIFO buffer is empty.

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Revision 2.4

[15] SPIENSTS


[12] RXTOIF

[11] RXOVIF

[10] RXTHIF

[9] RXFULL

[8] RXEMPTY

[7] SLVURIF

[6] SLVBEIF

[5] SLVTOIF


SPI Enable Bit Status (Read Only)

0 = Indicate the transmit control bit is disabled.

1 = Indicate the transfer control bit is active.

Note: The clock source of SPI controller logic is engine clock, it is asynchronous with the system clock. In order to make sure the function is disabled in SPI controller logic, this bit indicates the real status of SPIEN in SPI controller logic for user.

Reserved.

Receive Time-out Interrupt Status

0 = No receive FIFO time-out event.

1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over

64 SPI clock period in Master mode or over 576 SPI engine clock period in Slave mode.

When the received FIFO buffer is read by software, the time-out status will be cleared automatically.


Receive FIFO Overrun Status

When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.


Receive FIFO Threshold Interrupt Status (Read Only)

0 = The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RXTH.

1 = The valid data count within the receive FIFO buffer is larger than the setting value of

RXTH.

Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI controller will generate a SPI interrupt request.

Receive FIFO Buffer Full Indicator (Read Only)

0 = Receive FIFO buffer is not full.

1 = Receive FIFO buffer is full.

Receive FIFO Buffer Empty Indicator (Read Only)

0 = Receive FIFO buffer is not empty.

1 = Receive FIFO buffer is empty.

Slave Mode Error 1 Interrupt Status (Read Only)

In Slave mode, transmit under-run occurs when the slave select line goes to inactive state.

0 = No Slave mode error 1 event.

1 = Slave mode error 1 occurs.

Slave Mode Error 0 Interrupt Status (Read Only)

In Slave mode, there is bit counter mismatch with DWIDTH when the slave select line goes to inactive state.

0 = No Slave mode error 0 event.

1 = Slave mode error 0 occurs.

Note: If the slave select active but there is no any serial clock input, the SLVBEIF also active when the slave select goes to inactive state.

Slave Time-out Interrupt Status (Read Only)

When the Slave Select is active and the value of SLVTOCNT is not 0 and the serial clock input, the slave time-out counter in SPI controller logic will be start. When the value of time-out counter greater or equal than the value of SPI0_SSCTL.SLVTOCNT, during before one transaction done, the slave time-out interrupt event will active.

0 = Slave time-out is not active.

1 = Slave time-out is active.

Note: If the DWIDTH is set 16, one transaction is equal 16 bits serial clock period.

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Revision 2.4

[4] SSLINE

[3] SSINAIF

[2] SSACTIF

[1] UNITIF

[0] BUSY


Slave Select Line Bus Status (Read Only)

0 = Indicates the slave select line bus status is 0.

1 = Indicates the slave select line bus status is 1.

Note: If SPI0_SSCTL.SSACTPOL is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.

Slave Select Inactive Interrupt Status

0 = Slave select inactive interrupt is clear or not occur.

1 = Slave select inactive interrupt event has occur.


Slave Select Active Interrupt Status

0 = Slave select active interrupt is clear or not occur.

1 = Slave select active interrupt event has occur.


Unit Transfer Interrupt Status

0 = No transaction has been finished since this bit was cleared to 0.

1 = SPI controller has finished one unit transfer.


SPI Unit Bus Status (Read Only)

0 = No transaction in the SPI bus.

1 = SPI controller unit is in busy state.

The following listing are the bus busy conditions:

SPIEN = 1 and the TXEMPTY = 0.

For SPI Master, the TXEMPTY = 1 but the current transaction is not finished yet.

For SPI Slave receive mode, the SPIEN = 1 and there is serial clock input into the SPI core logic when slave select is active.

For SPI Slave transmit mode, the SPIEN = 1 and the transmit buffer is not empty in SPI core logic event if the slave select is inactive.

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Revision 2.4


SPI Receive Transaction Count (SPI0_RXTSNCNT)


SPI0_RXTSNCNT SPI0_BA + 0x18 R/W Receive Transaction Count Register

Table 5-97 SPI Receive Transaction Count (address SPI0_BA + 0x18)

Reset Value

0x0000_0000

15

7

14

6

13

5

12

RXTSNCNT

11

4 3

RXTSNCNT

10

2

9

1

8

0

Bits

[31:16]

[16:0]

Table 5-98 SPI Receive Transaction Count (SPI0_RXTSNCNT, address SPIx_BA + 0x18)

Description

Reserved

RXTSNCNT

Reserved.

DMA Receive Transaction Count

When using DMA to receive SPI data without transmitting data, this register can be used in conjunction with the control bit SPI0_CTL.RXTCNTEN to set number of transactions to perform. Without this, the SPI interface will only initiate a transaction when it receives a request from the DMA system, resulting in a lower achievable data rate.

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Revision 2.4


SPI Data Transmit Register (SPI0_TX)


SPI0_BA + 0x20 W FIFO Data Transmit Register SPI0_TX

31 30 29 28 27

TX

23 22 21 20 19

TX

15 14 13 12 11

TX

7 6 5 4 3

TX

26

18

10

2

25

17

9

1

Table 5-99 SPI Data Transmit Register (SPI0_TX, address SPIx_BA + 0x20)

Reset Value

0x0000_0000

24

16

8

0


[31:0] TX

Data Transmit Register

A write to the data transmit register pushes data onto into the 8-level transmit FIFO buffer. The number of valid bits depends on the setting of transmit bit width field of the SPI0_CTL register.

For example, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0, the SPI controller will perform a 32-bit transfer.

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Revision 2.4


SPI Data Receive Register (SPI0_RX)


SPI0_BA + 0x30 R FIFO Data Receive Register SPI0_RX

31 30 29 28 27

RX

23 22 21 20 19

RX

15 14 13 12 11

RX

7 6 5 4 3

RX

26

18

10

2

25

17

9

1

Table 5-100 SPI Data Receive Register (SPI0_RX, address SPIx_BA + 30)

Reset Value

0x0000_0000

24

16

8

0


[31:0] RX

Data Receive Register

A read from this register pops data from the 8-level receive FIFO. Valid data is present if the

SPI0_STATUS. RXEMPTY bit is not set to 1. This is a read-only register.

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Revision 2.4


5.10 Serial 1 Peripheral Interface (SPI1) Controller

5.10.1 Overview

The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol which operates in full duplex mode. Devices communicate in master/slave mode with 4-wire bi-directional interface. The ISD91200 contains an SPI controller performing a serial-to-parallel conversion of data received from an external device, and a parallel-to-serial conversion of data transmitted to an external device. The SPI1 controller can be set as a master; also can be set as a slave controlled by an off-chip master device.

5.10.2 Features

 Supports master or slave mode operation.

 Configurable word length of up to 32 bits. Up to two words can be transmitted per a transaction, giving a maximum of 64 bits for each data transaction.

 Provide burst mode operation.

 MSB or LSB first transfer.

 2 device/slave select lines in master mode, single device/slave select line in slave mode.

 Byte or word Sleep Suspend Mode .

 Support dual FIFO mode.

 PDMA access support.

5.10.3 SPI1 Block Diagram

Clock Generator

APB

IF

(32-bits) Status/Control

Register

SPI1_SCLK

SPI1_SSB

PDMA

Control

Core Logic

PIO

TX Bufer/

TX Bufer/

Shifter

RX Bufer/

RX Bufer/

Shifter

Figure 5-52 SPI1 Block Diagram

SPI1_MOSI

SPI1_MISO

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Revision 2.4


5.10.4 SPI1 Function Descriptions

5.10.4.1 SPI Engine Clock and SPI Serial Clock

The SPI controller derives its clock source from the system HCLK as determined by the CLKSEL1 register. The frequency of the SPI master clock is determined by the divisor ratio SPI1_CLKDIV.

In Master mode, the output frequency of the SPI serial clock output pin is equal to the SPI engine clock rate. In general, the SPI serial clock is denoted as SPI clock. In Slave mode, the SPI serial clock is provided by an off-chip master device. The SPI engine clock rate of slave device must be faster than the SPI serial clock rate of the master device. The frequency of SPI engine clock cannot be faster than the APB clock rate regardless of Master or Slave mode.

5.10.4.2 Master/Slave Mode

This SPI1 controller can be configured as in master or slave mode by setting the SLAVE bit

(SPI1_CTL.SLAVE). In master mode the ISD91200 generates SCLK and SSB signals to access one or more slave devices. In slave mode the ISD91200 monitors SCLK and SSB signals to respond to data transactions from an off-chip master. The signal directions are summarized in the below application block diagrams.

SCLK

MISO

I91200

SPI1 Controller

Master

MOSI

SSB

SCLK

MISO

MOSI

SS

Slave 0

Figure 5-53 SPI1 Master Mode Application Block Diagram

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Revision 2.4


SCLK

MISO

I91200

SPI1 Controller

Slave

MOSI

SSB

SCLK

MISO

MOSI

SS

Master

5.10.4.3 Slave Select

Figure 5-54 SPI1 Slave Mode Application Block Diagram

In master mode, the SPI controller can address up to one off-chip slave devices through the slave select output pins SPI1_SSB. Only one slave can be addressed at any one time. If more slave address lines are required, GPIO pins can be manually configured to provide additional SSB lines. In slave mode, the off-chip master device drives the slave select signal SPI_SSB to address the SPI1 controller.

The slave select signal can be programmed to be active low or active high via the SPI1_SSCTL.SSLVL bit. In addition the SPI1_SSCTL.SSLTRIG bit defines whether the slave select signals are level triggered or edge triggered. The selection of trigger condition depends on what type of peripheral slave/master device is connected.

5.10.4.4 Automatic Slave Select

In master mode, if the bit SPI1_SSCTL.AUTOSS is set, the slave select signals will be generated automatically and output to SPI1_SSB pins according to registers SPI1_SSCTL.SS. In this mode, SPI controller will assert SSB when transaction is triggered and de-assert when data transfer is finished. If the SPI1_SSCTL.AUTOSS bit is cleared, the slave select output signals are asserted and de-asserted by manual setting and clearing the related bits in the SPI1_SSCTL.SS register. The active level of the slave select output signals is specified by the SPI1_SSCTL.SSLVL bit.

5.10.4.5 Serial Clock

In master mode, writing a divisor into the SPI1_CLKDIV register will program the output frequency of serial clock to the SPI1_SCLK output port. In slave mode, the off-chip master device drives the serial clock through the SPI1_SCLK.

5.10.4.6 Clock Polarity

The SPI1_CTL.CLKP bit defines the serial clock idle state in master mode. If CLKP = 1, the output

SPI1_SCLK is high in idle state. If CLKP=0, it is low in idle state.

5.10.4.7 Transmit/Receive Bit Length

The bit length of a transfer word is defined in SPI1_CTL.TXBITLEN bit field. It is set to define the length of a transfer word and can be up to 32 bits in length. TXBITLEN=0x0 enables 32bit word length.

5.10.4.8 Burst Mode

The SPI controller has a burst mode controlled by the SPI1_CTL.TXNUM field. If set to 0x01, SPI controller will burst two transactions from the SPI1_TX0 and SPI1_TX1 registers as shown in the waveform below:

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Revision 2.4


Word suspend

SPICLK

CLK

MISO

CLK =

= 0

1

MS

0 [ 31 ]

MOSI

Tx 0 [ 30 ] Tx 0 [ 0 ]

Rx

MS

0 [ 31 ]

Rx 0 [ 30 ]

1st Transaction Word

Rx 0 [ 0 ]

Tx

Rx 1

1 [ 31 ] Tx 1 [ 30 ]

[ 31 ] Rx 1 [ 30 ]

LSB

1 [ 0 ]

LSB

Rx 1 [ 0 ]

2 nd Transaction Word

Figure 5-55 Two Transactions in One Transfer (Burst Mode)

5.10.4.9 LSB First

The SPI1_CTL.LSB bit defines the bit order of data transmission. If LSB=0 then MSB of transfer word is sent first in time. If LSB=1 then LSB of transfer word is sent first in time.

5.10.4.10 Transmit Edge

The SPI1_CTL.TXNEG bit determines whether transmit data is changed on the positive or negative edge of the SPI1_SCLK serial clock. If TXNEG=0 then transmitted data will change state on the rising edge of SPI1_SCLK. If TXNEG=1 then transmitted data will change state on the falling edge of

SPI1_SCLK.

5.10.4.11 Receive Edge

The SPI_CTL.RXNEG bit determines whether data is received at either the negative edge or positive edge of serial clock SPI1_SCLK. If RXNEG=1 then data is clocked in on the falling edge of SPI1_SCLK.

If RXNEG=0 data is clocked in on the rising edge of SPI1_SCLK. Note that RXNEG should be the inverse of TXNEG for standard SPI operation.

5.10.4.12 Word Sleep Suspend

The bit field SPI1_CTL.SLEEP provides a configurable suspend interval of SLEEP+2 serial clock periods between successive word transfers in master mode. The suspend interval is from the last falling clock edge of the preceding transfer word to the first rising clock edge of the following transfer word if

CLKP = 0. If CLKP = 1, the interval is from the rising clock edge of the preceding transfer word to the falling clock edge of the following transfer word. The default value of SLEEP is 0x0 (2 serial clock cycles). Word Sleep only occurs when TXNUM=1. For TXNUM=0, this parameter will determine a Byte

Sleep condition if the BYTESLEEP bit is set.

Word

Sleep

CLKP=0

SPICLK

CLKP=1

MISO

MOSI

MSB

Tx0[31]

MSB

Rx0[31]

Tx0[30]

Rx0[30]

1st Transfer Word

Tx0[0]

Rx0[0]

Tx1[31] Tx1[30]

Rx1[31] Rx1[30]

2nd Transfer Word

LSB

Tx1[0]

LSB

Rx1[0]

Figure 5-56 Word Sleep Suspend Mode

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Revision 2.4


5.10.4.13 Byte Endian

APB access to the SPI controller is via the 32bit wide TX and RX registers. When the transfer is set as

MSB first (SP1I_CTL.LSB = 0) and the SPI1_CTL.BYTEENDIAN bit is set, the data stored in the TX buffer and RX buffer will be rearranged such that the least significant physical byte is processed first.

For TXBITLEN =0 (32 bits transfer), the sequence of transmitted/received data will be BYTE0, BYTE1,

BYTE2, and then BYTE3. If TXBITLEN is set to 24-bits, the sequence will be BYTE0, BYTE1, and

BYTE2. The rule of 16-bits mode is the same as above.

SPI->TX[0]/SPI->RX[0]

MSB first

Byte3 Byte2 Byte1 Byte0

[31:24] [23:16] [15:8] [7:0]

LSB = 0 (MSB first)

BYTE_ENDIAN = 1

MSB first

TX/RX Buffer


TX_BIT_LEN = 32 bits

MSB first



MSB first



N/A N/A


MSB first

N/A Byte0

BYTE_ENDIAN = 0

MSB first

TX/RX Buffer



MSB first



MSB first



N/A N/A


MSB first

N/A Byte0

Time

Figure 5-57 Byte Re-Ordering Transfer

Byte ordering can be a confusing issue when converting from arrays of data processed by the CPU for transmission out the SPI port. The CortexM0 stores data in a little endian format; that is the LSB of a multi-byte word or half-word are stored first in memory. Consider how the CortexM0 stores the following arrays in memory:

3. unsigned char ucSPI_DATA[]={0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08};

4. unsigned int uiSPI_DATA[]={0x01020304, 0x05060708}; unsigned char ucSPI_DATA[]={0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08}; unsigned int uiSPI_DATA[]={0x01020304, 0x05060708};


0x20000014

0x20000010

0x2000000c uiSPI_DATA[]

→ 0x20000008


→ 0x20000000

0x08

0x04

0x05

0x01

APB Data Bus [7:0]

0x07

0x03

0x06

0x02

0x06

0x02

0x07

0x03

0x05

0x01

0x08

0x04

[15:8] [23:16] [31:24]


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Revision 2.4


It can be seen from Figure 5-58 Byte Order in Memory that byte order for an array of bytes is different

than that of an array of words. Now consider if this data were to be sent to the SPI port; the user could:

3. Set TXBITLEN=8 and send data byte-by-byte SPI1_TX[0] = ucSPI_DATA[i++]

4. Set TXBITLEN=32 and send word-by-word SPI1_TX[0] = uiSPI_DATA[i++]

Both of these would result in the byte stream {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08} being sent.

It would be common that a byte array of data is constructed but user, for efficiency, wishes to transfer data to SPI via word transfers. Consider the situation of below figure where a int pointer points to the byte data array. unsigned char ucSPI_DATA[]={0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08}; unsigned int *uiSPI_DATA = (unsigned int *)ucSPI_DATA[]; uiSPI_DATA[]

→


0x20000014

0x20000010

0x2000000c

Byte0

Byte0

0x08

0x20000008


→ 0x20000000

0x04

0x05

0x01

Byte1

Byte1

0x07

0x03

0x06

0x02

Byte2

Byte2

0x06

0x02

0x07

0x03

Byte3

Byte3

0x05

0x01

0x08

0x04

APB Data Bus [7:0] [15:8] [23:16] [31:24]


Now if we set TXBITLEN=32 and sent word-by-word SPI1_TX0 = uiSPI_DATA[i++], the order transmitted would be {0x04, 0x03, 0x02, 0x01, 0x08, 0x07, 0x06, 0x05}. However if we set

BYTEENDIAN=1, we would reverse this order to the desired stream: {0x01, 0x02, 0x03, 0x04, 0x05,

0x06, 0x07, 0x08}.

5.10.4.14 Byte Sleep Suspend

In master mode, if SPI1_CTL.BYTESLEEP is set to 1, the hardware will insert a suspend interval of

SPI1_CTL.SLEEP+2 serial clock periods between two successive bytes in a transfer word. Note that the byte suspend function is only valid for 32bit word transfers, that is TXBITLEN=0x00.

Byte

Sleep

Byte

Sleep

CLKP=0

SPICLK

CLKP=1

MISO

MOSI

MSB

Tx0[31]

MSB

Rx0[31]

Tx0[30]

Rx0[30]

1st Transfer Byte

Tx0[24]

Rx0[24]

Tx0[23] Tx0[22]

Rx0[23] Rx0[22]

Tx0[16]

Rx0[16]

2nd Transfer Byte

Transfer Word

Figure 5-60 Byte Suspend Mode

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Revision 2.4


5.10.4.15 Interrupt

The SPI controller can generate a CPU interrupt when data transfer is finished. When a transfer request triggered by EN is finished, the interrupt flag (SPI_CTL.IF) will be set by hardware. If the SPI interrupt is enabled (SPI1_CTL.IE) this will also generate a CPU interrupt. To clear the interrupt event flag, software must write a ‘1’ to it.

5.10.4.16 FIFO Mode

The SPI controller supports a dual buffer mode when SPI_CTL.FIFO is set as 1. In normal mode, software can only update the transmitted data when the current transmission is done. In FIFO mode, the next transmitted data can be written into the SPI_TX buffer at any time when in master mode or the

EN bit is set in slave mode. This data will load into the transmit buffer when the current transmission done.

After the FIFO bit is set, transmission is repeated automatically when the transmitted data is updated in time and it will continue until this bit is cleared. When cleared, the transmission will finish when the current transmission done. The user can also read the received data at any time before the next transmission is complete, wherein the receive buffer will be updated with new received data. If transmit data isn’t updated before the current transmission is done, the transaction will stop. The transmission will resume automatically when transmit data is written into this buffer again.

Before the FIFO bit is set, the user can write first data into SPI1_TX buffer. Setting FIFO active will load the first data into the current transmission buffer. A subsequent write to SPI_TX will load the TX FIFO which will be loaded into the transmission buffer after the 1st transmission is done.

This function is also supported in slave mode. The EN must be set as 1 before the external serial clock input and it will keep going until the FIFO is cleared.

The delay period between two transmissions is programmable. It is the same as the suspend interval on SLEEP parameter.

5.10.4.17 Two Channel Mode

The SPI controller supports a two channel mode where data can be sent and received on alternate

MOSI1 and MISO1 lines concurrently with data on MOSI0 and MISO0. The data for this second channel is the SPI1_RX1 and SPI1_TX1 buffers. Mode is enabled by setting the SPI_CTL.TWOB bit.

This mode is only available when TXNUM=0.

SPI->SS

SS.LVL=1

SS.LVL=0

CLKP=0

SPICLK

CLKP=1

MISOx0

MOSIx0

MISOx1

MSB

Tx0[31]

MSB

Rx0[31]

MSB

Tx1[31]

Tx0[30]

Rx0[30]

Tx1[30]

Tx0[16]

Rx0[16]

Tx1[16]

Tx0[15]

Rx0[15]

Tx1[15]

Tx0[14]

Rx0[14]

Tx1[14]

LSB

Tx0[0]

LSB

Rx0[0]

LSB

Tx1[0]

MOSIx1

MSB

Rx1[31]

Rx1[30] Rx1[16] Rx1[15] Rx1[14]

LSB

Rx1[0]

Figure 5-61 Two Bits Transfer Mode

5.10.4.18 Variable Serial Clock Frequency

In master mode 16 bit transfers, the output of serial clock can be programmed as variable frequency pattern if the Variable Clock Enable bit SPI1_CTL.VARCLKEN is enabled. The frequency pattern format is defined in SP1I_VARCLK register. If the bit content of VARCLK is ‘0’ the output period for that bit is

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Revision 2.4

ISD91200 Series Technical Reference Manual determined by setting of SPI1_CLKDIV, if the bit content of VARCLK is ‘1’, the output period for that bit is determined by the SPI1_ CLKDIV.DIV1 register. The following figure shows the timing relationships of serial clock (SCLK), to the VARCLK, the DIV0 and the DIV1 registers. A two-bit combination in the

VARCLK defines one clock cycle. The bit field VARCLK[31:30] defines the first clock cycle of SCLK.

The bit field VARCLK[29:28] defines the second clock cycle of SCLK and so on. The clock source selections are defined in VARCLK and must be set 1 cycle before the next clock option. For example, if there are 5 CLK1 cycle in SPICLK, the VARCLK shall set 9 ‘0’ in the MSB of VARCLK. The 10th shall be set as ‘1’ in order to switch the next clock source is CLK2. Note that when VARCLKEN bit is set, the setting of TXBITLEN must be programmed as 0x10 (16 bits mode only).

SPICLK

VARCLK

00000000011111111111111110000111

CLK1 (DIV)

CLK2 (DIV2)

Figure 5-62 Variable Serial Clock Frequency

5.10.5 SPI Timing Diagram

In master/slave mode, the device address/slave select (SPI_SSB) signal can be configured as active low or active high by the SPI1_ SSCTL.SSLVL bit. In slave mode, the SPI1>- SSCTL.SSLTRIG will determine whether the slave select signal is treated as a level triggered or edge triggered signal.

The serial clock phase and polarity is controlled by CLKP, RXNEG and TXNEG bits. The bit length of a transfer word is configured by the TXBITLEN parameter. Whether data transmission is MSB first or LSB first is controlled by the SPI1_CTL.LSB bit. Four examples of SPI timing diagrams for master/slave operations and the related settings are shown as below.

SPI->SS

SS.LVL=1

SS.LVL=0

SPICLK

CLKP=0

CLKP=1

MOSI

MISO

MSB

Tx0[7]

MSB

Rx0[7]

Tx0[6]

Rx0[6]

Tx0[5]

Rx0[5]

Tx0[4] Tx0[3]

Rx0[4] Rx0[3]

Tx0[2]

Rx0[2]

Tx0[1]

Rx0[1]

LSB

Tx0[0]

LSB

Rx0[0]

Master Mode: CTL.SLVAE=0, CTL.LSB=0, CTL.TXNUM=0x0, CTL.TXBITLEN=0x08

1. CTL.CLKP=0, CTL.TXNEG=1, CTL.RXNEG=0 or

2. CTL.CLKP=1, CTL.TXNEG=0, CTL.RXNEG=1

Figure 5-63 SPI Timing in Master Mode

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Revision 2.4


SPI->SS

SS.LVL=1

SS.LVL=0

SPICLK

CLKP=0

CLKP=1

MOSI

MISO

LSB

Tx0[0]

LSB

Rx0[0]

Tx0[1]

Rx0[1]

Tx0[2]

Rx0[2]

Tx0[3] Tx0[4]

Rx0[3] Rx0[4]

Tx0[5] Tx0[6]

Rx0[5] Rx0[6]

MSB

Tx0[7]

MSB

Rx0[7]

Master Mode: CTL.SLVAE=0, CTL.LSB=1, CTL.TXNUM=0x0, CTL.TXBITLEN=0x08



Figure 5-64 SPI Timing in Master Mode (Alternate Phase of SPICLK)

SPI->SS

SS.LVL=1

SS.LVL=0

SPICLK

CLKP=0

CLKP=1

MISO

MOSI

MSB

Tx0[7]

MSB

Rx0[7]

Tx0[6]

Rx0[6]

Tx0[0] Tx1[7] Tx1[6]

Rx0[0] Rx1[7] Rx1[6]

Slave Mode: CTL.SLVAE=1, CTL.LSB=0, CTL.TXNUM=0x01, CTL.TXBITLEN=0x08



LSB

Tx1[0]

LSB

Rx1[0]

Figure 5-65 SPI Timing in Slave Mode

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Revision 2.4


SPI->SS

SS.LVL=1

SS.LVL=0

SPICLK

CLKP=0

CLKP=1

MISO

MOSI

LSB

Tx0[0]

LSB

Rx0[0]

Tx0[1]

Rx0[1]

Tx0[7] Tx1[0]

Rx0[7] Rx1[0]

Tx1[6]

Rx1[6]

MSB

Tx1[7]

MSB

Rx1[7]

Slave Mode: CTL.SLVAE=1, CTL.LSB=1, CTL.TXNUM=0x01, CTL.TXBITLEN=0x08


2. CTL.CLKP=1, CT.LTXNEG=1, CTL.RXNEG=0

Figure 5-66 SPI Timing in Slave Mode (Alternate Phase of SPICLK)

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Revision 2.4


5.10.6 SPI Configuration Examples

 Example 1, SPI controller is set as a master to access an off-chip slave device with following specifications:



 Data be transferred from MSB first

 SCLK low in idle state


 Slave select signal is active low

 SCLK frequency is 10MHz


10) Write a divisor into the SPI1_CLKDIV register to determine the output frequency of serial clock.

11) Configure the SPI1_ SSCTL register to address device. For example to manually address, set

SPI1_SSCTL.ASS=0, SPI1_SSCTL.SSLVL=0 for active low SS. When software wishes to address device it will set SPI1_ SSCTL.SSR=1 to output an active SS on SPI1_SSB pin.

12) Configure the SPI1_CTL register. Set SPI1_CTL.SLAVE=0 for master mode, set

SPI1_CTL.CLKP=0 for SCLK polarity normally low, set SPI1_CTL.TXNEG=1 so that data changes on falling edge of SCLK, set SPI1_CTL.RXNEG=0 so that data is latched into device on positive edge of SCLK, set SPI1_CTL.TXBITLEN=8 and SPI_CNTRL.TXNUM=0 for a single byte transfer and finally set SPI1_CTL.LSB=0 for MSB first transfer.

13) If manually selecting slave device set SPI1_ SSCTL.SSR=1.

14) To transmit one byte of data, write data to SPI1_TX0 register. If only doing a receive, write a dummy byte to SPI1_TX0 register.

15) Enable the SPI1_CTL.EN bit to start the data transfer over the SPI interface.

-- Wait for SPI transfer to finish. Can be interrupt driven (if the interrupt enable SPI_CTL.IE bit is set) or by polling the EN bit which will be cleared to 0 by hardware automatically at end of transmission.

16) Read out the received one byte data from SPI1_ RX0

17) Go to 5) to continue another data transfer or set SPI1_ SSCTL.SSR=0 to deactivate the off-chip slave devices.

 Example 2, SPI controller is set as a slave device that controlled by an off-chip master device with the following characteristics:



 Data be transferred from LSB first

 SCLK high in idle state


 Slave select signal is active high level trigger

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Revision 2.4



8) Configure the SPI1_ SSCTL register. SPI1_ SSCTL.SSLVL=1 for active high slave select, SPI1_

SSCTL.SSR.SSLTRIG=1 for level sensitive trigger.

9) Configure the SPI1_CTL register. Set SPI1_CTL.SLAVE=1 for slave mode, set SPI1_CTL.CLKP=1 for SCLK polarity idle high, set SPI1_CTL.TXNEG=1 so that data changes on falling edge of SCLK, set SPI1_CTL.RXNEG=0 so that data is latched into device on positive edge of SCLK, set

SPI1_CTL.TXBITLEN=8 and SPI1_CTL.TXNUM=0 for a single byte transfer and finally set

SPI1_CTL.LSB=1 for LSB first transfer.

10) If SPI slave is to transmit one byte of data to the off-chip master device, write first byte to TX[0] register. If no data to be transmitted write a dummy byte.

11) Enable the EN bit to wait for the slave select trigger input and serial clock input from the off-chip master device to start the data transfer at the SPI interface.

-- -- Wait for SPI transfer to finish. Can be interrupt driven (if the interrupt enable SPI1_CTL.IE bit is set) or by polling the EN bit which will be cleared to 0 by hardware automatically at end of transmission. --

12) Read out the received data from SPI1_RX0 register.

13) Go to 3) to continue another data transfer or disable the EN bit to stop data transfer.

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Revision 2.4





SPI1 Base Address:

SPI1_BA = 0x4003_8000

SPI1_CTL SPI1_BA + 0x00

SPI1_CLKDIV SPI1_BA + 0x04

SPI1_BA + 0x08 SPI1_SSCTL

SPI1_RX0 SPI1_BA + 0x10

R/W

R/W

R/W

R

Control and Status Register

Clock Divider Register (Master Only)

Slave Select Register

Data Receive Register 0

SPI1_RX1

SPI1_TX0

SPI1_TX1

SPI1_VARCLK

SPI1_PDMACTL

SPI1_BA + 0x14

SPI1_BA + 0x20

SPI1_BA + 0x24

SPI1_BA + 0x34

SPI1_BA + 0x38

R

W

W

R/W

R/W

Data Receive Register 1

Data Transmit Register 0

Data Transmit Register 1

Variable Clock Pattern Register

SPI PDMA Control Register

Reset Value

0x0500_0004

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x007F_FF87

0x0000_0000

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Revision 2.4



SPI Control and Status Register (SPI_CTL)


SPI1_BA + 0x00 R/W Control and Status Register SPI1_CTL

31

23

VARCLKEN

15

7

30

Reserved

22

TWOB

14

29

21

FIFO

13

6

SLEEP

5

TXBITLEN

28

DMABURST

27

TXFULL

20 19

BYTEENDIAN BYTESLEEP

12 11

4

CLKP

3

26

TXEMPTY

18

SLAVE

10

LSB

2

TXNEG

25

RXFULL

17

IE

9

TXNUM

1

RXNEG

Reset Value

0x0500_0004

24

RXEMPTY

16

IF

8

0

EN

Table 5-101 SPI Control and Status Register (SPI_CTL, address 0x4003_8000)

Bits

[31:28]

[28]

[27]

[26]

[25]

[24]

[23]

Description

Reserved

DMABURST

TXFULL

TXEMPTY

RXFULL

RXEMPTY

VARCLKEN

Reserved

Enable DMA Automatic SS function.

When enabled, interface will automatically generate a SS signal for an entire PDMA access transaction.

Transmit FIFO FULL STATUS

1 = The transmit data FIFO is full.

0 = The transmit data FIFO is not full.

Transmit FIFO EMPTY STATUS

1 = The transmit data FIFO is empty.

0 = The transmit data FIFO is not empty.

Receive FIFO FULL STATUS

1 = The receive data FIFO is full.

0 = The receive data FIFO is not full.

Receive FIFO EMPTY STATUS

1 = The receive data FIFO is empty.

0 = The receive data FIFO is not empty.

Variable Clock Enable (Master Only)

1 = SCLK output frequency is variable. The output frequency is determined by the value of VARCLK, DIVIDER, and DIVIDER2.

0 = The serial clock output frequency is fixed and determined only by the value of DIVIDER.

Note that when enabled, the setting of TXBITLEN must be programmed as

0x10 (16 bits mode)

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Revision 2.4


[22]

[21]

[20]

[19]

[18]

[17]

[16]

[15:12]

[11]

TWOB

FIFO

BYTEENDIAN

BYTESLEEP

SLAVE

IE

IF

SLEEP

CLKP

Two Bits Transfer Mode

1 = Enable two-bit transfer mode.

0 = Disable two-bit transfer mode.

Note that when enabled in master mode, MOSI data comes from

SPI1_TX0 and MOSI data from SPI1_TX1. Likewise SPI1_RX0 receives bit stream from MISO0 and SPI1_RX1 from MISO1. Note that when enabled, the setting of TXNUM must be programmed as 0x00

FIFO Mode

0 = No FIFO present on transmit and receive buffer.

1 = Enable FIFO on transmit and receive buffer.

Byte Endian Reorder Function

This function changes the order of bytes sent/received to be least significant physical byte first.

Insert Sleep interval between Bytes

This function is only valid for 32bit transfers (TXBITLEN=0). If set then a pause of (SLEEP+2) SCLK cycles is inserted between each byte transmitted.

Master Slave Mode Control

0 = Master mode.

1 = Slave mode.

Interrupt Enable

0 = Disable SPI Interrupt.

1 = Enable SPI Interrupt to CPU.

Interrupt Flag

0 = Indicates the transfer is not finished yet.

1 = Indicates that the transfer is complete. Interrupt is generated to CPU if enabled.

NOTE : This bit is cleared by writing 1 to itself.

Suspend Interval (Master Only)

These four bits provide configurable suspend interval between two successive transmit/receive transactions in a transfer. The suspend interval is from the last falling clock edge of the current transaction to the first rising clock edge of the successive transaction if CLKP = 0. If CLKP = 1, the interval is from the rising clock edge to the falling clock edge. The default value is 0x0. When TXNUM = 00b, setting this field has no effect on transfer except as determined by REORDER[0] setting. The suspend interval is determined according to the following equation:

(SLEEP[3:0] + 2) * period of SCLK

Clock Polarity

0 = SCLK idle low.

1 = SCLK idle high.

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Revision 2.4

[10]

[9:8]

LSB

TXNUM


LSB First

0 = The MSB is transmitted/received first (which bit in SPI1_TX0/1 and

SPI1_RX0/1 register that is depends on the TXBITLEN field).

1 = The LSB is sent first on the line (bit 0 of SPI1_TX0/1), and the first bit received from the line will be put in the LSB position in the Rx register (bit 0 of SPI1_RX0/1).

Transmit/Receive Word Numbers

This field specifies how many transmit/receive word numbers should be executed in one transfer.

00 = Only one transmit/receive word will be executed in one transfer.

01 = Two successive transmit/receive word will be executed in one transfer.

10 = Reserved.

11 = Reserved.

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Revision 2.4

[7:3]

[2]

TXBITLEN

TXNEG


Transmit Bit Length

This field specifies how many bits are transmitted in one transmit/receive.

Up to 32 bits can be transmitted.

00001 = 1 bit

00010 = 2 bit

00011 = 3 bit

00100 = 4 bit

00101 = 5 bit

00110 = 6 bit

00111 = 7 bit

01000 = 8 bit

01001 = 9 bit

01010 = 10 bit

01011 = 11 bit

01100 = 12 bit

01101 = 13 bit

01110 = 14 bit

01111 = 15 bit

10000 = 16 bit

10001 = 17 bit

10010 = 18 bit

10011 = 19 bit

10100 = 20 bit

10101 = 21 bit

10110 = 22 bit

10111 = 23 bit

11000 = 24 bit

11001 = 25 bit

11010 = 26 bit

11011 = 27 bit

11100 = 28 bit

11101 = 29 bit

11110 = 30 bit

11111 = 31 bit

00000 = 32 bit

Transmit At Negative Edge

0 = The transmitted data output signal is changed at the rising edge of

SCLK.

1 = The transmitted data output signal is changed at the falling edge of

SCLK.

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Revision 2.4


[1]

[0]

RXNEG

EN

Receive At Negative Edge

0 = The received data input signal is latched at the rising edge of SCLK.

1 = The received data input signal is latched at the falling edge of SCLK.

Go and Busy Status

0 = Writing 0 to this bit has no effect.

1 = Writing 1 to this bit starts the transfer. This bit remains set during the transfer and is automatically cleared after transfer finished.

NOTE : All registers should be set before writing 1 to this EN bit. When a transfer is in progress, writing to any register of the SPI master/slave core has no effect.

SPI Divider Register (DIVIDER)


SPI1_CLKDIV

31

SPI1_BA + 0x04 R/W Clock Divider Register (Master Only)

30 29 26 25

0x0000_0000

24

23

15

7

22

14

6

21

13

5

28 27

20

CLKDIV1

19

12

CLKDIV1

11

4

CLKDIV0

3

CLKDIV0

18

10

2

17

9

1

16

8

0

Table 5-102 SPI Control and Status Register (SPI_CTL, address 0x4003_8004)

Bits

[31:16]

Description

CLKDIV1 Clock Divider 2 Register (master only)

The value in this field is the 2 nd

frequency divider of the system clock,

PCLK, to generate the serial clock on the output SCLK. The desired frequency is obtained according to the following equation: f sclk

= f pclk

(

DIVIDER

2

+

1 ) * 2

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Revision 2.4


[15:0] CLKDIV0 Clock Divider Register (master only)

The value in this field is the frequency division of the system clock, PCLK, to generate the serial clock on the output SCLK. The desired frequency is obtained according to the following equation: f sclk

= f

( pclk

DIVIDER

+

1 ) * 2

In slave mode, the period of SPI clock driven by a master shall satisfy f sclk

≤ f

5 pclk

In other words, the maximum frequency of SCLK clock is one fifth of the

SPI peripheral clock.

SPI Slave Select Register (SSCTL)


SPI1_BA + 0x08 R/W Slave Select Register SPI1_SSCTL

31 30 29

23

15

7

Reserved

22

14

6

21

13

5

LTRIGFLAG

28 27

Reserved

20 19

Reserved

12 11

Reserved

4

SSLTRIG

3

ASS

26

18

10

2

SSLVL

25

17

9

1

Reserved

Table 5-103 SPI Slave Select Register (SSCTL, address 0x4003_8008)

Reset Value

0x0000_0000

24

16

8

0

SSR

Bits

[31:6]

Description

Reserved

[5] LTRIGFLAG

Reserved

Level Trigger Flag

When the SSLTRIG bit is set in slave mode, this bit can be read to indicate the received bit number is met the requirement or not.

1 = The received number and received bits met the requirement which defines in TXNUM and TXBITLEN among one transfer.

0 = One of the received number and the received bit length doesn’t meet the requirement in one transfer.

Note: This bit is READ only

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Revision 2.4


[4]

[3]

[2]

[1]

[0]

SSLTRIG

ASS

SSLVL

Reserved

SSR

Slave Select Level Trigger (Slave only)

0 = The input slave select signal is edge-trigger. This is the default value.

1 = The slave select signal will be level-trigger. It depends on SSLVL to decide the signal is active low or active high.

Automatic Slave Select (Master only)

0 = If this bit is cleared, slave select signals are asserted and de-asserted by setting and clearing related bits in SSCTL register.

1 = If this bit is set, SPISS signals are generated automatically. It means that device/slave select signal, which is set in SSCTL register is asserted by the SPI controller when transmit/receive is started by setting EN, and is de-asserted after each transmit/receive is finished.

Slave Select Active Level

It defines the active level of device/slave select signal (SPISSx0/1).

0 = The slave select signal SPISSx0/1 is active at low-level/falling-edge.

1 = The slave select signal SPISSx0/1 is active at high-level/rising-edge.

Reserved

Slave Select Register (Master only)

If ASS bit is cleared, writing 1 to any bit location of this field sets the proper

SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.

If ASS bit is set, writing 1 to any bit location of this field will select appropriate SPISS line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. (The active level of SPISSx0/1 is specified in SSLVL).

Note: SPISS is always defined as device/slave select input signal in slave mode.

SPI Data Receive Register (RX0)


SPI1_BA + 0x10 R Data Receive Register 0 SPI1_RX0

31 30 29 28 27

RX

23 22 21 20 19

RX

15 14 13 12 11

RX

7 6 5 4 3

RX

26

18

10

2

25

17

9

1

Reset Value

0x0000_0000

24

16

8

0

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Revision 2.4


Table 5-104 SPI Data Receive Register (SPI1_RX1, address 0x4003_8010)


[31:0] RX


The Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the

SPI1_CTL register. For example, if TXBITLEN is set to 0x08 and TXNUM is set to 0x0, bit SPI1_RX0[7:0] holds the received data.

NOTE: The Data Receive Registers are read only registers.

SPI Data Receive Register (RX1)


SPI1_BA + 0x14 R Data Receive Register 1 SPI1_RX1

31 30 29 28 27

RX

23 22 21 20 19

RX

15 14 13 12 11

RX

7 6 5 4 3

RX

26

18

10

2

25

17

9

1

Reset Value

0x0000_0000

Table 5-105 SPI Data Receive Register (SPI1_RX1, address 0x4003_8014)

24

16

8

0


[31:0] RX


The Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the

SPI1_CTL register. For example, if TXBITLEN is set to 0x08 and TXNUM is set to 0x0, bit SPI1_RX0[7:0] holds the received data.

NOTE: The Data Receive Registers are read only registers.

SPI Data Transmit Register (TX0)


SPI1_BA + 0x20 W Data Transmit Register 0 SPI1_TX0

Reset Value

0x0000_0000

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Revision 2.4


31 30 29 28 27 26 25 24

TX

23 22 21 20 19 18 17 16

TX

15 14 13 12 11 10 9 8

TX

7 6 5 4 3 2 1 0

TX

Bits

[31:0]

Table 5-106 SPI Data Transmit Register (SPI1_TX0, address 0x4003_8020)

Description

TX


The Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the SPI1_CTL register. For example, if TXBITLEN is set to 0x08 and the TXNUM is set to

0x0, the bit SPI1_TX0[7:0] will be transmitted in next transfer. If TXBITLEN is set to 0x00 and TXNUM is set to 0x1, the core will perform two 32-bit transmit/receive successive using the same setting (the order is

SPI1_TX0[31:0], SPI1_TX1[31:0]).

SPI Data Transmit Register (TX1)


SPI1_BA + 0x24 W Data Transmit Register 1 SPI1_TX1

31 30 29 28 27

TX

23 22 21 20 19

TX

15 14 13 12 11

TX

7 6 5 4 3

TX

26

18

10

2

25

17

9

1

Reset Value

0x0000_0000

Table 5-107 SPI Data Transmit Register (SPI1_TX1, address 0x4003_8024)

24

16

8

0


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Revision 2.4


[31:0] TX


The Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the SPI1_CTL register. For example, if TXBITLEN is set to 0x08 and the TXNUM is set to

0x0, the bit SPI1_TX0[7:0] will be transmitted in next transfer. If TXBITLEN is set to 0x00 and TXNUM is set to 0x1, the core will perform two 32-bit transmit/receive successive using the same setting (the order is

SPI1_TX0[31:0], SPI1_TX1[31:0]).

SPI Variable Clock Pattern Flag Register (VARCLK)


SPI1_VARCLK SPI1_BA + 0x34 R/W Variable Clock Pattern Register

Reset Value

0x007F_FF87

31 30 29 26 25 24

23

15

7

22

14

6

21

13

5

28 27

20

VARCLK

19

12

VARCLK

11

4

VARCLK

3

VARCLK

18

10

2

17

9

1

16

8

0

Table 5-108 SPI Variable Clock Pattern Register (VARCLK, address 0x4003_8034)


[31:0] VARCLK

Variable Clock Pattern

The value in this field is the frequency pattern of the SPI clock. If the bit field of VARCLK is ‘0’, the output frequency of SCLK is given by the value of DIVIDER. If the bit field of VARCLK is ‘1’, the output frequency of SCLK is given by the value of CLKDIV1. Refer to register CLKDIV0.

Refer to Figure 5-62 Variable Serial Clock Frequency paragraph for

detailed description.

Note: Used for CLKP = 0 only, 16 bit transmission.

DMA Control Register (DMA)


SPI1_PDMACTL SPI1_BA + 0x38 R/W SPI PDMA Control Register

31 30 29 28 27 26 25

Reset Value

0x0000_0000

24

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Revision 2.4


Bits

[31:2]

23

15

7

[1]

[0]

22

14

6

21

13

5

Reserved

20

Reserved

19

12

Reserved

11

4

Reserved

3

18

10

2

17

9

16

8

1

RXMDAEN

0

TXMDAEN

Table 5-109 SPI DMA Control Register (DMA, address 0x4003_8038)

Description

Reserved

RXMDAEN

TXMDAEN

Reserved

Receive DMA Start

1 = Enable

0 = Disable

Set this bit to 1 will start the receive DMA process. SPI module will issue request to DMA module automatically.

Transmit DMA Start

1 = Enable

0 = Disable

Set this bit to 1 will start the transmit DMA process. SPI module will issue request to DMA module automatically.

If using DMA mode to transfer data, remember not to set EN bit of

SPI_CTL register. The DMA controller inside SPI module will set it automatically whenever necessary.

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Revision 2.4


5.11 Timer Controller

5.11.1 General Timer Controller

The ISD91200 provides two general 24bit timer modules, TIMER0 and TIMER1. They allow the user to implement event counting or provide timing control for applications. The timer can perform functions such as frequency measurement, event counting, interval measurement, clock generation and delay timing. The timer can generates an interrupt signal upon timeout and provide the current value of count during operation.

5.11.2 Features

 Independent clock source for each channel(TMR0_CLK, TMR1_CLK).

 Time out period = (Period of timer clock input) * (8-bit prescale + 1) * (24-bit CMPDAT)

 Maximum count cycle time = (1 / TMR_CLK) * (2^8) * (2^24).

 Internal 24-bit up counter is readable through TIMERx_CNT (Timer Data Register).

5.11.3 Timer Controller Block Diagram

Each channel is equipped with an 8-bit pre-scale counter, a 24-bit up-counter, a 24-bit compare register and an interrupt request signal. Refer to below figure for the timer controller block diagram. There are

five options of clock source for each channel, Figure 5-68 Clock Source of Timer Controller illustrate the

clock source control function.

TMRn_CTL.RSTCNT

Clear bit

TMRn_CTL.CNTEN

TMRx_CLK

Reset counter

8-bit Prescale

24-bit TDR latch

TMRn_CTL.CNTDATEN

Reset counter in

MODE=00/01

24-bit up-counter

+

-

=

24-bit TCMPR

D SET Q

Timer Interrupt

TMRn_INTSTS.TIF

CLR

Q

Figure 5-67 Timer Controller Block Diagram

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Revision 2.4


HCLK

TMx(GPIO)

OSC12M

OSC32K

OSC10K

1xx

011

010

001

000

SYSCLK->CLKSEL1.TMRx_S

SYSCLK->APBCLK.TMRx_EN

TMRx_CLK

Figure 5-68 Clock Source of Timer Controller




TMR Base Address:

TMRn_BA=0x4001_0000+(0x20*n) n=0,1

TMRn_CTL TMRn_BA+0x00 R/W Timer Control and Status Register

TMRn_BA+0x04 R/W Timer Compare Register TMRn_CMP

TMRn_INTSTS

TMRn_CNT

TMRn_BA+0x08 R/W

TMRn_BA+0x0C R/W

Timer Interrupt Status Register

Timer Data Register

Reset Value

0x0000_0005

0x0000_0000

0x0000_0000

0x0000_0000

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Revision 2.4



Timer Control Register (TIMERn_CTL)


TMRn_BA+0x00 R/W Timer Control and Status Register TMRn_CTL

31

Reserved

23

15

7

30

CNTEN

22

14

6

29

INTEN

21

13

5

28 27

OPMODE[1:0]

20 19

Reserved

12

Reserved

11

4 3

PSC[7:0]

26

RSTCNT

18

10

2

25

ACTSTS

17

9

1

Reset Value

0x0000_0005

24

Reserved

16

CNTDATEN

8

0

Table 5-110 Timer Control and Status Register (TIMERx_CTL, address 0x4001_0000 + x *0x20).

Bits

[31]

Description

Reserved

[30]

[29]

[28:27]

[26]

CNTEN

INTEN

OPMODE

RSTCNT

Reserved.

Counter Enable Bit

0 = Stops/Suspends counting.

1 = Starts counting.

Note1: Setting CNTEN = 1 enables 24-bit counter. It continues count from last value.

Note2: This bit is auto-cleared by hardware in one-shot mode (OPMODE = 00b) when the timer interrupt is generated (INTEN = 1b).

Interrupt Enable Bit

0 = Disable TIMER Interrupt.

1 = Enable TIMER Interrupt.

If timer interrupt is enabled, the timer asserts its interrupt signal when the count is equal to TIMERx_CMP.

Timer Operating Mode

0 = The timer is operating in the one-shot mode. The associated interrupt signal is generated once (if INTEN is enabled) and CNTEN is automatically cleared by hardware.

1 = The timer is operating in the periodic mode. The associated interrupt signal is generated periodically (if INTEN is enabled).

2 = Reserved.

3 = The timer is operating in continuous counting mode. The associated interrupt signal is generated when CNT = TIMERx_CMP (if INTEN is enabled); however, the

24-bit up-counter counts continuously without reset.

Counter Reset Bit

Set this bit will reset the timer counter, pre-scale and also force CNTEN to 0.

0 = No effect.

1 = Reset Timer’s pre-scale counter, internal 24-bit up-counter and CNTEN bit.

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Revision 2.4

[25]

[24:17]

[16]

[15:8]

[7:0]

ACTSTS

Reserved

CNTDATEN

Reserved

PSC


Timer Active Status Bit (Read Only)

This bit indicates the counter status of timer.

0 = Timer is not active.

1 = Timer is active.

Reserved.

Data Latch Enable

When CNTDATEN is set, TIMERx_CNT (Timer Data Register) will be updated continuously with the 24-bit up-counter value as the timer is counting.

1 = Timer Data Register update enable.

0 = Timer Data Register update disable.

Reserved.

Pre-scale Counter

Clock input is divided by PSC+1 before it is fed to the counter. If PSC = 0, then there is no scaling.

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Revision 2.4


Timer Compare Register (TIMERn_CMP)


TMRn_BA+0x04 R/W Timer Compare Register TMRn_CMP

31 30 29

23

15

7

22

14

6

21

13

5

28 27

Reserved

20 19

CMPDAT[23:16]

12 11

CMPDAT [15:8]

4

CMPDAT[7:0]

3

26

18

10

2

25

17

9

1

Reset Value

0x0000_0000

24

16

8

0

Table 5-111 Timer Compare Register (TIMERx_CMP, address 0x4001_0004 + x * 0x20)

Bits

[31:25]

Description

Reserved

[24:0] CMPDAT

Reserved.

Timer Comparison Value

CMPDAT is a 24-bit comparison register. When the 24-bit up-counter is enabled and its value is equal to CMPDAT value, a Timer Interrupt is requested if the timer interrupt is enabled with TIMERx_CTL.INTEN = 1. The CMPDAT value defines the timer cycle time.

Time out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT).

NOTE1: Never set CMPDAT to 0x000 or 0x001. Timer will not function correctly.

NOTE2: Regardless of CEN state, whenever a new value is written to this register,

TIMER will restart counting using this new value and abort previous count.

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Revision 2.4


Timer Interrupt Status Register (TIMERn_INTSTS)


TMRn_INTSTS TMRn_BA+0x08 R/W Timer Interrupt Status Register

31

23

15

7

30

22

14

6

29

21

13

5

28 27

Reserved

20 19

Reserved

12 11

Reserved

4

Reserved

3

26

18

10

2

25

17

9

1

Reset Value

0x0000_0000

24

16

8

0

TIF

Table 5-112 Timer Interrupt Status Register (TIMERx_INTSTS, address 0x4001_0008 + x * 0x20)

Bits

[31:1]

Description

Reserved

[0] TIF

Reserved.

Timer Interrupt Flag

This bit indicates the interrupt status of Timer.

TIF bit is set by hardware when the 24-bit counter matches the timer comparison value (CMPDAT). It is cleared by writing 1.

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Revision 2.4


Timer Data Register (TIMERn_CNT)


TMRn_BA+0x0C R/W Timer Data Register TMRn_CNT

31 30 29

23

15

7

22

14

6

21

13

5

28 27

Reserved

20

CNT[23:16]

19

12 11

CNT[15:8]

4 3

CNT[7:0]

26

18

10

2

25

17

9

1

Reset Value

0x0000_0000

Table 5-113 Timer Data Register (TIMERx_CNT, address 0x4001_000C + x *0x20).

24

16

8

0

Bits

[31:24]

Description

Reserved

[23:0] CNT

Reserved.

Timer Data Register

When TIMERx_CTL.CNTDATEN is set to 1, the internal 24-bit timer up-counter value will be latched into CNT. User can read this register for the up-counter value.

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Revision 2.4


5.12 Watchdog Timer

The purpose of Watchdog Timer is to perform a system reset if software is not responding as designed.

This prevents system from hanging for an infinite period of time. The watchdog timer includes a 18-bit free running counter with programmable time-out intervals.

Setting WDTEN enables the watchdog timer and the WDT counter starts counting up. When the counter reaches the selected time-out interval, Watchdog timer interrupt flag IF will be set immediately to request a WDT interrupt if the watchdog timer interrupt enable bit INTEN is set, in the meantime, a specified delay time follows the time-out event. User must set RSTCNT (Watchdog timer reset) high to reset the 18-bit WDT counter to prevent Watchdog timer reset before the delay time expires. RSTCNT bit is auto cleared by hardware after WDT counter is reset. There are eight time-out intervals with specific delay time which are selected by Watchdog timer interval select bits TOUTSEL. If the WDT counter has not been cleared after the specific delay time expires, the watchdog timer will set

Watchdog Timer Reset Flag (RSTF) high and reset CPU. This reset will last 64 WDT clocks then CPU restarts executing program from reset vector (0x0000 0000). RSTF will not be cleared by Watchdog reset. User may poll WTFR by software to recognize the reset source.

If the application uses any sleep modes (calling wfi or wfe instructions), the watchdog reset may not fully reset the M0 core due to parts of the core being un-clocked. In this case application should detect the RSTF in boot sequence and perform a Deep Power Down (DPD) to ensure complete reset. See the

Timer driver sample code for example.

Table 5-114 Watchdog Timeout Interval Selection

TOUTSEL Interrupt Timeout Watchdog Reset Timeout

RSTCNT Timeout Interval

(WDT_CLK=HIRC 49.152

MHz)

RSTCNT Timeout Interval

(WDT_CLK=LXT 32kHz)

000 2

4

WDT_CLK (2

4

+ 1024) WDT_CLK 21.2us 31.7 ms

001

010

011

100

2

2

8

6

2

10

2

12

WDT_CLK

WDT_CLK

WDT_CLK

WDT_CLK

(2

6

+ 1024) WDT_CLK

(2

8

+ 1024) WDT_CLK

(2

10

+ 1024) WDT_CLK

(2

12

+ 1024) WDT_CLK

22.1 us

26.0 us

41.7 us

104.2 us

33.2 ms

39 ms

64 ms

160 ms

101

110

111

2

14

WDT_CLK

2

16

WDT_CLK

2

18

WDT_CLK

(2

14

+ 1024) WDT_CLK

(2

16

+ 1024) WDT_CLK

(2

18

+ 1024) WDT_CLK

354.2 us

1.4 ms

5.4 ms

544 ms

2080 ms

8224 ms

SYSCLK->CLKSEL1.WDG_S

SYSCLK->APBCLK.WDG_EN

LIRC

HCLK/2048

LXT

HIRC

11

10

01

00

WDT_CLK

Figure 5-69 Watchdog Timer Clock Control

- 279 -


Revision 2.4


Reset WDT

Counter

WDT_CTL.RSTCNT

18-bit WDT Counter

0 ..

4 …...

15 16 17

WDT_CTL.IF

WDT_CTL.INTEN

:

:

000

001

110

111

Timeout select

WDT_CLK

WDT_CTL.WDTEN

Note:

1. Watchdog timer resets CPU and lasts 64 WDT_CLK.

WDT_CTL.TOUTSEL

Delay

1024

WDT clocks WDT_CTL.RSTEN

Watchdog

Interrupt

Watchdog

Reset [1]

WDT_CTL.RSTF

Figure 5-70 Watchdog Timer Block Diagram

- 280 -


Revision 2.4




Register Offset

WDT Base Address:

WDT_BA = 0x4000_4000

WDT_CTL

R/W Description

WDT_BA+0x00 R/W Watchdog Timer Control Register

Reset Value

0x0000_0700

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Revision 2.4



Watchdog Timer Control Register (WDT_CTL)

This is a protected register, to write to register, first issue the unlock sequence ( refer to SYS_REGLCTL ). Only flag bits, IF and RSTF are unprotected and can be write-cleared at any time.

Register

WDT_CTL

31


WDT_BA+0x00 R/W Watchdog Timer Control Register

30 29 28 27 26 25

Reset Value

0x0000_0700

24

Reserved

23 22 21 20 19 18 17 16

Reserved

15

7

WDTEN

Bits

[31:11]

14

6

INTEN

Description

Reserved

13

Reserved

5

Reserved

12

4

11

3

IF

10

2

RSTF

9

TOUTSEL

1

RSTEN

8

0

RSTCNT

[10:8]

[7]

[6]

[5:4]

[3]

TOUTSEL

WDTEN

INTEN

Reserved

IF

Reserved.

Watchdog Timer Interval Select

These three bits select the timeout interval for the Watchdog timer, a watchdog reset will occur 1024 clock cycles later if WDG not reset. The timeout is given by:

Interrupt Timeout = 2^(2xTOUTSEL+4) x WDT_CLK.

Reset Timeout = (2^(2xTOUTSEL+4) +1024) x WDT_CLK.

Where WDT_CLK is the period of the Watchdog Timer clock source.

Watchdog Timer Enable

0 = Disable the Watchdog timer (This action will reset the internal counter).

1 = Enable the Watchdog timer.

Watchdog Timer Interrupt Enable

0 = Disable the Watchdog timer interrupt.

1 = Enable the Watchdog timer interrupt.

Reserved.

Watchdog Timer Interrupt Flag

If the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. If the Watchdog timer interrupt is not enabled, then this bit indicates that a timeout period has elapsed.

0 = Watchdog timer interrupt has not occurred.

1 = Watchdog timer interrupt has occurred.

NOTE: This bit is cleared by writing 1 to this bit.

- 282 -


Revision 2.4

[2]

[1]

[0]

RSTF

RSTEN

RSTCNT


Watchdog Timer Reset Flag

When the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If RSTEN is disabled, then the Watchdog timer has no effect on this bit.

0 = Watchdog timer reset has not occurred.

1= Watchdog timer reset has occurred.

NOTE: This bit is cleared by writing 1 to this bit.

Watchdog Timer Reset Enable

Setting this bit will enable the Watchdog timer reset function.

0 = Disable Watchdog timer reset function.

1= Enable Watchdog timer reset function.

Clear Watchdog Timer

Set this bit will clear the Watchdog timer.


1 = Reset the contents of the Watchdog timer.

NOTE: This bit will auto clear after few clock cycle

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Revision 2.4


5.13 UART Interface Controller

The ISD91200 includes a Universal Asynchronous Receiver/Transmitter (UART). The UART supports high speed operation and flow control functions as well as protocols for Serial Infrared (IrDA) and Local interconnect Network (LIN).

5.13.1 Overview

The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-parallel conversion on data received from the peripheral, and a parallel-to-serial conversion on data transmitted from the CPU.

The UART controller also supports LIN(Local Interconnect Network) master mode function and IrDA

SIR (Serial Infrared)function. The UART channel supports seven types of interrupts including transmitter FIFO empty interrupt(THERINT), receiver threshold level interrupt (RDAINT), line status interrupt (overrun error or parity error or framing error or break interrupt) (RLSINT), time out interrupt

(RXTOINT), MODEM status interrupt (MODEMINT), Buffer error interrupt (BUFERRINT) and LIN receiver break field detected interrupt.

The UART has a 8-byte transmit FIFO (TX_FIFO) and a 8-byte receive FIFO (RX_FIFO) that reduces the number of interrupts presented to the CPU. The CPU can read the status of the UART at any time during the operation. The reported status information includes the type and condition of the transfer operations being performed by the UART, as well as 4 error conditions (parity error, overrun error, framing error and break interrupt) that can occur while receiving data. The UART includes a programmable baud rate generator that is capable of dividing master clock input by divisors to produce the baud rate clock. The baud rate equation is Baud Rate = UART_CLK / M * [BRD + 2], where M and

BRD are defined in Baud Rate Divider Register (UART_BAUD). Table 5-115 UART Baud Rate

Equation lists the equations under various conditions.

The UART controller supports auto-flow control function that uses two active-low signals,/CTS (clear-tosend) and /RTS (request-to-send), to control the flow of data transfer between the UART and external devices (e.g. Modem). When auto-flow is enabled, the UART will not receive data until the UART asserts /RTS to external device. When the number of bytes in the Rx FIFO equals the value of

UART_FIFO.RTSTRGLV, the /RTS is de-asserted. The UART sends data out when UART controller detects /CTS is asserted from external device. If /CTS is not detected the UART controller will not send data out.

The UART controller also provides Serial IrDA (SIR, Serial Infrared) function

(UART_FUNCSEL.IRDAEN =1 to enable IrDA function). The SIR specification defines a short-range infrared asynchronous serial transmission mode with one start bit, 8 data bits, and 1 stop bit. The maximum data rate is 115.2 Kbps (half duplex). The IrDA SIR block contains an IrDA SIR Protocol encoder/decoder. The IrDA SIR protocol is half-duplex only. So it cannot transmit and receive data at the same time. The IrDA SIR physical layer specifies a minimum 10ms transfer delay between transmission and reception. This delay must be implemented by software.

The alternate function of UART controller is LIN (Local Interconnect Network) function. The LIN mode is selected by setting the UART_FUNCSEL.LINEN bit. In LIN mode, one start bit, 8-bit data format with 1bit stop bit are generated in accordance with the LIN standard.

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Revision 2.4


Mode

0

1

2

BAUDM1

0

1

1

Baud rate

921600

460800

230400

115200

57600

38400

19200

9600

4800

BAUDM0

0

0

1

Table 5-115 UART Baud Rate Equation

EDIVM1[3:0] BRD[15:0] Baud Rate Equation

B A

B

Don’t care

A

A

UART_CLK / [16 * (A+2)]

UART_CLK / [(B+1) * (A+2)] , B

≥ 8

UART_CLK / (A+2), A

≥ 3

Mode0 x

Table 5-116 UART Baud Rate Setting Table

%err

System Clock = 49.152MHz

Mode1

A=4,B=8

%err

1.2 x A=10,B=8 x

A=25

A=51

A=78

A=158

A=318

A=638

1.2

-0.6

0.0

0.0

0.0

0.0

A=22,B=8

A=7,B=11

A=37,B=10

A=31,B=12

A=59,B=13

A=93,B=8

A=126,B=9

A=78,B=15

A=254,B=9

A=158,B=15

A=510,B=9

A=318,B=15

A=1022,B=9

A=638,B=15

1.2

0.0

0.0

0.0

0.0

0.1

0.2

0.0

0.0

1.2

1.2

0.5

0.5

0.0

0.0

Mode2

A=51

A=104

A=211

A=425

A=851

A=1278

A=2558

A=5118

A=10238

0.0

0.0

0.0

0.0

%err

-0.6

0.3

-0.2

0.1

0.0

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Revision 2.4


5.13.2 Features of UART controller

•

UART supports 8 byte FIFO for receive and transmit data payloads.

•

PDMA access support.

•

Auto flow control function (/CTS, /RTS) supported.

•

Programmable baud-rate generator.

•

Fully programmable serial-interface characteristics: o 5-, 6-, 7-, or 8-bit character. o Even, odd, or no-parity bit generation and detection. o 1-, 1&1/2, or 2-stop bit generation. o Baud rate generation. o False start bit detection.

•

IrDA SIR Function.

•

LIN master mode.

- 286 -


Revision 2.4


5.13.3 Block Diagram

The UART clock control and block diagram are shown as following.

CLK_APBCLK0->UARTx_EN

HCLK

UARTx_CLK

1/(UARTDIV+1)

CLK_CLKDIV0->UARTDIV

Figure 5-71 UART Clock Control Diagram

APB BUS

8

8

Status & control

TX_FIFO

Control and

Status registers

Status & control

8

RX_FIFO

TX shift register

Baud out

Baud Rate

Generator

Baud out

RX shift register

Serial Data Out UART0_CLK

Figure 5-72 UART Block Diagram

Serial Data In

- 287 -


Revision 2.4


TX_FIFO

The transmitter is buffered with an 8 byte FIFO to reduce the number of interrupts presented to the

CPU.

RX_FIFO

The receiver is buffered with an 8 byte FIFO (plus three error bits per byte) to reduce the number of interrupts presented to the CPU.

TX shift Register

Shifts the transmit data out serially

RX shift Register

Shifts the receive data in serially

Modem Control Register

This register controls the interface to the MODEM or data set (or a peripheral device emulating a

MODEM).

Baud Rate Generator

Divides the UART_CLK clock by the divisor to get the desired baud rate clock. Refer to Table 5-116

UART Baud Rate Setting Table for the baud rate equation.

Control and Status Register

This is a register set, including the FIFO control registers (UART_FIFO), FIFO status registers

(UART_FIFOSTS), and line control register (UART_LINE) for transmitter and receiver. The time out control register (UART_TOUT) identifies the condition of time out interrupt. This register set also includes the interrupt enable register (UART_INTEN) and interrupt status register (UART_INTSTS) to enable or disable the responding interrupt and to identify the occurrence of the responding interrupt.

There are six types of interrupts, transmitter FIFO empty interrupt(THERINT), receiver threshold level reaching interrupt (RDAINT), line status interrupt (overrun error or parity error or framing error or break interrupt) (RLSINT) , time out interrupt (RXTOINT), MODEM status interrupt (MODEMINT) and Buffer error interrupt (BUFERRINT).

Figure 5-73 Auto Flow Control Block Diagram demonstrates the auto-flow control block diagram.

Parallel to Serial

TX

Tx FIFO

APB

BUS

Flow Control

/CTS

Serial to Parallel

RX

Rx FIFO

Flow Control

/RTS

Figure 5-73 Auto Flow Control Block Diagram

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Revision 2.4


5.13.4 IrDA Mode

The UART supports IrDA SIR (Serial Infrared) Transmit Encoder and Receive Decoder. IrDA mode is selected by setting the UART_FUNCSEL.IRDAENbit.

When in IrDA mode, the UART_BAUD.BAUDM1 register must be zero and baud rate is given by:

Baud Rate = UART_CLK / (16 * BRD), where BRD is Baud Rate Divider in the UART_BAUD.BRD register.

TX

SOUT

UART

RX

SIN

IR_SOUT

IrDA

SIR

IR_SIN

TX pin Emit Infrared ray

RX pin

IR

Transceiver

Detect Infrared ray

IRCR

BAUD

IrDA_EN

TX_SELECT

INV_TX

INV_RX

Figure 5-74 IrDA Block Diagram

5.13.4.1 IrDA SIR Transmit Encoder

The IrDA SIR Transmit Encoder modulates Non-Return-to Zero (NRZ) transmission bit stream from

UART serial output. The IrDA SIR physical layer specifies use of Return-to-Zero, Inverted (RZI) modulation scheme which represents logic 0 as an infrared light pulse. The modulated output pulse stream is transmitted to an external output driver and infrared LED (Light Emitting Diode).In normal mode, the transmitted pulse width is specified as 3/16the period of the baud rate.

5.13.4.2 IrDA SIR Receive Decoder

The IrDA SIR Receive Decoder demodulates the return-to-zero bit stream from the input detector and outputs the NRZ serial bit stream to the UART received data input. The IR_SIN decoder input is normally high in the idle state. Because of this, UART_IRDA.RXINV should be set 1 by default). A start bit is detected when the IR_SIN decoder input is LOW.

5.13.4.3 IrDA SIR Operation

The IrDA SIR Encoder/decoder provides functionality which converts between UART data stream and half duplex serial SIR interface. Below figure shows the IrDA encoder/decoder waveform:

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Revision 2.4


START BIT STOP BIT

SOUT

(from uart TX)

Tx

Timing

IR_SOUT

(encoder output)

1 0 0 1 0 1

Rx

Timing

IR_SIN

(decorder input)

SIN

(To uart RX)

START BIT

1 0

3/16 bit width

1 0

3/16 bit width

0 1

1 1

0 1

0 0

0 0

1

1

STOP BIT

Bit pulse width

Figure 5-75 IrDA Tx/Rx Timing Diagram

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Revision 2.4


5.13.5 LIN (Local Interconnection Network) mode

The UART supports a Local Interconnection Network (LIN) function. LIN mode is selected by setting the

UART_FUNCSEL.LINEN bit. In LIN mode, each byte field is initiated by a start bit with value zero

(dominant), followed by 8 data bits (LSB is first)and ended by 1 stop bit with value one (recessive) in accordance with the LIN standard ( http://www.lin-subbus.org/ ).

Header

Frame slot

Frame

Response space

Response

Interframe space

Break

Field

Synch field

Protected

Identifier field

Data 1 Data 2 Data N Check

Sum

Figure 5-76 Structure of LIN Frame

The program flow of LIN Bus Transmit transfer (Tx) is shown as following

1. Set the UART_FUNCSEL.LINEN bit to enable LIN Bus mode.

2. Set UART_ALTCTL.BRKFL to choose break field length. The break field length is BRKFL+2.

3. Fill 0x55 to UART_DAT to request synch field transmission.

4. Request Identifier Field transmission by writing the protected identifier value to UART_DAT

5. Set the UART_ALTCTL.LINTXEN bit to start transmission (When break filed operation is finished,

LINTX_EN will be cleared automatically).

6. When the STOP bit of the last byte UART_DAT has been sent to bus, hardware will set flag

UART_FIFOSTS.TXEMPTYF to 1.

7. Fill N bytes data and Checksum to UART_DAT then repeat step 5 and 6 to transmit the data.

The program flow of LIN Bus Receiver transfer (Rx) is show as following

1. Set the UART_FUNCSEL.LINEN bit to enable LIN Bus mode.

2. Set the UART_ALTCTL.LINRXEN bit register to enable LIN Rx mode.

3. Wait for the flag UART_INTSTS.LINIF to indicate Rx received Break field or not.

4. Wait for the flag UART_INTSTS.RDAIF read back the UART_DAT register.

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Revision 2.4





UART Base Address:

UARTn_BA = 0x4005_0000 + (n*0x8000) n=0,1

UARTn_DAT UARTn_BA+0x00

UARTn_INTEN UARTn_BA+0x04

R/W UART Receive/Transfer FIFO Register.

R/W UART Interrupt Enable Register.

UARTn_FIFO

UARTn_LINE

UARTn_BA+0x08

UARTn_BA+0x0C

UARTn_MODEM UARTn_BA+0x10

UARTn_MODEMSTS UARTn_BA+0x14

UARTn_FIFOSTS UARTn_BA+0x18

UARTn_INTSTS

UARTn_TOUT

UARTn_BA+0x1C

UARTn_BA+0x20

UARTn_BAUD

UARTn_IRDA

UARTn_ALTCTL

UARTn_BA+0x24

UARTn_BA+0x28

UARTn_BA+0x2C

UARTn_FUNCSEL UARTn_BA+0x30

R/W UART FIFO Control Register.

R/W UART Line Control Register.

R/W UART Modem Control Register.

R/W UART Modem Status Register.

R/W UART FIFO Status Register.

R/W UART Interrupt Status Register.

R/W UART Time Out Register

R/W UART Baud Rate Divisor Register

R/W UART IrDA Control Register.

R/W UART LIN Control Register.

R/W UART Function Select Register.

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0010

0x1040_4000

0x0000_0002

0x0000_0000

0x0F00_0000

0x0000_0040

0x0000_0000

0x0000_0000

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Revision 2.4



Receive FIFO Data Register (UARTn_DAT)


UARTn_DAT

31

UARTn_BA+0x00 R/W UART Receive/Transfer FIFO Register.

30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5 4 3 2

DAT

Bits

[31:8]

[7:0]

25

17

9

1

Reset Value

0x0000_0000

24

16

8

0

Table 5-117 UART Receive FIFO Data Register (UARTn_DAT, address 0x4005_0000)

Description

Reserved

DAT

Receive FIFO Register

Reading this register will return data from the receive data FIFO. By reading this register, the UART will return the 8-bit data received from Rx pin (LSB first).

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Revision 2.4


Interrupt Enable Register (UARTn_INTEN)


UARTn_INTEN UARTn_BA+0x04 R/W UART Interrupt Enable Register.

31

23

30

22

15 14

DMARXEN DMATXEN

7 6

Reserved

29

21

13

ATOCTSEN

5

BUFERRIEN

28 27 26 25

Reserved

20 19 18 17

Reserved

12

ATORTSEN

11

TOCNTEN

10

Reserved

9

4 3 2 1

RXTOIEN MODEMIEN RLSIEN THREIEN

Reset Value

0x0000_0000

24

16

8

LINIEN

0

RDAIEN

Table 5-118 UART Interrupt Enable Register (UARTn_INTEN, address 0x4005_0004)

Bits

[31:16]

Description

Reserved

[15]

[14]

[13]

[12]

[11]

[10:9]

[8]

[7:6]

DMARXEN

DMATXEN

ATOCTSEN

ATORTSEN

TOCNTEN

Reserved

LINIEN

Reserved

Reserved.

Receive DMA Enable

If enabled, the UART will request DMA service when data is available in receive

FIFO.

Transmit DMA Enable

If enabled, the UART will request DMA service when space is available in transmit

FIFO.

CTS Auto Flow Control Enable

0 = Disable CTS auto flow control.

1 = Enable.

When CTS auto-flow is enabled, the UART will send data to external device when

CTS input is asserted (UART will not send data to device until CTS is asserted).

RTS Auto Flow Control Enable

0 = Disable RTS auto flow control.

1 = Enable.

When RTS auto-flow is enabled, if the number of bytes in the Rx FIFO equals

UART_FIFO.RTSTRGLV, the UART will de-assert the RTS signal.

Time-out Counter Enable

0 = Disable Time-out counter.

1 = Enable.

Reserved.

LIN RX Break Field Detected Interrupt Enable

0 = Mask off Lin bus Rx break field interrupt.

1 = Enable Lin bus Rx break field interrupt.

Reserved.

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Revision 2.4

[3]

[2]

[5]

[4]

[1]

[0]


BUFERRIEN

RXTOIEN

MODEMIEN

RLSIEN

THREIEN

RDAIEN

Buffer Error Interrupt Enable

0 = Mask off BUFERRINT.

1 = Enable IBUFERRINT.

Receive Time Out Interrupt Enable

0 = Mask off RXTOINT.

1 = Enable RXTOINT.

Modem Status Interrupt Enable

0 = Mask off MODEMINT.

1 = Enable MODEMINT.

Receive Line Status Interrupt Enable

0 = Mask off RLSINT.

1 = Enable RLSINT.

Transmit FIFO Register Empty Interrupt Enable

0 = Mask off THERINT.

1 = Enable THERINT.

Receive Data Available Interrupt Enable

0 = Mask off RDAINT.

1 = Enable RDAINT.

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Revision 2.4


FIFO Control Register (UARTn_FIFO)


UARTn_BA+0x08 R/W UART FIFO Control Register. UARTn_FIFO

31 30 29 28 27

Reserved

23 22 21 20 19

Reserved

15

7

14

6

RFITL

13

5

12 11

4

Reserved

3

Reserved

26

2

TXRST

25

18

RTSTRGLV

17

10 9

1

RXRST

Reset Value

0x0000_0000

24

16

8

0

Reserved

Table 5-119 UART FIFO Control Register (UARTn_FIFO, address 0x4005_0008)

Bits

[31:20]

Description

Reserved

[19:16]

[15:8]

[7:4]

[3]

[2]

RTSTRGLV

Reserved

RFITL

Reserved

TXRST

Reserved.

RTS Trigger Level for Auto-flow Control

Sets the FIFO trigger level when auto-flow control will de-assert RTS (request-to-send).

Value : Trigger Level (Bytes)

0 : 1

1 : 4

2 : 8

Reserved.

Receive FIFO Interrupt (RDAINT) Trigger Level

When the number of bytes in the receive FIFO equals the RFITL then the RDAIF will be set and, if enabled, an RDAINT interrupt will generated.

Value : INTR_RDA Trigger Level (Bytes)

0 : 1

1 : 4

Reserved.

Transmit FIFO Reset

When TXRST is set, all the bytes in the transmit FIFO are cleared and transmit internal state machine is reset.


1 = Writing 1 to this bit will reset the transmit internal state machine and pointers.

Note: This bit will auto-clear after 3 UART engine clock cycles.

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Revision 2.4

[1] RXRST

[0] Reserved


Receive FIFO Reset

When RXRST is set, all the bytes in the receive FIFO are cleared and receive internal state machine is reset.


1 = Writing 1 to this bit will reset the receiving internal state machine and pointers.

Note: This bit will auto-clear after 3 UART engine clock cycles.

Reserved.

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Revision 2.4


Line Control Register (UARTn_LINE)


UARTn_BA+0x0C R/W UART Line Control Register. UARTn_LINE

7

Reserved

6

BCB

5

SPE

4

EPE

3

PBE

2

NSB

1

Reset Value

0x0000_0000

WLS

Table 5-120 UART Line Control Register (UARTn_LINE, address 0x4005_000C)

0

Bits

[31:7]

Description

Reserved

[6]

[5]

[4]

[3]

[2]

[1:0]

BCB

SPE

EPE

PBE

NSB

WLS

Reserved.

Break Control Bit

When this bit is set to logic 1, the serial data output (Tx) is forced to the ‘Space’ state (logic 0).

Normal condition is serial data output is ‘Mark’ state. This bit acts only on Tx and has no effect on the transmitter logic.

Stick Parity Enable

0 = Disable stick parity.

1 = When bits PBE and SPE are set ‘Stick Parity’ is enabled. If EPE=0 the parity bit is transmitted and checked as always set, if EPE=1, the parity bit is transmitted and checked as always cleared.

Even Parity Enable

0 = Odd number of logic 1’s are transmitted or checked in the data word and parity bits.

1 = Even number of logic 1’s are transmitted or checked in the data word and parity bits.

This bit has effect only when PBE (parity bit enable) is set.

Parity Bit Enable

0 = Parity bit is not generated (transmit data) or checked (receive data) during transfer.

1 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data.

Number of STOP Bits

0= One “STOP bit” is generated after the transmitted data.

1= Two “STOP bits” are generated when 6-, 7- and 8-bit word length is selected; One and a half

“STOP bits” are generated in the transmitted data when 5-bit word length is selected;.

Word Length Select

0 (5bits), 1(6bits), 2(7bits), 3(8bits)

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Revision 2.4


MODEM Control Register (UARTn_MODEM)


UARTn_MODEM UARTn_BA+0x10 R/W UART Modem Control Register.

31

23

30

22

15 14

7

Reserved

6

Reserved

29

21

13

RTSSTS

5

28 27 26

Reserved

20 19 18

12

4

LBMEN

Reserved

11

Reserved

3

Reserved

10

2

25

17

9

RTSACTLV

1

RTS

Reset Value

0x0000_0000

24

16

8

Reserved

0

Reserved

Table 5-121 UART Modem Control Register (UARTn_MODEM, address 0x4005_0010)

Bits

[31:14]

Description

Reserved

[13]

[12:10]

[9]

[8:5]

[4]

[3:2]

[1]

[0]

RTSSTS

Reserved

RTSACTLV

Reserved

LBMEN

Reserved

RTS

Reserved

Reserved.

RTS Pin State (Read Only)

This bit is the pin status of RTS.

Reserved.

Request-to-send (RTS) Active Trigger Level

This bit can change the RTS trigger level.

0= RTS is active low level.

1= RTS is active high level.

Reserved.

Loopback Mode Enable

0=Disable.

1=Enable.

Reserved.

RTS (Request-to-send) Signal

If UART_INTEN.ATORTSEN = 0, this bit controls whether RTS pin is active or not.

0 = Drive RTS inactive ( = ~RTSACTLV).

1 = Drive RTS active ( = RTSACTLV).

Reserved.

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Revision 2.4


Modem Status Register (UARTn_MODEMSTS)


UARTn_MODEMSTS UARTn_BA+0x14 R/W UART Modem Status Register.

31

23

15

7

30

22

14

6

Reserved

29

21

13

5

28 27

Reserved

20

4

CTSSTS

19

Reserved

12

Reserved

11

3

26

18

10

2

Reserved

25

17

9

1

Reset Value

0x0000_0010

24

16

8

CTSACTLV

0

CTSDETF

Table 5-122 UART Modem Status Register (UARTn_MODEMSTS, address 0x4005_0014)

Bits

[31:9]

Description

Reserved

[8]

[7:5]

[4]

[3:1]

[0]

CTSACTLV

Reserved

CTSSTS

Reserved

CTSDETF

Reserved.

Clear-to-send (CTS) Active Trigger Level

This bit can change the CTS trigger level.

0= CTS is active low level.

1= CTS is active high level.

Reserved.

CTS Pin Status (Read Only)

This bit is the pin status of CTS.

Reserved.

Detect CTS State Change Flag

This bit is set whenever CTS input has state change. It will generate Modem interrupt to CPU when UART_INTEN.MODEMIEN = 1.

NOTE: This bit is cleared by writing 1 to itself.

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Revision 2.4


FIFO Status Register (UARTn_FIFOSTS)


UARTn_FIFOSTS UARTn_BA+0x18 R/W UART FIFO Status Register.

31

23

TXFULL

15

RXFULL

7

Reserved

30

Reserved

22

TXEMPTY

14

RXEMPTY

6

BIF

29

21

13

5

FEF

28

TXEMPTYF

20

12

4

PEF

27

19

26

Reserved

18

TXPTR

11 10

3

RXPTR

2

Reserved

25

17

9

1

Reset Value

0x1040_4000

24

TXOVIF

16

0

RXOVIF

Table 5-123 UART FIFO Status Register (UARTn_FIFOSTS, address 0x4005_0018)

8

Bits

[31:29]

Description

Reserved

[28]

[27:25]

[24]

[23]

[22]

[21:16]

TXEMPTYF

Reserved

TXOVIF

TXFULL

TXEMPTY

TXPTR

Reserved.

Transmitter Empty (Read Only)

Bit is set by hardware when Tx FIFO is empty and the STOP bit of the last byte has been transmitted.

Bit is cleared automatically when Tx FIFO is not empty or the last byte transmission has not completed.

NOTE: This bit is read only.

Reserved.

Tx Overflow Error Interrupt Flag

If the Tx FIFO (UART_DAT) is full, an additional write to UART_DAT will cause an overflow condition and set this bit to logic 1. It will also generate a BUFERRIF event and interrupt if enabled.


Transmit FIFO Full (Read Only)

This bit indicates whether the Tx FIFO is full or not.

This bit is set when Tx FIFO is full; otherwise it is cleared by hardware. TXFULL=0 indicates there is room to write more data to Tx FIFO.

Transmit FIFO Empty (Read Only)

This bit indicates whether the Tx FIFO is empty or not.

When the last byte of Tx FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared after writing data to FIFO (Tx FIFO not empty).

Tx FIFO Pointer (Read Only)

This field returns the Tx FIFO buffer pointer. When CPU writes a byte into the Tx

FIFO, TXPTR is incremented. When a byte from Tx FIFO is transferred to the

Transmit Shift Register, TXPTR is decremented.

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Revision 2.4

[15]

[14]

[5]

[4]

[3:1]

[0]

[13:8]

[7]

[6]

RXFULL

RXEMPTY

RXPTR

Reserved

BIF

FEF

PEF

Reserved

RXOVIF


Receive FIFO Full (Read Only)

This bit indicates whether the Rx FIFO is full or not.

This bit is set when Rx FIFO is full; otherwise it is cleared by hardware.

Receive FIFO Empty (Read Only)

This bit indicates whether the Rx FIFO is empty or not.

When the last byte of Rx FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.

Rx FIFO Pointer (Read Only)

This field returns the Rx FIFO buffer pointer. It is the number of bytes available for read in the Rx FIFO. When UART receives one byte from external device, RXPTR is incremented. When one byte of Rx FIFO is read by CPU, RXPTR is decremented.

Reserved.

Break Interrupt Flag

This bit is set to a logic 1 whenever the receive data input (Rx) is held in the "space” state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). It is reset whenever the CPU writes 1 to this bit.

Framing Error Flag

This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic

0), and is reset whenever the CPU writes 1 to this bit.

Parity Error Flag

This bit is set to logic 1 whenever the received character does not have a valid

"parity bit", and is reset whenever the CPU writes 1 to this bit.

Reserved.

Rx Overflow Error Interrupt Flag

If the Rx FIFO (UART_DAT) is full, and an additional byte is received by the UART, an overflow condition will occur and set this bit to logic 1. It will also generate a

BUFERRIF event and interrupt if enabled.


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Revision 2.4


Interrupt Status Register (UARTn_INTSTS)


UARTn_INTSTS UARTn_BA+0x1C R/W UART Interrupt Status Register.

31

DLININT

23

DLINIF

15

LININT

7

LINIF

30

Reserved

22

Reserved DBERRIF DRXTOIF

14 13 12

Reserved BUFERRINT RXTOINT

6

Reserved

29 28 27

DBERRINT DRXTOINT DMODEMI

21 20 19

5

BUFERRIF

4

RXTOIF

DMODEMIF

11

MODEMINT

3

MODENIF

26

DRLSINT

18

DRLSIF

10

RLSINT

2

RLSIF

Reset Value

0x0000_0002

25 24

Reserved

17 16

Reserved

9

THERINT

8

RDAINT

1

THREIF

0

RDAIF

Table 5-124 UART Interrupt Status Register (UARTn_INTSTS, address 0x4005_001C)


[31]

[30]

[29]

[28]

[27]

[26]

[25]

[24]

[23]

[22]

DLININT

Reserved

DBERRINT

DRXTOINT

DMODEMI

DRLSINT

Reserved

Reserved

DLINIF

Reserved

DMA MODE LIN Bus Rx Break Field Detected Interrupt Indicator to Interrupt

Controller

Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DLINIF.

Reserved.

DMA MODE Buffer Error Interrupt Indicator to Interrupt Controller

Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and

DBERRIF.

DMA MODE Time Out Interrupt Indicator to Interrupt Controller


DRXTOIF.

DMA MODE MODEM Status Interrupt Indicator to Interrupt


DMODENIF.

DMA MODE Receive Line Status Interrupt Indicator to Interrupt Controller

Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DRLSIF.

Reserved.

Reserved.

DMA MODE LIN Bus Rx Break Field Detected Flag

This bit is set when LIN controller detects a break field. This bit is cleared by writing a 1.

Reserved.

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Revision 2.4


[21]

[20]

[19]

[18]

[12]

[11]

[10]

[9]

[8]

[17:16]

[15]

[14]

[13]

[7]

[6]

DBERRIF

DRXTOIF

DMODEMIF

DRLSIF

Reserved

LININT

Reserved

BUFERRINT

RXTOINT

MODEMINT

RLSINT

THERINT

RDAINT

LINIF

Reserved

DMA MODE Buffer Error Interrupt Flag (Read Only)

This bit is set when either the Tx or Rx FIFO overflows (UART_FIFOSTS.TXOVIF or

UART_FIFOSTS.RXOVIF is set). When BUFERRIF is set, the serial transfer may be corrupted. If UART_INTEN.BUFERRIEN is enabled a CPU interrupt request will be generated.

NOTE: This bit is cleared when both UART_FIFOSTS.TXOVIF and

UART_FIFOSTS.RXOVIF are cleared.

DMA MODE Time Out Interrupt Flag (Read Only)

This bit is set when the Rx FIFO is not empty and no activity occurs in the Rx FIFO and the time out counter equal to TOIC. If UART_INTEN.TOUT_IEN is enabled a

CPU interrupt request will be generated.

NOTE: This bit is read only and user can read FIFO to clear it.

DMA MODE MODEM Interrupt Flag (Read Only)

This bit is set when the CTS pin has changed state

(UART_MODEMSTS.CTSDETF=1). If UART_INTEN.MODEMIEN is enabled, a CPU interrupt request will be generated.

NOTE: This bit is read only and reset when bit UART_MODEMSTS.CTSDETF is cleared by a write 1.

DMA MODE Receive Line Status Interrupt Flag (Read Only)

This bit is set when the Rx receive data has a parity, framing or break error (at least one of, UART_FIFOSTS.BIF, UART_FIFOSTS.FEF and UART_FIFOSTS.PEF, is set). If UART_INTEN.RLSIEN is enabled, the RLS interrupt will be generated.

NOTE: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.

Reserved.

LIN Bus Rx Break Field Detected Interrupt Indicator to Interrupt Controller

Logical AND of UART_INTEN.LINIEN and LINIF.

Reserved.

Buffer Error Interrupt Indicator to Interrupt Controller

Logical AND of UART_INTEN.BUFERRIEN and BUFERRIF.

Time Out Interrupt Indicator to Interrupt Controller

Logical AND of UART_INTEN.RXTOIEN and RXTOIF.

MODEM Status Interrupt Indicator to Interrupt

Logical AND of UART_INTEN.MODEMIEN and MODENIF.

Receive Line Status Interrupt Indicator to Interrupt Controller

Logical AND of UART_INTEN.RLSIEN and RLSIF.

Transmit Holding Register Empty Interrupt Indicator to Interrupt Controller

Logical AND of UART_INTEN.THREIEN and THREIF.

Receive Data Available Interrupt Indicator to Interrupt Controller

Logical AND of UART_INTEN.RDAIEN and RDAIF.

LIN Bus Rx Break Field Detected Flag

This bit is set when LIN controller detects a break field. This bit is cleared by writing a 1.

Reserved.

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Revision 2.4

[0]

[5]

[4]

[3]

[2]

[1]

BUFERRIF

RXTOIF

MODENIF

RLSIF

THREIF

RDAIF


Buffer Error Interrupt Flag (Read Only)

This bit is set when either the Tx or Rx FIFO overflows (UART_FIFOSTS.TXOVIF or

UART_FIFOSTS.RXOVIF is set). When BUFERRIF is set, the serial transfer may be corrupted. If UART_INTEN.BUFERRIEN is enabled a CPU interrupt request will be generated.

NOTE: This bit is cleared when both UART_FIFOSTS.TXOVIF and

UART_FIFOSTS.RXOVIF are cleared.

Time Out Interrupt Flag (Read Only)

This bit is set when the Rx FIFO is not empty and no activity occurs in the Rx FIFO and the time out counter equal to TOIC. If UART_INTEN.TOUT_IEN is enabled a

CPU interrupt request will be generated.

NOTE: This bit is read only and user can read FIFO to clear it.

MODEM Interrupt Flag (Read Only)

This bit is set when the CTS pin has changed state

(UART_MODEMSTS.CTSDETF=1). If UART_INTEN.MODEMIEN is enabled, a CPU interrupt request will be generated.

NOTE: This bit is read only and reset when bit UART_MODEMSTS.CTSDETF is cleared by a write 1.

Receive Line Status Interrupt Flag (Read Only)

This bit is set when the Rx receive data has a parity, framing or break error (at least one of, UART_FIFOSTS.BIF, UART_FIFOSTS.FEF and UART_FIFOSTS.PEF, is set). If UART_INTEN.RLSIEN is enabled, the RLS interrupt will be generated.

NOTE: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.

Transmit Holding Register Empty Interrupt Flag (Read Only)

This bit is set when the last data of Tx FIFO is transferred to Transmitter Shift

Register. If UART_INTEN.THREIEN is enabled, the THRE interrupt will be generated.

NOTE: This bit is read only and it will be cleared when writing data into the Tx FIFO.

Receive Data Available Interrupt Flag (Read Only)

When the number of bytes in the Rx FIFO equals UART_FIFO.RFITL then the

RDAIF will be set. If UART_INTEN.RDAIEN is enabled, the RDA interrupt will be generated.

NOTE: This bit is read only and it will be cleared when the number of unread bytes of Rx FIFO drops below the threshold level (RFITL).

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Revision 2.4


When the DMA controller is used to transmit or receive data to the UART, an alternate set of flags and interrupt indicators are generated. These are equivalent to the normal mode set above and are summarized in below tables.

Table 5-125 UART Interrupt Sources and Flags Table In DMA Mode

Flag Cleared By UART Interrupt

Source

Interrupt Enable Bit Interrupt Indicator To

Interrupt Controller

DLININT LIN RX Break Field

Detected interrupt

LINIEN

BUFERRIEN Buffer Error

Interrupt

BUFERRINT

Rx Timeout

Interrupt

RXTOINT

RXTOIEN

DBERRINT

DRXTOINT

DMODEMI Modem Status

Interrupt

MODEMINT

MODEMIEN

Receive Line Status

Interrupt

RLSIEN

RLSINT

DRLSINT

Interrupt Flag

DLINIF

DBERRIF =

(TXOVIF or RXOVIF)

DRXTOIF

DMODEMIF =

(CTSDETF)

DRLSIF =

(BIF or FEF or PEF)

Write ‘1’ to LINIF

Write ‘1’ to TXOVIF/

RXOVIF

Read data FIFO

Write ‘1’ to CTSDETF

Write ‘1’ to

BIF/FEF/PEF

Table 5-126 UART Interrupt Sources and Flags Table In Software Mode

UART Interrupt Source

LIN RX Break Field Detected interrupt

Interrupt Enable Bit Interrupt Indicator To

Interrupt Controller

Interrupt Flag

LINIEN LININT LINIF

BUFERRINT

Flag Cleared By

Write ‘1’ to LINIF

BUFERRIF =

(TXOVIF or RXOVIF)

Write ‘1’ to TXOVIF/

RXOVIF

Buffer Error Interrupt

BUF_ERR_INT

Rx Timeout Interrupt

RXTOINT

BUFERRIEN

RXTOIEN

Modem Status Interrupt

MODEMINT

Receive Line Status Interrupt

RLSINT

MODEMIEN

RLSIEN

RXTOINT

MODEMINT

RLSINT

RXTOIF

MODENIF =

(CTSDETF)

Read data FIFO

Write ‘1’ to CTSDETF

RLSIF =

(BIF or FEF or PEF)

Write ‘1’ to

BIF/FEF/PEF

THREIEN THERINT THREIF Write data FIFO Transmit Holding Register

Empty Interrupt

THERINT

Receive Data Available

Interrupt

RDAINT

RDAIEN RDAINT RDAIF Read data FIFO

- 306 -


Revision 2.4


Time Out Register (UARTn_TOUT)


UARTn_TOUT UARTn_BA+0x20 R/W UART Time Out Register

31

23

15

7

Reserved

30

22

14

6

29

21

13

5

28 27

Reserved

20 19

Reserved

12 11

4

Reserved

3

TOIC

26

18

10

2

25

17

9

1

Reset Value

0x0000_0000

Table 5-127 UART Time Out Register (UARTn_TOUT, address 0x4005_0020)

24

16

8

0

Bits

[31:7]

Description

Reserved

[6:0] TOIC

Reserved.

Time Out Interrupt Comparator

The time out counter resets and starts counting whenever the Rx FIFO receives a new data word. Once the content of time out counter is equal to that of time out interrupt comparator (TOIC), a receiver time out interrupt (RXTOINT) is generated if

UART_INTEN.RXTOIEN is set. A new incoming data word or RX FIFO empty clears

RXTOIF. The period of the time out counter is the baud rate.

- 307 -


Revision 2.4


Baud Rate Divider Register (UARTn_BAUD)


UARTn_BAUD UARTn_BA+0x24 R/W UART Baud Rate Divisor Register

Reset Value

0x0F00_0000

The baud rate generator takes the UART master clock UART_CLK and divides it to produce the baud rate (bit rate) clock. The divider has two division stages controlled by BRD and EDIVM1 fields. These are configured in three modes depending on the selections of BAUDM1 and BAUDM0. These modes

and the baud rate equations for them are described in Table 5-115 UART Baud Rate Equation.

31 30 26 25 24

23

15

7

Reserved

22

14

6

29

BAUDM1

21

13

5

28

BAUDM0

20

Reserved

27

19

12 11

BRD[15:0]

4 3

BRD[7:0]

18

10

2

EDIVM1

17

9

1

16

8

0

Table 5-128 UART Baud Rate Divider Register (UARTn_BAUD, address 0x4005_0024)

Bits

[31:30]

Description

Reserved

[29]

[28]

[27:24]

[23:16]

[15:0]

BAUDM1

BAUDM0

EDIVM1

Reserved

BRD

Reserved.

Divider X Enable

The baud rate equation is:

Baud Rate = UART_CLK / [ M * (BRD + 2) ] ; The default value of M is 16.

0 = Disable divider X ( M = 16).

1 = Enable divider X (M = EDIVM1+1, with EDIVM1

≥ 8).

Refer to Table 5-116 UART Baud Rate Setting Table for more information.

NOTE: When in IrDA mode, this bit must disabled.

Divider X Equal 1

0: M = EDIVM1+1, with restriction EDIVM1

≥ 8.

1: M = 1, with restriction BRD[15:0]

≥ 3.


Divider x

The baud rate divider M = EDIVM1+1.

Reserved.

Baud Rate Divider


- 308 -


Revision 2.4


IrDA Control Register (UARTn_IRDA)


UARTn_BA+0x28 R/W UART IrDA Control Register. UARTn_IRDA

7

Reserved

6

RXINV

5

TXINV

4

Reserved

3

Bits

[31:7]

[6]

[5]

[4:3]

[2]

[1]

[0]

2

LOOPBACK

1

TXEN

Reset Value

0x0000_0040

Table 5-129 UART IrDA Control Register (UARTn_IRDA, address 0x4005_0028)

Description

Reserved

RXINV

TXINV

Reserved

LOOPBACK

TXEN

Reserved

Reserved.

Receive Inversion Enable

0= No inversion.

1= Invert Rx input signal.

Transmit Inversion Enable

0= No inversion.

1= Invert Tx output signal.

Reserved.

IrDA Loopback Test Mode

Loopback Tx to Rx.

Transmit/Receive Selection

0=Enable IrDA receiver.

1= Enable IrDA transmitter.

Reserved.

0

Reserved

- 309 -


Revision 2.4


UART LIN Network Control Register (UARTn_ALTCTL)


UARTn_ALTCTL UARTn_BA+0x2C R/W UART LIN Control Register.

31 30 29 28 27

Reserved

23 22 21 20 19

Reserved

15 14 13 12 11

Reserved

7

LINTXEN

6

LINRXEN

5

Reserved

4 3

26

18

10

2

BRKFL

25

17

9

1

Reset Value

0x0000_0000

24

16

8

0

Table 5-130 UART LIN Network Control Register (UARTn_ALTCTL, address 0x4005_002C)

Bits

[31:8]

Description

Reserved

[7]

[6]

[5:4]

[3:0]

LINTXEN

LINRXEN

Reserved

BRKFL

Reserved.

LIN TX Break Mode Enable

0 = Disable LIN Tx Break Mode.

1 = Enable LIN Tx Break Mode.

NOTE: When Tx break field transfer operation finished, this bit will be cleared automatically.

LIN RX Enable

0 = Disable LIN Rx mode.

1 = Enable LIN Rx mode.

UART LIN Break Field Length Count

This field indicates a 4-bit LIN Tx break field count.

NOTE: This break field length is BRKFL + 2

- 310 -


Revision 2.4


UART Function Select Register (UARTn_FUNCSEL)


UARTn_FUNCSEL UARTn_BA+0x30 R/W UART Function Select Register.

31 30 29 28 27

Reserved

23 22 21 20 19

Reserved

15 14 13 12 11

Reserved

7 6 5 4 3

Reserved

26

18

10

2

25

17

9

1

IRDAEN

Reset Value

0x0000_0000

24

16

8

0

LINEN

Table 5-131 UART Function Select Register (UARTn_FUNCSEL, address 0x4005_0030)

Bits

[31:2]

Description

Reserved

[1]

[0]

IRDAEN

LINEN

Reserved.

Enable IrDA Function

0 = UART Function.

1 = Enable IrDA Function.

Enable LIN Function

0 = UART Function.

1 = Enable LIN Function.

Note that IrDA and LIN functions are mutually exclusive: both cannot be active at same time.

- 311 -


Revision 2.4


5.14 I2S Audio PCM Controller

5.14.1 Overview

The I2S controller is a peripheral for serial transmission and reception of audio PCM (Pulse-Code

Modulated) signals across a 4-wire bus. The bus consists of a bit clock (I2S_BCLK) a frame synchronization clock (I2S_FS) and serial data in (I2S_SDI) and out (I2S_SDO) lines. This peripheral allows communication with an external audio CODEC or DSP. The peripheral is capable of mono or stereo audio transmission with 8-32bit word sizes. Audio data is buffered in 8 word deep FIFO buffers and has DMA capability.

5.14.2 Features

 I2S can operate as either master or slave

 Master clock generation for slave device synchronization.

 Capable of handling 16, 24 and 32 bit word sizes.

 Mono and stereo audio data supported.

 I2S and MSB justified data format supported.

 8 word FIFO data buffers for transmit and receive.

 Generates interrupt requests when buffer levels crosses programmable boundary.

 Two DMA requests, one for transmit and one for receive.

- 312 -


Revision 2.4


5.14.3 I2S Block Diagram

OSC10K

OSC32K

HCLK

OSC48M

00

01

10

11

I2S 0 SEL( CLK_CLKSEL2[1:0]

I2S0CKEN( CLK_APBCLK0[29]

I2S_CLK

Figure 5-77 I2S Clock Control Diagram

I2S_MCLK

I2S_CLK_GEN

I2S_FS dma_req

APB

Interface

&

Control

Registers dma_ack

WS

MUX

Transmit

Contrl

&

TXFIFO

Tx Shift Register

Shift Clock

MUX

Receive

Control

&

RXFIFO

Rx Shift Register

SLAVE_MODE

Figure 5-78 I2S Controller Block Diagram

I2S_SDO

I2S_BCLK

I2S_SDI

- 313 -


Revision 2.4


5.14.4 I2S Operation

I2S_BCLK

//

I2S_FS

I2S_SDI

I2S_SDO

//

//

LSB MSB LSB

//

Word N-1

Right Channel

Word N

Left Channel

Figure 5-79 I2S Bus Timing Diagram (Format =0)

MSB

Word N

Right Channel

//

I2S_BCLK

I2S_FS

I2S_SDI

I2S_SDO

//

//

LSB MSB LSB

//

Word N-1

Right Channel

Word N

Left Channel

Figure 5-80 MSB Justified Timing Diagram (Format=1)

MSB

Word N

Right Channel

- 314 -


Revision 2.4

5.14.5 FIFO operation


Mono 16-bit data mode

N+1

15

Stereo 16-bit data mode

LEFT

15


0

0

15

15

N

23


23

LEFT

N

RIGHT


23

RIGHT

N

31


LEFT

31

31

0

0

0

0

N

0

N+1

0

0

N

RIGHT

Figure 5-81 FIFO contents for various I2S modes

0

N+1

- 315 -


Revision 2.4





I2S Base Address:

I2S_BA = 0x400A_0000

I2S_CTL I2S_BA + 0x00

I2S_CLK I2S_BA + 0x04

I2S_BA + 0x08 I2S_IEN

I2S_STATUS I2S_BA + 0x0C

R/W I2S Control Register

R/W I2S Clock Divider Register

R/W I2S Interrupt Enable Register

R/W I2S Status Register

I2S_TX

I2S_RX

I2S_BA + 0x10

I2S_BA + 0x14

W

R

I2S Transmit FIFO Register

I2S Receive FIFO Register

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0014_1100

0xXXXX_XXXX

0xXXXX_XXXX

- 316 -


Revision 2.4



I2S Control Register (I2S_CTL)


I2S_CTL

31

I2S_BA + 0x00 R/W I2S Control Register

23

Reserved

15

MCLKEN

7

FORMAT

30 29 28 27

Reserved

22 21 20

Reserved RXPDMAEN TXPDMAEN

14 13 12

19

RXCLR

11

6

MONO

RXTH

5

WDWIDTH

4 3

MUTE

Bits

[31:22]

[21]

[20]

[19]

[18]

[17]

26

18

TXCLR

10

TXTH

2

RXEN

25

17

LZCEN

9

1

TXEN

Reset Value

0x0000_0000

24

16

RZCEN

8

SLAVE

0

I2SEN

Table 5-132 I2S Control Register (I2S_CTL, address 0x400A_0000)

Description

Reserved

RXPDMAEN

TXPDMAEN

RXCLR

TXCLR

LZCEN

Reserved.

Enable Receive DMA

When RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to

SRAM if FIFO is not empty.

0 = Disable RX DMA.

1 = Enable RX DMA.

Enable Transmit DMA

When TX DMA is enables, I2S request DMA to transfer data from SRAM to transmit

FIFO if FIFO is not full.

0 = Disable TX DMA.

1 = Enable TX DMA.

Clear Receive FIFO

Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and

I2S_STATUS.RXCNT[3:0] returns to zero and receive FIFO becomes empty.

This bit is cleared by hardware automatically when clear operation complete.

Clear Transmit FIFO

Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and

I2S_STATUS.TXCNT[3:0] returns to zero and transmit FIFO becomes empty. Data in transmit FIFO is not changed.

This bit is cleared by hardware automatically when clear operation complete.

Left Channel Zero Cross Detect Enable

If this bit is set to 1, when left channel data sign bit changes, or data bits are all zero, the LZCIF flag in I2S_STATUS register will be set to 1.

0 = Disable left channel zero cross detect.

1 = Enable left channel zero cross detect.

- 317 -


Revision 2.4

[16]

[15]

[14:12]

[11:9]

[8]

[7]

[6]

[5:4]

[3]

RZCEN

MCLKEN

RXTH

TXTH

SLAVE

FORMAT

MONO

WDWIDTH

MUTE


Right Channel Zero Cross Detect Enable

If this bit is set to 1, when right channel data sign bit changes, or data bits are all zero, the RZCIF flag in I2S_STATUS register will be set to 1.

0 = Disable right channel zero cross detect.

1 = Enable right channel zero cross detect.

Master Clock Enable

The ISD91200can generate a master clock signal to an external audio CODEC to synchronize the audio devices. If audio devices are not synchronous, then data will be periodically corrupted. Software needs to implement a way to drop/repeat or interpolate samples in a jitter buffer if devices are not synchronized. The master clock frequency is determined by the I2S_CLKDIV.MCLKDIV[2:0] register.

0 = Disable master clock.

1 = Enable master clock.

Receive FIFO Threshold Level

When received data word(s) in buffer is equal or higher than threshold level then

RXTHI flag is set.

Threshold = RXTH+1 words of data in receive FIFO.

Transmit FIFO Threshold Level

If remaining data words in transmit FIFO less than or equal to the threshold level then TXTHI flag is set.

Threshold = TXTH words remaining in transmit FIFO.

Slave Mode

I2S can operate as a master or slave. For master mode, I2S_BCLK and I2S_FS pins are outputs and send bit clock and frame sync from ISD91200. In slave mode,

I2S_BCLK and I2S_FS pins are inputs and bit clock and frame sync are received from external audio device.

0 = Master mode.

1 = Slave mode.

Data Format

0 = I2S data format.

1 = MSB justified data format.

See Figure 5-79 I2S Bus Timing Diagram (Format =0) and Figure 5-80 MSB Justified

Timing Diagram (Format=1) for timing differences.

Monaural Data

This parameter sets whether mono or stereo data is processed. See Figure 5-81

FIFO contents for various I2S modes for details of how data is formatted in transmit

and receive FIFO.

0 = Data is stereo format.

1 = Data is monaural format.

Word Width

This parameter sets the word width of audio data. See Figure 5-81 FIFO contents for various I2S modes for details of how data is formatted in transmit and receive FIFO.

00 = data is 8 bit.

01 = data is 16 bit.



Transmit Mute Enable

0 = Transmit data is shifted from FIFO.

1= Transmit channel zero.

- 318 -


Revision 2.4

[2]

[1]

[0]

RXEN

TXEN

I2SEN


Receive Enable

0 = Disable data receive.

1 = Enable data receive.

Transmit Enable

0 = Disable data transmit.

1 = Enable data transmit.

Enable I2S Controller

0 = Disable.

1 = Enable.

- 319 -


Revision 2.4


I2S Clock Divider (I2S_CLKDIV)


I2S_BA + 0x04 R/W I2S Clock Divider Register I2S_CLKDIV

15 14 13 12 11

BCLKDIV

7 6 5

Reserved

4 3

10

2

9

1

MCLKDIV

Reset Value

0x0000_0000

Table 5-133 I2S Clock Divider Register (I2S_CLKDIV, address 0x400A_0004)

8

0

Bits

[31:16]

Description

Reserved

[15:8]

[7:3]

[2:0]

BCLKDIV

Reserved

MCLKDIV

Reserved.

Bit Clock Divider

If I2S operates in master mode, bit clock is provided by ISD91200. Software can program these bits to generate bit clock frequency for the desired sample rate.

For sample rate Fs, the desired bit clock frequency is:

F

BCLK

= Fs x Word_width_in_bytes x 16.

For example if Fs = 16kHz, and word width is 2-bytes (16bit) then desired bit clock frequency is 512kHz.

The bit clock frequency is given by:

F

BCLK

= F

I2S_CLKDIV

/ (2x (BCLKDIV+1)).

Or,

BCLKDIV = F

I2S_CLKDIV

/ (2 x F

BCLK

) -1.

So if F

I2S_CLKDIV

= HCLK = 49.152MHz

F

BCLK

= 512kHz then BCLKDIV = 47.

, desired

Reserved.

Master Clock Divider

ISD91200can generate a master clock to synchronously drive an external audio device. If MCLKDIV is set to 0, MCLK is the same as I2S_CLKDIV clock input, otherwise MCLK frequency is given by:

F

MCLK

= F

I2S_CLKDIV

/ (2 x MCLKDIV).

Or,

MCLKDIV = F

I2S_CLKDIV

/ (2 x F

MCLK

).

If the desired MCLK frequency is 4.092MHz (= 256Fs) and Fs = 16kHz then

MCLKDIV = 6 @ F

I2S_CLKDIV

= 49.152MHz

.

- 320 -


Revision 2.4


I2S Interrupt Enable Register (I2S_IEN)


I2S_BA + 0x08 R/W I2S Interrupt Enable Register I2S_IEN

15

7

14

Reserved

6

13 12

LZCIEN

4

11

RZCIEN

3 5

Reserved

10

TXTHIEN

2

RXTHIEN

9

TXOVIEN

1

RXOVIEN

Reset Value

0x0000_0000

Table 5-134 I2S Interrupt Enable Register (I2S_IEN, address 0x400A_0008)

8

TXUDIEN

0

RXUDIEN

Bits

[31:13]

Description

Reserved

[12]

[11]

[10]

[9]

[8]

[7:3]

[2]

[1]

LZCIEN

RZCIEN

TXTHIEN

TXOVIEN

TXUDIEN

Reserved

RXTHIEN

RXOVIEN

Reserved.

Left Channel Zero Cross Interrupt Enable

Interrupt will occur if this bit is set to 1 and left channel has zero cross event


1 = Enable interrupt.

Right Channel Zero Cross Interrupt Enable

Interrupt will occur if this bit is set to 1 and right channel has zero cross event



Transmit FIFO Threshold Level Interrupt Enable

Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than

TXTH[2:0].



Transmit FIFO Overflow Interrupt Enable

Interrupt occurs if this bit is set to 1 and transmit FIFO overflow flag is set to 1



Transmit FIFO Underflow Interrupt Enable

Interrupt occur if this bit is set to 1 and transmit FIFO underflow flag is set to 1.



Reserved.

Receive FIFO Threshold Level Interrupt

Interrupt occurs if this bit is set to 1 and data words in receive FIFO is greater than or equal to RXTH[2:0].



Receive FIFO Overflow Interrupt Enable



- 321 -


Revision 2.4

[0]


RXUDIEN

Receive FIFO Underflow Interrupt Enable

If software read receive FIFO when it is empty then RXUDIF flag in I2SSTATUS register is set to 1.



- 322 -


Revision 2.4


I2S Status Register (I2S_STATUS)


I2S_BA + 0x0C R/W I2S Status Register I2S_STATUS

31 28

23

LZCIF

15

7

30 29

22

RZCIF

TXCNT

21

TXBUSY

13 14

Reserved

6 5

Reserved

20

TXEMPTY

12

RXEMPTY

4

27

19

TXFULL

11

RXFULL

3

RIGHT

26 25

18

TXTHIF

RXCNT

17

TXOVIF

10

RXTHIF

9

RXOVIF

2

TXIF

1

RXIF

Table 5-135 I2S Status Register (I2S_STATUS, address 0x400A_000C)

Reset Value

0x0014_1100

24

16

TXUDIF

8

RXUDIF

0

I2SIF


[31:28]

[27:24]

[23]

[22]

[21]

[20]

[19]

TXCNT

RXCNT

LZCIF

RZCIF

TXBUSY

TXEMPTY

TXFULL

Transmit FIFO Level (Read Only)

TXCNT = number of words in transmit FIFO.

Receive FIFO Level (Read Only)

RXCNT = number of words in receive FIFO.

Left Channel Zero Cross Flag (Write ‘1’ to Clear, or Clear LZCEN)

0 = No zero cross detected.

1 = Left channel zero cross is detected.

Right Channel Zero Cross Flag (Write ‘1’ to Clear, or Clear RZCEN)

0 = No zero cross.

1 = Right channel zero cross is detected.

Transmit Busy (Read Only)

This bit is cleared when all data in transmit FIFO and Tx shift register is shifted out. It is set when first data is loaded to Tx shift register.

0 = Transmit shift register is empty.

1 = Transmit shift register is busy.

Transmit FIFO Empty (Read Only)

This is set when transmit FIFO is empty.

0 = Not empty.

1 = Empty.

Transmit FIFO Full (Read Only)

This bit is set when transmit FIFO is full.

0 = Not full.

1 = Full.

- 323 -


Revision 2.4

[8]

[7:4]

[3]

[18]

[17]

[16]

[15:13]

[12]

[11]

[10]

[9]

TXTHIF

TXOVIF

TXUDIF

Reserved

RXEMPTY

RXFULL

RXTHIF

RXOVIF

RXUDIF

Reserved

RIGHT


Transmit FIFO Threshold Flag (Read Only)

When data word(s) in transmit FIFO is less than or equal to the threshold value set in TXTH[2:0] the TXTHIF bit becomes to 1. It remains set until transmit FIFO level is greater than TXTH[2:0]. Cleared by writing to I2S_TX register until threshold exceeded.

0 = Data word(s) in FIFO is greater than threshold level.

1 = Data word(s) in FIFO is less than or equal to threshold level.

Transmit FIFO Overflow Flag (Write ‘1’ to Clear)

This flag is set if data is written to transmit FIFO when it is full.

0 = No overflow.

1 = Overflow.

Transmit FIFO Underflow Flag (Write ‘1’ to Clear)

This flag is set if I2S controller requests data when transmit FIFO is empty.

0 = No underflow.

1 = Underflow.

Reserved.

Receive FIFO Empty (Read Only)

This is set when receive FIFO is empty.

0 = Not empty.

1 = Empty.

Receive FIFO Full (Read Only)

This bit is set when receive FIFO is full.

0 = Not full.

1 = Full.

Receive FIFO Threshold Flag (Read Only)

When data word(s) in receive FIFO is greater than or equal to threshold value set in

RXTH[2:0] the RXTHIF bit becomes to 1. It remains set until receive FIFO level is less than RXTH[2:0]. It is cleared by reading I2S_RX until threshold satisfied.

0 = Data word(s) in FIFO is less than threshold level.

1 = Data word(s) in FIFO is greater than or equal to threshold level.

Receive FIFO Overflow Flag (Write ‘1’ to Clear)

This flag is set if I2S controller writes to receive FIFO when it is full. Audio data is lost.

0 = No overflow.

1 = Overflow.

Receive FIFO Underflow Flag (Write ‘1’ to Clear)

This flag is set if attempt is made to read receive FIFO while it is empty.

0 = No underflow.

1 = Underflow.

Reserved.

Right Channel Active (Read Only)

This bit indicates current data being transmitted/received belongs to right channel

0 = Left channel.

1 = Right channel.

- 324 -


Revision 2.4

[2]

[1]

[0]

TXIF

RXIF

I2SIF


I2S Transmit Interrupt (Read Only)

This indicates that there is an active transmit interrupt source. This could be

TXOVIF, TXUDIF, TXTHIF, LZCIF or RZCIF if corresponding interrupt enable bits are active. To clear interrupt the corresponding source(s) must be cleared.

0 = No transmit interrupt.

1 = Transmit interrupt occurred.

I2S Receive Interrupt (Read Only)

This indicates that there is an active receive interrupt source. This could be RXOVIF,

RXUDIF or RXTHIF if corresponding interrupt enable bits are active. To clear interrupt the corresponding source(s) must be cleared.

0 = No receive interrupt.

1 = Receive interrupt occurred.

I2S Interrupt (Read Only)

This bit is set if any enabled I2S interrupt is active.

0 = No I2S interrupt.

1 = I2S interrupt active.

- 325 -


Revision 2.4


I2S Transmit FIFO (I2S_TX)


I2S_BA + 0x10 W I2S Transmit FIFO Register I2S_TX

31 30 29 28 27

TX

23 22 21 20 19

TX

15 14 13 12 11

TX

7 6 5 4 3

TX

26

18

10

2

25

17

9

1

Table 5-136 I2S Transmit FIFO Register (I2S_TX, address 0x400A_0010)

Reset Value

0xXXXX_XXXX

24

16

8

0


[31:0] TX

Transmit FIFO Register (Write Only)

A write to this register pushes data onto the transmit FIFO. The transmit FIFO is eight words deep. The number of words currently in the FIFO can be determined by reading I2S_STATUS.TXCNT.

- 326 -


Revision 2.4


I2S Receive FIFO (I2S_RX)


I2S_BA + 0x14 R I2S Receive FIFO Register I2S_RX

31 30 29 28 27

RX

23 22 21 20 19

RX

15 14 13 12 11

RX

7 6 5 4 3

RX

26

18

10

2

25

17

9

1

Table 5-137 I2S Receive FIFO Register (I2S_RX, address 0x400A_0014)

Reset Value

0xXXXX_XXXX

24

16

8

0


[31:0] RX

Receive FIFO Register (Read Only)

A read of this register will pop data from the receive FIFO. The receive FIFO is eight words deep. The number of words currently in the FIFO can be determined by reading I2S_STATUS.RXCNT.

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Revision 2.4


5.15 PDMA Controller

5.15.1 Overview

The ISD91200 incorporates a Peripheral Direct Memory Access (PDMA) controller that transfers data between SRAM and APB devices. The PDMA has four channels of DMA PDMA CH0~CH3). PDMA transfers are unidirectional and can be Peripheral-to-SRAM,SRAM-to-Peripheral or SRAM-to-SRAM.

The peripherals available for PDMA transfer are SPI, UART, I2S, SDADC, SARADC and DPWM.

PDMA operation is controlled for each channel by configuring a source and destination address and specifying a number of bytes to transfer. Source and destination addresses can be fixed, automatically increment by the transfer size, update by an arbitrary value (span mode) or wrap around a circular buffer. When PDMA operation is complete, controller can be configured to provide CPU with an interrupt.

5.15.2 Features

 Provides access to SPI, UART, I2S, SDADC and DPWM peripherals.

 AMBA AHB master/slave interface, transfers can occur concurrently with CPU access to flash memory.

 PDMA source and destination addressing modes allow fixed, incrementing, wrap-around and spanned addressing.


SRAM

AHB ARB

CortexM0

PDMA

Controller

APB Bridge

AHB ARB

AHB BUS1

AHB BUS2

PDMA

Service

Request

Signals from

Peripherals

PDMA

Control

Registers

Figure 5-82 PDMA Controller Block Diagram

APB Bus

To

Peripherals

- 328 -


Revision 2.4


5.15.4 Function Description

The PDMA controller has four channels of DMA, each channel can be configured to one of the following transfer types: Peripheral-to-SRAM SRAM-to-Peripheral or SRAM-to-SRAM. The SRAM and the AHB-

APB bus bridge each have an AHB bus arbiter that allows AHB bus access to occur either from the

CPU or the PDMA controller. The PDMA controller requests bus transfers over the AHB bus from one address into a single word buffer within the PDMA controller then writes this buffer to another address over the AHB bus. Peripherals with PDMA capability generate control signals to the PDMA block requesting service when they need data (Rx request) or have data to transfer (Tx request). The PDMA control registers reside in address space on the AHB bus.

Transfer completion can be determined by polling of status registers or by generation of PDMA interrupt to CPU. A transfer is set up as a specified number of bytes from a source address to a destination address. Both source and destination address can be configured as a fixed address, an incrementing address or a wrap-around buffer address.

The general procedure to operate a DMA channel is as follows:

•

Enable PDMA channel n clock by setting PDMA_GCTLn.CHnCKEN

•

Enable PDMA channel n by setting PDMA_CTLn.CHEN

•

Set source address in PDMA_SADDRn

•

Set destination address in PDMA_DADDRn

•

Set the transfer count in PDMA_TXCNTn

•

Set transfer mode and address increment mode in

PDMA_CTLn.MODESEL

•

Route peripheral PDMA request signal to channel n in service selection register.

•

Trigger transfer PDMA_CTLn.TXEN

If the source or destination address is not in wraparound mode, the PDMA will continue the transfer until PDMA_CURTXCNTn decrements to zero ( PDMA_CURTXCNTn is initialized to PDMA_TXCNTn , in wraparound mode, PDMA_CURTXCNTn will reload and continue until PDMA_GCTL.CHnCKEN

is disabled). If an error occurs during the PDMA operation, the channel stops until software clears the error condition and sets the PDMA_CTnL.SWRST

bit to reset the PDMA channel. After reset the PDMA_CTLn.CHEN

and

PDMA_CTLn.TXEN

bits would need to be set to start a new operation.

- 329 -


Revision 2.4




Register Offset

PDMA Base Address:

PDMAn_BA = 0x5000_8000 +(n*0x100) n=0,1,2,3

PDMA Global Control Base Address:

PDMA_GCR_BA = 0x5000_8F00

PDMA_CTLn

R/W Description

PDMAn_BA+0x00 R/W PDMA Control Register of Channel n

PDMA_SADDRn

PDMA_DADDRn

Reset Value

0x0000_0000

PDMAn_BA+0x04 R/W

PDMA Transfer Source Address Register of

Channel n

0x4000_0000

PDMAn_BA+0x08 R/W

PDMA Transfer Destination Address Register of

Channel n

0x4000_0000

PDMA_TXCNTn PDMAn_BA+0x0C R/W PDMA Transfer Byte Count Register of Channel n 0x0000_0000

PDMA_INTPNTn

PDMA_CURSADDRn

PDMA_CURDADDRn

PDMA_CURTXCNTn

PDMA_INTENn

PDMAn_BA+0x10

PDMAn_BA+0x14

PDMAn_BA+0x18

PDMAn_BA+0x1C

R

R

R

R

PDMA Internal Buffer Pointer Register of Channel n

0xXXXX_XX00

PDMA Current Source Address Register of

Channel n

PDMA Current Destination Address Register of

Channel n

PDMA Current Transfer Byte Count Register of

Channel n

0xFFFF_FFFF

0xFFFF_FFFF

0x0000_0000

PDMAn_BA+0x20 R/W

PDMA Interrupt Enable Control Register of

Channel n

0x0000_0001

PDMA_INTSTSn PDMAn_BA+0x24 R/W PDMA Interrupt Status Register of Channel n 0x0000_0000

PDMA_SPANn

PDMA_CURSPANn

PDMA_GCTL

PDMA_SVCSEL0

PDMA_SVCSEL1

PDMA_GINTSTS

PDMAn_BA+0x34 R PDMA Span Increment Register of Channel n

PDMAn_BA+0x38 R/W

PDMA Current Span Increment Register of

Channel n

PDMA_GCR_BA+0x

00

R/W PDMA Global Control Register

PDMA_GCR_BA+0x

04

R/W PDMA Service Selection Control Register 0

PDMA_GCR_BA+0x

08

R/W PDMA Service Selection Control Register 1

PDMA_GCR_BA+0x

0C

R PDMA Global Interrupt Status Register

0x0000_0000

0x0000_0000

0x0000_0000

0xFFFF_FFFF

0xFFFF_FFFF

0x0000_0000

- 330 -


Revision 2.4



PDMA Control Register (PDMA_CTLn)


PDMA_CTLn PDMAn_BA+0x00 R/W PDMA Control Register of Channel n

31 30 29 28 27 26 25

Reserved

23

TXEN

15

7

DASEL

22 21

Reserved

14

WAINTSEL

13

6 5

SASEL

20

12

4

TXWIDTH

19

11

3

MODESEL

18

10

17

Reserved

9

Reserved

2 1

SWRST

Reset Value

0x0000_0000

24

16

8

0

CHEN

Table 5-138 PDMA Control and Status Register ( PDMA_CTLn , address 0x5000_8000 + n * 0x100)

Bits

[31:24]

Description

Reserved

[23]

[22:21]

[20:19]

[18:16]

TXEN

Reserved

TXWIDTH

Reserved

Trigger Enable – Start a PDMA Operation

0 = Write: no effect. Read: Idle/Finished.

1 = Enable PDMA data read or write transfer.

Note: When PDMA transfer completed, this bit will be cleared automatically.

If a bus error occurs, all PDMA transfer will be stopped. Software must reset PDMA channel, and then trigger again.

Peripheral Transfer Width Select

This parameter determines the data width to be transferred each PDMA transfer operation.

00 = One word (32 bits) is transferred for every PDMA operation.

01 = One byte (8 bits) is transferred for every PDMA operation.

10 = One half-word (16 bits) is transferred for every PDMA operation.

11 = Reserved.

Note: This field is meaningful only when MODESEL is IP to Memory mode (APB-to-

Memory) or Memory to IP mode (Memory-to-APB).

- 331 -


Revision 2.4

[15:12]

[11:8]

[7:6]

[5:4]

[3:2]

[1]

WAINTSEL

Reserved

DASEL

SASEL

MODESEL

SWRST


Wrap Interrupt Select x1xx: If this bit is set, and wraparound mode is in operation a Wrap Interrupt can be generated when half each PDMA transfer is complete. For example if

PDMA_TXCNTn = 32 then an interrupt could be generated when 16 bytes were sent. xxx1: If this bit is set, and wraparound mode is in operation a Wrap Interrupt can be generated when each PDMA transfer is wrapped. For example if PDMA_TXCNTn =

32 then an interrupt could be generated when 32 bytes were sent and PDMA wraps around. x1x1: Both half and w interrupts generated.

Destination Address Select

This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed, incremented or wrapped.

00 = Transfer Destination Address is incremented.

01 = Reserved.

10 = Transfer Destination Address is fixed (Used when data transferred from multiple addresses to a single destination such as peripheral FIFO input).

11 = Transfer Destination Address is wrapped.

When PDMA_CURTXCNTn (Current Byte Count) equals zero, the

PDMA_CURDADDR (Current Destination Address) and PDMA_CURTXCNTn registers will be reloaded from the PDMA_DADDRn (Destination Address) and

PDMA_TXCNTn (Byte Count) registers automatically and PDMA will start another transfer.

Cycle continues until software sets PDMA_CTLn.CHEN =0.

When PDMA_CTLn.CHEN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address.

Source Address Select

This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed, incremented or wrapped.

00 = Transfer Source address is incremented.

01 = Reserved.

10 = Transfer Source address is fixed.

11 = Transfer Source address is wrapped.

When PDMA_CURTXCNTn (Current Byte Count) equals zero, the

PDMA_CURSADDRn (Current Source Address) and PDMA_CURTXCNTn registers will be reloaded from the PDMA_SADDRn (Source Address) and PDMA_TXCNT

(Byte Count) registers automatically and PDMA will start another transfer.

Cycle continues until software sets PDMA_CTLn.CHEN = 0.

When PDMA_CTLn.CHEN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address.

PDMA Mode Select

This parameter selects to transfer direction of the PDMA channel. Possible values are:

00 = Memory to Memory mode (SRAM-to-SRAM).

01 = IP to Memory mode (APB-to-SRAM).

10 = Memory to IP mode (SRAM-to-APB).

Software Engine Reset


1 = Writing 1 to this bit will reset the internal state machine and pointers. The contents of the control register will not be cleared. This bit will auto clear after a few clock cycles.

- 332 -


Revision 2.4

[0] CHEN


PDMA Channel Enable

Setting this bit to 1 enables PDMA’s operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.

Note: SWRST will clear this bit.

- 333 -


Revision 2.4


PDMA Transfer Source Address Register (PDMA_SADDRn)


PDMAn_BA+0x04 R/W PDMA Transfer Source Address Register of Channel n PDMA_SADDRn

31 30 29 28 27 26 25

SADDR

23 22 21 20 19 18 17

SADDR

15 14 13 12 11 10 9

SADDR

7 6 5 4 3 2 1

SADDR

Reset Value

0x4000_0000

24

16

8

0

Table 5-139 PDMA Source Address Register (PDMA_DADDRn, address 0x5000_8004 + n *0x100)


[31:0] ADDR

PDMA Transfer Source Address Register

This register holds the initial Source Address of PDMA transfer.

Note: The source address must be word aligned.

- 334 -


Revision 2.4


PDMA Transfer Destination Address Register (PDMA_DADDRn)


PDMA_DADDRn

Reset Value

PDMAn_BA+0x08 R/W PDMA Transfer Destination Address Register of Channel n 0x4000_0000

Table 5-140 PDMA Destination Address Register (PDMAT_DADDRn, address 0x5000_8008 + n *0x100)


[31:0] ADDR

PDMA Transfer Destination Address Register

This register holds the initial Destination Address of PDMA transfer.

Note: The destination address must be word aligned.

- 335 -


Revision 2.4


PDMA Transfer Byte Count Register (PDMA_TXCNTn)


PDMA_TXCNTn PDMAn_BA+0x0C R/W PDMA Transfer Byte Count Register of Channel n

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

CNT [15:8]

7 6 5 4 3 2

CNT [7:0]

25

17

9

1

Reset Value

0x0000_0000

24

16

8

0

Table 5-141 PDMA Transfer Byte Count Register (PDMA_TXCNTn, address 0x5000_800C + n *0x100)

Bits

[31:16]

Description

Reserved

[15:0] CNT

Reserved.

PDMA Transfer Byte Count Register

This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF.

Note: When in memory-to-memory (TXBCCHn.MODESEL = 00b) mode, the transfer byte count must be word aligned, that is multiples of 4bytes.

- 336 -


Revision 2.4


PDMA Internal Buffer Pointer Register (PDMA_INTPNTn)


0xXXXX_XX00 PDMA_INTPNTn PDMAn_BA+0x10 R

31 30 29

PDMA Internal Buffer Pointer Register of Channel n

28 27 26 25 24

Reserved

23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8

Reserved

7 6 5 4 3 2 1 0

Reserved POINTER

Table 5-142 PDMA Internal Buffer Point Register (PDMA_INTPNTn, address 0x5000_8010 + n *0x100)

Bits

[31:4]

Description

Reserved

[3:0] POINTER

Reserved.

PDMA Internal Buffer Pointer Register (Read Only)

A PDMA transaction consists of two stages, a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between the read and write transactions are different, this register tracks which byte/half-word of the internal buffer is being processed by the current transaction.

- 337 -


Revision 2.4


PDMA Current Source Address Register (PDMA_CURSADDRn) )


0xFFFF_FFFF PDMA_CURSADDRn PDMAn_BA+0x14 R PDMA Current Source Address Register of Channel n

Table 5-143 PDMA Current Source Address Register (PDMA_CURSADDRn, address 0x5000_8014 + n *0x100)


[31:0] ADDR

PDMA Current Source Address Register (Read Only)

This register returns the source address from which the PDMA transfer is occurring.

This register is loaded from PDMA_SADDRn when PDMA is triggered or when a wraparound occurs.

- 338 -


Revision 2.4


PDMA Current Destination Address Register (PDMA_CURDADDRn)


PDMA_CURDADDRn PDMAn_BA+0x18 R

Reset Value

PDMA Current Destination Address Register of Channel n 0xFFFF_FFFF

Table 5-144 PDMA Current Destination Address Register (PDMA_CURDADDRn, address

0x5000_8018 + n *0x100)


[31:0] ADDR

PDMA Current Destination Address Register (Read Only)

This register returns the destination address to which the PDMA transfer is occurring.

This register is loaded from PDMA_DADDRn when PDMA is triggered or when a wraparound occurs.

- 339 -


Revision 2.4


PDMA Current Transfer Byte Count Register (PDMA_CURTXCNTn)


PDMA_CURTXCNTn PDMAn_BA+0x1C R

Reset Value

PDMA Current Transfer Byte Count Register of Channel n 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8

CNT

7 6 5 4 3 2 1 0

CNT

Table 5-145 PDMA Current Byte Count Register (PDMA_CURTXCNTn, address 0x5000_801C + n *0x100)

Bits

[31:16]

Description

Reserved

[15:0] CNT

Reserved.

PDMA Current Byte Count Register (Read Only)

This field indicates the current remaining byte count of PDMA transfer. This register is initialized with CNT register when PDMA is triggered or when a wraparound occurs

- 340 -


Revision 2.4


PDMA Interrupt Enable Control Register (PDMA_INTENn)


PDMA_INTENn PDMAn_BA+0x20 R/W PDMA Interrupt Enable Control Register of Channel n

31 30 29 28 27 26 25

Reserved

23 22 21 20 19 18 17

Reserved

15 14 13 12 11 10 9

Reserved

7 6 5

Reserved

4 3 2

WRAPIEN

1

TXIEN

Reset Value

0x0000_0001

24

16

8

0

ABTIEN

Table 5-146 PDMA Interrupt Enable Control Register (PDMA_INTENn, address 0x5000_8020 + n *0x100)

Bits

[31:3]

Description

Reserved

[2]

[1]

[0]

WRAPIEN

TXIEN

ABTIEN

Reserved.

Wraparound Interrupt Enable

If enabled, and channel source or destination address is in wraparound mode, the

PDMA controller will generate a WRAP interrupt to the CPU according to the setting of

PDMA_DSCTn_CTL.WAINTSEL. This can be interrupts when the transaction has finished and has wrapped around and/or when the transaction is half way in progress. This allows the efficient implementation of circular buffers for DMA.

0 = Disable Wraparound PDMA interrupt generation.

1 = Enable Wraparound interrupt generation.

PDMA Transfer Done Interrupt Enable

If enabled, the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete.

0 = Disable PDMA transfer done interrupt generation.

1 = Enable PDMA transfer done interrupt generation.

PDMA Read/Write Target Abort Interrupt Enable

If enabled, the PDMA controller will generate and interrupt to the CPU whenever a

PDMA transaction is aborted due to an error. If a transfer is aborted, PDMA channel must be reset to resume DMA operation.

0 = Disable PDMA transfer target abort interrupt generation.

1 = Enable PDMA transfer target abort interrupt generation.

- 341 -


Revision 2.4


PDMA Interrupt Status Register (PDMA_INTSTSn)


PDMA_INTSTSn PDMAn_BA+0x24 R/W PDMA Interrupt Status Register of Channel n

31

INTSTS

23

15

30

22

14

29

21

13

28

20

27

Reserved

19

Reserved

12 11

26

18

10

Reserved WRAPIF

25

17

9

7 6 5

Reserved

4 3 2 1

TXIF

Reset Value

0x0000_0000

24

16

8

0

ABTIF

Table 5-147 PDMA Interrupt Enable Status Register (PDMA_INTSTSn, address 0x5000_8024 + n *0x100)


[31]

[30:12]

[11:8]

[7:2]

[1]

[0]

INTSTS

Reserved

WRAPIF

Reserved

TXIF

ABTIF

Interrupt Pin Status (Read Only)

This bit is the Interrupt pin status of PDMA channel.

Reserved.

Wrap Around Transfer Byte Count Interrupt Flag

These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits.

0001 = Current transfer finished flag (PDMA_CURTXCNT == 0).

0100 = Current transfer half complete flag (PDMA_CURTXCNT == PDMA_TXCNT

/2).

Reserved.

Block Transfer Done Interrupt Flag

This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit.

0 = Transfer ongoing or Idle.

1 = Transfer Complete.

PDMA Read/Write Target Abort Interrupt Flag

This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller receives a bus error from AHB master. Upon occurrence PDMA will stop transfer and go to idle state. To resume, software must reset PDMA channel and initiate transfer again.

0 = No bus ERROR response received.

1 = Bus ERROR response received.


- 342 -


Revision 2.4


PDMA Span Increment Register (PDMA_SPANn)


PDMAn_BA+0x34 R PDMA Span Increment Register of Channel n PDMA_SPANn

31 30 29 28 27 26 25

Reserved

23 22 21 20 19 18 17

Reserved

15 14 13 12 11 10 9

Reserved

7 6 5 4 3 2 1

SPAN

Reset Value

0x0000_0000

24

16

8

0

Table 5-148 PDMA Span Increment Register (PDMA_SPANn, address 0x5000_8034 + n *0x100)

Bits

[31:8]

Description

Reserved

[7:0] SPAN

Reserved.

Span Increment Register

This is a signed number in range [-128,127] for use in spanned address mode. If destination or source addressing mode is set as spanned, then this number is added to the address register each transfer. The size of the transfer is determined by the

APB_TW setting. Note that span increment must be a multiple of the transfer width otherwise a memory addressing HardFault will occur. Also SPAN may be a negative number.

- 343 -


Revision 2.4


PDMA Current Span Increment Register (PDMA_CURSPANn)


PDMA_CURSPANn PDMAn_BA+0x38

Reset Value

R/W PDMA Current Span Increment Register of Channel n 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8

Reserved

7 6 5 4 3 2 1 0

SPAN

Table 5-149 PDMA Current Span Increment Register (PDMA_CURSPANn, address 0x5000_8038 + n *0x100)

Bits

[31:8]

Description

Reserved

[7:0] SPAN

Reserved.

Current Span Increment Register

This is a signed read only register for use in spanned address mode. It provides the current address offset from SADDR or DADDR if either is set to span mode.

- 344 -


Revision 2.4


PDMA Global Control Register (PDMA_GCTL)


PDMA_GCR_BA+0x00 R/W PDMA Global Control Register PDMA_GCTL

31 30 29 26

23

15

7

22

14

6

Reserved

21

13

5

28 27

Reserved

20 19

12

Reserved

11

CH3CKEN

3 4

Reserved

18

10

CH2CKEN

2

25

17

9

CH1CKEN

1

Reset Value

0x0000_0000

24

16

8

CH0CKEN

0

SWRST

Table 5-150 PDMA Global Control Register (PDMA_GCTL, address 0x5000_8F00)

Bits

[31:12]

Description

Reserved

[11]

[10]

[9]

[8]

[7:1]

[0]

CH3CKEN

CH2CKEN

CH1CKEN

CH0CKEN

Reserved

SWRST

Reserved.

PDMA Controller Channel 3 Clock Enable Control

1: Enable Channel 3 clock.

0: Disable Channel 3 clock.










Reserved.

PDMA Software Reset


1 = Writing 1 to this bit will reset the internal state machine and pointers. The contents of control register will not be cleared. This bit will auto clear after several clock cycles.

Note: This bit can reset all channels (global reset).

- 345 -


Revision 2.4


PDMA Service Selection Control Register 0(PDMA_SVCSEL0)


PDMA_SVCSEL0 PDMA_GCR_BA+0x04 R/W PDMA Service Selection Control Register 0

Reset Value

0xFFFF_FFFF

PDMA peripherals have transmit and/or receive request signals to control dataflow during PDMA transfers. These signals must be connected to the PDMA channel assigned by software for use with that peripheral. For instance if PDMA Channel 3 is to be used to transfer data from memory to DPWM peripheral, then DPWMTXSEL should be set to 3. This will route the DPWM transmit request signal to

PDMA channel 3, whenever DPWM has space in FIFO it will request transmission of data from PDMA.

When not used the selection should be set to 0xFF.

31 28 27 24

23

15

7

30 29

I2STXSEL

22

UART0XSEL

21

14 13

DPWMTXSEL

6 5

SPI0TXSEL

20

12

4

19

11

3

26 25

I2SRXSEL

18 17

UART0RXSEL

10 9

SDADCRXSEL

2 1

SPI0RXSEL

16

8

0

Table 5-151 PDMA Service Selection Control Register (PDMA_SVCSEL0, address 0x5000_8F04)


[31:28]

[27:24]

[23:20]

[19:16]

[15:12]

[11:8]

[7:4]

I2STXSEL

I2SRXSEL

UART0XSEL

UART0RXSEL

DPWMTXSEL

SDADCRXSEL

SPI0TXSEL

PDMA I2S Transmit Selection

This field defines which PDMA channel is connected to I2S peripheral transmit

(PDMA destination) request.

PDMA I2S Receive Selection

This field defines which PDMA channel is connected to I2S peripheral receive

(PDMA source) request.

PDMA UART0 Transmit Selection

This field defines which PDMA channel is connected to UART0 peripheral transmit


PDMA UART0 Receive Selection

This field defines which PDMA channel is connected to UART0 peripheral receive


PDMA DPWM Transmit Selection

This field defines which PDMA channel is connected to DPWM peripheral transmit


PDMA SDADC Receive Selection

This field defines which PDMA channel is connected to SDADC peripheral receive


PDMA SPI0 Transmit Selection

This field defines which PDMA channel is connected to SPI0 peripheral transmit


- 346 -


Revision 2.4

[3:0] SPI0RXSEL


PDMA SPI0 Receive Selection

This field defines which PDMA channel is connected to SPI0 peripheral receive


- 347 -


Revision 2.4


PDMA Service Selection Control Register 1(PDMA_SVCSEL1)


PDMA_SVCSEL1 PDMA_GCR_BA+0x08 R/W PDMA Service Selection Control Register 1

Reset Value

0xFFFF_FFFF

PDMA peripherals have transmit and/or receive request signals to control dataflow during PDMA transfers. These signals must be connected to the PDMA channel assigned by software for use with that peripheral. For instance if PDMA Channel 3 is to be used to transfer data from memory to DPWM peripheral, then DPWMTXSEL should be set to 3. This will route the DPWM transmit request signal to

PDMA channel 3, whenever DPWM has space in FIFO it will request transmission of data from PDMA.

When not used the selection should be set to 0xFF.

31 30 29 28 27 26 25 24

Reserved

23

15

7

22 21

Reserved

14

SPI1TXSEL

13

6

UART1XSEL

5

20

12

4

19

11

3

18 17

SARADCRXSEL

10

SPI1RXSEL

9

2 1

UART1RXSEL

16

8

0

Table 5-152 PDMA Service Selection Control Register (PDMA_SVCSEL1, address 0x5000_8F04)

Bits

[31:20]

Description

Reserved

[19:16]

[15:12]

[11:8]

[7:4]

[3:0]

SARADCRXSEL

SPI1TXSEL

SPI1RXSEL

UART1XSEL

UART1RXSEL

PDMA SARADC Receive Selection

This field defines which PDMA channel is connected to SARADC peripheral receive


PDMA SPI1 Transmit Selection

This field defines which PDMA channel is connected to SPI1 peripheral transmit


PDMA SPI1 Receive Selection

This field defines which PDMA channel is connected to SPI1 peripheral receive


PDMA UART1 Transmit Selection

This field defines which PDMA channel is connected to UART1 peripheral transmit


PDMA UART1 Receive Selection

This field defines which PDMA channel is connected to UART1 peripheral receive


- 348 -


Revision 2.4


PDMA Global Interrupt Status Register (PDMA_GINTSTS)


PDMA Global Interrupt Status Register PDMA_GINTSTS PDMA_GCR_BA+0x0C R

31 30 29

23

15

7

22

14

6

Reserved

21

13

5

Reset Value

0x0000_0000

28 27 26 25 24

Reserved

20 19 18 17 16

Reserved

12 11 10 9 8

4

Reserved

3 2 1 0

CH3INTSTS CH2INTSTS CH1INTSTS CH0INTSTS

Table 5-153 PDMA Global Interrupt Status Register (PDMA_GINTSTS, address 0x5000_8F0C)

Bits

[31:4]

Description

Reserved

[3]

[2]

[1]

[0]

CH3INTSTS

CH2INTSTS

CH1INTSTS

CH0INTSTS

Reserved.

Interrupt Pin Status of Channel 3 (Read Only)

This bit is the interrupt pin status of PDMA channel 3.







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Revision 2.4


5.16 Volume Control

5.16.1 Overview and feature

The volume control function is digital domain gain control and supports both side of SDADC and

DPWM. The audio signal can be changed from 36 dB to -108dB if using this feature.

The volume control is enabled by setting SDADCVOLEN and DPWMVOL_EN. The volume control shares a clock source with the BIQ filter so CLK_APBCLK0.BIQALCEN, also the volume value will multiply

BIQ result so BIQ_ DLCOEFF must be set to operate volume control.

5.16.2 Volume Control Register Map


Register Offset

VOLCTRL Base Address:

VOLCTRL_BA = 0x400B_00a0

VOLCTRL_EN

R/W Description

VOLCTRL_BA+0x00 R/W Volume Control Enable Register

VOLCTRL_ADCVAL VOLCTRL_BA+0x04 R/W ADC Volume Control Value

VOLCTRL_DPWMVAL VOLCTRL_BA+0x08 R/W DPWM Volume Control Value

Reset Value

0x0000_0000

0x0004_0000

0x0004_0000

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Revision 2.4


5.16.3 Volume Control register Description

Volume Control Enable Register (VOLCTRL_EN)


0x0000_0000 VOLCTRL_EN VOLCTRL_BA+0x00 R/W Volume Control Enable Register

31

23

15

7

30

22

14

6

Reserved

29

21

13

5

28 27 26 25 24

Reserved

20 19 18 17 16

Reserved

12 11 10 9 8

4

Reserved

3 2 1 0

DPWMZCEN SDADCZCEN DPWMVOLEN SDADCVOLE

N

Bits

[31:4]

Description

Reserved

[3]

[2]

[1]

[0]

DPWMZCEN

SDADCZCEN

DPWMVOLEN

SDADCVOLEN

Reserved

DPWM Audio Signal Volume Zero Crossing Enable

0 = disable zero crossing update gain.

1 = enable Zero crossing update gain.

Delta-Sigma ADC Signal Volume Zero Crossing Enable

0 = disable zero crossing update gain.

1 = enable Zero crossing update gain.

DPWM Audio Signal Volume Control Enable

0 = bypass the volume control function.

1 = enable the volume control function.

Delta-Sigma ADC Signal Volume Control Enable

0 = bypass the volume control function.

1 = enable the volume control function.

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Revision 2.4


ADC Volume Control Value(VOLCTRL_ADCVAL)


VOLCTRL_ADCVAL VOLCTRL_BA+0x04 R/W ADC Volume Control Value

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

VALUE

15 14 13 12 11 10

VALUE

7 6 5 4 3 2

VALUE

Bits

[31:24]

Description

Reserved

[23:0] VALUE

Reserved

Delta-Sigma ADC Signal Volume Control Value

Format <6,18>, gain range from -108.3dB to 36.1dB

0x00_0001 --- -108.3dB

…

0x04_0000 ---- 0dB(default)

…

0xCC_CCCC ---- 34.1dB

Others reserved

Volume db = 20*log10(VALUE)

25

17

9

1

Reset Value

0x0004_0000

24

16

8

0

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Revision 2.4


DAC Volume Control Value (VOLCTRL_DPWMVAL)


VOLCTRL_DPWMVAL VOLCTRL_BA+0x08 R/W DPWM Volume Control Value

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

VALUE

15 14 13 12 11 10

VALUE

7 6 5 4 3 2

VALUE

Bits

[31:24]

Description

Reserved

[23:0] VALUE

DPWM Audio Signal Volume Control Value

Format <6,18>. Gain range from 108.3dB to 36.1dB

0x00_0001 ---- -108.3dB

…

0x40_0000 ---- 0dB (default)

…

0xFF_FFFF ---- 36.1dB

Volume db = 20*log10(VALUE)

25

17

9

1

Reset Value

0x0004_0000

24

16

8

0

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Revision 2.4


6 FLASH MEMORY CONTROLLER (FMC)

6.1 Overview

The ISD91200 series is available with 64K/128K bytes of on-chip embedded Flash EEPROM for application program and data flash memory. The memory can be updated through procedures for In-

Circuit Programming (ICP) through the ARM Serial-Wire Debug (SWD) port or via In-System

Programming (ISP) functions under software control. In-System Programming (ISP) functions enable user to update program memory when chip is soldered onto PCB.

Main flash memory is divided into two partitions: Application Program ROM (APROM) and Data flash

(DATAF). In addition there are two other partitions, a 4K Byte Boot Loader ROM (LDROM),and

Configuration ROM (CONFIG).

Upon chip power-on, the Cortex-M0 CPU fetches code from APROM or LDROM determined by a boot select configuration in CONFIG.

The boundary between APROM and user DATA Flash can be configured to any page address boundary.

Erasable page size is 512 Byte.

This boundary is also specified in the CONFIG memory.

6.2 Features

 AHB interface compatible

 Runs up to 49 MHz with zero wait-state for continuous address read access

 Mini-cache to reduce flash access and power consumption.

 128/64KB application program memory (APROM)

 4KB in system programming (ISP) boot loader program memory (LDROM)

 Configurable data flash with 512 Bytes page erase unit

 Programmable data flash start address.

 In System Program (ISP) capability to update on chip Flash EEPROM

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Revision 2.4


6.3 Flash Memory Controller Block Diagram

The flash memory controller consist of AHB slave interface, ISP control logic, writer interface and flash macro interface timing control logic. The block diagram of flash memory controller is shown as following:

Cortex-M0

Debug

Access

Port

AHB Lite interface

AHB Bus

0x0001_FFFF

ICP

Writer

Interface

AHB Slave

Interface

ISP

Controller

0x0001_7FFF

Flash

Operation

Control

Power On

Initialization

Data Out

Control

CONFIG &

MAP

0x0000_FFFF

0x0000_0000

Application Memory

(APROM+DATA)

CBS=1

Figure 6-1 Flash Memory Control Block Diagram

0x0000_0FFF

0x0000_0000

ISP Program

Memory (LDROM)

CBS=0

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Revision 2.4


6.4 Flash Memory Organization

The ISD91200 flash memory consists of Application Program (APROM) memory (128/64KB), data flash

(DATAF), ISP boot loader (LDROM) program memory (4KB), user configuration (CONFIG). User configuration block provides 2 words that control system configuration, like flash security lock, boot select, brown out voltage level and data flash base address. The first two CONFIG words are loaded from CONFIG memory at power-on into device control registers to initialize certain chip functions. The data flash start address (FMC_DFBA) is defined in CONFIG memory and determines the relative size of the APROM and DATAF partitions.

Table 6-1 Memory Address Map

Block Name

APROM

Size

128 KB

Start Address

0x0000_0000

DATAF User Configurable DFBA

LDROM 4 KB 0x0010_0000

CONFIG 8B 0x0030_0000

The Flash memory organization is shown as below:

End Address

0x0001_FFFF (128KB)

DFBA-1 if DFEN!=0

0x0001_FFFF (128KB)

0x0010_0FFF

0x0030_0007

0x0030_01FF

0x0030_0000

0x0010_0FFF

Reserved

User Configuration

CONFIG

ISP Loader

Program Memory

LDROM

0x0010_0000

Reserved

0x0001_FFFF

Data Flash

DATAF

DFBADR

Application

Program Memory

APROM

0x0030_0004

0x0030_0000

CONFIG1

CONFIG0

0x0000_0000

Figure 6-2 Flash Memory Organization

6.5 Boot Selection

The ISD91200 provides an in-system programming (ISP) feature to enable user to update the application program memory when the chip is mounted on a PCB. A dedicated 4KBboot loader program memory is used to store ISP firmware. The user customizes this firmware to implement a protocol specific to their system to download updated application code. This firmware could utilize device

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Revision 2.4

ISD91200 Series Technical Reference Manual peripherals such as UART, SPI or I2C to fetch new application code. The memory area from which the

ISD91200 boots is controlled by the CBS bit in Config0 register.

6.6 Data Flash (DATAF)

The ISD91200 provides a data flash partition for user to store non-volatile data such as audio recordings. It accessed through ISP procedures via the Flash Memory Controller (FMC). The size of each erasable page is 512 byte and minimum write size is one word (4Bytes).An erase operation resets all memory in page to value 0xFF. A write operation can only change a ‘1’ bit to a ‘0’ bit. If a subset of the page needs to be changed, the entire 512B page must be copied to another page or into SRAM in advance as entire page must be erased before modification. Data flash and application program memory share the same memory space. If DFENB bit in Config0 is enabled (‘0’), the data flash base address is defined by DFBA and application program memory size is (X-N)KB and data flash size is N

KB, where X is the total device memory size (128/64) and N is number of Kbytes reserved for data flash.

0x0001_FFFF

Data Flash

DATAF

(N Kbytes)

DFBADR[31:0]=N*1024

Application

Program Memory

APROM

(X-N Kbytes)

X=128

Application

Program Memory

APROM

(X Kbytes)

0x0000_0000

DFENB=0 DFENB=1

Figure 6-3 Flash Memory Structure

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Revision 2.4


6.7 User Configuration (CONFIG)

Config0 (ISP Address = 0x0030_0000)

31 30 29 28

23

CBODEN

15

7

CBS

22

14

6

21

13

5

27

Reserved

20

12

19

Reserved

11

Reserved

4

Reserved

3

26

18

10

2

25

17

9

1

LOCK

24

16

8

0

DFEN

Table 6-2 User Configuration Register 0 (Config0, address 0x0030_0000 accessible through ISP only)

Config0

Bits

[31:23]

[23]

[22:8]

[7]

[6:2]

[1]

[0]

Address = 0x0030_0000

Description

Reserved Reserved for future use

CBODEN Brown Out Detector Enable

If set to ‘0’ the Brown Out Detector (BOD) will be enabled after power up. It will be configured at lowest voltage (2.1V) and if brown out condition detected will trigger the NMI interrupt to processor.

0= Enable

1=Disable brown out detect after power on

Reserved

CBS

Reserved

LOCK

DFENB

Reserved for future use

Configuration Boot Selection

0 = Chip will boot from LDROM

1 = Chip will boot from APROM

Reserved for future use

Security Lock

0 = Flash data is locked

1 = Flash data is not locked.

When flash data is locked, only device ID, Config0 and Config1 can be read by ICP through serial debug interface. Other data is locked as 0xFFFFFFFF. Once locked no SWD debugging is possible. ISP can read data anywhere regardless of LOCK bit value.

Data Flash Enable Bar

When data flash is enabled, flash memory is partitioned between APROM and

DATAF memory depending on the setting of data flash base address in Config1 register. If set to ‘0’ then no DATAF partition exists.

0 = Enable data flash

1 = Disable data flash

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Revision 2.4


Config1 (Address = 0x0030_0004)

31 30 29 28 27 26 25 24

Reserved

23 22 21 20 19 18 17 16

Reserved DFBA

15 14 13 12 11 10 9 8

DFBA

7 6 5 4 3 2 1 0

DFBA

Table 6-3 User Configuration Register 1 (Config1, address 0x0030_0004 accessible through ISP only)

Config1

Bits

[31:20]

[19:0]

Address = 0x0030_0004

Description

Reserved

DFBA

Reserved

It is mandatory to program 0x00 to these Reserved bits

Data Flash Base Address

This pointer sets the address for the start of data flash memory. Address must be on a 512 Byte page boundary so DFBA[8:0] must be 0x000.

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Revision 2.4


6.8 In-System Programming (ISP)

The program and data flash memory support both in hardware In-Circuit Programming (ICP) and firmware based In-System programming (ISP). Hardware ICP programming mode uses the Serial-Wire

Debug (SWD) port to program chip. Dedicated ICE Debug hardware or ICP gang-writers are available to reduce programming and manufacturing costs. For firmware updates in the field, the ISD91200 provides an ISP mode allowing a device to be reprogrammed under software control.

ISP is performed without removing the device from the system. Various interfaces enable LDROM firmware to fetch new program code from an external source. A common method to perform ISP would be via a UART controlled by firmware in LDROM. In this scenario, a PC could transfer new APROM code through a serial port. The LDROM firmware receives it and re-programs APROM through ISP commands. An alternative might be to fetch new firmware from an attached SD-Card via the SPI interface.

6.8.1 ISP Procedure

The ISD91200 will boot from APROM or LDROM from a power-on reset as defined by user configuration bit CBS. If user desires to update application program in APROM, the FMC_ISPCTL.BS can be set to ’1’ and a software reset issued. This will cause the chip to boot from LDROM. An example flow diagram of the ISP sequence is shown in Figure 6-5.

The FMC_ISPCTL register is a protected register, user must first follow the unlock sequence to gain access. This procedure is to protect the flash memory from unintentional access.

To enable ISP functionality software must first ensure the ISP clock (CLK_AHBCLK.ISPCKEN) is present then set the FMC_ISPCTL.ISPEN bit.

Several error conditions are checked after software writes the ISPTRIG register. If an error condition occurs, ISP operation is not started and the ISP fail flag (FMC_ISPCTL.ISPFF) will be set instead. The

ISPFF flag will remain set until it is cleared by software. Subsequent ISP procedure can be started even if ISPFF is set. It is recommended that software check ISPFF bit and clear it after each ISP operation if set.

When ISPTRIG register is set, the CoretxM0 CPU will wait for ISP operation to finish, during this period; peripherals operate as usual. If any interrupt requests occur, CPU will not service them until ISP operation finishes. As the ISP functions affect the operation of the flash memory M0 instruction pipeline should be flushed with an ISB (Instruction Synchronization Barrier) instruction after the ISP is triggered.

CPU writes ISPTRIG

HCLK

HREADY ss ss

ISP operation

CPU is halted but other peripherials keep working

Figure 6-4 ISP Operation Timing

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Revision 2.4


Power

On

A

CBS = 1 ?

YES

C

Fetch code from

APROM

NO

Fetch code from

LDROM

Enable ISPEN

Write

ISPADR/ ISPCMD/

ISPDAT

Update LD-ROM or write DataFlash

Execute ISP?

Set ISPTRIG = 1

End of Flash Operation

A A

(Read ISPDAT)

Check ISPFF = 1?

B B

Clear ISPEN and return to main program

Clear BS to 0 and set

SWRST = 1 to reboot in

APROM

End of ISP operation

?

YES

NO

C B

Figure 6-5 Boot Sequence and ISP Procedure

The ISP command set is shown in Table 6-4. Three registers determine the action of a command:

FMC_ISPCMD is the command register and accepts commands for reading ID registers and read/write/erase of flash memory. The FMC_ISPADDR is the address register where the flash memory address for access is written. FMC_ISPDAT is the data register that input data is written to and return data read from. An ISP command is executed by setting FMC_ISPCMD, FMC_ISPDAT and

FMC_ISPADDR then writing to the trigger register ISPTRIG.

Table 6-4 ISP Command Set

ISP Mode

Standby

FMC_ISPCMD

CMD[5:0]

0x3x

FMC_ISPADDR

A21 x

A20 x

A[19:0] x

FMC_ISPDAT

D[31:0] x

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Revision 2.4

Read Company ID

Read Device ID

FLASH Page Erase

FLASH Program

FLASH Read

CONFIG Page Erase

CONFIG Program

CONFIG Read

0x0B

0x0C

0x22

0x21

0x00

0x22

0x21

0x00


0

0

1

1

1 x x

0

1

1 x x x

0x00000

A[20] A[19:0]

Returns 0x0000_00DA x

A[20] A[19:0]

A[20] A[19:0]

1 A[19:0]

A[19:0]

A[19:0]

Data input

Data output x

Data input

Data output

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Revision 2.4


6.9 Register Map



FMC Base Address:

FMC_BA=0x5000_C000

FMC_ISPCTL FMC_BA+0x00

FMC_ISPADDR FMC_BA+0x04

R/W ISP Control Register

R/W ISP Address Register

FMC_ISPDAT

FMC_ISPCMD

FMC_ISPTRG

FMC_DFBA

FMC_BA+0x08

FMC_BA+0x0C

FMC_BA+0x10

FMC_BA+0x14

R/W ISP Data Register

R/W ISP Command Register

R/W ISP Trigger Control Register

R Data Flash Base Address

Reset Value

0x0002_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0xXXXX_XXXX

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Revision 2.4


6.10 Register Description

ISP Control Register (FMC_ISPCTL)

The FMC_ISPCTL register is a protected register, user must first follow the unlock sequence to gain access.

Register

FMC_ISPCTL

31

Offset

FMC_BA+0x00

30 29

R/W Description

R/W ISP Control Register

28 27 26 25

Reset Value

0x0002_0000

24

Reserved

23

15

Reserved

22

14

21

CACHEDIS

13

20 19 18

Reserved

10

17

9

16

8

7

Reserved

6

ISPFF

5

LDUEN

12 11

Reserved

4

CFGUEN

3

APUWEN

2

Reserved

1

BS

0

ISPEN

Table 6-6 ISP Control Register (FMC_ISPCTL, address 0x5000_C000)

Bits

[31:22]

Description

Reserved

[21]

[18:8]

[6]

[5]

[4]

[3]

CACHEDIS

Reserved

ISPFF

LDUEN

CFGUEN

APUWEN

Reserved.

Cache Disable

When set to 1, caching of flash memory reads is disabled.

Reserved.

ISP Fail Flag

This bit is set by hardware when a triggered ISP meets any of the following conditions:

(1) APROM writes to itself.

(2) LDROM writes to itself.

(3) Destination address is illegal, such as over an available range.

Write 1 to clear.

LDROM Update Enable

LDROM update enable bit.

0 = LDROM cannot be updated.

1 = LDROM can be updated when the MCU runs in APROM.

CONFIG Update Enable

0 = Disable.

1 = Enable.

When enabled, ISP functions can access the CONFIG address space and modify device configuration area.

APU Write Enable

1 = APROM write to itself.

0 = APROM can’t write itself. ISPFF with “1”

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Revision 2.4

[2]

[1]

[0]

Reserved

BS

ISPEN


Reserved.

Boot Select

0 = APROM.

1 = LDROM.

Modify this bit to select which ROM next boot is to occur. This bit also functions as

MCU boot status flag, which can be used to check where MCU booted from. This bit is initialized after power-on reset with the inverse of CBS in Config0; It is not reset for any other reset event.

ISP Enable

0 = Disable ISP function.

1 = Enable ISP function.

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Revision 2.4


ISP Address Register (FMC_ISPADDR)


R/W ISP Address Register FMC_ISPADDR FMC_BA+0x04

31 30 29 28 27

ISPADDR

23 22 21 20 19

ISPADDR

15 14 13 12 11

ISPADDR

7 6 5 4 3

ISPADDR

26

18

10

2

25

17

9

1

Table 6-7 ISP Address Register (FMC_ISPADDR, address 0x5000_C004)

Reset Value

0x0000_0000

24

16

8

0


[31:0] ISPADDR

ISP Address Register

This is the memory address register that a subsequent ISP command will access.

ISP operation are carried out on 32bit words only, consequently ISPADDR [1:0] must be 00b for correct ISP operation.

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Revision 2.4


ISP Data Register (FMC_ISPDAT)


FMC_BA+0x08 R/W ISP Data Register FMC_ISPDAT

31 30 29 28 27

ISPDAT

23 22 21 20 19

ISPDAT

15 14 13 12 11

ISPDAT

7 6 5 4 3

ISPDAT

26

18

10

2

25

17

9

1

Table 6-8 ISP Data Register (FMC_ISPDAT, address 0x5000_C008)

Reset Value

0x0000_0000

24

16

8

0


[31:0] ISPDAT

ISP Data Register

Write data to this register before an ISP program operation.

Read data from this register after an ISP read operation

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Revision 2.4


ISP Command (FMC_ISPCMD)


R/W ISP Command Register FMC_ISPCMD FMC_BA+0x0C

31 30 29 28 27

Reserved

23 22 21 20 19

Reserved

15 14 13 12 11

Reserved

7 6 5 4 3

Reserved CMD

26

18

10

2

25

17

9

1

Table 6-9 ISP Data Register (FMC_ISPCMD, address 0x5000_C00C)

Reset Value

0x0000_0000

24

16

8

0

Bits

[31:6]

Description

Reserved

[5:0] CMD

Reserved.

ISP Command

Operation Mode : CMD

Standby : 0x3X

Read : 0x00

Program : 0x21

Page Erase : 0x22

Read CID : 0x0B

Read DID : 0x0C

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Revision 2.4


ISP Trigger Control Register (FMC_ISPTRG)

The FMC_ISPTRG register is a protected register, user must first follow the unlock sequence to gain access.

Register Offset

FMC_BA+0x10

R/W Description

R/W ISP Trigger Control Register

Reset Value

0x0000_0000 FMC_ISPTRG

31 30 29 26 25 24

23

15

7

22

14

6

21

13

5

28 27

Reserved

20 19

Reserved

12 11

Reserved

4

Reserved

3

18

10

2

17

9

1

16

8

0

ISPGO

Table 6-10 ISP Trigger Control Register (FMC_ISPTRG, address 0x5000_C010)

Bits

[31:1]

Description

Reserved

[0] ISPGO

Reserved.

ISP Start Trigger

Write 1 to start ISP operation. This will be cleared to 0 by hardware automatically when ISP operation is finished.

0 = ISP operation is finished.

1 = ISP is on going.

After triggering an ISP function M0 instruction pipeline should be flushed with a ISB instruction to guarantee data integrity.

This is a protected register, user must first follow the unlock sequence to gain access.

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Revision 2.4


Data Flash Base Address Register (FMC_DFBA)


FMC_DFBA

31

FMC_BA+0x14

30 29

R Data Flash Base Address

28 27 26 25

DFBA

23 22 21 20 19 18 17

DFBA

15 14 13 12 11 10 9

DFBA

7 6 5 4 3 2 1

DFBA

Table 6-11 Data Flash Base Address Register (FMC_DFBA, address 0x5000_C014)


Reset Value

0xXXXX_XXXX

24

16

8

0

[31:0] DFBA

Data Flash Base Address

This register reports the data flash starting address. It is a read only register.

Data flash size is defined by user configuration; register content is loaded from Config1 when chip is reset.

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Revision 2.4


7 ANALOG SIGNAL PATH BLOCKS

This section describes the functional blocks that perform analog signal functions on the ISD91200. This includes the ADC, DPWM Speaker Driver, PGA Gain Amplifier, Automatic Gain Control and a variety of auxiliary analog functional blocks.

7.1 Sigma- Delta Analog-to-Digital Converter (SDADC)

7.1.1 Functional Description

The ISD91200 includes a Sigma-Delta Audio Analog-to-Digital converter. The converter can run at sampling rates up to 6.144MHz while a configurable decimation filter allows oversampling ratios of

64/128/192 and 384. The decimation input is 6.144 MHz oversample rate. The SINC filter and low pass filter can down sample up to 64000. Low pass filter is IIR filter implemented by BIQ filter.

7.1.2 Features

 Programmable volume control from -108dB to36dB in 0.5dB steps.

 Support Automatic Level Controller (ALC) function.

 Configurable down-sampling to support sample rate 64KHz.

 Programmable Bi-quad filter to support multiple sample rate 64KHz.

 DMA support for minimal CPU intervention.


Figure 7-1 ADC Signal Path Block Diagram

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Revision 2.4


7.1.4 Operation

The SDADC is an audio Sigma-Delta converter that operates by oversampling the analog input at low resolution and decimating the result by an over-sampling ratio to obtain a high resolution output which is pushed into the FIFO. The ultimate data rate is determined by the converter clock frequency, and the oversampling ratio.

The audio signal stream generated by the SDADC is most conveniently handled by PDMA which can load data into a streaming audio buffer for further processing. Alternatively an interrupt driven approach can be used to monitor the FIFO.

7.1.4.1 SDADC Clock Generator

SDADCSEL (CLK_CLKSEL1[3:2])

SDADCCKEN(CLK_APBCLK1[28])

HCLK

1/(SDADCDIV + 1)

SDADCDIV(CLK_CLKDIV0[23:16])

CLK12M

0

1

MCLK

48KHz

32KHz

Fs

Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.

7.1.4.2 Determining Sample Rate

The maximum clock rate of the Sigma-Delta Converter is 6.144MHz.

Sample rate is given by:

Fs = MCLK ÷ CLKDIV ÷ DSR

Down Sample Ratio(Real DSRate) = SDADC_CTL.DSRATE* BIQ_CTL.SDADCWNSR

Note :MCLK / SD_CLK >= 4

: DSR = SDADC_CTL.DSRATE*BIQ_CTL.SDADCWNSR

Table 7-1 Sample Rates for MCLK 24.576MHz

DSR

128

64

192

128

SD_CLK

6.144MHz

3.072MHz

6.144MHz

4.096MHz

CLKDIV

4

4

8

8

8

4

6

SDADC_CTL.DSRATE

64

64

64

32

64

32

32

16

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BIQ_CTL.SDADCWNSR

1

3

2

4

2

4

2

4


Revision 2.4


16KHz

Fs

48KHz

32KHz

8KHz

16KHz

64

384

256

2.048MHz

6.166MHz

4.096MHz

12

4

6

128

64

2.048MHz

1.024MHz

12

24

8KHz 384 3.072MHz

2.048MHz

8

12 256

128 1.024MHz 24

64 512KHz 48

Table 7-2 Sample Rates for MCLK 12.288MHz

DSR

64

64

128

64

SD_CLK

3.072MHz

2.048MHz

2.048MHz

1.024MHz

3.072MHz 384

256 2.048MHz

CLKDIV

4

6

6

12

4

6

64

32

32

16

64

64

64

64

32

32

16

64

32

16

64

64

64

SDADC_CTL.DSRATE

32

16

64

32

16

64

64

32

32

16

64

64

64

- 373 -

BIQ_CTL.SDADCWNSR

2

2

4

4

1

1

2

4

2

4

1

6

4


Revision 2.4

2

4

1

2

4

6

4

2

4

1

2

4

6

4

2

4

1


128 1.024MHz

64 512KHz

Table 7-3 Sample Rates for SINC

12

24

64

32

32

16

64

2

4

1

2

4

CHIP Decimator Output

Sample Rate

384Hz

384Hz

384Hz

384Hz

3072Hz

Low pass filter BIQ BS sample rate Software down sample

( get one out of 40/20/10/5/8 )

16000 (

BSRATE

=3) 10 th

order, 5 stage low_decm384_3.txt

16000 (

BSRATE

=3) 10 th


16000 (

BSRATE

=3) 10 th


9.6Hz

19.2Hz

38.4Hz

16000 (

BSRATE

=3) 10 th


76.8Hz

2000 (BS_OSR=0) 10 th


384Hz

384/9.6 = 40

384/19.2 = 20

384/38.4 =10

384/76.8 = 5

3072/384=8

Table 7-4 Sample Rates and cut-off frequency for BIQ

Sample rate (SPS) -3dB Cut-off frequency(Hz) FIFO out sample rate(Hz)

9.6

19.2

38.4

76.8

3

6

12

24

384

384

384

384

384 120 3072

Table 7-5 Low pass filter coefficient table low_decm384_3 low_decm384_6 low_decm384_12 low_decm384_24 low_decm3072_120

00ae7;//0.042480 00ae8;//0.042599 00b41;//0.043957 00d0e;//0.050989 044f2;//0.268669

7ea6d;//-0.084068 7eb09;//-0.081892 7ecce;//-0.074978 7f2c8;//-0.051643 07587;//0.457977

00ae7;//0.042480 00ae8;//0.042599 00b41;//0.043957 00d0e;//0.050989 044f2;//0.268669

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Revision 2.4


10000;//1.000000 10000;//1.000000 10000;//1.000000 10000;//1.000000 10000;//1.000000

6061e;//-1.976105 60c6b;//-1.951500 61b10;//-1.894287 63ef0;//-1.754158 06151;//0.380135

0fa45;//0.977615 0f505;//0.957108 0ea8d;//0.916214 0d6e9;//0.839493 0a46c;//0.642273

00070;//0.001709 0008a;//0.002111 000f5;//0.003744 00298;//0.010124 062df;//0.385269

7ff49;//-0.002789 7ff84;//-0.001886 00068;//0.001579 003c5;//0.014725 0c107;//0.752182

00070;//0.001709 0008a;//0.002111 000f5;//0.003744 00298;//0.010124 062df;//0.385269

10000;//1.000000 10000;//1.000000 10000;//1.000000 10000;//1.000000 10000;//1.000000

608e1;//-1.965317 6111b;//-1.933189 621d5;//-1.867851 642ee;//-1.738556 79038;//-0.436653

0f738;//0.965691 0ef40;//0.934570 0df8a;//0.873199 0c25a;//0.759186 03583;//0.209030

0348c;//0.204758 0349e;//0.205538 035ad;//0.209667 03a5c;//0.227968 06036;//0.374916

79781;//-0.407187 798fe;//-0.402370 79d7f;//-0.384785 7ae6f;//-0.318617 094cb;//0.579803

0348c;//0.204758 0349e;//0.205538 035ad;//0.209667 03a5c;//0.227968 06036;//0.374916

10000;//1.000000 10000;//1.000000 10000;//1.000000 10000;//1.000000 10000;//1.000000

601cf;//-1.992943 604a8;//-1.981812 60e05;//-1.945244 62ec0;//-1.817383 0cae6;//0.792564

0fed7;//0.995461 0fdc2;//0.991234 0fb8f;//0.982643 0f74f;//0.966042 0eff5;//0.937325

004b1;//0.018282 004c5;//0.018627 0053f;//0.020485 00754;//0.028631 08ead;//0.555977

7f6d9;//-0.035671 7f74f;//-0.033953 7f8ce;//-0.028109 7fe14;//-0.007509 105f2;//1.020729

004b1;//0.018282 004c5;//0.018627 0053f;//0.020485 00754;//0.028631 08ead;//0.555977

10000;//1.000000 10000;//1.000000 10000;//1.000000 10000;//1.000000 10000;//1.000000

607db;//-1.969315 60f63;//-1.939896 61f6d;//-1.877251 641d4;//-1.742859 7fde9;//-0.008163

0f85b;//0.970139 0f165;//0.942947 0e39e;//0.889130 0c9f0;//0.788818 06e5b;//0.431068

02826;//0.156454 0281d;//0.156698 028df;//0.159651 02cdd;//0.175240 07ade;//0.478783

7b040;//-0.310770 7b1d0;//-0.305422 7b64d;//-0.287893 7c5d7;//-0.227188 07ade;//0.478783

02826;//0.156454 0281d;//0.156698 028df;//0.159651 02cdd;//0.175240 00000;//0.000000

10000;//1.000000 10000;//1.000000 10000;//1.000000 10000;//1.000000 10000;//1.000000

60408;//-1.984261 608be;//-1.965858 61539;//-1.917107 63912;//-1.777069 7ada2;//-0.321747

0fc85;//0.986404 0f94e;//0.973846 0f2d7;//0.948586 0e691;//0.900642 00000;//0.000000

7.1.4.3 Configuring Analog Path

To operate the SDADC the entire analog path from analog input to SDADC needs to be configured for correct operation without BIQ and SDADC Volume control:

•

Selecting and powering up VMID reference: power on VMID generator, power on both low and high value resistor.

•

Wait 7 RC time, then turn off lower value resistor, and then wait 1or 2 RC time.

•

Enable SDADC clock source (CLK_APBCLK0.SDADCCKEN, CLKSEL1.SDADCSEL).

•

Reset SDADC block. (SYS_IPRST1.SDADCRST).

•

Enable SDADC power(SDCHOP.PD = 0)

•

Power up FEPGA and MICBIAS.

•

Setup sample rate based on current MCLK(in Table 7-1) frequency and Set SDADC_CLKDIV.

- 375 -


Revision 2.4


•

Setup FIFO data width SDADC_CTL.FIFOBITS

•

Setup down ampling rate, set SDADC_CTL.RATESEL=0 then set SDADC_CTL.DSRATE &

BIQ_CTL.SDADCWNSR for expected DSR & sampling rate(refer to Table 7-1)

•

Setup PDMA channel to receive data from SDADC.

•

Enable PDMA request.

•

Enable SDADC conversion(SDADC_EN.SDADCEN).

To operate the SDADC

the entire analog path from analog input to SDADC needs to be configured for correct operation with BIQ and SDADC Volume control:

•

Selecting and powering up VMID reference: power on VMID generator, power on both low and high value resistor.

•

Wait 7 RC time, then turn off lower value resistor, and then wait 1or 2 RC time.

•

Enable SDADC clock source (CLK_APBCLK0.SDADCCKEN, CLKSEL1.SDADCSEL).

•

Reset SDADC block. (SYS_IPRST1.EADCRST).

•

Enable SDADC power (SDCHOP.SDADC_PD = 0)

•

Power up FEPGA and MICBIAS.

•

Setup sample rate based on current MCLK frequency and Set SDADC_CLKDIV

•

Setup FIFO data width SDADC_CTL.FIFOBITS

•

Setup down ampling rate, set SDADC_CTL.RATESEL=0 then set SDADC_CTL.DSRATE &

BIQ_CTL.SDADCWNSR for expected DSR & sampling rate(refer to Table 7-1).

•

Enable BIQ clock source (CLK_APBCLK0.BIQALCKEN).

•

Enable BIQ on SDADC path (BIQ_CTL.DLCOEFF, BIQ_CTRL.BIQEN,

BIQ_CTL.PATHSEL=0, BIQ_CTRL.STAGE, BIQ_CTRL.HPFON).

•

Set BIQ coefficient(BIQ_COEFF)

•

Setup SDADC volume control (VOLCTRL_EN.SDADCVOLEN,VOLCTRL_ADCVAL).

(note: setup BIQ_CTL.DLCOEFF =1 and BIQ enable BIQ_CTL.BIQEN =1 for BIQ operation).

•

Setup PDMA channel to receive data from SDADC.

•

Enable PDMA request.

•

Enable SDADC conversion(SDADC_EN.SDADCEN).

7.1.4.4 Interrupt Sources

The SDADC can be configured to generate an interrupt when the data level in the FIFO exceeds a defined threshold. The interrupt condition is only cleared by disabling the interrupt or reading values from the FIFO. In addition two comparators can monitor the SDADC FIFO output to generate interrupts when set levels are exceeded.

FIFOIELEV

INT.IE

SDADC_CMPR0.CMPF

SDADC_CMPR0.CMPIE

SDADC_CMPR1.CMPF

SDADC_CMPR1.CMPIE

ADC_IRQ

Figure 7-2 SDADC Controller Interrupt

- 376 -


Revision 2.4


7.1.4.5 Peripheral DMA Request

Normal use of the SDADC is with PDMA. In this mode ADC requests PDMA service whenever data is in FIFO. PDMA channel will copy this data to a buffer and alert the CPU when buffer is full. In this way an entire buffer of data can be collected without any CPU intervention.

7.1.5 ADC Register Map


Register Offset

SDADC Base Address:

SDADC_BA = 0x400E_0000

SDADC_DAT

R/W

SDADC_BA+0x00 R

Description

SD ADC FIFO Data Read Register

Reset Value

SDADC_EN SDADC_BA+0x04 R/W SD ADC Enable Register

SDADC_CLKDIV SDADC_BA+0x08 R/W SD ADC Clock Divider Register

SDADC_CTL SDADC_BA+0x0C R/W SD ADC Control Register

SDADC_FIFOSTS SDADC_BA+0x10 R/W SD ADC FIFO Status Register

SDADC_PDMACTL SDADC_BA+0x14 R/W SD ADC PDMA Control Register

SDADC_CMPR0 SDADC_BA+0x18 R/W SD ADC Comparator 0 Control Register

SDADC_CMPR1 SDADC_BA+0x1C R/W SD ADC Comparator 1 Control Register

SDADC_SDCHOP SDADC_BA+0x20 R/W Sigma Delta Analog Block Control Register

0xxxxx_xxxx

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0002

0x0000_0000

0x0000_0000

0x0000_0000

0x001c_1021

- 377 -


Revision 2.4


7.1.6 ADC Register Description

SD ADC FIFO Data Register(SDADC_DAT)


SDADC_BA+0x00 R SD ADC FIFO Data Read Register SDADC_DAT

31 30 29

23

15

7

22

14

6

21

13

5

28 27

Reserved

20 19

Reserved

12 11

RESULT[15:8]

4

RESULT[7:0]

3

26

18

10

2


[15:0] RESULT

25

17

9

1

Reset Value

0xxxxx_xxxx

24

16

8

0

Delta-Sigma ADC DATA FIFO Read

A read of this register will read data from the audio FIFO and increment the read pointer. A read past empty will repeat the last data. Can be used with

SDADC_FIFOSTS.THIF to determine if valid data is present in FIFO.

- 378 -


Revision 2.4


SD ADC Enable Register(SDADC_EN)


SDADC_BA+0x04 R/W SD ADC Enable Register SDADC_EN

31 30 29 28 27

Reserved

23 22 21 20 19

Reserved

15 14 13 12 11

Reserved

7 6 5

Reserved

4 3

Bits

[31:3]

[2]

Description

Reserved

Reserved

[1]

[0]

DINEDGE

SDADCEN

26

18

10

2

Reserved

25

17

9

1

DINEDGE

Reset Value

0x0000_0000

0

SDADCEN

Reserved.

Reserved

ADC data input clock edge selection (for DMIC only, default 0 for AMIC)

1 = ADC clock positive edge latch

0 = ADC clock negetive edge latch

SDADC Enable

1 = ADC Conversion enabled.

0 = Conversion stopped and ADC is reset including FIFO pointers.

24

16

8

- 379 -


Revision 2.4


SD ADC Clock Divider Register (SDADC_CLKDIV)


SDADC_CLKDIV SDADC_BA+0x08 R/W SD ADC Clock Divider Register

31

23

15

7

30

22

14

6

29

21

13

5

28 27

Reserved

20 19

Reserved

12 11

Reserved

4

CLKDIV[7:0]

3

Bits

[31:8]

Description

Reserved

[7:0] CLKDIV

26

18

10

2

25

17

9

1

Reset Value

0x0000_0000

24

16

8

0

Reserved.

SD_CLK Clock Divider

SDADC internal clock divider. CLKDIV should be set to give a SD_CLK frequency in the range of 1.024-6.144MHz. (Refer to 7.1.4.2.)

CLKDIV must be greater than and equal 2.

CLKDIV = SD_CLK/Sample Rate/Down Sample Rate

- 380 -


Revision 2.4


SD ADC Control Register (SDADC_CTL)


SDADC_BA+0x0C R/W SD ADC Control Register SDADC_CTL

31 30 29

23

15

7

THIE

22 21

14 13

6

Reserved

5

FIFOTH

Reset Value

0x0000_0000

28 27 26 25 24

Reserved

20 19

12

4

Reserved

11

RATESEL

3

FIFOBITS

18

10

2

Reserved

17

9

1

DSRATE

16

8

DMICEN

0

Bits

[31:12]

[11]

[10:9]

Description

Reserved

RATESEL

Reserved

[8]

[7]

[6:4]

[3:2]

[1:0]

DMICEN

FIFOTHIE

FIFOTH

FIFOBITS

DSRATE

Reserved.

Should be 0

Reserved

Digital MIC Enable

1 = turn digital MIC function input from GPIO.

0 = keep SDADC function.

FIFO Threshold Interrupt Enable

0 = disable interrupt whenever FIFO level exceeds that set in FIFOTH.

1 = enable interrupt whenever FIFO level exceeds that set in FIFOTH.

FIFO Threshold:

Determines at what level the ADC FIFO will generate a interrupt.

Interrupt will be generated when number of words present in ADC FIFO is >

FIFOTH.

FIFO Data Bits Selection

0 = 32 bits

1 = 16 bits

2 = 8 bits

3 = 24 bits

Down Sampling Ratio

0 = reserved

1 = down sample X 16



- 381 -


Revision 2.4


SD ADC FIFO Status Register(SDADC_FIFOSTS)


SDADC_FIFOSTS SDADC_BA+0x10 R/W SD ADC FIFO Status Register

31

BISTEN

23

15

7

30

22

14

6

POINTER

29

21

13

5

28

20

27

Reserved

19

Reserved

12 11

4

Reserved

3

Reserved


[31]

[30:8]

[7:4]

[3]

[2]

[1]

[0]

BISTEN

Reserved

POINTER

Reserved

THIF

EMPTY

FULL

26

18

10

2

THIF

25

17

9

1

EMPTY

Reset Value

0x0000_0002

24

16

8

0

FULL

BIST Enable

1 = Enable SDADC FIFO BIST testing SDADC FIFO can be testing by Cortex-M0

0 = Disable SDADC FIFO BIST testing

Internal use

Reserved.

SDADC FIFO Pointer (Read Only)

The FULL bit and POINTER[3:0] indicates the field that the valid data count within the SDADC FIFO buffer.

The Maximum value shown in POINTER is 15. When the using level of SDADC

FIFO Buffer equal to 16, The FULL bit is set to 1.

Reserved.

ADC FIFO Threshold Interrupt Status (Read Only)

1 = The valid data count within the SDADC FIFO buffer is larger than or equal the setting value of FIFOTH.

0 = The valid data count within the transmit FIFO buffer is less than to the setting value of FIFOTH.

FIFO Empty

1= FIFO is empty.

0= FIFO is not empty.

FIFO Full

1 = FIFO is full.

0 = FIFO is not full.

- 382 -


Revision 2.4


SD ADC PDMA Control Register(SDADC_PDMACTL)


SDADC_PDMACTL SDADC_BA+0x14 R/W SD ADC PDMA Control Register

31

23

15

7

30

22

14

6

29

21

13

5

28

RESVERVED

27

20

RESVERVED

19

12 11

4

RESVERVED

3

RESVERVED

Bits

[31:1]

Description

Reserved

[0] PDMAEN

Reserved.

Enable SDADC PDMA Receive Channel

1 = Enable SDADC PDMA.

0 = Disable SDADC PDMA.

26

18

10

2

Reset Value

0x0000_0000

9

1

25

17

24

16

8

0

PDMAEN

- 383 -


Revision 2.4


A/D Compare Register 0 ( SDADC_CMPR0 )


SDADC_CMPR0 SDADC_BA+0x18 R/W SD ADC Comparator 0 Control Register

31

CMPOEN

23

15

7

30

22

14

29

21

13

6 5

CMPMATCNT

28

20

CMPD

27

CMPD

19

12 11

CMPD

4 3

CMPF

26

18

10

2

CMPCOND


[31]

[30:8]

[7:4]

[3]

[2]

[1]

[0]

CMPOEN

CMPD

CMPMATCNT

CMPF

CMPCOND

CMPIE

Reserved

25

17

9

1

CMPIE

Reset Value

0x0000_0000

24

16

8

0

Reserved

Compare Match output FIFO zero

1 = compare match then FIFO out zero

0 = FIFO data keep original one.

Comparison Data

23 bit value to compare to FIFO output word.

Compare Match Count

When the A/D FIFO result matches the compare condition defined by CMPCOND, the internal match counter will increase by 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.

Compare Flag

When the conversion result meets condition in CMPCOND and CMPMATCNT this bit is set to 1. It is cleared by writing 1 to self.

Compare Condition

1= Set the compare condition that result is greater or equal to CMPD

0= Set the compare condition that result is less than CMPD

Note: When the internal counter reaches the value (CMPMATCNT +1), the CMPF bit will be set.

Compare Interrupt Enable

1 = Enable compare function interrupt.

0 = Disable compare function interrupt.

If the compare function is enabled and the compare condition matches the setting of

CMPCOND and CMPMATCNT, CMPF bit will be asserted, if CMPIE is set to 1, a compare interrupt request is generated.

Reserved.

- 384 -


Revision 2.4


A/D Compare Register 1 ( SDADC_CMPR1 )


SDADC_CMPR1 SDADC_BA+0x1C R/W SD ADC Comparator 1 Control Register

31

CMPOEN

23

15

7

30

22

14

29

21

13

6 5

CMPMATCNT

28

20

CMPD

27

CMPD

19

12 11

CMPD

4 3

CMPF

26

18

10

2

CMPCOND


[31]

[30:8]

[7:4]

[3]

[2]

[1]

[0]

CMPOEN

CMPD

CMPMATCNT

CMPF

CMPCOND

CMPIE

Reserved

25

17

9

1

CMPIE

Reset Value

0x0000_0000

24

16

8

0

Reserved

Compare Match output FIFO zero

1 = compare match then FIFO out zero

0 = FIFO data keep original one.

Comparison Data

23 bit value to compare to FIFO output word.


When the A/D FIFO result matches the compare condition defined by CMPCOND, the internal match counter will increase by 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.

Compare Flag

When the conversion result meets condition in CMPCOND and CMPMATCNT this bit is set to 1. It is cleared by writing 1 to self.


1= Set the compare condition that result is greater or equal to CMPD

0= Set the compare condition that result is less than CMPD

Note: When the internal counter reaches the value (CMPMATCNT +1), the CMPF bit will be set.

Compare Interrupt Enable

1 = Enable compare function interrupt.

0 = Disable compare function interrupt.

If the compare function is enabled and the compare condition matches the setting of

CMPCOND and CMPMATCNT, CMPF bit will be asserted, if CMPIE is set to 1, a compare interrupt request is generated.

Reserved.

- 385 -


Revision 2.4


SD Analog Block Control Register(SDADC_SDCHOP)


SDADC_SDCHOP SDADC_BA+0x20 R/W Sigma Delta Analog Block Control Register

Reset Value

0x001c_1021

Bits

31 30

AUDIOPATHSEL

23

Reserved

15

22

14

29

Reserved

PGAADCDC

21

13

28

Reserved

20

PGAADCUP

12

PGACMLCK PGADISCH PGAGAIN PGAIBLOOP

7 6 5 4

PGAMODE PGAMUTE PGAPU

27

Reserved

19

PGABYPS

11

3

Reserved

26

Reserved

18

PGACLASSA

10

PGAIBCTR

2

BIAS

25

Reserved

24

Reserved

17 16

PGACMLCKADJ

9 8

1

PGAMODE

0

PD

Description

[31:30]

[29:23]

[22:21]

[20]

[19]

[18]

AUDIOPATHSEL

Reserved

PGA_ADCDC

PGA_HZMODE

PGA_TRIMOBC

PGA_CLASSA

Audio Path Selection, Connect SDADC input to

00 = PGA (default)

01 = MICN and MICP pins (bypass PGA)

10 = Reserved

11 = Reserved

Reserved

Action takes effect when PGA_DISCH=1

Bit[21]: ACDC_CTRL[0] charges INP to VREF

Bit[22]: ACDC_CTRL[1] charges INN to VREF

00=Default

Select input impedance

0 = 12k Ohm input impedance

1 = 500k Ohm input impedance (default)

Trim current in output driver

0=disable

1=enable (default)

Enable Class A mode of operation

0 = Class AB

1 = Class A (default)

- 386 -


Revision 2.4


[17:16]

[15]

[14]

[13]

[12]

[11:9]

[8:6]

[5]

[4]

[3]

[2:1]

[0]

PGA_CMLCKADJ

PGA_CMLCK

PGA_DISCH

PGA_GAIN

PGA_IBLOOP

PGA_IBCTR

PGA_MODE

PGA_MUTE

PGA_PU

Reserved

BIAS

PD

Common mode Threshold lock adjust. Action takes effect when

PGA_CMLCK=0

00---0.98 (default)

01---0.96

10---1.01

11---1.04 default=00

Common mode Threshold lock adjust enable

0 = Enable

1 = Disable

Charge inputs selected by PGA_ACDC[1:0] to VREF

1 = Enable

0 = Disable

PGA Gain (default=0)

PGA_GAIN

0

1

Trim PGA current

1=default

Trim PGA Current

0=default

PGA_HZMODE=0

0dB

6dB

Each bit has respective function as following.

PGA_MODE[0] = Disable anti-aliasing filter adjust

PGA_MODE [1] = Short the inputs (for calibrarion)

PGA_MODE[2] = Noise reduction enable.

1 = Enable

0 = Disable (default)

Mute control signal

0—disable

1—enable

Power up PGA

0—disable

1—enable

PGA_HZMODE=1

6dB

12dB

Reserved

SDADC Bias Current Selection

00 = 1

01 = 0.75

10 = 0.5

11 = 1.25

SDADC Power Down

0 = SDADC power on

1 = SDADC power off

7.2 Audio Class D Speaker Driver (DPWM)

- 387 -


Revision 2.4


7.2.1 Functional Description

The ISD91200 includes a differential Class D (PWM) speaker driver capable of delivering 0.5W into an

8

Ω load at 5V supply voltage. The driver works by up-sampling and modulating a PCM input to differentially drive the SPK+ and SPK- pins. The speaker driver operates from its own independent supply VCCSPK and VSSSPK. This supply should be well decoupled as peak currents from speaker driver are large.

7.2.2 Features

 Differential Audio PWM Output (DPWM).

 Direct connection of speaker

 0.5

W drive capability into 8Ω load at 5.5V.

 Configurable up-sampling to support sample rates from 8~48kHz.

 Programmable volume control from -108dB to +36dB in 0.5 dB step.

 Programmable biquad filter to support multiple sample rates from 8~48kHz.

 PDMA data channel for streaming of PCM audio data.


Figure 7-3 DPWM Block Diagram

7.2.4 Operation

The DPWM block receives audio data by writing PCM audio to the FIFO. FIFO is accessed through

PDMA for ease of streaming. The audio stream is sampled by a zero-order hold and fed to an upsampling Cascaded Integrator Comb (CIC) filter with an up-sampling ratio of 64. The signal is then modulated and sent to the driver stage through a non-overlap circuit. Master clock rate of the Delta-

Sigma modulator is controlled by DPWM_CLK. This clock can be HCLK/(DPWMDIV+1) or HXT (refer to

CLK_CLKSEL1). Ultimate SNR (Signal-to-Noise Ratio) is determined by the time resolution of the master clock.

- 388 -


Revision 2.4


7.2.4.1 DPWM switch frequecy

HCLK

49.152MHz

7.2.4.2 DPWM Clock Generator

DPWM_CLK=

HCLK/DPWMDIV

24.576MHz

12.288MHz

8.192MHz

6.144MHz

Switch frequency

614.4KHz

307.2KHz

204.8KHz

153.6KHz

HCLK

1/(DPWMDIV + 1)

DPWMDIV (CLK_CLKDIV0[15:12])

CLK12M

0

1

DPWMCKSEL(CLK_CLKSEL1[5:4])

DPWMCKEN(CLK_APBCLK0[13])

DPWM_CLK


7.2.4.3 Determining Sample Rate

The sample rate at which the DPWM block consumes audio data is given by:

Fs = DWPM_CLK ÷ ZOHDIV ÷64 ÷BIQ_CTL.DPWMPUSR

Where HCLK is the master CPU clock rate and DPWM_ZOHDIV is the divider control register. A table of common audio sample rates is provided below.

Table 7-1 DPWM Sample Rates for Various HCLK

DPWM_CLK = 24.576MHz

Fs

(sample rate)

48KHz

32KHz

ZOHDIV (clock divider)

0x40070010

8

4

2

12

6

4

3

BIQ Enable off on on off on on on

BIQ_CTL.DPWMPUSR

1x

2x

4x

1x

2x

3x

4x

DPWM OSR

64

128

256

64

128

192

256

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Revision 2.4


16KHz

8KHz

4

48

24

24

12

6 on off on off on on

6x

1x

2x

1x

2x

4x

64

128

256

384

64

128

12 on 4x 256

8 on 6x 384

7.2.4.4 Configuring Speaker Driver

To operate the speaker driver the following configuration is recommended:

•

Enable DPWM clock source (CLK_APBCLK0.DPWMCKEN, CLK_CLKSEL1.DPWMCKSEL).

•

Reset DPWM IP block. (SYS_IPRST1.DPWMRST)

•

Select sample rate based on current DPWM_CLK frequency.

•

Setup PDMA channel to provide data to DPWM.

•

Enable PDMA Request.

•

Enable Driver.

To operate the speaker driver the following configuration is recommended with BIQ and Volume control.

•

Enable DPWM clock source (APBCLK0.DPWMCKEN, CLKSEL1.DPWMSEL).

•

Reset DPWM IP block. (IPRST1.DPWMRST,IPRST1.BIQ_RST).

•

Enable BIQ clock source (APBCLK0.BIQALCEN).

•

Enable BIQ on DPWM path (BIQ_CTL.PATHSEL, BIQ_CTL.BIQEN,

BIQ_CTL.DPWMPUSR, BIQ_CTL.STAGE, BIQ_CTL.HPFON).

•

Set BIQ coefficient(BIQ_COEFF)

•

Setup DPWM volume control (VOLCTRL_EN.DPWMVOLEN,VOLCTRL_DPWMVAL).

(note: setup BIQ_CTL.DLCOEFF =1 and BIQ enable BIQ_CTL.BIQEN =1 for BIQ operation).

•

Select sample rate based on current DPWM_CLK frequency and set ZOHDIV

•

Setup PDMA channel to provide data to DPWM.

•

Enable PDMA Request.

•

Enable DPWM IP (DPWM_CTL.DPWMEN).


Normal use of the DPWM is with PDMA. In this mode DPWM requests PDMA service whenever there is space in FIFO. PDMA channel will copy data from a streaming buffer to the DPWM and alert the CPU when buffer is empty. In this way an entire buffer of data can be sent to DPWM without any CPU intervention.

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Revision 2.4


7.2.5 DPWM Register Map

R : read only, W : write only, R/W : both read and write.


DPWM Base Address:

DPWM_BA = 0x4007_0000

DPWM_CTL DPWM_BA+0x00

DPWM_STS

DPWM_DMACTL

DPWM_BA+0x04

DPWM_BA+0x08

DPWM_DATA

DPWM_ZOHDIV

DPWM_BA+0x0C

DPWM_BA+0x10

R/W

R

R/W

W

R/W

DPWM Control Register

DPWM DATA FIFO Status Register

DPWM PDMA Control Register

DPWM DATA FIFO Input

DPWM Zero Order Hold Division Register

Reset Value

0x0000_0000

0x0000_0002

0x0000_0000

0x0000_0000

0x0000_0006

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Revision 2.4


7.2.6 DPWM Register Description

DPWM Control Register (DPWM_CTL)


DPWM_CTL DPWM_BA+0x00 R/W DPWM Control Register

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

15 14

RXTH

7 6

DPWMDRVEN DPWMEN

13

5

Reserved

12

4

Reserved

11

RXTHIE

3

10

Reserved

2

DEADTIME Reserved

Bits

[31:16]

Description

Reserved

[15:12]

[11]

[10]

[9:8]

[7]

[6]

[5:4]

[3]

[2]

RXTH

RXTHIE

Reserved

Reserved

DWPMDRVEN

DPWMEN

Reserved

DEADTIME

Reserved

25

17

Reset Value

0x0000_0000

24

16

9 8

Reserved

1

FIFOWIDTH

0

Reserved.

DPWM FIFO Threshold

If the valid data count of the DPWM FIFO buffer is less than or equal to RXTH setting, the RXTHIF bit will set to 1, else the RXTHIF bit will be cleared to 0.

DPWM FIFO Threshold Interrupt

0 = DPWM FIFO threshold interrupt Disabled

1 = DPWM FIFO threshold interrupt Enabled.

Reserved

Reserved

DPWM Driver Enable

0 = Disable DPWM Driver.

1 = Enable DPWM Diver.

DPWM Enable

0 = Disable DPWM.

1 = Enable DPWM

Reserved.

DPWM Driver DEADTIME Control.

Enabling this bit will insert an additional clock cycle deadtime into the switching of

PMOS and NMOS driver transistors.

Reserved.

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Revision 2.4

[1:0] FIFOWIDTH


DPWM FIFO DATA WIDTH SELETION From PDMA

00 = PDMA MSB 24bits PWDATA[31:8]

01 = PDMA 16 bits PWDATA[15:0]

10 = PDMA 8bits PWDATA[7:0]

11 = PDMA 24bits PWDATA[23:0]

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Revision 2.4


DPWM FIFO Status Register (DPWM_STS)


DPWM_BA+0x04 R DPWM DATA FIFO Status Register DPWM_STS

31

BISTEN

23

15

7

30

22

14

6

FIFOPTR

29

21

13

5

28

20

27

Reserved

19

Reserved

12 11

4

Reserved

3

Reserved

26

18

10

2

RXTHIF

25

17

9

1

EMPTY

Reset Value

0x0000_0002

Table 7-2 DPWM FIFO Status Register (DPWM_STS, address 0x4007_0004)

24

16

8

0

FULL


[31]

[30:8]

[7:4]

[3]

[2]

[1]

[0]

BISTEN

Reserved

FIFOPTR

Reserved

RXTHIF

EMPTY

FULL

BIST Enable

0 = disable DPWM FIFO BIST testing.

1 = enable DPWM FIFO BIST testing.

DPWM FIFO can be testing by Cortex-M0

Internal use

Reserved.

DPWM FIFO Pointer (Read Only)

The FULL bit and FIFOPOINTER indicates the field that the valid data count within the DPWM FIFO buffer.

The Maximum value shown in FIFO_POINTER is 15. When the using level of

DPWM FIFO Buffer equal to 16, The FULL bit is set to 1.

Reserved.

DPWM FIFO Threshold Interrupt Status (Read Only)

0 = The valid data count within the DPWM FIFO buffer is larger than the setting value of RXTH.

1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of RXTH.

FIFO Empty

0 = FIFO is not empty.

1 = FIFO is empty.

FIFO Full

0 = FIFO is not full.

1 = FIFO is full.

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Revision 2.4


DPWM PDMA Control Register(DPWM_DMACTL)


DPWM_DMACTL DPWM_BA+0x08 R/W DPWM PDMA Control Register

31

23

15

7

30

22

14

6

29

21

13

5

28 27

Reserved

20 19

Reserved

12 11

Reserved

4

Reserved

3

26

18

10

2

25

17

9

1

Reset Value

0x0000_0000

24

16

8

0

DMAEN

Table 7-3 DPWM PDMA Control Register (DPWM_DMACTL, address 0x4007_0008)

Bits

[31:1]

Description

Reserved

[0] DMAEN

Reserved.

Enable DPWM DMA Interface

0 = Disable PDMA. No requests will be made to PDMA controller.

1 = Enable PDMA. Block will request data from PDMA controller whenever FIFO is not empty.

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Revision 2.4


DPWM FIFO Input (DPWM_DATA)


DPWM_BA+0x0C W DPWM DATA FIFO Input DPWM_DATA

31 30 29 28 27

INDATA

23 22 21 20 19

INDATA

15 14 13 12 11

INDATA

7 6 5 4 3

INDATA

26

18

10

2

25

17

9

1

Table 7-4 DPWM FIFO Input (DPWM_DATA, address 0x4007_000C)

Reset Value

0x0000_0000

24

16

8

0


[31:0] INDATA

DPWM FIFO Audio Data Input

A write to this register pushes data onto the DPWM FIFO and increments the write pointer. This is the address that PDMA writes audio data to.

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Revision 2.4


DPWM ZOH Division (DPWM_ZOHDIV)


DPWM_ZOHDIV DPWM_BA+0x10 R/W DPWM Zero Order Hold Division Register

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15 14 13 12 11 10

Reserved

7 6 5 4 3 2

ZOHDIV

25

17

9

1

Reset Value

0x0000_0006

24

16

8

0

Table 7-5 DPWM Zero Order Hold Division Register (DPWM_ZOHDIV, address 0x4007_0010)

Bits

[31:8]

Description

Reserved

[7:0] ZOHDIV

Reserved.

DPWM Zero Order Hold, Down-sampling Divisor

The input sample rate of the DPWM is set by DPWM_CLK frequency and the divisor set in this register by the following formula:

Fs = DPWM_CLK /(ZOHdiv *64* BIQ_CTL.DPWMPUSR).

Default is 6, which gives a sample rate of 16kHz up-sample 256 for a 24.576MHz

DPWM_CLK and BIQ_CTL.DPWMPUSR is 4.

ZOH_DIV must be greater than 2

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Revision 2.4


7.3 Analog Functional Blocks

7.3.1 Overview

The ISD91200 contains a variety of analog functional blocks that facilitate audio processing, enable analog GPIO functions (current source, relaxation oscillator, and comparator), adjust and measure internal oscillator and provide voltage regulation. These blocks are controlled by registers in the analog block address space. This section describes these functions and registers.

7.3.2 Features

 VMID reference voltage generation.

 Current source generation for AGPIO (Analog enabled GPIO).

 LDO control for GPIOA[7:0] power domain and external device use.

 Operational Amplifier

 Comparator

 Microphone Bias generator.

 Analog Multiplexer.

 Programmable Gain Amplifier (PGA) for Audio Path

 HIRC Frequency Control.

 CapSense Relaxation Oscillator.

 Oscillator Frequency Measurement block.


R : read only, W : write only, R/W : read/write


ANA_VMID

Offset

ANA Base Address:

ANA_BA = 0x4008_0000

ANA_BA+0x00

ANA_LDOSEL ANA_BA+0x20

ANA_LDOPD ANA_BA+0x24

ANA_MICBSEL ANA_BA+0x28

ANA_MICBEN

ANA_BA+0x2C

ANA_TRIM ANA_BA+0x84

ANA_FQMMCTL

ANA_BA+0x94

ANA_FQMMCNT ANA_BA+0x98

ANA_FQMMCYC ANA_BA+0x9C

R/W VMID Reference Control Register

R/W LDO Voltage Select Register

R/W LDO Power Down Register

R/W Microphone Bias Voltage Level Selection

R/W Microphone Bias Enable

R/W Oscillator Trim Register

R/W Frequency Measurement Control Register

R Frequency Measurement Count Register

R/W Frequency Measurement Cycle Register

Reset Value

0x0000_0007

0x0000_0000

0x0000_0001

0x0000_0000

0x0000_0001

0x0000_XXXX

0x0000_0001

0x0000_0000

0x0000_0000

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Revision 2.4


7.3.4 VMID Reference Voltage Generation

The analog path and blocks require a low noise, mid-rail, Voltage reference for operation, the VMID generation block provides this.

Control of this block allows user to power down the block, select its power down condition and control over the reference impedance. The block consists of a switchable resistive divider connected to the device VMID pin. A 4.7µF capacitor should be placed on this pin and returned to analog ground (VSSA) as shown in .

Before using the SDADC, PGA or other analog blocks, the VMID reference needs to be enabled. A low impedance option allows fast charging of the external noise de-coupling capacitor, while a higher impedance options provides lower power consumption. A pulldown option allows the reference to be discharged when off.

Internal

Reference

R

R

LDO15

VMID

VSSA

4.7uF

Note: LDO15 is IC internal signal

Figure 7-4 VMID Reference Generation

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Revision 2.4


VMID Control Register (ANA_VMID)


ANA_BA+0x00 R/W VMID Reference Control Register ANA_VMID

Reset Value

0x0000_0007

7 6 5

Reserved

4 3 2

PDHIRES

1 0

PDLORES PULLDOWN

Table 7-6 VMID Control Register (ANA_VMID, address 0x4008_0000).


[31:3] Reserved

[2]

[1]

PDHIRES

PDLORES

Reserved.

Power Down High (360k

Ω) Resistance Reference

0= Connect the High Resistance reference to VMID. Use this setting for minimum power consumption.

1= The High Resistance reference is disconnected from VMID. Default power down and reset condition.

Power Down Low (4.8k

Ω) Resistance Reference

0= Connect the Low Resistance reference to VMID. Use this setting for fast power up of VMID. Can be turned off after 50ms to save power.

1= The Low Resistance reference is disconnected from VMID. Default power down and reset condition.

[0]

VMID Pulldown

PULLDOWN 0= Release VMID pin for reference operation.

1= Pull VMID pin to ground. Default power down and reset condition.

7.3.5 LDO Power Domain Control

The ISD91200 provides a Low Dropout Regulator (LDO) that provides power to the I/O domain of GPIOA[7:0]. Using this regulator device can operate from a 5V supply rail and generate a 1.5-3.3V regulated supply to operate the

GPIOA[7:0] domain and external loads up to 30mA. The supply pin for the LDO is the VDDBS pin which should be connected to VCCD. If the LDO is not used, both VDDBS and VD33 should be tied to VCCD. Upon POR or reset the default condition of the LDO is off, meaning supply will be high impedance. Software must configure the LDO before

GPIOA[7:0] is usable (unless VD33=VCCD).

LDOPD[1:0]

LDO

LDOSET[1:0]

VCCLDO

VD33

GPIOA[7]

GPIOA[0]

To load

1 µ F 0.1

µ F

VSSD

Figure 7-5 LDO Power Domain

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Revision 2.4


LDO Voltage Control Register (ANA_LDOSEL)


ANA_LDOSEL ANA_BA+0x20 R/W LDO Voltage Select Register

Reset Value

0x0000_0000

7 6 5

Reserved

4 3 2 1

LDOSEL

Table 7-7 LDO Voltage Control Register ( ANA_LDOSEL , address 0x4008_0020).


[31:3] Reserved Reserved.

[2:0] LDOSEL

Select LDO Output Voltage

Note that maximum I/O pad operation speed only specified for voltage >2.4V.

0= 1.8V

1= 2.4V

2= 2.5V

3= 2.7V

4=3.0V

5=3.3V

6=1.5V

7=1.7V

0

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Revision 2.4


LDO Power Down Register (ANA_LDOPD)


ANA_BA+0x24 R/W LDO Power Down Register ANA_LDOPD

7 6 5 4 3

Reserved

Reset Value

0x0000_0001

2 1

DISCHAR

0

PD

Table 7-8 LDO Power Down Control Register (ANA_LDOPD, address 0x4008_0024).


[31:2] Reserved

[1]

[0]

DISCHAR

PD

Reserved.

Discharge

0 = Don’t discharge VD33.

1 = Switch discharge resistor to VD33.

Power Down LDO

When powered down no current delivered to VD33.

0= Enable LDO.

1= Power Down.

7.3.6 Microphone Bias

Microphone Bias Enable Register (ANA_MICBEN)


ANA_MICBEN ANA_BA+0x2C R/W Microphone Bias Enable

7 6 5 4

Reserved

3

Reset Value

0x0000_0001

2 1 0

PD

Table 7-9 Microphone Bias Enable Control Register (ANA_MICBEN, address 0x4008_002C).


[31:1] Reserved

[0] PD

Reserved.

Power Down Microphone Bias

0= Enable Microphone Bias

1= Power Down Microphone Bias

Note: MICBIAS output needs VMID enable together.

Microphone Bias Voltage Level Selection Register (ANA_MICBSEL)


ANA_MICBSEL ANA_BA+0x28 R/W Microphone Bias Voltage Level Selection

Reset Value

0x0000_0000

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Revision 2.4


7 6 5

Reserved

4 3 2 1

LVL

0

Table 7-10 Microphone Bias Voltage Level Selection Register (ANA_, address 0x4008_0028).


[31:3] Reserved

[2:0] LVL

Reserved.

LVL controls the voltage output of the MICBIAS generator, voltages are encoded as following:

0 - 1.5V

1 - 1.8V

2 - 1.95V

3 - 2.1V

4 - 2.25V

5 - 2.4V

6 - 2.55V

7 - 2.7

Note: MICBIAS voltage should be at least 300mV lower than VCCA.

7.3.7 Oscillator Frequency Measurement and Control

The ISD91200 provides a functional unit that can be used to measure PCLK frequency given a reference frequency such as the 32.768kHz crystal or an I2S frame synchronization signal. This is simply a special purpose timer/counter

as shown in Figure 7-6 Oscillator Frequency Measurement Block Diagram.

X032K

XI32K

I2S_WS

OSC16K

OSC32K

FM_SEL[1:0]

M

U

X

FM_CYCLE[7:0]

CYCLE_CNT

8 bits

PCLK

EN

Counter

16 bits

FREQ_CNT[15:0]

FM_DONE

Figure 7-6 Oscillator Frequency Measurement Block Diagram

The block can be used to trim/measure the internal high frequency oscillator to the reference frequency of the

32.768kHz oscillator or an external reference frequency fed in on the I2S frame sync input. With this the internal clock can be set at arbitrary frequencies, other than those trimmed at manufacturing, or can be periodically trimmed to account for temperature variation. The block can also be used to measure the 10kHz oscillator frequency relative to the internal master oscillator.

An example of use would be to measure the internal oscillator with reference to the 32768Hz crystal. To do this:

CLK_APBCLK0.ANACKEN = 1; /* Turn on analog peripheral clock */

ANA_FQMMCTL.CLKSEL = 1; // Select reference source as 32kHz XTAL input

ANA_FQMMCTL.CYCLESEL = DRVOSC_NUM_CYCLES-1;

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Revision 2.4


ANA_FQMMCTL. FQMMEN = TRUE; while( (ANA_FQMMCTL.MMSTS != 1) && (Timeout++ < 0x100000)); if( Timeout >= 0x100000) return(E_DRVOSC_MEAS_TIMEOUT);

Freq = ANA_FQMMCNT;

ANA_FQMMCTL.FQMMEN = FALSE;

Freq = Freq*32768 /DRVOSC_NUM_CYCLES;

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Revision 2.4


Oscillator Trim Register (ANA_TRIM)


ANA_TRIM ANA_BA+0x84 R/W Oscillator Trim Register

Reset Value

0x0000_XXXX

31 30 29 28 27 26 25

Reserved

23 22 21 20 19 18 17

Reserved

15 14 13 12 11 10 9

COARSE

7 6 5 4 3 2 1

OSCTRIM

Table 7-11 Oscillator Trim Register (ANA_TRIM, address 0x4008_0084).



[15:8]

[7:0]

COARSE

OSCTRIM

Reserved.

COARSE

Current COARSE range setting of the oscillator. Read Only

Oscillator Trim

Reads current oscillator trim setting. Read Only.

24

16

8

0

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Revision 2.4


Frequency Measurement Control Register (ANA_FQMMCTL)


ANA_FQMMCTL ANA_BA+0x94 R/W Frequency Measurement Control Register

31

FQMMEN

23

15

7

30

22

14

6

29

21

13

28

20

27

Reserved

19

12

CYCLESEL

11

Reserved

4 3

26

18

10

5

Reserved

2

MMSTS

25

17

9

1

Reset Value

0x0000_0001

24

16

8

0

CLKSEL

Bits

Table 7-12 Frequency Measurement Control Register (ANA_FQMMCTL, address 0x4008_0094).

Description

[31] FQMMEN


[23:16] CYCLESEL

[15:3] Reserved

[2]

[1:0]

MMSTS

CLKSEL

FQMMEN

0 = Disable/Reset block.

1 = Start Frequency Measurement.

Reserved.

Frequency Measurement Cycles

Number of reference clock periods plus one to measure target clock (PCLK). For example if reference clock is OSC32K (T is 30.5175us), set CYCLESEL to 7, then measurement period would be 30.5175*(7+1), 244.1us.

Reserved.

Measurement Done

0 = Measurement Ongoing.

1 = Measurement Complete.

Reference Clock Source

00b: OSC10k,

01b: OSC32K (default),

1xb: I2S_WS – can be GPIOA[4,8,12] according to SYS_GPA_MFP register, configure I2S in SLAVE mode to enable.

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Revision 2.4


Frequency Measurement Count (ANA_FQMMCNT)


ANA_FQMMCNT ANA_BA+0x98 R Frequency Measurement Count Register

31

23

15

7

30

22

14

6

29

21

13

5

28 27

Reserved

20 19

Reserved

12

FQMMCNT

11

4 3

FQMMCNT

26

18

10

2

25

17

9

1

Reset Value

0x0000_0000

24

16

8

0

Table 7-13 Frequency Measurement Count Register (ANA_FQMMCNT, address 0x4008_0098).



[15:0] FQMMCNT

Reserved.

Frequency Measurement Count

When MMSTS = 1 and FQMMEN = 1, this is number of PCLK periods counted for frequency measurement.

The frequency will be PCLK = FQMMCNT * Fref /(CYCLESEL+1) Hz.

Maximum resolution of measurement is Fref /(CYCLESEL+1)*2 Hz

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Revision 2.4


Frequency Measurement Cycle (ANA_FQMMCYC)


ANA_FQMMCYC ANA_BA+0x9C R/W Frequency Measurement Cycle Register

31

23

15

7

30

22

14

6

29

21

13

5

28 27

Reserved

20

FQMMCYC

19

12 11

FQMMCYC

4 3

FQMMCYC

26

18

10

2

25

17

9

1

Reset Value

0x0000_0000

24

16

8

0

Table 7-14 Frequency Measurement Cycle Register (ANA_FQMMCYC, address 0x4008_009C).



[23:0] FQMMCYC

Reserved.

Frequency Measurement Cycles

Number of reference clock periods plus one to measure target clock (PCLK). For example if reference clock is OSC32K (T = 30.5175µs), FQMMCYC = 7, then measurement period would be

30.5175*(7+1) = 244.1µs. This address access same register as ANA_FQMMCTL but allows access to more bits of register.

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Revision 2.4


7.4 Automatic Level Control (ALC)


The SDADC audio signal digital path is supported by digital automatic level control function. The ALC monitors the output of the SDADC biquad output when that filter is enabled in the SDADC path, or the output of the SINC filter otherwise. The SDADC output is fed into a peak detector, which updates the measured peak value whenever the absolute value of the input signal is higher than the current measured peak. The measured peak gradually decays to zero unless a new peak is detected, allowing for an accurate measurement of the signal envelope. Based on a comparison between the measured peak value and the target value, the ALC block adjusts the gain of audio signal.

Please note this gain is digital gain. Different from the trantional PGA gain which resides in analog domain and is typically adjusted by changing resistor value.

The ALC is enabled by setting ALCEN. The ALC shares a clock source with the Biquad filter so

CLK_APBCLK0.BQALCKEN must be set to operate ALC. The BIQ result also multiply the ALC result, so

BIQ should work together. The ALC has two functional modes, which is set by MODESEL.

•

Normal mode (MODESEL = LOW)

•

Peak Limiter mode (MODESEL = HIGH)

Input < noise gate threshold

ALC operation range

Target TARGETLV – 6dB

Gain (Attenuation) clipped at MINGAIN -12dB

+ 33 dB

PGA Gain

0 dB

12 dB

NGEN = 1

NGTH = 39 dB

MIC Boost Gain = 0 dB

TARGETLV = -6dB

ALCMIN = 12 dB

MAXGAIN = + 35 .

25 dB

39 dB

39 dB 6 dB + 6 dB

Input Level

Figure 7-8: ALC Response Graph

The registers listed in the following sections allow configuration of ALC operation with respect to:

•

ALC target level

•

Gain increment and decrement rates

•

Minimum and maximum PGA gain values for ALC operating range

•

Hold time before gain increments in response to input signal

•

Inhibition of gain increment during noise inputs

•

Limiter mode operation

The operating range of the ALC is set by MAXGAIN and MINGAIN bits such that the PGA gain generated by the ALC is constrained to be between the programmed minimum and maximum levels. When the ALC is enabled, the PGA gain setting from PGASEL has no effect.

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Revision 2.4


In Normal mode, the MAXGAIN bits set the maximum level for the PGA but in the Limiter mode MAXGAIN has no effect because the maximum level is set by the initial PGA gain setting upon enabling of the ALC.

7.4.1.1 Normal Mode

Normal mode is selected when MODESEL is set LOW and the ALC is enabled by setting ALCEN HIGH.

This block adjusts the PGA gain setting up and down in response to the input level. A peak detector circuit measures the envelope of the input signal and compares it to the target level set by TARGETLV.

The ALC increases the gain when the measured envelope is less than (target – 1.5dB) and decreases the gain when the measured envelope is greater than the target. The following waveform illustrates the behavior of the ALC.

PGA Input

PGA Output

PGA Gain

Figure 7-9: ALC Normal Mode Operation

7.4.1.2 ALC Hold Time (Normal mode Only)

The hold parameter HOLDTIME configures the time between detection of the input signal envelope being below the target range and the actual gain increase.

Input signals with different characteristics (e.g., voice vs. music) may require different settings for this parameter for optimal performance. Increasing the ALC hold time prevents the ALC from reacting too quickly to brief periods of silence such as those that may appear in music recordings; having a shorter hold time, on the other hand, may be useful in voice applications where a faster reaction time helps to adjust the volume setting for speakers with different volumes. The waveform below shows the operation of the HOLDTIME parameter.

PGA Input

PGA Output

PGA Gain

Hold Delay

Change

Figure 7-10: ALC Hold Time

7.4.1.3 Peak Limiter Mode

Peak Limiter mode is selected when MODESEL is set to HIGH and the ALC is enabled by setting ALCEN.

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Revision 2.4


In limiter mode, the PGA gain is constrained to be less than or equal to the gain setting at the time the limiter mode is enabled. In addition, attack and decay times are faster in limiter mode than in normal mode as indicated by the different lookup tables for these parameters for limiter mode. The following waveform illustrates the behavior of the ALC in Limiter mode in response to changes in various ALC parameters.

PGA Input

PGA

Output

PGA Gain

Limiter

Enabled

Figure 7-11: ALC Limiter Mode Operations

When the input signal exceeds 87.5% of full scale, the ALC block ramps down the PGA gain at the maximum attack rate (ATKSEL=0000) regardless of the mode and attack rate settings until the SDADC output level has been reduced below the threshold. This limits SDADC clipping if there is a sudden increase in the input signal level.

7.4.1.4 Attack Time

When the absolute value of the SDADC output exceeds the level set by the ALC threshold, TARGETLV, attack mode is initiated at a rate controlled by the attack rate register ATKSEL. The peak detector in the

ALC block loads the SDADC output value when the absolute value of the SDADC output exceeds the current measured peak; otherwise, the peak decays towards zero, until a new peak has been identified.

This sequence is continuously running. If the peak is ever below the target threshold, then there is no gain decrease at the next attack timer time; if it is ever above the target-1.5dB, then there is no gain increase at the next decay timer time.

7.4.1.5 Decay Times

The decay time DECAYSEL is the time constant used when the gain is increasing. In limiter mode, the time constants are faster than in ALC mode.

7.4.1.6 Noise gate (normal mode only)

A noise gate is used when there is no input signal or the noise level is below the noise gate threshold.

The noise gate is enabled by setting NGEN to HIGH. It does not remove noise from the signal. The noise gate threshold NGTH is set to a desired level so when there is no signal or a very quiet signal (pause), which is composed mostly of noise, the ALC holds the gain constant instead of amplifying the signal towards the target threshold. The noise gate only operates in conjunction with the ALC (ALCEN HIGH) and ONLY in Normal mode. The noise gate flag is asserted when

(Signal at SDADC – ALC gain) < NGTH (dB)

Levels at the extremes of the range may cause inappropriate operation, so care should be taken when setting up the function.

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Revision 2.4


PGA Input

PGA Output

PGA Gain

Figure 7-12: ALC Operation with Noise Gate disabled

Noise Gate Threshold PGA Input

PGA Output

PGA Gain

Figure 7-13: ALC Operation with Noise Gate Enabled

7.4.1.7 Zero Crossing

The PGA gain comes from either the ALC block when it is enabled or from the PGA gain register setting when the ALC is disabled. Zero crossing detection may be enabled to cause PGA gain changes to occur only at an input zero crossing. Enabling zero crossing detection limits clicks and pops that may occur if the gain changes while the input signal has a high volume.

There are two zero crossing detection enables:

•

Register ZCEN – is only relevant when the ALC is enabled.

If the zero crossing function is enabled (using either register), the zero cross timeout function may take effect. If the zero crossing flag does not change polarity within 0.25 seconds of a PGA gain update (either via ALC update or PGA gain register update), then the gain will update. This backup system prevents the gain from locking up if the input signal has a small swing and a DC offset that prevents the zero crossing flag from toggling.

- 412 -


Revision 2.4





ALC Base Address:

ALC_BA = 0x400B_0090

ALC_CTL ALC_BA+0x00

ALC_BA+0x04 ALC_GAIN

ALC_STS ALC_BA+0x08

ALC_BA+0x0C ALC_INTCTL

R/W

R/W

R/W

R/W

ALC Control Register

ALC GAIN Control Register

ALC Status Register

ALC Interrupt Control Register

Reset Value

0x0000_0000

0x6fdc_0010

0x0100_0000

0x0000_0000

- 413 -


Revision 2.4



Register

ALC Control Register (ALC_CTRL)


ALC_CTL ALC_BA+0x00 R/W ALC Control Register

Reset Value

0x0000_0000

Bits

Table 7-15 ALC Control Register (ALC_CTL, address 0x400B_0090)

31

PKLIMEN

23

30

PKSEL

22

29

NGPKSEL

MINGAIN[1:0]

15 14

7

21

ALCRANGES

EL

13

TARGETLV[2:0]

6

ATKSEL

5

28

ALCEN

20

12

MODESEL

4

27 26

MAXGAIN

18 19

11

HOLDTIME

10

3

NGEN

25

17

9

2

DECAYSEL

1

NGTHBST

24

MINGAIN[2]

16

TARGETLV[3]

8

0

Description

[31]

[30]

[29]

[28]

[27:25]

PKLIMEN

PKSEL

NGPKSEL

ALCEN

MAXGAIN

ALC Peak Limiter Enable

Default is “0”,

Please set as “1”

ALC Gain Peak Detector Select

0 = use absolute peak value for ALC training (default).

1 = use peak-to-peak value for ALC training.

ALC Noise Gate Peak Detector Select

0 = use peak-to-peak value for noise gate threshold determination (default).

1 = use absolute peak value for noise gate threshold determination.

ALC Select

0 = ALC disabled (default).

1 = ALC enabled.

ALC Maximum Gain

0 = -6.75 dB.

1 = -0.75 dB.

2 = +5.25 dB.

3 = +11.25 dB.

4 = +17.25 dB.

5 = +23.25 dB.

6 = +29.25 dB.

7 = +35.25 dB.

- 414 -


Revision 2.4

[24:22]

[21]

[20:17]

[16:13]

[12]

[11:8]

[7:4]

[3]


MINGAIN

ALC Minimum Gain

0 = -12 dB.

1 = -6 dB.

2 = 0 dB.

3 = 6 dB.

4 = 12 dB.

5 = 18 dB.

6 = 24 dB.

7 = 30 dB.

ALCRANGESEL

ALC Target range selection

0 = ALC target range -28.5~ -6dB

1 = ALC target range -22.5 ~-1.5dB

HOLDTIME

TARGETLV

MODESEL

DECAYSEL

ATKSEL

NGEN

ALC Hold Time

(Value: 0~10). Hold Time = (2^HOLDTIME) ms.

ALC Target Level

0 = -28.5 dB.

1 = -27 dB.

2 = -25.5 dB.

3 = -24 dB.

4 = -22.5 dB.

5 = -21 dB.

6 = -19.5 dB.

7 = -18 dB.

8 = -16.5 dB.

9 = -15 dB.

10 = -13.5 dB.

11 = -12 dB.

12 = -10.5 dB.

13 = -9 dB.

14 = -7.5 dB.

15 = -6 dB.

ALC Mode

0 = ALC normal operation mode.

1 = ALC limiter mode.

ALC Decay Time

(Value: 0~10)

When MODESEL = 0, Range: 500us to 512ms.

When MODESEL = 1,Range: 125us to 128ms (Both ALC time doubles with every step).

ALC Attack Time

(Value: 0~10)

When MODESEL = 0, Range: 125us to 128ms.

When MODESEL = 1, Range: 31us to 32ms (time doubles with every step).

Noise Gate Enable

0 = Noise gate disabled.

1 = Noise gate enabled.

- 415 -


Revision 2.4


[2:0] NGTHBST

Noise Gate Threshold

000 --- -39dB

001--- -45dB

010---- -51dB

011 --- -57dB

100 --- -63dB

101 --- -69dB

110 --- -75dB

111 --- -81dB

Register

ALC_GAIN

ALC Gain Control Register (ALC_GAIN)


ALC_BA+0x04 R/W ALC GAIN Control Register

Reset Value

0x6fdc_0010

Table 7-16 ALC GAIN Control Register (ALC_GAIN, address 0x400B_0094)

31

23

15

30

22

14

29

21

13

5

28 27

PKLIMT[15:8]

20

PKLIMIT[7:0]

19

12 11

Reserved

4 3

INITGAIN

26

18

10

2

25

17

9

1

24

16

8

0 7 6

INITGAINEN ALCZCD


[31:16]

[15:8]

[7]

[6]

PKLIMIT

Reserved

INITGAINEN

ZCEN

ALC Peak Limiter Threshold

Full scale - 0x7fff

Default value is 0x6fdc - 87.5% of full scale

Reserved.

ALC Update Initial Gain

0 = ALC PGA GAIN load automatic calculating gain.

1 = ALC PGA GAIN load ALCINIT_GAIN

ALC Zero Crossing Enable

0 = zero crossing disabled.

1 = zero crossing enabled when update gain.

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Revision 2.4

[5:0] INITGAIN


ALC Initial Gain

Set ALC initial gain.

Selects the PGA gain setting from -12dB to 35.25dB in 0.75dB step size. 0x00 is lowest gain setting at -12dB and 0x3F is largest gain at 35.25dB

- 417 -


Revision 2.4


Register

ALC_STS

ALC Status Register (ALC_STATUS)


ALC_BA+0x08 R/W ALC Status Register

Reset Value

0x0100_0000

31

23

15

7

Table 7-17 ALC Status Register (ALC_STS, address 0x400B_0098)

27 30 29 28

Reserved

22

14

ALCGAIN

13

PEAKVAL[4:0]

6

21 20

12

5

P2PVAL[5:0]

4

19

11

3

26 25 24

ALCGAIN

18 17

PEAKVAL[8:5]

10 9

P2PVAL[8:6]

16

8

2 1

NOISEF

0

CLIPF

Bits

[31:26]

Description

Reserved

[25:20]

[19:11]

[10:2]

[1]

[0]

ALCGAIN

PEAKVAL

P2PVAL

NOISEF

CLIPF

Reserved.

ALC GAIN

Current ADC gain setting

Peak Value

9 MSBs of measured absolute peak value

Peak-to-peak Value

9 MSBs of measured peak-to-peak value

Noise Flag

Asserted when signal level is detected to be below NGTHBST

Clipping Flag

Asserted when signal level is detected to be above 87.5% of full scale

Register

ALC_INTCTL

ALC Interrupt Register (ALC_INT)


ALC_BA+0x0C R/W ALC Interrupt Control Register

Reset Value

0x0000_0000

31

ALCINT

23

15

Table 7-18 ALC Interrupt Enable Register (ALC_INTCTL, address 0x400B_009C)

30 29 26 25

Reserved

22

14

21

13

GMINIF

28

20

27

Reserved

19

Reserved

12

GMAXIF

11

GDECIF

18

10

GINCIF

17

9

NGIF

24

16

8

PLMTIF

- 418 -


Revision 2.4


[30:14]

[13]

[1]

[0]

Bits

7

Reserved

6

Description

5

GMINIE

[31]

[12]

[11]

[10]

[9]

[8]

[7:6]

[5]

[4]

[3]

[2]

ALCIF

Reserved

GMINIF

GMAXIF

GDECIF

GINCIF

NGIF

PLMTIF

Reserved

GMINIE

GMAXIE

GDECIE

GINCIE

NGIE

PLMTIE

4

GMAXIE

3

GDECIE

2

GINCIE

1

NGIE

0

PLMTIE

ALC Interrupt flag

This interrupt flag asserts whenever the interrupt is enabled and the PGA gain is updated, either through an ALC change with the ALC enabled or through a PGA gain write with the ALC disabled.

Write a 1 to this register to clear.

Reserved.

GAIN less than minimum GAIN interrupt flag.

GAIN more than maximum GAIN interrupt flag.

GAIN Decrease interrupt flag

GAIN Increase interrupt flag

ALC noise gating interrupt flag

ALC Peak limiting Interrupt flag

Reserved.

GAIN less than minimum GAIN interrupt enable control

GAIN more than maximum GAIN interrupt enable control

GAIN Decrease interrupt enable control

GAIN Increase interrupt enable control

ALC noise gating interrupt enable control

ALC Peak limiting Interrupt enable control

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Revision 2.4


7.5 Capacitive Sensing Scan (CSCAN) and Operational Amplifiers


Capacitive Sensing Scanner has the ability to set up a capacitive sensing on up to 16 GPIO pins. The block can do a single measurement or be set up to scan a defined set of GPIO before interrupting the

CPU. The measurement can be done rapidly against a high precision clock (HIRC) in active mode or can be done slowly against a low frequency clock which can be done at low current in STOP or SPD power modes. The analog portion of the circuit consists of a relaxation oscillator producing a triangle wave on the parasitic capacitance attached to the GPIO.

7.5.2 Features

 Support single mode or scan mode for pin cap sensing, maximum 16 pins supported.

 Low power consumption (<10uA) touch wake up from STOP or SPD mode.

 Current source generation for AGPIO (Analog enabled GPIO)

 16 kinds of dummy delay time (maximum 3840 clocks setting in DUR_CNT) for additional duration of periodical wakeup.

7.5.3 Operation

To operate the CSCAN with scan mode for multi pin capacitive sensing, the below steps is the sequence.

•

Set CTRL.PD=0 to power up CSCAN engien

•

Select the cscan timebase clock by setting SLOW_CLK

•

Set AGPIO.AGPIO for expected GPIO pin to analog mode.

•

Set CYCCNT.MASK for all the pins which will have capacitive sensing.

•

Set CYCCNT.CYCLE_CNT for numbers of cycle to time a capacitive sensing.

•

Select scan mode by setting CTRL.MODE0=1

•

Set CTRL.MODE1 for interrupt with DUR_CNT delay or not. MODE1=0 for no delay, interrupt happens after finish all selected pins sensing. MODE1=1 for delay with DUR_CNT setting time.

•

Set CTRL.CURRENT for controlling the bias current of relaxation comparators.

•

Set CTRL.INT_EN to enable the IP interrupt

•

Enable NVIC CSCAN interrupt

•

Start the capacitive sensing with setting CTRL.EN

After interrupt happens, user program needs to read back the counter value of each pin capacitive sensing which sotred in SBRAM for touch algorithm judgement then trigger next loop of scan. The address is fixed for each pin, no matter pin is used for capacitive sensing or not.

SBRAM_BASE

(= 0x400F0000)

Offset

(unit: byte)

PB0 PB1 PB2

0x0 0x2 0x4

~

~

PB13 PB14 PB15

0x1A 0x1C 0x1E

7.5.4 Operational Amplifier

The ISD91200 contains two fully integrated Operational Amplifiers. These OPAs can be used for signal amplification according to specific user requirements. These blocks are controlled by registers in the analog block address space. This section describes these functions and registers

The internal Operational Amplifiers are fully under the control of internal registers, OPA0C0, OPA0C1,

OPA1C0, OPA1C1 and OPA1C2. These registers control enable/disable function, input path selection and gain control.

The following diagram and table illustrate the OPA0 switch control setting and the corresponding connections.

- 420 -


Revision 2.4


Figure 7-14 Operational Amplifier 0 Switch Control

The following diagram and table illustrate the OPA1 switch control setting and the corresponding connections. Note the PAGEN switch control selections will force some switches to be controlled by hardware automatically.

- 421 -


Revision 2.4


Figure 7-15 Operational Amplifier 1 Switch Control

The following diagram is OPAs bias setting,

If the OPBIASEN is set to “1”, that will turn on the resistor DC path, which will generate bias voltage for OPAs

Figure 7-16 Operational Amplifier bias Switch Control

- 422 -


Revision 2.4


7.5.5 Comparator

The ISD91200 contains two analog comparators are contained within the devices. These functions offer flexibility via their register controlled features such as power-down, interrupt etc. Sharing their pins with normal I/O pins, the comparators do not waste precious I/O pins if there functions are otherwise unused.

CNP

C2P C1N

CINT0

INT select

CMPINT

V

L0

V

H0

CMPES

SW1 SW2 SW3

CNPSEL C2PSEL

C1PSEL

C1OUTEN

C1OUT

A0O2CIN

S7C

OPA0

A1O2CIN

S10D

OPA1

CMP1

CMP2

C1INTEN

C2INTEN

CINT0

C2OUTEN

C2OUT

Figure 7-17 Comparator Switch Control



Description Register Offset

CSCAN Base Address:

CSCAN_BA = 0x400D_0000

CSCAN_CTRL CSCAN_BA+0x00

R/W

R/W

CSCAN_CYCCNT

CSCAN_COUNT

CSCAN_BA +0x04

CSCAN_BA +0x08

R/W

R/W

CSCAN Control Register

CSCAN Cycle Count Control Register

CSCAN Count Status Register

CSCAN_INT

CSCAN_AGPIO

CSCAN_OPACTL

CSCAN_CMPCTL

CSCAN_BA +0x0C R/W

CSCAN_BA+0x10 R/W

CSCAN_BA+0x14 R/W

CSCAN_BA+0x18 R/W

CSCAN Interrupt Register

CSCAN Analog GPIO function Register

Operational Amplifier Control Register

Comparator Control Register

- 423 -

Reset Value

0x8000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000


Revision 2.4



CSCAN Control Register (CSCAN_CTRL)


CSCAN_CTRL CSCAN_BA+0x00 R/W CSCAN Control Register

Bits

[31]

[30]

31

PD

23

MODE1

15

[27:24]

[23]

[22]

[21]

7

Reset Value

0x8000_0000

Table 7-19 CSCAN Control Register (CSCAN_CTRL, address 0x400D_0000)

30

EN

22

MODE0

14

6

29

Reserved

21

SLOW_CLK

13

5

28

Reserved

20

INT_EN

12

4

27

19

11

SEL

SEL

3

Reserved

26 25

18

DUR_CNT

17

10

2

9

1

CURRENT

24

16

8

0

Description

PD

EN

DUR_CNT

MODE1

MODE0

SLOW_CLK

Power Down

0: Enable analog circuit

1: Power down analog circuit and block.

CSCAN Enable

Write 1 to start. Reset by hardware when operation finished.

CSCAN Duration Count

This counter is used to set a wakeup time after a capacitive sensing scan is complete. It is in units of low frewquency clock period (either LXT or LIRC clock) and gives delay of 160, 320, 480,640, 800, 960, 1120, 1280, 1440,1600, 1920, 2240,

2560, 2880,3200 3840 periods for settings 0,..,15.

CSCAN Mode1

0 = Interrupt when scan finished

1 = Interrupt when DUR_CNT delay occurs.

CSCAN Mode0

0 = Single shot Capacitive sense

1 = Scans each channel set in SCAN_MASK and stores in RAM.

CSCAN Slow Clock

0 = Timebase clock is HIRC.

1 = Timebase clock is LIRC (XTAL32K_EN = 0) or XTAL (XTAL32K_EN = 1)

**Notes:

In low speed mode, for CYCLE_CNT <5, the minimum frequency of oscillation of a CAPSENSE GPIO must be > Fclk/2. Where Fclk is the frequency of LXT or

LIRC depending which is selected as reference.

- 424 -


Revision 2.4


[20]

[19:18]

[17:16]

[15:0]

INT_EN

Reserved

CURRENT

SEL

CSCAN Enable Interrupt

0 = Interrupt disabled.

1 = Interrupt enabled.

Keep with 0

CSCAN Oscillator current

Controls the analog bais current of the capacitive relaxation oscillator.

0: 300nA 1: 450nA 2: 600nA 3: 1200nA

CSCAN Select

In single mode selects the channel (GPIOB[15:0]) to perform measurement on.

CSCAN Cycle Count Control Register (CSCAN_CYCCNT)


CSCAN_CYCCNT CSCAN_BA +0x04 R/W CSCAN Cycle Count Control Register 0x0000_0000

Bits

31

23

15

7

Table 7-20 CSCAN Counat Control Register (CSCAN_CYCNT, address 0x400D_0004)

30 29 26 25 24

22

14

6

Reserved

21

13

5

28 27

MASK

20 19

12

4

MASK

Reserved

11

3

18

10

17

9

2

CYCLE_CNT

1

16

8

0

Description

[31:16]

[15:4]

MASK

Reserved

Scan Mask Register

If MASK[n] is set then GPIOB[n] is included in scan of capacitive sensing.

Reserved

- 425 -


Revision 2.4


[3:0] CYCLE_CNT

CSCAN Cycle Count

Number of cycles to time a CapSense even over 4 bit value decoded to 1, 2, 4, 8,

16, 32, 64, 128, 256, 512, 768, 1024, 1536, 2048, 2560, 3072

CYCLE_CNT

Cycles

CYCLE_CNT

Cycles

0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7

1 2 4 8 16 32 64 128

0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF

256 512 768 1024 1536 2048 2560 3072

Notes:

•

It is recommended to use CYCLE_CNT >= 5 (32 cycles or more) when

SLOW_CLK = 1. Inappropriate CSCAN_CTRL.CURRENT settings with short scan cyle (CYCLE_CNT <= 4) might disrupt Capsense Interrupt and power mode wake up.

•

It is recommended to check result of CYCLE_CNT > 2 (4 cycles ) when SLOW_CLK = 0 to avoid overflow the scan counter.

CSCAN Count Register (CSCAN_COUNT)


CSCAN_COUNT CSCAN_BA +0x08 R/W CSCAN Count Status Register 0x0000_0000

Table 7-21 CSCAN Count Register (CSCAN_COUNT, address 0x400D_0008)

26 25 31 30 29 28 27

Reseverd

23 22 21 20 19

Reserved

15 14 13 12 11

COUNT

7 6 5 4

Bits

[31:16]

[15:0]

Description

Reserved

COUNT

COUNT

Reserved

CSCAN Count

Count result of single scan.

CSCAN Interrupt Register (CSCAN_INT)


3

18

10

2

17

9

1

CSCAN_INT CSCAN_BA +0x0C R/W CSCAN Interrupt Register

24

16

8

0

Reset Value

0x0000_0000

- 426 -


Revision 2.4


31

23

15

7

Table 7-22 CSCAN Interrupt Register (CSCAN_INT, address 0x400D_000C)

30 29 26 25

22

14

6

21

13

5

28 27

Reseverd

20 19

12

4

Reserved

Reserved

11

3

Reserved

18

10

2

17

9

1

INT

24

16

8

0

Bits

[31:1]

Description

Reserved

[0] INT

CSCAN Interrupt active

Write ‘1’ to clear.

CSCAN Analog GPIO Register (CSCAN_AGPIO)


CSCAN_AGPIO CSCAN_BA+0x10 R/W CSCAN Analog GPIO function Register

Reset Value

0x0000_0000

Bits

[15:0]

31

23

15

[31:16]

7

Table 7-23 CSCAN AGPIO Register (CSCAN_AGPIO, address 0x400D_0010)

30

22

14

6

Description

Reserved

AGPIO

29 28 27 26 25 24

Reseverd

21 20 19 18 17 16

Reserved

13 12 11 10 9 8

AGPIO

5 4 3 2 1 0

AGPIO

Scan Mask Register

If MASK[n] is set then GPIOB[n] is included in scan of capacitive sensing.

CSCAN AGPIO

If bit set to 1 then corresponding GPIOB[n] is forced to an analog mode where digital input, output and pullup is disabled. Can be used to set pad into analog mode for

CapSensing, SAR ADC and OPAMP functions.

- 427 -


Revision 2.4


7.5.7.1 Operational Amplifier Control Register (OPACTRL)


CSCAN_OPACTL CSCAN_BA+0x14

31

23

A0O2A1N

15

A1X

7

A0X

30

22

A0O2A1P

14

A1O2N

6

A0O2N

R/W Operational Amplifier Control Register

29

Reserved

21

Reserved

13

A1PSEL

28

20

VREFEN

12

5 4

A0PSEL

27

19

PGAEN

11

A1PS

3

A0PS

26

A1O2CIN

18

10

A1NS

2

A0NS

25

A0O2CIN

17

PGA_GAIN

9

A1OEN

1

A0OEN

0x0000_0000

24

LPWREN

16

8

A1EN

0

A0EN

Bits

[31:25]

Description

Reserved

[26]

[25]

[24]

[23]

[22]

[21]

[20]

[19]

A1O2CIN

A0O2CIN

LPWREN

A0O2A1N

A0O2A1P

Reserved

VREFEN

PGAEN

Reserved.

OPA1 output to comparator input control bit

0= disable

1= enable

OPA0 output to comparator input control bit

0= disable

1= enable

Enable Opamps in STOP/SPD modes

0 = disable.

1 = enable.

OPA0 Output to OPA0 Inverting Input Control Bit

0 = disable.

1 = enable.

OPA0 Output to OPA1 Non-inverting Input Control Bit

0 = disable.

1 = enable.

Reserved

Enable OPA and Comparator Reference Voltage Generator

0 = disable.

1 = enable.

OPA1 PGA Gain Enable Control Bits

0 = disable.

1 = Enable.

- 428 -


Revision 2.4

[18:16] PGA

[15]

[14]

[11]

[10]

[9]

[8]

[7]

[6]

A1X

A102N

[13:12] A1PSEL

[5:4] A0PSEL

[3]

[2]

A1PS

A1NS

A1OEN

A1EN

A0X

A0O2N

A0PS

A0NS


OPA1 Gain Control Bits

000 = 1.

001 = 8.

010 = 16.

011 = 24.

100 = 32.

101 = 40.

110 = 48.

111 = 56.

Operational amplifier 1 output; positive logic This bit is read only


0 = disable.

1 = enable.

OPA1 Non-inverting Input Selection Bit

00 = no connection.

01 = from VH1 (0.9×VDDA).

10 = from VM (0.5×VDDA ).

11 =: from VL1 (0.1×VDDA).

A1P Pin to OPA1 Non-inverting Input Control Bit

0 = no connection.

1 = from A0P pin.

A1N Pin to OPA1 Inverting Input Control Bit

0 = no connection.

1 = from A0N pin.

OPA1 Output Enable or Disable Control Bit

0 = disable.

1 = enable.

OPA1 Enable or Disable Control Bit

0 = disable.

1 = enable.

Operational amplifier 0 output; positive logic This bit is read only


0 = disable.

1 = enable.

OPA0 Non-inverting Input Selection Bit

00 = no connection.

01 = from VH1 (0.9×VDDA).

10 = from VM (0.5×VDDA).

11 =: from VL1 (0.1×VDDA).

A0P Pin to OPA0 Non-inverting Input Control Bit

0 = no connection.

1 = from A0P pin.

A0N Pin to OPA0 Inverting Input Control Bit

0 = no connection.

1 = from A0N pin.

- 429 -


Revision 2.4


[1]

[0]

A0OEN

A0EN

OPA0 Output Enable or Disable Control Bit

0 = disable.

1 = enable.

OPA0 Enable or Disable Control Bit

0 = disable.

1 = enable.

Comparator Control Register (CMPCTRL)


CSCAN_CMPCT

L

CSCAN_BA+0x18 R/W Comparator Control Register

31 30

23

15

7

CMPES

22

14

6

29

21

28

Reserved

20

Reserved

27

19

26

18

25

17

C2OUT

9 13 12 11 10

Reserved Reserved C2INTEN C2OUTEN C2PSEL

5 4 3 2 1

Reset Value

0x0000_0000

24

LPWREN

16

C1OUT

8

CMP2EN

0

CNPSEL Reserved Reserved CMP_INT C1INTEN C1OUTEN C1NSEL CMP1EN

Bits

[31:25]

Description

Reserved

[24]

[23:18]

[17]

[16]

[15:14]

[13:12]

LPWREN

Reserved

C2OUT

C1OUT

CMPES

Reserved

Reserved

Comparator Low power mode enable

If ‘1’ comparator will remain enabled in STOP/SPD power modes.

Reserved

Comparator 2 Output.

Real time readback of comparator 2.

Comparator 1 Output.

Real time readback of comparator 1.

Interrupt edge control bits

00=disable

01= rising edge trigger

10= falling edge trigger

11= dual edge trigger

Reserved

- 430 -


Revision 2.4

[11]

[10]

[9]

[8]

[7]

[6:5]

[4]

[3]

[2]

[1]

[0]


C2INTEN

C2PSEL

CMP2EN

CNPSEL

:

Reserved

CMP_INT

C1INTEN

C1NSEL

CMP1EN

:

:

:

:

C2OUTEN

C1OUTEN

Comparator 2 interrupt control

0= disable

1= enable

Comparator 2 output pin control bit

0= disable

1= enable

Comparator 2 inverting input control

0= from VL0

1= from C2P pin

Comparator 2 enable or disable control

0= disable

1= enable

Comparator non-inverting input control

0= from OPA output

1= from CNP pin

Reserved

Comparator Interrupt.

Set by harddware.

Write 1 to clear.

Comparator 1 interrupt control

0= disable

1= enable

Comparator 1 output pin control bit

0= disable

1= enable

Comparator 1 inverting input control

0= from VH0

1= from C1N pin

Comparator 1 enable or disable control

0= disable

1= enable

- 431 -


Revision 2.4


7.6 Biquad Filter (BIQ)


A coefficient programmable 6-stage Biquad filter (12 th

-Order IIR filter) is available which can be used on either SDADC path or DPWM path to further reduce unwanted noise or filter the signal. Each biquad filter has the transfer function as H(z) and is implemented in Direct Form II Transpose structure as.

Upon power on reset or when the BIQ_CTL.DLCOEFF =1 is released, a set of default coefficients b n0

, b n1

, b n2

, a n1

, a n2

(n = 1,2,3 which is the stage number of the filter) will be written to the coefficient RAM automatically. And these coefficients can be over-written by the processor for different filter specifications.

Note that the fixed point coefficients have the format of 3.16 (19 bits) and are stored in the coefficient

RAM under normal operation. It takes 32 internal system clocks for the automatic write to finish when the

BIQ_CTL.DLCOEFF bit is released; it is important that the processor has enough delay before start the coefficient programming or enabling biquad (BIQ_CTL.BIQEN). Attempting to program the coefficients before the auto programming is done will result in unsuccessful programming. The default coefficient setting is a low pass filter with 3db cut-off frequency with 16KHz Fs (Sample Rate) and 256 OSR

Biquad is released from reset by setting BIQ_CTL.DLCOEFF =1. After 32 clock cycles, processor can setup other Biquad parameters or re-program coefficients before enabling filter.

The BIQ_CTL.PATHSEL register bit determines which path the BIQ is going to use. The default value is 0 which is the microphone ADC path, by setting this bit 1, the BIQ will be used in DPWM path.

If the BIQ is intended to be used in DPWM path, the BIQ can up sample the data rate by programming

BIQ_CTL.DPWMPUSR register which has default value at 1.

If the BIQ is intended to be used in ADC path, the BIQ can down sample the data rate by programming

BIQ_CTL.SDADCWNSR, register which has default value at 1.

The BIQ filter is in reset state in default. To use the BIQ function, the following sequence is recommended:

1. Set BIQ_CTL.DLCOEFF bit. By releasing the reset, the filter controller will download default coefficients automatically to the RAM.

2. Turn on the BIQ_CTL.PRGCOEFF bit if intending to change the coefficients. Otherwise skip to next step.

3. Setup the BIQ operation sample rate by program DPWMPUSR or SRDIV register bits if necessary.

4. Decide the SDADC or DPWM path to be used for the BIQ by programming PATHSEL, and turn off PRGCOEFF bit (if it was turned on in step #2).

5. Setup BIQ stage (BIQ_CTL.STAGE), set “1” BIQ with 5 stages, set “0” BIQ with 6 stages.

6. Setup high pass filter on or off (BIQ_CTL.HPFON. If HPF is ON, the BIQ Stage automatically set

6 stages, one for HPF).

7. Turn on BIQ_CTL.BIQEN, BIQ will start filter function.

- 432 -


Revision 2.4


Configuring Coefficient

1. BIQ function work on 6 stages, set BIQ_CTL.STAGE=0, BIQ function will call 30 coefficients from BIQ_BA+0x0 ~0x074

2. BIQ function work on 5 stages, set BIQ_CTL.STAGE=1, BIQ function will call 25 coefficients from BIQ_BA+0x00 ~0x060

3. If High pass filter is on (BIQ_CTL.HPFON=1), BIQ function automatically set 6 stages, one for

HPF. BIQ function will call 30 coefficients.

4. BIQ function work on one stage, set first stage coefficient and bypass other stages set b0 =

0x1000, b1 =0,b2=0,a1 =0,a2=0.

5. BIQ function work on two stages, set first and second stages coefficient and bypass other stages set b0 = 0x1000, b1 =0,b2=0,a1 =0,a2=0.

6. BIQ function work on three stages, set first, second and third stages coefficient and bypass other stages set b0 = 0x1000, b1 =0,b2=0,a1 =0,a2=0

7. BIQ function work on four stages, set first, second, third and fourth stages coefficient and bypass other stages set b0 = 0x1000, b1 =0,b2=0,a1 =0,a2=0


7.6.2.1 BIQ filter coefficients registers

Register Offset R/W

BIQ Base Address:

BIQ_BA = 0x400B_0000

Description Reset Value

BIQ_COEFF0

BIQ_COEFF1

BIQ_COEFF2

BIQ_COEFF3

BIQ_COEFF4

BIQ_COEFF5

BIQ_COEFF6

BIQ_COEFF7

BIQ_COEFF8

BIQ_COEFF9

BIQ_BA+0x00

BIQ_BA+0x004

BIQ_BA+0x008

BIQ_BA+0x00c

BIQ_BA+0x010

BIQ_BA + 0x14

BIQ_BA+0x018

BIQ_BA+0x01c

BIQ_BA+0x020

BIQ_BA+0x024

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Coefficient b0 In H(z) Transfer Function

(3.16 format) - 1 st

stage BIQ Coefficients







Coefficient a1 In H(z) Transfer Function







(3.16 format) - 2 nd














0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

- 433 -


Revision 2.4


BIQ_COEFF10

BIQ_COEFF11

BIQ_COEFF12

BIQ_COEFF13

BIQ_COEFF14

BIQ_COEFF15

BIQ_COEFF16

BIQ_COEFF17

BIQ_COEFF18

BIQ_COEFF19

BIQ_COEFF20

BIQ_COEFF21

BIQ_COEFF22

BIQ_COEFF23

BIQ_COEFF24

BIQ_COEFF25

BIQ_COEFF26

BIQ_COEFF27

BIQ_COEFF28

BIQ_COEFF29

BIQ_CTL

BIQ_STS

BIQ_BA + 0x28

BIQ_BA+0x02c

BIQ_BA+0x030

BIQ_BA+0x034

BIQ_BA+0x038

BIQ_BA + 0x3c

BIQ_BA+0x040

BIQ_BA+0x044

BIQ_BA+0x048

BIQ_BA+0x04c

BIQ_BA + 0x50

BIQ_BA+0x054

BIQ_BA+0x058

BIQ_BA+0x05c

BIQ_BA+0x060

BIQ_BA + 0x64

BIQ_BA+0x068

BIQ_BA+0x06c

BIQ_BA+0x070

BIQ_BA+0x074

BIQ_BA+0x080

BIQ_BA+0x084

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W


(3.16 format) - 3 rd



























































BIQ Control Register

BIQ status Register

- 434 -

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0110

0x8000_0000


Revision 2.4



BIQ Coefficient Register (BIQ_COEFFn)

Register

BIQ_COEFF0

BIQ_COEFF1

BIQ_COEFF2

BIQ_COEFF3

BIQ_COEFF4

BIQ_COEFF5

BIQ_COEFF6

BIQ_COEFF7

BIQ_COEFF8

BIQ_COEFF9

BIQ_COEFF10

BIQ_COEFF11

BIQ_COEFF12

BIQ_COEFF13

BIQ_COEFF14

BIQ_COEFF15

BIQ_COEFF16

BIQ_COEFF17

BIQ_COEFF18

Offset

BIQ_BA+0x00

BIQ_BA+0x004

BIQ_BA+0x008

BIQ_BA+0x00c

BIQ_BA+0x010

BIQ_BA + 0x14

BIQ_BA+0x018

BIQ_BA+0x01c

BIQ_BA+0x020

BIQ_BA+0x024

BIQ_BA + 0x28

BIQ_BA+0x02c

BIQ_BA+0x030

BIQ_BA+0x034

BIQ_BA+0x038

BIQ_BA + 0x3c

BIQ_BA+0x040

BIQ_BA+0x044

BIQ_BA+0x048

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Description


























































Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

- 435 -


Revision 2.4


BIQ_COEFF19

BIQ_COEFF20

BIQ_COEFF21

BIQ_COEFF22

BIQ_COEFF23

BIQ_COEFF24

BIQ_COEFF25

BIQ_COEFF26

BIQ_COEFF27

BIQ_COEFF28

BIQ_COEFF29

31 30

BIQ_BA+0x04c

BIQ_BA + 0x50

BIQ_BA+0x054

BIQ_BA+0x058

BIQ_BA+0x05c

BIQ_BA+0x060

BIQ_BA + 0x64

BIQ_BA+0x068

BIQ_BA+0x06c

BIQ_BA+0x070

BIQ_BA+0x074

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W


































29 26

23

15

7

22

14

6

21

13

5

28 27

COEFFDAT[31:24]

20 19

COEFFDAT[23:16]

12 11

COEFFDAT[15:9]

4 3

COEFFDAT[7:0]

18

10

2

Bits

[31:0]

Description

COEFFDAT Coefficient Data

25

17

9

1

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

24

16

8

0

- 436 -


Revision 2.4


BIQ Control Register (BIQ_CTL)

Register

BIQ_CTL


BIQ_BA+0x080 R/W BIQ Control Register

31

23

15

Table 7-24 BIQ Control Register (BIQ_CTL, address 0x400B_0080)

29 28 27 25 30

Reserved

22 21

26

SRDIV[12:8]

18 17

14 13

6

Reserved

5

SDADCWNSR

20 19

12

4

SRDIV[7:0]

11

STAGE

3

DLCOEFF

10

2

PATHSEL

9

DPWMPUSR

1

HPFON

7

PRGCOEFF

Bits

[31:12]

[28:16]

[15:12]

Description

Reserved

SRDIV

Reserved

[11]

[10:8]

[7]

[6:4]

STAGE

DPWMPUSR

PRGCOEFF

SDADCWNSR

Reserved

SR Divider

Reserved

BIQ Stage Number Control

0 = 6 stage.

1 = 5 stage.

DPWM Path Up Sample Rate (From SRDIV Result)

0001 --- up 1x ( no up sample)

0010 --- up 2x

0011 --- up 3x

0100 --- up 4x

0110 --- up 6x

Others reserved

Programming Mode Coefficient Control Bit

0 = Coefficient RAM is in normal mode.

1 = coefficient RAM is under programming mode.

This bit must be turned off when BIQEN is on.

SDADC Down Sample

001--- 1x (no down sample)

010 --- 2x

011 --- 3x

100 --- 4x

11 0--- 6x

Others reserved

Reset Value

0x0000_0110

24

16

8

0

BIQEN

- 437 -


Revision 2.4

[3]

[2]

[1]

[0]

DLCOEFF

PATHSEL

HPFON

BIQEN


Move BIQ Out of Reset State

0 = BIQ filter is in reset state.

1 = When this bit is on, the default coefficients will be downloaded to the coefficient ram automatically in 32 internal system clocks. Processor must delay enough time before changing the coefficients or turn the BIQ on.

AC Path Selection for BIQ

0 = used in SDADC path.

1 = used in DPWM path.

High Pass Filter On

0 = disable high pass filter.

1 = enable high pass filter.

Note :

If this register is on, BIQ only 5 stage left.for user.

SDADC path sixth stage coefficient is for HPF filter coefficient.

DPWM path first stage coefficient is for HPF filter coefficient.

BIQ Filter Start to Run

0 = BIQ filter is not processing.

1 = BIQ filter is on.

- 438 -


Revision 2.4


[30:3]

[2]

[1]

[0]

BIQ Status Register (BIQ_STATUS)

Register

BIQ_STS

31

RAMINITF

23

15

7

Offset

BIQ_BA+0x084

30

22

14

6

R/W

R/W

Description

BIQ status Register

Reset Value

0x8000_0000

Table 7-25 BIQ Status Register (BIQ_STATUS)

29 26

21

13

28

20

27

Reserved

19

Reserved

12 11

Reserved

4 3

18

10

5

Reserved

25

17

9

2 1

BISTDONE BISTFAILED

24

16

8

0

BISTEN


[31] RAMINITF

Reserved

BISTDONE

BISTFAILED

BISTEN

Coefficient Ram Initial Default Done Flag

0 = initial default value done.

1 = still working on.

Reserved

RAM BIST testing DONE flag for internal use

RAM BIST testing FAILED indicator for internal use

RAM BIST testing Enable for internal use

- 439 -


Revision 2.4


7.7 Successive Approximation Analog-to-Digital Convertor (SARADC)


– Analog input voltage range: 0~VREF

– Up to 12 single-end analog input channels

– Three operating modes

•

Single mode: A/D conversion is performed one time on a specified channel.

•

Single-cycle scan mode: A/D conversion is performed one cycle on all specified channels following the sequence from the lowest numbered channel to the highest numbered channel.

•

Continuous scan mode: A/D converter continuously performs Single cycle scan mode until software stops A/D conversion.

– An A/D conversion can be started by:

– Writing 1 to SWTRG bit through software

– External pin SARADC_TRIG (or called STADC in section)

– Conversion results are held in data registers for each channel with valid and overrun indicators

– Conversion result can be compared with specified value; can generate interrupt when conversion result matches the compare register setting.

- 440 -


Revision 2.4



STADC

V

REF

VALID & OVERRUN

Digital Control Logics

&

ADC Clock Generator

ADF

RSLT[11:0]

Successive

Approximations

Register

PDMA request

ADC_INT

12-bit DAC

ADC0

ADC1

ADC11

Sample and Hold

+

-

Comparator

Analog Control

Logics

Analog Macro

Figure 7-18 SARADC Block Diagram

7.7.3 Function description

The A/D converter operates by successive approximation with 12-bit resolution. The SARADC had three operation modes: single mode, single-cycle scan mode and continuous scan mode. When changing the operation mode or analog input channel, to prevent incorrect operation, software must clear SWTRG bit to “0” in CTL register.

- 441 -


Revision 2.4


7.7.3.1 SARADC Clock Generator

The SARADC engine has four clock sources selected by 2 bits SARADCSEL, the SARADC clock divided by 8 bits prescaler with the formula.

The SARADC clock frequency = (SARADC clock source frequency)/(SARADCDIV+1).

Where the 8 bits SARADCDIV is located in register CLKDIV0[31:24].

SARADCCKSEL(CLK_CLKSEL1[25:24])

SARADCEN(CLK_APBCLK0[17])

CLK_32K

CLK_49M

CLK_10K

HCLK

11

10

01

1/(SARADCDIV + 1)

SARADCDIV(CLK_CLKDIV0[31:24])

SARADC_CLK

00


Figure 7-19 SARADC Clock Generator

7.7.3.2 Single Mode

I n single mode, A/D conversion is performed only once on the specified single channel. The operations are as follows:

1. A/D conversion will be started when the SWTRG bit of CTL is set to 1 by software.

2. When A/D conversion is finished, the result is stored in the A/D data register corresponding to the channel.

3. The ADEF bit of STATUS register will be set to 1. If the ADCIE bit of CTL register is set to 1, the SARADC interrupt will be asserted.

4. The SWTRG bit remains 1 during A/D conversion. When A/D conversion ends, the SWTRG bit is automatically cleared to 0 and the A/D converter enters idle state.

Note: If software enables more than one channel in single mode, the channel with the smallest number will be selected and the other enabled channels will be ignored.

- 442 -


Revision 2.4


1 2 8 9 28

ADC_CLK

SWTRG sample

ADDRx[11:0]

ADEF

ADDRx[11:0]

Figure 7-20 Single Mode Conversion Timing Diagram

7.7.3.3 Single-Cycle Scan Mode

In single-cycle scan mode, A/D conversion will sample and convert the specified channels once in the sequence from the smallest number enabled channel to the largest number enabled channel.

1. When the SWTRG bit of CTL is set to 1 by software or external trigger input, A/D conversion starts on the channel with the smallest number.

2. When A/D conversion for each enabled channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel.

3. When the conversions of all the enabled channels are completed, the ADEF bit in STATUS is set to 1.

If the SARADC interrupt function is enabled, the SARADC interrupt occurs.

4. After A/D conversion ends, the SWTRG bit is automatically cleared to 0 and the A/D converter enters idle state. If SWTRG is cleared to 0 before all enabled SARADC channels conversion done, SARADC controller will finish current conversion and save the result to the DATx(ADDRx) of the current conversion channel.

An example timing diagram for single-cycle scan on enabled channels (0, 2, 3 and 7) is shown below:

- 443 -


Revision 2.4


ADC_CLK

SWTRG chsel[3:0] sample

SAR[15:0]

ADDR0

ADDR2

ADDR3

ADDR7

1 2

0000b

28

R0

R0

0010b

56

R2

0011b

R2

84

R3

0111b

R3

112

R7

R7

ADEF

Single-cycle scan on channel 0, 2, 3 and 7 (SARADC_CHEN[15:0] =

0010001101b)

Figure 7-21 Single-Cycle Scan on Enabled Channels Timing Diagram

7.7.3.4 Continuous Scan Mode

In continuous scan mode, A/D conversion is performed sequentially on the specified channels that enabled by

CHEN bits in CHEN register (maximum 12 channels for SARADC). The operations are as follows:

1. When the ADST bit in CTL is set to 1 by software, A/D conversion starts on the channel with the smallest number.

2. When A/D conversion for each enabled channel is completed, the result of each enabled channel is stored in the A/D data register corresponding to each enabled channel.

3. When A/D converter completes the conversions of all enabled channels sequentially, the ADEF bit

(STATUS[0]) will be set to 1. If the SARADC interrupt function is enabled, the SARADC interrupt occurs. The conversion of the enabled channel with the smallest number will start again if software has not cleared the ADST bit.

4. As long as the ADST bit remains at 1, the step 2 ~ 3 will be repeated. When ADST is cleared to 0,

SARADC controller will stop conversion.

An example timing diagram for continuous scan on enabled channels (0, 2, 3 and 7) is shown below:

- 444 -


Revision 2.4


ADC_CLK

1 27 28 55 56 84 112 1 28 56 84 112

SWTRG chsel[3:0] sample

ADDR0

ADDR2

ADDR3

ADDR7

Software clear

SWTRG

0000b 0010b 0011b 0111b 0000b 0010b 0011b 0111b 0000b

ADEF

Continuous scan on channel 0, 2, 3 and 7 (SARADC_CHEN[15:0] =

0010001101b)

Figure 7-22 Continuous Scan on Enabled Channels Timing Diagram

7.7.3.5 External trigger Input Sampling and A/D Conversion Time

In Single-cycle scan mode, A/D conversion can be triggered by external pin request. When the CTL.HWTRGEN is set to high to enable SARADC external trigger function. setting the HWTRGSEL[1] bits to 0b is to select external trigger input from the STADC pin. Software can set HWTRGCOND[1:0] to select trigger condition is falling/rising edge or low/high level. If level trigger condition is selected, the STADC pin must be kept at defined state at least 8 PCLKs.

The ADST bit will be set to 1 at the 9th PCLK and start to conversion. Conversion is continuous if external trigger input is kept at active state in level trigger mode. It is stopped only when external condition trigger condition disappears. If edge trigger condition is selected, the high and low state must be kept at least 4 PLCKs. Pulse that is shorter than this specification will be ignored.

7.7.3.6 Conversion Result Monitor by Compare Function

SARADC controller provide two sets of compare register SARADC_CMP0 and SARADC_CMP1, to monitor maximum two specified channels conversion result from A/D conversion controller, refer Figure… Software can select which channel to be monitored by set CMPCH(SARADC_CMPx[5:0]) and CMPCOND bit is used to check conversion result is less than specify value or greater than (equal to) value specified in CMPDAT[11:0]. When the conversion of the channel specified by CMPCH is completed, the comparing action will be triggered one time automatically. When the compare result meets the setting, compare match counter will increase 1, otherwise, the compare match counter will be cleared to 0. When counter value reach the setting of (CMPMCNT+1) then

ADCMPF bit will be set to 1, if ADCMPIE bit is set then an ADC_INT interrupt request is generated. Software can use it to monitor the external analog input pin voltage transition in scan mode without imposing a load on software. Detailed logics diagram is shown below:

- 445 -


Revision 2.4


CMPCH(CMPx[6:3])

CHANNEL(STATUS[7:4])

Channel

Addr.

CMPCOND(ADCMPRx[2])

CMPMATCNT

(CMPx[11:8])

AIN[0]

AIN[11]

A/D analog macro

RSLT < CMPD

ADDRx[11:0]

12-bit

Comparator

RSLT >=CMPD

0

1

Note:

CMPD=CMPx[27:16]

RSLT=ADDRx[11:0]

Match

Counter

ADCMPFx

(STATUS[2:1])

CMPD(CMPx[27:16])

Figure 7-23 A/D Conversion Result Monitor Logics Diagram

7.7.3.7 Interrupt Sources

There are three interrupt sources of SARADC interrupt. When an SARADC operation mode finishes its conversion, the A/D conversion end flag, ADEF, will be set to 1. . The ADCMPF0 and ADCMPF1 are the compare flags of compare function. When the conversion result meets the settings of ADCMPR0/1, the corresponding flag will be set to 1. When one of the flags, ADEF, ADCMPF0 and ADCMPF1, is set to 1 and the corresponding interrupt enable bit, ADCIE of CTL and ADCMPIE of SARADC_CMP0/SARADC_CMP1, is set to

1, the SARADC interrupt will be asserted. Software can clear the flag to revoke the interrupt request.

ADEF

ADCIE

STATUS.ADCMPF0

CMP0.ADCMPIE

SARADC_INT

STATUS.ADCMPF1

CMP1.ADCMPIE

Figure 7-24 A/D Controller Interrupt


When A/D conversion is finished, the conversion result will be loaded into DATx register and VALID bit will be set to 1. If the PTEN bit of CTL is set, SARADC controller will generate a request to PDMA. User can use PDMA to transfer the conversion results to a user-specified memory space without CPU's intervention. The source address of PDMA operation is fixed at the address of register PDMADAT no matter what channels was selected.

When PDMA is transferring the conversion result, SARADC will continue converting the next selected channel if the operation mode of SARADC is single scan mode or continuous scan mode. User can monitor current PDMA transfer data through reading PDMADAT register. If SARADC completes the conversion of a selected channel and the last conversion result of the same channel has not been transferred by PDMA, overrun OV bit of the corresponding channel will be set and the last SARADC conversion result will be overwritten by the new

SARADC conversion result. PDMA will transfer the latest data of selected channels to the user-specified destination address.

- 446 -


Revision 2.4



R : read only, W : write only, R/W : read/write

Register Offset

SARADC Base Address:

SARADC_BA = 0x4006_0000

SARADC_DAT0

R/W Description

SARADC_BA+0x00 R SAR ADC Data Register 0

SARADC_DAT1

SARADC_DAT2

SARADC_DAT3

SARADC_DAT4

SARADC_DAT5

SARADC_DAT6

SARADC_DAT7

SARADC_DAT8

SARADC_DAT9



SARADC_BA+0x0c R SAR ADC Data Register 3







SARADC_DAT10

SARADC_DAT11



SARADC_STATUS SARADC_BA+0x40 R/W SAR ADC status Register

SARADC_PDMADAT SARADC_BA+0x50 R SAR ADC PDMA Current Transfer Data

SARADC_ACTL SARADC_BA+0x5C R/W SAR ADC analog control register

SARADC_CTL

SARADC_CHEN

SARADC_CMP0

SARADC_BA+0x60

SARADC_BA+0x64

R/W SAR ADC Control Register

R/W SAR ADC Channel Enable Register

SARADC_BA+0x68 R/W SAR ADC Compare Register 0

SARADC_BA+0x6C R/W SAR ADC Compare Register 1 SARADC_CMP1

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

- 447 -


Revision 2.4


7.7.5 Register description

SAR ADC Data Register (SARADC_DATx)


SARADC_DAT0 SARADC_BA+0x00 R SAR ADC Data Register 0

SARADC_DAT1

SARADC_DAT2

SARADC_DAT3

SARADC_DAT4

SARADC_BA+0x04 R

SARADC_BA+0x08 R

SARADC_BA+0x0c R

SARADC_BA+0x10 R

SAR ADC Data Register 1




Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

SARADC_DAT5

SARADC_DAT6

SARADC_BA+0x14 R

SARADC_BA+0x18 R



SARADC_DAT7

SARADC_DAT8

SARADC_BA+0x1c R

SARADC_BA+0x20 R

SARADC_DAT9 SARADC_BA+0x24 R

SARADC_DAT10 SARADC_BA+0x28 R

SARADC_DAT11 SARADC_BA+0x2c R

31 30 29

23

15

22

14






21

28

Reserved

27

20 19

13

Reserved

12 11

7 6

Reserved

5

26

0x0000_0000

25

18 17

VALID

9 10

RESULT[11:8]

2 1 4

RESULT [7:0]

3

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

24

16

OV

8

0

Bits

[31:18]

Description

Reserved

[17] VALID

Reserved.

Valid Flag (Read Only)

0 = Data in RESULT[11:0] bits is not valid.

1 = Data in RESULT[11:0] bits is valid.

Note: This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after DAT register is read.

- 448 -


Revision 2.4

[16] OV

[15:12]

[11:0]

Reserved

RESULT


Overrun Flag (Read Only)

0 = Data in RESULT[11:0] is recent conversion result.

1 = Data in RESULT[11:0] is overwritten.

Note: If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1 and previous conversion result is gone. It is cleared by hardware after DAT register is read.

Reserved.

A/D Conversion Result

This field contains conversion result of SARADC.

12-bit SARADC conversion result with unsigned format.

ADC result in

RSLT[11:0]

1111_1111_1111

1111_1111_1110

1111_1111_1101

Note: Vref voltage comes from

AVDD for 64/48/36-pin package

1 LSB = Vref/4096

0000_0000_0010

0000_0000_0001

0000_0000_0000

1 LSB Vref - 1 LSB

Single-end Input voltage

Vin (V)

Figure 7-25 Conversion Result Mapping Diagram of Single-end Input

- 449 -


Revision 2.4


SAR ADC Status Register ( SARADC_STATUS )


SARADC_ST

ATUS

SARADC_BA+0x40 R/W SAR ADC status Register

31 30 29

23

15

7

22

14

6

CHANNEL

21

13

5

28 27

Reserved

20

VALID[15:8]

19

12

VALID[7:0]

11

4 3

BUSY

Bits

[31:24]

Description

Reserved

[23:8]

[7:4]

[3]

[2]

[1]

[0]

VALID

CHANNEL

BUSY

ADCMPF1

ADCMPF0

ADEF

26

18

10

2

ADCMPF1

25

17

9

1

ADCMPF0

Reset Value

0x0000_0000

24

16

8

0

ADEF

Reserved.

Data Valid Flag (Read Only)

It is a mirror of VALID bit in DATx.

Current Conversion Channel (Read Only)

This field reflects the current conversion channel when BUSY = 1. When BUSY = 0, it shows the number of the next converted channel.

BUSY/IDLE (Read Only)

0 = A/D converter is in idle state.

1 = A/D converter is busy at conversion.

This bit is mirror of as SWTRG bit in CTL.

Compare Flag

When the selected channel A/D conversion result meets setting condition in

SARADC_CMP1 then this bit is set to 1. And it is cleared by writing 1 to self.

0 = Conversion result in DAT register does not meet CMP1 register.

1 = Conversion result in DAT register meets CMP1 register.

Compare Flag

When the selected channel A/D conversion result meets setting condition in

SARADC_CMP0 then this bit is set to 1. And it is cleared by writing 1 to self.

0 = Conversion result in DAT register does not meet CMP0 register.

1 = Conversion result in DAT register meets CMP0 register.

A/D Conversion End Flag

A status flag that indicates the end of A/D conversion.

ADEF is set to 1 at these two conditions:

1. When A/D conversion ends in Single mode.

2. When A/D conversion ends on all specified channels in Scan mode.

Note: This bit can be cleared by writing ‘1’ to it.

- 450 -


Revision 2.4


SAR ADC PDMA Current Transfer Data Register (SARADC_PDMADAT)


SARADC_PD

MADAT

SARADC_BA+0x50 R SAR ADC PDMA Current Transfer Data

31 30 29 28 27 26

Reserved

23 22 21 20 19 18

Reserved

15

7

14

6

13

5

12

DATA[15:8]

11

4 3

DATA[7:0]

10

2

Bits

[31:18]

Description

Reserved

[17:0] DATA

25

17

DATA[17:16]

16

9 8

1

Reset Value

0x0000_0000

24

0

Reserved.

SAR ADC PDMA Current Transfer Data Register (Read Only)

When PDMA transferring, read this register can monitor current PDMA transfer data.

Current PDMA transfer data is the content of DAT0 ~ DAT11.

If PDMA word length = 32, data including Reserved bits, OV bit and VALID bit is moved

If PDMA word length = 16, only AD conversion result is moved.

- 451 -


Revision 2.4


SAR ADC Analog Control Register(SARADC_ACTL)


SARADC_A

CTL

SARADC_BA+0x5C R/W SAR ADC analog control register

[17]

[16]

[15:1]

[0]

31

Reserved

23

Bits

[31:18]

[18]

15

7

30 29 28 27

Reserved

19 22 21

Reserved

20

14

6

Description

Reserved

SAR_VREF

13 12 11

5

reserved

4

Reserved

3

Reserved

VREF selection

0 -- select VCCA as VREF

1 -- select MICBIAS as VREF

Reserved Reserved

Reserved Reserved

Reserved Reserved

SAR_SE_MODE Have to be 1

26

18

SAR_VREF

10

2

25

17

Reserved

9

1

Reset Value

0x0000_0000

24

16

Reserved

8

0

SAR_SE_MODE

- 452 -


Revision 2.4


SAR ADC Control Register(SARADC_CTL)


SARADC_CTL SARADC_BA+0x60 R/W SAR ADC Control Register

31

Reserved

23

15

7

30

22

14

6

HWTRGCOND

Reserved

29

21

13

5

HWTRGSEL

28

20

27

Reserved

19

Reserved

12

4

26

18

11

SWTRG

3

10

Reserved

OPMODE

2

Bits

[31]

[30:12]

Description

Reserved

Reserved

[11]

[10]

[9]

[8]

SWTRG

Reserved

PDMAEN

HWTRGEN

25

17

9

PDMAEN

1

ADCIE

Reset Value

0x0000_0000

24

16

8

HWTRGEN

0

ADCEN

Reserved

Reserved

A/D Conversion Start

0 = Conversion stops and A/D converter enter idle state.

1 = Conversion starts.

SWTRG bit can be set to 1 from three sources: software, external pin STADC. SWTRG will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode. In continuous scan mode, A/D conversion is continuously performed until software writes 0 to this bit or chip reset.

Reserved

PDMA Transfer Enable Bit

0 = PDMA data transfer Disabled.

1 = PDMA data transfer in DAT 0~11 Enabled.

When A/D conversion is completed, the converted data is loaded into DAT 0~11, software can enable this bit to generate a PDMA data transfer request.

When PDMA=1, software must set ADCIE=0 to disable interrupt.

Hardware Trigger Enable Bit

Enable or disable triggering of A/D conversion by hardware (external STADC pin or PWM

Center-aligned trigger).

0 = Disabled.

1 = Enabled.

SARADC hardware trigger function is only supported in single-cycle scan mode.

If hardware trigger mode, the SWTRG bit can be set to 1 by the selected hardware trigger source.

- 453 -


Revision 2.4

[0]

[7:6]

[5:4]

[3:2]

[1]


HWTRGCOND

HWTRGSEL

OPMODE

ADCIE

ADCEN

External Trigger Condition

These two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger.

00 = Low level.

01 = High level.

10 = Falling edge.

11 = Rising edge.

Hardware Trigger Source Selection

00 = A/D conversion is started by external STADC pin.

Others = Reserved.

Software should disable TRGEN and SWTRG before change HWTRGSEL.

A/D Converter Operation Mode

00 = Single conversion.

01 = Reserved.

10 = Single-cycle scan.

11 = Continuous scan.

When changing the operation mode, software should disable SWTRG bit firstly.

A/D Interrupt Enable Bit

0 = A/D interrupt function Disabled.

1 = A/D interrupt function Enabled.

A/D conversion end interrupt request is generated if ADCIE bit is set to 1.

A/D Converter Enable Bit

0 = Disabled.

1 = Enabled.

Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable

A/D converter analog circuit for saving power consumption.

- 454 -


Revision 2.4


SAR ADC Channel Enable Register ( SARADC_CHEN )


SARADC_CH

EN

SARADC_BA+0x64 R/W SAR ADC Channel Enable Register

31 30 29 28 27 26

Reserved

23

15

22

14

Reserved

21

13

20 19 18

Reserved

10

7 6 5

12 11

4

CHEN[15:8]

3

CHEN[7:0]

2

Bits

[31:12]

[23:20]

[19:17]

[16]

[15:0]

Description

Reserved

Reserved

Reserved

Reserved

CHEN

25

17

9

1

Reserved.

Reserved

Reserved

Reserved

Analog Input Channel Enable Bit

Set CHEN[11:0] to enable the corresponding analog input channel 11 ~ 0.

0 = SARADC input channel Disabled.

1 = SARADC input channel Enabled.

Note: Keep 0 for [15:12]

Reset Value

0x0000_0000

24

16

Reserved

8

0

- 455 -


Revision 2.4


SAR ADC Compare Register 0/1 (SARADC_CMP0/SARADC_CMP1)


SARADC_CM

P0

SARADC_BA+0x68 R/W SAR ADC Compare Register 0

SARADC_CM

P1

SARADC_BA+0x6C R/W SAR ADC Compare Register 1

31 30 29 28 27 26

Reserved CMPDAT

25

23 22 21 20 19 18 17

CMPDAT

15

7

Reserved

14

6

Reserved

13

5

CMPCH

12

4

11

3

10 9

CMPMCNT

2

CMPCOND

1

ADCMPIE

Reset Value

0x0000_0000

0x0000_0000

24

16

8

0

ADCMPEN

Bits

[31:28]

Description

Reserved

[27:16]

[15:12]

[11:8]

[7]

CMPDAT

Reserved

CMPMCNT

Reserved

Reserved.

Comparison Data

The 12-bit data is used to compare with conversion result of specified channel.

When ADCFMbit is set to 0, SARADC comparator compares CMPDAT with conversion result with unsigned format. CMPDAT should be filled in unsigned format.

When ADCFMbit is set to 1, SARADC comparator compares CMPDAT with conversion result with 2’complement format. CMPDAT should be filled in 2’complement format.

Reserved.


When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFx bit will be set.

Reserved.

- 456 -


Revision 2.4

[6:3]

[2]

[1]

[0]

CMPCH

CMPCOND

ADCMPIE

ADCMPEN


Compare Channel Selection

0000 = Channel 0 conversion result is selected to be compared.












1100 = Reserved.

1101 = Reserved.

1110 = Reserved.

1111 = Reserved


0 = Set the compare condition as that when a 12-bit A/D conversion result is less than the

12-bit CMPDAT (CMPx[27:16]), the internal match counter will increase one.

1 = Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (CMPx[27:16]), the internal match counter will increase one.

Note: When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFx bit will be set.

Compare Interrupt Enable Bit

0 = Compare function interrupt Disabled.

1 = Compare function interrupt Enabled.

Note: If the compare function is enabled and the compare condition matches the setting of

CMPCOND and CMPMCNT, ADCMPF bit will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated.

Compare Enable Bit

0 = Compare function Disabled.

1 = Compare function Enabled.

Note: Set this bit to 1 to enable SARADC controller to compare CMPDAT[11:0] with specified channel conversion result when converted data is loaded into DAT register.

- 457 -


Revision 2.4


8 APPLICATION DIAGRAM

CSB

DO

VCC

HOLDB

WPB CLK

GND

W25Q

DIO

VDD

0.1uF

MIC

4.7uF

2.2 K

Ω

0.1uF

2.2 K

Ω

0.1uF

0.1uF

1uF

5 VDDBS

11

8

PA.4/SPI0_MISO0

10

9

PA.3/SPI0_SSB0

6 VDDB

PA.2/SPI0_SCLK0

PA.1/SPI0_MOSI0

DMIC

4.7uF

DMIC_CLK

DMIC_DAT

ISD91260

LQFP64

64

MICBIAS

60

MIC+

62

MIC-

59

VMID

VCCD

VCCD

41

47 uF

0.1

uF

VSSD

15

VCCSPKL

VCCSPKR

19

24

VSSSPK

21

VSSSPK 22

SPK+

20

SPK-

23

XI32K

30

XO32K 31

VCCD

20pF

47 uF

0.1

uF

32.768K

20pF

VREG

39

1uF

VCCA

4

VCCA

47 uF

VSSA

58

0.1

uF

: Digital ground; : Analog ground;

Note:

1. For SPI flash quad mode access, disconnect HOLDB & WPB from VDDB, and then connect HOLDB to PA.0 and WPB to PA.5.

2. Cannot use AMIC and DMIC at the same time, only one can be used. DMIC_CLK and DMIC_DAT can be set with different GPIO share pins.

3. DMIC operating voltage may be different as ISD91200 series. Customer have to care the voltage and data high/low level for ISD91200 recognition.

- 458 -


Revision 2.4


9 PACKAGE DIMENSIONS

9.1 64L LQFP (7x7x1.4mm footprint 2.0mm)

- 459 -


Revision 2.4


9.2 QFN 32L 4X4 mm2, Thickness: 0.8mm (Max), Pitch: 0.40mm

- 460 -


Revision 2.4


10 ORDERING INFORMATION

I9 1x x x x x x

ISD Audio Product Family

Product Series

1: Cortex-M0

Family ID

2: Family Series ID

Flash ROM

3: 64KB

6: 128KB

SRAM

0: 12KB

Temperature

I: -40°C ~ +85°C

Package

R: LQFP-64

Y: QFN-32

Feature

Blank: Standard

C: Voice Recognition

P: SARADC, playback-only

G: Basic feature set

B: Bridge Sense

- 461 -


Revision 2.4


11 REVISION HISTORY

VERSION

V0.2

V0.21

V0.22

V0.23

DATE

Sep 1, 2017

Sep 5, 2017

Sep 7, 2017

Sep 26, 2017

V2.0

V2.1

V2.2

V2.3

V2.4

Oct 17, 2017

Nov 13, 2017

Dec 14, 2017

Jan 8, 2018

Sep 16, 2019

PAGE/

CHAP.

-

DESCRIPTION

Preliminary Release.

Add CSCAN feature and operation, fix Table & Figure reference errors

Add SAR_VREF bit and description

- Rename flash sector size as page size

- Power distruibution diagram revised

- OPA diagram revised

Add figure number in SARADC, change clock source naming, formal release

SPI0 and some typo corrected

- Add analog pin function in pin description

- Add more part feature in ordering information

- Modify SARADC maximum SPS to 700K

- Remove the DINBYPS

- Add description for DINEDGE

- Add DMIC circuit in Application Diagram

- Changed cover title

- Changed header title

- 462 -


Revision 2.4


Important Notice

Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life.

Furthermore, Nuvoton products are not intended for applications wherein failure of Nuvoton products could result or lead to a situation where personal injury, death or severe property or environmental damage could occur.

Nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper use or sales.

Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.

- 463 -


Revision 2.4