Holtek HT32F5828 32-Bit Arm Cortex-M0+ MCU User Manual

Holtek 32-Bit Microcontroller with Arm

®

Cortex

®

-M0+ Core

HT32F5828

User Manual

Revision: V1.00 Date: December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Table of Contents

1 Introduction ........................................................................................................... 28

Overview .............................................................................................................................. 28

Features ............................................................................................................................... 28

Device Information ............................................................................................................... 33

Block Diagram ..................................................................................................................... 34

2 Document Conventions ....................................................................................... 35

3 System Architecture ............................................................................................. 36

Arm ® Cortex ® -M0+ Processor .............................................................................................. 36

Bus Architecture ................................................................................................................... 37

Memory Organization .......................................................................................................... 38

Memory Map ................................................................................................................................... 39

Embedded Flash Memory ............................................................................................................... 41

Embedded SRAM Memory ............................................................................................................. 41

AHB Peripherals ............................................................................................................................. 41

APB Peripherals ............................................................................................................................. 42

4 Flash Memory Controller (FMC) .......................................................................... 43

Introduction .......................................................................................................................... 43

Features ............................................................................................................................... 43

Functional Descriptions ....................................................................................................... 44

Flash Memory Map ......................................................................................................................... 44

Flash Memory Architecture ............................................................................................................. 45

Wait State Setting ........................................................................................................................... 45

Booting Configuration ..................................................................................................................... 46

Page Erase ..................................................................................................................................... 46

Mass Erase ..................................................................................................................................... 48

Word Programming ......................................................................................................................... 49

Option Byte Description .................................................................................................................. 50

Page Erase/Program Protection ..................................................................................................... 51

Security Protection .......................................................................................................................... 52

Register Map ....................................................................................................................... 53

Register Descriptions ........................................................................................................... 54

Flash Target Address Register – TADR .......................................................................................... 54

Flash Write Data Register – WRDR ............................................................................................... 55

Flash Operation Command Register – OCMR ............................................................................... 56

Flash Operation Control Register – OPCR ..................................................................................... 57

Flash Operation Interrupt Enable Register – OIER ........................................................................ 58

Flash Operation Interrupt and Status Register – OISR .................................................................. 59

Flash Page Erase/Program Protection Status Register – PPSR .................................................... 61

Flash Security Protection Status Register – CPSR ........................................................................ 62

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Cortex ® -M0+ MCU

Flash Vector Mapping Control Register – VMCR ........................................................................... 63

Flash Manufacturer and Device ID Register – MDID ...................................................................... 64

Flash Page Number Status Register – PNSR ................................................................................ 65

Flash Page Size Status Register – PSSR ...................................................................................... 66

Device ID Register – DID ................................................................................................................ 66

Flash Pre-fetch Control Register – CFCR ...................................................................................... 67

Custom ID Register n – CIDRn (n = 0 ~ 3) ..................................................................................... 68

5 Reset Control Unit (RSTCU) ................................................................................ 69

Introduction .......................................................................................................................... 69


Power-On Reset ............................................................................................................................. 69

System Reset ................................................................................................................................. 70

AHB and APB Unit Reset ................................................................................................................ 70

Register Map ....................................................................................................................... 70


Global Reset Status Register – GRSR ........................................................................................... 71

AHB Peripheral Reset Register – AHBPRSTR ............................................................................... 72

APB Peripheral Reset Register 0 – APBPRSTR0 .......................................................................... 73

APB Peripheral Reset Register 1 – APBPRSTR1 .......................................................................... 75

6 Clock Control Unit (CKCU) .................................................................................. 77

Introduction .......................................................................................................................... 77

Features ............................................................................................................................... 79


High Speed External Crystal Oscillator – HSE ............................................................................... 79

High Speed Internal RC Oscillator – HSI ........................................................................................ 80

Auto Trimming of High Speed Internal RC Oscillator – HSI ............................................................ 80

Phase Locked Loop – PLL .............................................................................................................. 82

USB Phase Locked Loop – USB PLL ............................................................................................. 83

Low Speed External Crystal Oscillator – LSE ................................................................................. 85

Low Speed Internal RC Oscillator – LSI ......................................................................................... 85

Clock Ready Flag ........................................................................................................................... 85

System Clock (CK_SYS) Selection ................................................................................................ 85

HSE Clock Monitor ......................................................................................................................... 86

Clock Output Capability .................................................................................................................. 86

Register Map ....................................................................................................................... 87


Global Clock Configuration Register – GCFGR .............................................................................. 88

Global Clock Control Register – GCCR .......................................................................................... 89

Global Clock Status Register – GCSR ........................................................................................... 91

Global Clock Interrupt Register – GCIR .......................................................................................... 92

PLL Configuration Register – PLLCFGR ........................................................................................ 93

PLL Control Register – PLLCR ....................................................................................................... 94

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Cortex ® -M0+ MCU

AHB Configuration Register – AHBCFGR ...................................................................................... 95

AHB Clock Control Register – AHBCCR ........................................................................................ 96

APB Configuration Register – APBCFGR ....................................................................................... 98

APB Clock Control Register 0 – APBCCR0 .................................................................................... 99

APB Clock Control Register 1 – APBCCR1 .................................................................................. 101

Clock Source Status Register – CKST ......................................................................................... 103

APB Peripheral Clock Selection Register 0 – APBPCSR0 ........................................................... 104

APB Peripheral Clock Selection Register 1 – APBPCSR1 ........................................................... 106

HSI Control Register – HSICR ...................................................................................................... 108

HSI Auto Trimming Counter Register – HSIATCR ........................................................................ 109

APB Peripheral Clock Selection Register 2 – APBPCSR2 ............................................................110

Low Power Control Register – LPCR ............................................................................................111

MCU Debug Control Register – MCUDBGCR ...............................................................................112

7 Power Control Unit (PWRCU) ............................................................................ 115

Introduction ........................................................................................................................ 115

Features ............................................................................................................................. 116

Functional Descriptions ..................................................................................................... 116

V

DD

Power Domain .........................................................................................................................116

1.5 V Power Domain ......................................................................................................................118

V

LCD

Power Domain .......................................................................................................................118

Operation Modes ...........................................................................................................................118

Register Map ..................................................................................................................... 121

Register Descriptions ......................................................................................................... 121

Power Control Status Register – PWRSR .................................................................................... 121

Power Control Register – PWRCR ............................................................................................... 122

V

DD

Power Domain Test Register – PWRTEST ............................................................................ 124

Low Voltage / Brown-Out Detect Control and Status Register – LVDCSR ................................... 125

Power Control LDO Status Register – PWRLDOSR .................................................................... 127

8 External Interrupt/Event Controller (EXTI) .......................................................... 128

Introduction ........................................................................................................................ 128

Features ............................................................................................................................. 128


Wakeup Event Management......................................................................................................... 129

External Interrupt/Event Line Mapping ......................................................................................... 129

Interrupt and Debounce ................................................................................................................ 129

Register Map ..................................................................................................................... 130


EXTI Interrupt n Configuration Register – EXTICFGRn, n = 0 ~ 15 ............................................. 131

EXTI Interrupt Control Register – EXTICR ................................................................................... 132

EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR ................................................................ 133

EXTI Interrupt Edge Status Register – EXTIEDGESR ................................................................. 134

EXTI Interrupt Software Set Command Register – EXTISSCR .................................................... 135

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Cortex ® -M0+ MCU

EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR ........................................................ 136

EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR ................................................... 137

EXTI Interrupt Wakeup Flag Register – EXTIWAKUPFLG ........................................................... 138

9 General Purpose I/O (GPIO) ............................................................................... 139

Introduction ........................................................................................................................ 139

Features ............................................................................................................................. 140


Default GPIO Pin Configuration .................................................................................................... 140

General Purpose I/O – GPIO ........................................................................................................ 140

GPIO Locking Mechanism ............................................................................................................ 142

Register Map ..................................................................................................................... 142


Port A Data Direction Control Register – PADIRCR ..................................................................... 144

Port A Input Function Enable Control Register – PAINER ............................................................ 145

Port A Pull-Up Selection Register – PAPUR ................................................................................. 146

Port A Pull-Down Selection Register – PAPDR ............................................................................ 147

Port A Open-Drain Selection Register – PAODR .......................................................................... 148

Port A Drive Current Selection Register – PADRVR ..................................................................... 149

Port A Lock Register – PALOCKR ................................................................................................ 150

Port A Data Input Register – PADINR ........................................................................................... 151

Port A Output Data Register – PADOUTR .................................................................................... 151

Port A Output Set/Reset Control Register – PASRR .................................................................... 152

Port A Output Reset Register – PARR .......................................................................................... 153

Port B Data Direction Control Register – PBDIRCR ..................................................................... 153

Port B Input Function Enable Control Register – PBINER ........................................................... 154

Port B Pull-Up Selection Register – PBPUR ................................................................................ 155

Port B Pull-Down Selection Register – PBPDR ............................................................................ 156

Port B Open-Drain Selection Register – PBODR ......................................................................... 157

Port B Drive Current Selection Register – PBDRVR .................................................................... 158

Port B Lock Register – PBLOCKR ................................................................................................ 159

Port B Data Input Register – PBDINR .......................................................................................... 160

Port B Output Data Register – PBDOUTR ................................................................................... 160

Port B Output Set/Reset Control Register – PBSRR .................................................................... 161

Port B Output Reset Register – PBRR ......................................................................................... 162

Port C Data Direction Control Register – PCDIRCR .................................................................... 162

Port C Input Function Enable Control Register – PCINER ........................................................... 163

Port C Pull-Up Selection Register – PCPUR ................................................................................ 164

Port C Pull-Down Selection Register – PCPDR ........................................................................... 165

Port C Open-Drain Selection Register – PCODR ......................................................................... 166

Port C Drive Current Selection Register – PCDRVR .................................................................... 167

Port C Lock Register – PCLOCKR ............................................................................................... 168

Port C Data Input Register – PCDINR .......................................................................................... 169

Port C Output Data Register – PCDOUTR ................................................................................... 169

Port C Output Set/Reset Control Register – PCSRR ................................................................... 170

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Port C Output Reset Register – PCRR ......................................................................................... 171

Port D Data Direction Control Register – PDDIRCR .................................................................... 172

Port D Input Function Enable Control Register – PDINER ........................................................... 173

Port D Pull-Up Selection Register – PDPUR ................................................................................ 174

Port D Pull-Down Selection Register – PDPDR ........................................................................... 175

Port D Open-Drain Selection Register – PDODR ......................................................................... 176

Port D Drive Current Selection Register – PDDRVR .................................................................... 177

Port D Lock Register – PDLOCKR ............................................................................................... 178

Port D Data Input Register – PDDINR .......................................................................................... 179

Port D Output Data Register – PDDOUTR ................................................................................... 180

Port D Output Set/Reset Control Register – PDSRR ................................................................... 181

Port D Output Reset Register – PDRR ......................................................................................... 182

Port E Data Direction Control Register – PEDIRCR ..................................................................... 183

Port E Input Function Enable Control Register – PEINER ........................................................... 184

Port E Pull-Up Selection Register – PEPUR ................................................................................ 185

Port E Pull-Down Selection Register – PEPDR ............................................................................ 186

Port E Open-Drain Selection Register – PEODR ......................................................................... 187

Port E Drive Current Selection Register – PEDRVR .................................................................... 188

Port E Lock Register – PELOCKR ................................................................................................ 189

Port E Data Input Register – PEDINR .......................................................................................... 190

Port E Output Data Register – PEDOUTR ................................................................................... 191

Port E Output Set/Reset Control Register – PESRR .................................................................... 192

Port E Output Reset Register – PERR ......................................................................................... 193

10 Alternate Function Input/Output Control Unit (AFIO) .................................... 194

Introduction ........................................................................................................................ 194

Features ............................................................................................................................. 195


External Interrupt Pin Selection .................................................................................................... 195

Alternate Function ......................................................................................................................... 196

Lock Mechanism .......................................................................................................................... 196

Register Map ..................................................................................................................... 196


EXTI Source Selection Register 0 – ESSR0 ................................................................................ 197

EXTI Source Selection Register 1 – ESSR1 ................................................................................ 198

GPIO Port x Configuration Low Register – GPxCFGLR, x = A, B, C, D, E ................................... 199

GPIO Port x Configuration High Register – GPxCFGHR, x = A, B, C, D, E ................................. 200

11 Nested Vectored Interrupt Controller (NVIC) .................................................. 201

Introduction ........................................................................................................................ 201

Features ............................................................................................................................. 202


SysTick Calibration ....................................................................................................................... 203

Register Map ..................................................................................................................... 203

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Cortex ® -M0+ MCU

12 USB Device Controller (USB) .......................................................................... 204

Introduction ........................................................................................................................ 204

Features ............................................................................................................................. 204


Endpoints ...................................................................................................................................... 205

EP_SRAM ..................................................................................................................................... 205

Serial Interface Engine – SIE ........................................................................................................ 206

Double-Buffering ........................................................................................................................... 206

Suspend Mode and Wake-up ....................................................................................................... 207

Remote Wake-up .......................................................................................................................... 208

Register Map ..................................................................................................................... 208


USB Control and Status Register – USBCSR .............................................................................. 209

USB Interrupt Enable Register – USBIER .....................................................................................211

USB Interrupt Status Register – USBISR ..................................................................................... 212

USB Frame Count Register – USBFCR ....................................................................................... 213

USB Device Address Register – USBDEVAR .............................................................................. 214

USB Endpoint 0 Control and Status Register – USBEP0CSR ..................................................... 215

USB Endpoint 0 Interrupt Enable Register – USBEP0IER ........................................................... 216

USB Endpoint 0 Interrupt Status Register – USBEP0ISR ............................................................ 218

USB Endpoint 0 Transfer Count Register – USBEP0TCR ........................................................... 219

USB Endpoint 0 Configuration Register – USBEP0CFGR ........................................................... 220

USB Endpoint 1 ~ 3 Control and Status Register – USBEPnCSR, n = 1 ~ 3 ............................... 221

USB Endpoint 1 ~ 3 Interrupt Enable Register – USBEPnIER, n = 1 ~ 3 ..................................... 222

USB Endpoint 1 ~ 3 Interrupt Status Register – USBEPnISR, n = 1 ~ 3 ...................................... 223

USB Endpoint 1 ~ 3 Transfer Count Register – USBEPnTCR, n = 1 ~ 3 ..................................... 224

USB Endpoint 1 ~ 3 Configuration Register – USBEPnCFGR, n = 1 ~ 3 ..................................... 225

USB Endpoint 4 ~ 7 Control and Status Register – USBEPnCSR, n = 4 ~ 7 ............................... 226

USB Endpoint 4 ~ 7 Interrupt Enable Register – USBEPnIER, n = 4 ~ 7 ..................................... 228

USB Endpoint 4 ~ 7 Interrupt Status Register – USBEPnISR, n = 4 ~ 7 ...................................... 229

USB Endpoint 4 ~ 7 Transfer Count Register – USBEPnTCR, n = 4 ~ 7 ..................................... 230

USB Endpoint 4 ~ 7 Configuration Register – USBEPnCFGR, n = 4 ~ 7 ..................................... 231

13 Inter-Integrated Circuit (I 2 C) ............................................................................. 232

Introduction ........................................................................................................................ 232

Features ............................................................................................................................. 233


Two-Wire Serial Interface ............................................................................................................. 233

START and STOP Conditions ....................................................................................................... 233

Data Validity .................................................................................................................................. 234

Addressing Format ....................................................................................................................... 234

Data Transfer and Acknowledge ................................................................................................... 236

Clock Synchronization .................................................................................................................. 236

Arbitration ..................................................................................................................................... 237

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Cortex ® -M0+ MCU

General Call Addressing ............................................................................................................... 237

Bus Error ....................................................................................................................................... 237

Address Mask Enable ................................................................................................................... 238

Address Snoop ............................................................................................................................. 238

Operation Mode ............................................................................................................................ 238

Conditions of Holding SCL Line .................................................................................................... 242

I 2 C Timeout Function .................................................................................................................... 243

PDMA Interface ............................................................................................................................. 243

Register Map ..................................................................................................................... 244


I 2 C Control Register – I2CCR ....................................................................................................... 244

I 2 C Interrupt Enable Register – I2CIER ........................................................................................ 246

I 2 C Address Register – I2CADDR ................................................................................................. 247

I 2 C Status Register – I2CSR ......................................................................................................... 248

I 2 C SCL High Period Generation Register – I2CSHPGR .............................................................. 251

I 2 C SCL Low Period Generation Register – I2CSLPGR ............................................................... 252

I 2 C Data Register – I2CDR ........................................................................................................... 253

I 2 C Target Register – I2CTAR ....................................................................................................... 254

I 2 C Address Mask Register – I2CADDMR .................................................................................... 255

I 2 C Address Snoop Register – I2CADDSR ................................................................................... 256

I 2 C Timeout Register – I2CTOUT.................................................................................................. 257

14 Serial Peripheral Interface (SPI) ...................................................................... 258

Introduction ........................................................................................................................ 258

Features ............................................................................................................................. 259


Master Mode ................................................................................................................................. 259

Slave Mode ................................................................................................................................... 259

SPI Serial Frame Format .............................................................................................................. 259

SPI Dual Mode .............................................................................................................................. 264

Status Flags .................................................................................................................................. 266

PDMA Interface ............................................................................................................................. 269

Register Map ..................................................................................................................... 269


SPI Control Register 0 – SPICR0 ................................................................................................. 270

SPI Control Register 1 – SPICR1 ................................................................................................. 272

SPI Interrupt Enable Register – SPIIER ....................................................................................... 274

SPI Clock Prescaler Register – SPICPR ...................................................................................... 275

SPI Data Register – SPIDR .......................................................................................................... 275

SPI Status Register – SPISR ........................................................................................................ 276

SPI FIFO Control Register – SPIFCR ........................................................................................... 277

SPI FIFO Status Register – SPIFSR ............................................................................................ 278

SPI FIFO Time Out Counter Register – SPIFTOCR ..................................................................... 279

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Cortex ® -M0+ MCU

15 Universal Synchronous Asynchronous Receiver Transmitter (USART) ..... 280

Introduction ........................................................................................................................ 280

Features ............................................................................................................................. 281


Serial Data Format ........................................................................................................................ 281

Baud Rate Generation .................................................................................................................. 282

Hardware Flow Control ................................................................................................................. 284

IrDA ............................................................................................................................................... 285

RS485 Mode ................................................................................................................................. 287

Synchronous Master Mode ........................................................................................................... 289

Interrupts and Status .................................................................................................................... 291

PDMA Interface ............................................................................................................................. 291

Register Map ..................................................................................................................... 291


USART Data Register – USRDR .................................................................................................. 292

USART Control Register – USRCR .............................................................................................. 293

USART FIFO Control Register – USRFCR................................................................................... 295

USART Interrupt Enable Register – USRIER ............................................................................... 296

USART Status & Interrupt Flag Register – USRSIFR................................................................... 298

USART Timing Parameter Register – USRTPR ........................................................................... 300

USART IrDA Control Register – IrDACR ...................................................................................... 301

USART RS485 Control Register – RS485CR............................................................................... 302

USART Synchronous Control Register – SYNCR ........................................................................ 303

USART Divider Latch Register – USRDLR................................................................................... 304

USART Test Register – USRTSTR ............................................................................................... 305

16 Universal Asynchronous Receiver Transmitter (UART) ................................ 306

Introduction ........................................................................................................................ 306

Features ............................................................................................................................. 307


Serial Data Format ........................................................................................................................ 307

Baud Rate Generation .................................................................................................................. 308

Interrupts and Status .................................................................................................................... 309

PDMA Interface ............................................................................................................................. 309

Register Map ..................................................................................................................... 310


UART Data Register – URDR ....................................................................................................... 310

UART Control Register – URCR ....................................................................................................311

UART Interrupt Enable Register – URIER .................................................................................... 312

UART Status & Interrupt Flag Register – URSIFR ....................................................................... 314

UART Divider Latch Register – URDLR ....................................................................................... 315

UART Test Register – URTSTR .................................................................................................... 316

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Cortex ® -M0+ MCU

17 Smart Card Interface (SCI) ............................................................................... 317

Introduction ........................................................................................................................ 317

Features ............................................................................................................................. 318


Elementary Time Unit Counter ...................................................................................................... 318

Guard Time Counter ..................................................................................................................... 320

Waiting Time Counter ................................................................................................................... 321

Card Clock and Data Selection ..................................................................................................... 322

Card Detection ............................................................................................................................. 322

SCI Data Transfer Mode ............................................................................................................... 323

Interrupt Generator ....................................................................................................................... 325

PDMA Interface ............................................................................................................................. 326

Register Map ..................................................................................................................... 326


SCI Control Register – CR ............................................................................................................ 327

SCI Status Register – SR ............................................................................................................. 329

SCI Contact Control Register – CCR ............................................................................................ 330

SCI Elementary Time Unit Register – ETUR ................................................................................ 331

SCI Guard Time Register – GTR .................................................................................................. 332

SCI Waiting Time Register – WTR................................................................................................ 333

SCI Interrupt Enable Register – IER ............................................................................................. 334

SCI Interrupt Pending Register – IPR ........................................................................................... 335

SCI Transmit Buffer – TXB ............................................................................................................ 337

SCI Receive Buffer – RXB ............................................................................................................ 337

SCI Prescaler Register – PSCR ................................................................................................... 338

18 Inter-IC Sound (I 2 S) ........................................................................................... 339

Introduction ........................................................................................................................ 339

Features ............................................................................................................................. 339

Functional Description ....................................................................................................... 340

I 2 S Master and Slave Mode .......................................................................................................... 340

I 2 S Clock Rate Generator ............................................................................................................. 341

I 2 S Interface Format ...................................................................................................................... 343

FIFO Control and Arrangement .................................................................................................... 350

PDMA and Interrupt ...................................................................................................................... 351

Register Map ..................................................................................................................... 351


I 2 S Control Register – I2SCR ........................................................................................................ 352

I 2 S Interrupt Enable Register – I2SIER ......................................................................................... 354

I 2 S Clock Divider Register – I2SCDR ........................................................................................... 355

I 2 S TX Data Register – I2STXDR ................................................................................................. 356

I 2 S RX Data Register – I2SRXDR ................................................................................................. 356

I 2 S FIFO Control Register – I2SFCR ............................................................................................ 357

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Cortex ® -M0+ MCU

I 2 S Status Register – I2SSR ......................................................................................................... 358

I 2 S Rate Counter Value Register – I2SRCNTR ............................................................................ 360

19 Analog to Digital Converter (ADC) .................................................................. 361

Introduction ........................................................................................................................ 361

Features ............................................................................................................................. 362


ADC Clock Setup .......................................................................................................................... 363

Channel Selection ......................................................................................................................... 363

Conversion Mode .......................................................................................................................... 363

Start Conversion on External Event .............................................................................................. 366

Sampling Time Setting .................................................................................................................. 367

Data Format .................................................................................................................................. 367

Analog Watchdog.......................................................................................................................... 367

Interrupts ....................................................................................................................................... 368

PDMA Request ............................................................................................................................ 368

Voltage Reference Generator ....................................................................................................... 368

V

DDA

Voltage Monitor ..................................................................................................................... 369

Register Map ..................................................................................................................... 369


ADC Conversion Control Register – ADCCR ............................................................................... 370

ADC Conversion List Register 0 – ADCLST0 ............................................................................... 372

ADC Conversion List Register 1 – ADCLST1 ............................................................................... 373

ADC Input Sampling Time Register – ADCSTR ........................................................................... 374

ADC Conversion Data Register y – ADCDRy, y = 0 ~ 7 ............................................................... 375

ADC Trigger Control Register – ADCTCR .................................................................................... 376

ADC Trigger Source Register – ADCTSR ..................................................................................... 377

ADC Watchdog Control Register – ADCWCR .............................................................................. 378

ADC Watchdog Threshold Register – ADCTR .............................................................................. 380

ADC Interrupt Enable Register – ADCIER .................................................................................... 381

ADC Interrupt Raw Status Register – ADCIRAW ......................................................................... 382

ADC Interrupt Status Register – ADCISR ..................................................................................... 383

ADC Interrupt Clear Register – ADCICLR .................................................................................... 384

ADC DMA Request Register – ADCDMAR ................................................................................... 385

Voltage Reference Control Register – VREFCR .......................................................................... 386

Voltage Reference Value Register – VREFVALR ......................................................................... 387

20 Comparator (CMP) ............................................................................................ 388

Introduction ........................................................................................................................ 388

Features ............................................................................................................................. 388


Comparator Inputs and Output ..................................................................................................... 389

Comparator Voltage Reference .................................................................................................... 389

Interrupts and Wakeup.................................................................................................................. 390

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Cortex ® -M0+ MCU

Power Mode and Hysteresis ......................................................................................................... 391

Comparator Write-Protected Mechanism ..................................................................................... 391

Register Map ..................................................................................................................... 391


Comparator Control Register n – CMPCRn, n = 0 or 1 ................................................................ 392

Comparator Voltage Reference Value Register n – CVRVALRn, n = 0 or 1 ................................. 394

Comparator Interrupt Enable Register n – CMPIERn, n = 0 or 1 ................................................. 395

Comparator Transition Flag Register n – CMPTFRn, n = 0 or 1 .................................................. 396

21 Digital to Analog Converter (DAC) .................................................................. 397

Introduction ........................................................................................................................ 397

Features ............................................................................................................................. 397

Function Descriptions ........................................................................................................ 398

DAC Channel Enable .................................................................................................................... 398

DAC Operation Mode ................................................................................................................... 398

DAC Asynchronous Conversion ................................................................................................... 398

DAC Synchronous Conversion ..................................................................................................... 399

DAC Output Voltage ..................................................................................................................... 400

DAC Output Buffer ........................................................................................................................ 400

Register Map ..................................................................................................................... 400


DAC Configuration Register – DACCFGR .................................................................................... 401

DAC Channel 0 Control Register – DAC0CR ............................................................................... 402

DAC Channel 0 Data Holding Register – DAC0DHR ................................................................... 403

DAC Channel 0 Data Output Register – DAC0DOR .................................................................... 404

DAC Channel 1 Control Register – DAC1CR ............................................................................... 405

DAC Channel 1 Data Holding Register – DAC1DHR ................................................................... 406

DAC Channel 1 Data Output Register – DAC1DOR .................................................................... 407

22 General-Purpose Timer (GPTM) ...................................................................... 408

Introduction ........................................................................................................................ 408

Features ............................................................................................................................. 409


Counter Mode ............................................................................................................................... 409

Clock Controller .............................................................................................................................411

Trigger Controller .......................................................................................................................... 413

Slave Controller ............................................................................................................................ 414

Master Controller .......................................................................................................................... 416

Channel Controller ........................................................................................................................ 417

Input Stage ................................................................................................................................... 419

Quadrature Decoder ..................................................................................................................... 421

Output Stage ................................................................................................................................. 422

Update Management .................................................................................................................... 426

Single Pulse Mode ........................................................................................................................ 427

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Cortex ® -M0+ MCU

Asymmetric PWM Mode ............................................................................................................... 429

Timer Interconnection ................................................................................................................... 429

Trigger Peripherals Start .............................................................................................................. 431

PDMA Request ............................................................................................................................. 432

Register Map ..................................................................................................................... 433


Timer Counter Configuration Register – CNTCFR ....................................................................... 434

Timer Mode Configuration Register – MDCFR ............................................................................. 435

Timer Trigger Configuration Register – TRCFR ............................................................................ 438

Timer Control Register – CTR ...................................................................................................... 439

Channel 0 Input Configuration Register – CH0ICFR .................................................................... 440




Channel 0 Output Configuration Register – CH0OCFR ............................................................... 446




Channel Control Register – CHCTR ............................................................................................. 454

Channel Polarity Configuration Register – CHPOLR .................................................................... 455

Timer PDMA/Interrupt Control Register – DICTR ......................................................................... 456

Timer Event Generator Register – EVGR ..................................................................................... 458

Timer Interrupt Status Register – INTSR ...................................................................................... 459

Timer Counter Register – CNTR................................................................................................... 462

Timer Prescaler Register – PSCR ................................................................................................ 463

Timer Counter-Reload Register – CRR ........................................................................................ 464

Channel 0 Capture/Compare Register – CH0CCR ...................................................................... 465




Channel 0 Asymmetric Compare Register – CH0ACR ................................................................. 469




23 Pulse-Width-Modulation Timer (PWM) ............................................................ 471

Introduction ........................................................................................................................ 471

Features ............................................................................................................................. 472


Counter Mode ............................................................................................................................... 472

Clock Controller ............................................................................................................................ 475



Master Controller .......................................................................................................................... 479


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Output Stage ................................................................................................................................. 480


Single Pulse Mode ........................................................................................................................ 484

Asymmetric PWM Mode ............................................................................................................... 487

Timer Interconnection ................................................................................................................... 487

Trigger Peripherals Start ............................................................................................................... 490

PDMA Request ............................................................................................................................. 490

Register Map ..................................................................................................................... 491












Timer PDMA/Interrupt Control Register – DICTR ......................................................................... 508





Timer Counter-Reload Register – CRR ........................................................................................ 513

Channel 0 Compare Register – CH0CR ....................................................................................... 513








24 Single-Channel Timer (SCTM) ......................................................................... 518

Introduction ........................................................................................................................ 518

Features ............................................................................................................................. 519


Counter Mode ............................................................................................................................... 519

Clock Controller ............................................................................................................................ 520




Input Stage ................................................................................................................................... 526

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Cortex ® -M0+ MCU

Output Stage ................................................................................................................................. 527


Register Map ..................................................................................................................... 530






Channel Input Configuration Register – CHICFR ......................................................................... 535

Channel Output Configuration Register – CHOCFR .................................................................... 537



Timer Interrupt Control Register – DICTR .................................................................................... 540





Timer Counter Reload Register – CRR ........................................................................................ 545

Channel Capture/Compare Register – CHCCR ........................................................................... 546

25 Basic Function Timer (BFTM) .......................................................................... 547

Introduction ........................................................................................................................ 547

Features ............................................................................................................................. 547


Repetitive Mode ............................................................................................................................ 548

One Shot Mode ............................................................................................................................. 549

Trigger ADC Start ......................................................................................................................... 549

Register Map ..................................................................................................................... 550


BFTM Control Register – BFTMCR .............................................................................................. 550

BFTM Status Register – BFTMSR ................................................................................................ 551

BFTM Counter Value Register – BFTMCNTR .............................................................................. 552

BFTM Compare Value Register – BFTMCMPR ........................................................................... 552

26 Watchdog Timer (WDT) .................................................................................... 553

Introduction ........................................................................................................................ 553

Features ............................................................................................................................. 554


Register Map ..................................................................................................................... 556


Watchdog Timer Control Register – WDTCR ............................................................................... 556

Watchdog Timer Mode Register 0 – WDTMR0............................................................................. 557

Watchdog Timer Mode Register 1 – WDTMR1............................................................................. 558

Watchdog Timer Status Register – WDTSR ................................................................................. 559

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Watchdog Timer Protection Register – WDTPR ........................................................................... 560

Watchdog Timer Clock Selection Register – WDTCSR ................................................................ 561

27 Real Time Clock (RTC) ..................................................................................... 562

Introduction ........................................................................................................................ 562

Features ............................................................................................................................. 562


RTC Related Register Reset ........................................................................................................ 563

Reading RTC Register .................................................................................................................. 563

Low Speed Clock Configuration ................................................................................................... 563

RTC Counter Operation ................................................................................................................ 564

Interrupt and Wakeup Control ....................................................................................................... 564

RTCOUT Output Pin Configuration ............................................................................................... 564

Register Map ..................................................................................................................... 566


RTC Counter Register – RTCCNT ................................................................................................ 566

RTC Compare Register – RTCCMP ............................................................................................. 567

RTC Control Register – RTCCR ................................................................................................... 568

RTC Status Register – RTCSR..................................................................................................... 570

RTC Interrupt and Wakeup Enable Register – RTCIWEN ............................................................ 571

28 Cyclic Redundancy Check (CRC) .................................................................... 572

Introduction ........................................................................................................................ 572

Features ............................................................................................................................. 572


CRC Computation ......................................................................................................................... 573

Byte and Bit Reversal for CRC Computation ................................................................................ 573

CRC with PDMA ........................................................................................................................... 574

Register Map ..................................................................................................................... 574


CRC Control Register – CRCCR .................................................................................................. 574

CRC Seed Register – CRCSDR ................................................................................................... 575

CRC Checksum Register – CRCCSR .......................................................................................... 576

CRC Data Register – CRCDR ...................................................................................................... 577

29 Peripheral Direct Memory Access (PDMA) ..................................................... 578

Introduction ........................................................................................................................ 578

Features ............................................................................................................................. 578


AHB Master .................................................................................................................................. 579

PDMA Channel ............................................................................................................................. 579

PDMA Request Mapping .............................................................................................................. 579

Channel Transfer .......................................................................................................................... 580

Channel Priority ............................................................................................................................ 580

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Transfer Request .......................................................................................................................... 581

Address Mode ............................................................................................................................... 581

Auto-Reload .................................................................................................................................. 582

Transfer Interrupt .......................................................................................................................... 582

Register Map ..................................................................................................................... 582


PDMA Channel n Control Register – PDMACHnCR, n = 0 ~ 5 .................................................... 584

PDMA Channel n Source Address Register – PDMACHnSADR, n = 0 ~ 5 .................................. 586

PDMA Channel n Destination Address Register – PDMACHnDADR, n = 0 ~ 5 ........................... 587

PDMA Channel n Transfer Size Register – PDMACHnTSR, n = 0 ~ 5 ......................................... 588

PDMA Channel n Current Transfer Size Register – PDMACHnCTSR, n = 0 ~ 5 ......................... 589

PDMA Interrupt Status Register – PDMAISR ............................................................................... 590

PDMA Interrupt Status Clear Register – PDMAISCR ................................................................... 591

PDMA Interrupt Enable Register – PDMAIER .............................................................................. 592

30 Divider (DIV) ...................................................................................................... 594

Introduction ........................................................................................................................ 594

Features ............................................................................................................................. 594


Register Map ..................................................................................................................... 595


Divider Control Register – CR ...................................................................................................... 595

Dividend Data Register – DDR ..................................................................................................... 596

Divisor Data Register – DSR ........................................................................................................ 596

Quotient Data Register – QTR ...................................................................................................... 597

Remainder Data Register – RMR ................................................................................................. 597

31 Liquid Crystal Display Controller (LCD) ......................................................... 598

Introduction ........................................................................................................................ 598

Features ............................................................................................................................. 599


Frequency Generator .................................................................................................................... 599

Common and Segment Driver ...................................................................................................... 601

LCD Drive Selection ..................................................................................................................... 610

High Drive Duration .......................................................................................................................611

Dead Time .....................................................................................................................................611

Double Buffer Memory .................................................................................................................. 613

LCD Low-power Modes ................................................................................................................ 613

LCD Interrupts .............................................................................................................................. 613

Flowchart ........................................................................................................................... 614

Register Map ..................................................................................................................... 615


LCD Control Register – LCDCR ................................................................................................... 616

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LCD Frame Control Register – LCDFCR ...................................................................................... 618

LCD Interrupt Enable Register – LCDIER .................................................................................... 620

LCD Status Register – LCDSR ..................................................................................................... 621

LCD Status Clear Register – LCDSCR ......................................................................................... 622

LCD RAM – LCDRAM .................................................................................................................. 623

32 AES Encrypt/Decrypt Interface (AES) ............................................................. 624

Introduction ........................................................................................................................ 624

Features ............................................................................................................................. 624


AES Mode Description .................................................................................................................. 625

AES Status ................................................................................................................................... 627

AES PDMA Interface .................................................................................................................... 627

AES Interrupt ................................................................................................................................ 628

AES Initial Vector .......................................................................................................................... 628

AES Word Swap ........................................................................................................................... 629

Register Map ..................................................................................................................... 629


AES Control Register – AESCR ................................................................................................... 630

AES Status Register – AESSR ..................................................................................................... 631

AES DMA Register – AESDMAR .................................................................................................. 632

AES Interrupt Status Register – AESISR ...................................................................................... 633

AES Interrupt Enable Register – AESIER ..................................................................................... 634

AES DATA Input Register – AESDINR.......................................................................................... 635

AES DATA Output Register – AESDOUTR ................................................................................... 635

AES Key Register n – AESKEYRn, n = 0 ~ 3 ............................................................................... 636

AES Initial Vector Register n – AESIVRn, n = 0 ~ 3 ..................................................................... 636

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Cortex ® -M0+ MCU

List of Tables

Table 1. Features and Peripheral List ..................................................................................................... 33

Table 2. Document Conventions ............................................................................................................. 35

Table 3. Register Map ............................................................................................................................. 40

Table 4. Flash Memory and Option Byte ................................................................................................. 45

Table 5. Relationship between Wait State Cycle and HCLK ................................................................... 45

Table 6. Booting Modes .......................................................................................................................... 46

Table 7. Option Byte Memory Map ......................................................................................................... 50

Table 8. Access Permission of Protected Main Flash Page .................................................................... 51

Table 9. Access Permission When Security Protection is Enabled ......................................................... 52

Table 10. FMC Register Map .................................................................................................................. 53

Table 11. RSTCU Register Map .............................................................................................................. 70

Table 12. Output Divider 2 Value Mapping.............................................................................................. 82

Table 13. Feedback Divider 2 Value Mapping......................................................................................... 83

Table 14. USB PLL Output Divider 2 Value Mapping .............................................................................. 84

Table 15. USB PLL Feedback Divider 2 Value Mapping ......................................................................... 84

Table 16. CKOUT Clock Source ............................................................................................................. 87

Table 17. CKCU Register Map ............................................................................................................... 87

Table 18. Operation Mode Definitions ....................................................................................................119

Table 19. Enter/Exit Power Saving Modes .............................................................................................119

Table 20. Power Status after System Reset ......................................................................................... 120

Table 21. PWRCU Register Map .......................................................................................................... 121

Table 22. EXTI Register Map ................................................................................................................ 130

Table 23. AFIO, GPIO and I/O Pad Control Signal True Table.............................................................. 141

Table 24. GPIO Register Map ............................................................................................................... 142

Table 25. AFIO Selection for Peripheral Map Example ......................................................................... 196

Table 26. AFIO Register Map ................................................................................................................ 196

Table 27. Exception Types .................................................................................................................... 201

Table 28. NVIC Register Map ............................................................................................................... 203

Table 29. Endpoint Characteristics ....................................................................................................... 205

Table 30. USB Data Types and Buffer Size .......................................................................................... 205

Table 31. USB Register Map ................................................................................................................ 208

Table 32. Resume Event Detection ...................................................................................................... 210

Table 33. Conditions of Holding SCL line .............................................................................................. 242

Table 34. I 2 C Register Map ................................................................................................................... 244

Table 35. I 2 C Clock Setting Example .................................................................................................... 252

Table 36. SPI Interface Format Setup ................................................................................................... 260

Table 37. SPI Mode Fault Trigger Conditions ....................................................................................... 268

Table 38. SPI Master Mode SPI_SEL Pin Status .................................................................................. 268

Table 39. SPI Register Map .................................................................................................................. 269

Table 40. Baud Rate Deviation Error Calculation – CK_USART = 40 MHz .......................................... 283


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Table 43. USART Register Map ............................................................................................................ 291

Table 44. Baud Rate Deviation Error Calculation – CK_UART = 40 MHz ............................................ 308



Table 47. UART Register Map .............................................................................................................. 310

Table 48. DI Field Based Di Encoded Decimal Values ......................................................................... 319

Table 49. FI Field Based F i

Encoded Decimal Values .......................................................................... 319

Table 50. Possible ETU Values Obtained with the Fi/Di Ratio .............................................................. 319

Table 51. SCI Register Map ................................................................................................................. 326

Table 52. Recommend FS List @ 8 MHz PCLK ................................................................................... 342

Table 53. Recommend FS List @ 48 MHz PCLK ................................................................................. 342

Table 54. I 2 S Register Map .................................................................................................................. 351

Table 55. Data format in ADCDR [15:0] ................................................................................................ 367

Table 56. A/D Converter Register Map ................................................................................................. 369

Table 57. CMP Register Map ................................................................................................................ 391

Table 58. DAC Register Map ................................................................................................................ 400

Table 59. Counting Direction and Encoding Signals ............................................................................. 422

Table 60. Compare Match Output Setup .............................................................................................. 423

Table 61. GPTM Register Map ............................................................................................................. 433

Table 62. GPTM Internal Trigger Connection ....................................................................................... 438


Table 64. PWM Register Map ............................................................................................................... 491

Table 65. PWM Internal Trigger Connection ......................................................................................... 496


Table 67. SCTM Register Map .............................................................................................................. 530

Table 68. BFTM Register Map .............................................................................................................. 550

Table 69. Watchdog Timer Register Map .............................................................................................. 556

Table 70. LSE Startup Mode Operating Current and Startup Time ....................................................... 563

Table 71. RTCOUT Output Mode and Active Level Setting .................................................................. 565

Table 72. RTC Register Map................................................................................................................. 566

Table 73. CRC Register Map ................................................................................................................ 574

Table 74. PDMA Channel Assignments ................................................................................................ 580

Table 75. PDMA Address Modes .......................................................................................................... 581

Table 76. PDMA Register Map .............................................................................................................. 582

Table 77. DIV Register Map .................................................................................................................. 595

Table 78. Frame Rate Calculation Example – CK_LCD 32 kHz, Frame Rate 30 Hz ............................ 600

Table 79. Frame Rate Calculation Example – CK_LCD 32 kHz, Frame Rate 60 Hz ............................ 600

Table 80. Frame Rate Calculation Example – CK_LCD 32 kHz, Frame Rate 100 Hz .......................... 600

Table 81. Frame Rate Calculation Example – CK_LCD 1 MHz, Frame Rate 30 Hz ............................ 600

Table 82. Frame Rate Calculation Example – CK_LCD 1 MHz, Frame Rate 60 Hz ............................ 600

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Table 83. Frame Rate Calculation Example – CK_LCD 1 MHz, frame rate 100 Hz ............................. 601

Table 84. Dead Time Duration ...............................................................................................................611

Table 85. LCD in Power Saving Modes ................................................................................................ 613

Table 86. LCD Interrupts ....................................................................................................................... 613

Table 87. LCD Register Map ................................................................................................................. 615

Table 88. LCDRAM Register Map ......................................................................................................... 623

Table 89. AES Register Map ................................................................................................................. 629

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Cortex ® -M0+ MCU

List of Figures

Figure 1. Block Diagram ......................................................................................................................... 34

Figure 2. Cortex ® -M0+ Block Diagram .................................................................................................... 37

Figure 3. Bus Architecture ...................................................................................................................... 38

Figure 4. Memory Map ............................................................................................................................ 39

Figure 5. Flash Memory Controller Block Diagram ................................................................................. 43

Figure 6. Flash Memory Map .................................................................................................................. 44

Figure 7. Vector Remapping ................................................................................................................... 46

Figure 8. Page Erase Operation Flowchart ............................................................................................ 47

Figure 9. Mass Erase Operation Flowchart ............................................................................................ 48

Figure 10. Word Programming Operation Flowchart .............................................................................. 49

Figure 11. RSTCU Block Diagram .......................................................................................................... 69

Figure 12. Power-On Reset Sequence ................................................................................................... 70

Figure 13. CKCU Block Diagram ............................................................................................................ 78

Figure 14. External Crystal, Ceramic and Resonators for HSE .............................................................. 79

Figure 15. HSI Auto Trimming Block Diagram ........................................................................................ 81

Figure 16. PLL Block Diagram ................................................................................................................ 82

Figure 17. USB PLL Block Diagram ........................................................................................................ 83

Figure 18. External Crystal, Ceramic and Resonators for LSE ............................................................. 85

Figure 19. PWRCU Block Diagram ........................................................................................................115

Figure 20. Power-On Reset / Power-Down Reset Waveform ................................................................117

Figure 21. EXTI Block Diagram ............................................................................................................ 128

Figure 22. EXTI Wakeup Event Management ...................................................................................... 129

Figure 23. EXTI Interrupt Debounce Function ...................................................................................... 130

Figure 24. GPIO Block Diagram ........................................................................................................... 139

Figure 25. AFIO/GPIO Control Signal ................................................................................................... 141

Figure 26. AFIO Block Diagram ............................................................................................................ 194

Figure 27. EXTI Channel Input Selection ............................................................................................. 195

Figure 28. USB Block Diagram ............................................................................................................. 204

Figure 29. Endpoint Buffer Allocation Example ..................................................................................... 206

Figure 30. Double-buffering Operation Example .................................................................................. 207

Figure 31. I 2 C Module Block Diagram ................................................................................................... 232

Figure 32. START and STOP Condition ............................................................................................... 234

Figure 33. Data Validity ......................................................................................................................... 234

Figure 34. 7-bit Addressing Mode ......................................................................................................... 235

Figure 35. 10-bit Addressing Write Transmit Mode .............................................................................. 235

Figure 36. 10-bits Addressing Read Receive Mode ............................................................................ 235

Figure 37. I 2 C Bus Acknowledge .......................................................................................................... 236

Figure 38. Clock Synchronization during Arbitration ............................................................................. 236

Figure 39. Two Masters Arbitration Procedure...................................................................................... 237

Figure 40. Master Transmitter Timing Diagram .................................................................................... 239

Figure 41. Master Receiver Timing Diagram ........................................................................................ 240

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Figure 42. Slave Transmitter Timing Diagram ...................................................................................... 241

Figure 43. Slave Receiver Timing Diagram .......................................................................................... 242

Figure 44. SCL Timing Diagram ............................................................................................................ 252

Figure 45. SPI Block Diagram .............................................................................................................. 258

Figure 46. SPI Single Byte Transfer Timing Diagram – CPOL = 0, CPHA = 0 ...................................... 260

Figure 47. SPI Continuous Data Transfer Timing Diagram – CPOL = 0, CPHA = 0 ............................. 260


Figure 49. SPI Continuous Transfer Timing Diagram – CPOL = 0, CPHA = 1 ...................................... 261





Figure 54. SPI Dual Mode Bit Sequence – CPOL = 0, CPHA = 0, DFL = 0x8 (16-bit), MSB Transmitted

First ........................................................................................................................................................ 264

Figure 55. SPI Dual Mode Bit Sequence – CPOL = 0, CPHA = 1, DFL = 0x8 (16-bit), MSB Transmitted

First ........................................................................................................................................................ 264

Figure 56. SPI Dual Mode Bit Sequence – CPOL = 1, CPHA = 0, DFL = 0x8 (16-bit) , MSB Transmitted

First ........................................................................................................................................................ 265

Figure 57. SPI Dual Mode Bit Sequence – CPOL = 1, CPHA = 1, DFL = 0x8 (16-bit) , MSB Transmitted

First ........................................................................................................................................................ 265

Figure 58. SPI Dual Mode Data Read Example – CPOL = 1, CPHA = 1 .............................................. 266

Figure 59. SPI Multi-Master Slave Environment ................................................................................... 267

Figure 60. USART Block Diagram ........................................................................................................ 280

Figure 61. USART Serial Data Format ................................................................................................. 282

Figure 62. USART Clock CK_USART and Data Frame Timing ............................................................ 282

Figure 63. Hardware Flow Control between 2 USARTs ........................................................................ 284

Figure 64. USART RTS Flow Control ................................................................................................... 284

Figure 65. USART CTS Flow Control ................................................................................................... 285

Figure 66. IrDA Modulation and Demodulation ..................................................................................... 285

Figure 67. USART I/O and IrDA Block Diagram ................................................................................... 287

Figure 68. RS485 Interface and Waveform .......................................................................................... 288

Figure 69. USART Synchronous Transmission Example ..................................................................... 289

Figure 70. 8-bit Format USART Synchronous Waveform ..................................................................... 290

Figure 71. UART Block Diagram ........................................................................................................... 306

Figure 72. UART Serial Data Format .................................................................................................... 307

Figure 73. UART Clock CK_UART and Data Frame Timing ................................................................. 308

Figure 74. SCI Block Diagram .............................................................................................................. 317

Figure 75. Character Frame and Compensation Mode ........................................................................ 320

Figure 76. Guard Time Duration ........................................................................................................... 321

Figure 77. Character and Block Waiting Time Duration – CWT and BWT ............................................ 322

Figure 78. SCI Card Detection Diagram ............................................................................................... 323

Figure 79. SCI Interrupt Structure ......................................................................................................... 325

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Figure 80. I 2 S Block Diagram ................................................................................................................ 339

Figure 81. Simple I 2 S Master/Slave Configuration ................................................................................ 340

Figure 82. I 2 S Clock Generator Diagram .............................................................................................. 341

Figure 83. I 2 S-justified Stereo Mode Waveforms .................................................................................. 343

Figure 84. I 2 S-justified Stereo Mode Waveforms (32-bit Channel Enabled) ......................................... 343

Figure 85. Left-justified Stereo Mode Waveforms ................................................................................. 344

Figure 86. Left-justified Stereo Mode Waveforms (32-bit Channel Enabled) ........................................ 344

Figure 87. Right-justified Stereo Mode Waveforms .............................................................................. 345

Figure 88. Right-justified Stereo Mode Waveforms (32-bit Channel Enabled) ..................................... 345

Figure 89. I 2 S-justified Mono Mode Waveforms .................................................................................... 346

Figure 90. I 2 S-justified Mono Mode Waveforms (32-bit Channel Enabled) ........................................... 346

Figure 91. Left-justified Mono Mode Waveforms .................................................................................. 347

Figure 92. Left-justified Mono Mode Waveforms (32-bit Channel Enabled) ......................................... 347

Figure 93. Right-justified Mono Mode Waveforms ................................................................................ 348

Figure 94. Right-justified Mono Mode Waveforms (32-bit Channel Enabled) ....................................... 348

Figure 95. I 2 S-justified Repeat Mode Waveforms ................................................................................. 349

Figure 96. I 2 S-justified Repeat Mode Waveforms (32-bit Channel Enabled) ........................................ 349

Figure 97. FIFO Data Content Arrangement for Various Modes ........................................................... 350

Figure 98. ADC with V

REF

Block Diagram .............................................................................................. 361

Figure 99. One Shot Conversion Mode ................................................................................................ 364

Figure 100. Continuous Conversion Mode ........................................................................................... 364

Figure 101. Discontinuous Conversion Mode ....................................................................................... 366

Figure 102. Voltage Reference Generator Block Diagram ................................................................... 369

Figure 103. Comparator Block Diagram ............................................................................................... 388

Figure 104. Comparator Voltage Reference Block Diagram ................................................................. 389

Figure 105. Comparator Interrupt Signals ............................................................................................ 390

Figure 106. Comparator Wakeup Signal ............................................................................................... 390

Figure 107. DAC Channel Block Diagram ............................................................................................ 397

Figure 108. DAC Data Transfer Timing Diagram .................................................................................. 398

Figure 109. 12-bit Data Transfer in Asynchronous Mode ..................................................................... 398

Figure 110. 8-bit Data Transfer in Asynchronous Mode ........................................................................ 399

Figure 111. 12-bit Data Transfer in Synchronous Mode ........................................................................ 399

Figure 112. 8-bit Data Transfer in Synchronous Mode ......................................................................... 400

Figure 113. GPTM Block Diagram ........................................................................................................ 408

Figure 114. Up-counting Example......................................................................................................... 410

Figure 115. Down-counting Example .................................................................................................... 410

Figure 116. Center-aligned Counting Example ......................................................................................411

Figure 117. GPTM Clock Source Selection .......................................................................................... 412

Figure 118. Trigger Controller Block ..................................................................................................... 413

Figure 119. Slave Controller Diagram ................................................................................................... 414

Figure 120. GPTM in Restart Mode ...................................................................................................... 414

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Cortex ® -M0+ MCU

Figure 121. GPTM in Pause Mode ....................................................................................................... 415

Figure 122. GPTM in Trigger Mode ...................................................................................................... 415

Figure 123. Master GPTMn and Slave GPTMm/TMm Connection ...................................................... 416

Figure 124. MTO Selection ................................................................................................................... 416

Figure 125. Capture/Compare Block Diagram ...................................................................................... 417

Figure 126. Input Capture Mode ........................................................................................................... 418

Figure 127. PWM Pulse Width Measurement Example ........................................................................ 419

Figure 128. Channel 0 and Channel 1 Input Stages ............................................................................. 419

Figure 129. Channel 2 and Channel 3 Input Stages ............................................................................. 420

Figure 130. TI0 Digital Filter Diagram with N = 2 .................................................................................. 420

Figure 131. Input Stage and Quadrature Decoder Block Diagram ....................................................... 421

Figure 132. Both TI0 and TI1 Quadrature Decoder Counting ............................................................... 422

Figure 133. Output Stage Block Diagram ............................................................................................. 422

Figure 134. Toggle Mode Channel Output Reference Signal (CHxPRE = 0) ....................................... 423


Figure 136. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode .......... 424

Figure 137. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ..... 425

Figure 138. PWM Mode Channel Output Reference Signal and Counter in Centre-aligned Mode ...... 425

Figure 139. Update Event Setting Diagram .......................................................................................... 426

Figure 140. Single Pulse Mode ............................................................................................................. 427

Figure 141. Immediate Active Mode Minimum Delay ........................................................................... 428

Figure 142. Asymmetric PWM Mode versus Center-Aligned Counting Mode ...................................... 429

Figure 143. Pausing PWM0 using the GPTM CH0OREF Signal .......................................................... 430

Figure 144. Triggering PWM0 with GPTM Update Event ..................................................................... 430

Figure 145. Trigger GPTM and PWM0 with the GPTM CH0 Input ....................................................... 431

Figure 146. GPTM PDMA Mapping Diagram ........................................................................................ 432

Figure 147. PWM Block Diagram ......................................................................................................... 471

Figure 148. Up-counting Example ........................................................................................................ 472

Figure 149. Down-counting Example .................................................................................................... 473

Figure 150. Center-aligned Counting Example ..................................................................................... 474

Figure 151. PWM Clock Source Selection ............................................................................................ 475


Figure 153. Slave Controller Diagram .................................................................................................. 477

Figure 154. PWM in Restart Mode ....................................................................................................... 477

Figure 155. PWM in Pause Mode ......................................................................................................... 478

Figure 156. PWM in Trigger Mode ........................................................................................................ 478

Figure 157. Master PWMn and Slave PWMm/TMm Connection .......................................................... 479

Figure 158. MTO Selection ................................................................................................................... 479

Figure 159. Compare Block Diagram ................................................................................................... 480



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Cortex ® -M0+ MCU


Figure 163. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode .......... 482

Figure 164. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ..... 483

Figure 165. PWM Mode Channel Output Reference Signal and Counter in Center-aligned Mode ...... 483


Figure 167. Single Pulse Mode ............................................................................................................. 485

Figure 168. Immediate Active Mode Minimum Delay ........................................................................... 486

Figure 169. Asymmetric PWM Mode versus Center-aligned Counting Mode ....................................... 487

Figure 170. Pausing PWM1 using the PWM0 CH0OREF Signal ......................................................... 488

Figure 171. Triggering PWM1 with PWM0 Update Event ..................................................................... 488

Figure 172. Trigger PWM0 and PWM1 with the PWM0 Timer Enable Signal ...................................... 489

Figure 173. PWM PDMA Mapping Diagram ......................................................................................... 490

Figure 174. SCTM Block Diagram ........................................................................................................ 518

Figure 175. Up-counting Example ........................................................................................................ 519

Figure 176. SCTM Clock Source Selection .......................................................................................... 520


Figure 178. Slave Controller Diagram .................................................................................................. 522

Figure 179. SCTM in Restart Mode ...................................................................................................... 522

Figure 180. SCTM in Pause Mode ....................................................................................................... 523

Figure 181. SCTM in Trigger Mode ...................................................................................................... 523

Figure 182. Capture/Compare Block Diagram ...................................................................................... 524

Figure 183. Input Capture Mode ........................................................................................................... 525

Figure 184. Channel Input Stages ........................................................................................................ 526

Figure 185. TI Digital Filter Diagram with N = 2 .................................................................................... 526


Figure 187. Toggle Mode Channel Output Reference Signal (CHPRE = 0) ......................................... 528

Figure 188. Toggle Mode Channel Output Reference Signal (CHPRE = 1) ......................................... 528

Figure 189. PWM Mode Channel Output Reference Signal ................................................................. 529


Figure 191. BFTM Block Diagram ........................................................................................................ 547

Figure 192. BFTM – Repetitive Mode ................................................................................................... 548

Figure 193. BFTM – One Shot Mode .................................................................................................... 549

Figure 194. BFTM – One Shot Mode Counter Updating ...................................................................... 549

Figure 195. Watchdog Timer Block Diagram ....................................................................................... 553

Figure 196. Watchdog Timer Behavior ................................................................................................. 555

Figure 197. RTC Block Diagram ........................................................................................................... 562

Figure 198. CRC Block Diagram .......................................................................................................... 572

Figure 199. CRC Data Bit and Byte Reversal Example ........................................................................ 573

Figure 200. PDMA Block Diagram ........................................................................................................ 578

Figure 201. PDMA Request Mapping Architecture ............................................................................... 579

Figure 202. PDMA Channel Arbitration and Scheduling Example ........................................................ 581

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Cortex ® -M0+ MCU

Figure 203. Divider Functional Diagram ............................................................................................... 594

Figure 204. LCD Controller Block Diagram .......................................................................................... 598

Figure 205. Type A vs Type B Waveform – 1/3 Bias, 1/3 Duty.............................................................. 601

Figure 206. Static Waveforms ............................................................................................................... 602

Figure 207. 1/2 Duty, 1/2 Bias, Type A Waveforms ............................................................................... 603




Figure 211. 1/6 Duty, 1/3 Bas, Type A Waveforms ................................................................................ 607



Figure 214. LCD Voltage Control .......................................................................................................... 610

Figure 215. High Drive Duration ............................................................................................................611

Figure 216. Dead Time ......................................................................................................................... 612

Figure 217. Flowchart Example ............................................................................................................ 614

Figure 218. AES Block Diagram ........................................................................................................... 624

Figure 219. AES-ECB Mode ................................................................................................................. 625

Figure 220. AES-CBC Mode ................................................................................................................. 626

Figure 221. AES-CTR Mode ................................................................................................................. 627

Figure 222. AES Interrupt ..................................................................................................................... 628

Figure 223. Initial Vector for CTR Mode ............................................................................................... 628

Figure 224. AES Word Swap Function ................................................................................................. 629

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HT32F5828

Cortex ® -M0+ MCU

1

Introduction

Overview

This user manual provides detailed information including how to use the HT32F5828 device, system and bus architecture, memory organization and peripheral instructions. The target audiences for this document are software developers, application developers and hardware developers. For more information regarding pin assignment, package and electrical characteristics, please refer to the HT32F5828 datasheet.

The device is a high performance and low power consumption 32-bit microcontroller based around an Arm ® Cortex ® -M0+ processor core. The Cortex ® -M0+ is a next-generation processor core which is tightly coupled with Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug support.

The device operates at a frequency of up to 60 MHz with a Flash accelerator to obtain maximum efficiency. It provides up to 128 KB of embedded Flash memory for code/data storage and up to

16 KB of embedded SRAM memory for system operation and application program usage. A variety of peripherals, such as USB2.0 FS, PDMA, AES-128, Hardware Divider (DIV), SPI, I 2 S,

USART, UART, SCI, I 2 C, GPTM, PWM, SCTM, BFTM, CRC-16/32, RTC, WDT, ADC, CMP,

DAC, LCD and SW-DP (Serial Wire Debug Port), etc., are also implemented in the device. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, which is an especially important consideration in low power applications.

The above features ensure that the device is suitable for use in a wide range of applications, especially in areas such as white goods application controllers, power monitors, alarm systems, consumer products, handheld equipment, data logging applications, motor controllers and so on.

Features

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Core

● 32-bit Arm ® Cortex ® -M0+ processor core

● Up to 60 MHz operating frequency

● Single-cycle multiplication

● Integrated Nested Vectored Interrupt Controller (NVIC)

● 24-bit SysTick timer

On-Chip Memory

● Up to 128 KB on-chip Flash memory for instruction/data and option storage

● Up to 16 KB on-chip SRAM

● Supports multiple booting modes

Flash Memory Controller – FMC

● Flash accelerator to obtain maximum efficiency

● 32-bit word programming with In System Programming (ISP) and In Application

Programming (IAP)

● Flash protection capability to prevent illegal access

Rev. 1.00 28 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

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Reset Control Unit – RSTCU

● Supply supervisor: Power-On Reset / Power-Down Reset (POR/PDR), Brown-Out Detector

(BOD) and Programmable Low Voltage Detector (LVD)

Clock Control Unit – CKCU

● External 4 to 16 MHz crystal oscillator

● External 32,768 Hz crystal oscillator

● Internal 8 MHz RC oscillator trimmed to ±2 % accuracy at 3.3 V operating voltage and 25 ºC operating temperature

● Internal 32 kHz RC oscillator

● Integrated system clock PLL and USB PLL

● Independent clock divider and gating bits for peripheral clock sources

Power Management – PWRCU

●

●

Single V

Integrated 1.5 V LDO regulator for CPU core, peripheral and memory power supply

● V

DD

DD

power supply: 1.65 V to 3.6 V

●

power supply for RTC

Three power domains: V

DD

, V

LCD

and 1.5 V power domains

● Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2, Power-Down modes

External Interrupt/Event Controller – EXTI

● Up to 16 EXTI lines with configurable trigger source and type

● All GPIO pins can be selected as EXTI trigger source

● Source trigger type can be high level, low level, negative edge, positive edge or both edges

● Individual interrupt enable, wakeup enable and status bits for each EXTI line

● Software interrupt trigger mode for each EXTI line

● Integrated deglitch filter for short pulse blocking

I/O Ports – GPIO

● Up to 67 GPIOs

● Port A, B, C, D, E are mapped on 16 external interrupts – EXTI

● Almost all I/O pins have configurable output driving current

Universal Serial Bus Device Controller – USB

● Complies with USB 2.0 full-speed (12 Mbps) specification

● On-chip USB full-speed transceiver

● 1 control endpoint (EP0) for control transfer

● 3 single-buffered endpoints for bulk and interrupt transfer

● 4 double-buffered endpoints for bulk, interrupt and isochronous transfer

● 1,024 bytes EP_SRAM used as the endpoint data buffers

Inter-integrated Circuit – I 2 C

● Supports both master and slave modes with a frequency of up to 1 MHz

● Provides an arbitration function and clock synchronization

● Supports 7-bit and 10-bit addressing modes and general call addressing

● Supports slave multi-addressing mode with maskable address

Serial Peripheral Interface – SPI

● Supports both master and slave mode

● Frequency of up to (f

PCLK

/2) MHz for master mode and (f

● FIFO Depth: 8 levels

● Multi-master and multi-slave operation

PCLK

/3) MHz for slave mode

Rev. 1.00 29 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

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Universal Synchronous Asynchronous Receiver Transmitter – USART

●

●

Supports both asynchronous and clocked synchronous serial communication modes

Asynchronous operating baud rate clock frequency of up to (f operating baud rate clock frequency of up to (f

PCLK

/8) MHz

PCLK

/16) MHz and synchronous

● Capability of full duplex communication

● Fully programmable serial communication characteristics including word length, parity bit, stop bit and bit order

● Error detection: Parity, overrun and frame error

● Supports Auto hardware flow control mode – RTS, CTS

●

● RS485 mode with output enable control

●

IrDA SIR encoder and decoder

FIFO Depth: 8-level for both receiver and transmitter

Universal Asynchronous Receiver Transmitter – UART

● Asynchronous serial communication operating baud rate clock frequency of up to (f

PCLK

/16) MHz

● Capability of full duplex communication

● Fully programmable serial communication characteristics including word length, parity bit, stop bit and bit order

● Error detection: Parity, overrun and frame error

Smart Card Interface – SCI

● Supports ISO 7816-3 standard

● Character Transfer mode

● Single transmit buffer and single receive buffer

● 11-bit ETU (Elementary Time Unit) counter

● 9-bit guard time counter

●

● Parity generation and check functions

●

24-bit general purpose waiting time counter

Automatic character retry on parity error detection in transmission and reception modes

Inter-IC Sound – I 2 S

● Master or Slave mode

● Mono and Stereo

● I 2 S-justified, Left-justified and Right-justified mode

● 8/16/24/32-bit sample size with 32-bit channel extended

● 8 × 32-bit TX & RX FIFO with PDMA supported

● 8-bit Fractional Clock Divider with rate control

Analog to Digital Converter – ADC

● 12-bit SAR ADC engine

● Up to 1 Msps conversion rate

● Up to 10 external analog input channels

Comparator – CMP

● Rail-to-rail comparators

● Each comparator has configurable negative input used for flexible voltage selection

♦ External CN pin

♦ Internal 8-bit CVR output

● Programmable hysteresis

● Programming respond speed and power consumption

● Comparator output can be routed to I/O or to multiple timers or ADC trigger inputs

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

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● 8-bit CVR can be configurable to dedicated I/O for voltage reference

● Comparator has interrupt generation capability with wakeup from Sleep, Deep-Sleep1 or

Deep-Sleep2 mode through the EXTI controller

Digital to Analog Converter – DAC

● Two DAC converters each has one output channel

● 12-bit or 8-bit resolution

● Maximum 500 ksps conversion updating rate

● Dual DAC channels for implementing simultaneous conversion

● Supports voltage output buffer mode and bypass voltage output buffer mode

● Reference voltage from internal voltage reference V

REF

or V

DDA

General-Purpose Timer – GPTM

● 16-bit up/down auto-reload counter

● Up to 4 independent channels for each timer

● 16-bit programmable prescaler allowing counter clock frequency division by any factor between 1 and 65536

● Input Capture function

● Compare Match Output

● PWM waveform generation with Edge-aligned and Center-aligned Counting Modes

● Single Pulse Mode Output

● Encoder interface controller with two inputs using quadrature decoder

Pulse-Width-Modulation Timer – PWM

● 16-bit up/down auto-reload counter

● Up to 4 independent channels for each timer

● 16-bit programmable prescaler allowing counter clock frequency division by any factor between 1 and 65536


● PWM waveform generation with Edge-aligned and Center-aligned Counting Modes


Single-Channel Timer – SCTM

● 16-bit auto-reload up-counter

● One channel for each timer

● 16-bit programmable prescaler allowing counter clock frequency division by any factor between

1 and 65536



● PWM waveform generation with Edge-aligned

Basic Function Timer – BFTM

● 32-bit compare/match count-up counter – no I/O control features

● One shot mode – counting stops after a match condition

● Repetitive mode – restart counter after a match condition

Watchdog Timer – WDT

● 12-bit down-counter with a 3-bit prescaler

● Reset event for the system

● Programmable watchdog timer window function

● Registers write protection function

Rev. 1.00 31 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

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Real Time Clock – RTC

● 24-bit up-counter with a programmable prescaler

● Alarm function

● Interrupt and wakeup event

Cyclic Redundancy Check – CRC

●

●

Supports CRC16 polynomial: 0x8005, X 16 + X 15

Supports CCITT CRC16 polynomial: 0x1021, X

+ X

16

2 + 1

+ X 12 + X 5 + 1

● Supports IEEE-802.3 CRC32 polynomial: 0x04C11DB7, X 32 + X 26 + X 23 + X 22 + X 16 + X 12

+ X 11 + X 10 + X 8 + X 7 + X 5 + X 4 + X 2 + X + 1

● Supports 1’s complement, byte reverse and bit reverse operation on data and checksum

● Supports byte, half-word and word data size

● Programmable CRC initial seed value

● CRC computation done in 1 AHB clock cycle for 8-bit data and 4 AHB clock cycles for 32-bit data

● Supports PDMA to complete a CRC computation of a block of memory

Peripheral Direct Memory Access – PDMA

● 6 channels with trigger source grouping

● 8/16/32-bit width data transfer

● Supports linear address, circular address and fixed address mode

● 4-level programmable channel priority

● Auto reload mode

● Supports trigger sources:

ADC, SPI, USART, UART, SCI, I 2 C, I 2 S, GPTM, PWM, AES-128 and software request

Divider – DIV

● Signed/unsigned 32-bit divider

● Operation in 8 clock cycles, load in 1 clock cycle

● Division by zero error flag

Liquid Crystal Display Controller – LCD

● LCD Driver function with Static, 1/2, 1/3, 1/4, 1/6 and 1/8 duty

● LCD Driver function with Static, 1/2, 1/3 or 1/4 bias

● Supports R type bias type

● Clock source can be selected from the LSI (32 kHz), LSE (32.768 kHz) or a clock ratio of either the HSI or HSE

● Contains three embedded LCD bias reference resistor ladders

● Double buffered memory

● Software selectable charge pump voltage

● Programmable dead time between frames – up to 7/2 phase periods for type A waveforms and

7 phase periods for type B waveforms

● Software selectable waveform type: type A or type B waveform

● LCD frame interrupt

● Blink capability: Up to 1, 2, 3, 4, 6, 8 or all pixels which can be programmed to blink

Advanced Encryption Standard – AES-128

● Supports AES Encrypt / Decrypt Function

● Supports AES ECB/CBC/CTR mode

● Supports Key Size of 128 bits

● Supports 4 words of Initial Vector for CBC and CTR mode

● 4 × 32 bits AES data buffer – each IN and OUT FIFO capacity

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

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● Supports Word Data Swap Function

● Supports PDMA Interface

Debug Support

● Serial Wire Debug Port – SW-DP

● 4 comparators for hardware breakpoint or code/literal patch

● 2 comparators for hardware watchpoints

Package and Operation Temperature

● 48/64/80-pin LQFP packages

● Operation temperature range: -40 ºC to + 85 ºC

Device Information

Table 1. Features and Peripheral List

Peripherals

Main Flash (KB)

Option Bytes Flash (KB)

SRAM (KB)

Timers

Communication

GPTM

PWM

SCTM

BFTM

WDT

RTC

USB

SPI

USART

UART

I 2 C

I 2 S

SCI (ISO7816-3)

PDMA

AES-128

Hardware Divider

LCD (COM × SEG)

CRC-16/32

EXTI

12-bit ADC

Number of channels

Comparator

DAC

GPIO

CPU frequency

Operating voltage

Operating temperature

Package

HT32F5828

127

1

2

2

1

1

2

2

2

1

1

16

1

2

1

2

6 channels

1

1

Up to 8 × 33, 6 × 35, 4 × 37

1

16

1

Max. 10 Channels

2

2

Up to 67

Up to 60 MHz

1.65 V ~ 3.6 V

-40 °C ~ 85 °C

48/64/80-pin LQFP

Rev. 1.00 33 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Block Diagram

SWCLK SWDIO

AF

PA ~ PD[15:0], PE[3:0]

SW-DP

Cortex ® -M0+

Processor

NVIC

PDMA

6 Channels

TX, RX

RTS/TXE

CTS/SCK

TX, RX

CH0~CH3

SCTM

MCLK, BCLK

WS, SDO, SDI

ADC_IN0

ADC_IN11

DAC0O

DAC1O

CN0, CP0

COUT0

CN1, CP1

COUT1

VDDA

VSSA

12-bit

SAR ADC

DAC0 ~1

CMP

CMP0 ~1

CMP

Powered by V

DDA

Powered by V

DD15

Power supply:

Bus:

Control signal:

Alternate function: AF

Figure 1. Block Diagram

BOOT

AF

Flash Memory

Interface

PDMA

Control

Registers

AHB

Peripherals

FMC

Control

Registers

SRAM

Controller

AHB to APB

Bridge

Powered by V

DD15

Flash

Memory

CKCU/RSTCU

Control Registers

USB

Control/Data

Registers

SRAM

POR

/PDR

HSE

4 ~ 16 MHz

ULDO

1.5 V

LDO

1.5 V

BOD

LVD

Powered by V

DD

1.5 V

POR

PLL f

Max

: 60 MHz

USB PLL f: 48 MHz

HSI

8 MHz

VDD

VSS

XTALIN

XTALOUT

CLDO

CAP.

DP

DM

MOSI, MISO

SCK, SEL

SDA

SCL

CH0~CH3

RTC

PWRCU

LSI

32 kHz

LSE

32,768 Hz

Powered by V

DD

AF

X32KIN

X32KOUT

Powered by V

LCD

CLK, DIO,

DET

SEGx

COMx

VLCD

RTCOUT

VDD

VSS

WAKEUP nRST

Rev. 1.00 34 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

2

Document Conventions

The conventions used in this document are shown in the following table.

Table 2. Document Conventions

0x

Notation Example

0x5a05

Description

The number string with a 0x prefix indicates a hexadecimal number.

0xnnnn_nnnn b

NAME [n]

NAME [m:n]

X

RW

RO

RC

WC

W0C

0x2000_0100 b0101

ADDR [5]

ADDR [11:5]

32-bit Hexadecimal address or data.

The number string with a lowercase b prefix indicates a binary number.

Specific bit of NAME. NAME can be a register or field of register. For example, ADDR [5] means bit 5 of ADDR register (field).

Specific bits of NAME. NAME can be a register or field of register. For example, ADDR [11:5] means bit 11 to 5 of

ADDR register (field).

Don’t care notation which means any value is allowed.

b10X1

19

HSEEN

18

PLLEN

RW 0 RW 0

3

HSIRDY

2

RO 1 RO 0 no effect.

1

PDF

0

PORF

RC 0 RC 1

Software can only read this bit. A read operation will clear it to 0 automatically.

3 2

CKSF

WC 0 WC 0

1 0

MIF

W0C 0

Software can read and write to this bit.

Software can read this bit or clear it by writing 1. Writing 0 to it will have no effect.

Software can read this bit or clear it by writing 0. Writing 1 to it will have no effect.

WO

Reserved

Word

Half-word

Byte

1

CH1CCG

0

WO 0 WO 0 returns 0.

7 6

Reserved

Reserved bit(s) for future use. Data read from these bits is not well defined and should be treated as random data.

Normally these reserved bits should be set to a 0 value.

Note that reserved bit must be kept at reset value.

Data length of a word is 32-bit.

Data length of a half-word is 16-bit.

Data length of a byte is 8-bit.

Rev. 1.00 35 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

3

System Architecture

The system architecture of the device that includes the Arm ® Cortex ® -M0+ processor, bus architecture and memory organization will be described in the following sections. The

Cortex ® -M0+ is a next generation processor core which offers many new features. Integrated and advanced features make the Cortex ® -M0+ processor suitable for market products that require microcontrollers with high performance and low power consumption. In brief, The Cortex ® -M0+ processor includes the AHB-Lite bus interface. All memory accesses of the Cortex processor are executed on the AHB-Lite bus according to the different purposes and the target memory spaces. The memory organization uses a Harvard architecture, pre-defined memory map and up to 4 GB of memory space, making the system flexible and extendable.

® -M0+

Arm ® Cortex ® -M0+ Processor

The Cortex ® -M0+ processor is a very low gate count, highly energy efficient processor that is intended for microcontroller and deeply embedded applications that require an area optimized, low power processor. The processor is based on the ARMv6-M architecture and supports Thumb

Some system peripherals listed below are also provided by Cortex ® -M0+:

® instruction sets, single-cycle I/O ports, hardware multiplier and low latency interrupt respond time.

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Internal Bus Matrix connected with AHB-Lite Interface, Single-cycle I/O ports and Debug Accesses

Port (DAP)

Nested Vectored Interrupt Controller (NVIC)

Optional Wakeup Interrupt Controller (WIC)

Breakpoint and Watchpoint Unit

Optional Memory Protection Unit (MPU)

Serial Wire debug Port (SW-DP)

Optional Micro Trace Buffer Interface (MTB)

The following figure shows the Cortex ® -M0+ processor block diagram. For more information, refer to the Arm ® Cortex ® -M0+ Technical Reference Manual.

Rev. 1.00 36 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Interrupts

Cortex ® -M0+ Components

Execution Trace Interface

Cortex ® -M0+ Processor

Nested

Vectored

Interrupt

Controller

(NVIC)

Cortex ® -M0+

Processor

Core

Debug

‡ Breakpoint and

Watchpoint

Unit

‡ Wakeup

Interrupt

Controller

(WIC)

‡ Memory

Protection

Unit

‡ Debugger

Interface

Bus Matrix

‡ Optional Component

Figure 2. Cortex ® -M0+ Block Diagram

AHB-Lite Interface to System

‡ Single-cycle

I/O Port

‡ Debug

Access Port

(DAP)

‡ Serial Wire

Debug Port

Bus Architecture

The HT32F5828 device consists of two masters and four slaves in the bus architecture. The system bus and Peripheral Direct Memory Access (PDMA) are the masters while the internal SRAM access bus, the internal Flash memory access bus, the AHB peripheral access bus and the AHB to

APB bridge are the slaves. The single 32-bit AHB-Lite system interface provides simple integration to all system regions including the internal SRAM region and the peripheral region. All of the master buses are based on 32-bit Advanced High-performance Bus-Lite (AHB-Lite) protocol. The following figure shows the bus architecture of the HT32F5828 device.

Rev. 1.00 37 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

GPIO

Cortex ® -M0+

Processor

NVIC

PDMA

6 Channels

Flash Memory

Interface

PDMA

Control

Registers

FMC

Control

Registers

SRAM Controller

Flash Memory

CKCU/RSTCU

Control Registers

USB

Control/Data

Registers

SRAM

AHB to APB

Bridge

APB IPs

Figure 3. Bus Architecture

Memory Organization

The Arm ® Cortex ® -M0+ processor access and debug access share the single external interface to external AHB peripherals. The processor access takes priority over debug access. The maximum address range of the Cortex ® -M0+ is 4 GB since it has 32-bit bus address width. Additionally, a pre-defined memory map is provided by the Cortex ® -M0+ processor to reduce the software complexity of repeated implementation of different device vendors. However, some regions are used by the Arm ® Cortex ® -M0+ system peripherals. Refer to the Arm ® Cortex ® -M0+ Technical

Reference Manual for more information. The following figure shows the memory map of the

HT32F5828 device, including Code, SRAM, peripheral, and other pre-defined regions.

Rev. 1.00 38 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Memory Map

Peripheral

0xFFFF_FFFF

0xE010_0000

0xE000_0000

Private peripheral bus

0x4010_0000

0x4008_0000

0x4000_0000

Reserved

Reserved

AHB peripherals

APB peripherals

Reserved

SRAM

Code

0x2000_4000

0x2000_0000

0x1FF0_0400

0x1FF0_0000

0x1F00_0800

0x1F00_0000

0x0002_0000

Up to

16 KB on-chip SRAM

Reserved

Option byte alias

Reserved

Boot loader

Reserved

Up to

128 KB on-chip Flash

0x0000_0000

Up to

16 KB

1 KB

2 KB

Up to

128 KB

512 KB

512 KB

Reserved

DIV

AES-128

Reserved

GPIO A ~ D, E

Reserved

USB EP_SRAM

USB

Reserved

PDMA

Reserved

CRC

CKCU & RSTCU

Reserved

FMC

Reserved

BFTM1

BFTM0

Reserved

SCTM1

Reserved

PWM1

Reserved

GPTM

Reserved

RTC & PWRCU

Reserved

WDT

Reserved

CMP

Reserved

DAC

Reserved

I 2 C1

I 2 C0

Reserved

SPI1

SCI0

Reserved

UART1

Reserved

SCI1

Reserved

SCTM0

Reserved

PWM0

Reserved

I 2 S

Reserved

EXTI

Reserved

AFIO

Reserved

LCD

Reserved

ADC

Reserved

SPI0

Reserved

UART0

USART

0x400F_FFFF

0x400C_C000

0x400C_A000

0x400C_8000

0x400B_A000

0x400B_0000

0x400A_C000

0x400A_A000

0x400A_8000

0x4009_2000

0x4009_0000

0x4008_C000

0x4008_A000

0x4008_8000

0x4008_2000

0x4008_0000

0x4007_8000

0x4007_7000

0x4007_6000

0x4007_5000

0x4007_4000

0x4007_2000

0x4007_1000

0x4006_F000

0x4006_E000

0x4006_B000

0x4006_A000

0x4006_9000

0x4006_8000

0x4005_9000

0x4005_8000

0x4005_5000

0x4005_4000

0x4004_A000

0x4004_9000

0x4004_8000

0x4004_5000

0x4004_4000

0x4004_3000

0x4004_2000

0x4004_1000

0x4003_B000

0x4003_A000

0x4003_5000

0x4003_4000

0x4003_2000

0x4003_1000

0x4002_7000

0x4002_6000

0x4002_5000

0x4002_4000

0x4002_3000

0x4002_2000

0x4001_B000

0x4001_A000

0x4001_1000

0x4001_0000

0x4000_5000

0x4000_4000

0x4000_2000

0x4000_1000

0x4000_0000

AHB

APB

Figure 4. Memory Map

Rev. 1.00 39 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Rev. 1.00

Table 3. Register Map

Start Address

0x4000_0000

0x4000_1000

0x4000_2000

0x4000_4000

0x4000_5000

0x4001_0000

0x4001_1000

0x4001_A000

0x4001_B000

0x4002_2000

0x4002_3000

0x4002_4000

0x4002_5000

0x4002_6000

0x4002_7000

0x4003_1000

0x4003_2000

0x4003_4000

0x4003_5000

0x4003_A000

0x4003_B000

0x4004_1000

0x4004_2000

0x4004_3000

0x4004_4000

0x4004_5000

0x4004_8000

0x4004_9000

0x4004_A000

0x4005_4000

0x4005_5000

0x4005_8000

0x4005_9000

0x4006_8000

0x4006_9000

0x4006_A000

0x4006_B000

0x4006_E000

0x4006_F000

0x4007_1000

0x4007_2000

0x4007_4000

0x4007_5000

0x4007_6000

End Address

0x4000_0FFF

0x4000_1FFF

0x4000_3FFF

0x4000_4FFF

0x4000_FFFF

0x4001_0FFF

0x4001_9FFF

0x4001_AFFF

0x4002_1FFF

0x4002_2FFF

0x4002_3FFF

0x4002_4FFF

0x4002_5FFF

0x4002_6FFF

0x4003_0FFF

0x4003_1FFF

0x4003_3FFF

0x4003_4FFF

0x4003_9FFF

0x4003_AFFF

0x4004_0FFF

0x4004_1FFF

0x4004_2FFF

0x4004_3FFF

0x4004_4FFF

0x4004_7FFF

0x4004_8FFF

0x4004_9FFF

0x4005_3FFF

0x4005_4FFF

0x4005_7FFF

0x4005_8FFF

0x4006_7FFF

0x4006_8FFF

0x4006_9FFF

0x4006_AFFF

0x4006_DFFF

0x4006_EFFF

0x4007_0FFF

0x4007_1FFF

0x4007_3FFF

0x4007_4FFF

0x4007_5FFF

0x4007_6FFF

Peripheral

USART

UART0

Reserved

Reserved

SCTM0

Reserved

SCI1

Reserved

UART1

Reserved

SCI0

SPI1

Reserved

I 2 C0

I 2 C1

Reserved

SPI0

Reserved

ADC

Reserved

LCD

Reserved

AFIO

Reserved

EXTI

Reserved

I 2 S

Reserved

PWM0

DAC

Reserved

CMP

Reserved

WDT

Reserved

RTC & PWRCU

Reserved

GPTM

Reserved

PWM1

Reserved

SCTM1

Reserved

BFTM0

40 of 637

Bus

APB

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Start Address

0x4007_7000

0x4007_8000

0x4008_0000

0x4008_2000

0x4008_8000

0x4008_A000

0x4008_C000

0x4009_0000

0x4009_2000

0x400A_8000

0x400A_A000

0x400A_C000

0x400B_0000

0x400B_2000

0x400B_4000

0x400B_6000

0x400B_8000

0x400B_A000

0x400C_8000

0x400C_A000

0x400C_C000

End Address

0x4007_7FFF

0x4007_FFFF

0x4008_1FFF

0x4008_7FFF

0x4008_9FFF

0x4008_BFFF

0x4008_FFFF

0x4009_1FFF

0x400A_7FFF

0x400A_9FFF

0x400A_BFFF

0x400A_FFFF

0x400B_1FFF

0x400B_3FFF

0x400B_5FFF

0x400B_7FFF

0x400B_9FFF

0x400C_7FFF

0x400C_9FFF

0x400C_BFFF

0x400F_FFFF

Peripheral

BFTM1

Reserved

FMC

Reserved

CKCU & RSTCU

CRC

Reserved

PDMA

Reserved

USB

USB EP_SRAM

Reserved

GPIOA

GPIOB

GPIOC

GPIOD

GPIOE

Reserved

AES-128

DIV

Reserved

Bus

APB

AHB

Embedded Flash Memory

The HT32F5828 device provides an up to 128 KB on-chip Flash memory which is located at address 0x0000_0000. It supports byte, half-word and word access operations. Note that the

Flash memory only supports read operations for the bus access. Any write operations to the Flash memory will cause a bus fault exception. The Flash memory has up to 128 pages. Each page has a memory capacity of 1 KB and can be erased independently. A 32-bit programming interface provides the capability of changing bits from 1 to 0. A data storage or firmware upgrade can be implemented using several methods such as In System Programming (ISP), In Application

Programming (IAP) or In Circuit Programming (ICP). For more information, refer to the Flash

Memory Controller section.

Embedded SRAM Memory

The HT32F5828 device contains an up to 16 KB on-chip SRAM which is located at address

0x2000_0000. It supports byte, half-word and word access operations.

AHB Peripherals

The address of the AHB peripherals ranges from 0x4008_0000 to 0x400F_FFFF. Some peripherals such as Clock Control Unit, Reset Control Unit and Flash Memory Controller are connected to the

AHB bus directly. The AHB peripherals clocks are always enabled after a system reset. Access to registers for these peripherals can be achieved directly via the AHB bus. Note that all peripheral registers in the AHB bus support only word access.

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

APB Peripherals

The address of APB peripherals ranges from 0x4000_0000 to 0x4007_FFFF. An APB to AHB

Bridge provides access capability between the CPU and the APB peripherals. Additionally, the

APB peripheral clocks are disabled after a system reset. Software must enable the peripheral clocks by setting up the APBCCRn register in the Clock Control Unit before accessing the corresponding peripheral register. Note that the APB to AHB Bridge will duplicate the half-word or byte data to word width when a half-word or byte access is performed on the APB peripheral registers. In other words, the access result of a half-word or byte access on the APB peripheral register will vary depending on the data bit width of the access operation on the peripheral registers.

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

4

Flash Memory Controller (FMC)

Introduction

The Flash Memory Controller, FMC, provides all the necessary functions and pre-fetch buffer for the embedded on-chip Flash memory. The figure below shows the block diagram of FMC which includes programming interface, control register, pre-fetch buffer and access interface. Since the access speed of the Flash memory is slower than the CPU, a wide access interface with a pre-fetch buffer is provided to the Flash memory in order to reduce the CPU waiting time which will cause

CPU instruction execution delay. The Flash memory word programming/page erase functions are also provided for instruction/data storage.

Flash Memory Controller

Flash

Information

Block

AHB

Peripheral

Bus

Control Register

Pre-fetch Buffer

Wait State

Control

Addressing

Data

Programming

Control

Main Flash

Memory

Figure 5. Flash Memory Controller Block Diagram

Features

▆

▆

▆

▆

Up to 128 KB of on-chip Flash memory for storing instruction/data and option bytes

● 128 KB (instruction/data + Option Byte)

Page size of 1 KB, totally up to 128 pages

Wide access interface with a pre-fetch buffer to reduce instruction gaps

Page erase and mass erase capability

▆

▆

▆

▆

32-bit word programming

Interrupt function to indicate end of Flash memory operations or an error occurrence

Flash read protection to prevent illegal code/data access

Page erase/program protection to prevent unexpected operations

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Functional Descriptions

Flash Memory Map

The following figure is the Flash memory map of the system. The address ranges from

0x0000_0000 to 0x1FFF_FFFF (0.5 GB). The address from 0x1F00_0000 to 0x1F00_07FF is mapped to the Boot Loader Block with a capacity of 2 KB. Additionally, the region addressed from 0x1FF0_0000 to 0x1FF0_03FF is the alias of the Option Byte block with a capacity of 1 KB, which physically locates at the last page of the main Flash. The memory mapping on system view is shown below.

0x1FFF_FFFF

Reserved

0x1FF0_0400

0x1FF0_0000

0x1F00_0800

0x1F00_0000

Option Byte

Reserved

Boot Loader Block

Reserved

1 KB

2 KB

Main Flash Block

User Application

Up to

127 KB

0x0000_0000

Figure 6. Flash Memory Map

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Flash Memory Architecture

The Flash memory consists of up to 128 KB main Flash Block with 1 KB per page and 2 KB

Information Block for Boot Loader. The main Flash memory contains a total of 128 pages (or 64 pages for 64 KB device and so on) which can be erased individually. The following table shows the base address, size, and protection setting bit of each page.

Table 4. Flash Memory and Option Byte

Block Name Address

Page 0

Page 1

Page 2

Page 3

0x0000_0000 ~ 0x0000_03FF

0x0000_0400 ~ 0x0000_07FF

0x0000_0800 ~ 0x0000_0BFF

0x0000_0C00 ~ 0x0000_0FFF

Main Flash

Block

:

:

Page 124

:

:

0x0001_F000 ~ 0x0001_F3FF

Page 125

Page 126

0x0001_F400 ~ 0x0001_F7FF

0x0001_F800 ~ 0x0001_FBFF

Page 127

(Option Byte)

Physical address:

0x0001_FC00 ~ 0x0001_FFFF

Alias address:

0x1FF0_0000 ~ 0x1FF0_03FF

Information Block Boot Loader 0x1F00_0000 ~ 0x1F00_07FF

Page

Protection Bit Size

OB_PP [0]

OB_PP [1]

OB_PP [2]

OB_PP [3]

:

:

OB_PP [124]

OB_PP [125]

OB_PP [126]

OB_CP [1]

1 KB

1 KB

1 KB

1 KB

:

:

1 KB

1 KB

1 KB

1 KB

NA 2 KB

Notes: 1. The Information Block stores the boot loader and this block can not be programmed or erased by users.

2. The Option Byte is always located at the last page of the Main Flash Block.

Wait State Setting

When the CPU clock, HCLK, is faster than the Flash memory access speed, the wait state cycles must be inserted during CPU fetching instructions or loading data from the Flash memory. The wait state can be changed by setting the WAIT [2:0] field of the Flash Pre-fetch Control Register,

CFCR. In order to meet the wait state requirement, the following two rules should be considered.

▆

▆

The HCLK clock is switched from low to high frequency:

Change the wait state setting first and then switch the HCLK clock.

The HCLK clock is switched from high to low frequency:

Switch the HCLK clock first and then change the wait state setting.

The following table shows the relationship between the wait state cycle and HCLK. The default wait state is 0 since the High Speed Internal oscillator, HSI, which operates at a frequency of 8

MHz is selected as the HCLK clock source after a system reset.

Table 5. Relationship between Wait State Cycle and HCLK

Wait State Cycle

0

1

2

HCLK

0 MHz < HCLK ≤ 20 MHz



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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Booting Configuration

The system provides two kinds of booting modes which can be selected using the BOOT pin. The

BOOT pin status is sampled during the power-on reset or system reset. Once the logic value is decided, the first 4 words of vector will be remapped to the corresponding source according to the booting mode. The booting modes are shown in the following table.

Table 6. Booting Modes

Booting Mode Selection Pin

BOOT

0

1

Mode

Boot Loader

Main Flash

Descriptions

The vector source is Boot Loader

The vector source is main Flash

The Flash Vector Mapping Control Register, VMCR, is provided to change the vector remapping setting temporarily after the chip reset. The initial reset value of the VMCR register is determined by the BOOT pin status which will be sampled during the reset duration.

0xC Hard Fault Handler

0x8 NMI Handler

0x4 Program Counter

0x0 Initial Stack Point

Figure 7. Vector Remapping

1 : Main Flash

+ 0xC

+ 0x8

+ 0x4

0x0000_0000

Boot Setting

0 : Boot Loader

+ 0xC

+ 0x8

+ 0x4

0x1F00_0000

Page Erase

The FMC provides a page erase function which is used to reset partial content of the Flash memory.

Any page can be erased independently without affecting others. The following steps show the page erase operation register access sequence.

1. Check the OPCR register to confirm that no Flash memory operation is in progress (OPM [3:0] is equal to 0xE or 0x6). Otherwise, wait until the previous operation has been finished.

2. Write the page address to the TADR register.

3. Write the page erase command to the OCMR register (Set CMD [3:0] = 0x8).

4. Commit the page erase command to the FMC by setting the OPCR register (Set OPM [3:0] =

0xA).

5. Wait until all the operations have been completed by checking the value of the OPCR register

(OPM [3:0] is equal to 0xE).

6. Read and verify the page if required.

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Cortex ® -M0+ MCU

Note that a correct address of the target page must be confirmed. The software may run out of control if the target erase page is under the code fetching or data accessing status. The FMC will not provide any notification when this happens. Additionally, the page erase operation will be ignored on the protected pages. When this occurs, the OREF bit will be set by the FMC and then a Flash Operation Error interrupt will be generated if the OREIEN bit in the OIER register is set.

The software can check the PPEF bit in the OISR register to detect this condition in the interrupt handler. The following figure shows the page erase operation flow.

Start

No

Is OPM equal to 0xE or 0x6 ?

Yes

Set TADR, OCMR

Commit command by setting OPCR

No

Is OPM equal to 0xE ?

Yes

Finish

Figure 8. Page Erase Operation Flowchart

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Mass Erase

The FMC provides a mass erase function which is used to initialize all the main Flash memory contents to a high state. The following steps show the mass erase operation register access sequence.


2. Write the mass erase command to the OCMR register (Set CMD [3:0] = 0xA).

3. Commit the mass erase command to the FMC by setting the OPCR register (Set OPM [3:0] =

0xA).

4. Wait until all the operations have been finished by checking the value of the OPCR register (OPM [3:0] is equal to 0xE).

5. Read and verify the Flash memory if required.

Since all Flash data will be reset as 0xFFFF_FFFF, the mass erase operation can be implemented by the program that runs on the SRAM or by the debugging tool that accesses the FMC registers directly. The application program that is executed on the Flash memory will not trigger a mass erase operation. The following figure shows the mass erase operation flow.

Start

No


Yes

Set OCMR = 0xA


No


Yes

Finish

Figure 9. Mass Erase Operation Flowchart

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Word Programming

The FMC provides a 32-bit word programming function which is used to modify the Flash memory contents. The following steps show the word programming operation register access sequence.


2. Write the word address to the TADR register. Write the word data to the WRDR register.

3. Write the word programming command to the OCMR register (Set CMD [3:0] = 0x4).

4. Commit the word programming command to the FMC by setting the OPCR register (Set OPM [3:0]

= 0xA).


6. Read and verify the Flash memory if required.

Note that the word programming operation can not be successively applied to the same address twice. Successive word programming operation to the same address must be separated by a page erase operation. Additionally, the word programming operation will be ignored on the protected pages. When this occurs, the OREF bit will be set by the FMC and then a Flash Operation Error interrupt will be generated if the OREIEN bit in the OIER register is set. The software can check the PPEF bit in the OISR register to detect this condition in the interrupt handler. The following figure shows the word programming operation flow.

Start

No


Yes

Set TADR, WRDR and OCMR


No


Figure 10. Word Programming Operation Flowchart

Yes

Finish

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Option Byte Description

The Option Byte area can be treated as an independent Flash memory of which the base address is

0x1FF0_0000. The following table shows the functional description and the Option Byte memory map.

Table 7. Option Byte Memory Map

Option Byte Offset Description

Option Byte Base Address = 0x1FF0_0000

OB_PP

0x000

0x004

0x008

0x00C

Flash Page Erase/Program Protection (n = 0 ~ 127)

OB_PP [n] (n = 0 ~ 126)

0: Flash Page n Erase / Program Protection is enabled

1: Flash Page n Erase / Program Protection is disabled

OB_PP [n] (n = 127)

Reserved

OB_CP

OB_CK

OB_WDT

OB_TOOL

Reset Value

0xFFFF_FFFF

0xFFFF_FFFF

0xFFFF_FFFF

0xFFFF_FFFF

0x010

0x020

0x02C

Flash Security Protection

OB_CP [0]

0: Flash Security protection is enabled

1: Flash Security protection is disabled

Option Byte Protection

OB_CP [1]

0: Option Byte protection is enabled

1: Option Byte protection is disabled

OB_CP [31:2]: Reserved

0xFFFF_FFFF

Flash Option Byte Checksum

OB_CK [31:0]

OB_CK should be set as the sum of 5 words of Option Byte content, of which the offset address ranges from 0x000 to 0x010

(0x000 + 0x004 + 0x008 + 0x00C + 0x010), when the OB_

PP or OB_CP register content is not equal to 0xFFFF_FFFF.

Otherwise, both page erase/program protection and security protection will be enabled.

0xFFFF_FFFF

Flash Option Watchdog Timer Enable

OB_WDT [15:0]: 0x7A92

If the OB_WDT [15:0] is set to 0x7A92, the WDT will be enabled immediately when the MCU power on reset or system reset occurs. The WDT can be disabled by software.

OB_WDT [31:16]: Reserved

0xFFFF_FFFF

0x030 ~ 0x04C Reserved for Flash writer tool and boot loader.

0xFFFF_FFFF

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Page Erase/Program Protection

The FMC provides a page erase/program protection function to prevent unexpected operations on the protected Flash memory area. The page erase (CMD [3:0] = 0x8 in the OCMR register) or word programming (CMD [3:0] = 0x4) command will not be accepted by the FMC on the protected pages. When the page erase or word programming command aimed at the protected pages is sent to the FMC, the PPEF bit in the OISR register will then be set by the FMC and the Flash Operation

Error interrupt will be triggered to inform the CPU if the OREIEN bit in the OIER register is set.

The page protection function can be individually enabled for each page by configuring the OB_

PP registers in the Option Byte area. The following table shows the access permission of the main

Flash page when the page protection is enabled.

Table 8. Access Permission of Protected Main Flash Page

Operation

Read

Program

Page Erase

Mass Erase

Mode

ISP/IAP

X

O

O

X

ICP/Debug Mode

X

O

O

X

Notes: 1. Each write protection bit setting is for one specific page. The above access permission only affects the pages of which the protection function has been enabled. Other pages are not affected.

2. The main Flash page protection is configured by OB_PP [127:0]. Option Byte is physically located at the last page of the main Flash. The Option Byte page protection is configured by the OB_CP [1] bit.

3. The page erase operation on the Option Byte area can disable the page protection of the main Flash.

4. The page protection of the Option Byte can only be disabled by a mass erase operation.

The following steps show the register access sequence for the page erase/program protection procedure.


2. Write the OB_PP address to the TADR register (Set TADR = 0x1FF0_0000).

3. Write the desired data, which indicates the protection function of the corresponding page is to be enabled or disabled, into the WRDR register (0: Enabled, 1: Disabled).

4. Write the word programming command to the OCMR register (Set CMD [3:0] = 0x4).

5. Commit the word programming command to the FMC by setting the OPCR register (Set OPM [3:0]

= 0xA).


7. Read and verify the Option Byte if required.

8. The OB_CK field in the Option Byte area must be updated according to the Option Byte checksum rule.

9. Apply a system reset to activate the new OB_PP setting.

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Cortex ® -M0+ MCU

Security Protection

The FMC provides a security protection function to prevent illegal code/data access to the Flash memory. This function is useful for protecting the software/firmware from illegal users. The function is activated by setting OB_CP [0] in the Option Byte. Once the function has been enabled, all the main Flash data access through ICP/Debug mode, programming and page erase operation will not be allowed except the user’s application. However the mass erase operation will still be accepted by the FMC in order to disable this security protection function. The following table shows the access permission of the Flash memory when the security protection is enabled.

Table 9. Access Permission When Security Protection is Enabled

Mode

User Application (1) ICP/Debug Mode

Operation

Read

Program

Page Erase

Mass Erase

O

O (1)

O (1)

O

X

O

X (read as 0)

X

Notes: 1. User application means the software that is executed or booted from the main Flash memory with the JTAG/SW debugger being disconnected. However, the Option Byte area and page 0 are still under protection, where the Program/Page Erase operations are not accepted.

2. The Mass Erase operation can erase the Option Byte area and disable the security protection.

The following steps show the register access sequence for the security protection procedure.


2. Write the OB_CP address to the TADR register (Set TADR = 0x1FF0_0010).

3. Write data to the WRDR register to set OB_CP [0] to 0.

4. Write the word program command to the OCMR register (Set CMD [3:0] = 0x4).

5. Commit the word program command to the FMC by setting the OPCR register (Set OPM =

0xA).


7. Read and verify the Option Byte if required.

8. The OB_CK field in the Option Byte area must be updated according to the Option Byte checksum rule.

9. Apply a system reset to active the new OB_CP setting.

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Cortex ® -M0+ MCU

Register Map

The following table shows the FMC registers and reset values.

Table 10. FMC Register Map

Register Offset

TADR 0x000

WRDR

OCMR

0x004

0x00C

OPCR

OIER

OISR

PPSR

CPSR

VMCR

MDID

PNSR

PSSR

DID

CFCR

CIDR0

CIDR1

CIDR2

CIDR3

0x010

0x014

0x018

0x020

0x024

0x028

0x02C

0x030

0x100

0x180

0x184

0x188

0x18C

0x200

0x310

0x314

0x318

0x31C

Description

Flash Target Address Register

Flash Write Data Register

Flash Operation Command Register

Flash Operation Control Register

Flash Operation Interrupt Enable Register

Flash Operation Interrupt and Status Register

Flash Page Erase/Program Protection Status Register

Flash Security Protection Status Register

Flash Vector Mapping Control Register

Flash Manufacturer and Device ID Register

Flash Page Number Status Register

Flash Page Size Status Register

Device ID Register

Flash Pre-fetch Control Register

Custom ID Register 0




Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_000C

0x0000_0000

0x0001_0000

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0x0000_000X

0x0000_000X

0x0376_XXXX

0x0000_00XX

0x0000_0400

0x000X_XXXX

0x0000_0011

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

0xXXXX_XXXX

Note: “X” means various reset values which depend on the Device, Flash value, Option Byte value or power on reset setting.

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Cortex ® -M0+ MCU

Register Descriptions

Flash Target Address Register – TADR

This register specifies the target address of the page erase and word programming operations.

Offset: 0x000

Reset value: 0x0000_0000

31 30 29 28 27

TADB

26 25 24

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

23 22 21 20 19

TADB

18 17 16


15 14 13 12 11

TADB

10 9 8


7 6 5 4 3 2 1 0

TADB


Bits

[31:0]

Field

TADB

Descriptions

Flash Target Address Bits

For programming operations, the TADR register specifies the address where the data is written to. Since the programming length is 32-bit, the TADR register should be set as word-aligned (4 bytes). The TADB [1:0] bits will be ignored during programming operations. For page erase operations, the TADR register contains the page address which is to be erased. Since the page size is 1 KB, the TADB [9:0] bits will be ignored in order to limit the target address as 1 Kbyte-aligned. For

128 KB main Flash addressing, TADB [31:17] should be zero and TADB [31:16] should be zero for 64 KB and so on. The region of which the address ranges from

0x1FF0_0000 to 0x1FF0_03FF is the 1 KB Option Byte. This field for available Flash address must be within the range of 0x0000_0000 to 0x1FFF_FFFF. Otherwise, an Invalid Target Address interrupt will be generated if the corresponding interrupt enable bit is set.

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Cortex ® -M0+ MCU

Flash Write Data Register – WRDR

This register specifies the data to be written for the programming operation.

Offset: 0x004


31 30 29 28 27

WRDB

26 25 24


23 22 21 20 19

WRDB

18 17 16


15 14 13 12 11

WRDB

10 9 8


7 6 5 4 3 2 1 0

WRDB


Bits

[31:0]

Field

WRDB

Descriptions

Flash Write Data Bits

The data value for the programming operation.

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Cortex ® -M0+ MCU

Flash Operation Command Register – OCMR

This register is used to specify the Flash operation commands that include word programming, page erase and mass erase.

Offset: 0x00C


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11

Reserved

10 9 8

3 2 1

CMD

0

RW 0 RW 0 RW 0 RW 0

Bits

[3:0]

Field

CMD

Descriptions

Flash Operation Command

The following table shows the definitions of the operation command field, CMD [3:0], which specifies the Flash memory operation. If an invalid command is set and the

IOCMIEN bit is set to 1, an Invalid Operation Command interrupt will be generated.

CMD [3:0]

0x0

0x4

0x8

0xA

Others

Description

Idle (default)

Word programming

Page erase

Mass erase

Reserved

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Cortex ® -M0+ MCU

Flash Operation Control Register – OPCR

This register is used for controlling the command commitment and checking the status of the FMC operations.

Offset: 0x010

Reset value: 0x0000_000C

31 30 29

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

Reserved

21

13

5

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

12 11

Reserved

10 9 8

4 3 2

OPM

1

RW 0 RW 1 RW 1 RW 0

0

Reserved

Bits

[4:1]

Field

OPM

Descriptions

Operation Mode

The following table shows the FMC operation modes. Users can commit command which is set by the OCMR register to the FMC according to the address alias setting in the TADR register. The contents of the TADR, WRDR and OCMR registers should be prepared before setting this register. After all the operations have been finished, the

OPM field will be set to 0xE by the FMC hardware. The Idle mode can be set when all the operations have been finished for power saving purpose. Note that the operation status should be checked before executing next operation. The contents of the

TADR, WRDR, OCMR and OPCR registers should not be changed until the previous operation has been finished.

OPM [3:0]

0x6

0xA

0xE

Others

Description

Idle (default)

Commit command to main Flash

All operation finished on main Flash

Reserved

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Flash Operation Interrupt Enable Register – OIER

This register is used to enable or disable the FMC interrupt function. The FMC will generate the interrupt when the corresponding interrupt enable bit is set and the interrupt condition occurs.

Offset: 0x014


31 30 29

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

Reserved

21

13

5

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

12 11

Reserved

10 9 8

4 3 2 1 0

OREIEN IOCMIEN OBEIEN ITADIEN ORFIEN

RW 0 RW 0 RW 0 RW 0 RW 0

Bits

[4]

[3]

[2]

[1]

[0]

Field

OREIEN

IOCMIEN

OBEIEN

ITADIEN

ORFIEN

Descriptions

Operation Error Interrupt Enable

0: Operation Error Interrupt is disabled

1: Operation Error Interrupt is enabled

Invalid Operation Command Interrupt Enable

0: Invalid Operation Command Interrupt is disabled

1: Invalid Operation Command Interrupt is enabled

Option Byte Check Sum Error Interrupt Enable

0: Option Byte Check Sum Error Interrupt is disabled

1: Option Byte Check Sum Error Interrupt is enabled

Invalid Target Address Interrupt Enable

0: Invalid Target Address Interrupt is disabled

1: Invalid Target Address Interrupt is enabled

Operation Finished Interrupt Enable

0: Operation Finished Interrupt is disabled

1: Operation Finished Interrupt is enabled

Rev. 1.00 58 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Flash Operation Interrupt and Status Register – OISR

This register indicates the FMC interrupt status which is used to check if a Flash operation has been finished or if an error has occurred. The status bits, bit [4:0], if set high, are available to trigger the interrupts when the corresponding enable bits in the OIER register are set high.

Offset: 0x018


31 30 29

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

Reserved

21

13

5

28 27

Reserved

26 25 24

20

Reserved

19 18 17

PPEF

16

RORFF

RO 0 RO 1

9 8 12 11

Reserved

10

4

OREF

3

IOCMF

2

OBEF

1

ITADF

0

ORFF

WC 0 WC 0 WC 0 WC 0 WC 0

Bits

[17]

[16]

[4]

[3]

Field

PPEF

RORFF

OREF

IOCMF

Descriptions

Page Erase/Program Protected Error Flag

0: Page Erase/Program Protected Error does not occur

1: Operation error occurs due to an invalid erase/program operation being applied to a protected page

This bit is reset by hardware once a new flash operation command is committed.

Raw Operation Finished Flag

0: The last Flash operation command is not finished

1: The last Flash operation command is finished

The RORFF bit is directly connected to the Flash memory for debugging purpose.

Operation Error Flag

0: No Flash operation error occurred

1: The last Flash operation is failed

This bit will be set high when any Flash operation error occurs such as an invalid command, program error and erase error, etc. The Operation Error interrupt will be generated if the OREIEN bit in the OIER register is set. Reset this bit by writing 1.

Invalid Operation Command Flag

0: No invalid Flash operation command has been written into the OCMR register

1: An invalid Flash operation command has been written into the OCMR register

This bit will be set when an invalid Flash operation command has been written into the OCMR register. Then the Invalid Operation Command interrupt will be generated if the IOCMIEN bit in the OIER register is set. Reset this bit by writing 1.

Rev. 1.00 59 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[2]

[1]

[0]

Field

OBEF

ITADF

ORFF

Descriptions

Option Byte Checksum Error Flag

0: Option Byte checksum is correct

1: Option Byte checksum is incorrect

This bit will be set high when the Option Byte checksum is incorrect. The Option

Byte Checksum Error interrupt will be generated if the OBEIEN bit in the OIER register is set. This bit is cleared to zero by software writing “1” into it. However, the

Option Byte Checksum Error Flag can not be cleared by software until the interrupt condition is released, which means that the Option Byte checksum value has be correctly modified or the corresponding interrupt control is disabled. Otherwise, the interrupt will be continually generated.

Invalid Target Address Flag

0: The target address is valid

1: The target address is invalid

The data in the TADR field must be within the range from 0x0000_0000 to 0x1FFF_

FFFF. Otherwise, this bit will be set high and an Invalid Target Address interrupt will be generated if the ITADIEN bit in the OIER register is set. Reset this bit by writing 1.

Operation Finished Flag

0: Last Flash operation has not finished

1: Last Flash operation has finished

This bit will be set when the last Flash operation has finished. Then the Operation

Finished interrupt will be generated if the ORFIEN bit in the OIER register is set.

Reset this bit by writing 1.

Rev. 1.00 60 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Flash Page Erase/Program Protection Status Register – PPSR

This register indicates the page protection status of the Flash page erase/program protection functions.

Offset: 0x020 (0) ~ 0x02C (3)

Reset value: 0xXXXX_XXXX

31 30 29 28 27

PPSBn

26 25 24

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

23 22 21 20 19

PPSBn

18 17 16


15 14 13 12 11

PPSBn

10 9 8


7 6 5 4 3 2 1 0

PPSBn


Bits

[127:0]

Field

PPSBn

Descriptions

Page Erase/Program Protection Status Bits (n = 0 ~ 127)

PPSB[n] = OB_PP[n]

0: The corresponding page is protected

1: The corresponding page is not protected

The content of this register is not dynamically updated and will only be reloaded from the Option Byte when any kind of reset occurs. The erase or program function of the specific pages is not allowed when the corresponding bits of the PPSR registers are reset. The reset value of PPSR [127:0] is determined by the Option

Byte OB_PP [127:0] bits. Since the maximum page number of the main Flash is various and dependent on the chip specification. Therefore, the every page erase/ program protection status bit may protect one or two pages, depending on the chip specification. Other bits of the OB_PP and PPSR registers are reserved for future use.

Rev. 1.00 61 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Flash Security Protection Status Register – CPSR

This register indicates the Flash memory security protection status. The content of this register is not dynamically updated and will only be reloaded by the Option Byte loader which is activated when any kind of reset occurs.

Offset: 0x030

Reset value: 0x0000_000X

31 30 29 26 25 24

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

18

10

2

17

9

16

8

1

OBPSB

0

CPSB

RO X RO X

Bits

[1]

[0]

Field

OBPSB

CPSB

Descriptions

Option Byte Page Erase/Program Protection Status Bit

0: The Option Byte page is protected

1: The Option Byte page is not protected

The reset value of the OBPSB bit is determined by the Option Byte OB_CP [1] bit.

Flash Security Protection Status Bit

0: Flash Security protection is enabled

1: Flash Security protection is not enabled

The reset value of the CPSB bit is determined by the Option Byte OB_CP [0] bit.

Rev. 1.00 62 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Flash Vector Mapping Control Register – VMCR

This register is used to control the vector mapping. The reset value of the VMCR register is determined by the external booting pin, BOOT, during the power-on reset period.

Offset: 0x100

Reset value: 0x0000_000X

31 30 29 26 25 24

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

18

10

2

17

9

16

8

1

VMCB

RW X

0

Reserved

Bits

[1]

Field

VMCB

Descriptions

Vector Mapping Control Bit

The VMCB bit is used to control the mapping source of the first 4 words of vector addressed from 0x0 to 0xC. The following table shows the vector mapping setting.

BOOT

Low

High

VMCB

0

1

Descriptions

Boot Loader mode

The vector mapping source is the boot loader area.

Main Flash mode

The vector mapping source is the main Flash area.

The reset value of the VMCB bit is determined by the pin status of the external

BOOT pin during power-on reset and system reset. The vector mapping setting can be changed temporarily by configuring the VMCB bit when the application program is executed.

Rev. 1.00 63 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Flash Manufacturer and Device ID Register – MDID

This register specifies the manufacture ID and device part number information which can be used as the product identity.

Offset: 0x180

Reset value: 0x0376_XXXX

31 30 29 28 27

MFID

26 25 24

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1

23 22 21 20 19

MFID

18 17 16


15 14 13 12 11

ChipID

10 9 8


7 6 5 4 3 2 1 0

ChipID


Bits

[31:16]

[15:0]

Field

MFID

ChipID

Descriptions

Manufacturer ID

Read as 0x0376.

Chip ID

The last 4 digital codes of the MCU device part number.

Rev. 1.00 64 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Flash Page Number Status Register – PNSR

This register indicates the Flash memory page number.

Offset: 0x184

Reset value: 0x0000_00XX

31 30 29 28 27

PNSB

26 25 24


23 22 21 20 19

PNSB

18 17 16


15 14 13 12 11

PNSB

10 9 8


7 6 5 4 3 2 1 0

PNSB


Bits

[31:0]

Field

PNSB

Descriptions

Flash Page Number Status Bits

0x0000_0010: Totally 16 pages for the on-chip Flash memory device




0x0000_00FF: Totally 255 pages for the on-chip Flash memory device

Rev. 1.00 65 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Flash Page Size Status Register – PSSR

This register indicates the page size in bytes.

Offset: 0x188


31 30 29 28 27

PSSB

26 25 24


23 22 21 20 19

PSSB

18 17 16


15 14 13 12 11

PSSB

10 9 8


7 6 5 4 3 2 1 0

PSSB


Bits

[31:0]

Field

PSSB

Descriptions

Flash Page Size Status Bits

0x200: The page size is 512 Bytes per page

0x400: The page size is 1 K Bytes per page

0x800: The page size is 2 K Bytes per page

Device ID Register – DID

This register specifies the device part number information which can be used as the product identity.

Offset: 0x18C

Reset value: 0x000X_XXXX

31 30 29 28 27

Reserved

26 25 24

Type/Reset

Type/Reset

23

15

22

14

21

Reserved

13

20

12

19 18 17

ChipID

16

RO X RO X RO X RO X

11

ChipID

10 9 8


7 6 5 4 3

ChipID

2 1 0


Bits

[19:0]

Field

ChipID

Descriptions

Chip ID

The complete 5 digital codes of the MCU device part number.

Rev. 1.00 66 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Flash Pre-fetch Control Register – CFCR

This register is used for controlling the FMC pre-fetch module.

Offset: 0x200


31 30 29

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

Reserved

21

13

5

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

12 11

Reserved

10 9 8

4

PFBE

RW 1

3

Reserved

2 1

WAIT

0

RW 0 RW 0 RW 1

Bits

[4]

[2:0]

Field

PFBE

WAIT

Descriptions

Pre-fetch Buffer Enable Bit

0: Pre-fetch buffer is disabled

1: Pre-fetch buffer is enabled

The pre-fetch buffer is enabled by default setting. When the pre-fetch buffer is disabled, the instruction and data are directly provided by the Flash memory.

Flash Wait State Setting

The WAIT[2:0] field is used to set the HCLK wait clock during a non-sequential

Flash access. The actual wait clock is given by (WAIT[2:0] - 1). Since a wide access interface with a pre-fetch buffer is provided, the wait state of sequential

Flash access is very close to zero.

WAIT [2:0]

001

010

011

Others

Wait Status

0

1

2

Reserved

Allowed HCLK Range




Reserved

Rev. 1.00 67 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Custom ID Register n – CIDRn (n = 0 ~ 3)

This register specifies the custom ID information which can be used as the custom identity.

Offset: 0x310 (0) ~ 0x31C (3)

Reset value: 0xXXXX_XXXX – Various depending on Flash Manufacture Privilege Information Block

31 30 29 28 27

CID

26 25 24


23 22 21 20 19

CID

18 17 16


15 14 13 12 11

CID

10 9 8


7 6 5 4 3 2 1 0

CID


Bits

[31:0]

Field

CIDn

Descriptions

Custom ID

Read as the CIDn[31:0] (n = 0 ~ 3) field in the Custom ID registers in Flash

Manufacture Privilege Block.

Rev. 1.00 68 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

5

Reset Control Unit (RSTCU)

Introduction

The Reset Control Unit, RSTCU, has three kinds of reset, the power-on reset, system reset and

APB unit reset. The power-on reset, known as a cold reset, resets the full system during a power up. A system reset resets the processor core and peripheral IP components with the exception of the debug port controller. The resets can be triggered by an external signal, internal events and the reset generators. More information about these resets will be described in the following section.

Cortex ® -M0+ RSTCU

V

DD15

V

DD

1.5 V Core

Power POR

POR15

Brown-Out

Detector

RESET

BODRST

Filter

Filter nRST

V

DD

V

DD

Domain

POR

POR

Filter

WDT_RSTn

----

Filter

PWRST

WDTRST

Reset generator

PORRESETn

Delay

RTC/PWRCU reset

WDT reset

SYSRESETREQ

SYSRESETn

PORRESETn

NVIC

SYSRESETREQ

HRESETn

CM0+ Core

CORERESTn

HRESETn System Components

(BusMatrix, PMU)

System Debug

Components

URnRST

Reset generator

UARTn reset

Figure 11. RSTCU Block Diagram


Power-On Reset

The Power-on reset, POR, is generated by either an external reset or the internal reset generator.

Both types have an internal filter to prevent glitches from causing erroneous reset operations. By referring to Figure 12, the POR15 active low signal will be de-asserted when the internal LDO voltage regulator is ready to provide the 1.5 V power. In addition to the POR15 signal, the Power

Control Unit, PWRCU, will assert the BODF signal as a Power-Down Reset, PDR, when the

BODEN bit in the LVDCSR register is set and the brown-out event occurs. For more details about the PWRCU function, refer to the PWRCU chapter.

Rev. 1.00 69 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

V

DD33

V

DD15 t

1

PORRESETn t

2

SYSRESETn t

3 t

1 t

2 t

3

= 25 μ s *Typical.

= 100 μ s

= 150 μ s

* This timing is dependent on the internal LDO regulator output capacitor value.

Figure 12. Power-On Reset Sequence

System Reset

A system reset is generated by a power-on reset (PORRESETn), a Watchdog Timer reset (WDT_

RSTn), an nRST pin event or a software reset (SYSRESETREQ) event. For more information about

SYSRESETREQ event, refer to the related chapter in the Cortex ® -M0+ reference manual.

AHB and APB Unit Reset

The AHB and APB unit reset can be divided into hardware and software resets. A hardware reset can be generated by either power on reset or system reset for all AHB and APB units.

Each functional IP connected to the AHB and APB buses can be reset individually through the associated software reset bits in the RSTCU. For example, the application software can generate a

UART0 reset via the UR0RST bit in the APBPRSTR0 register.

Register Map

The following table shows the RSTCU registers and reset values.

Table 11. RSTCU Register Map

Register

GRSR

AHBPRSTR

APBPRSTR0

Offset

0x100

0x104

0x108

Description

Global Reset Status Register

AHB Peripheral Reset Register

APB Peripheral Reset Register 0

APBPRSTR1 0x10C APB Peripheral Reset Register 1

Reset Value

0x0000_0008

0x0000_0000

0x0000_0000

0x0000_0000

Rev. 1.00 70 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU


Global Reset Status Register – GRSR

This register specifies a variety of reset status conditions.

Offset: 0x100


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

Reserved

21

13

5

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11

Reserved

10 9 8

3 2 1 0

PORSTF WDTRSTF EXTRSTF NVICRSTF

WC 1 WC 0 WC 0 WC 0

Bits

[3]

[2]

[1]

[0]

Field

PORSTF

WDTRSTF

EXTRSTF

NVICRSTF

Descriptions

Core 1.5 V Power On Reset Flag

0: No POR occurred

1: POR occurred

This bit is set by hardware when a power-on reset occurs and reset by writing 1 into it.

Watchdog Timer Reset Flag

0: No Watchdog Timer reset occurred

1: Watchdog Timer occurred

This bit is set by hardware when a watchdog timer reset occurs and reset by writing 1 into it or by hardware when a power-on reset occurs.

External Pin Reset Flag

0: No pin reset occurred

1: Pin reset occurred

This bit is set by hardware when an external pin reset occurs and reset by writing

1 into it or by hardware when a power-on reset occurs.

NVIC Reset Flag

0: No NVIC asserting system reset occurred

1: NVIC asserting system reset occurred

This bit is set by hardware when a system reset occurs and reset by writing 1 into it or by hardware when a power-on reset occurs.

Rev. 1.00 71 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

AHB Peripheral Reset Register – AHBPRSTR

This register specifies several AHB peripherals software reset control bits.

Offset: 0x104


Type/Reset

31 30 29 28 27

Reserved

26 25 24

DIVRST

RW 0

16 23 22 21 20 19

Reserved

18 17

Type/Reset

15

AESRST

Type/Reset RW 0

7

CRCRST Reserved USBRST

Type/Reset RW 0

14

6

13 12

Reserved PERST

5

RW 0

11

PDRST

10

PCRST

9

PBRST

8

PARST


4 3 2 1 0

Reserved DMARST

RW 0

Bits

[24]

[15]

[12]

[11]

[10]

[9]

[8]

Field

DIVRST

AESRST

PERST

PDRST

PCRST

PBRST

PARST

Descriptions

Divider Reset Control

0: No reset

1: Reset Divider

This bit is set by software and cleared to 0 by hardware automatically.

AES Reset Control

0: No reset

1: Reset AES


GPIO Port E Reset Control

0: No reset

1: Reset Port E


GPIO Port D Reset Control

0: No reset

1: Reset Port D


GPIO Port C Reset Control

0: No reset

1: Reset Port C


GPIO Port B Reset Control

0: No reset

1: Reset Port B


GPIO Port A Reset Control

0: No reset

1: Reset Port A


Rev. 1.00 72 of 637 December 28, 2020

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Cortex ® -M0+ MCU

Bits

[7]

[5]

[0]

Field

CRCRST

USBRST

DMARST

Descriptions

CRC Reset Control

0: No reset

1: Reset CRC


USB Reset Control

0: No reset

1: Reset USB


Peripheral DMA (PDMA) Reset Control

0: No reset

1: Reset Peripheral DMA (PDMA)


APB Peripheral Reset Register 0 – APBPRSTR0

This register specifies several APB peripherals software reset control bits.

Offset: 0x108


Type/Reset

31

23

30

Reserved

22

29

21

28

20

27 26 25 24

SCI1RST Reserved I2SRST SCI0RST

RW 0

19

Reserved

18

RW 0 RW 0

17 16

Type/Reset

Type/Reset RW 0 RW 0

7 6 5 4

Reserved SPI1RST SPI0RST

Type/Reset

15 14

EXTIRST AFIORST

13 12 11 10 9 8

Reserved UR1RST UR0RST Reserved USRRST

RW 0 RW 0

RW 0 RW 0

3 2 1

RW 0

0

Reserved I2C1RST I2C0RST

RW 0 RW 0

Bits

[27]

[25]

[24]

Field

SCI1RST

I2SRST

SCI0RST

Descriptions

SCI1 Reset Control

0: No reset

1: Reset SCI1


I 2 S Reset Control

0: No reset

1: Reset I 2 S


SCI0 Reset Control

0: No reset

1: Reset SCI0


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HT32F5828

Cortex ® -M0+ MCU

Bits

[15]

[1]

[0]

[5]

[4]

[14]

[11]

[10]

[8]

Field

EXTIRST

AFIORST

UR1RST

UR0RST

USRRST

SPI1RST

SPI0RST

I2C1RST

I2C0RST

Descriptions

External Interrupt Controller Reset Control

0: No reset

1: Reset EXTI


Alternate Function I/O Reset Control

0: No reset

1: Reset Alternate Function I/O


UART1 Reset Control

0: No reset

1: Reset UART1


UART0 Reset Control

0: No reset

1: Reset UART0


USART Reset Control

0: No reset

1: Reset USART


SPI1 Reset Control

0: No reset

1: Reset SPI1


SPI0 Reset Control

0: No reset

1: Reset SPI0


I 2 C1 Reset Control

0: No reset

1: Reset I 2 C1


I 2 C0 Reset Control

0: No reset

1: Reset I 2 C0


Rev. 1.00 74 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

APB Peripheral Reset Register 1 – APBPRSTR1

This register specifies several APB peripherals software reset control bits.

Offset: 0x10C


Type/Reset

Type/Reset

Type/Reset

Type/Reset

31 30 29 28

Reserved SCTM1RST SCTM0RST

RW 0 RW 0

27 26

Reserved

25 24

ADCRST

RW 0

23 22 21 20 19 18 17 16

Reserved CMPRST DACRST Reserved LCDRST Reserved BFTM1RST BFTM0RST


15

7

14 13 12

Reserved PWM1RST PWM0RST

6

Reserved

RW 0 RW 0

5 4

WDTRST

RW 0

11

3

10

Reserved

2

9

1

Reserved

8

GPTMRST

RW 0

0

Bits

[29]

[28]

[24]

[22]

[21]

[19]

[17]

Field Descriptions

SCTM1RST SCTM1 Reset Control

0: No reset

1: Reset SCTM1


SCTM0RST SCTM0 Reset Control

0: No reset

1: Reset SCTM0


ADCRST ADC Reset Control

0: No reset

1: Reset A/D Converter


CMPRST CMP Reset Control

0: No reset

1: Reset CMP


DACRST

LCDRST

DAC Reset Control

0: No reset

1: Reset DAC


LCD Reset Control

0: No reset

1: Reset LCD


BFTM1RST BFTM1 Reset Control

0: No reset

1: Reset BFTM1


Rev. 1.00 75 of 637 December 28, 2020

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HT32F5828

Cortex ® -M0+ MCU

Bits

[16]

[13]

[12]

[8]

[4]


BFTM0RST BFTM0 Reset Control

0: No reset

1: Reset BFTM0


PWM1RST PWM1 Reset Control

0: No reset

1: Reset PWM1


PWM0RST PWM0 Reset Control

0: No reset

1: Reset PWM0


GPTMRST GPTM Reset Control

0: No reset

1: Reset GPTM


WDTRST Watchdog Timer Reset Control

0: No reset

1: Reset Watchdog Timer


Rev. 1.00 76 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

6

Clock Control Unit (CKCU)

Introduction

The Clock Control unit, CKCU, provides functions of High Speed Internal RC oscillator (HSI),

High Speed External crystal oscillator (HSE), Low Speed Internal RC oscillator (LSI), Low Speed

External crystal oscillator (LSE), Phase Lock Loop (PLL), HSE clock monitor, clock prescaler, clock multiplexer and clock gating. The clocks of AHB, APB, and CPU are derived from system clock (CK_SYS) which can come from HSI, HSE, LSI, LSE or PLL. Watchdog Timer and Real

Time Clock (RTC) use either LSI or LSE as their clock source. The maximum operating frequency of system clock f

CK_AHB

can be up to 60 MHz.

A variety of internal clocks can also be wired out through CKOUT for debugging purpose. The clock monitor can be used to get clock failure detection of HSE. Once the clock of HSE does not function such as being broken down or removed, etc., CKCU will force to switch the system clock source to the HSI clock to prevent system halt.

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Cortex ® -M0+ MCU

HSI Auto

Trimming

Controller

8 MHz

HSI RC

HSIEN

4 ~ 16 MHz

HSE XTAL

HSEEN

CK_LSE

USB Frame Pulse

CK_IN (2)

USBPLLSRC

USBPLLEN

1

0

USB

PLL

CKREFEN

USBEN

CK_USBPLL

PLLSRC

PLLEN

1

PLL

0

CK_PLL

SW[2:0]

CK_HSI

CK_HSE

00x f

CK_SYS,max

= 60 MHz

011

CK_SYS

010

AHB Prescaler

÷ 1,2,4,8,16,32

111

110

CKREFPRE

Prescaler

÷ 1 ~ 32

USBSRC

PAEN

PEEN

0

1

CM0PEN

(controlled by H/W)

PDMAEN

CRCEN

Divider

÷ 2

÷ 8

DIVEN

32.768 kHz

LSE OSC

LSEEN (1)

32 kHz

LSI RC

CK_LSE

CK_LSI

LCDSRC[1:0]

CK_LSI

CK_LSE

CK_HSI

CK_HSE

00

01

10

11

LCDEN

WDTSRC

1

0

WDTEN

RTCSRC (1)

1

0

Clock

Monitor

RTCEN (1)

CK_WDT

CK_RTC

LCD

Prescaler

÷ 1,2,4,8,16

CK_LCD

CM0PEN

FMCEN

CM0PEN

SRAMEN

CM0PEN

BMEN

CM0PEN

APBEN

AESEN

CKOUTSRC[2:0]

000

001

010

011

100

101

110

CK_REF

HCLKC/16

CK_SYS/16

CK_HSE/16

CK_HSI/16

CK_LSE

CK_LSI

Peripherals

Clock

Prescaler

÷ 1,2,4,8

Legend:

HSE = High Speed External clock

HSI = High Speed Internal clock

LSE = Low Speed External clock

LSI = Low Speed Internal clock

Note:

1. Those control bits are located in the RTC Control Register (RTCCR).

2. The CK_IN signal is sourced from the external CKIN pin.

ADCEN

CK_AHB

00

CK_AHB /2

01

CK_AHB /4

10

CK_AHB /8

11

SPIEN

SCIEN

ADC

Prescaler

÷ 1,2,3,4,8...

Figure 13. CKCU Block Diagram

CK_REF f

CK_USB

= 48 MHz

CK_USB

STCLK

(to SysTick)

CK_CRC

( to CRC)

CK_DIV

( to DIV)

CK_AES

( to AES)

HCLKF

( to Flash)

CK_GPIO

( to GPIO port)

FCLK

( free running clock)

HCLKC

( to Cortex ® -M0+)

HCLKD

( to PDMA)

HCLKS

( to SRAM)

HCLKBM

( to Bus Matrix)

HCLKAPB

( to APB Bridge)

CK_ADC IP

I

PCLK ( AFIO, ADC,

DAC, CMP, SCIx,

USART, UARTx, SPIx,

2 Cx, I 2 S, LCD, GPTM,

PWMx, SCTMx,

BFTMx, EXTI, RTC,

PWRCU, WDT)

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Cortex ® -M0+ MCU

Features

▆

▆

▆

▆

▆

▆

4 ~ 16 MHz external crystal oscillator (HSE)

Internal 8 MHz RC oscillator (HSI) with configuration option calibration and custom trimming capability

PLL with selectable clock source (from HSE or HSI) for system clock

32,768 Hz external crystal oscillator (LSE) for Watchdog Timer, RTC or system clock

Internal 32 kHz RC oscillator (LSI) for Watchdog Timer, RTC or system clock

HSE clock monitor


High Speed External Crystal Oscillator – HSE

The high speed external 4 to 16 MHz crystal oscillator (HSE) produces a highly accurate clock source to the system clock. The related hardware configuration is shown in the following figure. The crystal with specific frequency must be placed across the two HSE pins (XTALIN /

XTALOUT) and the external components such as resistors and capacitors are necessary to make it oscillate properly.

The following guidelines are provided to improve the stability of the crystal circuit PCB layout.

▆

▆

▆

The crystal oscillator should be located as close as possible to the MCU so that the trace lengths are kept as short as possible to reduce any parasitic capacitances.

Shield any lines in the vicinity of the crystal by using a ground plane to isolate signals and reduce noise.

Keep frequently switching signal lines away from the crystal area to prevent crosstalk.

OSC_EN

XTALIN XTALOUT

Crystal

C

L1

4 MHz ~ 16 MHz

C

L2

Figure 14. External Crystal, Ceramic and Resonators for HSE

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The HSE crystal oscillator can be switched on or off using the HSEEN bit in the Global Clock

Control Register (GCCR). The HSERDY flag in the Global Clock Status Register (GCSR) will indicate if the high speed external crystal oscillator is stable. While switching on the HSE, the HSE clock will still not be released until this HSERDY bit is set by the hardware. The specific delay period is well-known as “Start-up time”. As the HSE becomes stable, the HSE clock can then be used directly as the system clock source or be used as the PLL input clock.

High Speed Internal RC Oscillator – HSI

The high speed internal 8 MHz RC oscillator (HSI) is the default selection of clock source for the

CPU when the device is powered up. The HSI RC oscillator provides a clock source in a lower cost because no external components are required. The HSI RC oscillator can be switched on or off using the HSIEN bit in the Global Clock Control Register (GCCR). The HSIRDY flag in the Global

Clock Status Register (GCSR) will indicate if the internal RC oscillator is stable. The start-up time of HSI is shorter than the HSE crystal oscillator. The HSI clock can also be used as the PLL input clock.

The accuracy of the frequency of the high speed internal RC oscillator HSI can be calibrated via the configuration options, but it is still less accurate than the HSE crystal oscillator. The applications, the environments and the cost will determine the use of the oscillators.

Software could configure the Power Saving Wakeup RC Clock Enable bit, PSRCEN, to 1 to force the HSI clock to be the system clock when waking up from the Deep-Sleep1 or Deep-Sleep2 mode.

Subsequently, the system clock is back to the original clock source (HSE or PLL) if the original clock source ready flag is asserted. This function can reduce the wakeup time when using HSE or

PLL as system clock.

Auto Trimming of High Speed Internal RC Oscillator – HSI

The frequency accuracy of the high speed internal RC oscillator HSI can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by Holtek for ±2 % accuracy at V

DD

= 3.3 V and T

A

= 25 °C. But the accuracy is not enough for some application and environment requirements. Therefore, this device provides the trimming mechanism for HSI frequency calibration using a more accurate external reference clock. The detailed block diagram is shown as the following figure.

After reset, the factory trimming value is loaded in HSICOARSE[4:0] and HSIFINE[7:0] bits in the HSI Control Register (HSICR). The HSI frequency accuracy may be affected by voltage or temperature variations. If the application has to be driven by a more accurate HSI frequency, users can manually trim the HSI frequency using the HSIFINE[7:0] in the HSI Control Register (HSICR) or automatically adjust the HSI frequency using the Auto Trimming Controller (ATC) together with an external reference clock in the application. The reference clock can be provided from the following clock sources:

▆

▆

▆

32,768 Hz low speed external crystal or ceramic resonator oscillator LSE output clock

1 kHz USB frame pulse

External pin (CKIN) with 1 kHz pulse

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Cortex ® -M0+ MCU

Auto Trimming HSI Block Diagram

1

Fine-Trimming

Write Register

ATCEN

0

TMSEL

External pin (CKIN)

USB Frame Pulse

LSE

32.768 kHz

/32

1x

01

00

1 kHz

/1.024 kHz

REFCLKSEL

Auto Trimming

Controller

1

Factory

Trimming Bits

0

TRIMEN

Fine-Trimming

Read Register

HSIFINE [7:0]

HSICOARSE [4:0]

8 MHz HSI

Oscillator

8 MHz

AT

Counter

Register

Coarse-Trimming

Read Register

Figure 15. HSI Auto Trimming Block Diagram

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Cortex ® -M0+ MCU

Phase Locked Loop – PLL

This PLL can provide a 4 ~ 60 MHz clock output which is 1 ~ 15 multiples of a fundamental reference frequency of 4 ~ 16 MHz. The rationale of the clock synthesizer relies on the digital

Phase Locked Loop (PLL) which includes a reference divider, a two-stage feedback divider, a twostage output divider, a digital phase frequency detector (PFD), a current-controlled charge pump, a built-in loop filter and a voltage-controlled oscillator (VCO) to achieve a stable phase-locked state.

CLK

IN

= 4 ~ 16 MHz

Ref. Divider

(NR)

/2 or /4

PD CP VCO

Feedback Divider 2

(NF2)

Loop

Filter

Feedback Divider 1

(NF1)

/4

B3 ~ B0

Figure 16. PLL Block Diagram

VCO

OUT

= 48 ~ 120 MHz

Output Divider 1

(NO1)

/2

Output Divider 2

(NO2)

S1 ~ S0

PLL

OUT

= 4 ~ 60 MHz

Frequency of the PLL output clock can be determined by the following formula:

PLL

OUT

= CLK

IN

×

NF1 × NF2

NR × NO1 × NO2 = CLK IN

× 4 × NF2 = CLK

IN NO2 where NR = Ref divider = 2 or 4, NF1 = Feedback Divider 1 = 4, NF2 = Feedback Divider 2 = 1 ~ 16,

NO1 = Output Divider 1 = 2, NO2 = Output Divider 2 = 1, 2, 4 or 8

Considering the duty cycle with 50%, both input frequency and output frequency is divided by 2.

Assume that a given CLK

IN

frequency as PLL input generates a specific PLL output frequency; a larger number of NF2 is suggested because it will cause the PLL more stable and less jittered but enlarges the settling time. The output and feedback of divider 2 value are described in Table 12 and Table 13. All the configuration bits (S1 ~ S0, B3 ~ B0) in Table 12 and Table 13 as well as the

Bypass mode control are defined in the PLL Configuration Register (PLLCFGR) and PLL Control

Register (PLLCR) in the section of Register Definition. Note that VCO to 120 MHz. If VCO

OUT

PLL will not be promised to match the above PLL

OUT

formula.

OUT

is ranged from 48 MHz

by user’s configurations exceeds this range, the output frequency of the

The PLL can be switched on or off by using the PLLEN bit in the Global Clock Control Register

(GCCR). The PLLRDY flag in the Global Clock Status Register (GCSR) will indicate if the PLL clock is stable.

Table 12. Output Divider 2 Value Mapping

Output Divider 2 Setup Bits S1 ~ S0

(POTD Field in the PLLCFGR Register)

00

01

10

11

NO2

(Output Divider 2 Value)

1

2

4

8

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Table 13. Feedback Divider 2 Value Mapping

Feedback Divider 2 Setup Bits B3 ~ B0

(PFBD Field in the PLLCFGR Register)

0000

0001

1000

1001

1010

1011

1100

:

:

1111

0010

0011

0100

0101

0110

0111

NF2

(Feedback Divider 2 Value)

16

1

12

:

:

15

10

11

8

9

5

6

7

2

3

4

USB Phase Locked Loop – USB PLL

This USB PLL can provide a 48 MHz clock output for USB peripheral which is 3 ~ 12 multiples of a fundamental reference frequency of 4 ~ 16 MHz. The rationale of the clock synthesizer relies on the digital Phase Locked Loop (PLL) which includes a reference divider, a two-stage feedback divider, a two-stage output divider, a digital phase frequency detector (PFD), a current-controlled charge pump, a built-in loop filter and a voltage-controlled oscillator (VCO) to achieve a stable phase-locked state.

CLK

IN

= 4 ~ 16 MHz

Ref. Divider

(NR)

/2

PD

Feedback Divider 2

(NF2)

CP VCO

Loop

Filter

Feedback Divider 1

(NF1)

/4

B3 ~ B0

Figure 17. USB PLL Block Diagram

VCO

OUT

= 48 ~ 96 MHz

Output Divider 1

(NO1)

/2

Output Divider 2

(NO2)

S1 ~ S0

PLL

OUT

= 4 ~ 48 MHz

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Frequency of the PLL output clock can be determined by the following formula:

PLL

OUT

= CLK

IN

×

NF1 × NF2

NR × NO1 × NO2 = CLK IN

× 4 × NF2 = CLK

IN NO2 where NR = Ref divider = 2, NF1 = Feedback Divider 1 = 4, NF2 = Feedback Divider 2 = 1 ~ 16,

NO1 = Output Divider 1 = 2, NO2 = Output Divider 2 = 1, 2, 4, or 8

Considering the duty cycle with 50%, both input frequency and output frequency is divided by

2. Assume that a given CLK

IN

frequency as USB PLL input generates a specific USB PLL output frequency; a larger number of NF2 is suggested because it will cause the USB PLL more stable and less jittered but enlarges the settling time. The output and feedback of divider 2 value are described in Table 14 and Table 15. All the configuration bits (S1 ~ S0, B3 ~ B0) in Table 14 and Table 15 are defined in the PLL Configuration Register (PLLCFGR) in the section of Register Definition. Note that VCO

OUT

is ranged from 48 MHz to 96 MHz. If VCO

OUT

by user’s configurations exceeds this range, the output frequency of USB PLL will not be promised to match the above PLL

OUT

formula.

The USB PLL can be switched on or off by using the USBPLLEN bit in the Global Clock Control

Register (GCCR). The USBPLLRDY flag in the Global Clock Status Register (GCSR) will indicate if the USB PLL clock is stable.

Table 14. USB PLL Output Divider 2 Value Mapping

Output Divider 2 Setup Bits S1 ~ S0

(USBPOTD Field in the PLLCFGR Register)

00

01

10

11

NO2

(Output Divider 2 Value)

1

2

4

8

Table 15. USB PLL Feedback Divider 2 Value Mapping

Feedback Divider 2 Setup Bits B3 ~ B0

(USBPFBD Field in the PLLCFGR Register)

0000

0001

NF2

(Feedback Divider 2 Value)

16

1

1001

1010

1011

1100

:

:

1111

0010

0011

0100

0101

0110

0111

1000

9

10

11

12

:

:

15

6

7

8

4

5

2

3

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Cortex ® -M0+ MCU

Low Speed External Crystal Oscillator – LSE

The low speed external crystal or ceramic resonator oscillator with a 32,768 Hz frequency produces a low power but highly accurate clock source for the circuits of Real-Time-Clock peripheral,

Watchdog Timer or system clock. The associated hardware configuration is shown in the following figure. The crystal or ceramic resonator must be placed across the two LSE pins (X32KIN /

X32KOUT) and the external components such as resistors and capacitors are necessary to make it oscillate properly. The LSE oscillator can be switched on or off by using the LSEEN bit in the RTC

Control Register (RTCCR). The LSERDY flag in the Global Clock Status Register (GCSR) will indicate if the LSE clock is stable.

X32KIN

C

L1

32.768 kHz

X32KOUT

C

L2

Figure 18. External Crystal, Ceramic and Resonators for LSE

Low Speed Internal RC Oscillator – LSI

The low speed internal RC oscillator with a frequency of about 32 kHz produces a low power clock source for the circuits of Real-Time-Clock peripheral, Watchdog Timer or system clock. The LSI is also a low cost clock source because no external component is needed to make it oscillate. The frequency accuracy of the low speed internal RC oscillator LSI is shown in the corresponding data sheet. The LSIRDY flag in the Global Clock Status Register (GCSR) will indicate if the LSI clock is stable.

Clock Ready Flag

The CKCU provides clock ready flags for HSI, HSE, PLL, LSI, and LSE to confirm these clocks are stable before using them as system clock source or other purposes. Software can check specific clock is ready or not by polling separate clock ready status bits in GCSR register.

System Clock (CK_SYS) Selection

After a system reset occurs, the default source of the system clock CK_SYS will be the high speed internal RC oscillator HSI. The CK_SYS clock may come from the HSI, HSE, LSE, LSI or

PLL output clock and it can be switched from one clock source to another via the System Clock

Switch field, SW, in the Global Clock Control Register (GCCR). The system will still run under the original clock until the destination clock gets ready. The corresponding clock ready status bit in the

Global Clock Status Register (GCSR) will indicate whether the selected clock is ready to use or not.

The CKCU also contains the clock source status bits in the Clock Source Status Register (CKST) to indicate which clock is currently used as the system clock. If a clock source or the PLL output clock is used as the system clock, it is not possible to stop it. More details about clock enable function are described below.

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If any following action takes effect, the HSI is always under enable state.

▆

Enable PLL and configure its source clock to HSI. (PLLEN, PLLSRC)

▆

▆

Enable Clock monitor. (CKMEN)

Configure clock switch field to select HSI. (SW)

▆

Configure HSI enable bit to 1. (HSIEN)

If any following action takes effect, the HSE is always under enable state.

▆

Enable PLL and configure its source clock to HSE. (PLLEN, PLLSRC)

▆

▆

Configure clock switch field to select HSE. (SW)

Configure HSE enable bit to 1. (HSEEN)

If any following action takes effect, the PLL is always under enable state.

▆

Configure USB clock enable bit to 1. (USBEN)

▆

▆

Configure clock switch field to select PLL (SW)

Configure PLL enable bit to 1. (PLLEN)

Programming guide of system clock selection is listed below.

1. Enable any source clock which will become the system clock or PLL input clock.

2. Configure the PLLSRC bit after the ready flags of both HSI and HSE are asserted.

3. Configure the SW field to change the system clock source after the corresponding clock ready flag is asserted. Note that the system clock will force to HSI if the clock monitor is enabled and the PLL output clock or HSE clock configured as system clock is stuck at 0 or 1.

HSE Clock Monitor

The main function of the oscillator check is enabled by the HSE Clock Monitor Enable bit CKMEN in the Global Clock Control Register (GCCR). The HSE clock monitor should be enabled after the

HSE oscillator start-up delay and be disabled when the HSE oscillator is stopped. Once the HSE oscillator failure is detected, the HSE oscillator will automatically be disabled. The HSE clock stuck flag CKSF in the Global Clock Interrupt Register (GCIR) will be set and an interrupt of main oscillator failure will be generated if the clock stuck interrupt enable bit CKSIE in the GCIR is set.

This failure interrupt is connected to the exception vector of CPU Non-Maskable Interrupt (NMI).

If the HSE is directly used as the system clock source, when the HSE oscillator failure occurs, the HSE will be turned off and the system clock will be switched to the HSI automatically by the hardware. If the HSE is used as the clock input of the PLL circuit and the system clock comes from the PLL circuit output, the PLL circuit will also be turned off as well as the HSE when the failure happens.

Clock Output Capability

The device has the clock output capability to allow the clocks to be output on the specific external output pin CKOUT. The configuration registers of the corresponding GPIO port must be well configured in the Alternate Function I/O section, AFIO, to output the selected clock signal. There are seven output clock signals to be selected via the device clock output source selection field

CKOUTSRC in the Global Clock Configuration Register (GCFGR).

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Table 16. CKOUT Clock Source

CKOUTSRC[2:0]

000

001

010

011

100

101

110

Clock Source

CK_REF = CK_PLL / (CKREFPRE + 1) / 2

HCLKC / 16

CK_SYS / 16

CK_HSE / 16

CK_HSI / 16

CK_LSE

CK_LSI

Register Map

The following table shows the CKCU registers and reset values.

Table 17. CKCU Register Map

Register

GCFGR

GCCR

GCSR

Offset

0x000

0x004

0x008

Description

Global Clock Configuration Register

Global Clock Control Register

Global Clock Status Register

GCIR

PLLCFGR

PLLCR

0x00C

0x018

0x01C

AHBCFGR 0x020

AHBCCR 0x024

APBCFGR

APBCCR0

0x028

0x02C

APBCCR1

CKST

0x030

0x034

APBPCSR0 0x038

APBPCSR1 0x03C

Global Clock Interrupt Register

PLL Configuration Register

PLL Control Register

AHB Configuration Register

AHB Clock Control Register

APB Configuration Register

APB Clock Control Register 0

APB Clock Control Register 1

Clock Source Status Register

APB Peripheral Clock Selection Register 0


HSICR 0x040

HSIATCR 0x044

APBPCSR2 0x048

LPCR 0x300

MCUDBGCR 0x304

HSI Control Register

HSI Auto Trimming Counter Register


Low Power Control Register

MCU Debug Control Register

Reset Value

0x0000_0302

0x0000_0803

0x0000_0028

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0065

0x0001_0000

0x0000_0000

0x0000_0000

0x0100_0003

0x0000_0000

0x0000_0000

0xXXXX_0000 where X is undefined

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

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Global Clock Configuration Register – GCFGR

This register specifies the clock source for PLL/USB/LCD/CKOUT.

Offset: 0x000


31 30

LPMOD

29

Type/Reset RO 0 RO 0 RO 0

23 22 21

28 27 26

Reserved

25 24

20 19

Reserved

18 17 16

Type/Reset

13

CKREFPRE

10 9 8

USBSRC USBPLLSRC PLLSRC


7 6 5 4 3 2 1 0

Type/Reset

15 14

Reserved

12 11

LCDSRC Reserved

RW 0 RW 0

CKOUTSRC

RW 0 RW 1 RW 0

Bits

[31:29]

[15:11]

[10]

[9]

[8]

Field

LPMOD

Descriptions

Lower Power Mode Status

000: When chip is in running mode

001: When chip wants to enter Sleep mode

010: When chip wants to enter Deep-Sleep1 mode

011: When chip wants to enter Deep-Sleep2 mode

100: When chip wants to enter Power-Down mode

Set and reset by hardware.

CKREFPRE CK_REF Clock Prescaler Selection

CK_REF = CK_PLL / (CKREFPRE + 1) / 2

00000: CK_REF = CK_PLL / 2

00001: CK_REF = CK_PLL / 4

...

11111: CK_REF = CK_PLL / 64

Set and reset by software to control the CK_REF clock prescaler setting.

USBSRC USB Clock Source Selection

0: CK_PLL clock is selected

1: CK_USBPLL clock is selected

Set and reset by software to control the USB clock source.

USBPLLSRC USB PLL Clock Source Selection

0: External 4 ~ 16 MHz crystal oscillator clock is selected (HSE)

1: Internal 8 MHz RC oscillator clock is selected (HSI)

Set and reset by software to control the USB PLL clock source.

PLLSRC PLL Clock Source Selection

0: External 4 ~ 16 MHz crystal oscillator clock is selected (HSE)

1: Internal 8 MHz RC oscillator clock is selected (HSI)

Set and reset by software to control the PLL clock source.

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Bits

[5:4]

[2:0]


LCDSRC LCD Clock Source Selection

00: Internal 32 kHz RC oscillator clock is selected (LSI)

01: External 32.768 kHz crystal oscillator clock is selected (LSE)

10: HSI

11: HSE

When LCDSRC is selected, the LCDCPS field in the APBCFGR should be selected appropriately to make sure that LCDCLK is less than or equal to 1 MHz.

CKOUTSRC CKOUT Clock Source Selection

000: CK_REF is selected, CK_REF = CK_PLL / (CKREFPRE + 1) / 2

001: (HCLKC / 16) is selected

010: (CK_SYS / 16) is selected

011: (CK_HSE / 16) is selected

100: (CK_HSI / 16) is selected

101: CK_LSE is selected

110: CK_LSI is selected

111: Reserved

Set and reset by software to control the CKOUT clock source.

Global Clock Control Register – GCCR

This register specifies the clock enable bits.

Offset: 0x004


31 30

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

29 28 27

Reserved

26 25 24

21

13

Reserved

5

Reserved

20

Reserved

12

4

19

11

HSIEN

10

HSEEN

RW 0 RW 0

9 8

PLLEN HSEGAIN

RW 1 RW 0 RW 0 RW 0

3

USBPLLEN

18

2

17 16

PSRCEN CKMEN

1

SW

0

RW 0 RW 0 RW 1 RW 1

Bits

[17]

Field

PSRCEN

Descriptions

Power Saving Wakeup RC Clock Enable

0: No action

1: Use Internal 8 MHz RC clock (HSI) as system clock after a Deep-Sleep1/2 mode wakeup

Software can set PSRCEN high before entering the Deep-Sleep1/2 mode in order to reduce the waiting time after wakeup. When PSRCEN = 1, hardware will select HSI as clock source after the system wakeup from Deep-Sleep1/2 mode. Meanwhile, instruction can start execution since the HSI clock is provided to CPU. After the original clock source, which is selected as CK_SYS before entering the Deep-

Sleep1/2 mode, is ready, hardware will switch back the clock source as originally.

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[8]

[3]

[2:0]

Bits

[16]

[11]

[10]

[9]

Field

CKMEN

HSIEN

Descriptions

HSE Clock Monitor Enable

0: Disable external 4 ~ 16 MHz crystal oscillator clock monitor

1: Enable external 4 ~ 16 MHz crystal oscillator clock monitor

When hardware detects the HSE clock stuck at low/high state, internal hardware will switch the system clock to the internal high speed RC clock (HSI).

Internal High Speed Clock Enable

0: Internal 8 MHz RC oscillator clock is disabled

1: Internal 8 MHz RC oscillator clock is enabled

Set and reset by software. This bit can not be reset if the HSI clock is used as system clock or PLL input clock.

HSEEN

PLLEN

External High Speed Clock Enable

0: External 4 ~ 16 MHz crystal oscillator clock is disabled

1: External 4 ~ 16 MHz crystal oscillator clock is enabled

Set and reset by software. This bit can not be reset if the HSE clock is used as system clock or PLL input clock.

PLL Enable

0: PLL off

1: PLL on

Set and reset by software to control the PLL. This bit can not be reset if the PLL clock is used as system clock.

HSEGAIN External High Speed Clock Gain Selection

0: HSE low gain mode

1: HSE high gain mode

USBPLLEN USB PLL Enable

0: USB PLL is disabled

1: USB PLL is enabled

Set and reset by software to control the USB PLL.

SW System Clock Switch

00x: CK_PLL clock out as system clock

010: CK_HSE as system clock

011: CK_HSI as system clock

110: CK_LSE as system clock

111: CK_LSI as system clock

Other: CK_HSI as system clock

These bits are used to select the CK_SYS source. If the HSE oscillator is used directly or indirectly as the system clock and the HSE clock monitor function is enabled, once the HSE failure is detected, these bits will be set by hardware to force

HSI (b011) as the system clock.

Note: When switching the system clock using the SW field, the system clock will not be immediately switched and a certain delay is necessary. Software can monitor the CKSWST field in the clock source status register CKSTR to make sure which clock is currently used as the system clock.

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Global Clock Status Register – GCSR

This register indicates the clock ready status.

Offset: 0x008


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

14 13 12 11

Reserved

10 9 8

6 5 4 3 2 1 0

Reserved LSIRDY LSERDY HSIRDY HSERDY PLLRDY USBPLLRDY

RO 1 RO 0 RO 1 RO 0 RO 0 RO 0

Bits

[5]

[4]

[3]

[2]

[1]

[0]

Field

LSIRDY

Descriptions

Internal Low Speed Clock Ready Flag

0: Internal 32 kHz RC oscillator clock is not ready

1: Internal 32 kHz RC oscillator clock is ready

Set by hardware to indicate that the LSI is stable to be used.

LSERDY

HSIRDY

HSERDY

External Low Speed Clock Ready Flag

0: External 32,768 Hz crystal oscillator clock is not ready

1: External 32,768 Hz crystal oscillator clock is ready

Set by hardware to indicate that the LSE is stable to be used.

Internal High Speed Clock Ready Flag

0: Internal 8 MHz RC oscillator clock is not ready

1: Internal 8 MHz RC oscillator clock is ready

Set by hardware to indicate whether the HSI is stable or not.

External High Speed Clock Ready Flag

0: External 4 ~ 16 MHz crystal oscillator clock is not ready

1: External 4 ~ 16 MHz crystal oscillator clock is ready

Set by hardware to indicate that the HSE is stable to be used.

PLLRDY PLL Clock Ready Flag

0: PLL is not ready

1: PLL is ready

Set by hardware to indicate that the PLL is stable to be used.

USBPLLRDY USB PLL Clock Ready Flag

0: USB PLL is not ready

1: USB PLL is ready

Set by hardware to indicate that the USB PLL is stable to be used.

Rev. 1.00 91 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Global Clock Interrupt Register – GCIR

This register specifies interrupt enable and flag bits.

Offset: 0x00C


31 30 29

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

Reserved

27

Reserved

19

12

4

Reserved

11

Reserved

3

Type/Reset

Bits

[16]

[0]

Field

CKSIE

CKSF

26

18

10

25

17

9

24

16

CKSIE

RW 0

8

2 1 0

CKSF

WC 0

Descriptions

Clock Stuck Interrupt Enable

0: Disable clock fail interrupt

1: Enable clock fail interrupt

Set and reset by software to enable/disable interrupt caused by clock monitor.

Clock Stuck Interrupt Flag

0: Clock works normally

1: HSE clock is stuck

Set by hardware when the HSE clock stuck and CKMEN is set. Reset by software writing 1.

Rev. 1.00 92 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

PLL Configuration Register – PLLCFGR

This register specifies PLL configuration.

Offset: 0x018


31 30

Reserved

29

Type/Reset

23

PFBD

22 21

POTD

Type/Reset RW 0 RW 0 RW 0

15 14 13

Reserved

Type/Reset

7

USBPFBD

6 5

USBPOTD


28 27

REFDIV Reserved

RW 0

20 19

12

4

11

3

26 25

PFBD

24

RW 0 RW 0 RW 0

18

Reserved

17 16

10 8

RW 0 RW 0 RW 0

2 1 0

Reserved

9

USBPFBD

Bits

[28]

[26:23]

[22:21]

[10:7]

[6:5]

Field

REFDIV

PFBD

Descriptions

PLL Input Reference Clock Divider

0: Reference divider NR = 2

1: Reference divider NR = 4

PLL VCO Output Clock Feedback Divider (B3 ~ B0 in PLL Block Diagram)

Feedback Divider divides the output clock from VCO of PLL.

POTD PLL Output Clock Divider (S1 ~ S0 in PLL Block Diagram)

USBPFBD USB PLL VCO Output Clock Feedback Divider (B3 ~ B0 in USB PLL Block Diagram)

Feedback Divider divides the output clock from VCO of USB PLL.

USBPOTD USB PLL Output Clock Divider (S1 ~ S0 in USB PLL Block Diagram)

Rev. 1.00 93 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

PLL Control Register – PLLCR

This register specifies Bypass mode control of PLL.

Offset: 0x01C


30 29 31

PLLBPS

Type/Reset RW 0

23

Type/Reset

15

Type/Reset

7

Type/Reset

22

14

6

21

13

5

Bits

[31]

Field

PLLBPS

28

20

12

4

Descriptions

PLL Bypass Mode Enable

0: Disable PLL Bypass mode

1: Enable PLL Bypass mode where f

OUT

= f

IN

27

Reserved

19

Reserved

11

Reserved

3

Reserved

26

18

10

2

25

17

9

1

24

16

8

0

Rev. 1.00 94 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

AHB Configuration Register – AHBCFGR

This register specifies the system clock frequency.

Offset: 0x020


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11

Reserved

3

10 9 8

2 1

AHBPRE

0

RW 0 RW 0 RW 0

Bits

[2:0]

Field

AHBPRE

Descriptions

AHB Pre-scaler

000: CK_AHB = CK_SYS

001: CK_AHB = CK_SYS / 2







Set and reset by software to control the division factor of the AHB clock.

Rev. 1.00 95 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

AHB Clock Control Register – AHBCCR

This register specifies clock enable bits of AHB peripherals.

Offset: 0x024


Type/Reset

31

23

30

22

Reserved

29

21

28

Reserved

27 26 25 24

DIVEN

RW 0

20

PEEN

19

PDEN

18

PCEN

17

PBEN

16

PAEN

RW 0 RW 0 RW 0 RW 0 RW 0 Type/Reset

15 14 13 12 11 10

AESEN Reserved CRCEN Reserved CKREFEN USBEN

9 8

Reserved

Type/Reset RW 0

Type/Reset

7

Reserved

6

APBEN

RW 0

5

BMEN

4

RW 1 RW 1 RW 0

RW 0 RW 0

3 2

PDMAEN Reserved SRAMEN Reserved FMCEN

RW 1

1 0

RW 1

Bits

[24]

[20]

[19]

[18]

[17]

[16]

[15]

Field

DIVEN

PEEN

PDEN

PCEN

PBEN

PAEN

AESEN

Descriptions

Divider Clock Enable

0: Divider clock is disabled

1: Divider clock is enabled

Set and reset by software.

GPIO Port E Clock Enable

0: Port E clock is disabled

1: Port E clock is enabled


GPIO Port D Clock Enable

0: Port D clock is disabled

1: Port D clock is enabled


GPIO Port C Clock Enable

0: Port C clock is disabled

1: Port C clock is enabled


GPIO Port B Clock Enable

0: Port B clock is disabled

1: Port B clock is enabled


GPIO Port A Clock Enable

0: Port A clock is disabled

1: Port A clock is enabled


AES Module Clock Enable

0: AES clock is disabled

1: AES clock is enabled


Rev. 1.00 96 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[13]

[11]

[10]

[6]

[5]

[4]

[2]

[0]


CRCEN CRC Module Clock Enable

0: CRC clock is disabled

1: CRC clock is enabled


CKREFEN CK_REF Clock Enable

0: CK_REF clock is disabled

1: CK_REF clock is enabled


USBEN

APBEN

BMEN

PDMAEN

SRAMEN

FMCEN

USB Clock Enable

0: USB clock is disabled

1: USB clock is enabled


APB bridge Clock Enable

0: APB bridge clock is automatically disabled by hardware during Sleep mode

1: APB bridge clock is always enabled during Sleep mode

Set and reset by software. Users can set APBEN as 0 to reduce power consumption if the APB bridge is unused during Sleep mode.

Bus Matrix Clock Enable

0: Bus Matrix clock is automatically disabled by hardware during Sleep mode

1: Bus Matrix clock is always enabled during Sleep mode

Set and reset by software. Users can set BMEN as 0 to reduce power consumption if the bus matrix is unused during Sleep mode.

Peripheral DMA Clock Enable

0: PDMA clock is disabled

1: PDMA clock is enabled


Note: The PDMA can independently operate when the processor enters the sleep mode. But the relative clock of AHB bus slave or peripherals has to be enabled.

SRAM Clock Enable

0: SRAM clock is automatically disabled by hardware during Sleep mode

1: SRAM clock is always enabled during Sleep mode

Set and reset by software. Users can set SRAMEN as 0 to reduce power consumption if the SRAM is unused during Sleep mode.

Flash Memory Controller Clock Enable

0: FMC clock is automatically disabled by hardware during Sleep mode

1: FMC clock is always enabled during Sleep mode

Set and reset by software. Users can set FMCEN as 0 to reduce power consumption if the Flash Memory is unused during Sleep mode.

Rev. 1.00 97 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

APB Configuration Register – APBCFGR

This register specifies the ADC conversion clock frequency and LCD Clock Prescaler Selection.

Offset: 0x028


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

Reserved

13

Reserved

5

20

12

4

27

Reserved

26 25 24

19

11

3

Reserved

18 17

ADCDIV

16

RW 0 RW 0 RW 1

10 9

LCDCPS

8

RW 0 RW 0 RW 0

2 1 0

Type/Reset

Bits

[18:16]

[10:8]

Field

ADCDIV

LCDCPS

Descriptions

ADC Clock Frequency Division Selection

000: CK_ADC = CK_AHB

001: CK_ADC = CK_AHB / 2







Set and reset by software to control the ADC conversion clock division factor.

LCD Clock Prescaler Selection

000: No divider and bypass

001: Divided by 2 for LCD clock




Others: Reserved

When LCD clock source is selected in the LCDSRC filed of the GCFGR register,

LCDCPS should be appropriately configured to make sure LCDCLK clock is less than or equal to 1 MHz.

Rev. 1.00 98 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

APB Clock Control Register 0 – APBCCR0

This register specifies clock enable bits of APB peripherals.

Offset: 0x02C


Type/Reset

31

23

30

22

29

Reserved

21

28

20

27 26

SCI1EN Reserved

RW 0

19

Reserved

18

25

I2SEN

24

SCI0EN

RW 0 RW 0

17 16

Type/Reset

Type/Reset

15

EXTIEN

14

AFIOEN

13


7 6 5

Reserved SPI1EN

12 11

Reserved UR1EN

4

SPI0EN

RW 0 RW 0

3

10

UR0EN

RW 0 RW 0

2

9 8

Reserved USREN

1

Reserved I2C1EN

RW 0

0

I2C0EN

RW 0 RW 0

Bits

[27]

[25]

[24]

[15]

[14]

[11]

[10]

Field

SCI1EN

I2SEN

SCI0EN

EXTIEN

AFIOEN

UR1EN

UR0EN

Descriptions

Smart Card Interface 1 Clock Enable

0: SCI1 clock is disabled

1: SCI1 clock is enabled


I 2 S Interface Clock Enable

0: I

1: I

2

2

S clock is disabled

S clock is enabled


Smart Card Interface 0 Clock Enable

0: SCI0 clock is di abled

1: SCI0 clock is enabled


External Interrupt Clock Enable

0: EXTI clock is disabled

1: EXTI clock is enabled


Alternate Function I/O Clock Enable

0: AFIO clock is disabled

1: AFIO clock is enabled


UART1 Clock Enable

0: UART1 clock is disabled

1: UART1 clock is enabled


UART0 Clock Enable

0: UART0 clock is disabled

1: UART0 clock is enabled


Rev. 1.00 99 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[8]

[5]

[4]

[1]

[0]

Field

USREN

SPI1EN

SPI0EN

I2C1EN

I2C0EN

Descriptions

USART Clock Enable

0: USART clock is disabled

1: USART clock is enabled


SPI1 Clock Enable

0: SPI1 clock is disabled

1: SPI1 clock is enabled


SPI0 Clock Enable

0: SPI0 clock is disabled

1: SPI0 clock is enabled


I 2 C1 Clock Enable

0: I 2 C1 clock is disabled

1: I 2 C1 clock is enabled


I 2 C0 Clock Enable

0: I 2 C0 clock is disabled

1: I 2 C0 clock is enabled


Rev. 1.00 100 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

APB Clock Control Register 1 – APBCCR1

This register specifies clock enable bits of APB peripherals.

Offset: 0x030


Type/Reset

Type/Reset

Type/Reset

Type/Reset

31

15

30 29 28

Reserved SCTM1EN SCTM0EN

RW 0 RW 0

14 13 12

Reserved PWM1EN PWM0EN

7 6

RW 0 RW 0

5 4

Reserved VDDREN Reserved WDTREN

RW 0 RW 0

27

11

3

26

Reserved

10

Reserved

2

25

1

Reserved

24

ADCCEN

RW 0

23 22 21 20 19 18 17 16

Reserved CMPEN DACCEN LCDCEN LCDREN Reserved BFTM1EN BFTM0EN

RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

9 8

GPTMEN

RW 0

0

Bits

[29]

[28]

[24]

[22]

[21]

[20]

[19]


SCTM1EN SCTM1 Clock Enable

0: SCTM1 clock is disabled

1: SCTM1 clock is enabled


SCTM0EN SCTM0 Clock Enable

0: SCTM0 clock is disabled

1: SCTM0 clock is enabled


ADCCEN ADC Controller Clock Enable

0: ADC clock is disabled

1: ADC clock is enabled


CMPEN CMP Controller Clock Enable

0: CMP clock is disabled

1: CMP clock is enabled


DACCEN

LCDCEN

LCDREN

DAC Controller Clock Enable

0: DAC clock is disabled

1: DAC clock is enabled


LCD Controller Clock Enable

0: LCO controller clock is disabled

1: LCD controller clock is enabled


LCD Register Clock Enable

0: LCD register clock is disabled

1: LCD register clock is enabled


Rev. 1.00 101 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[17]

[16]

[13]

[12]

[8]

[6]

[4]


BFTM1EN BFTM1 Clock Enable

0: BFTM1 clock is disabled

1: BFTM1 clock is enabled


BFTM0EN BFTM0 Clock Enable

0: BFTM0 clock is disabled

1: BFTM0 clock is enabled


PWM1EN

PWM0EN

GPTMEN

VDDREN

WDTREN

PWM1 Clock Enable

0: PWM1 clock is disabled

1: PWM1 clock is enabled


PWM0 Clock Enable

0: PWM0 clock is disabled

1: PWM0 clock is enabled


GPTM Clock Enable

0: GPTM clock is disabled

1: GPTM clock is enabled


V

DD

Domain Clock Enable for Registers Access

0: Register access clock is disabled

1: Register access clock is enabled


Watchdog Timer Clock Enable for Registers Access

0: Register access clock is disabled

1: Register access clock is enabled


Rev. 1.00 102 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Clock Source Status Register – CKST

This register specifies status of various clock sources.

Offset: 0x034


31 30 28

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

29

Reserved

21

Reserved

13

Reserved

5

Reserved

20

12

4

Type/Reset

27 26 25

HSIST

24

RO 0 RO 0 RO 0 RO 1

19 18 17

HSEST

16

RO 0 RO 0 RO 0

11 10 9

PLLST

8

RO 0 RO 0 RO 0 RO 0

3 2 1 0

CKSWST

RO 0 RO 1 RO 1

Bits

[27:24]

[18:16]

[11:8]

[2:0]

Field

HSIST

HSEST

PLLST

CKSWST

Descriptions

Internal High Speed Clock Occupation Status (CK_HSI) xxx1: HSI is used by System Clock (CK_SYS) (SW = 0x3) xx1x: HSI is used by System PLL x1xx: HSI is used by Clock Monitor

1xxx: HSI is used by USB PLL

External High Speed Clock Occupation Status (CK_HSE) xx1: HSE is used by System Clock (CK_SYS) (SW = 0x2) x1x: HSE is used by System PLL

1xx: HSE is used by USB PLL

PLL Clock Occupation Status xxx1: PLL is used by System Clock (CK_SYS) xx1x: PLL is used by USART x1xx: PLL is used by USB

1xxx: PLL is used by CK_REF

Clock Switch Status

00x: CK_PLL clock out as system clock

010: CK_HSE as system clock

011: CK_HSI as system clock

110: CK_LSE as system clock

111: CK_LSI as system clock

The fields are status to indicate which clock source is using as system clock currently.

Rev. 1.00 103 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

APB Peripheral Clock Selection Register 0 – APBPCSR0

This register specifies APB peripheral clock prescaler selection.

Offset: 0x038


31 30

UR1PCLK

29 28

UR0PCLK

Type/Reset RW 0 RW 0 RW 0 RW 0

Type/Reset

23 22

Reserved

21 20

GPTMPCLK

RW 0 RW 0

27

19

26

Reserved

18

25 24

USRPCLK

RW 0 RW 0

17

Reserved

16

15 14

BFTM1PCLK

13 12

BFTM0PCLK

11 10 9

Reserved

8


7 6

SPI1PCLK

5 4

SPI0PCLK

3 2

I2C1PCLK

1 0

I2C0PCLK


Bits

[31:30]

[29:28]

[25:24]

[21:20]

[15:14]


UR1PCLK

UR0PCLK

USRPCLK

GPTMPCLK

UART1 Peripheral Clock Selection

00: PCLK = CK_AHB

01: PCLK = CK_AHB / 2



PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

UART0 Peripheral Clock Selection

00: PCLK = CK_AHB





USART Peripheral Clock Selection

00: PCLK = CK_AHB





GPTM Peripheral Clock Selection

00: PCLK = CK_AHB





BFTM1PCLK BFTM1 Peripheral Clock Selection

00: PCLK = CK_AHB

01: PCLK = CK_AHB/2

10: PCLK = CK_AHB/4

11: PCLK = CK_AHB/8


Rev. 1.00 104 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[13:12]

[7:6]

[5:4]

[3:2]

[1:0]


BFTM0PCLK BFTM0 Peripheral Clock Selection

00: PCLK = CK_AHB





SPI1PCLK SPI1 Peripheral Clock Selection

00: PCLK = CK_AHB





SPI0PCLK SPI0 Peripheral Clock Selection

00: PCLK = CK_AHB





I2C1PCLK

I2C0PCLK

I 2 C1 Peripheral Clock Selection

00: PCLK = CK_AHB





I 2 C0 Peripheral Clock Selection

00: PCLK = CK_AHB





Rev. 1.00 105 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU


This register specifies APB peripheral clock prescaler selection.

Offset: 0x03C


Type/Reset

31

23

30

22

Reserved

29

Reserved

28 27 26

SCTM1PCLK

25 24

SCTM0PCLK

RW 0 RW 0 RW 0 RW 0

21 20

I2SPCLK

19 18

SCI1PCLK

17 16

SCI0PCLK

RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Type/Reset

15 14

VDDRPCLK

13 12

WDTRPCLK

11 10

Reserved

9 8

CMPPCLK


Type/Reset

7 6

Reserved

5 4

ADCPCLK

3 2

EXTIPCLK

RW 0 RW 0

1 0

AFIOPCLK


Bits

[27:26]

[25:24]

[21:20]

[19:18]

[17:16]


SCTM1PCLK SCTM1 Peripheral Clock Selection

00: PCLK = CK_AHB





SCTM0PCLK SCTM0 Peripheral Clock Selection

00: PCLK = CK_AHB





I2SPCLK I 2 S Peripheral Clock Selection

00: PCLK = CK_AHB





SCI1PCLK

SCI0PCLK

SCI1 Peripheral Clock Selection

00: PCLK = CK_AHB





SCI0 Peripheral Clock Selection

00: PCLK = CK_AHB





Rev. 1.00 106 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[15:14]

[13:12]

[9:8]

[5:4]

[3:2]

[1:0]


VDDRPCLK

WDTRPCLK WDT Register Access Clock Selection

00: PCLK = CK_AHB





CMPPCLK

V

DD

Domain Register Access Clock Selection






CMP Peripheral Clock Selection

00: PCLK = CK_AHB





ADCPCLK

EXTIPCLK

AFIOPCLK

ADC Peripheral Clock Selection

00: PCLK = CK_AHB





EXTI Peripheral Clock Selection

00: PCLK = CK_AHB





AFIO Peripheral Clock Selection

00: PCLK = CK_AHB





Rev. 1.00 107 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

HSI Control Register – HSICR

This register is used to control the frequency trimming of the HSI RC oscillation.

Offset: 0x040

Reset value: 0xXXXX_0000 where X is undefined

Type/Reset

31

23

30

Reserved

22

29

21

28 27 26

HSICOARSE

25 24

RO X RO X RO X RO X RO X

20 19

HSIFINE

18 17 16

15 14 13 12 11

Reserved

10 9 8

Type/Reset

7

FLOCK

6 5

REFCLKSEL

4

TMSEL

3

ATMSEL

2

LTRSEL

1

ATCEN

0

TRIMEN

Type/Reset RO 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

Bits

[28:24]

[23:16]

[7]

[6:5]

[4]

[3]


HSICOARSE HSI Clock Coarse Trimming Value

These bits are initialized automatically at startup. They are adjusted by factory trimming and can not be trimmed by program.

HSIFINE

FLOCK

HSI Clock Fine Trimming Value

These bits are initialized automatically at startup. They are also adjusted by factory trimming. But these bits provide an additional user-programmable trimming value that is added to the HSICOARSE[4:0] bits to get more accurate or compensate the variations in voltage and temperature that influence the HSI frequency. It can be programmed by software or automatically adjusted by the

Auto Trimming Controller (ATC) together with an external reference clock.

Frequency Lock

0: HSI frequency is not trimmed into target range

1: HSI frequency is trimmed into target range

REFCLKSEL Reference Clock Selection

00: Select 32.768 kHz external low speed clock source (LSE)

01: Select 1 kHz USB frame pulse

1x: Select external pin (CKIN) 1 kHz pulse

These bits are used to select the reference clock for the HSI Auto Trimming

Controller.

TMSEL Trimming Mode Selection

0: Automatic by Auto Trimming Controller

1: Manual by user program

This bit is used to select the HSI RC oscillator trimming function by ATC hardware or user programming via the HSIFINE field in this register.

ATMSEL Automatic Trimming Mode Selection

0: Auto Trimming Controller is used binary search to approach the target range

1: Auto Trimming Controller is used linear search to approach the target range

This bit is used to select the automatic trimming method by ATC hardware for the

HSI RC oscillator.

Rev. 1.00 108 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[2]

[1]

[0]

Field

LTRSEL

ATCEN

TRIMEN

Descriptions

Lock Target Range Selection

0: 0.1 % variation

1: 0.2 % variation

This bit is used to select the lock target range of the internal HSI RC oscillator trimming function for 0.1 % or 0.2 % variation.

ATC Enable

0: Disable Auto Trimming Controller

1: Enable Auto Trimming Controller

Trimming Enable

0: HSI Trimming is disabled

1: HSI Trimming is enabled

Setting this bit high enables the HSI RC oscillator trimming function by ATC hardware or user programming.

HSI Auto Trimming Counter Register – HSIATCR

This register contains the counter value of the HSI auto trimming controller

Offset: 0x044


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

15

7

14

Reserved

6

13

5

12

4

11

3

10

ATCNT

2

9

1

8


0

ATCNT


Bits

[13:0]

Field

ATCNT

Descriptions

Auto Trimming Counter

This bit field contains the counter value of the HSI auto trimming controller.

Rev. 1.00 109 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU


This register specifies the APB peripheral clock prescaler selection.

Offset: 0x048


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30 29 28 27

Reserved

26 25 24

22

14

6

Reserved

21

Reserved

13

5

20

12

4

LCDPCLK

19 18

PWM1PCLK

17 16

PWM0PCLK

RW 0 RW 0 RW 0 RW 0

11

Reserved

10 9 8

3 2

DACPCLK

RW 0 RW 0 RW 0 RW 0

1 0

Reserved

Bits

[19:18]

[17:16]

[5:4]

[3:2]


PWM1PCLK PWM1 Peripheral Clock Selection

00: PCLK = CK_AHB





PWM0PCLK PWM0 Peripheral Clock Selection

00: PCLK = CK_AHB





LCDPCLK LCD Peripheral Clock Selection

00: PCLK = CK_AHB





DACPCLK DAC Peripheral Clock Selection

00: PCLK = CK_AHB





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Low Power Control Register – LPCR

This register specifies low power control.

Offset: 0x300


31 30 29

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

Reserved

4

11

3

Reserved

Type/Reset

Bits

[8]

26

18

10

2

25

17

9

1

24

16

8

USBSLEEP

RW 0

0


USBSLEEP USB Sleep Software Control Enable

0: Disable USB Software Sleeping

1: Enable USB Software Sleeping

Set and reset by software. Please refer to the Power Control Unit chapter for more information.

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Cortex ® -M0+ MCU

MCU Debug Control Register – MCUDBGCR

This register specifies the debug control of MCU.

Offset: 0x304

Reset value: 0x0000_0000 (Reset by V

DD

domain reset only)

31 30

DBPWM1 DBPWM0


29 28 27 26

Reserved

25 24

23 22 21 20 19

DBSCTM1 DBSCTM0 DBSCI1 Reserved DBUR1


18

DBUR0

17 16

DBBFTM1 DBBFTM0

RW 0 RW 0 RW 0 RW 0

15 14 13

DBSCI0 DBDSLP2 DBI2C1

12

DBI2C0

11

DBSPI1

10 9 8

DBSPI0 Reserved DBUSR

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

7 6

Reserved DBGPTM

5 4

Reserved

3

DBWDT

2 1

RW 0

0

DBPD DBDSLP1 DBSLP

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0

Bits

[31]

[30]

[23]

[22]

[21]

[19]

[18]

Field

DBPWM1

Descriptions

PWM1 Debug Mode Enable

0: PWM1 counter continues to count even if the core is halted

1: PWM1 counter is stopped when the core is halted


DBPWM0 PWM0 Debug Mode Enable

0: PWM0 counter continues to count even if the core is halted

1: PWM0 counter is stopped when the core is halted


DBSCTM1 SCTM1 Debug Mode Enable

0: SCTM1 counter continues even if the core is halted

1: SCTM1 counter is stopped when the core is halted


DBSCTM0 SCTM0 Debug Mode Enable

0: SCTM0 counter continues even if the core is halted

1: SCTM0 counter is stopped when the core is halted


DBSCI1

DBUR1

DBUR0

SCI1 Debug Mode Enable

0: Same behavior as in normal mode

1: SCI1 timeout is frozen when the core is halted


UART1 Debug Mode Enable


1: UART1 FIFO timeout is frozen when the core is halted


UART0 Debug Mode Enable


1: UART0 FIFO timeout is frozen when the core is halted


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Cortex ® -M0+ MCU

Bits

[17]

[10]

[8]

[12]

[11]

[16]

[15]

[14]

[13]

[6]

[3]

[2]


DBBFTM1 BFTM1 Debug Mode Enable

0: BFTM1 counter continues to count even if the core is halted

1: BFTM1 counter is stopped when the core is halted


DBBFTM0 BFTM0 Debug Mode Enable

0: BFTM0 counter continues to count even if the core is halted

1: BFTM0 counter is stopped when the core is halted


DBSCI0

DBDSLP2 Debug Deep-Sleep2 Mode

0: LDO = ULDO on, FCLK = Off and CM0PEN = 0 in Deep-Sleep2 mode

1: LDO = MLDO on, FCLK = On and CM0PEN = 1 in Deep-Sleep2 mode


DBI2C1

SCI0 Debug Mode Enable


1: SCI0 timeout is frozen when the core is halted


I 2 C1 Debug Mode Enable


1: I 2 C1 timeout is frozen when the core is halted


DBI2C0

DBSPI1

DBSPI0

DBUSR

I 2 C0 Debug Mode Enable


1: I 2 C0 timeout is frozen when the core is halted


SPI1 Debug Mode Enable


1: SPI1 FIFO timeout is frozen when the core is halted


SPI0 Debug Mode Enable


1: SPI0 FIFO timeout is frozen when the core is halted


USART Debug Mode Enable


1: USART FIFO timeout is frozen when the core is halted


DBGPTM

DBWDT

DBPD

GPTM Debug Mode Enable

0: GPTM counter continues to count even if the core is halted

1: GPTM counter is stopped when the core is halted


Watchdog Timer Debug Mode Enable

0: Watchdog Timer counter continues to count even if the core is halted

1: Watchdog Timer counter is stopped when the core is halted


Debug Power-Down Mode

0: MLDO = Off, FCLK = Off and CM0PEN = 0 in Power-Down mode

1: MLDO = On, FCLK = On and CM0PEN = 1 in Power-Down mode


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Bits

[1]

[0]


DBDSLP1 Debug Deep-Sleep1 Mode

0: LDO = ULDO on, FCLK = Off and CM0PEN = 0 in Deep-Sleep1 mode

1: LDO = MLDO on, FCLK = On and CM0PEN = 1 in Deep-Sleep1 mode


DBSLP Debug Sleep Mode

0: MLDO = On, FCLK = On and CM0PEN = 0 in Sleep mode

1: MLDO = On, FCLK = On and CM0PEN = 1 in Sleep mode


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7

Power Control Unit (PWRCU)

Introduction

The power consumption can be regarded as one of the most important issues for many embedded system applications. Accordingly the Power Control Unit, PWRCU, provides many types of power saving modes such as Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down modes. These modes reduce the power consumption and allow the application to achieve the best trade-off between the conflicting demands of CPU operating time, speed and power consumption. The dash line in the

Figure 19 indicates the power supply source of two digital power domains.

V

DD nRST

WAKEUP

RTCOUT

RTC

LSI

LSE

WKUP1

WKUP2

WKUP3

HSE

PWR_CTRL

LDOOFF

LDOLCM

ULDOON

LDO

Controller

V

DD

Domain

MLDO

ULDO

WKUP4

3.3 V

POR/PDR

LVD

SLEEPDEEP

SLEEPING

MCU

Core

V

DD15

1.5 V Domain

Memories

1.5 V

POR

APB I/F

Digital

Peripheral

HSI

PLL

V

DD15

V

LDOOUT

MLDO: Main Voltage Regulator

ULDO: Ultra-low Power Voltage Regulator

Figure 19. PWRCU Block Diagram

LVD: Low Voltage Detector

POR/PDR: Power On Reset/Power Down Reset

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Features

▆

▆

▆

▆

▆

▆

▆

Three power domains: V

DD

3.3 V, V

LCD

and V

DD15

1.5 V power domains

Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down modes

Internal Voltage regulator supplies 1.5 V voltage source

Additional ultra-low power voltage regulator supplies 1.5 V voltage source with low static current and low operating current

A power reset is generated when one of the following events occurs:

● Power-on / Power-down reset (POR / PDR reset)

● When exiting Power-Down mode

● The control bits BODEN = 1, BODRIS = 0 and the supply power V

DD

≤ V

BOD

The Brown-Out Detector can issue a system reset or an interrupt when V

DD than the Brown-Out Detector voltage V

BOD

.

power source is lower

The Low Voltage Detector can issue an interrupt or wakeup event when V

DD programmable threshold voltage V

LVD

.

is lower than a


V

DD

Power Domain

LDO Power Control

The main LDO and ultra-low power LDO (ULDO) will be automatically switched off when one of the following conditions occurs:

▆

▆

The Power-Down mode is entered

The supply power V

DD

≤ V

PDR

The main LDO will be automatically switched on by hardware when the supply power V if any of the following conditions occurs:

DD

> V

POR

▆

▆

▆

Resume operation from the power saving mode – RTC wakeup, LVD wakeup and WAKEUP pin rising edge

Detect a falling edge on the external reset pin (nRST)

The control bit BODEN = 1 and the supply power V

DD

> V

BOD

To enter the Deep-Sleep1 or Deep-Sleep2 mode, the PWRCU will turn off the main LDO and request the ULDO to operate in the low standby current mode to supply an alternative 1.5 V power.

Voltage Regulator

The main voltage regulator, LDO, ultra-low power LDO, ULDO, Low voltage Detector, LVD, Low

Speed Internal RC oscillator, LSI, High Speed External Crystal oscillator, HSE, and the Low Speed

External Crystal oscillator, LSE, are operated under the V

DD

power domain. The main LDO can be configured to operate in normal mode (LDOOFF = 0, LDOLCM = 0, I

OUT

= high current mode) and the ultra-low power LDO can be configured to operate in low current mode (LDOOFF = 0,

LDOLCM = 1, I

OUT

= low current mode) to supply the 1.5 V power. The ULDO output has ultralow static current characteristics and can be configured to operate in the Deep-Sleep2 mode for data retention purposes in the V

PWRCR register.

DD15

power domain. It is controlled using the ULDOON bit in the

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Cortex ® -M0+ MCU

Power-On Reset (POR) / Power-Down Reset (PDR)

The device has an integrated POR/PDR circuitry that allows proper operation starting from/ down to 1.65 V. When the device enters the Power-Down mode, it will remain in the Power-Down mode if V

DD

is below a specified threshold V characteristics of the corresponding datasheet.

PDR

, without the need for an external reset circuit. For more details concerning the power-on/power-down reset threshold voltage, refer to the electrical

V

DD

V

POR

Hysteresis

V

PDR

Time t

RSTD

POR Delay Time

RESET

Figure 20. Power-On Reset / Power-Down Reset Waveform

Low Voltage Detector / Brown-Out Detector

The Low Voltage Detector, LVD, can detect whether the supply voltage V programmable threshold voltage V

DD

is lower than a

LVD

. It is selected by the LVDS field in the LVDCSR register.

When a low voltage on the VDD power pin is detected, the LVDF flag will be active and an interrupt will be generated and sent to the MCU core if the LVDEN and LVDIWEN bits in the

LVDCSR register are set. For more details concerning the LVD programmable threshold voltage

V

LVD

, refer to the electrical characteristics of the corresponding datasheet.

The Brown-Out Detector, BOD, is used to detect if the V than V

BOD

DD

supply voltage is equal to or lower

. When the BODEN bit in the LVDCSR register is set to 1 and the V is lower than V

BOD

DD

supply voltage

then the BODF flag is active. The PWRCU will regard this as a power-down reset situation and then immediately disable the internal LDO regulator when the BODRIS bit is cleared to 0 or issue an interrupt to notify the CPU to execute a power-down procedure when the

BODRIS bit is set to 1. For more details concerning the Brown-Out Detector voltage V

BOD

, refer to the electrical characteristics of the corresponding datasheet.

High Speed External Oscillator

The High Speed External Oscillator, HSE, is located in the V

DD

power domain. The HSE crystal oscillator can be switched on or off using the HSEEN bit in the Global Clock Control Register,

GCCR. The HSE clock can then be used directly as the system clock source or be used as the PLL input clock.

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LSE, LSI and RTC

The Real Time Clock Timer clock source can be derived from either the Low Speed Internal RC oscillator, LSI, or the Low Speed External Crystal oscillator, LSE. Before entering the power saving mode by executing the WFI/WFE instruction, the MCU needs to setup the compare register with an expected wakeup time and enable the wakeup function to achieve the RTC timer wakeup event. After entering the power saving mode for a certain amount of time, the Compare Match flag, CMFLAG, will be asserted to wake up the device when the compare match event occurs. The details of the RTC configuration for wakeup timer will be described in the RTC chapter.

1.5 V Power Domain

The main functions that include the APB interface for the V

DD

domain, MCU core logic, AHB/APB peripherals and memories and so on are located in this power domain. Once the 1.5 V is powered up, the POR will generate a reset sequence on the 1.5 V power domain. Subsequently, to enter the expected power saving mode, the associated control bits including the LDOOFF, ULDOON and

LDOLCM bits must be configured. Then, once a WFI or WFE instruction is executed, the device will enter the expected power saving mode which will be discussed in the following section.

High Speed Internal Oscillator

The High Speed Internal Oscillator, HSI, is located in the V

DD15

1.5 V power domain. When exiting from the Deep-Sleep mode, the HSI clock can be configured as the system clock for a certain period by setting the PSRCEN bit to 1. This bit is located in the Global Clock Control Register,

GCCR, in the Clock Control Unit, CKCU. The system clock will not be switched back to the original clock source used before entering the Deep-Sleep mode until the original clock source, which may be either sourced from the PLL or HSE stabilizes. Also the system will force the HSI oscillator to be the system clock after a wakeup from Power-Down mode since a 1.5 V power-on reset will occur.

V

LCD

Power Domain

Most of the LCD circuits, including COM & SEG drivers, analog switches/MUX, resister ladders etc., are located in the V

LCD

Power Domain, the V power source or the internal charge pump circuit.

LCD

power can be supplied by either an external

Operation Modes

Run Mode

In the Run mode, the system operates with full functions and all power domains are active. There are two ways to reduce the power consumption in this mode. The first is to slow down the system clock by setting the AHBPRE field in the CKCU AHBCFGR register, and the second is to turn off the unused peripherals clock by setting the APBCCR0 and APBCCR1 registers or slow down the peripherals clock by setting the APBPCSR0 and APBPCSR1 registers to meet the application requirement. Reducing the system clock speed before entering the sleep mode will also help to minimize power consumption.

Additionally, there are several power saving modes to provide maximum optimization between device performance and power consumption.

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Table 18. Operation Mode Definitions

Mode Name

Run

Sleep

Deep-Sleep1 ~ 2

Hardware Action

After system reset, CPU fetches instructions to execute.

CPU clock will be stopped.

Peripherals, Flash and SRAM clocks can be stopped by setting.

Stop all clocks in the 1.5 V power domain.

Disable HSI, HSE and PLL.

Turn on the ultra-low power ULDO to reduce the 1.5 V power domain current.

Power-Down Shut down the 1.5 V power domain.

Sleep Mode

By default, only the CPU clock will be stopped in the Sleep mode. Clearing the FMCEN or

SRAMEN bit in the CKCU AHBCCR register to zero will have the effect of stopping the Flash clock or SRAM clock after the system enters the Sleep mode. If it is not necessary for the CPU to access the Flash memory and SRAM in the Sleep mode, it is recommended to clear the FMCEN and SRAMEN bits in the AHBCCR register to minimize power consumption. To enter the Sleep mode, it is only necessary to execute a WFI or WFE instruction and let the SLEEPDEEP bit to be

0. The system will exit from the Sleep mode via any interrupt or event trigger. The accompanying table provides more information about the power saving modes.

Table 19. Enter/Exit Power Saving Modes

Mode CPU

Instruction

Mode Entry

CPU

SLEEPDEEP LDOOFF ULDOON

Mode Exit

Sleep

Deep-Sleep1

Deep-Sleep2

Power-Down

WFI or WFE

(Takes effect)

0

1

1

1

X

0

X

1

X

0

1

0

WFI: Any interrupt

WFE:

Any wakeup event (1) or

Any interrupt (NVIC on) or

Any interrupt with SEVONPEND = 1

(NVIC off)

Any EXTI in event mode or

RTC wakeup or

CMP wakeup or

LVD wakeup (2)

USB resume

or

WAKEUP pin rising edge or

Any EXTI in event mode or

RTC wakeup or

CMP wakeup or

LVD wakeup (2) or

WAKEUP pin rising edge

RTC wakeup or

LVD wakeup (2) or

WAKEUP pin rising edge or

External reset (nRST)

Notes: 1. Wakeup event means EXTI line trigger event, RTC event, LVD event or WAKEUP pin rising edge.

2. If the system allows the LVD activity to wake it up after the system has entered the power saving mode, the LVDEWEN and LVDEN bits in the LVDCSR register must be set to 1 to make sure that the system can be woken up by an LVD event and then the main LDO can be turned on when the system is woken up from the Deep-Sleep2 mode and Power-Down mode.

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Deep-Sleep Mode

To enter the Deep-Sleep mode, configure the registers as shown in the preceding table and execute the WFI or WFE instruction. In the Deep-Sleep mode, all clocks including the PLL and high speed oscillators, known as HSI and HSE, will be stopped. In addition, the Deep-Sleep1 and Deep-

Sleep2 mode will turns off the main LDO and uses an ultra-low power LDO, ULDO, to keep the

1.5 V power. Once the PWRCU receives a wakeup event or an interrupt as shown in the preceding

Mode-Exiting table, the main LDO will then operate in normal mode and the high speed oscillators will be enabled. Finally, the CPU will return to the Run mode to handle the wakeup interrupt if required. A Low Voltage Detection also can be regarded as a wakeup event if the corresponding wakeup control bit LVDEWEN in the LVDCSR register is enabled. The last wakeup event is a transition from low to high on the external WAKEUP pin sent to the PWRCU to resume from the

Deep-Sleep mode. During the Deep-Sleep mode, retaining the register and memory contents will shorten the wakeup latency.

Power-Down Mode

The Power-Down mode is derived from the Deep-Sleep mode of the CPU together with the additional control bits LDOOFF and ULDOON. To enter the Power-Down mode, users can configure the registers shown in the preceding Mode-Entering table and execute the WFI or WFE instruction. An RTC wakeup trigger event, an LVD wakeup, a low to high transition on the external

WAKEUP pin or an external reset (nRST) signal will force the MCU out of the Power-Down mode.

In the Power-Down mode, the 1.5 V power supply will be turned off. The remaining active power supplies are the 3.3 V power (V

DD

/ V

DDA

).

After a system reset, the PORSTF bit in the RSTCU GRSR register, the PDF and PORF bits in the

PWRSR register should be checked by software to confirm if the device is being resumed from the

Power-Down mode by a power-on reset or other reset events (nRST, WDT, …). If the device has entered the Power-Down mode under the correct firmware procedure, the PDF bit will be set. The system information could be saved in the V

DD

power domain registers and be retrieved when the

1.5 V power domain is powered on again. More information about the PDF and PORF bits in the

PWRSR register and PORSTF bit in the RSTCU GRSR register is shown in the following table.

Table 20. Power Status after System Reset

PORF PDF PORSTF

1

0

0

1

0

0

1

1

1

1

1 x

Description

Power-up for the first time after the V

DD

Power-on reset when V

DD software reset command on the V

DD

power domain is reset:

is applied for the first time or executing

domain.

Restart from unexpected loss of the 1.5 V power or other reset (nRST,

WDT, …)

Restart from the Power-Down mode.

Reserved

WAKEUP Pin Wakeup

The software can set the WUPEN bit in register PWRCR to 1 to enable the WAKEUP pin function before entering the power saving mode, waiting for a wakeup trigger signal occurrence on the

WAKEUP pin to wake up the system from the power saving mode. The external WAKEUP pin interrupt shares the same exception number with the EXTI event wakeup interrupt. The software can set the EXTI Event Wakeup Interrupt Enable bit (EVWUPIEN) to 1 to assert the WKUP interrupt in the NVIC unit when both the WUPEN and WUPF bits are set to 1.

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Although the WUPEN bit is located in the V

DD

domain, it also can be reset by the nRST reset pin.

After the reset there will be a delay before the WUPEN bit is active. This bit will not be active until the system reset is finished and the V

DD

domain ISO signal is disabled. This means that the bit cannot be immediately set by software after a system reset is finished and the V

DD

domain ISO signal is disabled. The delay time requires at least three 32 kHz clock periods after the WUPEN bit reset has been finished.

Register Map

The following table shows the PWRCU registers and reset values. Note all the registers in this unit are located in the V

DD power domain.

Table 21. PWRCU Register Map

Register Offset

PWRSR

Description

0x100 Power Control Status Register

Reset Value

0x0000_0001

PWRCR

LVDCSR

0x104 Power Control Register

PWRTEST 0x108 V

DD

Power Domain Test Register

0x0000_0000

0x0000_0027

0x110 Low Voltage / Brown-Out Detect Control and Status Register 0x0000_0000

PWRLDOSR 0x11C Power Control LDO Status Register 0x30XX_XXXX


Power Control Status Register – PWRSR

This register indicates the power control status.

Offset: 0x100

Reset value: 0x0000_0001 (Reset only by V

DD

domain power-on reset)

31 30 29 26 25 24

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

12

Reserved

27

Reserved

19

Reserved

11

4

Reserved

3

18

10

2

17 16

9 8

WUPF

1

PDF

RC 0

0

PORF

RC 0 RC 1

Bits

[8]

Field

WUPF

Descriptions

External WAKEUP Pin Flag

0: The WAKEUP pin is not asserted

1: The WAKEUP pin is asserted

This bit is set by hardware when the WAKEUP pin is asserted and is cleared by software read. Software should read this bit to clear it after a system wakeup from the power saving mode.

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Bits

[1]

[0]

Field

PDF

PORF

Descriptions

Power-Down Flag

0: Wakeup from abnormal V

DD15

shutdown (loss of V

1: Wakeup from Power-Down mode (loss of V

DD15

is unexpected)

DD15

is under expectation)

This bit is set by hardware when the system has successfully entered the Power-Down mode under the correct firmware procedure. This bit is cleared by software read.

Power-On Reset Flag

0: V

DD

Power Domain reset does not occur

1: V

DD

Power Domain reset occurs

This bit is set by hardware when the V

DD

power-on reset occurs, either a hardware power-on reset or software reset. The bit is cleared by software read. This bit must be cleared after the system is first powered on, otherwise it will be impossible to detect when a V

DD

Power Domain reset has been triggered. When this bit is read as 1, a read software loop must be implemented until the bit returns again to 0.

This software loop is necessary to confirm that the V access.

DD

Power Domain is ready for

Power Control Register – PWRCR

This register provides power control bits for the different kinds of power saving modes.

Offset: 0x104


DD


30 29 31

Type/Reset

23

Type/Reset

15

ULDOSTS

Type/Reset RO 0

7

ULDOON

Type/Reset RW 0

22

14

6

21

13

5

Reserved

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

12

4

Reserved

11 10 9 8

WUPEN

RW 0

3 2 1 0

LDOOFF LDOLCM Reserved PWRST

RW 0 RW 0 WO 0

Bits

[15]


ULDOSTS Ultra-low power regulator Status

If the ULDOON bit in this register has been set to 1, this bit will be set high after the

MCU is waken up from the Deep-Sleep2 mode.

This bit is cleared to 0 if the ULDOON bit has been cleared to 0 or if a POR/PDR reset has occurred.

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Bits

[8]

[7]

[3]

[2]

[0]

Field

WUPEN

ULDOON

LDOOFF

LDOLCM

PWRST

Descriptions

External WAKEUP Pin Enable

0: Disable WAKEUP pin function

1: Enable WAKEUP pin function

The software can set the WUPEN bit as 1 to enable the WAKEUP pin function before entering the power saving mode. When WUPEN = 1, a rising edge on the

WAKEUP pin wakes up the system from the power saving mode. As the WAKEUP pin is active high, this pin should be configured to an input and pull-down state.

Ultra-low power regulator Control

0: ULDO is OFF

1: ULDO is ON

An ultra-low power regulator ULDO is implemented to provide an alternative voltage source for the 1.5 V power domain when the CPU enters the Deep-Sleep mode

(SLEEPDEEP = 1). The control bit ULDOON is set by software and cleared by software or V

DD

power domain reset. If the ULDOON bit is set to 1, the main LDO will automatically be turned off when the CPU enters the Deep-Sleep mode.

Main regulator Operating Mode Control

0: The LDO operates in a low current mode when CPU enters the Deep-Sleep mode (SLEEPDEEP = 1). That means MCU V supplied by the ultra-low power regulator ULDO.

DD15

power is available and

1: The LDO is turned off when the CPU enters the Deep-Sleep mode

(SLEEPDEEP = 1). That means MCU V

DD15

power is not available and enters the Power Down mode.

Note: This bit is only available when the ULDOON bit is cleared to 0.

LDO Low Current Mode

0: The V

DD15

power domain is supplied by main regulator LDO in normal current mode.

1: The V

DD15

power domain is supplied by ultra-low power regulator ULDO in low current mode.

Note: This bit is only available when MCU is in the Run mode. The ULDO output current capability will be limited at 5 mA below and lower static current when the LDOLCM bit is set. It is suitable for MCU which is operated at lower speed system clock to get a lower current consumption. This bit will be cleared to 0 when the MCU enters the Power Down mode or a V occurs.

DD

power domain reset

V

DD

Power Domain Software Reset

0: No action

1: V

DD

Power Domain Software Reset is activated

When this bit is set high, it will reset all RTC and PWRCU related registers.

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V

DD

Power Domain Test Register – PWRTEST

This register specifies a read-only value for the software to recognize whether V

DD access.

Power Domain is ready for

Offset: 0x108


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

Reserved

10 9 8

Type/Reset

7 6 5 4 3

PWRTEST

2 1 0


Bits

[7:0]


PWRTEST V

DD

Power Domain Test Bits

A constant 0x27 will be read when the V

DD

Power Domain is ready for CPU access.

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Cortex ® -M0+ MCU

Low Voltage / Brown-Out Detect Control and Status Register – LVDCSR

This register specifies flags, enable bits and option bits for low voltage detector.

Offset: 0x110


DD


31 30 29 28 27

Reserved

26 25 24

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23 22 21 20

Reserved LVDS [2] LVDEWEN LVDIWEN

19

LVDF

18

LVDS [1:0]

17 16

LVDEN

RW 0 RW 0 RW 0 RO 0 RW 0 RW 0 RW 0

15 14 13 12 11

Reserved

10 9 8

7 6 5

Reserved

4 3

BODF

RO 0

2 1 0

Reserved BODRIS BODEN

RW 0 RW 0

Bits

[21]

[20]

[19]

[22],

[18:17]


LVDEWEN LVD Event Wakeup Enable

0: LVD event wakeup is disabled

1: LVD event wakeup is enabled

Setting this bit to 1 will enable the LVD event wakeup function to wake up the system when an LVD condition occurs which results in the LVDF bit being asserted. If the system requires to be woken up from the Deep-Sleep or Power-Down mode by an

LVD condition, this bit must be set to 1.

LVDIWEN LVD Interrupt Wakeup Enable

0: LVD interrupt wakeup is disabled

1: LVD interrupt wakeup is enabled

Setting this bit to 1 will enable the LVD interrupt function. When an LVD condition occurs and the LVDIWEN bit is set to 1, an LVD interrupt will be generated and sent to the CPU NVIC unit.

LVDF Low Voltage Detect Status Flag

0: V

DD

is higher than the specific voltage level

1: V

DD

is equal to or lower than the specific voltage level

When the LVD condition occurs, the LVDF flag will be asserted. When the LVDF flag is asserted, an LVD interrupt will be generated for CPU if the LVDIWEN bit is set to

1. However, if the LVDEWEN bit is set to 1 and the LVDIWEN bit is cleared to 0, only an LVD event will be generated rather than an LVD interrupt when the LVDF flag is asserted.

LVDS [2:0] Low Voltage Detect Level Selection

For more details concerning the LVD programmable threshold voltage, refer to the electrical characteristics of the corresponding datasheet.

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Cortex ® -M0+ MCU

[3]

[1]

[0]

Bits

[16]

Field

LVDEN

BODF

BODRIS

BODEN

Descriptions

Low Voltage Detect Enable

0: Disable Low Voltage Detect

1: Enable Low Voltage Detect

Setting this bit to 1 will generate an LVD event when the V

DD

power is equal to or lower than the voltage set by the LVDS bits. Therefore when the LVD function is enabled before the system is into the Deep-Sleep2 (ULDO is turned on and main

LDO is powered down) or Power-Down mode (ULDO and main LDO are powered down), the LVDEWEN bit has to be enabled to avoid that the LDO does not activate in the meantime when the CPU is woken up by the low voltage detection activity.

Brown-Out Detect Flag

0: V

1: V

DD

> V

DD

≤ V

BOD

BOD

BOD Reset or Interrupt Selection

0: Reset the whole chip

1: Generate Interrupt

Brown-Out Detector Enable

0: Disable Brown-Out Detector

1: Enable Brown-Out Detector

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HT32F5828

Cortex ® -M0+ MCU

Power Control LDO Status Register – PWRLDOSR

This register specifies the LDO and the ULDO progress status.

Offset: 0x11C

Reset value: 0x30XX_XXXX

31

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

Reserved

22

29 28

LDOPST

RO 1 RO 1

21 20

27

19

Reserved

26

Reserved

18

25 24

ULDOPST

RO 0 RO 0

17 16

14 13 12 10 9 8

6 5 4

11

Reserved

3

Reserved

2 1 0

Type/Reset

Bits

[29:28]

[25:24]

Field

LDOPST

Descriptions

Main regulator Progress Status

00: LDO off

01: LDO on in progress

10: LDO off in progress

11: LDO on

ULDOPST Ultra-low power regulator Progress Status

00: ULDO off

01: ULDO on in progress

10: ULDO off in progress

11: ULDO on

Rev. 1.00 127 of 637 December 28, 2020

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8

External Interrupt/Event Controller (EXTI)

Introduction

The External Interrupt/Event Controller, EXTI, comprises 16 edge detectors which can generate wakeup events or interrupt requests independently. In the interrupt mode there are five trigger types which can be selected as the external interrupt trigger type, low level, high level, negative edge, positive edge and both edges, selectable using the SRCnTYPE field in the EXTICFGRn (n =

0 ~ 15) register. In the wakeup event mode, the wakeup event polarity can be configured by setting the EXTInWPOL (n = 0 ~ 15) field in the EXTIWAKUPPOLR register. If the EVWUPIEN bit in the EXTIWAKUPCR Register is set, the EVWUP interrupt can be generated when the associated wakeup event occurs and the corresponding EXTI wakeup enable bit is set. Each EXTI line can also be masked independently.

High or Low level

Rising or Falling or Both Edges

Edge/Level

Control

(SRCnTYPE[2:0])

EXTI_PCLK

Debounce

EXTI 0

∫

EXTI 15

16

16 16

DBnCNT[15:0] DBnEN

16 Edge/Level

Detection

Software

Activate

(EXTInSC)

16

16

Interrupt Enable bits

& Interrupt Flags

16

EXTI Interrupt

Control &

Status

16 External I/O Interrupt

(To NVIC control unit)

Deglitch

16 Polarity

Detection

16

Event Enable bits

& Event Flags

EXTI Event

Control &

Status

16

External I/O Event

(To NVIC control unit)

(To clock control unit)

Polarity

Control

(EXTInWPOL)

High or Low level

Figure 21. EXTI Block Diagram

Features

▆

▆

▆

▆

Up to 16 EXTI lines with configurable trigger source and type

● All GPIO pins can be selected as EXTI trigger source

● Source trigger type includes high level, low level, negative edge, positive edge or both edge

Individual interrupt enable, wakeup enable and status bits for each EXTI line

Software interrupt trigger mode for each EXTI line

Integrated deglitch filter for short pulse blocking

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Cortex ® -M0+ MCU


Wakeup Event Management

In order to wake up the system from the power saving mode, the EXTI controller provides a function which can monitor external events and send them to the CPU core and the Clock Control

Unit, CKCU. These external events include EXTI events, Low Voltage Detection, WAKEUP input pin, Comparator, USB and RTC wakeup functions. By configuring the wakeup event enable bit in the corresponding peripheral, the wakeup signal will be sent to the CPU core and the CKCU via the EXTI controller when the corresponding wakeup event occurs. Additionally, the software can enable the event wakeup interrupt function by setting the EVWUPIEN bit in the EXTIWAKUPCR register and the EXTI controller will then assert an interrupt when the wakeup event occurs.

EXTIn

WAKEUP

16

1

16

16

0 16

High/Low level detector

16 16

EXTInWPOL

EXTInWEN

CMP

CMP_WAKEUP

RTC

RTC_WAKEUP

PWRCU

LVD_WAKEUP

WUPF

USB

USB_WAKEUP

SLEEPING

(NVIC)

16

EXTInWFL

Figure 22. EXTI Wakeup Event Management

16

16

16

EVWUPIEN

EXTI Wakeup Event Management

WKUP interrupt

(NVIC)

HSI/HSE/PLL wakeup (CKCU)

Set event signal to NVIC

To wake up MCU

External Interrupt/Event Line Mapping

All GPIO pins can be selected as EXTI trigger sources by configuring the EXTInPIN[3:0] field in the AFIO ESSRn (n = 0 ~ 1) register to trigger an interrupt or event. Refer to the AFIO section for more details.

Interrupt and Debounce

The application software can set the DBnEN bit in the EXTIn Interrupt Configuration Register

EXTICFGRn (n = 0 ~ 15) to enable the corresponding pin debounce function and configure the

DBnCNT field in the EXTICFGRn register so as to select an appropriate debounce time for specific applications. The interrupt signal will however be delayed due to the debounce function. When the device is woken up from the power saving mode by an external interrupt, an interrupt request will be generated by the EXTI wakeup flag. After the device has been woken up and the clock has

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Cortex ® -M0+ MCU recovered, the EXTI wakeup flag that was triggered by the EXTI line must be read and then cleared by application software. The accompanying diagram shows the relationship between the EXTI input signal and the EXTI interrupt/event request signal.

Low pulse is shorter than debounce time

EXTIn pin input

EXTIn interrupt request

Figure 23. EXTI Interrupt Debounce Function

Debounce time delay

Register Map

The following table shows the EXTI registers and reset values.

Table 22. EXTI Register Map

Register

EXTICFGR0

EXTICFGR1

EXTICFGR2

Offset

0x000

0x004

0x008

EXTICFGR3

EXTICFGR4

EXTICFGR5

EXTICFGR6

EXTICFGR7

EXTICFGR8

EXTICFGR9

EXTICFGR10

EXTICFGR11

EXTICFGR12

EXTICFGR13

EXTICFGR14

EXTICFGR15

EXTICR

EXTIEDGEFLGR

EXTIEDGESR

0x040

0x044

0x048

EXTISSCR

EXTIWAKUPCR

0x04C

0x050

EXTIWAKUPPOLR 0x054

EXTIWAKUPFLG 0x058

0x00C

0x010

0x014

0x018

0x01C

0x020

0x024

0x028

0x02C

0x030

0x034

0x038

0x03C

Description

EXTI Interrupt 0 Configuration Register



Reset Value

0x0000_0000

0x0000_0000

0x0000_0000














0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

EXTI Interrupt Control Register

EXTI Interrupt Edge Flag Register

EXTI Interrupt Edge Status Register

0x0000_0000

0x0000_0000

0x0000_0000

EXTI Interrupt Software Set Command Register 0x0000_0000

EXTI Interrupt Wakeup Control Register 0x0000_0000

EXTI Interrupt Wakeup Polarity Register

EXTI Interrupt Wakeup Flag Register

0x0000_0000

0x0000_0000

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Cortex ® -M0+ MCU


EXTI Interrupt n Configuration Register – EXTICFGRn, n = 0 ~ 15

This register is used to specify the debounce function and select the trigger type.

Offset: 0x000 (0) ~ 0x03C (15)


31

DBnEN

30 29

SRCnTYPE

28


23 22 21 20

27 26 25

Reserved

24

19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

DBnCNT

10 9 8


7 6 5 4 3 2 1 0

DBnCNT


Bits

[31]

[30:28]

[15:0]

Field

DBnEN

Descriptions

EXTIn Debounce Circuit Enable Bit (n = 0 ~ 15)

0: Debounce circuit is disabled

1: Debounce circuit is enabled

SRCnTYPE EXTIn Interrupt Source Trigger Type (n = 0 ~ 15)

0

0

1

SRCnTYPE [2:0]

0 0 0

Interrupt Source Type

Low-level Sensitive

0 0 1 High-level Sensitive

1

1

X

0

1

X

Negative-edge Triggered

Positive-edge Triggered

Both-edge Triggered

DBnCNT EXTIn Debounce Counter (n = 0 ~ 15)

The debounce time is calculated with DBnCNT × APB clock (EXTI_PCLK) period and should be long enough to take effect on the input signal.

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Cortex ® -M0+ MCU

EXTI Interrupt Control Register – EXTICR

This register is used to control the EXTI interrupt.

Offset: 0x040


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11 10 9 8

EXTI15EN EXTI14EN EXTI13EN EXTI12EN EXTI11EN EXTI10EN EXTI9EN EXTI8EN


7 6 5 4 3 2 1 0

EXTI7EN EXTI6EN EXTI5EN EXTI4EN EXTI3EN EXTI2EN EXTI1EN EXTI0EN


Bits

[15:0]

Field

EXTInEN

Descriptions

EXTIn Interrupt Enable Bit (n = 0 ~ 15)

0: EXTI line n interrupt is disabled

1: EXTI line n interrupt is enabled

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Cortex ® -M0+ MCU

EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR

This register is used to indicate if an EXTI edge has been detected.

Offset: 0x044


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11 10 9 8

EXTI15EDF EXTI14EDF EXTI13EDF EXTI12EDF EXTI11EDF EXTI10EDF EXTI9EDF EXTI8EDF

Type/Reset WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0

7 6 5 4 3 2 1 0

EXTI7EDF EXTI6EDF EXTI5EDF EXTI4EDF EXTI3EDF EXTI2EDF EXTI1EDF EXTI0EDF


Bits

[15:0]


EXTInEDF EXTIn Edge Detection Flag (n = 0 ~ 15)

0: No edge is detected

1: Positive or negative edge is detected

This bit is set by the hardware circuitry when a positive or negative edge is detected on the corresponding EXTI line. Software should write 1 to clear it.

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Cortex ® -M0+ MCU

EXTI Interrupt Edge Status Register – EXTIEDGESR

This register indicates the polarity of a detected EXTI edge.

Offset: 0x048


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11 10 9 8

EXTI15EDS EXTI14EDS EXTI13EDS EXTI12EDS EXTI11EDS EXTI10EDS EXTI9EDS EXTI8EDS


7 6 5 4 3 2 1 0

EXTI7EDS EXTI6EDS EXTI5EDS EXTI4EDS EXTI3EDS EXTI2EDS EXTI1EDS EXTI0EDS


Bits

[15:0]


EXTInEDS EXTIn Edge Detection Status (n = 0 ~ 15)

0: Negative edge is detected

1: Positive edge is detected

Software should write 1 to clear it.

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Cortex ® -M0+ MCU

EXTI Interrupt Software Set Command Register – EXTISSCR

This register is used to activate the EXTI interrupt.

Offset: 0x04C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11 10 9 8

EXTI15SC EXTI14SC EXTI13SC EXTI12SC EXTI11SC EXTI10SC EXTI9SC EXTI8SC


7 6 5 4 3 2 1 0

EXTI7SC EXTI6SC EXTI5SC EXTI4SC EXTI3SC EXTI2SC EXTI1SC EXTI0SC


Bits

[15:0]

Field

EXTInSC

Descriptions

EXTIn Software Set Command (n = 0 ~ 15)

0: Deactivates the corresponding EXTI interrupt

1: Activates the corresponding EXTI interrupt

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Cortex ® -M0+ MCU

EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR

This register is used to control the EXTI interrupt and wakeup function.

Offset: 0x050


31

EVWUPIEN

Type/Reset RW 0

23

30 29 28 27

Reserved

26 25 24

22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11 10 9 8

EXTI15WEN EXTI14WEN EXTI13WEN EXTI12WEN EXTI11WEN EXTI10WEN EXTI9WEN EXTI8WEN


7 6 5 4 3 2 1 0

EXTI7WEN EXTI6WEN EXTI5WEN EXTI4WEN EXTI3WEN EXTI2WEN EXTI1WEN EXTI0WEN


Bits

[31]

[15:0]


EVWUPIEN EXTI Event Wakeup Interrupt Enable Bit

0: Disable EVWUP interrupt

1: Enable EVWUP interrupt

EXTInWEN EXTIn Wakeup Enable Bit (n = 0 ~ 15)

0: Power saving mode wakeup is disabled

1: Power saving mode wakeup is enabled

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Cortex ® -M0+ MCU

EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR

This register is used to select the EXTI line interrupt wakeup polarity.

Offset: 0x054


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11 10 9 8

EXTI15WPOL EXTI14WPOL EXTI13WPOL EXTI12WPOL EXTI11WPOL EXTI10WPOL EXTI9WPOL EXTI8WPOL


7 6 5 4 3 2 1 0

EXTI7WPOL EXTI6WPOL EXTI5WPOL EXTI4WPOL EXTI3WPOL EXTI2WPOL EXTI1WPOL EXTI0WPOL


Bits

[15:0]


EXTInWPOL EXTIn Wakeup Polarity (n = 0 ~ 15)

0: EXTIn wakeup is high level active

1: EXTIn wakeup is low level active

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Cortex ® -M0+ MCU

EXTI Interrupt Wakeup Flag Register – EXTIWAKUPFLG

This register is the EXTI interrupt wakeup flag register.

Offset: 0x058


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11 10 9 8

EXTI15WFL EXTI14WFL EXTI13WFL EXTI12WFL EXTI11WFL EXTI10WFL EXTI9WFL EXIT8WFL


7 6 5 4 3 2 1 0

EXTI7WFL EXTI6WFL EXTI5WFL EXTI4WFL EXTI3WFL EXTI2WFL EXTI1WFL EXTI0WFL


Bits

[15:0]


EXTInWFL EXTIn Wakeup Flag (n = 0 ~ 15)

0: No wakeup occurs

1: System is woken up by EXTIn

Software should write 1 to clear it.

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9

General Purpose I/O (GPIO)

Introduction

There are up to 67 General Purpose I/O ports, GPIO, named PA0 ~ PA15, PB0 ~ PB8, PB10 ~ PB15,

PC0 ~ PC15, PD0 ~ PD15 and PE0 ~ PE3 for the device to implement the logic input/output functions.

Each of the GPIO ports has related control and configuration registers to satisfy the requirement of specific applications. The actual available General Purpose I/O port numbers are dependent on the device specification and package type. Refer to the device datasheet for detailed information.

The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. The GPIO pins can be used as alternative functional pins by configuring the corresponding registers regardless of the AF input or output pins.

The external interrupts on the GPIO pins of the device have related control and configuration registers in the External Interrupt Control Unit (EXTI).

To AFIO MUX

Bus Interface

C

IOPAD

IEN

AFIO

PxDOUTn

PxRSTn

PxSETn

PxDVn

PxODn

PxPDn

PxPUn

PxDINn

PxINENn

PxDIRn

To IOPAD DS

To IOPAD PDN

To IOPAD PUN

To IOPAD IEN

To IOPAD OEN

OEN

AFIO

Figure 24. GPIO Block Diagram

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Cortex ® -M0+ MCU

Features

▆

▆

▆

▆

▆

▆

▆

▆

▆

▆

Input/output direction control

Schmitt Trigger Input function enable control

Input weak pull-up/pull-down control

Output push-pull/open-drain enable control

Output set/reset control

Output drive current selection

External interrupt with programmable trigger edge – using EXTI configuration registers

Analog input/output configurations – using AFIO configuration registers

Alternate function input/output configurations – using AFIO configuration registers

Port configuration lock


Default GPIO Pin Configuration

During or just after the reset period, the alternative functions are all inactive and the GPIO ports are configured into the input disable floating mode, i.e. input disabled without pull-up/pull-down resistors. Only the boot and Serial-Wired Debug pins which are pin-shared with the I/O pins are active after a device reset.

▆

▆

▆

PA9_BOOT: Input enable with internal pull-up

SWCLK: Input enable with internal pull-up

SWDIO: Input enable with internal pull-up

General Purpose I/O – GPIO

The GPIO pins can be configured as inputs or outputs via the data direction control registers

PxDIRCR (where x = A ~ E). When the GPIO pins are configured as input pins, the data on the external pads can be read if the enable bits in the input enable function register PxINER are set.

The GPIO pull-up/pull-down registers PxPUR/PxPDR can be configured to fit specific applications.

When the pull-up and pull-down functions are both enabled, the pull-up function has the higher priority while the pull-down function will be blocked until the pull-up function is released.

The GPIO pins can be configured as output pins where the output data is latched into the data register PxDOUTR. The output type can be setup to be either push-pull or open-drain by the opendrain selection register PxODR. Only one or several specific bits of the output data will be set or reset by configuring the port output set/reset control register PxSRR or the port output reset register PxRR without affecting the unselected bits. As the port output set and reset functions are both enabled, the port output set function has the higher priority and the port output reset function will be blocked. The output driving current of the GPIO pins can be selected by configuring the drive current selection register PxDRVR.

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PxCFGn

PUN

Input

DMUX

PDN

IEN

Output

IP

OEN

IP

MUX

AFIO

Control

IOPAD

OEN DS

ADC

AFIO

ADEN

PxDOUTn

PxDINn

PxRSTn

PxSETn

PxINENn

PxDIRn

PxDVn

PxODn

PxPDn

PxPUn

GPIO

Figure 25. AFIO/GPIO Control Signal

PxDINn/PxDOUTn (x = A ~ E): Data Input/Data Output PxRSTn/PxSETn (x = A ~ E): Reset/Set

PxDIRn (x = A ~ E): Direction PxINENn (x = A ~ E): Input Enable

PxDVn (x = A ~ E): Output Drive PxODn (x = A ~ E): Open-Drain

PxPDn/PxPUn (x = A ~ E): Pull-Down/Up PxCFGn (x = A ~ E): AFIO Configuration

Table 23. AFIO, GPIO and I/O Pad Control Signal True Table

Type

GPIO Input (Note)

ADEN

1

AFIO

AFIO

OEN

AFIO

1

IEN

1

AFIO

0

GPIO

PxDIRn PxINENn ADEN OEN IEN

1 1

PAD

1 0

GPIO Output (Note)

AFIO Input

AFIO Output

ADC Input

OSC Output

1

0

1

1

0

0

1

1

1

1

1

1

1

0

1

X

0

1

0

0

0 (1 if need)

X

0 (1 if need)

0 (1 if need)

0 (1 if need)

1

0

1

1

0

0

1

0

1

1

1 (0)

0

1 (0)

1 (0)

1 (0)

Note: The signals, IEN and OEN, for I/O pads are derived from the GPIO register bits PxINENn and

PxDIRn respectively when the associated pin is configured in the GPIO input/output mode.

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GPIO Locking Mechanism

The GPIO also offers a lock function to lock the port until a reset event occurs. The PxLOCKR

(x = A ~ E) registers are used to lock the port x and lock control options. The value 0x5FA0 is written into the PxLKEY field in the PxLOCKR registers to freeze the PxDIRCR, PxINER,

PxPUR, PxPDR, PxODR, PxDRVR control and AFIO mode configuration (GPxCFGHR or

GPxCFGLR, where x = A ~ E). If the value in the PxLOCKR register is 0x5FA0_0001, it means that the Port x Lock function is enabled and the Port x pin 0 is frozen.

Register Map

The following table shows the GPIO registers and reset values of the Port A ~ E.

Table 24. GPIO Register Map

Register Offset

GPIO A Base Address = 0x400B_0000

PADIRCR

PAINER

PAPUR

0x000

0x004

0x008

Description

Port A Data Direction Control Register

Port A Input Function Enable Control Register

Port A Pull-Up Selection Register

PAPDR

PAODR

PADRVR

PALOCKR

PADINR

PADOUTR

0x00C

0x010

0x014

0x018

0x01C

0x020

Port A Pull-Down Selection Register

Port A Open-Drain Selection Register

Port A Drive Current Selection Register

Port A Lock Register

Port A Data Input Register

Port A Data Output Register

PASRR

PARR

0x024

0x028

Port A Output Set/Reset Control Register

Port A Output Reset Control Register

GPIO B Base Address = 0x400B_2000

PBDIRCR 0x000 Port B Data Direction Control Register

PBINER

PBPUR

PBPDR

0x004

0x008

0x00C

Port B Input Function Enable Control Register

Port B Pull-Up Selection Register

Port B Pull-Down Selection Register

PBODR

PBDRVR

PBLOCKR

PBDINR

PBDOUTR

PBSRR

0x010

0x014

0x018

0x01C

0x020

0x024

Port B Open-Drain Selection Register

Port B Drive Current Selection Register

Port B Lock Register

Port B Data Input Register

Port B Data Output Register

Port B Output Set/Reset Control Register

PBRR 0x028 Port B Output Reset Control Register

GPIO C Base Address = 0x400B_4000

PCDIRCR 0x000 Port C Data Direction Control Register

PCINER 0x004 Port C Input Function Enable Control Register

PCPUR

PCPDR

PCODR

PCDRVR

PCLOCKR

PCDINR

0x008

0x00C

0x010

0x014

0x018

0x01C

Port C Pull-Up Selection Register

Port C Pull-Down Selection Register

Port C Open-Drain Selection Register

Port C Drive Current Selection Register

Port C Lock Register

Port C Data Input Register

Reset Value

0x0000_0000

0x0000_0200

0x0000_3200

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_3200

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

Rev. 1.00 142 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Register

PCDOUTR

PCSRR

PCRR

Offset

0x020

0x024

0x028

Description

Port C Data Output Register

Port C Output Set/Reset Control Register

Port C Output Reset Control Register

GPIO D Base Address = 0x400B_6000

PDDIRCR 0x000 Port D Data Direction Control Register

PDINER 0x004 Port D Input Function Enable Control Register

PDPUR

PDPDR

PDODR

0x008

0x00C

0x010

Port D Pull-Up Selection Register

Port D Pull-Down Selection Register

Port D Open-Drain Selection Register

PDDRVR

PDLOCKR

PDDINR

PDDOUTR

0x014

0x018

0x01C

0x020

Port D Drive Current Selection Register

Port D Lock Register

Port D Data Input Register

Port D Data Output Register

PDSRR

PDRR

0x024

0x028

Port D Output Set / Reset Control Register

Port D Output Reset Control Register

GPIO E Base Address = 0x400B_8000

PEDIRCR 0x000 Port E Data Direction Control Register

PEINER

PEPUR

0x004

0x008

Port E Input Function Enable Control Register

Port E Pull-Up Selection Register

PEPDR

PEODR

PEDRVR

PELOCKR

PEDINR

PEDOUTR

PESRR

PERR

0x00C

0x010

0x014

0x018

0x01C

0x020

0x024

0x028

Port E Pull-Down Selection Register

Port E Open-Drain Selection Register

Port E Drive Current Selection Register

Port E Lock Register

Port E Data Input Register

Port E Data Output Register

Port E Output Set / Reset Control Register

Port E Output Reset Control Register

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

Rev. 1.00 143 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU


Port A Data Direction Control Register – PADIRCR

This register is used to control the direction of the GPIO Port A pin as input or output.

Offset: 0x000


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PADIR

10 9 8


7 6 5 4 3 2 1 0

PADIR


Bits

[15:0]

Field

PADIRn

Descriptions

GPIO Port A pin n Direction Control Bits (n = 0 ~ 15)

0: Pin n is in input mode

1: Pin n is in output mode

Rev. 1.00 144 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port A Input Function Enable Control Register – PAINER

This register is used to enable or disable the GPIO Port A input function.

Offset: 0x004


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PAINEN

10 9 8


7 6 5 4 3 2 1 0

PAINEN


Bits

[15:0]

Field

PAINENn

Descriptions

GPIO Port A pin n Input Enable Control Bits (n = 0 ~ 15)

0: Pin n input function is disabled

1: Pin n input function is enabled

When the pin n input function is disabled, the input Schmitt trigger will be turned off and the Schmitt trigger output will remain at a zero state.

Rev. 1.00 145 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port A Pull-Up Selection Register – PAPUR

This register is used to enable or disable the GPIO Port A pull-up function.

Offset: 0x008


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PAPU

10 9 8


7 6 5 4 3 2 1 0

PAPU


Bits

[15:0]

Field

PAPUn

Descriptions

GPIO Port A pin n Pull-Up Selection Control Bits (n = 0 ~ 15)

0: Pin n pull-up function is disabled

1: Pin n pull-up function is enabled

Note: When the pull-up and pull-down functions are both enabled, the pull-up function will have the higher priority and therefore the pull-down function will be blocked and disabled.

Rev. 1.00 146 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port A Pull-Down Selection Register – PAPDR

This register is used to enable or disable the GPIO Port A pull-down function.

Offset: 0x00C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PAPD

10 9 8


7 6 5 4 3 2 1 0

PAPD


Bits

[15:0]

Field

PAPDn

Descriptions

GPIO Port A pin n Pull-Down Selection Control Bits (n = 0 ~ 15)

0: Pin n pull-down function is disabled

1: Pin n pull-down function is enabled


Rev. 1.00 147 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port A Open-Drain Selection Register – PAODR

This register is used to enable or disable the GPIO Port A open-drain function.

Offset: 0x010


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PAOD

10 9 8


7 6 5 4 3 2 1 0

PAOD


Bits

[15:0]

Field

PAODn

Descriptions

GPIO Port A pin n Open-Drain Selection Control Bits (n = 0 ~ 15)

0: Pin n Open-Drain output is disabled (The output type is CMOS output)

1: Pin n Open-Drain output is enabled (The output type is open-drain output)

Note: When the open-drain function is enabled, the pin n internal pull-up or pull-down configuration will be invalid.

Rev. 1.00 148 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port A Drive Current Selection Register – PADRVR

This register specifies the GPIO Port A output driving current.

Offset: 0x014


31 30

PADV15

29 28

PADV14

27 26

PADV13

25 24

PADV12


23 22

PADV11

21 20

PADV10

19 18

PADV9

17 16

PADV8


15 14

PADV7

13 12

PADV6

11 10

PADV5

9 8

PADV4


7 6 5 4 3 2 1 0

PADV3 PADV2 PADV1 PADV0


Bits

[31:0]

Field

PADVn[1:0]

Descriptions

GPIO Port A pin n Drive Current Selection Control Bits (n = 0 ~ 15)

00: 4 mA source/sink current




Rev. 1.00 149 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port A Lock Register – PALOCKR

This register specifies the GPIO Port A lock configuration.

Offset: 0x018


31 30 29 28 27

PALKEY

26 25 24


23 22 21 20 19

PALKEY

18 17 16


15 14 13 12 11

PALOCK

10 9 8


7 6 5 4 3 2 1 0

PALOCK


Bits

[31:16]

[15:0]

Field

PALKEY

Descriptions

GPIO Port A Lock Key

0x5FA0: Port A Lock function is enabled

Others: Port A Lock function is disabled

To lock the Port A function, a value of 0x5FA0 should be written into the PALKEY field in this register. To execute a successful write operation on this lock register, the value written into the PALKEY field must be 0x5FA0. If the value written into this field is not equal to 0x5FA0, any write operations on the PALOCKR register will be aborted. The result of a read operation on the PALKEY field returns the GPIO Port

A Lock Status which indicates whether the GPIO Port A is locked or not. If the read value of the PALKEY field is 0, this indicates that the GPIO Port A Lock function is disabled. Otherwise, it indicates that the GPIO Port A Lock function is enabled as the read value is equal to 1.

PALOCKn GPIO Port A Pin n Lock Control Bits (n = 0 ~ 15)

0: Port A Pin n is not locked

1: Port A Pin n is locked

The PALOCKn bits are used to lock the configurations of corresponding GPIO Pins when the correct Lock Key is applied to the PALKEY field. The locked configurations including PADIRn, PAINENn, PAPUn, PAPDn, PAODn and PADVn setting in the related GPIO registers. Additionally, the GPACFGHR or GPACFGLR register which is used to configure the alternative function of the associated GPIO pin will also be locked. Note that the PALOCKR register can only be written once which means that

PALKEY and PALOCKn (lock control bit) should be written together and can not be changed until a system reset or GPIO Port A reset occurs.

Rev. 1.00 150 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port A Data Input Register – PADINR

This register specifies the GPIO Port A input data.

Offset: 0x01C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PADIN

10 9 8


7 6 5 4 3 2 1 0

PADIN


Bits

[15:0]

Field

PADINn

Descriptions

GPIO Port A pin n Data Input Bits (n = 0 ~ 15)

0: The input data of the corresponding pin is 0

1: The input data of the corresponding pin is 1

Port A Output Data Register – PADOUTR

This register specifies the GPIO Port A output data.

Offset: 0x020


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PADOUT

10 9 8


7 6 5 4 3 2 1 0

PADOUT


Bits

[15:0]


PADOUTn GPIO Port A pin n Data Output Bits (n = 0 ~ 15)

0: Data to be output on pin n is 0


Rev. 1.00 151 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port A Output Set/Reset Control Register – PASRR

This register is used to set or reset the corresponding bit of the GPIO Port A output data.

Offset: 0x024


31 30 29 28 27

PARST

26 25 24

Type/Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0

23 22 21 20 19

PARST

18 17 16


15 14 13 12 11

PASET

10 9 8


7 6 5 4 3 2 1 0

PASET


Bits

[31:16]

[15:0]

Field

PARSTn

PASETn

Descriptions

GPIO Port A pin n Output Reset Control Bits (n = 0 ~ 15)

0: No effect on the PADOUTn bit

1: Reset the PADOUTn bit

Note that when the PARSTn bit in this register or (and) the PARSTn bit in the PARR register is enabled, the reset function on the PADOUTn bit will take effect.

GPIO Port A pin n Output Set Control Bits (n = 0 ~ 15)


1: Set the PADOUTn bit

Note that the function enabled by the PASETn bit has the higher priority if both the

PASETn and PARSTn bits are set at the same time.

Rev. 1.00 152 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port A Output Reset Register – PARR

This register is used to reset the corresponding bit of the GPIO Port A output data.

Offset: 0x028


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PARST

10 9 8


7 6 5 4 3 2 1 0

PARST


Bits

[15:0]

Field

PARSTn

Descriptions

GPIO Port A pin n Output Reset Control Bits (n = 0 ~ 15)


1: Reset the PADOUTn bit

Port B Data Direction Control Register – PBDIRCR

This register is used to control the direction of GPIO Port B pin as input or output.

Offset: 0x000


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PBDIR

10


7 6 5 4 3 2

9

Reserved

1

8

PBDIR

RW 0

0

PBDIR


Bits

[15:10]

[8:0]

Field

PBDIRn

Descriptions

GPIO Port B pin n Direction Control Bits (n = 0 ~ 8, 10 ~ 15)



Rev. 1.00 153 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port B Input Function Enable Control Register – PBINER

This register is used to enable or disable the GPIO Port B input function.

Offset: 0x004


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PBINEN

10


7 6 5 4 3 2

9

1

8

Reserved PBINEN

RW 0

0

PBINEN


Bits

[15:10]

[8:0]

Field

PBINENn

Descriptions

GPIO Port B pin n Input Enable Control Bits (n = 0 ~ 8, 10 ~ 15)




Rev. 1.00 154 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port B Pull-Up Selection Register – PBPUR

This register is used to enable or disable the GPIO Port B pull-up function.

Offset: 0x008


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PBPU

10


7 6 5 4 3 2

9

Reserved

1

8

PBPU

RW 0

0

PBPU


Bits

[15:10]

[8:0]

Field

PBPUn

Descriptions

GPIO Port B pin n Pull-Up Selection Control Bits (n = 0 ~ 8, 10 ~ 15)




Rev. 1.00 155 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port B Pull-Down Selection Register – PBPDR

This register is used to enable or disable the GPIO Port B pull-down function.

Offset: 0x00C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PBPD

10


7 6 5 4 3 2

9

Reserved

1

8

PBPD

RW 0

0

PBPD


Bits

[15:10]

[8:0]

Field

PBPDn

Descriptions

GPIO Port B pin n Pull-Down Selection Control Bits (n = 0 ~ 8, 10 ~ 15)




Rev. 1.00 156 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port B Open-Drain Selection Register – PBODR

This register is used to enable or disable the GPIO Port B open-drain function.

Offset: 0x010


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PBOD

10


7 6 5 4 3 2

9

Reserved

1

8

PBOD

RW 0

0

PBOD


Bits

[15:10]

[8:0]

Field

PBODn

Descriptions

GPIO Port B pin n Open-Drain Selection Control Bits (n = 0 ~ 8, 10 ~ 15)




Rev. 1.00 157 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port B Drive Current Selection Register – PBDRVR

This register specifies the GPIO Port B output driving current.

Offset: 0x014


31 30

PBDV15

29 28

PBDV14

27 26

PBDV13

25 24

PBDV12


23 22

PBDV11

21 20

PBDV10


19 18

Reserved

17 16

PBDV8

RW 0 RW 0

15 14

PBDV7

13 12

PBDV6

11 10

PBDV5

9 8

PBDV4


7 6 5 4 3 2 1 0

PBDV3 PBDV2 PBDV1 PBDV0


Bits

[31:20],

[17:0]

Field

PBDVn[1:0]

Descriptions

GPIO Port B pin n Drive Current Selection Control Bits (n = 0 ~ 8, 10 ~ 15)





Rev. 1.00 158 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port B Lock Register – PBLOCKR

This register specifies the GPIO Port B lock configuration.

Offset: 0x018


31 30 29 28 27

PBLKEY

26 25 24


23 22 21 20 19

PBLKEY

18 17 16


15 14 13 12 11

PBLOCK

10


7 6 5 4 3 2

9

1

8

Reserved PBLOCK

RW 0

0

PBLOCK


Bits

[31:16]

[15:10]

[8:0]

Field

PBLKEY

Descriptions

GPIO Port B lock Key

0x5FA0: Port B lock function is enabled

Others: Port B Lock function is disabled

To lock the Port B function, a value of 0x5FA0 should be written into the PBLKEY field in this register. To execute a successful write operation on this lock register, the value written into the PBLKEY field must be 0x5FA0. If the value written into this field is not equal to 0x5FA0, any write operations on the PBLOCKR register will be aborted. The result of a read operation on the PBLKEY field returns the GPIO Port

B Lock Status which indicates whether the GPIO Port B is locked or not. If the read value of the PBLKEY field is 0, this indicates that the GPIO Port B Lock function is disabled. Otherwise, it indicates that the GPIO Port B Lock function is enabled as the read value is equal to 1.

PBLOCKn GPIO Port B pin n Lock Control Bits (n = 0 ~ 8, 10 ~ 15)

0: Port B pin n is not locked

1: Port B pin n is locked

The PBLOCKn bits are used to lock the configurations of corresponding GPIO Pins when the correct Lock Key is applied to the PBLKEY field. The locked configurations including PBDIRn, PBINENn, PBPUn, PBPDn, PBODn and PBDVn setting in the related GPIO registers. Additionally, the GPBCFGHR or GPBCFGLR register which is used to configure the alternative function of the associated GPIO pin will also be locked. Note that the PBLOCKR register can only be written once which means that

PBLKEY and PBLOCKn (lock control bit) should be written together and can not be changed until a system reset or GPIO Port B reset occurs.

Rev. 1.00 159 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port B Data Input Register – PBDINR

This register specifies the GPIO Port B input data.

Offset: 0x01C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PBDIN

10

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

7 6 5 4 3 2

9

Reserved

1

8

PBDIN

RO 0

0

PBDIN


Bits

[15:10]

[8:0]

Field

PBDINn

Descriptions

GPIO Port B pin n Data Input Bits (n = 0 ~ 8, 10 ~ 15)

0: The input data of corresponding pin is 0


Port B Output Data Register – PBDOUTR

This register specifies the GPIO Port B output data.

Offset: 0x020


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PBDOUT

10


7 6 5 4 3 2

9

1

8

Reserved PBDOUT

RW 0

0

PBDOUT


Bits

[15:10]

[8:0]


PBDOUTn GPIO Port B pin n Data Output Bits (n = 0 ~ 8, 10 ~ 15)



Rev. 1.00 160 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port B Output Set/Reset Control Register – PBSRR

This register is used to set or reset the corresponding bit of the GPIO Port B output data.

Offset: 0x024


31 30 29 28 27

PBRST

26

Type/Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0

25 24

Reserved PBRST

WO 0

23 22 21 20 19

PBRST

18 17 16


15 14 13 12 11

PBSET

10


7 6 5 4 3 2

9

1

8

Reserved PBSET

WO 0

0

PBSET


Bits

[31:26]

[24:16]

[15:10]

[8:0]

Field

PBRSTn

PBSETn

Descriptions

GPIO Port B pin n Output Reset Control Bits (n = 0 ~ 8, 10 ~ 15)

0: No effect on the PBDOUTn bit

1: Reset the PBDOUTn bit

Note that when the PBRSTn bit in this register or (and) the PBRSTn bit in the PBRR register is enabled, the reset function on the PBDOUTn bit will take effect.

GPIO Port B pin n Output Set Control Bits (n = 0 ~ 8, 10 ~ 15)


1: Set the PBDOUTn bit

Note that the function enabled by the PBSETn bit has the higher priority if both the

PBSETn and PBRSTn bits are set at the same time.

Rev. 1.00 161 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port B Output Reset Register – PBRR

This register is used to reset the corresponding bit of the GPIO Port B output data.

Offset: 0x028


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PBRST

10


7 6 5 4 3 2

9

1

8

Reserved PBRST

WO 0

0

PBRST


Bits

[15:10]

[8:0]

Field

PBRSTn

Descriptions

GPIO Port B pin n Output Reset Control Bits (n = 0 ~ 8, 10 ~ 15)


1: Reset the PBDOUTn bit

Port C Data Direction Control Register – PCDIRCR

This register is used to control the direction of GPIO Port C pin as input or output.

Offset: 0x000


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PCDIR

10 9 8


7 6 5 4 3 2 1 0

PCDIR


Bits

[15:0]

Field

PCDIRn

Descriptions

GPIO Port C pin n Direction Control Bits (n = 0 ~ 15)



Rev. 1.00 162 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port C Input Function Enable Control Register – PCINER

This register is used to enable or disable the GPIO Port C input function.

Offset: 0x004


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PCINEN

10 9 8


7 6 5 4 3 2 1 0

PCINEN


Bits

[15:0]

Field

PCINENn

Descriptions

GPIO Port C pin n Input Enable Control Bits (n = 0 ~ 15)




Rev. 1.00 163 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port C Pull-Up Selection Register – PCPUR

This register is used to enable or disable the GPIO Port C pull-up function.

Offset: 0x008


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PCPU

10 9 8


7 6 5 4 3 2 1 0

PCPU


Bits

[15:0]

Field

PCPUn

Descriptions

GPIO Port C pin n Pull-Up Selection Control Bits (n = 0 ~ 15)




Rev. 1.00 164 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port C Pull-Down Selection Register – PCPDR

This register is used to enable or disable the GPIO Port C pull-down function.

Offset: 0x00C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PCPD

10 9 8


7 6 5 4 3 2 1 0

PCPD


Bits

[15:0]

Field

PCPDn

Descriptions

GPIO Port C pin n Pull-Down Selection Control Bits (n = 0 ~ 15)




Rev. 1.00 165 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port C Open-Drain Selection Register – PCODR

This register is used to enable or disable the GPIO Port C open-drain function.

Offset: 0x010


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PCOD

10 9 8


7 6 5 4 3 2 1 0

PCOD


Bits

[15:0]

Field

PCODn

Descriptions

GPIO Port C pin n Open-Drain Selection Control Bits (n = 0 ~ 15)




Rev. 1.00 166 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port C Drive Current Selection Register – PCDRVR

This register specifies the GPIO Port C output driving current.

Offset: 0x014


31 30

PCDV15

29 28

PCDV14

27 26

PCDV13

25 24

PCDV12


23 22

PCDV11

21 20

PCDV10

19 18

PCDV9

17 16

PCDV8


15 14

PCDV7

13 12

PCDV6

11 10

PCDV5

9 8

PCDV4


7 6 5 4 3 2 1 0

PCDV3 PCDV2 PCDV1 PCDV0


Bits

[31:0]

Field

PCDVn[1:0]

Descriptions

GPIO Port C pin n Drive Current Selection Control Bits (n = 0 ~ 15)





Rev. 1.00 167 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port C Lock Register – PCLOCKR

This register specifies the GPIO Port C lock configuration.

Offset: 0x018


31 30 29 28 27

PCLKEY

26 25 24


23 22 21 20 19

PCLKEY

18 17 16


15 14 13 12 11

PCLOCK

10 9 8


7 6 5 4 3 2 1 0

PCLOCK


Bits

[31:16]

[15:0]

Field

PCLKEY

Descriptions

GPIO Port C lock Key

0x5FA0: Port C Lock function is enable

Others: Port C Lock function is disable

To lock the Port C function, a value of 0x5FA0 should be written into the PCLKEY field in this register. To execute a successful write operation on this lock register, the value written into the PCLKEY field must be 0x5FA0. If the value written into this field is not equal to 0x5FA0, any write operations on the PCLOCKR register will be aborted. The result of a read operation on the PCLKEY field returns the GPIO Port

C Lock Status which indicates whether the GPIO Port C is locked or not. If the read value of the PCLKEY field is 0, this indicates that the GPIO Port C Lock function is disabled. Otherwise, it indicates that the GPIO Port C Lock function is enabled as the read value is equal to 1.

PCLOCKn GPIO Port C pin n Lock Control Bits (n = 0 ~ 15)

0: Port C pin n is not locked

1: Port C pin n is locked

The PCLOCKn bits are used to lock the configurations of corresponding GPIO Pins when the correct Lock Key is applied to the PCLKEY field. The locked configurations including PCDIRn, PCINENn, PCPUn, PCPDn, PCODn and PCDVn setting in the related GPIO registers. Additionally, the GPCCFGHR or GPCCFGLR register which is used to configure the alternative function of the associated GPIO pin will also be locked. Note that the PCLOCKR register can only be written once which means that

PCLKEY and PCLOCKn (lock control bit) should be written together and can not be changed until a system reset or GPIO Port C reset occurs.

Rev. 1.00 168 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port C Data Input Register – PCDINR

This register specifies the GPIO Port C input data.

Offset: 0x01C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PCDIN

10 9 8


7 6 5 4 3 2 1 0

PCDIN


Bits

[15:0]

Field

PCDINn

Descriptions

GPIO Port C pin n Data Input Bits (n = 0 ~ 15)



Port C Output Data Register – PCDOUTR

This register specifies the GPIO Port C output data.

Offset: 0x020


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PCDOUT

10 9 8


7 6 5 4 3 2 1 0

PCDOUT


Bits

[15:0]


PCDOUTn GPIO Port C pin n Data Output Bits (n = 0 ~ 15)



Rev. 1.00 169 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port C Output Set/Reset Control Register – PCSRR

This register is used to set or reset the corresponding bit of the GPIO Port C output data.

Offset: 0x024


31 30 29 28 27

PCRST

26 25 24


23 22 21 20 19

PCRST

18 17 16


15 14 13 12 11

PCSET

10 9 8


7 6 5 4 3 2 1 0

PCSET


Bits

[31:16]

[15:0]

Field

PCRSTn

PCSETn

Descriptions

GPIO Port C pin n Output Reset Control Bits (n = 0 ~ 15)

0: No effect on the PCDOUTn bit

1: Reset the PCDOUTn bit

Note that when the PCRSTn bit in this register or (and) the PCRSTn bit in the PCRR register is enabled, the reset function on the PCDOUTn bit will take effect.

GPIO Port C pin n Output Set Control Bits (n = 0 ~ 15)


1: Set the PCDOUTn bit

Note that the function enabled by the PCSETn bit has the higher priority if both the

PCSETn and PCRSTn bits are set at the same time.

Rev. 1.00 170 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port C Output Reset Register – PCRR

This register is used to reset the corresponding bit of the GPIO Port C output data.

Offset: 0x028


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PCRST

10 9 8


7 6 5 4 3 2 1 0

PCRST


Bits

[15:0]

Field

PCRSTn

Descriptions

GPIO Port C pin n Output Reset Control Bits (n = 0 ~ 15)


1: Reset the PCDOUTn bit

Rev. 1.00 171 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port D Data Direction Control Register – PDDIRCR

This register is used to control the direction of GPIO Port D pin as input or output.

Offset: 0x000


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PDDIR

10 9 8


7 6 5 4 3 2 1 0

PDDIR


Bits

[15:0]

Field

PDDIRn

Descriptions

GPIO Port D pin n Direction Control Bits (n = 0 ~ 15)



Rev. 1.00 172 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port D Input Function Enable Control Register – PDINER

This register is used to enable or disable the GPIO Port D input function.

Offset: 0x004


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PDINEN

10 9 8


7 6 5 4 3 2 1 0

PDINEN


Bits

[15:0]

Field

PDINENn

Descriptions

GPIO Port D pin n Input Enable Control Bits (n = 0 ~ 15)




Rev. 1.00 173 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port D Pull-Up Selection Register – PDPUR

This register is used to enable or disable the GPIO Port D pull-up function.

Offset: 0x008


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PDPU

10 9 8


7 6 5 4 3 2 1 0

PDPU


Bits

[15:0]

Field

PDPUn

Descriptions

GPIO Port D pin n Pull-Up Selection Control Bits (n = 0 ~ 15)




Rev. 1.00 174 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port D Pull-Down Selection Register – PDPDR

This register is used to enable or disable the GPIO Port D pull-down function.

Offset: 0x00C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PDPD

10 9 8


7 6 5 4 3 2 1 0

PDPD


Bits

[15:0]

Field

PDPDn

Descriptions

GPIO Port D pin n Pull-Down Selection Control Bits (n = 0 ~ 15)




Rev. 1.00 175 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port D Open-Drain Selection Register – PDODR

This register is used to enable or disable the GPIO Port D open-drain function.

Offset: 0x010


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PDOD

10 9 8


7 6 5 4 3 2 1 0

PDOD


Bits

[15:0]

Field

PDODn

Descriptions

GPIO Port D pin n Open-Drain Selection Control Bits (n = 0 ~ 15)




Rev. 1.00 176 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port D Drive Current Selection Register – PDDRVR

This register specifies the GPIO Port D output driving current.

Offset: 0x014


31 30

PDDV15

29 28

PDDV14

27 26

PDDV13

25 24

PDDV12


23 22

PDDV11

21 20

PDDV10

19 18

PDDV9

17 16

PDDV8


15 14

PDDV7

13 12

PDDV6

11 10

PDDV5

9 8

PDDV4


7 6 5 4 3 2 1 0

PDDV3 PDDV2 PDDV1 PDDV0


Bits

[31:0]

Field

PDDVn[1:0]

Descriptions

GPIO Port D pin n Drive Current Selection Control Bits (n = 0 ~ 15)





Rev. 1.00 177 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port D Lock Register – PDLOCKR

This register specifies the GPIO Port D lock configuration.

Offset: 0x018


31 30 29 28 27

PDLKEY

26 25 24


23 22 21 20 19

PDLKEY

18 17 16


15 14 13 12 11

PDLOCK

10 9 8


7 6 5 4 3 2 1 0

PDLOCK


Bits

[31:16]

[15:0]

Field

PDLKEY

Descriptions

GPIO Port D Lock Key

0x5FA0: Port D Lock function is enable

Others: Port D Lock function is disable

To lock the Port D function, a value 0x5FA0 should be written into the PDLKEY field in this register. To execute a successful write operation on this lock register, the value written into the PDLKEY field must be 0x5FA0. If the value written into this field is not equal to 0x5FA0, any write operations on the PDLOCKR register will be aborted. The result of a read operation on the PDLKEY field returns the GPIO Port

D Lock Status which indicates whether the GPIO Port D is locked or not. If the read value of the PDLKEY field is 0, this indicates that the GPIO Port D Lock function is disabled. Otherwise, it indicates that the GPIO Port D Lock function is enabled as the read value is equal to 1.

PDLOCKn GPIO Port D pin n Lock Control Bits (n = 0 ~ 15)

0: Port D pin n is not locked

1: Port D pin n is locked

The PDLOCKn bits are used to lock the configurations of corresponding GPIO Pins when the correct Lock Key is applied to the PDLKEY field. The locked configurations including PDDIRn, PDINENn, PDPUn, PDPDn, PDODn and PDDVn setting in the related GPIO registers. Additionally, the GPDCFGHR or GPDCFGLR field which is used to configure the alternative function of the associated GPIO pin will also be locked. Note that the PDLOCKR can only be written once which means that

PDLKEY and PDLOCKn (lock control bit) should be written together and can not be changed until a system reset or GPIO Port D reset occurs.

Rev. 1.00 178 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port D Data Input Register – PDDINR

This register specifies the GPIO Port D input data.

Offset: 0x01C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PDDIN

10 9 8


7 6 5 4 3 2 1 0

PDDIN


Bits

[15:0]

Field

PDDINn

Descriptions

GPIO Port D pin n Data Input Bits (n = 0 ~ 15)



Rev. 1.00 179 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port D Output Data Register – PDDOUTR

This register specifies the GPIO Port D output data.

Offset: 0x020


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PDDOUT

10 9 8


7 6 5 4 3 2 1 0

PDDOUT


Bits

[15:0]


PDDOUTn GPIO Port D pin n Data Output Bits (n = 0 ~ 15)



Rev. 1.00 180 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port D Output Set/Reset Control Register – PDSRR

This register is used to set or reset the corresponding bit of the GPIO Port D output data.

Offset: 0x024


31 30 29 28 27

PDRST

26 25 24


23 22 21 20 19

PDRST

18 17 16


15 14 13 12 11

PDSET

10 9 8


7 6 5 4 3 2 1 0

PDSET


Bits

[31:16]

[15:0]

Field

PDRSTn

PDSETn

Descriptions

GPIO Port D pin n Output Reset Control Bits (n = 0 ~ 15)

0: No effect on the PDDOUTn bit

1: Reset the PDDOUTn bit

Note that when the PDRSTn bit in this register or (and) the PDRSTn bit in the PDRR register is enabled, the reset function on the PDDOUTn bit will take effect.

GPIO Port D pin n Output Set Control Bits (n = 0 ~ 15)


1: Set the PDDOUTn bit

Note that the function enabled by the PDSETn bit has the higher priority if both the

PDSETn and PDRSTn bits are set at the same time.

Rev. 1.00 181 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port D Output Reset Register – PDRR

This register is used to reset the corresponding bit of the GPIO Port D output data.

Offset: 0x028


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PDRST

10 9 8


7 6 5 4 3 2 1 0

PDRST


Bits

[15:0]

Field

PDRSTn

Descriptions

GPIO Port D pin n Output Reset Bits (n = 0 ~ 15)


1: Reset the PDDOUTn bit

Rev. 1.00 182 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port E Data Direction Control Register – PEDIRCR

This register is used to control the direction of GPIO Port E pin as input or output.

Offset: 0x000


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11

Reserved

10 9 8

3 2 1

PEDIR

0

RW 0 RW 0 RW 0 RW 0

Bits

[3:0]

Field

PEDIRn

Descriptions

GPIO Port E pin n Direction Control Bits (n = 0 ~ 3)



Rev. 1.00 183 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port E Input Function Enable Control Register – PEINER

This register is used to enable or disable the GPIO Port E input function.

Offset: 0x004


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11

Reserved

10 9 8

3 2 1

PEINEN

0

RW 0 RW 0 RW 0 RW 0

Bits

[3:0]

Field

PEINENn

Descriptions

GPIO Port E pin n Input Enable Control Bits (n = 0 ~ 3)




Rev. 1.00 184 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port E Pull-Up Selection Register – PEPUR

This register is used to enable or disable the GPIO Port E pull-up function.

Offset: 0x008


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11

Reserved

10 9 8

3 2 1

PEPU

0

RW 0 RW 0 RW 0 RW 0

Bits

[3:0]

Field

PEPUn

Descriptions

GPIO Port E pin n Pull-Up Selection Control Bits (n = 0 ~ 3)




Rev. 1.00 185 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port E Pull-Down Selection Register – PEPDR

This register is used to enable or disable the GPIO Port E pull-down function.

Offset: 0x00C


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11

Reserved

10 9 8

3 2 1

PEPD

0

RW 0 RW 0 RW 0 RW 0

Bits

[3:0]

Field

PEPDn

Descriptions

GPIO Port E pin n Pull-Down Selection Control Bits (n = 0 ~ 3)




Rev. 1.00 186 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port E Open-Drain Selection Register – PEODR

This register is used to enable or disable the GPIO Port E open-drain function.

Offset: 0x010


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11

Reserved

10 9 8

3 2 1

PEOD

0

RW 0 RW 0 RW 0 RW 0

Bits

[3:0]

Field

PEODn

Descriptions

GPIO Port E pin n Open Drain Selection Control Bits (n = 0 ~ 3)

0: Pin n Open Drain output is disabled (The output type is CMOS output)

1: Pin n Open Drain output is enabled (The output type is open-drain output)


Rev. 1.00 187 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port E Drive Current Selection Register – PEDRVR

This register specifies the GPIO Port E output driving current.

Offset: 0x014


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

Reserved

10 9 8

Type/Reset

7 6

PEDV3

5 4

PEDV2

3 2

PEDV1

1 0

PEDV0


Bits

[7:0]

Field

PEDVn[1:0]

Descriptions

GPIO Port E pin n Drive Current Selection Control Bits (n = 0 ~ 3)





Rev. 1.00 188 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port E Lock Register – PELOCKR

This register specifies the GPIO Port E lock configuration.

Offset: 0x018


31 30 29 28 27

PELKEY

26 25 24


23 22 21 20 19

PELKEY

18 17 16


15 14 13 12 11

Reserved

10 9 8

Type/Reset

Type/Reset

7 6 5

Reserved

4 3 2 1

PELOCK

0

RW 0 RW 0 RW 0 RW 0

Bits

[31:16]

[3:0]


PELKEY GPIO Port E lock Key

0x5FA0: Port E Lock function is enable

Others: Port E Lock function is disable

To lock the Port E function, a value 0x5FA0 should be written into the PELKEY field in this register. To execute a successful write operation on this lock register, the value written into the PELKEY field must be 0x5FA0. If the value written into this field is not equal to 0x5FA0, any write operations on the PELOCKR register will be aborted. The result of a read operation on the PELKEY field returns the GPIO Port

E Lock Status which indicates whether the GPIO Port E is locked or not. If the read value of the PELKEY field is 0, this indicates that the GPIO Port E Lock function is disabled. Otherwise, it indicates that the GPIO Port E Lock function is enabled as the read value is equal to 1.

PELOCKn GPIO Port E pin n Lock Control Bits (n = 0 ~ 3)

0: Port E pin n is not locked

1: Port E pin n is locked

The PELOCKn bits are used to lock the configurations of corresponding GPIO Pins when the correct Lock Key is applied to the PELKEY field. The locked configurations including PEDIRn, PEINENn, PEPUn, PEPDn, PEODn and PEDVn setting in the related GPIO registers. Additionally, the GPECFGHR or GPECFGLR field which is used to configure the alternative function of the associated GPIO pin will also be locked. Note that the PELOCKR can only be written once which means that

PELKEY and PELOCKn (lock control bit) should be written together and can not be changed until a system reset or GPIO Port E reset occurs.

Rev. 1.00 189 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port E Data Input Register – PEDINR

This register specifies the GPIO Port E input data.

Offset: 0x01C


31 30 29 28

Type/Reset

23 22 21 20

Type/Reset

15 14 13 12

Type/Reset

7 6 5

Reserved

4

Type/Reset

27

Reserved

19

Reserved

26

18

25

17

24

16

11

Reserved

10 9 8

3 2 1

PEDIN

0

RO 0 RO 0 RO 0 RO 0

Bits

[3:0]

Field

PEDINn

Descriptions

GPIO Port E pin n Data Input Bits (n = 0 ~ 3)



Rev. 1.00 190 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port E Output Data Register – PEDOUTR

This register specifies the GPIO Port E output data.

Offset: 0x020


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11

Reserved

10 9 8

3 2 1

PEDOUT

0

RW 0 RW 0 RW 0 RW 0

Bits

[3:0]


PEDOUTn GPIO Port E pin n Data Output Bits (n = 0 ~ 3)



Rev. 1.00 191 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port E Output Set/Reset Control Register – PESRR

This register is used to set or reset the corresponding bit of the GPIO Port E output data.

Offset: 0x024


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

Reserved

13

5

Reserved

20

12

4

27

Reserved

26 25 24

19 18 17

PERST

16

WO 0 WO 0 WO 0 WO 0

11

Reserved

10 9 8

3 2 1

PESET

0

WO 0 WO 0 WO 0 WO 0

Bits

[19:16]

[3:0]

Field

PERSTn

PESETn

Descriptions

GPIO Port E pin n Output Reset Control Bits (n = 0 ~ 3)

0: No effect on the PEDOUTn bit

1: Reset the PEDOUTn bit

Note that when the PERSTn bit in this register or (and) the PERSTn bit in the PERR register is enabled, the reset function on the PEDOUTn bit will take effect.

GPIO Port E pin n Output Set Control Bits (n = 0 ~ 3)


1: Set the PEDOUTn bit

Note that the function enabled by the PESETn bit has the higher priority if both the

PESETn and PERSTn bits are set at the same time.

Rev. 1.00 192 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Port E Output Reset Register – PERR

This register is used to reset the corresponding bit of the GPIO Port E output data.

Offset: 0x028


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11

Reserved

10 9 8

3 2 1

PERST

0

WO 0 WO 0 WO 0 WO 0

Bits

[3:0]

Field

PERSTn

Descriptions

GPIO Port E pin n Output Reset Bits (n = 0 ~ 3)


1: Reset the PEDOUTn bit

Rev. 1.00 193 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

10

Alternate Function Input/Output Control

Unit (AFIO)

Introduction

In order to expand the flexibility of the GPIO or the usage of peripheral functions, each I/O pin can be configured to have up to sixteen different functions such as GPIO or IP functions by setting the

GPxCFGLR or GPxCFGHR register where x is the different port name. According to the usage of the IP resource and application requirements, suitable pin-out locations can be selected by using the peripheral I/O remapping mechanism. Additionally, various GPIO pins can be selected to be the EXTI interrupt line by setting the EXTInPIN [3:0] field in the ESSRn register to trigger an interrupt or event. Please refer to the EXTI section for more details.

APB Interface

AFIO Configuration

Registers

AFIO control signal

Lock Signal

Peripheral IP I / O

Alternative Function

Output Selections

AFIO output signal

Alternate function output through GPIO

APB Interface

AFIO Configuration

Registers

AFIO control signal

Lock Signal

Peripheral IPm Input

AFIO Input signal

PxLOCKR

GPIO Module

PxLOCKR

GPIOx

GPIOx

Peripheral IPn Input

Alternate function input through GPIO

Figure 26. AFIO Block Diagram

AFIO Input signal

GPIO Module

Rev. 1.00 194 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Features

▆

▆

▆

▆

APB slave interface for register access

EXTI source selection

Configurable pin function for each GPIO, up to sixteen alternative functions on each pin

AFIO lock mechanism


External Interrupt Pin Selection

The GPIO pins are connected to the 16 EXTI lines as shown in the accompanying figure. For example, the user can set the EXTI0PIN [3:0] field in the ESSR0 register to b0000 to select the

GPIO PA0 pin as EXTI line 0 input. Since not all the pins of the Port A ~ E are available in all package types, refer to the pin assignment section for detailed pin information. The setting of the

EXTInPIN [3:0] field is invalid when the corresponding pin is not available.

PA0

PB0

PC0

PD0

PE0

EXTIx Pin Selection

EXTI0PIN[3:0]

0000

0001

0010

0011

0100

EXTI 0

PA15

PB15

PC15

PD15

PE15

Figure 27. EXTI Channel Input Selection

EXTI15PIN[3:0]

0000

0001

0010

0011

0100

EXTI 15

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Alternate Function

Up to sixteen alternative functions can be chosen for each I/O pad by setting the PxCFGn [3:0] field in the GPxCFGLR or GPxCFGHR (n = 0 ~ 15, x = A ~ E) registers. If the pin is selected as unavailable item which is noted as “N/A” in the “Alternate Function Mapping” table of the device datasheet, this pin will be defined as default alternate function. Refer to the “Alternate Function

Mapping” table in the device datasheet for detailed mapping of the alternate function I/O pins.

In addition to this flexible I/O multiplexing architecture, each peripheral has alternate functions mapped onto different I/O pins to optimize the number of peripherals available in smaller packages.

The following description shows the setting of the PxCFGn [3:0] field.

▆

▆

▆

▆

▆

▆

PxCFGn [3:0] = 0000: The default alternated function (after reset, AF0)

PxCFGn [3:0] = 0001: Alternate Function 1 (AF1)


…….



Table 25. AFIO Selection for Peripheral Map Example

AF0 AF1 AF2 AF3

System

Default GPIO

ADC/

AF4

DAC CMP GPTM

AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

2 C SCI N/A I 2 S N/A N/A SCTM/

Lock Mechanism

The device also offers a lock function to lock the AFIO configuration using the GPIO lock register,

PxLOCKR (x = A ~ E), until a reset event occurs. Refer to the GPIO Locking Mechanism section in the GPIO chapter for more details.

Register Map

The following table shows the AFIO registers and reset values.

Table 26. AFIO Register Map

Register Offset

ESSR0

ESSR1

GPACFGLR

GPACFGHR

0x000

0x004

0x020

0x024

Description

EXTI Source Selection Register 0

EXTI Source Selection Register 1

GPIO Port A Configuration Low Register

GPIO Port A Configuration High Register

GPBCFGLR

GPBCFGHR

GPCCFGLR

GPCCFGHR

GPDCFGLR

GPDCFGHR

GPECFGLR

GPECFGHR

0x028

0x02C

0x030

0x034

0x038

0x03C

0x040

0x044

GPIO Port B Configuration Low Register

GPIO Port B Configuration High Register

GPIO Port C Configuration Low Register

GPIO Port C Configuration High Register

GPIO Port D Configuration Low Register

GPIO Port D Configuration High Register

GPIO Port E Configuration Low Register

GPIO Port E Configuration High Register

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

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EXTI Source Selection Register 0 – ESSR0

This register specifies the I/O selection of EXTI0 ~ EXTI7.

Offset: 0x000


31 30 29

EXTI7PIN

28 27 26 25

EXTI6PIN

24


23 22 21

EXTI5PIN

20 19 18 17

EXTI4PIN

16


15 14 13

EXTI3PIN

12 11 10 9

EXTI2PIN

8


7 6 5 4 3 2 1 0

EXTI1PIN EXTI0PIN


Bits

[31:0]

Field

EXTInPIN[3:0]

Descriptions

EXTIn Pin Selection (n = 0 ~ 7)

0000: PA Bit n is selected as EXTIn source signal

0001: PB Bit n is selected as EXTIn source signal

0010: PC Bit n is selected as EXTIn source signal

0011: PD Bit n is selected as EXTIn source signal

0100: PE Bit n is selected as EXTIn source signal

Others: Reserved

Note: Since not all GPIO pins are available in all products and package types, refer to the pin assignment section for detailed pin information. The

EXTInPIN [3:0] field setting is invalid when the corresponding pin is not available.

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Cortex ® -M0+ MCU

EXTI Source Selection Register 1 – ESSR1

This register specifies the I/O selection of EXTI8 ~ EXTI15.

Offset: 0x004


31 30 29

EXTI15PIN

28 27 26 25

EXTI14PIN

24


23 22 21

EXTI13PIN

20 19 18 17

EXTI12PIN

16


15 14 13

EXTI11PIN

12 11 10 9

EXTI10PIN

8


7 6 5 4 3 2 1 0

EXTI9PIN EXTI8PIN


Bits

[31:0]

Field

EXTInPIN[3:0]

Descriptions

EXTIn Pin Selection (n = 8 ~ 15)

0000: PA Bit n is selected as EXTIn source signal

0001: PB Bit n is selected as EXTIn source signal

0010: PC Bit n is selected as EXTIn source signal

0011: PD Bit n is selected as EXTIn source signal

0100: PE Bit n is selected as EXTIn source signal

Others: Reserved

Note: Since not all GPIO pins are available in all products and package types, refer to the pin assignment section for detailed pin information. The

EXTInPIN [3:0] field setting is invalid when the corresponding pin is not available.

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GPIO Port x Configuration Low Register – GPxCFGLR, x = A, B, C, D, E

This low register specifies the alternate function of GPIO Port x, x = A, B, C, D, E

Offset: 0x020, 0x028, 0x030, 0x038, 0x040


31 30 29

PxCFG7

28 27 26 25

PxCFG6

24


23 22 21

PxCFG5

20 19 18 17

PxCFG4

16


15 14 13

PxCFG3

12 11 10 9

PxCFG2

8


7 6 5 4 3 2 1 0

PxCFG1 PxCFG0


Bits

[31:0]

Field

PxCFGn[3:0]

Descriptions

Alternate function selection for port x pin n (n = 0 ~ 7)

0000: Port x pin n is selected as AF0


.

.



If the pin is selected as unavailable item which is noted as “N/A” in the “Alternate

Function Mapping” table of the device datasheet, this pin will be defined as default alternate function. Refer to the “Alternate Function Mapping” table in the device datasheet for detailed mapping of the alternate function I/O pins.

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GPIO Port x Configuration High Register – GPxCFGHR, x = A, B, C, D, E

This high register specifies the alternate function of GPIO Port x, x = A, B, C, D, E

Offset: 0x024, 0x02C, 0x034, 0x03C, 0x044


31 30 29

PxCFG15

28 27 26 25

PxCFG14

24


23 22 21

PxCFG13

20 19 18 17

PxCFG12

16


15 14 13

PxCFG11

12 11 10 9

PxCFG10

8


7 6 5 4 3 2 1 0

PxCFG9 PxCFG8


Bits

[31:0]

Field

PxCFGn[3:0]

Descriptions

Alternate function selection for port x pin n (n = 8 ~ 15)



.

.



If the pin is selected as unavailable item which is noted as “N/A” in the “Alternate

Function Mapping” table of the device datasheet, this pin will be defined as default alternate function. Refer to the “Alternate Function Mapping” table in the device datasheet for detailed mapping of the alternate function I/O pins.

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11

Nested Vectored Interrupt Controller

(NVIC)

Introduction

In order to reduce the latency and increase the interrupt processing efficiency, a tightly coupled integrated section, which is named as Nested Vectored Interrupt Controller (NVIC) is provided by the Cortex ® -M0+. The NVIC controls the system exceptions and the peripheral interrupts which include functions such as the enable/disable control, priority, clear-pending, active status report, software trigger and vector table remapping. Refer to the Technical Reference Manual of

Cortex ® -M0+ for more details.

Additionally, an integrated simple, 24-bit down-count timer (SysTick) is provided by the

Cortex ® -M0+ to be used as a tick timer for the Real Timer Operation System (RTOS) or as a simple counter. The SysTick counts down from the reloaded value and generates a system interrupt when it reaches zero. The accompanying table lists the system exceptions types and a variety of peripheral interrupts.

Table 27. Exception Types

Interrupt

Number

—

—

Exception

Number

0

1

Exception

Reset

Type

—

-14

-

-2

-1

0

-13

-

-5

1

2

3

7

8

9

4

5

6

10

2

19

23

24

25

20

21

22

26

3

4-10

11

12-13

14

15

16

17

18

NMI

Hard Fault

Reserved

SVCall

Reserved

PendSV

SysTick

LVD

RTC

FMC

WKUP

EXTI0 ~ 1

EXTI2 ~ 3

EXTI4 ~ 15

CMP & DAC

ADC

AES

Reserved

Priority

-3 (Highest) 0x004

-2

—

Vector

Address

0x000

0x008

-1

—

0x00C

—

Configurable (1) 0x02C

—

Configurable (1)

—

0x038


Configurable (2) 0x040

Configurable (2)

Configurable (2)

0x044

0x048


Configurable (2)

Configurable (2)

0x050

0x054


Configurable (2)

Configurable (2)

0x05C

0x060


— 0x068

Description

Initial Stack Point value

Reset

Non-Maskable Interrupt. The clock stuck interrupt signal (clock monitor function provided by Clock Control Unit) is connected to the NMI input

All fault classes

—

SVC instruction System service call

—

System Service Pendable request

SysTick timer decreased to zero

Low voltage detection interrupt

RTC global interrupt

FMC global interrupt

EXTI event wakeup or external WAKEUP pin interrupt (3)

EXTI Line 0 & 1 interrupt

EXTI Line 2 & 3 interrupt

EXTI Line 4 ~ 15 interrupt

Comparator & DAC global interrupt

ADC global interrupt

AES global interrupt

—

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Interrupt

Number

11

12

13

24

25

26

20

21

22

23

17

18

19

14

15

16

27

28

29

30

31

Exception

Number

27

28

29

40

41

42

36

37

38

39

33

34

35

30

31

32

43

44

45

46

47

Exception

Type

LCD

GPTM

SCTM0

Priority

Configurable (2)

Vector

Address

0x06C



I

SCTM1

PWM0

PWM1

BFTM0

BFTM1

2 C0

I 2 C1

SPI0

SPI1

USART

Configurable (2)

Configurable (2)

0x078

0x07C


Configurable (2)

Configurable (2)

0x084

0x088


Configurable

Configurable

(2)

(2)

0x090

0x094



Reserved

UART0

UART1

SCI0~1

I 2 S

USB

PDMA_CH0 ~ 1

—

Configurable (2)

0x0A0

0x0A4

Configurable (2) 0x0A8

Configurable (2)

Configurable (2)

0x0AC

0x0B0

Configurable (2) 0x0B4

Configurable

PDMA_CH2 ~ 5 Configurable

(2)

(2)

0x0B8

0x0BC

Description

LCD global interrupt

GPTM global interrupt

SCTM0 global interrupt

SCTM1 global interrupt

PWM0 global interrupt

PWM1 global interrupt

BFTM0 global interrupt

BFTM1 global interrupt

I 2 C0 global interrupt

I 2 C1 global interrupt

SPI0 global interrupt

SPI1 global interrupt

USART global interrupt

—

UART0 global interrupt

UART1 global interrupt

SCI0 & SCI1 global interrupt

I 2 S global interrupt

USB global interrupt

PDMA channel 0 & 1 global interrupt

PDMA channel 2 ~ 5 global interrupt

Notes: 1 .

The exception priority can be changed using the NVIC System Handler Priority Registers. For more information, refer to the Arm “Cortex ® -M0+ Devices Generic User Guide” document.

2. The interrupt priority can be changed using the NVIC Interrupt Priority Registers. For more information, refer to the Arm “Cortex ® -M0+ Devices Generic User Guide” document.

3. Refer to the PWRCU chapter for the relevant configuration descriptions about the WAKEUP-pin wakeup interrupt.

Features

▆

▆

▆

▆

▆

▆

7 system Cortex ® -M0+ exceptions

Up to 32 Maskable peripheral interrupts

4 programmable priority levels (2 bits for interrupt priority setting)

Non-Maskable interrupt

Low-latency exception and interrupt handling

Vector table remapping capability

● Integrated simple, 24-bit system timer, SysTick

● 24-bit down-counter

● Auto-reloading capability

● Maskable system interrupt generation when counter decreases to 0

● SysTick clock source derived from the HCLK clock divided by 8

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SysTick Calibration

The SysTick Calibration Value Register (SYST_CALIB) is provided by the NVIC to give a reference time base of 1ms for the RTOS tick timer or other purposes. The TENMS field in the SYST_CALIB register has a fixed value of 7500 which is the counter reload value to indicate 1 ms when the clock source comes from the SysTick reference input clock STCLK with a frequency of 7.5 MHz

(60 MHz divide by 8).

Register Map

The following table shows the NVIC registers and reset values.

Table 28. NVIC Register Map

Register Offset

NVIC Base Address = 0xE000_E000

SYST_CSR

SYST_RVR

SYST_CVR

CPUID

ICSR

VTOR

AIRCR

SCR

CCR

SHPR2

SHPR3

SYST_CALIB

NVIC_ISER

NVIC_ICER

NVIC_ISPR

NVIC_ICPR

NVIC_IPR0

NVIC_IPR1

NVIC_IPR2

NVIC_IPR3

NVIC_IPR4

NVIC_IPR5

NVIC_IPR6

NVIC_IPR7

0x010

0x014

0x018

0x01C

0x100

0x180

0x200

0x280

0x400

0x404

0x408

0x40C

0x410

0x414

0x418

0x41C

0xD00

0xD04

0xD08

0xD0C

0xD10

0xD14

0xD1C

0xD20

Description

SysTick Control and Status Register

SysTick Reload Value Register

SysTick Current Value Register

SysTick Calibration Value Register

Interrupt Set Enable Register

Interrupt Clear Enable Register

Interrupt Set Pending Register

Interrupt Clear Pending Register

Interrupt 0 ~ 3 Priority Register








CPUID register

Interrupt Control and State Register

Vector Table Offset Register

Application Interrupt and Reset Control Register

System Control Register

Configuration and Control Register

System Handlers Priority Register 2

System Handlers Priority Register 3

Reset Value

0x0000_0000

Unpredictable

Unpredictable

0x4000_1D4C

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x410C_C601

0x0000_0000

0x0000_0000

0xFA05_0000

0x0000_0000

0x0000_0208

0x0000_0000

0x0000_0000

Note: For more detailed descriptions of the above registers, refer to the “Cortex ®

User Guide” document from Arm.

-M0+ Devices Generic

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12

USB Device Controller (USB)

Introduction

The USB device controller is compliant with the USB 2.0 full-speed specification. There is one control endpoint know as Endpoint 0 and seven configurable endpoints (EP1 ~ EP7). A 1024byte EP_SRAM is used for the endpoint buffers. Each endpoint buffer size is programmable by corresponding registers, which provides maximum flexibility for various applications. The integrated USB full-speed transceiver helps to minimize overall system complexity and cost. The

USB also contains the suspend and resume features to meet low-power consumption requirement.

The accompanying figure shows the USB block diagram.

Registers Control Logic

HCLK

48 MHz_CLK

Interrupt

256 32-bit

EP_SRAM

Endpoint 0

Ctrl

IN and OUT

Endpoint type A

Int/Bulk

IN or OUT

Endpoint type B

Int/Bulk/Iso

IN or OUT

USB Device Controller (USB)

Figure 28. USB Block Diagram

Serial

Interface

Engine

(SIE)

DP

On-chip

USB Full-Speed

Transceiver

DM

Features

▆

Complies with USB 2.0 full-speed (12 Mbps) specification

▆

▆

▆

▆

▆

Fully integrated USB full-speed transceiver

1 control endpoint (EP0) for control transfer

3 single-buffered endpoints (EP1 ~ EP3) for bulk and interrupt transfer

4 double-buffered endpoints (EP4 ~ EP7) for bulk, interrupt and isochronous transfer

1,024 bytes EP_SRAM used as endpoint data buffers

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Endpoints

The USB Endpoint 0 is the only bidirectional endpoint dedicated to USB control transfer. The device also contains seven unidirectional endpoints for other USB transfer types. There are three endpoints (EP1 ~ EP3) which support a single buffering function which is used for Bulk and

Interrupt IN or OUT data transfer. There are four other endpoints (EP4 ~ EP7) which support single or double buffering functions for Bulk, Interrupt and Isochronous IN or OUT data transfer.

The address of the seven unidirectional endpoints (EP1 ~ EP7) can be configured by the application software. The following table lists the endpoint characteristics.

Table 29. Endpoint Characteristics

Endpoint

Number

0

1 ~ 3

4 ~ 7

Number

Address

Fixed

Transfer Type

Control

Configurable Interrupt/Bulk

Direction Buffer Type

IN and OUT Single buffering

IN or OUT Single buffering

Configurable Interrupt/Bulk/Isochronous IN or OUT Single or Double buffering

EP_SRAM

The USB controller contains a dedicated memory space, EP_SRAM, which is used for the USB endpoint buffers. The EP_SRAM, which is connected to the APB bus, can be accessed by the MCU and PDMA. The EP_SRAM base address is 0x400A_A000 with an offset which ranges from 0x000 to 0x3FF. The EP_SRAM first two words are reserved for Endpoint 0 to temporarily store the 8-byte

SETUP data. Therefore the valid start address of the endpoint buffer should start from 0x400A_

A008 and align to a 4-byte boundary. Each endpoint buffer size is programmable. The following table lists the maximum USB endpoint buffer size which is compliant with USB 2.0 full-speed device specification.

Table 30. USB Data Types and Buffer Size

Transfer Type Direction Supported Buffer Size Bandwidth CRC Retrying

Control Bidirectional 8, 16, 32, 64 bytes Not guaranteed Yes Automatic

Bulk Unidirectional 8, 16, 32, 64 bytes Not guaranteed Yes Yes

Interrupt

Isochronous

Unidirectional ≤ 64 bytes

Unidirectional < 512 bytes

Not guaranteed

Guaranteed

Yes

Yes

Yes

No

In the following endpoint buffer allocation example, the Endpoint “4” is configured as a doublebuffered Bulk IN endpoint while the Endpoint “5” is configured as a double-buffered Bulk OUT endpoint. Each endpoint buffer size is set to 64 bytes.

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1,024 bytes EP_SRAM

0x3FF

Not used space: 158 words

0x188

Endpoint 5 buffer 1: 64 bytes

0x148


0x108


0x0C8


0x088

Endpoint 0 OUT buffer: 64 bytes

0x048

0x008

0x000

Endpoint 0 IN buffer: 64 bytes

Reserved for Endpoint 0: 8 bytes

Figure 29. Endpoint Buffer Allocation Example

Double-buffered

Bulk OUT endpoint

Double-buffered

Bulk IN endpoint

Bidirectional

Control endpoint

Serial Interface Engine – SIE

The Serial Interface Engine, SIE, which is connected to the USB full-speed transceiver and internal

USB control circuitry, provides a temporal buffer for the transmitted and received data. The SIE also decodes the SE0 signal, SE1 signal, J-state, K-state, USB RESET event and End of Packet event signals, EOP, when the USB module receives data, transmits data or transmits the resume signal for remote control. The SIE detects the number of SOF packets and generates the SOF interrupt signal to the USB control circuitry which includes data format conversion from parallel to serial or serial to parallel. It also includes CRC checking and generation, PID decoder, bit-stuffing and debit-stuffing functions.

Double-Buffering

The double buffering function is recommended to be enabled when the corresponding endpoint is specified to be used for Isochronous transfer or high throughput Bulk transfer. The double buffering function stores the preceding data packet sent by the USB host in a simple buffer for the MCU to process and the hardware will ensure that it continues to receive the current data packet in the other buffer during an OUT transaction, and vice versa. Using a double buffering function can achieve the highest possible data transfer rate. The details regarding double buffering usage is provided in the corresponding UDBTG and MDBTG control bit description in the USBEPnCSR register where the denotation n ranges from 4 to 7.

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IN Transaction

Buffer Accessed by USB SIE

Buffer Accessed by MCU

[UDBTG,MDBTG]= [0,0]

Endpoint 4

Buf 0

1st Data packet processed by MCU

Endpoint 4

Buf 1

2nd Data packet processed by MCU

Buffer toggled by SIE hardware

Endpoint 4

Buf 0

1st Data packet transmitted to Host

Buffer toggled by MCU software

Endpoint 4

Buf 1

2nd Data packet transmitted to Host

Endpoint 4

Buf 0

3rd Data packet processed by MCU

Endpoint 4

Buf 0

3rd Data packet transmitted to Host

Endpoint 4

Buf 1

[0,1] [1,1] [1,0] [0,0] [0,1] [1,1] [1,0] [0,0] t

OUT Transaction

Buffer Accessed by USB SIE

Endpoint 4

Buf 0

1st Data packet received from Host

Buffer toggled by SIE hardware

Endpoint 4

Buf 1

2nd Data packet received from Host

Endpoint 4

Buf 0

3rd Data packet received from Host

Buffer toggled by MCU software

Endpoint 4

Buf 1

Buffer Accessed by MCU

Endpoint 4

Buf 0

1st Data packet processed by MCU

[0,0]

Endpoint 4

Buf 1

2nd Data packet processed by MCU

[0,1] [1,1]

Endpoint 4

Buf 0

3rd Data packet processed by MCU

[1,0] [0,0] t

[UDBTG,MDBTG]= [0,0] [0,1] [1,1] [1,0]

Figure 30. Double-buffering Operation Example

Suspend Mode and Wake-up

According to USB specifications, the device must enter the suspend mode after a 3 ms bus idle time. When the USB device enters the suspend mode, the current from the USB bus must not be greater than 500 μA to meet the specification suspend mode current requirements. The USB control circuitry will generate a suspend interrupt if the bus is in the idle state for 3 ms. Here the software should set the LPMODE and PDWN bits in the USBCSR register to 1. The LPMODE bit is used to determine whether the USB controller enters the low-power mode or not by holding the USB bus in a reset condition while the PDWN bit is used to determine if the integrated USB full-speed transceiver is turned off or not.

There are two ways for the USB host to wake up the USB device, one is to send a USB reset signal,

SE0, and the other is to send a USB resume signal known as the K-state. After a wake-up signal, regardless of whether an SE0 signal or a K-state is detected, the USB device will be woken up.

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Remote Wake-up

As the USB device has a remote wake-up function, it can wake up the USB host by sending a resume request signal by setting the GENRSM bit in the USBCSR register to 1. Once the USB host receives the remote wake-up signal from the USB device, it will send a resume signal to the USB device.

Register Map

The following table shows the USB registers and reset values.

Table 31. USB Register Map

Register

USBCSR

USBIER

USBISR

USBFCR

Offset

0x000

0x004

0x008

0x00C

Description

USB Control and Status Register

USB Interrupt Enable Register

USB Interrupt Status Register

USB Frame Count Register

USBDEVAR

USBEP0CSR

USBEP0IER

0x010

0x014

0x018

USBEP0ISR

USBEP0TCR

0x01C

0x020

USBEP0CFGR 0x024

USBEP1CSR

USBEP1IER

USBEP1ISR

0x028

0x02C

0x030

USBEP1TCR 0x034

USBEP1CFGR 0x038

USBEP2CSR

USBEP2IER

0x03C

0x040

USBEP2ISR

USBEP2TCR

0x044

0x048

USBEP2CFGR 0x04C

USBEP3CSR

USBEP3IER

USBEP3ISR

0x050

0x054

0x058

USBEP3TCR 0x05C

USBEP3CFGR 0x060

USBEP4CSR

USBEP4IER

0x064

0x068

USBEP4ISR

USBEP4TCR

0x06C

0x070

USBEP4CFGR 0x074

USBEP5CSR

USBEP5IER

USBEP5ISR

0x078

0x07C

0x080

USBEP5TCR 0x084

USBEP5CFGR 0x088

USB Device Address Register

USB Endpoint 0 Control and Status Register

USB Endpoint 0 Interrupt Enable Register

USB Endpoint 0 Interrupt Status Register

USB Endpoint 0 Transfer Count Register

USB Endpoint 0 Configuration Register


























Reset Value

0x0000_00X6

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0002

0x0000_0000

0x0000_0000

0x0000_0000

0x8000_0008

0x0000_0002

0x0000_0000

0x0000_0000

0x0000_0000

0x1000_03FF

0x0000_0002

0x0000_0000

0x0000_0000

0x0000_0000

0x1000_03FF

0x0000_0002

0x0000_0000

0x0000_0000

0x0000_0000

0x1000_03FF

0x0000_0002

0x0000_0000

0x0000_0000

0x0000_0000

0x1000_03FF

0x0000_0002

0x0000_0000

0x0000_0000

0x0000_0000

0x1000_03FF

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Register

USBEP6CSR

USBEP6IER

USBEP6ISR

Offset

0x08C

0x090

0x094

USBEP6TCR 0x098

USBEP6CFGR 0x09C

USBEP7CSR 0x0A0

USBEP7IER

USBEP7ISR

USBEP7TCR

0x0A4

0x0A8

0x0AC

USBEP7CFGR 0x0B0

Description












USB Control and Status Register – USBCSR

This register specifies the USB control bits and USB data line status.

Offset: 0x000

Reset value: 0x0000_00X6

Reset Value

0x0000_0002

0x0000_0000

0x0000_0000

0x0000_0000

0x1000_03FF

0x0000_0002

0x0000_0000

0x0000_0000

0x0000_0000

0x1000_03FF

31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

15

7

RXDM

14

Reserved

6

RXDP

13

5

Type/Reset RO X RO X RW 0

12 11 10 9 8

FREST DPWKEN DPPUEN SRAMRSTC ADRSET


4 3

GENRSM Reserved LPMODE

2

PDWN

1

FRES

RW 0 RW 1 RW 1

0

Reserved

Bits

[12]

[11]

[10]

[9]

Field

FREST

DPWKEN

Descriptions

Force USB Reset Control Timing

This bit is used to decide the timing to release the USB reset state.

0: When the FRES bit is cleared, immediately release the USB reset state

1: When the FRES bit is set, wait to release the USB reset state until SE0 is detected

DP Wake-Up Enable

0: Disable DP wake-up

1: Enable DP wake-up

DPPUEN DP Pull-Up Enable

0: Disable DP pull-up

1: Enable DP pull-up

SRAMRSTC EP_SRAM Reset Condition

0: Reset EP_SRAM when (DP, DM) = (0, 0)

1: Users can access EP_SRAM in spite of (DP, DM) state

Rev. 1.00 209 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

[7]

[6]

[5]

Bits

[8]

[3]

[2]

[1]

Field

ADRSET

RXDM

RXDP

GENRSM

LPMODE

PDWN

FRES

Descriptions

Device Address Setting Control

This bit is used to determine when the USB SIE updates the device address with the value of the USBDEVAR register.

0: The SIE updates the device address immediately after an address is written into the USBDEVAR register.

1: The SIE updates the device address after the USB Host has successfully read the data from the device by the IN operation. This bit is cleared by the SIE after the device address is updated.

Received DM Line Status

This bit is used to observe the status of DM data line status at the end of suspend routines to determine whether a wakeup event has occurred.

Received DP Line Status

This bit is used to observe the status of DP data line status at the end of suspend routines to determine whether a wake-up event has occurred.

Resume Request Generation Control

This bit is used to generate a resume request which is sent to the USB host by writing 1 into this bit location. The USB remote wake-up function is always enabled.

This bit will be cleared to 0 after a resume signal sent by the USB host has been received.

Low-power Mode Control

This bit is used to determine the USB operating mode. Setting this bit will force the

USB to enter the low-power mode. When USB bus traffic, known as a wake-up event, is detected by the hardware, this bit should be cleared by software.

0: Exit the Low-power mode

1: Enter the Low-power mode

Power-Down Mode Control

Setting this bit will power down the full-speed USB PHY transceiver. This will disconnect the USB PHY transceiver from the USB bus.

0: Exit the Power-Down

1: Enter the Power-Down mode

Force USB Reset Control

This bit is used to reset the USB circuitry. Setting this bit will force the USB into a reset state until the software clears it. A USB reset interrupt will be generated if the corresponding interrupt enable bit in the USBIER register is set to 1. All related USB registers are reset to their default values.

0: Release USB reset

1: Force USB reset

Table 32. Resume Event Detection

[RXDP, RXDM] Status

00

10

01

11

Wake-up Event

Root reset

None (noise on bus)

Required Resume Software Action

None

Go back to suspend mode

Root resume None

Not allowed (noise on bus) Go back to suspend mode

Rev. 1.00 210 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

USB Interrupt Enable Register – USBIER

This register specifies the USB interrupt enable control.

Offset: 0x004


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15

EP7IE

14

EP6IE

13

EP5IE

12

EP4IE

11

EP3IE

10

EP2IE

9

EP1IE

8

EP0IE


7 6 5 4 3 2 1 0

Type/Reset

Reserved FRESIE ESOFIE SUSPIE RSMIE URSTIE SOFIE UGIE

RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

Bits

[15:8]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

Field

EPnIE

FRESIE

ESOFIE

SUSPIE

RSMIE

URSTIE

SOFIE

UGIE

Descriptions

Endpoint n Interrupt Enable Control (n = 0 ~ 7)

0: Disable interrupt

1: Enable interrupt

Force USB Reset Control (FRES) Interrupt Enable Control

0: Disable FRES interrupt

1: Enable FRES interrupt

Expected Start-Of-Frame (ESOF) Interrupt Enable Control

0: Disable ESOF interrupt

1: Enable ESOF interrupt

Suspend Interrupt Enable Control

0: Disable Suspend interrupt

1: Enable Suspend interrupt

Resume Interrupt Enable Control

0: Disable Resume interrupt

1: Enable Resume interrupt

USB Reset Interrupt Enable Control

0: Disable USB Reset interrupt

1: Enable USB Reset interrupt

Start-Of-Frame (SOF) Interrupt Enable Control

0: Disable SOF interrupt

1: Enable SOF interrupt

USB Global Interrupt Enable Control

0: Disable USB Global interrupt

1: Enable USB Global interrupt

This bit must be set to 1 to enable the corresponding USB interrupt function. If this bit is cleared to 0, the relevant USB interrupt will not be generated, however, the corresponding interrupt flags will still be asserted.

Rev. 1.00 211 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

USB Interrupt Status Register – USBISR

This register specifies the USB interrupt status.

Offset: 0x008


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

15

EP7IF

Reserved

14

EP6IF

FRESIF

13

EP5IF

ESOFIF

12

EP4IF

SUSPIF

11

EP3IF

RSMIF

10

EP2IF

URSTIF

9

EP1IF

SOFIF

WC 0 RW 0 WC 0 WC 0 WC 0 WC 0

8

EP0IF


7 6 5 4 3 2 1 0

Reserved

Bits

[15:8]

[6]

[5]

[4]

[3]

Field

EPnIF

FRESIF

ESOFIF

SUSPIF

RSMIF

Descriptions

Endpoint n Interrupt Flag (n = 0 ~ 7)

This bit is set by the hardware to indicate the generation of relevant endpoint interrupts.

Writing 1 into this bit to clear it. It is important to note that the interrupt flag can only be cleared when the endpoint interrupt status bit in the USBEPnISR register is equal to 0.

Force USB Reset Control (FRES) Interrupt Flag

This bit is set by the hardware. When this bit is set 1, this means that Force USB

Reset FRES has finished.

This bit is cleared to 0 by writing 1.

Expected Start-Of-Frame Interrupt Flag

This bit is set by the hardware when an SOF packet is expected to be received.

The USB host sends an SOF (Start-Of-Frame) packet each millisecond. If the USB device hardware does not receive it properly, an ESOF interrupt will be generated when the ESOFIE bit in the USBIER register is set to 1. If three consecutive ESOF interrupts are generated, which means that the SOF packet has been missed 3 times, the SUSPIF flag will be set to 1. This bit will be set to 1 when the missing

SOF packets occur if the timer is not yet locked.

This bit can be read or written. However, only 0 can be written into this bit. Writing 1 has no effect.

Suspend Interrupt Flag

This bit is set by the hardware when no data transfer has occurred for 3ms, indicating that a suspend request has been sent from the USB host. The suspend condition check is enabled immediately after a USB reset.


Resume Interrupt Flag

This bit is set by the hardware. When this bit is set 1, this means that a device resume has occurred.


Rev. 1.00 212 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[2]

[1]

Field

URSTIF

SOFIF

Descriptions

USB Reset Interrupt Flag

This bit is set by the hardware when the USB reset has been detected. When a

USB reset occurs, the internal protocol state machine will be reset and an USB reset interrupt will be generated if the URSTIE bit in the USBIER register is set to

1. Data reception and transmission are disabled until the URSTIF bit is cleared to

0. The USB configuration related registers (USBCSR, USBIER, USBISR, USBFCR and USBDEVAR) will not be reset by a USB reset event except for the USB device address (USBDEVAR), this is to ensure that a USB reset interrupt can be safely excited and any data transactions immediately followed by the USB reset can be completely accessed by the software. Therefore the microcontroller must properly reset these registers. The USB endpoint related registers (USBEPnCSR,

USBEPnISR and USBEPnTCR) are also reset by a USB reset event, however, the endpoint configuration (USBEPnCFGR) and interrupt enable (USBEPnIER) registers are not affected by the USB reset event and will remain unchanged.


SOF Interrupt Flag

This bit is set by the hardware when a start-of-frame packet has been received.


USB Frame Count Register – USBFCR

This register specifies the lost Start-of-Frame number and the USB frame count.

Offset: 0x00C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

Type/Reset

23

15

22

14

21

Reserved

13

Reserved

20

12

19

11

18

10

17

LSOF

9

FRNUM

16

SOFLCK

RO 0 RO 0 RO 0

8

Type/Reset

7 6 5 4 3

FRNUM

RO 0 RO 0 RO 0

2 1 0


Bits

[18:17]

Field

LSOF

Descriptions

Lost Start-of-Frame number

These bits are written and incremented by 1 by the hardware each time the ESOFIF bit is set. It is used to count the number of lost SOF packets. Once this field equals to 3, which means that the SOF packet has been lost 3 times, the SUSPIF flag will be set to 1. When a SOF packet has been received, these bits are cleared.

Rev. 1.00 213 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[16]

[10:0]

Field

SOFLCK

FRNUM

Descriptions

Start-of-Frame Lock Flag

This bit is set by the hardware when SOF packets have been received before the frame timer times out. Once this flag is set to 1, the frame number which is sent from the USB host will be loaded into the Frame Number field FRNUM in the USBFCR register. If there is no SOF packet has been received during the 1ms frame time duration, this bit will be cleared to 0.

Frame Number

This field stores the frame number received from the USB host.

USB Device Address Register – USBDEVAR

This register specifies the USB device address.

Offset: 0x010


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

Reserved

10 9 8

Type/Reset

Type/Reset

7

Reserved

6 5 4 3

DEVA

2 1 0


Bits

[6:0]

Field

DEVA

Descriptions

Device Address

This field is used to specify the USB device address. This field is cleared when a

USB reset event occurs.

Rev. 1.00 214 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

USB Endpoint 0 Control and Status Register – USBEP0CSR

This register specifies the Endpoint 0 control and status.

Offset: 0x014


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

14 13 12 11

Reserved

10 9 8

6 5

Reserved STLRX

4

NAKRX

3

DTGRX

2

STLTX

1

NAKTX

0

DTGTX


Bits

[5]

[4]

[3]

[2]

Field

STLRX

NAKRX

DTGRX

STLTX

Descriptions

STALL Status for reception (OUT) transfer

This bit is set to 1 by the application software and then returns a STALL signal in the handshake phase of an OUT transaction if a functional error is detected. This means that a control request delivered from the USB host is not supported by the USB device. The STALL status is cleared by the hardware circuitry when a new SETUP token is received.

This bit can be read and written and can only be toggled by writing 1.

NAK Status for reception (OUT) transfer

This bit is toggled from 0 to 1 by the hardware circuitry, which will result in an NAK signal in the handshake phase of an OUT transaction after an ACK signal has been transmitted. This means that the USB device will be temporarily unable to accept data from the USB host. Therefore, more time will be required for the received data to be properly processed.


Data Toggle Status for reception (OUT) transfer

This bit contains the expected value of the data toggle bit (0 = DATA0, 1 = DTAT1) for the next data packet to be received. When the current valid data packet is received and the corresponding ACK signal is sent to the USB host by the USB device, the hardware circuitry will toggle this bit and the device will be ready to receive the next data packet. For Endpoint 0, the hardware circuitry will toggle this bit to 1 after the

SETUP token is received as Endpoint 0 is addressed. This bit can also be toggled by the software to initialize its value for certain applications.


STALL Status for transmission (IN) transfer

This bit is set to 1 by the application software and then returns a STALL signal in response to an IN token if a functional error is detected. This means that the USB device is unable to transmit data. The STALL status is cleared by the hardware circuitry when a new SETUP token is received.


Rev. 1.00 215 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[1]

[0]

Field

NAKTX

DTGTX

Descriptions

NAK Status for transmission (IN) transfer

This bit is toggled from 0 to 1 by the hardware circuitry, which will result in a NAK signal in the handshake phase of an IN transaction after an ACK signal has been received. It indicates that the USB device is temporarily unable to transmit data to the

USB host. Therefore, there will be more time for the application software to properly prepare the data to be transmitted.


Data Toggle Status for transmission (IN) transfer

This bit contains the required value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be transmitted. When the current data packet is transmitted by the USB device and the corresponding ACK signal sent by the USB host is received, the hardware circuitry will toggle this bit and the next data packet will be transmitted. For Endpoint 0, the hardware circuitry will toggle this bit to 1 after the

SETUP token is received as Endpoint 0 is addressed. This bit can also be toggled by the software to initialize its value for certain applications.


USB Endpoint 0 Interrupt Enable Register – USBEP0IER

This register specifies the Endpoint 0 interrupt control bits.

Offset: 0x018


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13

Reserved

12 11

ZLRXIE

10

SDERIE

9

SDRXIE

8

STRXIE

Type/Reset

7

UERIE

6

STLIE

5

NAKIE

4

IDTXIE

RW 0 RW 0 RW 0 RW 0

3

ITRXIE

2

ODOVIE

1

ODRXIE

0

OTRXIE


Bits

[11]

[10]

[9]

Field

ZLRXIE

SDERIE

SDRXIE

Descriptions

Zero Length Data Received Interrupt Enable Control


1: Enable interrupt

SETUP Data Error Interrupt Enable Control


1: Enable interrupt

SETUP Data Received Interrupt Enable Control


1: Enable interrupt

Rev. 1.00 216 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[8]

[1]

[0]

[3]

[2]

[5]

[4]

[7]

[6]

Field

STRXIE

UERIE

STLIE

NAKIE

IDTXIE

ITRXIE

ODOVIE

ODRXIE

OTRXIE

Descriptions

SETUP Token Received Interrupt Enable Control


1: Enable interrupt

USB Error Interrupt Enable Control


1: Enable interrupt

STALL Transmitted Interrupt Enable Control


1: Enable interrupt

NAK Transmitted Interrupt Enable Control


1: Enable interrupt

IN Data Transmitted Interrupt Enable Control


1: Enable interrupt

IN Token Received Interrupt Enable Control


1: Enable interrupt

OUT Data Buffer Overrun Interrupt Enable Control


1: Enable interrupt

OUT Data Received Interrupt Enable Control


1: Enable interrupt

OUT Token Received Interrupt Enable Control


1: Enable interrupt

Rev. 1.00 217 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

USB Endpoint 0 Interrupt Status Register – USBEP0ISR

This register specifies the Endpoint 0 interrupt status.

Offset: 0x01C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13

Reserved

12 11

ZLRXIF

10 9

SDERIF SDRXIF

8

STRXIF

Type/Reset

7

UERIF

6

STLIF

5

NAKIF

4

IDTXIF

WC 0 WC 0 WC 0 WC 0

3

ITRXIF

2 1

ODOVIF ODRXIF

0

OTRXIF


Bits

[11]

[10]

[9]

[8]

[7]

[6]

[5]

Field

ZLRXIF

SDERIF

SDRXIF

STRXIF

UERIF

STLIF

NAKIF

Descriptions

Zero Length Data Received Interrupt Flag

This bit is set by the hardware when a zero length data packet is received.

This bit is cleared by hardware when a SETUP Token is received or by writing 1.

SETUP Data Error Interrupt Flag

This bit is set by the hardware when the SETUP data packet length is not 8 bytes.


SETUP Data Received Interrupt Flag

This bit is set by the hardware when a SETUP data packet from the USB host has been received. This bit is cleared by the hardware when a SETUP Token is received or by writing 1. If the received SETUP data is not accessed by the application software before the next SETUP packet is received, the SETUP data buffer will be overwritten.

SETUP Token Received Interrupt Flag

This bit is set by the hardware when a SETUP token is received and is cleared by writing 1.

USB Error Interrupt Flag

This bit is set by the hardware when an error occurs during the Endpoint 0 transaction.


STALL Transmitted Interrupt Flag

This bit is set by the hardware when a STALL signal is sent in response to an IN or

OUT transaction.


NAK Transmitted Interrupt Flag

This bit is set by the hardware when a NAK signal is sent in response to an IN or

OUT transaction.


Rev. 1.00 218 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

[3]

[2]

Bits

[4]

[1]

[0]

Field

IDTXIF

ITRXIF

ODOVIF

ODRXIF

OTRXIF

Descriptions

IN Data Transmitted Interrupt Flag

This bit is set by the hardware when a data packet is transmitted to and then an ACK signal is received from the USB host.


IN Token Received Interrupt Flag

This bit is set by the hardware when the IN token is received from the USB host.


OUT Data Buffer Overrun Interrupt Flag

This bit is set by the hardware when the number of received data bytes is larger than the endpoint buffer size.


OUT Data Received Interrupt Flag

This bit is set by the hardware when a data packet is successfully received from the

USB host and then an ACK signal is sent to the USB host.


OUT Token Received Interrupt Flag

This bit is set by the hardware when the OUT token is received from the USB host.


USB Endpoint 0 Transfer Count Register – USBEP0TCR

This register specifies the Endpoint 0 data transfer byte count.

Offset: 0x020


31 30 29 28 27

Reserved

26 25 24

Type/Reset

Type/Reset

23

Reserved

15

22 21 20 19

RXCNT

18 17 16

RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

14 13 12 11

Reserved

10 9 8

Type/Reset

Type/Reset

7

Reserved

6 5 4 3

TXCNT

2 1 0


Bits

[22:16]

[6:0]

Field

RXCNT

TXCNT

Descriptions

Reception Byte Count

The bit field contains the number of data bytes received by Endpoint 0 in the preceding SETUP transaction.

Transmission Byte Count

The bit field contains the number of data bytes to be transmitted by Endpoint 0 in the next IN token. If the value of this field is zero, it indicates that a zero length packet will be sent.

Rev. 1.00 219 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

USB Endpoint 0 Configuration Register – USBEP0CFGR

This register specifies the Endpoint 0 configurations.

Offset: 0x024


31

EPEN

Type/Reset RO 1

23

30

22

29

Reserved

21

28

20

Reserved

27 26 25

EPADR

24

RO 0 RO 0 RO 0 RO 0

19 18 17 16

EPLEN

RW 0 Type/Reset

15 14 13 12

EPLEN

11 10 9 8

EPBUFA


7 6 5 4 3 2 1 0

EPBUFA


Bits

[31]

[27:24]

[16:10]

[9:0]

Field

EPEN

EPADR

EPLEN

EPBUFA

Descriptions

Endpoint Enable Control

This bit is always set to 1 by the hardware circuitry to always enable Endpoint 0.

Endpoint Address

This field is always set to 0 by the hardware circuitry.

Endpoint Buffer Length

This field is used to specify the control transfer packet size which can be 8, 16, 32 or

64 bytes as defined in the USB full-speed standard specification.

Endpoint Buffer Address

This field is used to specify the star address of the Endpoint 0 buffer allocated in the

EP_SRAM. It starts from 0x008 and should be aligned to 4-byte boundary.

Start address of EP0 IN buffer = EPBUFA

Start address of EP0 OUT buffer = EPBUFA + EPLEN

Rev. 1.00 220 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

USB Endpoint 1 ~ 3 Control and Status Register – USBEPnCSR, n = 1 ~ 3

This register specifies the Endpoint 1 ~ 3 control and status bit.

Offset: 0x028 (n = 1), 0x03C (n = 2), 0x050 (n = 3)


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

14 13 12 11

Reserved

10 9 8

6 5

Reserved STLRX

4

NAKRX

3

DTGRX

2

STLTX

1

NAKTX

0

DTGTX


Bits

[5]

[4]

[3]

[2]

[1]

Field

STLRX

NAKRX

DTGRX

STLTX

NAKTX

Descriptions

STALL bit for reception transfers

This bit is set to 1 by the application software if a functional error has been detected.

This bit can be read and written and can only be toggled by writing 1. It can also be toggled by the software to initialize the value under certain conditions.

NAK bit for reception transfers

This bit is toggled from 0 to 1 by the hardware circuitry, which will result in a NAK signal in the handshake phase of an OUT transaction after an ACK signal has been transmitted. It means that the USB device will be temporarily unable to accept data from the USB host until the received data is properly processed.

This bit can be read and written and can be only toggled by writing 1.

Data Toggle bit for reception transfers

This bit contains the expected value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be received. When the current valid data packet is received and the corresponding ACK signal is sent to the USB host by the USB device, the hardware circuitry will toggle this bit and the device will be ready to receive the next data packet.

This bit can be read and written and can only be toggled by writing 1. This bit can also be toggled by the software to initialize its value under certain conditions.

STALL bit for transmission transfers


This bit can be read and written and can be only toggled by writing 1. It can also be toggled by the software to initialize its value under certain conditions.

NAK bit for transmission transfers

This bit is toggled from 0 to 1 by the hardware circuitry, which will result in a NAK signal in the handshake phase of an IN transaction after an ACK signal has been received. It means that the USB device will be temporarily unable to transmit data packet until the data to be transmitted is appropriately prepared by the application software.


Rev. 1.00 221 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[0]

Field

DTGTX

Descriptions

Data Toggle bit for transmission transfers

This bit contains the required value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be transmitted. When the current data packet is transmitted by the USB device and the corresponding ACK signal sent from the USB host is received, the hardware circuitry will toggle this bit and then the next data packet will be transmitted.

This bit can be read and written and can only be toggled by writing 1. It can also be toggled by the software to initialize its value under certain conditions.

USB Endpoint 1 ~ 3 Interrupt Enable Register – USBEPnIER, n = 1 ~ 3

This register specifies the Endpoint 1 ~ 3 interrupt enable control bits.

Offset: 0x02C (n = 1), 0x040 (n = 2), 0x054 (n = 3)


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

Reserved

10 9 8

Type/Reset

7

UERIE

6

STLIE

5

NAKIE

4

IDTXIE

3

ITRXIE

2

ODOVIE

1

ODRXIE

0

OTRXIE


Bits

[7]

[6]

[5]

[4]

[3]

[2]

Field

UERIE

STLIE

NAKIE

IDTXIE

ITRXIE

ODOVIE

Descriptions



1: Enable interrupt



1: Enable interrupt



1: Enable interrupt



1: Enable interrupt



1: Enable interrupt



1: Enable interrupt

Rev. 1.00 222 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[1]

[0]

Field

ODRXIE

OTRXIE

Descriptions



1: Enable interrupt

OUT Token Received Interrupt Enable Control.


1: Enable interrupt

USB Endpoint 1 ~ 3 Interrupt Status Register – USBEPnISR, n = 1 ~ 3

This register specifies the Endpoint 1 ~ 3 interrupt status.

Offset: 0x030 (n = 1), 0x044 (n = 2), 0x058 (n = 3)


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

Reserved

10 9 8

Type/Reset

7

UERIF

6

STLIF

5

NAKIF

4

IDTXIF

3

ITRXIF

2

ODOVIF

1

ODRXIF

0

OTRXIF


Bits

[7]

[6]

[5]

[4]

[3]

Field

UERIF

STLIF

NAKIF

IDTXIF

ITRXIF

Descriptions

USB Error Interrupt Flag

This bit is set by the hardware when an error occurs during the transaction.

Writing 1 into this status bit will clear it to 0.

STALL Transmitted Interrupt Flag

This bit is set by hardware circuitry when a STALL signal is sent in response to an IN or OUT token and is cleared to 0 by writing 1.

NAK Transmitted Interrupt Flag

This bit is set by hardware circuitry when an NAK signal is sent in response to an IN or OUT token and is cleared to 0 by writing 1.

IN Data Transmitted Interrupt Flag

This bit is set by hardware circuitry when a data packet is successfully transmitted to the host in response to an IN token and an ACK signal is received.


IN Token Received Interrupt Flag

This bit is set by the hardware circuitry when the endpoint receives an IN token from the host and is cleared to 0 by writing 1.

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Bits

[2]

[1]

[0]

Field

ODOVIF

ODRXIF

OTRXIF

Descriptions

OUT Data Buffer Overrun Interrupt Flag

This bit is set by the hardware circuitry when the received data byte count is larger than the corresponding endpoint OUT data buffer size.


OUT Data Received Interrupt Flag

This bit is set by the hardware circuitry when a data packet is successfully received from the host for an OUT token and when an endpoint n ACK signal is sent to the host.


OUT Token Received Interrupt Flag

This bit is set by the hardware circuitry when the endpoint receives an OUT token from the host and is cleared to 0 by writing 1.

USB Endpoint 1 ~ 3 Transfer Count Register – USBEPnTCR, n = 1 ~ 3

This register specifies the Endpoint 1 ~ 3 transfer byte count.

Offset: 0x034 (n = 1), 0x048 (n = 2), 0x05C (n = 3)


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

15

7

14

6

13

5

12

Reserved

4

11

3

TCNT

10

2

9

1

8

TCNT

RW 0

0


Bits

[8:0]

Field

TCNT

Descriptions

Transfer Byte Count

This field contains the number of bytes received by the endpoint n in the preceding

OUT transaction or the number of bytes to be transmitted by the endpoint n in the next IN transaction.

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USB Endpoint 1 ~ 3 Configuration Register – USBEPnCFGR, n = 1 ~ 3

This register specifies the Endpoint 1 ~ 3 configurations.

Offset: 0x038 (n = 1), 0x04C (n = 2), 0x060 (n = 3)

Reset value: 0x1000_03FF

31

EPEN

Type/Reset RW 0

23

30 29

Reserved EPTYPE

28

EPDIR

27 26 25

EPADR

24


22 21 20

Reserved

19 18 17 16

EPLEN

RW 0 Type/Reset

15 14 13 12

EPLEN

11 10 9 8

EPBUFA


7 6 5 4 3 2 1 0

EPBUFA


Bits

[31]

[29]

[28]

[27:24]

[16:10]

[9:0]

Field

EPEN

EPTYPE

EPDIR

EPADR

EPLEN

EPBUFA

Descriptions

Enable Control

0: Disable the endpoint n

1: Enable the endpoint n

Transfer Type

This bit is set to 0 by the hardware circuitry to specify that the endpoint n transfer type is an Interrupt or Bulk transfer type.

Transfer Direction

0: OUT

1: IN

Endpoint Address

The EPADR field value can be assigned by the application software to specify the address of the endpoint n. It is important to note that this EPADR field should not be set to 0; otherwise, the endpoint will be disabled.

Buffer Length

This field is used to specify the endpoint n data packet size. The field value must be word-aligned to a 4-byte boundary. The maximum size in this field can be 64 bytes which is the maximum payload as defined in the USB full-speed standard specification. Note that the EPLEN value should not be assigned to 0 which will result in the endpoint being disabled.

Endpoint Buffer Address

This field is used to specify the endpoint n data buffer start address which ranges from 0x008 to 0x3FC in the EP_SRAM which has a capacity of 1024 bytes and whose field value must be a multiple of 4.

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USB Endpoint 4 ~ 7 Control and Status Register – USBEPnCSR, n = 4 ~ 7

This register specifies the Endpoint 4 ~ 7 control and status bits.

Offset: 0x064 (n = 4), 0x078 (n = 5), 0x08C (n = 6), 0x0A0 (n = 7)


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

Reserved

10 9 8

Type/Reset

7

UDBTG

6

MDBTG

5

STLRX

4

NAKRX

3

DTGRX

2

STLTX

1

NAKTX

0

DTGTX


Bits

[7]


UDBTG USB Double Buffer Toggle bit

The UDBTG and MDBTG bits are used to indicate which data buffer is accessed by the USB SIE hardware and which data buffer is accessed by the MCU software if the double buffering function is enabled. The UDBTG bit will be toggled by the SIE hardware circuitry after the current buffer operation is complete. After the UDBTG bit is toggled by the SIE, an NAK signal will be sent automatically to the USB host by the hardware circuitry. Therefore, the data transfer will be stopped temporarily until the data in the other buffer has been properly setup after which the MDBTG bit is toggled by the

MCU application software.

The following tables show the double buffering operation and the UDBTG and MDBTG bit status for an IN or OUT transaction.

Transaction

Type

UDBTG MDBTG Buffer Read by SIE Buffer Written by MCU

IN

1

1

0

0

1

0

0

1

None*

EP_BUF0

None*

EP_BUF1

EP_BUF0

EP_BUF1

EP_BUF1

EP_BUF0

Transaction

Type

UDBTG MDBTG Buffer Written by SIE Buffer Read by MCU

OUT

1

1

0

0

1

0

0

1

None*

EP_BUF0

None*

EP_BUF1

EP_BUF0

EP_BUF1

EP_BUF1

EP_BUF0

* Means the USB device sends a NAK signal to the USB host using the hardware circuitry.

The UDBTG and MDBTG bits setting procedure for the double buffering function is shown in the following example:

[UDBTG, MDBTG] = [0, 0] → [0, 1] → [1, 1] → [1, 0] → [0, 0] → [0, 1] → [1, 1] → [1, 0]

→...

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[5]

[4]

Bits

[6]

[3]

[2]

[1]


MDBTG MCU Double Buffer Toggle bit

The MDBTG bit is used to indicate which data buffer is accessed by the MCU if the double buffering function is enabled. It can be toggled to switch to the other buffer by the MCU application software after the data in the current buffer accessed by the MCU has been properly setup. The double buffering operation together with the UDBTG and

MDBTG bits are shown in the preceding two tables for the UDBTG bit definition

STLRX STALL bit for reception transfers


This bit can be read and written and can only be toggled by writing 1. It can also be toggled by software to initialize its value under certain conditions.

NAKRX NAK bit for reception transfers

This bit is toggled from 0 to 1 by the hardware circuitry, which will result in a NAK signal in the handshake phase of an OUT transaction after an ACK signal has been transmitted. It means that the USB device will be temporarily unable to accept data from the USB host until the received data is properly processed. If the endpoint is defined as an Isochronous transfer type, this bit is not available for usage. The hardware will not change the NAKRX bit status after a complete transaction.


DTGRX Data Toggle bit for reception transfers

If the endpoint is not used for Isochronous transfer, this bit is available for usage. This bit contains the expected value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be received. When the current valid data packet is received and the corresponding ACK signal is sent to the USB host by the USB device, the hardware circuitry will toggle this bit and the device will be ready to receive the next data packet.

If the endpoint is defined as an Isochronous transfer type, this bit is not used since no data toggling is used and only the DATA0 packet will be transferred for normal

Isochronous transfers.

This bit can be read and written and can only be toggled by writing 1. This bit can also be toggled by the software to initialize its value under certain conditions.

STLTX STALL bit for transmission transfers

This bit is set to 1 by the application software if there a functional error has been detected.

This bit can be read and written and can be only toggled by writing 1. It can be toggled by the software to initialize its value under certain conditions.

NAKTX NAK bit for transmission transfers

This bit is toggled from 0 to 1 by the hardware circuitry, which will result in a NAK signal in the handshake phase of an IN transaction after an ACK signal has been received.

It means that the USB device will be temporarily unable to transmit a data packet until the data to be transmitted is properly setup by the application software. If the endpoint is defined as an Isochronous transfer type, then this bit is not available for usage. The hardware will not change the NAKTX bit status after a complete transaction.

This bit can be read and written and can be only toggled by writing 1. It can also be toggled by the software to initialize its value under certain conditions.

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Cortex ® -M0+ MCU

Bits

[0]


DTGTX Data Toggle bit for transmission transfers

If the endpoint is not used for Isochronous transfer, this bit is available for usage. This bit contains the required value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be transmitted. When the current data packet is transmitted by the

USB device and the corresponding ACK signal sent from the USB host is received, the hardware circuitry will toggle this bit and then the next data packet will be transmitted. If the endpoint is used for Isochronous transfer, this bit is not used since no data toggling is used and only the DATA0 packet will be transferred for normal Isochronous transfer.

This bit can be read and written and can only be toggled by writing 1. It can also be toggled by the software to initialize its value under certain conditions.

USB Endpoint 4 ~ 7 Interrupt Enable Register – USBEPnIER, n = 4 ~ 7

This register specifies the Endpoint 4 ~ 7 interrupt enable control bits.

Offset: 0x068 (n = 4), 0x07C (n = 5), 0x090 (n = 6), 0x0A4 (n = 7)


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

Reserved

10 9 8

Type/Reset

7

UERIE

6

STLIE

5

NAKIE

4

IDTXIE

3

ITRXIE

2

ODOVIE

1

ODRXIE

0

OTRXIE


Bits

[7]

[6]

[5]

[4]

[3]

Field

UERIE

STLIE

NAKIE

IDTXIE

ITRXIE

Descriptions



1: Enable interrupt



1: Enable interrupt



1: Enable interrupt



1: Enable interrupt



1: Enable interrupt

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Bits

[2]

[1]

[0]

Field

ODOVIE

ODRXIE

OTRXIE

Descriptions



1: Enable interrupt



1: Enable interrupt

OUT Token Received Interrupt Enable Control


1: Enable interrupt

USB Endpoint 4 ~ 7 Interrupt Status Register – USBEPnISR, n = 4 ~ 7

This register specifies the Endpoint 4 ~ 7 interrupt status.

Offset: 0x06C (n = 4), 0x080 (n = 5), 0x094 (n = 6), 0x0A8 (n = 7)


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

Reserved

10 9 8

Type/Reset

7

UERIF

6

STLIF

5

NAKIF

4

IDTXIF

3

ITRXIF

2

ODOVIF

1

ODRXIF

0

OTRXIF


Bits

[7]

[6]

[5]

[4]

[3]

Field

UERIF

STLIF

NAKIF

IDTXIF

ITRXIF

Descriptions

USB Error Interrupt flag

This bit is set by the hardware circuitry when an error occurs during the transaction.


STALL Transmitted Interrupt flag

This bit is set by the hardware circuitry when a STALL signal is sent in response to an IN or OUT token and is cleared to 0 by writing 1.

NAK Transmitted Interrupt flag

This bit is set by the hardware circuitry when an NAK signal is sent in response to an

IN or OUT token and is cleared to 0 by writing 1.

IN Data Transmitted Interrupt flag

This bit is set by the hardware circuitry when a data packet is successfully transmitted to the host in response to an IN token and an ACK signal is received.


IN Token Received Interrupt flag

This bit is set by the hardware circuitry when the endpoint receives an IN token from the host and is cleared to 0 by writing 1.

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Cortex ® -M0+ MCU

Bits

[2]

[1]

[0]

Field

ODOVIF

ODRXIF

OTRXIF

Descriptions

OUT Data Buffer Overrun Interrupt flag

This bit is set by the hardware circuitry when the received data byte count is larger than the endpoint OUT data buffer size.


OUT Data Received Interrupt flag

This bit is set by the hardware circuitry when a data packet is successfully received from the host for an OUT token and an ACK signal is sent to the host.


OUT Token Received Interrupt flag

This bit is set by the hardware circuitry when the endpoint receives an OUT token from the host and is cleared to 0 by writing 1.

USB Endpoint 4 ~ 7 Transfer Count Register – USBEPnTCR, n = 4 ~ 7

This register specifies the Endpoint 4 ~ 7 transfer byte count.

Offset: 0x070 (n = 4), 0x084 (n = 5), 0x098 (n = 6), 0x0AC (n = 7)


Type/Reset

31 30 29 28

Reserved

27 26 25 24

TCNT1

RW 0 RW 0

17 16

Type/Reset

23 22 21 20

Reserved

19

TCNT1

18


15 14 13 12 11 10 9 8

TCNT0

RW 0 RW 0

7 6 5 4 3

TCNT0

2 1 0


Bits

[25:16]

[9:0]

Field

TCNT1

TCNT0

Descriptions

Buffer 1 Transfer Byte Count

This bit field contains the number of data bytes received by the endpoint n buffer 1 in the preceding OUT transaction or the number of data bytes to be transmitted by the endpoint n buffer1 in the next IN transaction.

Buffer 0 Transfer Byte Count

This bit field contains the number of data bytes received by the endpoint n buffer 0 in the preceding OUT transaction or the number of data bytes to be transmitted by the endpoint n buffer 0 in the next IN transaction. Only the TCNT0 field is used for the endpoint data transfer count when the endpoint is configured as a single-buffering transfer type.

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USB Endpoint 4 ~ 7 Configuration Register – USBEPnCFGR, n = 4 ~ 7

This register specifies the Endpoint 4 ~ 7 configurations.

Offset: 0x074 (n = 4), 0x088 (n = 5), 0x09C (n = 6), 0x0B0 (n = 7)

Reset value: 0x1000_03FF

31

EPEN

Type/Reset RW 0

23

SDBS

Type/Reset RW 0

30 29

Reserved EPTYPE

28

EPDIR

27 26 25

EPADR

24


22 21

Reserved

20 19 18 17

EPLEN

16

RW 0 RW 0 RW 0 RW 0

15 14 13 12

EPLEN

11 10 9 8

EPBUFA


7 6 5 4 3 2 1 0

EPBUFA


Bits

[31]

[29]

[28]

[27:24]

[23]

[19:10]

[9:0]

Field

EPEN

EPTYPE

EPDIR

EPADR

SDBS

EPLEN

EPBUFA

Descriptions

Enable Control

0: Disable the endpoint n

1: Enable the endpoint n

Transfer Type

0: Interrupt or Bulk transfer type

1: Isochronous transfer type

Transfer Direction

0: OUT

1: IN

Endpoint Address

The EPADR field can be configured by the application software to specify the address of endpoint n. It is important to note that this EPADR field should not be set to 0; otherwise, the endpoint n will be disabled.

Single-Buffering or Double-Buffering Selection

0: Single-buffering

1: Double-buffering

If the SDBS bit is set to 1, the endpoint buffer size is twice that of the EPLEN value:

- Endpoint Buffer 0 start address is EPBUFA

- Endpoint Buffer 1 start address is (EPBUFA + EPLEN)

Buffer Length

This field is used to specify the endpoint n data packet size whose field value must be word-aligned to a 4-byte boundary. Note that the endpoint will be disabled if the

EPLEN value is assigned to 0.

Buffer Address

This field is used to specify the endpoint n data buffer start address which ranges from 0x008 to 0x3FC in the EP_SRAM which has a capacity of 1024 bytes where the endpoint transfer data is stored. Note that the buffer start address value must be a multiple of 4.

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13

Inter-Integrated Circuit (I

2

C)

Introduction

The I 2 C Module is an internal circuit allowing communication with an external I 2 C interface which is an industry standard two-line serial interface used for connection to external hardware. These two serial lines are known as a serial data line, SDA, and a serial clock line, SCL. The I 2 C module provides three data transfer rates: (1) 100 kHz in the Standard mode, (2) 400 kHz in the Fast mode and (3) 1MHz in the Fast mode plus. The SCL period generation registers are used to set different kinds of duty cycle implementation for the SCL pulse.

The SDA line which is connected to the whole I 2 C bus is a bidirectional data line between the master and slave devices used for the transmission and reception of data. The I 2 C module also has an arbitration detection function to prevent the situation where more than one master attempts to transmit data on the I 2 C bus at the same time.

APB Bus

Control Register Interrupts

Bit

Counter

SCL High/Low

Period

Generation

Target Register

SCL

Generator

Address/Data

SCL Out

Control

SCL Sync

SCL_out

SDA Out

Control SDA_out

Data Shift Register Sync SDA_in

SCL Edge

Detect Data Register

Address

Register

Status

Register

Address

Comparator

Arbitration

Bus Status

SCL_in

Figure 31. I 2 C Module Block Diagram

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Cortex ® -M0+ MCU

Features

▆

▆

▆

▆

▆

▆

▆

▆

▆

▆

Two-wire I 2 C serial interface

● Serial data line (SDA) and serial clock (SCL)

Multiple speed modes

● Standard mode – 100 kHz

● Fast mode – 400 kHz

● Fast mode plus – 1 MHz

Bidirectional data transfer between master and slave

Multi-master bus – no central master

● The same interface can act as Master or Slave

Arbitration among simultaneous transmitting masters without corrupting serial data on the bus

Clock synchronization

● Allow devices with different bit rates to communicate via one serial bus

Supports 7-bit and 10-bit addressing modes and general call addressing

Multiple slave addresses using address mask function

Timeout function

Supports PDMA Interface


Two-Wire Serial Interface

The I 2 C module has two external lines, the serial data SDA and serial clock SCL lines, to carry information between the interconnected devices connected to the bus. The SCL and SDA lines are both bidirectional and must be connected to a pull-high resistor. When the I connected devices.

2 C bus is in the free or idle state, both pins are at a high level to perform the required wired-AND function for multiple

START and STOP Conditions

A master device can initialize a transfer by sending a START signal and terminate the transfer with a STOP signal. A START signal is usually referred to as the “S” bit, which is defined as a High to

Low transition on the SDA line while the SCL line is high. A STOP signal is usually referred to as the “P” bit, which is defined as a Low to High transition on the SDA line while SCL is high.

A repeated START signal, which is denoted as the “Sr” bit, is functionally identical to the normal

START condition. A repeated START signal allows the I 2 C interface to communicate with another slave device or with the same device but in a different transfer direction without releasing the I 2 bus control.

C

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SDA

SDA

SCL

S

START Condition

Figure 32. START and STOP Condition

P

STOP Condition

SCL

Data Validity

The data on the SDA line must be stable during the high period of the SCL clock. The SDA data state can only be changed when the clock signal on the SCL line is in a low state.

SDA

SCL

Stable data line

Change of data allowed

Figure 33. Data Validity

Addressing Format

The I 2 C interface starts to transfer data after the master device has sent the address to confirm the targeted slave device. The address frame is sent just after the START signal by the master device.

The addressing mode selection bit named ADRM in the I2CCR register should be defined to choose either the 7-bit or 10-bit addressing mode.

7-bit Address Format

The 7-bit address format is composed of the 7-bit length slave address, which the master device wants to communicate with, a R/W bit and an ACK bit. The R/W bit defines the direction of the data transfer.

R/W = 0 (Write): The master transmits data to the addressed slave.

R/W = 1 (Read): The master receives data from the addressed slave.

The slave address can be assigned through the ADDR field in the I2CADDR register. The slave device sends back the acknowledge bit (ACK) if its slave address matches the transmitted address sent by the master.

Note that it is forbidden to own the same address for two slave devices.

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Sent by master

S

MSB

A6 A5 A4 A3 A2 A1

LSB

A0 R/W ACK

S = START condition

R/W = 1: Read direction

= 0: Write direction

ACK = Acknowledge bit

Slave address

Figure 34. 7-bit Addressing Mode

Sent by slave

10-bit Address Format

In order to prevent address clashes, due to the limited range of the 7-bit addresses, a new 10-bit address scheme has been introduced. This enhancement can be mixed with the 7-bit addressing mode which increases the available address range about ten times. For the 10-bit addressing mode, the first two bytes after a START signal include a header byte and an address byte that usually determines which slave will be selected by the master. The header byte is composed of a leading

“11110”, the 10 th and 9 slave device address.

th bits of the slave address. The second byte is the remaining 8 bits of the

S 1 1 1 1 0

MSB

A

9

A

8

W A ck

A

7

A

6

A

5

A

4

A

3

A

2

A

1

LSB

A

0

A ck

S = START condition

W = Write command

A ck

A

9

= Acknowledge

~ A

0

= 10-bit Address

Figure 35. 10-bit Addressing Write Transmit Mode

Data

S 1 1 1 1 0

MSB

A

9

A

8

W A

CK

A

7

A

6

A

5

S = START condition

Sr = Repeated-START condition

W = Write command

R = Read command

A

CK

A

9

= Acknowledge

~ A

0

= 10-bit Address

A

4

A

3

A

2

A

1

LSB

A

0

A

CK

Sr 1

Figure 36. 10-bits Addressing Read Receive Mode

1 1 1 0 A

9

A

8

R A

CK

Data

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Data Transfer and Acknowledge

Once the slave device address has been matched, the data can be transmitted to or received from the slave device according to the transfer direction specified by the R/W bit. Each byte is followed by an acknowledge bit on the 9 th SCL clock.

If the slave device returns a Not-Acknowledge (NACK) signal to the master device, the master device can generate a STOP signal to terminate the data transfer or generate a repeated START signal to restart the transfer.

If the master device sends a Not-Acknowledge (NACK) signal to the slave device, the slave device should release the SDA line for the master device to generate a STOP signal to terminate the transfer.

Data Frame

Acknowledge bit

SCL from

Master

Data output by

Transmitter

Data output by Receiver

Figure 37. I 2 C Bus Acknowledge

1 2 8

Not acknowledge acknowledge

9

Clock Synchronization

Only one master device can generate the SCL clock under normal operation. However when there is more than one master trying to generate the SCL clock, the clock should be synchronized so that the data output can be compared. Clock synchronization is performed using the wired-AND connection of the I 2 C interface to the SCL line.

Wait state

Start High period

SCL from device 1

SCL from device 2

I 2

SCL on

C BUS

Figure 38. Clock Synchronization during Arbitration

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Arbitration

A master may start a transfer only if the I 2 C bus line is in the free or idle mode. If two or more masters generate a START signal at approximately the same time, an arbitration procedure will occur.

Arbitration takes place on the SDA line and can continue for many bits. The arbitration procedure gives a higher priority to the device that transmits serial data with a binary low bit (logic low).

Other master devices which want to transmit binary high bits (logic high) will lose the arbitration.

As soon as a master loses the arbitration, the I 2 C module will set the ARBLOS bit in the I2CSR register and generate an interrupt if the interrupt enable bit, ARBLOSIE, in the I2CIER register is set to 1. Meanwhile, it stops sending data and listens to the bus in order to detect an I 2 C stop signal.

When the stop signal is detected, the master which has lost the arbitration may try to access the bus again.

SCL

Data from device 1

Data from device 2

1

1

0

0

SDA line

1

Figure 39. Two Masters Arbitration Procedure

0

1

Device 1 loses arbitration

0 1

0 1

1

1

General Call Addressing

The general call addressing function can be used to address all the devices connected to the I 2 C bus. The master device can activate the general call function by configuring the TAR field value to zero field and clearing the RWD bit to 0 in the I2CTAR register on the addressing frame.

The device can support the general call addressing function by setting the corresponding enable control bit GCEN to 1. If the GCEN bit is set to 1 to support the general call addressing, the AA bit in the I2CCR register should also be set to 1 to send an acknowledge signal back when the device receives an address frame with a value of 00H. When this condition occurs, the general call flag,

GCS, will be set to 1, but the ADRS flag will not be set.

Bus Error

If an unpredictable START or STOP condition occurs when the data is being transferred on the I 2 C bus, it will be considered as a bus error and the transferring data will be aborted. When a bus error event occurs, the relevant bus error flag BUSERR in the I2CSR register will set to 1 and both the

SDA and SCL lines are released. The BUSERR flag should be cleared by writing a 1 to it to initiate the I 2 C module to an idle state.

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Address Mask Enable

The I 2 C module provides an address mask function for users to decide which address bit can be ignored during the comparison with the address frame sent from the master. The ADRS flag will be asserted when the unmasked address bits and the address frame sent from the master are matched.

Note that this function is only available in the slave mode.

For instance, the user sets a data transfer with the 7-bit addressing mode together with the

I2CADDMR register value as 0x05 and the I2CADDR register value as 0x55, this means if an address which is sent by an I 2 C master on the bus is equal to 0x50, 0x51, 0x54 or 0x55, the I asserted after the address frame.

2 C slave address will all be considered to be matched and the ADRS flag in the I2CSR register will be

Address Snoop

The Address Snoop register, I2CADDSR, is used to monitor the calling address on the I 2 C bus during the whole data transfer operation no matter if the I 2 C module operates as a master or a slave device. Note that the I2CADDSR register is a read only register and each calling address on the I 2 C bus will be stored in the I2CADDSR register automatically even if the I 2 C device is not addressed.

Operation Mode

The I 2 C module can operate in the following modes:

▆

▆

▆

▆

Master Transmitter

Master Receiver

Slave Transmitter

Slave Receiver

The I 2 C module operates in the slave mode by default. The interface will switch to the master mode automatically after generating a START signal.

Master Transmitter Mode

Start Condition

Users write the target slave device address and communication direction into the I2CTAR register after setting the I2CEN bit in the I2CCR register. The STA flag in the I2CSR register is set by hardware after a start condition occurs. In order to send the following address frame, the STA flag must be cleared to 0 if it has been set to 1. The STA flag is cleared by reading the I2CSR register.

Address Frame

The ADRS flag in the I2CSR register will be set after the address frame is sent by the master device and the acknowledge signal from the address matched slave device is received. In order to send the following data frame, the ADRS flag must be cleared to 0 if it has been set to 1. The

ADRS bit is cleared by reading the I2CSR register.

Data Frame

The data to be transmitted to the slave device must be transferred to the I2CDR register.

The TXDE bit in the I2CSR register is set to indicate that the I2CDR register is empty, which results in the SCL line being held at a logic low state. New data must then be transferred to the

I2CDR register to continue the data transfer process. Writing a data into the I2CDR register will clear the TXDE flag.

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Close / Continue Transmission

After transmitting the last data byte, the STOP bit in the I2CCR register can be set to terminate the transmission or re-assign another slave device by configuring the I2CTAR register to restart a new transfer.

7-bit Master Transmitter

S Address A

STA

BEH1

ADRS TXDE

BEH1 BEH2

Data1 A

TXDE

BEH2

Data2 A

TXDE

BEH2

...

DataN A

TXDE

BEH3

P

10-bit Master Transmitter

S Header A

STA

BEH1

Address A

ADRS TXDE

BEH1 BEH2

Data1 A

TXDE

BEH2

Data2 A

TXDE

BEH2

...

DataN A

TXDE

BEH3

P

BEH1 : cleared by reading I2CSR register

BEH2 : cleared by writing I2CDR register

BEH3 : cleared by HW automatically by sending STOP condition

Figure 40. Master Transmitter Timing Diagram

Master Receiver Mode

Start Condition

The target slave device address and communication direction must be written into the I2CTAR register. The STA flag in the I2CSR register is set by hardware after a start condition occurs. In order to send the following address frame, the STA flag must be cleared to 0 if it has been set to 1.The

STA flag is cleared by reading the I2CSR register.

Address Frame

In the 7-bit addressing mode: The ADRS flag is set after the address frame is sent by the master device and the acknowledge signal from the address matched slave device is received. In order to receive the following data frame, the ADRS bit must be cleared to 0 if it has been set to 1. The

ADRS bit is cleared after reading the I2CSR register.

In the 10-bit addressing mode: The ADRS bit in the I2CSR register will be set twice in the 10-bit addressing mode. The first time the ADRS bit is set is when the first header byte and the second address byte are sent and the acknowledge signals from the slave device are received. The second time the ADRS bit is set is when the second header byte is sent and the slave acknowledge signal is received. In order to receive the following data frame, the ADRS bit must be cleared to 0 if it has been set to 1. The ADRS bit is cleared after reading the I2CSR register. The detailed master receiver mode timing diagram is shown in the following figure.

Data Frame

In the master receiver mode, data is transmitted from the slave device. Once a data is received by the master device, the RXDNE flag in the I2CSR register is set but it will not hold the SCL line.

However, if the device receives a complete new data byte and the RXDNE flag has already been set

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Close / Continue Transmission

The master device needs to reset the AA bit in the I2CCR register to send an NACK signal to the slave device before the last data byte transfer has been completed. After the last data byte has been received from the slave device, the master device will hold the SCL line at a logic low state following an NACK signal sent by the master device to the slave device. The STOP bit can be set to terminate the data transfer process or re-assign the I2CTAR register to restart a new transfer.

7-bit Master Receiver

S Address A

STA

BEH1

ADRS

BEH1

Data1 A

RXDNE

BEH2

Data2 A

RXDNE

BEH2

...

RXDNE

BEH3

DataN NA

RXDNE

BEH4

P

10-bit Master Receiver

S Header

STA

BEH1

A Address A

ADRS #1

BEH1

Sr Header A Data1 A

STA

BEH1

ADRS #2

BEH1

RXDNE

BEH2


BEH2 : cleared by reading I2CDR register

BEH3 : cleared by reading I2CDR register, set AA=0 to send NACK signal

BEH4 : cleared by reading I2CDR register, set STOP=1 to send STOP signal

Data2 A

RXDNE

BEH2

...

RXDNE

BEH3

DataN NA

RXDNE

BEH4

P

Figure 41. Master Receiver Timing Diagram

Slave Transmitter Mode

Address Frame

In the 7-bit addressing mode, the ADRS bit in the I2CSR register is set after the slave device receives the calling address which matches with the slave device address. In the 10-bit addressing mode, the ADRS bit is set for the first time when the first header byte and the second address byte are both matched. Not that when the second header byte is also matched, the ADRS bit will be set again. After the ADRS bit has been set to 1, it must be cleared to 0 to continue the data transfer process. The ADRS bit is cleared after reading the I2CSR register.

Data Frame

In the Slave transmitter mode, the TXDE bit is set to indicate that the I2CDR is empty, which results in the SCL line being held at a logic low state. New transmission data must then be written into the I2CDR register to continue the data transfer process. Writing a data into the I2CDR register will clear the TXDE bit.

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Receive Not-Acknowledge

When the slave device receives a Not-Acknowledge signal, the RXNACK bit in the I2CSR Register is set but it will not hold the SCL line. Writing “1” to RXNACK will clear the RXNACK flag.

STOP Condition

When the slave device detects a STOP condition, the STO bit in the I2CSR register is set to indicate that the I flag.

2 C interface transmission is terminated. Reading the I2CSR register can clear the STO

7-bit Slave Transmitter

S Address A

ADRS

BEH1

TXDE

BEH2

Data1 A

TXDE

BEH2

Data2 A

TXDE

BEH2

...

DataN NA

RXNACK

BEH3

P

STO

BEH4

10-bit Slave Transmitter

S Header A Address A

ADRS #1

BEH1

Sr Header A

ADRS #2

BEH1

TXDE

BEH2

Data1 A

TXDE

BEH2

Data2 A

TXDE

BEH2


BEH2 : cleared by writing I2CDR register

BEH3 : cleared by writing 1 clear for RXNACK flag, TXDE is not set when NACK is received.


Figure 42. Slave Transmitter Timing Diagram

...

DataN NA

RXNACK

BEH3

P

STO

BEH4

Slave Receiver Mode

Address Frame

The ADRS bit in the I2CSR register is set after the slave device receives the calling address which matches with the slave device address. After the ADRS bit has been set to 1, it must be cleared to 0 to continue the data transfer process. The ADRS flag is cleared after reading the I2CSR register.

Data Frame

In the slave receiver mode, the data is transmitted from the master device. Once a data byte is received by the slave device, the RXDNE flag in the I2CSR register is set but it will not hold the

SCL line. However, if the device receives a complete new data byte and the RXDNE bit has been set to 1, the RXBF bit in the I2CSR register will be set to 1 and the SCL line will be held at a logic low state. When this situation occurs, data from the I2CDR register should be read to continue the data transfer process. The RXDNE flag bit can be cleared after reading the I2CDR register.

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STOP Condition

When the slave device detects a STOP condition, the STO flag bit in the I2CSR register is set to indicate that the I

STO flag bit.

2 C interface transmission is terminated. Reading the I2CSR register can clear the

7-bit Slave Receiver

S Address A

ADRS

BEH1

Data1 A

RXDNE

BEH2

Data2 A

RXDNE

BEH2

...

DataN A

RXDNE

BEH2

P

STO

BEH3

10-bit Slave Receiver

S Header A Address A Data1 A

ADRS

BEH1


BEH2 : cleared by reading I2CDR register


Figure 43. Slave Receiver Timing Diagram

RXDNE

BEH2

Data2 A

RXDNE

BEH2

...

DataN A

RXDNE

BEH2

P

STO

BEH3

Conditions of Holding SCL Line

The following conditions will cause the SCL line to be held at a logic low state by hardware resulting in all the I 2 C transfers being stopped. Data transfer will be continued after the creating conditions are eliminated.

Table 33. Conditions of Holding SCL line

Type Condition

TXDE

Description

I 2 C is used in transmitter mode and I2CDR register needs to have data to transmit.

(Note: TXDE won’t be asserted after receiving an NACK)

Eliminating Condition

Master case:

Writing data to I2CDR register

Set TAR

Set STOP

Slave case:

Writing data to I2CDR register

Flag

GCS

ADRS

STA

RXBF

I 2 C is addressed as slave through general call Reading I2CSR register

Master:

I 2 C address frame is sent and an ACK from slave is returned

(Note: Reference Figure 40 and Figure 41)

Reading I2CSR register

I

Slave:

2 C is addressed as slave device

(Note: Reference Figure 42 and Figure 43)

Master sends a START signal

Received a complete new data and meanwhile the RXDNE flag has been set already before.

Reading I2CSR register

Reading I2CDR register

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Type

Event

Condition

Master receives NACK

Description

No matter in address or data frame, once received an NACK signal will hold SCL line in master mode.

Eliminating Condition

Set TAR

Set STOP

Master sends NACK used in receiver mode

Occurred when receiving the last data byte in

Master receiver mode

(Note: Reference Figure 41, and RXNACK flag won’t be asserted in this case)

Set TAR

Set STOP

I

2

C Timeout Function

In order to reduce the occurrence of I 2 C lockup problem due to the reception of erroneous clock source, a timeout function is provided. If the I 2 C bus clock source is not received for a certain timeout period, then a corresponding I 2 C timeout flag will be asserted. This timeout period is determined by a 16-bit down-counting counter with a programmable preload value. The timeout counter is driven by the I 2 C timeout clock, f

I2CTO

, which is specified by the timeout prescaler field in the I2CTOUT register. The TOUT field in the I2CTOUT register is used to define the timeout counter preload value. The timeout function is enabled by setting the ENTOUT bit in the I2CCR register. The timeout counter will start to count down from the preloaded value if the ENTOUT bit is set to 1 and one of the following conditions occurs:

▆

▆

▆

The I 2 C master module sends a START signal.

The I 2 C slave module detects a START signal.

The RXBF, TXDE, RXDNE, RXNACK, GCS or ADRS flag is asserted.

The timeout counter will stop counting when the ENTOUT bit is cleared. However, the counter will also stop counting when one of the conditions listed as follows occurs:

▆

▆

▆

▆

The I 2 C slave module is not addressed.

The I 2 C slave module detects a STOP signal.

The I 2 C master module sends a STOP signal.

The ARBLOS or BUSERR flag in the I2CSR register is asserted.

If the timeout counter underflows, the corresponding timeout flag, TOUTF, in the I2CSR register will be set to 1 and a timeout interrupt will be generated if the relevant interrupt is enabled.

PDMA Interface

The PDMA interface is integrated in the I 2 C module. The PDMA function can be enabled by setting the TXDMAE or RXDMAE bit to 1 in the transmitter or receiver mode respectively. When the data register is empty in the transmitter mode and the TXDMAE bit is set to 1, the PMDA function will be activated to move data from a certain memory location into the I 2 C data register.

Similarly, when the data register is not empty in the receiver mode and the RXDMAE bit is set to

1, the PDMA function will also be activated to move data from the I 2 C data register to a specific memory location.

The DMA NACK control bit, DMANACK, is used to determine whether the NACK signal is sent or not when the I 2 C module operates in the master receiver mode and the PDMA function is enabled. If the DMANACK bit is set to 1 and the data has all been received and moved using the

PDMA interface, an NACK signal will automatically be sent out to properly terminate the data transfer.

For a more detailed description about the PDMA configurations, refer to the PDMA chapter.

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Register Map

The following table shows the I 2 C registers and reset values.

Table 34. I 2 C Register Map

Register Offset

I2CCR

I2CIER

I2CADDR

0x000

0x004

0x008

Description

I 2 C Control Register

I 2 C Interrupt Enable Register

I 2 C Address Register

I2CSR 0x00C

I2CSHPGR 0x010

I2CSLPGR 0x014

I2CDR

I2CTAR

0x018

0x01C

I2CADDMR 0x020

I2CADDSR 0x024

I2CTOUT 0x028

I 2 C Status Register

I 2 C SCL High Period Generation Register

I 2 C SCL Low Period Generation Register

I 2 C Data Register

I 2 C Target Register

I 2 C Address Mask Register

I 2 C Address Snoop Register

I 2 C Timeout Register


I

2

C Control Register – I2CCR

This register specifies the corresponding I 2 C function enable control

Offset: 0x000


Reset Value

0x0000_2000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15


7 6 5 4

ADRM

Type/Reset RW 0

14 13 12 11 10 9 8

SEQFILTER COMBFILTEREN ENTOUT Reserved DMANACK RXDMAE TXDMAE

Reserved

3

I2CEN

RW 0 RW 0 RW 0

2

GCEN

1

STOP

0

AA

RW 0 RW 0 RW 0 RW 0

Bits

[15:14]

[13]

Field

SEQFILTER

Descriptions

SDA or SCL Input Sequential Filter Configuration Bits

00: Sequential filter is disabled

01: 1 PCLK glitch filter

1x: 2 PCLK glitch filter

Note: This setting would affect the frequency of SCL. Details are described in

I2CSLPGR register.

COMBFILTEREN SDA or SCL Input Combinational Filter Enable Bit

0: Combinational filter is disabled

1: Combinational filter is enabled

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[3]

[2]

[10]

[9]

Bits

[12]

[8]

[7]

[1]

[0]

Field

ENTOUT

DMANACK

RXDMAE

TXDMAE

ADRM

I2CEN

GCEN

STOP

AA

Descriptions

I 2 C Timeout Function Enable Control

0: Timeout Function is disabled

1: Timeout Function is enabled

This bit is used to enable or disable the I 2 C timeout function. It is recommended that users have to properly configure the PSC and TOUT fields in the I2CTOUT register before the timeout counter starts to count by setting the ENOUT bit to 1.

DMA Mode NACK Control

0: No operation

1: The I 2 C master receiver module sends an NACK signal automatically after receiving the last byte from the slave transmitter in the DMA mode

DMA Mode RX Request Enable Control

0: RX DMA request is disabled

1: RX DMA request is enabled

If the data register is not empty in the receiver mode and the RXDMAE bit is set to 1, the relevant PDMA channel will be activated to move the data from the data register to a specific location which is defined in the corresponding PDMA register.

DMA Mode TX Request Enable Control

0: TX DMA request is disabled

1: TX DMA request is enabled

If the data register is empty in the transmitter mode and the TXDMAE bit is set to 1, the relevant PDMA channel will be activated to move the data from a specific location defined in the related PDMA register to the data register.

Addressing Mode

0: 7-bit addressing mode

1: 10-bit addressing mode

When the I 2 C master/slave module operates in the 7-bit addressing mode, it can only send out and respond to a 7-bit address and vice versa.

I 2 C Interface Enable

0: I

1: I 2

2 C interface is disabled

C interface is enabled

General Call Enable

0: General call is disabled

1: General call is enabled

When the device receives the calling address with a value of 0x00 and if both the GCEN and the AA bits are set to 1, then the I 2 C interface is addressed as a slave and the GCS bit in the I2CSR register is set to 1.

STOP Condition Control

0: No action

1: Send a STOP condition in master mode

This bit is set to 1 by software to generate a STOP condition and automatically cleared to 0 by hardware. The STOP bit is only available for the master device.

Acknowledge Bit

0: Send a Not-Acknowledge (NACK) signal after a byte is received

1: Send an Acknowledge (ACK) signal after a byte is received

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I

2

C Interrupt Enable Register – I2CIER

This register specifies the corresponding I 2 C interrupt enable bits.

Offset: 0x004


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

Reserved

13

Reserved

5

Reserved

20

12

4

27

Reserved

26 25 24

19 18

RXBFIE

17

TXDEIE

16

RXDNEIE

RW 0 RW 0 RW 0

11 10 9 8

TOUTIE BUSERRIE RXNACKIE ARBLOSIE

RW 0 RW 0 RW 0 RW 0

3 2 1 0

GCSIE ADRSIE STOIE STAIE

RW 0 RW 0 RW 0 RW 0

Bits

[18]

[17]

[16]

[11]

[10]

[9]

[8]

[3]

[2]


RXBFIE

TXDEIE

RX Buffer Full Interrupt Enable Bit

0: Interrupt is disabled

1: Interrupt is enabled

Data Register Empty Interrupt Enable Bit in Transmitter Mode



RXDNEIE Data Register Not Empty Interrupt Enable Bit in Received Mode



TOUTIE Timeout Interrupt Enable Bit



BUSERRIE Bus Error Interrupt Enable Bit



RXNACKIE Received Not-Acknowledge Interrupt Enable Bit



ARBLOSIE Arbitration Loss Interrupt Enable Bit in the I 2 C multi-master mode



GCSIE

ADRSIE

General Call Slave Interrupt Enable Bit



Slave Address Match Interrupt Enable Bit



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Bits

[1]

[0]

Field

STOIE

STAIE

Descriptions

STOP Condition Detected Interrupt Enable Bit



The bit is used for the I 2 C slave mode only.

START Condition Transmit Interrupt Enable Bit



The bit is used for the I 2 C master mode only.

I

2

C Address Register – I2CADDR

This register specifies the I 2 C device address.

Offset: 0x008


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

15 14 13 12

Reserved

11 10 9 8

ADDR

RW 0 RW 0

7 6 5 4 3

ADDR

2 1 0


Bits

[9:0]

Field

ADDR

Descriptions

Device Address

The register indicates the I

2

2 C device address. When the I

C master device.

2 C device is used in the

7-bit addressing mode, only the ADDR[6:0] bits will be compared with the received address sent from the I

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I

2

C Status Register – I2CSR

This register contains the I 2 C operation status.

Offset: 0x00C


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30 29 28 27

Reserved

26 25 24

22 21 20 19 18

Reserved TXNRX MASTER BUSBUSY RXBF

17

TXDE

16

RXDNE


14

6

13

Reserved

5

Reserved

12

4

11

TOUTF

10 9

BUSERR RXNACK

8

ARBLOS

WC 0 WC 0 WC 0 WC 0

3 2 1 0

GCS ADRS STO STA

RC 0 RC 0 RC 0 RC 0

Bits

[21]

[20]

[19]

[18]

Field

TXNRX

Descriptions

Transmitter / Receiver Mode

0: Receiver mode

1: Transmitter mode

Read only bit.

MASTER Master Mode

0: I 2 C is in the slave mode or idle

1: I

The I 2

2 C is in the master mode

C interface is switched as a master device on the I 2 C bus when the I2CTAR register is assigned and the I when software disables the I

2 C bus is idle. The MASTER bit is cleared by hardware

2 C bus by clearing the I2CEN bit to 0 or sends a STOP condition to the I 2 C bus or the bus error is detected. This bit is set and cleared by hardware and is a read only bit.

BUSBUSY Bus Busy

0: I 2 C bus is idle

1: I

The I 2

2 C bus is busy

C interface hardware starts to detect the I 2 C bus status if the interface is enabled by setting the I2CEN bit to 1. It is set to 1 when the SDA or SCL signal is detected to have a logic low state and cleared when a STOP condition is detected.

RXBF Buffer Full Flag in Receiver Mode

0: Data buffer is not full

1: Data buffer is full

This bit is set when the data register I2CDR has already stored a data byte and meanwhile the data shift register also has been received a complete new data byte.

The RXBF bit is cleared by software reading the I2CDR register.

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[11]

[10]

Bits

[17]

[16]

[9]

[8]

[3]

Field

TXDE

RXDNE

TOUTF

BUSERR

RXNACK

ARBLOS

GCS

Descriptions

Data Register Empty in Transmitter Mode

0: Data register I2CDR is not empty

1: Data register I2CDR is empty

This bit is set when the I2CDR register is empty in the Transmitter mode. Note that the TXDE bit will be set after the address frame is being transmitted to inform that the data to be transmitted should be loaded into the I2CDR register. The TXDE bit is cleared by software writing data to the I2CDR register in both the master and slave mode or cleared automatically by hardware after setting the STOP signal to terminate the data transfer or setting the I2CTAR register to restart a new data transfer in the master mode.

Data Register Not Empty in Receiver Mode

0: Data register I2CDR is empty

1: Data register I2CDR is not empty

This bit is set when the I2CDR register is not empty in the receiver mode. The

RXDNE bit is cleared by software reading the data byte from the I2CDR register.

Timeout Counter Underflow Flag

0: No timeout counter underflow has occurred

1: Timeout counter underflow has occurred

Writing “1” to this bit will clear the TOUTF flag.

Bus Error Flag

0: No bus error has occurred

1: Bus error has occurred

This bit is set by hardware when the I 2 C interface detects a misplaced START or

STOP condition in a transfer process. Writing a “1” to this bit will clear the BUSERR flag.

In Master Mode: Once the Bus Error event occurs, both the SDA and SCL lines are released by hardware and the BUSERR flag is asserted. The application software has to clear the BUSERR flag before the next address byte is transmitted.

In Slave Mode: Once a misplaced START or STOP condition has been detected by the slave device, the software must clear the BUSERR flag before the next address byte is received.

Received Not-Acknowledge Flag

0: Acknowledge is returned from receiver

1: Not-Acknowledge is returned from receiver

The RXNACK bit indicates that the Not-Acknowledge signal is received in master or slave transmitter mode. Writing “1” to this bit will clear the RXNACK flag.

Arbitration Loss Flag

0: No arbitration loss is detected

1: Bit arbitration loss is detected

This bit is set by hardware on the current clock which the I 2 C interface loses the bus arbitration to another master during the address or data frame transmission. Writing

“1” to this bit will clear the ARBLOS flag. Once the ARBLOS flag is asserted by hardware, the ARBLOS flag must be cleared before the next transmission.

General Call Slave Flag

0: No general call slave occurs

1: I 2 C interface is addressed by a general call command

When the I 2 C interface receives an address with a value of 0x00 or 0x000 in the

7-bit or 10-bit addressing mode, if both the GCEN and the AA bit are set to 1, then it is switched as a general call slave. This flag is cleared automatically after being read.

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Bits

[2]

[1]

[0]

Field

ADRS

STO

STA

Descriptions

Address Transmit (master mode) / Address Receive (slave mode) Flag

Address Sent in Master Mode:

0: Address frame has not been transmitted

1: Address frame has been transmitted

For the 7-bit addressing mode, this bit is set after the master device receives the address frame acknowledge bit sent from the slave device. For the 10-bit addressing mode, this bit is set after receiving the acknowledge bits of the first header byte and the second address. Note that when the second header byte, if exists, is acknowledged, this bit will also be set.

Address Matched in Slave Mode:

0: I

1: I

2

2

C interface is not addressed

C interface is addressed as slave

When the I 2 C interface has received the calling address that matches the address defined in the I2CADDR register together with the AA bit being set to

1 in the I2CCR register, it will be switched to a slave mode. This flag is cleared automatically after the I2CSR register has been read.

STOP Condition Detected Flag

0: No STOP condition is detected

1: STOP condition is detected in slave mode

This bit is only available for the slave mode and is cleared automatically after the

I2CSR register is read.

START Condition Transmit

0: No START condition is detected

1: START condition is transmitted in master mode

This bit is only available for the master mode and is cleared automatically after the

I2CSR register is read.

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I

2

C SCL High Period Generation Register – I2CSHPGR

This register specifies the I 2 C SCL clock high period interval.

Offset: 0x010


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

SHPG

10 9 8


7 6 5 4 3 2 1 0

SHPG


Bits

[15:0]

Field

SHPG

Descriptions

SCL Clock High Period Generation

High period duration setting SCL

HIGH

= T

PCLK

× (SHPG + d) where T

PCLK

is the

APB bus peripheral clock (PCLK) period, and d value depends on the setting of

SEQFILTER in the I 2 C Control Register (I2CCR).

If SEQFILTER = 00, d = 6


If SEQFILTER = 10 or 11, d = 9

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I

2

C SCL Low Period Generation Register – I2CSLPGR

This register specifies the I 2 C SCL clock low period interval.

Offset: 0x014


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

SLPG

10 9 8


7 6 5 4 3 2 1 0

SLPG


Bits

[15:0]

Field

SLPG

Descriptions

SCL Clock Low Period Generation

Low period duration setting SCL

LOW

= T

PCLK

× (SLPG + d) where TPCLK is the

APB bus peripheral clock (PCLK) period, and d value depends on the setting of

SEQFILTER in the I 2 C Control Register (I2CCR).



If SEQFILTER = 10 or 11, d = 9

High period duration

T

PCLK

× (SHPG + d) High period duration

SCL

Low period duration

T

PCLK

× (SLPG + d)

Low period duration

Figure 44. SCL Timing Diagram

Table 35. I 2 C Clock Setting Example

I 2 C Clock

100 kHz (Standard Mode)

T

SCL

= T

PCLK

× [ (SHPG + d) + (SLPG + d) ] (where d = 6)

SHPG + SLPG Value at PCLK

8 MHz 20 MHz 24 MHz 40 MHz 48 MHz 60 MHz

68 188 228 388 468 588

400 kHz (Fast Mode)

1 MHz (Fast Mode Plus)

8

N/A

38

8

48

12

88

28

108

36

138

48

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I

2

C Data Register – I2CDR

This register specifies the data to be transmitted or received by the I 2 C module.

Offset: 0x018


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

Reserved

10 9 8

Type/Reset

7 6 5 4 3

DATA

2 1 0


Bits

[7:0]

Field

DATA

Descriptions

I 2 C Data Register

For the transmitter mode, a data byte which is transmitted to a slave device can be assigned to these bits. The TXDE flag is cleared if the application software assigns new data to the I2CDR register. For the receiver mode, a data byte is received bit by bit from MSB to LSB through the I 2 C interface and stored in the data shift register.

Once the acknowledge bit is given, the data shift register value is delivered into the

I2CDR register if the RXDNE flag is equal to 0.

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I

2

C Target Register – I2CTAR

This register specifies the target device address to be communicated.

Offset: 0x01C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

15

7

14

6

13

Reserved

5

12

4

11

3

TAR

10

RWD

2

9

1

8

TAR

RW 0 RW 0 RW 0

0


Bits

[10]

[9:0]

Field

RWD

TAR

Descriptions

Read or Write Direction

0: Write direction to target slave address

1: Read direction from target slave address

If this bit is set to 1 in the 10-bit master receiver mode, the I 2 C interface will initiate a byte with a value of 11110XX0b in the first header frame and then continue to deliver a byte with a value of 11110XX1b in the second header frame by hardware automatically.

Target Slave Address

The I 2 C interface will assign a START signal and send a target slave address automatically once the data is written to this register. When the system wants to send a repeated START signal to the I 2 C bus, it is suggested to set the I2CTAR register after a byte transfer is completed. It is not allowed to set TAR in the address frame. I2CTAR[9:7] is not available under the 7-bit addressing mode.

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I

2

C Address Mask Register – I2CADDMR

This register specifies which bit of the I 2 received address frame.

C address is masked and not compared with corresponding bit of the

Offset: 0x020


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

15

7

14

6

13

5

12

Reserved

4

11

3

ADDMR

10

2

9

1

8

ADDMR

RW 0 RW 0

0


Bits

[9:0]

Field

ADDMR

Descriptions

I

Address Mask Control Bit

The ADDMR[i] is used to specify whether the i th bit of the ADDR field in the I2CADDR register is masked and is compared with the received address frame or not on the

2 C bus. The register is only used for the I 2 C slave mode only.

0: i

1: i th th

bit of the ADDR is compared with the address frame on the I 2 C bus.

bit of the ADDR is masked and not compared with the address frame on the

I 2 C bus.

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I

2

C Address Snoop Register – I2CADDSR

This register is used to indicate the address frame value appeared on the I 2 C bus.

Offset: 0x024


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

15

7

14

6

13

5

12

Reserved

4

11

3

ADDSR

10

2

9

1

8

ADDSR

RO 0 RO 0

0


Bits

[9:0]

Field

ADDSR

Descriptions

Address Snoop

Once the I2CEN bit is enabled, the calling address value on the I automatically be loaded into this ADDSR field.

2 C bus will

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I

2

C Timeout Register – I2CTOUT

This register specifies the I 2 C timeout counter preload value and clock prescaler ratio.

Offset: 0x028


31 30 29 28 27

Reserved

26 25 24

Type/Reset

Type/Reset

23 22 21

Reserved

20 19 18 17

PSC

16

RW 0 RW 0 RW 0

15 14 13 12 11

TOUT

10 9 8


7 6 5 4 3 2 1 0

TOUT


Bits

[18:16]

[15:0]

Field

PSC

TOUT

Descriptions

I 2 C Timeout Counter Prescaler Selection

This PSC field is used to specify the I 2 C timeout counter clock frequency, f

I2CTO

. The timeout clock frequency is obtained using the following formula.

f

I2CTO

= f PCLK

2 PSC

PSC = 0 → f

PSC = 1 → f

PSC = 2 → f

…

PSC = 7 → f

I2CTO

I2CTO

= f

I2CTO

= f

= f

PCLK

PCLK

/ 2

PCLK

/ 2

/ 2

0 = f

1 = f

PCLK

PCLK

/ 2

2 = f

PCLK

/ 4

I2CTO

= f

PCLK

/ 2 7 = f

PCLK

/ 128

I 2 C Timeout Counter Preload Value

The TOUT field is used to define the counter preloaded value.

The counter value is reloaded as any one of the following conditions occurs:

1. The RXBF, TXDE, RXDNE, RXNACK, GCS or ADRS flag in the I2CSR register is asserted.

2. The I 2 C master module sends a START signal.

3. The I 2 C slave module detects a START signal.

The counter stops counting as any one of the following conditions occurs:

1. The I 2

2. The I

3. The I

2

2

C slave device is not addressed.

C master module sends a STOP signal.

C slave module detects a STOP signal.

4. The ARBLOS or BUSERR flag in the I2CSR register is asserted.

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14

Serial Peripheral Interface (SPI)

Introduction

The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive functions in both master or slave mode. The SPI interface uses 4 pins, among which are the serial data input and output lines SPI_MISO and SPI_MOSI, the clock line SPI_SCK, and the slave select line

SPI_SEL. One SPI device acts as a master who controls the data flow using the SEL and SCK signals to indicate the start of the data communication and the data sampling rate. To receive the data bits, the streamlined data bits which range from 1 bit to 16 bits specified by the DFL field in the SPICR1 register are latched on a specific clock edge and stored in the data register or in the RX

FIFO. Data transmission is carried out in a similar way but with the reverse sequence. The mode fault detection provides a capability for multi-master applications.

SPIDR

TXFIFO

Status

SPISR

SPIFSR

APB

Bus

MOSI

MISO

SEL

SCK

Transmit/Receive

Logic

Shift

Register

TX Buffer

RX Buffer

RXFIFO

Control

SPICR0

SPICR1

SPIFCR

SPIIER

SPICPR

SPIFTOCR

Figure 45. SPI Block Diagram

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Features

▆

▆

▆

▆

▆

▆

▆

▆

▆

▆

▆

Master or slave mode

Master mode speed up to f

PCLK

/2

Slave mode speed up to f

PCLK

/3

Programmable data frame length up to 16 bits

FIFO Depth: 8 levels

MSB or LSB first shift selection

Programmable slave select high or low active polarity

Multi-master and multi-slave operation

Master mode supports dual output read mode of SPI series NOR Flash

Four error flags with individual interrupt

● Read overrun

● Write collision

● Mode fault

● Slave abort

Support PDMA interface


Master Mode

Each data frame can range from 1 to 16 bits in data length. The first bit of the transmitted data can be either an MSB or LSB determined by the FIRSTBIT bit in the SPICR1 register. The SPI module is configured as a master or a slave by setting the MODE bit in the SPICR1 register. When the MODE bit is set, the SPI module is configured as a master and will generate the serial clock on the SPI_SCK pin. The data stream will transmit data in the shift register to the SPI_MOSI pin on the serial clock edge. The SPI_SEL pin is active during the full data transmission. When the

SELAP bit in the SPICR1 register is set, the SPI_SEL pin is active high during the complete data transactions. When the SELM bit in the SPICR1 register is set, the SPI_SEL pin will be driven by the hardware automatically and the time interval between the active SEL edge and the first edge of

SCK is equal to half an SCK period.

Slave Mode

In the slave mode, the SPI_SCK pin acts as an input pin and the serial clock will be derived from the external master device. The SPI_SEL pin also acts as an input. When the SELAP bit is cleared to 0, the SEL signal is active low during the full data stream reception. When the SELAP bit is set to 1, the SEL signal will be active high during the full data stream reception.

Note: For the slave mode, the APB clock, known as f external SCK clock input frequency.

PCLK

, must be at least 3 times faster than the

SPI Serial Frame Format

The SPI interface format is based on the Clock Polarity, CPOL, and the Clock Phase, CPHA, configurations.

▆

Clock Polarity Bit – CPOL

When the Clock Polarity bit is cleared to 0, the SCK line idle state is low. When the Clock

Polarity bit is set to 1, the SCK line idle state is high.

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▆

Clock Phase Bit – CPHA

When the Clock Phase bit is cleared to 0, the data is sampled on the first SCK clock transition.

When the Clock Phase bit is set to1, the data is sampled on the second SCK clock transition.

There are four formats contained in the SPI interface. Table 36 shows how to configure these formats by setting the FORMAT field in the SPICR1 register.

Table 36. SPI Interface Format Setup

FORMAT [2:0]

001

010

110

101

Others

CPOL

0

0

1

1

Reserved

CPHA

0

1

0

1

CPOL = 0, CPHA = 0

In this format, the received data is sampled on the SCK line rising edge while the transmitted data is changed on the SCK line falling edge. In the master mode, the first bit is driven when data is written into the SPIDR Register. In the slave mode, the first bit is driven when the SEL signal goes to an active level. Figure 46 shows the single byte data transfer timing of this format.

SEL (SELAP=0)

SEL (SELAP=1)

SCK

½ SCK

MOSI TX[7] TX[6] TX[5] TX[4] TX[3] TX[2] TX[1] TX[0]

MISO RX[7] RX[6] RX[5] RX[4] RX[3] RX[2] data sampled

Figure 46. SPI Single Byte Transfer Timing Diagram – CPOL = 0, CPHA = 0

RX[1] RX[0]

Figure 47 shows the continuous data transfer timing diagram of this format. Note that the SEL signal must change to an inactive level between each data frame.

SEL (SELAP=0)

SEL (SELAP=1)

SCK

MOSI/MISO Data1 Data2

Figure 47. SPI Continuous Data Transfer Timing Diagram – CPOL = 0, CPHA = 0

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CPOL = 0, CPHA = 1

In this format, the received data is sampled on the SCK line falling edge while the transmitted data is changed on the SCK line rising edge. In the master mode, the first bit is driven when data is written into the SPIDR register. In the slave mode, the first bit is driven at the first SCK clock rising edge. Figure 48 shows the single data byte transfer timing.

SEL(SELAP=0)

SEL(SELAP=1)

SCK

½ SCK


MISO RX[7] RX[6] RX[5] RX[4] RX[3] RX[2]

Data sampled


RX[1] RX[0]

Figure 49 shows the continuous data transfer diagram timing. Note that the SEL signal must remain active until the last data transfer has completed.

SEL (SELAP=0)

SEL (SELAP=1)

SCK


Figure 49. SPI Continuous Transfer Timing Diagram – CPOL = 0, CPHA = 1

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CPOL = 1, CPHA = 0

In this format, the received data is sampled on the SCK line falling edge while the transmitted data is changed on the SCK line rising edge. In the master mode, the first bit is driven when data is written into the SPIDR register. In the slave mode, the first bit is driven when the SEL signal changes to an active level. Figure 50 shows the single byte transfer timing of this format.

SEL (SELAP=0)

SEL (SELAP=1)

SCK

MOSI

½ SCK

TX[7] TX[6] TX[5] TX[4] TX[3] TX[2] TX[1] TX[0]



RX[1] RX[0]

Figure 51 shows the continuous data transfer timing of this format. Note that the SEL signal must change to an inactive level between each data frame.

SEL (SELAP=0)

SEL (SELAP=1)

SCK

½ SCK

½ SCK

MOSI/MISO Data1


Data2

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CPOL = 1, CPHA = 1

In this format, the received data is sampled on the SCK line rising edge while the transmitted data is changed on the SCK line falling edge. In the master mode, the first bit is driven when data is written into the SPIDR register. In the slave mode, the first bit is driven at the first SCK falling edge. Figure 52 shows the single byte transfer timing of this format.

SEL (SELAP=0)

SEL (SELAP=1)

SCK

½ SCK




RX[1] RX[0]

Figure 53 shows the continuous data transfer timing of this format. Note that the SEL signal must remain active until the last data transfer has completed.

SEL (SELAP=0)

SEL (SELAP=1)

SCK



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SPI Dual Mode

When in the Master mode, the SPI interface operation can be configured to Dual mode. A more efficient data transfer can then be implemented by using this Dual mode together with the four formats described above. In the Dual mode, the SPI data transmission only supports input direction, that is, the SPI_MOSI pin is also switched from output to an input function. In this way a twowire transfer method is formed to read data from an external device synchronously. In addition, the Dual mode only supports a data length of 16-bit (DFL=0x8). The Dual mode is commonly used to read data from an external serial SPI Flash. The following figures show the transfer format bit sequences in the SPI Dual mode.

DUALEN

SEL (SELAP=0)

SEL (SELAP=1)

SCK

½

SCK

MOSI RX[6] RX[4] RX[2] RX[0] RX[14] RX[12] RX[10] RX[8]

MISO RX[7] RX[5] RX[3] RX[1] RX[15] RX[13] RX[11] RX[9]

Data sampled

Figure 54. SPI Dual Mode Bit Sequence – CPOL = 0, CPHA = 0, DFL = 0x8 (16-bit), MSB

Transmitted First

DUALEN

SEL(SELAP=0)

SEL(SELAP=1)

SCK

½

SCK

MOSI RX[6] RX[4] RX[2] RX[0] RX[14] RX[12] RX[10] RX[8]


Data sampled

Figure 55. SPI Dual Mode Bit Sequence – CPOL = 0, CPHA = 1, DFL = 0x8 (16-bit), MSB


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DUALEN

SEL (SELAP=0)

SEL (SELAP=1)

SCK

MOSI

½

SCK

RX[6] RX[4] RX[2] RX[0] RX[14] RX[12] RX[10] RX[8]


Data sampled

Figure 56. SPI Dual Mode Bit Sequence – CPOL = 1, CPHA = 0, DFL = 0x8 (16-bit) , MSB


DUALEN

SEL (SELAP=0)

SEL (SELAP=1)

SCK

MOSI

½

SCK

RX[6] RX[4] RX[2] RX[0] RX[14] RX[12] RX[10] RX[8]


Data sampled

Figure 57. SPI Dual Mode Bit Sequence – CPOL = 1, CPHA = 1, DFL = 0x8 (16-bit) , MSB


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Figure 58 shows the bit sequence of the SPI Dual mode reading data from an external serial SPI

Flash.

DUALEN

Command Address Dummy Data

SEL

∙∙∙∙

∙∙∙∙

∙∙∙∙

∙∙∙∙

SCK

MOSI C7 C6 C5 C4 C3 C2 C1 C0 A23 A22 ∙∙∙∙ A1 A0 ∙∙∙∙ D6 D4 D2 D0 D6 D4 D2 D0

MISO

C7-C0

∙∙∙∙

A23-A0

∙∙∙∙

Figure 58. SPI Dual Mode Data Read Example – CPOL = 1, CPHA = 1

D7 D5 D3

Byte 1

D1 D7 D5 D3

Byte 2

D1

Status Flags

TX Buffer Empty – TXBE

This TXBE flag is set when the TX buffer is empty in the non-FIFO mode or when the TX FIFO data length is equal to or less than the TX FIFO threshold level as defined by the TXFTLS field in the SPIFCR register in the FIFO mode. The following data to be transmitted can then be loaded into the buffer again. After this, the TXBE flag will be reset when the TX buffer already contains new data in the non-FIFO mode or when the TX FIFO data length is greater than the TX FIFO threshold level determined by the TXFTLS field in FIFO mode.

Transmission Register Empty – TXE

This TXE flag is set when both the TX buffer and the TX shift registers are empty. It will be reset when the TX buffer or the TX shift register contains new transmitted data.

RX Buffer Not Empty – RXBNE

This RXBNE flag is set when there is valid received data in the RX buffer in the non-FIFO mode or the RX FIFO data length is equal to or greater than the RX FIFO threshold level as defined by the RXFTLS field in the SPIFCR register in the SPI FIFO mode. This flag will be automatically cleared by hardware when the received data have been read out from the RX buffer totally in the non-FIFO mode or when the RX FIFO data length is less than the RX FIFO threshold level set in the RXFTLS field.

Time Out Flag – TO

The time out function is only available in the SPI FIFO mode and is disabled by loading a zero value into the TOC field in the Time Out Counter register. The time out counter will start counting if the SPI RX FIFO is not empty, once data is read from the SPIDR register or new data is received, the time out counter will be reset to 0 and count again. When the time out counter value is equal to the value specified by the TOC field in the SPIFTOCR register, the TO flag will be set. The flag is cleared by writing 1 to this bit.

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Mode Fault – MF

The mode fault flag can be used to detect SPI bus usage in the SPI multi-master mode. For the multi-master mode, the SPI module is configured as a master device and the SEL signal is set as an input signal. The mode fault flag is set when the SPI_SEL pin is suddenly changed to an active level by another SPI master. This means that another SPI master is requesting to use the SPI bus.

Therefore, when an SPI mode fault occurs, it will force the SPI module to operate in the slave mode and also disable all of the SPI interface signals to avoid SPI bus signal collisions. For the same reason, if the SPI master wants to transfer data, it also needs to inform other SPI masters by driving their SEL signals to an active state. The detailed configuration diagram for the SPI multi-master mode is shown in the following figure.

SPI

Master

SCK

MOSI

MISO

SEL

I/O 0

I/O 1

I/O 2

SCK

MOSI

MISO

SEL

SCK

MOSI

MISO

SEL

SCK

MOSI

MISO

SEL

I/O 0

I/O 1

I/O 2

SPI

Master

SPI

Slave

SPI

Slave

Figure 59. SPI Multi-Master Slave Environment

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Table 37. SPI Mode Fault Trigger Conditions

Mode Fault

Trigger Condition

SPI Behavior

Descriptions

1.

SPI Master mode.

2. SELOEN = 0 in the SPICR0 register – SPI_SEL pin is configured to be the input mode.

3. SEL signal changes to an active level when driven by the external SPI master.

1. Mode fault flag is set.

2. The SPIEN bit in the SPICR0 register is reset. This disables the SPI interface and blocks all output signals from the device.

3. The MODE bit in the SPICR1 register is reset. This forces the device into slave mode.

Table 38. SPI Master Mode SPI_SEL Pin Status

Multi-Master

SEL as Input – SELOEN = 0 SEL as Output – SELOEN = 1

Supported Not supported

Continuous Transfer

Case 1 Case 2

Not supported Supported

SPI_SEL pin in hardware or software control mode – using SELM setting

Case 1 Case 2

Case 1: SEL signal must be inactive between each data transfer.

Case 2: SEL signal will not to be inactive until the last data frame has finished.

Note: When the SPI is in the slave mode, the SEL signal is always an input and not affected by the

SELOEN bit in the SPICR0 register.

Write Collision – WC

The following conditions will assert the Write Collision Flag.

▆

The FIFOEN bit in the SPIFCR register is cleared

The write collision flag is asserted when new data is written into the SPIDR register while both the TX buffer and the shift register are already full. Any new data written into the TX buffer will be lost.

▆

The FIFOEN bit in the SPIFCR register is set

The write collision flag is asserted to indicate that new data is written into the SPIDR register while both the TX FIFO and the TX shift register are already full. Any new data written into the

TX FIFO will be lost.

Read Overrun – RO

▆

The FIFOEN bit in the SPIFCR register is cleared

The read overrun flag is asserted to indicate that both the RX shift register and the RX buffer are already full, if one more data is received. This will result in the newly received data not being shifted into the SPI shift register. As a result the latest received data will be lost.

▆

The FIFOEN bit in the SPIFCR register is set

The read overrun flag is set to indicate that the RX shift register and the RX FIFO are both full, if one more data is received. This means that the latest received data can not be shifted into the

SPI shift register. As a result the latest received data will be lost.

Slave Abort – SA

In the SPI slave mode, the slave abort flag is set to indicate that the SPI_SEL pin suddenly changed to an inactive state during the reception of a data frame transfer. The data frame length is set by the

DFL field in the SPICR1 register.

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PDMA Interface

The PDMA interface is integrated in the SPI module. The PDMA function can be enabled by setting the TXDMAE or RXDMAE bit to 1 in the transmitter or receiver mode respectively. When the transmit buffer empty flag, TXBE, is asserted and the TXDMAE bit is set to 1, the PDMA function will be activated to move data from the memory location that users designated into the SPI data register or the TX FIFO until the TXBE flag is cleared to 0. The TXBE flag will be asserted when the transmit buffer is empty in the non-FIFO mode or the data contained in the TX FIFO is equal to or less than the level defined by the TXFTLS field in the FIFO mode.

Similarly, when the receive buffer not empty flag, RXBNE, is asserted and the RXDMAE bit is set to 1, the PDMA function will be activated to move data from the SPI data register or the RX FIFO to the memory location that users designated until the RXBNE flag is cleared to 0. The RXBNE flag will be asserted when the receive buffer is not empty in the non-FIFO mode or the data contained in the RX FIFO is equal to or greater than the level defined by the RXFTLS field in the

FIFO mode.

For a more detailed description about the PDMA configurations, refer to the PDMA chapter.

Register Map

The following table shows the SPI registers and reset values.

Table 39. SPI Register Map

Register Offset

SPICR0 0x000

SPICR1 0x004

Description

SPI Control Register 0

SPI Control Register 1

SPIIER

SPICPR

SPIDR

SPISR

SPIFCR

SPIFSR

0x008

0x00C

0x010

0x014

0x018

0x01C

SPIFTOCR 0x020

SPI Interrupt Enable Register

SPI Clock Prescaler Register

SPI Data Register

SPI Status Register

SPI FIFO Control Register

SPI FIFO Status Register

SPI FIFO Time Out Counter Register

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0003

0x0000_0000

0x0000_0000

0x0000_0000

Rev. 1.00 269 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU


SPI Control Register 0 – SPICR0

This register specifies the SEL control and the SPI enable bits.

Offset: 0x000


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13

SELHT

12 11 10 9

GUADT

8


7 6 5 4 3 2 1 0

GUADTEN DUALEN Reserved SSELC


SELOEN RXDMAE TXDMAE SPIEN


Bits

[15:12]

[11:8]

[7]

[6]


SELHT

GUADT

Chip Select Hold Time

0x0: 1/2 SCK

0x1: 1 SCK

0x2: 3/2 SCK

0x3: 2 SCK

....

Note that SELHT is for master mode only.

Guard Time

GUADTEN = 1

0x0: 1 SCK

0x1: 2 SCK

0x2: 3 SCK

...

Note that GUADT is for master mode only.

GUADTEN Guard Time Enable

0: Guard Time is 1/2 SCK

1: When this bit is set, guard time can be controlled by GUADT

Note that GUADTEN is for master mode only.

DUALEN Dual Mode Enable

0: Dual Mode is disabled

1: Dual Mode is enabled

The control bit is used to support the dual output read mode of the series SPI NOR

Flash. When this bit is set and the MOSI signal will change the direction from output to input and receive the series data stream. That means the DUALEN control bit is only for master mode.

Rev. 1.00 270 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

[2]

[1]

[0]

Bits

[4]

[3]

Field

SSELC

SELOEN

RXDMAE

TXDMAE

SPIEN

Descriptions

Software Slave Select Control

0: Set the SEL output to an inactive state

1: Set the SEL output to an active state

The application software can set the SEL output to an active or inactive state by configuring the SSELC bit. The active level is configured by the SELAP bit in the

SPICR1 register. Note that the SSELC bit is only available when the SELOEN bit is set to 1 for enabling the SEL output meanwhile the SELM bit is cleared to 0 for controlling the SEL signal by software. Otherwise, the SSELC bit has no effect.

Slave Select Output Enable

0: Set the SEL signal to the input mode for multi-master mode

1: Set the SEL signal to the output mode for slave select

The SELOEN is only available in the master mode to set the SEL signal as an input or output signal. When the SEL signal is configured to operate in the output mode, it is used as a slave select signal in either the hardware or software mode according to the SELM bit setting in the SPICR1 register. The SEL signal is used for mode fault detection in the multi-master environment when it is configured to operate in the input mode

RX PDMA request enable

0: SPI RX path PDMA request is disabled

1: SPI RX path PDMA request is enabled

TX PDMA request enable

0: SPI TX path PDMA request is disabled

1: SPI TX path PDMA request is enabled

SPI Enable

0: SPI interface is disabled

1: SPI interface is enabled

Rev. 1.00 271 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

SPI Control Register 1 – SPICR1

This register specifies the SPI parameters including the data length, the transfer format, the SEL active polarity/ mode, the LSB/MSB control and the master/slave mode.

Offset: 0x004


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

Type/Reset

15

Reserved

7

14

MODE

13

SELM

Reserved

12 11

FIRSTBIT SELAP

10 9

FORMAT


6 5 4 3 2 1 0

DFL

8

RW 0 RW 0 RW 0 RW 0

Bits

[14]

[13]

[12]

[11]

Field

MODE

SELM

FIRSTBIT

SELAP

Descriptions

Master or Slave Mode

0: Slave mode

1: Master mode

Slave Select Mode

0: SEL signal is controlled by software – asserted or de-asserted by the

SSELC bit

1: SEL signal is controlled by hardware – generated automatically by the SPI hardware

Note that the SELM bit is available for master mode only, i.e., MODE = 1.

LSB or MSB Transmitted First

0: MSB is transmitted first

1: LSB is transmitted first

Slave Select Active Polarity

0: SEL signal is active low

1: SEL signal is active high

Rev. 1.00 272 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[10:8]

[3:0]

Field

FORMAT

DFL

Descriptions

SPI Data Transfer Format

These three bits are used to determine the data transfer format of the SPI interface .

FORMAT [2:0] CPOL

001 0

010 0

110

101

Others

1

1

CPHA

Reserved

0

1

0

1

CPOL: Clock Polarity

0: SCK Idle state is low

1: SCK Idle state is high

CPHA: Clock Phase

0: Data is captured on the first SCK clock edge

1: Data is captured on the second SCK clock edge

Data Frame Length

Selects the data transfer frame from 1 bit to 16 bits.

DFL[3:0]

0001

0010

0011

0100

0101

0110

0111

1000

1001

...

1111

SPI Serial Mode

1 bit

2 bits

3 bits

4 bits

5 bits

6 bits

7 bits

8 bits

9 bits

...

15 bits

SPI Dual Mode

—

—

—

—

—

—

—

16 bits

—

—

—

0000 16 bits —

Notes: 1. The total number of data bits is determined by the DFL field configuration together with the selected SPI device transmission mode.

2. Taking the 16-bit data transmission for example, the DFL setting can be figured out as follows

In the Serial Mode: Data frame length = 16/1 = 16, DFL = 0x0;

In the Dual SPI Mode: Data frame length = 16/2 = 8, DFL = 0x8;

3. Dual mode only supports 16-bit data length.

Rev. 1.00 273 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

SPI Interrupt Enable Register – SPIIER

This register contains the corresponding SPI interrupt enable control bit.

Offset: 0x008


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

Reserved

10 9 8

Type/Reset

7

TOIEN

6

SAIEN

5

MFIEN

4

ROIEN

3 2 1

WCIEN RXBNEIEN TXEIEN

0

TXBEIEN


Bits

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

Field

TOIEN

SAIEN

Descriptions

Time Out Interrupt Enable

0: Disable

1: Enable

Slave Abort Interrupt Enable

0: Disable

1: Enable

MFIEN

ROIEN

WCIEN

Mode Fault Interrupt Enable

0: Disable

1: Enable

Read Overrun Interrupt Enable

0: Disable

1: Enable

Write Collision Interrupt Enable

0: Disable

1: Enable

RXBNEIEN RX Buffer Not Empty Interrupt Enable

0: Disable

1: Enable

An interrupt is generated when the RXBNE flag is set and RXBNEIEN is set. In the FIFO mode, the interrupt being generated depends upon the RX FIFO trigger level setting.

TXEIEN Transmission Register Empty Interrupt Enable

0: Disable

1: Enable

The transmission register empty interrupt request will be generated when the TXE flag and the TXEIEN bit are set.

TXBEIEN TX Buffer Empty Interrupt Enable

0: Disable

1: Enable

The TX buffer empty interrupt request will be generated when the TXBE flag and the TXBEIEN bit are set. In the FIFO mode, the interrupt request being generated depends upon the TX FIFO trigger level setting.

Rev. 1.00 274 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

SPI Clock Prescaler Register – SPICPR

This register specifies the SPI clock prescaler ratio.

Offset: 0x00C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CP

10 9 8


7 6 5 4 3 2 1 0

CP


Bits

[15:0]

Field

CP

Descriptions

SPI Clock Prescaler

The SPI clock (SCK) is determined by the following equation: f

SCK

= f

PCLK

/ (2 × (CP + 1)), where the CP ranges is from 0 to 65535

Note: For the SPI master mode, the APB clock (f than the SPI SCK output.

PCLK

) must be at least 2 times faster

SPI Data Register – SPIDR

This register stores the SPI received or transmitted Data.

Offset: 0x010


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

DR

10 9 8


7 6 5 4 3 2 1 0

DR


Rev. 1.00 275 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[15:0]

Field

DR

Descriptions

Data Register

The SPI data register is used to store the serial bus transmitted or received data.

In the non-FIFO mode, writing data into the SPI data register will also load the data into the data transmission buffer, known as the TX buffer. Reading data from the SPI data register will return the data held in the data received buffer, named RX buffer.

SPI Status Register – SPISR

This register contains the relevant SPI status.

Offset: 0x014


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12

Reserved

11 10 9 8

BUSY

Type/Reset

7

TO

6

SA

5

MF

4

RO

3

WC

2

RXBNE

1

TXE

RO 0

0

TXBE

Type/Reset WC 0 WC 0 WC 0 WC 0 WC 0 RO 0 RO 1 RO 1

Bits

[8]

[7]

[6]

Field

BUSY

TO

SA

Descriptions

SPI Busy flag

0: SPI not busy

1: SPI busy

In the master mode, this flag is reset when the TX buffer and TX shift register are both empty and is set when the TX buffer or the TX shift register are not empty.

In the slave mode, this flag is set when SEL changes to an active level and is reset when SEL changes to an inactive level.

Time Out flag

0: No Rx FIFO time out

1: Rx FIFO time out has occurred

Once the time out counter value is equal to the TOC field setting in the SPIFTOCR register, the time out flag will be set and an interrupt will be generated if the TOIEN bit in the SPIIER register is enabled. This bit is cleared by writing 1.

Note: This Time Out flag function is only available in the SPI FIFO mode.

Slave Abort flag

0: No slave abort

1: Slave abort has occurred

This bit is set by hardware and cleared by writing 1.

Rev. 1.00 276 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

[1]

[0]

Bits

[5]

[4]

[3]

[2]

Field

MF

RO

WC

RXBNE

TXE

TXBE

Descriptions

Mode Fault flag

0: No mode fault

1: Mode fault has occurred


Read Overrun flag

0: No read overrun

1: Read overrun has occurred


Write Collision flag

0: No write collision

1: Write collision has occurred


RX Buffer Not Empty flag

0: RX buffer is empty

1: RX buffer is not empty

This bit indicates the RX buffer status in the non-FIFO mode. It is also used to indicate if the RX FIFO trigger level has been reached in the FIFO mode. This bit will be cleared when the SPI RX buffer is empty in the non-FIFO mode or if the number of data contained in RX FIFO is less than the trigger level which is specified by the

RXFTLS field in the SPIFCR register in the SPI FIFO mode.

Transmission Register Empty flag

0: TX buffer or TX shift register is not empty

1: TX buffer and TX shift register both are empty

TX Buffer Empty flag

0: TX buffer is not empty

1: TX buffer is empty

In the FIFO mode, this bit if set indicates that the number of data contained in TX

FIFO is equal to or less than the trigger level specified by the TXFTLS field in the

SPIFCR register.

SPI FIFO Control Register – SPIFCR

This register contains the related SPI FIFO control including the FIFO enable control and the FIFO trigger level selections.

Offset: 0x018


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

15

7

14

6

13

Reserved

5

RXFTLS

12

4

11

3

10

FIFOEN

RW 0

2

9

1

TXFTLS

8

Reserved

0


Rev. 1.00 277 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[10]

[7:4]

[3:0]

Field

FIFOEN

RXFTLS

TXFTLS

Descriptions

FIFO Enable

0: FIFO is disabled

1: FIFO is enabled

This bit can not be set or reset when the SPI interface is in transmitting.

RX FIFO Trigger Level Select

0000: Trigger level is 0


...


Others: Reserved

The RXFTLS field is used to specify the RX FIFO trigger level. When the number of data contained in the RX FIFO is equal to or greater than the trigger level defined by the RXFTLS field, the RXBNE flag will be set

TX FIFO Trigger Level Select



...


Others: Reserved

The TXFTLS field is used to specify the TX FIFO trigger level. When the number of data contained in the TX FIFO is equal to or less than the trigger level defined by the

TXFTLS field, the TXBE flag will be set.

SPI FIFO Status Register – SPIFSR

This register contains the relevant SPI FIFO status.

Offset: 0x01C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

Reserved

10 9 8

Type/Reset

7 6 5

RXFS

4 3 2 1

TXFS

0


Rev. 1.00 278 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[7:4]

[3:0]

Field

RXFS

TXFS

Descriptions

RX FIFO Status

0000: RX FIFO empty

0001: RX FIFO contains 1 data

...


Others: Reserved

TX FIFO Status

0000: TX FIFO empty

0001: TX FIFO contains 1 data

…


Others: Reserved

SPI FIFO Time Out Counter Register – SPIFTOCR

This register stores the SPI RX FIFO time out counter value.

Offset: 0x020


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

TOC

10 9 8


7 6 5 4 3 2 1 0

TOC


Bits

[15:0]

Field

TOC

Descriptions

Time Out Counter Compare Value

The time out counter starts to count from 0 after the SPI RX FIFO receives a data, and the counter value is reset once the data is read from the SPIDR register by software or another new data is received. If the FIFO does not receive new data or the software does not read data from the SPIDR register the time out counter value will continuously increase. When the time out counter value is equal to the

TOC setting value, the TO flag in the SPISR register will be set and an interrupt will be generated if the TOIEN bit in the SPIIER register is set. The time out counter will be stopped when the RX FIFO is empty. The SPI FIFO time out function can be disabled by setting the TOC field to zero. The time out counter is driven by the system APB clock, named f

PCLK

.

Rev. 1.00 279 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

15

Universal Synchronous Asynchronous

Receiver Transmitter (USART)

Introduction

The Universal Synchronous Asynchronous Receiver Transceiver, USART, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. The USART is used to translate data between parallel and serial interfaces, and is also commonly used for RS232 standard communication. The USART peripheral function supports a variety of interrupts.

The USART module includes an 8-level transmit FIFO, TX FIFO, and an 8-level receive FIFO, RX

FIFO. Software can detect a USART error status by reading the USART Status & Interrupt Flag

Register, USRSIFR. The status includes the condition of the transfer operations as well as several error conditions resulting from Parity, Overrun, Framing and Break events.

The USART includes a programmable baud rate generator which is capable of dividing the USART clock CK_APB (CK_USART) to produce a baud rate clock for the USART transmitter and receiver.

CK_USART

APB

Interface

USART Control and

Configuration

Registers

USART

Interrupt

Transmit FIFO

TXD

Transmit Shift Register

Receive Shift Register

Receive FIFO

Baud Rate

Clock

Generator

Reference

Divisor Clock

IrDA _EN

RXD

USART I/O and IrDA

TX

RX

RTS

CTS

Figure 60. USART Block Diagram

Rev. 1.00 280 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Features

▆

▆

▆

▆

▆

▆

▆

▆

▆

▆

Supports both asynchronous and clocked synchronous serial communication modes

Full Duplex Communication Capability

Programmable baud rate clock frequency up to (f

(f

PLCK

/8) MHz for synchronous mode

PLCK

/16) MHz for asynchronous mode and

IrDA SIR encoder and decoder

● Support normal 3/16 bit duration and low-power (1.41 ~ 2.23 μs) durations

Supports RS485 mode with output enable

Auto hardware flow control mode – RTS, CTS

Fully programmable serial communication functions including:

● Word length: 7, 8 or 9-bit character

● Parity: Even, odd, or no-parity bit generation and detection

● Stop bit: 1 or 2 stop bits generation

● Bit order: LSB-first or MSB-first transfer

Error detection: Parity, overrun and frame error

FIFO:

● Receive FIFO: 8-level

● Transmit FIFO: 8-level



Serial Data Format

The USART module performs a parallel-to-serial conversion on data that is written to the transmit

FIFO registers and then sends the data with the following format: Start bit, 7 ~ 9 LSB/MSB first data bits, optional Parity bit and finally 1 ~ 2 Stop bits. The Start bit has the opposite polarity of the data line idle state. The Stop bit is the same as the data line idle state and provides a delay before the next start situation. Both the Start and Stop bits are used for data synchronization during the asynchronous data transmission.

The USART module also performs a serial-to-parallel conversion on the data that is read from the receive FIFO registers. It will first check the Parity bit and will then look for a Stop bit. If the

Stop bit is not found, the USART module will consider the entire word transmission as failed and respond with a Framing Error.

Rev. 1.00 281 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Start Bit Bit0

Start Bit Bit0

Start Bit Bit0

Bit1

Bit1

Bit1

Bit2

Bit2

Bit2

Bit3

7-Bit Data Format

(WLS[1:0]=b00,PBE=0)

Bit4 Bit5 Bit6 Stop Bit

Next Start

Bit

Bit3


(WLS[1:0]=b01,PBE=0)

Bit4 Bit5 Bit6 Bit7

Bit3

(WLS[1:0]=b00,PBE=1)

Bit4 Bit5 Bit6 Parity Bit Stop Bit

Next Start

Bit

Start Bit Bit0 Bit1 Bit2 Bit3


(WLS[1:0]=b10,PBE=0)

Bit4 Bit5 Bit6

Bit3

(WLS[1:0]=b01,PBE=1)

Bit4 Bit5 Bit6 Start Bit Bit0 Bit1 Bit2

Figure 61. USART Serial Data Format

Bit7 Bit8 Stop Bit

Next Start

Bit

Bit7 Parity Bit Stop Bit

Next Start

Bit

Baud Rate Generation

The baud rate for the USART receiver and transmitter are both set with the same values. The baud rate divisor, BRD, has the following relationship with the USART clock which is known as CK_

USART.

Baud Rate Clock = CK_USART / BRD

Where the CK_USART clock is the APB clock connected to the USART while the BRD range is from 16 to 65535 for asynchronous mode and 8 to 65535 for synchronous mode.

CK_USART

BRD = 18

Reference

Divisor Clock

Start Bit Bit0 Bit1 Bit2 Bit3 Bit4

Figure 62. USART Clock CK_USART and Data Frame Timing

～～

Parity Bit

Bitn

n = 7 ~ 8

Stop Bit

Next Start

Bit

Rev. 1.00 282 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Table 40. Baud Rate Deviation Error Calculation – CK_USART = 40 MHz

Baud Rate CK_USART = 40 MHz

No.

7

8

9

10

5

6

3

4

1

2

Kbps

2.4

9.6

19.2

57.6

115.2

230.4

460.8

921.6

2250

3000

Actual

2.4

9.6

19.2

57.6

115.3

229.9

459.8

930.2

2222.2

—

BRD

16667

4167

2083

694

347

174

87

43

18

—

Deviation

Error Rate

0.00%

-0.01%

0.02%

0.06%

0.06%

-0.22%

-0.22%

0.94%

-1.23%

—



No.

1

2

Kbps

2.4

9.6

Actual

2.4

9.6

BRD

20000

5000

Deviation

Error Rate

0.00%

0.00%

8

9

6

7

3

4

5

10

19.2

57.6

115.2

230.4

460.8

921.6

2250

3000

19.2

57.6

115.1

230.8

461.5

923.1

2285.7

3000.0

2500

833

417

208

104

52

21

16

0.00%

0.04%

-0.08%

0.16%

0.16%

0.16%

1.59%

0.00%



No.

1

Kbps

2.4

Actual

2.4

BRD

25000

Deviation

Error Rate

0.00%

6

7

8

4

5

2

3

9

10

9.6

19.2

57.6

115.2

230.4

460.8

921.6

2250

3000

9.6

19.2

57.6

115.2

230.8

461.5

923.1

2222.2

3000.0

6250

3125

1042

521

260

130

65

27

20

0.00%

0.00%

-0.03%

-0.03%

0.16%

0.16%

0.16%

-1.23%

0.00%

Rev. 1.00 283 of 637 December 28, 2020

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Cortex ® -M0+ MCU

Hardware Flow Control

The USART supports the hardware flow control function which is enabled by setting the HFCEN bit in the USRCR register to 1. It is possible to control the serial data flow between two USART devices by using the CTS input and the RTS output. The Figure 58 shows the connection diagram in this mode. The hardware flow control function is categorized into two types. One is the RTS flow control function and the other is the CTS flow control function.

USART 1

Transmitter

Receiver

TX

CTS

RX

RTS

RX

RTS

TX

CTS

USART 2

Receiver

Transmitter

Figure 63. Hardware Flow Control between 2 USARTs

RTS Flow Control

In the RTS flow control, the USART RTS pin is active with a logic low state when the receive data register is empty. It means that the receiver is ready to receive a new data. When the RX FIFO reaches the trigger level which is specified by configuring the RXTL field in the USRFCR register, the USART RTS pin is inactive with a logic high state. Figure 59 shows the example of RTS flow control.

Parity Bit

Bit N Stop Bit

N=6~8

Start Bit

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4

RTS

RXFS[3:0] 3

Parity Bit

Bit N

N=6~8

Stop Bit Idle

Start Bit


4

Reach the RX trigger level

RXTL[1:0] = b10

Figure 64. USART RTS Flow Control

Read data until RX FIFO is empty

0 1

CTS Flow Control

If the hardware flow control function is enabled, the URTXEN bit in the USRCR register is controlled by the USART CTS input signal. If the USART CTS pin is forced to a logic low state, the URTXEN bit will automatically be set to 1 to enable the data transmission. However, if the

USART CTS pin is forced to a logic high state, the URTXEN bit will be cleared to 0 and then the data transmission will also be disabled.

Rev. 1.00 284 of 637 December 28, 2020

32-Bit Arm ®

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Cortex ® -M0+ MCU

When the USART CTS pin is forced to a logic high state during a data transmission period, the current data transmission will be continued until the stop bit is completed. The Figure 60 shows an example of communication with CTS flow control.

Start Bit


CTS

Parity Bit

Bit N

N=6~8

Stop Bit Idle

Start Bit


Parity Bit

Bit N

N=6~8

Stop

Bit

Start Bit

Bit 0

TXFS[3:0] 4

Figure 65. USART CTS Flow Control

3 2

IrDA

The USART IrDA mode is provided for half-duplex point-to-point wireless communication.

The USART module includes an integrated modulator and demodulator which allow a wireless communication using infrared transceivers. The transmitter specifies a logic data ‘0’ as a ‘high’ pulse and a logic data ‘1’ as a ‘low’ level while the Receiver specifies a logic data ‘0’ as a ‘low’ pulse and a logic data ‘1’ as ‘high’ level in the IrDA mode.

TX_Data 1

START

0 1 0 1

Data Frame

0 1 1 1 0

STOP

IrDA TX

Modulation

Signal bit width

IrDA RX

Demodulation

Signal

RX_Data 1

START

0 1 0

3/16 bit width

1

Data Frame

0 1 1 1 0

STOP

Figure 66. IrDA Modulation and Demodulation

The IrDA mode provides two operation modes, one is the normal mode, and the other is the lowpower mode.

Rev. 1.00 285 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

IrDA Normal Mode

For the IrDA normal mode, the width of each transmitted pulse generated by the transmitter modulator is specified as 3/16 of the baud rate clock period. The receiver pulse width for the IrDA receiver demodulator is based on the IrDA receive debounce filter which is implement using an

8-bit down-counting counter. The debounce filter counter value is specified by the IrDAPSC field in the IrDACR register. When a falling edge is detected on the receiver pin, the debounce filter counter starts to count down, driven by the CK_USART clock. If a rising edge is detected on the receiver pin, the counter stops counting and is reloaded with the IrDAPSC value. When a low pulse falling edge on the receiver pin is detected and then before the debounce filter has counted down to zero, a rising edge is also detected, then this low pulse will be considered as glitch noise and will be discarded. If a low pulse falling edge appears on the receiver pin but no rising edge is detected before the debounce counter reaches 0, then the input is regarded as a valid data “0” for this bit duration. The IrDAPSC value must be set to be greater than or equal to 0x01, then the

IrDA receiver demodulation operation can function properly. The IrDAPSC value can be adjusted to meet the USART baud rate setting to filter the IrDA received glitch noise of which the width is smaller than the prescaler setting duration.

IrDA Low-Power Mode

In the IrDA low-power mode, the transmitted IrDA pulse width generated by the transmitter modulator is not kept at 3/16 of the baud rate clock period. Instead, the pulse width is fixed and is calculated by the following formula. The transmitted pulse width can be adjusted by the IrDAPSC field to meet the minimum pulse width specification of the external IrDA receiver device.

T

IrDA_L

= 3 × IrDAPSC / CK_USART

Note: T

IrDA_L

is the transmitted pulse width in the low-power mode.

The IrDAPSC filed is the IrDACR prescaler value in the IrDA Control Register IrDACR.

The debounce behavior in the IrDA low-power receiving mode is similar to the IrDA normal mode.

For glitch detection, the low pulse of which the pulse width is shorter than 1 × (IrDAPSC / CK_

USART) should be discarded in the IrDA receiver demodulation. A valid low data is accepted if its low pulse width is greater than 2 × (IrDAPSC / CK_USART) duration.

The IrDA physical layer specification specifies a minimum delay with a value of 10 ms between the transmission and reception switch; and this IrDA receiver set-up time also should be managed by the software.

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TX_Data 0

1

TX

Transmitter

Modulation

SEL

TXSEL

RX_Data

0

1

IrDAEN

Figure 67. USART I/O and IrDA Block Diagram

Receiver

Demodulation

SEL

RX

RS485 Mode

The RS485 mode of USART provides the data transmission on interface transmitted over a 2-wire twisted pair bus. The RS485 transceiver interprets the voltage levels of the differential signals with respect to a third common voltage. Without this common reference, the transceiver may interpret the differential signals incorrectly. This enhances the noise rejection capabilities of the RS485 interface. The USART RTS pin is used to control the external RS485 transceiver whose polarity can be selected by configuring the TXENP bit in the RS485 Control Register, named RS485CR, when the USART operates in the RS485 mode.

RS485 Auto Direction Mode – AUD

When the RS485 mode is configured as a master transmitter, it will operate in the Auto Direction

Mode, AUD. In the AUD mode the polarity of the USART RTS pin is configurable according to the

TXENP bit in the RS485 Control Register in the RS485 mode. This pin can be used to control the external RS485 transceiver to enable the transmitter.

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RX

RS-485 Transceiver

Differential

Bus

USART

TX

RTS

Reference

Divisor Clock

TX

RTS

TXENP = 0

Start D0 D1 D2 D3 D4 D5 D6 D7 Parity

Bit

Stop

Bit

TG = 4

RTS

TXENP = 1

Figure 68. RS485 Interface and Waveform

RS485 Normal Multi-drop Operation Mode – NMM

When the RS485 mode is configured as an addressable slave, it will operate in the Normal Multidrop Operation Mode, NMM. This mode is enabled when the RSNMM field is set in the RS485CR register. Regardless of the URRXEN value in the USRCR register, all the received data with a parity bit “0” will be ignored until the first address byte is detected with a parity bit “1” and then the received address byte will be stored in the RX FIFO. Once the first address data is detected and stored in the RX FIFO, the RSADD flag in the USRSIFR register will be set and generate an interrupt if the RSADDIE bit in the USRIER register is set to 1. Application software can determine whether the receiver is enabled or disabled to accept the following data by configuring the URRXEN bit. When the receiver is enabled by setting the URRXEN bit to 1, all received data will be stored in the RX FIFO. Otherwise, all received data will be ignored if the receiver is disabled by clearing the URRXEN bit to 0.

RS485 Auto Address Detection Operation Mode – AAD

Except in the Normal Multi-drop Operation Mode, the RS485 mode can operate in the Auto

Address Detection Operation Mode, AAD, when it is configured as an addressable slave. This

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Cortex ® -M0+ MCU mode is enabled by setting the RSAAD filed to 1 in the RS485CR register. The receiver will detect the address frame with a parity bit “1” and then compare the received address data with the

ADDMATCH field value which is a programmable 8-bit address value specified in the RS485CR register. If the address data matches the ADDMATCH value, it will be stored in the RX FIFO and the URRXEN bit will be automatically set. When the receiver is enabled, all received data will be stored in the RX FIFO until the next address frame does not match the ADDMATCH value and then the receiver will be automatically disabled. After the receiver is enabled, software can disable the receiver by setting the URRXEN bit to ‘0’.

Synchronous Master Mode

The data is transmitted in a full-duplex style in the USART Synchronous Master Mode, i.e., data transmission and reception both occur at the same time and only support master mode. The

USART CTS pin is the synchronous USART transmitter clock output. In this mode, no clock pulses will be sent to the CTS pin during the start bit, parity bit and stop bit duration. The CPS bit in the Synchronous Control Register SYNCR, can be used to determine whether data is captured on the first or the second clock edge. The CPO bit in the SYNCR can be used to configure the clock polarity in the USART Synchronous Mode idle state. Detailed timing information is shown in the

Figure 64.

In the USART synchronous Mode, the USART CTS/SCK clock output pin is only used to transmit the data to slave device. If the transmission data register USRDR, is written with valid data, the

USART synchronous mode will automatically transmit this data with the corresponding clock output and the USART receiver will also receive data on the RX pin. Otherwise the receiver will not obtain synchronous data if no data is transmitted.

USART

(Master)

TX

RX

CTS/SCK

GPIO for Chip Select

Data in

Data out

Clock

Device

(Slave)

CS

Figure 69. USART Synchronous Transmission Example

Note: The USART supports the synchronous master mode only: it can not receive or send data related to an input clock. The USART CTS/SCK clock is always an output.

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(CPS=1, WLS[1:0]=b01, PBE=0)

Clock (CPO=0)

Clock (CPO=1)

USART TX

(From Master to Slave)

USART RX

(From Slave to Master)

Start D0 D1

D0 D1

D2

D2

D3

D3

D4

D4

D5

D5

D6

D6

D7 Stop

D7

(CPS=1, WLS[1:0]=b00, PBE=1)

Clock (CPO=0)

Clock (CPO=1)

USART TX


USART RX


Start D0 D1

D0 D1

D2

D2

D3

D3

D4

D4

D5

D5

D6 Parity Stop

D6 Parity

(CPS=0, WLS[1:0]=b01, PBE=0)

Clock (CPO=0)

Clock (CPO=1)

USART TX


USART RX


Start D0

D0

D1 D2 D3

D2 D3

D4

D4 D1

(CPS=0, WLS[1:0]=b00, PBE=1)

D5

D5

Clock (CPO=0)

Clock (CPO=1)

USART TX


USART RX


Start D0

D0

D1

D1

D2

D2

D3

D3

Figure 70. 8-bit Format USART Synchronous Waveform

D4

D4

D6

D6

D7 Stop

D7

D5

D5

D6 Parity Stop

D6 Parity

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Interrupts and Status

The USART can generate interrupts when the following events occur and the corresponding interrupt enable bits are set:

▆

▆

▆

▆

▆

Receive FIFO time-out interrupt: An interrupt is generated when the USART receive FIFO is not empty and does not receive a new data package during the specified time-out interval.

Receiver line status interrupts: The interrupts are generated when the USART receiver overrun error, parity error, framing error and break events occur.

Transmit FIFO threshold level interrupt: An interrupt is generated when the data to be transmitted in the USART Transmit FIFO is less than the specified threshold level.

Transmit complete interrupt: An interrupt is generated when the Transmit FIFO is empty and the content of the transmit shift register (TSR) is also completely shifted.

Receive FIFO threshold level interrupt: An interrupt is generated when the FIFO received data amount has reached the specified threshold level.

PDMA Interface

The PDMA interface is integrated in the USART. The PDMA function can be enabled by setting the TXDMAEN or RXDMAEN bit in the USRCR register to 1 in the transmit or receive mode respectively. When the data to be transmitted in the USART Transmit FIFO is less than the TX

FIFO threshold level specified by the TXTL field in the USRFCR register and the TXDMAEN bit is set to 1, the PDMA function will be activated to move data from a source location into the

USART TX FIFO.

Similarly, when the received data amount in the receive FIFO is equal to the RX FIFO threshold level specified by the RXTL field in the USRFCR register and the RXDMAEN bit is set to 1, the

PDMA function will be activated to move data from the USART RX FIFO to a specific destination location. For a more detailed description about the PDMA configurations, refer to the PDMA chapter.

Register Map

The following table shows the USART registers and reset values.

Table 43. USART Register Map

Register Offset

USRDR 0x000

USRCR 0x004

Description

USART Data Register

USART Control Register

USRFCR

USRIER

USRSIFR

USRTPR

IrDACR

RS485CR

0x008

0x00C

0x010

0x014

0x018

0x01C

SYNCR

USRDLR

0x020

0x024

USRTSTR 0x028

USART FIFO Control Register

USART Interrupt Enable Register

USART Status & Interrupt Flag Register

USART Timing Parameter Register

USART IrDA Control Register

USART RS485 Control Register

USART Synchronous Control Register

USART Divider Latch Register

USART Test Register

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0980

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0010

0x0000_0000

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USART Data Register – USRDR

The register is used to access the USART transmitted and received FIFO data.

Offset: 0x000


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

15

7

14

6

13

5

12

Reserved

4

11

3

DB

10

2

9

1

8

DB

RW 0

0


Bits

[8:0]

Field

DB

Descriptions

Reading data from this receiver buffer register will return the data from the receive

FIFO. The receive FIFO has a capacity of up to 8 × 9 bits. By reading this register, the USART will return a 7, 8 and 9-bit received data. The DB field bit 8 is valid for the

9-bit mode only and is fixed at 0 for the 8-bit mode. For the 7-bit mode, the DB[6:0] field contains the available bits.

Writing data to this buffer register will load data into the Transmit FIFO. The Transmit

FIFO has a capacity of up to 8 × 9 bits. By writing to this register, the USART will send out 7, 8 or 9-bit transmitted data. The DB field bit 8 is valid for the 9-bit mode only and will be ignored for the 8-bit mode. For the 7-bit mode, the DB[6:0] field contains the available bits.

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USART Control Register – USRCR

The register specifies the serial parameters such as data length, parity and stop bit for the USART. It also contains the USART enable control bits together with the USART mode and data transfer mode selection.

Offset: 0x004


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15

RTS

14

BCB

13

SPE

12

EPE

11

PBE

10

NSB

9 8

WLS


7 6 5 4 3 2 1 0

RXDMAEN TXDMAEN URRXEN URTXEN HFCEN TRSM MODE


Bits

[15]

[14]

[13]

[12]

[11]

Field

RTS

BCB

SPE

EPE

PBE

Descriptions

Request-To-Send Signal

0: Drive USART RTS pin to logic 1

1: Drive USART RTS pin to logic 0

Note that the RTS bit is used to control the USART RTS pin status when the HFCEN bit is reset.

When the HFCEN bit is set, this RTS bit is read only and indicates the pin status that is controlled by hardware flow control function.

Break Control Bit

When this bit is set 1, the serial data output on the USART TX pin will be forced to the Spacing State (logic 0). This bit acts only on the USART TX output pin and has no effect on the transmitter logic.

Stick Parity Enable

0: Disable stick parity

1: Stick Parity bit is transmitted

This bit is only available when the PBE bit is set to 1. If both the PBE and SPE bits are set to 1 and the EPE bit is cleared to 0, the transmitted parity bit will be stuck to

1. However, when the PBE and SPE bits are set to 1 and also the EPE bit is set to

1, the transmitted parity bit will be stuck to 0.

Even Parity Enable

0: Odd number of logic 1’s are transmitted or checked in the data word and parity bits

1: Even number of logic 1’s are transmitted or checked in the data word and parity bits

This bit is only available when the PBE bit is set to 1.

Parity Bit Enable

0: Parity bit is not generated (transmitted data) or checked (received data) during transfer

1: Parity bit is generated or checked during transfer

Note: When the WLS field is set to “10” to select the 9-bit data format, writing to the

PBE bit has no effect.

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[5]

[4]

[7]

[6]

[3]

[2]

[1:0]

Bits

[10]

[9:8]

Field

NSB

Descriptions

Number of STOP bit

0: One STOP bit is generated in the transmitted data

1: Two STOP bits are generated when 8-bit or 9-bit word length is selected

WLS

RXDMAEN USART RX DMA Enable

0: Disable

1: Enable

TXDMAEN USART TX DMA Enable

0: Disable

1: Enable

URRXEN

Word Length Select

00: 7 bits

01: 8 bits

10: 9 bits

11: Reserved

URTXEN

USART RX Enable

0: Disable

1: Enable

USART TX Enable

0: Disable

1: Enable

HFCEN

TRSM

MODE

Hardware Flow Control Function Enable

0: Disable

1: Enable

Transfer Mode Selection

This bit is used to select the data transfer protocol.

0: LSB first

1: MSB first

USART Mode Selection

00: Normal operation

01: IrDA

10: RS485

11: Synchronous

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USART FIFO Control Register – USRFCR

This register specifies the USART FIFO control and configurations including threshold level and reset function together with the USART FIFO status.

Offset: 0x008


Type/Reset

31

23

30

22

29

Reserved

21

Reserved

28

20

27

RO 0 RO

19

26

18

25

RXFS

0 RO 0 RO

24

17

TXFS

0 RO 0 RO

16

9 8

0

Type/Reset

15 14 13 12

Type/Reset

7 6

RXTL

5 4

TXTL


RO

11

Reserved

0 RO

10

3 2

Reserved

0

1

RXR

0

TXR

WO 0 WO 0

Bits

[27:24]

[19:16]

[7:6]

[5:4]

[1]

Field

RXFS

TXFS

RXTL

TXTL

RXR

Descriptions

RX FIFO Status

The RXFS field shows the current number of data contained in the RX FIFO.

0000: RX FIFO is empty


...


Others: Reserved

TX FIFO Status

The TXFS field shows the current number of data contained in the TX FIFO.

0000: TX FIFO is empty


...


Others: Reserved

RX FIFO Threshold Level Setting

00: 1 data

01: 2 data

10: 4 data

11: 6 data

The RXTL field defines the RX FIFO trigger level.

TX FIFO Threshold Level Setting

00: 0 data

01: 2 data

10: 4 data

11: 6 data

The TXTL field determines the TX FIFO trigger level.

RX FIFO Reset

Setting this bit will generate a reset pulse to reset the RX FIFO which will empty the

RX FIFO, i.e., the RX pointer will be reset to 0 after a reset signal. This bit returns to

0 automatically after the reset pulse is generated.

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Bits

[0]

Field

TXR

Descriptions

TX FIFO Reset

Setting this bit will generate a reset pulse to reset the TX FIFO which will empty the

TX FIFO, i.e., the TX pointer will be reset to 0 after a reset signal. This bit returns to

0 automatically after the reset pulse is generated.

USART Interrupt Enable Register – USRIER

This register is used to enable the related USART interrupt function. The USART module generates interrupts to the controller when the corresponding events occur and the corresponding interrupt enable bits are set.

Offset: 0x00C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12

Reserved

11 10 9

CTSIE

8

RXTOIE

Type/Reset

7

RSADDIE

6

BIE

5

FEIE

4

PEIE

3

OEIE

2

TXCIE

RW 0 RW 0

1 0

TXDEIE RXDRIE


Bits

[9]

[8]

[7]

[6]

Field

CTSIE

RXTOIE

RSADDIE

BIE

Descriptions

CTS Clear-To-Send Interrupt Enable

0: Disable

1: Enable

If this bit is set, an interrupt will be generated when the CTSC bit in the USRSIFR register is set.

Receive FIFO Time-Out Interrupt Enable

0: Disable

1: Enable

If this bit is set, an interrupt will be generated when the RXTOF bit in the

USRSIFR register is set.

RS485 Address Detection Interrupt Enable

0: Disable

1: Enable

If this bit is set, an interrupt will be generated when the RSADD bit in the

USRSIFR register is set.

Break Interrupt Enable

0: Disable

1: Enable

If this bit is set, an interrupt will be generated when the BII bit in the USRSIFR register is set.

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Bits

[5]

[4]

[3]

[2]

[1]

[0]

Field

FEIE

PEIE

OEIE

TXCIE

TXDEIE

RXDRIE

Descriptions

Framing Error Interrupt Enable

0: Disable

1: Enable

If this bit is set, an interrupt will be generated when the FEI bit in the URSIFR register is set.

Parity Error Interrupt Enable

0: Disable

1: Enable

If this bit is set, an interrupt will be generated when the PEI bit in the USRSIFR register is set.

Overrun Error Interrupt Enable

0: Disable

1: Enable

If this bit is set, an interrupt will be generated when the OEI bit in the USRSIFR register is set.

Transmit Complete Interrupt Enable

0: Disable

1: Enable

If this bit is set, an interrupt will be generated when the TXC bit in the USRSIFR register is set.

Transmit Data Empty Interrupt Enable

0: Disable

1: Enable

If this bit is set, an interrupt will be generated when the TXDE bit in the USRSIFR register is set.

Receive Data Ready Interrupt Enable

0: Disable

1: Enable

If this bit is set, an interrupt will be generated when the RXDR bit in the USRSIFR register is set.

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USART Status & Interrupt Flag Register – USRSIFR

This register contains the corresponding USART status.

Offset: 0x010


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13

Reserved

12 11

CTSS

10

CTSC

9

RSADD

8

TXC

Type/Reset

7

TXDE

6

RXTOF

5

RXDR

4

BII

RO 1 WC 0 WC 0 RO 1

3

FEI

2

PEI

1

OEI

0

RXDNE

Type/Reset RO 1 WC 0 RO 0 WC 0 WC 0 WC 0 WC 0 RO 0

Bits

[11]

[10]

[9]

[8]

[7]

Field

CTSS

CTSC

RSADD

TXC

TXDE

Descriptions

CTS Clear-To-Send Status

0: CTS pin is inactive

1: CTS pin is active and kept at a logic low state

CTS Status Change Flag

This bit will be set whenever the CTS input pin status has been changed and an

Interrupt will be generated if the CTSIE bit in the USRIER register is set. Writing 1 to this bit clears the flag.

RS485 Address Detection

0: Address is not detected

1: Address is detected

This bit will be set to 1 when the receiver detects the address. An interrupt will be generated if the RSADDIE bit in the USRIER register is set. Writing 1 to this bit clears the flag.

Note: This bit is only used in the RS485 mode by setting the MODE field in the

USRCR register.

Transmit Complete

0: Either transmit FIFO (TX FIFO) or transmit shift register (TSR) is not empty

1: Both the TX FIFO and TSR register are empty

When this bit is set, an interrupt will be generated if the TXCIE bit in the USRIER register is set. This bit is cleared by a write to the USRDR register with new data.

Transmit Data FIFO Empty

0: TX FIFO level is higher than threshold

1: TX FIFO level is equal to or less than threshold

The TXDE bit will be set when the transmit FIFO level is less than the transmit FIFO threshold level specified by the TXTL field in the USRFCR register. This bit will be cleared when the USRDR register is written with new data and the TX FIFO level is higher than the threshold setting.

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[3]

[2]

[1]

Bits

[6]

[5]

[4]

[0]

Field

RXTOF

RXDR

BII

FEI

PEI

OEI

RXDNE

Descriptions

Receive FIFO Time-Out Flag

0: RX FIFO Time-Out does not occur

1: RX FIFO Time-Out occurs

The RXTOF bit will be set if the RX FIFO is not empty and no activities have occurred in the RX FIFO during the time-out duration specified by the RXTOC field.

If an RX FIFO time-out condition has occurred, this flag must be cleared before reading the RX FIFO. Writing 1 to this bit clears the flag.

Receive FIFO Ready Flag

0: RX FIFO level is less than threshold

1: RX FIFO level is equal to or higher than threshold

The RXDR bit will be set when the FIFO received data amount has reached the threshold level specified by the RXTL field in the USRFCR register. This bit will be cleared when the data is read from the USRDR register and the RX FIFO level is less than threshold setting.

Break Interrupt Indicator

This bit will be set to 1 whenever the received data input is held in the “spacing state” (logic 0) for longer than a full word transmission time, which is the total time of “start bit” + data bits + “parity” + “stop bits” duration. Writing 1 to this bit clears the flag.

Framing Error Indicator

This bit will be set 1 whenever the next character to be read in the RX FIFO does not have a valid “stop bit”, which means the stop bit following the last data bit or parity bit is detected as logic 0. Writing 1 to this bit clears the flag.

Parity Error Indicator

This bit will be set to 1 whenever the received character does not have a valid “parity bit”. Writing 1 to this bit clears the flag.

Overrun Error Indicator

An overrun error will occur only after the RX FIFO is full and when the next character has been completely received in the RX shift register. The character in the shift register will be overwritten if a new character is received in the RX shift register after an overrun event occurs, but the data in the RX FIFO will not be overwritten. The

OEI bit is used to indicate the overrun event as soon as it happens. Writing 1 to this bit clears the flag.

RX FIFO Data Not Empty

0: RX FIFO is empty

1: RX FIFO contains at least 1 received data word

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USART Timing Parameter Register – USRTPR

This register contains the USART timing parameters including the transmitter time guard parameters and the receive FIFO time-out value together with the RX FIFO time-out interrupt enable control.

Offset: 0x014


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

TG

10 9 8


7 6 5 4 3 2 1 0

RXTOEN RXTOC


Bits

[15:8]

[7]

[6:0]

Field

TG

RXTOEN

RXTOC

Descriptions

Transmitter Time Guard

The transmitter time guard counter is driven by the baud rate clock. When the

TX FIFO transmits data, the counter is reset and then starts to count after a word transmission has completed. Only when the counter content is equal to the TG value, are further word transmission transactions allowed.

Receive FIFO Time-Out Counter Enable

0: RX FIFO Time-Out Counter is disabled

1: RX FIFO Time-Out Counter is enabled

Receive FIFO Time-Out Counter Compare Value

The RX FIFO time-out counter is driven by the baud rate clock. When the RX FIFO receives new data, the counter is reset and then starts to count. Once the time-out counter content is equal to the time-out counter compare value RXTOC, a receive

FIFO time-out interrupt, RXTOI, will be generated if the RXTOIE bit in the USRIER register is set to 1. New received data or the empty RX FIFO after being read will clear the RX FIFO time-out counter.

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USART IrDA Control Register – IrDACR

This register is used to control the IrDA mode of USART.

Offset: 0x018


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

15 14

Reserved

13 11

IrDAPSC


7 6 5 4 3 2 1 0

RXINV

12

TXINV LB

10

TXSEL

9

IrDALP

8

IrDAEN


Bits

[15:8]

[5]

[4]

[3]

[2]

[1]

Field

IrDAPSC

RXINV

TXINV

LB

TXSEL

IrDALP

Descriptions

IrDA Prescaler value

This field contains the 8-bit debounce prescaler value.

The debounce count-down counter is driven by the USART clock, named as CK_

USART. The counting period is specified by the IrDAPSC field. The IrDAPSC field must be set to a value equal to or greater than 0x01 for normal debounce counter operation. If the pulse width is less than the duration specified by the IrDAPSC field, the pulse will be considered as glitch noise and discarded.

00000000: Reserved – can not be used

00000001: CK_USART clock divided by 1



...

RX Signal Inverse Control

0: No inversion

1: RX input signal is inversed

TX Signal Inverse Control

0: No inversion

1: TX output signal is inversed

IrDA Loop Back Mode

0: Disable IrDA loop back mode

1: Enable IrDA loop back mode for self-testing

Transmit Select

0: Enable IrDA receiver

1: Enable IrDA transmitter

IrDA Low-Power Mode

Selects the IrDA operation mode.

0: Normal mode

1: IrDA low-power mode

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Bits

[0]

Field

IrDAEN

Descriptions

IrDA Enable control

0: Disable IrDA mode

1: Enable IrDA mode

USART RS485 Control Register – RS485CR

This register is used to control the RS485 mode of USART.

Offset: 0x01C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

ADDMATCH

10 9 8


7 6 5

Reserved

4 3 2

RSAAD

1

RSNMM

0

TXENP


Bits

[15:8]

[2]

[1]

[0]


ADDMATCH RS485 Auto Address Match value

The field contains the address match value for the RS485 auto address detection operation mode.

RSAAD RS485 Auto Address Detection Operation Mode Control

0: Disable

1: Enable

RSNMM

TXENP

RS485 Normal Multi-drop Operation Mode Control

0: Disable

1: Enable

USART RTS/TXE Pin Polarity

0: RTS/TXE is active high in the RS485 transmission mode

1: RTS/TXE is active low in the RS485 transmission mode

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USART Synchronous Control Register – SYNCR

This register is used to control the USART synchronous mode.

Offset: 0x020


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11

Reserved

10 9 8

3

CPO

2

CPS

RW 0 RW 0

1 0

Reserved CLKEN

RW 0

Bits

[3]

[2]

[0]

Field

CPO

CPS

CLKEN

Descriptions

Clock Polarity

0: CTS/SCK pin idle state is low

1: CTS/SCK pin idle state is high

Selects the polarity of the clock output on the USART CTS/SCK pin in the synchronous mode. Works in conjunction with the CPS bit to specify the desired clock idle state.

Clock Phase

0: Data is captured on the first clock edge

1: Data is captured on the second clock edge

This bit allows the user to select the phase of the clock output on the USART

CTS/SCK pin in the synchronous mode. Works in conjunction with the CPO bit to determine the data capture edge.

Clock Enable

0: CTS/SCK pin is disabled

1: CTS/SCK pin is enabled

Enable/disable the USART CTS/SCK pin.

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USART Divider Latch Register – USRDLR

The register is used to determine the USART clock divided ratio to generate the appropriate baud rate.

Offset: 0x024


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

BRD

10 9 8


7 6 5 4 3 2 1 0

BRD


Bits

[15:0]

Field

BRD

Descriptions

Baud Rate Divider

The 16 bits define the USART clock divider ratio.

Baud Rate = CK_USART / BRD

Where the CK_USART clock is the clock connected to the USART module.

BRD = 16 ~ 65535 for asynchronous mode;

BRD = 8 ~ 65535 for synchronous mode.

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USART Test Register – USRTSTR

This register controls the USART debug mode.

Offset: 0x028


31 30 29

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

Type/Reset

Bits

[1:0]

Field

LBM

Descriptions

Loopback Test Mode Select

00: Normal Operation

01: Reserved

10: Automatic Echo Mode

11: Loopback Mode

26

18

10

25

17

9

24

16

8

2 1 0

LBM

RW 0 RW 0

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16

Universal Asynchronous Receiver

Transmitter (UART)

Introduction

The Universal Asynchronous Receiver Transceiver, UART, provides a flexible full duplex data exchange using asynchronous transfer. The UART is used to translate data between parallel and serial interfaces, and is also commonly used for RS232 standard communication. The UART peripheral function supports a variety of interrupts.

The UART module includes a transmit data register TDR and transmit shift register TSR, and a receive data register RDR and receive shift register RSR. Software can detect a UART error status by reading the UART Status & Interrupt Flag Register, URSIFR. The status includes the condition of the transfer operations as well as several error conditions resulting from Parity, Overrun,

Framing and Break events.

The UART includes a programmable baud rate generator which is capable of dividing the UART clock CK_APB (CK_UART) to produce a baud rate clock for the UART transmitter and receiver.

CK_UART

APB

Interface UART Control and

Configuration

Registers

UART

Interrupt

Transmit Data Register (TDR)

TXD

Transmit Shift Register (TSR)

Receive Shift Register (RSR)

Receive Data Register (RDR)

Baud Rate

Clock

Generator

Reference

Divisor Clock

RXD

UART I/O

TX

RX

Figure 71. UART Block Diagram

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Features

▆

▆

▆

▆

▆

▆

Supports asynchronous serial communication modes

Full Duplex Communication Capability

Programming baud rate clock frequency up to (f

PCLK

/16) MHz

Fully programmable serial communication functions including:

● Word length: 7, 8 or 9-bit character

●

● Stop bit: 1 or 2 stop bits generation

●

Parity: Even, odd or no-parity bit generation and detection

Bit order: LSB-first or MSB-first transfer

Error detection: Parity, overrun, and frame error



Serial Data Format

The UART module performs a parallel-to-serial conversion on data that is written to the transmit data register and then sends the data with the following format: Start bit, 7 ~ 9 LSB/MSB first data bits, optional Parity bit and finally 1 ~ 2 Stop bits. The Start bit has the opposite polarity of the data line idle state. The Stop bit is the same as the data line idle state and provides a delay before the next start situation. Both the Start and Stop bits are used for data synchronization during the asynchronous data transmission.

The UART module also performs a serial-to-parallel conversion on the data that is read from the receive data register. It will first check the Parity bit and will then look for a Stop bit. If the Stop bit is not found, the UART module will consider the entire word transmission as failed and respond with a Framing Error.

Start Bit Bit0

Start Bit Bit0

Start Bit Bit0

Start Bit Bit0

Bit1

Bit1

Bit1

Bit1

Bit2

Bit2

Bit2

Bit2

Start Bit Bit0 Bit1 Bit2

Figure 72. UART Serial Data Format

Bit3


(WLS[1:0]=b00, PBE=0)

Bit4 Bit5 Bit6 Stop Bit

Next Start

Bit

Bit3


(WLS[1:0]=b01, PBE=0)

Bit4 Bit5 Bit6 Bit7 Stop Bit

Next Start

Bit

Bit3

(WLS[1:0]=b00, PBE=1)

Bit4 Bit5 Bit6 Parity Bit Stop Bit

Next Start

Bit

Bit3


(WLS[1:0]=b10, PBE=0)

Bit4 Bit5 Bit6

Bit3

(WLS[1:0]=b01, PBE=1)

Bit4 Bit5 Bit6

Bit7 Bit8

Bit7 Parity Bit

Stop Bit

Stop Bit

Next Start

Bit

Next Start

Bit

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Baud Rate Generation

The baud rate for the UART receiver and transmitter are both set with the same values. The baud rate divisor, BRD, has the following relationship with the UART clock which is known as CK_

UART.

Baud Rate Clock = CK_UART / BRD

Where the CK_UART clock is the APB clock connected to the UART while the BRD range is from

16 to 65535.

CK_UART

BRD = 18

Reference

Divisor Clock

Start Bit Bit0 Bit1 Bit2 Bit3 Bit4

～～

Parity Bit

Bitn

n = 7 ~ 8

Stop Bit

Next Start

Bit

Figure 73. UART Clock CK_UART and Data Frame Timing

Table 44. Baud Rate Deviation Error Calculation – CK_UART = 40 MHz

Baud Rate CK_UART = 40 MHz

No.

5

6

7

3

4

1

2

8

9

10

Kbps

2.4

9.6

19.2

57.6

115.2

230.4

460.8

921.6

2250

3000

Actual

2.4

9.6

19.2

57.6

115.3

229.9

459.8

930.2

2222.2

—

BRD

16667

4167

2083

694

347

174

87

43

18

—

Deviation

Error Rate

0.00%

-0.01%

0.02%

0.06%

0.06%

-0.22%

-0.22%

0.94%

-1.23%

—

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No.

7

8

9

10

5

6

3

4

1

2

Kbps

2.4

9.6

19.2

57.6

115.2

230.4

460.8

921.6

2250

3000

Actual

2.4

9.6

19.2

57.6

115.1

230.8

461.5

923.1

2285.7

3000.0

BRD

20000

5000

2500

833

417

208

104

52

21

16

Deviation

Error Rate

0.00%

0.00%

0.00%

0.04%

-0.08%

0.16%

0.16%

0.16%

1.59%

0.00%



No.

8

9

6

7

10

3

4

5

1

2

Kbps

2.4

9.6

19.2

57.6

115.2

230.4

460.8

921.6

2250

3000

Actual

2.4

9.6

19.2

57.6

115.2

230.8

461.5

923.1

2222.2

3000.0

BRD

25000

6250

3125

1042

521

260

130

65

27

20

Deviation

Error Rate

0.00%

0.00%

0.00%

-0.03%

-0.03%

0.16%

0.16%

0.16%

-1.23%

0.00%

Interrupts and Status

The UART can generate interrupts when the following events occur and the corresponding interrupt enable bits are set:

▆

▆

▆

▆

Receiver line status interrupts: The interrupts are generated when the UART receiver overrun error, parity error, framing error and break event occur.

Transmit data register empty interrupt: An interrupt is generated when the content of the transmit data register is transferred to the transmit shift register (TSR).

Transmit complete interrupt: An interrupt is generated when the transmit data register (TDR) is empty and the content of the transmit shift register (TSR) is also completely shifted.

Receive data ready interrupt: An interrupt is generated when the content of the receive shift register (RSR) has been transferred to the URDR register and is ready to read.

PDMA Interface

The PDMA interface is integrated in the UART. The PDMA function can be enabled by setting the TXDMAEN or RXDMAEN bit in the URCR register to 1 in the transmit or receive mode respectively. When the UART transmit data register (TDR) is empty and the TXDMAEN bit is

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Cortex ® -M0+ MCU set to 1, the PDMA function will be activated to move data from a source location into the UART transmit data register (TDR).

Similarly, when the received data has been in the UART receive data register (RDR) and the

RXDMAEN bit is set to 1, the PDMA function will be activated to move data from the UART receive data register (RDR) to a specific destination location. For a more detailed description about the PDMA configurations, refer to the PDMA chapter.

Register Map

The following table shows the UART registers and reset values.

Table 47. UART Register Map

Register Offset

URDR

URCR

URIER

URSIFR

0x000

0x004

0x00C

0x010

Description

UART Data Register

UART Control Register

UART Interrupt Enable Register

UART Status & Interrupt Flag Register

URDLR

URTSTR

0x024

0x028

UART Divider Latch Register

UART Test Register

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0180

0x0000_0010

0x0000_0000


UART Data Register – URDR

The register is used to access the UART transmitted and received data.

Offset: 0x000


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

15 14 13 12

Reserved

11 10 9 8

DB

RW 0

7 6 5 4 3

DB

2 1 0


Bits

[8:0]

Field

DB

Descriptions

By reading this register, the UART will return a 7, 8 and 9-bit received data. The DB field bit 8 is valid for the 9-bit mode only and is fixed at 0 for the 8-bit mode. For the

7-bit mode, the DB[6:0] field contains the available bits.

By writing to this register, the UART will send out 7, 8 or 9-bit transmitted data. The

DB field bit 8 is valid for the 9-bit mode only and will be ignored for the 8-bit mode.

For the 7-bit mode, the DB[6:0] field contains the available bits.

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UART Control Register – URCR

The register specifies the serial parameters such as data length, parity and stop bit for the UART.

Offset: 0x004


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

15

Reserved

14

BCB

13

SPE

12

EPE

11

PBE

10

NSB

9

7


6 5 4 3

RXDMAEN TXDMAEN URRXEN URTXEN Reserved

2

TRSM

1 0

Reserved

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0

8

WLS

Bits

[14]

[13]

[12]

[11]

[10]

[9:8]

Field

BCB

SPE

EPE

PBE

NSB

WLS

Descriptions

Break Control Bit

When this bit is set 1, the serial data output on the UART TX pin will be forced to the Spacing State (logic 0). This bit acts only on the UART TX output pin and has no effect on the transmitter logic.

Stick Parity Enable

0: Disable stick parity

1: Stick Parity bit is transmitted

This bit is only available when the PBE bit is set to 1. If both the PBE and SPE bits are set to 1 and the EPE bit is cleared to 0, the transmitted parity bit will be stuck to

1. However, when the PBE and SPE bits are set to 1 and also the EPE bit is set to

1, the transmitted parity bit will be stuck to 0.

Even Parity Enable

0: Odd number of logic 1’s are transmitted or checked in the data word and parity bits

1: Even number of logic 1’s are transmitted or checked in the data word and parity bits

This bit is only available when the PBE bit is set to 1.

Parity Bit Enable

0: Parity bit is not generated (transmitted data) and checked (receive data) during transfer

1: Parity bit is generated and checked during transfer

Note: When the WLS field is set to “10” to select the 9-bit data format, writing to the

PBE bit has no effect.

Number of STOP bit

0: One STOP bit is generated in the transmitted data

1: Two STOP bits are generated when 8-bit or 9-bit word length is selected

Word Length Select

00: 7 bits

01: 8 bits

10: 9 bits

11: Reserved

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Bits

[7]

[4]

[2]

[6]

[5]


RXDMAEN UART RX DMA Enable

0: Disable

1: Enable

TXDMAEN UART TX DMA Enable

0: Disable

1: Enable

URRXEN UART RX Enable

0: Disable

1: Enable

URTXEN

TRSM

UART TX Enable

0: Disable

1: Enable

Transfer Mode Selection

This bit is used to select the data transfer protocol.

0: LSB first

1: MSB first

UART Interrupt Enable Register – URIER

This register is used to enable the related UART interrupt function. The UART module generates interrupts to the controller when the corresponding events occur and the corresponding interrupt enable bits are set.

Offset: 0x00C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

Reserved

10 9 8

Type/Reset

Type/Reset

7

Reserved

6

BIE

5

FEIE

4

PEIE

3

OEIE

2

TXCIE

1

TXDEIE

0

RXDRIE


Bits

[6]

[5]

Field

BIE

FEIE

Descriptions

Break Interrupt Enable

0: Disable

1: Enable

If this bit is set, an interrupt will be generated when the BII bit in the URSIFR register is set.

Framing Error Interrupt Enable

0: Disable

1: Enable

If this bit is set, an interrupt will generated when the FEI bit in the URSIFR register is set.

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Bits

[4]

[3]

[2]

[1]

[0]

Field

PEIE

OEIE

TXCIE

TXDEIE

RXDRIE

Descriptions

Parity Error Interrupt Enable

0: Disable

1: Enable

If this bit is set, an interrupt will be generated when the PEI bit in the URSIFR register is set.

Overrun Error Interrupt Enable

0: Disable

1: Enable

If this bit is set, an interrupt will be generated when the OEI bit in the URSIFR register is set.

Transmit Complete Interrupt Enable

0: Disable

1: Enable

If this bit is set, an interrupt will be generated when the TXC bit in the URSIFR register is set.

Transmit Data Register Empty Interrupt Enable

0: Disable

1: Enable

If this bit is set, an interrupt will be generated when the TXDE bit in the URSIFR register is set.

Receive Data Ready Interrupt Enable

0: Disable

1: Enable

If this bit is set, an interrupt will be generated when the RXDR bit in the URSIFR register is set.

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UART Status & Interrupt Flag Register – URSIFR

This register contains the corresponding UART status.

Offset: 0x010


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15

Type/Reset

7

TXDE

Type/Reset RO 1

14 13 12

Reserved

11 10 9

6 5

Reserved RXDR

4

BII

3

FEI

2

PEI

1

OEI

RO 0 WC 0 WC 0 WC 0 WC 0

8

TXC

RO 1

0

Reserved

Bits

[8]

[7]

[5]

[4]

[3]

Field

TXC

TXDE

RXDR

BII

FEI

Descriptions

Transmit Complete

0: Either the transmit data register (TDR) or transmit shift register (TSR) is not empty

1: Both the transmit data register (TDR) and transmit shift register (TSR) are empty

When this bit is set, an interrupt will be generated if the TXCIE bit in the URIER register is set to 1. This bit is cleared by a write to the URDR register with new data.

Transmit Data Register Empty

0: Transmit data register is not empty

1: Transmit data register is empty

The TXDE bit is set by hardware when the content of the transmit data register is transferred to the transmit shift register (TSR). An interrupt will be generated if the

TXEIE bit in the URIER register is set to 1. This bit is cleared by a write to the URDR register with new data.

RX Data Ready

0: Receive data register is empty

1: The received data in receive data register is ready to read

This bit is set by hardware when the content of the receive shift register (RSR) has been transferred to the URDR register. An interrupt will be generated if the RXDRIE bit in the URIER register is set to 1. It is cleared by a read to the URDR register.

Break Interrupt Indicator

This bit is set to 1 whenever the received data input is held in the “spacing state”

(logic 0) for longer than a full character transmission time, which is the total time of

“start bit” + data bits + “parity” + “stop bits” duration. Writing 1 to this bit clears the flag.

Framing Error Indicator

This bit is set 1 whenever the received character does not have a valid stop bit, which means, the stop bit following the last data bit or parity bit is detected as logic

0. Writing 1 to this bit clears the flag.

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Bits

[2]

[1]

Field

PEI

OEI

Descriptions

Parity Error Indicator

This bit is set to 1 whenever the received character does not have a valid parity bit.

Writing 1 to this bit clears the flag.

Overrun Error Indicator

An overrun error will occur only after the receive data register is full and when the next character has been completely received in the receive shift register. The character in the receive shift register will be overwritten when a new character is received in the receive shift register after an overrun event occurs, but the data in the receive shift register will not be transferred to the receive data register. The OEI bit is used to indicate event as soon as it happens. Writing 1 to this bit clears the flag.

UART Divider Latch Register – URDLR

The register is used to determine the UART clock divided ratio to generate the appropriate baud rate.

Offset: 0x024


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

BRD

10 9 8


7 6 5 4 3

BRD

2 1 0


Bits

[15:0]

Field

BRD

Descriptions

Baud Rate Divider

The 16 bits define the UART clock divider ratio.

Baud Rate = CK_UART / BRD

Where the CK_UART clock is the clock connected to the UART module.

BRD = 16 ~ 65535 for the UART mode

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UART Test Register – URTSTR

This register controls the UART debug mode.

Offset: 0x028


31 30 29

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

Type/Reset

Bits

[1:0]

Field

LBM

Descriptions

Loopback Test Mode Select

00: Normal Operation

01: Reserved

10: Automatic Echo Mode

11: Loopback Mode

26

18

10

25

17

9

24

16

8

2 1 0

LBM

RW 0 RW 0

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17

Smart Card Interface (SCI)

Introduction

The Smart Card Interface, SCI, is compatible with the ISO 7816-3 standard. This interface includes functions for card Insertion/Removal detection, SCI data transfer control logic and data buffers, internal Timer Counters and corresponding control logic circuits to perform the required Smart

Card operations. The Smart Card interface acts as a Smart Card Reader to facilitate communication with the external Smart Card. The overall functions of the Smart Card interface are controlled by a series of registers including control and status registers together with several corresponding interrupts which are generated to get the attention of the microcontroller for SCI transfer status.

As the complexity of ISO7816-3 standard data protocol does not permit comprehensive specifications to be provided in this datasheet, the reader should therefore consult other external information for a detailed understanding of this standard.

f

PCLK

6-bit Prescaler f

PSC_CK f

PSC_CK

11-bit Elementary

Time Unit

(ETU) f

ETU f

ETU

24-bit

Waiting Time

Counter

(WT) f

WT

9-bit

Guard Time

Counter

(GT) f

GT

SCI transfer

Control

Circuitry

Control

Circuitry

SCI TX/RX buffers

Clock

Control

I/O

Control

SCI_CLK

SCI_DIO

Interrupt Control

SCI Interrupt to NVIC

Figure 74. SCI Block Diagram

Card

Detection

SCI_DET

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Features

▆

▆

▆

▆

▆

▆

▆

▆

▆

Supports ISO 7816-3 standard

Character Transfer Mode

1 transmit buffer and 1 receive buffer

11-bit ETU (elementary time unit) counter

9-bit guard time counter

24-bit general purpose waiting time counter

Parity generation and checking

Automatic character repetition on parity error detection in transmission and reception modes

Supports PDMA access at a transmission or reception completion


To communicate with an external Smart Card, the integrated Smart Card Interface has a series of external pins known as SCI_CLK, SCI_DIO and SCI_DET. The SCI_CLK pin is the clock output signal used to communicate with the external Smart Card together with the serial data pin named SCI_DIO. The operation of the SCI_CLK and SCI_DIO pins can be selected to be the SCI data Transfer Mode which is driven automatically by the SCI control circuits or to be the Manual mode which is controlled by configuring the internal CLK and DIO register bits respectively by the application program. The SCI_DET pin is the external card detection input pin. Insertion or removal of the external Smart Card can be automatically detected and generate an interrupt signal which is sent to the microcontroller if the corresponding interrupt function is enabled.

For proper data transfer, some timing related procedures must be executed before the Smart

Card Interface can begin to communicate with the external card. There are three counters named

Elementary Time Unit Counter, ETU, Guard Time Counter, GT, and Waiting Time Counter, WT, which are used for the timing related functions in Smart Card Interface data transfer operations.

Elementary Time Unit Counter

The Elementary Time Unit, ETU, is an 11-bit up-counting counter which generates a clock denoted as f

ETU

to be used as the operating frequency source for the SCI data transmission and reception. The clock source of the ETU comes from the Smart Card clock , named f

PSC_CK

, which is derived from the 6-bit prescaler. The data transfer of the SCI is a character frame based protocol, f which basically consists of a Start bit, 8-bits of data and a Parity bit. The time period , t

ETU

(1/

ETU

), generated by the ETU, is the time unit for a character bit. There is a register related to the

Elementary Time Unit known as the ETUR register which stores the expected contents of the

ETU. Each time the ETUR register is written, the ETU circuitry will reload the new written value and restart counting. The elementary time unit t

ETU

is obtained from the following formula which defines the bit rate in the ISO 7816-3 standard specification.

1etu = t

ETU

=

F i

D i

× f

1

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▆

▆

▆

▆ etu is the nominal duration of the data bit on the signal SCI_DIO provided to the card by the interface

Di is the bit-rate adjustment factor

Fi is the clock rate conversion factor f is the frequency value of the clock signal SCI_CLK provided to the card by the interface

D i is an encoded decimal value based on a 4-bit field, named DI, as represented in the accompanying table.

Table 48. DI Field Based Di Encoded Decimal Values

DI field 0001 0010 0011 0100 0101 0110 0111 1000 1001

Di (decimal) 1 2 4 8 16 32 64 12 20

F i is an encoded decimal value based on a 4-bit field, named FI, as represented in the following table.

Table 49. FI Field Based F i

Encoded Decimal Values

FI field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101

Fi (decimal) 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048

The values of FI and DI, as they appear in the preceding tables, will be obtained from the Answerto-Reset packet sent from the external Smart Card to the Smart Card Interface the first time the external Smart Card is inserted. When the SCI receives the FI and DI information, the Fi and

Di value s can be obtained by looking up the preceding two tables. After the Fi and Di values are obtained, the value which should be written into the ETUR register can be calculated by Fi/Di. The following table shows the possible ETU values obtained by the F i

/D i

ratio.

64

12

20

16

32

4

8

Table 50. Possible ETU Values Obtained with the Fi/Di Ratio

Fi

Di

1

2

372 558 744 1116 1488 1860 512 768 1024 1536 2048

372

186

558

279

744 1116 1488 1860 512

372 558 744 930 256

93 139.5

186

46.5

69.75

93

279 372 465

139.5

186 232.5

23.25 34.87

46.5

69.75

93 116.2

11.62 17.43 23.25 34.87

46.5

58.13

128

64

32

16

5.81

8.72

11.63 17.44 23.25 29.06

31 46.5

62 93 124 155

8

42.66

18.6

27.9

37.2

55.8

74.4

93

12

64

25.6

38.4

768 1024 1536 2048

384 512 768 1024

192

96

48

24

256

128

64

32

384

192

96

48

512

256

128

64

16

85.33

51.2

24

128

76.8

32

170.6

102.4

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Compensation mode

As the value of the ETUR register is obtained by the above procedure, the calculation results of the value may not be an integer. If the calculation result is not an integer and is less than the integer n but greater than the integer (n-1), either the integer n or (n-1) should be written into the ETUR register depending upon whether the result is closer to integer n or (n-1). The integer n mentioned here is a decimal.

If the calculation result is close to the value of (n-0.5), the compensation mode should be enabled by setting the compensation enable control bit, COMP, in the ETUR register to 1 for successful data transfer. When the result is close to the value of (n-0.5) and the compensation mode is enabled, the value written into the ETUR register should be n. The ETU circuitry will then generate the time unit sequence with n clock cycles and next (n-1) clock cycles alternately and so on. This results in an average time unit of (n-0.5) clock cycles and allows a time granularity down to a half clock cycle. Note that the ETU will reload the ETUR register value and restart counting at the time when the Start bit appears in the SCI data Transfer Mode.

SCI_DIO

Start bit Parity bit

Data bits

P n n t

ETU n n

Character n n n n n n

SCI_CLK COMP=0

SCI_CLK n n-1 n n-1 n n-1 n n-1 n n-1

SCI_CLK n-1 n n-1 n n-1 n n-1 n n-1

Note: The ETUR register value = n, i.e. 1 t

ETU

= n clocks in this example.

n

Figure 75. Character Frame and Compensation Mode

COMP=1

(Average time unit= n-0.5)

Guard Time Counter

The Guard Time Counter, GT, is a 9-bit up-counting counter which generates a minimum time duration known as a character frame, denoted as t

GT

, between the leading edges of two consecutive characters in the SCI data transfer. The clock source of the guard time counter comes from the

ETU , named f

ETU

in the block diagram. There is a register related to the guard time counter known as the GTR register, which stores the expected value of the guard time counter. The guard time value will be reloaded at the end of the current guard time period. Note that the guard time between the last character received from the Smart Card and the next character transmitted by the SCI circuitry which should be properly managed by the application program. There is no guard time insertion when the first character is transmitted.

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Start

Char 0

SCI_DIO t

GT

Smart Card → SCI

Figure 76. Guard Time Duration

Start

Char 1 t

GT

Start Start

Char n t

GT t

GT

Start

Char 0 t

GT

SCI → Smart Card

Start

Char 1 t

GT

Start

SCI_DIO

Waiting Time Counter

The Waiting Time counter, WT, is a 24-bit down counting counter which generates a maximum time duration, denoted as t from the ETU

WT

, for data transfer. The clock source of the waiting time counter comes

and is named f

ETU

.

There is a register for the waiting time counter known as the WTR register which stores the expected waiting time counter value. The waiting time counter can be used in both the SCI data

Transfer Mode and manual mode and can reload the value for specific conditions. The function of the waiting time counter is controlled by the WTEN bit in the CR register. When the SCI is configured to be operated in the SCI data Transfer Mode and the waiting time counter is enabled by setting the WTEN bit to 1, the updated WTR register value will be loaded into the waiting time counter when the Start bit is detected. Note that the WTEN bit should not be set to 1 to enable the waiting time counter in the SCI data Transfer Mode until after the external Smart Card is inserted.

If the SCI is configured to operate in the manual mode, the waiting time counter can be used as a general purpose timer and this timer is enabled or disabled by setting or clearing the WTEN bit.

The updated WTR register value will not be loaded into the waiting time counter if the waiting time counter is enabled. When the waiting time counter is disabled by setting the WTEN bit to 0 and an updated value is written into the WTR register, the new value will immediately be loaded into the waiting time counter and then the counter will start to count after the WTEN bit is again set to 1.

Software can change the Waiting Time value on-the-fly. For example, in T = 1 mode, the value of the Block Waiting Time, t

BWT

, should be written into the WTR register before the Start bit of the last transmitted character occurs. After the transmission of the last character is completed, software should write the Character Waiting Time value, t

CWT

, into the WTR register.

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SCI_DIO Char 0

SCI → Smart

Card

Program the BWT

Start bit

Char 1

Program the CWT

Char n t

BWT

BWT is reloaded on Start bit

Start bit

Char 0 t

CWT

Smart Card → SCI

Figure 77. Character and Block Waiting Time Duration – CWT and BWT

Char 1 SCI_DIO

Card Clock and Data Selection

The SCI communicates with an external Smart Card using a series of external pins. These are the serial data pin, SCI_DIO, output clock pin, SCI_CLK, and the Card Detection input pin, SCI_DET.

The SCI serial data pin, named SCI_DIO, can be controlled by the SCI hardware circuitry or the software control bits depending upon whether the SCI is operated in the SCI Transfer Mode or in the Manual Mode. The mode selection is determined by the SCIM bit in the CR register. The SCI_

DIO pin status is controlled by the CDIO bit in the CCR register when the SCI is configured to operate in the Manual mode by clearing the SCIM bit in the CR register. In the Manual Mode the

SCI_DIO pin status is a copy of the CDIO bit. However, when the SCI is configured to operate in the SCI Transfer Mode, the SCI_DIO pin status is determined by the SCI transfer circuitry.

The SCI clock output pin named SCI_CLK can be controlled by the 6-bit SCI prescaler or the software control bits depending upon the condition of the CLKSEL bit in the CCR register. The

SCI_CLK pin status is controlled by the CCLK bit in the CCR register when the CLKSEL bit is cleared to 0. The SCI_CLK pin status is a copy of the CCLK bit. However, when the CLKSEL bit is set to 1, the SCI_CLK signal is sourced from the 6-bit prescaler output. The prescaler division ratio is determined by the PSC field in the PSCR register.

Card Detection

When an external Smart Card is inserted, the internal card detector can detect this insertion operation and generate a card insertion interrupt if the corresponding interrupt enable control bit, CARDIRE, in the IER register is set to 1. Similarly, if the card is removed, the internal card detector can also detect the removal and consequently generate a card removal interrupt when the corresponding interrupt function is enabled by setting the control bit, CARDIRE, in the IER register, to 1.

The card detector can support two kinds of card detect switch mechanisms. One is a normally open switch mechanism when the card is not present and the other is a normally closed switch mechanism. After noting which card detect switch mechanism type is used, the card switch selection should be configured by setting the selection bit, DETCNF, in the CR register to correctly detect the card presence. No matter what type of the card switch is selected, by configuring the

DETCNF bit, the card Insertion/Removal flag, CPREF, in the SR register will be set to 1 when the card is actually present on the SCI_DET pin. Note that there are no hardware de-bounce circuits in the card detector. Any change of the SCI_DET pin level will cause the CPREF bit to change. The required de-bounce time should be handled by the application program.

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CPREF

Edge

Detection

Card Insertion / Removal

Interrupt request

0

1

SCI_DET

CARDIRE

Figure 78. SCI Card Detection Diagram

DETCNF

SCI Data Transfer Mode

The SCI data transfer with the external Smart Card is implemented with two operating modes. One is the SCI mode while the other is the Manual Mode. The data Transfer Mode is selected by the

SCI mode selection bit, SCIM, in the CR register. When the SCIM bit is set to 1, the SCI mode is enabled and data will automatically be transferred by the SCI transfer circuitry. Otherwise, data transfer operates in the Manual Mode if the SCIM bit is cleared to 0. The SCI transfer interface is a half-duplex interface and communicates with the external Smart Card via the SCI_CLK and SCI_

DIO pins. After a reset condition the SCI transfer interface is in the reception mode but the SCI transfer operation is disabled. When the SCI mode is enabled, data transfer is driven by the SCI transfer circuitry automatically through the SCI_CLK and SCI_DIO pins.

There are two data registers related to data transmission and reception, TXB and RXB, which store the data to be transmitted and received respectively. If a character is written into the TXB register in the SCI Transfer Mode, the SCI transfer interface will automatically switch to the Transmission

Mode from the reception mode after a reset. When the SCI transmission or reception has finished, the corresponding request flag, named TXCF or RXCF, in the SR register is set to 1. If the transmit buffer is empty, the transmit buffer empty flag, TXBEF, in the SR register will be set to 1.

Parity Check Function

The SCI transfer interface supports a parity generator and a parity check function. As the parity error occurs during a data transfer, the corresponding request flag, named PARF in the SR register, will be set to 1. Once the PARF bit is set to 1, the parity error pending flag, PARP, in the

IPR register will also be set to 1 if the relevant interrupt control bit, PARE, in the IER register is enabled.

If the data transmitted by the SCI is received by the external Smart Card without a parity error, the

SCI transmission request flag, TXCF, will be set to 1 and the SCI parity error request flag, PARF, will be cleared to 0. If the data transmitted by the external Smart Card is received by the SCI without a parity error, the SCI reception request flag, RXCF, will be set to 1 and the parity error flag, PARF, will remain zero.

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Repetition Function

There is a Character Repetition function supported by the SCI transfer circuitry when a parity error occurs. The Character Repetition function is enabled by setting the CREP bit in the CR register to 1. A repetition function will then be activated when a parity error occurs during a data transfer.

The repetition time number can be selected to be 4 or 5 by configuring the RETRY bit in the CR register.

When the CREP bit is set to 1, the character repetition function will be activated. Taking a 4 time repetition as an example, when the CREP bit is set to 1 and the RETRY bit is set to 1, in the

Transmission Mode, the SCI will repeatedly transmit the data a maximum of 4 times when an error signal occurs. However, if the SCI is informed that there is still an error signal during the 4 transmissions, the parity error flag PARF will be set to 1 after the same data has been transmitted

4 times but the TXCF flag will not be set. At this time the data in the transmit buffer will be loaded into the transmit shift register and the transmit buffer will be empty which will result in the

TXBEF flag being set to 1.

Similarly, when the SCI operates in the reception mode, it will inform the external Smart Card that there is a parity error for a maximum of 4 times if the character repetition function is enabled. If the SCI informs the external Smart Card that there is still an error signal for the 4 receptions, the parity error flag, PARF, will be set to 1 together with the reception request flag, RXCF.

If the CREP bit is cleared to 0, the character repetition function will be disabled. When the SCI operates in the reception mode, both the PARF and RXCF bits will be set to 1 as data with a parity error has been received. If the SCI is informed that there is a parity error in the Transmission

Mode, the PARF bit will be set to 1 but the TXCF bit will not be set.

Manual Data Transfer Mode

When the SCIM bit is cleared to 0, data will be transferred in the Manual Mode. In the Manual

Mode, the data is controlled by the control bit, CDIO, in the CCR register. The CDIO bit value will be reflected immediately on the SCI_DIO pin in the Manual Mode. Note that in the Manual

Mode the character repetition function can not be used as well as the related flags and all the data transfer is handled by the application program. The clock used to drive the external Smart Card that appears on the SCI_CLK pin can be derived from the internal clock source , which is the 6-bit prescaler output, f

PSC_CK

, or from the control bit, CCLK, in the CCR register . The clock source is selected using the bit, CLKSEL, in the CCR register. When CLKSEL bit is set to 1, the clock used to drive the Smart Card will be sourced from the 6-bit prescaler output, f managed manually, the CLKSEL bit should first be cleared to 0 and then the value of the CCLK bit will be present in the SCI_CLK pin.

PSC_CK

. If the clock is to be

Data Transfer Direction Convention

If the direction convention used by the Smart Card is the same as the convention used by the SCI, the SCI will generate a reception interrupt if the reception interrupt is enabled without a parity error flag. Otherwise, the SCI will generate a reception interrupt and the parity error flag will be asserted. By checking the parity error flag, the SCI can know if the data direction convention is correct or not.

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Interrupt Generator

There are several conditions for the SCI to generate an SCI interrupt. When these conditions are met, an interrupt signal will be generated to obtain the attention of the microcontroller. These conditions are a Smart Card Insertion/Removal, a Waiting Time Counter Underflow, a Parity error, an end of a Character Transmission or Reception and an empty Transmit buffer. When a

Smart Card interrupt is generated by any of these conditions, then if the SCI global interrupt and the corresponding SCI interrupt are together enabled, the program will jump to the corresponding interrupt vector where it can be serviced before returning to the main program.

For SCI interrupt events, there are corresponding pending flags which can be masked by the relevant interrupt enable control bit. When the related interrupt enable control is disabled, the corresponding interrupt pending flag will not be affected by the request flag and no interrupt will be generated. If the related interrupt enable control is enabled, the relevant interrupt pending flag will be affected by the request flag and then the interrupt will be generated. The pending flag register, named IPR, is read only and once the pending flag is read by the application program, it will be automatically cleared while the related request flag should be cleared by the application program manually.

For an SCI Interrupt to be serviced, in addition to the bits for the corresponding interrupt enable control in the SCI being set, the SCI global interrupt enable control bit in the NVIC must also be set. If this SCI global interrupt control bit is not set, then no SCI interrupt will be serviced.

Card Insertion/Removal

Request flag CPREF

Transmit Buffer Empty request flag TXBEF

End of Transmission

Request flag TXCF

End of Reception

Request flag RXCF

Parity Error

Request flag PARF

WTC Underflow

Request flag WTF

CSR Register

Figure 79. SCI Interrupt Structure

CARDIRE

0

1

0

1

TXBEE

0

1

TXCE

0

1

RXCE

0

1

PARE

0

1

WTE

CIER Register

Card Insertion/Removal pending flag CARDIRP

Transmit Buffer Empty pending flag TXBEP

End of Transmission pending flag TXCP

End of Reception pending flag RXCP

Parity Error pending flag PARP

WTC Underflow pending flag WTP

CIPR Register

SCI Interrupt Signal sent to NVIC

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PDMA Interface

The PDMA interface is integrated in the SCI module. The PDMA function can be enabled by setting the TXDMA or RXDMA bit to 1 in the transmitter or receiver mode respectively. When the transmit buffer is empty which results in the transmit buffer empty flag, TXBEF, being asserted and the TXDMA bit is set to 1, the PDMA function will be activated to move data from a certain memory location into the SCI Transmit buffer. Similarly, when the SCI receives a character which results in the character received flag, RXCF, being asserted and the RXDMA bit is set to 1, the

PDMA function will be activated to move data from the SCI Receive buffer to a specific memory location.

For a more detailed descriptions on the PDMA configurations, refer to the PDMA chapter.

Register Map

There are several registers associated with the Smart Card function. Some of these registers control the SCI overall function as well as the interrupts, while some of the registers contain the status bits which indicate the Smart Card data transfer situation and error conditions. Also there are two registers for the SCI transmission and reception respectively to store the data received from or to be transmitted to the external Smart Card. The following table shows the SCI register list and reset values.

Table 51. SCI Register Map

Register

CR

SR

CCR

ETUR

Offset

0x000

0x004

0x008

0x00C

Description

SCI Control Register

SCI Status Register

SCI Contact Control Register

SCI Elementary Time Unit Register

GTR

WTR

IER

IPR

TXB

RXB

PSCR

0x010

0x014

0x018

0x01C

0x020

0x024

0x028

SCI Guard Time Register

SCI Waiting Time Register

SCI Interrupt Enable Register

SCI Interrupt Pending Register

SCI Transmit Buffer

SCI Receive Buffer

SCI Prescaler Register

Reset Value

0x0000_0000

0x0000_0080

0x0000_0008

0x0000_0174

0x0000_000C

0x0000_2580

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

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SCI Control Register – CR

This register contains the SCI control bits.

Offset: 0x000


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

Type/Reset

15 14 13 12

Reserved

11 10 9

RXDMA

8

TXDMA

7 6

Reserved DETCNF

5

ENSCI

4

RETRY

3

SCIM

2

WTEN

RW 0 RW 0

1

CREP

0

CONV


Bits

[9]

[8]

[6]

[5]

[4]

Field

RXDMA

TXDMA

DETCNF

ENSCI

RETRY

Descriptions

SCI reception DMA request enable

0: SCI reception DMA request is disabled

1: SCI reception DMA request is enabled

SCI transmission DMA request enable control

0: SCI transmission DMA request is disabled

1: SCI transmission DMA request is enabled

Card switch type selection

0: Switch is normally opened if no card is present

1: Switch is normally closed if no card is present

DETCNF

0

0

SCI_DET pin

1

0

STATUS

No card insert

Card insert

1

1

1

0

Card insert

No card insert

This bit is set and cleared by the application program to configure the card detector switch type.

SCI finite state machine enable bit

0: SCI FSM is disabled and forced to its initial state

1: SCI FSM is enabled

Character transfer repetition time selection for a parity error condition

0: Data transfer 5 times when parity error occurs

1: Data transfer 4 times when parity error occurs

The bit is available only when the CREP bit is set to 1. When this bit is set to 1, the data will be transmitted or received 4 times once a parity error occurs. If the bit is cleared to 0, the data will be transferred 5 times if a parity error occurs.

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Bits

[3]

[2]

[1]

[0]

Field

SCIM

WTEN

CREP

CONV

Descriptions

SCI Mode Selection

0: SCI data transfer in manual mode

1: SCI data transfer in SCI mode

This bit is set and cleared by the application program to select the SCI data Transfer

Mode. If it is cleared to 0, the SCI_DIO pin status is the same as the value of the

CDIO bit in the CCR register. If it is set to 1, the SCI_DIO pin is driven by the internal

SCI control circuitry. Before the data transfer type is switched from the Manual Mode to the SCI Mode, the CDIO bit must be set to 1 to avoid an SCI malfunction.

Waiting Time Counter enable control

0: Waiting Time Counter stops counting

1: Waiting Time Counter starts counting

The WTEN bit is set and cleared by the application program. When the WTEN bit is cleared to 0, a write access to the WTR register will load the value into the waiting time counter. If it is set to 1, the waiting time counter is enabled and automatically reloaded with the value at each start bit occurrence.

Automatic character repetition enable control for a parity error condition

0: No retry on parity error

1: Automatic retry on parity error

The CREP bit is set and cleared by the application program. When the CREP bit is cleared to 0, both the RXCF and PARF flags will be set when a parity error occurs in the reception mode after the data is received. However, in the Transmission Mode, the PARF flag will be set but the TXCF flag will not be set when a parity error occurs.

If the CREP bit is set to 1, a character transfer will automatically be activated 4 or 5 times depending upon the RETRY bit value. In the Transmission Mode the character will be re-transmitted if the transmitted data has a parity error. Here the parity error flag, PARF, will be set at the end of the 4 th or 5 th transmission without the TXCF bit being set. In the reception mode if the received data has a parity error, the SCI will inform the external Smart Card for 4 or 5 times and then the PARF and RXCF flags will both be set at the end of the 4 th or 5 th reception.

Data direction convention select

0: LSB is transferred first; a data “1” is a logic high level on the SCI_DIO pin and the parity bit is added after the MSB.

1: MSB is transferred first; a data “1” is a logic low level on the SCI_DIO pin and the parity bit is added after the LSB.

This bit is set and cleared by the application program to select if the data is transmitted LSB or MSB first. When the data direction convention is the same as the data direction specified by the external Smart Card, only the RXCF flag will be set to 1 without a parity error. Otherwise, both the RXCF and PARF flags will be set to 1 after the data is received.

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SCI Status Register – SR

This register contains the SCI status bits.

Offset: 0x004


31 30

Type/Reset

23 22

Type/Reset

15 14

Type/Reset

7

TXBEF

6

CPREF

Type/Reset RO 1 RO 0

29

21

13

5

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

12 11

Reserved

10 9 8

4 reserved

3

WTF

2

TXCF

1

RXCF

0

PARF

RO 0 W0C 0 RO 0 W0C 0

Bits

[7]

[6]

[3]

[2]

Field

TXBEF

CPREF

WTF

TXCF

Descriptions

Transmit Buffer Empty Request Flag

0: Transmit buffer is not empty

1: Transmit buffer is empty

This bit is used to indicate if the transmit buffer is empty and is set or cleared by hardware automatically.

Card Presence Request Flag

0: No card is present

1: A card is present

This bit is used to indicate if a card is present and is set or cleared by hardware automatically. The card presence detection function is enabled after the ENSCI bit is set.

Waiting Time Counter Underflow Request Flag

0: No Waiting Time Counter underflow

1: The Waiting Time Counter underflows

This bit is set and cleared by the application program and indicates if the Waiting

Time Counter underflows.

Character Transmission Request Flag.

0: No character transmitted

1: A character has been transmitted

This bit is set by hardware and cleared by writing a “0” into it.

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Bits

[1]

[0]

Field

RXCF

PARF

Descriptions

Character Received Request Flag.

0: No character received

1: A character has been received

This bit is set by hardware and cleared after a read access to the RXB register by the application program. The RXCF bit will be set to 1 when a character is received regardless of the result of the parity check.

When the character has been received, the received data stored in the RXB register should be moved to the data memory as specified by the application program. If the contents of the RXB register are not read before the end of the next character to be shifted in, the data stored in the RXB register will be overwritten.

Parity Error Request Flag.

0: No parity error occurs

1: Parity error has occurred

This bit is set by hardware and cleared by writing a “0” into it. When a character is received, the parity check circuitry will check that the parity is correct or not. If the result of the parity check is not correct, the parity error request flag, PARF, will be set to 1. Otherwise, the PARF bit will remain zero. In the Transmission Mode when the SCI is informed that there is a parity error in the transmitted character by the external Smart Card, the PARF bit will also be set to 1.

SCI Contact Control Register – CCR

This register specifies the SCI pin setting and clock selection.

Offset: 0x008


30 29 28 31

Type/Reset

23

Type/Reset

15

Type/Reset

7

CLKSEL

Type/Reset RW 0

22

14

6

21

13

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

11

Reserved

10

3

CDIO

2

CCLK

RW 1 RW 0

Bits

[7]

Field

CLKSEL

25

17

9

1

24

16

8

0

Reserved

Descriptions

Card Clock Selection

0: The CCLK bit content is present on the external SCI_CLK pin

1: The clock output on the external SCI_CLK pin is sourced from the f

PSC_CK by the application program. It is recommended that to activate the clock at a known level a certain value should be first programmed into the CCLK bit before the

CLKSEL bit is switched from 1 to 0.

clock

This bit is used to select the external SCI_CLK pin clock source. It is set and cleared

Rev. 1.00 330 of 637 December 28, 2020

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Cortex ® -M0+ MCU

Bits

[3]

[2]

Field

CDIO

CCLK

Descriptions

SCI_DIO pin control

0: SCI_DIO pin is logic level 0

1: SCI_DIO pin in open-drain condition

This bit is available only when the SCIM bit in the CR register is cleared to 0 to configure the SCI to operate in the Manual Transfer Mode. It is set and cleared by application program to control the external SCI_DIO pin status in the Manual Mode.

Reading this bit will return the present status of the SCI_DIO pin.

SCI_CLK pin control.

0: SCI_CLK pin is logic level 0

1: SCI_CLK pin is logic level 1

This bit is available when the SCI operates in the Manual Transfer Mode. It is set and cleared by application program to control the external SCI_CLK pin status in the

Manual Mode. Reading this bit will return the current value in the register and not the present status of the external SCI_CLK pin. To ensure that the clock remains at a known level a certain value should be first programmed into the CCLK bit before the CLKSEL bit is switched from 1 to 0.

SCI Elementary Time Unit Register – ETUR

The register specifies the value determined by the formula described in the ETU section. It also includes the

Compensation function enable control bit for the ETU time granularity.

Offset: 0x00C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15

COMP

Type/Reset RW 0

14 13 12

Reserved

11 10 9

ETU

8

RW 0 RW 0 RW 1

7 6 5 4 3

ETU

2 1 0


Bits

[15]

Field

COMP

Descriptions

Elementary Time Unit Compensation mode enable control

0: Compensation mode is disabled

1: Compensation mode is enabled

This bit is set and cleared by application program and used to control the ETU compensation function. For more details regarding the compensation function consult the Elementary Time Unit section.

Rev. 1.00 331 of 637 December 28, 2020

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Cortex ® -M0+ MCU

Bits

[10:0]

Field

ETU

Descriptions

ETU value for a character data bit

This field is configured by the application program to modify the ETU time duration.

Note that the value of ETU must be in the range of 0x00C to 0x7FF. To obtain the maximum ETU decimal value of 2048, a 0x000 value should be written into this bit field.

SCI Guard Time Register – GTR

This register specifies the guard time value obtained from the Answer-to-Reset packet described in the Guard

Time Counter section.

Offset: 0x010

Reset value: 0x0000_000C

31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

15

7

14

6

13

5

12

Reserved

4

11

3

GT

10

2

9

1

8

GT

RW 0

0


Bits

[8:0]

Field

GT

Descriptions

Character Guard Time value

This field is configured by the application program to modify the guard time duration.

The updated GT value will be loaded into the GT counter at the end of the current guard time period. Note that the GT value must be in the range from 0x00C to

0x1FF.

Rev. 1.00 332 of 637 December 28, 2020

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Cortex ® -M0+ MCU

SCI Waiting Time Register – WTR

This register specifies the waiting time value obtained from the Answer-to-Reset packet described in the Waiting

Time Counter section.

Offset: 0x014


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

WT

18 17 16


15 14 13 12 11

WT

10 9 8


7 6 5 4 3 2 1 0

WT


Bits

[23:0]

Field

WT

Descriptions

Character Waiting Time value expressed in ETU (0/16777215).

This field is configured by the application program to modify the waiting time duration. The reload conditions of the updated waiting time counter value are described in the waiting time counter section. Refer to the waiting time counter section for more details. Note that the WT value can range from 0x00_0000 to 0xFF_FFFF.

Rev. 1.00 333 of 637 December 28, 2020

32-Bit Arm ®

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Cortex ® -M0+ MCU

SCI Interrupt Enable Register – IER

This register specifies the interrupt enable control bits for all of the interrupt events in the SCI.

Offset: 0x018


29 31 30

Type/Reset

23 22

Type/Reset

15 14

Type/Reset

7 6

TXBEE CARDIRE


21

13

5

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

12 11

Reserved

10 9 8

4

Reserved

3

WTE

2

TXCE

1

RXCE

0

PARE

RW 0 RW 0 RW 0 RW 0

Bits

[7]

[6]

[3]

[2]

Field

TXBEE

Descriptions

Transmit buffer empty interrupt enable control

0: Disabled

1: Enabled

This bit is set and cleared by application program and is used to control the Transmit

Buffer Empty interrupt. If this bit is set to 1, the transmit buffer empty interrupt will be generated when the transmit buffer is empty.

CARDIRE Card Insertion / Removal interrupt enable control

0: Disabled

1: Enabled

This bit is set and cleared by application program and is used to control the card insertion/removal interrupt. If this bit is set to 1, the card insertion/removal interrupt will be generated when the external Smart Card is inserted or removed.

WTE Waiting Timer Underflow interrupt enable control

0: Disabled

1: Enabled

This bit is set and cleared by the application program and is used to control the

Waiting Timer underflow interrupt. If this bit is set to 1, the waiting time counter underflow interrupt will be generated when the waiting time counter underflows.

TXCE Character Transmission Completion interrupt enable control

0: Disabled

1: Enabled


Character Transmission Completion interrupt. If this bit is set to1, the Character

Transmission Completion interrupt will be generated at the end of the character transmission.

Rev. 1.00 334 of 637 December 28, 2020

32-Bit Arm ®

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Cortex ® -M0+ MCU

Bits

[1]

[0]

Field

RXCE

PARE

Descriptions

Character Reception Completion interrupt enable control

0: Disabled

1: Enabled


Character Reception Completion interrupt. If this bit is set to 1, the Character

Reception Completion interrupt will be generated at the end of the character reception.

Parity Error interrupt enable control

0: Disabled

1: Enabled

This bit is set and cleared by the application program and is used to control the parity error interrupt. if this bit is set to 1, the Parity Error interrupt will be generated when a parity error occurs.

SCI Interrupt Pending Register – IPR

This register contains the interrupt pending flags for all of the interrupt events in the SCI. These pending flags can be masked by the corresponding interrupt enable control bits.

Offset: 0x01C


29 31 30

Type/Reset

23 22

Type/Reset

15 14

Type/Reset

7 6

TXBEP CARDIRP

Type/Reset RC 0 RC 0

21

13

5

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

12 11

Reserved

10 9 8

4

Reserved

3

WTP

2

TXCP

1

RXCP

0

PARP

RC 0 RC 0 RC 0 RC 0

Bits

[7]

Field

TXBEP

Descriptions

Transmit Buffer Empty interrupt pending flag

0: No interrupt pending

1: Interrupt pending

This bit is set by hardware and cleared by a read access to this register using the application program. This bit is used to indicate if there is a Transmit Buffer Empty interrupt pending or not. If the Transmit Buffer is empty and the corresponding interrupt enable control bit is set to 1, this bit will be set to 1 to indicate that the transmit buffer empty interrupt is pending.

Rev. 1.00 335 of 637 December 28, 2020

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Cortex ® -M0+ MCU

Bits

[6]

[3]

[2]

[1]

[0]


CARDIRP Card Insertion/Removal interrupt pending flag



This bit is set by hardware and cleared by a read access to this register using the application program. It is used to indicate if there is an external Smart Card insertion/ removal interrupt pending or not. If an external Smart Card is inserted or removed and the corresponding interrupt enable control bit is set to 1, this bit will be set to 1 to indicate that the Card insertion/removal interrupt is pending.

WTP Waiting Timer Underflow interrupt pending flag



This bit is set by hardware and cleared by a read access to this register using the application program. It is used to indicate if there is a waiting time counter underflow interrupt pending or not. If the waiting time counter underflows and the corresponding interrupt enable control bit is set to 1, this bit will be set to 1 to indicate that the waiting time counter underflow interrupt is pending.

TXCP

RXCP

PARP

Character Transmission Completion interrupt pending flag



This bit is set by hardware and cleared by a read access to this register using the application program. It is used to indicate if there is a Character Transmission

Completion interrupt pending or not. If a character has been transmitted and the related interrupt enable control bit is set to 1, this bit will be set to 1 to indicate that the character transmission completion interrupt is pending.

Character Reception Completion interrupt pending flag



This bit is set by hardware and cleared by a read access to this register using the application program. It is used to indicate if there is a Character Reception

Completion interrupt pending or not. If a character has been received and the relevant interrupt enable control bit is set to 1, this bit will be set to 1 to indicate that the character reception completion interrupt is pending.

Parity Error interrupt pending flag



This bit is set by hardware and cleared by a read access to this register using the application program. It is used to indicate if there is a Parity Error interrupt pending or not. If the parity error occurs and its interrupt enable control bit is set to 1, this bit will be set to 1 to indicate that the parity error interrupt is pending.

Rev. 1.00 336 of 637 December 28, 2020

32-Bit Arm ®

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Cortex ® -M0+ MCU

SCI Transmit Buffer – TXB

This register is used to store the SCI data to be transmitted.

Offset: 0x020


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

Reserved

10 9 8

Type/Reset

7 6 5 4 3

TB

2 1 0


Bits

[7:0]

Field

TB

Descriptions

SCI data byte to be transmitted

SCI Receive Buffer – RXB

This register is used to store the SCI received data.

Offset: 0x024


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

Reserved

10 9 8

Type/Reset

7 6 5 4 3

RB

2 1 0


Bits

[7:0]

Field

RB

Descriptions

SCI Received data byte

Rev. 1.00 337 of 637 December 28, 2020

32-Bit Arm ®

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Cortex ® -M0+ MCU

SCI Prescaler Register – PSCR

This register specifies the prescaler division ratio which is used the SCI internal clock.

Offset: 0x028


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

14 13 12 11

Reserved

10 9 8

6

Reserved

5 4 3 2

PSC

1 0


Bits

[5:0]

Field

PSC

Descriptions

SCI prescaler division ratio

0: f

PSC_CK

= f

PCLK

1~63: f

PSC_CK 2 ×

PCLK

PSC

Rev. 1.00 338 of 637 December 28, 2020

32-Bit Arm ®

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Cortex ® -M0+ MCU

18

Inter-IC Sound (I

2

S)

Introduction

The I 2 S is a synchronous communication interface that can be used as a master or slave to exchange data with other audio peripherals, such as ADCs or DACs. The I 2 S supports a variety of data formats. In addition to the stereo I 2 S-justified, Left-justified and Right-justified modes, there are mono PCM modes with 8/16/24/32-bit sample size. When the I 2 S operates in the master mode, then when using the fractional divider, it can provide an accurate sampling frequency output and support the rate control function and fine-tuning of the output frequency to avoid system problems caused by the cumulative frequency error between different devices.

I2SMCLK

I 2 S Clock

Generator

I2SWS

I2SDO

I2SBCLK

TX FIFO TX Shift Register

APB

Interface

&

Control

Registers

PDMA Req

PDMA Ack

RX FIFO RX Shift Register

Master/Slave

Figure 80. I 2 S Block Diagram

Features

▆

▆

Master or slave mode

Mono and stereo

▆

▆

▆

▆

I 2 S-justified, Left-justified and Right-justified mode

8/16/24/32-bit sample size with 32-bit channel extended

8 × 32-bit TX & RX FIFO with PDMA supported

8-bit Fractional Clock Divider with rate control

I2SDI

Rev. 1.00 339 of 637 December 28, 2020

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Functional Description

I

2

S Master and Slave Mode

The I 2 S can operate in slave or master mode. Within the I 2 S module the difference between these modes lies in the word select (WS) signal which determines the timing of data transmissions.

▆

▆

▆

▆

In the master mode, the word select signal is generated internally by a clock rate generator.

In the slave mode, the word select signal is input on the I2S_WS pin.

When an I 2 S bus is enabled, the word select, bit clock signals are sent continuously by the bus master.

The mute control bit will place the transmit channel in a mute condition. When the mute mode is enabled, the transmit channel FIFO operates normally, but the output data stream is discarded and replaced by zeroes. This bit does not affect the receive channel so data reception can occur normally.

I 2 S Master

I2S_BCLK

I2S_WS

I2S_DI

I2S_DO

I2S_BCLK

I2S_WS

I2S_DO

I2S_DI

I 2 S Slave

I 2 S Slave

I2S_BCLK

I2S_WS

I2S_DI

I2S_DO

Figure 81. Simple I 2 S Master/Slave Configuration

Controller

Master

I2S_BCLK

I2S_WS

I2S_DO

I2S_DI

I 2 S Slave

Rev. 1.00 340 of 637 December 28, 2020

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Cortex ® -M0+ MCU

I

2

S Clock Rate Generator

The main (I2S_MCLK) and bit clock (I2S_BCLK) rates for the I 2 S are determined by the values in the I2SCDR register. The required I 2 S bit clock rate setting depends on the desired audio sample rate desired, the format (stereo/mono) used, and the data size. The main clock rate (I2S_MCLK) is generated using a fractional rate divider which is a divided down PCLK frequency of the I 2 S.

Values of the numerator (X) and the denominator (Y) must be chosen to produce a frequency twice that of the main clock (I2S_MCLK). The output frequency of the divider is divided by 2 in order to get the duty cycle of the output clock more even. The I 2 S clock generator block diagram is shown in

Figure 200. The equation for the fractional rate divider is:

I2S_MCLK = 1/2 × PCLK × (X/Y), and X/Y ≤ 1, X = 1 ~ 255, Y = 1 ~ 255

I2S_BCLK = I2S_MCLK / (N+1), N = 0 ~ 255

Because the fractional rate divider is a fully digital implementation function, the divider output clock transitions are synchronous with the input source clock. Therefore, the fractional rate divider will generate some jitter with some divider settings. Users should make note of this phenomenon when choosing the X and Y setup values. It is possible to avoid jitter entirely by choosing fractions such that X divides evenly into Y. For example, 2/4, 2/6, 3/9, etc.

The tables below show the recommended setup values to reduce clock jitter for different source clocks and sample rates.

PCLK

X Y

8-bit Fractional

Rate Divider

& Fine-Tuning

Controller

I 2 S Clock Generator

2

N

(1 to 64)

I2S_MCLK

I2S_BCLK

I 2 S Control

Logic

I2S_WS

Figure 82. I 2 S Clock Generator Diagram

Rev. 1.00 341 of 637 December 28, 2020

32-Bit Arm ®

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Cortex ® -M0+ MCU

Table 52. Recommend FS List @ 8 MHz PCLK

Fs (Hz)

8,000

11,025

512 F

S

X

—

Y

—

— —

384 F

S

X

96

256 F

Y X

125 64

S

192 F

Y X

125 48

S

— —

Y

125

170 241 118 223

12,000

16,000

22,050

24,000

32,000

44,100

48,000

96,000

192,000

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

96

—

—

—

—

—

125 72

— 96

—

—

—

—

—

—

—

—

—

—

—

—

—

—

125

125

—

—

—

—

—

—

—

128 F

S

X

32

Y

125

90 255

48

64

125

125

170 241

96 125

—

—

—

—

—

—

—

—

—

—

X

16

64 F

S

Y

125

42 238

24

32

90

48

125

125

255

125

64 125

170 241

96 125

—

—

—

—

Table 53. Recommend FS List @ 48 MHz PCLK

Fs (Hz)

8,000

11,025

12,000

512 F

S

X

36

Y

211

4

32

17

125

384 F

S

X

16

256 F

Y X

125 18

S

6

24

34 2

125 16

Y

211

X

8

192 F

S

Y

125

17 6

125 12

68

125

16,000

22,050

24,000

32,000

44,100

48,000

96,000

192,000

86

8

64

252

17

125

32

6

48

125 36

17 4

125 32

142 208 64 125 86

238 253 170 241 8

— — 96 125 64

—

—

—

—

—

—

—

—

—

—

211

17

16

6

125 24

252 32

17 6

125 48

—

—

96

—

125

34

125

125

17

125

125

—

36

4

32

18

2

16

64

—

128 F

S

X

10

Y

234

2

8

34

125

211

17

125

211

17

125

125

—

18

2

16

10

2

8

32

64

2

4

X

2

64 F

S

Y

94

68

125

234

34

125

211

17

125

125

125

Rev. 1.00 342 of 637 December 28, 2020

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I

2

S Interface Format

I 2 S-justified Stereo Mode

The standard I 2 S-justified mode is where the Most Significant Bit (MSB) of the stereo audio sample data is available on the second rising edge of the BCLK clock following a WS signal transition. In the stereo mode, a low WS state indicates left channel data and a high state indicates right channel data. Figure 83 and Figure 84 show the standard I 2 S-justified stereo mode format.

BCLK

WS

SDO/SDI

Channel Left

MSB

Sample size: 8, 16, 24 or 32-bit

Figure 83. I 2 S-justified Stereo Mode Waveforms

LSB MSB

Channel Right

LSB

32 BCLK cycles mode

BCLK

WS

SDO/SDI MSB

Channel Left

LSB 0 forced or skipped MSB

Channel Right

LSB 0 forced or skipped

Sample size: 8, 16 or 24-bit (32 - Sample size) bits remaining

Figure 84. I 2 S-justified Stereo Mode Waveforms (32-bit Channel Enabled)

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Left-justified Stereo Mode

Left-Justified mode is where the Most Significant Bit (MSB) of the stereo audio sample data is available on the first rising edge of BCLK following a WS transition. Figure 85 and Figure 86 are shown with a left I 2 S-justified stereo mode format.

BCLK

WS

SDO/SDI

Channel Left

MSB


Figure 85. Left-justified Stereo Mode Waveforms

LSB MSB

Channel Right

LSB

BCLK

WS

SDO/SDI

Channel Left


Channel Right



Figure 86. Left-justified Stereo Mode Waveforms (32-bit Channel Enabled)

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Right-justified Stereo Mode

Right-Justified mode is where the Least Significant Bit (LSB) of the stereo audio sample data is available on the rising edge of BCLK preceding a WS transition and where the MSB is transmitted first. Figure 87 and Figure 88 show a right I 2 S-justified stereo mode format.

BCLK

WS

SDO/SDI

Channel Left

MSB


Figure 87. Right-justified Stereo Mode Waveforms

LSB MSB

Channel Right

LSB

BCLK

WS

SDO/SDI

Channel Left

0 forced or skipped MSB

Channel Right


(32 - Sample size) bits remaining

Sample size: 8, 16 or 24-bit

Figure 88. Right-justified Stereo Mode Waveforms (32-bit Channel Enabled)

LSB

Rev. 1.00 345 of 637 December 28, 2020

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I 2 S-justified Mono Mode

In the I 2 S-justified mono mode, the Most Significant Bit (MSB) of the mono audio sample data is available on the second rising edge of the BCLK clock following a falling edge on the WS signal.

Figure 89 and Figure 90 show an I 2 S-justified mono mode format.

BCLK

INV

BCLK

WS

SDO/SDI MSB

1 BCLK Sample size: 8, 16, 24 or 32-bit

Figure 89. I 2 S-justified Mono Mode Waveforms

LSB MSB LSB

BCLK

INV

BCLK

WS

SDO/SDI MSB LSB 0 forced or skipped MSB

1 BCLK Sample size: 8, 16 or 24-bit


Figure 90. I 2 S-justified Mono Mode Waveforms (32-bit Channel Enabled)


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Left-justified Mono Mode

In the left-justified mono mode, the Most Significant Bit (MSB) of the mono audio sample data is available on the first rising edge of the BCLK clock following a falling edge on the WS signal.

Figure

91 and

Figure

92 show a left-justified mono mode format.

BCLK

INV

BCLK

WS

SDO/SDI MSB

1 BCLK Sample size: 8, 16, 24 or 32-bit

Figure 91. Left-justified Mono Mode Waveforms

LSB MSB LSB

BCLK

INV

BCLK

WS

SDO/SDI MSB LSB 0 forced or skipped MSB

1 BCLK Sample size: 8, 16 or

24-bit


Figure 92. Left-justified Mono Mode Waveforms (32-bit Channel Enabled)


Rev. 1.00 347 of 637 December 28, 2020

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Right-justified Mono Mode

In the right-justified mono mode, the Least Significant Bit (LSB) of the mono audio sample data is available on the last rising edge of the BCLK clock preceding a rising edge on the WS signal.

Figure 93 and Figure 94 show the right-justified mono mode format.

BCLK

INV

BCLK

WS

SDO/SDI MSB LSB MSB


Figure 93. Right-justified Mono Mode Waveforms

1 BCLK

LSB

BCLK

INV

BCLK

WS

SDO/SDI 0 forced or skipped MSB LSB 0 forced or skipped MSB


Sample size: 8, 16 or

24-bit

1 BCLK

Figure 94. Right-justified Mono Mode Waveforms (32-bit Channel Enabled)

LSB

Rev. 1.00 348 of 637 December 28, 2020

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I 2 S-justified Repeat Mode

In the I 2 S-justified repeat mode, the Most Significant Bit (MSB) of the mono audio sample data is available on the second rising edge of the BCLK clock following a WS signal transition. In this mode the same data is transmitted twice, once when WS is low and again when WS is high.

Figure

95 and Figure 96 show the I

2 S-justified repeat mode format.

BCLK

WS

SDO/SDI

Mono Sample

MSB


Figure 95. I 2 S-justified Repeat Mode Waveforms repeat sample or skipped

LSB MSB LSB

BCLK

WS

SDO/SDI MSB

Mono Sample

LSB 0 forced or skipped repeat sample or skipped

MSB LSB


Figure 96. I 2 S-justified Repeat Mode Waveforms (32-bit Channel Enabled)

0 forced

Rev. 1.00 349 of 637 December 28, 2020

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FIFO Control and Arrangement

The I 2 S handles audio data for transmission and reception and is performed via the FIFO controller.

Each transmitted or received FIFO has a depth of 8 words (8 × 32-bit) and can buffer the data. The format is dependent upon the stereo/mono mode and sample size setting. The detailed FIFO data

content format is shown in Figure 97. The FIFO controller consists of comparators which compare

the current FIFO levels with configurable depth settings. The current level of the TX or RX FIFO status can be seen in the TXFS and RXFS fields of the I 2 S status register (I2SSR).

0 7

N+1

0 7

N

0

FIFO Pointer

Address

M

7

Mono 8-bit Data

N+3

0 7

15

Mono 16-bit Data

N+1

Mono 24-bit Data

31 23

Mono 32-bit Data

31

N+2

0 15

N

N

N

0 M

0

M

0 M

7

Stereo 8-bit Data

LEFT+1

0 7

15

Stereo 16-bit Data

LEFT

Stereo 24-bit Data

31 23

RIGHT+1

0 7

0 15

LEFT

LEFT

RIGHT

31

31

Stereo 32-bit Data

23

LEFT

0 7

RIGHT

RIGHT

31

RIGHT

Figure 97. FIFO Data Content Arrangement for Various Modes

0

0

0

0

0

0

M

M

M

M+1

M

M+1

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PDMA and Interrupt

When the level of received data in the RX FIFO is equal to or greater than the level defined by the

RXFTLS field in the I 2 S FIFO control register (I2SFCR), the relative RXFTL flag will be set and then an I 2 S RX PDMA request will be generated. A CPU interrupt will be generated if the enable bit of the I 2 S RX PDMA request or the RX FIFO trigger level interrupt is asserted. When the level of transmitted data in the TX FIFO is equal to or less than the level defined by the TXFTLS field in the I 2 S FIFO control register (I2SFCR), the relative TXFTL flag will be set and an I 2 S TX PDMA request will be generated. A CPU interrupt will be generated if the enable bit of the I 2 S TX PDMA request or TX FIFO trigger level interrupt is asserted.

The I 2 S transmitter and receiver have separate PDMA requests and can be assigned to two different

PDMA channels. When a PDMA request is enabled for the I 2 S transmitter (TXDMAEN = 1) then this will automatically request that data is transferred to the assigned I 2 S TX PDMA channel whenever TX FIFO space is available and TXFTL is active. When a PDMA request is enabled for the receiver (RXDMAEN = 1) then this will automatically request the data transfers to the I

PDMA channel whenever data is present in the receive FIFO and when RXFTL is active.

2 S RX

Register Map

The following table shows the I 2 S registers and reset values.

Table 54. I 2 S Register Map

Register Offset

I2SCR

I2SIER

I2SCDR

I2STXDR

0x000

0x004

0x008

0x00C

I2SRXDR

I2SFCR

I2SSR

I2SRCNTR

0x010

0x014

0x018

0x01C

Description

I 2 S Control Register

I 2 S Interrupt Enable Register

I 2 S Clock Divider Register

I 2 S TX Data Register

I 2 S RX Data Register

I 2 S FIFO Control Register

I 2 S Status Register

I 2 S Rate Counter Value Register

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0809

0x0000_0000

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I

2

S Control Register – I2SCR

This register specifies the corresponding I 2 S function enable control.

Offset: 0x000


31 30 29 28 27

Reserved

26 25 24

Type/Reset

Type/Reset

23 22 21

Reserved

20 19 18

MCKINV BCKINV

17

RCSEL

16

RCEN

RW 0 RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

CLKDEN RXDMAEN TXDMAEN TXMUTE CHANNEL REPEAT MCLKEN BITEXT


7 6 5 4 3 2 1 0

FORMAT SMPSIZE MS RXEN TXEN I2SEN


Bits

[19]

[18]

[17]

[16]

[15]

[14]

[13]

[12]

Field

MCKINV

BCKINV

Descriptions

MCLK Inverse Enable

0: Disable

1: Enable

BCLK Inverse Enable

0: Disable

1: Enable

RCSEL

RCEN

Rate Control Select (master only)

0: slower

1: faster

Rate Control Enable (master only)

0: Disable

1: Enable

CLKDEN Clock Divider Enable (master only)

0: Disable

1: Enable

The clock divider can be used to generate the MCLK and BCLK clock of the I interface for master mode.

2 S

RXDMAEN RX PDMA Request Enable

0: Disable

1: Enable

TXDMAEN TX PDMA Request Enable

0: Disable

1: Enable

TXMUTE TX Mute Enable

0: Disable

1: Enable

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[9]

[8]

[3]

[2]

[1]

[0]

Bits

[11]

[10]

[7:6]

[5:4]

Field

CHANNEL

REPEAT

MCLKEN

BITEXT

FORMAT

SMPSIZE

MS

RXEN

TXEN

I2SEN

Descriptions

Stereo or Mono

0: Stereo

1: Mono

Note: This bit should be configured when I 2 S is disabled.

Repeat Mode

0: Disable

1: Enable

This mode is for I 2 S-justified stereo configuration only, transmitting the mono data on both channels and receiving just the left channel data and ignoring the right. The repeat mode is only available when the CHANNEL is configured to select Stereo.

Note: This bit should be configured when the I 2 S is disabled.

MCLK Output Enable (master only)

0: Disable

1: Enable


32-bit Channel Enable

0: Disable

1: Enable

Setting this bit will force the channel size to 32-bits. If the sample size is 8/16/24bits, the remaining bits will be forced to 0 in the TX and ignored in the RX.


Data Format

00: I 2 S-justified

01: Left-justified

10: Right-justified

11: reserved


Sample Size

00: 8-bit

01: 16-bit

10: 24-bit

11: 32-bit


Master or Slave Mode

0: Master

1: Slave


RX Enable

0: Disable

1: Enable

TX Enable

0: Disable

1: Enable

I 2 S Enable

0: Disable

1: Enable

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I

2

S Interrupt Enable Register – I2SIER

This register contains the corresponding I 2 S interrupt enable bits.

Offset: 0x004


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

Type/Reset

15 14 13 12 11

Reserved

10 9 8

7 6 5 4 3 2 1 0

Reserved RXOVIEN RXUDIEN RXFTLIEN Reserved TXOVIEN TXUDIEN TXFTLIEN


Bits

[6]

[5]

[4]

[2]

[1]

[0]

Field

RXOVIEN

RXUDIEN

RXFTLIEN

TXOVIEN

TXUDIEN

TXFTLIEN

Descriptions

RX FIFO Overflow Interrupt Enable

0: Disable

1: Enable

RX FIFO Underflow Interrupt Enable

0: Disable

1: Enable

RX FIFO Trigger Level Interrupt Enable

0: Disable

1: Enable

TX FIFO Overflow Interrupt Enable

0: Disable

1: Enable

TX FIFO Underflow Interrupt Enable

0: Disable

1: Enable

TX FIFO Trigger Level Interrupt Enable

0: Disable

1: Enable

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I

2

S Clock Divider Register – I2SCDR

This register specifics the I 2 S clock divider ratio.

Offset: 0x008


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

N_DIV

18 17 16


15 14 13 12 11

X_DIV

10 9 8


7 6 5 4 3 2 1 0

Y_DIV


Bits

[23:16]

[15:8]

[7:0]

Field

N_DIV

X_DIV

Y_DIV

Descriptions

N divider for BCLK

0x00: divide 1

0x01: divide 2

...

0xFF: divide 256


X divider for MCLK

(X = 1 ~ 255) && (X / Y ≤ 1)


Y divider for MCLK

(Y = 1 ~ 255) && (X / Y ≤ 1)


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I

2

S TX Data Register – I2STXDR

This register is used to specify the I 2 S transmitted data.

Offset: 0x00C


31 30 29 28 27

TXDR

26 25 24


23 22 21 20 19

TXDR

18 17 16


15 14 13 12 11

TXDR

10 9 8


7 6 5 4 3 2 1 0

TXDR


Bits

[31:0]

Field

TXDR

Descriptions

TX Data Register

I

2

S RX Data Register – I2SRXDR

This register is used to store the I 2 S received data.

Offset: 0x010


31 30 29 28 27

RXDR

26 25 24


23 22 21 20 19 18 17 16

RXDR


15 14 13 12 11

RXDR

10 9 8


7 6 5 4 3 2 1 0

RXDR


Bits

[31:0]

Field

RXDR

Descriptions

RX Data Register

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Bits

[9]

[8]

[7:4]

I

2

S FIFO Control Register – I2SFCR

This register contains the related I 2 S FIFO control bits.

Offset: 0x014


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12

Reserved

11 10 9 8

RXFRST TXFRST

Type/Reset

7 6 5

RXFTLS

4 3 2

RW 0 RW 0

1

TXFTLS

0


[3:0]

Field

RXFRST

TXFRST

RXFTLS

TXFTLS

Descriptions

RX FIFO Reset

Set this bit to reset the RX FIFO.

TX FIFO Reset

Set this bit to reset the TX FIFO.

RX FIFO Trigger Level Select



...


1xxx: Trigger level is 8

When the data contained in the RX FIFO is equal to or greater than the level defined by the RXFTLS field, the RXFTL flag will be set.

TX FIFO Trigger Level Select



...


1xxx: Trigger level is 8

When the data contained in the TX FIFO is equal to or less than the level defined by the TXFTLS field, the TXFTL flag will be set.

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I

2

S Status Register – I2SSR

This register contains the relevant I 2 S status.

Offset: 0x018


31 30 29

RXFS

28 27 26 25

TXFS

24


Type/Reset

23 22 21

Reserved

20 19 18 17

CLKRDY TXBUSY

16

CHS

RO 0 RO 0 RO 0

Type/Reset

Type/Reset

15

7

14

Reserved

6

Reserved

13

5

12 11 10

RXFFUL RXFEMT RXFOV

9

RXFUD

8

RXFTL

RO 0 RO 1 WC 0 WC 0 WC 0

4 3 2 1 0

TXFFUL TXFEMT TXFOV TXFUD TXFTL

RO 0 RO 1 WC 0 WC 0 WC 1

Bits

[31:28]

[27:24]

[18]

[17]

[16]

[12]

[11]

Field

RXFS

TXFS

CLKRDY

TXBUSY

CHS

RXFFUL

RXFEMT

Descriptions

RX FIFO Status

0000: RX FIFO empty


...


Others: Reserved

TX FIFO Status

0000: TX FIFO empty


…


Others: Reserved

Clock Divider Output Ready Flag

0: not ready

1: ready

TX Busy Flag

0: not busy

1: busy

Channel Status

0: left channel

1: right channel

RX FIFO Full Flag

0: RX FIFO not full

1: RX FIFO full

RX FIFO Empty Flag

0: RX FIFO not empty

1: RX FIFO empty

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Bits

[10]

[9]

[8]

[4]

[3]

[2]

[1]

[0]

Field

RXFOV

RXFUD

RXFTL

TXFFUL

TXFEMT

TXFOV

TXFUD

TXFTL

Descriptions

RX FIFO Overflow Flag

0: RX FIFO not overflow

1: RX FIFO overflow


RX FIFO Underflow Flag

0: RX FIFO not underflow

1: RX FIFO underflow


RX FIFO Trigger Level Flag

0: Data in the RX FIFO is less than the trigger level

1: Data in the RX FIFO is equal to or higher than the trigger level


TX FIFO Full Flag

0: TX FIFO not full

1: TX FIFO full

TX FIFO Empty Flag

0: TX FIFO not empty

1: TX FIFO empty

TX FIFO Overflow Flag

0: TX FIFO not overflow

1: TX FIFO overflow


TX FIFO Underflow Flag

0: TX FIFO not underflow

1: TX FIFO underflow


TX FIFO Trigger Level Flag

0: Data in the TX FIFO is higher than the trigger level

1: Data in the TX FIFO is equal to or less than the trigger level


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I

2

S Rate Counter Value Register – I2SRCNTR

This register specifics the I 2 S rate control counter value.

Offset: 0x01C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

Type/Reset

23 22 21

Reserved

20 19 18 17

RCNTR

16

RW 0 RW 0 RW 0 RW 0

15 14 13 12 11

RCNTR

10 9 8


7 6 5 4 3 2 1 0

RCNTR


Bits

[19:0]

Field

RCNTR

Descriptions

Rate Counter Value

This value must be higher than zero for useful rate fine-tuning control.

RCSEL = 1, RCNTR = 1 ~ (2Y-1): MCLK' = (1 +

RCSEL = 1, RCNTR > (2Y-1): MCLK' = (1 +

(2Y-1) )

1

1

× MCLK

RCNTR )

× MCLK

RCSEL = X, RCNTR = 0: MCLK' = MCLK

RCSEL = 0, RCNTR > (2Y+1): MCLK' = (1 +

1

RCNTR )

RCSEL = 0, RCNTR = 1 ~ (2Y+1): MCLK' = (1 +

1

2Y+1 )

× MCLK

× MCLK

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19

Analog to Digital Converter (ADC)

Introduction

A 12-bit multi-channel Analog to Digital Converter (ADC) with a Voltage Reference Generator

(V

REF

) is integrated in the device. There are a total of 16 multiplexed channels including 10 external channels on which the external analog signal can be supplied and 6 internal channels. If the input voltage is required to remain within a specific threshold window, the Analog Watchdog function will monitor and detect the signal. An interrupt will then be generated to inform that the input voltage is higher or lower than the set thresholds. There are three conversion modes to convert an analog signal to digital data. The A/D conversion can be operated in one shot, continuous and discontinuous conversion mode. A 16-bit data register is provided to store the data after conversion.

ADC_IN0

ADC_IN1

ADC_IN9

VDDA

Up to 16 Channels

MVDDAEN

From ADC Prescaler

CK_ADC

V

DDA

DAC1O

DAC0O

V

REF

V

MV

SSA

DDA

0

1

9

12

13

14

15

16

17

ADCIN

12-bit A/D

Converter

VDDA

VREF+

VSSA

R

MV

DDA

R

Voltage Reference Generator (V

VREFEN

Bandgap

REF

)

VREF-

VSSA

V

REF

PA0

AFIO15

ADCTCR[4:0]

ADC Control Logic

Analog Watchdog

High Threshold

Low Threshold

Analog Watchdog Event

Analog Watchdog

Interrupt

ADCTSR[31:0]

Start Trigger

DMA Request

EOC OV

Interrupt

Generator ADC Interrupt to NVIC

VREFVAL[6:0]

VREFSEL[1:0]

PA0

Figure 98. ADC with V

REF

Block Diagram

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Features

▆

▆

▆

▆

▆

▆

▆

▆

▆

▆

▆

▆

▆

12-bit SAR ADC engine

Up to 1 Msps conversion rate

Up to 10 external analog input channels

1 channel for internal voltage reference (V

REF

)

2 channels for monitor external V

DDA

power support pin

2 channels for internal DAC output

Programmable sampling time for conversion channel

Up to 8 programmable conversion channel sequence and dedicated data registers for conversion result

Three conversion mode

● One shot conversion mode

● Continuous conversion mode

● Discontinuous conversion mode

Analog watchdog for predefined voltage range monitor

● Lower/upper threshold register

● Interrupt generation

Various trigger start sources for conversion modes

● Software trigger

●

● GPTM trigger

●

EXTI – external interrupt input pin

PWM0 / PWM1 trigger

● BFTM0 / BFTM1 trigger

● CMP0 / CMP1 trigger

Multiple generated interrupts

● End of single conversion

●

● End of cycle conversion

●

End of subgroup conversion

Analog Watchdog

● Data register overwriting

PDMA request on end of conversion occurred

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ADC Clock Setup

The ADC clock, CK_ADC is provided by the Clock Controller which is synchronous and divided by with the AHB clock known as HCLK. Refer to the Clock Control Unit chapter for more details.

Notes that the ADC requires at least two ADC clock cycles to switch between power-on and poweroff conditions (ADEN bit = ‘0’).

Channel Selection

The A/D converter supports 16 multiplexed channels and organizes the conversion results into a specific group. A conversion group can organize a sequence which can be implemented on the channels arranged in a specific conversion sequence length from 1 to 8. For example, conversion can be carried out with the following channel sequence: CH2, CH4, CH7, CH5, CH6, CH3, CH0 and CH1 one after another.

A group is composed of up to 8 conversions. The selected channels of the group conversion can be specified in the ADCLST0 ~ ADCLST1 registers. The total conversion sequence length is setup using the ADSEQL[2:0] bits in the ADCCR register.

Modifying the ADCCR register during a conversion process will reset the current conversion, after which a new start pulse is required to restart a new conversion.

Conversion Mode

The A/D has three operating conversion modes. The conversion modes are One Shot Conversion

Mode, Continuous Conversion Mode, and Discontinuous Conversion mode. Details are provided later.

One Shot Conversion Mode

In the One Shot Conversion mode, the ADC will perform conversion cycles on the channels specified in the A/D conversion list registers ADCLSTn with a specific sequence when an A/D converter trigger event occurs. When the A/D conversion mode field ADMODE [1:0] in the

ADCCR register is set to 0x0, the A/D converter will operate in the One Shot Conversion Mode.

This mode can be started by a software trigger, a comparator output transition event, an external

EXTI event or a TM event determined by the Trigger Control Register ADCTCR and the Trigger

Source Register ADCTSR.

After Conversion:

▆

The converted data will be stored in the 16-bit ADCDRy (y = 0 ~ 7) registers.

▆

The ADC single sample end of conversion event raw status flag, ADIRAWS, in the ADCIRAW register will be set when the single sample conversion is finished.

▆

▆

An interrupt will be generated after a single sample end of conversion if the ADIES bit in the

ADCIER register is enabled.

An interrupt will be generated after a group cycle end of conversion if the ADIEC bit in the


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Conversion (ex: Sequence Length=8)

Cycle

CH2 CH4 CH7 CH5 CH6 CH3 CH0 CH1

Start of

Conversion

Single sample

End of

Conversion

Cycle End of

Conversion

Figure 99. One Shot Conversion Mode

Cycle

CH2 CH4 CH7 CH5 CH6

Continuous Conversion Mode

In the Continuous Conversion Mode, repeated conversion cycle will restart automatically without requiring additional A/D start trigger signals after a channel group conversion has completed.

When the A/D conversion mode field ADMODE[1:0] is set to 0x2, the A/D converter will operate in the Continuous Conversion Mode which can be started by a software trigger, a comparator output transition event, an external EXTI event or a TM event determined by the Trigger Control

Register ADCTCR and the Trigger Source Register ADCTSR.

After conversion:

▆

The converted data will be stored in the 16-bit ADCDRy (y = 0 ~ 7) registers.

▆

▆

The ADC group cycle end of conversion event raw status flag, ADIRAWC, in the ADCIRAW register will be set when the conversion cycle is finished.

An interrupt will be generated after a group cycle end of conversion if the ADIEC bit in the


Continuous Conversion Mode

(ex: Sequence Length=8)

Idle

Cycle Cycle

CH2 CH4 CH7 CH5 CH6 CH3 CH0 CH1 CH2 CH4 CH7 CH1

Start of Conversion

Single sample End of

Conversion

Cycle End of Conversion

Figure 100. Continuous Conversion Mode

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Discontinuous Conversion Mode

The A/D converter will operate in the Discontinuous Conversion Mode for channels group when the A/D conversion mode bit field ADMODE [1:0] in the ADCCR register is set to 0x3.

The group to be converted can have up to 8 channels and can be arranged in a specific sequence by configuring the ADCLSTn registers where n ranges from 0 to 1. This mode is provided to convert data for the group with a short sequence, named as the A/D conversion subgroup, each time a trigger event occurs. The subgroup length is defined by the ADSUBL [2:0] field in the

ADCCR register to specify the subgroup length. In the Discontinuous Conversion Mode the A/D converter can be started by a software trigger, a comparator output transition event, an external

EXTI event or a TM event for the groups determined by the Trigger Control Register ADCTCR and the Trigger Source Register ADCTSR.

In the Discontinuous Conversion Mode, the A/D Converter will start to convert the next n conversions where the number n is the subgroup length defined by the ADSUBL field. When a trigger event occurs, the channels to be converted with a specific sequence are specified in the

ADCLSTn registers. After n conversions have completed, the subgroup EOC interrupt raw flag

ADIRAWG in the ADCIRAW register will be asserted. The A/D converter will now not continue to perform the next n conversions until the next trigger event occurs. The conversion cycle will end after all the group channels, of which the total number is defined by the ADSEQL[2:0] bits in the

ADCCR register, have finished their conversion, at which point the cycle EOC interrupt raw flag

ADIRAWC in the ADCIRAW register will be asserted. If a new trigger event occurs after all the subgroup channels have all been converted, i.e., a complete conversion cycle has been finished, the conversion will restart from the first subgroup.

Example:

A/D subgroup length = 3 (ADSUBL = 2) and sequence length = 8 (ADSEQL = 7), channels to be converted = 2, 4, 7, 5, 6, 3, 0 and 1 – specific converting sequence as defined in the ADCLSTn registers,

▆

▆

▆

▆

Trigger 1: subgroup channels to be converted are CH2, CH4 and CH7 with the ADIRAWG flag being asserted after subgroup EOC.

Trigger 2: subgroup channels to be converted are CH5, CH6 and CH3 with the ADIRAWG flag being asserted after subgroup EOC.

Trigger 3: subgroup channels to be converted are CH0 and CH1 with the ADIRAWG flag being asserted after subgroup EOC. Also a Cycle end of conversion (EOC) interrupt raw flag

ADIRAWC will be asserted.

Trigger 4: subgroup channels to be converted are CH2, CH4 and CH7 with the ADIRAWG flag being asserted - conversion sequence restarts from the beginning.

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Discontinuous Conversion Mode

(ex: Sequence Length=8, Subgroup Length=3 )

Cycle

CH2 CH4 CH7 CH5 CH6 CH3

Subgroup 0 Subgroup 1

Start of

Conversion

Single sample

End of

Conversion

Subgroup End of Conversion

Cycle End of

Conversion

Figure 101. Discontinuous Conversion Mode

CH0 CH1

Subgroup 2

Cycle

CH2 CH4 CH7

Subgroup 0

Start Conversion on External Event

An A/D conversion can be initiated by a software trigger, a comparator output transition event, a General-Purpose Timer Module (GPTM) event, a Pulse Width Modulator (PWM) event, a

Basic Function Timer Module (BFTM) event or an external trigger. Each trigger source can be enabled by setting the corresponding enable control bit in the ADCTCR register and then selected by configuring the associated selection bits in the ADCTSR register to start a group channel conversion.

An A/D conversion can be started by setting the software trigger bit, ADSC, in the ADCTSR register for the group channel when the software trigger enable bit, ADSW, in the ADCTCR register is set to 1. After the A/D converter starts converting the analog data, the corresponding enable bit ADSC will be cleared to 0 automatically.

The A/D converter can also be triggered to start a group conversion by a TM event. The TM events include a GPTM or PWM master trigger output MTO, four GPTM or PWM channel outputs CH0

~ CH3 and a BFTM trigger output. If the corresponding Timer trigger enable bit is set to 1 and the trigger output or the TM channel event is selected via the relevant TM event selection bits, the A/D converter will start a conversion when a rising edge of the selected trigger event occurs.

In addition to the internal trigger sources, the A/D converter can be triggered to start a conversion by an external trigger event. The external trigger event is derived from the external lines of the

EXTI unit. If the external trigger enable bit ADEXTI is set to 1 and the corresponding EXTI line is selected by configuring the ADEXTIS field in the ADCTSR register, the A/D converter will start a conversion when an EXTI line active edge determined in the EXTI Unit occurs.

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Sampling Time Setting

The conversion channel sampling time can be programmed according to the input resistance of the input voltage source. This sampling time must be enough for the input voltage source to charge the internal sample and hold capacitor in the A/D converter to the input voltage level. Each conversion channel is sampled with the same sampling time. By modifying the ADST[7:0] bits in the ADCSTR register, the sampling time of the analog input signal can be determined.

The total conversion time (T conv

) is calculated using the following formula:

T conv

= T

Sampling

+ T

Latency

Where the minimum sampling time T

Sampling channel conversion latency T

Latency

= 1.5 cycles (when ADST[7:0] = 0) and the minimum

= 12.5 cycles.

Example:

With the A/D Converter clock CK_ADC = 14 MHz and a sampling time = 1.5 cycles:

T conv

= 1.5 + 12.5 = 14 cycles = 1 μs

Data Format

The ADC conversion result can be read in the ADCDRy register and the data format is shown in

the following table.

Table 55. Data format in ADCDR [15:0]

Description

Right aligned

ADCDR register Data Format

“0_0_0_0_d11_d10_d9_d8_d7_d6_d5_d4_d3_d2_d1_d0”

Analog Watchdog

The A/D converter includes a watchdog function to monitor the converted data. There are two kinds of thresholds for the watchdog monitor function, known as the watchdog lower threshold and watchdog upper threshold, which are specified by the ADLT bit field and ADUT bit field in the

ADCTR register respectively. The watchdog monitor function is enabled by setting the watchdog upper and lower threshold monitor function enable bits, ADWUE and ADWLE, in the watchdog control register ADCWCR. The channel to be monitored can be specified by configuring the

ADWCH and ADWALL bits. When the converted data is less or higher than the lower or upper threshold, as defined by the ADLT bit field and ADUT bit field in the ADCTR register respectively, the watchdog lower or upper threshold interrupt raw flags, ADIRAWL or ADIRAWU in the

ADCIRAW register, will be asserted if the watchdog lower or upper threshold monitor function is enabled. If the lower or upper threshold interrupt raw flag is asserted and the corresponding interrupt is enabled by setting the ADIEL or ADIEU bit in the ADCIER register, the A/D watchdog lower or upper threshold interrupt will be generated.

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Interrupts

When an A/D conversion is completed, an End of Conversion EOC event will occur. There are three types of EOC events which are known as single sample EOC, subgroup EOC and cycle EOC for A/D conversion. A single sample EOC event will occur and the single sample EOC interrupt raw flag, ADIRAWS bit in the ADCIRAW register, will be asserted when a single channel conversion has completed. A subgroup EOC event will occur and the subgroup EOC interrupt raw flag, ADIRAWG in the ADCIRAW register, will be asserted when a subgroup conversion has completed. A cycle EOC event will occur and the cycle EOC interrupt raw flag, ADIRAWC bits in the ADCIRAW register, will be asserted when a cycle conversion is finished. When a single sample

EOC, a subgroup EOC or a cycle EOC raw flag is asserted and the corresponding interrupt enable bit, ADIES, ADIEG or ADIEC bit in the ADCIER register, is set to 1, the associated interrupt will be generated.

After a conversion has completed, the 12-bit digital data will be stored in the associated ADCDRy registers and the value of the data valid flag named as ADVLDy will be changed from low to high.

The converted data should be read by the application program, after which the data valid flag

ADVLDy will be automatically changed from high to low. Otherwise, a data overwrite event will occur and the data overwrite interrupt raw flag ADIRAWO bit in the ADCIRAW register will be asserted. When the related data overwrite raw flag is asserted, the data overwrite interrupt will be generated if the interrupt enable bit ADIEO in the ADCIER register is set to 1.

If the A/D watchdog monitor function is enabled and the data after a channel conversion is less than the lower threshold or higher than the upper threshold, the watchdog lower or upper threshold interrupt raw flag ADIRAWL or ADIRAWU in the ADCIRAW register will be asserted. When the ADIRAWL or ADIRAWU flag is asserted and the corresponding interrupt enable bit, ADIEL or ADIEU in the

ADCIER register, is set a watchdog lower or upper threshold interrupt will be generated.

The A/D Converter interrupt clear bits are used to clear the associated A/D converter interrupt raw and interrupt status bits. Writing a 1 into the specific A/D converter interrupt clear bit in the A/D converter interrupt clear register ADCICLR will clear the corresponding A/D converter interrupt raw and interrupt status bits. These bits are automatically cleared to 0 by hardware after being set to 1.

PDMA Request

The converted channel value will be stored in the corresponding data register. The A/D Converter can inform the MCU using the A/D Converter EOC interrupt if a new conversion data is already stored in the ADCDRy register. Users also can determine if the PDMA request is asserted by setting the ADDMAC, ADDMAG or ADDMAS bits in the ADCDMAR register. A PDMA request will be automatically generated at the relevant end of A/D conversion. The detail description will be introduced in the ADCDMAR register description.

Voltage Reference Generator

The internal voltage reference generator (V

REF

Comparators. The V

REF the V

REF

) provides a stable voltage output for the ADC and

is internally connected to the ADC input channel. The precise voltage of

is individually measured and calculated for each part by manufacture during production test and stored in the Flash Manufacture Privilege Information Block. It can be accessed using the VREFVALR register in the read-only mode. Refer to the datasheet for additional information.

When not in use or using the external voltage reference from the VREF pin, the internal V

REF generator can be configured in the power down mode to save power consumption.

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Cortex ® -M0+ MCU

Voltage Reference Generator (V

REF

)

VREFEN

V

DDA

VREFVAL[6:0]

Bandgap

VREFSEL[1:0]

Figure 102. Voltage Reference Generator Block Diagram

V

REF

PA0

AFIO15

PA0

V

DDA

Voltage Monitor

The MVDDAEN bit in the VREFCR register allows the application to measure the V on the VDDA pin. As the V

DDA

DDA

voltage

voltage could be higher than the ADC reference voltage, in order to ensure the correct operation of the ADC, the VDDA pin is internally connected to a bridge divider by 2. This bridge is automatically enabled when the MVDDAEN bit is set, to connect the V the ADC input channel. As a consequence, the converted digital value is half of the V

DDA

To prevent any unwanted consumption on the battery, it is recommended to enable the V

DDA divider only when the ADC conversion is required

DDA

/2 to

voltage.

power

Register Map

The following table shows the A/D Converter registers and reset values.

Table 56. A/D Converter Register Map

Register

ADCCR

Offset

0x000

Description

ADC Conversion Control Register

ADCLST0 0x004

ADCLST1 0x008

ADCSTR

ADCDR0

ADCDR1

0x020

0x030

0x034

ADCDR2

ADCDR3

ADCDR4

ADCDR5

0x038

0x03C

0x040

0x044

ADCDR6

ADCDR7

ADCTCR

ADCTSR

0x048

0x04C

0x070

0x074

ADCWCR 0x078

ADCTR 0x07C

ADCIER 0x080

ADCIRAW 0x084

ADCISR 0x088

ADCICLR 0x08C

ADCDMAR 0x090

VREFCR 0x0A0

VREFVALR 0x0A4

ADC Conversion List Register 0

ADC Conversion List Register 1

ADC Input Sampling Time Register

ADC Conversion Data Register 0








ADC Trigger Control Register

ADC Trigger Source Register

ADC Watchdog Control Register

ADC Watchdog Threshold Register

ADC Interrupt Enable register

ADC Interrupt Raw Status Register

ADC Interrupt Status Register

ADC Interrupt Clear Register

ADC DMA Request Register

Voltage Reference Control Register

Voltage Reference Value Register

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_00XX

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ADC Conversion Control Register – ADCCR

This register specifies the mode setting, sequence length and subgroup length of the ADC conversion mode.

Note that once the content of ADCCR is changed, the conversion in progress will be aborted and the A/D converter will return to an idle state. The application program has to wait for at least one CK_ADC clock before issuing the next command.

Offset: 0x000


31 30 29 28

Type/Reset

23 22 21

Reserved

Type/Reset

15 14

Type/Reset

7 6

ADCEN ADCRST


13

Reserved

5

20

12

4

Reserved

27

Reserved

19

11

3

26 25 24

18 17

ADSUBL

16

RW 0 RW 0 RW 0

10 9

ADSEQL

8

RW 0 RW 0 RW 0

2 1 0

ADMODE

RW 0 RW 0

Bits

[18:16]

[10:8]

[7]

[6]

Field

ADSUBL

ADSEQL

ADCEN

ADCRST

Descriptions

ADC Conversion Subgroup Length

The ADSUBL field specifies the conversion channel length of each subgroup in the Discontinuous Conversion Mode. Subgroup length = ADSUBL [2:0] + 1. If the sequence length (ADSEQL [2:0] + 1) is not a multiple of the subgroup length

(ADSUBL [2:0] + 1), the last subgroup will be the rest of the group channels that have not been converted.

ADC Conversion Length

0x00: The channel specified by the ADSEQ0 field in the ADCLST0 register will be converted

Others: Sequence length = ADSEQL [2:0] + 1

The ADSEQL field specifies the whole conversion sequence length for the conversion group.

ADC Enable

0: ADC is disabled

1: ADC is enabled

When this bit is cleared to 0, the A/D converter will be disabled and the CK_ADC clock will also be switched off.

ADC Reset

0: No effect

1: Reset A/D converter except for the A/D converter controller

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Bits

[1:0]


ADMODE ADC Conversion Mode

ADMODE [1:0]

00

01

10

11

Mode

One shot mode

Descriptions

After a start trigger, the conversion will be executed on the specific channels for the whole conversion sequence once.

Reserved

Continuous mode

Discontinuous mode

After a start trigger, the conversion will be executed on the specific channels for the whole sequence continuously until conversion mode is changed.

After a start trigger, the conversion will be executed on the current subgroup. When the last subgroup is finished, the conversion will restart from the first subgroup if another start trigger occurs.

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Cortex ® -M0+ MCU

ADC Conversion List Register 0 – ADCLST0

This register specifies the conversion sequence order No.0 ~ No.3 of the ADC.

Offset: 0x004


Type/Reset

Type/Reset

Type/Reset

Type/Reset

31

23

15

7

30

Reserved

22

Reserved

14

Reserved

6

Reserved

29

21

13

5

28 27 26

ADSEQ3

25 24


20 19 18

ADSEQ2

17 16


12 11 10

ADSEQ1

9 8


4 3 2 1 0

ADSEQ0


Bits

[28:24]

[20:16]

[12:8]

[4:0]

Field

ADSEQ3

ADSEQ2

ADSEQ1

ADSEQ0

Descriptions

ADC Conversion Sequence Select 3

Select the ADC input channel for the 3 rd ADC conversion sequence.

0x0: ADC_IN0

0x1: ADC_IN1

0x2: ADC_IN2

0x3: ADC_IN3

0x4: ADC_IN4

0x5: ADC_IN5

0x6: ADC_IN6

0x7: ADC_IN7

0x8: ADC_IN8

0x9: ADC_IN9

0xA~0xB: Reserved

0xC: V

DDA

0xD: DAC1O

0xE: DAC0O

0xF: Internal Voltage Reference (V

0x10: Analog ground V

SSA

0x11: Analog power MV

DDA

(V

DDA

/2)

REF

)

0x12 ~ 0x1F: Invalid setting. These values must not be selected as it may cause the ADC abnormal operations.




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Cortex ® -M0+ MCU

ADC Conversion List Register 1 – ADCLST1

This register specifies the conversion sequence order No.4 ~ No.7 of the ADC.

Offset: 0x008


Type/Reset

Type/Reset

Type/Reset

Type/Reset

31

23

15

7

30

Reserved

22

Reserved

14

Reserved

6

Reserved

29

21

13

5

28 27 26

ADSEQ7

25 24


20 19 18

ADSEQ6

17 16


12 11 10

ADSEQ5

9 8


4 3 2 1 0

ADSEQ4


Bits

[28:24]

[20:16]

[12:8]

[4:0]

Field

ADSEQ7

ADSEQ6

ADSEQ5

ADSEQ4

Descriptions


Select the ADC input channel for the 7 th ADC conversion sequence.

0x0: ADC_IN0

0x1: ADC_IN1

0x2: ADC_IN2

0x3: ADC_IN3

0x4: ADC_IN4

0x5: ADC_IN5

0x6: ADC_IN6

0x7: ADC_IN7

0x8: ADC_IN8

0x9: ADC_IN9

0xA~0xB: Reserved

0xC: V

DDA

0xD: DAC1O

0xE: DAC0O

0xF: Internal Voltage Reference (V

0x10: Analog ground V

SSA

0x11: Analog power MV

DDA

(V

DDA

/2)

REF

)

0x12 ~ 0x1F: Invalid setting. These values must not be selected as it may cause the ADC abnormal operations.




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Cortex ® -M0+ MCU

ADC Input Sampling Time Register – ADCSTR

This register specifies the A/D converter input channel sampling time.

Offset: 0x020


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

Reserved

10 9 8

Type/Reset

7 6 5 4 3

ADST

2 1 0


Bits

[7:0]

Field

ADST

Descriptions

ADC Input Channel Sampling Time

Sampling time = (ADST[7:0] + 1.5) × CK_ADC clocks.

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ADC Conversion Data Register y – ADCDRy, y = 0 ~ 7

This register is used to store the conversion data of the conversion sequence order No.y which is specified by the ADSEQy field in the ADCLSTn (n = 0 ~ 1) registers.

Offset: 0x030 ~ 0x04C


31

ADVLDy

Type/Reset RC 0

23

30 29 28 27

Reserved

26 25 24

22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

ADDy

10 9 8


7 6 5 4 3 2 1 0

ADDy


Bits

[31]

[15:0]

Field

ADVLDy

ADDy

Descriptions

ADC Conversion Data of Sequence Order No.y Valid Bit (y = 0 ~ 7)

0: Data are invalid or have been read

1: New data is valid

ADC Conversion Data of Sequence Order No.y (y = 0 ~ 7)

The conversion result of Sequence Order ADSEQy in the ADCLSTn (n = 0 ~ 1) registers

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Cortex ® -M0+ MCU

ADC Trigger Control Register – ADCTCR

This register contains the ADC start conversion trigger enable bits.

Offset: 0x070


31 30 29

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

Reserved

21

13

5

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

12 11

Reserved

10 9 8

4

CMP

3

TM1

2

TM0

1

ADEXTI

0

ADSW


Bits

[4]

[3]

[2]

[1]

[0]

Field

CMP

TM1

TM0

ADEXTI

ADSW

Descriptions

ADC Conversion CMP Event Trigger enable control

0: Disable conversion trigger by CMP output transition

1: Enable conversion trigger by CMP output transition

ADC Conversion BFTM or PWM Event Trigger enable control

0: Disable conversion trigger by BFTM or PWM events

1: Enable conversion trigger by BFTM or PWM events

ADC Conversion GPTM Event Trigger enable control

0: Disable conversion trigger by GPTM events

1: Enable conversion trigger by GPTM events

ADC Conversion EXTI Event Trigger enable control

0: Disable conversion trigger by EXTI lines

1: Enable conversion trigger by EXTI lines

ADC Conversion Software Trigger enable control

0: Disable conversion trigger by software trigger bit

1: Enable conversion trigger by software trigger bit

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Cortex ® -M0+ MCU

ADC Trigger Source Register – ADCTSR

This register contains the trigger source selection and the software trigger bit of the conversion.

Offset: 0x074


Type/Reset

31 30

Reserved

29 28

TM1E

27 26 25

TM0E

24


23 22 21

TM1S[2:1] Reserved


Type/Reset

Type/Reset

15

7

14

6

13

Reserved

5

20

CMPS

12

4

Reserved

19

TM1S[0]


11

18

10

17

TM0S

9

ADEXTIS

16

8

RW 0 RW 0 RW 0 RW 0

3 2 1 0

ADSC

RW 0

Bits

[29:27]

[26:24]

[20]

[23:22],

[19]

[18:16]

Field

TM1E

TM0E

CMPS

TM1S

TM0S

Descriptions

PWM Trigger Event Selection of ADC Conversion

000: PWM MTO event

001: PWM CH0O event

010: PWM CH1O event

011: PWM CH2O event

100: PWM CH3O event

Others: Reserved -- Should not be used to avoid unpredictable results

GPTM Trigger Event Selection of ADC Conversion

000: GPTM MTO event

001: GPTM CH0O event




Others: Reserved – Should not be used to avoid unpredictable results

CMP Trigger Selection of ADC Conversion

0: CMP0

1: CMP1

BFTM or PWM Trigger Timer Selection of ADC Conversion

000: BFTM0

001: BFTM1

010: PWM0

011: PWM1

Others: Reserved – Should not be used to avoid unpredictable results

GPTM Trigger Timer Selection of ADC Conversion

000: Reserved

001: Reserved

010: GPTM

011: Reserved

Others: Reserved - Should not be used to avoid unpredictable results

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HT32F5828

Cortex ® -M0+ MCU

Bits

[11:8]

[0]

Field

ADEXTIS

ADSC

Descriptions

EXTI Trigger Source Selection of ADC Conversion

0x00: EXTI line 0

0x01: EXTI line 1

…

0x0F: EXTI line 15

Note that the EXTI line active edge to start an A/D conversion is determined in the

External Interrupt/Event Control Unit, EXTI.

ADC Conversion Software Trigger Bit

0: No operation

1: Start conversion immediately

This bit is set by software to start a conversion manually and then cleared by hardware automatically after conversion started.

ADC Watchdog Control Register – ADCWCR

This register provides the control bits and status of the ADC watchdog function.

Offset: 0x078


Type/Reset

Type/Reset

Type/Reset

Type/Reset

31

23

15

7

30

22

14

6

29

Reserved

21

Reserved

13

Reserved

5

Reserved

28

20

12

4

27 26 25

ADUCH

24

RO 0 RO 0 RO 0 RO 0

19 18 17 16

ADLCH

RO 0 RO 0 RO 0 RO 0

11 10 9

ADWCH

8

RW 0 RW 0 RW 0 RW 0

3 2 1

ADWALL ADWUE

0

ADWLE

RW 0 RW 0 RW 0

Bits

[27:24]

Field

ADUCH

Descriptions

Upper Threshold Channel Status

0000: ADC_IN0 converted data is higher than the upper threshold


...


Others: Reserved

If one of these status bits is set to 1 by the watchdog monitor function, the status field value should first be stored in the user-defined memory location in the corresponding ISR. Otherwise, the ADUCH field will be changed if another input channel converted data is higher than the upper threshold.

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[2]

[1]

[0]

Bits

[19:16]

[11:8]

Field

ADLCH

ADWCH

ADWALL

ADWUE

ADWLE

Descriptions

Lower Threshold Channel Status

0000: ADC_IN0 converted data is lower than the lower threshold


...


Others: Reserved

If one of these status bits is set to 1 by the watchdog monitor function, the status field value should first be stored in the user-defined memory location in the corresponding ISR. Otherwise, the ADLCH field will be changed if another input channel converted data is lower than the lower threshold.

ADC Watchdog Specific Channel Selection

0000: ADC_IN0 is monitored


...


Others: Reserved

ADC Watchdog Specific or All Channel Setting

0: Only the channel which specified by the ADWCH field is monitored

1: All channels are monitored

ADC Watchdog Upper Threshold Enable Bit

0: Disable upper threshold monitor function

1: Enable upper threshold monitor function

ADC Watchdog Lower Threshold Enable Bit

0: Disable lower threshold monitor function

1: Enable lower threshold monitor function

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Cortex ® -M0+ MCU

ADC Watchdog Threshold Register – ADCTR

This register specifies the upper and lower threshold of the ADC watchdog function.

Offset: 0x07C


Type/Reset

31 30 29

Reserved

28 27 26 25

ADUT

24

RW 0 RW 0 RW 0 RW 0

23 22 21 20 19

ADUT

18 17 16


Type/Reset

15

7

14

6

13

Reserved

5

12

4

11

3

10

2

9

ADLT

1

8

RW 0 RW 0 RW 0 RW 0

0

ADLT


Bits

[27:16]

[11:0]

Field

ADUT

ADLT

Descriptions

ADC Watchdog Upper Threshold Value

Specify the upper threshold for the ADC watchdog monitor function.

ADC Watchdog Lower Threshold Value

Specify the lower threshold for the ADC watchdog monitor function.

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Cortex ® -M0+ MCU

ADC Interrupt Enable Register – ADCIER

This register contains the ADC interrupt enable bits.

Offset: 0x080


31 30

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

29

21

13

5

Reserved

28

Reserved

20

Reserved

12

4

27

19

26

18

25 24

ADIEO

RW 0

17

ADIEU

16

ADIEL

RW 0 RW 0

9 8 11

Reserved

3

10

2

ADIEC

1

ADIEG

0

ADIES

RW 0 RW 0 RW 0

Bits

[24]

[17]

[16]

[2]

[1]

[0]

Field

ADIEO

ADIEU

ADIEL

ADIEC

ADIEG

ADIES

Descriptions

ADC Data Register Overwrite Interrupt enable

0: ADC data register overwrite interrupt is disabled

1: ADC data register overwrite interrupt is enabled

ADC Watchdog Upper Threshold Interrupt enable

0: ADC watchdog upper threshold interrupt is disabled

1: ADC watchdog upper threshold interrupt is enabled

ADC Watchdog Lower Threshold Interrupt enable

0: ADC watchdog lower threshold interrupt is disabled

1: ADC watchdog lower threshold interrupt is enabled

ADC Cycle EOC Interrupt enable

0: ADC cycle end of conversion interrupt is disabled

1: ADC cycle end of conversion interrupt is enabled

ADC Subgroup EOC Interrupt enable

0: ADC subgroup end of conversion interrupt is disabled

1: ADC subgroup end of conversion interrupt is enabled

ADC Single EOC Interrupt enable

0: ADC single end of conversion interrupt is disabled

1: ADC single end of conversion interrupt is enabled

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ADC Interrupt Raw Status Register – ADCIRAW

This register contains the ADC interrupt raw status bits.

Offset: 0x084


31 30

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

29

21

13

5

Reserved

28

Reserved

20

Reserved

12

4

27

19

26

18

25 24

ADIRAWO

RO 0

17 16

ADIRAWU ADIRAWL

RO 0 RO 0

9 8 11

Reserved

3

10

2 1 0

ADIRAWC ADIRAWG ADIRAWS

RO 0 RO 0 RO 0

Bits

[24]

[17]

[16]

[2]

[1]

[0]


ADIRAWO ADC Data Register Overwrite Interrupt Raw Status

0: ADC data register overwrite event does not occur

1: ADC data register overwrite event occurs

ADIRAWU ADC Watchdog Upper Threshold Interrupt Raw Status

0: ADC watchdog upper threshold event does not occur

1: ADC watchdog upper threshold event occurs

ADIRAWL ADC Watchdog Lower Threshold Interrupt Raw Status

0: ADC watchdog lower threshold event does not occurs

1: ADC watchdog lower threshold event occurs

ADIRAWC ADC Cycle EOC Interrupt Raw Status

0: ADC cycle end of conversion event does not occur

1: ADC cycle end of conversion event occurs

ADIRAWG ADC Subgroup EOC Interrupt Raw Status

0: ADC subgroup end of conversion event does not occur

1: ADC subgroup end of conversion event occurs

ADIRAWS ADC Single EOC Interrupt Raw Status

0: ADC single end of conversion event does not occur

1: ADC single end of conversion event occurs

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Cortex ® -M0+ MCU

ADC Interrupt Status Register – ADCISR

This register contains the ADC interrupt status bits. The corresponding interrupt status will be set to 1 if the associated interrupt event occurs and the related enable bit is set to 1.

Offset: 0x088


31 30

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

29

21

13

5

Reserved

28

Reserved

20

Reserved

12

4

27

19

26

18

25 24

ADISRO

RO 0

17

ADISRU

16

ADISRL

RO 0 RO 0

9 8 11

Reserved

3

10

2 1 0

ADISRC ADISRG ADISRS

RO 0 RO 0 RO 0

Bits

[24]

[17]

[16]

[2]

[1]

[0]

Field

ADISRO

ADISRU

ADISRL

ADISRC

ADISRG

ADISRS

Descriptions

ADC Data Register Overwrite Interrupt Status

0: ADC data register overwrite interrupt does not occur or the data register overwrite interrupt is disabled.

1: ADC data register overwrite interrupt occurs as the data register overwrite interrupt is enabled.

ADC Watchdog Upper Threshold Interrupt Status

0: ADC watchdog upper threshold interrupt does not occur or the watchdog upper threshold interrupt is disabled.

1: ADC watchdog upper threshold interrupt occurs as the watchdog upper threshold interrupt is enabled.

ADC Watchdog Lower Threshold Interrupt Status

0: ADC watchdog lower threshold interrupt does not occur or the watchdog lower threshold interrupt is disabled.

1: ADC watchdog lower threshold interrupt occurs as the watchdog lower threshold interrupt is enabled.

ADC Cycle EOC Interrupt Status

0: ADC cycle end of conversion interrupt does not occur or the cycle end of conversion interrupt is disabled.

1: ADC cycle end of conversion interrupt occurs as the cycle end of conversion interrupt is enabled.

ADC Subgroup EOC Interrupt Status

0: ADC subgroup end of conversion interrupt does not occur or the subgroup end of conversion interrupt is disabled.

1: ADC subgroup end of conversion interrupt occurs as the subgroup end of conversion interrupt is enabled.

ADC Single EOC Interrupt Status

0: ADC single end of conversion interrupt does not occur or the single end of conversion interrupt is disabled.

1: ADC single end of conversion interrupt occurs as the single end of conversion interrupt is enabled.

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HT32F5828

Cortex ® -M0+ MCU

ADC Interrupt Clear Register – ADCICLR

This register provides the clear bits used to clear the interrupt raw and masked status of the ADC. These bits are set to 1 by software to clear the interrupt status and automatically cleared to 0 by hardware after being set to 1.

Offset: 0x08C


31 30

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

29

21

13

5

Reserved

28

Reserved

20

Reserved

12

4

27

19

26

18

25 24

ADICLRO

WO 0

17 16

ADICLRU ADICLRL

WO 0 WO 0

9 8 11

Reserved

3

10

2 1 0

ADICLRC ADICLRG ADICLRS

WO 0 WO 0 WO 0

Bits

[24]

[17]

[16]

[2]

[1]

[0]


ADICLRO ADC Data Register Overwrite Interrupt Status Clear Bit

0: No effect

1: Clear ADISRO and ADIRAWO bits

ADICLRU ADC Watchdog Upper Threshold Interrupt Status Clear Bit

0: No effect

1: Clear ADISRU and ADIRAWU bits

ADICLRL

ADICLRC

ADC Watchdog Lower Threshold Interrupt Status Clear Bit

0: No effect

1: Clear ADISRL and ADIRAWL bits

ADC Cycle EOC Interrupt Status Clear Bit

0: No effect

1: Clear ADISRC and ADIRAWC bits

ADICLRG ADC Subgroup EOC Interrupt Status Clear Bit

0: No effect

1: Clear ADISRG and ADIRAWG bits

ADICLRS ADC Single EOC Interrupt Status Clear Bit

0: No effect

1: Clear ADISRS and ADIRAWS bits

Rev. 1.00 384 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

ADC DMA Request Register – ADCDMAR

This register contains the ADC DMA request enable bits.

Offset: 0x090


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11

Reserved

3

10 9 8

2 1 0

ADDMAC ADDMAG ADDMAS

RW 0 RW 0 RW 0

Bits

[2]

[1]

[0]

Field

ADDMAC

ADDMAG

ADDMAS

Descriptions

ADC Cycle EOC DMA Request Enable Bit

0: ADC cycle end of conversion DMA request is disabled

1: ADC cycle end of conversion DMA request is enabled

ADC Subgroup EOC DMA Request Enable Bit

0: ADC subgroup end of conversion DMA request is disabled

1: ADC subgroup end of conversion DMA request is enabled

ADC Single EOC DMA Request Enable Bit

0: ADC single end of conversion DMA request is disabled

1: ADC single end of conversion DMA request is enabled

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Voltage Reference Control Register – VREFCR

This register contains the internal voltage reference control bits.

Offset: 0x0A0


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

14 13 12

Reserved

6

Reserved

5 4

VREFSEL

RW 0 RW 0

27

Reserved

19

Reserved

11

3

26

18

10

2

Reserved

Bits

[8]

[5:4]

[0]


MVDDAEN Measurement V

0: Disable

DDA

/2 power Enable

1: Enable measurement V

DDA

/2 power

VREFSEL

VREFEN

Voltage Reference Output Selection

00: 1.215 V

01: 2.0 V

10: 2.5 V

11: 2.7 V

These bits select the Voltage Reference output level.

Voltage Reference Enable

0: Disable Voltage Reference

1: Enable Voltage Reference

25

17

24

16

9

1

8

MVDDAEN

RW 0

0

VREFEN

RW 0

Rev. 1.00 386 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Voltage Reference Value Register – VREFVALR

This register contains the internal voltage reference trim value.

Offset: 0x0A4

Reset value: 0x0000_00XX (Various depending on Flash Manufacture Privilege Information Block)

31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

Type/Reset

15 14 13 12 11

Reserved

10 9 8

7

Reserved

6 5 4 3

VREFVAL

2 1 0

RO X RO X RO X RO X RO X RO X RO X

Bits

[6:0]

Field

VREFVAL

Descriptions

Voltage Reference Calibration Value

During the manufacturing process, the calibration data of the internal voltage reference is stored in the Flash Manufacture Privilege Information Block and downloaded to this filed when the system is powered on.

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Cortex ® -M0+ MCU

20

Comparator (CMP)

Introduction

Two general purpose comparators (CMP) are implemented within the device. They can be configured either as standalone comparators or combined with the different kinds of peripheral IP.

Each comparator is capable of asserting interrupts to the NVIC or waking up the CPU from the

Sleep, Deep-Sleep1 or Deep-Sleep2 mode through the EXTI wakeup event management unit.

Comparator Analog IP

Programmable

Hysteresis

CMPEN

CP

CN

Reserved

Reserved

V

DDA

0

V

REF 1

CVRSS

V

SSA

CVREN

8-Bit

CVR

CVRVAL[7:0]

CMPINSEL[1:0]

Programmable

Response Time

V

CVR

CVROE

V

DDA

Domain

Figure 103. Comparator Block Diagram

0

1

CMPPOL

V

CORE

Domain

CMPOUT

Sync

0

CMPSTS

1

PCLK

GPIO

AFIO

SYNCSEL

Control &

Interrupt

Generator

CMP Status

& Interrupt

Reguest

ADC

GPTM

To EXTI

Wakeup

Event

Management

COUT

Features

▆

Rail-to-rail comparator

▆

▆

▆

▆

▆

▆

Configurable negative inputs for flexible voltage selection

● External CN pin

● Internal 8-bit CVR output

Programmable hysteresis

Programmable response speed and power consumption

Comparator output can be routed to I/O pin, to multiple timers or to ADC trigger inputs

8-bit CVR can be configured to dedicate I/O for voltage reference

Comparator has interrupt generation capability with wakeup function from the Sleep, Deep-

Sleep1 or Deep-Sleep2 mode through the EXTI controller

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Cortex ® -M0+ MCU


Comparator Inputs and Output

The I/O pins used as comparator input or output must be configured in the AFIO controller registers. The detailed comparator input and output information will be referred in pin assignment table in the datasheet. The output can also be internally connected to a variety of timers or ADC for trigger purpose. The comparator output can simultaneously be used for both internal and external functions.

Comparator Voltage Reference

The comparator voltage reference is a 256-tap resistor ladder network that provides a selectable reference voltage. A block diagram of the comparator voltage reference is shown in Figure 104. It also has a power-down function to conserve power when the reference is not used. The comparator voltage reference provides 256 distinct levels. The equation used to calculate the value of the reference voltage is as follows:

V

CVR

= CVRVAL × (V

RP

- V

SSA

) / 255

The supply voltage V

RP

can come from either the V

DDA

or the internal voltage reference V

REF by configuring the CVRSS bit in the Comparator Control Register CMPCRn. The CVR output

V

CVR

is used to provide a reference voltage for the analog comparator. It can be internally used or configured to connect to the CN pin by setting the CVROE bit in the Comparator Control Register

CMPCRn . The settling time of the comparator voltage reference must be considered when the V

CVR output voltage is changed.

V

DDA

V

REF

CVRSS = 0

CVRSS = 1

V

RP

CVRVAL[7:0]

CVREN

R

R

R

R V

CVR

R

R

R

Figure 104. Comparator Voltage Reference Block Diagram

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Cortex ® -M0+ MCU

Interrupts and Wakeup

The comparator can generate an interrupt when its output waveform generates a rising or falling edge and its corresponding interrupt enable control bit is also set.

For example, when a comparator output rising edge occurs, the comparator rising edge flag bit

CMPRF in the Comparator Transition Flag Register CMPTFRn will be set. If the comparator output rising edge interrupt enable control bit CMPRIEN in the Comparator Interrupt Enable

Register CMPIERn is enabled, an interrupt will then be generated and sent to the NVIC unit.

Writing “1” into the comparator rising edge flag bit CMPRF in the Comparator Transition Flag

Register CMPTFRn will clear the CMPRF bit. The comparator output falling edge interrupt also has the same corresponding interrupt setting. A block diagram of interrupt signals for comparators is shown in Figure 105.

CMPRF

CMPRIEN

CMP0

CMPFF

CMPFIEN

NVIC CMP Interrupt

CMPRF

CMPRIEN

CMP1

CMPFF

CMPFIEN

Figure 105. Comparator Interrupt Signals

The comparator outputs are also internally connected to the EXTI Wakeup Event Management unit. The comparator output rising transition is used to wake up the MCU from the Sleep, Deep-

Sleep1 or Deep-Sleep2 mode when the comparator wakeup enable bit CMPWPEN is set in the

Comparator Control Register CMPCR n. A block diagram of wakeup signal for each comparator is shown in Figure 106.

CMP0

CMPWPEN

CMPOUT

EXTI

CMP_WAKEUP

CMP1

CMPWPEN

CMPOUT

Figure 106. Comparator Wakeup Signal

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Cortex ® -M0+ MCU

Power Mode and Hysteresis

The comparator response time can be programmed to meet the trade-off between the power consumption and application speed requirements. The bit CMPSM in the CMPCRn register can be programmed as “0” to make the comparator operate in the low speed mode with low power consumption.

The comparator also has four hysteresis levels to avoid spurious output transitions in case of noisy signals. The bits CMPHM[1:0] in the CMPCRn register can be configured to obtain different hysteresis levels for the comparator.

Comparator Write-Protected Mechanism

As the comparator can be used for safety purposes, it is necessary to ensure that the comparator configurations will not be altered due to spurious register access or program counter corruption.

For this purpose, the write-protected function is provided by writing a specific value into the

PROTECT filed in the Comparator Control Register CMPCRn. The write-protected function is enabled by default. Before configuring the bits [15:0] in the Comparator Control Register CMPCRn, the pattern, 0x9C3A, must first be written into the register protection bits [31:16] in the CMPCRn register. Then the write-protected function will be disabled and the bits [15:0] can be configured by application program. For the same reason, the comparator input and output can also be locked using the corresponding configuration lock bit in the Port n Lock Register PnLOCKR (n = A ~ E) in the

GPIO unit.

Register Map

The following table shows the CMP registers and reset values.

Table 57. CMP Register Map

Register

CMPCR0

CVRVALR0

Offset

0x000

0x004

Description

Comparator Control Register 0

Comparator Voltage Reference Value Register 0

CMPIER0

CMPTFR0

CMPCR1

CVRVALR1

CMPIER1

CMPTFR1

0x008

0x00C

0x100

0x104

0x108

0x10C

Comparator Interrupt Enable Register 0

Comparator Transition Flag Register 0

Comparator Control Register 1

Comparator Voltage Reference Value Register 1

Comparator Interrupt Enable Register 1

Comparator Transition Flag Register 1

Reset Value

0x0001_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0001_0000

0x0000_0000

0x0000_0000

0x0000_0000

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Cortex ® -M0+ MCU


Comparator Control Register n – CMPCRn, n = 0 or 1

This register contains the comparator function and voltage reference control bits.

Offset: 0x000 (n = 0), 0x100 (n = 1)


31 30 29 28 27

PROTECT

26 25 24


23 22 21 20 19

PROTECT

18 17 16


15 14

CMPSTS CMPWPEN

13 12

CMPOSEL

11 10

CVRSS

9

CVROE

8

CVREN

Type/Reset RO 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

SYNCSEL CMPPOL CMPINSEL CMPHM CMPSM CMPEN


Bits

[31:16]

[15]

[14]


PROTECT Register Protection

For write operation:

0x9C3A: Disable the CMPCRn register write protection

Others values: Enable the CMPCRn register write protection

For read operation:

0x0000: CMPCRn register write protection is disabled

0x0001: CMPCRn register write protection is enabled

These bits are used to enable or disable the write protection of the filed [14:0] in the CMPCRn register. Enabling the write protection will make the filed [14:0] in the

CMPCRn register become read-only to prevent any unexpected write operation.

The value read from this field indicates if the write protection is enabled or not.

CMPSTS Comparator Output Status

0: Output is low

1: Output is high

This read-only bit is a copy of the comparator output state after the polarity selection and synchronization.

CMPWPEN Comparator Wakeup Enable

0: Disable comparator wakeup function

1: Enable comparator wakeup function

This bit is used to enable the MCU wakeup function from the Sleep, Deep-Sleep1 or Deep-Sleep2 mode when the comparator output after the polarity selection occurring the rising transition event.

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Cortex ® -M0+ MCU

[1]

[0]

[10]

[9]

[8]

Bits

[13:11]

[7]

[6]

[5:4]

[3:2]


CMPOSEL Comparator 0 Output Selection

000: No selection

001: GPTM capture channel 3

100: ADC trigger input

Others: Reserved

Comparator 1 Output Selection

000: No selection

001: GPTM capture channel 3

100: ADC trigger input

Others: Reserved

These bits are used to select the destination for the comparator output after the polarity selection and synchronization.

CVRSS Comparator Voltage Reference Source Selection

0: 8-bit CVR supply voltage comes from V

DDA

1: 8-bit CVR supply voltage comes from internal voltage reference V

REF

CVROE

CVREN

SYNCSEL

Comparator Voltage Reference Output Enable

0: Disable 8-bit CVR output to CN pin

1: Enable 8-bit CVR output to CN pin

Comparator Voltage Reference Enable

0: Disable 8-bit CVR

1: Enable 8-bit CVR

Setting this bit will enable the CVR to output a configured reference voltage.

Synchronization Selection

0: Asynchronous signal of comparator output is selected

1: Synchronous signal of comparator output is selected

The synchronous comparator output should be selected before being passed to the

AFIO unit.

CMPPOL

CMPINSEL Comparator Inverted Input Selection

00: External CN pin

01: Internal 8-bit CVR output

1x: Reserved

These bits are used to select the comparator inverted input source.

CMPHM

Comparator Output Polarity Selection

0: Comparator output is not inverted

1: Comparator output is inverted

Comparator Hysteresis Mode Selection

00: No hysteresis

01: Low hysteresis mode

10: Middle hysteresis mode

11: High hysteresis mode

CMPSM

CMPEN

Comparator Response Speed Mode Selection

0: Low speed mode

1: High speed mode

Comparator Enable

0: Disable Comparator

1: Enable Comparator

Rev. 1.00 393 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Comparator Voltage Reference Value Register n – CVRVALRn, n = 0 or 1

The register is used to set the comparator voltage reference level.

Offset: 0x004 (n = 0), 0x104 (n = 1)


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

Reserved

10 9 8

Type/Reset

7 6 5 4 3

CVRVAL

2 1 0


Bits

[7:0]

Field

CVRVAL

Descriptions

Comparator Voltage Reference Value

There are 256 levels of the comparator voltage reference, which is set using the

CVRVAL bits. The relationship between the CVRVAL field value and the CVR output,

V

V

CVR

CVR

, is given by the following equation:

= CVRVAL × (V

RP

- V

SSA

) / 255, where V

RP

can come from the V

DDA

or V

REF

.

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Cortex ® -M0+ MCU

Comparator Interrupt Enable Register n – CMPIERn, n = 0 or 1

The register is used to enable the comparator n interrupt when the comparator output transition event occurs.

Offset: 0x008 (n = 0), 0x108 (n = 1)


31 30 29 26 25 24

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

18

10

2

17

9

16

8

1 0

CMPRIEN CMPFIEN

RW 0 RW 0

Bits

[1]

[0]


CMPRIEN Comparator Output Rising Edge Interrupt Enable

0: Disable comparator output rising edge interrupt

1: Enable comparator output rising edge interrupt

CMPFIEN Comparator Output Falling Edge Interrupt Enable

0: Disable comparator output falling edge interrupt

1: Enable comparator output falling edge interrupt

Rev. 1.00 395 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Comparator Transition Flag Register n – CMPTFRn, n = 0 or 1

This register contains the comparator n output transition detection enable bits and relevant flags.

Offset: 0x00C (n = 0), 0x10C (n = 1)


31 30 29 26 25

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

12

Reserved

4

Reserved

27

Reserved

19

Reserved

11

3

18

10

2

17

24

16

9 8

CMPRDEN CMPFDEN

RW 0 RW 0

1 0

CMPRF CMPFF

WC 0 WC 0

Bits

[9]

[8]

[1]

[0]


CMPRDEN Comparator Output Rising Edge Detection Enable

0: Disable comparator output rising edge detection

1: Enable comparator output rising edge detection

Note that the signal to be detected is a copy of the comparator output state after the polarity selection and synchronization by the PCLK clock.

CMPFDEN Comparator Output Falling Edge Detection Enable

0: Disable comparator output falling edge detection

1: Enable comparator output falling edge detection

Note that the signal to be detected is a copy of the comparator output state after the polarity selection and synchronization by the PCLK clock.

CMPRF Comparator Output Rising Edge Flag

0: No comparator output rising edge occurs

1: Comparator output rising edge occurs

This flag is available when the comparator output rising edge detection is enabled.

This bit is set to 1 by hardware and cleared to 0 by writing a “1” into it.

CMPFF Comparator Output Falling Edge Flag

0: No Comparator output falling edge occurs

1: Comparator output falling edge occurs

This flag is available when the comparator output falling edge detection is enabled.

This bit is set to 1 by hardware and cleared to 0 by writing a “1” into it.

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Cortex ® -M0+ MCU

21

Digital to Analog Converter (DAC)

Introduction

A 12-bit Digital to Analog Converter (DAC) module is integrated in the device. The DAC module has two output channels with which each has its own converter and output buffer. The two channel data conversions can be stand-alone implementation in asynchronous mode or be simultaneous implementation in synchronous mode.

DACxDHR

8/12-bit

DACxCR

Control logic

VDDA

VSSA

Internal

Voltage

Reference

(V

REF

)

VREFSEL[1:0]

12-bit

DACxDOR

12-bit

DACEN

V

DACREF

Digital to Analog

Converterx DON

DBON

DACx_OUT x: 0~1

Figure 107. DAC Channel Block Diagram

Features

▆

▆

▆

▆

▆

Two DAC channels with respective output buffer independent or simultaneous conversion

8-bit / 12-bit right alignment data format

Maximum 500 ksps conversion rate

Voltage Reference from Internal Voltage Reference V

REF

or V

DDA

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Function Descriptions

DAC Channel Enable

Each DAC channel can be powered on by setting the corresponding DACEN bit in the DACxCR register. It should be noted that the DACEN bit only enables the analog D/A converter. The digital

DAC controller is enabled by the DACCEN bit in the APBCCR1 register located in the CKCU unit.

DAC Operation Mode

The two DAC channels can be operated in synchronous mode which converts two channel data simultaneously by setting the MODE bit in the DACCFGR register or in asynchronous mode which converts two channel data independently by clearing the MODE bit.

Whenever in the synchronous mode or asynchronous mode, the DAC clock source is the same for the DAC CH0 and CH1 channel.

DAC Asynchronous Conversion

In the asynchronous mode, the data conversion of each DAC channel is performed by loading data into the corresponding DACxDHR register. And the data will automatically be transferred into the

DACxDOR register at the next DAC clock cycle.

t

When the DACxDOR register is loaded, the analog output voltage becomes available after a time

SETTLE

that depends on the power supply and the analog output load.

PCLK_DAC

DACxDHR

0x945

DACxDOR

Figure 108. DAC Data Transfer Timing Diagram

0x945 t

SETTLE

Output voltage is available on the DACx_OUT pin

The data format for the DACxDHR register is right alignment. In 8-bit data resolution setting, the hardware will pad 4 bits of zero into the LSB automatically when the DACxDOR register is loaded.

DACxDHR

31 15 11 0

DACxDATA

31

DACxDOR

15

Figure 109. 12-bit Data Transfer in Asynchronous Mode

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11

DACxDATA

0

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Cortex ® -M0+ MCU

31

DACxDHR

15 7

DACxDATA

0

DACxDOR

31 15 11

DACxDATA

4

0000

0

Figure 110. 8-bit Data Transfer in Asynchronous Mode

DAC Synchronous Conversion

In the synchronous mode, the data conversion of two DAC channel are performed the MCU writes a DAC output by simultaneously trigger data into the DAC0DHR register. And the data will automatically be transferred into the corresponding DAC0DOR and DAC1DOR register at the next

DAC clock cycle.

The DAC data resolution setting in this mode is determined by the DACRES bit in the DAC0CR register.

31

DAC0DHR

27 16 11 0

DAC1DATA DAC0DATA

31

DAC0DOR

31

DAC1DOR

Figure 111. 12-bit Data Transfer in Synchronous Mode

15

11

DAC0DATA

0

15 11 0

DAC1DATA

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31

DAC0DHR

15

DAC1DATA

7

DAC0DATA

0

31

DAC0DOR

15 11

DAC0DATA

4

0000

0

31

DAC1DOR

15 11

DAC1DATA

4

0000

0

Figure 112. 8-bit Data Transfer in Synchronous Mode

DAC Output Voltage

The 12-bit digital data is converted to analog voltage on a linear conversion between 0 and V

The DAC voltage reference V analog power V

DDA

.

DACREF

can be selected from the Internal Voltage Reference V

DACREF

.

REF

or the

The output voltage on each DAC channel is determined by the following equation:

DACx_OUT = DACxDOR × (V

DACREF

/ 4095)

DAC Output Buffer

Two output buffers are integrated that can be used to drive external loads directly. Each DAC channel output buffer can be enabled or disabled by configuring the corresponding DBON bit in the DACxCR register. It should be noted that both DBON bit and DON bit cannot be set at the same time, otherwise it will lead to unpredictable results.

Register Map

The following table shows the DAC register and reset value.

Table 58. DAC Register Map

Register

DACCFGR

Offset

0x000

Description

DAC Configuration Register

DAC0CR

DAC0DHR

DAC0DOR

DAC1CR

DAC1DHR

DAC1DOR

0x010

0x01C

0x020

0x030

0x03C

0x040

DAC Channel 0 Control Register

DAC Channel 0 Data Holding Register

DAC Channel 0 Data Output Register

DAC Channel 1 Control Register

DAC Channel 1 Data Holding Register

DAC Channel 1 Data Output Register

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

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DAC Configuration Register – DACCFGR

This register specifies the DAC global configuration.

Offset: 0x000


31 30 29

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

Type/Reset

Bits

[0]

Field

MODE

Descriptions

Conversion Mode Selection

0: Asynchronous mode

1: Synchronous mode

26

18

10

2

25

17

24

16

9 8

1 0

MODE

RW 0

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DAC Channel 0 Control Register – DAC0CR

This register specifies the DAC channel 0 configurations and enable bits.

Offset: 0x010


29 31 30

Type/Reset

23 22

Type/Reset

15 14

VREFSEL


7 6

DBON DON


21

13

5

28

20

12

4

Reserved

27

Reserved

19

Reserved

11

3

26

18

25

17

24

16

10

Reserved

9 8

2 1 0

DACRES Reserved DACEN

RW 0 RW 0

Bits

[15:14]

[7]

[6]

[2]

[0]


VREFSEL DAC Channel Voltage Reference Source Selection

00: V

01: V

DDA

REF

Others: Reserved

DBON

DON

DACRES

DACEN

DAC Channel Output Buffer Enable

0: DAC channel output buffer is disabled

1: DAC channel output buffer is enabled

DAC Channel Directly Output Enable

0: DAC channel directly output is disabled

1: DAC channel directly output is enabled

DAC Channel Resolution Selection

0: 12-bit resolution

1: 8-bit resolution

If the DAC is operated in the synchronous mode, the DAC resolution is determined by the DACRES bit in the DAC0CR register, in such case the same bit in the

DAC1CR will be ignored.

DAC Channel Enable

0: DAC channel is disabled

1: DAC channel is enabled

Users should select only one DAC output path from DAC output, namely with buffer or directly output by configuring the DBON or DON bit respectively. It is forbidden to set both DBON and DON bits high at the same time, otherwise it will lead to unpredictable results.

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

DAC Channel 0 Data Holding Register – DAC0DHR

This register contains the right alignment data for DAC channel 0 and DAC channel 1.

Offset: 0x01C


Type/Reset

31 30 29

Reserved

28 27 26 25

DAC0DATA

24

RW 0 RW 0 RW 0 RW 0

23 22 21 20

DAC0DATA

19 18 17 16


15 14 13 12

DAC0DATA

11 10 9 8


7 6 5 4 3 2 1 0

DAC0DATA


Bits

[27:0]


DAC0DATA DAC Channel 0 Holding Data

In the asynchronous mode:

- For 8-bit resolution: DAC channel 0 data should be loaded into the DAC0DHR

[7:0] bits


[11:0] bits

In the synchronous mode:


[7:0] bits and DAC channel 1 data should be loaded into the DAC0DHR [15:8] bits


[11:0] bits and DAC channel 1 data should be loaded into the DAC0DHR [27:16] bits

Rev. 1.00 403 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

DAC Channel 0 Data Output Register – DAC0DOR

This register contains the data output for DAC channel 0.

Offset: 0x020


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

15

7

14

6

13

Reserved

5

12 11 10

DAC0DOUT

9 8

RO 0 RO 0 RO 0 RO 0

4

DAC0DOUT

3 2 1 0


Bits

[11:0]


DAC0DOUT DAC Channel 0 Data Output

These bits contain data output for DAC channel 0.

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HT32F5828

Cortex ® -M0+ MCU

DAC Channel 1 Control Register – DAC1CR

This register specifies the DAC channel 1 configurations and enable bits.

Offset: 0x030


29 31 30

Type/Reset

23 22

Type/Reset

15 14

VREFSEL


7 6

DBON DON


21

13

5

28

20

12

4

Reserved

27

Reserved

19

Reserved

11

3

26

18

25

17

24

16

10

Reserved

9 8

2 1 0

DACRES Reserved DACEN

RW 0 RW 0

Bits

[15:14]

[7]

[6]

[2]

[0]


VREFSEL DAC Channel Voltage Reference Source Selection

00: V

01: V

DDA

REF

Others: Reserved

DBON

DON

DACRES

DACEN

DAC Channel Output Buffer Enable

0: DAC channel output buffer is disabled

1: DAC channel output buffer is enabled

DAC Channel Directly Output Enable

0: DAC channel directly output is disabled

1: DAC channel directly output is enabled

DAC Channel Resolution Selection

0: 12-bit resolution

1: 8-bit resolution

If the DAC is operated in the synchronous mode, the DAC resolution is determined by the DACRES bit in the DAC0CR register, in such case the same bit in the

DAC1CR will be ignored.

DAC Channel Enable

0: DAC channel is disabled

1: DAC channel is enabled

Users should select only one DAC output path from DAC output, namely with buffer or directly output by configuring the DBON or DON bit respectively. It is forbidden to set both DBON and DON bits high at the same time, otherwise it will lead to unpredictable results.

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

DAC Channel 1 Data Holding Register – DAC1DHR

This register contains the right alignment data for DAC channel 1.

Offset: 0x03C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

15

7

14

6

13

Reserved

5

12 11 10

DAC1DATA

9 8

RW 0 RW 0 RW 0 RW 0

4

DAC1DATA

3 2 1 0


Bits

[11:0]


DAC1DATA DAC Channel 1 Holding Data

In the asynchronous mode:


[7:0] bits


[11:0] bits

Rev. 1.00 406 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

DAC Channel 1 Data Output Register – DAC1DOR

This register contains the data output for DAC channel 1.

Offset: 0x040


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

15

7

14

6

13

Reserved

5

12 11 10

DAC1DOUT

9 8

RO 0 RO 0 RO 0 RO 0

4

DAC1DOUT

3 2 1 0


Bits

[11:0]


DAC1DOUT DAC Channel 1 Data Output

These bits contain data output for DAC channel 1.

Rev. 1.00 407 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

22

General-Purpose Timer (GPTM)

Introduction

The General-Purpose Timer consists of one 16-bit up/down-counter, four 16-bit Capture/

Compare Registers (CCRs), one 16-bit Counter-Reload Register (CRR) and several control/status registers. It can be used for a variety of purposes including general timer, input signal pulse width measurement or output waveform generation such as single pulse generation or PWM output. The

GPTM supports an encoder interface using a quadrature decoder with two inputs.

ITI0

ITI1

ITI2

Edge

Detector

UEVG

TI0BED

TI0S0ED

TI1S1ED

TI0S1ED

TI1S0ED

TI0S0

TI1S1 f

CLKIN

TRCED

Quadrature

Decoder

STIED

CLKPULSE

Clock

Controller

UEVG

TEV

TME

UEV

CHxOREF

(x = 0 ~ 3)

CEVx

MDCFR

Register

STI

Up/Dn

Control

Slave

Controller

Master

Controller

MTO

To other Timers,

ADC and so on

TEV : Trigger Event

CEVx : Channel x Capture Event

MEVx : Channel x Compare Match Event

UEV : Update Event

GT_CH0

GT_CH1

GT_CH2

XOR

TI0

TI1

Input Filter

& Polarity Selection

& Edge Detection

TI0S0ED

TI0S1ED

Input Filter


& Edge Detection

TI1S0ED

TI1S1ED

TI2 Input Filter


& Edge Detection

TI2S2ED

TI2S3ED

GT_CH3

TI3

Input Filter


& Edge Detection

TI3S2ED

TI3S3ED

TRCED

Figure 113. GPTM Block Diagram

CK_PSC PSC

PRESCALER

CK_CNT

Restart

Pause

Trigger

Up/Dn

Reload Register

TM_CNT

(CRR)

UEV

CH0

PRESCALER

CH1

PRESCALER

CH2

PRESCALER

CH3

PRESCALER

CEV0

CEV1

CEV2

CEV3

CH0 Capture/Compare

Register (CH0CCR)

MEV0

CH0OREF Output

Control



MEV1

CH1OREF Output

Control



MEV2

CH2OREF Output

Control



MEV3

CH3OREF Output

Control

GT_CH0O

GT_CH1O

GT_CH2O

GT_CH3O

Rev. 1.00 408 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Features

▆

▆

▆

▆

▆

▆

▆

16-bit up/down auto-reload counter

16-bit programmable prescaler that allows division of the prescaler clock source by any factor between 1 and 65536 to generate the counter clock frequency

Up to 4 independent channels for:



● Generation of PWM waveform – Edge and Center-aligned Mode


Encoder interface controller with two inputs using quadrature decoder

Synchronization circuit to control the timer with external signals and to interconnect several timers together

Interrupt/PDMA generation with the following events:

● Update event

●

● Input capture event

●

Trigger event

Output compare match event

GPTM Master/Slave mode controller


Counter Mode

Up-Counting

In this mode the counter counts continuously from 0 to the counter-reload value, which is defined in the CRR register, in a count-up direction. Once the counter reaches the counter-reload value, the Timer Module generates an overflow event and the counter restarts to count once again from

0. This action will continue repeatedly. The counting direction bit DIR in the CNTCFR register should be set to 0 for the up-counting mode.

When the update event is generated by setting the UEVG bit in the EVGR register to 1, the counter value will also be initialized to 0.

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HT32F5828

Cortex ® -M0+ MCU

CK_PSC

CNT_EN

CK_CNT

CNTR

CRR

CRR Shadow

Register

PSCR

PSCR Shadow

Register

PSC_CNT

Counter Overflow

Update Event Flag

F5

F2

0

F5

0

0

F3

Write a new value

Figure 114. Up-counting Example

F4 F5

0

0

Update the new value

1

36

0

1

1

1

36

1

0

2

1

Software clearing

0

3

1

Down-Counting

In this mode the counter counts continuously from the counter-reload value, which is defined in the CRR register, to 0 in a count-down direction. Once the counter reaches 0, the Timer module generates an underflow event and the counter restarts to count once again from the counter-reload value. This action will continue repeatedly. The counting direction bit DIR in the CNTCFR register should be set to 1 for the down-counting mode.

When the update event is set by the UEVG bit in the EVGR register, the counter value will also be initialized to the counter-reload value.

CK_PSC

CNT_EN

CK_CNT

CNTR

CRR

CRR Shadow

Register

PSCR

PSCR Shadow

Register

PSC_CNT

Counter Underflow

Update Event Flag

F5

3

0

F5

0

0

2

Write a new value

Figure 115. Down-counting Example

1 0

0

36

Update a new value

1

36

0

35

1

1

36

1

0

34

Software clearing

1

33

0 1

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Center-Aligned Counting

In the center-aligned counting mode, the counter counts up from 0 to the counter-reload value and then counts down to 0 alternatively. The Timer module generates an overflow event when the counter counts to the counter-reload value in the up-counting mode and generates an underflow event when the counter counts to 0 in the down-counting mode. The counting direction bit DIR in the CNTCFR register is read-only and indicates the counting direction when in the center-aligned mode. The counting direction is updated by hardware automatically.

Setting the UEVG bit in the EVGR register will initialize the counter value to 0 irrespective of whether the counter is counting up or down in the center-aligned counting mode.

The update event interrupt flag bit in the INTSR register will be set to 1, when an overflow or underflow event occurs.

CK_PSC

CNT_EN

CK_CNT

CNTR

CRR

CRR Shadow

Register

Counter Overflow

Counter Underflow

Update Event Flag

F2

F5

F5

F3 F4 4

Write a new value

Figure 116. Center-aligned Counting Example

3 2

Software clearing

4

1

4

0 1 2

Software clearing

3

Clock Controller

The following describes the Timer Module clock controller which determines the clock source of the internal prescaler counter.

▆

Internal APB clock f

CLKIN

:

The default internal clock source is the APB clock f

CLKIN

used to drive the counter prescaler when the slave mode is disabled. When the slave mode selection bits SMSEL in the MDCFR register are set to 0x4, 0x5 or 0x6, the internal APB clock f

CLKIN

is the counter prescaler driving clock source. If the slave mode controller is enabled by setting SMSEL field in the MDCFR register to an available value including 0x1, 0x2, 0x3 and 0x7, the prescaler is clocked by other clock sources selected by the TRSEL field in the TRCFR register and described as follows.

▆

Quadrature Decoder:

To select Quadrature Decoder mode the SMSEL field should be set to 0x1, 0x2 or 0x3 in the

MDCFR register. The Quadrature Decoder function uses two input states of the GT_CH0 and

GT_CH1 pins to generate the clock pulse to drive the counter prescaler. The counting direction bit DIR is modified by hardware automatically at each transition on the input source signal. The input source signal can be derived from the GT_CH0 pin only, the GT_CH1 pin only or both

GT_CH0 and GT_CH1 pins.

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HT32F5828

Cortex ® -M0+ MCU

CLKPULSE

(Quadrature Decoder) f

CLKIN

(Internal APB clock)

STIED

(Trigger events)

▆

STIED:

The counter prescaler can count during each rising edge of the STI signal. This mode can be selected by setting the SMSEL field to 0x7 in the MDCFR register. Here the counter will act as an event counter. The input event, known as STI here, can be selected by setting the TRSEL field to an available value except the value of 0x0. When the STI signal is selected as the clock source, the internal edge detection circuitry will generate a clock pulse during each STI signal rising edge to drive the counter prescaler. It is important to note that if the TRSEL field is set to

0x0 to select the software UEVG bit as the trigger source, then when the SMSEL field is set to

0x7, the counter will be updated instead of counting.

PSCR CRR

CK_PSC

CLK

PSC Prescaler

Reset

CK_CNT

CLK

CNTR

Reset

Update Event

TM_CNT

TRSEL

SMSEL

Start/Stop

Figure 117. GPTM Clock Source Selection

Overflow /

Underflow UEVG bit

Slave Restart mode trigger

Rev. 1.00 412 of 637 December 28, 2020

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HT32F5828

Cortex ® -M0+ MCU

Trigger Controller

The trigger controller is used to select the trigger source and setup the trigger level or trigger edge condition. For the internal trigger input, it can be selected by the Trigger Selection bits TRSEL in the TRCFR register. For all the trigger sources except the UEVG bit software trigger, the internal edge detection circuitry will generate a clock pulse at each trigger signal rising edge to stimulate some GPTM functions which are triggered by a trigger signal rising edge.

Trigger Controller Block = Edge Trigger Mux + Level Trigger Mux

Internal Trigger Input

ITI0

ITI1

ITI2

Edge

Detection

ITI0ED

ITI1ED f

CLKIN

ITI2ED

Edge Trigger Source = Internal (ITIx) + Channel input (TIn)

Edge Trigger Mux

0

TI0S0ED

TI1S1ED

Reserved

Reserved

TRSEL[2:0]

TI0BED

ITI0ED

ITI1ED

ITI2ED

Reserved

000

001

010

011 others

STIED_S1

000

001

010

011 others

STIED_S0

0

1

TRSEL[3]

STIED

TRCED

Level Trigger Source = Internal (ITIx) + Channel input (TIn) + Software UEVG bit

S/W Set

UEVG Bit

TI0S0

TI1S1

Level Trigger Mux

Reserved

Reserved

TRSEL[2:0]

0

ITI0

ITI1

ITI2

Reserved

000

001

010

011 others

STI_S1

000

001

010

011 others

STI_S0

0

1

TRSEL[3]

STI

Figure 118. Trigger Controller Block

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HT32F5828

Cortex ® -M0+ MCU

Slave Controller

The GPTM can be synchronized with an external trigger in several modes including the Restart mode, the Pause mode and the Trigger mode which can be selected by the SMSEL field in the

MDCFR register. The trigger input of these modes comes from the STI signal which is selected by the TRSEL field in the TRCFR register. The operation modes in the Slave Controller are described in the accompanying sections.

Trigger Controller

STI

Slave

Controller

Trigger Event

Reset/Stop/Start Counter

SMSEL Restart/Pause/Trigger Mode

Figure 119. Slave Controller Diagram

Restart Mode

The counter and its prescaler can be reinitialized in response to a rising edge of the STI signal.

When an STI rising edge occurs, the update event software generation bit named UEVG will automatically be asserted by hardware and the trigger event flag will also be set. Then the counter and prescaler will be reinitialized. Although the UEVG bit is set to 1 by hardware, the update event does not really occur. It depends upon whether the update event disable control bit UEVDIS is set to 1 or not. If the UEVDIS is set to 1 to disable the update event to occur, there will no update event be generated, however the counter and prescaler are still reinitialized when the STI rising edge occurs. If the UEVDIS bit in the CNTCFR register is cleared to enable the update event to occur, an update event will be generated together with the STI rising edge, then all the preloaded registers will be updated.

Timer Counter Reload Register CRR = 32

STI source signal

(polarity=0)

STI source signal

(polarity=1)

STI

CK_CNT

UEVG bit

(reset counter)

CNTR

(Up-counting)

CNTR

(Down-counting)

TEVIF

27

27

28

26

29

25

Figure 120. GPTM in Restart Mode

Sync.

30

24

31

23

Trigger Event

0

32

1

31

2

30

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HT32F5828

Cortex ® -M0+ MCU

Pause Mode

In the Pause Mode, the selected STI input signal level is used to control the counter start/stop operation. The counter starts to count when the selected STI signal is at a high level and stops counting when the STI signal is changed to a low level, here the counter will maintain its present value and will not be reset. Since the Pause function depends upon the STI level to control the counter stop/start operation, the selected STI trigger signal can not be derived from the TI0BED signal.

STI source signal

(polarity=0)

STI source signal

(polarity=1)

STI

CK_ CNT

CNT_ EN

CNTR

TEVIF

Sync

27 28 29

Sync

30 31

Software clearing

Figure 121. GPTM in Pause Mode

Trigger Mode

After the counter is disabled to count, the counter can resume counting when an STI rising edge signal occurs. When an STI rising edge occurs, the counter will start to count from the current value in the counter. Note that if the STI signal is selected to be derived from the UEVG bit software trigger, the counter will not resume counting. When software triggering using the UEVG bit is selected as the STI source signal, there will be no clock pulse generated which can be used to make the counter resume counting. Note that the STI signal is only used to enable the counter to resume counting and has no effect on controlling the counter to stop counting.

STI source signal

(polarity=0)

STI source signal

(polarity=1)

STI

CK_CNT

CNT_EN

CNTR

(Up-counting)

TEVIF

27

Sync

28 29 30 31 32

Software clearing

Figure 122. GPTM in Trigger Mode

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Cortex ® -M0+ MCU

Master Controller

The GPTMs and TMs can be linked together internally for timer synchronization or chaining.

When one GPTM is configured to be in the Master Mode, the GPTM Master Controller will generate a Master Trigger Output (MTO) signal which includes a reset, a start, a stop signal or a clock source which is selected by the MMSEL field in the MDCFR register to trigger or drive another GPTM or TM, if exists, which is configured in the Slave Mode.

GPTMn Master

MMSEL

TSE

MTO ITI

GPTMm/TMm Slave

SMSEL

TRSEL

Figure 123. Master GPTMn and Slave GPTMm/TMm Connection

The Master Mode Selection field, MMSEL, in the MDCFR register is used to select the MTO source for synchronizing another slave GPTM or TM if exists.

UEVG bit

Counter enable signal

Update Event

Channel 0 Capture/Compare event

CH0OREF

CH1OREF

CH2OREF

CH3OREF

MTO

MMSEL

Figure 124. MTO Selection

For example, setting the MMSEL field to 0x5 is to select the CH1OREF signal as the MTO signal to synchronize another slave GPTM or TM. For a more detailed description, refer to the related

MMSEL field definitions in the MDCFR register.

Rev. 1.00 416 of 637 December 28, 2020

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Cortex ® -M0+ MCU

Channel Controller

The GPTM has four independent channels which can be used as capture inputs or compare match outputs. Each capture input or compare match output channel is composed of a preload register and a shadow register. Data access of the APB bus is always implemented by reading/writing the preload register.

When used in the input capture mode, the counter value is captured into the CHxCCR shadow register first and then transferred into the CHxCCR preload register when the capture event occurs.

When used in the compare match output mode, the contents of the CHxCCR preload register is copied into the associated shadow register, the counter value is then compared with the register value.

APB Bus Interface

CHxPSC

CHxCCR

(Preload Register)

Capture

Controller

Capture Transfer

Read CHxCCR

CHxCCR

(Shadow Register)

CHxCCS

CHxCCG

CHxE

Capture

Figure 125. Capture/Compare Block Diagram

Compare Transfer

Compare

Controller

CHxCCR

TM_CNT

CHxCCS

CHxPRE

Write CHxCCR

Update Event

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Capture Counter Value Transferred to CHxCCR

When the channel is used as a capture input, the counter value is captured into the Channel

Capture/Compare Register (CHxCCR) when an effective input signal transition occurs. Once the capture event occurs, the CHxCCIF flag in the INTSR register is set accordingly. If the CHxCCIF bit is already set, i.e., the flag has not yet been cleared by software, and another capture event on this channel occurs, the corresponding channel Over-Capture flag, named CHxOCF, will be set.

f

CLKIN

GT_CH0

(TI0)

CNTR 25

CHxCCR 0

26

CHxCCIF

CHxOCF

Figure 126. Input Capture Mode

27 28

26

29 30 31 32 33

32

34 35

Pulse Width Measurement

The input capture mode can be also used for pulse width measurement from signals on the GT_

CHx pins, TIx. The following example shows how to configure the GPTM operated in the input capture mode to measure the high pulse width and the input period on the GT_CH0 pin using channel 0 and channel 1. The basic steps are shown as follows.

▆

▆

▆

▆

▆

▆

▆

Configure the capture channel 0 (CH0CCS = 0x1) to select the TI0 signal as the capture input.

Configure the CH0P bit to 0 to choose the rising edge of the TI0 input as the active polarity.

Configure the capture channel 1 (CH1CCS = 0x2) to select the TI0 signal as the capture input.

Configure the CH1P bit to 1 to choose the falling edge of the TI0 input as the active polarity.

Configure the TRSEL bits to 0x1 to select TI0S0 as the trigger input.

Configure the Slave controller to operate in the Restart mode by setting the SMSEL field in the

MDCFR register to 0x4.

Enable the input capture mode by setting the CH0E and CH1E bits in the CHCTR register to 1.

As the following diagram shows, the high pulse width on the GT_CH0 pin will be captured into the CH1CCR register while the input period will be captured into the CH0CCR register after input capture operation.

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Cortex ® -M0+ MCU

Restart mode

Reset counter value

Restart mode

Reset counter value

GT_CH0

(TI0)

CNTR

7 0

Capture CH0

1 2 3 4 5

Capture CH1

6 7 0 1 2 3 4 5 6

CH0CCR

CH1CCR

Figure 127. PWM Pulse Width Measurement Example

7

4

Input Stage

The input stage consists of a digital filter, a channel polarity selection, edge detection and a channel prescaler. The channel 0 input signal (TI0) can be chosen to come from the GT_CH0 signal or the

Excusive-OR function of the GT_CH0, GT_CH1 and GT_CH2 signals. The channel input signal

(TIx) is sampled by a digital filter to generate a filtered input signal TIxFP. Then the channel polarity and the edge detection block can generate a TIxS0ED or TIxS1ED signal for the input capture function. The effective input event number can be set by the channel capture input source prescaler setting field, CHxPSC.

GT_CH0

GT_CH1

GT_CH2 f

XOR

TI0 sampling

TI0XOR

Filter

TI0F

TI0SRC f

CLKIN

TI0FP

TRCED

Edge

Detection

Edge

Detection f

CLKIN

TI0S0

TI0FN

CH0P

TI1S0

TI0S1

CH1P

TI1S1

GT_CH1 f

TI1 sampling

Filter

TI1FP

TI1F

TI1FN

Figure 128. Channel 0 and Channel 1 Input Stages

Edge

Detection

TI0S0ED

Edge

Detection

TI1S0ED

Edge

Detection

TI0S1ED

Edge

Detection

TI1S1ED

CH0CCS

CH1CCS

CH0PRESCALER

CH0PSC

CH1PRESCALER

CH1PSC

TI0BED

CH0PSC

CH0CAP Event

CH1PSC

CH1CAP Event

Rev. 1.00 419 of 637 December 28, 2020

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Cortex ® -M0+ MCU

GT_CH2

TI2 f sampling

Filter

TI2F

GT_CH3 f

TI3 sampling

Filter

TI3F

TI2FP

TI2FN

TRCED f

CLKIN

TI2S2

CH2P

TI3S2

TI3FP

TI3FN

TI2S3

CH3P

TI3S3

Edge

Detection

TI2S2ED

Edge

Detection

TI3S2ED

Edge

Detection

TI2S3ED

Edge

Detection

TI3S3ED

CH2CCS

CH2PRESCALER

CH2PSC

CH2PSC

CH2CAP Event

CH3PRESCALER

CH3PSC

CH3PSC

CH3CAP Event

CH3CCS

Figure 129. Channel 2 and Channel 3 Input Stages

Digital Filter

The digital filters are embedded in the input stage for the GT_CH0 ~ GT_CH3 pins respectively.

The digital filter in the GPTM is an N-event counter where N refers to how many valid transitions are necessary to output a filtered signal. The N value can be 0, 2, 4, 5, 6 or 8 according to the user selection for each filter by setting the TIxF field in the CHxICFR register.

Digital Filter (N=2)

No Filtered

TI0

D Q D Q D Q f

SYSTEM

CK CK f sampling

CK

Figure 130. TI0 Digital Filter Diagram with N = 2

J

CK

Q

K

Filtered

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Cortex ® -M0+ MCU

Quadrature Decoder

The Quadrature Decoder function uses two quadrantal inputs TI0 and TI1 derived from the GT_CH0 and GT_CH1 pins respectively to interact to generate the counter value. The DIR bit is modified by hardware automatically during each input source transition. The input source can be either

TI0 only, TI1 only or both TI0 and TI1, the selection made by setting the SMSEL field to 0x1,

0x2 or 0x3. The mechanism for changing the counter direction is shown in the following table.

The Quadrature decoder can be regarded as an external clock with a directional selection. This means that the counter counts continuously in the interval between 0 and the counter-reload value.

Therefore, users must configure the CRR register before the counter starts to count.

TI0SRC f

CLKIN

TRCED

Edge

Detection

GT_CH0

GT_CH1

GT_CH2

XOR

TI0XOR

Edge

Detection

TI0 f sampling

Filter

TI0FP TI0FN f

CLKIN

TI0S0 Edge

Detection

TI0S0ED

CH0CCS

CH0P CH0PRESCALER

TI0F

TI1S0 Edge

Detection

TI1S0ED

CH0PSC

TI0S1

Edge

Detection

TI0S1ED

CH1P

CH1PRESCALER

GT_CH1

TI1 f sampling

Filter

TI1FP TI1FN

TI1S1 Edge

Detection

TI1S1ED

CH1PSC

TI1F

Figure 131. Input Stage and Quadrature Decoder Block Diagram

TI0S0

TI1S1

TI0S0ED

TI1S0ED

TI0S1ED

TI1S1ED

CH1CCS

Quadrature

Decoder

SMSEL

TI0BED

CH0PSC

CH0CAP Event

CH1PSC

CH1CAP Event

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Table 59. Counting Direction and Encoding Signals

Counting Mode

Counting on TI0 only

(SMSEL = 0x1)

Counting on TI1 only

(SMSEL = 0x2)

Counting on TI0 and TI1

(SMSEL = 0x3)

Level

TI1S1 = High

TI1S1 = Low

TI0S0 = High

TI0S0 = Low

TI1S1 = High

TI1S1 = Low

TI0S0 = High

TI0S0 = Low

Rising

TI0S0

Falling

Down Up

Up Down

—

—

Down

Up

X

X

—

—

Up

Down

X

X

Rising

TI1S1

Falling

— —

—

Up

Down

X

X

Up

Down

—

Down

Up

X

X

Down

Up

Note : “—” → means “no counting”; “X” → impossible

TI0

TI1

Up

Down

Quadrature Decoder

Counting on Both TI0 & TI1

(CH0P = 0, CH1P = 0)

Figure 132. Both TI0 and TI1 Quadrature Decoder Counting

Output Stage

The GPTM has four channels for compare match, single pulse or PWM output function. The channel output GT_CHxO is controlled by the CHxOM, CHxP and CHxE bits in the corresponding

CHxOCFR, CHPOLR and CHCTR registers.

CNTR

CHxCCR f

CLKIN

Output Mode

Controller

CHxOREF

CHxP

CHxOM x: 0 ~ 3

Figure 133. Output Stage Block Diagram

Output Enable

Controller

CHxE

GT_CHxO

CHxOREF

CHxCMP Event

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Channel Output Reference Signal

When the GPTM is used in the compare match output mode, the Channel x Output Reference signal, CHxOREF, is defined by the CHxOM field setup. The CHxOREF signal has several types of output function which defines what happens to the output when the counter value matches the contents of the CHxCCR register. In addition to the low, high and toggle CHxOREF output types, there are also PWM mode 1 and PWM mode 2 outputs. In these modes, the CHxOREF signal level is changed according to the count direction and the relationship between the counter value and the CHxCCR content. There are also two modes which will force the output into an inactive or active state irrespective of the CHxCCR content or counter values. With regard to a more detailed description refer to the relative bit definition. The accompanying Table 60 shows a summary of the output type setup.

Table 60. Compare Match Output Setup

CHxOM Value

0x0

0x1

No change

Clear Output to 0

Compare Match Level

0x2

0x3

0x4

0x5

0x6

0x7

Set Output to 1

Toggle Output

Force Inactive Level

Force Active Level

PWM Mode 1

PWM Mode 2

Counter Value

CRR

CHxCCR

(New value 2)

CHxCCR

(New value 3)

CHxCCR

(New value 1)

CHxCCR

Update

CHxCCR value

TME

CHxOREF

CHxOM=0x3, CHxPRE=0

(Output toggle, preload disable)

(1) (2) (3)

Time

Figure 134. Toggle Mode Channel Output Reference Signal (CHxPRE = 0)

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Counter Value

CRR

CHxCCR

(New value 2)

CHxCCR

(New value 3)

CHxCCR

(New value 1)

CHxCCR

Update

CHxCCR value

TME

CHxOREF

CHxOM=0x3, CHxPRE=1

(Output toggle, preload enable)

(1) (2) (3)


Time

Counter Value

CRR

CHxCCR

Counter Value

CHxCCR

CRR

Counter Value

CRR

CHxOM = 0x6 CHxCCR = 0x0000

100%

CHxOREF

CHxCCIF

CHxOREF CHxOREF 0%

CHxCCIF CHxCCIF

CHxOM = 0x7

CHxOREF

Figure 136. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode

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Counter Value

CRR

CHxCCR

Counter Value

CHxCCR

CRR

CHxOM = 0x6

CHxOREF

100%

CHxOREF

CHxCCIF

CHxOM = 0x7

CHxOREF

CHxCCIF

Figure 137. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode

CMSEL= 0x1

0

CHxCCR = 3

CHxCCIF

CHxCCR = 4

CHxCCIF

CHxCCR >= 5

CHxCCIF

1

Up-counting

2 3

100%

4

CRR = 5

5 4

Down-counting

3 2 1 0 1

CHxCCR = 0 0%

CHxCCIF

Figure 138. PWM Mode Channel Output Reference Signal and Counter in Centre-aligned Mode

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Update Management

The Update event is used to update the CRR, the PSCR, the CHxACR and the CHxCCR values from the actual registers to the corresponding shadow registers. An update event occurs when the counter overflows or underflows, the software update control bit is triggered or an update event from the slave controller is generated.

The UEVDIS bit in the CNTCFR register can determine whether the update event occurs or not. When the update event occurs, the corresponding update event interrupt will be generated depending upon whether the update event interrupt generation function is enabled or not by configuring the UGDIS bit in the CNTCFR register. For more detailed description, refer to the

UEVDIS and UGDIS bit definition in the CNTCFR register

Update Event Management

Counter Overflow / Underflow

UEVG

Slave Restart mode

UEV (Update PSCR, CRR,

CHxCCR, CHxACR

Shadow Registers)

UEVDIS

Update Event Interrupt Management


UEVG

Slave Restart mode

UGDIS

Figure 139. Update Event Setting Diagram

UEVDIS

UEV interrupt

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STI

CHxOREF

(PWM1)

(PWM2)

CHxOREF

(PWM1)

(PWM2)

Single Pulse Mode

Once the timer is set to operate in the single pulse mode, it is not necessary to set the timer enable bit TME in the CTR register to 1 to enable the counter. The trigger to generate a pulse can be sourced from the STI signal rising edge or by setting the TME bit to 1 using software. Setting the

TME bit to 1 or a trigger from the STI signal rising edge can generate a pulse and then keep the

TME bit at a high state until the update event occurs or the TME bit is written to 0 by software.

If the TME bit is cleared to 0 using software, the counter will be stopped and its value held. If the

TME bit is automatically cleared to 0 by a hardware update event, the counter will be reinitialized.

Counter Value

CRR

CHxCCR

Counter reinitialized Counter stopped and held

Time

TME bit

Triggered by STI

Cleared by

Update Event

Triggered by S/W Cleared by S/W delay delay min. delay min. delay delay delay delay delay

Flag is set by update event and cleared by S/W

CHxIMAE=0

CHxIMAE=1

UEVIF

CHxCCIF

Flag is set by compare match and cleared by S/W

Figure 140. Single Pulse Mode

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In the Single Pulse mode, the STI active edge which sets the TME bit to 1 will enable the counter.

However, there exist several clock delays to perform the comparison result between the counter value and the CHxCCR value. In order to reduce the delay to a minimum value, the user can set the CHxIMAE bit in each CHxOCFR register. After an STI rising edge trigger occurs in the single pulse mode, the CHxOREF signal will immediately be forced to the state which the CHxOREF signal will change to as the compare match event occurs without taking the comparison result into account. The CHxIMAE bit is available only when the output channel is configured to operate in the PWM mode 1 or PWM mode 2 and the trigger source is derived from the STI signal.

Counter Value

CKDIV = 0

CRR

Up-Counting Mode

6

5

CHxCCR

3

2

1

0

GT_CNT

ITIx

STI

TME

Counter Start Time

CHxIMAE

CHxOREF

(PWM1)

(PWM2)

Minimum delay

Figure 141. Immediate Active Mode Minimum Delay

4

Time

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Asymmetric PWM Mode

Asymmetric PWM mode allows two center-aligned PWM signals to be generated with a programmable phase shift. While the PWM frequency is determined by the value of the CRR register, the duty cycle and the phase-shift are determined by the CHxCCR and CHxACR register.

When the counter is counting up, the PWM uses the value in CHxCCR as up-count compare value.

When the counter is into counting down stage, the PWM uses the value in CHxACR as down-count compare value. The Figure 142 is shown as an example for asymmetric PWM mode in centeraligned counting mode.

Note: Asymmetric PWM mode can only be operated in center-aligned counting mode.

CNTR 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1

CRR = 8

PWM center-aligned mode

CRR = 8

CCR = 3, ACR = X

CCR = 3

CHxOREF


CRR = 8

CCR = 5, ACR = X

CCR = 5

CHxOREF

Asymmetric PWM center-aligned mode

CRR = 8

CCR = 3, ACR = 5

CCR = 3

ACR = 5

CHxOREF


CRR = 8

CCR = 5, ACR = 3

CCR = 5

ACR = 3

CHxOREF

Figure 142. Asymmetric PWM Mode versus Center-Aligned Counting Mode

Phase delay = 2

Timer Interconnection

The timers can be internally connected together for timer chaining or synchronization. This can be implemented by configuring one timer to operate in the Master mode while configuring another timer to be in the Slave mode. The following figures present several examples of trigger selection for the master and slave modes.

Using One Timer to Enable/Disable another Timer Start or Stop Counting

▆

Configure GPTM as the master mode to send its channel 0 Output Reference signal CH0OREF as a trigger output (MMSEL = 0x4).

▆

▆

▆

▆

▆

Configure GPTM CH0OREF waveform.

Configure PWM0 to receive its input trigger source from the GPTM trigger output (TRSEL = 0xA).

Configure PWM0 to operate in the pause mode (SMSEL = 0x5).

Enable PWM0 by writing ‘1’ to the TME bit.

Enable GPTM by writing ‘1’ to the TME bit.

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Master GPTM f

CLKIN

GPTM

CH0OREF

GPTM

CNTR

Slave PWM0

PWM0

CNTR

PWM0

TEVIF

32 33

FA

34

FB

35

Figure 143. Pausing PWM0 using the GPTM CH0OREF Signal

FC

36

Software clearing

00

FD

01

Using one Timer to Trigger another Timer Start Counting

▆

Configure GPTM to operate in the master mode to send its Update Event UEV as the trigger output (MMSEL = 0x2).

▆

Configure the GPTM period by setting the CRR register.

▆

▆

▆

Configure PWM0 to get the input trigger source from the GPTM trigger output (TRSEL = 0xA).

Configure PWM0 to be in the slave trigger mode (SMSEL = 0x6).

Start GPTM by writing ‘1’ to the TME bit.

f

CLKIN

GPTM

UEVIF

GPTM

CNTR 13 14 15 00

PWM0

CNTR

PWM0

TME bit

FA FB

PWM0

TEVIF

Software clearing

Figure 144. Triggering PWM0 with GPTM Update Event

01

FC

02

FD

03

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Starting Two Timers Synchronously in Response to an External Trigger

▆

Configure GPTM to operate in the master mode to send its enable signal as a trigger output

(MMSEL = 0x1).

▆

▆

▆

▆

▆

Configure GPTM slave mode to receive its input trigger source from GT_CH0 pin (TRSEL = 0x1).

Configure GPTM to be in the slave trigger mode (SMSEL = 0x6).

Enable the GPTM master timer synchronization function by setting the TSE bit in the MDCFR register to 1 to synchronize the slave timer.

Configure PWM0 to receive its input trigger source from the GPTM trigger output (TRSEL = 0xA).


Master GPTM f

DTS

=f

CLKIN

TI0

TI0FP

TI0S0ED

GPTM (TME bit)

GPTM (TEVIF)

GPTM CK_PSC

GPTM CNTR

TSE=1

Delay

34 0

Write UEVG bit

1

ITI

Slave PWM0

PWM0 (TME bit)

PWM0 (TEVIF)

PWM0 CK_PSC

PWM0 CNTR 11 0 0

Write UEVG bit

Figure 145. Trigger GPTM and PWM0 with the GPTM CH0 Input

1

2

2

3

3

4 5

4 5

Trigger Peripherals Start

To interconnect to the peripherals, such as ADC, Timer and so on, the GPTM could output the

MTO signal or the channel compare match output signal CHxOREF (x = 0 ~ 3) to be used as peripherals input trigger signal and depending on the MCU specification.

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PDMA Request

The GPTM supports the interface for PDMA data transfer. There are certain events which can generate the PDMA requests if the corresponding enable control bits are set to 1 to enable the

PDMA access. These events are the GPTM update events, trigger events and channel capture/ compare events. When the PDMA request is generated from the GPTM channel, it can be derived from the channel capture/compare event or the GPTM update event selected by the channel PDMA selection bit, CHCCDS, for all channels. For more detailed PDMA configuring information, refer to the corresponding section in the PDMA chapter.

CHCCDS

CH0_EV

UEV_EV

CH1_EV

UEV_EV

CH2_EV

UEV_EV

CH3_EV

UEV_EV

UEV_EV

UEVDE

TRIG_EV

TEVDE

Figure 146. GPTM PDMA Mapping Diagram

CH0CCDE

0

1

0

1

0

1

0

1

CH1CCDE

CH2CCDE

CH3CCDE

CH0 PDMA Request

CH1 PDMA Request

CH2 PDMA Request

CH3 PDMA Request

UEV PDMA Request

Trigger PDMA Request

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Register Map

The following table shows the GPTM registers and reset values.

Table 61. GPTM Register Map

Register

CNTCFR

MDCFR

TRCFR

Offset Description

0x000 Timer Counter Configuration Register

0x004 Timer Mode Configuration Register

0x008 Timer Trigger Configuration Register

INTSR

CNTR

PSCR

CRR

CH0CCR

CH1CCR

CH2CCR

CH3CCR

CH0ACR

CH1ACR

CH2ACR

CH3ACR

CTR

CH0ICFR

CH1ICFR

CH2ICFR

CH3ICFR

CH0OCFR

CH1OCFR

CH2OCFR

CH3OCFR

CHCTR

CHPOLR

DICTR

EVGR

0x010 Timer Control Register

0x020 Channel 0 Input Configuration Register



0x02C Channel 3 Input Configuration Register

0x040 Channel 0 Output Configuration Register



0x04C Channel 3 Output Configuration Register

0x050 Channel Control Register

0x054 Channel Polarity Configuration Register

0x074 Timer PDMA/Interrupt Control Register

0x078 Timer Event Generator Register

0x07C Timer Interrupt Status Register

0x080 Timer Counter Register

0x084 Timer Prescaler Register

0x088 Timer Counter-Reload Register

0x090 Channel 0 Capture/Compare Register



0x09C Channel 3 Capture/Compare Register

0x0A0 Channel 0 Asymmetric Compare Register



0x0AC Channel 3 Asymmetric Compare Register

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_FFFF

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

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Timer Counter Configuration Register – CNTCFR

This register specifies the GPTM counter configuration.

Offset: 0x000


31 30 29 27

Type/Reset

Type/Reset

Type/Reset

Type/Reset

Bits

[24]

[17:16]

[9:8]

23

15

Field

DIR

7

CMSEL

CKDIV

22

14

6

21

13

5

28

Reserved

20

Reserved

12

Reserved

4

Reserved

19

11

3

26

18

10

2

25 24

DIR

RW 0

17 16

CMSEL

RW 0 RW 0

9 8

CKDIV

RW 0 RW 0

1 0

UGDIS UEVDIS

RW 0 RW 0

Descriptions

Counting Direction

0: Count-up

1: Count-down

Note: This bit is read only when the Timer is configured to be in the Center-aligned mode or when used as a Quadrature decoder.

Counter Mode Selection

00: Edge-aligned mode. Normal up-counting and down-counting available for this mode. Counting direction is defined by the DIR bit.

01: Center-aligned mode 1. The counter counts up and down alternatively. The compare match interrupt flag is set during the count-down period.

10: Center-aligned mode 2. The counter counts up and down alternatively. The compare match interrupt flag is set during the count-up period.

11: Center-aligned mode 3. The counter counts up and down alternatively. The compare match interrupt flag is set during the count-up and count-down periods.

Clock Division

These two bits define the frequency ratio between the timer clock (f dead-time clock (f

DTS clock.

00: f

01: f

10: f

DTS

= f

DTS

= f

DTS

= f

CLKIN

CLKIN

/ 2

CLKIN

11: Reserved

/ 4

CLKIN

) and the

). The dead-time clock is also used for digital filter sampling

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Bits

[1]

[0]

Field

UGDIS

UEVDIS

Descriptions

Update event interrupt generation disable control

0: Any of the following events will generate an update PDMA request or interrupt

- Counter overflow/underflow

- Setting the UEVG bit

- Update generation through the slave mode

1: Only counter overflow/underflow generates an update PDMA request or interrupt

Update Event Disable control

0: Enable the update event request by one of following events:




1: Disable the update event (However the counter and the prescaler are reinitialized if the UEVG bit is set or if a hardware restart is received from the slave mode)

Timer Mode Configuration Register – MDCFR

This register specifies the GPTM master and slave mode selection and single pulse mode.

Offset: 0x004


Type/Reset

Type/Reset

Type/Reset

Type/Reset

31

23

15

7

30

22

14

6

29

21

Reserved

13

Reserved

5

28

Reserved

20

12

4

Reserved

27

19

11

3

26 25 24

SPMSET

RW 0

16 18 17

MMSEL

RW 0 RW 0 RW 0

10 9

SMSEL

8

RW 0 RW 0 RW 0

2 1 0

TSE

RW 0

Bits

[24]

Field

SPMSET

Descriptions

Single Pulse Mode Setting

0: Counter counts normally irrespective of whether the update event occurred or not

1: Counter stops counting at the next update event and then the TME bit is cleared by hardware

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Bits

[18:16]

Field

MMSEL

Descriptions

Master Mode Selection

Master mode selection is used to select the MTO signal source which is used to synchronize the other slave timer.

MMSEL [2:0] Mode

000

001

010

011

Reset Mode

Enable Mode

Update Mode

Capture/Compare

Mode

Descriptions

The MTO signal in the Reset mode is an output derived from one of the following cases:

1. Software setting UEVG bit

2. The STI trigger input signal which will be output on the MTO signal line when the Timer is used in the slave Restart mode

The Counter Enable signal is used as the trigger output.

The update event is used as the trigger output according to one of the following cases when the

UEVDIS bit is cleared to 0:

1. Counter overflow / underflow

2. Software setting UEVG

3. Slave trigger input when used in slave restart mode

When a Channel 0 capture or compare match event occurs, it will generate a positive pulse used as the master trigger output.

100

101

110

111

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Bits

[10:8]

[0]

Field

SMSEL

TSE

Descriptions

Slave Mode Selection

SMSEL [2:0] Mode

000

001

010

011

100

101

110

111

Disable Mode

Quadrature

Decoder Mode 1

Quadrature

Decoder Mode 2

Quadrature

Decoder Mode 3

Restart Mode

Pause Mode

Trigger Mode

STIED

Descriptions

The prescaler is clocked directly by the internal clock.

The counter uses the clock pulse generated from the interaction between the TI0 and TI1 signals to drive the counter prescaler. A transition of the TI0 edge is used in this mode depending upon the TI1 level.

The counter uses the clock pulse generated from the interaction between the TI0 and TI1 signals to drive the counter prescaler. A transition of the TI1 edge is used in this mode depending upon the TI0 level.

The counter uses the clock pulse generated from the interaction between the TI0 and TI1 signals to drive the counter prescaler. A transition of one channel edge is used in the quadrature decoder mode 3 depending upon the other channel level.

The counter value restarts from 0 or the CRR shadow register value depending upon the counter mode on the rising edge of the STI signal.

The registers will also be updated.

The counter starts to count when the selected trigger input STI is high. The counter stops counting on the instant, not being reset, when the

STI signal changes its state to a low level. Both the counter start and stop control are determined by the STI signal.

The counter starts to count from the original value in the counter on the rising edge of the selected trigger input STI. Only the counter start control is determined by the STI signal.

The rising edge of the selected trigger signal STI will clock the counter.

Timer Synchronization Enable

0: No action

1: Master timer (current timer) will generate a delay to synchronize its slave timer through the MTO signal.

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Timer Trigger Configuration Register – TRCFR

This register specifies the trigger source selection of GPTM.

Offset: 0x008


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11

Reserved

10 9 8

3 2 1

TRSEL

0

RW 0 RW 0 RW 0 RW 0

Bits

[3:0]

Field

TRSEL

Descriptions

Trigger Source Selection

These bits are used to select the trigger input (STI) for counter synchronization.

0000: Software Trigger by setting the UEVG bit

0001: Filtered input of channel 0 (TI0S0)

0010: Filtered input of channel 1 (TI1S1)

0011: Reserved

1000: Channel 0 Edge Detector (TI0BED)

1001: Internal Timing Module Trigger 0 (ITI0)



Others: Reserved

Note: These bits must be updated only when they are not in use, i.e. the slave mode is disabled by setting the SMSEL field to 0x0.

Table 62. GPTM Internal Trigger Connection

Slave Timing Module

GPTM

ITI0

PWM0

ITI1

—

ITI2

PWM1

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Timer Control Register – CTR

This register specifies the timer enable bit (TME), CRR buffer enable bit (CRBE) and Channel PDMA selection bit (CHCCDS).

Offset: 0x010


31 30 29 26 25 24

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

Reserved

27

Reserved

19

12

4

Reserved

11

Reserved

3

18

10

2

17

9

16

CHCCDS

RW 0

8

1

CRBE

0

TME

RW 0 RW 0

Bits

[16]

[1]

[0]

Field

CHCCDS

CRBE

TME

Descriptions

Channel PDMA event selection

0: Channel PDMA request derived from the channel capture/compare event.

1: Channel PDMA request derived from the Update event.

Counter-Reload register Buffer Enable

0: Counter-reload register can be updated immediately

1: Counter-reload register can not be updated until the update event occurs

Timer Enable bit

0: GPTM off

1: GPTM on – GPTM functions normally

When the TME bit is cleared to 0, the counter is stopped and the GPTM consumes no power in any operation mode except for the single pulse mode and the slave trigger mode. In these two modes the TME bit can automatically be set to 1 by hardware which permits all the GPTM registers to function normally.

Rev. 1.00 439 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Channel 0 Input Configuration Register – CH0ICFR

This register specifies the channel 0 input mode configuration.

Offset: 0x020


30 29 28 31

TI0SRC

Type/Reset RW 0

23

Type/Reset

15

Type/Reset

7

Type/Reset

22

14

6

21

Reserved

13

5

Reserved

20

12

4

27

Reserved

26 25 24

19 18

CH0PSC

17 16

CH0CCS

RW 0 RW 0 RW 0 RW 0

11

Reserved

10 9 8

3 2 1

TI0F

0

RW 0 RW 0 RW 0 RW 0

Bits

[31]

[19:18]

[17:16]

Field

TI0SRC

CH0PSC

CH0CCS

Descriptions

Channel 0 Input Source TI0 Selection

0: The GT_CH0 pin is connected to channel 0 input TI0

1: The XOR operation output of the GT_CH0, GT_CH1, and GT_CH2 pins are connected to the channel 0 input TI0

Channel 0 Capture Input Source Prescaler Setting

These bits define the effective events of the channel 0 capture input. Note that the prescaler is reset once the Channel 0 Capture/Compare Enable bit, CH0E, in the

Channel Control register named CHCTR is cleared to 0.

00: No prescaler, channel 0 capture input signal is chosen for each active event

01: Channel 0 Capture input signal is chosen for every 2 events



Channel 0 Capture/Compare Selection

00: Channel 0 is configured as an output

01: Channel 0 is configured as an input derived from the TI0 signal


11: Channel 0 is configured as an input which comes from the TRCED signal derived from the Trigger Controller

Note: The CH0CCS field can be accessed only when the CH0E bit is cleared to 0.

Rev. 1.00 440 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[3:0]

Field

TI0F

Descriptions

Channel 0 Input Source TI0 Filter Setting

These bits define the frequency divided ratio used to sample the TI0 signal. The

Digital filter in the GPTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.

0000: No filter, the sampling clock is f

SYSTEM

0001: f sampling

0010: f

0011: f

0100: f sampling sampling sampling

0101: f sampling

0110: f sampling

0111: f sampling

1000: f sampling

= f

= f

= f

= f

DTS

= f

= f

= f

CLKIN

CLKIN

CLKIN

DTS

DTS

DTS

= f

DTS

, N = 2

, N = 4

, N = 8

/ 2, N = 6

/ 2, N = 8

/ 4, N = 6

/ 4, N = 8

/ 8, N = 6

1001: f

1010: f

1011: f

1100: f sampling sampling sampling sampling

1101: f sampling

1110: f sampling

1111: f sampling

= f

= f

= f

= f

= f

DTS

= f

DTS

= f

DTS

DTS

DTS

DTS

DTS

/ 8, N = 8

/ 16, N = 5

/ 16, N = 6

/ 16, N = 8

/ 32, N = 5

/ 32, N = 6

/ 32, N = 8



Offset: 0x024


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

Reserved

13

5

Reserved

20

12

4

27

Reserved

26 25 24

19 18

CH1PSC

17 16

CH1CCS

RW 0 RW 0 RW 0 RW 0

11

Reserved

10 9 8

3 2 1

TI1F

0

RW 0 RW 0 RW 0 RW 0

Bits

[19:18]

Field

CH1PSC

Descriptions








Rev. 1.00 441 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[17:16]

[3:0]

Field

CH1CCS

TI1F

Descriptions











SYSTEM

0001: f sampling

0010: f

0011: f


0101: f sampling

0110: f sampling

0111: f sampling

1000: f sampling

= f

= f

= f

= f

DTS

= f

= f

= f

CLKIN

CLKIN

CLKIN

DTS

DTS

DTS

= f

DTS

, N = 2

, N = 4

, N = 8

/ 2, N = 6

/ 2, N = 8

/ 4, N = 6

/ 4, N = 8

/ 8, N = 6

1001: f

1010: f

1011: f


1101: f sampling

1110: f sampling

1111: f sampling

= f

= f

= f

= f

= f

DTS

= f

DTS

= f

DTS

DTS

DTS

DTS

DTS

/ 8, N = 8

/ 16, N = 5

/ 16, N = 6

/ 16, N = 8

/ 32, N = 5

/ 32, N = 6

/ 32, N = 8

Rev. 1.00 442 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU



Offset: 0x028


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

Reserved

13

5

Reserved

20

12

4

27

Reserved

26 25 24

19 18

CH2PSC

17 16

CH2CCS

RW 0 RW 0 RW 0 RW 0

11

Reserved

10 9 8

3 2 1

TI2F

0

RW 0 RW 0 RW 0 RW 0

Bits

[19:18]

[17:16]

Field

CH2PSC

CH2CCS

Descriptions














Rev. 1.00 443 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[3:0]

Field

TI2F

Descriptions





SYSTEM

0001: f sampling

0010: f

0011: f


0101: f sampling

0110: f sampling

0111: f sampling

1000: f sampling

= f

= f

= f

= f

DTS

= f

= f

= f

CLKIN

CLKIN

CLKIN

DTS

DTS

DTS

= f

DTS

, N = 2

, N = 4

, N = 8

/ 2, N = 6

/ 2, N = 8

/ 4, N = 6

/ 4, N = 8

/ 8, N = 6

1001: f

1010: f

1011: f


1101: f sampling

1110: f sampling

1111: f sampling

= f

= f

= f

= f

= f

DTS

= f

DTS

= f

DTS

DTS

DTS

DTS

DTS

/ 8, N = 8

/ 16, N = 5

/ 16, N = 6

/ 16, N = 8

/ 32, N = 5

/ 32, N = 6

/ 32, N = 8



Offset: 0x02C


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

Reserved

13

5

Reserved

20

12

4

27

Reserved

26 25 24

19 18

CH3PSC

17 16

CH3CCS

RW 0 RW 0 RW 0 RW 0

11

Reserved

10 9 8

3 2 1

TI3F

0

RW 0 RW 0 RW 0 RW 0

Bits

[19:18]

Field

CH3PSC

Descriptions








Rev. 1.00 444 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[17:16]

[3:0]

Field

CH3CCS

TI3F

Descriptions











SYSTEM

0001: f sampling

0010: f

0011: f


0101: f sampling

0110: f sampling

0111: f sampling

1000: f sampling

= f

= f

= f

= f

DTS

= f

= f

= f

CLKIN

CLKIN

CLKIN

DTS

DTS

DTS

= f

DTS

, N = 2

, N = 4

, N = 8

/ 2, N = 6

/ 2, N = 8

/ 4, N = 6

/ 4, N = 8

/ 8, N = 6

1001: f

1010: f

1011: f


1101: f sampling

1110: f sampling

1111: f sampling

= f

= f

= f

= f

= f

DTS

= f

DTS

= f

DTS

DTS

DTS

DTS

DTS

/ 8, N = 8

/ 16, N = 5

/ 16, N = 6

/ 16, N = 8

/ 32, N = 5

/ 32, N = 6

/ 32, N = 8

Rev. 1.00 445 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Channel 0 Output Configuration Register – CH0OCFR

This register specifies the channel 0 output mode configuration.

Offset: 0x040


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

14 13 12 11

Reserved

6 5 4 3

Reserved CH0IMAE CH0PRE Reserved

RW 0 RW 0

10

2

9

1

CH0OM[2:0]

8

CH0OM[3]

RW 0

0

RW 0 RW 0 RW 0

Bits

[5]

[4]


CH0IMAE Channel 0 Immediate Active Enable

0: No action

1: Single pulse Immediate Active Mode is enabled

The CH0OREF signal will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH0CCR values.

The effective duration ends automatically at the next overflow or underflow event.

Note: The CH0IMAE bit is available only if the channel 0 is configured to be operated in the PWM mode 1 or PWM mode 2.

CH0PRE Channel 0 Capture/Compare Register (CH0CCR) Preload Enable

0: CH0CCR preload function is disabled

The CH0CCR register can be immediately assigned a new value when the CH0PRE bit is cleared to 0 and the updated CH0CCR value is used immediately.

1: CH0CCR preload function is enabled

The new CH0CCR value will not be transferred to its shadow register until the update event occurs.

Rev. 1.00 446 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[8][2:0]


CH0OM[3:0] Channel 0 Output Mode Setting

These bits define the functional types of the output reference signal CH0OREF.

0000: No Change

0001: Output 0 on compare match


0011: Output toggles on compare match

0100: Force inactive – CH0OREF is forced to 0

0101: Force active – CH0OREF is forced to 1

0110: PWM mode 1

- During up-counting, channel 0 has an active level when CNTR <

CH0CCR or otherwise has an inactive level.

- During down-counting, channel 0 has an inactive level when CNTR >

CH0CCR or otherwise has an active level.

0111: PWM mode 2

- During up-counting, channel 0 is has an inactive level when CNTR <


- During down-counting, channel 0 has an active level when CNTR >


1110: Asymmetric PWM mode 1




CH0ACR or otherwise has an active level.


- During up-counting, channel 0 has an inactive level when CNTR <



CH0ACR or otherwise has an inactive level

Note: When channel 0 is used as asymmetric PWM output mode, the Counter Mode

Selection bit in Counter Configuration Register must be configured as Centeraligned Counting mode (CMSEL = 0x1/0x2/0x3).

Rev. 1.00 447 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU



Offset: 0x044


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

14 13 12 11

Reserved

6 5 4 3


RW 0 RW 0

10

2

9

1

CH1OM[2:0]

8

CH1OM[3]

RW 0

0

RW 0 RW 0 RW 0

Bits

[5]

[4]



0: No action






0: CH1CCR preload function is disabled.




Rev. 1.00 448 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[8][2:0]




0000: No Change






0110: PWM mode 1





0111: PWM mode 2

















Rev. 1.00 449 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU



Offset: 0x048


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

14 13 12 11

Reserved

6 5 4 3


RW 0 RW 0

10

2

9

1

CH2OM[2:0]

8

CH2OM[3]

RW 0

0

RW 0 RW 0 RW 0

Bits

[5]

[4]



0: No action










Rev. 1.00 450 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[8][2:0]




0000: No Change






0110: PWM mode 1





0111: PWM mode 2

















Rev. 1.00 451 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU



Offset: 0x04C


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

14 13 12 11

Reserved

6 5 4 3


RW 0 RW 0

10

2

9

1

CH3OM[2:0]

8

CH3OM[3]

RW 0

0

RW 0 RW 0 RW 0

Bits

[5]

[4]



0: No action










Rev. 1.00 452 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[8][2:0]



These bits define the functional types of the output reference signal CH3OREF

0000: No Change






0110: PWM mode 1





0111: PWM mode 2




CH3CCR or otherwise has an inactive level













Rev. 1.00 453 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Channel Control Register – CHCTR

This register contains the channel capture input or compare output function enable control bits.

Offset: 0x050


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

Type/Reset

15 14 13 12 11

Reserved

10 9 8

7

Reserved

6

CH3E

RW 0

5

Reserved

4

CH2E

RW 0

3

Reserved

2

CH1E

RW 0

1

Reserved

0

CH0E

RW 0

Bits

[6]

[4]

[2]

Field

CH3E

CH2E

CH1E

Descriptions

Channel 3 Capture/Compare Enable

- Channel 3 is configured as an input (CH3CCS = 0x1/0x2/0x3)

0: Input Capture Mode is disabled

1: Input Capture Mode is enabled

- Channel 3 is configured as an output (CH3CCS = 0x0)

0: Off – Channel 3 output signal CH3O is not active

1: On – Channel 3 output signal CH3O is generated on the corresponding output pin















Rev. 1.00 454 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[0]

Field

CH0E

Descriptions








Channel Polarity Configuration Register – CHPOLR

This register contains the channel capture input or compare output polarity control.

Offset: 0x054


Type/Reset

31

23

30

22

29

21

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

Type/Reset

Type/Reset

Type/Reset

15 14 13 12 11

Reserved

10 9 8

7

Reserved

6

CH3P

RW 0

5

Reserved

4

CH2P

RW 0

3

Reserved

2

CH1P

RW 0

1

Reserved

0

CH0P

RW 0

Bits

[6]

[4]

Field

CH3P

CH2P

Descriptions

Channel 3 Capture/Compare Polarity

- When Channel 3 is configured as an input (CH3CCS = 0x1/0x2/0x3)

0: capture event occurs on a Channel 3 rising edge

1: capture event occurs on a Channel 3 falling edge

- When Channel 3 is configured as an output (CH3CCS = 0x0)

0: Channel 3 Output is active high

1: Channel 3 Output is active low








Rev. 1.00 455 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[2]

[0]

Field

CH1P

CH0P

Descriptions















Timer PDMA/Interrupt Control Register – DICTR

This register contains the timer PDMA and interrupt enable control bits.

Offset: 0x074


Type/Reset

Type/Reset

Type/Reset

Type/Reset

31

23

15

7

30

22

14

6

29

Reserved

21

Reserved

13

Reserved

5

Reserved

28

20

12

4

27 26 25 24

TEVDE Reserved UEVDE

19

RW 0

18 17

RW 0

16

CH3CCDE CH2CCDE CH1CCDE CH0CCDE

RW 0 RW 0 RW 0 RW 0

11 10 9 8

TEVIE

RW 0

Reserved UEVIE

RW 0

3 2 1 0

CH3CCIE CH2CCIE CH1CCIE CH0CCIE

RW 0 RW 0 RW 0 RW 0

Bits

[26]

[24]

[19]

[18]


TEVDE

UEVDE

Trigger event PDMA Request Enable

0: Trigger PDMA request is disabled

1: Trigger PDMA request is enabled

Update event PDMA Request Enable

0: Update event PDMA request is disabled

1: Update event PDMA request is enabled

CH3CCDE Channel 3 Capture/Compare PDMA Request Enable

0: Channel 3 PDMA request is disabled

1: Channel 3 PDMA request is enabled




Rev. 1.00 456 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[17]

[2]

[1]

[0]

[8]

[3]

[16]

[10]








TEVIE Trigger event Interrupt Enable

0: Trigger event interrupt is disabled

1: Trigger event interrupt is enabled

UEVIE

CH3CCIE

Update event Interrupt Enable

0: Update event interrupt is disabled

1: Update event interrupt is enabled

Channel 3 Capture/Compare Interrupt Enable

0: Channel 3 interrupt is disabled

1: Channel 3 interrupt is enabled

CH2CCIE

CH1CCIE

CH0CCIE










Rev. 1.00 457 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Timer Event Generator Register – EVGR

This register contains the software event generation bits.

Offset: 0x078


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

Reserved

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11 10

TEVG

9

Reserved

8

UEVG

3

WO 0

2 1

WO 0

0

CH3CCG CH2CCG CH1CCG CH0CCG

WO 0 WO 0 WO 0 WO 0

Bits

[10]

[8]

[3]

[2]

Field

TEVG

UEVG

CH3CCG

CH2CCG

Descriptions

Trigger Event Generation

The trigger event TEV can be generated by setting this bit. It is cleared by hardware automatically.

0: No action

1: TEVIF flag is set

Update Event Generation

The update event UEV can be generated by setting this bit. It is cleared by hardware automatically.

0: No action

1: Reinitialize the counter

The counter value returns to 0 or the CRR preload value, depending on the counter mode in which the current timer is being used. An update operation of any related registers will also be performed. For more detailed descriptions, refer to the corresponding section.

Channel 3 Capture/Compare Generation

A Channel 3 capture/compare event can be generated by setting this bit. It is cleared by hardware automatically.

0: No action

1: Capture/compare event is generated on channel 3

If Channel 3 is configured as an input, the counter value is captured into the

CH3CCR register and then the CH3CCIF bit is set. If Channel 3 is configured as an output, the CH3CCIF bit is set.



0: No action




Rev. 1.00 458 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[1]

[0]

Field

CH1CCG

CH0CCG

Descriptions



0: No action






0: No action




Timer Interrupt Status Register – INTSR

This register stores the timer interrupt status.

Offset: 0x07C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

15 14 13

Reserved

12 11 10

TEVIF

W0C 0

9

Reserved

8

UEVIF

W0C 0

7 6 5 4 3 2 1 0

CH3OCF CH2OCF CH1OCF CH0OCF CH3CCIF CH2CCIF CH1CCIF CH0CCIF

Type/Reset W0C 0 W0C 0 W0C 0 W0C 0 W0C 0 W0C 0 W0C 0 W0C 0

Bits

[10]

Field

TEVIF

Descriptions

Trigger Event Interrupt Flag

This flag is set by hardware on a trigger event and is cleared by software.

0: No trigger event occurs

1: Trigger event occurs

Rev. 1.00 459 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[8]

[7]

[6]

[5]

[4]

[3]

[2]

Field

UEVIF

CH3OCF

CH2OCF

CH1OCF

CH0OCF

CH3CCIF

CH2CCIF

Descriptions

Update Event Interrupt Flag

This bit is set by hardware on an update event and is cleared by software.

0: No update event occurs

1: Update event occurs

Note: The update event is derived from the following conditions:

- The counter overflows or underflows

- The UEVG bit is asserted

- A restart trigger event occurs from the slave trigger input

Channel 3 Over-Capture Flag

This flag is set by hardware and cleared by software.

0: No over-capture event is detected

1: Capture event occurs again when the CH3CCIF bit is already set and it is not yet cleared by software




1: Capture event occurs again when the CH2CCIF bit is already set and it is not cleared yet by software




1: Capture event occurs again when the CH1CCIF bit is already set and it is not cleared yet by software.




1: Capture event occurs again when the CH0CCIFbit is already set and it is not yet cleared by software.

Channel 3 Capture/Compare Interrupt Flag

- Channel 3 is configured as an output:

0: No match event occurs

1: The content of the counter CNTR has matched the content of the CH3CCR register

This flag is set by hardware when the counter value matches the CH3CCR value except in the center-aligned mode. It is cleared by software.

- Channel 3 is configured as an input:

0: No input capture occurs

1: Input capture occurs

This bit is set by hardware on a capture event. It is cleared by software or by reading the CH3CCR register.








1: Input capture occurs.


Rev. 1.00 460 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[1]

[0]

Field

CH1CCIF

CH0CCIF

Descriptions



















Rev. 1.00 461 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Timer Counter Register – CNTR

This register stores the timer counter value.

Offset: 0x080


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CNTV

10 9 8


7 6 5 4 3 2 1 0

CNTV


Bits

[15:0]

Field

CNTV

Descriptions

Counter Value

Rev. 1.00 462 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Timer Prescaler Register – PSCR

This register specifies the timer prescaler value to generate the counter clock.

Offset: 0x084


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PSCV

10 9 8


7 6 5 4 3 2 1 0

PSCV


Bits

[15:0]

Field

PSCV

Descriptions

Prescaler Value

These bits are used to specify the prescaler value to generate the counter clock frequency f

CK_CNT

.

f

CK_CNT

= f

CK_PSC

PSCV[15:0]+1

, where the f

CK_PSC

is the prescaler clock source.

Rev. 1.00 463 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Timer Counter-Reload Register – CRR

This register specifies the timer counter-reload value.

Offset: 0x088

Reset value: 0x0000_FFFF

31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CRV

10 9 8


7 6 5 4 3 2 1 0

CRV


Bits

[15:0]

Field

CRV

Descriptions

Counter-Reload Value

The CRV is the reload value which is loaded into the actual counter register.

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Channel 0 Capture/Compare Register – CH0CCR

This register specifies the timer channel 0 capture/compare value.

Offset: 0x090


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH0CCV

10 9 8


7 6 5 4 3 2 1 0

CH0CCV


Bits

[15:0]

Field

CH0CCV

Descriptions

Channel 0 Capture/Compare Value

- When Channel 0 is configured as an output:

The CH0CCR value is compared with the counter value and the comparison result is used to trigger the CH0OREF output signal.

- When Channel 0 is configured as an input:

The CH0CCR register stores the counter value captured by the last channel 0 capture event.

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Cortex ® -M0+ MCU



Offset: 0x094


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH1CCV

10 9 8


7 6 5 4 3 2 1 0

CH1CCV


Bits

[15:0]

Field

CH1CCV

Descriptions






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HT32F5828

Cortex ® -M0+ MCU



Offset: 0x098


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH2CCV

10 9 8


7 6 5 4 3 2 1 0

CH2CCV


Bits

[15:0]

Field

CH2CCV

Descriptions






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HT32F5828

Cortex ® -M0+ MCU



Offset: 0x09C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH3CCV

10 9 8


7 6 5 4 3 2 1 0

CH3CCV


Bits

[15:0]

Field

CH3CCV

Descriptions






Rev. 1.00 468 of 637 December 28, 2020

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Cortex ® -M0+ MCU

Channel 0 Asymmetric Compare Register – CH0ACR

This register specifies the timer channel 0 asymmetric compare value.

Offset: 0x0A0


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH0ACV

10 9 8


7 6 5 4 3 2 1 0

CH0ACV


Bits

[15:0]

Field

CH0ACV

Descriptions

Channel 0 Asymmetric Compare Value

When channel 0 is configured as asymmetric PWM mode and the counter is counting down, the value written into this register will be compared to the counter.



Offset: 0x0A4


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH1ACV

10 9 8


7 6 5 4 3

CH1ACV

2 1 0


Bits

[15:0]

Field

CH1ACV

Descriptions



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Cortex ® -M0+ MCU



Offset: 0x0A8


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH2ACV

10 9 8


7 6 5 4 3 2 1 0

CH2ACV


Bits

[15:0]

Field

CH2ACV

Descriptions





Offset: 0x0AC


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH3ACV

10 9 8


7 6 5 4 3

CH3ACV

2 1 0


Bits

[15:0]

Field

CH3ACV

Descriptions



Rev. 1.00 470 of 637 December 28, 2020

ITI0

ITI1

ITI2

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

23

Pulse-Width-Modulation Timer (PWM)

Introduction

The Pulse-Width-Modulation Timer consists of one 16-bit up/down-counter, four 16-bit Compare

Registers (CRs), one 16-bit Counter-Reload Register (CRR) and several control/status registers. It can be used for a variety of purposes including general timer and output waveform generation such as single pulse generation or PWM output.

f

CLKIN

Edge

Detector

STIED

STI

Clock

Controller

TEV UEVG

TME

UEV

CHxOREF

(x = 0 ~ 3)

MDCFR

Register

Slave

Controller

Master

Controller

MTO To other Timers,

ADC and so on

TEV : Trigger Event

MEVx : Channel x Compare Match Event

UEV : Update Event

CK_PSC PSC

PRESCALER

CK_CNT

Restart

Pause

Trigger

Up/Down

TM_CNT

Reload

Register

(CRR)

UEV

CH0 Compare Register

(CH0CR)

MEV0

CH0OREF


(CH1CR)

MEV1

CH1OREF


(CH2CR)

MEV2

CH2OREF


(CH3CR)

MEV3

CH3OREF

Figure 147. PWM Block Diagram

Output

Control

Output

Control

Output

Control

Output

Control

PWM_CH0

PWM_CH1

PWM_CH2

PWM_CH3

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Cortex ® -M0+ MCU

Features

▆

▆

▆

▆

▆

▆

16-bit up/down auto-reload counter

16-bit programmable prescaler that allows division of the prescaler clock source by any factor between 1 and 65536 to generate the counter clock frequency

Up to 4 independent channels for:


● Generation of PWM waveform - Edge and Center-aligned Mode


Synchronization circuit to control the timer with external signals and to interconnect several timers together

Interrupt/PDMA generation with the following events:

● Update event

● Trigger event

● Output compare match event

PWM Master/Slave mode controller


Counter Mode

Up-Counting

In this mode the counter counts continuously from 0 to the counter-reload value, which is defined in the CRR register, in a count-up direction. Once the counter reaches the counter-reload value, the Timer Module generates an overflow event and the counter restarts to count once again from

0. This action will continue repeatedly. The counting direction bit DIR in the CNTCFR register should be set to 0 for the up-counting mode.

When the update event is generated by setting the UEVG bit in the EVGR register to 1, the counter value will also be initialized to 0.

CK_PSC

CNT_EN

CK_CNT

CNTR

CRR

CRR Shadow

Register

PSCR

PSCR Shadow

Register

PSC_CNT

Counter Overflow

Update Event Flag

F5

F2

0

F5

0

0

F3

Write a new value


F4 F5

0

0


1

36

0

1

1

1

36

1

0

2

1

Software clearing

0

3

1

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Cortex ® -M0+ MCU

Down-Counting

In this mode the counter counts continuously from the counter-reload value, which is defined in the CRR register, to 0 in a count-down direction. Once the counter reaches 0, the Timer module generates an underflow event and the counter restarts to count once again from the counter-reload value. This action will continue repeatedly. The counting direction bit DIR in the CNTCFR register should be set to 1 for the down-counting mode.

When the update event is set by the UEVG bit in the EVGR register, the counter value will also be initialized to the counter-reload value.

CK_PSC

CNT_EN

CK_CNT

CNTR

CRR

CRR Shadow

Register

PSCR

PSCR Shadow

Register

PSC_CNT

Counter Underflow

Update Event Flag

F5

3

0

F5

0

0

2

Write a new value

Figure 149. Down-counting Example

1 0

0

36

Update a new value

1

36

0

35

1

1

36

1

0

34

Software clearing

1

33

0 1

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HT32F5828

Cortex ® -M0+ MCU

Center-Aligned Counting

In the center-aligned counting mode, the counter counts up from 0 to the counter-reload value and then counts down to 0 alternatively. The Timer module generates an overflow event when the counter counts to the counter-reload value in the up-counting mode and generates an underflow event when the counter counts to 0 in the down-counting mode. The counting direction bit DIR in the CNTCFR register is read-only and indicates the counting direction when in the center-aligned mode. The counting direction is updated by hardware automatically.

Setting the UEVG bit in the EVGR register will initialize the counter value to 0 irrespective of whether the counter is counting up or down in the center-aligned counting mode.

The update event interrupt flag bit in the INTSR register will be set to 1, when an overflow or underflow event occurs.

CK_PSC

CNT_EN

CK_CNT

CNTR

CRR

CRR Shadow

Register

Counter Overflow

Counter Underflow

Update Event Flag

F2

F5

F5

F3 F4 4

Write a new value

Figure 150. Center-aligned Counting Example

3 2

Software clearing

4

1

4

0 1 2

Software clearing

3

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Cortex ® -M0+ MCU



▆


CLKIN

:


CLKIN

used to drive the counter prescaler.

▆

STIED:




PSCR CRR f

CLKIN

(Internal APB clock) Update Event

STIED

(Trigger events)

CK_PSC

CLK

PSC Prescaler

Reset

CK_CNT

CLK

CNTR

Reset

TM_CNT

TRSEL

SMSEL

Start/Stop

Figure 151. PWM Clock Source Selection

Overflow /

Underflow UEVG bit


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Cortex ® -M0+ MCU


The trigger controller is used to select the trigger source and setup the trigger level or edge trigger condition. For the internal trigger input, it can be selected by the Trigger Selection bits TRSEL in the TRCFR register. For all the trigger sources except the UEVG bit software trigger, the internal edge detection circuitry will generate a clock pulse at each trigger signal rising edge to stimulate some PWM functions which are triggered by a trigger signal rising edge.

Trigger Controller Block = Edge Trigger Mux + Level Trigger Mux

Internal Trigger Input

ITI0

ITI1

ITI2

Edge Detection

ITI0ED

ITI1ED

ITI2ED f

CLKIN

Edge Trigger Source = Internal (ITIx)


Reserved

ITI0ED

ITI1ED

ITI2ED

Reserved

0000

1001

1010

1011 others

TRSEL[3:0]

STIED

Level Trigger Source = Internal (ITIx) + Software UEVG bit


S/W Set UEVG Bit

ITI0

ITI1

ITI2

Reserved

0000

1001

1010

1011 others

TRSEL[3:0]


STI

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Cortex ® -M0+ MCU


The PWM can be synchronized with an external trigger in several modes including the Restart mode, the Pause mode and the Trigger mode which is selected by the SMSEL field in the MDCFR register. The trigger input of these modes comes from the STI signal which is selected by the

TRSEL field in the TRCFR register. The operation modes in the Slave Controller are described in the accompanying sections.

Trigger Controller

STI

Slave

Controller

Trigger Event


SMSEL Restart/Pause/Trigger Mode


Restart Mode




STI source signal

(polarity=0)

STI source signal

(polarity=1)

STI

CK_CNT

UEVG bit

(reset counter)

CNTR

(Up-counting)

CNTR

(Down-counting)

TEVIF

27

27

28

26

29

25

Figure 154. PWM in Restart Mode

Sync.

30

24

31

23

Trigger Event

0

32

1

31

2

30

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Cortex ® -M0+ MCU

Pause Mode

In the Pause Mode, the selected STI input signal level is used to control the counter start/stop operation. The counter starts to count when the selected STI signal is at a high level and stops counting when the STI signal is changed to a low level, here the counter will maintain its present value and will not be reset. Since the Pause function depends upon the STI level to control the counter stop/start operation.

STI source signal

(polarity=0)

STI source signal

(polarity=1)

STI

CK_ CNT

CNT_ EN

CNTR

TEVIF

Sync

27 28 29

Sync

30 31

Software clearing

Figure 155. PWM in Pause Mode

Trigger Mode


STI source signal

(polarity=0)

STI source signal

(polarity=1)

STI

CK_CNT

CNT_EN

CNTR

(Up-counting)

TEVIF

27

Sync

28 29 30 31 32

Software clearing

Figure 156. PWM in Trigger Mode

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Cortex ® -M0+ MCU

Master Controller

The PWMs and TMs can be linked together internally for timer synchronization or chaining. When one PWM is configured to be in the Master Mode, the PWM Master Controller will generate a

Master Trigger Output (MTO) signal which includes a reset, a start, a stop signal or a clock source which is selected by the MMSEL field in the MDCFR register to trigger or drive another PWM or

TM, if exists, which is configured in the Slave Mode.

PWMn Master

MMSEL

TSE

MTO ITI

PWMm/TMm Slave

SMSEL

TRSEL

Figure 157. Master PWMn and Slave PWMm/TMm Connection

The Master Mode Selection bits, MMSEL, in the MDCFR register are used to select the MTO source for synchronizing another slave PWM or TM if exists.

UEVG bit

Counter enable signal

Update Event

CH0OREF

CH1OREF

CH2OREF

CH3OREF

MTO

MMSEL

Figure 158. MTO Selection

For example, setting the MMSEL field to 0x5 is to select the CH1OREF signal as the MTO signal to synchronize another slave PWM or TM. For a more detailed description, refer to the related

MMSEL field definitions in the MDCFR register.

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Cortex ® -M0+ MCU


The PWM has four independent channels which can be used as compare match outputs. Each compare match output channel is composed of a preload register and a shadow register. Data access of the APB bus is always implemented by reading/writing preload register.

When used in the compare match output mode, the contents of the CHxCR preload register is copied into the associated shadow register; the counter value is then compared with the register value.

APB Bus Interface

CHxCR

(Preload Register)

Compare Transfer

CHxCR

(Shadow Register)

Compare

Controller

Write CHxCR

Update Event

CNTR CHxPRE

Figure 159. Compare Block Diagram

Output Stage

The PWM has four channels for compare match, single pulse or PWM output function. The channel output PWM_CHx is controlled by the CHxOM, CHxP and CHxE bits in the corresponding

CHxOCFR, CHPOLR and CHCTR registers.

CNTR

CHxCR f

CLKIN

Output Mode

Controller x: 0 ~ 3

CHxOM


CHxOREF

CHxP

Output Enable

Controller

CHxE

PWM_CHx

CHxOREF

CHxCMP Event

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Cortex ® -M0+ MCU


When the PWM is used in the compare match output mode, the Channel x Output Reference signal,

CHxOREF, is defined by the CHxOM field setup. The CHxOREF signal has several types of output function which defines what happens to the output when the counter value matches the contents of the CHxCR register. In addition to the low, high and toggle CHxOREF output types; there are also

PWM mode 1 and PWM mode 2 outputs. In these modes, the CHxOREF signal level is changed according to the count direction and the relationship between the counter value and the CHxCR content. There are also two modes which will force the output into an inactive or active state irrespective of the CHxCR content or counter values. With regard to a more detailed description refer to the relative bit definition. The accompanying Table 63 shows a summary of the output type setup.


CHxOM Value

0x0

0x1

No change

Clear Output to 0


0x2

0x3

0x4

0x5

0x6

0x7

0xE

0xF

Set Output to 1

Toggle Output


Force Active Level

PWM Mode 1

PWM Mode 2

Asymmetric PWM mode 1

Asymmetric PWM mode 2

Counter Value

CRR

CHxCR

(New value 2)

CHxCR

(New value 3)

CHxCR

(New value 1)

CHxCR

Update

CHxCR value

TME

CHxOREF

CHxOM=0x3, CHxPRE=0


(1) (2) (3)

Time


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Cortex ® -M0+ MCU

Counter Value

CRR

CHxCR

(New value 2)

CHxCR

(New value 3)

CHxCR

(New value 1)

CHxCR

Update

CHxCR value

TME

CHxOREF

CHxOM=0x3, CHxPRE=1


(1) (2) (3)


Time

Counter Value

CRR

CHxCR

Counter Value

CHxCR

CRR

Counter Value

CRR

CHxOM = 0x6 CHxCR = 0x0000

100%

CHxOREF

CHxCIF

CHxOM = 0x7

CHxOREF

CHxOREF

CHxCIF

CHxOREF

CHxCIF

0%

Figure 163. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode

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Cortex ® -M0+ MCU

Counter Value

CRR

CHxCR

Counter Value

CHxCR

CRR

CHxOM = 0x6

CHxOREF CHxOREF

100%

CHxCIF

CHxOM = 0x7

CHxOREF

CHxCIF

Figure 164. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode

CMSEL= 0x1

0

CHxCR = 3

CHxCIF

CHxCR = 4

CHxCIF

CHxCR >= 5

CHxCIF

1

Up-counting

2 3

100%

4

CRR = 5

5 4

Down-counting

3 2 1 0 1

CHxCR = 0

0%

CHxCIF

Figure 165. PWM Mode Channel Output Reference Signal and Counter in Center-aligned Mode

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Cortex ® -M0+ MCU


The Update event is used to update the CRR, the PSCR, the CHxACR and the CHxCR values from the actual registers to the corresponding shadow registers. An update event occurs when the counter overflows or underflows, the software update control bit is triggered or an update event from the slave controller is generated.


UEVDIS and UGDIS bit definition in the CNTCFR register.



UEVG

Slave Restart mode


CHxCR, CHxACR

Shadow Registers)

UEVDIS



UEVG

Slave Restart mode

UGDIS


UEVDIS

UEV interrupt

Single Pulse Mode

Once the timer is set to operate in the single pulse mode, it is not necessary to set the timer enable bit TME in the CTR register to 1 to enable the counter. The trigger to generate a pulse can be sourced from the STI signal rising edge or by setting the TME bit to 1 using software. Setting the

TME bit to 1 or a trigger from the STI signal rising edge can generate a pulse and then keep the

TME bit at a high state until the update event occurs or the TME bit is written to 0 by software.

If the TME bit is cleared to 0 using software, the counter will be stopped and its value held. If the

TME bit is automatically cleared to 0 by a hardware update event, the counter will be reinitialized.

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Cortex ® -M0+ MCU

TME bit

STI

CHxOREF

(PWM1)

(PWM2)

CHxOREF

(PWM1)

(PWM2)

UEVIF

CHxCIF

Counter Value

CRR

CHxCR

Counter reinitialized Counter stopped and held

Time

Triggered by STI

Cleared by

Update Event

Triggered by S/W Cleared by S/W delay delay min. delay min. delay delay delay delay

Flag is set by update event and cleared by S/W delay

CHxIMAE=0

CHxIMAE=1

Flag is set by compare match and cleared by S/W

Figure 167. Single Pulse Mode

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Cortex ® -M0+ MCU

In the Single Pulse mode, the STI active edge which sets the TME bit to 1 will enable the counter.

However, there exist several clock delays to perform the comparison result between the counter value and the CHxCR value. In order to reduce the delay to a minimum value, the user can set the

CHxIMAE bit in each CHxOCFR register. After a STI rising edge trigger occurs in the single pulse mode, the CHxOREF signal will immediately be forced to the state which the CHxOREF signal will change to as the compare match event occurs without taking the comparison result into account. The CHxIMAE bit is available only when the output channel is configured to operate in the PWM mode 1 or PWM mode 2 and the trigger source is derived from the STI signal.

Counter Value

Up-Counting Mode

CRR 6

5

CHxCR 4

3

2

1

0

Time

GT_CNT

ITIx

STI

TME

Counter Start Time

CHxIMAE

CHxOREF

(PWM1)

(PWM2)

Minimum delay

Figure 168. Immediate Active Mode Minimum Delay

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Cortex ® -M0+ MCU

Asymmetric PWM Mode

Asymmetric PWM mode allows two center-aligned PWM signals to be generated with a programmable phase shift. While the PWM frequency is determined by the value of the CRR register, the duty cycle and the phase-shift are determined by the CHxCR and CHxACR register.

When the counter is counting up, the PWM uses the value in CHxCR as up-count compare value.

When the counter is into counting down stage, the PWM uses the value in CHxACR as downcount compare value. The Figure 169 is shown an example for asymmetric PWM mode in centeraligned counting mode.

Note: Asymmetric PWM mode can only be operated in center-aligned counting mode.

CNTR 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1

CRR = 8


CRR = 8

CR = 3, ACR = X

CR = 3

CHxOREF


CRR = 8

CR = 5, ACR = X

CR = 5

CHxOREF


CRR = 8

CR = 3, ACR = 5

CR = 3

ACR = 5

CHxOREF


CRR = 8

CR = 5, ACR = 3

CR = 5

ACR = 3

CHxOREF

Figure 169. Asymmetric PWM Mode versus Center-aligned Counting Mode

Phase delay = 2

Timer Interconnection

The timers can be internally connected together for timer chaining or synchronization. This can be implemented by configuring one timer to operate in the Master mode while configuring another timer to be in the Slave mode. The following figures present several examples of trigger selection for the master and slave modes.

Using one timer to enable/disable another timer start or stop counting

▆

Configure PWM0 as the master mode to send its channel 0 Output Reference signal CH0OREF as a trigger output (MMSEL = 0x4).

▆

▆

Configure PWM0 CH0OREF waveform.

Configure PWM1 to receive its input trigger source from the PWM0 trigger output (TRSEL =

0x9).

▆

▆

▆

Configure PWM1 to operate in the pause mode (SMSEL = 0x5).



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Cortex ® -M0+ MCU

Master PWM0 f

CLKIN

PWM0

CH0OREF

PWM0

CNTR

32

Slave PWM1

PWM1

CNTR

PWM1

TEVIF

33

FA

34

FB

35

Figure 170. Pausing PWM1 using the PWM0 CH0OREF Signal

FC

36

Software clearing

00

FD

01

Using one timer to trigger another timer start counting

▆

Configure PWM0 to operate in the master mode to send its Update Event UEV as the trigger output (MMSEL = 0x2).

▆

▆

▆

Configure the PWM0 period by setting the CRR register.

Configure PWM1 to get the input trigger source from the PWM0 trigger output (TRSEL = 0x9).


▆

Start PWM0 by writing ‘1’ to the TME bit.

f

CLKIN

PWM0

UEVIF

PWM0

CNTR 13 14 15 00

PWM1

CNTR

PWM1

TME bit

PWM1

TEVIF

FA FB

Software clearing

Figure 171. Triggering PWM1 with PWM0 Update Event

01

FC

02

FD

03

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Starting two timers synchronously with the master enable MTO signal trigger

▆

Configure PWM0 to operate in the master mode to send its enable signal as a trigger output

(MMSEL = 0x1).

▆

▆

▆

▆

Enable the PWM0 master timer synchronization function by setting the TSE bit in the MDCFR register to 1 to synchronize the slave timer.

Configure PWM1 to receive its input trigger source from the PWM0 trigger output (TRSEL = 0x9).


Start PWM0 by writing ‘1’ to the TME bit.

Master PWM0 f

DTS

=f

CLKIN

PWM0 (TME bit)

PWM0 CK_PSC

TSE=1

Delay

PWM0 CNTR 34

Write UEVG bit

0 1 2 3

ITI

Slave PWM1

PWM1 (TME bit)

PWM1 (TEVIF)

PWM1 CK_PSC

PWM1 CNTR 11 0

Write UEVG bit

1 2

Figure 172. Trigger PWM0 and PWM1 with the PWM0 Timer Enable Signal

3

4 5

4 5

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Cortex ® -M0+ MCU

Trigger Peripherals Start

To interconnect to the peripherals, such as ADC, Timer and so on, the PWM could output the MTO signal or the channel compare match output signal CHxOREF (x = 0 ~ 3) to be used as peripherals input trigger signal and depending on the MCU specification.

PDMA Request

The PWM supports the interface for PDMA data transfer. There are certain events which can generate the PDMA requests if the corresponding enable control bits are set to 1 to enable the

PDMA access. These events are the PWM update events, trigger events and channel compare events. When the PDMA request is generated from the PWM channel, it can be derived from the channel compare event or the PWM update event selected by the channel PDMA selection bit, CHCDS, for all channels. For more detailed PDMA configuring information, refer to the corresponding section in the PDMA chapter.

CHCDS

CH0CDE

CH0_EV

UEV_EV

CH1_EV

UEV_EV

CH2_EV

UEV_EV

CH3_EV

UEV_EV

UEV_EV

UEVDE

0

1

0

1

0

1

0

1

CH1CDE

CH2CDE

CH3CDE

CH0 PDMA Request

CH1 PDMA Request

CH2 PDMA Request

CH3 PDMA Request

UEV PDMA Request

TRIG_EV

TEVDE

Figure 173. PWM PDMA Mapping Diagram

Trigger PDMA Request

Rev. 1.00 490 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Register Map

The following table shows the PWM registers and reset values.

Table 64. PWM Register Map

Register

CNTCFR

MDCFR

TRCFR





CTR

CH0OCFR

CH1OCFR

CH2OCFR

CH3OCFR

CHCTR

CHPOLR

DICTR

EVGR

INTSR

CNTR

PSCR

CRR

CH0CR

CH1CR

CH2CR

CH3CR

CH0ACR

CH1ACR

CH2ACR

CH3ACR





0x04C Channel 3 Output Configuration Register



0x074 Timer PDMA / Interrupt Control Register





0x088 Timer Counter-Reload Register

0x090 Channel 0 Compare Register



0x09C Channel 3 Compare Register




0x0AC Channel 3 Asymmetric Compare Register

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_FFFF

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

Rev. 1.00 491 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU



This register specifies the PWM counter configuration.

Offset: 0x000


31 30 29

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

Reserved

20

Reserved

27

19

12

4

Reserved

11

Reserved

3

Type/Reset

26

18

10

2

Bits

[24]

[17:16]

[1]

Field

DIR

CMSEL

UGDIS

25 24

DIR

RW 0

17 16

CMSEL

RW 0 RW 0

9 8

1

UGDIS

0

UEVDIS

RW 0 RW 0

Descriptions

Counting Direction

0: Count-up

1: Count-down

Note: This bit is read only when the Timer is configured to be in the Center-aligned mode.

Counter Mode Selection

00: Edge-aligned mode. Normal up-counting and down-counting available for this mode. Counting direction is defined by the DIR bit.

01: Center-aligned mode 1. The counter counts up and down alternatively. The compare match interrupt flag is set during the count-down period.

10: Center-aligned mode 2. The counter counts up and down alternatively. The compare match interrupt flag is set during the count-up period.

11: Center-aligned mode 3. The counter counts up and down alternatively. The compare match interrupt flag is set during the count-up and count-down periods.


0: Any of the following events will generate an update PDMA request or interrupt




1: Only counter overflow/underflow generates an update PDMA request or interrupt

Rev. 1.00 492 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[0]

Field

UEVDIS

Descriptions

Update event Disable control







This register specifies the PWM master and slave mode selection and single pulse mode.

Offset: 0x004


Type/Reset

Type/Reset

Type/Reset

Type/Reset

31

23

15

7

30

22

14

6

29

21

Reserved

28

Reserved

20

13

Reserved

5

12

4

Reserved

27

19

11

3

26 25 24

SPMSET

RW 0

16 18 17

MMSEL

RW 0 RW 0 RW 0

10 9 8

SMSEL

RW 0 RW 0 RW 0

2 1 0

TSE

RW 0

Bits

[24]

Field

SPMSET

Descriptions

Single Pulse Mode Setting

0: Counter counts normally irrespective of whether the update event occurred or not.

1: Counter stops counting at the next update event and then the TME bit is cleared by hardware.

Rev. 1.00 493 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[18:16]

Field

MMSEL

Descriptions

Master Mode Selection

Master mode selection is used to select the MTO signal source which is used to synchronize the other slave timer.

MMSEL [2:0] Mode

000

001

010

011

Reset Mode

Enable Mode

Update Mode

—

Descriptions

The MTO signal in the Reset mode is an output derived from one of the following cases:

1. Software setting UEVG bit

2. The STI trigger input signal which will be output on the MTO signal line when the Timer is used in the slave Restart mode

The Counter Enable signal is used as the trigger output.

The update event is used as the trigger output according to one of the following cases when the

UEVDIS bit is cleared to 0:

1. Counter overflow / underflow

2. Software setting UEVG

3. Slave trigger input when used in slave restart mode

Reserved

100

101

110

111

Rev. 1.00 494 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[11:8]

[0]

Field

SMSEL

TSE

Descriptions


SMSEL [2:0]

000

001

010

011

100

101

110

111

Mode Descriptions

Disable mode The prescaler is clocked directly by the internal clock.

— Reserved

—

—

Restart Mode

Reserved

Reserved

The counter value restarts from 0 or the CRR shadow register value depending upon the counter mode on the rising edge of the STI signal. The registers will also be updated.

Pause Mode

Trigger Mode

STIED

The counter starts to count when the selected trigger input STI is high. The counter stops counting on the instant, not being reset, when the STI signal changes its state to a low level. Both the counter start and stop control are determined by the STI signal.



Timer Synchronization Enable

0: No action

1: Master timer (current timer) will generate a delay to synchronize its slave timer through the MTO signal.

Rev. 1.00 495 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU


This register specifies the trigger source selection of PWM.

Offset: 0x008


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11

Reserved

10 9 8

3 2 1

TRSEL

0

RW 0 RW 0 RW 0 RW 0

Bits

[3:0]

Field

TRSEL

Descriptions







Others: Reserved


Table 65. PWM Internal Trigger Connection

Slave Timing Module

PWM0

PWM1

ITI0

PWM1

PWM0

ITI1

GPTM

GPTM

ITI2

—

—

Rev. 1.00 496 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU


This register specifies the timer enable bit (TME), CRR buffer enable bit (CRBE) and Channel PDMA selection bit (CHCDS).

Offset: 0x010


31 30 29 26 25 24

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

Reserved

27

Reserved

19

12

4

Reserved

11

Reserved

3

18

10

2

17

9

16

CHCDS

RW 0

8

1

CRBE

0

TME

RW 0 RW 0

Bits

[16]

[1]

[0]

Field

CHCDS

CRBE

TME

Descriptions

Channel PDMA event selection

0: Channel PDMA request derived from the channel compare event.

1: Channel PDMA request derived from the Update event.


0: Counter-reload register can be updated immediately

1: Counter-reload register can not be updated until the update event occurs

Timer Enable bit

0: PWM off

1: PWM on

When the TME bit is cleared to 0, the counter is stopped and the PWM consumes no power in any operation mode except for the single pulse mode and the slave trigger mode. In these two modes the TME bit can automatically be set to 1 by hardware which permits all the PWM registers to function normally.

Rev. 1.00 497 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU



Offset: 0x040


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

14 13 12 11

Reserved

6 5 4 3


RW 0 RW 0

10

2

9

1

CH0OM[2:0]

8

CH0OM[3]

RW 0

0

RW 0 RW 0 RW 0

Bits

[5]

[4]



0: No action


The CH0OREF signal will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH0CR values.



CH0PRE Channel 0 Compare Register (CH0CR) Preload Enable

0: CH0CR preload function is disabled

The CH0CR register can be immediately assigned a new value when the

CH0PRE bit is cleared to 0 and the updated CH0CR value is used immediately.

1: CH0CR preload function is enabled

The new CH0CR value will not be transferred to its shadow register until the update event occurs.

Rev. 1.00 498 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[8][2:0]




0000: No Change






0110: PWM mode 1

- During up-counting, channel 0 has an active level when CNTR < CH0CR or otherwise has an inactive level.


CH0CR or otherwise has an active level.

0111: PWM mode 2

- During up-counting, channel 0 is has an inactive level when CNTR <



CH0CR or otherwise has an inactive level.









CH0ACR or otherwise has an inactive level.


Selection bit in Counter Configuration Register must be configured as Centeraligned Counting mode (CMSEL = 0x1/0x2/0x3)

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU



Offset: 0x044


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

14 13 12 11

Reserved

6 5 4 3


RW 0 RW 0

10

2

9

1

CH1OM[2:0]

8

CH1OM[3]

RW 0

0

RW 0 RW 0 RW 0

Bits

[5]

[4]



0: No action






0: CH1CR preload function is disabled.

The CH1CR register can be immediately assigned a new value when the CH1PRE bit is cleared to 0 and the updated CH1CR value is used immediately.



Rev. 1.00 500 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[8][2:0]




0000: No Change






0110: PWM mode 1




0111: PWM mode 2
















Rev. 1.00 501 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU



Offset: 0x048


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

14 13 12 11

Reserved

6 5 4 3


RW 0 RW 0

10

2

9

1

CH2OM[2:0]

8

CH2OM[3]

RW 0

0

RW 0 RW 0 RW 0

Bits

[5]

[4]



0: No action











Rev. 1.00 502 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[8][2:0]




0000: No Change






0110: PWM mode 1




0111: PWM mode 2
















Rev. 1.00 503 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU



Offset: 0x04C


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

14 13 12 11

Reserved

6 5 4 3


RW 0 RW 0

10

2

9

1

CH3OM[2:0]

8

CH3OM[3]

RW 0

0

RW 0 RW 0 RW 0

Bits

[5]

[4]



0: No action











Rev. 1.00 504 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[8][2:0]




0000: No Change






0110: PWM mode 1




0111: PWM mode 2




CH3CR or otherwise has an inactive level












Rev. 1.00 505 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU


This register contains the channel compare output function enable control bits.

Offset: 0x050


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

Type/Reset

15 14 13 12 11

Reserved

10 9 8

7

Reserved

6

CH3E

RW 0

5

Reserved

4

CH2E

RW 0

3

Reserved

2

CH1E

RW 0

1

Reserved

0

CH0E

RW 0

Bits

[6]

[4]

[2]

[0]

Field

CH3E

CH2E

CH1E

CH0E

Descriptions

Channel 3 Compare Enable












Rev. 1.00 506 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU


This register contains the channel compare output polarity control.

Offset: 0x054


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

Type/Reset

15 14 13 12 11

Reserved

10 9 8

7

Reserved

6

CH3P

RW 0

5

Reserved

4

CH2P

RW 0

3

Reserved

2

CH1P

RW 0

1

Reserved

0

CH0P

RW 0

Bits

[6]

[4]

[2]

[0]

Field

CH3P

CH2P

CH1P

CH0P

Descriptions

Channel 3 Compare Polarity












Rev. 1.00 507 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Timer PDMA/Interrupt Control Register – DICTR

This register contains the timer PDMA and interrupt enable control bits.

Offset: 0x074


Type/Reset

Type/Reset

Type/Reset

Type/Reset

31

23

15

7

30

22

14

6

29

Reserved

21

Reserved

13

Reserved

5

Reserved

28

20

12

4

27 26 25 24

TEVDE Reserved UEVDE

RW 0 RW 0

19 18 17 16

CH3CDE CH2CDE CH1CDE CH0CDE

RW 0 RW 0 RW 0 RW 0

11 10

TEVIE

9

Reserved

8

UEVIE

3

CH3CIE

RW 0

2 1

CH2CIE CH1CIE

RW 0

0

CH0CIE

RW 0 RW 0 RW 0 RW 0

Bits

[26]

[24]

[19]

[18]

[17]

[16]

[10]

[8]

[3]

[2]

Field

TEVDE

UEVDE

CH3CDE

CH2CDE

CH1CDE

CH0CDE

TEVIE

UEVIE

CH3CIE

CH2CIE

Descriptions

Trigger event PDMA Request Enable

0: Trigger PDMA request is disabled

1: Trigger PDMA request is enabled

Update event PDMA Request Enable

0: Update event PDMA request is disabled

1: Update event PDMA request is enabled

Channel 3 Compare PDMA Request Enable












Trigger event Interrupt Enable






Channel 3 Compare Interrupt Enable






Rev. 1.00 508 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[1]

[0]

Field

CH1CIE

CH0CIE

Descriptions









Offset: 0x078


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

Reserved

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11 10

TEVG

9

Reserved

8

UEVG

3

CH3CG

WO 0

2

CH2CG

1

CH1CG

WO 0

0

CH0CG

WO 0 WO 0 WO 0 WO 0

Bits

[10]

[8]

[3]

Field

TEVG

UEVG

CH3CG

Descriptions



0: No action




0: No action


The counter value returns to 0 or the CRR preload value, depending on the counter mode in which the current timer is being used. An update operation of any related registers will also be performed. For more detailed descriptions, refer to the corresponding section.

Channel 3 Compare Generation

A Channel 3 compare event can be generated by software setting this bit. It is cleared by hardware automatically.

0: No action

1: Compare event is generated on channel 3

Rev. 1.00 509 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[2]

[1]

[0]

Field

CH2CG

CH1CG

CH0CG

Descriptions



0: No action




0: No action




0: No action




Offset: 0x07C


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

Reserved

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11 10

TEVIF

9

Reserved

8

UEVIF

W0C 0 W0C 0

3

CH3CIF

2

CH2CIF

1

CH1CIF

0

CH0CIF

W0C 0 W0C 0 W0C 0 W0C 0

Bits

[10]

Field

TEVIF

Descriptions





Rev. 1.00 510 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[8]

[3]

[2]

[1]

[0]

Field

UEVIF

CH3CIF

CH2CIF

CH1CIF

CH0CIF

Descriptions






- The counter overflows or underflows



Channel 3 Compare Interrupt Flag


1: The content of the counter CNTR has matched the contents of the CH3CR register.

This flag is set by hardware when the counter value matches the CH3CR value except in the center-aligned mode. It is cleared by software.



1: The content of the counter CNTR has matched the contents of the CH2CR register




1: The content of the counter CNTR has matched the contents of the CH1CR register




1: The content of the counter CNTR has matched the content of the CH0CR register


Rev. 1.00 511 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU



Offset: 0x080


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CNTV

10 9 8


7 6 5 4 3 2 1 0

CNTV


Bits

[15:0]

Field

CNTV

Descriptions

Counter Value



Offset: 0x084


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PSCV

10 9 8


7 6 5 4 3 2 1 0

PSCV


Bits

[15:0]

Field

PSCV

Descriptions

Prescaler Value


CK_CNT

.

f

CK_CNT

= f

CK_PSC

PSCV[15:0]+1

, where the f

CK_PSC


Rev. 1.00 512 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Timer Counter-Reload Register – CRR

This register specifies the timer counter-reload value.

Offset: 0x088


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CRV

10 9 8


7 6 5 4 3 2 1 0

CRV


Bits

[15:0]

Field

CRV

Descriptions

Counter-Reload Value


Channel 0 Compare Register – CH0CR

This register specifies the timer channel 0 compare value.

Offset: 0x090


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH0CV

10 9 8


7 6 5 4 3 2 1 0

CH0CV


Bits

[15:0]

Field

CH0CV

Descriptions

Channel 0 Compare Value

The CH0CR value is compared with the counter value and the comparison result is used to trigger the CH0OREF output signal.

Rev. 1.00 513 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU



Offset: 0x094


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH1CV

10 9 8


7 6 5 4 3 2 1 0

CH1CV


Bits

[15:0]

Field

CH1CV

Descriptions





Offset: 0x098


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH2CV

10 9 8


7 6 5 4 3

CH2CV

2 1 0


Bits

[15:0]

Field

CH2CV

Descriptions



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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU



Offset: 0x09C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH3CV

10 9 8


7 6 5 4 3 2 1 0

CH3CV


Bits

[15:0]

Field

CH3CV

Descriptions





Offset: 0x0A0


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH0ACV

10 9 8


7 6 5 4 3

CH0ACV

2 1 0


Bits

[15:0]

Field

CH0ACV

Descriptions



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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU



Offset: 0x0A4


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH1ACV

10 9 8


7 6 5 4 3 2 1 0

CH1ACV


Bits

[15:0]

Field

CH1ACV

Descriptions





Offset: 0x0A8


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH2ACV

10 9 8


7 6 5 4 3

CH2ACV

2 1 0


Bits

[15:0]

Field

CH2ACV

Descriptions



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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU



Offset: 0x0AC


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH3ACV

10 9 8


7 6 5 4 3 2 1 0

CH3ACV


Bits

[15:0]

Field

CH3ACV

Descriptions



Rev. 1.00 517 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

24

Single-Channel Timer (SCTM)

Introduction

The Single-Channel Timer consists of one 16-bit up-counter, one 16-bit Capture/Compare Register

(CCR), one 16-bit Counter-Reload Register (CRR) and several control/status registers. It can be used for a variety of purposes including general timer, input signal pulse width measurement or output waveform generation such as PWM output. f

CLKIN

TIBED

TISED

STIED

Clock

Controller

UEVG

TIS

Trigger

Controller

MDCFR

Register

STI Slave

Controller

TEV

TEV : Trigger Event

CEV : Capture Event

MEV : Compare Match Event

UEV : Update Event

SCTM_CH

TI Input Filter


& Edge Detection

TISED

TIBED

CK_PSC PSC

PRESCALER

CK_CNT

Restart

Pause

Trigger

TM_CNT

Reload

Register

(CRR)

UEV

CH

PRESCALER

CEV

Channel Capture/Compare

Register (CHCCR)

MEV

CHOREF Output

Control

Figure 174. SCTM Block Diagram

SCTM_CHO

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Features

▆

▆

▆

▆

16-bit auto-reload up-counter

16-bit programmable prescaler that allows division of the counter clock frequency by any factor between 1 and 65536

Single channel for:



● PWM waveform output

Interrupt generation with the following events:

● Update event

●

● Input capture event

●

Trigger event

Output compare match event


Counter Mode

Up-Counting

The counter counts continuously from 0 to the counter-reload value, which is defined in the

CRR register. Once the counter reaches the counter-reload value, the Timer Module generates an overflow event and the counter restarts to count once again from 0. This action will continue repeatedly. When the update event is generated by setting the UEVG bit in the EVGR register to 1, the counter value will also be initialized to 0.

CK_PSC

CNT_EN

CK_CNT

CNTR

CRR

CRR Shadow Register

PSCR

PSCR Shadow Register

PSC_CNT

Counter Overflow

Update Event Flag

F5

F2

0

F5

Write a new value


0

0

F3 F4 F5

0

0


1

36

0

1

1

1

36

1

0

2

1

Software clearing

0

3

1

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▆


CLKIN


0x6, the internal APB clock f

CLKIN

CLKIN

used to drive the counter prescaler when the slave mode is disabled. When the slave mode selection bits SMSEL are set to 0x4, 0x5 or

is the counter prescaler driving clock source. If the slave mode controller is enabled by setting SMSEL field in the MDCFR register to 0x7, the prescaler is clocked by other clock sources selected by the TRSEL field in the TRCFR register and described as follows.

▆

STIED




PSCR CRR

Update Event f

CLKIN

(Internal APB clock)

STIED

(Trigger events)

CK_PSC

CLK

PSC Prescaler

Reset

CK_CNT

CLK

CNTR

Reset

TM_CNT

TRSEL

SMSEL

Start/Stop

Figure 176. SCTM Clock Source Selection

Overflow

UEVG bit


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Cortex ® -M0+ MCU


The trigger controller is used to select the trigger source and setup the trigger level or edge trigger condition. For the internal trigger input, it can be selected by the Trigger Selection bits TRSEL in the TRCFR register. For all the trigger sources except the UEVG bit software trigger, the internal edge detection circuitry will generate a clock pulse at each trigger signal rising edge to stimulate some SCTM functions which are triggered by a trigger signal rising edge.

Edge Trigger Source = Channel input


0

TISED

TIBED

Reserved

Reserved

Reserved

Reserved

000

001

010

011 others

Reserved

Reserved

Reserved

TRSEL[2:0]

STIED_S1

000

001

010

011 others STIED_S0

0

1

TRSEL[3]

STIED

Level Trigger Source = Channel input + Software UEVG bit

S/W Set

UEVG Bit

TIS


TRSEL[2:0]

Reserved

Reserved

Reserved

0

Reserved

Reserved

Reserved

Reserved

000

001

010

011 others

STI_S1

000

001

010

011 others

STI_S0

0

1

TRSEL[3]


STI

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Cortex ® -M0+ MCU


The SCTM can be synchronized with an external trigger in several modes including the Restart mode, the Pause mode and the Trigger mode which is selected by the SMSEL field in the MDCFR register. The trigger input of these modes comes from the STI signal which is selected by the

TRSEL field in the TRCFR register. The operation modes in the Slave Controller are described in the accompanying sections.

Trigger Controller

STI

Slave

Controller

SMSEL

Trigger Event


Restart/Pause/Trigger Mode


Restart Mode




STI source signal

(polarity=0)

STI source signal

(polarity=1)

STI

CK_CNT

UEVG bit

(reset counter)

CNTR

(Up-counting)

TEVIF

27 28 29

Figure 179. SCTM in Restart Mode

Sync.

30 31

Trigger Event

0 1 2

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Pause Mode

In the Pause Mode, the selected STI input signal level is used to control the counter start/stop operation. The counter starts to count when the selected STI signal is at a high level and stops counting when the STI signal is changed to a low level, here the counter will maintain its present value and will not be reset. Since the Pause function depends upon the STI level to control the counter stop/start operation, the selected STI trigger signal can not be derived from the TIBED signal.

STI source signal

(polarity=0)

STI source signal

(polarity=1)

STI

CK_ CNT

CNT_ EN

CNTR

TEVIF

Sync

27 28 29

Sync

30 31

Software clearing

Figure 180. SCTM in Pause Mode

Trigger Mode


STI source signal

(polarity=0)

STI source signal

(polarity=1)

STI

CK_CNT

CNT_EN

CNTR

(Up-counting)

TEVIF

27

Sync

28 29 30 31 32

Software clearing

Figure 181. SCTM in Trigger Mode

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Cortex ® -M0+ MCU


The SCTM channel can be used as the capture input or compare match output. The capture input or compare match output channel is composed of a preload register and a shadow register. Data access of the APB bus is always implemented by reading/writing the preload register.

When used in the input capture mode, the counter value is captured into the CHCCR shadow register first and then transferred into the CHCCR preload register when the capture event occurs.

When used in the compare match output mode, the contents of the CHCCR preload register is copied into the associated shadow register; the counter value is then compared with the register value.

APB Bus Interface

CHPSC

Read CHCCR

Capture

Controller

CHCCS

CHCCG

CHE

Capture Transfer

CHCCR

(Preload Register)

Compare Transfer

Compare

Controller

CHCCR

(Shadow Register)

Capture

CHCCS

CHPRE

CHCCR

TM_CNT

Figure 182. Capture/Compare Block Diagram

Write CHCCR

Update Event

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Cortex ® -M0+ MCU

Capture Counter Value Transferred to CHCCR

When the channel is used as a capture input, the counter value is captured into the Channel

Capture/Compare Register (CHCCR) when an effective input signal transition occurs. Once the capture event occurs, the CHCCIF flag in the INTSR register is set accordingly. If the CHCCIF bit is already set, i.e., the flag has not yet been cleared by software, and another capture event on this channel occurs, the corresponding channel Over-Capture flag, named CHOCF, will be set.

f

CLKIN

SCTM_CH

CNTR 25

CHCCR 0

26

CHCCIF

CHOCF

Figure 183. Input Capture Mode

27 28

26

29 30 31 32 33 34 35

32

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Cortex ® -M0+ MCU

Input Stage

The input stage consists of a digital filter, a channel polarity selection, edge detection and a channel prescaler. The channel input signal (TI) is sampled by a digital filter to generate a filtered input signal TIFP. Then the channel polarity and the edge detection block can generate a TISED signal for the input capture function. The effective input event number can be set by the channel capture input source prescaler setting field (CHPSC).

f

CLKIN

Edge

Detection

Edge

Detection

CHCCS

TIBED

SCTM_CH

TI f sampling

Filter

TIFP TIFN

TIF

Figure 184. Channel Input Stages f

CLKIN

TIS

CHP

Edge

Detection

TISED

CH

PRESCALER

CHPSC

CHPSC

CHCAP Event

Digital Filter

The digital filter is embedded in the channel input stage. The digital filter in the SCTM is an N-event counter where N refers to how many valid transitions are necessary to output a filtered signal. The

N value can be 0, 2, 4, 5, 6 or 8 according to the user selection for this digital filter.

No Filtered

Digital Filter (N=2)

TI

D Q D Q D Q f

SYSTEM

CK CK f sampling

CK

Figure 185. TI Digital Filter Diagram with N = 2

J

CK

Q

K

Filtered

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Cortex ® -M0+ MCU

Output Stage

The SCTM output has function for compare match or PWM output. The channel output SCTM_

CHO is controlled by the CHOM, CHP and CHE bits in the corresponding CHOCFR, CHPOLR and CHCTR registers.

CNTR

CHCCR f

CLKIN

Output Mode

Controller

CHOREF

CHP

CHOM


Output Enable

Controller

CHE

SCTM_CHO

CHOREF

CHCMP Event


When the SCTM is used in the compare match output mode, the CHOREF signal (Channel Output

Reference signal) is defined by the CHOM bit setup. The CHOREF signal has several types of output function which defines what happens to the output when the counter value matches the contents of the CHCCR register. In addition to the low, high and toggle CHOREF output types; there are also PWM mode 1 and PWM mode 2 outputs. In these modes, the CHOREF signal level is changed according to the relationship between the counter value and the CHCCR content. There are also two modes which will force the output into an inactive or active state irrespective of the

CHCCR content or counter values. With regard to a more detailed description refer to the relative bit definition. The Table 66 shows a summary of the output type setup.


CHOM value

0x0

0x1

No change

Clear Output to 0


0x2

0x3

0x4

0x5

0x6

0x7

Set Output to 1

Toggle Output


Force Active Level

PWM Mode 1

PWM Mode 2

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Cortex ® -M0+ MCU

Counter Value

CRR

CHCCR

(New value 2)

CHCCR

(New value 3)

CHCCR

(New value 1)

CHCCR

Update

CHCCR value

TME

CHOREF

CHOM=0x3, CHPRE=0


(1) (2) (3)

Time

Figure 187. Toggle Mode Channel Output Reference Signal (CHPRE = 0)

Counter Value

CRR

CHCCR

(New value 2)

CHCCR

(New value 3)

CHCCR

(New value 1)

CHCCR

Update

CHCCR value

TME

CHOREF

CHOM=0x3, CHPRE=1


(1) (2) (3)

Figure 188. Toggle Mode Channel Output Reference Signal (CHPRE = 1)

Time

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Cortex ® -M0+ MCU

Counter Value

CRR

CHCCR

Counter Value

CHCCR

CRR

CHOM = 0x6

100%

CHOREF

CHCCIF

CHOREF

CHCCIF

CHOM = 0x7

CHOREF

Figure 189. PWM Mode Channel Output Reference Signal

Counter Value

CRR

CHCCR = 0x0000

CHOREF

CHCCIF

0%


The Update event is used to update the CRR, the PSCR and the CHCCR values from the actual registers to the corresponding shadow registers. An update event will occur when the counter overflows, the software update control bit is triggered or an update event from the slave controller is generated.


UEVDIS and UGDIS bit definition in the CNTCFR register.

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Counter Overflow

UEVG

Slave Restart mode

UEVDIS


Counter Overflow

UEVG

Slave Restart mode

UEVDIS

UGDIS


Register Map

The following table shows the SCTM registers and reset values.

Table 67. SCTM Register Map

Register

CNTCFR



MDCFR

TRCFR

CTR

CHICFR

CHOCFR

CHCTR

CHPOLR

DICTR

EVGR

INTSR

CNTR

PSCR

CRR

CHCCR




0x020 Channel Input Configuration Register

0x040 Channel Output Configuration Register



0x074 Timer Interrupt Control Register





0x088 Timer Counter Reload Register

0x090 Channel Capture/Compare Register


CHCCR Shadow Registers)

UEV interrupt

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_FFFF

0x0000_0000

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This register specifies the SCTM counter configuration.

Offset: 0x000


31 30 29

Type/Reset

Type/Reset

Type/Reset

Type/Reset

Bits

[9:8]

[1]

[0]

23

15

7

Field

CKDIV

UGDIS

UEVDIS

22

14

6

21

13

5

28

20

12

Reserved

4

Reserved

27

Reserved

19

Reserved

11

3

26

18

10

2

25

17

24

16

9 8

CKDIV

RW 0 RW 0

1 0

UGDIS UEVDIS

RW 0 RW 0

Descriptions

Clock Division

These two bits define the frequency ratio between the timer clock (f dead-time clock (f clock.

00: f

01: f

10: f

DTS

= f

DTS

= f

DTS

= f

CLKIN

CLKIN

/ 2

CLKIN

/ 4

11: Reserved

CLKIN

) and the

DTS

). The dead-time clock is also used for digital filter sampling


0: Any of the following events will generate an update interrupt

- Counter overflow



1: Only counter overflow generates an update interrupt

Update event Disable control


- Counter overflow




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This register specifies the SCTM slave mode selection.

Offset: 0x004


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

Reserved

5

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11

3

Reserved

10 9

SMSEL

8

RW 0 RW 0 RW 0

2 1 0

Type/Reset

Bits

[10:8]

Field

SMSEL

Descriptions


SMSEL [2:0]

000

Mode Descriptions

Disable mode The prescaler is clocked directly by the internal clock.

100

101

110

111

Others

Pause Mode

Trigger Mode

STIED

The counter starts to count when the selected trigger input STI is high. The counter stops counting on the instant, not being reset, when the STI signal changes its state to a low level. Both the counter start and stop control are determined by the STI signal.



Reserved

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Cortex ® -M0+ MCU


This register specifies the trigger source selection of SCTM.

Offset: 0x008


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11

Reserved

10 9 8

3 2 1

TRSEL

0

RW 0 RW 0 RW 0 RW 0

Bits

[3:0]

Field

TRSEL

Descriptions




0001: Filtered input of the channel (TIS)

1000: Channel both edge detector (TIBED)

Others: Reserved


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Cortex ® -M0+ MCU


This register specifies the timer enable bit (TME), CRR buffer enable bit (CRBE).

Offset: 0x010


31 30 29

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

Type/Reset

26

18

10

2

Bits

[1]

[0]

Field

CRBE

TME

25

17

9

24

16

8

1

CRBE

0

TME

RW 0 RW 0

Descriptions


0: Counter reload register can be updated immediately

1: Counter reload register cannot be updated until the update event occurs

Timer Enable bit

0: SCTM off

1: SCTM on – SCTM functions normally

When the TME bit is cleared to 0, the counter is stopped and the SCTM consumes no power in any operation mode except for the slave trigger mode. In this mode the TME bit can automatically be set to 1 by hardware which permits all the SCTM registers to function normally.

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Cortex ® -M0+ MCU

Channel Input Configuration Register – CHICFR

This register specifies the channel input mode configuration.

Offset: 0x020


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

Reserved

13

5

Reserved

20

12

4

27

Reserved

26 25 24

19 18

CHPSC

17 16

CHCCS

RW 0 RW 0 RW 0 RW 0

11

Reserved

10 9 8

3 2 1

TIF

0

RW 0 RW 0 RW 0 RW 0

Bits

[19:18]

[17:16]

Field

CHPSC

CHCCS

Descriptions

Channel Capture Input Source Prescaler Setting

These bits define the effective events of the channel capture input. Note that the prescaler is reset once the Channel Capture/Compare Enable bit, CHE, in the


00: No prescaler, channel capture input signal is chosen for each active event.

01: Channel Capture input signal is chosen for every 2 events.



Channel Capture/Compare Selection.

00: Channel is configured as an output.

01: Channel is configured as an input derived from the TI signal.

10: Reserved.

11: Channel is configured as an input which comes from the TIBED signal.

Note: The CHCCS field can be accessed only when the CHE bit is cleared to 0.

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Cortex ® -M0+ MCU

Bits

[3:0]

Field

TIF

Descriptions

Channel Input Source TI Filter Setting

These bits define the frequency divided ratio used to sample the TI signal. The

Digital filter in the SCTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.


SYSTEM

0001: f

0010: f

0011: f

0100: f

0101: f

0110: f sampling sampling

= f

= f sampling

= f sampling

= f

CLKIN

, N = 2

CLKIN

, N = 4

CLKIN

DTS

, N = 8

/ 2, N = 6 sampling

= f

DTS

/ 2, N = 8 sampling

= f

DTS

/ 4, N = 6

.

0111: f

1000: f

1001: f

1010: f

1011: f

1100: f

1101: f

1110: f


= f

= f

= f

= f

DTS

DTS

DTS

DTS

/ 4, N = 8

/ 8, N = 6

/ 8, N = 8

/ 16, N = 5 sampling

= f

DTS


= f

DTS


= f

DTS


= f

DTS


= f

DTS

/ 32, N = 8

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Cortex ® -M0+ MCU

Channel Output Configuration Register – CHOCFR

This register specifies the channel output mode configuration.

Offset: 0x040


31 30 29

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

Reserved

21

13

5

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

12 11

Reserved

10 9 8

4 3

CHPRE Reserved

RW 0

2 1

CHOM

0

RW 0 RW 0 RW 0

Bits

[4]

[2:0]

Field

CHPRE

CHOM

Descriptions

Channel Capture/Compare Register (CHCCR) Preload Enable

0: CHCCR preload function is disabled

The CHCCR register can be immediately assigned a new value when the

CHPRE bit is cleared to 0 and the updated CHCCR value is used immediately.

1: CHCCR preload function is enabled

The new CHCCR value will not be transferred to its shadow register until the update event occurs.

Channel Output Mode Setting

These bits define the functional types of the output reference signal CHOREF.

000: No Change




100: Force inactive – CHOREF is forced to 0

101: Force active – CHOREF is forced to 1

110: PWM mode 1

- During up-counting, channel has an active level when CNTR < CHCCR or otherwise has an inactive level.

111: PWM mode 2

- During up-counting, channel is has an inactive level when CNTR <

CHCCR or otherwise has an active level.

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Cortex ® -M0+ MCU


This register contains the channel capture input or compare output function enable control bit.

Offset: 0x050


31 30 29 26 25

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

18

10

2

17

9

1

Type/Reset

Bits

[0]

Field

CHE

24

16

8

0

CHE

RW 0

Descriptions

Channel Capture/Compare Enable

- Channel is configured as an input (CHCCS = 0x1/0x3)



- Channel is configured as an output (CHCCS = 0x0)

0: Off – Channel output signal CHO is not active

1: On – Channel output signal CHO generated on the corresponding output pin

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Cortex ® -M0+ MCU


This register contains the channel capture input or compare output polarity control.

Offset: 0x054


31 30 29 26

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

18

10

2

Type/Reset

Bits

[0]

Field

CHP

Descriptions

Channel Capture/Compare Polarity

- When Channel is configured as an input (CHCCS = 0x1/0x3)

0: Capture event occurs on a Channel rising edge

1: Capture event occurs on a Channel falling edge

- When Channel is configured as an output (CHCCS = 0x0)

0: Channel Output is active high

1: Channel Output is active low

25

17

9

1

24

16

8

0

CHP

RW 0

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HT32F5828

Cortex ® -M0+ MCU

Timer Interrupt Control Register – DICTR

This register contains the timer interrupt enable control bits.

Offset: 0x074


31 30

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

29

21

28

20

13

Reserved

5

12

4

Reserved

27

Reserved

19

Reserved

11

3

26

18

25

17

24

16

10

TEVIE

RW 0

2

9

Reserved

1

8

UEVIE

RW 0

0

CHCCIE

RW 0

Bits

[10]

[8]

[0]

Field

TEVIE

UEVIE

CHCCIE

Descriptions

Trigger event Interrupt Enable






Channel Capture/Compare Interrupt Enable

0: Channel interrupt is disabled

1: Channel interrupt is enabled

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Cortex ® -M0+ MCU



Offset: 0x078


31 30

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

29

21

28

20

13

Reserved

5

12

4

Reserved

27

Reserved

19

Reserved

11

3

26

18

25

17

24

16

10

TEVG

WO 0

2

9

Reserved

1

8

UEVG

WO 0

0

CHCCG

WO 0

Bits

[10]

[8]

[0]

Field

TEVG

UEVG

CHCCG

Descriptions



0: No action




0: No action


If this bit is set, the counter value returns to 0. An update operation of any related registers will also be performed. For more detail descriptions, refer to the corresponding section.

Channel Capture/Compare Generation

A Channel capture/compare event can be generated by setting this bit. It is cleared by hardware automatically.

0: No action

1: Capture/compare event is generated on channel.

If the channel is configured as an input, the counter value is captured into the

CHCCR register and then the CHCCIF bit is set. If the channel is configured as an output, the CHCCIF bit is set.

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Offset: 0x07C


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

14

6

Reserved

13

Reserved

5

12

4

CHOCF

W0C 0

27

Reserved

19

Reserved

11

3

26

18

25

17

24

16

10

TEVIF

W0C 0

2

Reserved

9

Reserved

1

8

UEVIF

W0C 0

0

CHCCIF

W0C 0

Bits

[10]

[8]

[4]

[0]

Field

TEVIF

UEVIF

CHOCF

CHCCIF

Descriptions










- The counter overflows



Channel Over-Capture Flag



1: Capture event occurs again when the CHCCIF bit is already set and it is not yet cleared by software.

Channel Capture/Compare Interrupt Flag

- Channel is configured as an output:


1: The contents of the counter CNTR have matched the content of the CHCCR register

This flag is set by hardware when the counter value matches the CHCCR value.

It is cleared by software.

- Channel is configured as an input:



This bit is set by hardware on a capture event. It is cleared by software or by reading the CHCCR register.

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HT32F5828

Cortex ® -M0+ MCU



Offset: 0x080


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CNTV

10 9 8


7 6 5 4 3 2 1 0

CNTV


Bits

[15:0]

Field

CNTV

Descriptions

Counter Value

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HT32F5828

Cortex ® -M0+ MCU



Offset: 0x084


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PSCV

10 9 8


7 6 5 4 3 2 1 0

PSCV


Bits

[15:0]

Field

PSCV

Descriptions

Prescaler Value


CK_CNT

.

f

CK_CNT

= f

CK_PSC

PSCV[15:0] + 1

, where the f

CK_PSC


Rev. 1.00 544 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Timer Counter Reload Register – CRR

This register specifies the timer counter reload value.

Offset: 0x088


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CRV

10 9 8


7 6 5 4 3 2 1 0

CRV


Bits

[15:0]

Field

CRV

Descriptions

Counter Reload Value


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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Channel Capture/Compare Register – CHCCR

This register specifies the timer channel capture/compare value.

Offset: 0x090


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CHCCV

10 9 8


7 6 5 4 3 2 1 0

CHCCV


Bits

[15:0]

Field

CHCCV

Descriptions

Channel Capture/Compare Value

- When Channel is configured as an output

The CHCCR value is compared with the counter value and the comparison result is used to trigger the CHOREF output signal.

- When Channel is configured as an input

The CHCCR register stores the counter value captured by the last channel capture event.

Rev. 1.00 546 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

25

Basic Function Timer (BFTM)

Introduction

The Basic Function Timer is a 32-bit up-counting counter designed to measure time intervals, generate one shot pulses or generate repetitive interrupts. The BFTM can operate in two modes which are repetitive and one shot modes. The repetitive mode restarts the counter at each compare match event which is generated by the internal comparator. The BFTM also supports a one shot mode which will force the counter to stop counting when a compare match event occurs.

OSM Counter

Controller

To A/D Converter

BFTM APB clock

EN CLR

32-bit Up-Counter Comparator

MIF

MIEN

To NVIC

BFTMCNTR

Figure 191. BFTM Block Diagram

BFTMCMPR

Features

▆

32-bit up-counting counter

▆

▆

▆

▆

▆

▆

▆

Compare Match function

Includes debug mode

Clock source: BFTM APB clock

Counter value can be Read/Written on the fly

One shot mode: counter stops counting when compare match occurs

Repetitive mode: counter restarts when compare match occurs

Compare Match interrupt enable/disable control

Rev. 1.00 547 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU


The BFTM is a 32-bit up-counting counter which is driven by the BFTM APB clock, PCLK. The counter value can be changed or read at any time even when the timer is counting. The BFTM supports two operating modes known as the repetitive mode and one shot mode allowing the measurement of time intervals or the generation of periodic time durations.

Repetitive Mode

The BFTM counts up from zero to a specific compare value which is pre-defined by the

BFTMCMPR register. When the BFTM operates in the repetitive mode and the counter reaches a value equal to the specific compare value in the BFTMCMPR register, the timer will generate a compare match event signal, MIF. When this occurs, the counter will be reset to 0 and resume its counting operation. When the MIF signal is generated, a BFTM compare match interrupt will also be generated periodically if the compare match interrupt is enabled by setting the corresponding interrupt control bit, MIEN, to 1. The counter value will remain unchanged and the counter will stop counting if it is disabled by clearing the CEN bit to 0.

0xFFFF_FFFF

CMP

Keep counter value when CEN is reset

Time

CNT

MIF

CEN

: Updated by software

Figure 192. BFTM – Repetitive Mode

: Cleared by software

Rev. 1.00 548 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

One Shot Mode

By setting the OSM bit in BFTMCR register to 1, the BFTM will operate in the one shot mode. The

BFTM starts to count when the CEN bit is set to 1 by the application program. The counter value will remain unchanged if the CEN bit is cleared to 0 by the application program. However, the counter value will be reset to 0 and stop counting when the CEN bit is cleared automatically to 0 by the internal hardware when a counter compare match event occurs.

CMP

CNT value unchanged when CEN is reset

By S/W

: Updated by software

: Cleared by software

: Cleared by hardware

Time

CNT

MIF

CEN

Figure 193. BFTM – One Shot Mode

0xFFFF_FFFF

CMP

CNT

MIF

Time

CEN

: Updated by software : Cleared by software

Figure 194. BFTM – One Shot Mode Counter Updating

: Cleared by hardware

Trigger ADC Start

When a BFTM compare match event occurs, a compare match interrupt flag, MIF, will be generated which can be used as an A/D Converter input trigger source.

Rev. 1.00 549 of 637 December 28, 2020

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HT32F5828

Cortex ® -M0+ MCU

Register Map

The following table shows the BFTM registers and reset values.

Table 68. BFTM Register Map

Register

BFTMCR

BFTMSR

BFTMCNTR

BFTMCMPR

Offset

0x000

0x004

0x008

0x00C

Description

BFTM Control Register

BFTM Status Register

BFTM Counter Value Register

BFTM Compare Value Register


BFTM Control Register – BFTMCR

This register specifies the overall BFTM control bits.

Offset: 0x000


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

Reserved

20

12

4

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0xFFFF_FFFF

27

Reserved

19

Reserved

26

18

25

17

24

16

11

Reserved

3

10 9 8

2

CEN

1

OSM

0

MIEN

RW 0 RW 0 RW 0

Bits

[2]

[1]

[0]

Field

CEN

OSM

MIEN

Descriptions

BFTM Counter Enable Control

0: BFTM is disabled

1: BFTM is enabled

When this bit is set to 1, the BFTM counter will start to count. The counter will stop counting and the counter value will remain unchanged when the CEN bit is cleared to 0 by the application program regardless of whether it is in the repetitive or one shot mode. However, in the one shot mode, the counter will stop counting and be reset to 0 when the CEN bit is cleared to 0 by the timer hardware circuitry which results from a compare match event.

BFTM One Shot Mode Selection

0: Counter operates in repetitive mode

1: Counter operates in one shot mode

BFTM Compare Match Interrupt Enable Control

0: Compare Match Interrupt is disabled

1: Compare Match Interrupt is enabled

Rev. 1.00 550 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

BFTM Status Register – BFTMSR

This register specifies the BFTM status.

Offset: 0x004


31 30 29

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

Type/Reset

Bits

[0]

Field

MIF

26

18

10

25

17

9

24

16

8

2 1 0

MIF

W0C 0

Descriptions

BFTM Compare Match Interrupt Flag

0: No compare match event occurs

1: Compare match event occurs

When the counter value, CNT, is equal to the compare register value, CMP, a compare match event will occur and the corresponding interrupt flag, MIF will be set.

The MIF bit is cleared to 0 by writing a data “0”.

Rev. 1.00 551 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

BFTM Counter Value Register – BFTMCNTR

This register specifies the BFTM counter value.

Offset: 0x008


31 30 29 28 27

CNT

26 25 24


23 22 21 20 19

CNT

18 17 16


15 14 13 12 11

CNT

10 9 8


7 6 5 4 3 2 1 0

CNT


Bits

[31:0]

Field

CNT

Descriptions

BFTM Counter Value

A 32-bit BFTM counter value is stored in this field which can be read or written on the fly.

BFTM Compare Value Register – BFTMCMPR

The register specifies the BFTM compare value.

Offset: 0x00C

Reset value: 0xFFFF_FFFF

31 30 29 28 27

CMP

26 25 24


23 22 21 20 19

CMP

18 17 16


15 14 13 12 11

CMP

10 9 8


7 6 5 4 3

CMP

2 1 0


Bits

[31:0]

Field

CMP

Descriptions

BFTM Compare Value

This register specifies a 32-bit BFTM compare value which is used for comparison with the BFTM counter value.

Rev. 1.00 552 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

26

Watchdog Timer (WDT)

Introduction

The Watchdog Timer is a hardware timing circuitry that can be used to detect a system lock-up due to software trapped in a deadlock. The Watchdog Timer can be operated in a reset mode. The

Watchdog Timer will generate a reset when the counter counts down to a zero value. Therefore, the software should reload the counter value before a Watchdog Timer underflow occurs. In addition, a reset is also generated if the software reloads the counter before it reaches a delta value. That means that the Watchdog Timer prevents a software deadlock that continuously triggers the Watchdog, the reload must occur when the Watchdog Timer value has a value within a limited window of 0 and WDTD. The Watchdog Timer counter can be stopped when the processor is in the debug or the three sleep modes. The register write protection function can be enabled to prevent an unexpected change in the Watchdog Timer configuration.

WDTV

WDTRS

RSKEY[15:0]

LSI RC

32 kHz

LSE OSC

32.768 kHz

0

1

WDTEN

WDTSRC

CK_WDT

Clear

Prescaler

1, /2, /4, /8,

… /128

WPSC[2:0]

Reload

12-bit

Down-Counter

WDTD

Underflow

WDTUF

WDTERR

WDT Error

WDT_RSTn

WDTRSTEN

Read WDTSR Register

Figure 195. Watchdog Timer Block Diagram

Rev. 1.00 553 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Features

▆

▆

▆

▆

▆

▆

▆

▆

Clock source from either the internal 32 kHz RC oscillator (LSI) or the external 32,768 Hz oscillator (LSE)

Can be independently setup to keep running or to stop when entering the Sleep or Deep-Sleep1 mode

12-bit down-counter with 3-bit prescaler structure

Provides reset to the system

Limited reload window setup function for custom Watchdog Timer reload times

Watchdog Timer may be stopped when the processor is in the debug mode

Reload lock key to prevent unexpected operation

Configuration register write protection function for counter value, reset enable, delta value, and prescaler value


The Watchdog Timer is formed from a 12-bit count-down counter and a fixed 3-bit prescaler. The largest time-out period is 16 seconds, using the LSE or LSI clock and a 1/128 maximum prescaler value.

The Watchdog Timer configuration setup includes programmable counter reload value, reset enable, window value and prescaler value. These configurations are set using the WDTMR0 and WDTMR1 registers which must be properly programmed before the Watchdog Timer starts counting. In order to prevent unexpected write operations to those configurations, a register write protection function can be enabled by writing any value, other than 0x35CA to PROTECT[15:0], in the WDTPR register. A value of 0x35CA can be written to PROTECT[15:0] to disable the register write protection function before accessing any configuration register. A read operation on

PROTECT[0] can obtain the enable/disable status of the register write protection function.

During normal operation, the Watchdog Timer counter should be reloaded before it underflows to prevent the generation of a Watchdog reset. The 12-bit count-down counter can be reloaded with the required Watchdog Timer Counter Value (WDTV) by first setting the WDTRS bit to1 with the correct key, which is 0x5FA0 in the WDTCR register.

If a software deadlock occurs during a Watchdog Timer reload routine, the reload operation will still go ahead and therefore the software deadlock cannot be detected. To prevent this situation from occurring, the reload operation must be executed in such a way that the value of the Watchdog

Timer counter is limited to within a delta value (WDTD). If the Watchdog Timer counter value is greater than the delta value and a reload operation is executed, a Watchdog Timer error will occur.

The Watchdog Timer error will cause a Watchdog reset if the related functional control is enabled.

Additionally, the above features can be disabled by programming a WDTD value greater than or equal to the WDTV value.

The WDTERR and WDTUF flags in the WDTSR register will be set respectively when the

Watchdog Timer error occurs or when a Watchdog Timer underflows. A system reset or writing “1” operation on the WDTSR register will clear the WDTERR and WDTUF flags.

The Watchdog Timer uses two clocks: PCLK and CK_WDT. The PCLK clock is used for APB access to the watchdog registers. The CK_WDT clock is used for the Watchdog Timer functionality and counting. There is some synchronization logic between these two clock domains.

Rev. 1.00 554 of 637 December 28, 2020

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Cortex ® -M0+ MCU

When the system enters the Sleep mode or Deep-Sleep1 mode, the Watchdog Timer counter will either continue to count or stop depending on the WDTSHLT field setup in the WDTMR0 register.

However, the Watchdog Timer will always stop when the system is in the Deep-Sleep2 mode.

When the Watchdog stops counting, the count value is retained so that it continues counting after the system is woken up from these three sleep modes. A Watchdog reset will occur any time when the Watchdog Timer is running and when it has an operating clock source. When the system enters the debug mode, the Watchdog Timer counter will either continue to count or stop depending on the DBWDT bit of the MCUDBGCR register in the Clock Control Unit.

The Watchdog timer should be used in the following manners:

▆

▆

▆

▆

▆

Set the Watchdog Timer reload value (WDTV) and reset in the WDTMR0 register.

Set the Watchdog Timer delta value (WDTD) and prescaler in the WDTMR1 register.

Start the Watchdog Timer by writing to the WDTCR register with WDTRS = 1 and RSKEY =

0x5FA0.

Write to the WDTPR register to lock all the Watchdog Timer registers except for WDTCR and

WDTPR.

The Watchdog Timer counter should be reloaded again within the delta value (WDTD).

Counter value

0xFFF

Reset occurred

(If WDTRSTEN = 1)

Reset not occurred

(If WDTRSTEN = 0)

WDTV

Reload is not allowed

WDTD

. . .

Reload is allowed

0

Start counter

Reload counter when counter ≤ WDTD

Normal behavior

Figure 196. Watchdog Timer Behavior

Reload counter when counter > WDTD

Watchdog Timer error

Watchdog Timer underflow

Time

Rev. 1.00 555 of 637 December 28, 2020

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HT32F5828

Cortex ® -M0+ MCU

Register Map

The following table shows the Watchdog Timer registers and reset values.

Table 69. Watchdog Timer Register Map

Register Offset

WDTCR 0x000

WDTMR0

WDTMR1

0x004

0x008

WDTSR

WDTPR

WDTCSR

0x00C

0x010

0x018

Description

Watchdog Timer Control Register

Watchdog Timer Mode Register 0

Watchdog Timer Mode Register 1

Watchdog Timer Status Register

Watchdog Timer Protection Register

Watchdog Timer Clock Selection Register

Reset Value

0x0000_0000

0x0000_0FFF

0x0000_7FFF

0x0000_0000

0x0000_0000

0x0000_0000


Watchdog Timer Control Register – WDTCR

This register is used to reload the Watchdog timer.

Offset: 0x000


31

23

30

22

29

21

28

20

27

RSKEY

26 25 24


19

RSKEY

18 17 16


15 14 13 12 11

Reserved

10 9 8

Type/Reset

Type/Reset

7 6 5 4

Reserved

3 2 1 0

WDTRS

WO 0

Bits

[31:16]

[0]

Field

RSKEY

WDTRS

Descriptions

Watchdog Timer Reload Lock Key

The RSKEY [15:0] bits should be written with a 0x5FA0 value to enable the WDT reload operation function. Writing any other value except 0x5FA0 in this field will abort the write operation.

Watchdog Timer Reload

0: No effect

1: Reload Watchdog Timer

This bit is used to reload the Watchdog timer counter as a WDTV value which is stored in the WDTMR0 register. It is set to 1 by software and cleared to 0 by hardware automatically.

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Watchdog Timer Mode Register 0 – WDTMR0

This register specifies the Watchdog timer counter reload value and reset enable control.

Offset: 0x004

Reset value: 0x0000_0FFF

31 30 29 28 27

Reserved

26 25 24

Type/Reset

Type/Reset

23 22 21 20 19

Reserved

18 17 16

WDTEN

RW 0

15 14 13 12

WDTSHLT WDTRSTEN Reserved


7 6 5 4

11 10 9

WDTV

8

RW 1 RW 1 RW 1 RW 1

3 2 1 0

WDTV


Bits

[16]

[15:14]

[13]

[11:0]

Field

WDTEN

Descriptions

Watchdog Timer Running Enable

0: Watchdog Timer is disabled

1: Watchdog Timer is enabled to run

When the Watchdog Timer is disabled, the counter will be reset to its hardware default condition. When the WDTEN bit is set, the Watchdog Timer will be reloaded with the WDTV value and count down.

WDTSHLT Watchdog Timer Sleep Halt

00: The Watchdog runs when the system is in the Sleep mode or Deep-Sleep1 mode

01: The Watchdog runs when the system is in the Sleep mode and halts in Deep-

Sleep1 mode

10 or 11: The Watchdog halts when the system is in the Sleep mode and Deep-

Sleep1 mode

Note that the Watchdog timer always halts when the system is in the Deep-

Sleep2 mode. The Watchdog stops counting when the WDTSHLT field is properly configured in the Sleep mode or Deep-Sleep1 mode. When the Watchdog stops counting, the count value is retained so that it continues counting after the system wakes up from these three sleep modes. If a Watchdog reset occurs in the Sleep or

Deep-Sleep1 mode, it will wake up the device.

WDTRSTEN Watchdog Timer Reset Enable

0: A Watchdog Timer underflow or error has no effect on the system reset

1: A Watchdog Timer underflow or error triggers a Watchdog Timer system reset

WDTV Watchdog Timer Counter Value

WDTV defines the value loaded into the 12-bit Watchdog down-counter.

Rev. 1.00 557 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Watchdog Timer Mode Register 1 – WDTMR1

This register specifies the Watchdog delta value and the prescaler selection.

Offset: 0x008

Reset value: 0x0000_7FFF

31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

15

Reserved

7

14

6

13

WPSC

5

12

4

11

3

10

2

9

WDTD

1

8


0

WDTD


Bits

[14:12]

[11:0]

Field

WPSC

WDTD

Descriptions

Watchdog Timer Prescaler Selection

000: 1/1

001: 1/2

010: 1/4

011: 1/8

100: 1/16

101: 1/32

110: 1/64

111: 1/128

Watchdog Timer Delta Value

Define the permitted range to reload the Watchdog Timer. If the Watchdog Timer counter value is less than or equal to WDTD, writing to the WDTCR register with

WDTRS = 1 and RSKEY = 0x5FA0 will reload the timer. If the Watchdog Timer value is greater than WDTD, then writing WDTCR with WDTRS = 1 and RSKEY = 0x5FA0 will cause a Watchdog Timer error. This feature can be disabled by programming a

WDTD value greater then or equal to the WDTV value.

Rev. 1.00 558 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Watchdog Timer Status Register – WDTSR

This register specifies the Watchdog timer status.

Offset: 0x00C


31 30 29

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

Type/Reset

Bits

[1]

[0]

26

18

10

25

17

9

24

16

8

2 1 0

WDTERR WDTUF

WC 0 WC 0

Field

WDTERR

WDTUF

Descriptions

Watchdog Timer Error

0: No Watchdog Timer error has occurred since the last read of this register

1: A Watchdog Timer error has occurred since the last read of this register

Note: A reload operation when the Watchdog Timer counter value is larger than

WDTD causes a Watchdog Timer error. Note that this bit is a write-one-clear flag.

Watchdog Timer Underflow

0: No Watchdog Timer underflow has occurred since the last read of this register

1: A Watchdog Timer underflow has occurred since the last read of this register

Note that this bit is a write-one-clear flag.

Rev. 1.00 559 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Watchdog Timer Protection Register – WDTPR

This register specifies the Watchdog timer protect key configuration.

Offset: 0x010


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PROTECT

10 9 8


7 6 5 4 3 2 1 0

PROTECT


Bits

[15:0]


PROTECT Watchdog Timer Register Protection

For write operation:

0x35CA: Disable the Watchdog Timer register write protection

Others: Enable the Watchdog Timer register write protection

For read operation:

0x0000: Watchdog Timer register write protection is disabled

0x0001: Watchdog Timer register write protection is enabled

This register is used to enable/disable the Watchdog timer configuration register write protection function. All configuration registers become read only except for

WDTCR and WDTPR when the register write protection is enabled. Additionally, the read operation of PROTECT[0] can obtain the enable/disable status of the register write protection function.

Rev. 1.00 560 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Watchdog Timer Clock Selection Register – WDTCSR

This register specifies the Watchdog timer clock source selection and lock configuration.

Offset: 0x018


31 30 29

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

Reserved

21

13

5

28

20

27

Reserved

19

Reserved

26

18

12

4

WDTLOCK

RW 0

11

Reserved

3

10

2

Reserved

Bits

[4]

[0]

25

17

9

24

16

8

1 0

WDTSRC

RW 0


WDTLOCK Watchdog Timer Lock Mode

0: This bit is only set to 0 on any reset. It can not be cleared by software.

1: This bit is set once only by software and locks the Watchdog Timer function.

Software can set this bit to 1 at any time. Once the WDTLOCK bit is set, the function and registers of the Watchdog Timer cannot be modified or disabled, including the

Watchdog Timer clock source. The lock mode can only be disabled until a system reset occurs.

WDTSRC Watchdog Timer Clock Source Selection

0: Internal 32 kHz RC oscillator clock is selected (LSI)

1: External 32.768 kHz crystal oscillator clock is selected (LSE)

Select using software to control the Watchdog timer clock source.

Rev. 1.00 561 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

27

Real Time Clock (RTC)

Introduction

The Real Time Clock, RTC, circuitry includes the APB interface, a 24-bit up-counter, a control register, a prescaler, a compare register and a status register. Most of the RTC circuits are located in the V

DD

Power Domain, as shown in dotted red box in the accompanying figure, except for the APB interface. The APB interface is located in the V

DD15

domain. Therefore, it is necessary to be isolated by the ISO signal that comes from the power control unit when the V

DD15

domain is powered off, i.e., when the device enters the Power-Down mode. The RTC counter is used as a wakeup timer to let the system resume from the power-saving modes. The detailed RTC function will be described in the following sections.

LSE

OSC

CK_LSE

1

LSI RC

OSC

CK_LSI

0

RTCSRC

CK_RTC

ISO

APB Bus

APB Interface and

ISO & Level Shift

Prescaler

CK_SECOND

24-bit Counter

CMPCLR

Compare

Register

24

Match

24

V

DD

Power Domain V

DD

1.5 V Core Power Domain V

DD15 set

CSECFLAG set set

OVFLAG

CMFLAG

Figure 197. RTC Block Diagram

CSECIEN

OVIEN

CMIEN

CSECWEN

OVWEN

CMWEN

RTCINT

( To NVIC )

RTCWAKEUP

( To EXTI and PWRCU )

Features

▆

24-bit up-counter for counting elapsed time

▆

▆

▆

▆

▆

Programmable clock prescaler

● Division factor: 1, 2, 4, 8…, 32768

24-bit compare register for alarm usage

RTC clock source

● LSE oscillator clock

● LSI oscillator clock

Three RTC Interrupt/wakeup settings

● RTC second clock interrupt/wakeup

● RTC compare match interrupt/wakeup

● RTC counter overflow interrupt/wakeup

The RTC interrupt/wakeup event can work together with power management to wake up the chip from power saving mode

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Cortex ® -M0+ MCU


RTC Related Register Reset

The RTC registers can only be reset by either a V

Domain software reset by setting the PWRST bit in the PWRCR register. Other reset events have no effect to clear the RTC registers.

DD

Domain power on reset, POR, or by a V

DD

Reading RTC Register

The RTC control logic and the related registers are powered by the V the APB bus, which is located in the V in the V

DD15

DD

supply voltage. Therefore, the RTC circuitry remains operational in the Power-Down mode where V

DD15

is powered off. Only

domain, is interconnected to the RTC circuits located

DD

domain using level shift circuitry and isolated by the ISO signals when the V

DD15

supply voltage is powered off.

Low Speed Clock Configuration

The default RTC clock source, CK_RTC, is derived from the LSI oscillator. The CK_RTC clock can be derived from either the external 32768 Hz crystal oscillator, named the LSE oscillator, or the internal 32K RC oscillator named the LSI oscillator, by setting the RTCSRC bit in the RTCCR register. A prescaler is provided to divide the CK_RTC by a ratio ranged from 2 0 to 2 15 determined by the RPRE [3:0] field. For instance, setting the prescaler value RPRE [3:0] to 0xF will generate an exact 1 Hz CK_SECOND clock if the CK_RTC clock frequency is equal to 32,768 Hz. The

LSE oscillator can be enabled by the LSEEN control bit in the RTCCR register. In addition, the

LSE oscillator startup mode can be selected by configuring the LSESM bit in the RTCCR register.

This enables the LSE oscillator to have either a shorter startup time or a lower power consumption, both of which are traded off depending upon specific application requirements. An example of the startup time and the power consumption for different startup modes are shown in the accompanying table for reference.

Table 70. LSE Startup Mode Operating Current and Startup Time

Startup Mode

Normal startup

LSESM Setting in the RTCCR Register

0

Operating Current

2.0 μA

Startup Time

Above 500 ms

Fast startup 1 3.5 μA Below 300 ms

@ V

DD

= 3.3 V and LSE clock = 32,768 Hz; these values are only for reference, actual values are dependent on the specification of the external 32.768 kHz crystal.

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HT32F5828

Cortex ® -M0+ MCU

RTC Counter Operation

The RTC provides a 24-bit up-counter which increases at the falling edge of the CK_SECOND clock and whose value can be read from the RTCCNT register asynchronously via the APB bus.

A 24-bit compare register, RTCCMP, is provided to store the specific value to be compared with the RTCCNT content. This is used to define a pre-determined time interval. When the RTCCNT register content is equal to the RTCCMP register value, the match flag CMFLAG in the RTCSR register will be set by hardware and an interrupt or wakeup event can be sent according to the corresponding enable bits in the RTCIWEN register. The RTC counter will be either reset to zero or keep counting when the compare match event occurs, dependent upon the CMPCLR bit in the RTCCR register. For example, if the RPRE [3:0] is set to 0xF, the RTCCMP register content is set to a decimal value of 60 and the CMPCLR bit is set to 1, then the CMFLAG bit will be set every minute. In addition, the OVFLAG bit in the RTCSR register will be set when the RTC counter overflows. A read operation on the RTCSR register clears the status flags including the

CSECFLAG, CMFLAG and OVFLAG bits.

Interrupt and Wakeup Control

The falling edge of the CK_SECOND clock causes the CSECFLAG bit in the RTCSR register to be set and generates an interrupt if the corresponding interrupt enable bit, CSECIEN, in the

RTCIWEN register is set. The wakeup event can also be generated to wake up the HSI/HSE oscillators, the PLL circuitry, the LDO and the CPU core if the corresponding wakeup enable bit CSECWEN is set. When the RTC counter overflows or a compare match event occurs, it will generate an interrupt or a wake up event determined by the corresponding interrupt or wakeup enable control bits, OVIEN/OVWEN or CMIEN/CMWEN bits, in the RTCIWEN register. Refer to the related register definitions for more details.

RTCOUT Output Pin Configuration

The following table shows the RTCOUT output format according to the mode, polarity, and event selection setting.

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Cortex ® -M0+ MCU

Table 71. RTCOUT Output Mode and Active Level Setting

ROWM ROES RTCOUT Output Waveform

1

(Level mode)

0

(Compare match)

1

(Second clock)

0

(Compare match)

1

(Second clock)

RTCCMP

RTCCNT

RTCOUT (ROAP = 0)

RTCOUT (ROAP = 1)

ROLF

3

T

R

0

(Pulse mode)

RTCCMP

RTCCNT 3

T

R

T

RTCOUT (ROAP = 0)

RTCOUT (ROAP = 1)

ROLF

R

RTCCMP

RTCCNT

RTCOUT (ROAP = 0)

RTCOUT (ROAP = 1)

ROLF

RTCCMP

RTCCNT

RTCOUT (ROAP = 0)

RTCOUT (ROAP = 1)

ROLF

T

R

: RTCOUT output pulse time = 1 / f

CK_RTC

→: Cleared by software reading ROLF bit

3

3

→ →

4

4

X

4

4

4

4

X

T

R

→

5

5

5

5

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Cortex ® -M0+ MCU

Register Map

The following table shows the RTC registers and reset values. Note all the registers in this unit are located at the V

DD

power domain.

Table 72. RTC Register Map

Register Offset

RTCCNT 0x000

Description

RTC Counter Register

RTCCMP

RTCCR

RTCSR

0x004

0x008

0x00C

RTCIWEN 0x010

RTC Compare Register

RTC Control Register

RTC Status Register

RTC Interrupt and Wakeup Enable Register

Reset Value

0x0000_0000

0x0000_0000

0x0000_0F04

0x0000_0000

0x0000_0000


RTC Counter Register – RTCCNT

This register defines a 24-bit up-counter which is increased by the CK_SECOND clock.

Address: 0x000


DD

Power Domain reset only)

31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

RTCCNTV

18 17 16


15 14 13 12 11

RTCCNTV

10 9 8


7 6 5 4 3

RTCCNTV

2 1 0


Bits

[23:0]


RTCCNTV RTC Counter Value

The current value of the RTC counter is returned when reading the RTCCNT register. The RTCCNT register is updated during the falling edge of the CK_

SECOND clock. This register is reset by one of the following conditions:

- V

- V

DD

Domain software reset – set the PWRST bit in the PWRCR register

DD

Domain power on reset – POR

- Compare match (RTCCNT = RTCCMP) when CMPCLR = 1 (in the RTCCR register)

- RTCEN bit changed from 0 to 1

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Cortex ® -M0+ MCU

RTC Compare Register – RTCCMP

This register defines a specific value to be compared with the RTC counter value.

Address: 0x004


DD


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

RTCCMPV

18 17 16


15 14 13 12 11

RTCCMPV

10 9 8


7 6 5 4 3 2 1 0

RTCCMPV


Bits

[23:0]


RTCCMPV RTC Compare Match Value

A match condition happens when the value in the RTCCNT register is equal to the

RTCCMP value. An interrupt can be generated if the CMIEN bit in the RTCIWEN register is set. When the CMPCLR bit in the RTCCR register is set to 0 and a match condition happens, the CMFLAG bit in the RTCSR register is set while the value in the RTCCNT register is not affected and will continue to count until overflow. When the CMPCLR bit is set to 1 and a match condition happens, the CMFLAG bit in the

RTCSR register is set and the RTCCNT register will be reset to zero and then the counter continues to count.

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Cortex ® -M0+ MCU

RTC Control Register – RTCCR

This register specifies a range of RTC circuitry control bits.

Address: 0x008

Reset value: 0x0000_0F04 (Reset by V

DD


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30 29 28 27

Reserved

26 25 24

22

Reserved

21 20

ROLF

19

ROAP

18

ROWM

17

ROES

16

ROEN

RC 0 RW 0 RW 0 RW 0 RW 0

14 13

Reserved

12 11 10 9

RPRE

8

6 5 4

RW 1 RW 1 RW 1 RW 1

3 2 1 0

Reserved LSESM CMPCLR LSEEN Reserved RTCSRC RTCEN


Bits

[20]

[19]

[18]

[17]

[16]

Field

ROLF

ROAP

ROWM

ROES

ROEN

Descriptions

RTCOUT Level Mode Flag

0: RTCOUT Output is inactive

1: RTCOUT Output is holding as active level

Set by hardware when in the level mode (ROWM = 1) and a RTCOUT output event occurs. Cleared by software reading this flag. The RTCOUT signal will return to the inactive level after software has read this bit.

RTCOUT Output Active Polarity

0: Active level is high

1: Active level is low

RTCOUT Output Waveform Mode

0: Pulse mode

The output pulse duration is one RTC clock (CK_RTC) period.

1: Level mode

The RTCOUT signal will remain at an active level until the ROLF bit is cleared by software reading the ROLF bit.

RTCOUT Output Event Selection

0: RTC compare match is selected

1: RTC second clock (CK_SECOND) event is selected

The ROES bit can be used to select whether the RTCOUT signal is output on the

RTCOUT pin when a RTC compare match event or the RTC second clock (CK_

SECOND) event occurs.

RTCOUT Output Pin Enable

0: Disable RTCOUT output pin

1: Enable RTCOUT output pin

When the ROEN bit is set to 1, the RTCOUT signal will be at an active level once a RTC compare match or the RTC second clock (CK_SECOND) event occurs. The active polarity and output waveform mode can be configured by the ROAP and

ROWM bits respectively. When the ROEN bit is cleared to 0, the RTCOUT pin will be in a floating state.

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Cortex ® -M0+ MCU

[5]

[4]

[3]

[1]

[0]

Bits

[11:8]

Field

RPRE

LSESM

CMPCLR

LSEEN

RTCSRC

RTCEN

Descriptions

RTC Clock Prescaler Select

CK_SECOND = CK_RTC / 2 RPRE

0000: CK_SECOND = CK_RTC / 2 0



…


LSE oscillator Startup Mode

0: Normal startup and requires less operating power

1: Fast startup but requires higher operating current

Compare Match Counter Clear

0: 24-bit RTC counter is not affected when compare match condition occurs

1: 24-bit RTC counter is cleared when compare match condition occurs

LSE oscillator Enable Control

0: LSE oscillator is disabled

1: LSE oscillator is enabled

RTC Clock Source Selection

0: LSI oscillator is selected as the RTC clock source

1: LSE oscillator is selected as the RTC clock source

RTC Enable Control

0: RTC is disabled

1: RTC is enabled

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Cortex ® -M0+ MCU

RTC Status Register – RTCSR

This register stores the counter flags.

Address: 0x00C


DD

Power Domain reset and RTCEN bit change from 1 to 0)

31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11

Reserved

3

10 9 8

2 1 0

OVFLAG CMFLAG CSECFLAG

RC 0 RC 0 RC 0

Bits

[2]

[1]

[0]


OVFLAG

CMFLAG

Counter Overflow Flag

0: Counter overflow has not occurred since the last RTCSR register read operation

1: Counter overflow has occurred since the last RTCSR register read operation

This bit is set by hardware when the counter value in the RTCCNT register changes from 0x00FF_FFFF to 0x0000_0000 and cleared by read operation. This bit is suggested to be read in the RTC IRQ handler and should be taken care when software polling is used.

Compare Match Condition Flag

0: Compare match condition has not occurred since the last RTCSR register read operation

1: Compare match condition has occurred since the last RTCSR register read operation.

This bit is set by hardware on the CK_SECOND clock falling edge when the

RTCCNT register value is equal to the RTCCMP register content. It is cleared by software reading this bit. This bit is suggested for access in the corresponding RTC interrupt routine – do not use software polling during software free running.

CSECFLAG CK_SECOND Occurrence Flag

0: CK_SECOND has not occurred since the last RTCSR register read operation

1: CK_SECOND has occurred since the last RTCSR register read operation

This bit is set by hardware on the CK_SECOND clock falling edge. It is cleared by software reading this bit. This bit is suggested for access in the corresponding RTC interrupt routine – do not use software polling during software free running.

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Cortex ® -M0+ MCU

RTC Interrupt and Wakeup Enable Register – RTCIWEN

This register contains the interrupt and wakeup enable bits.

Address: 0x010


DD


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

Reserved

5

Reserved

20

12

4

27

Reserved

19

Reserved

11

3

26

18

25

17

24

16

10 9 8

OVWEN CMWEN CSECWEN

RW 0 RW 0 RW 0

2 1 0

OVIEN CMIEN CSECIEN

RW 0 RW 0 RW 0

Bits

[10]

[9]

[8]

[2]

[1]

[0]


OVWEN

CMWEN

Counter Overflow Wakeup Enable

0: Counter overflow wakeup is disabled

1: Counter overflow wakeup is enabled

Compare Match Wakeup Enable

0: Compare match wakeup is disabled

1: Compare match wakeup is enabled

CSECWEN Counter Clock CK_SECOND Wakeup Enable

0: Counter Clock CK_SECOND wakeup is disabled

1: Counter Clock CK_SECOND wakeup is enabled

OVIEN Counter Overflow Interrupt Enable

0: Counter Overflow Interrupt is disabled

1: Counter Overflow Interrupt is enabled

CMIEN Compare Match Interrupt Enable

0: Compare Match Interrupt is disabled

1: Compare Match Interrupt is enabled

CSECIEN Counter Clock CK_SECOND Interrupt Enable

0: Counter Clock CK_SECOND Interrupt is disabled

1: Counter Clock CK_SECOND Interrupt is enabled

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28

Cyclic Redundancy Check (CRC)

Introduction

The CRC (Cyclic Redundancy Check) calculation unit is an error detection technique test algorithm and is used to verify data transmission or storage data correctness. A CRC calculation takes a data stream or a block of data as input and generates a 16-bit or 32-bit output remainder. Ordinarily, a data stream is suffixed by a CRC code and used as a checksum when being sent or stored.

Therefore, the received or restored data stream is calculated by the same generator polynomial as described above. If the new CRC code result does not match the one calculated earlier, that means data stream contains a data error.

CRC Control

Register

CRC Seed

Register

CRC Data

Register

B3

B2

B1

B0

MUX

1's

COMP

BIT

REVERSE

CCITT-16

POLY

CRC-16

POLY

CRC-32

POLY

MUX

MUX

CRC FSM

CRC

REG

1's

COMP

BIT

REVERSE

BYTE

REVERSE

CRC Sum

Register

BYTE

REVERSE

Figure 198. CRC Block Diagram

Features

▆

Supports CRC16 polynomial: 0x8005, X 16 + X 15 + X 2 + 1

▆

▆

▆

▆

▆

▆

▆

Supports CCITT CRC16 polynomial: 0x1021, X 16 + X 12 + X 5 + 1

Supports IEEE-802.3 CRC32 polynomial: 0x04C11DB7, X 32

+ X 10 + X 8 + X 7 + X 5 + X 4 + X 2 + X + 1

+ X 26 + X 23 + X 22 + X 16 + X 12 + X 11

Supports 1’s complement, byte reverse and bit reverse operation on data and checksum

Supports byte, half-word and word data size

Programmable CRC initial seed value

CRC computation done in 1 AHB clock cycle for 8-bit data and 4 AHB clock cycles for 32-bit data

Supports PDMA to complete a CRC computation of a block of memory

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Cortex ® -M0+ MCU


This unit only enables the calculation in the CRC16, CCITT CRC16 and IEEE-802.3 CRC32 polynomials. In this unit, the generator polynomial is fixed to the numeric values for those modes; therefore, the CRC value based on other generator polynomials cannot be calculated.

CRC Computation

The CRC calculation unit has a 32-bit write CRC data register (CRCDR) and a read CRC checksum register (CRCCSR). The CRCDR register is used to input new data (write access) and the CRCCSR register is used to hold the result of the previous CRC calculation (read access). Each write operation to the CRCDR register creates a combination of the previous CRC value (stored in CRCCSR) and the new one. The CRC block diagram is shown as Figure 198. The CRC unit calculates the CRC data register (CRCDR) value byte by byte and the default byte and bit order is big-endian. The CRCDR register can be written by word, right-aligned half-word and right-aligned byte. For the other registers only 32-bit access is allowed. The duration of the computation depends on data width:

▆

▆

▆

4 AHB clock cycles for 32-bit data input

2 AHB clock cycles for 16-bit data input

1 AHB clock cycle for 8-bit data input

Byte and Bit Reversal for CRC Computation

The byte reordering and byte-level bit reversal operation can be occurred before the data is used in the CRC calculation or after the CRC checksum output. They are configurable using the corresponding setting field of the CRCCR register. These operations occur on word or half-word writes. The hardware ignores the DATBYRV bit of the CRCCR register during any byte writes but the bit reversal setting DATBIRV are still applied to the byte. Figure 199 shows the byte and bit reversal operation example.

Byte 3 Byte 2 Byte 1 Byte 0

Input data is big-endian

Byte Reversal Enable

Byte 0 Byte 1 Byte 2 Byte 3

Bit Reversal Enable

Byte 0 Byte 1

Figure 199. CRC Data Bit and Byte Reversal Example

Rev. 1.00 573 of 637

Byte 2 Byte 3

December 28, 2020

32-Bit Arm ®

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Cortex ® -M0+ MCU

CRC with PDMA

A PDMA channel with software trigger may be used to transfer data into the CRC unit. If a huge block data needs to be calculated, the recommended PDMA model is to use the PDMA to transfer all available words of data and use software writes to transfer the other remaining bytes. To write data into the CRC unit, the PDMA should use word access method to transfer data from the source location of memory to the CRC data register (CRCDR) in fixed address mode. Then software can write any remaining bytes to the CRC data register (CRCDR) and read the CRC calculation result value from the CRC checksum register (CRCCSR).

Register Map

The following table shows the CRC registers and reset values.

Table 73. CRC Register Map

Register Offset

CRCCR 0x000

Description

CRC Control Register

CRCSDR

CRCCSR

CRCDR

0x004

0x008

0x00C

CRC Seed Register

CRC Checksum Register

CRC Data Register

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000


CRC Control Register – CRCCR

This register specifies the corresponding CRC function enable control.

Offset: 0x000


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

Reserved

10 9 8

Type/Reset

7 6 5 4 3 2

SUMCMPL SUMBYRV SUMBIRV DATCMPL DATBYRV DATBIRV

1 0

POLY


Bits

[7]

[6]


SUMCMPL 1’s Complement operation on Checksum Output

0: Disable

1: Enable

SUMBYRV Byte Reverse operation on Checksum Output

0: Disable

1: Enable

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Cortex ® -M0+ MCU

Bits

[5]

[4]

[3]

[2]

[1:0]

Field

SUMBIRV

DATCMPL

DATBYRV

DATBIRV

POLY

Descriptions

Bit Reverse operation on Checksum Output

0: Disable

1: Enable

1’s Complement operation on Data

0: Disable

1: Enable

Byte Reverse operation on Data

0: Disable

1: Enable

Bit Reverse operation on Data

0: Disable

1: Enable

CRC polynomial

00: CRC-CCITT (0x1021)

01: CRC-16 (0x8005)

1x: CRC-32 (0x04C11DB7)

CRC Seed Register – CRCSDR

This register is used to specify the CRC seed.

Offset: 0x004


31 30 29 28 27

SEED

26 25 24


23 22 21 20 19 18 17 16

SEED


15 14 13 12 11

SEED

10 9 8


7 6 5 4 3

SEED

2 1 0


Bits

[31:0]

Field

SEED

Descriptions

CRC Seed Data

Put the 16/32-bit seed value in this register according to the polynomial setting in the CRCCR register.

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CRC Checksum Register – CRCCSR

This register contains the CRC checksum output.

Offset: 0x008


31 30 29 28 27

CHKSUM

26 25 24


23 22 21 20 19

CHKSUM

18 17 16


15 14 13 12 11

CHKSUM

10 9 8


7 6 5 4 3 2 1 0

CHKSUM


Bits

[31:0]

Field

CHKSUM

Descriptions

CRC Checksum Data

Get the CRC 16/32-bit checksum result from this register according to the polynomial setting in the CRCCR register after all data are written to the CRCDR register.

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CRC Data Register – CRCDR

This register is used to specify the CRC input data.

Offset: 0x00C


31 30 29 28 27

CRCDATA

26 25 24


23 22 21 20 19

CRCDATA

18 17 16


15 14 13 12 11

CRCDATA

10 9 8


7 6 5 4 3 2 1 0

CRCDATA


Bits

[31:0]


CRCDATA CRC Input Data

Byte, half-word and word writes are allowed. 1’s complement, byte reverse and bit reverse operation can be applied.

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29

Peripheral Direct Memory Access (PDMA)

Introduction

The Peripheral Direct Memory Access circuitry, PDMA, provides 6 unidirectional channels for dedicated peripherals to implement the peripheral-to-memory and memory-to-peripheral data transfer. The memory-to-memory data transfer such as the FLASH-to-SRAM or SRAM-to-

SRAM type is also supported and requested by the application program. Each PDMA channel configuration is independent. The PDMA channel transfer is split into multiple block transactions and the size of a block is equal to the block length multiplied by the data width.

Features

▆

▆

▆

▆

▆

▆

▆

6 unidirectional PDMA channels

Memory-to-peripheral, peripheral-to-memory and memory-to-memory data transfer

8-bit, 16-bit and 32-bit width data transfer

Software and hardware requested data transfer with configurable channel priority

Linear address, circular address and fixed address modes

4 transfer event flags – Transfer Complete, Half Transfer, Block End and Transfer Error

Auto-Reload function

AHB Slave

Interface

Channel Logic &

Registers

AHB Master

Interface

Figure 200. PDMA Block Diagram

PDMA

Req. & Ack

Interface

Control Logic &

Registers

Transfer

Interrupts

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AHB Master

The PDMA is an AHB master connected to other AHB peripherals such as the FLASH memory, the SRAM memory and the AHB-to-APB bridges through the bus-matrix. The CPU and PDMA can access different AHB slaves at the same time via the bus-matrix.

PDMA Channel

There are 6 unidirectional PDMA channels used to support data transfer between the peripherals and the memory. The configuration and operation of each PDMA channel is independent. For a bidirectional transfer application, two PDMA channels are required. Each PDMA channel is designed to support the dedicated multiple peripherals with the same registers. Therefore, one

PDMA channel only can service one peripheral at the same time. The related registers of the

PDMA channel are limited to be accessed with 32-bit operation; otherwise a system hard fault event will occur.

PDMA Request Mapping

The multiple requests from the peripherals (ADC, SPI, I 2 C, USART and so on) are simply logically

ANDed before entering the PDMA, which means that only one request must be enabled at a time in each PDMA channel. Refer to Figure 79 – PDMA request mapping architecture and detailed peripheral IP requests mapping table is shown as the Table 47. The peripheral DMA requests can be independently activated/de-activated by programming the DMA control bit in the registers of the corresponding peripheral.

IP1

Peripheral request signals

CH0 H/W REQ

IPn

CH0 S/W REQ

0

Channel 0

1

SWTRIG Enable

Channel 1

High priority

Channel 2 PDMA

Request

IPx

IPy

CHn H/W REQ

CHn S/W REQ

0

1

Channel n

Figure 201. PDMA Request Mapping Architecture

SWTRIG Enable

Low priority

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32-Bit Arm ®

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Cortex ® -M0+ MCU

Table 74. PDMA Channel Assignments

IP

(x = 0, 1) CH0

ADC

CH1

PDMA Channel Number

CH2 CH3

ADC

SPIx

USART

UARTx

SCIx

I 2 Cx

GPTM

PWMx

I 2 S

AES

USR_RX

GT_CH1

GT_CH3

PWM0_CH1

PWM0_CH3

USR_TX

GT_CH2

GT_UEV

PWM0_CH2

PWM0_UEV

I2S_RX

SPI0_RX

UR0_RX

SCI1_RX

I2C0_RX

GT_CH0

GT_TRIG

PWM0_CH0

PWM0_TRIG

I2S_TX

SPI0_TX

UR0_TX

SCI1_TX

I2C1_RX

PWM1_CH1

PWM1_CH3

CH4

SPI1_RX

UR1_RX

SCI0_RX

I2C0_TX

UR1_TX

SCI0_TX

I2C1_TX

PWM1_CH2

PWM1_UEV

PWM1_CH0

PWM1_TRIG

AES_OUT

CH5

SPI1_TX

AES_IN

Channel Transfer

A PDMA channel transfer is split into multiple block transactions with PDMA arbitration occurring at the end of each block transaction. Although these channel transfers can all be activated, there is only one block transaction being transferred through the bus at a time. The channel transfer sequence depends upon the channel priority setting of each PDMA channel. The total transfer size is calculated from the block transaction count and block size. The block size is equal to the product of the block length and data bit width. For an efficient transfer, it is recommended that the block length is set as a multiple of 4.

The total transfer data size calculation is shown as the following equation:

A PDMA channel total transfer data size = Block transaction count × (Block length × Data width)

Channel Priority

The PDMA provides four priority levels, known as very high, high, medium and low, which can be configured by the application software. The PDMA also provides two methods to determine the channel priority. One is determined by application software configuration and the other is determined by the fixed hardware channel number. The PDMA arbitration processor will first check the software configuring channel priority level used to request the PDMA to provide the data transfer services. If more than one channel has the same priority, the channel with a smaller channel number will have priority over one with a larger channel number after arbitration.

Note that the highest priority channel will not occupy the PDMA service all the time when other lower priority channel requests are pending. The highest priority channel will be skipped for one block transaction time duration after one block transaction is complete. Then a block transaction requested by the second priority channel will be performed. After a block transaction of the second priority channel is complete, the PDMA arbitration processor will re-check all of the requested channel priority with the exception of the second priority channel since the second priority channel will be excluded after the end of a block transaction. Therefore, a block data transaction of the higher priority channel will be serviced and this channel will be excluded from the priority arbitration at the end of the block transaction. The PDMA will keep transferring the data using the method described above until all of the requested channel data transfer is complete. Refer to the accompanying figure for an example which shows the PDMA channel arbitration and scheduling.

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32-Bit Arm ®

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Cortex ® -M0+ MCU

Channel 0: priority=very high, block count=2, block length=2

Channel 1: priority=high,

Channel 2: priority=low,

Priority: CH0 > CH1 > CH2 block count=3, block length=4 block count=3, block length=6

Priority: CH1 > CH2

Skip: CH0

Priority: CH1 > CH2

Skip: CH0

Priority: CH1

Skip: CH2

CH0

Block 0

CH1

Block 0

CH0

Block 1

CH1

Block 1

CH2

Block 0

CH1

Block 2

CH2

Block 1

Priority: CH0 > CH2

Skip: CH1

Priority: CH0 > CH1 > CH2

Skip: n/a

Priority: CH2

Skip: CH1

Figure 202. PDMA Channel Arbitration and Scheduling Example

Priority: CH2

Skip: n/a

Priority: CH2

Skip: n/a

CH2

Block 2

Time

Transfer Request

For a peripheral-to-memory or memory-to-peripheral transfer, one peripheral hardware request will trigger one block transaction of the dedicated PDMA channel. However, a complete data transfer of the relevant dedicated PDMA channel will be triggered when a software request occurs. It is recommended that the PDMA channel is configured to have a lower priority level and a smaller block length which is requested by the software for memory-to-memory data copy applications.

Address Mode

The PDMA provides three kinds of address modes which are the linear address, circular address and fixed address modes. These different address modes are used to support different kinds of source and destination address arrangements. The following table shows the detailed address mode combinations.

Table 75. PDMA Address Modes

Source Address Mode

Linear Increment / Decrement Address



Circular Increment / Decrement Address


Fixed Address

Fixed Address

Destination Address Mode



Fixed Address




Fixed Address

Linear Address Mode

After data is transferred, the current address will be increased or decreased by 1, 2 or 4 depending upon the data bit width setting.

Circular Address Mode

After data is transferred, the current address will be increased or decreased by 1, 2 or 4 depending upon the data bit width setting. When a block transaction is complete, the current address is loaded with the configured start address.

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HT32F5828

Cortex ® -M0+ MCU

Fixed Address Mode

After data is transferred, the current address remains unchanged.

Auto-Reload

When the auto-reload control bit, AUTORLn, in the PDMA channel n control register

PDMACHnCR is set, both the channel n current address and the channel n current transfer size will be automatically reloaded with the corresponding start value after the current PDMA channel data transfer has totally completed. The channel n will still be activated and the next relative

PDMA request can be serviced without any re-configuration using the application software.

Transfer Interrupt

There are five transfer events during which the interrupts can be asserted for each PDMA channel.

These are the block transaction end (BE), half transfer (HT), transfer complete (TC), transfer error (TE) and global transfer event (GE). Setting the corresponding control bits in the PDMA interrupt enable register PDMAIER will enable the relevant interrupt events. The global interrupt event, GE, will be generated if any of the four interrupt events including the BE, HT, TC and TE occurs. Clearing the BE, HT, TC or TE event flag will also clear the GE flag. Clearing the GE flag will automatically clear all other event flags. The TE interrupt event will occur when the

PDMA accesses a system reserved address space or when the PDMA receives a request but the corresponding transfer size setting is equal to zero.

Register Map

The following table shows the PDMA registers and reset values.

Table 76. PDMA Register Map

Register Offset

PDMA Channel 0 Registers

PDMACH0CR 0x000

Description

PDMA Channel 0 Control Register

PDMACH0SADR 0x004

PDMACH0DADR 0x008

PDMACH0TSR 0x010

PDMACH0CTSR 0x014


PDMACH1CR 0x018

PDMA Channel 0 Source Address Register

PDMA Channel 0 Destination Address Register

PDMA Channel 0 Transfer Size Register

PDMA Channel 0 Current Transfer Size Register


PDMACH1SADR 0x01C PDMA Channel 1 Source Address Register

PDMACH1DADR 0x020 PDMA Channel 1 Destination Address Register

PDMACH1TSR 0x028 PDMA Channel 1 Transfer Size Register

PDMACH1CTSR 0x02C PDMA Channel 1 Current Transfer Size Register


PDMACH2CR 0x030

PDMACH2SADR 0x034



PDMACH2DADR

PDMACH2TSR

PDMACH2CTSR

0x038

0x040

0x044


PDMACH3CR 0x048



PDMA Channel 2 Current Transfer Size Register


Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Register Offset Description


PDMACH3DADR 0x050

PDMACH3TSR 0x058





PDMACH4CR 0x060 PDMA Channel 4 Control Register

PDMACH4SADR 0x064

PDMACH4DADR 0x068

PDMACH4TSR 0x070




PDMACH4CTSR 0x074 PDMA Channel 4 Current Transfer Size Register


PDMACH5CR 0x078 PDMA Channel 5 Control Register


PDMACH5DADR 0x080

PDMACH5TSR 0x088




PDMA Global Register

PDMAISR 0x120

PDMAISCR 0x128

PDMAIER 0x130

PDMA Interrupt Status Register

PDMA Interrupt Status Clear Register

PDMA Interrupt Enable Register

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

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Cortex ® -M0+ MCU


PDMA Channel n Control Register – PDMACHnCR, n = 0 ~ 5

This register is used to specify the PDMA channel n data transfer configuration.

Offset: 0x000 (0), 0x018 (1), 0x030 (2), 0x048 (3), 0x060 (4), 0x078 (5)


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13

Reserved

12 11 10

AUTORLn FIXAENn

9 8

CHnPRI

Type/Reset

7 6 5 4

SRCAMODn SRCAINCn DSTAMODn DSTAINCn

RW 0 RW 0 RW 0 RW 0

3 2 1 0

DWIDTHn SWTRIGn CHnEN


Bits

[11]

[10]

[9:8]


AUTORLn Channel n Auto-Reload Enable Control

0: Disable Auto-Reload function

1: Enable Auto-Reload function

If this bit is set to 1 to enable the auto-reload function, both the channel n current address and the channel n current transfer size will be reloaded with the relevant start value and the PDMA channel n will still be activated when a transfer is complete. If this bit is cleared to 0, the channel n current address and the channel n current transfer size will remain unchanged and the PDMA channel n will be disabled after a transfer completion.

FIXAENn

CHnPRI

Channel n Fixed Address Enable control

0: Disable fixed address function in the circular address mode

1: Enable fixed address function in the circular address mode

Note that this bit is only available when the source or destination address mode is set to be in the circular address mode. For example, the source address mode is set as in the linear address mode and the destination address mode is set as in the circular mode. If this bit is set to enable the fixed address function, then the source address mode will still be in the linear address but the destination address mode will be in the fixed address mode instead of the circular address mode.

Channel n Priority

00: Low

01: Medium

10: High

11: Very high

The CHnPRI field is used to configure the channel priority using the application program. If there are more than one channel which have the same software configured priority level, the channel with the smaller channel number will have priority to transfer one block of data after the arbitration.

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[7]

[6]

[5]

[4]

[3:2]

[1]


SRCAMODn Channel n Source Address Mode selection

0: Linear address mode

1: Circular address mode

In the linear address mode, the current source address value can be increased or decreased, determined by the SRCAINCn bit value during a complete transfer.

In the circular address mode, the current source address value can be increased or decreased which is also determined by the SRCAINCn bit value during a block transfer and will be loaded with the lower 16-bit value of the PDMACHnSADR register, which will be regarded as the current source address when a block transaction has completed.

SRCAINCn Channel n Source Address Increment control

0: Increment

1: Decrement

This bit is used to determine whether the current source address is increased or decreased during a complete transfer in the linear address mode or a block transfer in the circular address mode.

DSTAMODn Channel n Destination Address Mode selection

0: Linear address mode

1: Circular address mode

In linear address mode, the current destination address value can be increased or decreased, determined by the DSTAINCn bit value during a complete transfer. In the circular address mode, the current destination address value can be increased or decreased which is also determined by the DSTAINCn bit value during a block transfer and will be loaded with the lower 16-bit value of the PDMACHnDADR register, which will be regarded as the current destination address when a block transfer has completed.

DSTAINCn Channel n Destination Address Increment Control

0: Increment

1: Decrement

This bit is used to determine if the current destination address is increased or decreased during a complete transfer in the linear address mode or a block transfer in the circular address mode.

DWIDTHn Data Bit Width selection

00: 8-bit

01: 16-bit

10: 32-bit

11: Reserved

The field is used to select the data bit width of the corresponding PDMA channel n.

SWTRIGn Software Trigger control

0: No operation

1: Software triggered transfer request

Setting this bit will generate a memory-to-memory software transfer request on the corresponding PDMA channel n. It is automatically cleared when a transfer has completely finished.

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HT32F5828

Cortex ® -M0+ MCU

Bits

[0]

Field

CHnEN

Descriptions

Channel n Enable control

0: Disable the PDMA channel n

1: Enable the PDMA channel n

Setting this bit will enable a software or hardware transfer request on the PDMA channel n. It is automatically cleared by hardware when a transfer has completed with the auto-reload function being disabled. However, if the AUTORLn bit is set to 1 to enable the auto-reload function, this bit will be remain high to enable the

PDMA channel n function for the next transfer request instead of automatically being cleared by hardware after a transfer has finished.

PDMA Channel n Source Address Register – PDMACHnSADR, n = 0 ~ 5

This register specifies the source address of the PDMA channel n.

Offset: 0x004 (0), 0x01C (1), 0x034 (2), 0x04C (3), 0x064 (4), 0x07C (5)


31 30 29 28 27

SADRn

26 25 24


23 22 21 20 19

SADRn

18 17 16


15 14 13 12 11

SADRn

10 9 8


7 6 5 4 3

SADRn

2 1 0


Bits

[31:0]

Field

SADRn

Descriptions

Channel n Source Address

The register is used to specify the 32-bit source address of the PDMA channel n.

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HT32F5828

Cortex ® -M0+ MCU

PDMA Channel n Destination Address Register – PDMACHnDADR, n = 0 ~ 5

This register specifies the destination address of the PDMA channel n.

Offset: 0x008 (0), 0x020 (1), 0x038 (2), 0x050 (3), 0x068 (4), 0x080 (5)


31 30 29 28 27

DADRn

26 25 24


23 22 21 20 19

DADRn

18 17 16


15 14 13 12 11

DADRn

10 9 8


7 6 5 4 3 2 1 0

DADRn


Bits

[31:0]

Field

DADRn

Descriptions

Channel n Destination Address

The register is used to specify the 32-bit destination address of the PDMA channel n.

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HT32F5828

Cortex ® -M0+ MCU

PDMA Channel n Transfer Size Register – PDMACHnTSR, n = 0 ~ 5

This register is used to specify the block transaction count and block transaction length.

Offset: 0x010 (0), 0x028 (1), 0x040 (2), 0x058 (3), 0x070 (4), 0x088 (5)


31 30 29 28 27

BLKCNTn

26 25 24


23 22 21 20 19

BLKCNTn

18 17 16


15 14 13 12 11

Reserved

10 9 8

Type/Reset

7 6 5 4 3

BLKLENn

2 1 0


Bits

[31:16]

[7:0]


BLKCNTn Channel n Block Transaction Count

BLKCNTn represents the number of block transactions for a channel n complete transfer. The capacity of a complete transfer is the product of the BLKCNTn and

BLKLENn values. The maximum BLKCNTn value is 65,535.

BLKLENn Channel n Block Length

The BLKLENn represents the length of a data block. The data width is defined by the

DWIDTHn field in the PDMACHnCR register. The maximum BLKLENn value is 255.

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Cortex ® -M0+ MCU

PDMA Channel n Current Transfer Size Register – PDMACHnCTSR, n = 0 ~ 5

This register is used to indicate the current block transaction count.

Offset: 0x014 (0), 0x02C (1), 0x044 (2), 0x05C (3), 0x074 (4), 0x08C (5)


31 30 29 28 27

CBLKCNTn

26 25 24


23 22 21 20 19

CBLKCNTn

18 17 16


15 14 13 12 11

Reserved

10 9 8

Type/Reset

7 6 5 4 3

Reserved

2 1 0

Type/Reset

Bits

[31:16]


CBLKCNTn Channel n Current Block Count

The CBLKCNTn field is a 16-bit read-only value indicating the number of data blocks that remain to be transferred. After a data block has transferred completely, the

CBLKCNTn value will be decreased by 1. Writing a new value to the BLKCNTn field in the PDMACHnTSR register will update the CBLKCNTn field value.

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HT32F5828

Cortex ® -M0+ MCU

PDMA Interrupt Status Register – PDMAISR

This register is used to indicate the corresponding interrupt status of the PDMA channel 0 ~ 5.

Offset: 0x120


Type/Reset

31 30 29 28 27 26 25 24

Reserved TEISTA5 TCISTA5 HTISTA5 BEISTA5 GEISTA5 TEISTA4


23 22 21 20 19 18 17 16

TCISTA4 HTISTA4 BEISTA4 GEISTA4 TEISTA3 TCISTA3 HTISTA3 BEISTA3


15 14 13 12 11 10 9 8

GEISTA3 TEISTA2 TCISTA2 HTISTA2 BEISTA2 GEISTA2 TEISTA1 TCISTA1


7 6 5 4 3 2 1 0

HTISTA1 BEISTA1 GEISTA1 TEISTA0 TCISTA0 HTISTA0 BEISTA0 GEISTA0


Bits

[29], [24],

[19], [14],

[9], [4]

Field

TEISTAn

[28], [23],

[18], [13],

[8], [3]

TCISTAn

[27], [22],

[17], [12],

[7], [2]

HTISTAn

[26], [21],

[16], [11],

[6], [1]

BEISTAn

Descriptions

Channel n Transfer Error Interrupt Status (n = 0 ~ 5)

0: No Transfer Error occurs

1: Transfer Error occurs

This bit is set by hardware and is cleared by writing a “1” into the corresponding interrupt status clear bit in the PDMAISCR register. A Transfer error will occur when the PDMA accesses a system reserved address space or when the PDMA receives a request but the corresponding transfer capacity is equal to zero.

Channel n Transfer Complete Interrupt Status (n = 0 ~ 5)

0: No Transfer Completion Occurs

1: Transfer Completion Occurs

This bit is set by hardware and is cleared by writing a “1” into the corresponding interrupt status clear bit in the PDMAISCR register. The Transfer Completion event will occur when the PDMA has completed a data transfer task.

Channel n Half Transfer Interrupt Status (n = 0 ~ 5)

0: No Half Transfer Event Occurs

1: Half Transfer Event Occurs

This bit is set by hardware and is cleared by writing a “1” into the corresponding interrupt status clear bit in the PDMAISCR register. A Half Transfer event will occur when the PDMA has completed half of the data transfer task.

Channel n Block Transaction End Interrupt Status (n = 0 ~ 5)

0: No Block Transaction End Event Occurs

1: Block Transaction End Event Occurs

This bit is set by hardware and is cleared by writing a “1” into the corresponding interrupt status clear bit in the PDMAISCR register. A Block Transaction End event will occur when the PDMA completes a data block transaction task.

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[25], [20],

[15], [10],

[5], [0]

Field

GEISTAn

Descriptions

Channel n Global Transfer Interrupt Status (n = 0 ~ 5)

0: No TE, TC, HT or BE event occurs

1: TE, TC, HT, or BE event occurs

This bit is set by hardware and is cleared by writing a “1” into the corresponding interrupt status clear bit, GEICLRn, in the PDMAISCR register. A Global Transfer

Event will occur if any of the BE, HT, TC and TE events occurs. Also clearing any of the BE, HT, TC and TE event interrupt flags will clear the GE interrupt flag. Note that if a “1” is written into the GEICLRn bit in the PDMAISCR register to clear the GE interrupt flag, the BE, HT, TC and TE event interrupt flags will also be cleared to 0 together with the GE interrupt status flag.

PDMA Interrupt Status Clear Register – PDMAISCR

This register is used to clear the corresponding interrupt status bits in the PDMAISR Register.

Offset: 0x128


Type/Reset

31 30 29 28 27 26 25 24

Reserved TEICLR5 TCICLR5 HTICLR5 BEICLR5 GEICLR5 TEICLR4

WC 0 WC 0 WC 0 WC 0 WC 0 WC 0

23 22 21 20 19 18 17 16

TCICLR4 HTICLR4 BEICLR4 GEICLR4 TEICLR3 TCICLR3 HTICLR3 BEICLR3


15 14 13 12 11 10 9 8

GEICLR3 TEICLR2 TCICLR2 HTICLR2 BEICLR2 GEICLR2 TEICLR1 TCICLR1


7 6 5 4 3 2 1 0

HTICLR1 BEICLR1 GEICLR1 TEICLR0 TCICLR0 HTICLR0 BEICLR0 GEICLR0


Bits

[29], [24],

[19], [14],

[9], [4]

[28], [23],

[18], [13],

[8], [3]

[27], [22],

[17], [12],

[7], [2]

Field

TEICLRn

TCICLRn

Descriptions

Channel n Transfer Error Interrupt Status Clear (n = 0 ~ 5)

0: No Operation

1: Clear the corresponding TEISTAn bit in the PDMAISR register

Writing a “1” into the TEICLRn bit will clear the TEISTAn status bit in the PDMAISR register. This bit will be automatically cleared to 0 after a “1” is written.

Channel n Transfer Complete Interrupt Status Clear (n = 0 ~ 5)

0: No Operation

1: Clear the corresponding TCISTAn bit in the PDMAISR register

Writing a “1” into the TCICLRn bit will clear the TCISTAn status bit in the PDMAISR register. This bit will be automatically cleared to 0 after a “1” is written.

HTRICLRn Channel n Half Transfer Interrupt Status Clear (n = 0 ~ 5)

0: No Operation

1: Clear the corresponding HTISTAn bit in the PDMAISR register

Writing a “1” into the HTRICLRn bit will clear the HTISTAn status bit in the PDMAISR register. This bit will be automatically cleared to 0 after a “1” is written.

Rev. 1.00 591 of 637 December 28, 2020

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HT32F5828

Cortex ® -M0+ MCU

Bits

[26], [21],

[16], [11],

[6], [1]

Field

BEICLRn

[25], [20],

[15], [10],

[5], [0]

GEICLRn

Descriptions

Channel n Block Transaction End Interrupt Status Clear (n = 0 ~ 5)

0: No Operation

1: Clear the corresponding BEISTAn bit in the PDMAISR register

Writing a “1” into the BEICLRn bit will clear the BEISTAn status bit in the PDMAISR register. This bit will automatically cleared to 0 after a data “1” is written.

Channel n Global Transfer Event Interrupt Status Clear (n = 0 ~ 5)

0: No Operation

1: Clear the TEISTAn, TCISTAn, HTISTAn, BEISTAn and GEISTAn bits in the

PDMAISR register

Writing a “1” into the GEICLRn bit will clear the GEISTAn status bit together with the

TEISTAn, TCISTAn, HTISTAn and BEISTAn bits in the PDMAISR register. This bit will be automatically cleared to 0 after a “1” is written.

PDMA Interrupt Enable Register – PDMAIER

This register is used to enable or disable the related interrupts of the PDMA channel 0 ~ 5.

Offset: 0x130


Type/Reset

31

23

TCIE4

30

Reserved

22

HTIE4

29

TEIE5

21

BEIE4

28

TCIE5

20

GEIE4

27

HTIE5

19

TEIE3

26

BEIE5

18

TCIE3

25

GEIE5

17

HTIE3

24

TEIE4


16

BEIE3


15

GEIE3

14

TEIE2

13

TCIE2

12

HTIE2

11

BEIE2

10

GEIE2

9

TEIE1

8

TCIE1


7

HTIE1

6

BEIE1

5

GEIE1

4

TEIE0

3

TCIE0

2

HTIE0

1

BEIE0

0

GEIE0


Bits

[29], [24],

[19], [14],

[9], [4]

[28], [23],

[18], [13],

[8], [3]

[27], [22],

[17], [12],

[7], [2]

Field

TEIEn

TCIEn

HTIEn

Descriptions

Channel n Transfer Error Interrupt Enable control (n = 0 ~ 5)

0: Transfer Error interrupt is disabled

1: Transfer Error interrupt is enabled

This bit is set and cleared by software.

Channel n Transfer Complete Interrupt Enable control (n = 0 ~ 5)

0: Transfer Completion interrupt is disabled

1: Transfer Completion interrupt is enabled


Channel n Half Transfer Interrupt Enable control (n = 0 ~ 5)

0: Half Transfer interrupt is disabled

1: Half Transfer interrupt is enabled


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HT32F5828

Cortex ® -M0+ MCU

Bits

[26], [21],

[16], [11],

[6], [1]

[25], [20],

[15], [10],

[5], [0]

Field

BEIEn

GEIEn

Descriptions

Channel n Block Transaction End Interrupt Enable control (n = 0 ~ 5)

0: Block Transaction End interrupt is disabled

1: Block Transaction End interrupt is enabled


Channel n Global Transfer Event Interrupt Enable control (n = 0 ~ 5)

0: Global Transfer Event interrupt is disabled

1: Global Transfer Event interrupt is enabled


Rev. 1.00 593 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

30

Divider (DIV)

Introduction

In order to enhance MCU performance, a divider is implemented within the device.

Features

▆

▆

Signed/unsigned 32-bit divider

Operation in 8 clock cycles, Load in 1 clock cycle

▆

Division by zero error flag


The division and modulus functions of the truncated division are related in the following way:

A / B = Q…R

Where “A” is Dividend, “B” is Divisor, “Q” is Quotient and “R” is Remainder. Divider requires a software trigger start signal by controlling the START bit in the CR register. The divider calculation complete flag will be set to 1 after 8 clock cycles, however, if the divisor register data is zero during the calculation, the division by zero error flag will be set to 1.

32-bit Divisor

32-bit Dividend

S/W Trigger

Figure 203. Divider Functional Diagram

32-bit / 32-bit

Divider

32-bit Quotient

32-bit Remainder

Division by Zero Error Flag

Calculation Complete Flag

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HT32F5828

Cortex ® -M0+ MCU

Register Map

The following table shows the DIV registers and reset values.

Table 77. DIV Register Map

Register Offset

CR 0x000

DDR

DSR

0x004

0x008

QTR

RMR

0x00C

0x010

Description

Divider Control Register

Dividend Data Register

Divisor Data Register

Quotient Data Register

Remainder Data Register

Reset Value

0x0000_0008

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000


Divider Control Register – CR

This register contains the divider calculation complete flag, division by zero error flag and the calculation start control bit.

Offset: 0x000


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11

Reserved

10 9 8

3

COM

RO 1 RO

2

ZEF

0

1 0

Reserved START

RW 0

Bits

[3]

[2]

[0]

Field

COM

ZEF

START

Descriptions

Calculation Complete Flag

0: Data are invalid

1: New data are valid

When this bit is set to 1 by hardware, it indicates that the divider calculation is completed and data are valid. This bit is cleared to 0 by hardware after the calculation start.

Division By Zero Error Flag

0: Divisor is not zero

1: Divisor is zero

This bit is cleared to 0 by hardware after the calculation start.

Calculation Start Control Bit

0: No operation

1: Start the divider calculation

Writing 1 to this bit will start the divider calculation.

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Dividend Data Register – DDR

The register contains the dividend of the divider.

Offset: 0x004


31 30 29 28 27

DDR

26 25 24


23 22 21 20 19

DDR

18 17 16


15 14 13 12 11

DDR

10 9 8


7 6 5 4 3 2 1 0

DDR


Bits

[31:0]

Field

DDR

Descriptions

This bit field is used to specify the dividend of the divider calculation.

Divisor Data Register – DSR

The register contains the divisor of the divider.

Offset: 0x008


31 30 29 28 27

DSR

26 25 24


23 22 21 20 19 18 17 16

DSR


15 14 13 12 11

DSR

10 9 8


7 6 5 4 3 2 1 0

DSR


Bits

[31:0]

Field

DSR

Descriptions

This bit field is used to specify the divisor of the divider calculation.

Rev. 1.00 596 of 637 December 28, 2020

32-Bit Arm ®

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Cortex ® -M0+ MCU

Quotient Data Register – QTR

The register contains the quotient of the divider calculation result.

Offset: 0x00C


31 30 29 28 27

QTR

26 25 24


23 22 21 20 19

QTR

18 17 16


15 14 13 12 11

QTR

10 9 8


7 6 5 4 3 2 1 0

QTR


Bits

[31:0]

Field

QTR

Descriptions

This bit field is used to store the queotient of the divider calculation result.

Remainder Data Register – RMR

The register contains the remainder of the divider calculation result.

Offset: 0x010


31 30 29 28 27

RMR

26 25 24


23 22 21 20 19 18 17 16

RMR


15 14 13 12 11

RMR

10 9 8


7 6 5 4 3 2 1 0

RMR


Bits

[31:0]

Field

RMR

Descriptions

This bit field is used to store the remainder of the divider calculation result.

Rev. 1.00 597 of 637 December 28, 2020

32-Bit Arm ®

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31

Liquid Crystal Display Controller (LCD)

Introduction

The LCD controller is a digital controller/driver for monochrome passive liquid crystal displays with up to 8 common terminals and up to 37 segment terminals to drive 148 (4 commons × 37 segments) or 264 (8 commons × 33 segments) LCD picture elements (pixels). The exact number of terminals depends on the device pinout.

Each segment consists of a layer of liquid crystal molecules aligned between two electrodes. When a voltage greater than a threshold voltage is applied across the liquid crystal, the segment becomes visible.

An integrated charge pump function can be enabled to provide the LCD glass with higher voltage than the system voltage. The LCD display segment will degrade if the applied voltage has a DCcomponent. It is the average voltage generated by the LCD driver applied to the LCD segment that should be considered. If the applied root-mean-square (RMS) voltage is lower than the segment threshold voltage, the LCD segment will be clear, otherwise it will be dark.

APB Bus

CK_LSI

CK_LSE

CK_HSI

CK_HSE

LCDSRC[1:0]

LCDCPS[2:0]

÷ 1/2/4/8/16

( In CKCU IP)

CK_LCD

LCDPS[3:0]

PCLK_LCD

CK_LCD

PCLK_LCD

PCLK_LCD

Frequency Generator

16-bit prescaler

LCD Register LCDDIV[3:0]

MUX

CK_PS

Divide by 16 to 31

Interrupt

CK_DIV

COM0

LCD RAM

LCD Register

TYPE

STATIC

LCDPR

LCDEN

Pulse

Generator

HDEN

BIAS[1:0]

CPVS[2:0]

SEG

Driver

SEG[36:0]

37

READY

Contrast

Controller

Charge Pump

Resistor

Ladders

COM

Driver

COM[3:0]

COM[7:4]

COM3

SEG

COM

MUX

SEG[36:33]

4

SEG[32:0]

33

V

SS

1/3 ~ 1/4 V

LCD

2/3 ~ 3/4 V

LCD

1/2 V

LCD

V

LCD

SEG0

Analog

Switch

Array

SEG32

SEG33/

COM4

SEG34/

COM5

SEG35/

COM6

SEG36/

COM7

Figure 204. LCD Controller Block Diagram

Rev. 1.00 598 of 637 December 28, 2020

32-Bit Arm ®

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Features

▆

▆

▆

▆

▆

▆

▆

▆

▆

▆

▆

LCD Driver function with Static, 1/2, 1/3, 1/4, 1/6 and 1/8 duty

LCD Driver function with Static, 1/2, 1/3 or 1/4 bias

Supports R type

LCD clock source can be selected from the LSI (32 kHz), LSE (32 kHz) or a clock ratio of the

HSI or HSE

Contains three embedded LCD bias reference resistor ladders

Double buffered memory

Software selectable charge pump voltage

The contrast can be adjusted using two different methods:

● When using the charge pump, the software can adjust the maximum output voltage VLCD

● Programmable dead time between frames – up to 7/2 phase periods for type A waveforms and

7 phase periods for type B waveforms

Software selectable waveform type: type A or type B waveform

LCD frame interrupt

Blink capability: Up to 1, 2, 3, 4, 6, 8 or all pixels which can be programmed to blink


Frequency Generator

The frequency generator can generate various LCD frame rates starting from an LCD input clock frequency, CK_LCD. The CK_LCD source can be chosen from the 32.768 kHz Low Speed

External RC (LSE), the 32 kHz Low Speed Internal RC (LSI) or a clock ratio of the HSI or HSE by configuring bits LCDSRC[1:0] in the GCFGR register in the CKCU IP. The LCDCPS[2:0] bits in the APBCFGR register in CKCU will select either the HSI or HSE divided by 1, 2 , 4, 8 or 16.

The input clock, CK_LCD, can be divided by any value from 1 to 2 15 × 31. The LCDPS[3:0] bits in the LCDFCR register, is used to select the CK_LCD divided ratio by 2 LCDPS[3:0] . The LCDDIV[3:0] bits in the LCDFCR register, can be used to divide the clock further by 16 to 31. The output of the frequency generator block is f

CK_DIV

which forms the time base for the entire LCD controller.

The output clock frequency f

CK_PS is: f

CK_PS

= f

CK_LCD

/ 2 LCDPS

And the relation between the frequency generator input clock frequency, f

CK_LCD clock frequency f

CK_DIV

is:

, and its output f

CK_DIV

= f

CK_LCD

/ [2 LCDPS × (16 + LCDDIV)]

The frame frequency, f frame

, is obtained by multiplying f

CK_DIV

with the duty: f frame

= f

CK_DIV

× duty

The frame frequency is often selected to be within a range of 30 Hz to 100 Hz. A dedicated blink prescaler selects the blink frequency. This frequency is defined as: f

BLINK

= f frame

/ 2 (BLINKF+3) , BLINKF[2:0] = 0, 1, 2, … , 7

Rev. 1.00 599 of 637 December 28, 2020

32-Bit Arm ®

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Table 78. Frame Rate Calculation Example – CK_LCD 32 kHz, Frame Rate 30 Hz

CK_LCD

32768 Hz

32768 Hz

LCDPS

3

3 f

CK_PS

4096 Hz

4096 Hz

LCDDIV

1

6 f

CK_DIV

240.94 Hz

186.18 Hz

Duty

1/8

1/6 f frame

30.12 Hz

31.03 Hz

32768 Hz

32768 Hz

32768 Hz

32768 Hz

4

4

5

6

2048 Hz

2048 Hz

1024 Hz

512 Hz

1

6

1

1

120.47 Hz

93.09 Hz

60.24 Hz

30.12 Hz

1/4

1/3

1/2 static

30.12 Hz

31.03 Hz

30.12 Hz

30.12 Hz


CK_LCD LCDPS f

CK_PS

LCDDIV f

CK_DIV

Duty f frame

32768 Hz

32768 Hz

32768 Hz

2

2

3

8192 Hz

8192 Hz

4096 Hz

1

6

1

481.88 Hz

372.36 Hz

240.94 Hz

1/8

1/6

1/4

60.24 Hz

62.06 Hz

60.24 Hz

32768 Hz

32768 Hz

32768 Hz

3

4

5

4096 Hz

2048 Hz

1024 Hz

6

1

1

186.18 Hz

120.47 Hz

60.24 Hz

1/3

1/2 static

62.06 Hz

60.24 Hz

60.24 Hz


CK_LCD

32768 Hz

LCDPS

1 f

CK_PS

16384 Hz

LCDDIV

4 f

CK_DIV

819.20 Hz

Duty

1/8 f frame

102.40 Hz

32768 Hz

32768 Hz

32768 Hz

32768 Hz

32768 Hz

1

2

2

3

4

16384 Hz

8192 Hz

8192 Hz

4096 Hz

2048 Hz

11

4

11

4

4

606.80 Hz

409.60 Hz

303.41 Hz

204.80 Hz

102.40 Hz

1/6

1/4

1/3

1/2 static

101.14

102.40 Hz

101.14 Hz

102.40 Hz

102.40 Hz

Table 81. Frame Rate Calculation Example – CK_LCD 1 MHz, Frame Rate 30 Hz

CK_LCD

1 MHz

1 MHz

LCDPS

8

8 f

CK_PS

3906.25 Hz

3906.25 Hz

LCDDIV

0

5 f

CK_DIV

244.14 Hz

186.01 Hz

Duty

1/8

1/6 f frame

30.52 Hz

31.00 Hz

1 MHz

1 MHz

1 MHz

1 MHz

9

9

10

11

1953.13 Hz

1953.13 Hz

976.56 Hz

488.28 Hz

0

5

0

0

122.07 Hz

93.00 Hz

61.04 Hz

30.52 Hz

1/4

1/3

1/2 static

30.52 Hz

31.00 Hz

30.52 Hz

30.52 Hz

Table 82. Frame Rate Calculation Example – CK_LCD 1 MHz, Frame Rate 60 Hz

CK_LCD LCDPS f

CK_PS

LCDDIV f

CK_DIV

Duty f frame

1 MHz

1 MHz

1 MHz

7

7

8

7812.5 Hz

7812.5 Hz

3906.25 Hz

0

5

0

488.28 Hz

372.02 Hz

244.14 Hz

1/8

1/6

1/4

61.04 Hz

62.00 Hz

61.04 Hz

1 MHz

1 MHz

1 MHz

8

9

10

3906.25 Hz

1953.13 Hz

976.56 Hz

5

0

0

186.01 Hz

122.07 Hz

61.04 Hz

1/3

1/2 static

62.00 Hz

61.04 Hz

61.04 Hz

Rev. 1.00 600 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Table 83. Frame Rate Calculation Example – CK_LCD 1 MHz, frame rate 100 Hz

CK_LCD

1 MHz

1 MHz

LCDPS

6

6 f

CK_PS

15625 Hz

15625 Hz

LCDDIV

3

10 f

CK_DIV

822.37 Hz

600.96 Hz

Duty

1/8

1/6 f frame

102.80 Hz

100.16 Hz

1 MHz

1 MHz

1 MHz

1 MHz

7

7

8

9

7812.5 Hz

7812.5 Hz

3906.25 Hz

1953.13 Hz

3

10

3

3

411.18 Hz

300.48 Hz

205.59 Hz

102.80 Hz

1/4

1/3

1/2 static

102.80 Hz

100.16 Hz

102.80 Hz

102.80 Hz

Common and Segment Driver

The Common and Segment signals are generated by the common and segment driver block. LCDs can be driven by two types of waveforms, type A and type B. The LCD waveform type is selected by the TYPE bit in the LCDCR register. The Common signal has its max amplitude V is:

LCD

or V

SS only in the corresponding phase of a frame cycle, while during other phases, the signal amplitude

▆

▆

▆

1/2 V

LCD

for 1/2 bias

1/3 V

LCD

or 2/3 V

LCD

for 1/3 bias

1/4 V

LCD

or 3/4 V

LCD

for 1/4 bias

The bias mode can be selected to be 1/2, 1/3 or 1/4 using the BIAS bits in the LCDCR register.

The frame period in type A waveforms is equal to one odd or one even frame period in type B. The phase periods in type A and type B waveforms are equal (type A phase 0 = type B phase 0), and the phase period is equal to 1/ f

CK_DIV

:

Phase 0 = Phase 1 = Phase 2 = 1/ f

CK_DIV

Type A Waveforms

1 frame

Odd frame

Type B Waveforms

Even frame

1 frame

(odd frame)

COM

SEG

COM - SEG

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

- 1/3 V

LCD

- 2/3 V

LCD

- V

LCD

Phase

0

Phase

1

Phase

2

Phase

0

Phase

1

Phase

2

Phase

0

Phase

1

Phase

2

Phase

0

Phase

1

Phase

2

Figure 205. Type A vs Type B Waveform – 1/3 Bias, 1/3 Duty

Rev. 1.00 601 of 637 December 28, 2020

32-Bit Arm ®

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COM0

Depending upon the condition of the DTYC[2:0] bits in the LCDCR register, the COM signals are generated with a static duty, 1/2 duty, 1/3 duty, 1/4 duty, 1/6 duty or 1/8 duty. COM[n] (n = 0 to 7) is active during phase n in each frame. In type A waveforms, the COM pin is driven to V then to V and to V

SS

SS

within one phase. In type B waveforms, the COM pin is driven to V

LCD

in odd frames

in even frames.

LCD

and

When the LCDEN bit is cleared, all segment and common lines are pulled down to V

SS

.

COM0

SEG0

SEG1

COM0 - SEG0

COM0 - SEG1

V

LCD

V

SS

V

LCD

V

SS

V

LCD

V

SS

V

LCD

V

SS

- V

LCD

V

SS

Figure 206. Static Waveforms

Rev. 1.00 602 of 637 December 28, 2020

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COM1

COM0

COM0

COM1

SEG0

SEG1

COM0 - SEG0

(selected waveform)

COM0 – SEG1

(non-selected waveform)

Figure 207. 1/2 Duty, 1/2 Bias, Type A Waveforms

1 frame

V

LCD

1/2 V

LCD

V

SS

V

SS

V

LCD

1/2 V

LCD

V

SS

- 1/2 V

LCD

- V

LCD

V

LCD

1/2 V

LCD

V

SS

- 1/2 V

LCD

- V

LCD

V

LCD

1/2 V

LCD

V

SS

V

LCD

1/2 V

LCD

V

SS

V

LCD

1/2 V

LCD

Rev. 1.00 603 of 637 December 28, 2020

32-Bit Arm ®

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Cortex ® -M0+ MCU

COM1

COM0

COM0

COM1

SEG0

SEG1

COM0 - SEG0

(selected waveform)

COM0 – SEG1



Rev. 1.00 604 of 637

1 frame

December 28, 2020

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

- 1/3 V

LCD

- 2/3 V

LCD

- V

LCD

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

- 1/3 V

LCD

- 2/3 V

LCD

- V

LCD

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

COM2

COM1

COM0

COM2

SEG0

COM0

COM1

SEG1

COM0 - SEG0


COM0 – SEG1

(selected waveform)


1 frame

Rev. 1.00 605 of 637 December 28, 2020

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

- 1/3 V

LCD

- 2/3 V

LCD

- V

LCD

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

- 1/3 V

LCD

- 2/3 V

LCD

- V

LCD

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

COM2

COM1

COM0

COM3

COM0

COM1

COM2

COM3

SEG0

SEG1

COM0 – SEG0

(selected waveform)

COM0 – SEG1


1 frame


Rev. 1.00 606 of 637

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

- 1/3 V

LCD

- 2/3 V

LCD

- V

LCD

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

- 1/3 V

LCD

- 2/3 V

LCD

- V

LCD

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

COM0

COM0

COM1

COM2

COM3

COM4

COM5

COM1

COM2

SEG0 SEG1

COM5

SEG0

COM0 – SEG0


COM1 – SEG0

(selected waveform)

1 frame

Figure 211. 1/6 Duty, 1/3 Bas, Type A Waveforms

Rev. 1.00 607 of 637

1/3 V

LCD

V

SS

- 1/3 V

LCD

- 2/3 V

LCD

- V

LCD

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

- 1/3 V

LCD

- 2/3 V

LCD

- V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

COM5

COM4

COM1

COM0

COM7

COM6

COM0

COM3

COM2 COM1

COM2

COM7

SEG0

COM0 – SEG0


COM1 – SEG0

(selected waveform)

1 frame


Rev. 1.00 608 of 637 December 28, 2020

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

-1/3 V

LCD

-2/3 V

LCD

-V

LCD

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

-1/3 V

LCD

-2/3 V

LCD

-V

LCD

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

COM5

COM4

COM1

COM0

COM7

COM6

COM0

COM2

COM3

COM1

COM2

COM7

SEG0

COM0 – SEG0


COM1 – SEG0

(selected waveform)

1 frame


V

LCD

3/4 V

LCD

2/4 V

LCD

1/4 V

LCD

V

SS

V

LCD

3/4 V

LCD

2/4 V

LCD

1/4 V

LCD

V

SS

V

LCD

3/4 V

LCD

2/4 V

LCD

1/4 V

LCD

V

SS

V

LCD

3/4 V

LCD

2/4 V

LCD

1/4 V

LCD

V

SS

V

LCD

3/4 V

2/4 V

1/4 V

V

SS

LCD

LCD

LCD

V

LCD

3/4 V

LCD

2/4 V

LCD

1/4 V

LCD

V

SS

- 1/4 V

LCD

- 2/4 V

LCD

- 3/4 V

LCD

- V

LCD

V

LCD

3/4 V

LCD

2/4 V

LCD

1/4 V

LCD

V

SS

- 1/4 V

LCD

- 2/4 V

LCD

- 3/4 V

LCD

- V

LCD

Rev. 1.00 609 of 637 December 28, 2020

32-Bit Arm ®

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LCD Drive Selection

The LCD bias voltages are driven by the resistive networks. The resistive networks, one with low value resistor (R

L

) and one with high value resistor (R

H

) are respectively used to increase the current during transitions and reduce power consumption in the static state. If the LCDEN bit is set, the EN switch is closed. When clearing the LCDEN bit in type A waveforms, the EN switch is open at the end of the frame. In type B waveforms, the EN switch is open at the end of the even frame in order to avoid a medium voltage level different from 0.

HDEN EN

HRLEN

V

LCD

3 R

L

R

L

3 R

H

3/4 × V

LCD

R

H

2/3 × V

LCD

V

LCDR1

2 R

L

2 R

H

1/2 × V

LCD

V

LCDR2

2 R

L

R

L

3 R

L

2 R

H

1/3 × V

LCD

R

H

1/4 × V

LCD

3 R

H

V

LCDR3

BIAS[1]

/STATIC

Figure 214. LCD Voltage Control

V

SS

Rev. 1.00 610 of 637 December 28, 2020

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High Drive Duration

The high drive duration bits, HDD[2:0], configure the time during which R

L

is enabled through the high drive enable switch, HDEN, when the levels of the common and segment lines change.

The low value resistor ladder can be reduced to half of its value by setting the half low resistor R

L enable bit, HRLEN. A short drive time will lead to lower power consumption but will also need a longer drive time to achieve the target contrast. In Figure 210, as the high drive duration HDD[2:0] is set to 3, the high drive duration is 3 × (1/f

CK_PS remaining time, HDEN is disabled by the hardware.

) during a single segment time. During the

▆

▆

▆

When HDEN=0, HDD[2:0]=0: HDEN switch is open and there is no high drive function.

When HDEN=0, HDD[2:0] have values other than 0, then the HDEN switch will be setup according to HDD[2:0] setup timing interval as shown below.

When HDEN=1, no matter what the value of HDD[2:0] is, the HDEN switch will always remain closed with the high drive function active.

Single Segment Time f

CK_PS

COUNT

HDD[2:0]

H00 H01 H02 H03 H04 H05 H06 H07

H3

High drive disable

(HDEN = 0)

High Drive

Duration

High drive enable

(HDEN = 1)

3/f

CK_PS

Figure 215. High Drive Duration

H00 H01

High drive enable

(HDEN = 1)

Dead Time

The LCD contrast can also be reduced by programming a dead time without modifying the frame rate. In the following figure, for type A waveforms, dead times are inserted between each frame.

For type B waveforms, dead times are inserted between the even and odd frames. During the dead time, the COM and SEG values are pulled down to V waveforms. The dead time duration is defined as follows:

SS

. The DEAD[2:0] bits can be used to program a time of up to 7/2 phase periods in type A waveforms and up to 7 periods in type B

Table 84. Dead Time Duration

DEAD[2:0]

Type A Waveforms

Phase Period Number b000 b001 b010 b011 b100 b101 b110 b111

0 1/2 2/2 3/2 4/2 5/2 6/2 7/2

Type B Waveforms

Phase Period Number

0 1 2 3 4 5 6 7

Rev. 1.00 611 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

1 frame

Type A Waveforms (DEAD[2:0] = 6)

Dead time

(3 phase periods)

COM

SEG

Odd frame

1 phase period 1/2 phase period

Type B Waveforms (DEAD[2:0] = 2)

Dead time

(2 phase periods)

Even frame

Odd frame

COM

SEG

1 phase period

Figure 216. Dead Time

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

Even frame

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

Rev. 1.00 612 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Double Buffer Memory

There are two levels of buffer memory. The first buffer level LCD RAM can be accessed by the application software through the APB interface. Once the LCD RAM is modified by the user program, the update display request flag, UDR, should be set to request the updated information to be moved to the second buffer level. This operation is implemented synchronously with the frame.

The LCD RAM is write-protected and the UDR flag will remain high until the update is completed.

Once the update is completed, the update display done flag, UDD, will be set and an interrupt will be generated if the UDDIE bit is set. The update will not occur (UDR = 1 and UDD = 0) until the display is enabled (LCDEN = 1).

LCD Low-power Modes

The LCD controller can be displayed in three power saving modes: Sleep, Deep-Sleep1,

Deep-Sleep2 modes. It can also be fully disabled to reduce the power consumption.

Table 85. LCD in Power Saving Modes

Mode

Sleep

Deep-Sleep1

Deep-Sleep2

Power-Down

LCD is active

LCD is active

LCD is active

LCD is inactive

Description

LCD Interrupts

There are two types of LCD interrupts: Start of Frame (SOF) and Update Display Done (UDD) interrupts. The SOF interrupt is executed if the SOFIE bit is set. The SOF flag is cleared by writing

1 to the SOFC bit. The LCD UDD interrupt is executed if the UDDIE bit is set. The UDD flag is cleared by writing 1 to the UDDC bit.

Table 86. LCD Interrupts

Interrupt Event

Start Of Frame – SOF

Update Display Done – UDD

Flag

SOF

UDD

Clearing Method Interrupt Enable Bit

Write SOFC = 1

Write UDDC = 1

SOFIE

UDDIE

Rev. 1.00 613 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Flowchart

START

Initialization

Enable AFIO, LCD clocks in CKCU

Configure LCD GPIO pins as alternate functions

Configure LCD controller according to the Display to be driven

Load the initial data to LCD RAM and set the UDR bit

Program desired frame rate (LCDPS[3:0] and LCDDIV[3:0])

Choose waveform type (TYPE bit)

Charge pump configuration (if charge pump is used)

Program charge pump voltage CPVS[2:0]

Set LCDPR bit

NO

Is charge pump ready?

(RDY = 1?)

YES

Enable the display (set LCDEN bit)

NO

Adjust contrast?

NO

Modify data?

NO

Change blink?

NO

Disable LCD

YES

Change LCDPS, LCDDIV, HDD, DEAD,HDEN or HRLEN

YES

YES

UDR=1?

NO

Modify the LCD RAM

Set UDR bit

YES

Change BLINK or BLINKF

YES

Disable the charge pump (clear LCDPR bit)

Disable the display (clear LCDEN)

NO

LCDENS = 0?

END

YES

Figure 217. Flowchart Example

Rev. 1.00 614 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Register Map

The following table shows the LCD registers and their reset values.

Table 87. LCD Register Map

Register

LCDCR

LCDFCR

LCDIER

LCDSR

LCDCLR

Offset

0x000

0x004

0x008

Description

LCD Control Register

LCD Frame Control Register

LCD Interrupt Enable Register

LCDRAM

0x00C

0x010

0x020

0x024

0x028

0x02C

0x030

0x034

0x038

0x03C

0x040

0x044

0x048

0x04C

0x050

0x054

0x058

0x05C

LCD Status Register

LCD Clear Register

LCD Display Memory COM0 (SEG31 to SEG0)
















Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

Rev. 1.00 615 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU


LCD Control Register – LCDCR

This register specifies the LCD control and the enable bits.

Offset: 0x000


Type/Reset

31 30 29 28

Reserved

27 26 25 24

MMASK

RW 0

16 23 22 21 20 19

Reserved

18 17

Type/Reset

15

HRLEN

14

DSTAO

13 12 11 10 9 8

Reserved MUXCOM7 MUXCOM6 MUXCOM5 MUXCOM4


7

TYPE

6 5

BIAS

4

RW 0 RW 0 RW 0 RW 0

3

DTYC

2 1

LCDPR

0

LCDEN


Bits

[24]

[15]

[14]

[11]

[10]

[9]

[8]

Field

MMASK

Descriptions

MCONT Signal Mask Timing Selection

0: Mask time 25 ns

1: Mask time 40 ns

This bit controls the mask signal timing to mask the COM and SEG switch transient state.

HRLEN Half of R

L

Value Enable

0: Disable

1: Enable

The value of R

L

resistors are divided by 2 if HRLEN = 1.

DSTAO /STATIC Switch Control during Dead time

0: /STATIC switch is closed

1: /STATIC switch is open

This bit is used to control that the /STATIC switch is open or closed during the dead time duration.

MUXCOM7 Mux SEG[36] Enable

0: Mux SEG[36]/COM[7] is selected as COM[7]

1: Mux SEG[36]/COM[7] is selected as SEG[36]










Rev. 1.00 616 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[7]

[6:5]

[4:2]

[1]

[0]

Field

TYPE

BIAS

DTYC

LCDPR

LCDEN

Descriptions

Waveform Type Selection

0: Type A waveform

1: Type B waveform

Bias Selection

00: Bias 1/4

01: Bias 1/2

10: Bias 1/3

11: STATIC

These bits determine the bias used. When this field is set to value 11, the STATIC waveform is selected.

Duty Selection

000: Static duty

001: 1/2 duty

010: 1/3 duty

011: 1/4 duty

100: 1/6 duty

101: 1/8 duty

110: Reserved

111: Reserved

These bits determine the duty cycle. Values “110” and “111” are forbidden.

LCD Power Selection

0: External source VLCD pin – charge pump is disabled

1: Internal source – charge pump is enabled

The charge pump is enabled when this bit is set and is otherwise disabled when this bit is cleared.

LCD Controller Enable

0: LCD Controller disabled

1: LCD Controller enabled

This bit is set by software to enable the LCD Controller. If it is cleared by software to turn off the LCD, the LCD display will not stop immediately until the current frame is finished. When the LCD is disabled all COM and SEG pins are driven to V

SS

.

Rev. 1.00 617 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

LCD Frame Control Register – LCDFCR

This register specifies the LCD frame control bits.

Offset: 0x004


Type/Reset

31 30 29 28

Reserved

27 26 25 24

LCDPS

RW 0 RW 0

23 22

LCDPS

21 20 19

LCDDIV

18 17 16

BLINK


15 8

DEAD


7 6 5 4 3 2 1 0

DEAD

14

BLINKF

13

HDD

12


11

CPVS

10

Reserved

9

HDEN

RW 0

Bits

[25:22]

[21:18]

[17:16]

[15:13]

Field

LCDPS

LCDDIV

BLINK

BLINKF

Descriptions

LCD 16-bit Prescaler

0000: f

0001: f

0010: f

...

1111: f

CK_PS

CK_PS

CK_PS

CK_PS

= f

= f

= f

= f

CK_LCD

(do not support type A)

CK_LCD

CK_LCD

CK_LCD

/2

/4

/32768

These bits are written by software to define the division factor of the 16-bit prescaler.

LCD Clock Divider

0000: f

0001: f

0010: f

...

1111: f

CK_DIV

CK_DIV

CK_DIV

CK_DIV

= f

= f

= f

= f

CK_PS

/16

CK_PS

CK_PS

CK_PS

/17

/18

/31

These bits are written by software to define the division factor of the LCDDIV divider.

Blink Mode Selection

00: Blink is disabled

01: Blink is enabled on SEG[0], COM[0] – 1 pixel

10: Blink is enabled on SEG[0], all COMs – up to 8 pixels depending on the programmed duty

11: Blink is enabled on all SEGs and all COMs – all pixels

In the LCD RAM, the pixel will only blink if it is set to 1.

Blink Frequency Selection

000: f frame

/8

001: f frame

010: f frame

011: f frame

100: f frame

101: f frame

110: f frame

111: f frame

/16

/32

/64

/128

/256

/512

/1024

Rev. 1.00 618 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[12:10]

[9:7]

[6:4]

[0]

Field

CPVS

DEAD

HDD

HDEN

Descriptions

Charge Pump Voltage Selection

000: 2.65 V

001: 2.75 V

010: 2.85 V

011: 2.95 V

100: 3.10 V

101: 3.25 V

110: 3.40 V

111: 3.55 V

These bits specify one of the V

LCD

maximum voltages independent of V

DD

.

Dead Time Duration

In type A waveforms:

000: No dead time

001: 1/2 phase period dead time


......


In type B waveforms:

000: No dead time

001: 1 phase period dead time


......


These bits are written by software to configure the length of the dead time between frames. During the dead time the COM and SEG voltage levels are held at 0 V to reduce the contrast without modifying the frame rate.

High Drive Duration

000: 0

001: 1/f

010: 2/f

CK_PS

011: 3/f

100: 4/f

CK_PS

CK_PS

CK_PS

101: 5/f

110: 6/f

CK_PS

CK_PS

111: 7/f

CK_PS

These bits are written by software to define the high drive duration in terms of CK_

PS clock pulses. A short pulse will lead to lower power consumption, but displays with high internal resistance may need a longer pulse to achieve a satisfactory contrast. For type A waveforms, when the segment voltage needs to change it will be managed by the high drive.

High Drive Enable

0: Permanent high drive disabled

1: Permanent high drive enabled

This bit is written by software to enable a low resistance divider. Displays with high internal resistance may need a longer drive time to achieve a satisfactory contrast.

This bit is useful in cases where some additional power consumption can be tolerated.

Rev. 1.00 619 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

LCD Interrupt Enable Register – LCDIER

This register contains the corresponding LCD interrupt enable control bit.

Offset: 0x008


31 30 29

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

Type/Reset

Bits

[1]

[0]

Field

UDDIE

SOFIE

Descriptions

Update Display Done Interrupt Enable

0: LCD Update Display Done interrupt disable

1: LCD Update Display Done interrupt enable


Start of Frame Interrupt Enable

0: LCD Start of Frame interrupt disable

1: LCD Start of Frame interrupt enable


26

18

10

2

25

17

9

24

16

8

1

UDDIE

0

SOFIE

RW 0 RW 0

Rev. 1.00 620 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

LCD Status Register – LCDSR

This register contains the relevant LCD controller status.

Offset: 0x00C


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

14 13 12 11

Reserved

10 9 8

6 5

Reserved FCRSF

4

RDY

3

UDD

2

UDR

1

SOF

0

LCDENS

RO 0 RO 0 RO 0 RW 0 RO 0 RO 0

Bits

[5]

[4]

[3]

[2]

Field

FCRSF

RDY

UDD

UDR

Descriptions

LCD Frame Control Register Synchronization Flag

0: LCD Frame Control Register is not synchronised yet

1: LCD Frame Control Register is synchronised

This bit is set by hardware each time the LCDFCR register is updated in the

LCDCLK domain. It is cleared by hardware when writing to the LCDFCR register.

Ready Flag

0: Not ready

1: Charge pump is enabled and ready to provide the correct voltage

This bit indicates the status of the charge pump. It is set and cleared by hardware and only valid when the LCDPR bit is set high. When the LCDPR bit is set low, the

RDY bit will be kept low.

Update Display Done

0: No event

1: Update Display Request done. A UDD interrupt is generated if the UDDIE bit in the LCDIER register is set.

This bit is set by hardware. It is cleared by writing 1 to the UDDC bit in the LCDCLR register.

Update Display Request

0: No effect

1: Update Display request

Each time the software modifies the LCD RAM it must set the UDR bit to transfer the updated data to the second level buffer. The UDR bit remains set until the end of the update.

Note that before modifying the LCD RAM, it is necessary to read UDR to confirm that the hardware has cleared it to 0 before writing to the LCD RAM.

Rev. 1.00 621 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[1]

[0]

Field

SOF

LCDENS

Descriptions

Start of Frame Flag

0: No event

1: Start of Frame event occurred. An LCD Start of Frame Interrupt is generated if the SOFIE bit is set.

This bit is set by hardware at the beginning of a new frame at the same time as the display data is updated. It is cleared by writing 1 to the SOFC bit in the LCDCLR register.

LCD Enabled Status

0: LCD Controller is disabled

1: LCD Controller is enabled

This bit is set and cleared by hardware. This bit is set immediately when the LCDEN bit goes from 0 to 1. On deactivation this bit reflects the real status of the LCD so it becomes 0 at the end of the last displayed frame.

LCD Status Clear Register – LCDSCR

This register contains the LCD status clear bits.

Offset: 0x010


31 30 29 28 27

Reserved

Type/Reset

23 22 21 20 19

Reserved

Type/Reset

15 14 13 12 11

Reserved

Type/Reset

7 6 5 4

Reserved

3

Type/Reset

Bits

[1]

[0]

Field

UDDC

SOFC

26

18

10

25

17

9

24

16

8

2 1

UDDC

0

SOFC

WC 0 WC 0

Descriptions

Update Display Done Clear

0: No effect

1: Clear UDD flag

This bit is written by software to clear the UDD flag in the LCDSR register.

Start of Frame Flag Clear

0: No effect

1: Clear SOF flag

This bit is written by software to clear the SOF flag in the LCDSR register.

Rev. 1.00 622 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

LCD RAM – LCDRAM

This register contains pixels.

Offset: 0x020 ~ 0x05C


31 30 29 28 27

SEG_DATA

26 25 24


23 22 21 20 19

SEG_DATA

18 17 16


15 14 13 12 11

SEG_DATA

10 9 8


7 6 5 4 3 2 1 0

SEG_DATA


Bits

[31:0]


SEG_DATA SEG_DATA[31:0]

0: Pixel inactive

1: Pixel active

Each bit corresponds to one pixel of the LCD display.

Table 88. LCDRAM Register Map

Offset

0x20

0x24

0x28

Register

LCDRAM

(COM0)

LCDRAM

0x44

0x48

0x4C

0x50

0x54

0x58

0x5C

0x2C

0x30

0x34

0x38

0x3C

0x40

(COM1)

LCDRAM

(COM2)

LCDRAM

(COM3)

LCDRAM

(COM4)

LCDRAM

(COM5)

LCDRAM

(COM6)

LCDRAM

(COM7)

Bit[31:5]

SEG31 to SEG0

Reserved

SEG31 to SEG0

Reserved

SEG31 to SEG0

Reserved

SEG31 to SEG0

Reserved

SEG31 to SEG0

Reserved

SEG31 to SEG0

Reserved

SEG31 to SEG0

Reserved

SEG31 to SEG0

Reserved

Bit[4:0]

SEG36 to SEG32

SEG36 to SEG32

SEG36 to SEG32

SEG36 to SEG32

SEG36 to SEG32

SEG36 to SEG32

SEG36 to SEG32

SEG36 to SEG32

Rev. 1.00 623 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

32

AES Encrypt/Decrypt Interface (AES)

Introduction

The AES core supports both encryption and decryption functions and supports 128-bit input data.

It should be noted that hardware does not pad out any input data bit, therefore users need to do pad action by software at first.

AES

Cryp

Core

Module

AES Ctrl / Status / DMA / INT

Registers

Key Register

Initial Vector Register

AES Buffer

4 × 32 bits

Swap

Figure 218. AES Block Diagram

Features

▆

▆

▆

▆

▆

▆

▆

Supports AES Encrypt / Decrypt functions

Supports AES ECB/CBC/CTR modes

Supports Key Size of 128 bits

Supports 4 words Initial Vector for CBC and CTR modes

4 × 32 bits AES data buffer – each IN and OUT FIFO capacity

Supports Word Data Swap function


AHB Bus

Rev. 1.00 624 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU


AES Mode Description

AES Electronic Codebook (AES-ECB) Mode

The 128-bit plaintext data comes from IN FIFO and will be sent to the AES core to do encryption operation after word swapping operation. The AES core uses a 128-bit key to process the encryption. After encryption, the AES core generates the ciphertext, which will be written into the

OUT FIFO after the word swapping operation.

IN FIFO

Plaintext

128

AES ECB

Encryption

SWAP

IN FIFO

Ciphertext

128

AES ECB

Decryption

SWAP

128

AES Core

Encryption

128

128

Key

128

AES Core

Decryption

128

128

Key

SWAP SWAP

128

OUT FIFO

Ciphertext

Figure 219. AES-ECB Mode

128

OUT FIFO

Plaintext

Rev. 1.00 625 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

AES Cipher Block Chaining (AES-CBC) Mode

During encryption in the CBC mode, each block of plaintext is XORed with the previous ciphertext block before being encrypted. The first initial vectors are initialized in the 1st encryption operation.

The plaintext after word swapping will be XORed with the initial vectors before encryption. When the encryption output data is pushed into the OUT FIFO, the initial vectors are updated by the encryption output data at the same time.

During decryption in the CBC mode, each block of plaintext is XORed with the previous ciphertext block after being decrypted. The first initial vectors are initialized in the 1st decryption operation.

The ciphertext after word swapping and decryption will be XORed with the initial vectors. When the XORed decryption output data is pushed into the OUT FIFO, the initial vectors are updated by the decryption input data at the same time for the next round ciphertext.

IN FIFO

Plaintext

128

AES CBC

Encryption

+

128

128

128

128

AES Core

Encryption

128

SWAP

IV0~3

Key

AHB Bus

SWAP

128

OUT FIFO

Ciphertext

Figure 220. AES-CBC Mode

When encryption output data is pushed into AES

Buffer, IV0~3 are updated by encryption output data at the same time

IN FIFO

Ciphertext

128

AES CBC

Decryption

128

AES Core

Decryption

128

+

128

128

128

SWAP

SWAP

Key

IV0~3

AHB Bus

128

OUT FIFO

Plaintext

When decryption output data is pushed into AES

Buffer, IV0~3 are updated by decryption input data at the same time

Rev. 1.00 626 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

AES Counter (AES-CTR) Mode

In the CTR mode, the initial vector counter value, after being increased by one, will be sent to the

AES core for encryption to generate ciphertext. The AES core uses the same AES direction setting in both encryption and decryption.

During encryption and decryption in the CTR mode, the IN FIFO data after word swapping is

XORed with the ciphertext. The XORed data is sent to the OUT FIFO after word swapping. The initial vector counter will be increased by one at the same time for the next round ciphertext.

SWAP

IN FIFO

Plaintext

128

AES CTR

Encryption

128

IV0~3

SWAP

AHB Bus

+1

+

128

128

128

AES Core

Encryption

128

OUT FIFO

Ciphertext

128

Key

When XORed output data is pushed into

AES buffer, IV0~3 are updated by IV0~3 + 1 at the same time

Figure 221. AES-CTR Mode

SWAP

IN FIFO

Ciphertext

128

AES CTR

Decryption

128

IV0~3

SWAP

AHB Bus

+1

128

+

128

128

AES Core

Decryption

128

128

Key

When XORed output data is pushed into

AES buffer, IV0~3 are updated by IV0~3 + 1 at the same time

OUT FIFO

Plaintext

AES Status

There are five status conditions in the AES for the user to monitor the AES situation. The

IFEMPTY bit will be set when the input FIFO is empty while the IFNFULL bit will be set when the input FIFO is not full. The OFNEMPTY bit will be set when there is data in the output FIFO.

The OFFULL bit will be set when the output FIFO is full. The BUSY bit will be set when the AES core is executing an encryption/decryption operation or the key is in expansion state.

AES PDMA Interface

The AES supports the 32 bits PDMA data transfer. When the IN FIFO is empty, the AES will send an IN FIFO request to the PDMA. When the OUT FIFO is full, the AES will send an OUT FIFO request to the PDMA.

Rev. 1.00 627 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

AES Interrupt

The IFINT request will be generated when the input FIFO is less than or equal to 1 AES block (4 ×

32 bits). The OFINT request will be generated when there is data in the AES buffer. When the

IFINT bit is set high, an AES interrupt will be generated if the IFINT interrupt is enabled and the

AES remains enabled. When the OFINT bit is set high, an AES interrupt can also be generated if the OFINT interrupt is enabled irrespective of the AES enable/disable condition.

AES_EN

IFINT

IFINTEN

OFINT

OFINTEN

Figure 222. AES Interrupt

AES_INT

AES Initial Vector

The initial vectors (IV0 ~ 3) are not used in the ECB mode. The initial vectors are initialized in the first block of AES input data in the CBC and CTR modes. After the first AES block of input data, the values of the initial vectors will be updated by hardware automatically for the next block of

AES input data. The initial vectors in the CTR mode contain nonce, initial vector and counter. The counter will be increased by 1 after every AES data block action.

Nonce ( 32 bits )

Initial Vector

( 64 bits )

Counter ( 32 bits )

IV0

IV1, 2

IV3

Figure 223. Initial Vector for CTR Mode

Rev. 1.00 628 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

AES Word Swap

The AES supports a word swap function. The swap action is performed between IN FIFO and

AES block data, it is also executed between the AES block data and OUT FIFO. If the word swap function is required, the SWAP bit in the AESCR register should be set high.

31 0

.

.

.

Word 3

Word 2

Word 1

Word 0

31 0

Word 0

Word 1

Word 2

Word 3

.

.

.

AES Block Data

SWAP = 0

127 96

Word 0

95 64

Word 1

63 32

Word 2

31 0

Word 3

Word 2 Word 1 Word 0 SWAP = 1

Figure 224. AES Word Swap Function

Word 3

Register Map

The following table shows the AES registers and reset values.

Table 89. AES Register Map

Register Offset

AESCR 0x000 AES Control Register

Description

AESSR

AESDMAR

AESISR

AESIER

0x004

0x008

0x00C

0x010

AESDINR 0x014

AESDOUTR 0x018

AESKEYR0 0x01C

AESKEYR1 0x020

AESKEYR2 0x024

AESKEYR3 0x028

AESIVR0

AESIVR1

AESIVR2

AESIVR3

0x03C

0x040

0x044

0x048

AES Status Register

AES DMA Register

AES Interrupt Status Register

AES Interrupt Enable Register

AES Data Input Register

AES Data Output Register

AES Key Register 0

AES Key Register 1

AES Key Register 2

AES Key Register 3

AES Initial Vector Register 0




Reset Value

0x0000_0200

0x0000_0003

0x0000_0000

0x0000_0001

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

Rev. 1.00 629 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU


AES Control Register – AESCR

This register specifies the AES control setting.

Offset: 0x000


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

Type/Reset

15

7

Reserved

14 13

Reserved

12 11 10

FFLUSH

9

ENDIAN

8

SWAP

6 5 4

KEYSIZE KEYSTART

3

RW 0 RW 1 RW 0

2

MODE

1

DIR

0

AESEN

RO 0 RO 0 RW 0 RW 0 RW 0 RW 0 RW 0

Bits

[10]

[9]

[8]

[6:5]

[4]

[3:2]

[1]

[0]

Field

FFLUSH

ENDIAN

Descriptions

AES IN/OUT FIFO Flush

0: No action

1: Flush FIFO

The bit is cleared to 0 by hardware automatically. The bit can be set only in the AES disable state.

Endian Selection

0: Big-endian

1: Little-endian

This setting will apply to IN/OUT FIFO data, KEY and IV.

SWAP AES Data Swap Function

0: No Swap

1: Word Swap

This setting will apply to IN/OUT FIFO data.

KEYSIZE AES Key Size

00: 128 bits

Others: Reserved

KEYSTART AES Key Start

0: Key doesn’t Start

1: Key Start

It is cleared to 0 by hardware automatically. The bit works when in the AES enable state.

MODE

DIR

AESEN

AES Function Mode

00: ECB mode

01: CBC mode

1x: CTR mode

AES Direction

0: Encryption

1: Decryption

AES Enable

0: AES is disabled

1: AES is enabled

Rev. 1.00 630 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

AES Status Register – AESSR

This register specifies the AES status.

Offset: 0x004


31 30 29

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

Reserved

21

13

5

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

12 11

Reserved

10 9 8

4

BUSY

3 2 1 0

OFFULL OFNEMPTY IFNFULL IFEMPTY

RO 0 RO 0 RO 0 RO 1 RO 1

Bits

[4]

[3]

[2]

[1]

[0]

Field

BUSY

OFFULL

Descriptions

Busy bit

0: AES is not busy

1: AES is busy

AES is busy when AES is executing the encryption/decryption operation or the key is in expansion state.

Output FIFO is Full

0: Output FIFO is not full

1: Output FIFO is full

OFNEMPTY Output FIFO is not Empty

0: Output FIFO is empty

1: Output FIFO is not empty

IFNFULL Input FIFO is not Full

0: Input FIFO is full

1: Input FIFO is not full

IFEMPTY Input FIFO is Empty

0: Input FIFO is not empty

1: Input FIFO is empty

Rev. 1.00 631 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

AES DMA Register – AESDMAR

This register specifies the DMA setting.

Offset: 0x008


31 30 29

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

Type/Reset

Bits

[1]

[0]


OFDMAEN Output FIFO DMA Enable

0: DMA is disabled

1: DMA is enabled

IFDMAEN Input FIFO DMA Enable

0: DMA is disabled

1: DMA is enabled

26

18

10

25

17

9

24

16

8

2 1 0

OFDMAEN IFDMAEN

RW 0 RW 0

Rev. 1.00 632 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

AES Interrupt Status Register – AESISR

The register specifies the interrupt status setting.

Offset: 0x00C


31 30 29

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

Type/Reset

Bits

[1]

[0]

Field

OFINT

IFINT

Descriptions

Output FIFO Interrupt Status

0: No Output FIFO Interrupt

1: Output FIFO Interrupt

Input FIFO interrupt Status

0: No Input FIFO Interrupt

1: Input FIFO Interrupt

26

18

10

25

17

9

24

16

8

2 1

OFINT

0

IFINT

RO 0 RO 1

Rev. 1.00 633 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

AES Interrupt Enable Register – AESIER

The register specifies the interrupt enable setting.

Offset: 0x010


31 30 29

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

Type/Reset

Bits

[1]

[0]

Field

OFINTEN

IFINTEN

Descriptions

Output FIFO Interrupt Enable bit



Input FIFO Interrupt Enable bit



26

18

10

25

17

9

24

16

8

2 1 0

OFINTEN IFINTEN

RW 0 RW 0

Rev. 1.00 634 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

AES DATA Input Register – AESDINR

The register specifies the data input setting.

Offset: 0x014


31 30 29 28 27

DIN

26 25 24


23 22 21 20 19

DIN

18 17 16


15 14 13 12 11

DIN

10 9 8


7 6 5 4 3 2 1 0

DIN


Bits

[31:0]

Field

DIN

Descriptions

AES DATA Input

0x0000_0000 ~ 0xFFFF_FFFF

AES DATA Output Register – AESDOUTR

The register specifies the data output setting.

Offset: 0x018


31 30 29 28 27

DOUT

26 25 24


23 22 21 20 19 18 17 16

DOUT


15 14 13 12 11

DOUT

10 9 8


7 6 5 4 3 2 1 0

DOUT


Bits

[31:0]

Field

DOUT

Descriptions

AES Data Output


Rev. 1.00 635 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

AES Key Register n – AESKEYRn, n = 0 ~ 3

The register specifies the data of Key data n.

Offset: 0x01C ~ 0x028


31 30 29 28 27

KeyData

26 25 24


23 22 21 20 19

KeyData

18 17 16


15 14 13 12 11

KeyData

10 9 8


7 6 5 4 3 2 1 0

KeyData


Bits

[31:0]

Field

KeyData

Descriptions

KeyData


AES Initial Vector Register n – AESIVRn, n = 0 ~ 3

The register specifies the data of Initial Vector data n.

Offset: 0x03C ~ 0x048


31 30 29 28 27

IVData

26 25 24


23 22 21 20 19 18 17 16

IVData


15 14 13 12 11

IVData

10 9 8


7 6 5 4 3 2 1 0

IVData


Bits

[31:0]

Field

IVData

Descriptions

Initial Vector Data


Rev. 1.00 636 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Copyright

©

2020 by HOLTEK SEMICONDUCTOR INC.

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.

holtek.com.

Rev. 1.00 637 of 637 December 28, 2020