Infineon SAK-TC1762-128F80HL AC Microcontroller Data Sheet

D a t a S h e e t , V 1 . 0 , A p r . 2 0 0 8

T C 1 7 6 2

3 2 - B i t S i n g l e - C h i p M i c r o c o n t r o l l e r

T r i C o r e

M i c r o c o n t r o l l e r s

Edition 2008-04

Published by

Infineon Technologies AG

81726 München, Germany

© Infineon Technologies AG 2008.

All Rights Reserved.

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of noninfringement of intellectual property rights of any third party.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies Office ( www.infineon.com

).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

D a t a S h e e t , V 1 . 0 , A p r . 2 0 0 8

T C 1 7 6 2

3 2 - B i t S i n g l e - C h i p M i c r o c o n t r o l l e r

T r i C o r e

M i c r o c o n t r o l l e r s

TC1762

Preliminary

42

54

91

102

106

33

35

41

TC1762 Data Sheet

Revision History: V1.0, 2008-04

Previous Version: V0.5 2007-03

Page Subjects (major changes since last revision)

7

8 ,

10

VSSOSC3 is deleted from the TC1762 Logic Symbol.

TDATA0 of Pin 17, TCLK0 of Pin 20, TCLK0 of Pin 74 and TDATA0 of Pin

77 are updated in the Pinning Diagram and Pin Definition and Functions

Table.

Transmit DMA request in Block Diagram of ASC Interfaces is updated.

Alternate output functions in block diagram of SSC interfaces are updated.

Programmable baud rate of the MLI is updated.

TDATA0 and TCLK0 of the block diagram of MLI interfaces are updated.

The description for WDT double reset detection is updated.

The power sequencing details is updated.

MLI timing, maximum operating frequency limit is extended, t31 is added.

Thermal resistance junction leads is updated.

Trademarks

TriCore® is a trademark of Infineon Technologies AG.

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?

Your feedback will help us to continuously improve the quality of this document.

Please send your proposal (including a reference to this document) to: [email protected]

Data Sheet V1.0, 2008-04

TC1762

Preliminary

Table of Contents

1

2

2.1

2.2

2.3

2.4

2.5

4

4.1

4.1.1

4.1.2

4.1.3

4.1.4

4.2

3.8

3.9

3.10

3.11

3.12

3.12.1

3.13

3.14

3.15

3.16

3.17

3.18

3.19

3.20

3.21

3.22

3.23

3

3.1

3.2

3.3

3.4

3.5

3.6

3.7


Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Pad Driver and Input Classes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

System Architecture and On-Chip Bus Systems . . . . . . . . . . . . . . . . . . . . .24

On-Chip Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Architectural Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Memory Protection System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

DMA Controller and Memory Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Asynchronous/Synchronous Serial Interfaces (ASC0, ASC1) . . . . . . . . . . .33

High-Speed Synchronous Serial Interface (SSC0) . . . . . . . . . . . . . . . . . . .35

Micro Second Bus Interface (MSC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

MultiCAN Controller (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Micro Link Serial Bus Interface (MLI0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

General Purpose Timer Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Functionality of GPTA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Analog-to-Digital Converter (ADC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Fast Analog-to-Digital Converter Unit (FADC) . . . . . . . . . . . . . . . . . . . . . . .49

System Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

System Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Power Management System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Clock Generation and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Identification Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . . .67

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Data Sheet 1 V1.0, 2008-04

TC1762

Preliminary

5

5.1

5.2

5.3

5.4

4.2.1

4.2.2

4.2.3

4.2.4

4.2.5

4.2.6

4.3

4.3.1

4.3.2

4.3.3

4.3.4

4.3.5

4.3.6

4.3.7

4.3.8

4.3.8.1

4.3.8.2

4.3.8.3


Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Analog to Digital Converter (ADC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Fast Analog to Digital Converter (FADC) . . . . . . . . . . . . . . . . . . . . . . . . .82

Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Output Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Power, Pad and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Debug Trace Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

Timing for JTAG Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

Micro Link Interface (MLI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .102

Micro Second Channel (MSC) Interface Timing . . . . . . . . . . . . . . . .104

Synchronous Serial Channel (SSC) Master Mode Timing . . . . . . . . .105

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

Data Sheet 2 V1.0, 2008-04

TC1762

Preliminary Summary of Features

1 Summary of Features

The TC1762 has the following features:

• High-performance 32-bit super-scaler TriCore v1.3 CPU with 4-stage pipeline

– Superior real-time performance

– Strong bit handling

– Fully integrated DSP capabilities

– Single precision Floating Point Unit (FPU)

– 66 or 80 MHz operation at full temperature range

• Multiple on-chip memories

– 32 Kbyte Local Data Memory (SRAM)

– 4 Kbyte Overlay Memory

– 8 Kbyte Scratch-Pad RAM (SPRAM)

– 8 Kbyte Instruction Cache (ICACHE)

– 1024 Kbyte Flash Memory

– 16 Kbyte Data Flash (2 Kbyte EEPROM emulation)

– 16 Kbyte Boot ROM

• 8-channel DMA Controller

• Fast-response interrupt system with 255 hardware priority arbitration levels serviced by CPU

• High-performance on-chip bus structure

– 64-bit Local Memory Bus (LMB) to Flash memory

– System Peripheral Bus (SPB) for interconnections of functional units

• Versatile on-chip Peripheral Units

– Two Asynchronous/Synchronous Serial Channels (ASCs) with baudrate generator, parity, framing and overrun error detection

– One High Speed Synchronous Serial Channel (SSC) with programmable data length and shift direction

– One Micro Second Bus (MSC) interface for serial port expansion to external power devices

– One high-speed Micro Link Interface (MLI) for serial inter-processor communication

– One MultiCAN Module with two CAN nodes and 64 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer

– One General Purpose Timer Array Module (GPTA) with a powerful set of digital signal filtering and timer functionality to realize autonomous and complex

Input/Output management

– One 16-channel Analog-to-Digital Converter unit (ADC) with selectable 8-bit, 10bit, or 12-bit, supporting 32 input channels

– One 2-channel Fast Analog-to-Digital Converter unit (FADC) with concatenated comb filters for hardware data reduction: supporting 10-bit resolution, with minimum conversion time of 262.5ns (@ 80 MHz) or 318.2ns (@ 66 MHz)

Data Sheet 3 V1.0, 2008-04

TC1762


• 32 analog input lines for ADC and FADC

• 81 digital general purpose I/O lines

• Digital I/O ports with 3.3 V capability

• On-chip debug support for OCDS Level 1 and 2 (CPU, DMA)

• Dedicated Emulation Device chip for multi-core debugging, tracing, and calibration via USB V1.1 interface available (TC1766ED)

• Power Management System

• Clock Generation Unit with PLL

• Core supply voltage of 1.5 V

• I/O voltage of 3.3 V

• Full automotive temperature range: -40° to +125°C

• PG-LQFP-176-2 package

Data Sheet 4 V1.0, 2008-04

TC1762


Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies:

• The derivative itself, i.e. its function set, the temperature range, and the supply voltage

• The package and the type of delivery

For the available ordering codes for the TC1762, please refer to the “Product Catalog

Microcontrollers” that summarizes all available microcontroller variants.

This document describes the derivatives of the device.The

Table 1-1 enumerates these

derivatives and summarizes the differences.

Table 1-1

Derivative

TC1762 Derivative Synopsis

SAK-TC1762-128F66HL

SAK-TC1762-128F80HL

Ambient Temperature Range

T

A

= -40 o

C to +125 o

C; 66 MHz operation frequency

T

A

= -40 o

C to +125 o

C; 80 MHz operation frequency

Data Sheet 5 V1.0, 2008-04

TC1762

Preliminary General Device Information

2 General Device Information

Chapter 2 provides the general information for the TC1762.

2.1

Block Diagram

Figure 2-1 shows the TC1762 block diagram.

PMI

8 KB SPRAM

8 KB ICACHE

PMU

16 KB BROM

1024 KB Pflash

16 KB DFlash

4 KB OVRAM

FPU

TriCore

(TC1.3M)

CPS

DMI

32 KB LDRAM

Local Memory Bus (LMB)

LFI Bridge

LBCU

Abbreviations:

ICACHE:

SPRAM:

LDRAM:

OVRAM:

BROM:

PFlash:

DFlash:

LMB:

SPB:

Instruction Cache

Scratch-Pad RAM

Local Data RAM

Overlay RAM

Boot ROM

Program Flash

Data Flash

Local Memory Bus

System Peripheral Bus

OCDS Debug

Interface/JTAG

ASC0

ASC1

GPTA

Ext.

Request

Unit

SCU

Multi CAN

(2 Nodes,

64 Buffer) f

FPI f

CPU

MSC0

STM

SBCU

Ports

DMA

8 ch.

SMIF

MLI0

Mem

Check

SSC0

ADC0

32 ch.

FADC

2 ch.

MCB06056

Figure 2-1 TC1762 Block Diagram

Data Sheet 6 V1.0, 2008-04

TC1762

General Device Information Preliminary

2.2

Logic Symbol

Figure 2-2 shows the TC1762 logic symbol.

General Control

MSC0 Control

ADC Analog Inputs

ADC/FADC Analog

Power Supply

Digital Circuitry

Power Supply

PORST

HDRST

NMI

BYPASS

TESTMODE

FCLP 0A

FCLN0

SOP0A

SON0

AN[35:0]

V

DDM

V

SSM

V

DDMF

V

SSMF

V

DDAF

V

SSAF

V

AREF0

V

AGND0

V

FAREF

V

FAGND

V

DDFL3

V

DD

V

DDP

V

SS

7

8

9

TC1762

Port 0 16-bit

Alternate Functions

GPTA, SCU

GPTA, ADC Port 1 15-bit

Port 2 14-bit SSC0, MLI0, GPTA , MSC0

Port 3 16-bit

Port 4 4-bit

Port 5 16-bit

TRST

TCK

TDI

TDO

TMS

BRKIN

BRKOUT

TRCLK

XTAL1

XTAL2

V

DDOSC3

ASC0/1, SSC0, SCU, CAN

GPTA, SCU

GPTA, OCDS L 2, MLI0

OCDS / JTAG Control

Oscillator

V

DDOSC

V

SSOSC

MCB06066

Figure 2-2 TC1762 Logic Symbol

Data Sheet 7 V1.0, 2008-04

Preliminary

2.3

Pin Configuration

Figure 2-3 shows the TC1762 pin configuration.

TC1762

General Device Information

OCDSDBG0/OUT40/IN40/P5.0








TRCLK

V

DD

V

DDP

V

SS

OCDSDBG8/RDATA0B/P5.8

OCDSDBG9/RVALID0B/P5.9

OCDSDBG10/RREADY0B/P5.10

OCDSDBG11/RCLK0B/P5.11

OCDSDBG12/TDATA0/P5.12

OCDSDBG13/TVALID0B/P5.13

OCDSDBG14/TREADY0B/P5.14

OCDSDBG15/TCLK0/P5.15

N.C.

V

SSAF

V

DDAF

V

DDMF

V

SSMF

V

FAREF

V

FAGND

AN35

AN34

AN33

AN32

AN31

AN30

AN29

AN28

AN7

AN27

AN26

AN25

AN24

AN23

AN22

AN21

AN20

20

21

22

23

24

25

14

15

16

17

18

19

26

27

28

29

30

31

8

9

10

11

12

13

5

6

7

1

2

3

4

37

38

39

40

41

42

43

44

32

33

34

35

36

TC1762

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

P3.4/MTSR0

P3.7/SLSI0/SLSO02

P3.3/MRST0

P3.2/SCLK0

P3.8/SLSO06/TXD1A

P3.6/SLSO01/SLSO01

P3.5/SLSO00/SLSO00

V

SS

V

DDP

V

DD

HDRST

PORST

NMI

BYPASS

TESTMODE

BRKIN

BRKOUT

TCK

TRST

TDO

TMS

TDI

P1.7/IN23/OUT23/OUT79



P1.4/IN20/EMG_IN/OUT20/OUT76

V

DDOSC3

V

DDOSC

V

SSOSC

XTAL2

XTAL1

V

SS

V

DDP

V

DD


P1.11/IN27/IN51/OUT27/OUT51







P4.3/IN31/IN55/OUT31/OUT55/SYSCLK

N.C.

Figure 2-3 TC1762 Pinning for PG-LQFP-176-2 Package

MCP06067

Data Sheet 8 V1.0, 2008-04

TC1762


2.4

Pad Driver and Input Classes Overview

The TC1762 provides different types and classes of input and output lines. For understanding of the abbreviations in

Table 2-1 starting at the next page,

Table 4-1

gives an overview on the pad type and class types.

Data Sheet 9 V1.0, 2008-04

TC1762

Preliminary

2.5

Pin Definitions and Functions

Table 2-1 shows the TC1762 pin definitions and functions.


Table 2-1

Symbol

Pin Definitions and Functions

Pins I/O Pad

Driver

Class

Power

Supply

Functions

Parallel Ports

P0

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P0.8

P0.9

P0.10

P0.11

P0.12

P0.13

P0.14

P0.15

145

146

147

148

166

167

173

174

149

150

151

152

168

169

175

176

I/O A1 V

DDP

Port 0

Port 0 is a 16-bit bi-directional general- purpose I/O port which can be alternatively used for GPTA I/O lines or external trigger inputs.

IN0 / OUT0 /

IN1 / OUT1 /

IN2 / OUT2 /

IN3 / OUT3 /

IN4 / OUT4 /

IN5 / OUT5 /

IN6 / OUT6 /

REQ2

IN7 / OUT7 /

REQ3

IN8 / OUT8 /

IN9 / OUT9 /

IN10 / OUT10 /

IN11 / OUT11 /

IN12 / OUT12 /

IN13 / OUT13 /

IN14 / OUT14 /

REQ4

IN15 / OUT15 /

REQ5

OUT56 line of GPTA

OUT57 line of GPTA

OUT58 line of GPTA

OUT59 line of GPTA

OUT60 line of GPTA

OUT61 line of GPTA

OUT62 line of GPTA

External trigger input 2

OUT63 line of GPTA


OUT64 line of GPTA

OUT65 line of GPTA

OUT66 line of GPTA

OUT67 line of GPTA

OUT68 line of GPTA

OUT69 line of GPTA

OUT70 line of GPTA


OUT71 line of GPTA


In addition, the state of the port pins are latched into the software configuration input register SCU_SCLIR at the rising edge of

HDRST. Therefore, Port 0 pins can be used for operating mode selections by software.

Data Sheet 10 V1.0, 2008-04

TC1762


Table 2-1 Pin Definitions and Functions (cont’d)

Symbol Pins I/O Pad

Driver

P1

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P1.8

P1.9

P1.10

P1.11

P1.12

P1.13

P1.14

91

92

93

98

107

108

109

110

94

95

96

97

73

72

71

I/O

Class

A1

A1

A1

A1

A1

A1

A1

A1

A2

A2

A2

A2

A1

A1

A1

Power

Supply

V

DDP

Functions

Port 1

Port 1 is a 15-bit bi-directional general purpose I/O port which can be alternatively used for GPTA I/O lines and ADC0 interface.

IN16 / OUT16 /

IN17 / OUT17 /

IN18 / OUT18 /

IN19 / OUT19 /

IN20 / OUT20 /

IN21 / OUT21 /

IN22 / OUT22 /

IN23 / OUT23 /

IN24 / OUT24 /

IN25 / OUT25 /

IN26 / OUT26 /

IN27 / OUT27 /

AD0EMUX0

AD0EMUX1

AD0EMUX2

OUT72 line of GPTA

OUT73 line of GPTA

OUT74 line of GPTA

OUT75 line of GPTA

OUT76 line of GPTA

OUT77 line of GPTA

OUT78 line of GPTA

OUT79 line of GPTA

IN48 / OUT48 line of GPTA




ADC0 external multiplexer control output 0



In addition, P1.4 also serves as emergency

shut-off input for certain I/O lines (e.g. GPTA related outputs).

Data Sheet 11 V1.0, 2008-04

TC1762




Driver

P2

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

74

75

76

77

78

79

80

81

I/O

Class

A2

A2

A2

A2

A1

A2

A1

A1

Power

Supply

V

DDP

Functions

Port 2

Port 2 is a 14-bit bi-directional general- purpose I/O port which can be alternatively used for GPTA I/O, and interface for MLI0,

MSC0 or SSC0.

TCLK0

IN32 / OUT32

TREADY0A

IN33 / OUT33

SLSO03

TVALID0A

IN34 / OUT34

TDATA0

IN35 / OUT35

RCLK0A

IN36 / OUT36

RREADY0A

IN37 / OUT37

RVALID0A

IN38 / OUT38

RDATA0A

IN39 / OUT39

MLI0 transmit channel clock output A line of GPTA

MLI0 transmit channel ready input A line of GPTA

SSC0 slave select output 3

MLI0 transmit channel valid output A line of GPTA

MLI0 transmit channel data output A line of GPTA

MLI0 receive channel clock input A line of GPTA

MLI0 receive channel ready output A line of GPTA

MLI0 receive channel valid input A line of GPTA

MLI0 receive channel data input A line of GPTA

Data Sheet 12 V1.0, 2008-04

TC1762

Preliminary

Table 2-1


Driver

P2.8

164

Pin Definitions and Functions (cont’d)

Power

Supply

Functions

Class

A2

P2.9

160 A2

SLSO04

EN00

SLSO05

EN01

P2.10

P2.11

P2.12

P2.13

161

162

163

165

A2

A2

A2

A1

FCLP0B

SOP0B

SDI0


SSC0 Slave Select output 4

MSC0 enable output 0

SSC0 Slave Select output 5

MSC0 enable output 1

MSC0 clock output B

MSC0 serial data output B

MSC0 serial data input

Data Sheet 13 V1.0, 2008-04

TC1762




Driver

P3

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

P3.8

P3.9

P3.10

P3.11

P3.12

P3.13

P3.14

P3.15

136

135

129

130

132

126

127

131

128

138

137

144

143

142

134

133

I/O

Class

A2

A2

A2

A2

A2

A2

A2

A2

A2

A2

A1

A1

A2

A2

A2

A2

Power

Supply

V

DDP

Functions

Port 3

Port 3 is a 16-bit bi-directional general- purpose I/O port which can be alternatively used for ASC0/1, SSC0 and CAN lines.

RXD0A

TXD0A

ASC0 receiver inp./outp. A

ASC0 transmitter output A

SLSO00

SLSO01

SLSI0

SLSO02

SLSO06

TXD1A

RXD1A

REQ0

REQ1

RXDCAN0

RXD0B

TXDCAN0

TXD0B

RXDCAN1

RXD1B

TXDCAN1

TXD1B

This pin is sampled at the rising edge of

PORST. If this pin and the BYPASS input pin are both active, then oscillator bypass mode is entered.

SCLK0

MRST0

MTSR0

SSC0 clock input/output

SSC0 master receive input/ slave transmit output

SSC0 master transmit output/slave receive input



SSC0 slave select input



ASC1 transmitter output A

ASC1 receiver inp./outp. A



CAN node 0 receiver input

ASC0 receiver inp./outp. B

CAN node 0 transm. output

ASC0 transmitter output B

CAN node 1 receiver input

ASC1 receiver inp./outp. B

CAN node 1 transm. output

ASC1 transmitter output B

Data Sheet 14 V1.0, 2008-04

TC1762




Driver

Class

P4

P4.[3:0]

P4.0

P4.1

P4.2

P4.3

86

87

88

90

I/O

A1

A1

A2

A2

Power

Supply

V

DDP

Functions

Port 4 / Hardware Configuration Inputs

HWCFG[3:0] Boot mode and boot location inputs; inputs are latched with the rising edge of

HDRST.

During normal operation, Port 4 pins may be used as alternate functions for GPTA or system clock output.

IN28 / OUT28 /

IN29 / OUT29 /

IN30 / OUT30 /

IN31 / OUT31 /

SYSCLK





System Clock Output

Data Sheet 15 V1.0, 2008-04

TC1762




Driver

P5

P5.0

P5.1

P5.2

P5.3

P5.4

P5.5

P5.6

P5.7

1

2

3

4

5

6

7

8

Class

I/O A2

Power

Supply

V

DDP

Functions

Port 5

Port 5 is a 16-bit bi-directional general- purpose I/O port. In emulation, it is used as a trace port for OCDS Level 2 debug lines. In normal operation, it is used for GPTA I/O or the MLI0 interface.

OCDSDBG0

IN40 / OUT40

OCDSDBG1

IN41 / OUT41

OCDSDBG2

IN42 / OUT42

OCDSDBG3

IN43 / OUT43

OCDSDBG4

IN44 / OUT44

OCDSDBG5

IN45 / OUT45

OCDSDBG6

IN46 / OUT46

OCDSDBG7

IN47 / OUT47

OCDS L2 Debug Line 0

(Pipeline Status Sig. PS0) line of GPTA










(Break Qualification Line

BRK0) line of GPTA



BRK1) line of GPTA



BRK2) line of GPTA

Data Sheet 16 V1.0, 2008-04

TC1762

Preliminary



Driver

P5.8

13

Class

Power

Supply

Functions

OCDSDBG8

P5.9

P5.10

P5.11

P5.12

P5.13

P5.14

P5.15

14

15

16

17

18

19

20


RDATA0B

OCDSDBG9

RVALID0B

OCDSDBG10

RREADY0B

OCDSDBG11

RCLK0B

OCDSDBG12

TDATA0

OCDSDBG13

TVALID0B

OCDSDBG14

TREADY0B

OCDSDBG15

TCLK0


(Indirect PC Addr. PC0)

MLI0 receive channel data input B



MLI0 receive channel valid input B



MLI0 receive channel ready output B



MLI0 receive channel clock input B



MLI0 transmit channel data output B



MLI0 transmit channel valid output B


(Indirect PC Address PC6)

MLI0 transmit channel ready input B


(Indirect PC Address PC7)

MLI0 transmit channel clock output B

Data Sheet 17 V1.0, 2008-04

TC1762




Driver

Class

MSC0 Outputs

FCLP0A

FCLN0

SOP0A

SON0

157

156

159

158

O

O

O

O

C

Power

Supply

V

DDP

Functions

LVDS MSC Clock and Data Outputs

2)

MSC0 Differential Driver Clock Output

Positive A

MSC0 Differential Driver Clock Output

Negative

MSC0 Differential Driver Serial Data Output

Positive A

MSC0 Differential Driver Serial Data Output

Negative

Data Sheet 18 V1.0, 2008-04

TC1762


AN8

AN9

AN10

AN11

AN12

AN13

AN14

AN15

AN16

AN17

AN18

AN19

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN20

AN21

AN22

AN23

AN24

AN25

AN26

AN27

AN28

AN29

AN30

55

50

49

48

47

46

45

60

59

58

57

56

67

66

65

64

63

62

61

36

40

39

38

37

35

34

33

44

43

42

41



Driver

Class

Analog Inputs

AN[35:0] I D

Power

Supply

–

Functions

Analog Input Port

The Analog Input Port provides altogether 36 analog input lines to ADC0 and FADC.

AN[31:0]: ADC0 analog inputs [31:0]

AN[35:32]: FADC analog differential inputs

Analog input 0

Analog input 1

Analog input 2

Analog input 3

Analog input 4

Analog input 5

Analog input 6

Analog input 7

Analog input 8

Analog input 9

Analog input 10

Analog input 11

Analog input 12

Analog input 13

Analog input 14

Analog input 15

Analog input 16

Analog input 17

Analog input 18

Analog input 19

Analog input 20

Analog input 21

Analog input 22

Analog input 23

Analog input 24

Analog input 25

Analog input 26

Analog input 27

Analog input 28

Analog input 29

Analog input 30

Data Sheet 19 V1.0, 2008-04

TC1762




Driver

Class

AN31

AN32

AN33

AN34

AN35

32

31

30

29

28

I D

System I/O

TRST

TCK

TDI

114

115

111

I

I

I A2

1)

A2

1)

A1

1)

TDO

TMS

113 O A2

112 I A2

1)

BRKIN 117 I/O A3

BRK

OUT

116 I/O A3

TRCLK

NMI

9

120 I

O A4

A2

4)5)

HDRST 122 I/O A2

6)

PORST

7)

121 I A2

4)

Power

Supply

–

V

V

V

V

V

V

V

V

V

V

V

DDP

DDP

DDP

DDP

DDP

DDP

DDP

DDP

DDP

DDP

DDP

Functions

Analog input 31

Analog input 32

Analog input 33

Analog input 34

Analog input 35

JTAG Module Reset/Enable Input

JTAG Module Clock Input

JTAG Module Serial Data Input

JTAG Module Serial Data Output

JTAG Module State Machine Control Input

OCDS Break Input (Alternate Output)

2)3)

OCDS Break Output (Alternate Input)

2)3)

Trace Clock for OCDS_L2 Lines

Non-Maskable Interrupt Input

Hardware Reset Input /

Reset Indication Output

Power-on Reset Input

2)

BYPASS 119 I A1

1)

V

DDP

TEST

MODE

XTAL1

XTAL2

N.C.

118 I

102

103

21,

89

A2

4)8)

I

O n.a.

– –

V

V

–

DDP

DDOSC

PLL Clock Bypass Select Input

This input has to be held stable during poweron resets. With BYPASS = 1, the spike filters in the HDRST, PORST and NMI inputs are switched off.

Test Mode Select Input

For normal operation of the TC1762, this pin should be connected to high level.

Oscillator/PLL/Clock Generator

Input/Output Pins

Not Connected

These pins are reserved for future extension and must not be connected externally.

Data Sheet 20 V1.0, 2008-04

TC1762




Driver

Class

Power Supplies

V

DDM

V

SSM

V

DDMF

V

SSMF

V

DDAF

V

SSAF

V

AREF0

V

AGND0

V

FAREF

V

V

V

V

V

V

FAGND

DDOSC

DDOSC3

SSOSC

DDFL3

DD

54 – –

53 – –

24 – –

25 – –

23 – –

22 – –

52 – –

51 – –

26 – –

27 – –

105 – –

106 – –

104 – –

141 – –

10,

68,

84,

99,

123,

153,

170

– –

Power

Supply

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

Functions

ADC Analog Part Power Supply (3.3 V)

ADC Analog Part Ground for V

DDM

FADC Analog Part Power Supply (3.3 V)

FADC Analog Part Ground for V

DDMF

FADC Analog Part Logic Power Supply

(1.5 V)

FADC Analog Part Logic Ground for V

DDAF

ADC Reference Voltage

ADC Reference Ground

FADC Reference Voltage

FADC Reference Ground

Main Oscillator and PLL Power Supply

(1.5 V)

Main Oscillator Power Supply (3.3 V)

Main Oscillator and PLL Ground

Power Supply for Flash (3.3 V)

Core Power Supply (1.5 V)

Data Sheet 21 V1.0, 2008-04

TC1762




Driver

Class

V

DDP

11,

69,

83,

100,

124,

154,

171,

139

– –

Power

Supply

–

Functions

Port Power Supply (3.3 V)

V

SS

12,

70,

85,

101,

125,

155,

172,

140,

82

– – – Ground

1) These pads are I/O pads with input only function. Its input characteristics are identical with the input characteristics as defined for class A pads.

2) In case of a power-fail condition (one or more power supply voltages drop below the specified voltage range), an undefined output driving level may occur at these pins.

3) Programmed by software as either break input or break output.

4) These pads are input only pads with input characteristics.

5) Input only pads with input spike filter.

6) Open drain pad with input spike filter.

7) The dual input reset system of TC1762/TC1766ED, assumes that the PORST reset pin is used for power-on reset only. It has to be taken into account that if a system uses the PORST reset input for other system resets, the emulation part of the TC1766ED Emulation Device is reset as well. Thus, it will always force a complete re-initialization of the emulator and will prevent the user debugging across these types of resets.

8) Input only pads without input spike filter.

Data Sheet 22 V1.0, 2008-04

TC1762


Table 2-2 List of Pull-up/Pull-down Reset Behavior of the Pins

Pins PORST = 0 PORST = 1

All GPIOs, TDI, TMS, TDO

HDRST

BYPASS

Pull-up

Drive-low

Pull-up

Pull-up

High-impedance

Pull-down TRST, TCK

TRCLK

BRKIN, BRKOUT, TESTMODE

NMI, PORST

High-impedance

High-impedance

Pull-up

Pull-down

Data Sheet 23 V1.0, 2008-04

TC1762

Preliminary Functional Description

3 Functional Description

Chapter 3 provides an overview of the TC1762 functional description.

3.1

System Architecture and On-Chip Bus Systems

The TC1762 has two independent on-chip buses (see also TC1762 block diagram on

Page 2-6 ):

• Local Memory Bus (LMB)

• System Peripheral Bus (SPB)

The LMB Bus connects the CPU local resources for data and instruction fetch. The Local

Memory Bus interconnects the memory units and functional units, such as CPU and

PMU. The main target of the LMB bus is to support devices with fast response times, optimized for speed. This allows the DMI and PMI fast access to local memory and reduces load on the FPI bus. The Tricore system itself is located on LMB bus.

The Local Memory Bus is a synchronous, pipelined, split bus with variable block size transfer support. It supports 8-, 16-, 32- and 64-bit single transactions and variable length 64-bit block transfers.

The SPB Bus is accessible to the CPU via the LMB Bus bridge. The System Peripheral

Bus (SPB Bus) in TC1762 is an on-chip FPI Bus. The FPI Bus interconnects the functional units of the TC1762, such as the DMA and on-chip peripheral components.

The FPI Bus is designed to be quick to be acquired by on-chip functional units, and quick to transfer data. The low setup overhead of the FPI Bus access protocol guarantees fast

FPI Bus acquisition, which is required for time-critical applications.The FPI Bus is designed to sustain high transfer rates. For example, a peak transfer rate of up to 320

Mbyte/s can be achieved with a 80 MHz bus clock and 32-bit data bus. With a 66 MHz bus clock, the peak transfer rate is up to 264 Mbytes/s. Multiple data transfers per bus arbitration cycle allow the FPI Bus to operate at close to its peak bandwidth.

Both the LMB Bus and the SPB Bus runs at full CPU speed. The maximum CPU speed is 66 or 80 MHz depending on the derivative.

Additionally, two simplified bus interfaces are connected to and controlled by the DMA

Controller:

• DMA Bus

• SMIF Interface

Data Sheet 24 V1.0, 2008-04

TC1762


3.2

On-Chip Memories

As shown in the TC1762 block diagram on

Page 2-6 , some of the TC1762 units provide

on-chip memories that are used as program or data memory.

• Program memory in PMU

– 16 Kbyte Boot ROM (BROM)

– 1024 Kbyte Program Flash (PFlash)

• Program memory in PMI

– 8 Kbyte Scratch-Pad RAM (SPRAM)

– 8 Kbyte Instruction Cache (ICACHE)

• Data memory in PMU

– 16 Kbyte Data Flash (DFlash)

– 4 Kbyte Overlay RAM (OVRAM)

• Data memory in DMI

– 32 Kbyte Local Data RAM (LDRAM)

• On-chip SRAM with parity error protection

Features of Program Flash

• 1024 Kbyte on-chip program Flash memory

• Usable for instruction code or constant data storage

• 256-byte program interface

– 256 bytes are programmed into PFLASH page in one step/command

• 256-bit read interface

– Transfer from PFLASH to CPU/PMI by four 64-bit single cycle burst transfers

• Dynamic correction of single-bit errors during read access

• Detection of double-bit errors

• Fixed sector architecture

– Eight 16 Kbyte, one 128 Kbyte, one 256 Kbyte and one 512 Kbyte sectors

– Each sector separately erasable

– Each sector separately write-protectable

• Configurable read protection for complete PFLASH with sophisticated read access supervision, combined with write protection for complete PFLASH (protection against

“Trojan horse” software)

• Configurable write protection for each sector

– Each sector separately write-protectable

– With capability to be re-programmed

– With capability to be locked forever (OTP)

• Password mechanism for temporary disabling of write and read protection

• On-chip generation of programming voltage

• JEDEC-standard based command sequences for PFLASH control

– Write state machine controls programming and erase operations

– Status and error reporting by status flags and interrupt

• Margin check for detection of problematic PFLASH bits

Data Sheet 25 V1.0, 2008-04

TC1762


Features of Data Flash

• 16 Kbyte on-chip data Flash memory, organized in two 8 Kbyte banks

• Usable for data storage with EEPROM functionality

• 128 Byte of program interface

– 128 bytes are programmed into one DFLASH page by one step/command

• 64-bit read interface (no burst transfers)

• Dynamic correction of single-bit errors during read access

• Detection of double-bit errors

• Fixed sector architecture

– Two 8 Kbyte banks/sectors

– Each sector separately erasable

• Configurable read protection (combined with write protection) for complete DFLASH together with PFLASH read protection

• Password mechanism for temporary disabling of write and read protection

• Erasing/programming of one bank possible while reading data from the other bank

• Programming of one bank while erasing the other bank possible

• On-chip generation of programming voltage

• JEDEC-standard based command sequences for DFLASH control

– Write state machine controls programming and erase operations

– Status and error reporting by status flags and interrupt

• Margin check for detection of problematic DFLASH bits

Data Sheet 26 V1.0, 2008-04

TC1762


3.3

Architectural Address Map

Table 3-1 shows the overall architectural address map as defined for the TriCore and as

implemented in TC1762.

Table 3-1

Segment

0-7

TC1762 Architectural Address Map

Contents Size Description

8

9

10

11

12

13

14

15

Global

Global

Memory

Global

Memory

Global

Memory

Global

Memory

8 x 256

Mbyte

256 Mbyte

256 Mbyte

256 Mbyte

256 Mbyte

Reserved (MMU space); cached

Reserved (246 Mbyte); PMU, Boot ROM; cached

FPI space; cached

Reserved (246 Mbyte), PMU, Boot ROM; noncached

FPI space; non-cached

Local LMB

Memory

DMI

256 Mbyte Reserved; bottom 4 Mbyte visible from FPI bus in segment 14; cached

64 Mbyte Local Data Memory RAM; non-cached

PMI

EXT_PER

64 Mbyte

96 Mbyte

Local Code Memory RAM; non-cached

Reserved; non-cached

EXT_EMU

BOOTROM

EXTPER

CPU[0 ..15] image region

LMB_PER

CSFRs

INT_PER

16 Mbyte

16 Mbyte

Reserved; non-cached

Boot ROM space, Boot ROM mirror; non-cached

128 Mbyte Reserved; non-speculative; non-cached; no execution

16 x 8

Mbyte

Non-speculative; non-cached; no execution

256

Mbyte

CSFRs of CPUs[0 ..15];

LMB & FPI Peripheral Space; non-speculative; non-cached; no execution

Data Sheet 27 V1.0, 2008-04

TC1762


3.4

Memory Protection System

The TC1762 memory protection system specifies the addressable range and read/write permissions of memory segments available to the current executing task. The memory protection system controls the position and range of addressable segments in memory.

It also controls the types of read and write operations allowed within addressable memory segments. Any illegal memory access is detected by the memory protection hardware, which then invokes the appropriate Trap Service Routine (TSR) to handle the error. Thus, the memory protection system protects critical system functions against both software and hardware errors. The memory protection hardware can also generate signals to the Debug Unit to facilitate tracing illegal memory accesses.

There are two Memory Protection Register Sets in the TC1762, numbered 0 and 1, which specify memory protection ranges and permissions for code and data. The

PSW.PRS bit field determines which of these is the set currently in use by the CPU. As the TC1762 uses a Harvard-style memory architecture, each Memory Protection

Register Set is broken down into a Data Protection Register Set and a Code Protection

Register Set. Each Data Protection Register Set can specify up to four address ranges to receive a particular protection modes. Each Code Protection Register Set can specify up to two address ranges to receive a particular protection modes.

Each Data Protection Register Sets and Code Protection Register Sets determines the range and protection modes for a separate memory area. Each set contains a pair of registers which determine the address range (the Data Segment Protection Registers and Code Segment Protection Registers) and one register (Data Protection Mode

Register) which determines the memory access modes that applies to the specified range.

Data Sheet 28 V1.0, 2008-04

TC1762


3.5

DMA Controller and Memory Checker

The DMA Controller of the TC1762 transfers data from data source locations to data destination locations without intervention of the CPU or other on-chip devices. One data move operation is controlled by one DMA channel. Eight DMA channels are provided in one DMA Sub-Block. The Bus Switch provides the connection of the DMA Sub-Block to the two FPI Bus interfaces and an MLI bus interface. In the TC1762, the FPI Bus interfaces are connected to the System Peripheral Bus and the DMA Bus. The third specific bus interface provides a connection to the Micro Link Interface module (MLI0 in the TC1762) and other DMA-related devices (Memory Checker module in the TC1762).

Clock control, address decoding, DMA request wiring, and DMA interrupt service request control are implementation-specific and managed outside the DMA controller kernel.

Figure 3-1 shows the implementation details and interconnections of the DMA module.

Clock

Control f

DMA

DMA Controller

System

Periphera

Bus

DMA

Requests of

On-chip

Periph.

Units

DMA Sub-Block 0

Request

CH0n_OUT

Arbitration

DMA

Channels

00-07

Transaction

Control Unit

Bus

Switch

DMA Bus

Address

Decoder

Interrupt

Request

Nodes

SR[15:0]

DMA Interrupt Control

Arbiter/

Switch

Control

MLI0

Memory

Checker

MCB06149

Figure 3-1 DMA Controller Block Diagram

Features

• 8 independent DMA channels

Data Sheet 29 V1.0, 2008-04

TC1762


– 8 DMA channels in the DMA Sub-Block

– Up to 8 selectable request inputs per DMA channel

– 2-level programmable priority of DMA channels within the DMA Sub-Block

– Software and hardware DMA request

– Hardware requests by selected on-chip peripherals and external inputs

• Programmable priority of the DMA Sub-Blocks on the bus interfaces

• Buffer capability for move actions on the buses (at least 1 move per bus is buffered).

• Individually programmable operation modes for each DMA channel

– Single Mode: stops and disables DMA channel after a predefined number of DMA transfers

– Continuous Mode: DMA channel remains enabled after a predefined number of

DMA transfers; DMA transaction can be repeated.

– Programmable address modification

• Full 32-bit addressing capability of each DMA channel

– 4 Gbyte address range

– Support of circular buffer addressing mode

• Programmable data width of DMA transfer/transaction: 8-bit, 16-bit, or 32-bit

• Micro Link bus interface support

• Register set for each DMA channel

– Source and destination address register

– Channel control and status register

– Transfer count register

• Flexible interrupt generation (the service request node logic for the MLI channels is also implemented in the DMA module)

• All buses connected to the DMA module must work at the same frequency.

• Read/write requests of the System Bus side to the peripherals on DMA Bus are bridged to the DMA Bus (only the DMA is the master on the DMA bus), allowing easy access to these peripherals by CPU

Memory Checker

The Memory Checker Module (MCHK) makes it possible to check the data consistency of memories. Any SPB bus master may access the memory checker. It is preferable the

DMA does it as described hereafter. It uses DMA 8-bit, 16-bit, or 32-bit moves to read from the selected address area and to write the value read in a memory checker input register. With each write operation to the memory checker input register, a polynomial checksum calculation is triggered and the result of the calculation is stored in the memory checker result register.

The memory checker uses the standard Ethernet polynomial, which is given by:

G

32

= x

32

+ x

26

+ x

23

+ x

22

+ x

16

+ x

12

+ x

11

+ x

10

+ x

8

+ x

7

+ x

5

+ x

4

+ x

2

+ x +1

Note: Although the polynomial above is used for generation, the generation algorithm differs from the one that is used by the Ethernet protocol.

Data Sheet 30 V1.0, 2008-04

TC1762


3.6

Interrupt System

The TC1762 interrupt system provides a flexible and time-efficient means of processing interrupts. An interrupt request is serviced by the CPU, which is called the “Service

Provider”. Interrupt requests are called “Service Requests” rather than “Interrupt

Requests” in this document.

Each peripheral in the TC1762 can generate service requests. Additionally, the Bus

Control Units, the Debug Unit, and even the CPU itself can generate service requests to the Service Provider.

As shown in

Figure 3-2 , each TC1762 unit that can generate service requests is

connected to one or multiple Service Request Nodes (SRN). Each SRN contains a

Service Request Control Register mod_SRCx, where “mod” is the identifier of the service requesting unit and “x” an optional index. The CPU Interrupt Arbitration Bus connects the SRNs with the Interrupt Control Unit (ICU), which arbitrates service requests for the CPU and administers the CPU Interrupt Arbitration Bus.

The Debug Unit can generate service requests to the CPU. The CPU makes service requests directly to itself (via the ICU). The CPU Service Request Nodes are activated through software.

•

•

Depending on the selected system clock frequency f

SYS

, the number of f

SYS

clock cycles per arbitration cycle must be selected as follows: f f

SYS

< 60 MHz: ICR.CONECYC = 1

SYS

> 60 MHz: ICR.CONECYC = 0

Data Sheet 31 V1.0, 2008-04

TC1762

Functional Description Preliminary

Service

Requestors

Service Req.

Nodes

CPU

Interrupt

Arbitration Bus

MSC0

MLI0

SSC0

ASC0

ASC1

MultiCAN

ADC0

FADC

GPTA0

STM

FPU

Flash

Ext. Int

2

4

3

4

4

6

4

2

38

2

1

1

2

2

2 SRNs

4

4 SRNs

3

3 SRNs

4 SRNs

4

4 SRNs

4

6

6 SRNs

4

4 SRNs

2 SRNs

38 SRNs

38

2

2 SRNs

2

1

1 SRN

1

1 SRN

2 SRNs

2

5

CPU Interrupt

Control Unit

5 SRNs

5

Interrupt

Service

Provider

Software and

Breakpoint

Interrupts

CPU

CPU Interrupt

Control Unit

ICU

Int. Req.

PIPN

Int. Ack.

CCPN

1

Service Req.

Nodes

1 SRN

1

1

1 SRN

1

4

4 SRNs

4

1

1 SRN

1

1

1 SRN

1

Service

Requestors

LBCU

SBCU

DMA

Cerberus

DMA Bus

MCA06181

Figure 3-2 Block Diagram of the TC1762 Interrupt System

Data Sheet 32 V1.0, 2008-04

TC1762


3.7

Asynchronous/Synchronous Serial Interfaces (ASC0, ASC1)

Figure 3-3 shows a global view of the functional blocks and interfaces of the two

Asynchronous/Synchronous Serial Interfaces, ASC0 and ASC1.

Clock

Control f

ASC

Address

Decoder

Interrupt

Control

EIR

TBIR

TIR

RIR

To

DMA

ASC0_RDR

ASC0_TDR

ASC0

Module

(Kernel)

RXD_I0

RXD_I1

RXD_O

TXD_O

Port 3

Control

A2

A2

P3.0 /

RXD0A

P3.1 /

TXD0A

A2

A2

P3.12 /

RXD0B

P3.13 /

TXD0B

ASC1

Module

(Kernel)

RXD_I0

RXD_I1

RXD_O

TXD_O

A2

P3.9 /

RXD1A

A2

P3.8 /

TXD1A

Interrupt

Control

EIR

TBIR

TIR

RIR

To

DMA

ASC1_RDR

ASC1_TDR

A2

P3.14 /

RXD1B

A2

P3.15 /

TXD1B

MCB06211c

Figure 3-3 Block Diagram of the ASC Interfaces

The ASC provides serial communication between the TC1762 and other microcontrollers, microprocessors, or external peripherals.

The ASC supports full-duplex asynchronous communication and half-duplex synchronous communication. In Synchronous Mode, data is transmitted or received synchronous to a shift clock that is generated by the ASC internally. In Asynchronous

Mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be

Data Sheet 33 V1.0, 2008-04

TC1762

Preliminary Functional Description selected. Parity, framing, and overrun error detection are provided to increase the reliability of data transfers. Transmission and reception of data is double-buffered. For multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. Testing is supported by a loop-back option. A 13-bit baud rate generator provides the ASC with a separate serial clock signal, which can be accurately adjusted by a prescaler implemented as fractional divider.

Features

• Full-duplex asynchronous operating modes

– 8-bit or 9-bit data frames, LSB first

– Parity-bit generation/checking

– One or two stop bits

– Baud rate from 5.0 Mbit/s to 1.19 bit/s (@ 80 MHz module clock) and 4.1Mbit/s to

0.98 bit/s (@ 66 MHz module clock)

– Multiprocessor mode for automatic address/data byte detection

– Loop-back capability

• Half-duplex 8-bit synchronous operating mode

– Baud rate from 10.0 Mbit/s to 813.8 bit/s (@ 80 MHz module clock) and 8.25 Mbit/s to 671.4 bit/s (@ 66 MHz module clock)

• Double-buffered transmitter/receiver

• Interrupt generation

– On a transmit buffer empty condition

– On a transmit last bit of a frame condition

– On a receive buffer full condition

– On an error condition (frame, parity, overrun error)

Data Sheet 34 V1.0, 2008-04

TC1762


3.8

High-Speed Synchronous Serial Interface (SSC0)

Figure 3-4 shows a global view of the functional blocks and interfaces of the high-speed

Synchronous Serial Interface, SSC0.

Clock

Control f

SSC 0 f

C L C0

Address

Decoder

Interrupt

Control

EIR

TIR

RIR

To

DMA

SSC0_RDR

SSC0_TDR

M/S Select

1 )

Enable 1 )

SSC0

Module

(Kernel)

Master

Slave

Slave

Master

Slave

MRSTA

MRSTB

MTSR

MTSRA

MTSRB

MRST

SCLKA

SCLKB

SCLK

SLSI1

SLSI[7:2] 1 )

SLSO[2:0]

Port 3

Control

Master

SLSO[5:3]

SLSO6

SLSO7

1)

A2 P3.4 /MTSR0

A2 P3.3 /MRST0

A2 P3.2 /SCLK0

A2 P3.7 /SLSI0

A2 P3.5 /SLSO00

A2 P3.6 /SLSO01

A2 P3.7 /SLSO02

A2 P3.8 /SLSO06

Port 2

Control

A2 P2.1 /SLSO03

A2 P2.8 /SLSO04

A2

P2.9 /SLSO05

1) These lines are not connected

MCB06225

Figure 3-4 Block Diagram of the SSC Interfaces

The SSC supports full-duplex and half-duplex serial synchronous communication up to

40.0 MBaud at 80 MHz module clock and up to 33 MBaud at 66 MHz module clock. The serial clock signal can be generated by the SSC itself (Master Mode) or can be received from an external master (Slave Mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices.

Transmission and reception of data is double-buffered. A shift clock generator provides the SSC with a separate serial clock signal. Seven slave select inputs are available for

Data Sheet 35 V1.0, 2008-04

TC1762


Slave Mode operation. Eight programmable slave select outputs (chip selects) are supported in Master Mode.

Features

• Master and Slave Mode operation

– Full-duplex or half-duplex operation

– Automatic pad control possible

• Flexible data format

– Programmable number of data bits: 2 to 16 bits

– Programmable shift direction: LSB or MSB shift first

– Programmable clock polarity: Idle low or idle high state for the shift clock

– Programmable clock/data phase: Data shift with leading or trailing edge of the shift clock

• Baud rate generation from 40.0 Mbit/s to 610.36 bit/s (@ 80 MHz module clock) and

503.5 bit/s to 33 Mbit/s (@ 66 MHz module clock)

• Interrupt generation

– On a transmitter empty condition

– On a receiver full condition

– On an error condition (receive, phase, baud rate, transmit error)

• Flexible SSC pin configuration

• Seven slave select inputs SLSI[7:1] in Slave Mode

• Eight programmable slave select outputs SLSO[7:0] in Master Mode

– Automatic SLSO generation with programmable timing

– Programmable active level and enable control

Data Sheet 36 V1.0, 2008-04

TC1762


3.9

Micro Second Bus Interface (MSC0)

The MSC interface provides a serial communication link typically used to connect power switches or other peripheral devices. The serial communication link includes a fast synchronous downstream channel and a slow asynchronous upstream channel.

Figure 3-5 shows a global view of the MSC interface signals.

SR15 (from CAN)

Clock

Control f

MSC0 f

CLC0

FCLP

FCLN

SOP

SON

Address

Decoder

Interrupt

Control

SR[1:0]

To DMA SR[3:2]

16

ALTINL[15:0]

(from GPTA)

ALTINH[15:0]

16

EMGSTOPMSC

(from SCU)

MSC0

Module

(Kernel)

EN0

EN1

SDI[0]

1) SDI[7:1] are connected to high level

1)

Port 2

Control

C FCLP0A

C FCLN0

C SOP0A

C SON0

A2 P2.11 / FCLP0B

A2 P2.12 / SOP0B

A2 P2.8 / EN00

A2 P2.9 / EN01

A1 P2.13 / SDI0

MCA06255

Figure 3-5 Block Diagram of the MSC Interfaces

The downstream and upstream channels of the MSC module communicate with the external world via nine I/O lines. Eight output lines are required for the serial communication of the downstream channel (clock, data, and enable signals). One out of eight input lines SDI[7:0] is used as serial data input signal for the upstream channel. The source of the serial data to be transmitted by the downstream channel can be MSC register contents or data that is provided at the ALTINL/ALTINH input lines. These input lines are typically connected to other on-chip peripheral units (for example with a timer unit like the GPTA). An emergency stop input signal makes it possible to set bits of the serial data stream to dedicated values in emergency cases.

Data Sheet 37 V1.0, 2008-04

TC1762


Clock control, address decoding, and interrupt service request control are managed outside the MSC module kernel. Service request outputs are able to trigger an interrupt or a DMA request.

Features

• Fast synchronous serial interface to connect power switches in particular, or other peripheral devices via serial buses

• High-speed synchronous serial transmission on downstream channel

– Serial output clock frequency: f

FCL

= f

MSC

/2

– Fractional clock divider for precise frequency control of serial clock f

MSC

– Command, data, and passive frame types

– Start of serial frame: Software-controlled, timer-controlled, or free-running

– Programmable upstream data frame length (16 or 12 bits)

– Transmission with or without SEL bit

– Flexible chip select generation indicates status during serial frame transmission

– Emergency stop without CPU intervention

• Low-speed asynchronous serial reception on upstream channel

– Baud rate: f

MSC

divided by 4, 8, 16, 32, 64, 128, or 256

– Standard asynchronous serial frames

– Parity error checker

– 8-to-1 input multiplexer for SDI lines

– Built-in spike filter on SDI lines

Data Sheet 38 V1.0, 2008-04

TC1762


3.10

MultiCAN Controller (CAN)

Figure 3-6 shows a global view of the MultiCAN module with its functional blocks and

interfaces.

Clock

Control f

CAN f

CLC

MultiCAN Module Kernel

Address

Decoder

DMA

Interrupt

Control

INT_O

[1:0]

INT_O

[5:2]

INT_O15

Message

Object

Buffer

64

Objects

Linked

List

Control

CAN Control

CAN

Node 1

CAN

Node 0

TXDC1

RXDC1

TXDC0

Port 3

Control

RXDC0

A2

A2

P3.15 /

TXDCAN1

P3.14 /

RXDCAN1

A2

A2

P3.13 /

TXDCAN0

P3.12 /

RXDCAN0

MCA06281

Figure 3-6 Block Diagram of MultiCAN Module

The MultiCAN module contains two independently-operating CAN nodes with Full-CAN functionality that are able to exchange Data and Remote Frames via a gateway function.

Transmission and reception of CAN frames is handled in accordance with CAN specification V2.0 B (active). Each CAN node can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers.

Both CAN nodes share a common set of message objects. Each message object can be individually allocated to one of the CAN nodes. Besides serving as a storage container for incoming and outgoing frames, message objects can be combined to build gateways between the CAN nodes or to setup a FIFO buffer.

The message objects are organized in double-chained linked lists, where each CAN node has its own list of message objects. A CAN node stores frames only into message objects that are allocated to the message object list of the CAN node, and it transmits only messages belonging to this message object list. A powerful, command-driven list controller performs all message object list operations.

The bit timings for the CAN nodes are derived from the module timer clock ( f

CAN

), and are programmable up to a data rate of 1 Mbit/s. External bus transceivers are connected to a CAN node via a pair of receive and transmit pins.

Data Sheet 39 V1.0, 2008-04

TC1762


MultiCAN Features

• CAN functionality conforms to CAN specification V2.0 B active for each CAN node

(compliant to ISO 11898)

• Two independent CAN nodes

• 64 independent message objects (shared by the CAN nodes)

• Dedicated control registers for each CAN node

• Data transfer rate up to 1Mbit/s, individually programmable for each node

• Flexible and powerful message transfer control and error handling capabilities

• Full-CAN functionality: message objects can be individually

– assigned to one of the two CAN nodes

– configured as transmit or receive object

– configured as message buffer with FIFO algorithm

– configured to handle frames with 11-bit or 29-bit identifiers

– provided with programmable acceptance mask register for filtering

– monitored via a frame counter

– configured for Remote Monitoring Mode

• Automatic Gateway Mode support

• 6 individually programmable interrupt nodes

• CAN analyzer mode for bus monitoring

Data Sheet 40 V1.0, 2008-04

TC1762


3.11

Micro Link Serial Bus Interface (MLI0)

The Micro Link Interface is a fast synchronous serial interface that allows data exchange between microcontrollers of the 32-bit AUDO microcontroller family without intervention

of a CPU or other bus masters. Figure 3-7 shows how two microcontrollers are typically

connected together via their MLI interface. The MLI operates in both microcontrollers as a bus master on the system bus.

Controller 1

CPU

Controller 2

CPU

Peripheral

A

Peripheral

B

Peripheral

C

Peripheral

D

Memory MLI MLI Memory

System Bus System Bus

MCA06061

Figure 3-7 Typical Micro Link Interface Connection

Features

• Synchronous serial communication between MLI transmitters and MLI receivers located on the same or on different microcontroller devices

• Automatic data transfer/request transactions between local/remote controller

• Fully transparent read/write access supported (= remote programming)

• Complete address range of remote controller available

• Specific frame protocol to transfer commands, addresses and data

• Error control by parity bit

• 32-bit, 16-bit, and 8-bit data transfers

• Programmable baud rates

– MLI transmitter baud rate: max. f

MLI

/2 (= 40 Mbit/s @ 80 MHz module clock)

– MLI receiver baud rate: max. f

MLI

• Multiple remote (slave) controllers are supported

MLI transmitter and MLI receiver communicate with other off-chip MLI receivers and MLI transmitters via a 4-line serial I/O bus each. Several I/O lines of these I/O buses are available outside the MLI module kernel as four-line output or input buses.

Data Sheet 41 V1.0, 2008-04

TC1762


Figure 3-8 shows a global view of the functional blocks of the MLI module with its

interfaces.

Clock

Control f

ML I0

Address

Decoder

Interrupt

Control

SR[3:0]

MLI 0

Module

(Kernel)

To DMA

SR[4:7]

Cerberus

BRKOUT

TCLK

TREADYA

TREADYB

TREADYD

TVALIDA

TVALIDB

TVALIDD

TDATA

RCLKA

RCLKB

RCLKD

RREADYA

RREADYB

RREADYD

RVALIDA

RVALIDB

RVALIDD

RDATAA

RDATAB

RDATAD

Port 2

Control

Port 5

Control

A2 P2.0 / TCLK0

A2 P2.1 / TREADY0A

A2 P2.2 / TVALID0A

A2 P2.3 / TDATA0

A1 P2.4 / RCLK0A

A2 P2.5 / RREADY0A

A1 P2.6 / RVALID0A

A1 P2.7 / RDATA0A

A2 P5.15 / TCLK0

A2 P5.14 / TREADY0B

A2 P5.13 / TVALID0B

A2 P5.12 / TDATA0

A2 P5.11 / RCLK0B

A2 P5.10 / RREADY0B

A2 P5.9 / RVALID0B

A2 P5.8 / RDATA0B

MCB06322

Figure 3-8 Block Diagram of the MLI Module

Data Sheet 42 V1.0, 2008-04

TC1762


3.12

General Purpose Timer Array

The GPTA provides a set of timer, compare, and capture functionalities that can be flexibly combined to form signal measurement and signal generation units. They are optimized for tasks typical of engine, gearbox, electrical motor control applications, but can also be used to generate simple and complex signal waveforms needed in other industrial applications.

The TC1762 contains one General Purpose Timer Array (GPTA0).

Figure 3-9

shows a global view of the GPTA module.

GT0

GT1

GTC00

GTC01

GTC02

GTC03

Global

Timer

Cell Array

GTC30

GTC31

FPC0

FPC1

FPC2

FPC3

FPC4

FPC5

PDL0

GPTA

Clock Generation Unit

DCM0

DCM1

DCM2

DIGITAL

PLL

PDL1

DCM3 f

Clock

Conn.

Signal

Generation Unit

LTC00

LTC01

LTC02

LTC03

Local

Timer

Cell Array

LTC62

LTC63

I/O Line Sharing Unit

Interrupt Sharing Unit

MCB06063

Figure 3-9 Block Diagram of the GPTA Module

Data Sheet 43 V1.0, 2008-04

TC1762


3.12.1

Functionality of GPTA0

The General Purpose Timer Array GPTA0 provides a set of hardware modules required for high-speed digital signal processing:

• Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation.

• Phase Discrimination Logic units (PDL) decode the direction information output by a rotation tracking system.

• Duty Cycle Measurement Cells (DCM) provide pulse-width measurement capabilities.

• A Digital Phase Locked Loop unit (PLL) generates a programmable number of GPTA module clock ticks during an input signal’s period.

• Global Timer units (GT) driven by various clock sources are implemented to operate as a time base for the associated Global Timer Cells.

• Global Timer Cells (GTC) can be programmed to capture the contents of a Global

Timer on an external or internal event. A GTC may also be used to control an external port pin depending on the result of an internal compare operation. GTCs can be logically concatenated to provide a common external port pin with a complex signal waveform.

• Local Timer Cells (LTC) operating in Timer, Capture, or Compare Mode may also be logically tied together to drive a common external port pin with a complex signal waveform. LTCs — enabled in Timer Mode or Capture Mode — can be clocked or triggered by various external or internal events.

Input lines can be shared by an LTC and a GTC to trigger their programmed operation simultaneously.

The following list summarizes the specific features of the GPTA unit.

Clock Generation Unit

• Filter and Prescaler Cell (FPC)

– Six independent units

– Three basic operating modes:

Prescaler, Delayed Debounce Filter, Immediate Debounce Filter

– Selectable input sources:

Port lines, GPTA module clock, FPC output of preceding FPC cell

– Selectable input clocks:

GPTA module clock, prescaled GPTA module clock, DCM clock, compensated or uncompensated PLL clock

– f

GPTA

/2 maximum input signal frequency in Filter Modes

• Phase Discriminator Logic (PDL)

– Two independent units

– Two operating modes (2- and 3-sensor signals)

– f

GPTA

/4 maximum input signal frequency in 2-sensor Mode, signal frequency in 3-sensor Mode f

GPTA

/6 maximum input

Data Sheet 44 V1.0, 2008-04

TC1762


• Duty Cycle Measurement (DCM)

– Four independent units

– 0 - 100% margin and time-out handling

–

– f

GPTA

maximum resolution f

GPTA

/2 maximum input signal frequency

• Digital Phase Locked Loop (PLL)

– One unit

– Arbitrary multiplication factor between 1 and 65535

–

– f

GPTA


GPTA


• Clock Distribution Unit (CDU)

– One unit

– Provides nine clock output signals: f

GPTA

, divided f

GPTA

clocks, FPC1/FPC4 outputs, DCM clock, LTC prescaler clock

Signal Generation Unit

• Global Timers (GT)

– Two independent units

– Two operating modes (Free-Running Timer and Reload Timer)

– 24-bit data width

–

– f

GPTA


GPTA


• Global Timer Cell (GTC)

– 32 units related to the Global Timers

– Two operating modes (Capture, Compare and Capture after Compare)


–

– f

GPTA


GPTA


• Local Timer Cell (LTC)

– 64 independent units

– Three basic operating modes (Timer, Capture and Compare) for 63 units

– Special compare modes for one unit


–

– f

GPTA


GPTA


Interrupt Control Unit

• 111 interrupt sources, generating up to 38 service requests

Data Sheet 45 V1.0, 2008-04

TC1762


I/O Sharing Unit

• Interconnecting inputs and outputs from internal clocks, FPC, GTC, LTC, ports, and

MSC interface

Data Sheet 46 V1.0, 2008-04

TC1762


3.13

Analog-to-Digital Converter (ADC0)

Section 3.13

shows the global view of the ADC module with its functional blocks and

interfaces and the features which are provided by the module.

Clock

Control

Address

Decoder f f

ADC

CLC

Interrupt

Control

SR[3:0]

V

AGND0

V

DD

V

SS

V

V

DDM

SSM

V

AREF0

GPRS

EMUX0

EMUX1

Port 1

Control

ASGT

SW0TR, SW0GT

ETR, EGT

QTR, QGT

TTR, TGT

External

Request

Unit

(SCU)

ADC0

Module

Kernel

Group 0

AIN0

AIN15

AIN16

Group 1

SR[7:4]

AIN30

To DMA

AIN31

0

1

Die

Temperature

Measurement

A1

P1.14 /

AD0EMUX2 (GRPS)

A1 P1.13 /AD0EMUX1

8

A1 P1.12 /AD0EMUX0

From Ports

2

From MSC0

6

From GPTA

D AN0

D AN15

D AN16

D AN30

D AN31

SCU_CON.DTSON

MCA06427

Figure 3-10 Block Diagram of the ADC Module

The ADC module has 16 analog input channels. An analog multiplexer selects the input line for the analog input channels from among 32 analog inputs. Additionally, an external analog multiplexer can be used for analog input extension. External Clock control, address decoding, and service request (interrupt) control are managed outside the ADC module kernel. External trigger conditions are controlled by an External Request Unit.

This unit generates the control signals for auto-scan control (ASGT), software trigger control (SW0TR, SW0GT), the event trigger control (ETR, EGT), queue control (QTR,

QGT), and timer trigger control (TTR, TGT).

An automatic self-calibration adjusts the ADC module to changing temperatures or process variations.

Figure 3-10 shows the global view of the ADC module with its

functional blocks and interfaces.

Data Sheet 47 V1.0, 2008-04

TC1762


Features

• 8-bit, 10-bit, 12-bit A/D conversion

• Conversion time below 2.5

µs @ 10-bit resolution

• Extended channel status information on request source

• Successive approximation conversion method

• Total Unadjusted Error (TUE) of

±2 LSB @ 10-bit resolution

• Integrated sample & hold functionality

• Direct control of up to 16 analog input channels

• Dedicated control and status registers for each analog channel

• Powerful conversion request sources

• Selectable reference voltages for each channel

• Programmable sample and conversion timing schemes

• Limit checking

• Flexible ADC module service request control unit

• Automatic control of external analog multiplexers

• Equidistant samples initiated by timer

• External trigger and gating inputs for conversion requests

• Power reduction and clock control feature

• On-chip die temperature sensor output voltage measurement

Data Sheet 48 V1.0, 2008-04

TC1762


3.14

Fast Analog-to-Digital Converter Unit (FADC)

The on-chip FADC module of the TC1762 basically is a 2-channel A/D converter with 10bit resolution that operates by the method of the successive approximation.

As shown in

Figure 3-11 , the main FADC functional blocks are:

• The Input Stage — contains the differential inputs and the programmable amplifier

• The A/D Converter — is responsible for the analog-to-digital conversion

• The Data Reduction Unit — contains programmable antialiasing and data reduction filters

• The Channel Trigger Control block — determines the trigger and gating conditions for the two FADC channels

• The Channel Timers — can independently trigger the conversion of each FADC channel

• The A/D Control block is responsible for the overall FADC functionality

•

•

•

The FADC module is supplied by the following power supply and reference voltage lines:

V

V

V

DDMF

/ V

DDMF

:FADC Analog Part Power Supply (3.3 V)

DDAF

/ V

DDAF

:FADC Analog Part Logic Power Supply (1.5 V)

FAREF

/ V

FAGND

:FADC Reference Voltage (3.3 V)/FADC Reference Ground

Data Sheet 49 V1.0, 2008-04

TC1762


V

FAREF

V

DDAF

V

FAGND

V

SSAF

V

DDMF

V

SSMF

Clock

Control f f

FADC

CLC

Address

Decoder

Interrupt

Control

SR[1:0]

SR[3:2]

DMA

FADC

Module

Kernel

FAIN0P

FAIN0N

FAIN1P

FAIN1N

D AN32

D AN33

D AN34

D AN35

GPTA0

OUT1

OUT9

OUT18

OUT26

OUT2

OUT10

OUT19

OUT27

GS[7:0]

TS[7:0]

A1 P3.10 / REQ0

A1 P3.11 / REQ1

A1 P0.14 / REQ4

A1 P0.15 / REQ5

External Request Unit

(SCU)

PDOUT2

PDOUT3

Figure 3-11 Block Diagram of the FADC Module

MCA06445

Features

• Extreme fast conversion, 21 cycles of f

FADC

clock (262.5 ns @ f

FADC

318.2 ns @ f

FADC

= 66 MHz)

• 10-bit A/D conversion

= 80 MHz and

– Higher resolution by averaging of consecutive conversions is supported

• Successive approximation conversion method

• Two differential input channels

• Offset and gain calibration support for each channel

• Differential input amplifier with programmable gain of 1, 2, 4 and 8 for each channel

• Free-running (Channel Timers) or triggered conversion modes

• Trigger and gating control for external signals

• Built-in Channel Timers for internal triggering

• Channel timer request periods independently selectable for each channel

Data Sheet 50 V1.0, 2008-04

TC1762


• Selectable, programmable anti-aliasing and data reduction filter block

3.15

System Timer

The TC1762’s STM is designed for global system timing applications requiring both high precision and long period.

Features

• Free-running 56-bit counter

• All 56 bits can be read synchronously

• Different 32-bit portions of the 56-bit counter can be read synchronously

• Flexible interrupt generation based on compare match with partial STM content

• Driven by maximum 66 or 80 MHz (= derivative f

SYS

, default after reset =

• Counting starts automatically after a reset operation f

SYS

/2) depending on

• STM is reset by:

– Watchdog reset

– Software reset (RST_REQ.RRSTM must be set)

– Power-on reset

• STM (and clock divider STM_CLC.RMC) is not reset at a hardware reset (HDRST =

0)

• STM can be halted in debug/suspend mode (via STM_CLC register)

The STM is an upward counter, running either at the system clock frequency f

SYS

or at a fraction of it. The STM clock frequency is f

STM

= f

SYS

/RMC with RMC = 0-7 (default after reset is f

STM

= f

SYS

/2, selected by RMC = 010

B)

. RMC is a bit field in register STM_CLC.

In case of a power-on reset, a watchdog reset, or a software reset, the STM is reset. After one of these reset conditions, the STM is enabled and immediately starts counting up. It is not possible to affect the content of the timer during normal operation of the TC1762.

The timer registers can only be read but not written to.

The STM can be optionally disabled for power-saving purposes, or suspended for debugging purposes via its clock control register. In suspend mode of the TC1762

(initiated by writing an appropriate value to STM_CLC register), the STM clock is stopped but all registers are still readable.

Due to the 56-bit width of the STM, it is not possible to read its entire content with one instruction. It needs to be read with two load instructions. Since the timer would continue to count between the two load operations, there is a chance that the two values read are not consistent (due to possible overflow from the low part of the timer to the high part between the two read operations). To enable a synchronous and consistent reading operation of the STM content, a capture register (STM_CAP) is implemented. It latches the content of the high part of the STM each time when one of the registers STM_TIM0 to STM_TIM5 is read. Thus, STM_CAP holds the upper value of the timer at exactly the

Data Sheet 51 V1.0, 2008-04

TC1762

Preliminary Functional Description same time when the lower part is read. The second read operation would then read the content of the STM_CAP to get the complete timer value.

The STM can also be read in sections from seven registers, STM_TIM0 through

STM_TIM6, that select increasingly higher-order 32-bit ranges of the STM. These can be viewed as individual 32-bit timers, each with a different resolution and timing range.

The content of the 56-bit System Timer can be compared with the content of two compare values stored in the STM_CMP0 and STM_CMP1 registers. Interrupts can be generated on a compare match of the STM with the STM_CMP0 or STM_CMP1 registers.

The maximum clock period is 2

56 × f

STM

. At f

STM

= 80 MHz, for example, the STM counts

28.56 years before overflowing. Thus, it is capable of timing the entire expected product life-time of a system without overflowing continuously.

Figure 3-12 shows an overview on the System Timer with the options for reading parts

of the STM contents.

Data Sheet 52 V1.0, 2008-04

TC1762

Functional Description Preliminary

STMIR1

Interrupt

Control

STMIR0

Clock

Control

Enable /

Disable f

STM

Address

Decoder

PORST

STM_CMP0

31 23 15

Compare Register 0

7

STM_CMP1

31

0

23 15

Compare Register1

7

55 47 39 31 23

56-Bit System Timer

15

STM Module

7

0

0

00

H

00

H

STM_TIM5

STM_TIM4

STM_TIM3

STM_TIM2

STM_TIM1

STM_TIM0

STM_CAP

STM_TIM6

MCB06185

Figure 3-12 General Block Diagram of the STM Module Registers

Data Sheet 53 V1.0, 2008-04

TC1762


3.16

Watchdog Timer

The WDT provides a highly reliable and secure way to detect and recover from software or hardware failure. The WDT helps to abort an accidental malfunction of the TC1762 in a user-specified time period. When enabled, the WDT will cause the TC1762 system to be reset if the WDT is not serviced within a user-programmable time period. The CPU must service the WDT within this time interval to prevent the WDT from causing a

TC1762 system reset. Hence, routine service of the WDT confirms that the system is functioning as expected.

In addition to this standard “Watchdog” function, the WDT incorporates the End-of-

Initialization (Endinit) feature and monitors its modifications. A system-wide line is connected to the WDT_CON0.ENDINIT bit, serving as an additional write-protection for critical registers (besides Supervisor Mode protection). Registers protected via this line can only be modified when Supervisor Mode is active and bit ENDINIT = 0.

A further enhancement in the TC1762’s WDT is its reset prewarning operation. Instead of resetting the device upon the detection of an error immediately (the way that standard

Watchdogs do), the WDT first issues a Non-Maskable Interrupt (NMI) to the CPU before resetting the device at a specified time period later. This step gives the CPU a chance to save the system state to the memory for later investigation of the cause of the malfunction; an important aid in debugging.

Features

• 16-bit Watchdog counter

• Selectable input frequency: f

SYS

/256 or f

SYS

/16384

• 16-bit user-definable reload value for normal Watchdog operation, fixed reload value for Time-Out and Prewarning Modes

• Incorporation of the ENDINIT bit and monitoring of its modifications

• Sophisticated Password Access mechanism with fixed and user-definable password fields

• Proper access always requires two write accesses. The time between the two accesses is monitored by the WDT and is limited.

• Access Error Detection: Invalid password (during first access) or invalid guard bits

(during second access) trigger the Watchdog reset generation

• Overflow Error Detection: An overflow of the counter triggers the Watchdog reset generation.

• Watchdog function can be disabled; access protection and ENDINIT monitor function remain enabled.

• Double Reset Detection: If a Watchdog induced reset occurs twice, a severe system malfunction is assumed and the TC1762 is held in reset until a power-on or hardware reset occurs. This prevents the device from being periodically reset if, for instance, connection to the external memory has been lost such that system initialization could not even be performed.

Data Sheet 54 V1.0, 2008-04

TC1762


• Important debugging support is provided through the reset prewarning operation by first issuing an NMI to the CPU before finally resetting the device after a certain period of time.

3.17

System Control Unit

The System Control Unit (SCU) of the TC1762 handles several system control tasks.

The system control tasks of the SCU are:

• Clock system selection and control

• Reset and boot operation control

• Power management control

• Configuration input sampling

• External Request Unit

• System clock output control

• On-chip SRAM parity control

• Pad driver temperature compensation control

• Emergency stop input control for GPTA outputs

• GPTA input IN1 control

• Pad test mode control for dedicated pins

• ODCS level 2 trace control

• NMI control

• Miscellaneous SCU control

Data Sheet 55 V1.0, 2008-04

TC1762


3.18

Boot Options

The TC1762 booting schemes provide a number of different boot options for the start of code execution.

Table 3-2

shows the boot options available in the TC1762.

Table 3-2 TC1762 Boot Selections

BRKIN HWCFG

[3:0]

TESTMODE Type of Boot BootROM

Exit Jump

Address

Normal Boot Options

1 0000

0001

0010

0011

1111

B

B

B

B

B

1 Enter bootstrap loader mode 1:

Serial ASC0 boot via ASC0 pins

D400 0000

H

Enter bootstrap loader mode 2:

Serial CAN boot via P3.12 and

P3.13 pins

Start from internal PFLASH

Alternate boot mode (ABM): Start from internal PFLASH after CRC check is correctly executed; enter a serial bootstrap loader mode

1)

if

CRC check fails

Enter bootstrap loader mode 3:

Serial ASC0 boot via P3.12 and

P3.13 pins

A000 0000

H

Defined in

ABM header or D400 0000

H

D400 0000

H others

Debug Boot Options

Reserved; execute stop loop –

0 0000

B others

1 irrel.

Tri-state chip

Reserved; execute stop loop

–

–

1) The type of the alternate bootstrap loader mode is selected by the value of the SCU_SCLIR.SWOPT[2:0] bit field, which contains the levels of the P0.[2:0] latched in with the rising edge of the HDRST.

Data Sheet 56 V1.0, 2008-04

TC1762


3.19

Power Management System

The TC1762 power management system allows software to configure the various processing units so that they automatically adjust to draw the minimum necessary power for the application. There are three power management modes:

• Run Mode

• Idle Mode

• Sleep Mode

The operation of each system component in each of these states can be configured by software. The power-management modes provide flexible reduction of power consumption through a combination of techniques, including stopping the CPU clock, stopping the clocks of other system components individually, and individually clockspeed reduction of some peripheral components.

Besides these explicit software-controlled power-saving modes, special attention has been paid to automatic power-saving in those operating units which are not required at a certain point of time, or idle in the TC1762. In that case, they are shut off automatically until their operation is required again.

Table 3-3 describes the features of the power management modes.

Table 3-3 Power Management Mode Summary

Mode

Run

Idle

Sleep

Description

The system is fully operational. All clocks and peripherals are enabled, as determined by software.

The CPU clock is disabled, waiting for a condition to return it to Run

Mode. Idle Mode can be entered by software when the processor has no active tasks to perform. All peripherals remain powered and clocked.

Processor memory is accessible to peripherals. A reset, Watchdog

Timer event, a falling edge on the NMI pin, or any enabled interrupt event will return the system to Run Mode.

The system clock signal is distributed only to those peripherals programmed to operate in Sleep Mode. The other peripheral module will be shut down by the suspend signal. Interrupts from operating peripherals, the Watchdog Timer, a falling edge on the NMI pin, or a reset event will return the system to Run Mode. Entering this state requires an orderly shut-down controlled by the Power Management

State Machine.

In typical operation, Idle Mode and Sleep Mode may be entered and exited frequently during the run time of an application. For example, system software will typically cause the CPU to enter Idle Mode each time it has to wait for an interrupt before continuing its tasks. In Sleep Mode and Idle Mode, wake-up is performed automatically when any

Data Sheet 57 V1.0, 2008-04

TC1762

Preliminary Functional Description enabled interrupt signal is detected, or when the count value (WDT_SR.WDTTIM) changes from 7FFF

H

to 8000

H

.

3.20

On-Chip Debug Support

Figure 3-13 shows a block diagram of the TC1762 OCDS system.

OCDS

L1

BCU

SPB

Peripheral

Unit 1

SPB

Peripheral

Unit n OCDS2[15:0]

16

OCDS

L2

TriCore

OCDS

L1

Watchdog

Timer

TDO

TDI

TMS

TCK

TRST

BRKIN

BRKOUT

JTAG

Controller

OSCU

JDI

Debug

I/F

MCBS

Break

Switch

Figure 3-13 OCDS System Block Diagram

The TC1762 basically supports three levels of debug operation:

• OCDS Level 1 debug support



Data Sheet 58

DMA

MCB06195

V1.0, 2008-04

TC1762


OCDS Level 1 Debug Support

The OCDS Level 1 debug support is mainly assigned for real-time software debugging purposes which have a demand for low-cost standard debugger hardware.

The OCDS Level 1 is based on a JTAG interface that is used by the external debug hardware to communicate with the system. The on-chip Cerberus module controls the interactions between the JTAG interface and the on-chip modules. The external debug hardware may become master of the internal buses, and read or write the on-chip register/memory resources. The Cerberus also makes it possible to define breakpoint and trigger conditions as well as to control user program execution (run/stop, break, single-step).


The OCDS Level 2 debug support makes it possible to implement program tracing capabilities for enhanced debuggers by extending the OCDS Level 1 debug functionality with an additional 16-bit wide trace output port with trace clock. With the trace extension, the following four trace capabilities are provided (only one of the three trace capabilities can be selected at a time):

• Trace of the CPU program flow

• Trace of the DMA Controller transaction requests

• Trace of the DMA Controller Move Engine status information


The OCDS Level 3 debug support is based on a special TC1766 emulation device, the

TC1766ED, which provides additional features required for high-end emulation purposes. The TC1766ED is a device which includes the TC1766 product chip and additional emulation extension hardware in a package with the same footprint as the

TC1766.

Data Sheet 59 V1.0, 2008-04

TC1762


3.21

Clock Generation and PLL

The TC1762 clock system performs the following functions:

• Acquires and buffers incoming clock signals to create a master clock frequency

• Distributes in-phase synchronized clock signals throughout the TC1762’s entire clock tree

• Divides a system master clock frequency into lower frequencies required by the different modules for operation.

• Dynamically reduces power consumption during operation of functional units

• Statically reduces power consumption through programmable power-saving modes

• Reduces electromagnetic interference (EMI) by switching off unused modules

The clock system must be operational before the TC1762 can function, so it contains special logic to handle power-up and reset operations. Its services are fundamental to the operation of the entire system, so it contains special fail-safe logic.

Features

• PLL operation for multiplying clock source by different factors

• Direct drive capability for direct clocking

• Comfortable state machine for secure switching between basic PLL, direct or prescaler operation

• Sleep and Power-Down Mode support

The TC1762 Clock Generation Unit (CGU) as shown in

Figure 3-14 allows a very

flexible clock generation. It basically consists of an main oscillator circuit and a Phase-

Locked Loop (PLL). The PLL can converts a low-frequency external clock signal from the oscillator circuit to a high-speed internal clock for maximum performance.

The system clock f

SYS

is generated from an oscillator clock f

OSC

in either one of the four hardware/software selectable ways:

• Direct Drive Mode (PLL Bypass):

In Direct Drive Mode, the TC1762 clock system is directly driven by an external clock signal. input, i.e. f

CPU

= f

OSC

and f

SYS

= f

OSC

. This allows operation of the TC1762 with a reasonably small fundamental mode crystal.

• VCO Bypass Mode (Prescaler Mode):

In VCO Bypass Mode, f

CPU

and f

SYS

are derived from f

OSC

by the two divider stages,

P-Divider and K-Divider. The system clock f

SYS

is equal to f

CPU

.

• PLL Mode:

In PLL Mode, the PLL is running. The VCO clock f

VCO

is derived from f

OSC

, divided by the P factor, multiplied by the PLL (N-Divider). The clock signals f

CPU

and f

SYS

are derived from f

VCO

by the K-Divider. The system clock f

SYS

is equal to f

CPU

.

• PLL Base Mode:

In PLL Base Mode, the PLL is running at its VCO base frequency and f

CPU

and f

SYS

Data Sheet 60 V1.0, 2008-04

TC1762

Preliminary Functional Description are derived from f

VCO

only by the K-Divider. In this mode, the system clock f

SYS

is equal to f

CPU

.

XTAL1

XTAL2

Oscillator

Circuit f

OSC

Osc. Run

Detect.

P

Divider

Clock Generation Unit (CGU)

≥

1

Phase

Detect.

VCO

PLL

N

Divider f

VCO

1

0

M

U

X

1:1

Divider

K:1

Divider

M

U

X f

SYS f

CPU

Lock

Detector

BYPASS

OGC MOSC OSCR PDIV

[2:0]

OSC

DISC

PLL_

LOCK

Register

OSC_CON

OSC_

BYPASS

NDIV

[6:0]

VCO_

SEL[1:0]

System Control Unit (SCU)

VCO_

BYPASS

Register PLL_CLC

KDIV

[3:0]

SYS

FSL

PLL_

BYPASS

MCA06083

Figure 3-14 Clock Generation Unit

Recommended Oscillator Circuits

The oscillator circuit, a Pierce oscillator, is designed to work with both, an external crystal oscillator or an external stable clock source. It basically consists of an inverting amplifier and a feedback element with XTAL1 as input, and XTAL2 as output.

When using a crystal, a proper external oscillator circuitry must be connected to both pins, XTAL1 and XTAL2. The crystal frequency can be within the range of 4 MHz to 25 MHz. Additionally, it is necessary to have two load capacitances C

X1

and C

X2

, and depending on the crystal type, a series resistor R

X2

, to limit the current. A test resistor R

Q may be temporarily inserted to measure the oscillation allowance (negative resistance) of the oscillator circuitry. R

Q

values are typically specified by the crystal vendor. The C

X1 and C

X2

values shown in Figure 3-15 can be used as starting points for the negative

resistance evaluation and for non-productive systems. The exact values and related operating range are dependent on the crystal frequency and have to be determined and optimized together with the crystal vendor using the negative resistance method.

Data Sheet 61 V1.0, 2008-04

TC1762


Oscillation measurement with the final target system is strongly recommended to verify the input amplitude at XTAL1 and to determine the actual oscillation allowance (margin negative resistance) for the oscillator-crystal system.

When using an external clock signal, the signal must be connected to XTAL1. XTAL2 is left open (unconnected). The external clock frequency can be in the range of 0 - 40 MHz if the PLL is bypassed, and 4 - 40 MHz if the PLL is used.

The oscillator can also be used in combination with a ceramic resonator. The final circuitry must also be verified by the resonator vendor.

Figure 3-15 shows the recommended external oscillator circuitries for both operating

modes, external crystal mode and external input clock mode. A block capacitor is recommended to be placed between V

DDOSC

/ V

DDOSC3

and V

SSOSC

.

V

DDOSC

V

DDOSC3

V

DDOSC

V

DDOSC3 f

OSC

4 - 25

MHz

R

Q

C

X1

XTAL1

TC1762

Oscillator

R

X2

XTAL2

C

X2

Fundamental

Mode Crystal

V

SSOSC

Crystal Frequency

4 MHz

8 MHz

12 MHz

16 - 25 MHz

C

X1

, C

X2

1)

33 pF

18 pF

12 pF

10 pF

1) Note that these are evaluation start values!

0

0

R

X2

1)

0

0

External Clock

Signal 4 - 40

MHz

XTAL1

TC1762

Oscillator

XTAL2 f

OSC

V

SSOSC

MCS06084

Figure 3-15 Oscillator Circuitries

Note: For crystal operation, it is strongly recommended to measure the negative resistance in the final target system (layout) to determine the optimum parameters for the oscillator operation. Please refer to the minimum and maximum values of the negative resistance specified by the crystal supplier.

Data Sheet 62 V1.0, 2008-04

TC1762


3.22

Power Supply

The TC1762 has several power supply lines for different voltage classes:

• 1.5 V: Core logic, oscillator and A/D converter supply

• 3.3 V: I/O ports, Flash memories, oscillator, and A/D converter supply with reference voltages

Figure 3-16 shows the power supply concept of the TC1762 with the power supply pins

and its connections to the functional units.

V

DDM

(3.3V)

V

SSM

2

V

AREF

(3.3V)

V

AGND

2

V

DDAF

(1.5V)

V

SSAF

2

V

DDMF

(3.3V)

V

SSMF

2

V

FAREF

(3.3V)

V

FAGND

2

TC1762

ADC FADC

V

SSA

1

V

DDA

(1.5 V)

1

PLL

Core

Ports

9

V

SS

7

V

DD

(1.5 V)

8

V

DDP

(3.3 V)

Flash

Memories

1

V

DDFL3

3.3 V

OSC

3

V

V

DDOSC3

(3.3 V)

DDOSC

(1.5 V)

V

SSOSC

TC1762 PwrSupply

Figure 3-16 Power Supply Concept of TC1762

Data Sheet 63 V1.0, 2008-04

TC1762


3.23

Identification Register Values

Table 3-4 shows the address map and reset values of the TC1762 Identification

Registers.

Table 3-4

Short Name

SCU_ ID

MANID

CHIPID

RTID

SBCU_ID

STM_ID

CBS_ JDPID

MSC0_ ID

ASC0_ ID

ASC1_ ID

GPTA0_ ID

DMA_ID

CAN_ID

SSC0_ ID

FADC_ ID

ADC0_ID

MLI0_ ID

MCHK_ ID

CPS_ID

CPU_ID

PMU_ID

FLASH_ID

DMI_ID

PMI_ID

TC1762 Identification Registers

Address

F000 0008

H

F000 0070

H

F000 0074

H

F000 0078

H

F000 0108

F000 0208

F000 0408

F010 0108

F010 C008

F010 C208

F7E0 FF08

F7E1 FE18

F800 0508

H

H

H

F000 0808

H

F000 0A08

H

F000 0B08

H

F000 1808

H

F000 3C08

H

F000 4008

H

H

F010 0308

H

F010 0408

H

H

F800 2008

H

H

H

H

H

F87F FC08

H

F87F FD08

H

Reset Value

002C C002

H

0000 1820

H

0000 8B02

H

0000 0001

H

0000 0011

H

0000 0007

H

0000 6A0A

H

0000 C006

H

0000 6307

H

0028 C001

H

0000 4402

H

0000 4402

H

0029 C004

H

001A C012

H

002B C012

H

0000 4510

H

0027 C012

H

0030 C001

H

0025 C006

H

001B C001

H

0015 C006

H

000A C005

H

002E C012

H

0041 C002

H

0008 C004

H

000B C004

H

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Stepping

-

-

AA-Step

AB-Step

AC-Step

Data Sheet 64 V1.0, 2008-04

TC1762

Preliminary

Table 3-4

Short Name

LBCU_ID

LFI_ID

TC1762 Identification Registers

Address

F87F FE08

H

F87F FF08

H

Reset Value

000F C005

H

000C C005

H

Functional Description

-

-

Stepping

Data Sheet 65 V1.0, 2008-04

TC1762

Preliminary Electrical Parameters

4 Electrical Parameters

Chapter 4 provides the characteristics of the electrical parameters which are

implementation-specific for the TC1762.

4.1

General Parameters

The general parameters are described here to aid the users in interpreting the parameters mainly in

Section 4.2

and

Section 4.3

. The absolute maximum ratings and

its operating conditions are provided for the appropriate setting in the TC1762.

4.1.1

Parameter Interpretation

The parameters listed in this section partly represent the characteristics of the TC1762 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are marked with an two-letter abbreviation in column “Symbol”:

• CC

Such parameters indicate Controller Characteristics which are a distinctive feature of the TC1762 and must be regarded for a system design.

• SR

Such parameters indicate System Requirements which must provided by the microcontroller system in which the TC1762 designed in.

Data Sheet 66 V1.0, 2008-04

TC1762


4.1.2

Pad Driver and Pad Classes Summary

This section gives an overview on the different pad driver classes and its basic characteristics. More details (mainly DC parameters) are defined in

Section 4.2.1

.

Table 4-1 Pad Driver and Pad Classes Overview

Class Power

Supply

Type Sub Class Speed

Grade

Load Leakage

1)

A 3.3V

LVTTL

I/O,

LVTTL outputs

A1

(e.g. GPIO)

A4

(e.g. Trace

Clock)

6 MHz 100 pF 500 nA

A2

(e.g. serial

I/Os)

A3

(e.g. BRKIN,

BRKOUT)

40

MHz

66 or

80

MHz

2)

66 or

80

MHz

2)

50 pF

50 pF

6

6

µA

µA

25 pF 6

µA

Termination

No

Series termination recommended


(for f > 25 MHz)


C 3.3V

LVDS – 50

MHz

– Parallel termination

3)

100

Ω ± 10%

,

D – Analog inputs, reference voltage inputs

1) Values are for T

Jmax

= 150 °C.

2) This value corresponds to the operating frequency of the device, which depending on the derivative, can be

66 or 80 MHz.

3) In applications where the LVDS pins are not used (disabled), these pins must be either left unconnected, or properly terminated with the differential parallel termination of 100

Ω ± 10%.

Data Sheet 67 V1.0, 2008-04

TC1762


4.1.3

Absolute Maximum Ratings

Table 4-2 shows the absolute maximum ratings of the TC1762 parameters.

Table 4-2 Absolute Maximum Rating Parameters

Parameter Symbol Limit Values Unit Notes

Min.

Max.

Ambient temperature

Storage temperature

Junction temperature

T

A

T

ST

T

J

V

DD

SR -40

SR -65

SR -40

125

150

150

°C

Under bias

°C

–

°C

Under bias

Voltage at 1.5 V power supply pins with respect to V

SS

1)

Voltage at 3.3 V power supply pins with respect to V

SS

2)

Voltage on any Class A input pin and dedicated input pins with respect to V

SS

V

V

DDP

IN

SR –

SR –

SR -0.5

2.25

3.75

V

DDP

+ 0.5

or max. 3.7

V

V

V

–

–

Whatever is lower

Voltage on any Class D analog input pin with respect to V

AGND

Voltage on any Class D analog input pin with respect to V

SSAF

V

V

V

V

AIN,

AREFx

AINF,

FAREF

SR -0.5

SR -0.5

V

V

DDM

+ 0.5

or max. 3.7

DDMF

+ 0.5

or max. 3.7

V

V

Whatever is lower

Whatever is lower

CPU & LMB Bus

Frequency

3)4) f

CPU

SR – 66 or 80 MHz –

FPI Bus Frequency

3)4)

f

SYS

SR – 66 or 80 MHz

5)

1) Applicable for V

DD

, V

DDOSC

, V

DDPLL

, and V

DDAF

.

2) Applicable for V

DDP

, V

DDFL3,

V

DDM

, and V

DDMF

.

3) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter parameters.

4) This value depend on the derivative and the operating frequency it is designated for. For a device operating at 66 MHz, the absolute maximum frequency is also 66 MHz. Similarly, for a device operating at 80 MHz, the absolute maximum frequency is 80 MHz.

5) The ratio between f

CPU

and f

SYS

is fixed at 1:1.

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute

Data Sheet 68 V1.0, 2008-04

TC1762

Preliminary Electrical Parameters maximum rating conditions for extended periods may affect device reliability.

During absolute maximum rating overload conditions ( V

IN

V

IN

< V

SS

) the voltage on the related V

> related

DD

pins with respect to ground ( V

V

DD

or

SS

) must not exceed the values defined by the absolute maximum ratings.

4.1.4

Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct operation of the TC1762. All parameters specified in the following table refer to these operating conditions, unless otherwise noted.

Table 4-3 Operating Condition Parameters

Parameter Symbol

Digital supply voltage

1)

SR

Limit

Values

Min.

Max.

1.42

1.58

2)

V

DD

V

DDOSC

V

DDP

V

DDOSC3

SR

Digital ground voltage

Ambient temperature under bias

Analog supply voltages

CPU clock

Short circuit current

Absolute sum of short circuit currents of a pin group (see

Table 4-4 )

Absolute sum of short circuit currents of the device f

V

V

T

–

DDFL3

SS

A

CPU

I

SC

Σ| I

SC

|

Σ|

I

SC

|

SR

SR

SR

–

SR –

SR -5

4)

SR –

SR

Unit Notes

Conditions

V –

3.13

3.47

3)

V

3.13

3.47

3)

V –

0 V –

-40 +125

°C

–

For Class A pins

(3.3V

± 5%)

–

–

80

5)

+5

20

– See separate specification

Page 4-75

,

Page 4-82

MHz – mA

6) mA See note

7)

100 mA See note

7)

Data Sheet 69 V1.0, 2008-04

TC1762


Table 4-3 Operating Condition Parameters

Parameter Symbol Limit

Values

Unit Notes

Conditions

Min.

Max.

Inactive device pin current

(V

DD

= V

DDP

= 0)

External load capacitance

I

C

ID

L

SR

SR

-1

–

1

See

DC chara cterist ics mA Voltage on all power supply pins V

DDx

= 0 pF Depending on pin class

1) Digital supply voltages applied to the TC1762 must be static regulated voltages which allow a typical voltage swing of

±5%.

2) Voltage overshoot up to 1.7 V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100

µs and the cumulated summary of the pulses does not exceed 1 h.

3) Voltage overshoot to 4 V is permissible at Power-Up and PORST low, provided the pulse duration is less than

100


4) The TC1762 uses a static design, so the minimum operation frequency is 0 MHz. Due to test time restriction no lower frequency boundary is tested, however.

5) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter parameters.

6) Applicable for digital outputs.

7) See additional document “TC1796 Pin Reliability in Overload“ for overload current definitions.

Data Sheet 70 V1.0, 2008-04

TC1762


6

7

8

1

2

3

4

5

Table 4-4

Group

Pin Groups for Overload/Short-Circuit Current Sum Parameter

Pins

TRCLK, P5.[7:0], P0.[7:6], P0.[15:14]

P0.[13:12], P0.[5:4], P2.[13:8], SOP0A, SON0, FCLP0A, FCLN0

P0.[11:8], P0.[3:0], P3.[13:11]

P3[10:0], P3.[15:14]

HDRST, PORST, NMI, TESTMODE, BRKIN, BRKOUT, BYPASS, TCK,

TRST, TDO, TMS, TDI, P1.[7:4]

P1.[3:0], P1.[11:8], P4.[3:0]

P2.[7:0], P1.[14:12]

P5.[15:8]

Data Sheet 71 V1.0, 2008-04

TC1762


4.2

DC Parameters

The electrical characteristics of the DC Parameters are detailed in this section.

4.2.1

Input/Output Pins

Table 4-5 provides the characteristics of the input/output pins of the TC1762.

Table 4-5 Input/Output DC-Characteristics (Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Conditions

General Parameters

Pull-up current

1)

| I

PUH

Min.

| CC 10

20

Max.

100

200

µA

µA

V

IN

< V

IHAmin

; class A1/A2/Input pads.

V

IN

< V

IHAmin

; class A3/A4 pads.

Pull-down

current

1)

| I

PDL

| CC 10

20

150

200

µA

µA

Pin capacitance

1)

(Digital I/O)

C

IO

CC – 10 pF

Input only Pads ( V

DDP

= 3.13 to 3.47 V = 3.3V

±5%)

Input low voltage V

ILA

SR -0.3

0.34

× class A1/A2 pins V

DDP

V

Input high voltage class A1/A2 pins

V

IHA

SR 0.64

×

V

DDP

V

DDP

+

0.3 or

V max. 3.6

Ratio V

IL

/ V

IH

Input low voltage class A3 pins

V

ILA3

CC 0.53

SR –

Input high voltage class A3 pins

V

IHA3

SR 2.0

Input hysteresis HYSA CC 0.1

×

V

DDP

Input leakage current

I

OZI

CC –

–

0.8

–

–

±3000

±6000

–

V

V

V f

V

IN

> V

ILAmax

; class A1/A2/Input pads.

V

IN

> V

ILAmax

; class A3/A4 pads.

T

–

= 1 MHz

A

= 25

°C

Whatever is lower

–

–

–

2)5)

nA (( V

DDP

/2)-1) < V

IN

< (( V

DDP otherwise

3)

/2)+1)

Data Sheet 72 V1.0, 2008-04

TC1762


Table 4-5 Input/Output DC-Characteristics (cont’d)(Operating Conditions apply)

Parameter

Min.

Max.

Class A Pads ( V

DDP

= 3.13 to 3.47 V = 3.3V

±5%)

Output low voltage

4)

V

OLA

CC – 0.4

Output high voltage

3)

Symbol

V

OHA

CC 2.4

V

DDP

-

0.4

Limit Values Unit Test Conditions

–

–

V

V

V

I

OL

= 2 mA for strong driver mode, (Not applicable to

Class A1 pins)

I

OL

= 1.8 mA for medium driver mode, A2 pads

I

OL

= 1.4 mA for medium

I driver mode, A1 pads

OL

= 370

µA for weak driver mode

I

OH

= -2 mA for strong driver mode, (Not applicable to Class A1 pins)

I

OH

= -1.8 mA for medium

I driver mode, A1/A2 pads

OH

= -370


I

OH

= -1.4 mA for strong driver mode, (Not applicable to Class A1 pins)

I

OH

= -1 mA for medium

I driver mode, A1/A2 pads

OH

= -280


Input low voltage class A1/2 pins

Input high voltage class A1/2 pins

V

V

ILA

IHA

SR -0.3

SR 0.64

×

V

DDP

0.34

×

V

DDP

V

DDP

+

0.3 or

3.6

V

V

–

Whatever is lower

Ratio V

IL

/ V

IH

CC 0.53

Input hysteresis HYSA CC 0.1

×

V

DDP

–

–

–

V

–

2)5)

Data Sheet 73 V1.0, 2008-04

TC1762


Table 4-5 Input/Output DC-Characteristics (cont’d)(Operating Conditions apply)


Input leakage current Class

A2/3/4 pins

Input leakage current

Class A1 pins

I

I

OZA24

OZA1

Min.

CC –

CC –

Max.

±3000

±6000

±500

Class C Pads ( V

DDP

= 3.13 to 3.47 V = 3.3V

±5%)

Output low voltage

Output high voltage

V

OL

V

OH

CC 815

CC 1545

Output differential voltage

Output offset voltage

V

OD

V

OS

Limit Values Unit Test Conditions

CC 150

CC 1075

600

1325 nA (( mV

V

DDP

/2)-1) < V

<(( V

DDP otherwise

3)

/2)+1) nA 0 V < V

IN

< V

DDP

IN mV Parallel termination mV

100

Ω ± 1% mV

Output impedance R

0

Class D Pads see ADC Characteristics

CC 40 140 –

– – – –

1) Not subject to production test, verified by design / characterization.

2) The pads that have spike filter function in the input path: PORST, HDRST, NMI do not have hysteresis.

3) Only one of these parameters is tested, the other is verified by design characterization

4) Max. resistance between pin and next power supply pin 25

Ω for strong driver mode

(verified by design characterization).

5) Function verified by design, value is not subject to production test - verified by design/characterization.

Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses switching due to external system noise.

Data Sheet 74 V1.0, 2008-04

TC1762


4.2.2

Analog to Digital Converter (ADC0)

Table 4-6 provides the characteristics of the ADC module in the TC1762.

Table 4-6

Parameter

Analog supply voltage

ADC Characteristics (Operating Conditions apply)

Symbol

Min.

Limit Values Unit Test Conditions /

Remarks

V

V

DDM

DD

SR

SR

3.13

1.42

Typ.

Max.

3.3

3.47

1)

1.5

1.58

2)

V

V

–

Power supply for

ADC digital part, internal supply

Analog ground voltage

V

SSM

Analog reference voltage

17)

V

AREFx

SR -0.1

SR V

AGNDx

1V

+

–

V

DDM

0.1

V

DDM

0.05

1)

+

3)4)

V

V

–

–

Analog reference ground

17)

Analog reference voltage range

5)17)

Analog input voltage range

V

DDM supply current

Power-up calibration time

V

AGNDx

V

AREFx

-

V

AGNDx

V

AIN

I

DDM t

PUC

Internal ADC clocks

Sample time f

BC f

ANA t

S

SR

SR

SR

SR

V

SSMx

-

0.05V

V

DDM

/2

V

AGNDx

CC –

CC 2

0

–

CC 0.5

– 10

CC 4

× (CHCONn.STC

+ 2)

× t

BC

8

× t

BC

– –

V

AREF

- 1 V

V

DDM

+ 0.05

V

V

AREFx

V

2.5

4

–

–

3840

40 mA rms f

ADC

CLK

MHz

µs

–

–

6)

– f

BC

= f

ANA

× 4

MHz f

ANA

µs

–

= f

BC

/ 4

Data Sheet 75 V1.0, 2008-04

TC1762


Table 4-6

Parameter

ADC Characteristics (cont’d) (Operating Conditions apply)

Conversion time

Total unadjusted error

4)

DNL error

11)5)

t

Symbol

C

TUE

7)

TUE

DNL

Limit Values Unit Test Conditions /

Remarks

CC

Min.

t

S

+ 40

× t

Typ.

Max.

BC

+ 2

× t

DIV

µs

For 8-bit conversion t

S

+ 48

× t

S

CC –

–

–

–

CC –

+ 56

× t t

BC

BC

+ 2

×

+ 2

× t

DIV t

DIV

µs

For 10-bit conversion

µs

For 12-bit conversion

–

–

±1

±2

LSB For 8-bit conv.

LSB For 10-bit conv.

–

–

±4

±8



10)9)

8)9)

±1.5 ±3.0


12)

9)

INL error

11)5)

Gain error

11)5)

Offset error

11)5)

TUE

INL

TUE

GAIN

TUE

OFF

CC –

CC –

CC –

±1.5 ±3.0

LSB

For 12-bit conv.

12)

9)

±0.5 ±3.5

LSB

For 12-bit conv.

12)

9)

±1.0 ±4.0

LSB

For 12-bit conv.

12)

9)

Input leakage current at analog inputs AN0, AN1 and AN31.

see Figure 4-3

13)

I

OZ1

14)

CC –1000 –

–200

–200

–200

300 nA (0% V

DDM

) < V

IN

<

(2% V

DDM

)

400 nA (2% V

DDM

) < V

IN

<

(95% V

DDM

)

1000 nA (95% V

DDM

) < V

IN

< (98% V

DDM

)

3000 nA (98% V

DDM

) < V

IN

< (100% V

DDM

)

Data Sheet 76 V1.0, 2008-04

TC1762


Table 4-6

Parameter

Input leakage current at analog inputs AN2 to

AN30, see

Figure 4-3

Input leakage current at V

AREF

ADC Characteristics (cont’d) (Operating Conditions apply)

I

I

Symbol

OZ1

OZ2

14)

Min.

Limit Values

Typ.

Max.

CC –1000 –

–200

–200

–200

CC –

CC –

CC –

–

35

–

Unit Test Conditions /

Remarks

200 nA (0% V

DDM

) < V

IN

<

(2% V

DDM

)

300 nA (2% V

DDM

) < V

IN

<

(95% V

DDM

)

1000 nA (95% V

DDM

) < V

IN

< (98% V

DDM

)

3000 nA (98% V

DDM

) < V

IN

< (100% V

DDM

)

±1 µA

0 V < V

AREF

V

DDM,

no conversion

< running

75

25

µA rms pF

0 V <

V

9)

DDM

V

AREF

15)

< Input current at

V

AREF

17)

Total capacitance of the voltage reference inputs

16)17)

I

AREF

C

AREFTOT

Switched capacitance at the positive reference voltage

input

17)

Resistance of the reference voltage

input path

16)

C

AREFSW

R

AREF

Total capacitance of the analog inputs

16)

C

AINTOT

C

AINSW

Switched capacitance at the analog voltage inputs

CC –

CC –

CC –

CC –

15

1

–

–

20

1.5

25

7 pF k

Ω

500 Ohm increased for

AN[1:0] used as reference input

9)

pF

6)9)

pF

9)18)

9)19)

Data Sheet 77 V1.0, 2008-04

TC1762


Table 4-6 ADC Characteristics (cont’d) (Operating Conditions apply)


Min.

Limit Values

Typ.

Max.

Unit Test Conditions /

Remarks

ON resistance of the transmission gates in the analog voltage path

ON resistance for the ADC test

(pull-down for

AIN7)

R

AIN

R

AIN7T

CC –

CC 200

1 1.5

k

Ω

9)

300 1000

Ω

Test feature available only for

AIN7

9)

Current through resistance for the

ADC test (pulldown for AIN7)

I

AIN7T

CC – 15 rms

30 peak mA Test feature available only for

AIN7

9)

1) Voltage overshoot to 4 V are permissible, provided the pulse duration is less than 100


2) Voltage overshoot to 1.7 V are permissible, provided the pulse duration is less than 100


3) A running conversion may become inexact in case of violating the normal operating conditions (voltage overshoot).

4) If the reference voltage V

AREF

increases or the

V

DDM

V

DDM

decreases, so that

+ 0.07 V), then the accuracy of the ADC decreases by 4LSB12.

V

AREF

= ( V

DDM

+ 0.05 V to

5) If a reduced reference voltage in a range of V

DDM

/2 to V

DDM

is used, then the ADC converter errors increase.

If the reference voltage is reduced with the factor k (k<1), then TUE, DNL, INL Gain and Offset errors increase with the factor 1/k.

If a reduced reference voltage in a range of 1 V to V

DDM

/2 is used, then there are additional decrease in the

ADC speed and accuracy.

6) Current peaks of up to 6 mA with a duration of max. 2 ns may occur

7) TUE is tested at V

AREF

= 3.3 V, V

AGND

= 0 V and V

DDM

= 3.3 V

8) ADC module capability.


10) Value under typical application conditions due to integration (switching noise, etc.).

11) The sum of DNL/INL/Gain/Offset errors does not exceed the related TUE total unadjusted error.

12) For 10-bit conversions the DNL/INL/Gain/Offset error values must be multiplied with factor 0.25.

For 8-bit conversions the DNL/INL/Gain/Offset error values must be multiplied with 0.0625.

13) The leakage current definition is a continuous function, as shown in

Figure 4-3 . The numerical values defined

determine the characteristic points of the given continuous linear approximation - they do not define step function.

14) Only one of these parameters is tested, the other is verified by design characterization.

Data Sheet 78 V1.0, 2008-04

TC1762


15) I

AREF_MAX

is valid for the minimum specified conversion time. The current flowing during an ADC conversion with a duration of up to t

C

= 25

µs can be calculated with the formula

I

AREF_MAX

= Q

CONV

/ t

C

. Every conversion needs a total charge of Q

CONV

= 150pC from V

AREF

.

All ADC conversions with a duration longer than t

C

= 25

µs consume an I

AREF_MAX

= 6

µA.

16) For the definition of the parameters see also Figure 4-2 .

17) Applies to AIN0 and AIN1, when used as auxiliary reference inputs.

18) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead of this smaller capacitances are successively switched to the reference voltage.

19) The sampling capacity of the conversion C-Network is pre-charged to V

AREF

/2 before the sampling moment.

Because of the parasitic elements the voltage measured at AINx is lower then V

AREF

/2.

f

CLC

A/D Converter Module

Fractional

Divider f

DIV

Programmable

Clock Divider

(1:1) to (1:256) f

BC

1:4 f

ANA Programmable

Counter

Sample

Time t

S

Arbiter

(1:20) f

TIMER

CON.CTC

Control Unit

(Timer)

CHCONn.STC

Control/Status Logic

Interrupt Logic

External Trigger Logic

External Multiplexer Logic

Request Generation Logic

MCA04657_mod

Figure 4-1 ADC0 Clock Circuit

Data Sheet 79 V1.0, 2008-04

TC1762

Electrical Parameters Preliminary

R

EXT

V

AIN

= C

EXT

ANx

V

AGNDx

Analog Input Circuitry

R

AIN, On

R

AIN7T

C

AINTOT

- C

AINSW

C

AINSW

V

AREFx

V

AREF

V

AGNDx

Reference Voltage Input Circuitry

R

AREF, On

C

AREFTOT

- C

AREFSW

C

AREFSW

Analog_InpRefDiag

Figure 4-2 ADC0 Input Circuits

Data Sheet 80 V1.0, 2008-04

TC1762


Ioz1

3uA

AN0, AN1 and AN31

1uA

400nA

300nA

-200nA

2%

-1uA

Ioz1

3uA

AN2 to AN30

1uA

300nA

200nA

-200nA

2%

-1uA

Figure 4-3 ADC0 Analog Inputs Leakage

95%

V

IN

[V

DDM

98% 100%

%]

V

IN

[V

DDM

%]

95% 98% 100%

Data Sheet 81 V1.0, 2008-04

TC1762


4.2.3

Fast Analog to Digital Converter (FADC)

Table 4-7 provides the characteristics of the FADC module in the TC1762.

Table 4-7

Parameter

FADC Characteristics (Operating Conditions apply)

Symbol Limit Values Unit

Min.

Max.

Remarks

Conditions

DNL error

INL error

Gradient error

1)12)

E

DNL

E

INL

E

GRAD

CC –

CC –

CC –

±1

±4

±3

LSB

LSB

%

12)

12)

2)

With calibration, gain 1, 2

– ±5 %

Offset error

12)

E

OFF

3)

Reference error of internal V

FAREF

/2

Input leakage current at analog inputs

AN32 to AN35.

5)

see Figure 4-5

E

REF

I

OZ1

6)

–

CC –

–

CC –

–200

±6

±20

4)

±60

4)

±60

CC –1000 300

400

% mV mV mV nA nA

Without calibration gain 1, 2, 4

Without calibration gain 8

2)

With calibration

Without calibration

–

Analog supply voltages

Analog ground voltage

Analog reference voltage

Analog reference ground

Analog input voltage range

V

DDMF

V

DDAF

V

SSAF

V

FAREF

V

FAGND

V

AINF

–200

–200

SR 3.13

SR 1.42

SR -0.1

SR 3.13

SR

SR

V

0.05V

V

SSAF

-

FAGND

1000

3000

3.47

7)

1.58

8)

0.1

3.47

7)9)

V

SSAF

+0.05V

V

DDMF nA nA

V

V

V

V

V

V

–

–

(0% V

DDM

) < V

IN

<

(2% V

DDM

)

(2% V

DDM

) < V

IN

<

(95% V

DDM

)

(95% V

DDM

) < V

IN

<

(98% V

DDM

)

(98% V

DDM

) < V

IN

<

(100% V

DDM

)

–

Nominal 3.3 V

–

–

Data Sheet 82 V1.0, 2008-04

TC1762


Table 4-7 FADC Characteristics (cont’d)(Operating Conditions apply)

Parameter Symbol Limit Values

Min.

Max.

Unit Remarks

Conditions

Analog supply currents

Input current at each

V

FAREF


FAREF

11)


FAGND

Conversion time

I

DDMF

I

DDAF

I

FAREF

I

FOZ2

I

FOZ3 t

C

SR –

SR –

CC –

CC –

CC

9

17

150

±500

±8 mA mA

µA rms nA

µA

–

10)

Independent of conversion

0 V < V

IN

< V

DDMF

Converter Clock

Input resistance of the analog voltage path (Rn, Rp) f

ADC

R

FAIN

CC –

CC –

CC 100

21

80

200

CLK of f

ADC

For 10-bit conv.

MHz – k

Ω 12)

Channel Amplifier

Cutoff Frequency f

COFF

CC 2 MHz –

Settling Time of a

Channel Amplifier after changing ENN or ENP t

SET

CC 5

µsec

–

1) Calibration of the gain is possible for the gain of 1 and 2, and not possible for the gain of 4 and 8.

2) Calibration should be performed at each power-up. In case of continuous operation, calibration should be performed minimum once per week.

3) The offset error voltage drifts over the whole temperature range typically ±2 LSB.

4) Applies when the gain of the channel equals one. For the other gain settings, the offset error increases; it must be multiplied with the applied gain.

5) The leakage current definition is a continuous function, as shown in

Figure 4-5 . The numerical values defined

determine the characteristic points of the given continuous linear approximation - they do not define step function.

6) Only one of these parameters is tested, the other is verified by design characterization.

7) Voltage overshoot to 4 V are permissible, provided the pulse duration is less than 100


8) Voltage overshoot to 1.7 V are permissible, provided the pulse duration is less than 100

µs and the cumulated sum of the pulses does not exceed 1 h.

9) A running conversion may become inexact in case of violating the normal operating conditions (voltage overshoots).

10) Current peaks of up to 40 mA with a duration of max. 2 ns may occur

Data Sheet 83 V1.0, 2008-04

TC1762

Preliminary

11) This value applies in power-down mode.


Electrical Parameters

The calibration procedure should run after each power-up, when all power supply voltages and the reference voltage have stabilized. The offset calibration must run first, followed by the gain calibration.

FAINxN

V

FAGND

FAINxP

FADC Analog Input Stage

R

N

-

+

V

FAREF

/2

+

R

P

-

V

FAREF

V

FAREF

FADC Reference Voltage

Input Circuitry

I

FAREF

V

FAGND

FADC_InpRefDiag

Figure 4-4 FADC Input Circuits

Data Sheet 84 V1.0, 2008-04

TC1762


Ioz1

3uA

AN32 to AN35

1uA

400nA

300nA

-200nA

2%

-1uA

Figure 4-5 Analog Inputs AN32-AN35 Leakage

V

IN

[V

DDM

%]

95% 98% 100%

Data Sheet 85 V1.0, 2008-04

TC1762


4.2.4

Oscillator Pins

Table 4-8 provides the characteristics of the oscillator pins in the TC1762.

Table 4-8

Parameter

Oscillator Pins Characteristics (Operating Conditions apply)

Symbol Limit values Unit Test Conditions

Min.

Max.

Frequency Range f

OSC

CC 4 25 MHz –

Input low voltage at

XTAL1

1)

V

ILX

SR -0.2

0.3

×

V

DDOSC3

V –

Input high voltage at

XTAL1

1)

V

IHX

SR 0.7

×

V

DDOSC3

V

DDOSC3

+ 0.2

V –

Input current at XTAL1 I

IX1

CC –

±25 µA

0 V < V

IN

< V

DDOSC3

1) If the XTAL1 pin is driven by a crystal, reaching a minimum amplitude (peak-to-peak) of 0.3

×

V

DDOSC3

is necessary.

Note: It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits specified by the crystal supplier.

Data Sheet 86 V1.0, 2008-04

TC1762


4.2.5

Temperature Sensor

Table 4-9 provides the characteristics of the temperature sensor in the TC1762.

Table 4-9

Parameter

Temperature

Sensor Range

Start-up time after resets inactive

Temperature Sensor Characteristics (Operating Conditions apply)

Symbol Limit Values Unit Remarks t

T

SR

TSST

Min.

SR -40

SR

Max.

150

10

°C

µs

–

Temperature of the die at the sensor location

T

TS

CC

CC

T

TS

= (ADC_Code - 487)

× 0.396 - 40

°C 10-bit ADC result

T

TS

= (ADC_Code - 1948)

× 0.099 - 40 °C

12Bit ADC result

±10

°C Sensor

Inaccuracy

A/D Converter clock for DTS signal

T

TSA f

ANA

SR – 10 MHz Conversion with ADC0

Data Sheet 87 V1.0, 2008-04

TC1762


4.2.6

Power Supply Current

Table 4-10

provides the characteristics of the power supply current in the TC1762.

Table 4-10 Power Supply Current (Operating Conditions apply)


Min. Typ. Max.

Unit Test

Conditions /

Remarks

PORST low current at

V

DD

PORST low current at

V

DDP

I

I

DD_PORST

DDP_PORST

CC –

CC –

–

–

96

1)

138

2)

12

1)

13

2)

mA The PLL running at the base frequency mA The PLL running at the base frequency mA f

CPU

= 80MHz f

CPU

/ f

SYS

= 1:1

Active mode core supply current

3)4)

Active mode core supply current

3)4)

I

I

DD

DD

CC –

CC –

–

–

290

1)

330

2)

250

1)

300

2)

– mA f

CPU

= 66MHz f

CPU

/ f

SYS

= 1:1

Active mode analog supply current

Oscillator and PLL core power supply

Oscillator and PLL pads power supply

I

I

I

I

DDAx;

DDMx

DDOSC

DDOSC3

CC –

CC –

CC –

–

–

–

5

3.6

5) mA See

ADC0/FADC mA – mA –

FLASH power supply current

I

DDFL3

CC – – 45 mA –

LVDS port supply

(via V

DDP

)

6)

Maximum Allowed

Power Dissipation

7)

I

P

LVDS

Dmax

CC –

SR

– 25 mA LVDS pads active

P

D

× R

TJA

< 25°C – At worst case,

T

A

= 125 °C

1) Maximum value measured at T

A

= 125 °C.

2) Maximum value measured at T

J

= 150 °C.

3) Infineon Power Loop: CPU and PCP running, all peripherals active. The power consumption of each custom application will most probably be lower than this value, but must be evaluated separately.

4) The I

DD

decreases typically to 240mA if the f

CPU

is decreased to 40 MHz, at constant T

J

Infineon Max. Power Loop.

= 150 °C, for the

5) Estimated value; double-bonded at package level with V

DDP

.

6) In case the LVDS pads are disabled, the power consumption per pair is negligible (less than 1

µA).

7) For the calculation of the junction to ambient thermal resistance R

TJA

, see

Chapter 5.1

.

Data Sheet 88 V1.0, 2008-04

TC1762


4.3

AC Parameters

All AC parameters are defined with the temperature compensation disabled, which means that pads are constantly kept at the maximum strength.

4.3.1

Testing Waveforms

The testing waveforms for rise/fall time, output delay and output high impedance are shown in

Figure 4-6

,

Figure 4-7 and Figure 4-8 .

V

DDP

V

SS

90%

10% t

R

90% t

F

10% rise_fall

Figure 4-6 Rise/Fall Time Parameters

V

DDP

V

SS

V

DDE

/ 2 Test Points V

DDE

/ 2

Mct04881_LL.vsd

Figure 4-7 Testing Waveform, Output Delay

V

Load

+ 0.1 V

V

Load

- 0.1 V

Timing

Reference

Points

V

OH

- 0.1 V

V

OL

- 0.1 V

MCT04880_LL

Figure 4-8 Testing Waveform, Output High Impedance

Data Sheet 89 V1.0, 2008-04

TC1762


4.3.2

Output Rise/Fall Times

Table 4-11

provides the characteristics of the output rise/fall times in the TC1762.

Table 4-11 Output Rise/Fall Times (Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Conditions

Min.

Max.

Class A1 Pads

Rise/fall times

1)

Class A1 pads t

RA1

, t

FA1

50

140

18000

150

550

65000 ns Regular (medium) driver, 50 pF

Regular (medium) driver, 150 pF

Regular (medium) driver, 20 nF

Weak driver, 20 pF

Weak driver, 150 pF

Weak driver, 20 000 pF

Class A2 Pads

Rise/fall times

1)

Class A2 pads t

FA2

, t

FA2

3.3

6

5.5

16

50

140

18000

150

550

65000 ns Strong driver, sharp edge, 50 pF

Strong driver, sharp edge, 100pF

Strong driver, med. edge, 50 pF

Strong driver, soft edge, 50 pF

Medium driver, 50 pF

Medium driver, 150 pF

Medium driver, 20 000 pF

Weak driver, 20 pF

Weak driver, 150 pF

Weak driver, 20 000 pF

Class A3 Pads

Rise/fall times

1)

Class A3 pads t

FA3

, t

FA3

2.5

ns 50 pF

Class A4 Pads

Rise/fall times

1)

Class A4 pads

Class C Pads t

FA4

, t

FA4

2.0

ns 25 pF

Rise/fall times

Class C pads t rC,

t fC

2 ns

1) Not all parameters are subject to production test, but verified by design/characterization and test correlation.

Data Sheet 90 V1.0, 2008-04

TC1762


4.3.3

Power Sequencing

There is a restriction for the power sequencing of the 3.3 V domain as shown in

Figure 4-9 . It must always be higher than 1.5 V domain - 0.5 V. The gray area shows the

valid range for V

3.3V

relative to an exemplary V

1.5V

ramp. V

DDP

, V

DDOSC3

, V

DDM

, V

DDMF

,

V

DDFL3

belong to the 3.3 V domain. The V

DDM

and V

DDMF subdomains are connected with antiparallel ESD protection diodes. There are no other such connections between the subdomains. V

DD ,

V

DDOSC and V

DDAF

belong to the 1.5 V domain.

Power Supply Voltage

3.3V

V

3 .3

V

1 .5

1.5V

V al id

a re a fo r

V

3.

3

V al id

a re a fo r V

3.3

V

3 .3

> V

1 .5

- 0.5V

Time

V

D D P

(3.3V)

PORST

Time

PowerSeq

Figure 4-9 V

DDP

/ V

DD

Power Up Sequence

All ground pins V

SS

must be externally connected to one single star point in the system.

The difference voltage between the ground pins must not exceed 200 mV.

The PORST signal must be activated at latest before any power supply voltage falls below the levels shown on the figure below. In this case, only the memory row of a Flash memory that was the target of the write at the moment of the power loss will contain unreliable content. Additionally, the PORST signal should be activated as soon as possible. The sooner the PORST signal is activated, the less time the system operates outside of the normal operating power supply range.

Data Sheet 91 V1.0, 2008-04

Preliminary

TC1762


V

DDP

V

DDPmin

V

PORST3.3

Power Supply Voltage

3.3V

3.13V

V

DDP

-5%

2.9V

-12% t

PORST

V

DD

V

DDmin

V

PORST1.5min

1.5V

V

DD

1.42V

1.32V

-5%

-12% t t

PORST

PowerDown3.3_1.5_reset_only_LL.vsd

Figure 4-10 Power Down / Power Loss Sequence t

Data Sheet 92 V1.0, 2008-04

TC1762


4.3.4

Power, Pad and Reset Timing

Table 4-12

provides the characteristics of the power, pad and reset timing in the

TC1762.

Table 4-12 Power, Pad and Reset Timing Parameters


Min.

Limit Values

Max.

Unit

Min. V

DDP

voltage to ensure defined pad states

1)

Oscillator start-up time

2)

V

DDPPA

Minimum PORST active time after power supplies are stable at operating levels

HDRST pulse width t

OSCS t

POA t

HD

CC 0.6

CC –

SR 10

–

10

–

V ms ms

CC 1024 clock cycles

3)

SR –

– f

SYS

PORST rise time

Setup time to PORST rising edge

4)

Hold time from PORST rising edge

4)

Setup time to HDRST rising edge

5)

Hold time from HDRST rising edge

5)

t t t

POR t

POS t

POH

HDS

HDH

SR 0

SR 100

SR 0

SR 100 +

(2

× 1/ f

SYS

)

CC –

50

–

–

–

– ms ns ns ns ns

Ports inactive after PORST reset active

6)7) t

PIP

150 ns

Ports inactive after HDRST reset active

8)

Minimum threshold.

V

9)

DDP

PORST activation t

V

PI

PORST3.3

CC –

SR –

150 +

5

× 1/

2.9

f

SYS ns

V

Minimum

threshold.

V

DD

9)

PORST activation

Power-on Reset Boot Time

10)

V

PORST1.5

SR – 1.32

V

Hardware/Software Reset Boot Time at f

CPU

=80MHz

11) t t

BP

B

CC 2.15

CC 500

3.50

800 ms

µs

Hardware/Software Reset Boot Time at f

CPU

=66MHz

11)

t

B

CC 560 860

µs

1) This parameter is valid under assumption that PORST signal is constantly at low-level during the powerup/power-down of the V

DDP

.

Data Sheet 93 V1.0, 2008-04

TC1762


2) This parameter is verified by device characterization. The external oscillator circuitry must be optimized by the customer and checked for negative resistance as recommended and specified by crystal suppliers.

3) Any HDRST activation is internally prolonged to 1024 FPI bus clock ( f

SYS

) cycles.

4) Applicable for input pins TESTMODE, TRST, BRKIN, and TXD1A with noise suppression filter of PORST switched-on (BYPASS = 0).

5) The setup/hold values are applicable for Port 0 and Port 4 input pins with noise suppression filter of HDRST switched-on (BYPASS = 0), independently whether HDRST is used as input or output.


7) This parameter includes the delay of the analog spike filter in the PORST pad.


9) In case of power loss during internal flash write, prevents Flash write to random address.

10) Booting from Flash, the duration of the boot-time is defined between the rising edge of the PORST and the moment when the first user instruction has entered the CPU and its processing starts.

11) Booting from Flash, the duration of the boot time is defined between the following events:

1. Hardware reset: the falling edge of a short HDRST pulse and the moment when the first user instruction has entered the CPU and its processing starts, if the HDRST pulse is shorter than 1024

×

If the HDRST pulse is longer than 1024

×

T

SYS

, only the time beyond the 1024

×

T

T

SYS

.

SYS

should be added to the boot time (HDRST falling edge to first user instruction).

2. Software reset: the moment of starting the software reset and the moment when the first user instruction has entered the CPU and its processing starts

VDDP

V

DDPPA V

DDPPA

VDD t oscs

OSC

PORST

HDRST

Pads

Padstate undefined t

POA t

POA t hd t hd

2)

1) t pi

1) as programmed

2) Tri-state, pull device active

2)

Figure 4-11 Power, Pad and Reset Timing

Data Sheet 94

V

DDPR

1)

2)

Padstate undefined reset_beh

V1.0, 2008-04

TC1762


4.3.5

Phase Locked Loop (PLL)

Section 4.3.5

provides the characteristics of the PLL parameters and its operation in the

TC1762.

Note: All PLL characteristics defined on this and the next page are verified by design characterization.

Table 4-13 PLL Parameters (Operating Conditions apply)

Parameter

Accumulated jitter

VCO frequency range

PLL base frequency

1) f f

Symbol

D

P

VCO

PLLBASE

Min.

Limit Values

Max.

See

Figure 4-12

400

500

600

140

150

500

600

700

320

400

Unit

–

MHz

MHz

MHz

MHz

MHz

PLL lock-in time t

L

200

–

480

200

MHz

µs

1) The CPU base frequency which is selected after reset is calculated by dividing the limit values by 16 (this is the K factor after reset).

Phase Locked Loop Operation

When PLL operation is enabled and configured, the PLL clock f

VCO

(and with it the CPU clock and f f

CPU

) is constantly adjusted to the selected frequency. The relation between

SYS

is defined by: f

VCO

= K

× f

CPU

. The PLL causes a jitter of f

CPU f

VCO

and affects the clock outputs TRCLK and SYSCLK (P4.3) which are derived from the PLL clock f

VCO

.

There are two formulas that define the (absolute) approximate maximum value of jitter

D

P

in ns dependent on the K-factor, the CPU clock frequency f

CPU

in MHz, and the number P of consecutive f

CPU

clock periods.

P

×

K

<

900 =

±





5

×

P fcpu MHz

]

+

,





(4.1)

P

×

K

≥

900 =

±





4500

+

,





(4.2)

K : K-Divider Value

P : Number of f

CPU

periods

D

P

: Jitter in ns f

CPU

: CPU frequency in MHz

Data Sheet 95 V1.0, 2008-04

TC1762


Note: The frequency of system clock f

SYS

can be selected to be either f

CPU

or f

CPU

/2.

With rising number P of clock cycles the maximum jitter increases linearly up to a value of P that is defined by the K-factor of the PLL. Beyond this value of P the maximum accumulated jitter remains at a constant value. Further, a lower CPU clock frequency f

CPU

results in a higher absolute maximum jitter value.

Figure 4-12 illustrates the jitter curve for for several K/

f

CPU

combinations.

TC1762 PLL Jitter (Preliminary)

±13.0

±12.0

±11.0

±10.0

±9.0

±8.0

±7.0

±6.0

±5.0

±4.0

±3.0

f

CP U

= 40 MHz (K = 10) f

CP U

= 40 MHz

(K = 17) f

CP U

= 80 MHz (K = 5) f

CP U

= 66 MHz ( K = 7) f

CP U

= 80 MHz (K = 8) f

CP U

= 66 MHz (K = 10)

±2.0

±1.0

±0.0

1 25 50 75 100 125 150 175

P [Periods] oo

Figure 4-12 Approximated Maximum Accumulated PLL Jitter for Typical CPU

Clock Frequencies f

CPU

(overview)

Data Sheet 96 V1.0, 2008-04

TC1762


±1.40

±1.30

±1.20

±1.10

±1.00

±0.90

1

TC1762 PLL Jitter (preliminary ) f

CP U

= 40 MHz f

CP U

= 66 MHz

2 3 f

CP U

= 80 MHz

4 5

P [Periods]

Figure 4-13 Approximated Maximum Accumulated PLL Jitter for Typical CPU

Clock Frequencies f

CPU

(detail)

Note: The maximum peak-to-peak noise on the main oscillator and PLL power supply

(measured between V

DDOSC

and V

SSOSC

) is limited to a peak-to-peak voltage of

V

PP

= 10 mV. This condition can be achieved by appropriate blocking to the supply pins and using PCB supply and ground planes.

Data Sheet 97 V1.0, 2008-04

TC1762


4.3.6

Debug Trace Timing

V

SS

= 0 V; V

DDP

= 3.13 to 3.47 V (Class A); T

A

= -40

°C to +125 °C;

C

L

(TRCLK) = 25 pF; C

L

(TR[15:0]) = 50 pF

Table 4-14 Debug Trace Timing Parameter

1)

Parameter

TR[15:0] new state from TRCLK t

Symbol

9

Min.

Limit Values

Max.

CC -1 4

Unit ns

1) Not subject to production test, verified by design/characterization.

TRCLK

TR[15:0] Old State t

9

New State

Trace_Tmg

Figure 4-14 Debug Trace Timing

Data Sheet 98 V1.0, 2008-04

TC1762

Preliminary

4.3.7

Timing for JTAG Signals

(Operating Conditions apply, C

L

= 50 pF)


Table 4-15 TCK Clock Timing Parameter


TCK clock period

TCK high time

TCK low time

1)

TCK clock rise time

TCK clock fall time

1) f

TCK

should be lower or equal to f

SYS t t

1 t

2 t

3 t

4

TCK

Min.

Limit Values

Max.

SR 25

SR 10

SR 10

SR –

SR –

–

–

–

4

4

Unit ns ns ns ns ns

0.9 V

DD

0.1 V

DD

TCK

0.5 V

DD t

1 t

TCK t

2

Figure 4-15 TCK Clock Timing t

4 t

3

Data Sheet 99 V1.0, 2008-04

TC1762


Table 4-16 JTAG Timing Parameter

1)

Parameter

TMS setup to TCK t

Symbol

1

Limit

Values

Min. Max.

SR 6.0

–

Unit Test

Conditions /

Remarks ns –

TMS hold to TCK

TDI setup to TCK t

2 t

1

SR 6.0

–

SR 6.0

– ns ns

–

–

SR 6.0

– ns TDI hold to TCK

TDO valid output from TCK

2)

TDO high impedance to valid output from TCK

2)

t t

2 t

3

4

CC – 14.5

ns

3.0

–

CC – 15.5

ns

–

C

L

= 50 pF

3)4)

C

L

= 20 pF

C

L

= 50 pF

3)4)

TDO valid output to high impedance from TCK

2)

t

5

CC – 14.5

ns C

L

= 50 pF

4)


2) The falling edge on TCK is used to capture the TDO timing.

3) By reducing the load from 50 pF to 20 pF, a reduction of approximately 1.0 ns in timing is expected.

4) By reducing the power supply range from +/-5 % to +5/-2 %, a reduction of approximately 0.5 ns in timing is expected.

Data Sheet 100 V1.0, 2008-04

TC1762


TCK t

1 t

2

TMS t

1 t

2

TDI t

4 t

3 t

5

TDO

Figure 4-16 JTAG Timing

Note: The JTAG module is fully compliant with IEEE1149.1-2000 with JTAG clock at

20 MHz. The JTAG clock at 40 MHz is possible with the modified timing diagram shown in

Figure 4-16 .

Data Sheet 101 V1.0, 2008-04

TC1762


4.3.8

Peripheral Timings

Section 4.3.8

provides the characteristics of the peripheral timings in the TC1762.

Note: Peripheral timing parameters are not subject to production test. They are verified by design/characterization.

4.3.8.1

Micro Link Interface (MLI) Timing

Table 4-17

provides the characteristics of the MLI timing in the TC1762.

Table 4-17 MLI Timing (Operating Conditions apply, C

L

= 50 pF)


TCLK clock period

1)2)

Min.

CC 2

3)

Max.

–

RCLK clock period

MLI outputs delay from TCLK t

30 t

31 t

35

SR 1

CC 0

–

8

MLI inputs setup to RCLK t

36

SR 4 –

MLI inputs hold to RCLK

RREADY output delay from RCLK t

37 t

38

SR 4

CC 0

1) TCLK signal rise/fall times are the same as the A2 Pads rise/fall times.

2) TCLK high and low times can be minimum 1

×

T

MLI

3) T

MLImin

= T

SYS

= 1/ f

SYS

. When f

SYS

= 80MHz, t

30

= 25ns

–

8

Unit ns ns ns

1/ f

SYS

1/ f

SYS ns

Data Sheet 102 V1.0, 2008-04

Preliminary

TC1762

Electrical Parameters t

30

TCLKx

TDATAx

TVALIDx

TREADYx t

35 t

35

0.9 V

DDP

0.1 V

DDP t

30

RCLKx t

36 t

37

RDATAx

RVALIDx t

38 t

38

RREADYx

MLI_Tmg_1.vsd

Figure 4-17 MLI Interface Timing

Note: The generation of RREADYx is in the input clock domain of the receiver. The reception of TREADYx is asynchronous to TCLKx.

Data Sheet 103 V1.0, 2008-04

TC1762


4.3.8.2

Micro Second Channel (MSC) Interface Timing

Table 4-18

provides the characteristics of the MSC timing in the TC1762.

Table 4-18 MSC Interface Timing (Operating Conditions apply, CL = 50 pF)


FCLP clock period

1)2)

SOP/ENx outputs delay from FCLP t t

40

45

Min.

CC 2

×

T

MSC

3)

CC -10

Max.

–

10

Unit ns ns

SDI bit time

SDI rise time t

46 t

48

SR 8

×

SR

SDI fall time t

49

SR

1) FCLP signal rise/fall times are the same as the A2 Pads rise/fall times.

2) FCLP signal high and low can be minimum 1

×

T

MSC

.

3) T

MSCmin

= T

SYS

= 1/ f

SYS

. When f

SYS

= 80MHz, t

40

= 25ns

T

MSC

–

100

100 ns ns ns t

40

FCLP

0.9 V

DDP

0.1 V

DDP t

45 t

45

SOP

EN

SDI t

46 t

48 t

46 t

49

0.9 V

DDP

0.1 V

DDP

MSC_Tmg_1.vsd

Figure 4-18 MSC Interface Timing

Note: The data at SOP should be sampled with the falling edge of FCLP in the target device.

Data Sheet 104 V1.0, 2008-04

TC1762


4.3.8.3

Synchronous Serial Channel (SSC) Master Mode Timing

Table 4-19

provides the characteristics of the SSC timing in the TC1762.

Table 4-19 SSC Master Mode Timing (Operating Conditions apply, CL = 50 pF)

Parameter Symbol Limit Values Unit

SCLK clock period

1)2)

MTSR/SLSOx delay from SCLK t t

50

51

Min.

CC 2

×

T

SSC

3)

CC 0

Max.

–

8 ns ns

MRST setup to SCLK

MRST hold from SCLK t

52 t

53

SR 10

SR 5

1) SCLK signal rise/fall times are the same as the A2 Pads rise/fall times.

2) SCLK signal high and low times can be minimum 1

×

T

SSC

.

3) T

SSCmin

= T

SYS

= 1/ f

SYS

. When f

SYS

= 80 MHz, t

50

= 25ns

–

– ns ns t

50

SCLK 1)2) t

51 t

51

MTSR 1)

MRST 1) t

52 t

53

Data valid t

51

SLSOx 2)

1) This timing is based on the following setup: CON.PH = CON.PO = 0.

2) The transition at SLSOx is based on the following setup: SSOTC.TRAIL = 0

and the first SCLK high pulse is in the first one of a transmission.

SSC_Tmg_1.vsd

Figure 4-19 SSC Master Mode Timing

Data Sheet 105 V1.0, 2008-04

TC1762

Preliminary Packaging

5 Packaging

Chapter 5 provides the information of the TC1762 package and reliability section.

5.1

Package Parameters

Table 5-1 provides the characteristics of the package parameters.

Table 5-1 Package Parameters (PG-LQFP-176-2)


R

TJCT

Limit Values Unit Notes

Min.

Max.

CC – 5.4

K/W – Thermal resistance junction case top

1)

Thermal resistance junction leads

1)

R

TJL

CC – 21.5

K/W –

1) The thermal resistances between the case top and the ambient (R

TCAT

), the leads and the ambient (R

TLA

) are to be combined with the thermal resistances between the junction and the case top (R

TJCT

), the junction and the leads (R

TJL

) given above, in order to calculate the total thermal resistance between the junction and the ambient (R

TJA

). The thermal resistances between the case top and the ambient (R

TCAT

), the leads and the ambient (R

TLA

) depend on the external system (PCB, case) characteristics, and are under user responsibility.

The junction temperature can be calculated using the following equation: T

J

=T

A

+R

TJA

× P

D

, where the R

TJA

is the total thermal resistance between the junction and the ambient. This total junction ambient resistance R

TJA can be obtained from the upper four partial thermal resistances.

Data Sheet 106 V1.0, 2008-04

Preliminary

5.2

Package Outline

Figure 5-1 shows the package outlines of the TC1762.

PG-LQFP-176-2

Plastic Low Profile Quad Flat Package

TC1762

Packaging

Figure 5-1 Package Outlines PG-LQFP-176-2

You can find all of our packages, sorts of packing and others in our

Infineon Internet Page “Products”: http://www.infineon.com/products.

SMD = Surface Mounted Device

Dimensions in mm

Data Sheet 107 V1.0, 2008-04

TC1762


5.3

Flash Memory Parameters

The data retention time of the TC1762’s Flash memory (i.e. the time after which stored data can still be retrieved) depends on the number of times the Flash memory has been erased and programmed.

Table 5-2 Flash Parameters

Parameter Symbol Limit Values Unit Notes

Program Flash

Retention Time,

Physical Sector

1) 2) t

RET

Min.

20

Max.

– years Max. 1000 erase/program cycles

Program Flash

Retention Time,

Logical Sector

1)2)

Data Flash Endurance

(32 Kbyte)

Data Flash Endurance,

EEPROM Emulation

(8

× 4 Kbyte) t

N

N

RETL

E

E8

20

15 000

–

–

120 000 – years Max. 50 erase/program cycles

–

–

Max. data retention time 5 years

Max. data retention time 5 years

Programming Time per

Page

3) t

PR

– 5 ms –

Program Flash Erase

Time per 256-Kbyte sector t

ERP

– 5 s f

CPU

= 80 MHz

Data Flash Erase Time per 16-Kbyte sector t

ERD

– 0.625

s f

CPU

= 80 MHz

Wake-up time t

WU

1) Storage and inactive time included.

4300

× 1/ f

CPU

+ 40

µs

2) At average weighted junction temperature T

J

= 100 °C, or the retention time at average weighted temperature of T

J

= 110 °C is minimum 10 years, or the retention time at average weighted temperature of T

J

= 150 °C is minimum 0.7 years.

3) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The reprogramming takes additional 5ms.

Data Sheet 108 V1.0, 2008-04

TC1762


5.4

Quality Declaration

Table 5-3 shows the characteristics of the quality parameters in the TC1762.

Table 5-3

Parameter

Quality Parameters

Symbol

Operation Lifetime

1)2) t

OP

–

–

–

Limit Values Unit Notes

Min.

–

Max.

24000 hours At average weighted junction temperature

T

J

= 127°C

66000 hours At average weighted junction temperature

T

J

= 100°C

20 years At average weighted junction temperature

T

J

= 85°C

2000 V Conforming to

EIA/JESD22-

A114-B

– 500 V –

ESD susceptibility according to Human Body

Model (HBM)

V

HBM

ESD susceptibility of the

LVDS pins

V

HBM1

ESD susceptibility according to Charged

Device Model (CDM) pins

V

CDM

– 500 V Conforming to

JESD22-C101-C

Moisture Sensitivity Level

(MSL)

– 3 V Conforming to

J-STD-020C for

240°C

1) This lifetime refers only to the time when the device is powered-on.

2) An example of a detailed temperature profile is as below:

2000 hours at T

J

= 150 o C

16000 hours at T

J

= 125 o

6000 hours at T

J

= 110 o

C

C

This example is equivalent to the operation lifetime and average temperatures given in

Table 5-3 .

Note: Information about soldering can be found on the “package” information page under: http://www.infineon.com/products .

Data Sheet 109 V1.0, 2008-04

w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG

Infineon SAK-TC1762-128F80HL AC Microcontroller Data Sheet

Table of Contents

1 Summary of Features

2 General Device Information

3 Functional Description

4 Electrical Parameters

5 Packaging

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Table of contents

Infineon SAK-TC1762-128F80HL AC Microcontroller Data Sheet

Table of Contents

1 Summary of Features

2 General Device Information

3 Functional Description

4 Electrical Parameters

5 Packaging

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Table of contents