Micro Link Serial Bus Interface (MLI0). Infineon SAK-TC1762-128F66HL AC, SAK-TC1762-128F80HL AC

TC1762

Preliminary Functional Description

3.11

Micro Link Serial Bus Interface (MLI0)

The Micro Link Interface is a fast synchronous serial interface that allows data exchange between microcontrollers of the 32-bit AUDO microcontroller family without intervention

of a CPU or other bus masters. Figure 3-7 shows how two microcontrollers are typically

connected together via their MLI interface. The MLI operates in both microcontrollers as a bus master on the system bus.

Controller 1

CPU

Controller 2

CPU

Peripheral

A

Peripheral

B

Peripheral

C

Peripheral

D

Memory MLI MLI Memory

System Bus System Bus

MCA06061

Figure 3-7 Typical Micro Link Interface Connection

Features

• Synchronous serial communication between MLI transmitters and MLI receivers located on the same or on different microcontroller devices

• Automatic data transfer/request transactions between local/remote controller

• Fully transparent read/write access supported (= remote programming)

• Complete address range of remote controller available

• Specific frame protocol to transfer commands, addresses and data

• Error control by parity bit

• 32-bit, 16-bit, and 8-bit data transfers

• Programmable baud rates

– MLI transmitter baud rate: max. f

MLI

/2 (= 40 Mbit/s @ 80 MHz module clock)

– MLI receiver baud rate: max. f

MLI

• Multiple remote (slave) controllers are supported

MLI transmitter and MLI receiver communicate with other off-chip MLI receivers and MLI transmitters via a 4-line serial I/O bus each. Several I/O lines of these I/O buses are available outside the MLI module kernel as four-line output or input buses.

Data Sheet 41 V1.0, 2008-04

TC1762

Preliminary Functional Description

Figure 3-8 shows a global view of the functional blocks of the MLI module with its

interfaces.

Clock

Control f

ML I0

Address

Decoder

Interrupt

Control

SR[3:0]

MLI 0

Module

(Kernel)

To DMA

SR[4:7]

Cerberus

BRKOUT

TCLK

TREADYA

TREADYB

TREADYD

TVALIDA

TVALIDB

TVALIDD

TDATA

RCLKA

RCLKB

RCLKD

RREADYA

RREADYB

RREADYD

RVALIDA

RVALIDB

RVALIDD

RDATAA

RDATAB

RDATAD

Port 2

Control

Port 5

Control

A2 P2.0 / TCLK0

A2 P2.1 / TREADY0A

A2 P2.2 / TVALID0A

A2 P2.3 / TDATA0

A1 P2.4 / RCLK0A

A2 P2.5 / RREADY0A

A1 P2.6 / RVALID0A

A1 P2.7 / RDATA0A

A2 P5.15 / TCLK0

A2 P5.14 / TREADY0B

A2 P5.13 / TVALID0B

A2 P5.12 / TDATA0

A2 P5.11 / RCLK0B

A2 P5.10 / RREADY0B

A2 P5.9 / RVALID0B

A2 P5.8 / RDATA0B

MCB06322

Figure 3-8 Block Diagram of the MLI Module

Data Sheet 42 V1.0, 2008-04