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Power Supply Current. Infineon SAK-TC1762-128F66HL AC, SAK-TC1762-128F80HL AC
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TC1762
Preliminary Electrical Parameters
4.2.6
Power Supply Current
provides the characteristics of the power supply current in the TC1762.
Table 4-10 Power Supply Current (Operating Conditions apply)
Parameter Symbol Limit Values
Min. Typ. Max.
Unit Test
Conditions /
Remarks
PORST low current at
V
DD
PORST low current at
V
DDP
I
I
DD_PORST
DDP_PORST
CC –
CC –
–
–
96
1)
138
2)
mA The PLL running at the base frequency mA The PLL running at the base frequency mA f
CPU
= 80MHz f
CPU
/ f
SYS
= 1:1
Active mode core supply current
3)4)
Active mode core supply current
I
I
DD
DD
CC –
CC –
–
–
290
330
250
300
– mA f
CPU
= 66MHz f
CPU
/ f
SYS
= 1:1
Active mode analog supply current
Oscillator and PLL core power supply
Oscillator and PLL pads power supply
I
I
I
I
DDAx;
DDMx
DDOSC
DDOSC3
CC –
CC –
CC –
–
–
–
5
3.6
5) mA See
ADC0/FADC mA – mA –
FLASH power supply current
I
DDFL3
CC – – 45 mA –
LVDS port supply
(via V
DDP
)
6)
Maximum Allowed
Power Dissipation
7)
I
P
LVDS
Dmax
CC –
SR
– 25 mA LVDS pads active
P
D
× R
TJA
< 25°C – At worst case,
T
A
= 125 °C
1) Maximum value measured at T
A
= 125 °C.
2) Maximum value measured at T
J
= 150 °C.
3) Infineon Power Loop: CPU and PCP running, all peripherals active. The power consumption of each custom application will most probably be lower than this value, but must be evaluated separately.
4) The I
DD
decreases typically to 240mA if the f
CPU
is decreased to 40 MHz, at constant T
J
Infineon Max. Power Loop.
= 150 °C, for the
5) Estimated value; double-bonded at package level with V
DDP
.
6) In case the LVDS pads are disabled, the power consumption per pair is negligible (less than 1
µA).
7) For the calculation of the junction to ambient thermal resistance R
TJA
, see
Data Sheet 88 V1.0, 2008-04
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Table of contents
- 7 Summary of Features
- 10 General Device Information
- 10 Block Diagram
- 11 Logic Symbol
- 12 Pin Configuration
- 13 Pad Driver and Input Classes Overview
- 14 Pin Definitions and Functions
- 28 Functional Description
- 28 System Architecture and On-Chip Bus Systems
- 29 On-Chip Memories
- 31 Architectural Address Map
- 32 Memory Protection System
- 33 DMA Controller and Memory Checker
- 35 Interrupt System
- 37 Asynchronous/Synchronous Serial Interfaces (ASC0, ASC1)
- 39 High-Speed Synchronous Serial Interface (SSC0)
- 41 Micro Second Bus Interface (MSC0)
- 43 MultiCAN Controller (CAN)
- 45 Micro Link Serial Bus Interface (MLI0)
- 47 General Purpose Timer Array
- 48 Functionality of GPTA
- 51 Analog-to-Digital Converter (ADC0)
- 53 Fast Analog-to-Digital Converter Unit (FADC)
- 55 System Timer
- 58 Watchdog Timer
- 59 System Control Unit
- 60 Boot Options
- 61 Power Management System
- 62 On-Chip Debug Support
- 64 Clock Generation and PLL
- 67 Power Supply
- 68 Identification Register Values
- 70 Electrical Parameters
- 70 General Parameters
- 70 Parameter Interpretation
- 71 Pad Driver and Pad Classes Summary
- 72 Absolute Maximum Ratings
- 73 Operating Conditions
- 76 DC Parameters
- 76 Input/Output Pins
- 79 Analog to Digital Converter (ADC0)
- 86 Fast Analog to Digital Converter (FADC)
- 90 Oscillator Pins
- 91 Temperature Sensor
- 92 Power Supply Current
- 93 AC Parameters
- 93 Testing Waveforms
- 94 Output Rise/Fall Times
- 95 Power Sequencing
- 97 Power, Pad and Reset Timing
- 99 Phase Locked Loop (PLL)
- 102 Debug Trace Timing
- 103 Timing for JTAG Signals
- 106 Peripheral Timings
- 106 Micro Link Interface (MLI) Timing
- 108 Micro Second Channel (MSC) Interface Timing
- 109 Synchronous Serial Channel (SSC) Master Mode Timing
- 110 Packaging
- 110 Package Parameters
- 111 Package Outline
- 112 Flash Memory Parameters
- 113 Quality Declaration