STMicroelectronics STM6510 Datasheet
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STM6510
Dual push-button Smart Reset
TM
with capacitor-adjustable delays
Features
■
■
■
■
■
■
■
■
■
Dual Smart Reset™ push-button inputs with capacitor-adjustable extended reset setup delay (t
SRC
)
Capacitor-adjustable reset pulse duration
(t
REC
)
Power-on reset
– RST active-low, open-drain
Factory-programmable thresholds to monitor
V
CC in the range of 1.575 to 4.625 V typ.
Operating voltage 1.0 V (active-low output valid) to 5.5 V
Low supply current (1.4 µA)
Operating temperature: industrial grade –40 °C to +85 °C
TDFN8 package: 2 mm x 2 mm x 0.75 mm
RoHS compliant
TDFN8 (DG)
2 mm x 2 mm
Applications
■
■
■
■
■
■
Mobile phones, smartphones e-books
MP3 players
Games
Portable navigation devices
Any application that requires delayed reset push-button(s) response for improved system stability
February 2010 Doc ID 16788 Rev 2 1/26
www.st.com
1
Contents
Contents
STM6510
Smart Reset™ devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SS
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Smart Reset™ push-button inputs (SR0, SR1) . . . . . . . . . . . . . . . . . . . . 9
Adjustable delay of Smart Reset™ input (SRC pin) . . . . . . . . . . . . . . . . 9
Adjustable reset timeout (TREC
ADJ
pin) . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/26 Doc ID 16788 Rev 2
STM6510
List of tables
List of tables
TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package mechanical data . . . . . . . . . . . . . 18
Doc ID 16788 Rev 2 3/26
List of figures
List of figures
STM6510
) vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
) vs. temperature, C
SRC
= 0.56 µF . . . . . . . . . . . . . . . . . . . . . . 11
) vs. temperature, C tREC
= 0.01 µF . . . . . . . . . . . . . . . . . . . . . 12
RST
) vs. temperature, “S” threshold option, V
CC
falling. . . . . . . . . . . . . 12
4/26 Doc ID 16788 Rev 2
STM6510
1 Description
1.1
Description
Smart Reset™ devices
The Smart Reset™ device family STM65xx provides a useful feature that ensures inadvertent short reset push-button closures do not cause system resets. This is done by implementing an extended Smart Reset™ input delay (t
SRC
). Once the valid Smart Reset™ input levels and setup delay are met, the device generates an output reset pulse with userprogrammable timeout period (t
REC
).
The typical application hookup shows that the dual Smart Reset™ inputs can be also connected to the applications interrupt to allow the control of both the interrupt pin and the hard reset functions. If the push-buttons are closed for a short time, the processor is only interrupted. If the system still does not respond properly, holding the push-buttons for the extended setup time (t
SRC
) causes a hard reset of the processor through the reset output.
The Smart Reset™ feature helps significantly increase system stability.
The STM65xx family of Smart Reset™ devices consists of low-current microprocessor reset circuits targeted at applications such as MP3 players, portable navigation devices or mobile phones, generally any application that requires delayed reset push-button(s) response for improved system stability. The STM65xx devices feature single or dual Smart Reset™ inputs (SRx). The delayed Smart Reset™ setup time (t
SRC
) options are adjustable by adding an external capacitor on the SRC pin or selectable by three-state logic. The delayed setup period ignores switch closures shorter than t
SRC
, thus preventing undesired resets.
The STM65xx devices have active-low (optionally active-high) open-drain reset (RST) output(s) with or without an internal pull-up resistor or push-pull as output options, with or without the power-on reset function.
Some devices also have an undervoltage monitoring feature: the reset output is also asserted when the monitored supply voltage V
CC
drops below the specified threshold. The reset output remains asserted for the reset timeout period (t
REC voltage goes above the specified threshold.
) after the monitored supply
1.2 STM6510
The STM6510 has two combined Smart Reset™ inputs (SR0 and SR1) with Smart Reset™ setup delay (t
SRC
) programmed by an external capacitor on the SRC pin. An additional
STM6510 feature is adjustable output reset pulse time t
REC
by adding an external capacitor
(C tREC
).
Additionally, the V
CC
is monitored and if it drops below the selected V
RST
threshold, the reset output goes active and remains active while V
CC
is below the V
RST
threshold, plus the defined duration of the reset pulse t
REC
.
Doc ID 16788 Rev 2 5/26
Description
Figure 1.
Logic diagram
STM6510
VCC
SR0
SR1
SRC
STM6510
RST
TRECADJ
VSS
AM00389a
Figure 2.
Pin connections
RST
VSS
SR1
NC
1
2
3
4
STM
6510
6
5
8
7
VCC
SR0
TRECADJ
SRC
AM00390
Table 1.
Signal names
Symbol Input/output
RST
SR0
SR1
SRC
TREC
ADJ
V
CC
V
SS
NC
Description
Output
Input
Input
Reset output, active-low (open-drain).
Primary push-button Smart Reset™ input. Active-low, internal 65 k
Ω pull-up resistor to V
CC
.
Secondary push-button Smart Reset™ input. Active-low, internal 65 k
Ω pull-up resistor to V
CC
.
Input
Input
Smart Reset™ input delay setup control. Connect an external capacitor to this pin to adjust the delay setup time (t
SRC
).
Input pin for t
REC
reset pulse duration adjustment. Connect an external capacitor (C tREC
) to this pin to determine t
REC
.
Supply
Supply voltage input. Power supply for the device and an input for the monitored supply voltage. A 0.1 µF decoupling ceramic capacitor is recommended to be connected between V
CC
and V
SS
pins.
Supply Ground
No connect (not bonded); should be connected to V
SS.
6/26 Doc ID 16788 Rev 2
STM6510
Figure 3.
Block diagram
VCC
VRST
COMPARE
65 k
Ω
65 k
Ω
SR0
SR1
SRC
Logic
Description
tREC generator
TRECADJ
CtREC
RST
AM00391a
Doc ID 16788 Rev 2 7/26
Description
Figure 4.
Single-button Smart Reset™ typical hookup
VCC
100 k
Ω
CtREC
VCC
TRECADJ
RST
SRC
STM6510
SR1
VSS
SR0
CSRC
RESET
VCC
MCU
INT/
NMI
VSS
PUSH-BUTTON
SWITCH
STM6510
Note:
AM04870v1
When only one Smart Reset™ input push-button is used, tie both the SR inputs together.
Figure 5.
Dual-button Smart Reset™ typical hookup
VCC
100 k
Ω
CtREC
VCC
TRECADJ
RST
SRC
STM6510
SR1
VSS
SR0
CSRC
RESET
VCC
MCU
INT/
NMI
VSS
PUSH-BUTTON
SWITCH
PUSH-BUTTON
SWITCH
AM004871v1
8/26 Doc ID 16788 Rev 2
STM6510 Description
1.3.1 Power supply (V
CC
)
This pin is used to provide the power to the Smart Reset™ device and to monitor the power supply. A 0.1 µF decoupling ceramic capacitor is recommended to be connected between the V
CC
and V
SS
pins.
1.3.2 Ground )
This is the supply ground for the device.
1.3.3 Smart Reset™ push-button inputs (SR0, SR1)
Both SR0 and SR1 need to be held active at the same time for at least t
SRC
to activate the reset output pulse. Include an internal 65 k
Ω pull-up resistor to V
CC for each input.
Figure 6.
Timing waveforms
tSRC tREC
SR0
SR1
RST
AM00393
This pin controls the setup time before the push-button action is validated by the reset output. It is connected to an external capacitor (C
SRC
), which is tied to ground to provide the desired value of setup time (t
SRC
).
Calculated t
SRC
and C
SRC
.
Table 2.
t
SRC
programmed by an ideal external capacitor
Setup delay t
SRC
[s]
(1)(2)
Calculated C
SRC value [µF]
Min.
Typ.
Max.
Closest common
C
SRC
value [µF]
0.2
0.3
0.6
1
2
3
6
10
3
4.5
9
15
4
6
12
20
0.22
0.33
0.56
1
1.
Example calculations based on an ideal capacitor. During application design and component selection it should be considered that the current flowing into the external t
SRC
programming capacitor (C
SRC
) is on the order of 100 nA, therefore a low-leakage capacitor (ceramic or film capacitor) and an adequate PCB environment should be used to prevent t
SRC value of C
SRC
is 0.01 µF.
accuracy from being affected. A recommended minimum
2.
In case of repeated activations of the t
SRC activations to fully discharge C
SRC counter, an interval of 10 ms min. is needed between the
, so that the next t
SRC
is as specified.
Doc ID 16788 Rev 2 9/26
Description
1.3.5
STM6510
Reset output (RST)
RST is active-low, open-drain.
reset timeout (TREC
ADJ pin)
The reset timeout (t
REC
) is adjustable by connecting an external capacitor C tREC
to this pin.
Calculated t
REC
and C tREC examples are given in
.
Table 3.
t
REC
programmed by an ideal external capacitor t
REC
[ms]
(1)(2)
Calculated C tREC value [µF]
Min.
Typ.
Max.
Closest common
C tREC
value [µF]
0.001
0.002
0.01
0.014
0.028
0.056
0.112
10
20
100
140
280
560
1120
15
30
150
210
420
840
1680
20
40
200
280
560
1120
2240
0.001
0.0022
0.01
0.015
0.027
0.056
0.1
1.
Example calculations based on an ideal capacitor. During application design and component selection it should be considered that the current flowing into the external t
REC
programming capacitor (C tREC
) is on the order of 100 nA, therefore a low-leakage capacitor (ceramic or film capacitor) and an adequate PCB environment should be used to prevent t
REC value of C tREC
is 0.001 µF.
accuracy from being affected. A recommended minimum
2.
In case of repeated activations of the t
REC
counter, an interval of 10 ms min. is needed between t
REC intervals to fully discharge C tREC
, so that the next t
REC
is as specified.
10/26 Doc ID 16788 Rev 2
STM6510
2 Typical operating characteristics
Typical operating characteristics
Figure 7.
Supply current (I
CC
) vs. temperature
2.4
-60 -40 -20
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
2.2
2
1.8
1.6
20
5.5 V
40
Temperature [°C]
3.3 V 5 V
60
3 V
80
Figure 8.
Smart Reset™ delay (t
SRC
) vs. temperature, C
SRC
= 0.56 µF
12
100 120 140
AM04876v1
-60 -40
7
-20
6
0
11
10
9
8
20 40
Temperature [°C]
5.75 V 5.5 V
60
3.3 V
80 100 120 140
AM04877v1
Doc ID 16788 Rev 2 11/26
Typical operating characteristics
Figure 9.
Reset timeout period (t
REC
) vs. temperature, C tREC
= 0.01 µF
-60 -40 -20
200
190
180
170
160
150
140
130
120
110
100
0 80 20 40
Temperature [°C]
5.75 V 5.5 V
60
3.3 V
100 120
Figure 10.
Reset threshold (V
RST
) vs. temperature, “S” threshold option, V
CC
falling
STM6510
140
AM04878v1
-60 -40
2.93
2.91
2.89
2.87
-20
2.85
0
2.99
2.97
2.95
20 40
Temperature [°C]
60 80 100 120 140
AM04879v1
12/26 Doc ID 16788 Rev 2
STM6510 Maximum ratings
Stressing the device above the rating listed in the
Table 4: Absolute maximum ratings
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics™ SURE
Program and other relevant quality documents.
Table 4.
Symbol
Absolute maximum ratings
Parameter Value Unit
T
STG
T
SLD
(1)
θ
JA
V
IO
V
CC
Storage temperature (V
CC
off)
Lead solder temperature for 10 seconds
Thermal resistance (junction to ambient)
Input or output voltage
Supply voltage
TDFN8
–55 to +150
260
149.0
–0.3 to V
CC
+0.3
–0.3 to 7
°C/W
1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
°C
°C
V
V
Doc ID 16788 Rev 2 13/26
DC and AC parameters
4 DC and AC parameters
STM6510
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the
Table 6: DC and AC characteristics
that follow, are derived from tests performed under the Measurement Conditions summarized in
Table 5: Operating and measurement conditions
. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.
Table 5.
Operating and measurement conditions
Parameter Value
V
CC
supply voltage
Ambient operating temperature (T
A
)
Input rise and fall times
Input pulse voltages
Input and output timing ref. voltages
1.0 to 5.5
–40 to +85
≤ 5
0.2 to 0.8 V
CC
0.3 to 0.7 V
CC
Figure 11.
AC testing input/output waveforms
Unit
V
°C ns
V
V
0.8 VCC
0.2 VCC
0.7 VCC
0.3 VCC
AM00478
14/26 Doc ID 16788 Rev 2
STM6510 DC and AC parameters
Table 6.
Symbol
V
CC
V
I
CC
V
OL
RST
DC and AC characteristics
Parameter
Supply voltage range
Supply current (V
CC
)
Reset output voltage low
Test conditions
(1)
Reset output valid - active-low
V
CC
= 5.0 V
V
CC
= 3.0 V
(3)
V
CC
≥ 4.5 V, sinking 3.2 mA
V
CC
≥ 3.3 V, sinking 2.5 mA
V
CC
≥ 1.0 V, sinking 0.1 mA
V
CC
undervoltage reset threshold (refer to
–40 to +85 °C
25 °C
Min.
1.0
V
RST
–2.5%
V
RST
–2.0%
Typ.
V
V
1.5
1.4
(2)
RST
RST
0.3
0.3
0.3
V
RST
+2.5%
V
RST
+2.0%
Max.
Units
5.5
2.4
V
V
V
V
µA
µA
V
V
V
HYST
Hysteresis of V
V
CC
RST
to reset delay
(4)
L, M
T, S, R, Z, Y, W, V
V
CC
falling from (V
RST
+ 100 mV) to (V
RST
- 100 mV) at 10 mV/µs
0.5%
1%
20 µs t
User-adjustable reset timeout period on RST. Refer to
Smart Reset™ inputs
10 000 x
C tREC
(µF)
15 000 x
C tREC
(µF)
20 000 x
C tREC
(µF) t
SRC
(5)
User-adjustable delayed Smart
Reset™ setup time. Refer to
10 x
C
SRC
(µF)
15 x
C
SRC
(µF)
V
IL
V
IH
SR0, SR1 input voltage low
SR0, SR1 input voltage high 0.7 V
CC
R
PUI
Internal pull-up resistor, SR0,
SR1 inputs
65
1.
Valid for ambient operating temperature: T
A
= –40 to +85 °C; V
CC
= 1.0 to 5.5 V (except where noted).
2.
Typical value is at 25 °C and V
CC
= 3.3 V unless otherwise noted.
3.
For devices with V
RST
< 3.0 V.
4.
Guaranteed by design.
5.
Input glitch immunity is equal to t
SRC
(when both SR inputs are low, otherwise infinite).
20 x
C
SRC
(µF)
0.3 V
CC ms k s
V
V
Ω
Doc ID 16788 Rev 2 15/26
DC and AC parameters
Table 7.
Possible V
CC
voltage thresholds
±2.5% (–40 °C to +85 °C)
V
CC
voltage threshold V
RST
Typ.
Min.
Max.
L (falling)
M (falling)
T (falling)
S (falling)
R (falling)
Z (falling)
Y (falling)
W (falling)
V (falling)
4.625
4.375
3.075
2.925
2.625
2.313
2.188
1.665
1.575
4.509
4.266
2.998
2.852
2.559
2.255
2.133
1.623
1.536
4.741
4.484
3.152
2.998
2.691
2.371
2.243
1.707
1.614
±2.0% (25 °C)
Min.
4.533
4.288
3.014
2.867
2.573
2.267
2.144
1.632
1.544
Max.
4.718
4.463
3.137
2.984
2.678
2.359
2.232
1.698
1.607
STM6510
Unit
V
V
V
V
V
V
V
V
V
16/26 Doc ID 16788 Rev 2
STM6510
5 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at:
www.st.com
.
ECOPACK
®
is an ST trademark.
Doc ID 16788 Rev 2 17/26
Package mechanical data
Figure 12.
TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package outline
D
A
B
STM6510
PIN 1 INDEX AREA
E
0.10 C 2x
0.10 C 2x
TOP VIEW
0.10 C
A
0.08 C
PIN 1 INDEX AREA
1
SIDE VIEW e
A1
SEAT ING
PLANE
C
4 b
0.10
C A B
18/26
Pin#1 ID
L
8
5
BOTTOM VIEW
8070540_A
Table 8.
Symbol
TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package mechanical data
Dimension (mm) Dimension (inches)
A
A1 b
D
BSC
E
BSC e
L
Min.
0.70
0.00
0.15
0.45
Nom.
0.75
0.02
0.20
2.00
2.00
0.50
0.55
Max.
0.80
0.05
0.25
0.65
Min.
0.028
0.000
0.006
0.018
Nom.
0.030
0.001
0.008
0.079
0.079
0.020
0.022
Max.
0.031
0.002
0.010
0.026
Doc ID 16788 Rev 2
STM6510 Package mechanical data
Figure 13.
Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad
D
P
E E1
L b
AM00441
Table 9.
Parameter for landing pattern - TDFN – 8-lead 2 x 2 mm package
Dimension (mm)
Parameter Description
Min.
Nom.
Max.
E
E1
L b
D
P
Contact length
Contact width
Max. land pattern Y-direction
Contact gap spacing
Max. land pattern X-direction
Contact pitch
1.05
0.25
—
—
—
—
—
—
2.75
0.65
1.75
0.5
1.15
0.30
—
—
—
—
Doc ID 16788 Rev 2 19/26
Package mechanical data
Figure 14.
Carrier tape
STM6510
T
Top cover tape
D P2
P0
B0
A0
F
E
W
K0
Center lines of cavity
User direction of feed
P1
AM03073v2
Table 10.
Carrier tape dimensions
Package
TDFN8
W D E P
0
P
2
F A
0
B
0
K
0
P
1
T Unit
Bulk qty.
8.00
+0.30
–0.10
1.50
+0.10/
–0.00
1.75
±0.10
4.00
±0.10
2.00
±0.10
3.50
±0.05
2.30
±0.05
2.30
±0.05
1.00
±0.05
4.00
±0.10
0.250
±0.05
mm 3000
20/26 Doc ID 16788 Rev 2
STM6510
Figure 15.
Reel dimensions
Package mechanical data
T
40 mm min.
acces hole at slot location
B
D
C
N
A
Full radius
Tape slot in core for tape start
25 mm min width
G measured at hub
AM00443
Table 11.
Reel dimensions
Tape sizes A max.
B min.
8 mm 180 (7 inches)
C
1.50
13.0 +/– 0.20
D min.
20.20
N min.
60
G T max.
8.4 +2/–0 14.40
Doc ID 16788 Rev 2 21/26
Package mechanical data
Figure 16.
Tape trailer/leader
End
STM6510
Start
Top cover tape
No components
T R A I L E R
160 mm min.
Components 100 mm min.
No components
L E A D E R
400 mm min.
Sealed with cover tape
User direction of feed
AM00444
Figure 17.
Pin 1 orientation
User direction of feed
Note: 1 Drawings are not to scale.
2 All dimensions are in mm, unless otherwise noted.
AM00442
22/26 Doc ID 16788 Rev 2
STM6510 Part numbering
Table 12.
Ordering information scheme
Example:
STM6510 W C A C DG 6 F
Device type
STM6510
Reset (V
CC
monitoring threshold) voltage V
RST
L = 4.625 V (typ., falling)
M = 4.375 V
T = 3.075 V
S = 2.925 V
R = 2.625 V
Z = 2.313 V
Y = 2.188 V
W = 1.665 V
V = 1.575 V
Smart Reset™ setup delay control (t
SRC
); presence of internal input pull-up on all
Smart Reset™ inputs (SR0, SR1)
C = 1 to 15 s, user-programmable (external capacitor); 65 k
Ω input pull-up
Output type
A = open-drain, active-low
Reset timeout period (t
REC
)
C = user-programmable (external capacitor)
Package
DG = TDFN8 - 2 x 2 x 0.75 mm, 0.5 mm pitch
Temperature range
6 = –40 °C to +85 °C
Shipping method
F = ECOPACK
® package, tape and reel
For device options currently available refer to
. For other options, voltage threshold values etc. or
for more information on any aspect of this device, please contact the ST sales office nearest you.
Doc ID 16788 Rev 2 23/26
Package marking STM6510
Note:
Table 13.
Package marking
Part name t
SRC delay control
STM6510WCACDG6F C
SRC
STM6510SCACDG6F C
SRC
STM6510RCACDG6F C
SRC
Smart
Reset™ inputs type
V
RST
Reset output type t
REC programming
Topmark
AL, PU
AL, PU
AL, PU
W
S
R
AL, OD
AL, OD
AL, OD
C tREC
C tREC
C tREC
8WK
8SK
8RK
AL = Active-Low, AH = Active-High; PU = with internal pull-up resistor, OD = Open-Drain.
Figure 18.
Package marking, top view
B
A
C D
E
Topmark
A = dot (pin 1 reference)
B = assembly plant (P)
C = assembly year (Y, 0-9): 9 = 2009 etc.
D = assembly work week (WW, 01 to 52): 20 = WW20 etc.
E = marking area (topmark)
AM00479
24/26 Doc ID 16788 Rev 2
STM6510 Revision history
Table 14.
Document revision history
Date Revision
12-Feb-2010
26-Feb-2010
1
2
Changes
Initial release.
; updated footnote
; updated
,
textual and formatting changes.
Doc ID 16788 Rev 2 25/26
STM6510
Please Read Carefully:
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26/26 Doc ID 16788 Rev 2
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