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240pin Unbuffered DIMM based on 2Gb C-die
78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
Rev. 1.2, May. 2010
M378B5773CH0
M391B5773CH0
M378B5273CH0
M391B5273CH0
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
2010 Samsung Electronics Co., Ltd. All rights reserved.
- 1 -
Unbuffered DIMM
Revision History
Revision No.
1.0
1.1
1.11
1.12
1.2
History
- First Release
- Changed DIMM IDD Definition
- Added DIMM IDD Specification
- Deleted operation frequency of 800Mbps 6-6-6
- Corrected Typo.
- Corrected Typo.
- Changed Module line-up
Rev. 1.2
DDR3 SDRAM
Draft Date
Dec. 2009
Jan. 2010
Remark
-
-
Editor
S.H.Kim
S.H.Kim
Mar. 2010
May. 2010
May. 2010
-
-
-
S.H.Kim
S.H.Kim
S.H.Kim
- 2 -
Unbuffered DIMM
Rev. 1.2
DDR3 SDRAM
Table Of Contents
240pin Unbuffered DIMM based on 2Gb C-die
Tolerances.................................................................................................................................................... 16
- 3 -
Unbuffered DIMM
1. DDR3 Unbuffered DIMM Ordering Information
Part Number Density Organization
M378B5773CH0-CF8/H9/K0
M391B5773CH0-CF8/H9/K0
M378B5273CH0-CF8/H9/K0
M391B5273CH0-CF8/H9/K0
2GB
2GB
4GB
4GB
NOTE :
- "##" - F8/H9/K0
- F8 - 1066Mbps 7-7-7 & H9 - 1333Mbps 9-9-9 & K0 - 1600Mbps 11-11-11
256Mx64
256Mx72
512Mx64
512Mx72
Component Composition
256Mx8(K4B2G0846C-HC##)*8
256Mx8(K4B2G0846C-HC##)*9
256Mx8(K4B2G0846C-HC##)*16
256Mx8(K4B2G0846C-HC##)*18
Rev. 1.2
DDR3 SDRAM
Number of
Rank
1
1
2
2
Height
30mm
30mm
30mm
30mm
2. Key Features
Speed tCK(min)
CAS Latency tRCD(min) tRP(min) tRAS(min) tRC(min)
DDR3-800
6-6-6
2.5
6
15
15
37.5
52.5
DDR3-1066
7-7-7
1.875
7
13.125
13.125
37.5
50.625
DDR3-1333
9-9-9
1.5
9
13.5
13.5
36
49.5
DDR3-1600
11-11-11
1.25
11
13.75
13.75
35
48.75
Unit ns nCK ns ns ns ns
• JEDEC standard 1.5V ± 0.075V Power Supply
• V
DDQ
= 1.5V ± 0.075V
• 400MHz f
CK
for 800Mb/sec/pin, 533MHz f
CK
for 1066Mb/sec/pin, 667MHz f
CK
for 1333Mb/sec/pin, 800MHz f
CK
for 1600Mb/sec/pin
• 8 independent internal bank
• Programmable CAS Latency: 6,7,8,9,10,11
• Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
• Programmable CAS Write Latency(CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333) and 8 (DDR3-1600)
• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data Strobe
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower then T
CASE
85
°C, 3.9us at 85°C < T
CASE
≤ 95°C
• Asynchronous Reset
3. Address Configuration
Organization
256Mx8(2Gb) based Module
Row Address
A0-A14
Column Address
A0-A9
Bank Address
BA0-BA2
Auto Precharge
A10/AP
- 4 -
Unbuffered DIMM
4. x64 DIMM Pin Configurations (Front side/Back side)
Back
V
SS
DQ4
DQ5
V
SS
DM0
NC
V
SS
DQ6
NC
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
NC
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
V
SS
DM3
NC
V
SS
DQ30
DQ31
V
SS
NC
NC
V
SS
NC
27
28
29
30
31
24
25
26
32
33
34
35
36
37
38
39
40
41
9
10
15
16
17
18
11
12
13
14
19
20
21
22
23
5
6
3
4
7
8
Pin
1
2
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
Pin
121
122
129
130
135
136
137
138
131
132
133
134
139
140
141
142
143
123
124
125
126
127
128
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1
DQS1
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
DQ25
V
SS
DQS3
DQS3
V
SS
DQ26
Front
V
REFDQ
V
SS
DQ0
DQ1
V
SS
DQS0
DQ27
V
SS
NC
NC
V
SS
67
68
69
70
71
64
65
66
72
73
74
75
76
77
78
79
80
81
49
50
55
56
57
58
51
52
53
54
59
60
61
62
63
Pin
42
43
44
45
46
47
48
Front
NC
NC
V
SS
NC
NC
V
SS
NC
NC
A4
V
DD
A2
V
DD
CK1,NC
2
CK1,NC
2
V
DD
V
DD
V
REF
CA
NC
V
DD
A10/AP
BA0
V
DD
WE
CAS
V
DD
S1, NC
1
ODT1, NC
1
V
DD
NC
V
SS
DQ32
CKE0
V
DD
BA2
NC
V
DD
A11
A7
V
DD
A5
KEY
Pin
162
163
164
165
166
167
168
NOTE :
NC = No Connect; NU = Not Used; RFU = Reserved Future Use
1. S1, ODT1, CKE1: Used for dual-rank UDIMMs; NC on single-rank UDIMMs
2. CK1,NC and CK1,NC : Used for dual-rank UDIMMs; not used on single-rank UDIMMs, but terminated
3. TEST (pin 167) used by memory bus analysis tools (unused on memory DIMMs)
Back
NC
V
SS
NC
NC
V
SS
NC (TEST)
3
Reset
CK0
CK0
V
DD
NC
A0
V
DD
BA1
V
DD
RAS
S0
V
DD
ODT0
A9
V
DD
A8
A6
V
DD
A3
A1
V
DD
V
DD
CKE1,NC
1
V
DD
NC
A14
V
DD
A12/BC
A13
V
DD
NC
V
SS
DQ36
DQ37
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
169
170
175
176
177
178
171
172
173
174
179
180
181
182
183
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Pin
82
83
90
91
96
97
98
99
92
93
94
95
100
101
102
103
104
84
85
86
87
88
89
Rev. 1.2
DDR3 SDRAM
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Pin
202
203
210
211
216
217
218
219
212
213
214
215
220
221
222
223
224
204
205
206
207
208
209
DQ55
V
SS
DQ60
DQ61
V
SS
DM7
NC
V
SS
DQ62
DQ63
V
SS
V
DDSPD
SA1
SDA
V
SS
V
TT
Back
V
SS
DM4
NC
V
SS
DQ38
DQ39
V
SS
DQ44
DQ47
V
SS
DQ52
DQ53
V
SS
DM6
NC
V
SS
DQ54
DQ45
V
SS
DM5
NC
V
SS
DQ46
DQ35
V
SS
DQ40
DQ41
V
SS
DQS5
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
DQS6
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7
DQS7
V
SS
DQ58
DQ59
V
SS
SA0
Front
DQ33
V
SS
DQS4
DQS4
V
SS
DQ34
SCL
SA2
V
TT
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
- 5 -
Unbuffered DIMM
5. x72 DIMM Pin Configurations (Front side/Back side)
Back
V
SS
DQ4
DQ5
V
SS
DM0
NC
V
SS
DQ6
NC
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
NC
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
V
SS
DM3
NC
V
SS
DQ30
DQ31
V
SS
CB4
CB5
V
SS
DM8
27
28
29
30
31
24
25
26
32
33
34
35
36
37
38
39
40
41
9
10
15
16
17
18
11
12
13
14
19
20
21
22
23
5
6
3
4
7
8
Pin
1
2
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
Pin
121
122
129
130
135
136
137
138
131
132
133
134
139
140
141
142
143
123
124
125
126
127
128
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1
DQS1
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
DQ25
V
SS
DQS3
DQS3
V
SS
DQ26
Front
V
REFDQ
V
SS
DQ0
DQ1
V
SS
DQS0
DQ27
V
SS
CB0
CB1
V
SS
67
68
69
70
71
64
65
66
72
73
74
75
76
77
78
79
80
81
49
50
55
56
57
58
51
52
53
54
59
60
61
62
63
Pin
42
43
44
45
46
47
48
Front
NC
NC
V
SS
CB2
CB3
V
SS
NC
NC
A4
V
DD
A2
V
DD
CK1,NC
2
CK1,NC
2
V
DD
V
DD
V
REF
CA
NC
V
DD
A10/AP
BA0
V
DD
WE
CAS
V
DD
S1, NC
1
ODT1, NC
1
V
DD
NC
V
SS
DQ32
CKE0
V
DD
BA2
NC
V
DD
A11
A7
V
DD
A5
KEY
Pin
162
163
164
165
166
167
168
NOTE :
NC = No Connect; NU = Not Used; RFU = Reserved Future Use
1. S1, ODT1, CKE1: Used for dual-rank UDIMMs; NC on single-rank UDIMMs
2. CK1,NC and CK1,NC : Used for dual-rank UDIMMs; not used on single-rank UDIMMs, but terminated
3. TEST (pin 167) used by memory bus analysis tools (unused on memory DIMMs)
Back
NC
V
SS
CB6
CB7
V
SS
NC (TEST)
3
Reset
CK0
CK0
V
DD
EVENT
A0
V
DD
BA1
V
DD
RAS
S0
V
DD
ODT0
A9
V
DD
A8
A6
V
DD
A3
A1
V
DD
V
DD
CKE1,NC
1
V
DD
NC
A14
V
DD
A12/BC
A13
V
DD
NC
V
SS
DQ36
DQ37
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
169
170
175
176
177
178
171
172
173
174
179
180
181
182
183
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Pin
82
83
90
91
96
97
98
99
92
93
94
95
100
101
102
103
104
84
85
86
87
88
89
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
DQ35
V
SS
DQ40
DQ41
V
SS
DQS5
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
DQS6
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7
DQS7
V
SS
DQ58
DQ59
V
SS
SA0
Front
DQ33
V
SS
DQS4
DQS4
V
SS
DQ34
SCL
SA2
V
TT
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Pin
202
203
210
211
216
217
218
219
212
213
214
215
220
221
222
223
224
204
205
206
207
208
209
Rev. 1.2
DDR3 SDRAM
DQ55
V
SS
DQ60
DQ61
V
SS
DM7
NC
V
SS
DQ62
DQ63
V
SS
V
DDSPD
SA1
SDA
V
SS
V
TT
Back
V
SS
DM4
NC
V
SS
DQ38
DQ39
V
SS
DQ44
DQ47
V
SS
DQ52
DQ53
V
SS
DM6
NC
V
SS
DQ54
DQ45
V
SS
DM5
NC
V
SS
DQ46
- 6 -
Unbuffered DIMM
Rev. 1.2
DDR3 SDRAM
6. Pin Description
Pin Name
A0-A14
BA0-BA2
Description
SDRAM address bus
SDRAM bank select
RAS
CAS
WE
SDRAM row address strobe
SDRAM column address strobe
SDRAM write enable
S0, S1
CKE0,CKE1
DIMM Rank Select Lines
SDRAM clock enable lines
ODT0, ODT1 On-die termination control lines
DQ0 - DQ63
CB0 - CB7
DQS0 - DQS8
DQS0-DQS8
DM0-DM8
CK0, CK1
CK0, CK1
DIMM memory data bus
DIMM ECC check bits
SDRAM data strobes
(positive line of differential pair)
SDRAM differential data strobes
(negative line of differential pair)
SDRAM data masks/high data strobes
(x8-based x72 DIMMs)
SDRAM clocks
(positive line of differential pair)
SDRAM clocks
(negative line of differential pair)
NOTE :
* The V
DD
and V
DDQ pins are tied common to a single power-plane on these designs.
** DM8, DQS8 and DQS8 are for ECC UDIMM only.
Pin Name
SCL
SDA
SA0-SA2
V
DD
*
V
DDQ
*
V
REFDQ
V
REFCA
V
SS
V
DDSPD
NC
TEST
RESET
EVENT
V
TT
RFU
Description
I
2
C serial bus clock for EEPROM
I
2
C serial bus data line for EEPROM
I
2
C serial address select for EEPROM
SDRAM core power supply
SDRAM I/O Driver power supply
SDRAM I/O reference supply
SDRAM command/address reference supply
Power supply return (ground)
Serial EEPROM positive power supply
Spare Pins(no connect)
Used by memory bus analysis tools
(unused on memory DIMMs)
Set DRAMs Known State
Reserved for optional temperature-sensing hardware
SDRAM I/O termination supply
Reserved for future use
7. SPD and Thermal Sensor for ECC UDIMMs
On DIMM thermal sensor will provide DRAM temperature readout through a integrated thermal sensor.
EVENT
SCL
R1
0
Ω
R2
0
Ω
WP/EVENT
SA0 SA1
SA0 SA1
SA2
SA2
SDA
NOTE :
1. Raw Cards D (1Rx8 ECC) and E (2Rx8 ECC) support a thermal sensor.
2. When the SPD and the thermal sensor are placed on the module, R1 is placed but R2 is not.
When only the SPD is placed on the module, R2 is placed but R1 is not.
[ Table 1 ] Temperature Sensor Characteristics
Grade
B
Range
75 < Ta < 95
40 < Ta < 125
-20 < Ta < 125
Resolution
Min.
-
-
-
Temperature Sensor Accuracy
Typ. Max.
+/- 0.5
+/- 1.0
+/- 2.0
0.25
+/- 1.0
+/- 2.0
+/- 3.0
Units
°C
°C /LSB
NOTE
-
-
-
-
- 7 -
Unbuffered DIMM
Rev. 1.2
DDR3 SDRAM
8. Input/Output Functional Description
CK0-CK1
CK0-CK1
V
V
V
REFDQ
REFCA
DDQ
Symbol
CKE0-CKE1
S0-S1
RAS, CAS, WE
ODT0-ODT1
BA0-BA2
A0-A14
Type
SSTL
SSTL
Function
CK and CK are differential clock inputs. All the DDR3 SDRAM addr/cntl inputs are sampled on the crossing of positive edge of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of crossing)
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self-Refresh mode
SSTL
Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new command are ignored but previous operations continue. This signal provides for external rank selection on systems with multiple ranks.
SSTL RAS, CAS, and WE (ALONG WITH S) define the command being entered.
SSTL
When high, termination resistance is enabled for all DQ, DQS, DQS and DM pins, assuming the function is enabled in the
Extended Mode Register Set (EMRS).
Supply Reference voltage for SSTL 15 I/O inputs.
Supply Reference voltage for SSTL 15 command/address inputs.
Supply
Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity. For all current DDR3 unbuffered
DIMM designs, V
DDQ
shares the same power plane as V
DD
pins.
SSTL Selects which SDRAM bank of eight is activated.
SSTL
During a Bank Activate command cycle, Address input defines the row address (RA0-RA13)
During a Read or Write command cycle, Address input defines the column address, In addition to the column address,
AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1, BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a precharge command cycle, AP is used in conjunction with BA0, BA1, BA2 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0, BA1 or BA2. If AP is low, BA0, BA1 and BA2 are used to define which bank to precharge. A12(BC) is sampled during READ and WRITE commands to determine if burst chop
(on-the-fly) will be performed (HIGH, no burst chop; Low, burst chopped).
DQ0-DQ63
CB0-CB7
SSTL Data and Check Bit Input/Output pins.
DM0-DM8
V
DD
,V
SS
1 SSTL
Supply
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading.
Power and ground for DDR3 SDRAM input buffers, and core logic. V
DD
and V
DDQ
pins are tied to V
DD
/V
DDQ
planes on these modules.
DQS0-DQS8
1
DQS0-DQS8
1
SSTL Data strobe for input and output data.
SA0-SA2
SDA
SCL
V
DDSPD
RESET
EVENT
-
-
-
Supply
-
Output
These signals and tied at the system planar to either V
SS
or V
DDSPD
to configure the serial SPD EERPOM address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. An external resistor may be connected from the SDA bus line to V
DDSPD
to act as a pull-up on the system board.
This signal is used to clock data into and out of the SPD EEPROM. An external resistor may be connected from the SCL bus time to V
DDSPD
to act as a pull-up on the system board.
Power supply for SPD EEPROM. This supply is separate from the V
DD
/V
DDQ power plane. EEPROM supply is operable from 3.0V to 3.6V.
The RESET pin is connected to the RESET pin on each DRAM. When low, all DRAMs are set to a know state.
This signal indicates that a thermal event has been detected in the thermal sensing device. The system should guarantee the electrical level requirement is met for the EVENT pin on TS/SPD part
NOTE :
1. DM8, DQS8 and DQS8 are for ECC UDIMM only.
- 8 -
Unbuffered DIMM
Rev. 1.2
DDR3 SDRAM
8.1 Address Mirroring Feature
There is a via grid located under the DRAMs for wiring the CA signals (address, bank address, command, and control lines) to the DRAM pins. The length of the traces from the vias to the DRAMs places limitations on the bandwidth of the module. The shorter these traces, the higher the bandwidth. To extend the bandwidth of the CA bus for DDR3 modules, a scheme was defined to reduce the length of these traces.
The pins on the DRAM are defined in a manner that allows for these short trace lengths. The CA bus pins in Columns 2 and 8, ignoring the mechanical support pins, do not have any special functions (secondary functions). This allows the most flexibility with these pins. These are address pins A3, A4, A5,
A6, A7, A8 and bank address pins BA0 and BA1. Refer to Table . Rank 0 DRAM pins are wired straight, with no mismatch between the connector pin assignment and the DRAM pin assignment. Some of the Rank 1 DRAM pins are cross wired as defined in the table. Pins not listed in the table are wired straight.
8.1.1 DRAM Pin Wiring Mirroring
A7
A8
BA0
BA1
A3
A4
A5
A6
DRAM Pin
Connector Pin
Rank 0
A3
A4
A5
A6
A7
A8
BA0
BA1
Rank 1
A4
A3
A6
A5
A8
A7
BA1
BA0
Figure 1. Wiring Differences for Mirrored and Non-Mirrored Addresses
Since the cross-wired pins have no secondary functions, there is no problem in normal operation. Any data written is read the same way. There are limitations however. When writing to the internal registers with a "load mode" operation, the specific address is required. See the DDR3 UDIMM SPD specification for these details. The controller must read the SPD and have the capability of de-mirroring the address when accessing the second rank.
SAMSUNG DDR3 dual rank UDIMM R/C B(2Rx8) and R/C E(2Rx8) Modules are using Mirrored Addresses mode.
- 9 -
Unbuffered DIMM
9. Function Block Diagram:
9.1 2GB, 256Mx64 Non ECC Module (Populated as 1 rank of x8 DDR3 SDRAMs)
Rev. 1.2
DDR3 SDRAM
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D0
ZQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D4
ZQ
DQS1
DQS1
DM1
DQS5
DQS5
DM5
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D1
ZQ
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D5
ZQ
DQS2
DQS2
DM2
DQS6
DQS6
DM6
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D2
ZQ
DQS3
DQS3
DM3
BA0 - BA2
A0 - A13
RAS
CAS
CKE0
WE
ODT0
CK0
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
NU/ CS DQS DQS
D3
ZQ
Serial PD
SCL
BA0-BA2 : SDRAMs D0 - D7
A0-A13 : SDRAMs D0 - D7
RAS : SDRAMs D0 - D7
CAS : SDRAMs D0 - D7
CKE : SDRAMs D0 - D7
WE : SDRAMs D0 - D7
ODT : SDRAMs D0 - D7
CK : SDRAMs D0 - D7
V
DDSPD
V
DD
/V
DDQ
V
REFDQ
V
SS
V
REFCA
WP
A0 A1 A2
SA0 SA1 SA2
DQS7
DQS7
DM7
SDA
SPD
D0 - D7
D0 - D7
D0 - D7
D0 - D7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D6
ZQ
CS DQS DQS
D7
ZQ
NOTE :
1. For each DRAM, a unique ZQ resistor is connected to
ground. The ZQ resistor is 240 Ohm +/- 1%
2. One SPD exists per module.
- 10 -
Unbuffered DIMM
Rev. 1.2
DDR3 SDRAM
9.2 2GB, 256Mx72 ECC Module (Populated as 1 rank of x8 DDR3 SDRAMs)
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D0
ZQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D4
ZQ
DQS1
DQS1
DM1
DQS5
DQS5
DM5
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D1
ZQ
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D5
ZQ
DQS2
DQS2
DM2
DQS6
DQS6
DM6
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D2
ZQ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D6
ZQ
DQS3
DQS3
DM3
DQS7
DQS7
DM7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D3
ZQ
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D7
ZQ
DQS8
DQS8
DM8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D8
ZQ
SCL
EVENT
Serial PD
EVENT
A0 A1 A2
SA0 SA1 SA2
SDA
BA0 - BA2
A0 - A15
RAS
CAS
CKE0
WE
ODT0
CK0
BA0-BA2 : SDRAMs D0 - D8
A0-A15 : SDRAMs D0 - D8
V
DDSPD
V
DD
/V
DDQ
RAS : SDRAMs D0 - D8
V
REFDQ
CAS : SDRAMs D0 - D8
V
SS
CKE : SDRAMs D0 - D8
V
REFCA
WE : SDRAMs D0 - D8
ODT : SDRAMs D0 - D8
CK : SDRAMs D0 - D8
SPD
D0 - D8
D0 - D8
D0 - D8
D0 - D8
NOTE :
1. For each DRAM, a unique ZQ resistor is connected to
ground. The ZQ resistor is 240 Ohm +/- 1%
2. Refer to "SPD and Thermal sensor for ECC UDIMMs" for SPD detail.
- 11 -
Unbuffered DIMM
Rev. 1.2
DDR3 SDRAM
9.3 4GB, 512Mx64 Non ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs)
S1
S0
DQS0
DQS0
DM0
DQS1
DQS1
DM1
DQS2
DQS2
DM2
DQS3
DQS3
DM3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D0
ZQ
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D1
ZQ
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D2
ZQ
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D3
ZQ
DQS4
DQS4
DM4
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D8
ZQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DQS5
DM5
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D9
ZQ
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D11
ZQ
DQS6
DQS6
DM6
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D10
ZQ
DQS7
DQS7
DM7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D4
ZQ
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D5
ZQ
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D6
ZQ
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D7
ZQ
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D12
ZQ
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D13
ZQ
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D14
ZQ
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D15
ZQ
BA0 - BA2
A0 - A15
CKE1
CKE0
RAS
CAS
WE
ODT0
ODT1
CK0
CK1
BA0-BA2 : SDRAMs D0 - D15
A0-A15 : SDRAMs D0 - D15
CKE : SDRAMs D8 - D15
CKE : SDRAMs D0 - D7
RAS : SDRAMs D0 - D15
CAS : SDRAMs D0 - D15
WE : SDRAMs D0 - D15
ODT : SDRAMs D0 - D7
ODT : SDRAMs D8 - D15
CK : SDRAMs D0 - D7
CK : SDRAMs D8 - D15
SCL
V
DDSPD
V
DD
/V
DDQ
V
REFDQ
V
SS
V
REFCA
Serial PD
WP
A0 A1 A2
SA0 SA1 SA2
SDA
SPD
D0 - D15
D0 - D15
D0 - D15
D0 - D15
NOTE :
1. For each DRAM, a unique ZQ resistor is connected to
ground. The ZQ resistor is 240 Ohm +/- 1%
2. One SPD exists per module.
- 12 -
BA0 - BA2
A0 - A15
CKE1
CKE0
RAS
CAS
WE
ODT0
ODT1
CK0
CK1
Unbuffered DIMM
9.4 4GB, 512Mx72 ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs)
S1
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D0
ZQ
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D9
ZQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D4
ZQ
Rev. 1.2
DDR3 SDRAM
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D13
ZQ
DQS1
DQS1
DM1
DQS5
DQS5
DM5
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D1
ZQ
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D10
ZQ
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D5
ZQ
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D14
ZQ
DQS2
DQS2
DM2
DQS6
DQS6
DM6
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D2
ZQ
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D11
ZQ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D6
ZQ
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D15
ZQ
DQS3
DQS3
DM3
DQS7
DQS7
DM7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D3
ZQ
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D12
ZQ
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D7
ZQ
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D16
ZQ
DQS8
DQS8
DM8
SCL
EVENT
Serial PD
EVENT
A0 A1 A2
SA0 SA1 SA2
SDA
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D8
ZQ
BA0-BA2 : SDRAMs D0 - D17
A0-A15 : SDRAMs D0 - D17
CKE : SDRAMs D9 - D17
CKE : SDRAMs D0 - D8
RAS : SDRAMs D0 - D17
CAS : SDRAMs D0 - D17
WE : SDRAMs D0 - D17
ODT : SDRAMs D0 - D8
ODT : SDRAMs D9 - D17
CK : SDRAMs D0 - D8
CK : SDRAMs D9 - D17
V
DDSPD
V
DD
/V
DDQ
V
REFDQ
V
SS
V
REFCA
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D17
ZQ
SPD
D0 - D17
D0 - D17
D0 - D17
D0 - D17
NOTE :
1. For each DRAM, a unique ZQ resistor is connected to
ground. The ZQ resistor is 240 Ohm +/- 1%
2. Refer to "SPD and Thermal sensor for ECC UDIMMs"
for SPD detail.
- 13 -
Unbuffered DIMM
Rev. 1.2
DDR3 SDRAM
10. Absolute Maximum Ratings
10.1 Absolute Maximum DC Ratings
Symbol
V
DD
V
DDQ
V
IN,
V
OUT
T
STG
Parameter
Voltage on V
DD
pin relative to V
SS
Voltage on V
DDQ
pin relative to V
SS
Voltage on any pin relative to V
SS
Storage Temperature
Rating
-0.4 V ~ 1.975 V
-0.4 V ~ 1.975 V
-0.4 V ~ 1.975 V
-55 to +100
Units
V
V
V
NOTE
1,3
1,3
1
NOTE :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
3. V
DD
and V
DDQ
must be within 300mV of each other at all times; and V
REF
must be not greater than 0.6 x V
DDQ
, When V
DD
and V
DDQ
are less than 500mV; V
REF
may be equal to or less than 300mV.
10.2 DRAM Component Operating Temperature Range
Symbol
T
OPER
Parameter
Operating Temperature Range rating
0 to 95
Unit
°C
NOTE
1, 2, 3
NOTE :
1. Operating Temperature T
OPER
is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document
JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0-85
°C under all operating conditions
3. Some applications require operation of the Extended Temperature Range between 85
°C and 95°C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us. It is also possible to specify a component with 1X refresh (tREFI to 7.8us) in the Extended Temperature Range.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature
Range capability (MR2 A6 = 0b and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range.
11. AC & DC Operating Conditions
11.1 Recommended DC Operating Conditions (SSTL-15)
Symbol Parameter
V
DD
V
DDQ
Supply Voltage
Supply Voltage for Output
Min.
1.425
1.425
NOTE:
1. Under all conditions V
DDQ
must be less than or equal to V
DD
.
2. V
DDQ
tracks with V
DD
. AC parameters are measured with V
DD
and V
DDQ
tied together.
Rating
Typ.
1.5
1.5
Max.
1.575
1.575
Units
V
V
NOTE
1,2
1,2
- 14 -
Unbuffered DIMM
Rev. 1.2
DDR3 SDRAM
12. AC & DC Input Measurement Levels
12.1 AC & DC Logic Input Levels for Single-ended Signals
[ Table 2 ] Single Ended AC and DC input levels for Command and Address
Symbol Parameter
V
IH.CA
(DC) DC input logic high
V
IL.CA
(DC) DC input logic low
V
IH.CA
(AC) AC input logic high
V
IL.CA
(AC) AC input logic low
V
IH.CA
(AC150) AC input logic high
V
IL.CA
(AC150) AC input logic low
V
REFCA
(DC)
Reference Voltage for ADD,
CMD inputs
Min.
V
REF
+ 100
V
SS
V
REF
+ 175
DDR3-800/1066
Max.
V
DD
V
REF
- 100
-
V
REF
- 175
V
REF
+150
-
0.49*V
DD
-
V
REF
-150
0.51*V
DD
Min.
DDR3-1333/1600
Max.
V
REF
+ 100
V
SS
V
REF
+ 175
V
V
REF
DD
- 100
-
V
REF
- 175
V
REF
+150
-
0.49*V
DD
NOTE :
1. For input only pins except RESET, V
REF
= V
REFCA
(DC)
2. See "Overshoot and Undershoot specifications" section.
3. The AC peak noise on V
REF
may not allow V
REF
to deviate from V
REF
(DC) by more than ± 1% V
DD
(for reference : approx. ± 15mV)
4. For reference : approx. V
DD
/2 ± 15mV
-
V
REF
-150
0.51*V
DD
Unit NOTE mV mV mV mV mV mV
V
1,2
1,2
1,2
1
1
1,2
3,4
[ Table 3 ] Single Ended AC and DC input levels for DQ and DM
Symbol Parameter
V
IH.DQ
(DC100) DC input logic high
V
IL.DQ
(DC100) DC input logic low
V
IH.DQ
(AC175) AC input logic high
V
IL.DQ
(AC175) AC input logic low
V
IH.DQ
(AC150) AC input logic high
V
IL.DQ
(AC150) AC input logic low
V
REF DQ
(DC) I/O Reference Voltage(DQ)
Min.
V
REF
+ 100
V
SS
V
REF
+ 175
DDR3-800/1066
Max.
V
DD
V
REF
- 100
-
V
REF
- 175
V
REF
+ 150
NOTE 2
0.49*V
DD
NOTE 2
V
REF
- 150
0.51*V
DD
Min.
DDR3-1333/1600
Max.
V
REF
+ 100
V
SS
V
REF
+ 150
-
-
-
0.49*V
DD
V
V
REF
DD
- 100
-
V
REF
- 150
-
-
0.51*V
DD
NOTE :
1. For input only pins except RESET, V
REF
= V
REFDQ
(DC)
2. See "Overshoot and Undershoot specifications" section.
3. The AC peak noise on V
REF
may not allow V
REF
to deviate from V
REF
(DC) by more than ± 1% V
DD
(for reference : approx. ± 15mV)
4. For reference : approx. V
DD
/2 ± 15mV
5. Single ended swing requirement for DQS - DQS is 350mV (peak to peak). Differential swing requirement for DQS - DQS is 700mV (peak to peak).
Unit NOTE mV mV mV mV mV mV
V
1
1
1,2,5
1,2,5
1,2,5
1,2,5
3,4
- 15 -
Unbuffered DIMM
Rev. 1.2
DDR3 SDRAM
12.2 V
REF
Tolerances.
The dc-tolerance limits and ac-noise limits for the reference voltages V
REFCA
and V
REFDQ
are illustrate in Figure 2. It shows a valid reference voltage
V
REF
(t) as a function of time. (V
REF
stands for V
REFCA
and V
REFDQ
likewise).
V
REF
(DC) is the linear average of V
REF
(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements of V
REF
. Furthermore V
REF
(t) may temporarily deviate from V
REF
(DC) by no more than ± 1% V
DD
.
voltage
V
DD
V
SS
Figure 2. Illustration of VREF(DC) tolerance and VREF ac-noise limits time
The voltage levels for setup and hold time measurements V
IH
(AC), V
IH
(DC), V
IL
(AC) and V
IL
(DC) are dependent on V
REF
.
"V
REF
" shall be understood as V
REF
This clarifies, that dc-variations of V
REF
affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for V
REF
(DC) deviations from the optimum position within the data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V
REF
ac-noise.
Timing and voltage effects due to ac-noise on V
REF
up to the specified limit (+/-1% of V
DD
) are included in DRAM timings and their associated deratings.
- 16 -
Unbuffered DIMM
12.3 AC and DC Logic Input Levels for Differential Signals
12.3.1 Differential Signals Definition tDVAC
V
IH
.DIFF.AC.MIN
V
IH
.DIFF.MIN
0.0
half cycle
V
IL
.DIFF.MAX
V
IL
.DIFF.AC.MAX
tDVAC time
Figure 3. Definition of differential ac-swing and "time above ac level" tDVAC
Rev. 1.2
DDR3 SDRAM
12.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS)
Symbol Parameter min
+0.2
DDR3-800/1066/1333/1600 max
NOTE 3 unit NOTE
V
IHdiff
V
ILdiff
V
IHdiff
(AC)
V
ILdiff
(AC) differential input high differential input low differential input high ac
NOTE 3
2 x (V
IH
(AC)-V
REF
)
NOTE 3
-0.2
NOTE 3
V
V
V
1
1
2 differential input low ac 2 x (V
REF
- V
IL
(AC)) V 2
NOTE :
1. Used to define a differential signal slew-rate.
2. for CK - CK use V
IH
/V
IL
(AC) of ADD/CMD and V
REFCA
; for DQS - DQS use V
IH
/V
IL
(AC) of DQs and V
REFDQ
; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL need to be within the respective limits (V
IH
(DC) max, V
IL
(DC)min) for singleended signals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undersheet Specification"
[ Table 4 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS.
Slew Rate [V/ns]
> 4.0
4.0
3.0
2.0
1.8
1.6
1.4
1.2
1.0
< 1.0
tDVAC [ps] @ |V
IH/Ldiff
(AC)| = 350mV min
75 max
-
57
50
38
34
-
-
-
-
29
22
13
0
0
-
-
-
-
tDVAC [ps] @ |V
IH/Ldiff
(AC)| = 300mV min
175 max
-
170
167
163
162
-
-
-
-
161
159
155
150
150
-
-
-
-
-
- 17 -
Unbuffered DIMM
Rev. 1.2
DDR3 SDRAM
12.3.3 Single-ended Requirements for Differential Signals
Each individual component of a differential signal (CK, DQS, CK, DQS) has also to comply with certain requirements for single-ended signals.
CK and CK have to approximately reach V
SEH min / V
SEL max (approximately equal to the ac-levels ( V
IH
(AC) / V
IL
(AC) ) for ADD/CMD signals) in every half-cycle.
DQS have to reach V
SEH min / V
SEL max (approximately the ac-levels ( V
IH
(AC) / V
IL
(AC) ) for DQ signals) in every half-cycle proceeding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if V
IH
150(AC)/V
IL
150(AC) is used for ADD/CMD signals, then these ac-levels apply also for the single-ended signals CK and CK .
V
DD
or V
DDQ
V
SEH
min
V
SEH
V
DD
/2 or V
DDQ
/2
CK or DQS
V
SEL
max
V
SEL
V
SS
or V
SSQ time
Figure 4. Single-ended requirement for differential signals
Note that while ADD/CMD and DQ signal requirements are with respect to V
REF
, the single-ended components of differential signals have a requirement with respect to V
DD
/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For singleended components of differential signals the requirement to reach V
SEL max, V
SEH min has no bearing on timing, but adds a restriction on the common mode characteristics of these signals.
[ Table 5 ] Single ended levels for CK, DQS, CK, DQS
Symbol
V
V
SEH
SEL
Parameter
Single-ended high-level for strobes
Single-ended high-level for CK, CK
Single-ended low-level for strobes
Single-ended low-level for CK, CK
DDR3-800/1066/1333/1600
Min
(V
DD
/2)+0.175
Max
NOTE 3
(V
DD
/2)+0.175
NOTE 3
NOTE 3
(V
NOTE 3
DD
/2)-0.175
(V
DD
/2)-0.175
Unit
V
V
V
V
NOTE
1, 2
1, 2
1, 2
1, 2
NOTE :
1. For CK, CK use V
IH
/V
IL
2. V
IH
(AC)/V
IL
(AC) of ADD/CMD; for strobes (DQS, DQS) use V
(AC) for DQs is based on V
REFDQ
; V
IH
IH
/V
IL
(AC) of DQs.
(AC)/V
IL
(AC) for ADD/CMD is based on V
REFCA
; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here
3. These values are not defined, however the single-ended signals CK, CK, DQS, DQS need to be within the respective limits (V
IH
(DC) max, V
IL
(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specification"
- 18 -
Unbuffered DIMM
Rev. 1.2
DDR3 SDRAM
12.3.4 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage V
IX
is measured from the actual cross point of true and complement signal to the mid level between of V
DD
and V
SS
.
V
DD
CK, DQS
V
IX
V
DD
/2
V
IX
V
IX
CK, DQS
V
SS
Figure 5. V
IX
Definition
[ Table 6 ] Cross point voltage for differential input signals (CK, DQS)
Symbol
V
IX
Parameter
Differential Input Cross Point Voltage relative to V
DD
/2 for CK,CK
DDR3-800/1066/1333/1600
Min Max
-150
-175
150
175
-150 150
Unit mV mV mV
NOTE
1
V
IX
Differential Input Cross Point Voltage relative to V
DD
/2 for DQS,DQS
NOTE :
1. Extended range for V
IX
is only allowed for clock and if single-ended clock input signals CK and CK are monotonic, have a single-ended swing V
±250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns.
SEL
/ V
SEH
of at least V
DD
/2
12.4 Slew Rate Definition for Single Ended Input Signals
See "Address / Command Setup, Hold and Derating" for single-ended slew rate definitions for address and command signals.
See "Data Setup, Hold and Slew Rate Derating" for single-ended slew rate definitions for data signals.
12.5 Slew rate definition for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in below.
[ Table 7 ] Differential input slew rate definition
Description
Differential input slew rate for rising edge (CK-CK and DQS-DQS)
From
Measured
To
V
ILdiffmax
V
IHdiffmin
Differential input slew rate for falling edge (CK-CK and DQS-DQS) V
IHdiffmin
NOTE : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds
V
ILdiffmax
V
IHdiffmin
0
V
ILdiffmax delta TFdiff delta TRdiff
Figure 6. Differential input slew rate definition for DQS, DQS and CK, CK
Defined by
V
IHdiffmin
- V
ILdiffmax
Delta TRdiff
V
IHdiffmin
- V
ILdiffmax
Delta TFdiff
- 19 -
Unbuffered DIMM
Rev. 1.2
DDR3 SDRAM
13. AC & DC Output Measurement Levels
13.1 Single Ended AC and DC Output Levels
[ Table 8 ] Single Ended AC and DC output levels
Symbol
V
OH
V
V
OM
OL
(DC) DC output high measurement level (for IV curve linearity)
(DC)
(DC)
Parameter
DC output mid measurement level (for IV curve linearity)
DC output low measurement level (for IV curve linearity)
DDR3-800/1066/1333/1600
0.8 x V
DDQ
0.5 x V
DDQ
0.2 x V
DDQ
Units
V
V
V
NOTE
V
OH
(AC) AC output high measurement level (for output SR) V
TT
+ 0.1 x V
DDQ
V 1
V
OL
(AC) AC output low measurement level (for output SR) V
TT
- 0.1 x V
DDQ
V 1
NOTE : 1. The swing of +/-0.1 x V
DDQ load of 25
Ω to V
TT
=V
DDQ
is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40
Ω and an effective test
/2.
13.2 Differential AC and DC Output Levels
[ Table 9 ] Differential AC and DC output levels
Symbol Parameter DDR3-800/1066/1333/1600 Units NOTE
V
OHdiff
(AC) AC differential output high measurement level (for output SR) +0.2 x V
DDQ
V 1
V
OLdiff
(AC) AC differential output low measurement level (for output SR) -0.2 x V
DDQ
V 1
NOTE : 1. The swing of +/-0.2xV
DDQ load of 25
Ω to V
TT
=V
DDQ
is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40
Ω and an effective test
/2 at each of the differential outputs.
13.3 Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V
OL
(AC) and V
OH
(AC) for single ended signals as shown in below.
[ Table 10 ] Single ended Output slew rate definition
Measured
Description Defined by
From To
Single ended output slew rate for rising edge
Single ended output slew rate for falling edge
V
V
OL
OH
(AC)
(AC)
V
V
OH
OL
(AC)
(AC)
V
OH
(AC)-V
OL
(AC)
Delta TRse
V
OH
(AC)-V
OL
(AC)
Delta TFse
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 11 ] Single ended output slew rate
Parameter Symbol
DDR3-800
Min Max
2.5
5 Single ended output slew rate SRQse
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output) se : Single-ended Signals
For Ron = RZQ/7 setting
DDR3-1066
Min Max
2.5
5
DDR3-1333
Min Max
2.5
5
DDR3-1600
Min Max
2.5
5
Units
V/ns
V
OHdiff
(AC)
V
TT
V
OLdiff
(AC) delta TFdiff delta TRdiff
Figure 7. Single-ended output slew rate definition
- 20 -
Unbuffered DIMM
Rev. 1.2
DDR3 SDRAM
13.4 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V
OLdiff
(AC) and V
OHdiff
(AC) for differential signals as shown in below.
[ Table 12 ] Differential Output slew rate definition
Description
Differential output slew rate for rising edge
From
Measured
To
V
OLdiff
(AC) V
OHdiff
(AC)
Differential output slew rate for falling edge V
OHdiff
(AC) V
OLdiff
(AC)
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
Defined by
V
OHdiff
(AC)-V
OLdiff
(AC)
Delta TRdiff
V
OHdiff
(AC)-V
OLdiff
(AC)
Delta TFdiff
[ Table 13 ] Differential Output slew rate
Parameter Symbol
DDR3-800
Min Max
5 10 Differential output slew rate SRQdiff
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output) diff : Differential Signals
For Ron = RZQ/7 setting
DDR3-1066
Min Max
5 10
DDR3-1333
Min Max
5 10
DDR3-1600
Min Max
5 10
Units
V/ns
V
OHdiff
(AC)
V
TT
V
OLdiff
(AC) delta TFdiff delta TRdiff
Figure 8. Differential output slew rate definition
- 21 -
Unbuffered DIMM
Rev. 1.2
DDR3 SDRAM
14. DIMM IDD specification definition
Symbol
IDD0
IDD1
IDD2N
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
IDD5B
IDD6
IDD6ET
IDD7
IDD8
Description
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: 0; CS: High between ACT and PRE;
Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers
2)
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Operating One Bank Active-Read-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: 0; CS: High between ACT, RD and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers
2)
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode
Registers
2)
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
2)
;
ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exit
3)
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
2)
;
ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit
3)
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
2)
;
ODT Signal: stable at 0
Active Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode
Registers
2)
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers
2)
; ODT
Signal: stable at 0
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: 0; CS: High between RD; Command, Address,
Bank Address Inputs: partially toggling ; Data IO: seamless read data burst with different data between one burst and the next one ; DM:stable at 0; Bank
Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers
2)
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: 0; CS: High between WR; Command, Address,
Bank Address Inputs: partially toggling ; Data IO: seamless write data burst with different data between one burst and the next one ; DM: stable at 0; Bank
Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers
2)
; ODT Signal: stable at HIGH; Pattern Details: Refer to Component Datasheet for detail pattern
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: 0; CS: High between REF; Command,
Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC ; Output Buffer and
RTT: Enabled in Mode Registers
2)
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled
4)
; Self-Refresh Temperature Range (SRT): Normal
5)
; CKE: Low; External clock: Off; CK and CK:
LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;
Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers
2)
; ODT Signal: FLOATING
Self-Refresh Current: Extended Temperature Range (optional)
6)
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled
4)
; Self-Refresh Temperature Range (SRT): Extended
5)
; CKE: Low; External clock: Off; CK and CK:
LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;
Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers
2)
; ODT Signal: FLOATING
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern ; BL: 8
1)
; AL: CL-1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling ; Data IO: read data bursts with different data between one burst and the next one ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing ; Output Buffer and RTT:
Enabled in Mode Registers
2)
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
RESET Low Current
RESET : Low; External clock : off; CK and CK : LOW; CKE : FLOATING ; CS, Command, Address, Bank Address, Data IO : FLOATING ; ODT Signal :
FLOATING
- 22 -
Unbuffered DIMM
Rev. 1.2
DDR3 SDRAM
NOTE :
1) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
2) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B
3) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
4) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
5) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range
6) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device
7) IDD current measure method and detail patterns are described on DDR3 component datasheet
8) VDD and VDDQ are merged on module PCB.
9) DIMM IDD SPEC is measured with Qoff condition
(IDDQ values are not considered)
- 23 -
Unbuffered DIMM
15. IDD SPEC Table
M378B5773CH0 : 2GB(256Mx64) Module
Symbol
IDD0
IDD1
IDD2P0(slow exit)
IDD2P1(fast exit)
IDD2N
IDD2Q
IDD3P(fast exit)
IDD3N
IDD4R
IDD4W
IDD5B
IDD6
IDD7
IDD8
CF8
(DDR3-1066@CL=7)
440
560
96
160
240
240
240
400
800
920
1360
96
1360
96
CH9
(DDR3-1333@CL=9)
480
600
96
160
280
240
240
440
920
1120
1360
96
1680
96
NOTE :
1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N.
Rev. 1.2
DDR3 SDRAM
CK0
(DDR3-1600@CL=11)
520
640
96
200
280
280
280
480
1040
1200
1440
96
1720
96
Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA
NOTE
1
1
1
1
1
1
M391B5773CH0 : 2GB(256Mx72) Module
Symbol
IDD0
IDD1
IDD2P0(slow exit)
IDD2P1(fast exit)
IDD2N
IDD2Q
IDD3P(fast exit)
IDD3N
IDD4R
IDD4W
IDD5B
IDD6
IDD7
IDD8
CF8
(DDR3-1066@CL=7)
495
630
108
180
270
270
270
450
900
1035
1530
108
1530
108
CH9
(DDR3-1333@CL=9)
540
675
108
180
315
270
270
495
1035
1260
1530
108
1890
108
NOTE :
1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N.
CK0
(DDR3-1600@CL=11)
585
720
108
225
315
315
315
540
1170
1350
1620
108
1935
108
Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA
NOTE
1
1
1
1
1
1
- 24 -
Unbuffered DIMM
Rev. 1.2
DDR3 SDRAM
M378B5273CH0 : 4GB(512Mx64) Module
Symbol
IDD0
IDD1
IDD2P0(slow exit)
IDD2P1(fast exit)
IDD2N
IDD2Q
IDD3P(fast exit)
IDD3N
IDD4R
IDD4W
IDD5B
IDD6
IDD7
IDD8
CF8
(DDR3-1066@CL=7)
680
800
192
320
480
480
480
640
1040
1160
1600
192
1600
192
CH9
(DDR3-1333@CL=9)
760
880
192
320
560
480
480
720
1200
1400
1640
192
1960
192
NOTE :
1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N.
CK0
(DDR3-1600@CL=11)
800
920
192
400
560
560
560
760
1320
1480
1720
192
2000
192
Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA
NOTE
1
1
1
1
1
1
M391B5273CH0 : 4GB(512Mx72) Module
Symbol
IDD0
IDD1
IDD2P0(slow exit)
IDD2P1(fast exit)
IDD2N
IDD2Q
IDD3P(fast exit)
IDD3N
IDD4R
IDD4W
IDD5B
IDD6
IDD7
IDD8
CF8
(DDR3-1066@CL=7)
765
900
216
360
540
540
540
720
1170
1305
1800
216
1800
216
CH9
(DDR3-1333@CL=9)
855
990
216
360
630
540
540
810
1350
1575
1845
216
2205
216
NOTE :
1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N.
CK0
(DDR3-1600@CL=11)
900
1035
216
450
630
630
630
855
1485
1665
1935
216
2250
216
Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA
NOTE
1
1
1
1
1
1
- 25 -
Unbuffered DIMM
16. Input/Output Capacitance
16.1 Non ECC UDIMM
Parameter
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input capacitance (CK and CK)
Input capacitance (All other input-only pins)
Parameter
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input capacitance (CK and CK)
Input capacitance (All other input-only pins)
16.2 ECC UDIMM
Parameter
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input capacitance (CK and CK)
Input capacitance (All other input-only pins)
Symbol
CIO
CCK
CI
Symbol
CIO
CCK
CI
Symbol
CIO
CCK
CI
Parameter
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input capacitance (CK and CK)
Input capacitance (All other input-only pins)
Symbol
CIO
CCK
CI
Rev. 1.2
DDR3 SDRAM
DDR3-1066
Min Max
TBD
-
-
TBD
TBD
M378B5773CH0
DDR3-1333
Min Max
TBD
-
-
TBD
TBD
DDR3-1600
Min Max
TBD
-
-
TBD
TBD
Units NOTE pF pF pF
DDR3-1066
Min Max
TBD
-
-
TBD
TBD
M378B5273CH0
DDR3-1333
Min Max
-
-
-
TBD
TBD
TBD
DDR3-1600
Min Max
TBD
-
-
TBD
TBD
Units NOTE pF pF pF
DDR3-1066
Min Max
TBD
-
-
TBD
TBD
M391B5773CH0
DDR3-1333
Min Max
TBD
-
-
TBD
TBD
DDR3-1600
Min Max
TBD
-
-
TBD
TBD
Units NOTE pF pF pF
DDR3-1066
Min Max
-
-
-
TBD
TBD
TBD
M391B5273CH0
DDR3-1333
Min Max
-
-
-
TBD
TBD
TBD
DDR3-1600
Min Max
-
-
-
TBD
TBD
TBD
Units NOTE pF pF pF
- 26 -
Unbuffered DIMM
17. Electrical Characteristics and AC timing
(0
°C<T
CASE
≤95 °C, V
DDQ
= 1.5V
± 0.075V; V
DD
= 1.5V
± 0.075V)
Rev. 1.2
DDR3 SDRAM
17.1 Refresh Parameters by Device Density
Parameter
All Bank Refresh to active/refresh cmd time
Average periodic refresh interval tREFI
Symbol tRFC
0
°C ≤ T
CASE
≤ 85°C
85
°C < T
CASE
≤ 95°C
1Gb
110
7.8
3.9
2Gb
160
7.8
3.9
4Gb
300
7.8
3.9
8Gb
350
7.8
3.9
Units ns
μs
μs
NOTE
1
NOTE :
1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this material.
17.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
Bin (CL - tRCD - tRP)
Parameter
CL tRCD tRP tRAS tRC tRRD tFAW
DDR3-800
6-6-6 min
6
15
15
37.5
52.5
10
40
DDR3-1066
7-7-7 min
7
13.13
13.13
37.5
50.63
7.5
37.5
DDR3-1333
9-9-9 min
9
13.5
13.5
36
49.5
6.0
30
DDR3-1600
11-11-11 min
11
13.75
13.75
35
48.75
6.0
30
Units tCK ns ns ns ns ns ns
NOTE
17.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin
DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
[ Table 14 ] DDR3-800 Speed Bins
Speed
CL-nRCD-nRP
Parameter
Internal read command to first data
ACT to internal read or write delay time
PRE command period
ACT to ACT or REF command period
ACT to PRE command period
CL = 6 / CWL = 5
Supported CL Settings
Supported CWL Settings
Symbol tAA tRCD tRP tRC tRAS tCK(AVG) min
15
15
15
52.5
37.5
2.5
DDR3-800
6 - 6 - 6 max
20
-
-
-
9*tREFI
3.3
6
5
Units ns ns nCK nCK ns ns ns ns
NOTE
1,2,3
- 27 -
Unbuffered DIMM
[ Table 15 ] DDR3-1066 Speed Bins
Speed
CL-nRCD-nRP
Parameter
Internal read command to first data
ACT to internal read or write delay time
PRE command period
ACT to ACT or REF command period
ACT to PRE command period
CL = 6
CL = 7
CL = 8
CWL = 5
CWL = 6
CWL = 5
CWL = 6
CWL = 5
CWL = 6
Supported CL Settings
Supported CWL Settings
Symbol tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) min
13.125
13.125
13.125
50.625
37.5
2.5
1.875
1.875
DDR3-1066
7 - 7 - 7 max
20
-
-
-
9*tREFI
3.3
Reserved
Reserved
<2.5
Reserved
<2.5
6,7,8
5,6
[ Table 16 ] DDR3-1333 Speed Bins
Speed
CL-nRCD-nRP
Parameter
Internal read command to first data
ACT to internal read or write delay time
PRE command period
ACT to ACT or REF command period
ACT to PRE command period
CL = 6
CWL = 5
CWL = 6
CWL = 7
CWL = 5
CL = 7
CL = 8
CL = 9
CWL = 6
CWL = 7
CWL = 5
CWL = 6
CWL = 7
CWL = 5,6
CWL = 7
CWL = 5,6
CL = 10
CWL = 7
Supported CL Settings
Supported CWL Settings
Symbol tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) min
13.5 (13.125)
8
13.5 (13.125)
8
13.5 (13.125)
8
49.5 (49.125)
8
DDR3-1333
9 -9 - 9
36
2.5
Reserved
Reserved
Reserved
1.875
(Optional) NOTE 8
Reserved
Reserved max
20
-
-
-
9*tREFI
3.3
<2.5
1.875
<2.5
Reserved
Reserved
1.5
<1.875
Reserved
1.5
<1.875
(Optional)
6,7,8,9
5,6,7
Rev. 1.2
DDR3 SDRAM
Units ns ns ns ns ns ns ns ns ns ns ns nCK nCK
NOTE
1,2,3,5
1,2,3,4
4
1,2,3,4
4
1,2,3
Units ns ns ns ns ns ns ns ns ns ns nCK nCK ns ns ns ns ns ns ns ns ns
NOTE
1,2,3,6
1,2,3,4,6
4
4
1,2,3,4,6
1,2,3,4
4
1,2,3,6
1,2,3,4
4
1,2,3,4
4
1,2,3
- 28 -
Unbuffered DIMM
[ Table 17 ] DDR3-1600 Speed Bins
Speed
CL-nRCD-nRP
Parameter
Intermal read command to first data
ACT to internal read or write delay time
PRE command period
ACT to ACT or REF command period
ACT to PRE command period
CL = 6
CWL = 5
CWL = 6
CWL = 7, 8
CWL = 5
CWL = 6
CL = 7
CL = 8
CL = 9
CWL = 7
CWL = 8
CWL = 5
CWL = 6
CWL = 7
CWL = 8
CWL = 5,6
CWL = 7
CL = 10
CL = 11
Supported CL Settings
Supported CWL Settings
CWL = 8
CWL = 5,6
CWL = 7
CWL = 8
CWL = 5,6,7
CWL = 8
Symbol tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG)
DDR3-1600
11-11-11 min
13.75
(13.125)
8
13.75
(13.125)
8
13.75
(13.125)
8
48.75
(48.125)
8
35
2.5
max
20
-
-
-
9*tREFI
3.3
Reserved
Reserved
Reserved
1.875
<2.5
(Optional) NOTE 8
Reserved
Reserved
Reserved
1.875
1.5
1.5
1.25
<2.5
Reserved
Reserved
Reserved
(Optional) NOTE 8
TBD
Reserved
<1.875
<1.875
(Optional) NOTE 8
Reserved
Reserved
<1.5
6,7,8,9,10,11
5,6,7,8
Rev. 1.2
DDR3 SDRAM
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns nCK nCK
NOTE
1,2,3,4
4
1,2,3,7
1,2,3,4
4
1,2,3
1,2,3,7
1,2,3,4,7
4
4
1,2,3,4,7
1,2,3,4,7
4
4
1,2,3,7
1,2,3,4,7
1,2,3,4
4
1,2,3,4,7
- 29 -
Unbuffered DIMM
Rev. 1.2
DDR3 SDRAM
17.3.1 Speed Bin Table Notes
Absolute Specification (T
OPER
; V
DDQ
= V
DD
= 1.5V +/- 0.075 V);
NOTE :
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next "SupportedCL".
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or
1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED.
4. "Reserved" settings are not allowed. User must program a different value.
5. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
6. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
7. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
8. For devices supporting optional downshift to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 ns or lower. SPD settings must be programmed to match. For example,
DDR3-1333(CL9) devices supporting downshift to DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte
20). DDR3-1600(CL11) devices supporting downshift to DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte16), tRCDmin (Byte
18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accordingly. For example, 49.125ns (tRASmin
+ tRPmin=36ns+13.125ns) for DDR3-1333(CL9) and 48.125ns (tRASmin+tRPmin=35ns+13.125ns) for DDR3-1600(CL11).
- 30 -
Unbuffered DIMM
Rev. 1.2
DDR3 SDRAM
18. Timing Parameters by Speed Grade
[ Table 18 ] Timing Parameters by Speed Bin
Speed
Parameter Symbol
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
Average Clock Period tCK(DLL_OF
F) tCK(avg)
DDR3-800
MIN MAX
8 -
Clock Period
Average high pulse width
Average low pulse width
Clock Period Jitter
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
Cycle to Cycle Period Jitter during DLL locking period
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles tCK(abs) tCH(avg) tCL(avg) tJIT(per) tJIT(per, lck) tJIT(cc) tJIT(cc, lck) tERR(2per) tERR(3per) tERR(4per) tERR(5per) tERR(6per) tERR(7per) tERR(8per) tERR(9per) tERR(10per) tERR(11per) tERR(12per)
0.47
0.47
-100
-90
- 147
- 175
- 194
- 209
- 222
- 232
- 241
- 249
- 257
- 263
- 269
200
180
222
232
241
249
147
175
194
209
257
263
269
0.53
0.53
100
90
Cumulative error across n = 13, 14 ... 49, 50 cycles tERR(nper)
Absolute clock HIGH pulse width
Absolute clock Low pulse width
Data Timing
DQS,DQS to DQ skew, per group, per access tCH(abs) tCL(abs)
DQ output hold time from DQS, DQS
DQ low-impedance time from CK, CK
DQ high-impedance time from CK, CK
Data setup time to DQS, DQS referenced to
V
IH
(AC)V
IL
(AC) levels
Data hold time to DQS, DQS referenced to
V
IH
(AC)V
IL
(AC) levels
DQ and DM Input pulse width for each input tDQSQ tQH tLZ(DQ) tHZ(DQ) tDS(base) tDH(base) tDIPW
Data Strobe Timing
DQS, DQS READ Preamble
DQS, DQS differential READ Postamble
DQS, DQS output high time tRPRE tRPST tQSH tQSL DQS, DQS output low time
DQS, DQS WRITE Preamble
DQS, DQS WRITE Postamble
DQS, DQS rising edge output access time from rising
CK, CK tWPRE tWPST tDQSCK
DQS, DQS low-impedance time (Referenced from RL-1) tLZ(DQS)
DQS, DQS high-impedance time (Referenced from
RL+BL/2) tHZ(DQS)
DQS, DQS differential input low pulse width
DQS, DQS differential input high pulse width
DQS, DQS rising edge to CK, CK rising edge
DQS,DQS falling edge setup time to CK, CK rising edge
DQS,DQS falling edge hold time to CK, CK rising edge tDQSL tDQSH tDQSS tDSS tDSH
0.43
0.43
-400
-800
-
0.45
0.45
-0.25
0.2
0.2
0.9
0.3
0.38
0.38
0.9
0.3
-
0.38
-800
-
75
150
600
200
-
400
400
-
-
-
-
-
400
400
400
0.55
0.55
0.25
-
-
NOTE 19
NOTE 11
-
-
-
-
DDR3-1066
MIN MAX
100
490
-300
-600
-
0.45
0.45
-0.25
0.2
0.2
0.9
0.3
0.38
0.38
0.9
0.3
-
0.38
-600
-
25
8 8 -
0.47
0.47
-90
-80
180
160
See Speed Bins Table tCK(avg)min + tJIT(per)min tCK(avg)max + tJIT(per)max
0.53
0.47
0.53
90
80
0.47
-80
-70
160
140
0.53
0.53
80
70
- 132
- 157
- 175
- 188
- 200
- 209
- 217
- 224
132
157
175
188
200
209
217
224
- 118
- 140
- 155
- 168
- 177
- 186
- 193
- 200
- 231
- 237
231
237
- 205
- 210
205
210
- 242 242 - 215 215 tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max
0.43
0.43
-
-
0.43
0.43
-
-
177
186
193
200
118
140
155
168
150
-
300
300
-
-
-
300
300
300
0.55
0.55
0.25
-
-
NOTE 19
NOTE 11
-
-
-
-
DDR3-1333
MIN MAX
65
400
-255
-500
-
0.45
0.45
-0.25
0.2
0.2
0.9
0.3
0.4
0.4
0.9
0.3
-
0.38
-500
-
30
125
-
250
250
-
-
-
255
250
250
0.55
0.55
0.25
-
-
NOTE 19
NOTE 11
-
-
-
-
DDR3-1600
MIN MAX
-
0.38
-450
-
10
45
360
8
-155
-163
-169
-175
-103
-122
-136
-147
-180
-184
-188
0.47
0.47
-70
-60
140
120
0.53
0.53
70
60
155
163
169
175
103
122
136
147
180
184
188
0.43
0.43
-
-
ns ps ps ps ps ps ps ps ps ps ps ps tCK(avg) tCK(avg) ps ps ps ps ps ps ps tCK(avg) tCK(avg)
100
-
225
225
Units NOTE
6
24
25
26 ps tCK(avg) ps ps ps
13
13, g
13,14, f
13,14, f d, 17 ps ps d, 17
28
-225
-450
-
0.45
0.45
-0.27
0.18
0.18
0.9
0.3
0.4
0.4
0.9
0.3
225
225
225
0.55
0.55
0.27
-
-
NOTE 19
NOTE 11
-
-
-
tCK tCK tCK(avg) tCK(avg) tCK tCK ps ps ps tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg)
13, 19, g
11, 13, b
13, g
13, g
13,f
13,14,f
13,14,f
29, 31
30, 31 c c, 32 c, 32
- 31 -
Unbuffered DIMM
Rev. 1.2
DDR3 SDRAM
[ Table 18 ] Timing Parameters by Speed Bin (Cont.)
Speed
Parameter
Command and Address Timing
DLL locking time internal READ Command to PRECHARGE Command delay
Delay from start of internal write transaction to internal read command
WRITE recovery time
Mode Register Set command cycle time
Mode Register Set command update delay
CAS# to CAS# command delay
Auto precharge write recovery + precharge time
Multi-Purpose Register Recovery Time
ACTIVE to PRECHARGE command period
ACTIVE to ACTIVE command period for 1KB page size
ACTIVE to ACTIVE command period for 2KB page size
Symbol
DDR3-800
MIN MAX
DDR3-1066
MIN MAX
DDR3-1333
MIN MAX
DDR3-1600
MIN tDLLK tRTP tWTR tWR tMRD tMOD
512 max
(4nCK,7.5ns
) max
(4nCK,7.5ns
)
15
4 max
(12nCK,15n s)
4
-
-
-
-
-
-
512 max
(4nCK,7.5ns
)
-
-
512 max
(4nCK,7.5ns
) max
(4nCK,7.5ns
)
15
4
-
-
max
(4nCK,7.5ns
)
15
4 max
(12nCK,15n s)
4
max
(12nCK,15n s)
4
WR + roundup (tRP / tCK(AVG))
-
-
-
-
-
-
512 max
(4nCK,7.5ns) max
(4nCK,7.5ns)
15
4 max
(12nCK,15ns
)
4 tCCD tDAL(min) tMPRR tRAS tRRD
-
1 max
(4nCK,10ns)
1 1 1
See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin” on page 40
max
(4nCK,7.5ns
)
max
(4nCK,6ns)
max
(4nCK,6ns) tRRD tFAW tFAW max
(4nCK,10ns)
40
50
-
-
max
(4nCK,10ns)
37.5
50
-
-
max
(4nCK,7.5ns
)
30
45
-
-
max
(4nCK,7.5ns)
30
40
MAX
-
-
-
-
-
-
-
-
-
-
-
-
Four activate window for 1KB page size
Four activate window for 2KB page size
Command and Address setup time to CK, CK referenced to V
IH
(AC) / V
IL
(AC) levels
Command and Address hold time from CK, CK referenced to V
IH
(AC) / V
IL
(AC) levels
Command and Address setup time to CK, CK referenced to V
IH
(AC) / V
IL
(AC) levels
Control & Address Input pulse width for each input
Calibration Timing
Power-up and RESET calibration time
Normal operation Full calibration time
Normal operation short calibration time
Reset Timing tIS(base) tIH(base) tIS(base)
AC150 tIPW tZQinitI tZQoper tZQCS
200
275
200 + 150
900
512
256
64
-
-
-
-
-
-
-
125
200
125 + 150
780
512
256
64
-
-
-
-
-
-
-
65
140
65+125
620
512
256
64
-
-
-
-
-
-
-
45
120
45+125
560
512
256
64
-
-
-
-
-
-
-
Exit Reset from CKE HIGH to a valid command tXPR max(5nCK, tRFC +
10ns)
max(5nCK, tRFC +
10ns)
max(5nCK, tRFC +
10ns)
max(5nCK, tRFC + 10ns)
-
Self Refresh Timing
Exit Self Refresh to commands not requiring a locked
DLL tXS
Exit Self Refresh to commands requiring a locked DLL tXSDLL
Minimum CKE low width for Self refresh entry to exit timing
Valid Clock Requirement after Self Refresh Entry
(SRE) or Power-Down Entry (PDE)
Valid Clock Requirement before Self Refresh Exit
(SRX) or Power-Down Exit (PDX) or Reset Exit tCKESR tCKSRE tCKSRX max(5nCK,t
RFC + 10ns) tDLLK(min) tCKE(min) +
1tCK max(5nCK,
10ns) max(5nCK,
10ns)
-
-
-
-
max(5nCK,t
RFC + 10ns) tDLLK(min) tCKE(min) +
1tCK max(5nCK,
10ns) max(5nCK,
10ns)
-
-
-
-
max(5nCK,t
RFC + 10ns) tDLLK(min) tCKE(min) +
1tCK max(5nCK,
10ns) max(5nCK,
10ns)
-
-
-
-
max(5nCK,tR
FC + 10ns) tDLLK(min) tCKE(min) +
1tCK max(5nCK,
10ns) max(5nCK,
10ns)
-
-
-
-
-
Units NOTE nCK ns nCK e,18 e,18 nCK nCK nCK ns nCK e
22 e e ps ps ps ns ns ps e e e b,16 b,16 b,16,27
28 nCK nCK nCK 23
- 32 -
Unbuffered DIMM
Rev. 1.2
DDR3 SDRAM
[ Table 18 ] Timing Parameters by Speed Bin (Cont.)
Power Down Timing
Exit Power Down with DLL on to any valid command;Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL
Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL
CKE minimum pulse width
Command pass disable delay
Power Down Entry to Exit Timing
Timing of ACT command to Power Down entry
Timing of PRE command to Power Down entry
Timing of RD/RDA command to Power Down entry
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BL4OTF)
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BL4OTF)
Timing of WR command to Power Down entry
(BL4MRS)
Speed
Parameter
Timing of WRA command to Power Down entry
(BL4MRS)
Timing of REF command to Power Down entry
Timing of MRS command to Power Down entry
ODT Timing
ODT high time without write command or with write command and BC4
ODT high time with Write command and BL8
Asynchronous RTT turn-on delay (Power-Down with
DLL frozen)
Asynchronous RTT turn-off delay (Power-Down with
DLL frozen)
ODT turn-on
RTT_NOM and RTT_WR turn-off time from ODTLoff reference
RTT dynamic change skew
Write Leveling Timing
First DQS pulse rising edge after tDQSS margining mode is programmed
DQS/DQS delay after tDQS margining mode is programmed
Setup time for tDQSS latch
Write leveling hold time from rising DQS, DQS crossing to rising CK, CK crossing
Write leveling output delay
Write leveling output error
Symbol
ODTH4
ODTH8 tAONPD tAOFPD tAON tAOF tADC tWLMRD tWLDQSEN tWLS tWLH tWLO tWLOE
MIN
4
6
2
2
0.3
0.3
40
25
325
325
0
0
DDR3-800 tXP tXPDLL tCKE max
(3nCK,
7.5ns) max
(10nCK,
24ns) max
(3nCK,
7.5ns)
1 tCKE(min) tCPDED tPD tACTPDEN tPRPDEN tRDPDEN tWRPDEN tWRAPDEN
1
1
RL + 4 +1
WL + 4
+(tWR/ tCK(avg))
WL + 4
+WR +1 tWRPDEN
WL + 2
+(tWR/ tCK(avg)) tWRAPDEN
WL +2 +WR
+1 tREFPDEN 1 tMRSPDEN tMOD(min)
-400
MAX
-
-
-
-
9*tREFI
-
-
-
-
-
-
-
-
-
-
-
8.5
8.5
400
0.7
0.7
-
-
-
-
9
2
DDR3-1066
MIN MAX max
(3nCK,
7.5ns) max
(10nCK,
24ns) max
(3nCK,
5.625ns)
1 tCKE(min)
1
1
RL + 4 +1
WL + 4
+(tWR/ tCK(avg))
WL + 4
+WR +1
WL + 2
+(tWR/ tCK(avg))
WL +2 +WR
+1
1 tMOD(min)
4
6
2
2
-300
0.3
0.3
40
25
245
245
0
0
-
-
-
-
9*tREFI
-
-
-
-
-
-
-
9
2
-
-
-
-
8.5
8.5
300
0.7
0.7
-
-
-
-
DDR3-1333
MIN MAX max
(3nCK,6ns)
max
(3nCK,6ns)
max
(10nCK,
24ns) max
(3nCK,
5.625ns)
1 tCKE(min)
1
1
RL + 4 +1
WL + 4
+(tWR/ tCK(avg))
WL + 4
+WR +1
WL + 2
+(tWR/ tCK(avg))
WL +2 +WR
+1
1 tMOD(min)
-
max
(10nCK,
24ns) max
(3nCK,5ns)
-
9*tREFI
-
-
-
-
-
-
-
-
-
1 tCKE(min)
1
1
RL + 4 +1
WL + 4
+(tWR/ tCK(avg))
WL + 4 +WR
+1
WL + 2
+(tWR/ tCK(avg))
WL +2 +WR
+1
1 tMOD(min)
-
-
-
9*tREFI
-
-
-
-
-
-
-
-
-
4
6
2
2
-250
0.3
0.3
40
25
195
195
0
0
8.5
8.5
250
-
-
9
2
-
-
-
-
0.7
0.7
DDR3-1600
MIN MAX
4
6
2
2
-225
0.3
0.3
40
25
165
165
0
0
8.5
225
0.7
0.7
-
-
8.5
-
-
7.5
2
-
-
Units nCK tCK nCK nCK nCK nCK nCK nCK ns ps tCK(avg) tCK(avg) tCK tCK ps ps ns ns nCK nCK ns
NOTE
2
7,f
8,f f
15
20
20
9
10
9
10
20,21
3
3
- 33 -
Unbuffered DIMM
Rev. 1.2
DDR3 SDRAM
18.1 Jitter Notes
Specific Note a Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm, another Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min.
Specific Note b
Specific Note c
Specific Note d
Specific Note e
Specific Note f
Specific Note g
These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not.
These parameters are measured from a data strobe signal (DQS, DQS) crossing to its respective clock signal (CK, CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not.
These parameters are measured from a data signal (DM, DQ0, DQ1, etc.) transition edge to its respective data strobe signal
(DQS, DQS) crossing.
For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [ns] / tCK(avg) [ns] }, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the device will support tnRP = RU{tRP / tCK(avg)} = 6, as long as the input clock jitter specifications are met, i.e. Precharge command at Tm and Active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to input clock jitter.
When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input clock, where 2 <= m <= 12. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = - 172 ps and tERR(mper),act,max = +
193 ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 400 ps - 193 ps = - 593 ps and tDQSCK,max(derated) = tDQSCK,max - tERR(mper),act,min = 400 ps + 172 ps = + 572 ps. Similarly, tLZ(DQ) for DDR3-800 derates to tLZ(DQ),min(derated) = - 800 ps - 193 ps = - 993 ps and tLZ(DQ),max(derated) = 400 ps + 172 ps = + 572 ps. (Caution on the min/max usage!)
Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <=
12, and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12.
When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tCK(avg),act = 2500 ps, tJIT(per),act,min = - 72 ps and tJIT(per),act,max = + 93 ps, then tRPRE,min(derated) = tRPRE,min + tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. Similarly, tQH,min(derated) = tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (Caution on the min/ max usage!)
- 34 -
Unbuffered DIMM
Rev. 1.2
DDR3 SDRAM
18.2 Timing Parameter Notes
1. Actual value dependant upon measurement level definitions which are TBD.
2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.
3. The max values are system dependent.
4. WR as programmed in mode register
5. Value must be rounded-up to next higher integer value
6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.
7. For definition of RTT turn-on time tAON see "Device Operation & Timing Diagram Datasheet"
8. For definition of RTT turn-off time tAOF see "Device Operation & Timing Diagram Datasheet".
9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.
10. WR in clock cycles as programmed in MR0
11. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. See "Device Operation & Timing
Diagram Datasheet.
12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated
by TBD
13. Value is only valid for RON34
14. Single ended signal parameter. Refer to chapter 8 and chapter 9 for definition and measurement method.
15. tREFI depends on T
OPER
16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals,
V
REF
(DC) = V
REF
DQ(DC). FOr input only pins except RESET, V
REF
(DC)=V
REF
CA(DC).
See "Address/Command Setup, Hold and Derating" on component datasheet.
17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals,
V
REF
(DC)= V
REF
DQ(DC). For input only pins except RESET, V
REF
(DC)=V
REF
CA(DC).
See "Data Setup, Hold and Slew Rate Derating" on component datasheet.
18. Start of internal write transaction is defined as follows ;
For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL.
For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL
For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL
19. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. See "Device Operation & Timing Diagram
Datasheet"
20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down
IDD spec will not be applied until finishing those operations.
21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time
such as tXPDLL(min) is also required. See "Device Operation & Timing Diagram Datasheet".
22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming the maximum sensitivities specified in the ’Output Driver Voltage and Temperature Sensitivity’ and ’ODT Voltage and Temperature Sensitivity’ tables. The appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters.
One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. The interval could be defined by the following formula:
ZQCorrection
(TSens x Tdriftrate) + (VSens x Vdriftrate) where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities.
For example, if TSens = 1.5% /
°C, VSens = 0.15% / mV, Tdriftrate = 1°C / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calculated as:
0.5
(1.5 x 1) + (0.15 x 15)
24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.
25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge.
26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.
27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100 ps of derating to accommodate for the lower alternate threshold of 150 mV and another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns].
28. Pulse width of a input signal is defined as the width between the first crossing of V
REF
(DC) and the consecutive crossing of V
REF
(DC)
29. tDQSL describes the instantaneous differential input low pulse width on DQS-DQS, as measured from one falling edge to the next consecutive rising edge.
30. tDQSH describes the instantaneous differential input high pulse width on DQS-DQS, as measured from one rising edge to the next consecutive falling edge.
31. tDQSH, act + tDQSL, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.
32. tDSH, act + tDSS, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.
- 35 -
Unbuffered DIMM
19. Physical Dimensions
19.1 256Mbx8 based 256Mx64/x72 Module (1 Rank) - M378/91B5773CH0
133.35 ± 0.15
128.95
(2)
2.50
54.675
47.00
A B
N/A
(for x64)
ECC
(for x72)
SPD
71.00
Rev. 1.2
DDR3 SDRAM
Units : Millimeters
Max 4.0
5.00
1.50±0.10
2.50
Detail A
3.80
The used device is 256M x8 DDR3 SDRAM, FBGA.
DDR3 SDRAM Part NO : K4B2G0846C-HC
∗∗
* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.
- 36 -
1.00
Detail B
0.80 ± 0.05
0.2 ± 0.15
1.270 ± 0.10
2x 2.10 ± 0.15
Unbuffered DIMM
Rev. 1.2
DDR3 SDRAM
19.2 256Mbx8 based 512Mx64/x72 Module (2 Ranks) - M378/91B5273CH0
133.35 ± 0.15
128.95
(2)
2.50
54.675
47.00
A B
N/A
(for x64)
ECC
(for x72)
SPD
71.00
N/A
(for x64)
ECC
(for x72)
Units : Millimeters
Max 4.0
1.270 ± 0.10
5.00
3.80
1.50±0.10
2.50
Detail A
The used device is 256M x8 DDR3 SDRAM, FBGA.
DDR3 SDRAM Part NO : K4B2G0846C-HC
∗∗
* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.
1.00
Detail B
0.80 ± 0.05
0.2 ± 0.15
- 37 -
2x 2.10 ± 0.15
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