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Unbuffered DIMM
Rev. 1.2
DDR3 SDRAM
6. Pin Description
Pin Name
A0-A14
BA0-BA2
Description
SDRAM address bus
SDRAM bank select
RAS
CAS
WE
SDRAM row address strobe
SDRAM column address strobe
SDRAM write enable
S0, S1
CKE0,CKE1
DIMM Rank Select Lines
SDRAM clock enable lines
ODT0, ODT1 On-die termination control lines
DQ0 - DQ63
CB0 - CB7
DQS0 - DQS8
DQS0-DQS8
DM0-DM8
CK0, CK1
CK0, CK1
DIMM memory data bus
DIMM ECC check bits
SDRAM data strobes
(positive line of differential pair)
SDRAM differential data strobes
(negative line of differential pair)
SDRAM data masks/high data strobes
(x8-based x72 DIMMs)
SDRAM clocks
(positive line of differential pair)
SDRAM clocks
(negative line of differential pair)
NOTE :
* The V
DD
and V
DDQ pins are tied common to a single power-plane on these designs.
** DM8, DQS8 and DQS8 are for ECC UDIMM only.
Pin Name
SCL
SDA
SA0-SA2
V
DD
*
V
DDQ
*
V
REFDQ
V
REFCA
V
SS
V
DDSPD
NC
TEST
RESET
EVENT
V
TT
RFU
Description
I
2
C serial bus clock for EEPROM
I
2
C serial bus data line for EEPROM
I
2
C serial address select for EEPROM
SDRAM core power supply
SDRAM I/O Driver power supply
SDRAM I/O reference supply
SDRAM command/address reference supply
Power supply return (ground)
Serial EEPROM positive power supply
Spare Pins(no connect)
Used by memory bus analysis tools
(unused on memory DIMMs)
Set DRAMs Known State
Reserved for optional temperature-sensing hardware
SDRAM I/O termination supply
Reserved for future use
7. SPD and Thermal Sensor for ECC UDIMMs
On DIMM thermal sensor will provide DRAM temperature readout through a integrated thermal sensor.
EVENT
SCL
R1
0
Ω
R2
0
Ω
WP/EVENT
SA0 SA1
SA0 SA1
SA2
SA2
SDA
NOTE :
1. Raw Cards D (1Rx8 ECC) and E (2Rx8 ECC) support a thermal sensor.
2. When the SPD and the thermal sensor are placed on the module, R1 is placed but R2 is not.
When only the SPD is placed on the module, R2 is placed but R1 is not.
[ Table 1 ] Temperature Sensor Characteristics
Grade
B
Range
75 < Ta < 95
40 < Ta < 125
-20 < Ta < 125
Resolution
Min.
-
-
-
Temperature Sensor Accuracy
Typ. Max.
+/- 0.5
+/- 1.0
+/- 2.0
0.25
+/- 1.0
+/- 2.0
+/- 3.0
Units
°C
°C /LSB
NOTE
-
-
-
-
- 7 -
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Table of contents
- 4 1. DDR3 Unbuffered DIMM Ordering Information
- 4 2. Key Features
- 4 3. Address Configuration
- 5 4. x64 DIMM Pin Configurations (Front side/Back side)
- 6 5. x72 DIMM Pin Configurations (Front side/Back side)
- 7 6. Pin Description
- 7 7. SPD and Thermal Sensor for ECC UDIMMs
- 8 8. Input/Output Functional Description
- 9 8.1 Address Mirroring Feature
- 9 8.1.1. DRAM Pin Wiring Mirroring
- 10 9. Function Block Diagram
- 10 9.1 2GB, 256Mx64 Non ECC Module (Populated as 1 rank of x8 DDR3 SDRAMs)
- 11 9.2 2GB, 256Mx72 ECC Module (Populated as 1 rank of x8 DDR3 SDRAMs)
- 12 9.3 4GB, 512Mx64 Non ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs)
- 13 9.4 4GB, 512Mx72 ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs)
- 14 10. Absolute Maximum Ratings
- 14 10.1 Absolute Maximum DC Ratings
- 14 10.2 DRAM Component Operating Temperature Range
- 14 11. AC & DC Operating Conditions
- 14 11.1 Recommended DC Operating Conditions (SSTL-15)
- 15 12. AC & DC Input Measurement Levels
- 15 12.1 AC & DC Logic Input Levels for Single-ended Signals
- 16 Tolerances
- 17 12.3 AC and DC Logic Input Levels for Differential Signals
- 17 12.3.1. Differential Signals Definition
- 17 12.3.2. Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS)
- 18 12.3.3. Single-ended Requirements for Differential Signals
- 19 12.3.4. Differential Input Cross Point Voltage
- 19 12.4 Slew Rate Definition for Single Ended Input Signals
- 19 12.5 Slew rate definition for Differential Input Signals
- 20 13. AC & DC Output Measurement Levels
- 20 13.1 Single Ended AC and DC Output Levels
- 20 13.2 Differential AC and DC Output Levels
- 20 13.3 Single-ended Output Slew Rate
- 21 13.4 Differential Output Slew Rate
- 22 14. DIMM IDD specification definition
- 24 15. IDD SPEC Table
- 26 16. Input/Output Capacitance
- 26 16.1 Non ECC UDIMM
- 26 16.2 ECC UDIMM
- 27 17. Electrical Characteristics and AC timing
- 27 17.1 Refresh Parameters by Device Density
- 27 17.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
- 27 17.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin
- 30 17.3.1. Speed Bin Table Notes
- 31 18. Timing Parameters by Speed Grade
- 34 18.1 Jitter Notes
- 35 18.2 Timing Parameter Notes
- 36 19. Physical Dimensions
- 36 19.1 256Mbx8 based 256Mx64/x72 Module (1 Rank) - M378/91B5773CH
- 37 19.2 256Mbx8 based 512Mx64/x72 Module (2 Ranks) - M378/91B5273CH