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Unbuffered DIMM
Rev. 1.2
DDR3 SDRAM
13.4 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V
OLdiff
(AC) and V
OHdiff
(AC) for differential signals as shown in below.
[ Table 12 ] Differential Output slew rate definition
Description
Differential output slew rate for rising edge
From
Measured
To
V
OLdiff
(AC) V
OHdiff
(AC)
Differential output slew rate for falling edge V
OHdiff
(AC) V
OLdiff
(AC)
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
Defined by
V
OHdiff
(AC)-V
OLdiff
(AC)
Delta TRdiff
V
OHdiff
(AC)-V
OLdiff
(AC)
Delta TFdiff
[ Table 13 ] Differential Output slew rate
Parameter Symbol
DDR3-800
Min Max
5 10 Differential output slew rate SRQdiff
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output) diff : Differential Signals
For Ron = RZQ/7 setting
DDR3-1066
Min Max
5 10
DDR3-1333
Min Max
5 10
DDR3-1600
Min Max
5 10
Units
V/ns
V
OHdiff
(AC)
V
TT
V
OLdiff
(AC) delta TFdiff delta TRdiff
Figure 8. Differential output slew rate definition
- 21 -
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Table of contents
- 4 1. DDR3 Unbuffered DIMM Ordering Information
- 4 2. Key Features
- 4 3. Address Configuration
- 5 4. x64 DIMM Pin Configurations (Front side/Back side)
- 6 5. x72 DIMM Pin Configurations (Front side/Back side)
- 7 6. Pin Description
- 7 7. SPD and Thermal Sensor for ECC UDIMMs
- 8 8. Input/Output Functional Description
- 9 8.1 Address Mirroring Feature
- 9 8.1.1. DRAM Pin Wiring Mirroring
- 10 9. Function Block Diagram
- 10 9.1 2GB, 256Mx64 Non ECC Module (Populated as 1 rank of x8 DDR3 SDRAMs)
- 11 9.2 2GB, 256Mx72 ECC Module (Populated as 1 rank of x8 DDR3 SDRAMs)
- 12 9.3 4GB, 512Mx64 Non ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs)
- 13 9.4 4GB, 512Mx72 ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs)
- 14 10. Absolute Maximum Ratings
- 14 10.1 Absolute Maximum DC Ratings
- 14 10.2 DRAM Component Operating Temperature Range
- 14 11. AC & DC Operating Conditions
- 14 11.1 Recommended DC Operating Conditions (SSTL-15)
- 15 12. AC & DC Input Measurement Levels
- 15 12.1 AC & DC Logic Input Levels for Single-ended Signals
- 16 Tolerances
- 17 12.3 AC and DC Logic Input Levels for Differential Signals
- 17 12.3.1. Differential Signals Definition
- 17 12.3.2. Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS)
- 18 12.3.3. Single-ended Requirements for Differential Signals
- 19 12.3.4. Differential Input Cross Point Voltage
- 19 12.4 Slew Rate Definition for Single Ended Input Signals
- 19 12.5 Slew rate definition for Differential Input Signals
- 20 13. AC & DC Output Measurement Levels
- 20 13.1 Single Ended AC and DC Output Levels
- 20 13.2 Differential AC and DC Output Levels
- 20 13.3 Single-ended Output Slew Rate
- 21 13.4 Differential Output Slew Rate
- 22 14. DIMM IDD specification definition
- 24 15. IDD SPEC Table
- 26 16. Input/Output Capacitance
- 26 16.1 Non ECC UDIMM
- 26 16.2 ECC UDIMM
- 27 17. Electrical Characteristics and AC timing
- 27 17.1 Refresh Parameters by Device Density
- 27 17.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
- 27 17.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin
- 30 17.3.1. Speed Bin Table Notes
- 31 18. Timing Parameters by Speed Grade
- 34 18.1 Jitter Notes
- 35 18.2 Timing Parameter Notes
- 36 19. Physical Dimensions
- 36 19.1 256Mbx8 based 256Mx64/x72 Module (1 Rank) - M378/91B5773CH
- 37 19.2 256Mbx8 based 512Mx64/x72 Module (2 Ranks) - M378/91B5273CH