M48T35

M48T35Y, M48T35Y

256 Kbit (32Kb x 8) TIMEKEEPER

®

SRAM

INTEGRATED ULTRA LOW POWER SRAM,

REAL TIME CLOCK, POWER-FAIL CONTROL

CIRCUIT and BATTERY

BYTEWIDE



RAM-LIKE CLOCK ACCESS

BCD CODED YEAR, MONTH, DAY, DATE,

HOURS, MINUTES and SECONDS

FREQUENCY TEST OUTPUT for REAL TIME

CLOCK

AUTOMATIC POWER-FAIL CHIP DESELECT and

WRITE PROTECTION

WRITE PROTECT VOLTAGES

(V

PFD

= Power-fail Deselect Voltage):

– M48T35: 4.5V

≤

V

PFD

≤

4.75V

– M48T35Y: 4.2V

≤

V

PFD

≤

4.5V

– M48T35V: 2.7V

≤

V

PFD

≤

3.0V

SELF-CONTAINED BATTERY and CRYSTAL in the CAPHAT DIP PACKAGE

PACKAGING INCLUDES a 28-LEAD SOIC and SNAPHAT

®

TOP

(to be Ordered Separately)

SOIC PACKAGE PROVIDES DIRECT

CONNECTION for a SNAPHAT TOP

CONTAINS the BATTERY and CRYSTAL

PIN and FUNCTION COMPATIBLE with

JEDEC STANDARD 32K x 8 SRAMs

DESCRIPTION

The M48T35/35Y/35V TIMEKEEPER

®

RAM is a

32 Kbit x 8 non-volatile static RAM and real time clock. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory and real time clock solution.

Table 1. Signal Names

A0-A14

DQ0-DQ7

E

G

W

V

CC

V

SS

Address Inputs

Data Inputs / Outputs

Chip Enable

Output Enable

Write Enable

Supply Voltage

Ground

July 1998

SNAPHAT (SH)

Battery/Crystal

28

1

SOH28 (MH)

28

Figure 1. Logic Diagram

A0-A14

15

W

E

G

VCC

M48T35

M48T35Y

M48T35V

VSS

1

PCDIP28 (PC)

Battery/Crystal

CAPHAT

8

DQ0-DQ7

AI01620C

1/17

M48T35, M48T35Y, M48T35V

Figure 2A. DIP Pin Connections

DQ0

DQ1

DQ2

VSS

A4

A3

A2

A1

A0

A14

A12

A7

A6

A5

11

12

13

14

6

7

8

9

10

3

4

1

2

5

M48T35

M48T35Y

18

17

16

15

22

21

20

19

28

27

26

25

24

23

AI01621B

G

A10

E

DQ7

DQ6

DQ5

DQ4

DQ3

VCC

W

A13

A8

A9

A11

Figure 2B. SOIC Pin Connections

A14

A12

A7

A6

DQ0

DQ1

DQ2

VSS

A5

A4

A3

A2

A1

A0

9

10

11

12

13

14

6

7

8

4

5

1

2

3

M48T35Y

M48T35V

24

23

22

21

20

19

18

17

16

15

28

27

26

25

AI01622C

E

DQ7

DQ6

DQ5

DQ4

DQ3

VCC

W

A13

A8

A9

A11

G

A10

Table 2. Absolute Maximum Ratings

(1)

Symbol

T

A

T

STG

T

SLD

(2)

V

IO

V

CC

I

O

P

D

Parameter

Ambient Operating Temperature

Storage Temperature (V

CC

Input or Output Voltages

Supply Voltage

Output Current

Power Dissipation

Off, Oscillator Off)

Lead Solder Temperature for 10 seconds

Value

0 to 70

–40 to 85

260

–0.3 to 7

–0.3 to 7

20

1

Unit

°

C

°

C

°

C

V

V mA

W

Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability.

2. Soldering temperature not to exceed 260

°

C for 10 seconds (total thermal budget not to exceed 150

°

C for longer than 30 seconds).

CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.

CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.

DESCRIPTION (cont’d)

The M48T35/35Y/35V is a non-volatile pin and function equivalent to any JEDEC standard 32K x8

SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special write timing or limitations on the number of writes that can be performed.

The 28 pin 600mil DIP CAPHAT



houses the

M48T35/35Y/35V silicon with a quartz crystal and a long life lithium button cell in a single package.

The 28 pin 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the

SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion.

2/17

M48T35, M48T35Y, M48T35V

Table 3. Operating Modes

(1)

Mode

Deselect

Write

Read

V

CC

4.75V to 5.5V

or

4.5V to 5.5V

or

3.0V to 3.6V

E

V

IH

V

V

IL

IL

G

X

X

V

IL

Read V

IL

V

IH

Deselect

Deselect

V

SO

to V

PFD

(min)

(2)

≤

V

SO

X

X

Notes: 1. X = V

IH

or V

IL

; V

SO

= Battery Back-up Switchover Voltage.

2. See Table 7 for details.

X

X

Figure 3. Block Diagram

V

IH

X

X

W

X

V

IL

V

IH

DQ0-DQ7

High Z

D

IN

D

OUT

High Z

High Z

High Z

Power

Standby

Active

Active

Active

CMOS Standby

Battery Back-up Mode

32,768 Hz

CRYSTAL

OSCILLATOR AND

CLOCK CHAIN

POWER

LITHIUM

CELL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

VPFD

8 x 8 BiPORT

SRAM ARRAY

32,760 x 8

SRAM ARRAY

A0-A14

DQ0-DQ7

E

W

G

VCC VSS

AI01623

The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in

Tape & Reel form.

For the 28 lead SOIC, the battery/crystal package

( i.e. SNA PHAT ) p art num ber is "M 4T28-

BR12SH1".

As Figure 3 shows, the static memory array and the q ua r t z c o nt r ol led c loc k o sc i lla t or of t h e

M48T35/35Y/35V are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDE



clock information in the bytes with addresses 7FF8h-7FFFh.

The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year), 30, and

31 day months are made automatically. Byte

7FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting.

3/17

M48T35, M48T35Y, M48T35V

Table 4. AC Measurement Conditions

Input Rise and Fall Times

Input Pulse Voltages

≤

5ns

0 to 3V

Input and Output Timing Ref. Voltages 1.5V

Note that Output Hi-Z is defined as the point where data is no longer driven.

Figure 4. AC Testing Load Circuit

DEVICE

UNDER

TEST

645

Ω

CL = 100pF

(or 5pF)

1.75V

CL includes JIG capacitance

AI02586

DESCRIPTION (cont’d)

The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORT



read/write memory cells.

The M48T35/35Y/35V includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array.

The M48T35/35Y/35V also has its own Power-fail

Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When V

CC

is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low V

CC

. As V

CC

falls below approximately 3V, the control circuitry connects the battery which maintains data and clock operation until valid power returns.

READ MODE

The M48T35/35Y/35V is in the Read Mode whenever W (Write Enable) is high and E (Chip Enable) is low. The unique address specified by the 15

Address Inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (t

AVQV

) after the last address input signal is stable, providing that the E and G access times are also satisfied.

If the E and G access times are not met, valid data will be available after the latter of the Chip Enable

Access time (t

ELQV

) or Output Enable Access time

(t

GLQV

).

The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before t

AVQV

, the data lines will be driven to an indeterminate state until t

AVQV

. If the Address Inputs are changed while E and G remain active, output data will remain valid for Output Data Hold time (t

AXQX

) but will go indeterminate until the next

Address Access.

WRITE MODE

The M48T35/35Y/35V is in the Write Mode whenever W and E are low. The start of a write is referenced from the latter occurring falling edge of

W or E. A write is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of t

EHAX

from Chip Enable or t

WHAX

from

Write Enable prior to the initiation of another read or write cycle. Data-in must be valid t

DVWH

prior to the end of write and remain valid for t

WHDX

afterward. G should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on

W will disable the outputs t

WLQZ

after W falls.

4/17

M48T35, M48T35Y, M48T35V

Table 5. Capacitance

(1, 2)

(T

A

= 25

°

C, f = 1 MHz )

Symbol Parameter Test Condition

C

IN

C

IO

(3)

Input Capacitance

Input / Output Capacitance

Notes: 1. Effective capacitance measured with power supply at 5V.

2. Sampled only, not 100% tested.

3. Outputs deselected

V

IN

= 0V

V

OUT

= 0V

Table 6A. DC Characteristics

(T

A

= 0 to 70

°

C; V

CC

= 4.75V to 5.5V or 4.5V to 5.5V)

Symbol

I

LI

(1)

I

LO

(1)

I

CC

I

CC1

I

CC2

V

IL

(2)

V

IH

Parameter

Input Leakage Current

Output Leakage Current

Supply Current

Supply Current (Standby) TTL

Supply Current (Standby) CMOS

Input Low Voltage

Input High Voltage

Test Condition

0V

≤

V

IN

≤

V

CC

0V

≤

V

OUT

≤

V

CC

Outputs open

E = V

E = V

CC

IH

– 0.2V

V

OL

Output Low Voltage I

OL

= 2.1mA

V

OH

Output High Voltage I

OH

= –1mA

Notes: 1. Outputs Deselected.

2. Negative spikes of –1V allowed for up to 10ns once per Cycle.

Min Max

10

10

Unit

pF pF

Min

–0.3

2.2

2.4

Max

±

1

±

5

50

3

3

0.8

V

CC

+ 0.3

0.4

Unit

µ

A

µ

A mA mA mA

V

V

V

V

Table 6B. DC Characteristics

(T

A

= 0 to 70

°

C; V

CC

= 3.0V to 3.6V)

Symbol

I

LI

(1)

I

LO

(1)

Parameter

Input Leakage Current

Output Leakage Current

Test Condition

0V

≤

V

IN

≤

V

CC

0V

≤

V

OUT

≤

V

CC

I

CC

I

CC1

I

CC2

V

IL

(2)

V

IH

V

OL

Supply Current

Supply Current (Standby) TTL

Supply Current (Standby) CMOS

Input Low Voltage

Input High Voltage

Output Low Voltage

Outputs open

E = V

E = V

CC

IH

– 0.2V

I

OL

= 2.1mA

V

OH

Output High Voltage I

OH

= –1mA

Notes: 1. Outputs Deselected.

2. Negative spikes of –1V allowed for up to 10ns once per Cycle.

Min

–0.3

2.2

2.4

Max

±

1

±

5

30

2

2

0.8

V

CC

+ 0.3

0.4

Unit

µ

A

µ

A mA mA mA

V

V

V

V

5/17

M48T35, M48T35Y, M48T35V

Table 7. Power Down/Up Trip Points DC Characteristics

(1)

(T

A

= 0 to 70

°

C)

Symbol Parameter Min

V

PFD

V

PFD

V

PFD

V

SO

Power-fail Deselect Voltage (M48T35)

Power-fail Deselect Voltage (M48T35Y)

Power-fail Deselect Voltage (M48T35V)

Battery Back-up Switchover Voltage (M48T35/35Y)

4.5

4.2

2.7

V

SO

Battery Back-up Switchover Voltage (M48T35V) t

DR

(2, 3)

Expected Data Retention Time

Notes: 1. All voltages referenced to V

SS

.

2. At 25°C.

3. CAPHAT only, SNAPHAT t

DR

= 7yrs (typ).

10

Typ

4.6

4.35

2.9

3.0

VPFD –

100mV

Max

4.75

4.5

3.0

Table 8. Power Down/Up Mode AC Characteristics

(T

A

= 0 to 70

°

C)

Symbol Parameter

t t t

PD

F

(1)

FB

(2) t t

R

RB

E or W at V

V

V

V

V

PFD

PFD

PFD

SO

(max) to V

(min) to V

(min) to V

to V

PFD

IH

before Power Down

PFD

SO

PFD

V

(max) V

(min) V

(min) V

CC

CC

CC

CC

Fall Time

Fall Time

Rise Time

Rise Time

Min

0

300

10

10

1

Max Unit

µ s

µ s

µ s

µ s

µ s t

REC

V

PFD

(max) to Inputs Recognized 40 200

Notes: 1. V

PFD

(max) to V

PFD

(min) fall time of less than t

F

may result in deselection/write protection not occurring until 200

µ s after

V

CC

passes V

PFD

(min).

2. V

PFD

(min) to V

SO

fall time of less than t

FB

may cause corruption of RAM data.

ms

Unit

V

V

V

V

V

YEARS

Figure 5. Power Down/Up Mode AC Waveforms

VCC

VPFD (max)

VPFD (min)

VSO

INPUTS tF tPD

RECOGNIZED tFB

OUTPUTS VALID

(PER CONTROL INPUT) tDR tRB

DON'T CARE

HIGH-Z tR tREC

RECOGNIZED

VALID

(PER CONTROL INPUT)

AI01168B

6/17

M48T35, M48T35Y, M48T35V

Table 9. Read Mode AC Characteristics

(T

A

= 0 to 70

°

C; V

CC

= 4.75V to 5.5V or 4.5V to 5.5V or 3.0V to 3.6V)

M48T35 / M48T35Y

Symbol Parameter

-70

Min Max

t

AVAV t

AVQV

(1)

Read Cycle Time

Address Valid to Output Valid t

ELQV

(1) t

GLQV

(1) t

ELQX

(2) t

GLQX

(2)

Chip Enable Low to Output Valid

Output Enable Low to Output Valid

Chip Enable Low to Output Transition

Output Enable Low to Output Transition t

EHQZ

(2) t

GHQZ

(2)

Chip Enable High to Output Hi-Z

Output Enable High to Output Hi-Z t

AXQX

(1)

Address Transition to Output Transition

Notes: 1. C

L

= 100pF (see Figure 4).

2. C

L

= 5pF (see Figure 4).

70

5

5

10

70

70

35

25

25

M48T35V

-100

Min Max

100

100

100

50

10

5

50

40

10

Unit

ns ns ns ns ns ns ns ns ns

Figure 6. Read Mode AC Waveforms

A0-A14

E

G

DQ0-DQ7 tAVQV tELQV tELQX tGLQV tGLQX tAVAV

VALID

VALID tGHQZ tAXQX tEHQZ

AI00925

Note: Write Enable (W) = High

7/17

M48T35, M48T35Y, M48T35V

Table 10. Write Mode AC Characteristics

(T

A

= 0 to 70

°

C; V

CC

= 4.75V to 5.5V or 4.5V to 5.5V or 3.0V to 3.6V)

M48T35 / M48T35Y

Symbol Parameter

Min

-70

Max

M48T35V

-100

Min Max

t

AVAV t

AVWL t

AVEL t

WLWH t

ELEH t

WHAX t

EHAX t

DVWH t

DVEH

Write Cycle Time

Address Valid to Write Enable Low

Address Valid to Chip Enable Low

Write Enable Pulse Width

Chip Enable Low to Chip Enable High

Write Enable High to Address Transition

Chip Enable High to Address Transition

Input Valid to Write Enable High

Input Valid to Chip Enable High

70

0

0

50

55

0

0

30

30

80

80

10

10

50

50 t

WHDX t

EHDX t

WLQZ

(1, 2) t

AVWH

Write Enable High to Input Transition

Chip Enable High to Input Transition

Write Enable Low to Output Hi-Z

Address Valid to Write Enable High

5

5

60

25

5

5

80 t

AVEH t

WHQX

(1, 2)

Address Valid to Chip Enable High

Write Enable High to Output Transition

60

5

Notes: 1. C

L

= 5pF (see Figure 4).

2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

80

10

100

0

0

50

Unit

DATA RETENTION MODE

With valid V

CC

applied, the M48T35/35Y/35V operates as a conventional BYTEWIDE static RAM.

Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when V

CC

f alls within the V

PFD

(max),

V

PFD

(min) window. All outputs become high impedance, and all inputs are treated as "don’t care."

Note: A power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM’s content. At voltages below V

PFD

(min), the user can be assured the memory will be in a write protected state, provided the V

CC

fall time is not less than t

F

.

The M48T35/35Y/35V may respond to transient noise spikes on V

CC

that reach into the deselect window during the time the device is sampling V

CC

.

Therefore, decoupling of the power supply lines is recommended.

When V

CC

drops below V

SO

, the control circuit switches power to the internal battery which preserves data and powers the clock. The internal bu t t o n c e l l wi l l m a in t a i n da t a in t he

M48T35/35Y/35V for an accumulated period of at least 7 years when V

CC

is less than V

SO

. As system power returns and V

CC

rises above V

SO

, the battery is disconnected, and the power supply is switched to external V

CC

. Write protection continues until

V

CC

reaches V

PFD

(min) plus t

REC

(min). E should be kept high as V

CC

rises past V

PFD

(min) to prevent inadvertent write cycles prior to processor stabilization. Normal RAM operation can resume t

REC after V

CC

exceeds V

PFD

(max).

For more information on Battery Storage Life refer to the Application Note AN1012.

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

8/17

M48T35, M48T35Y, M48T35V

Figure 7. Write Enable Controlled, Write AC Waveforms

A0-A14

E

W

DQ0-DQ7 tAVAV

VALID tAVWH tAVEL tWHAX tAVWL tWLQZ tWLWH tWHDX

DATA INPUT tDVWH tWHQX

AI00926

Figure 8. Chip Enable Controlled, Write AC Waveforms

A0-A14

E

W

DQ0-DQ7 tAVEL tAVWL tAVAV

VALID tAVEH tELEH tEHAX

DATA INPUT tDVEH tEHDX

AI00927

9/17

M48T35, M48T35Y, M48T35V

CLOCK OPERATIONS

Reading the Clock

Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent reading data in transition. Because the BiPORT TIME-

KEEPER cells in the RAM array are only data registers, and not the actual clock counters, updating the registers can be halted without disturbing the clock itself.

Updating is halted when a ’1’ is written to the READ bit, D6 in the Control Register 7FF8h. As long as a

’1’ remains in that position, updating is halted.

After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued.

All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a ’0’.

Setting the Clock

Bit D7 of the Control Register 7FF8h is the WRITE bit. Setting the WRITE bit to a ’1’, like the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24 hour BCD format (see Table

11). Resetting the WRITE bit to a ’0’ then transfers the values of all time registers 7FF9h-7FFFh to the actual TIMEKEEPER counters and allows normal operation to resume. The FT bit and the bits marked as ’0’ in Table 11 must be written to ’0’ to allow for normal TIMEKEEPER and RAM operation. After the WRITE bit is reset, the next clock update will occur in approximately one second.

See the Application Note AN923 "TIMEKEEPER rolling into the 21st century" on the ST Web site for information on Century Rollover.

Stopping and Starting the Oscillator

The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP bit is the MSB of the seconds register. Setting it to a ’1’ stops the oscillator. The M48T35/35Y/35V is shipped from STMicroelectronics with the STOP bit s et t o a ’ 1 ’. W h en r e s e t t o a ’ 0’, t he

M48T35/35Y/35V oscillator starts within 1 second.

Calibrating the Clock

The M48T35/35Y/35V is driven by a quartz controlled oscillator with a nominal frequency of 32,768

Hz. The devices are tested not to exceed 35 ppm

(parts per million) oscillator frequency error at

25

°

C, which equates to about

±

1.53 minutes per month. With the calibration bits properly set, the accuracy of each M48T35/35Y/35V improves to better than

±

4 ppm at 25

°

C.

Table 11. Register Map

Address

Data

Function/Range

BCD Format

D7 D6 D5 D4 D3 D2 D1 D0

7FFFh

7FFEh 0

0

0

10 Years

0

0

10 M.

10 Date

Year

Month

Year

Month

00-99

01-12

7FFDh

7FFCh

Date Date

Century/Day

01-31

0-1/01-07 0

0

FT

0

CEB CB

10 Hours

0

Hours

Day

7FFBh

7FFAh

Hour

Minutes

00-23

00-59 0

ST

10 Minutes

10 Seconds

Minutes

Seconds 7FF9h Seconds 00-59

7FF8h W R S Calibration Control

Keys: S = SIGN Bit

FT = FREQUENCY TEST Bit (Must be set to ’0’ upon power, for normal clock operation)

R = READ Bit

W = WRITE Bit

ST = STOP Bit

CEB= CENTURY ENABLE Bit

CB = CENTURY Bit

0 = Must be set to ’0’

Note: When CEB is set to ’1’, CB will toggle from ’0’ to ’1’ or from ’1’ to ’0’ at the turn of the century (dependent upon the initial value set).

When CEB is set to ’0’, CB will not toggle.

The WRITE Bit does not need to be set to write to CEB and CE.

10/17

M48T35, M48T35Y, M48T35V

The oscillation rate of any crystal changes with temperature (see Figure 10). Most clock chips compensate for crystal frequency and temperature shift error with cumbersome trim capacitors. The

M48T35/35Y/35V design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 9.

The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five Calibration bits found in the Control

Register. Adding counts speeds the clock up, subtracting counts slows the clock down.

The Calibration byte occupies the five lower order bits (D4-D0) in the Control Register 7FF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign bit; ’1’ indicates positive calibration, ’0’ indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by

128 or lengthened by 256 oscillator cycles. If a binary ’1’ is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on.

Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles; that is,

+4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz, each of the 31 increments in the Calibration byte would represent +10.7 or - 5.35 seconds per month which corresponds to a total range of +5.5 or - 2.75

minutes per month.

Figure 9. Clock Calibration

Two methods are available for ascertaining how much calibration a given M48T35/35Y/35V may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts).

While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure.

All the designer has to do is provide a simple utility that accesses the Calibration byte.

The second approach is better suited to a manufacturing environment, and involves the use of some test equipment. When the Frequency Test

(FT) bit, the seventh-most significant bit in the Day

Register is set to a ’1’, and D7 of the Seconds

Register is a ’0’ (Oscillator Running), DQ0 will toggle at 512Hz during a read of the Seconds

Register. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of

512.01024 Hz would indicate a +20 PPM oscillator frequency error, requiring a -10 (WR001010) to be loaded into the Calibration Byte for correction. Note that setting or changing the Calibration Byte does not affect the Frequency test output frequency.

The FT bit MUST be reset to ’0’ in order to read the seconds register. A valid read mode (G and E enabled, W disabled) must be set in order to see the 512Hz signal on DQ6. The FT bit is automatically Reset on power-up.

For more information on calibration, see the Application Note AN934 "TIMEKEEPER Calibration".

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

AI00594B

11/17

M48T35, M48T35Y, M48T35V

Figure 10. Crystal Accuracy Across Temperature

ppm

20

0

-20

-40

-60

-80

∆

F = -0.038

F ppm

C

2

(T - T

0

)

2 ±

10%

T

0

= 25

°

C

-100

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70

AI02124

°

C

Figure 11. Supply Voltage Protection

VCC

0.1

µ

F

VCC

DEVICE

VSS

AI02169

POWER ON DEFAULTS

Upon application of power to the device, the following register bits are set to a ’0’ state: FT, W, R.

POWER SUPPLY DECOUPLING and UNDER-

SHOOT PROTECTION

I

CC

transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the V

CC

bus. These transients can be reduced if capacitors are used to store energy, which stabilizes the V

CC

bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1

µ

F (as shown in Figure 11) is recommended in order to provide the needed filtering.

In addition to transients that are caused by normal

SRAM operation, power cycling can generate negative voltage spikes on V

CC

that drive it to values below V

SS

by as much as one Volt. These negative spikes can cause data corruption in the

SRAM while in battery backup mode. To protect from these voltage spikes, it is recommeded to connect a schottky diode from V

CC

to V

SS

(cathode connected to V

CC

, anode to V

SS

). Schottky diode

1N5817 is recommended for through hole and

MBRS120T3 is recommended for surface mount.

12/17

ORDERING INFORMATION SCHEME

Example: M48T35Y -70 MH 1 TR

M48T35, M48T35Y, M48T35V

Supply Voltage and Write

Protect Voltage

35

(1)

V

CC

= 4.75V to 5.5V

V

PFD

= 4.5V to 4.75V

35Y V

CC

= 4.5V to 5.5V

V

PFD

= 4.2V to 4.5V

35V V

CC

= 3.0V to 3.6V

V

PFD

= 2.7V to 3.0V

Speed Package

-70 70ns

(M48T35/Y)

-10 100ns

(M48T35V)

PC PCDIP28

MH

(2)

SOH28

Temp.Range

1 0 to 70

°

C

Shipping Method for SOIC

blank Tubes

TR Tape & Reel

Notes: 1. The M48T35 part is offered with the PCDIP28 (i.e. CAPHAT) package only.

2. The SOIC package (SOH28) requires the battery/crystal package (SNAPHAT) which is ordered separately under the part number

"M4T28-BR12SH1" in plastic tube or "M4T28-BR12SH1TR" in Tape & Reel form.

Caution: Do not place the SNAPHAT battery/crystal package "M4T28-BR12SH1" in conductive foam since this will drain the lithium button-cell battery.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.

13/17

Symb

C

D

E e1 e3 eA

L

N

A

A1

A2

B

B1

M48T35, M48T35Y, M48T35V

PCDIP28 - 28 pin Plastic DIP, battery CAPHAT

Typ mm

Min

8.89

0.38

8.38

0.38

1.14

0.20

39.37

17.83

2.29

29.72

15.24

3.05

28

Max

9.65

0.76

8.89

0.53

1.78

0.31

39.88

18.34

2.79

36.32

16.00

3.81

Typ inches

Min

0.350

0.015

0.330

0.015

0.045

0.008

1.550

0.702

0.090

1.170

0.600

0.120

28

Max

0.380

0.030

0.350

0.021

0.070

0.012

1.570

0.722

0.110

1.430

0.630

0.150

Drawing is not to scale.

14/17

B1

N

1 e3

B

D

A2 A

A1 e1

L

E eA

C

PCDIP

M48T35, M48T35Y, M48T35V

Symb

D

E e eB

H

L

α

N

CP

A

A1

A2

B

C

SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT

Typ mm

Min Typ inches

Min

1.27

0.05

2.34

0.36

0.15

17.71

8.23

–

3.20

11.51

0.41

0

°

28

Max

3.05

0.36

2.69

0.51

0.32

18.49

8.89

–

3.61

12.70

1.27

8

°

0.10

0.050

0.002

0.092

0.014

0.006

0.697

0.324

–

0.126

0.453

0.016

0

°

28

Max

0.120

0.014

0.106

0.020

0.012

0.728

0.350

–

0.142

0.500

0.050

8

°

0.004

B e

N

D

A2

CP

E H

1

SOH

Drawing is not to scale.

A eB

A1

α

L

C

15/17

M48T35, M48T35Y, M48T35V

Symb

D

E eA eB

L

A

A1

A2

A3

B

SH - SNAPHAT Housing for 28 lead Plastic Small Outline

Typ mm

Min Typ inches

Min

6.73

6.48

0.46

21.21

14.22

15.55

3.20

2.03

Max

9.78

7.24

6.99

0.38

0.56

21.84

14.99

15.95

3.61

2.29

0.265

0.255

0.018

0.835

0.560

0.612

0.126

0.080

Max

0.385

0.285

0.275

0.015

0.022

0.860

0.590

0.628

0.142

0.090

Drawing is not to scale.

16/17 eA

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A1

A

B eB

A3

A2

L

E

SH

M48T35, M48T35Y, M48T35V

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

© 1998 STMicroelectronics - All Rights Reserved

® TIMEKEEPER and SNAPHAT are registered trademarks of STMicroelectronics



CAPHAT, BYTEWIDE and BiPORT are trademarks of STMicroelectronics

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands -

Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

17/17