STMicroelectronics M48T08Y Datasheet
Below you will find brief information for real-time clock M48T 08. The M48T08, M48T08Y, and M48T18 devices offer an 8 K x 8 non-volatile static RAM and real-time clock. These devices provide a highly integrated battery-backed memory and real-time clock solution for a variety of applications.
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M48T08
M48T08Y, M48T18
5 V, 64 Kbit (8 Kb x 8) TIMEKEEPER
®
SRAM
Features
■
■
■
■
■
■
■
■
■
■
■
■
Integrated ultra low power SRAM, real-time clock, power-fail control circuit, and battery
BYTEWIDE
™
RAM-like clock access
BCD coded year, month, day, date, hours, minutes, and seconds
Typical clock accuracy of ±1 minute a month, at
25 °C
Automatic power-fail chip deselect and WRITE protection
WRITE protect
V
PFD
= power-fail deselect voltage):
– M48T08: V
CC
4.5 V
≤ V
PFD
= 4.75 to 5.5 V;
≤ 4.75 V
– M48T18/T08Y: V
CC
4.2 V
≤ V
PFD
= 4.5 to 5.5 V;
≤ 4.5 V
Software controlled clock calibration for high accuracy applications
Self-contained battery and crystal in the
CAPHAT
™
DIP package
Packaging includes a 28-lead SOIC and
SNAPHAT
® top (to be ordered separately)
SOIC package provides direct connection for a snaphat top which contains the battery and crystal
Pin and function compatible with DS1643 and
JEDEC standard 8 K x 8 SRAMs
RoHS compliant
– Lead-free second level interconnect
28
1
PCDIP28 battery/crystal
CAPHAT™
SNAPHAT
® battery/crystal
28
1
SOH28
June 2011 Doc ID 2411 Rev 11 1/31
www.st.com
1
Contents
Contents
M48T08, M48T08Y, M48T18
Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CC
noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 18
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2/31 Doc ID 2411 Rev 11
M48T08, M48T08Y, M48T18
List of tables
List of tables
PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package mech. data . . . . . . . . . . . . . 23
SOH28 – 28-lead plastic SO, 4-socket battery SNAPHAT
®
, package mech. data. . . . . . . 24
housing for 48 mAh battery & crystal, package mech. data . . . . . 25
housing for 120 mAh battery & crystal, package mech. data . . . . 26
Doc ID 2411 Rev 11 3/31
List of figures
List of figures
M48T08, M48T08Y, M48T18
PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline . . . . . . . . . . . . . . . . . 23
SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT
, package outline . . . 24
housing for 48 mAh battery & crystal, package outline. . . . . . . . . 25
housing for 120 mAh battery & crystal, package outline. . . . . . . . 26
4/31 Doc ID 2411 Rev 11
M48T08, M48T08Y, M48T18
1 Description
Description
The M48T08/18/08Y TIMEKEEPER
®
RAM is an 8 K x 8 non-volatile static RAM and realtime clock which is pin and function compatible with the DS1643. The monolithic chip is available in two special packages to provide a highly integrated battery-backed memory and real-time clock solution.
The M48T08/18/08Y is a non-volatile pin and function equivalent to any JEDEC standard
8 K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed.
The 28-pin, 600 mil DIP CAPHAT™ houses the M48T08/18/08Y silicon with a quartz crystal and a long-life lithium button cell in a single package.
The 28-pin, 330 mil SOIC provides sockets with gold-plated contacts at both ends for direct connection to a separate SNAPHAT
® housing containing the battery and crystal. The unique design allows the SNAPHAT
®
battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT
®
housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT
®
housing is keyed to prevent reverse insertion.
The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in tape & reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT
®
) part number is “M4T28-BR12SH” or “M4T32-BR12SH”.
Figure 1.
Logic diagram
VCC
A0-A12
13
W
E1
E2
G
M48T08
M48T08Y
M48T18
8
DQ0-DQ7
INT
VSS
AI01020
Doc ID 2411 Rev 11 5/31
Description
Table 1.
A0-A12
G
W
V
CC
V
SS
DQ0-DQ7
INT
E1
E2
Signal names
Address inputs
Data inputs / outputs
Power fail interrupt (open drain)
Chip enable 1
Chip enable 2
Output enable
WRITE enable
Supply voltage
Ground
Figure 2.
DIP connections
A3
A2
A1
A0
DQ0
DQ1
DQ2
INT
A12
A7
A6
A5
A4
VSS
11
12
13
7
8
9
10
3
4
1
2
5
6
14
M48T08
M48T18
22
21
20
19
18
17
16
28
27
26
25
24
23
15
G
A10
E1
DQ7
DQ6
DQ5
DQ4
VCC
W
E2
A8
A9
A11
DQ3
M48T08, M48T08Y, M48T18
AI01182
Figure 3.
SOIC connections
INT
A12
A7
DQ0
DQ1
DQ2
VSS
A6
A5
A4
A3
A2
A1
A0
6
7
8
4
5
9
10
1
2
3
11
12
13
14
M48T08Y
25
24
23
22
21
20
19
18
17
16
15
28
27
26
VCC
W
E2
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5
DQ4
DQ3
AI01021B
6/31 Doc ID 2411 Rev 11
M48T08, M48T08Y, M48T18
Figure 4.
Block diagram
OSCILLATOR AND
CLOCK CHAIN
32,768 Hz
CRYSTAL
POWER
LITHIUM
CELL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
VPFD
8 x 8 BiPORT
SRAM ARRAY
8184 x 8
SRAM ARRAY
VCC INT VSS
Description
A0-A12
DQ0-DQ7
E1
E2
W
G
AI01333
Doc ID 2411 Rev 11 7/31
Operation modes M48T08, M48T08Y, M48T18
Note:
As
shows, the static memory array and the quartz-controlled clock oscillator of the M48T08/18/08Y are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with addresses 1FF8h-1FFFh.
The clock locations contain the year, month, date, day, hour, minute, and second in 24-hour
BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. Byte 1FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting.
The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORT™ READ/WRITE memory cells. The M48T08/18/08Y includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array.
The M48T08/18/08Y also has its own power-fail detect circuit. The control circuitry constantly monitors the single 5 V supply for an out-of-tolerance condition. When V
CC
is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low V battery backup switchover voltage (V
SO
CC
. As V
CC
falls below the
), the control circuitry connects the battery which maintains data and clock operation until valid power returns.
Table 2.
Operating modes
Mode V
CC
E1
Deselect
Deselect
READ
READ
V
IH
X
WRITE
4.75 to 5.5 V or
4.5 to 5.5 V
V
IL
V
IL
V
IL
Deselect
Deselect
V
SO
to
V
PFD
(min)
(1)
≤ V
SO
(1)
X
X
1.
See
E2
X
V
IL
V
IH
V
IH
V
IH
X
X
G
X
X
X
V
IL
V
IH
X
X
W
X
X
V
IL
V
IH
V
IH
X
X
X = V
IH
or V
IL
; V
SO
= Battery backup switchover voltage.
DQ0-DQ7
High Z
High Z
D
IN
D
OUT
High Z
High Z
High Z
Power
Standby
Standby
Active
Active
Active
CMOS standby
Battery backup mode
8/31 Doc ID 2411 Rev 11
M48T08, M48T08Y, M48T18 Operation modes
The M48T08/18/08Y is in the READ mode whenever W (WRITE enable) is high, E1 (chip enable 1) is low, and E2 (chip enable 2) is high. The device architecture allows ripplethrough access of data from eight of 65,536 locations in the static storage array. Thus, the unique address specified by the 13 address inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be available at the data I/O pins within address access time (t
AVQV
) after the last address input signal is stable, providing that the E1, E2, and G access times are also satisfied. If the E1, E2 and G access times are not met, valid data will be available after the latter of the chip enable access times (t
E1LQV
or t
E2HQV
) or output enable access time (t
GLQV
).
The state of the eight three-state data I/O signals is controlled by E1, E2 and G. If the outputs are activated before t
AVQV
, the data lines will be driven to an indeterminate state until t
AVQV
. If the address inputs are changed while E1, E2 and G remain active, output data will remain valid for output data hold time (t
AXQX
) but will go indeterminate until the next address access.
Figure 5.
READ mode AC waveforms
A0-A12 tAVAV
VALID tAVQV tE1LQV tAXQX tE1HQZ
E1 tE1LQX tE2HQV tE2LQZ
E2 tE2HQX tGLQV tGHQZ
G tGLQX
DQ0-DQ7 VALID
AI00962
Note: WRITE enable (W) = high.
Doc ID 2411 Rev 11 9/31
Operation modes M48T08, M48T08Y, M48T18
t
AVAV t
AVQV t
E1LQV t
E2HQV t
GLQV t
E1LQX t
E2HQX t
GLQX t
E1HQZ t
E2LQZ t
GHQZ t
AXQX
Note:
Table 3.
Symbol
READ mode AC characteristics
M48T08/M48T18/T08Y
Parameter
(1)
READ cycle time
Address valid to output valid
Chip enable 1 low to output valid
Chip enable 2 high to output valid
Output enable low to output valid
Chip enable 1 low to output transition
Chip enable 2 high to output transition
Output enable low to output transition
Chip enable 1 high to output Hi-Z
Chip enable 2 low to output Hi-Z
Output enable high to output Hi-Z
Address transition to output transition
–100/–10 (T08Y)
Min
100
Max
100
100
100
50
10
10
5
50
50
40
5
–150/–15 (T08Y)
Min
150
Max
150
150
150
75
10
10
5
75
75
60
5
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
Valid for ambient operating temperature: T
A
= 0 to 70 °C; V
CC
(except where noted).
= 4.75 to 5.5 V or 4.5 to 5.5 V
The M48T08/18/08Y is in the WRITE mode whenever W, E1, and E2 are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E1, or the rising edge of
E2. A WRITE is terminated by the earlier rising edge of W or E1, or the falling edge of E2.
The addresses must be held valid throughout the cycle. E1 or W must return high or E2 low for a minimum of t
E1HAX
or t
E2LAX
from chip enable or t
WHAX
from WRITE enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid t
DVWH
prior to the end of
WRITE and remain valid for t
WHDX
afterward. G should be kept high during WRITE cycles to avoid bus contention; however, if the output bus has been activated by a low on E1 and G and a high on E2, a low on W will disable the outputs t
WLQZ
after W falls.
10/31 Doc ID 2411 Rev 11
M48T08, M48T08Y, M48T18
Figure 6.
WRITE enable controlled, WRITE AC waveform
A0-A12 tAVAV
VALID tAVWH tAVE1L
E1 tAVE2H
E2 tWLWH tAVWL
W tWLQZ
DQ0-DQ7 tWHDX
DATA INPUT tDVWH tWHAX tWHQX
Operation modes
AI00963
Figure 7.
Chip enable controlled, WRITE AC waveforms
A0-A12 tAVE1L tAVAV
VALID tAVE1H tE1LE1H
E1 tE1HAX tAVE2H tAVE2L tE2HE2L tE2LAX
E2 tAVWL
W
DQ0-DQ7 DATA INPUT tDVE1H tDVE2L tE1HDX tE2LDX
AI00964B
Doc ID 2411 Rev 11 11/31
Operation modes M48T08, M48T08Y, M48T18
Table 4.
WRITE mode AC characteristics
M48T08/M48T18/T08Y
Symbol Parameter
(1)
–100/–10 (T08Y) –150/–15 (T08Y)
Min Max Min Max
t
DVWH t
DVE1H t
DVE2L t
WHDX t
E1HDX t
E2LDX t
WLQZ t
AVWH t
AVAV t
AVWL t
AVE1L t
AVE2H t
WLWH t
E1LE1H t
E2HE2L t
WHAX t
E1HAX t
E2LAX t
AVE1H t
AVE2L t
WHQX
WRITE cycle time
Address valid to WRITE enable low
Address valid to chip enable 1 low
Address valid to chip enable 2 high
WRITE enable pulse width
Chip enable 1 low to chip enable 1 high
Chip enable 2 high to chip enable 2 low
WRITE enable high to address transition
Chip enable 1 high to address transition
Chip enable 2 low to address transition
Input valid to WRITE enable high
Input valid to chip enable 1 high
Input valid to chip enable 2 low
WRITE enable high to input transition
Chip enable 1 high to input transition
Chip enable 2 low to input transition
WRITE enable low to output Hi-Z
Address valid to WRITE enable high
Address valid to chip enable 1 high
Address valid to chip enable 2 low
WRITE enable high to output transition
100
0
0
0
80
80
80
10
10
10
50
50
50
5
5
5
80
80
80
10
50
150
0
0
0
100
130
130
10
10
10
70
70
70
5
5
5
130
130
130
10
70
1.
Valid for ambient operating temperature: T
A
= 0 to 70 °C; V
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
12/31 Doc ID 2411 Rev 11
M48T08, M48T08Y, M48T18 Operation modes
Note:
Note:
2.4
With valid V
CC
applied, the M48T08/18/08Y operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when V
CC
falls within the V
PFD
(max), V
PFD
(min) window. All outputs become high impedance, and all inputs are treated as “Don't care.”
A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below V
PFD
(min), the user can be assured the memory will be in a write protected state, provided the V
CC
fall time is not less than t
F
. The M48T08/18/08Y may respond to transient noise spikes on V
CC
that reach into the deselect window during the time the device is sampling V
CC
. Therefore, decoupling of the power supply lines is recommended.
When V
CC
drops below V
SO
, the control circuit switches power to the internal battery which preserves data and powers the clock. The internal button cell will maintain data in the
M48T08/18/08Y for an accumulated period of at least 10 years when V
CC
is less than V
SO
.
Requires use of M4T32-BR12SH SNAPHAT
®
top when using the SOH28 package.
As system power returns and V
CC
rises above V
SO
, the battery is disconnected and the power supply is switched to external V
CC
.
Write protection continues until V
CC
reaches V
PFD
(min) plus t rec
(min). E1 should be kept high or E2 low as V
CC
rises past V
PFD
(min) to prevent inadvertent WRITE cycles prior to system stabilization. Normal RAM operation can resume t rec
after V
CC exceeds V
PFD
(max).
For more information on battery storage life refer to the application note AN1012.
Power-fail interrupt pin
The M48T08/18/08Y continuously monitors V
CC
. When V
CC
falls to the power-fail detect trip point, an interrupt is immediately generated. An internal clock provides a delay of between
10 µs and 40 µs before automatically deselecting the M48T08/18/08Y. The INT pin is an open drain output and requires an external pull-up resistor, even if the interrupt output function is not being used.
Doc ID 2411 Rev 11 13/31
Clock operations M48T08, M48T08Y, M48T18
3.1
3.2
Reading the clock
Updates to the TIMEKEEPER
®
registers should be halted before clock data is read to prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself.
Updating is halted when a '1' is written to the READ bit, the seventh bit in the control register. As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a '0.'
Setting the clock
The eighth bit of the control register is the WRITE bit. Setting the WRITE bit to a '1,' like the
READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24-hour BCD format (on
WRITE bit to a '0' then transfers the values of all time registers (1FF9h-1FFFh) to the actual
TIMEKEEPER counters and allows normal operation to resume. The FT bit and the bits
must be written to '0' to allow for normal TIMEKEEPER and RAM operation.
See the application note AN923, “TIMEKEEPER
®
rolling Into the 21 st
century” for information on century rollover.
14/31 Doc ID 2411 Rev 11
M48T08, M48T08Y, M48T18 Clock operations
1FFFh
1FFEh
1FFDh
1FFCh
1FFBh
1FFAh
1FF9h
1FF8h
Table 5.
Address
0
0
ST
W
0
0
0
Register map
D7 D6 D5 D4
10 years
0 0
0
FT
10 M
0
10 date
0
0 10 hours
10 minutes
R
10 seconds
S
Data
Function/range
BCD format
D3 D2 D1 D0
0
Year
Month
Date
Day
Year
Month
Date
Day
Hours
Minutes
Hours
Minutes
Seconds Seconds
Calibration Control
00-99
01-12
01-31
01-07
00-23
00-59
00-59
Keys:
S = SIGN bit
FT = FREQUENCY TEST bit (set to '0' for normal clock operation)
R = READ bit
W = WRITE bit
ST = STOP bit
0 = Must be set to '0'
3.3
Note:
3.4
Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP bit (ST) is the MSB of the seconds register. Setting it to a '1' stops the oscillator. The M48T08/18/08Y (in the PCDIP28 package) is shipped from
STMicroelectronics with the STOP bit set to a '1.' When reset to a '0,' the M48T08/18/08Y oscillator starts within one second.
To guarantee oscillator startup after initial power-up, first write the STOP bit (ST) to '1,' then reset to '0.'
Calibrating the clock
The M48T08/18/08Y is driven by a quartz-controlled oscillator with a nominal frequency of
32,768 Hz. A typical M48T08/18/08Y is accurate within 1 minute per month at 25 °C without calibration. The devices are tested not to exceed ± 35 ppm (parts per million) oscillator frequency error at 25 °C, which equates to about ±1.53 minutes per month. With the calibration bits properly set, the accuracy of each M48T08/18/08Y improves to better than
+1/–2 ppm at 25 °C.
The oscillation rate of any crystal changes with temperature.
frequency error that can be expected at various temperatures. Most clock chips compensate for crystal frequency and temperature shift error with cumbersome “trim” capacitors. The
Doc ID 2411 Rev 11 15/31
Clock operations
Note:
M48T08, M48T08Y, M48T18
M48T08/18/08Y design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in
. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five-bit calibration byte found in the control register. Adding counts speeds the clock up, subtracting counts slows the clock down.
The calibration byte occupies the five lower order bits in the control register. This byte can be set to represent any value between 0 and 31 in binary form. The sixth bit is the sign bit;
'1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a
64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles; that is +4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or
–2.75 minutes per month.
Two methods are available for ascertaining how much calibration a given M48T08/18/08Y may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accesses the calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use of standard test equipment. When the frequency test (FT) bit, the seventh-most significant bit in the day register, is set to a '1,' and the oscillator is running at 32,768 Hz, the LSB
(DQ0) of the seconds register will toggle at 512 Hz. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a
–10 (WR001010) to be loaded into the calibration byte for correction.
Setting or changing the calibration byte does not affect the frequency test output frequency.
The device must be selected and addresses must be stable at address 1FF9h when reading the 512 Hz on DQ0.
The LSB of the seconds register is monitored by holding the M48T08/18/08Y in an extended
READ of the seconds register, but without having the READ bit set. The FT bit MUST be reset to '0' for normal clock operations to resume.
For more information on calibration, see the application note AN934, “TIMEKEEPER
® calibration.”
16/31 Doc ID 2411 Rev 11
M48T08, M48T08Y, M48T18
Figure 8.
Crystal accuracy across temperature
ppm
20
0
-20
-40
-60
-80
ΔF
F
= -0.038
ppm
C
2
(T - T
0
)
2 ± 10%
T
0
= 25
°C
Clock operations
-100
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
°C
AI02124
Figure 9.
Clock calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
Doc ID 2411 Rev 11 17/31
Clock operations M48T08, M48T08Y, M48T18
3.5 V
CC
noise and negative going transients
I
CC
transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the V
CC
bus. These transients can be reduced if capacitors are used to store energy which stabilizes the V
CC
bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in
) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on V
CC
that drive it to values below V
SS
by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a
Schottky diode from V
CC
to V
SS
(cathode connected to V
CC
, anode to V
SS
). Schottky diode
1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount.
Figure 10.
Supply voltage protection
VCC
VCC
0.1µF DEVICE
VSS
AI02169
18/31 Doc ID 2411 Rev 11
M48T08, M48T08Y, M48T18 Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 6.
Symbol
Absolute maximum ratings
Parameter Value Unit
T
A
T
STG
T
SLD
(1)(2)(3)
V
IO
V
CC
I
O
P
D
Ambient operating temperature
Storage temperature (V
CC
off, oscillator off)
Lead solder temperature for 10 seconds
Input or output voltages
Supply voltage
Output current
Power dissipation
0 to 70
–40 to 85
260
–0.3 to 7
–0.3 to 7
20
1
°C
°C
°C
V
V mA
W
1.
For DIP package, soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds.
Furthermore, the devices shall not be exposed to IR reflow nor preheat cycles (as performed as part of wave soldering). ST recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries.
2.
For DIP packaged devices, ultrasound vibrations should not be used for post-solder cleaning to avoid damaging the crystal.
3.
For SO package, lead-free (Pb-free) lead finish: reflow at peak temperature of 260 °C (the time above
255 °C must not exceed 30 seconds).
Caution:
Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup mode.
Caution:
Do NOT wave solder SOIC to avoid damaging SNAPHAT
®
sockets.
Doc ID 2411 Rev 11 19/31
DC and AC parameters
5 DC and AC parameters
Note:
M48T08, M48T08Y, M48T18
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 7.
Operating and AC measurement conditions
Parameter M48T08 M48T18/T08Y
Supply voltage (V
CC
)
Ambient operating temperature (T
A
)
Load capacitance (C
L
)
Input rise and fall times
Input pulse voltages
Input and output timing ref. voltages
4.75 to 5.5
0 to 70
100
≤ 5
0 to 3
1.5
4.5 to 5.5
0 to 70
100
≤ 5
0 to 3
1.5
Output Hi-Z is defined as the point where data is no longer driven.
Figure 11.
AC testing load circuit
Unit
V
°C pF ns
V
V
5V
DEVICE
UNDER
TEST
1k
Ω
1.8k
Ω
OUT
CL = 100pF
CL includes JIG capacitance
Table 8.
Symbol
Capacitance
Parameter
(1)(2)
Min Max
C
IN
C
IO
(3)
Input capacitance
Input / output capacitance -
10
10
1.
Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested.
2.
At 25 °C, f = 1 MHz.
3.
Outputs deselected.
AI01019
Unit
pF pF
20/31 Doc ID 2411 Rev 11
M48T08, M48T08Y, M48T18 DC and AC parameters
Table 9.
DC characteristics
M48T08/M48T18/T08Y
Symbol Parameter Test condition
(1)
Min Max
I
LI
I
LO
(2)
I
CC
I
CC1
(3)
Input leakage current
Output leakage current
Supply current
0V
≤ V
IN
≤ V
CC
0V
≤ V
OUT
≤ V
CC
Outputs open
±1
±1
80
I
CC2
(3)
Supply current (standby) TTL
Supply current (standby) CMOS
E1 = V
IH,
E2 = V
IL
E1 = V
CC
– 0.2V,
E2 = V
SS
+ 0.2V
3
3
V
V
V
IL
IH
OL
V
OH
Input low voltage
Input high voltage
Output low voltage
Output low voltage (INT)
Output high voltage
(4)
I
OL
= 2.1 mA
I
OL
= 0.5 mA
I
OH
= –1 mA
–0.3
2.2
2.4
0.8
V
CC
+ 0.3
0.4
0.4
1.
Valid for ambient operating temperature: T
A
= 0 to 70 °C; V
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).
2.
Outputs deselected.
3.
Measured with control bits set as follows: R = '1'; W, ST, FT = '0.'
4.
The INT pin is open drain.
Unit
mA
µA
µA mA mA
V
V
V
V
V
Figure 12.
Power down/up mode AC waveforms
VCC
VPFD (max)
VPFD (min)
VSO tF tDR tR tPD tFB tPFX tRB tPFH
INT trec
RECOGNIZED INPUTS RECOGNIZED DON'T CARE NOTE
Note:
HIGH-Z
OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI00566
Inputs may or may not be recognized at this time. Caution should be taken to keep E1 high or E2 low as V
CC
rises past V
PFD
(min). Some systems may perform inadvertent WRITE cycles after V
CC
rises above V
PFD
(min) but before normal system operations begin. Even though a power on reset is being applied to the processor, a reset condition may not occur until after the system clock is running.
Doc ID 2411 Rev 11 21/31
DC and AC parameters M48T08, M48T08Y, M48T18
Table 10.
Power down/up AC characteristics
Symbol Parameter
(1)
Min Max Unit
t
PD t
F
(2) t
FB
(3) t
R t
RB t rec t
PFX t
PFH
E1 or W at V
IH
or E2 at V
IL
before power-down
V
PFD
(max) to V
PFD
(min) V
CC
fall time
V
PFD
(min) to V
SS
V
PFD
V
CC
fall time
V
PFD
(min) to V
PFD
(max) V
CC
rise time
V
SS
to V
PFD
(min) V
CC
rise time
E1 or W at V
IH
or E2 at V
IL before power-up
INT low to auto deselect
(max) to INT high
0
300
10
0
1
1
10 40
120
µs
µs
µs
µs
µs ms
µs
µs
1.
Valid for ambient operating temperature: T
A noted).
= 0 to 70 °C; V
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where
2.
V
PFD
(max) to V
PFD until 200 µs after V
(min) fall time of less than t
F
CC
passes V
PFD
(min).
may result in deselection/write protection not occurring
3.
V
PFD
(min) to V
SS
fall time of less than t
FB
may cause corruption of RAM data.
Table 11.
Power down/up trip points DC characteristics
Symbol Parameter
(1)(2)
Min Typ Max Unit
M48T08 4.5
4.6
4.75
V
V
PFD
Power-fail deselect voltage
M48T18/T08Y 4.2
4.3
4.5
V
V
SO t
DR
Battery backup switchover voltage
Expected data retention time 10
(3)
3.0
V
Years
1.
All voltages referenced to V
SS
.
2.
Valid for ambient operating temperature: T
A noted).
= 0 to 70 °C; V
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where
3.
At 55 °C, V
CC
= 0 V; t
DR
= 8.5 years (typ) at 70 °C. Requires use of M4T32-BR12SH SNAPHAT using the SOH28 package.
®
top when
22/31 Doc ID 2411 Rev 11
M48T08, M48T08Y, M48T18
6 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at:
www.st.com
.
ECOPACK
®
is an ST trademark.
Figure 13.
PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline
Note:
A2 A
A1 e1
L C
B1 e3
B
D eA
N
E
1
PCDIP
Drawing is not to scale.
Table 12.
PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package mech. data
mm inches
Symb
Typ Min Max Typ Min Max
e3 eA
L
N
C
D
E e1
A
A1
A2
B
B1
33.02
8.89
0.38
8.38
0.38
1.14
0.20
39.37
17.83
2.29
15.24
3.05
28
9.65
0.76
8.89
0.53
1.78
0.31
39.88
18.34
2.79
16.00
3.81
1.3
0.350
0.015
0.330
0.015
0.045
0.008
1.550
0.702
0.090
0.600
0.120
28
0.380
0.030
0.350
0.021
0.070
0.012
1.570
0.722
0.110
0.630
0.150
Doc ID 2411 Rev 11 23/31
Package mechanical data M48T08, M48T08Y, M48T18
Figure 14.
SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT
®
, package outline
A2 A
C
B e
CP eB
D
N
Note:
E H
A1
α
L
1
SOH-A
Drawing is not to scale.
Table 13.
SOH28 – 28-lead plastic SO, 4-socket battery SNAPHAT
®
, package mech. data mm inches
Symb
Typ Min Max Typ Min Max
E e
C
D
A
A1
A2
B eB
H
L
α
N
CP
1.27
0.05
2.34
0.36
0.15
17.71
8.23
–
3.20
11.51
0.41
0°
28
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
3.61
12.70
1.27
8°
0.10
0.050
0.002
0.092
0.014
0.006
0.697
0.324
–
0.126
0.453
0.016
0°
28
0.004
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
0.142
0.500
0.050
8°
24/31 Doc ID 2411 Rev 11
M48T08, M48T08Y, M48T18 Package mechanical data
Figure 15.
SH – 4-pin SNAPHAT
®
housing for 48 mAh battery & crystal, package outline
eA
D
A1
A
B eB
A3
A2
L
Note:
E
SHTK-A
Drawing is not to scale.
Table 14.
SH – 4-pin SNAPHAT
®
housing for 48 mAh battery & crystal, package mech. data mm inches
Symb
Typ Min Max Typ Min Max
A
A1
A2
A3
B
D
E eA eB
L
6.73
6.48
0.46
21.21
14.22
15.55
3.20
2.03
9.78
7.24
6.99
0.38
0.56
21.84
14.99
15.95
3.61
2.29
0.265
0.255
0.018
0.835
0.560
0.612
0.126
0.080
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.628
0.142
0.090
Doc ID 2411 Rev 11 25/31
Package mechanical data M48T08, M48T08Y, M48T18
Figure 16.
SH – 4-pin SNAPHAT
®
housing for 120 mAh battery & crystal, package outline
A1
A A3
A2 eA
D
B eB
L
Note:
E
SHTK-A
Drawing is not to scale.
Table 15.
SH – 4-pin SNAPHAT
®
housing for 120 mAh battery & crystal, package mech. data mm inches
Symb
Typ Min Max Typ Min Max
A3
B
D
E
A
A1
A2 eA eB
L
8.00
7.24
0.46
21.21
17.27
15.55
3.20
2.03
10.54
8.51
8.00
0.38
0.56
21.84
18.03
15.95
3.61
2.29
0.315
0.285
0.018
0.835
0.680
0.612
0.126
0.080
0.415
.0335
0.315
0.015
0.022
0.860
.0710
0.628
0.142
0.090
26/31 Doc ID 2411 Rev 11
M48T08, M48T08Y, M48T18 Part numbering
Table 16.
Ordering information scheme
Example: M48T 18 –100 PC 1 E
Device type
M48T
Supply voltage and write protect voltage
08
(1)
= V
CC
= 4.75 to 5.5 V; V
PFD
= 4.5 to 4.75 V
18/08Y = V
CC
= 4.5 to 5.5 V; V
PFD
= 4.2 to 4.5 V
Speed
–100 = 100 ns
–150 = 150 ns
–10 = 100 ns (M48T08Y)
Package
PC
(1)
= PCDIP28
MH
(2)
= SOH28
Temperature range
1 = 0 to 70 °C
Shipping method
For SOH28:
blank = Tubes (not for new design - use E)
E = ECOPACK
®
package, tubes
F = ECOPACK
®
package, tape & reel
TR = Tape & reel (not for new design - use F)
For PCDIP28:
blank = ECOPACK
®
package, tubes
1.
The M48T08/18 part is offered with the PCDIP28 (e.g., CAPHAT™) package only.
2.
The SOIC package (SOH28) requires the SNAPHAT
®
battery/crystal package which is ordered separately under the part number “M4TXX-BR12SH” in plastic tube or “M4TXX-BR12SHTR” in tape & reel form (see
). The M48T08Y part is offered in the SOH28 (SNAPHAT) package only.
Caution:
Do not place the SNAPHAT
®
battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell battery.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Doc ID 2411 Rev 11 27/31
Part numbering
Table 17.
SNAPHAT
®
battery table
Part number
M4T28-BR12SH
M4T32-BR12SH
Description
Lithium battery (48 mAh) SNAPHAT
®
Lithium battery (120 mAh) SNAPHAT
®
M48T08, M48T08Y, M48T18
Package
SH
SH
28/31 Doc ID 2411 Rev 11
M48T08, M48T08Y, M48T18
Figure 17.
Recycling symbols
Environmental information
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations.
Doc ID 2411 Rev 11 29/31
Revision history M48T08, M48T08Y, M48T18
Table 18.
Document revision history
Date
Dec-1999
07-Feb-2000
11-Jul-2000
16-Jul-2001
01-Aug-2001
21-Dec-2001
06-Mar-2002
20-May-2002
29-Aug-2002
28-Mar-2003
10-Dec-2003
30-Mar-2004
13-Dec-2005
04-Jul-2007
10-Feb-2009
21-Jun-2010
07-Jun-2011
Revision
1
2
2.1
3
3.1
3.2
3.3
3.4
3.5
4
5
6
7
8
9
10
11
Changes
First Issue
From Preliminary Data to Datasheet; Battery Low Flag paragraph
changed; 100ns speed class identifier changed (
,
) t
FB
changed (
); Watchdog Timer paragraph changed
Reformatted; SNAPHAT battery table added (
temp./voltage info. to tables (
,
,
Reference to App. Note corrected in “Calibrating the Clock” section
Changes to text in document to reflect addition of M48T08Y option
Fix Ordering Information table and add to footnote (
)
Modify reflow time and temperature footnotes (
t
DR
specification temperature updated (
) v2.2 template applied; updated test conditions (
Reformatted
Reformatted; Lead-free (Pb-free) information package update (
,
Updated template, Lead-free information, removed footnote (
,
Reformatted; added lead-free second level interconnect information to cover page and
Section 6: Package mechanical data
.
Updated
Section 6: Package mechanical data
Section 8: Environmental information
Updated
Updated footnote
1
of
Table 6: Absolute maximum ratings
; updated
Section 8: Environmental information
30/31 Doc ID 2411 Rev 11
M48T08, M48T08Y, M48T18
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Information in this document supersedes and replaces all information previously supplied.
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Doc ID 2411 Rev 11 31/31
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Key features
Integrated ultra low power SRAM
Real-time clock
Power-fail control circuit
Battery backup
BYTEWIDE RAM-like clock access
BCD coded year, month, day, date, hours, minutes, and seconds
Clock accuracy of ±1 minute a month
Automatic power-fail chip deselect
WRITE protection
Software controlled clock calibration
Frequently asked questions
The M48T08 has a VCC range of 4.75 to 5.5 V and a VPFD range of 4.5 to 4.75 V. The M48T18/T08Y has a VCC range of 4.5 to 5.5 V and a VPFD range of 4.2 to 4.5 V.
The M48T08/18/08Y employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five-bit calibration byte found in the control register. Adding counts speeds the clock up, subtracting counts slows the clock down.
The internal button cell will maintain data in the M48T08/18/08Y for an accumulated period of at least 10 years when VCC is less than VSO.