RAM is a 32 Kbit x 8 non-volatile static RAM and real-time clock. The monolithic chip is available in two special packages to provide a highly integrated battery-backed memory and real-time clock solution.

The M48T35AV is a non-volatile pin and function equivalent to any JEDEC standard

32 Kb x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed.

The 28-pin, 600 mil DIP CAPHAT

™

houses the M48T35AV silicon with a quartz crystal and a long-life lithium button cell in a single package.

The 28-pin, 330 mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT

housing containing the battery and crystal. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion.

The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in tape & reel form.

For the 28-lead SOIC, the battery/crystal package part numbers are M4T28-BR12SH1 (48 mAh lithium battery SNAPHAT), M4T32-BR12SH1 (120 mAh lithium battery SNAPHAT), and M4T32-BR12SH6 (120 mAh lithium battery SNAPHAT, –40 to +85 °C crystal).

Figure 1.

Logic diagram

VCC

A0-A14

M48T35AV

DQ0-DQ7

VSS

AI02797B

Doc ID 6845 Rev 9 5/29

Description

Table 1.

A0-A14

DQ0-DQ7

Signal names

Figure 2.

DIP connections

Address inputs

Data inputs / outputs

Chip enable

Output enable

WRITE enable

Supply voltage

Ground

A14

A12

DQ0

DQ1

DQ2

VSS

M48T35AV

VCC

A13

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

Figure 3.

SOIC connections

A14

A12

DQ0

DQ1

DQ2

VSS

M48T35AV

VCC

A13

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

6/29 Doc ID 6845 Rev 9

M48T35AV

AI02798B

AI02799

M48T35AV

Figure 4.

Block diagram

32,768 Hz

CRYSTAL

OSCILLATOR AND

CLOCK CHAIN

POWER

LITHIUM

CELL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

VPFD

8 x 8 BiPORT

SRAM ARRAY

32,760 x 8

SRAM ARRAY

VCC VSS

Description

A0-A14

DQ0-DQ7

AI01623

Doc ID 6845 Rev 9 7/29

Operation modes M48T35AV

Note:

Figure 4 on page 7

shows, the static memory array and the quartz controlled clock oscillator of the M48T35AV are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible

BYTEWIDE™ clock information in the bytes with addresses 7FF8h-7FFFh.

The clock locations contain the year, month, date, day, hour, minute, and second in 24-hour

BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. Byte 7FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting.

The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORT™ READ/WRITE memory cells. The M48T35AV includes a clock control circuit which updates the clock bytes with current information once per second.

The information can be accessed by the user in the same manner as any other location in the static memory array.

The M48T35AV also has its own power-fail detect circuit. The control circuitry constantly monitors the single 3 V supply for an out of tolerance condition. When V

is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low V

. As V

falls below the battery backup switchover voltage (V

), the control circuitry connects the battery which maintains data and clock operation until valid power returns.

Table 2.

Mode

Deselect

WRITE

READ

Deselect

Operating modes

3.0 to 3.6 V

Deselect

to V

PFD

(min)

(1)

≤ V

(1)

X X X

See

Table 11 on page 21

for details.

X = V

or V

; V

= Battery backup switchover voltage.

W DQ0-DQ7

High Z

OUT

High Z

Power

Standby

Active

CMOS standby

Battery backup mode

The M48T35AV is in the READ mode whenever W (WRITE enable) is high and E (chip enable) is low. The unique address specified by the 15 address inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data will be available at the data I/O pins within address access time (t

AVQV

) after the last address input signal is stable, providing that the E and G access times are also satisfied.

If the E and G access times are not met, valid data will be available after the latter of the chip enable access time (t

ELQV

) or output enable access time (t

GLQV

8/29 Doc ID 6845 Rev 9

M48T35AV

Note:

Operation modes

The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are activated before t

AVQV

, the data lines will be driven to an indeterminate state until t

AVQV

. If the Address Inputs are changed while E and G remain active, output data will remain valid for output data hold time (t

AXQX

) but will go indeterminate until the next address access.

Figure 5.

READ mode AC waveforms

A0-A14 tAVAV

VALID tAVQV tELQV tAXQX tEHQZ

E tELQX tGLQV tGHQZ

G tGLQX

DQ0-DQ7 VALID

AI00925

WRITE enable (W) = High.

Table 3.

READ mode AC characteristics

M48T35AV

Symbol Parameter

(1)

–100

Min Max

AVAV t

AVQV t

ELQV t

GLQV t

ELQX

(2) t

GLQX

(2) t

EHQZ

(2) t

GHQZ

(2) t

AXQX

READ cycle time

Address valid to output valid

Chip enable low to output valid

Output enable low to output valid

Chip enable low to output transition

Output enable low to output transition

Chip enable high to output Hi-Z

Output enable high to output Hi-Z

Address transition to output transition

100

Valid for ambient operating temperature: T

= 0 to 70 °C; V

= 3.0 to 3.6 V (except where noted).

= 5 pF.

Unit

ns ns ns ns ns ns ns ns ns

Doc ID 6845 Rev 9 9/29

Operation modes M48T35AV

The M48T35AV is in the WRITE mode whenever W and E are low. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of t

EHAX

from chip enable or t

WHAX

from WRITE enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid t

DVWH

prior to the end of WRITE and remain valid for t

WHDX

afterward. G should be kept high during WRITE cycles to avoid bus contention; however, if the output bus has been activated by a low on E and G, a low on W will disable the outputs t

WLQZ

after W falls.

Figure 6.

WRITE enable controlled, WRITE mode AC waveform

A0-A14 tAVAV

VALID tAVWH tAVEL tWHAX

E tWLWH tAVWL

W tWLQZ tWHQX

DQ0-DQ7 tWHDX

DATA INPUT tDVWH

AI00926

Figure 7.

Chip enable controlled, WRITE mode AC waveforms

A0-A14 tAVEL tAVAV

VALID tAVEH tELEH

E tAVWL

W tEHDX tEHAX

DQ0-DQ7 DATA INPUT tDVEH

AI00927

10/29 Doc ID 6845 Rev 9

M48T35AV Operation modes

Table 4.

WRITE mode AC characteristics

M48T35AV

Symbol Parameter

(1)

Min Max

AVAV t

AVWL t

AVEL t

WLWH t

ELEH t

WHAX t

EHAX t

DVWH t

DVEH t

WHDX t

EHDX t

WLQZ

(2)(3) t

AVWH t

AVEH t

WHQX

(2)(3)

WRITE cycle time

Address valid to WRITE enable low

Address valid to chip enable low

WRITE enable pulse width

Chip enable low to chip enable high

WRITE enable high to address transition

Chip enable high to address transition

Input valid to WRITE enable high

Input valid to chip enable high

WRITE enable high to input transition

Chip enable high to input transition

WRITE enable low to output Hi-Z

Address valid to WRITE enable high

Address valid to chip enable high

WRITE enable high to output transition

100

Valid for ambient operating temperature: T

= 0 to 70 °C; V

= 3.0 to 3.6 V (except where noted).

= 5 pF.

If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

Unit

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Note:

With valid V

applied, the M48T35AV operates as a conventional BYTEWIDE™ static

RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when V

falls within the V

PFD

(max), V

PFD

(min) window (see

Figure 13

Table 10

, and

Table 11 on page 21

). All outputs become high impedance, and all inputs are

treated as “don't care.”

A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below V

PFD

(min), the user can be assured the memory will be in a write protected state, provided the V

fall time is not less than t

. The M48T35AV may respond to transient noise spikes on V

that reach into the deselect window during the time the device is sampling V

. Therefore, decoupling of the power supply lines is recommended.

When V

drops below V

, the control circuit switches power to the internal battery which preserves data and powers the clock. The internal button cell will maintain data in the

M48T35AV for an accumulated period of at least 7 years when V

CC system power returns and V

rises above V

is less than V

. As

, the battery is disconnected and the power supply is switched to external V

. Write protection continues until V

reaches V

PFD

(min) plus t rec

(min). E should be kept high as V

rises past V

PFD

(min) to prevent inadvertent

WRITE cycles prior to processor stabilization. Normal RAM operation can resume t rec

after

exceeds V

PFD

(max).

Doc ID 6845 Rev 9 11/29

Operation modes M48T35AV

Also, as V

rises, the battery voltage is checked. If the voltage is less than approximately

2.5 V, an internal battery not OK (BOK) flag will be set. The BOK flag can be checked after power up. If the BOK flag is set, the first WRITE attempted will be blocked. The flag is

automatically cleared after the first WRITE, and normal RAM operation resumes.

Figure 8

illustrates how a BOK check routine could be structured.

For more information on battery storage life refer to the application note AN1012.

Figure 8.

Checking the BOK flag status

POWER-UP

READ DATA

AT ANY ADDRESS

WRITE DATA

COMPLEMENT BACK

TO SAME ADDRESS

READ DATA

AT SAME

ADDRESS AGAIN

IS DATA

COMPLEMENT

OF FIRST

READ?

(BATTERY OK) YES

NO (BATTERY LOW)

NOTIFY SYSTEM

OF LOW BATTERY

(DATA MAY BE

CORRUPTED)

WRITE ORIGINAL

DATA BACK TO

SAME ADDRESS

CONTINUE

AI00607

12/29 Doc ID 6845 Rev 9

M48T35AV Clock operations

3.1

3.2

3.3 Reading the clock

Updates to the TIMEKEEPER

registers (see

Table 5

) should be halted before clock data is read to prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself.

Updating is halted when a '1' is written to the READ bit, D6 in the control register 7FF8h. As long as a '1' remains in that position, updating is halted.

After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued.

All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a '0.'

Setting the clock

Bit D7 of the control register 7FF8h is the WRITE bit. Setting the WRITE bit to a '1,' like the

READ bit, halts updates to the TIMEKEEPER

registers. The user can then load them with

the correct day, date, and time data in 24-hour BCD format (see

Table 5

). Resetting the

WRITE bit to a '0' then transfers the values of all time registers 7FF9h-7FFFh to the actual

TIMEKEEPER counters and allows normal operation to resume. The FT bit and the bits

marked as '0' in

Table 5

must be written to '0' to allow for normal TIMEKEEPER and RAM

operation. After the WRITE bit is reset, the next clock update will occur within one second.

See the application note AN923, “TIMEKEEPER

rolling into the 21 st

century” for information on century rollover.

Stopping and starting the oscillator

The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP bit is the MSB of the seconds register. Setting it to a '1' stops the oscillator. The M48T35AV is shipped from STMicroelectronics with the STOP bit set to a '1.'

When reset to a '0,' the M48T35AV oscillator starts within 1 second.

Doc ID 6845 Rev 9 13/29

Clock operations

Note:

M48T35AV

Table 5.

Address

7FFFh

7FFEh

7FFDh

7FFCh

7FFBh

7FFAh

7FF9h

7FF8h

Register map

D7 D6 D5 D4

10 years

0 0 10 M.

0 10 date

FT CEB CB

0 10 hours

10 minutes

10 seconds

R S

Data

Function/range

BCD format

D3 D2 D1 D0

Year

Month

Date

Day

Hours

Minutes

Seconds

Year

Month

Date

Century/day

Hours

Minutes

Seconds

Calibration Control

00-99

01-12

01-31

00-01/01-07

00-23

00-59

Keys:

S = SIGN bit

FT = FREQUENCY TEST bit (must be set to '0' upon power for normal operation)

R = READ bit

W = WRITE bit

ST = STOP bit

0 = Must be set to '0'

CEB = CENTURY ENABLE bit

CB = CENTURY bit

When CEB is set to '1,' CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century

(dependent upon the initial value set).

When CEB is set to '0,' CB will not toggle. The WRITE bit does not need to be set to write to

CEB.

3.4 Calibrating the clock

The M48T35AV is driven by a quartz-controlled oscillator with a nominal frequency of

32,768 Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25°C, which equates to about ±1.53 minutes per month. With the calibration bits properly set, the accuracy of each M48T35AV improves to better than

+1/–2 ppm at 25°C.

The oscillation rate of any crystal changes with temperature (see

Figure 9 on page 16

Most clock chips compensate for crystal frequency and temperature shift error with cumbersome “trim” capacitors. The M48T35AV design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in

Figure 10 on page 16

. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the control register. Adding counts speeds the clock up, subtracting counts slows the clock down.

The calibration byte occupies the five lower order bits (D4-D0) in the control register 7FF8h.

These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is the

SIGN bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration

14/29 Doc ID 6845 Rev 9

M48T35AV

Note:

Clock operations

occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on.

Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –

2.75 minutes per month.

Two methods are available for ascertaining how much calibration a given M48T35AV may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure.

The second approach is better suited to a manufacturing environment, and involves the use of some test equipment. When the FREQUENCY TEST (FT) bit, the seventh-most significant bit in the day register is set to a '1,' and D7 of the seconds register is a '0'

(oscillator running), DQ0 will toggle at 512 Hz during a READ of the seconds register. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a –10 (WR001010) to be loaded into the calibration byte for correction.

Setting or changing the calibration byte does not affect the frequency test output frequency.

The FT bit MUST be reset to '0' for normal clock operations to resume. The FT bit is automatically reset on power-down.

For more information on calibration, see application note AN934, “TIMEKEEPER

Calibration.”

Note:

Bit D5 and D4 of clock register 7FFCh contain the CENTURY ENABLE bit (CEB) and the

CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'

CB will not toggle.

The WRITE bit must be set in order to write to the CENTURY bit.

Doc ID 6845 Rev 9 15/29

Clock operations

Figure 9.

Crystal accuracy across temperature

ppm

-20

-40

-60

-80

ΔF

= -0.038

ppm

(T - T

)

2 ± 10%

= 25

°C

M48T35AV

-100

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70

°C

AI02124

Figure 10.

Clock calibration

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

AI00594B

16/29 Doc ID 6845 Rev 9

M48T35AV Clock operations

3.6 V

noise and negative going transients

transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the V

bus. These transients can be reduced if capacitors are used to store energy which stabilizes the V

bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A bypass capacitor value of 0.1 µF (as shown in

Figure 11

) is recommended in order to provide the needed filtering.

In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on V

that drive it to values below V

by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a

Schottky diode from V

to V

(cathode connected to V

, anode to V

). Schottky diode

1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount.

Figure 11.

Supply voltage protection

VCC

0.1µF DEVICE

VSS

AI02169

Doc ID 6845 Rev 9 17/29

Maximum ratings M48T35AV

Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 6.

Symbol

Absolute maximum ratings

Parameter Value Unit

STG

SLD

(1)(2)(3)

Ambient operating temperature

Storage temperature (V

off, oscillator off)

Lead solder temperature for 10 seconds

Input or output voltages

Supply voltage

Output current

Power dissipation

0 to 70

–40 to 85

260

–0.3 to 4.6

°C

V mA

For DIP package, soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds.

Furthermore, the devices shall not be exposed to IR reflow nor preheat cycles (as performed as part of wave soldering). ST recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries.

For DIP packaged devices, ultrasonic vibrations should not be used for post-solder cleaning to avoid damaging the crystal.

For SOH28 package, lead-free (Pb-free) lead finish: reflow at peak temperature of 260 °C (the time above

255 °C must not exceed 30 seconds).

Caution:

Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup mode.

Caution:

Do NOT wave solder SOIC to avoid damaging SNAPHAT

sockets.

18/29 Doc ID 6845 Rev 9

M48T35AV

5 DC and AC parameters

Note:

DC and AC parameters

This section summarizes the operating and measurement conditions, as well as the DC and

AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.

Table 7.

Operating and AC measurement conditions

Parameter M48T35AV

Supply voltage (V

)

Ambient operating temperature (T

)

Load capacitance (C

)

Input rise and fall times

Input pulse voltages

Input and output timing ref. voltages

3.0 to 3.6

0 to 70

≤ 5

0 to 3

1.5

Output Hi-Z is defined as the point where data is no longer driven.

Figure 12.

AC measurement load circuit

Unit

°C pF ns

DEVICE

UNDER

TEST

CL = 50pF

(or 5pF)

1.75V

CL includes JIG capacitance

Table 8.

Symbol

Capacitance

Parameter

(1)(2)

Min Max

OUT

(3)

Input capacitance

Output capacitance

Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested.

At 25 °C, f = 1 MHz.

Outputs deselected.

Unit

pF pF

AI02586

Doc ID 6845 Rev 9 19/29

DC and AC parameters

Table 9.

DC characteristics

M48T35AV

Symbol Parameter Test condition

(1)

Min

(2)

CC1

CC2

(3)

Input leakage current

Output leakage current

Supply current

Supply current (standby) TTL

Supply current (standby) CMOS

Input low voltage

Input high voltage

Output low voltage

Output high voltage

0 V

≤ V

0 V

≤ V

OUT

≤ V

Outputs open

E = V

– 0.2 V

= 2.1 mA

= –1 mA

–0.3

2.2

2.4

Valid for ambient operating temperature: T

= 0 to 70 °C; V

= 3.0 to 3.6 V (except where noted).

Outputs deselected.

Negative spikes of –1 V allowed for up to 10 ns once per cycle.

Max

±1

0.8

+ 0.3

0.4

Figure 13.

Power down/up mode AC waveforms

M48T35AV

Unit

µA

µA mA mA mA

VCC

VPFD (max)

VPFD (min)

VSO

INPUTS tPD tF

RECOGNIZED tFB tDR tRB

DON'T CARE

HIGH-Z tR trec

RECOGNIZED

OUTPUTS VALID

(PER CONTROL INPUT)

VALID

(PER CONTROL INPUT)

AI01168C

20/29 Doc ID 6845 Rev 9

M48T35AV DC and AC parameters

Table 10.

Power down/up AC characteristics

Symbol Parameter

(1)

Min Max Unit

PD t

(2) t

(3) t t t

RB rec

E or W at V

PFD

before power down

(max) to V

PFD

(min) to V

(min) V

fall time

PFD

(min) to V

PFD

(max) V

rise time

to V

PFD

(min) V

rise time

PFD

(max) to inputs recognized

300

150

40 200

µs

µs ms

Valid for ambient operating temperature: T

A noted).

= 0 to 70 °C or –40 to 85 °C; V

= 4.5 to 5.5 V or 3.0 to 3.6 V (except where

PFD

(max) to V

PFD

passes V

PFD

(min) fall time of less than t

may result in deselection/write protection not occurring until 200 µs after

(min).

PFD

(min) to V

fall time of less than t

may cause corruption of RAM data.

Table 11.

Power down/up trip points DC characteristics

Symbol Parameter

(1)(2)

Min Typ Max Unit

PFD

SO t

(3)

Power-fail deselect voltage

Battery backup switchover voltage

Expected data retention time

2.7

(4)

PFD

2.9

–100mV

3.0

Years

Valid for ambient operating temperature: T

A noted).

= 0 to 70 °C or –40 to 85 °C; V

= 4.5 to 5.5 V or 3.0 to 3.6 V (except where

All voltages referenced to V

At 25 °C, V

= 0 V.

CAPHAT™ and M4T32-BR12SH1 SNAPHAT

only, M4T28-BR12SH1 SNAPHAT

top t

= 7 years (typ).

Doc ID 6845 Rev 9 21/29

Package mechanical data

6 Package mechanical data

M48T35AV

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at:

www.st.com

ECOPACK

is an ST trademark.

Figure 14.

PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline

Note:

A2 A

A1 e1

L C

B1 e3

D eA

PCDIP

Drawing is not to scale.

Table 12.

PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, pack. mech. data mm inches

Symb

Typ Min Max Typ Min Max

e3 eA

E e1

33.02

8.89

0.38

8.38

0.38

1.14

0.20

39.37

17.83

2.29

15.24

3.05

9.65

0.76

8.89

0.53

1.78

0.31

39.88

18.34

2.79

16.00

3.81

1.3

0.350

0.015

0.330

0.015

0.045

0.008

1.550

0.702

0.090

0.600

0.120

0.380

0.030

0.350

0.021

0.070

0.012

1.570

0.722

0.110

0.630

0.150

22/29 Doc ID 6845 Rev 9

M48T35AV Package mechanical data

Figure 15.

SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT

, package outline

A2 A

C eB

B e

Note:

E H

SOH-A

Drawing is not to scale.

CP e eB

Table 13.

SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT

, pack. mech. data mm inches

Symb

Typ Min Max Typ Min Max

1.27

0.05

2.34

0.36

0.15

17.71

8.23

–

3.20

11.51

0.41

0°

3.05

0.36

2.69

0.51

0.32

18.49

8.89

–

3.61

12.70

1.27

8°

0.050

0.002

0.092

0.014

0.006

0.697

0.324

–

0.126

0.453

0.016

0°

0.120

0.014

0.106

0.020

0.012

0.728

0.350

–

0.142

0.500

0.050

8°

0.10

0.004

Doc ID 6845 Rev 9 23/29

Package mechanical data M48T35AV

Figure 16.

SH – 4-pin SNAPHAT

housing for 48 mAh battery & crystal, pack. outline

B eB

Note:

SHTK-A

Drawing is not to scale.

Table 14.

SH – 4-pin SNAPHAT

housing for 48 mAh battery & crystal, pack. mech. data mm inches

Symb

Typ Min Max Typ Min Max

E eA

A3 eB

6.73

6.48

0.46

21.21

14.22

15.55

3.20

2.03

9.78

7.24

6.99

0.38

0.56

21.84

14.99

15.95

3.61

2.29

0.265

0.255

0.018

0.835

0.560

0.612

0.126

0.080

0.385

0.285

0.275

0.015

0.022

0.860

0.590

0.628

0.142

0.090

24/29 Doc ID 6845 Rev 9

M48T35AV Package mechanical data

Figure 17.

SH – 4-pin SNAPHAT

housing for 120 mAh battery & crystal, pack. outline

B eB

Note:

SHTK-A

Drawing is not to scale.

Table 15.

SH – 4-pin SNAPHAT

housing for 120 mAh battery & crystal, pack. mech. data mm inches

Symb

Typ Min Max Typ Min Max

E eA

A3 eB

8.00

7.24

0.46

21.21

17.27

15.55

3.20

2.03

10.54

8.51

8.00

0.38

0.56

21.84

18.03

15.95

3.61

2.29

0.315

0.285

0.018

0.835

0.680

0.612

0.126

0.080

0.415

0.335

0.315

0.015

0.022

0.860

0.710

0.628

0.142

0.090

Doc ID 6845 Rev 9 25/29

Part numbering M48T35AV

Table 16.

Ordering information scheme

Example:

M48T 35AV –10 MH 1 E

Device type

M48T

Supply voltage and write protect voltage

35AV = V

= 3.0 to 3.6 V; V

PFD

= 2.7 to 3.0 V

Speed

–10 = 100 ns (35AV)

Package

PC = PCDIP28

(1)

= SOH28

Temperature range

1 = 0 to 70°C

Shipping method

For SOH28:

E = Lead-free package (ECOPACK

), tubes

F = Lead-free package (ECOPACK

), tape & reel

For PCDIP28:

blank = tubes

The SOIC package (SOH28) requires the SNAPHAT

battery package which is ordered separately under

the part number “M4TXX-BR12SHx” in plastic tubes (see

Table 17

Caution:

Do not place the SNAPHAT

battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell battery.

For other options, or for more information on any aspect of this device, please contact the

ST sales office nearest you.

Table 17.

SNAPHAT

battery table

Part number

M4T28-BR12SH1

M4T32-BR12SH1

M4T32-BR12SH6

Description

Lithium battery (48 mAh) SNAPHAT

Lithium battery (120 mAh) SNAPHAT

, –40 to +85 °C crystal

Package

26/29 Doc ID 6845 Rev 9

M48T35AV

Figure 18.

Recycling symbols

Environmental information

This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product.

Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations.

Doc ID 6845 Rev 9 27/29

Revision history M48T35AV

Table 18.

Document revision history

Date

Nov-1999

21-Apr-2000

29-May-2000

20-Jul-2001

20-May-2002

31-Mar-2003

01-Apr-2004

21-Nov-2007

23-Mar-2009

21-Oct-2010

24-Jun-2011

Revision

2.1

3.1

Changes

First issue

From preliminary data to datasheet t

change (

Table 10

)

Reformatted; temp./voltage info. added to tables (

Table 8

); add century bit text

Modify reflow time and temperature footnotes (

Table 6

) v2.2 template applied; data retention condition updated (

Table 11

)

Reformatted; updated with lead-free package information (

Table 6

)

Reformatted document; added lead-free second level interconnect information to cover page and

Section 6: Package mechanical data

updated

Table 16

; removed M48T35AY and all references.

Updated

Table 6

Section 6: Package mechanical data

; added

Section 8: Environmental information

; minor formatting changes.

Updated

Section 4

Table 12

; reformatted document.

Updated footnote

Table 6: Absolute maximum ratings

; updated

Features

and

Section 8: Environmental information

28/29 Doc ID 6845 Rev 9

M48T35AV

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Doc ID 6845 Rev 9 29/29

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®

Features

Contents

List of tables

List of figures

1 Description

3.1

3.2

3.3

Reading the clock

Setting the clock

Stopping and starting the oscillator

3.4 Calibrating the clock

3.6 V

noise and negative going transients

5 DC and AC parameters

6 Package mechanical data

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