STMicroelectronics M48T58 Datasheet
Below you will find brief information for M48T58 TIMEKEEPER SRAM, M48T58Y TIMEKEEPER SRAM. These devices integrate SRAM, real-time clock, power-fail control, and battery, offering BYTEWIDE clock access and BCD coded timekeeping. Key features encompass automatic power-fail protection and compatibility with JEDEC standard SRAMs. The device ensures data retention and clock functionality upon power loss.
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M48T58
M48T58Y
5.0 V, 64 Kbit (8 Kb x 8) TIMEKEEPER
®
SRAM
Features
■
■
■
■
■
■
■
■
■
■
■
Integrated, ultra low power SRAM, real-time clock, power-fail control circuit and battery
BYTEWIDE
™
RAM-like clock access
BCD coded year, month, day, date, hours, minutes, and seconds
Frequency test output for real-time clock
Automatic power-fail chip deselect and WRITE protection
WRITE protect voltages
(V
PFD
= power-fail deselect voltage):
– M48T58: V
CC
4.5 V
≤ V
PFD
= 4.75 to 5.5 V;
≤ 4.75 V
– M48T58Y: V
CC
4.2 V
≤ V
PFD
= 4.5 to 5.5 V;
≤ 4.5 V
Self-contained battery and crystal in the
CAPHAT
™
DIP package
Packaging includes a 28-lead SOIC and
SNAPHAT
® top (to be ordered separately)
SOIC package provides direct connection for a snaphat housing containing the battery and crystal
Pin and function compatible with JEDEC standard 8 Kb x 8 SRAMs
RoHS compliant
– Lead-free second level interconnect
28
1
PCDIP28
Battery/crystal
CAPHAT™
SNAPHAT
®
Battery/crystal
28
1
SOH28
June 2011 Doc ID 2412 Rev 8 1/33
www.st.com
1
Contents
Contents
M48T58, M48T58Y
Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CC
noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/33 Doc ID 2412 Rev 8
M48T58, M48T58Y
List of tables
List of tables
PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package mech. data . . . . . . . . . . . . . 25
SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT
, package mech. data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
housing for 48 mAh battery & crystal, package mech. data . . . . . 27
housing for 120 mAh battery & crystal, package mech. data . . . . 28
battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Doc ID 2412 Rev 8 3/33
List of figures
List of figures
M48T58, M48T58Y
PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline . . . . . . . . . . . . . . . . . 25
SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT
, package outline . . . 26
housing for 48 mAh battery & crystal, pack. outline . . . . . . . . . . . 27
housing for 120 mAh battery & crystal, package outline. . . . . . . . 28
4/33 Doc ID 2412 Rev 8
M48T58, M48T58Y
1 Description
Description
The M48T58/Y TIMEKEEPER
®
RAM is a 8 Kb x 8 non-volatile static RAM and real-time clock. The monolithic chip is available in two special packages to provide a highly integrated battery-backed memory and real-time clock solution.
The M48T58/Y is a non-volatile pin and function equivalent to any JEDEC standard
8b Kb x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed.
The 28-pin, 600 mil DIP CAPHAT
™
houses the M48T58/Y silicon with a quartz crystal and a long life lithium button cell in a single package.
The 28-pin, 330 mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT
®
housing containing the battery and crystal. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in tape & reel form.
For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is “M4T28-
BR12SH”.
Figure 1.
Logic diagram
VCC
A0-A12
13
W
E1
E2
G
M48T58
M48T58Y
8
DQ0-DQ7
FT
VSS
AI01374B
Doc ID 2412 Rev 8 5/33
Description
Table 1.
Signal names
A0-A12 Address inputs
DQ0-DQ7
FT
E1
E2
G
W
V
CC
V
SS
Data inputs / outputs
Frequency test output (open drain)
Chip enable 1
Chip enable 2
Output enable
WRITE enable
Supply voltage
Ground
Figure 2.
DIP connections
FT
A12
A7
DQ0
DQ1
DQ2
VSS
A6
A5
A4
A3
A2
A1
A0
6
7
8
4
5
9
10
1
2
3
11
12
13
14
M48T58
M48T58Y
21
20
19
25
24
23
22
28
27
26
18
17
16
15
VCC
W
E2
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5
DQ4
DQ3
Figure 3.
SOIC connections
FT
A12
DQ0
DQ1
DQ2
VSS
A7
A6
A5
A4
A3
A2
A1
A0
1
2
7
8
9
10
5
6
3
4
11
12
13
14
M48T58Y
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W
E2
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5
DQ4
DQ3
6/33 Doc ID 2412 Rev 8
M48T58, M48T58Y
AI01375B
AI01376B
M48T58, M48T58Y
Figure 4.
Block diagram
FT
OSCILLATOR AND
CLOCK CHAIN
32,768 Hz
CRYSTAL
POWER
LITHIUM
CELL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
VPFD
8 x 8 BiPORT
SRAM ARRAY
8184 x 8
SRAM ARRAY
VCC VSS
Description
A0-A12
DQ0-DQ7
E1
E2
W
G
AI01377C
Doc ID 2412 Rev 8 7/33
Operation modes M48T58, M48T58Y
Note:
As
shows, the static memory array and the quartz controlled clock oscillator of the M48T58/Y are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with addresses 1FF8h-1FFFh. The clock locations contain the century, year, month, date, day, hour, minute, and second in 24 hour
BCD format (except for the century). Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. Byte 1FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting.
The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORT™ READ/write memory cells. The M48T58/Y includes a clock control circuit which updates the clock bytes with current information once per second.
The information can be accessed by the user in the same manner as any other location in the static memory array.
The M48T58/Y also has its own power-fail detect circuit. The control circuitry constantly monitors the single 5 V supply for an out-of-tolerance condition. When V
CC
is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low V
CC
. As V
CC
falls below the battery backup switchover voltage (V
SO
), the control circuitry connects the battery which maintains data and clock operation until valid power returns.
Table 2.
Operating modes
Mode V
CC
E1
Deselect
Deselect
READ
READ
V
IH
X
WRITE
4.75 to 5.5 V or
4.5 to 5.5 V
V
IL
V
IL
V
IL
Deselect
Deselect
V
SO
to V
(min)
PFD
(1)
≤ V
SO
(1)
X
X
1.
See
E2
X
V
IL
V
IH
V
IH
V
IH
X
X
G
X
X
X
V
IL
V
IH
X
X
W
X
X
V
IL
V
IH
V
IH
X
X
X = V
IH
or V
IL
; V
SO
= Battery backup switchover voltage.
DQ0-DQ7
High Z
High Z
D
IN
D
OUT
High Z
High Z
High Z
Power
Standby
Standby
Active
Active
Active
CMOS standby
Battery backup mode
8/33 Doc ID 2412 Rev 8
M48T58, M48T58Y READ mode
The M48T58/Y is in the READ mode whenever W (WRITE enable) is high, E1 (chip enable
1) is low, and E2 (chip enable 2) is high. The unique address specified by the 13 address inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be available at the data I/O pins within address access time (t
AVQV
) after the last address input signal is stable, providing that the E1, E2, and G access times are also satisfied. If the E1,
E2 and G access times are not met, valid data will be available after the latter of the chip enable access times (t
E1LQV
or t
E2HQV
) or output enable access time (t
GLQV
).
The state of the eight three-state data I/O signals is controlled by E1, E2 and G. If the outputs are activated before t
AVQV
, the data lines will be driven to an indeterminate state until t
AVQV
. If the address inputs are changed while E1, E2 and G remain active, output data will remain valid for output data hold time (t
AXQX
) but will go indeterminate until the next address access.
Figure 5.
READ mode AC waveforms
A0-A12 tAVAV
VALID tAVQV tE1LQV tAXQX tE1HQZ
E1 tE1LQX tE2HQV tE2LQZ
E2 tE2HQX tGLQV tGHQZ
G tGLQX
DQ0-DQ7 VALID
AI00962
Note: WRITE enable (W) = high.
Doc ID 2412 Rev 8 9/33
READ mode M48T58, M48T58Y
Table 3.
READ mode AC characteristics
M48T58/Y
Symbol Parameter
(1)
Unit
Min Max
t
AVAV t
AVQV t
E1LQV t
E2HQV t
GLQV t
E1LQX
(2) t
E2HQX
(2) t
GLQX
(2) t
E1HQZ
(2) t
E2LQZ
(2) t
GHQZ
(2) t
AXQX
READ cycle time
Address valid to output valid
Chip enable 1 low to output valid
Chip enable 2 high to output valid
Output enable low to output valid
Chip enable 1 low to output transition
Chip enable 2 high to output transition
Output enable low to output transition
Chip enable 1 high to output Hi-Z
Chip enable 2 low to output Hi-Z
Output enable high to output Hi-Z
Address transition to output transition
70
5
5
5
10
70
70
70
35
25
25
25 ns ns ns ns ns ns ns ns ns ns ns ns
1.
Valid for ambient operating temperature: T
A noted).
= 0 to 70 °C; V
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where
2.
C
L
= 5 pF.
10/33 Doc ID 2412 Rev 8
M48T58, M48T58Y WRITE mode
The M48T58/Y is in the WRITE mode whenever W and E1 are low and E2 is high. The start of a WRITE is referenced from the latter occurring falling edge of W or E1, or the rising edge of E2. A WRITE is terminated by the earlier rising edge of W or E1, or the falling edge of E2.
The addresses must be held valid throughout the cycle. E1 or W must return high or E2 low for a minimum of t
E1HAX
or t
E2LAX
from chip enable or t
WHAX
from WRITE enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid t
DVWH
prior to the end of
WRITE and remain valid for t
WHDX
afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E1 and G and a high on E2, a low on W will disable the outputs t
WLQZ
after W falls.
Figure 6.
WRITE enable controlled, WRITE AC waveform
A0-A12 tAVAV
VALID tAVWH tAVE1L tWHAX
E1 tAVE2H
E2 tWLWH tAVWL
W tWLQZ tWHQX
DQ0-DQ7 tWHDX
DATA INPUT tDVWH
AI00963
Doc ID 2412 Rev 8 11/33
WRITE mode
Figure 7.
Chip enable controlled, WRITE AC waveforms
A0-A12 tAVE1L tAVAV
VALID tAVE1H tE1LE1H
E1 tAVE2H tAVE2L tE2HE2L
E2 tAVWL
W
DQ0-DQ7 DATA INPUT tDVE1H tDVE2L tE1HDX tE2LDX
M48T58, M48T58Y
tE1HAX tE2LAX
AI00964B
12/33 Doc ID 2412 Rev 8
M48T58, M48T58Y WRITE mode
Table 4.
WRITE mode AC characteristics
M48T58/Y
Symbol Parameter
(1)
Unit
Min Max
t
AVAV t
AVWL t
AVE1L t
AVE2H t
WLWH t
E1LE1H t
E2HE2L t
WHAX t
E1HAX t
E2LAX t
DVWH t
DVE1H t
DVE2L t
WHDX t
E1HDX t
E2LDX t
WLQZ
(2)(3) t
AVWH t
AVE1H t
AVE2L t
WHQX
(2)(3)
WRITE cycle time
Address valid to WRITE enable low
Address valid to chip enable 1 low
Address valid to chip enable 2 high
WRITE enable pulse width
Chip enable 1 low to chip enable 1 high
Chip enable 2 high to chip enable 2 low
WRITE enable high to address transition
Chip enable 1 high to address transition
Chip enable 2 low to address transition
Input valid to WRITE enable high
Input valid to chip enable 1 high
Input valid to chip enable 2 low
WRITE enable high to input transition
Chip enable 1 high to input transition
Chip enable 2 low to input transition
Write enable low to output Hi-Z
Address valid to WRITE enable high
Address valid to chip enable 1 high
Address valid to chip enable 2 low
WRITE enable high to output transition
70
0
0
0
50
55
55
0
0
0
30
30
30
5
5
5
60
60
60
5
25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1.
Valid for ambient operating temperature: T
A noted).
= 0 to 70 °C; V
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where
2.
C
L
= 5 pF.
3.
If E1 goes low or E2 high simultaneously with W going low, the outputs remain in the high impedance state.
Doc ID 2412 Rev 8 13/33
Data retention mode
5 Data retention mode
Note:
M48T58, M48T58Y
With valid V
CC
applied, the M48T58/Y operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when V
CC
falls within the V
PFD
(max), V
PFD
(min) window. All outputs become high impedance, and all inputs are treated as “don't care.”
A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below V
PFD
(min), the user can be assured the memory will be in a write protected state, provided the V
CC
fall time is not less than t
F
. The M48T58/Y may respond to transient noise spikes on V
CC
that reach into the deselect window during the time the device is sampling V
CC
. Therefore, decoupling of the power supply lines is recommended.
When V
CC
drops below V
SO
, the control circuit switches power to the internal battery which preserves data and powers the clock. The internal button cell will maintain data in the
M48T58/Y for an accumulated period of at least 7 years when V
CC
is less than V
SO
. As system power returns and V
CC
rises above V
SO
, the battery is disconnected, and the power supply is switched to external V
CC
. Write protection continues until V
CC
reaches V
PFD
(min) plus t rec
(min). E1 should be kept high or E2 low as V
CC
rises past V
PFD
(min) to prevent inadvertent WRITE cycles prior to system stabilization. Normal RAM operation can resume t rec
after V
CC
exceeds V
PFD
(max).
For more information on battery storage life refer to the application note AN1012.
14/33 Doc ID 2412 Rev 8
M48T58, M48T58Y Clock operations
6.1
6.2
6.3
Reading the clock
Updates to the TIMEKEEPER
®
registers (see
) should be halted before clock data is read to prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself.
Updating is halted when a '1' is written to the READ bit, D6 in the control register 1FF8h. As long as a '1' remains in that position, updating is halted.
After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a '0.'
Setting the clock
Bit D7 of the control register (1FF8h) is the WRITE bit. Setting the WRITE bit to a '1,' like the
READ bit, halts updates to the TIMEKEEPER
®
registers. The user can then load them with
the correct day, date, and time data in 24-hour BCD format (see
). Resetting the
WRITE bit to a '0' then transfers the values of all time registers (1FF9h-1FFFh) to the actual
TIMEKEEPER counters and allows normal operation to resume. The bits marked as '0' in
must be written to '0' to allow for normal TIMEKEEPER and RAM operation. After the WRITE bit is reset, the next clock update will occur within one second.
See the application note AN923 “TIMEKEEPER Rolling Into the 21st Century” for information on century rollover.
Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP bit is the MSB of the seconds register. Setting it to a '1' stops the oscillator. The M48T58/Y is shipped from STMicroelectronics with the STOP bit set to a '1.'
When reset to a '0,' the M48T58/Y oscillator starts within 1 second.
Doc ID 2412 Rev 8 15/33
Clock operations
Note:
M48T58, M48T58Y
Table 5.
Address
1FFFh
1FFEh
1FFDh
1FFCh
1FFBh
1FFAh
1FF9h
1FF8h
Register map
D7 D6 D5 D4
0
10 Years
0
BLE BL
0 10 M
10 date
0
0
0
ST
W
FT
0
R
CEB
10 minutes
10 seconds
CB
10 hours
S
Data
Function/range
BCD format
D3 D2 D1 D0
0
Year
Month
Date
Day
Hours
Minutes
Seconds
Year
Month
Date
Century/day
Hours
Minutes
Seconds
Calibration Control
00-99
01-12
01-31
0-1/1-7
00-23
00-59
00-59
Keys:
S = SIGN bit
FT = FREQUENCY TEST bit
R = READ bit
W = WRITE bit
ST = STOP bit
0 = Must be set to '0'
BLE = Battery low enable bit
BL = Battery low bit (read only)
CEB = Century enable bit
CB = Century bit
When CEB is set to '1,' CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century
(dependent upon the initial value set).
When CEB is set to '0,' CB will not toggle. The WRITE bit does not need to be set to write to
CEB.
6.4
16/33
Calibrating the clock
The M48T58/Y is driven by a quartz-controlled oscillator with a nominal frequency of 32,768
Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25°C, which equates to about ±1.53 minutes per month. With the calibration bits properly set, the accuracy of each M48T58/Y improves to better than +1/–2 ppm at 25°C.
The oscillation rate of any crystal changes with temperature (see
).
Most clock chips compensate for crystal frequency and temperature shift error with cumbersome “trim” capacitors. The M48T58/Y design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in
are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the control register. Adding counts speeds the clock up, subtracting counts slows the clock down.
The calibration byte occupies the five lower order bits (D4-D0) in the control register 1FF8h.
These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is the
Doc ID 2412 Rev 8
M48T58, M48T58Y Clock operations
sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –
2.75 minutes per month.
Two methods are available for ascertaining how much calibration a given M48T58/Y may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accesses the calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use of some test equipment. When the frequency test (FT) bit (D6 in the day register) is set to a
'1,' and D7 of the seconds register is a '0' (oscillator running), The frequency test (pin 1) will toggle at 512 Hz. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a –10 (WR001010) to be loaded into the calibration byte for correction.
The frequency test pin is an open drain output which requires a pull-up resistor for proper operation. A 500-10 k
Ω resistor is recommended in order to control the rise time.
For more information on calibration, see application note AN934, “TIMEKEEPER
® calibration.”
Doc ID 2412 Rev 8 17/33
Clock operations
Figure 8.
Crystal accuracy across temperature
ppm
20
M48T58, M48T58Y
0
-20
-40
-60
-80
ΔF
F
= -0.038
ppm
C
2
(T - T
0
)
2 ± 10%
T
0
= 25
°C
-100
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
°C
AI02124
Figure 9.
Clock calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
18/33 Doc ID 2412 Rev 8
M48T58, M48T58Y
6.5
Note:
Note:
Clock operations
Battery low flag
The M48T58/Y automatically performs periodic battery voltage monitoring upon power-up.
The battery low flag (BL), bit D6 of the flags register 1FFDh, will be asserted high if the internal or SNAPHAT
®
battery is found to be less than approximately 2.5 V and the battery low enable (BLE) bit has been previously set to '1.' The BL flag will remain active until completion of battery replacement and subsequent battery low monitoring tests.
If a battery low is generated during a power-up sequence, this indicates that the battery voltage is below 2.5 V (approximately), which may be insufficient to maintain data integrity.
Data should be considered suspect and verified as correct. A fresh battery should be installed.
The SNAPHAT top may be replaced while V
CC
is applied to the device.
This will cause the clock to lose time during the interval the SNAPHAT
®
battery/crystal top is disconnected.
Battery monitoring is a useful technique only when performed periodically. The M48T58/Y only monitors the battery when a nominal V
CC
is applied to the device. Thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial.
Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique.
Note:
Bit D5 and D4 of clock register 1FFCh contain the CENTURY ENABLE bit (CEB) and the
CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'
CB will not toggle.
The WRITE bit must be set in order to write to the CENTURY bit.
Doc ID 2412 Rev 8 19/33
Clock operations M48T58, M48T58Y
6.7 V
CC
noise and negative going transients
I
CC
transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the V
CC
bus. These transients can be reduced if capacitors are used to store energy which stabilizes the V
CC
bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A bypass capacitor value of 0.1 µF (as shown in
) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on V
CC
that drive it to values below V
SS
by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a
Schottky diode from V
CC
to V
SS
(cathode connected to V
CC
, anode to V
SS
). Schottky diode
1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount.
Figure 10.
Supply voltage protection
VCC
VCC
0.1µF DEVICE
VSS
AI02169
20/33 Doc ID 2412 Rev 8
M48T58, M48T58Y Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 6.
Symbol
Absolute maximum ratings
Parameter Value Unit
T
A
T
STG
T
SLD
(1)(2)(3)
V
IO
V
CC
I
O
P
D
Ambient operating temperature
Storage temperature (V
CC
off, oscillator off)
Lead solder temperature for 10 seconds
Input or output voltages
Supply voltage
Output current
Power dissipation
0 to 70
–40 to 85
260
–0.3 to 7
–0.3 to 7
20
1
°C
°C
°C
V
V mA
W
1.
For DIP package, soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds.
Furthermore, the devices shall not be exposed to IR reflow nor preheat cycles (as performed as part of wave soldering). ST recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries.
2.
For DIP packaged devices, ultrasonic vibrations should not be used for post-solder cleaning to avoid damaging the crystal.
3.
For SOH28 package, lead-free (Pb-free) lead finish: reflow at peak temperature of 260°C (the time above
255°C must not exceed 30 seconds).
Caution:
Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup mode.
Caution:
Do NOT wave solder SOIC to avoid damaging SNAPHAT
® sockets.
Doc ID 2412 Rev 8 21/33
DC and AC parameters
8 DC and AC parameters
Note:
M48T58, M48T58Y
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in
Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 7.
Operating and AC measurement conditions
Parameter
Supply voltage (V
CC
)
Ambient operating temperature (T
A
)
Load capacitance (C
L
)
Input rise and fall times
Input pulse voltages
Input and output timing ref. voltages
M48T58
4.75 to 5.5
0 to 70
100
≤ 5
0 to 3
1.5
M48T58Y
4.5 to 5.5
0 to 70
100
≤ 5
0 to 3
1.5
Output Hi-Z is defined as the point where data is no longer driven.
Figure 11.
AC measurement load circuit
Unit
V
°C pF ns
V
V
5V
DEVICE
UNDER
TEST
1k
Ω
1.9k
Ω
OUT
CL = 100pF or 5pF
CL includes JIG capacitance
Table 8.
Symbol
Capacitance
Parameter
(1)(2)
Min Max
C
IN
C
OUT
(3)
Input capacitance
Output capacitance
-
-
10
10
1.
Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested.
2.
At 25 °C, f = 1 MHz.
3.
Outputs deselected.
Unit
pF pF
AI01030
22/33 Doc ID 2412 Rev 8
M48T58, M48T58Y DC and AC parameters
Table 9.
DC characteristics
M48T58 M48T58Y
Symbol Parameter Test condition
(1)
Unit
Min Max Min Max
I
LI
I
LO
(2)
I
CC
Input leakage current
Output leakage current
Supply current
0 V
≤ V
IN
≤ V
CC
0 V
≤ V
OUT
≤ V
CC
Outputs open
±1
±1
50
±1
±1
50
µA
µA mA
I
I
CC1
CC2
Supply current (standby) TTL
Supply current (standby)
CMOS
E1 = V
IH
E2 = V
IO
E1 = V
CC
– 0.2 V
E2 = V
SS
+ 0.2 V
3
3
3
3 mA mA
V
IL
V
V
IH
OL
V
OH
Input low voltage
Input high voltage
Output low voltage
Output low voltage (FT)
Output high voltage
(3)
I
OL
= 2.1 mA
I
OL
= 10 mA
I
OH
= –1 mA
–0.3
2.2
2.4
0.8
V
CC
+ 0.3
0.4
0.4
–0.3
2.2
2.4
V
0.8
CC
+ 0.3
0.4
0.4
1.
Valid for ambient operating temperature: T
A
= 0 to 70 °C; V
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).
2.
Outputs deselected.
3.
The FT pin is open drain.
V
V
V
V
Figure 12.
Power down/up mode AC waveforms
VCC
VPFD (max)
VPFD (min)
VSO tF tR tFB tRB
INPUTS tPD
RECOGNIZED tDR
DON'T CARE trec
RECOGNIZED
HIGH-Z
OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI01168C
Doc ID 2412 Rev 8 23/33
DC and AC parameters M48T58, M48T58Y
Table 10.
Power down/up AC characteristics
Symbol Parameter
(1)
Min Max Unit
t t t
PD
F
(2)
FB
(3)
E1 or W at V
IH
or E2 at V
IL
before power down
V
PFD
(max) to V
PFD
(min) V
CC
fall time
M48T58
V
PFD
(min) to V
SS
V
CC
fall time
M48T58Y
0
300
10
10 t
R t
RB t rec
V
PFD
(min) to V
PFD
(max) V
CC
rise time
V
SS
to V
PFD
(min) V
CC
rise time
V
PFD
(max) to inputs recognized
10
1
40 200
µs
µs ms
1.
Valid for ambient operating temperature: T
A noted).
= 0 to 70 °C; V
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where
2.
V
PFD
(max) to V
PFD until 200 µs after V
(min) fall time of less than t
F
CC
passes V
PFD
(min).
may result in deselection/write protection not occurring
3.
V
PFD
(min) to V
SS
fall time of less than t
FB
may cause corruption of RAM data.
µs
µs
µs
µs
Table 11.
Power down/up trip points DC characteristics
Symbol Parameter
(1)(2)
Min Typ Max Unit
V
PFD
Power-fail deselect voltage
M48T58
M48T58Y
4.5
4.2
4.6
4.35
4.75
4.5
V
V
V
SO t
DR
(3)
Battery backup switchover voltage
Expected data retention time 7
3.0
V
Years
1.
Valid for ambient operating temperature: T
A noted).
= 0 to 70 °C; V
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where
2.
All voltages referenced to V
SS
.
3.
At 25 °C, V
CC
= 0 V.
24/33 Doc ID 2412 Rev 8
M48T58, M48T58Y
9 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at:
www.st.com
.
ECOPACK
®
is an ST trademark.
Figure 13.
PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline
Note:
A2 A
A1 e1
L C
B1 e3
B
D eA
N
E
1
PCDIP
Drawing is not to scale.
Table 12.
PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package mech. data mm inches
Symb
Typ Min Max Typ Min Max
e3 eA
L
N
C
D
E e1
A
A1
A2
B
B1
33.02
8.89
0.38
8.38
0.38
1.14
0.20
39.37
17.83
2.29
15.24
3.05
28
9.65
0.76
8.89
0.53
1.78
0.31
39.88
18.34
2.79
16.00
3.81
1.3
0.350
0.015
0.330
0.015
0.045
0.008
1.550
0.702
0.090
0.600
0.120
28
0.380
0.030
0.350
0.021
0.070
0.012
1.570
0.722
0.110
0.630
0.150
Doc ID 2412 Rev 8 25/33
Package mechanical data M48T58, M48T58Y
Figure 14.
SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT
®
, package outline
A2 A
C
B e
CP eB
D
N
Note:
E H
A1 a
L
1
SOH-A
Drawing is not to scale.
e eB
H
L a
N
CP
A
A1
A2
B
C
D
E
Table 13.
SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT
®
, package mech. data mm inches
Symb
Typ Min Max Typ Min Max
1.27
0.05
2.34
0.36
0.15
17.71
8.23
–
3.20
11.51
0.41
0°
28
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
3.61
12.70
1.27
8°
0.050
0.002
0.092
0.014
0.006
0.697
0.324
–
0.126
0.453
0.016
0°
28
0.10
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
0.142
0.500
0.050
8°
0.004
26/33 Doc ID 2412 Rev 8
M48T58, M48T58Y Package mechanical data
Figure 15.
SH – 4-pin SNAPHAT
®
housing for 48 mAh battery & crystal, pack. outline
A1
A A3
A2 eA
D
B eB
L
E
Note:
SHTK-A
Drawing is not to scale.
Table 14.
SH – 4-pin SNAPHAT
®
housing for 48 mAh battery & crystal, package mech. data mm inches
Symb
Typ Min Max Typ Min Max
B
D
E eA
A
A1
A2
A3 eB
L
6.73
6.48
0.46
21.21
14.22
15.55
3.20
2.03
9.78
7.24
6.99
0.38
0.56
21.84
14.99
15.95
3.61
2.29
0.265
0.255
0.018
0.835
0.560
0.612
0.126
0.080
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.628
0.142
0.090
Doc ID 2412 Rev 8 27/33
Package mechanical data M48T58, M48T58Y
Figure 16.
SH – 4-pin SNAPHAT
®
housing for 120 mAh battery & crystal, package outline
A1
A A3
A2 eA
D
B eB
L
E
Note:
SHTK-A
Drawing is not to scale.
Table 15.
SH – 4-pin SNAPHAT
® housing for 120 mAh battery & crystal, package mech. data mm inches
Symb
Typ Min Max Typ Min Max
B
D
E eB
L
A
A1
A2
A3
8.00
7.24
0.46
21.21
17.27
3.20
2.03
10.54
8.51
8.00
0.38
0.56
21.84
18.03
3.61
2.29
0.315
0.285
0.018
0.835
0.680
0.126
0.080
0.415
0.335
0.315
0.015
0.022
0.860
0.710
0.142
0.090
28/33 Doc ID 2412 Rev 8
M48T58, M48T58Y Part numbering
Table 16.
Ordering information scheme
Example: M48T 58
Device type
M48T
Supply voltage and write protect voltage
58
(1)
= V
CC
= 4.75 to 5.5 V; V
PFD
= 4.5 to 4.75 V
58Y = V
CC
= 4.5 to 5.5 V; V
PFD
= 4.2 to 4.5 V
Speed
–70 = 70 ns
Package
PC = PCDIP28
MH
(2)
= SOH28
Temperature range
1 = 0 to 70°C
Shipping method
For SOH28:
blank = Tubes (not for new design - use E)
E = Lead-free package (ECOPACK
®
), tubes
F = Lead-free package (ECOPACK
®
), tape & reel
TR = Tape & reel (not for new design - use F)
For PCDIP28:
blank = Tubes
–70 MH 1 E
1.
The M48T58 part is offered with the PCDIP28 (e.g., CAPHAT™) package only.
2.
The SOIC package (SOH28) requires the SNAPHAT
®
battery package which is ordered separately under the part number “M4TXX-BR12SH” in plastic tube or “M4TXX-BR12SHTR” in Tape & Reel form (see
Caution:
Do not place the SNAPHAT
®
battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell battery.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Doc ID 2412 Rev 8 29/33
Part numbering
Table 17.
SNAPHAT
®
battery table
Part number
M4T28-BR12SH
M4T32-BR12SH
Description
Lithium battery (48 mAh) SNAPHAT
®
Lithium battery (120 mAh) SNAPHAT
®
M48T58, M48T58Y
Package
SH
SH
30/33 Doc ID 2412 Rev 8
M48T58, M48T58Y
Figure 17.
Recycling symbols
Environmental information
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations.
Doc ID 2412 Rev 8 31/33
Revision history M48T58, M48T58Y
Table 18.
Document revision history
Date
Jul-1999
27-Jul-2000
04-Jun-2001
31-Jul-2001
20-May-2002
01-Apr-2003
17-Jul-2003
02-Apr-2004
30-Aug-2007
24-Mar-2009
02-Aug-2010
07-Jun-2011
Revision
1
1.1
2
2.1
2.2
3
3.1
4
5
6
7
8
Changes
First issue
Century bit and battery low flag paragraphs added; power down/up AC characteristics table and waveforms changed (
,
Reformatted; temperature information added (
,
)
Formatting changes from recent document review findings
Modify reflow time and temperature footnotes (
) v2.2 template applied; test condition updated (
)
Update “battery low flag” information
Reformatted; update lead-free packaging information (
,
Reformatted; added lead-free second level interconnect information to
Section 9: Package mechanical data
.
Updated
Section 9: Package mechanical data
; minor reformatting.
,
.
Updated footnote
1
Table 6: Absolute maximum ratings
; updated
Section 11: Environmental information
.
32/33 Doc ID 2412 Rev 8
M48T58, M48T58Y
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Doc ID 2412 Rev 8 33/33
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Key features
Integrated SRAM, real-time clock, power-fail control, and battery
BYTEWIDE RAM-like clock access
Automatic power-fail chip deselect and WRITE protection
Self-contained battery and crystal options
Frequently asked questions
It integrates non-volatile SRAM with a real-time clock, power-fail control circuit, and battery backup.
It utilizes BYTEWIDE RAM-like clock access.
It provides automatic power-fail chip deselect and WRITE protection.
The internal button cell will maintain data in the M48T58/Y for an accumulated period of at least 7 years when VCC is less than VSO.