Chapter
4
System Architecture Overview
The router architecture consists of two major components:
Packet Forwarding Engine—Performs Layer 2 and Layer 3 packet switching, route
lookups, and packet forwarding.
Routing Engine—Provides Layer 3 routing services and network management.
The Packet Forwarding Engine and the Routing Engine perform independently but
communicate constantly through a 100-Mbps internal link. This arrangement provides
streamlined forwarding and routing control and the ability to run Internet-scale networks at
high speeds. Figure 11 illustrates the relationship between the Packet Forwarding Engine and
the Routing Engine.
Figure 11: System Architecture
Routing Engine
Packets
in
Packet Forwarding
Engine
Packets
out
1244
100-Mbps link
For a discussion of the architectural components, see the following sections:
Packet Forwarding Engine Architecture on page 32
Routing Engine Architecture on page 33
System Architecture Overview
31
Packet Forwarding Engine Ar chitectur e
Packet Forwarding Engine Architecture
The Packet Forwarding Engine performs Layer 2 and Layer 3 packet switching. It can forward
up to 40 million packets per second for all packet sizes, which exceeds the line speed of eight
OC-48/STM-16 lines. The aggregate throughput for the router is 40 gigabits per second (Gbps)
simplex or 2.5 Gbps per FPC installed in the system. The Packet Forwarding Engine is
implemented in application-specific integrated circuits (ASICs). It uses a centralized route
lookup engine and shared memory.
Packet Forwarding Engine includes the following components (see Figure 12):
Physical Interface Cards (PICs)—Physically connect the router to a complete range of
fiber-optic and digital network media. A controller ASIC in each PIC performs control
functions specific to the PIC media type.
Flexible PIC Concentrators (FPCs)—House PICs and provide shared memory for
processing incoming and outgoing packets. Each FPC hosts an I/O Manager ASIC, which
divides incoming data packets into memory blocks (cells) and reassembles the cells into
data packets when they are ready for transmission.
Backplane—Transports packets, notifications, and other signals between the FPCs and
the SCB (as well as other system components). Hosts the Distributed Buffer Manager
ASIC, which distributes incoming data cells to the shared memory buffers on the FPCs
and notifies the FPCs of forwarding decisions for outgoing packets.
System Control Board (SCB)—Hosts the Internet Processor or Internet Processor II ASIC,
which makes forwarding decisions.
Figure 12: Packet Forwarding Engine Components and Data Flow
PIC
PIC
Controller
FPC
Packet
in
System Control
Board
I/O
manager
Internet
Processor
Controller
FPC
I/O
manager
Packet
out
= ASIC
Distributed Buffer
Manager
Routing Engine
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1243a
Backplane
Routing Engine Architecture
Data Flow through the Packet Forwarding Engine
Use of ASICs promotes efficient movement of data packets through the system. Packets flow
through the Packet Forwarding Engine in the following sequence (see Figure 12):
1.
Packets arrive at an incoming PIC interface.
2.
The PIC passes the packets to the FPC, where the I/O Manager ASIC processes the
packet headers, divides the packets into 64-byte data cells, and passes the cells to the
backplane.
3.
The Distributed Buffer Manager ASIC on the backplane distributes the data cells
throughout the memory buffers located on and shared by all the FPCs.
4.
The Internet Processor or Internet Processor II ASIC on the SCB performs route lookups
and makes forwarding decisions.
5.
The Internet Processor or Internet Processor II ASIC notifies a second Distributed Buffer
Manager ASIC on the backplane of the routing decision.
6.
The Distributed Buffer Manager ASIC forwards the notification to the FPC that hosts the
outbound PIC.
7.
The I/O Manager ASIC on the FPC reassembles data cells in shared memory into data
packets as they are ready for transmission and passes them to the outbound PIC.
8.
The outbound PIC transmits the data packets.
Routing Engine Architecture
The Routing Engine is an Intel-based PCI platform running the JUNOS Internet software,
which Juniper Networks has developed and optimized to handle large numbers of network
interfaces and routes. The software consists of a set of system processes running in protected
memory modules on top of an independent operating system. The JUNOS kernel supports
JUNOS system processes, which handle system management processes, routing protocols,
and control functions (see Figure 13).
The Routing Engine has a dedicated 100-Mbps internal connection to the Packet Forwarding
Engine.
System Architecture Overview
33
Routing Engine Ar chitectur e
Figure 13: Routing Engine Architecture
JUNOS
System
management
processes
Routing
protocols
Control
functions
Kernel
System processes
Operating system
1164
Intel-based PCI platform
Routing Engine Functions
The Routing Engine handles all routing protocol processes, as well as the software processes
that control the router’s interfaces, the chassis components, system management, and user
access to the router. These routing and software processes run on top of a kernel that
interacts with the Packet Forwarding Engine. For more information about the processes, see
“Routing Engine Software Components” on page 26.
The Routing Engine includes the following functions and features:
Processing of routing protocol packets—The Routing Engine handles all packets that
concern routing protocols, freeing the Packet Forwarding Engine to handle only packets
that represent Internet traffic.
Software modularity—Because each software process is devoted to a different function
and uses a separate process space, the failure of one process has little or no effect on the
others.
In-depth Internet functionality—Each routing protocol is implemented with a complete
set of Internet features and provides full flexibility for advertising, filtering, and
modifying routes. Routing policies are set according to route parameters (for example,
prefix, prefix lengths, and Border Gateway Protocol [BGP] attributes).
Scalability—The JUNOS routing tables have been designed to hold all the routes in
current networks with ample capacity for expansion. Additionally, the JUNOS Internet
software can efficiently support large numbers of interfaces and virtual circuits.
Management interface—Different levels of system management tools are provided,
including the JUNOS command-line interface (CLI), the JUNOScript application
programming interface, the craft interface, and SNMP.
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M40 Internet Router Hardware Guide
Routing Engine Architecture
Storage and change management—Configuration files, system images, and microcode
can be held and maintained in primary and secondary storage systems, permitting local
or remote upgrades.
Monitoring efficiency and flexibility—The router supports functions such as alarm
handling and packet counting on every port, without degrading packet-forwarding
performance.
The Routing Engine constructs and maintains one or more routing tables. From the routing
tables, the Routing Engine derives a table of active routes, called the forwarding table, which
is then copied into the Packet Forwarding Engine. The design of the Internet Processor II
ASIC allows the forwarding table in the Packet Forwarding Engine to be updated without
interrupting forwarding performance. See Figure 14.
Figure 14: Control Packet Handling: Routing and Forwarding Table Updates
Routing protocol
process
Routing Engine
Forwarding table
updates
Routing protocol
packets from network
Forwarding table
Packet Forwarding
Engine
Packets
out
1240
Packets
in
System Architecture Overview
35
Routing Engine Ar chitectur e
36
M40 Internet Router Hardware Guide
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