package houses the M48T02/12 silicon with a quartz crystal and a long life lithium button cell to form a highly integrated battery-backed memory and real-time clock solution.

The M48T02/12 button cell has sufficient capacity and storage life to maintain data and clock functionality for an accumulated time period of at least 10 years in the absence of power over the operating temperature range.

The M48T02/12 is a non-volatile pin and function equivalent to any JEDEC standard

2 Kb x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed.

Figure 1.

Logic diagram

VCC

DQ0-DQ7 A0-A10

M48T02

M48T12

VSS

Table 1.

A0-A10

DQ0-DQ7

Signal names

Address inputs

Data inputs / outputs

Chip enable

Output enable

WRITE enable

Supply voltage

Ground

AI01027

Doc ID 2410 Rev 9 5/25

Description

Figure 2.

DIP connections

DQ0

DQ1

DQ2

VSS

M48T02

M48T12

VCC

A10

DQ7

DQ6

DQ5

DQ4

DQ3

Figure 3.

Block diagram

32,768 Hz

CRYSTAL

LITHIUM

CELL

OSCILLATOR AND

CLOCK CHAIN

8 x 8 BiPORT

SRAM ARRAY

POWER

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

VPFD

BOK

2040 x 8

SRAM ARRAY

M48T02, M48T12

AI01028

A0-A10

DQ0-DQ7

VCC VSS

AI01329

6/25 Doc ID 2410 Rev 9

M48T02, M48T12 Operation modes

Note:

Figure 3 on page 6

shows, the static memory array and the quartz controlled clock oscillator of the M48T02/12 are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible

BYTEWIDE™ clock information in the bytes with addresses 7F8h-7FFh. The clock locations contain the year, month, date, day, hour, minute, and second in 24-hour BCD format.

Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically.

Byte 7F8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting.

The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORT™ READ/WRITE memory cells. The M48T02/12 includes a clock control circuit which updates the clock bytes with current information once per second.

The information can be accessed by the user in the same manner as any other location in the static memory array.

The M48T02/12 also has its own power-fail detect circuit. The control circuitry constantly monitors the single 5 V supply for an out of tolerance condition. When V

is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low V

. As V

CC falls below approximately 3 V, the control circuitry connects the battery which maintains data and clock operation until valid power returns.

Table 2.

Operating modes

Mode V

Deselect

WRITE

READ

4.75 to 5.5 V or

4.5 to 5.5 V

Deselect

PFD

(min)

(1)

≤ V

(1)

See

Table 11 on page 20

for details.

X = V

or V

; V

= Battery backup switchover voltage.

DQ0-DQ7

High Z

OUT

High Z

Power

Standby

Active

CMOS standby

Battery backup mode

The M48T02/12 is in the READ mode whenever W (WRITE enable) is high and E (chip enable) is low. The device architecture allows ripple-through access of data from eight of

16,384 locations in the static storage array. Thus, the unique address specified by the 11

Address Inputs defines which one of the 2,048 bytes of data is to be accessed. Valid data will be available at the data I/O pins within address access time (t

AVQV

) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the chip enable access time (t

ELQV

) or output enable access time (t

GLQV

Doc ID 2410 Rev 9 7/25

Operation modes M48T02, M48T12

The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are activated before t

AVQV

, the data lines will be driven to an indeterminate state until t

AVQV

. If the address inputs are changed while E and G remain active, output data will remain valid for output data hold time (t

AXQX

) but will go indeterminate until the next address access.

Figure 4.

READ mode AC waveforms

A0-A10 tAVAV

VALID tAVQV tELQV tAXQX tEHQZ

E tELQX tGLQV tGHQZ

G tGLQX

DQ0-DQ7 VALID

AI01330

Note: WRITE enable (W) = High.

Table 3.

READ mode AC characteristics

M48T02/M48T12

Symbol Parameter

(1)

–70 –150 –200

Min Max Min Max Min Max

AVAV t

AVQV t

ELQV t

GLQV t

ELQX t

GLQX t

EHQZ t

GHQZ t

AXQX

READ cycle time

Address valid to output valid

Chip enable low to output valid

Output enable low to output valid

Chip enable low to output transition

Output enable low to output transition

Chip enable high to output Hi-Z

Output enable high to output Hi-Z

Address transition to output transition

150

200

Valid for ambient operating temperature: T

= 0 to 70 °C; V

= 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).

Unit

ns ns ns ns ns ns ns ns ns

8/25 Doc ID 2410 Rev 9

M48T02, M48T12 Operation modes

The M48T02/12 is in the WRITE mode whenever W and E are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of t

EHAX

from chip enable or t

WHAX

from WRITE enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid t

DVWH

prior to the end of WRITE and remain valid for t

WHDX

afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs t

WLQZ

after W falls.

Figure 5.

WRITE enable controlled, WRITE AC waveform

A0-A10 tAVAV

VALID tAVWH tAVEL tWHAX

E tWLWH tAVWL

W tWLQZ tWHQX

DQ0-DQ7 tWHDX

DATA INPUT tDVWH

AI01331

Figure 6.

Chip enable controlled, WRITE AC waveforms

A0-A10 tAVEL tAVAV

VALID tAVEH tELEH

E tAVWL

W tEHAX tEHDX

DQ0-DQ7 DATA INPUT tDVEH

AI01332B

Doc ID 2410 Rev 9 9/25

Operation modes M48T02, M48T12

Table 4.

WRITE mode AC characteristics

M48T02/M48T12

Symbol Parameter

(1)

–70 –150 –200 Unit

Min Max Min Max Min Max

AVAV t

AVWL t

AVEL t

WLWH t

ELEH t

WHAX t

EHAX t

DVWH t

DVEH t

WHDX t

EHDX t

WLQZ t

AVWH t

AVEH t

WHQX

WRITE cycle time

Address valid to WRITE enable low

Address valid to chip enable low

WRITE enable pulse width

Chip enable low to chip enable high

WRITE enable high to address transition

Chip enable high to address transition

Input valid to WRITE enable high

Input valid to chip enable high

WRITE enable high to input transition

Chip enable high to input transition

WRITE enable low to output Hi-Z

Address valid to WRITE enable high

Address valid to chip enable high

WRITE enable high to output transition

150

120

200

120

140

60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Valid for ambient operating temperature: T

A noted).

= 0 to 70 °C; V

= 4.75 to 5.5 V or 4.5 to 5.5 V (except where

Note:

With valid V

applied, the M48T02/12 operates as a conventional BYTEWIDE™ static

RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when V

falls within the V

PFD

(max), V

PFD

(min) window. All outputs become high impedance, and all inputs are treated as “don't care.”

A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below V

PFD

(min), the user can be assured the memory will be in a write protected state, provided the V

fall time is not less than t

. The M48T02/12 may respond to transient noise spikes on V

CC that reach into the deselect window during the time the device is sampling V

. Therefore, decoupling of the power supply lines is recommended.

The power switching circuit connects external V

to the RAM and disconnects the battery when V

rises above V

. As V

rises, the battery voltage is checked. If the voltage is too low, an internal battery not oK (BOK) flag will be set. The BOK flag can be checked after power up. If the BOK flag is set, the first WRITE attempted will be blocked. The flag is

automatically cleared after the first WRITE, and normal RAM operation resumes.

Figure 7 on page 11

illustrates how a BOK check routine could be structured.

For more information on a battery storage life refer to the application note AN1012.

10/25 Doc ID 2410 Rev 9

M48T02, M48T12

Figure 7.

Checking the BOK flag status

POWER-UP

READ DATA

AT ANY ADDRESS

WRITE DATA

COMPLEMENT BACK

TO SAME ADDRESS

READ DATA

AT SAME

ADDRESS AGAIN

Operation modes

IS DATA

COMPLEMENT

OF FIRST

READ?

(BATTERY OK) YES

NO (BATTERY LOW)

NOTIFY SYSTEM

OF LOW BATTERY

(DATA MAY BE

CORRUPTED)

WRITE ORIGINAL

DATA BACK TO

SAME ADDRESS

CONTINUE

AI00607

Doc ID 2410 Rev 9 11/25

Clock operations M48T02, M48T12

3.1

3.2 Reading the clock

Updates to the TIMEKEEPER

registers should be halted before clock data is read to prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself.

Updating is halted when a '1' is written to the READ bit, the seventh bit in the control register. As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued.

All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a '0.'

Setting the clock

The eighth bit of the control register is the WRITE bit. Setting the WRITE bit to a '1,' like the

READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24-hour BCD format (on

Table 5 on page 13

Resetting the WRITE bit to a '0' then transfers the values of all time registers (7F9-7FF) to the actual TIMEKEEPER counters and allows normal operation to resume. The FT bit and the bits marked as '0' in

Table 5 on page 13

must be written to '0' to allow for normal

TIMEKEEPER and RAM operation.

See the application note AN923, “TIMEKEEPER

rolling into the 21 st

century” for information on century rollover.

12/25 Doc ID 2410 Rev 9

M48T02, M48T12 Clock operations

Table 5.

Address

7FF

7FE

7FD

7FC

7FB

7FA

7F9

7F8

Register map

D7 D6 D5 D4

10 years

0 0

10 M

10 date

0 0

10 hours

10 minutes

10 seconds

R S

Data

Function/range

BCD format

D3 D2 D1 D0

Year

Month

Date

Day

Hours

Minutes

Seconds

Year

Month

Date

Day

Hours

Minutes

Seconds

Calibration Control

00-99

01-12

01-31

01-07

00-23

00-59

Keys:

S = SIGN bit

FT = FREQUENCY TEST bit (set to '0' for normal clock operation)

R = READ bit

W = WRITE bit

ST = STOP bit

0 = Must be set to '0'

3.3 Stopping and starting the oscillator

The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP bit is the MSB of the seconds register. Setting it to a '1' stops the oscillator. The M48T02/12 is shipped from STMicroelectronics with the STOP bit set to a '1.'

When reset to a '0,' the M48T02/12 oscillator starts within one second.

3.4 Calibrating the clock

The M48T02/12 is driven by a quartz-controlled oscillator with a nominal frequency of

32,768 Hz. A typical M48T02/12 is accurate within 1 minute per month at 25°C without calibration. The devices are tested not to exceed ± 35 ppm (parts per million) oscillator frequency error at 25°C, which equates to about ±1.53 minutes per month.

The oscillation rate of any crystal changes with temperature.

Figure 8 on page 15

shows the

frequency error that can be expected at various temperatures. Most clock chips compensate for crystal frequency and temperature shift error with cumbersome “trim” capacitors. The

M48T02/12 design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as

shown in

Figure 9 on page 15

. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five-bit calibration byte found in the control register. Adding counts speeds the clock up, subtracting counts slows the clock down.

The calibration byte occupies the five lower order bits in the control register. This byte can be set to represent any value between 0 and 31 in binary form. The sixth bit is the sign bit;

Doc ID 2410 Rev 9 13/25

Clock operations

Note:

M48T02, M48T12

'1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a

64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on.

Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles; that is +4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or

–2.75 minutes per month.

Two methods are available for ascertaining how much calibration a given M48T02/12 may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accesses the calibration byte.

The second approach is better suited to a manufacturing environment, and involves the use of some test equipment. When the Frequency Test (FT) bit, the seventh-most significant bit in the day register, is set to a '1,' and the oscillator is running at 32,768 Hz, the LSB (DQ0) of the seconds register will toggle at 512 Hz. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of

512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring

–10 (WR001010) to be loaded into the calibration byte for correction.

Setting or changing the calibration byte does not affect the frequency test output frequency.

The device must be selected and addresses must be stable at address 7F9 when reading the 512 Hz on DQ0.

The FT bit must be set using the same method used to set the clock: using the WRITE bit.

The LSB of the seconds register is monitored by holding the M48T02/12 in an extended

READ of the seconds register, but without having the READ bit set. The FT bit MUST be reset to '0' for normal clock operations to resume.

It is not necessary to set the WRITE bit when setting or resetting the frequency test bit (FT) or the stop bit (ST).

For more information on calibration, see the application note AN924, “TIMEKEEPER

® calibration.”

14/25 Doc ID 2410 Rev 9

M48T02, M48T12

Figure 8.

Crystal accuracy across temperature

ppm

Clock operations

-20

-40

-60

ΔF

= -0.038

ppm

(T - T

)

± 10%

= 25

°C

-80

-100

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70

°C

AI02124

Figure 9.

Clock calibration

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

AI00594B

Doc ID 2410 Rev 9 15/25

Clock operations M48T02, M48T12

3.5 V

noise and negative going transients

transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the V

bus. These transients can be reduced if capacitors are used to store energy which stabilizes the V

bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in

Figure 10 on page 16

In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on V

that drive it to values below V

by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a

Schottky diode from V

to V

(cathode connected to V

, anode to V

). Schottky diode

1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount.

Figure 10.

Supply voltage protection

VCC

0.1

μF

DEVICE

VSS

AI02169

16/25 Doc ID 2410 Rev 9

M48T02, M48T12 Maximum ratings

Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 6.

Symbol

Absolute maximum ratings

Parameter Value Unit

STG

SLD

(1)(2)

Ambient operating temperature

Storage temperature (V

off, oscillator off)

Lead solder temperature for 10 seconds

Input or output voltages

Supply voltage

Output current

Power dissipation

0 to 70

–40 to 85

260

–0.3 to 7

°C

V mA

Soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. Furthermore, the devices shall not be exposed to IR reflow nor preheat cycles (as performed as part of wave soldering). ST recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries.

For DIP packaged devices, ultrasonic vibrations should not be used for post-solder cleaning to avoid damaging the crystal.

Caution:

Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup mode.

Doc ID 2410 Rev 9 17/25

DC and AC parameters

5 DC and AC parameters

Note:

M48T02, M48T12

This section summarizes the operating and measurement conditions, as well as the DC and

AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.

Table 7.

Operating and AC measurement conditions

Parameter

Supply voltage (V

)

Ambient operating temperature (T

)

Load capacitance (C

)

Input rise and fall times

Input pulse voltages

Input and output timing ref. voltages

M48T02

4.75 to 5.5

0 to 70

100

≤ 5

0 to 3

1.5

Output Hi-Z is defined as the point where data is no longer driven.

M48T12

4.5 to 5.5

0 to 70

100

≤ 5

0 to 3

1.5

Figure 11.

AC testing load circuit

Unit

°C pF ns

DEVICE

UNDER

TEST

1.8k

OUT

CL = 100pF

CL includes JIG capacitance

Table 8.

Symbol

Capacitance

Parameter

(1)(2)

Min Max

(3)

Input capacitance

Input / output capacitance

Effective capacitance measured with power supply at 5 V. Sampled only, not 100% tested.

At 25 °C, f = 1 MHz.

Outputs deselected.

AI01019

Unit

pF pF

18/25 Doc ID 2410 Rev 9

M48T02, M48T12 DC and AC parameters

Table 9.

Symbol

DC characteristics

Parameter Test condition

(1)

Min Max

(2)

CC1

(3)

CC2

(3)

Input leakage current

Output leakage current

Supply current

Supply current (standby) TTL

Supply current (standby) CMOS

Input low voltage

Input high voltage

Output low voltage

Output high voltage

≤ V

OUT

Outputs open

E = V

≤ V

– 0.2 V

= 2.1 mA

= –1 mA

–0.3

2.2

2.4

0.8

±1

+ 0.3

0.4

Valid for ambient operating temperature: T

= 0 to 70 °C; V

= 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).

Outputs deselected.

Measured with control bits set as follows: R = '1'; W, ST, FT = '0.'

Unit

µA

µA mA mA

Figure 12.

Power down/up mode AC waveforms

VCC

VPFD (max)

VPFD (min)

VSO tPD tF tFB tDR tRB

DON'T CARE tR

NOTE trec

RECOGNIZED

INPUTS

RECOGNIZED

HIGH-Z

Note:

OUTPUTS VALID

(PER CONTROL INPUT)

VALID

(PER CONTROL INPUT)

AI00606

Inputs may or may not be recognized at this time. Caution should be taken to keep E high as

rises past V

PFD

(min). Some systems may perform inadvertent WRITE cycles after V

CC rises above V

PFD

(min) but before normal system operations begin. Even though a power on reset is being applied to the processor, a reset condition may not occur until after the system clock is running.

Doc ID 2410 Rev 9 19/25

DC and AC parameters M48T02, M48T12

Table 10.

Power down/up AC characteristics

Symbol Parameter

(1)

Min Max Unit

PD t

(2) t

(3) t

R t

RB t rec

E or W at V

before power down

PFD

(max) to V

PFD

(min) V

fall time

PFD

(min) to V

fall time

PFD

(min) to V

PFD

(max) V

rise time

to V

PFD

(min) V

rise time

E or W at V

IH before power-up

300

µs

µs ms

Valid for ambient operating temperature: T

A noted).

= 0 to 70 °C; V

= 4.75 to 5.5 V or 4.5 to 5.5 V (except where

PFD

(max) to V

PFD until 200 µs after V

(min) fall time of less than t

passes V

PFD

(min).

may result in deselection/write protection not occurring

PFD

(min) to V

fall time of less than t

may cause corruption of RAM data.

Table 11.

Power down/up trip points DC characteristics

Symbol Parameter

(1)(2)

Min Typ Max Unit

PFD

SO t

(3)

Power-fail deselect voltage

Battery backup switchover voltage

Expected data retention time

M48T02

M48T12

4.5

4.2

4.6

4.3

3.0

4.75

4.5

YEARS

All voltages referenced to V

Valid for ambient operating temperature: T

A noted).

= 0 to 70 °C; V

= 4.75 to 5.5 V or 4.5 to 5.5 V (except where

At 25 °C; V

= 0 V.

20/25 Doc ID 2410 Rev 9

M48T02, M48T12

6 Package mechanical data

Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at:

www.st.com

ECOPACK

is an ST trademark.

Figure 13.

PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package outline

Note:

A2 A

A1 e1

L C

B1 e3

D eA

PCDIP

Drawing is not to scale.

E e1 e3 eA

Table 12.

PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package mech. data mm inches

Symb

Typ Min Max Typ Min Max

8.89

0.38

8.38

0.38

1.14

0.20

34.29

17.83

2.29

9.65

0.76

8.89

0.53

1.78

0.31

34.80

18.34

2.79

0.350

0.015

0.330

0.015

0.045

0.008

1.350

0.702

0.090

27.94

15.24

3.05

16.00

3.81

1.1

0.600

0.120

0.380

0.030

0.350

0.021

0.070

0.012

1.370

0.722

0.110

0.630

0.150

Doc ID 2410 Rev 9 21/25

Part numbering M48T02, M48T12

Table 13.

Ordering information scheme

Example: M48T 02 –70 PC 1

Device type

M48T

Supply voltage and write protect voltage

02 = V

= 4.75 to 5.5 V; V

PFD

= 4.5 to 4.75 V

12 = V

= 4.5 to 5.5 V; V

PFD

= 4.2 to 4.5 V

Speed

–70 = 70 ns (M48T02/12)

–150 = 150 ns (M48T02/12)

–200 = 200 ns (M48T02/12)

(1)

Package

PC = PCDIP24

Temperature range

1 = 0 to 70 °C

Shipping method

blank = ECOPACK

package, tubes

Not recommended for new design. Contact ST sales office for availability.

For other options, or for more information on any aspect of this device, please contact the

ST sales office nearest you.

22/25 Doc ID 2410 Rev 9

M48T02, M48T12

Figure 14.

Recycling symbols

Environmental information

This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product.

Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations.

Doc ID 2410 Rev 9 23/25

Revision history M48T02, M48T12

Table 14.

Document revision history

Date

Jul-2000

13-Jul-2000

07-May-2001

14-May-2001

16-Jul-2001

20-May-2002

26-Jun-2002

28-Mar-2003

31-Mar-2004

12-Dec-2005

21-Sep-2007

13-Jan-2009

02-Aug-2010

07-Jun-2011

Revision

2.2

2.3

2.4

3.0

1.0

1.1

2.0

2.1

4.0

5.0

Changes

First issue t rec

change (

Table 10

)

Reformatted; temp. / voltage info. added to tables (

Table 8

)

Note added to clock calibration section; table footnote correction (

Table 2

)

Basic formatting / content changes (cover page,

Table 8

)

Add countries to disclaimer

Add footnote to table (

Table 11

)

v2.2 template applied; test conditions updated (

Table 10

)

Reformatted; lead-free (Pb-free) package information update (

Table 6

)

Updated template, lead-free text, removed footnote (

Table 9

)

Added lead-free second level interconnect information to cover page and

Section 6: Package mechanical data

Added

Section 8: Environmental information

; updated text in

Section 6:

Package mechanical data

; minor formatting changes.

Reformatted document; updated

Section 4

Table 12

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Table 6: Absolute maximum ratings

; updated

Section 8: Environmental information

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M48T02, M48T12

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