STMicroelectronics M48Z129V Datasheet
ಜಾಹಿರಾತು
ಜಾಹಿರಾತು
M48Z129V
3.3 V, 1 Mbit (128 Kb x 8) ZEROPOWER
®
SRAM
Not recommended for new design
Features
■
■
■
■
■
■
■
■
■
■
Integrated, ultra low power SRAM, power-fail control circuit, and battery
Conventional SRAM operation; unlimited
WRITE cycles
10 years of data retention in the absence of power
Microprocessor power-on reset (reset valid even during battery backup mode)
Battery low pin - provides warning of battery end-of-life
Automatic power-fail chip deselect and WRITE protection
WRITE protect voltages
– V
CC
= 3.0 to 3.6 V; 2.7 V
≤ V
PFD
≤ 3.0 V
(V
PFD
= power-fail deselect voltage)
Self-contained battery in the CAPHAT
™
DIP package
Pin and function compatible with JEDEC standard 128 K x 8 SRAMs
RoHS compliant
– Lead-free second level interconnect
32
1
PMDIP32 module
Obsolete Product(s) - Obsolete Product(s)
September 2011 Doc ID 5716 Rev 8
This is information on a product still in production but not recommended for new designs.
1/20
www.st.com
1
Contents
Contents
M48Z129V
CC
noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 11
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Obsolete Product(s) - Obsolete Product(s)
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M48Z129V
List of tables
List of tables
Obsolete Product(s) - Obsolete Product(s)
Doc ID 5716 Rev 8 3/20
List of figures
List of figures
M48Z129V
Chip enable or output enable controlled, READ mode AC waveforms. . . . . . . . . . . . . . . . . 8
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M48Z129V
1 Description
Description
The M48Z129V ZEROPOWER
®
SRAM is a 1,048,576 bit non-volatile static RAM organized as 131,072 words by 8 bits. The device combines an internal lithium battery, a CMOS SRAM and a control circuit in a plastic 32-pin DIP module. The M48Z129V directly replaces industry standard 128 K x 8 SRAM. It also provides the non-volatility of FLASH without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed.
Figure 1.
Logic diagram
VCC
A0-A16
17
W
E
G
M48Z129V
8
DQ0-DQ7
RST
BL
VSS
Table 1.
Signal names
A0-A16 Address inputs
DQ0-DQ7
E
G
W
RST
BL
Data inputs / outputs
Chip enable
Output enable
WRITE enable
Reset output (open drain)
Battery low output (open drain)
Supply voltage V
CC
Ground V
SS
Obsolete Product(s) - Obsolete Product(s)
AI02309
Doc ID 5716 Rev 8 5/20
Description
Figure 2.
DIP connections
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
RST
A16
A14
A12
A7
A6
14
15
16
11
12
13
4
5
6
1
2
3
7
8
26
9
10
M48Z129V
25
24
23
32
31
30
29
28
27
19
18
17
22
21
20
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VCC
A15
BL
W
A13
A8
Figure 3.
Block diagram
VCC
E
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
POWER
E
131,072 x 8
SRAM ARRAY
INTERNAL
BATTERY
RST BL VSS
W
G
A0-A16
DQ0-DQ7
M48Z129V
AI02310
AI03608
Obsolete Product(s) - Obsolete Product(s)
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M48Z129V Operation modes
Note:
The M48Z129V also has its own power-fail detect circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition. When V
CC
is out of tolerance, the circuit write protects the SRAM, providing data security in the midst of unpredictable system operation. As V
CC
falls, the control circuitry automatically switches to the battery, maintaining data until valid power is restored.
Table 2.
Operating modes
Mode
Deselect
4.5 to 5.5 V
WRITE
READ or
3.0 to 3.6 V
READ
Deselect V
SO
to V
PFD
(min)
(1)
Deselect
≤ V
1.
See
V
CC
E
V
IH
V
IL
V
IL
V
IL
X
X
G
X
X
V
IL
V
IH
X
X
W
X
V
IL
V
IH
V
IH
X
X
X = V
IH
or V
IL
; V
SO
= battery backup switchover voltage
DQ0-DQ7
High Z
D
IN
D
OUT
High Z
High Z
High Z
Power
Standby
Active
Active
Active
CMOS standby
Battery backup mode
The M48Z129V is in the READ mode whenever W (WRITE enable) is high and E (chip enable) is low. The unique address specified by the 17 address inputs defines which one of the 131,072 bytes of data is to be accessed. Valid data will be available at the data I/O pins within t
AVQV
(address access time) after the last address input signal is stable, providing the
E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the chip enable access times (t
ELQV
) or output enable access time (t
GLQV
).
The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are activated before t
AVQV
, the data lines will be driven to an indeterminate state until t
AVQV
. If the address inputs are changed while E and G remain active, output data will remain valid for t
AXQX
(output data hold time) but will go indeterminate until the next address access.
Figure 4.
Address controlled, READ mode AC waveforms
Note:
A0-A16 tAXQX
DATA VALID tAVQV
VALID
DQ0-DQ7
DATA VALID
Chip enable (E) and output enable (G) = low, WRITE enable (W) = high
AI02324
Doc ID 5716 Rev 8 7/20
Operation modes M48Z129V
Figure 5.
Chip enable or output enable controlled, READ mode AC waveforms
A0-A16 tAVAV
VALID tAVQV tELQV tAXQX tEHQZ
E tELQX tGLQV tGHQZ
G
DQ0-DQ7 tGLQX
DATA OUT
AI01197
Table 3.
Symbol
READ mode AC characteristics
Parameter
(1)
t
AVAV t
AVQV t
ELQV t
GLQV t
ELQX
(2) t
GLQX
(2) t
EHQZ
(2) t
GHQZ
(2) t
AXQX
READ cycle time
Address valid to output valid
Chip enable low to output valid
Output enable low to output valid
Chip enable low to output transition
Output enable low to output transition
Chip enable high to output Hi-Z
Output enable high to output Hi-Z
Address transition to output transition
1.
Valid for ambient operating temperature: T
A
= 0 to 70 °C; V
CC
= 3.0 to 3.6 V (except where noted).
2.
C
L
= 5pF (see
).
Min
85
5
5
5
Max
85
85
45
40
25
Unit
ns ns ns ns ns ns ns ns ns
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M48Z129V Operation modes
The M48Z129V is in the WRITE mode whenever W (WRITE enable) and E (chip enable) are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A
WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of t
EHAX from chip enable or t
WHAX
from WRITE enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid t
DVWH
prior to the end of WRITE and remain valid for t
WHDX
afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G a low on W will disable the outputs t
WLQZ
after
W falls.
Figure 6.
WRITE enable controlled, WRITE mode AC waveform
A0-A16 tAVAV
VALID tAVWH tAVEL tWHAX
E tWLWH tAVWL
W tWLQZ tWHQX
DQ0-DQ7 tWHDX
DATA INPUT tDVWH
AI02382
Figure 7.
Chip enable controlled, WRITE mode AC waveforms
A0-A16 tAVEL tAVAV
VALID tAVEH tELEH tEHAX
E tWLWH tAVWL
W tEHDX
DQ0-DQ7 DATA INPUT
AI03611
Doc ID 5716 Rev 8 9/20
Operation modes
Table 4.
Symbol
WRITE mode AC characteristics
Parameter
(1)
t
AVAV t
AVWL t
AVEL t
WLWH t
ELEH t
WHAX t
EHAX t
DVWH t
DVEH t
WHDX t
EHDX t
WLQZ
(2)(3) t
AVWH t
AVEH t
WHQX
(2)(3)
WRITE cycle time
Address valid to WRITE enable low
Address valid to chip enable low
WRITE enable pulse width
Chip enable low to chip enable high
WRITE enable high to address transition
Chip enable high to address transition
Input valid to WRITE enable high
Input valid to chip enable high
WRITE enable high to input transition
Chip enable high to input transition
WRITE enable low to output Hi-Z
Address valid to WRITE enable high
Address valid to chip enable high
WRITE enable high to output transition
1.
Valid for ambient operating temperature: T
A
= 0 to 70 °C; V
CC
= 3.0 to 3.6 V (except where noted).
2.
C
L
= 5 pF (see
3.
If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Min
75
5
15
35
85
0
0
65
35
0
15
75
75
5
M48Z129V
Max
30
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note:
With valid V
CC
applied, the M48Z129V operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically deselect, write protecting itself when V
CC
falls between V
PFD
(max), V
PFD
(min) window. All outputs become high impedance and all inputs are treated as “Don’t care”.
A power failure during a WRITE cycle may corrupt data at the current addressed location, but does not jeopardize the rest of the RAM’s content. At voltages below V
PFD
(min), the memory will be in a write protected state, provided the V
CC
fall time is not less than t
F
. The
M48Z129V may respond to transient noise spikes on V
CC
that cross into the deselect window during the time the device is sampling V
CC
. Therefore, decoupling of the power supply lines is recommended.
drops below V
SO
, the control circuit switches power to the internal battery, When V
CC
Obsolete Product(s) - Obsolete Product(s) accumulated period of at least 10 years at room temperature. As system power rises above
V
SO
, the battery is disconnected, and the power supply is switched to external V
CC
.
Deselect continues for t
REC
after V
CC reaches V
PFD
(max).
For more information on battery storage life refer to the application note AN1012.
10/20 Doc ID 5716 Rev 8
M48Z129V Operation modes
2.4 V
CC
noise and negative going transients
I
CC
transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the V
CC
bus. These transients can be reduced if capacitors are used to store energy which stabilizes the V
CC
bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in
) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on V
CC
that drive it to values below V
SS
by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a
Schottky diode from V
CC
to V
SS
(cathode connected to V
CC
, anode to V
SS
). Schottky diode
1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount.
Figure 8.
Supply voltage protection
VCC
VCC
0.1µF DEVICE
VSS
AI02169
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Doc ID 5716 Rev 8 11/20
Maximum ratings M48Z129V
Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 5.
Symbol
Absolute maximum ratings
Parameter Value Unit
T
A
T
STG
T
SLD
(1)
V
IO
V
CC
I
O
P
D
Ambient operating temperature
Storage temperature (V
CC
off, oscillator off)
Lead solder temperature for 10 seconds
Input or output voltages
Supply voltage
Output current
Power dissipation
0 to 70
–40 to 85
260
–0.3 to 7
–0.3 to 7
20
1
°C
°C
°C
V
V mA
W
1.
Soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. Furthermore, the devices shall not be exposed to IR reflow nor preheat cycles (as performed as part of wave soldering). ST recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries.
Caution:
Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup mode.
Obsolete Product(s) - Obsolete Product(s)
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M48Z129V
4 DC and AC parameters
Note:
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 6.
Operating and AC measurement conditions
Parameter
Supply voltage (V
CC
)
Ambient operating temperature (T
A
)
Load capacitance (C
L
)
Input rise and fall times
Input pulse voltages
Input and output timing ref. voltages
3.0 to 3.6
0 to 70
50
≤ 5
0 to 3
1.5
Output Hi-Z is defined as the point where data is no longer driven.
Figure 9.
AC testing load circuit
Unit
V
°C pF ns
V
V
650
Ω
DEVICE
UNDER
TEST
1.75V
CL = 100pF
or 50pF
(1)
CL includes JIG capacitance
AI03630
1.
50 pF for M48Z129V (3.3 V).
Table 7.
Symbol
Capacitance
Parameter
(1)(2)
Min Max Unit
Input capacitance 10 pF C
IN
(3)
Input / output capacitance C
IO
Obsolete Product(s) - Obsolete Product(s)
2.
At 25 °C, f = 1 MHz.
10 pF
3.
Outputs deselected.
Doc ID 5716 Rev 8 13/20
DC and AC parameters M48Z129V
Table 8.
Sym
DC characteristics
Parameter Test condition
(1)
Min
I
LI
I
LO
(2)
I
CC
I
CC1
I
CC2
V
IL
V
IH
V
V
OL
OH
Input leakage current
Output leakage current
Supply current
Supply current (standby) TTL
Supply current (standby) CMOS
Input low voltage
Input high voltage
Output low voltage
Output high voltage
0 V
≤ V
E
= V
CC
IN
≤ V
CC
0 V
≤ V
OUT
E = V
≤ V
CC
Outputs open
IH
– 0.2 V
I
OL
= 2.1 mA
I
OH
= –1 mA
–0.3
2.2
2.2
1.
Valid for ambient operating temperature: T
A
= 0 to 70 °C; V
CC
= 3.0 to 3.6 V (except where noted).
2.
Outputs deselected.
Max
±1
±1
50
4
3
0.6
V
CC
+ 0.3
0.4
Unit
mA
V
V
V
µA
µA mA mA
V
Obsolete Product(s) - Obsolete Product(s)
14/20 Doc ID 5716 Rev 8
M48Z129V
Figure 10.
Power down/up mode AC waveforms
VCC
VPFD (max)
VPFD (min)
VSO
E tF tWPT
RECOGNIZED tFB tDR tRB
DON'T CARE
HIGH-Z
OUTPUTS VALID
(PER CONTROL INPUT)
RST
DC and AC parameters
tR tREC
RECOGNIZED
VALID
(PER CONTROL INPUT)
AI03610
Table 9.
Symbol
Power down/up AC characteristics
Parameter
(1)
Min Max Unit
t
F
(2) t
FB
(3) t
R t
RB t
WPT t
REC
V
PFD
(max) to V
PFD
V
PFD
(min) to V
SS
V
SS
(min) V
CC
fall time
V
CC
fall time
V
PFD
(min) to V
PFD
(max) V
CC
rise time
to V
PFD
(min) V
CC
rise time
Write protect time
300
150
10
1
40 250
µs
µs
µs
µs
µs
V
PFD
(max) to RST high 40 200 ms
1.
Valid for ambient operating temperature: T
A
= 0 to 70 °C; V
CC
= 3.0 to 3.6 V (except where noted).
2.
V
PFD
V
CC
(max) to V
PFD
passes V
PFD
(min) fall time of less than t
F
may result in deselection/write protection not occurring until 200 µs after
(min).
3.
V
PFD
(min) to V
SS
fall time of less than t
FB
may cause corruption of RAM data.
Table 10.
Power down/up trip points DC characteristics
Symbol Parameter
(1)(2)
Min Typ Max Unit
Power-fail deselect voltage 2.7
2.9
3.0
V V
PFD
V
SO t
DR
(3)
Battery backup switchover voltage
Expected data retention time 10
2.45
V
Years
1.
All voltages referenced to V
SS
.
2.
Valid for ambient operating temperature: T
A
= 0 to 70 °C; V
CC
= 3.0 to 3.6 V (except where noted).
3.
At 25 °C, V
CC
= 0 V.
Doc ID 5716 Rev 8 15/20
Package mechanical data
5 Package mechanical data
M48Z129V
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at:
www.st.com
.
ECOPACK
®
is an ST trademark.
Figure 11.
PMDIP32 – 32-pin plastic module DIP, package outline
A
C
S
A1 e1
L eA e3
B
D
N
E
1
Note: Drawing is not to scale.
Table 11.
PMDIP32 – 32-pin plastic DIP, package mechanical data mm inches
Symb
Typ Min Max Typ Min Max
A
A1
B
C
D
L
S
N
9.27
0.38
0.43
0.20
42.42
3.05
1.91
32
9.52
–
0.59
0.33
43.18
0.365
0.015
0.017
0.008
1.670
0.120
0.075
32
0.375
–
0.023
0.013
1.700
E 18.03
18.80
0.710
0.740
e1 e3 38.1
2.29
2.79
1.5
0.090
0.110
Obsolete Product(s) - Obsolete Product(s) eA 14.99
16.00
0.590
0.630
3.81
2.79
0.150
0.110
PMDIP
16/20 Doc ID 5716 Rev 8
M48Z129V Part numbering
Table 12.
Ordering information scheme
Example: M48Z 129Y –70 PM
Device Type
M48Z
Supply voltage and write protect voltage
129V
(1)
= V
CC
= 3.0 to 3.6 V; 2.7 V
≤ V
PFD
≤ 3.0 V
Speed
–85 = 85 ns
Package
PM = PMDIP32
Temperature range
1 = 0 to 70 °C
1
Shipping method
blank = ECOPACK
®
package, tubes
1.
Device is not recommended for new design. Contact local ST sales office for availability.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Obsolete Product(s) - Obsolete Product(s)
Doc ID 5716 Rev 8 17/20
Environmental information
Figure 12.
Recycling symbols
M48Z129V
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations.
Obsolete Product(s) - Obsolete Product(s)
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M48Z129V Revision history
Table 13.
Document revision history
Date
Dec-1999
30-Mar-2000
20-Jun-2000
14-Sep-2001
29-May-2002
02-Apr-2003
18-Feb-2005
22-Apr-2010
23-Jun-2010
26-Sep-2011
Revision
1
2
2.1
3
3.1
4
5
6
7
8
Changes
First issue
From preliminary data to datasheet t
GLQX
changed for M48Z129Y (
Reformatted; temperature information added to tables (
,
Add countries to disclaimer
v2.2 template applied; test condition updated (
Reformatted; IR reflow update (
, footnote
of
; added Ecopack
®
text to
Section 7: Environmental information
; minor textual changes.
Devices are not recommended for new design (updated cover page,
); updated footnote of
Table 5: Absolute maximum ratings
updated
Section 7: Environmental information
Obsolete Product(s) - Obsolete Product(s)
Doc ID 5716 Rev 8 19/20
M48Z129V
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
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ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
Obsolete Product(s) - Obsolete Product(s)
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
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20/20 Doc ID 5716 Rev 8
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