STMicroelectronics LED1642GW Datasheet

LED1642GW

16 channel LED driver with error detection current gain control and

12/16-bit PWM brightness control

Datasheet

-

production data

Applications

•

Full color/monochrome large displays

•

LED signage

QSOP-24

TSSOP24

TSSOP24

(exposed pad)

Features

•

16 constant current output channels

•

Output current: from 3 mA to 40 mA

•

Current programmable through external resistor

•

7-bit global current gain adjustment in two ranges

•

12/16-bit PWM grayscale brightness control

•

Programmable output turn-on/off time

•

Error detection mode (both open and shorted-

LED)

•

Programmable shorted-LED detection thresholds

•

Auto power saving/auto-wakeup

•

Selectable SDO synchronization on the CLK falling edge

•

Gradual output delay (selectable)

•

Supply voltage: 3 V to 5.5 V

•

Thermal shutdown and overtemperature alert

•

30 MHz 4-wires interface

•

20 V current generator rated voltage

Description

The LED1642GW is a monolithic, low voltage, low current power 16-bit shift register designed for

LED panel displays. The LED1642GW guarantees 20 V output driving capability allowing the user to connect several LEDs in series. In the output stage, sixteen regulated current sources provide from 3 mA to 40 mA constant current to drive the LEDs. The current is programmed through an external resistor and can be adjusted by a 7-bit current gain register in two subranges.

The brightness can be adjusted separately for each channel through 12/16-bit grayscale control.

Programmable turn-on and turn-off time (four different values available) improves the low noise generation performance of the system.

Open/short error detection mode is available in the LED1642GW. The auto power-shutdown and auto power-on features (selectable) allow the device to save power without external intervention.

Thermal management includes an overtemperature data alert and output thermal shutdown (170 °C). The high clock frequency is up to 30 MHz and it makes the device suitable for high data rate transmission. A selectable gradual output delay reduces the inrush current, whereas the selectable SDO synchronization feature works when the device is used in daisy-chain configuration. The supply voltage range is between 3 V and 5.5 V.

November 2015

This is information on a product in full production.

DocID024395 Rev 6 1/42

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Contents

Contents

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10

LED1642GW

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Simplified internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.1

Equivalent circuits of inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . 15

Digital blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8.1

Gain control (from CFG 0 to 5) and current ranges (CFG- 6) . . . . . . . . . 19

8.2

Error detection mode (CFG-7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8.3

Error detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.4

Auto-wakeup/auto power shutdown (CFG-10) . . . . . . . . . . . . . . . . . . . . . 24

8.5

Programmable turn-on/turn-off time (CFG-11/12) . . . . . . . . . . . . . . . . . . 24

8.6

SDO delay (CFG-13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8.7

Gradual output delay (CFG-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.8

PWM counter setting and brightness register (CFG-15) . . . . . . . . . . . . . 27

Thermal flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Dropout voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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Contents

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

11.1

QSOP-24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

11.2

QFN-24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

11.3

TSSOP24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

11.4

TSSOP24 exposed pad package information . . . . . . . . . . . . . . . . . . . . . 37

11.5

TSSOP24 and TSSOP24 exposed pad packing information . . . . . . . . . . 39

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

DocID024395 Rev 6 3/42

42

List of tables

List of tables

LED1642GW

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Programmable TON/TOFF (output rise and fall time). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Digital key summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 9.

Example of current ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 10.

Gain steps for the current range selected by REXT = 11 kW . . . . . . . . . . . . . . . . . . . . . . . 20

Table 11.

Diagnostic thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 12.

Minimum dropout voltage for some current values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 13.

QSOP-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 14.

QFN-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 15.

TSSOP24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 16.

TSSOP24 exposed pad mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 17.

TSSOP24 and TSSOP24 exposed pad tape and reel mechanical data. . . . . . . . . . . . . . . 39

Table 18.

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 19.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4/42 DocID024395 Rev 6

LED1642GW

List of figures

List of figures

Figure 1.

TSSOP24, TSSOP24EP, QSOP-24 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2.

QFN-24 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3.

Typical chip-to-chip accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4.

Typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5.

Timing for clock, serial in, serial out, latch enable and outputs. . . . . . . . . . . . . . . . . . . . . . 14

Figure 6.

LED1642GW simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 7.

Input and output equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 8.

Digital keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 9.

Channel data and write switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 10.

Channel current vs. gain register value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 11.

Error detection action sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 12.

Error detection power-on timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 13.

Configuration register reading sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 14.

Configuration register reading sequence (zoom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 15.

Configuration register reading sequence - SDO delay actives . . . . . . . . . . . . . . . . . . . . . . 23

Figure 16.

Configuration register reading sequence - SDO delay actives (zoom) . . . . . . . . . . . . . . . . 23

Figure 17.

Output TON (current rise time) CFG -12 = CFG - 11 = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 18.

Output TOFF (current fall time) CFG - 2 = CFG - 11 = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 19.

Output TON (current rise time) CFG -12 = CFG - 11 = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 20.

Output TOFF (current fall time) CFG -12 = CFG - 11 = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 21.

SDO delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 22.

Gradual output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 23.

PWCLK counter and comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 24.

Brightness register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 25.

Thermal flag status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 26.

Typical channel dropout voltage vs. output current (VDD = 3.3 V). . . . . . . . . . . . . . . . . . . 30

Figure 27.

QSOP-24 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 28.

QFN-24 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 29.

TSSOP24 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 30.

TSSOP24 exposed pad outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 31.

TSSOP24 and TSSOP24 exposed pad tape and reel outline . . . . . . . . . . . . . . . . . . . . . . 39

DocID024395 Rev 6 5/42

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Pin description LED1642GW

Figure 1. TSSOP24, TSSOP24EP, QSOP-24 pinout

GND

SDI

CLK

LE

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

VDD

R-EXT

SDO

PWCLK

OUT15

OUT14

OUT13

OUT12

OUT11

OUT10

OUT9

OUT8

Figure 2. QFN-24 pinout

AM13686v1

6/42

LE

OUT0

OUT1

OUT2

OUT3

OUT4

1

24

23 22 21 20

19

18

2

3

4

17

16

15

5

14

6

13

7

8 9 10 11 12

PWCLK

OUT15

OUT14

OUT13

OUT12

OUT11

TSSOP24

TSSOP24EP

QSOP-24

4

5-20

21

1

2

3

QFN-24

22

23

24

1

2-17

18

Table 1. Pin description

Symbol Name and function

GND

SDI

CLK

Ground terminal

Serial data input terminal

Clock input terminal

LE Latch input terminal

OUT0-OUT15 Output terminals

PWCLK Clock input for PWM counter

DocID024395 Rev 6

AM13687V1

LED1642GW Absolute maximum ratings

TSSOP24

TSSOP24EP

QSOP-24

22

23

24

QFN-24

19

20

21

Table 1. Pin description (continued)

Symbol

SDO

R-EXT

VDD

Name and function

Serial data output terminal

Terminal for external resistor for constant current programming

Supply voltage terminal

Stressing the device above the ratings listed in the

Table 2

may cause the device permanent damage. Operating under conditions above those indicated in the operating section is not implied. Exposure to absolute maximum rating conditions for extended periods may affect the device reliability.

Symbol

V

DD

V

OUT

I

OUT

V i

I

GND

ESD

Table 2. Absolute maximum ratings

Parameter Value

Supply voltage

Output voltage

Output current

Input voltage

GND terminal current

Electrostatic discharge protection

HBM human body model

0 to 7

-0.5 to 20

50

-0.4 to V

DD

+0.4

1400

±2

Unit

V

V mA

V mA kV

DocID024395 Rev 6 7/42

42

Thermal characteristics LED1642GW

Symbol

T a

T

OPR

T

STG

R thj-amb

Table 3. Thermal characteristics

Parameter

Operative free-air temperature range

(1)

Operative junction temperature range

Storage ambient temperature range

QFN-24

(2)

Thermal resistance junction-ambient

TSSOP24

TSSOP24EP

QSOP-24

(2)

Value

-40 to +85

-40 to +125

-55 to +150

30

85

37.5

72

Unit

°C

°C/W

1.

This data must be considered in adequate power dissipation conditions, the junction temperature must be maintained below 125 °C.

2.

The exposed pad should be soldered directly to the PCB to get the thermal benefits. The exposed pad can be attached to a metal land electrically isolated or connected to ground.

Symbol

V

DD

V

OUT

V

IH

V

IL

V

OL

V

OH

I

Oleak

V uvlo

Hy uvlo

V

DD

= 3.3 V, T j

= 25 °C, unless otherwise specified.

Parameter

Table 4. Electrical characteristics

Conditions

Supply voltage

Output voltage

Input voltage

Serial data output voltage

(SDO)

Output leakage current

UVLO threshold (rising)

UVLO threshold (falling)

UVLO hysteresis

Out 0 - out 15

V

DD

= 3 to 5.5 V

I = +/- 1 mA

V

OUT

= 19 V, all outputs OFF

Min.

3

-

0.7 x V

DD

GND

-

V

DD

-0.4

-

2.2

Typ.

Max.

Unit

-

2.7

2.3

400

-

5.5

19

-

-

V

DD

0.3 x V

DD

0.4

-

0.5

2.9

V

µA

V mV

8/42 DocID024395 Rev 6

LED1642GW Electrical characteristics

Symbol

∆

I

OL1

∆

I

OL2

∆

I

OL3

∆

I

OL2a

%/dV

OUT

%/dV

DD

Rup

Rdw

R

EXT

I

DD

(OFF1)

I

DD

(ON1)

I

DD

(ON2)

Table 4. Electrical characteristics (continued)

Parameter Conditions Min.

Output current precision channel-to-channel

(all outputs ON)

(1)(2)

Output current precision device-to-device

(all outputs ON)

(1)

Output current vs. output voltage regulation

(3)

Output current vs. supply voltage regulation

(4)

V

OUT

= 0.1 V; (I

OUT

= 3 mA)

R

EXT

= 11 k

Ω

CFG-0…CFG-5= “000000”

CFG-6 = “0”

V

OUT

= 0.5 V; (I

OUT

= 20 mA)

R

EXT

= 11 k

Ω

CFG-0…CFG-5 = “011010”

CFG-6 = “1”

V

OUT

= 0.8 V; (I

OUT

= 36 mA)

R

EXT

= 11 k

Ω

CFG-0…CFG-5 = “111111”

CFG-6 = “1”

V

OUT

= 0.5 V; (I

OUT

= 20 mA)

R

EXT

=1 1 k

Ω

CFG-0…CFG-5 = “011010”

CFG-6 = “1”

V

OUT from 1 V to 3 V; (I

OUT

36 mA) R

EXT

= 11 k

Ω

=

CFG-0…CFG-5 = “111111”

CFG-6 = “1”

V

DD

from 3 V to 5.5 V

V

OUT

= 0.8 V; (I

OUT

= 36 mA)

R

EXT

= 11 k

Ω

CFG-0…CFG-5 = “111111”

CFG-6 = “1”

-

-

-

-

-

-

Pull-up resistor for PWCLK pin

Pull-down resistor for LE pin

External current setup resistance

400

400

Supply current (OFF)

Supply current (ON)

R

EXT

= 11 k

Ω

OUT 0 to 15 = OFF

CFG = default

R

EXT

= 11 k

Ω

; I

OUT

= 20 mA

OUT 0 to 15 = ON

CFG-0…CFG-5 = “011010”

CFG-6 = “1”

R

EXT

= 11 k

Ω

; I

OUT

= 36 mA

OUT 0 to 15 = ON

CFG-0…CFG-5 = “111111”

CFG-6 = “1”

-

-

-

Typ.

Max.

Unit

-

-

-

-

±0.1

±1

500

500

-

±4

±3

±3

±6

-

-

600

600

100

6

8

10

%

%

%/V

K

Ω mA

DocID024395 Rev 6 9/42

42

Electrical characteristics LED1642GW

Symbol

I

DD

(auto

OFF)

Table 4. Electrical characteristics (continued)

Parameter Conditions Min.

Supply current (auto OFF)

R

EXT

= 11 k

Ω

;

OUT 0 to 15 = OFF

CFG-0…CFG-5 = “111111”

CFG-6 = “1”

-

T flg

T sd

Thermal flag

Thermal shutdown

(5)

T sd-hy

Thermal shutdown hysteresis

(5)

1.

Tested with just one output loaded.

2.

((Ioutn - Ioutavg1-15)/ Ioutavg1-15) x 100.

3.

Δ

(% / V )

=

( Ioutn @ Voutn

=

3

( Ioutn

.

0 V

@

)

−

( Ioutn @ Voutn

Voutn

=

1 .

0 V )

=

1 .

0 V )

×

100

3

−

1

4.

Δ

(% / V )

=

( Ioutn @ V dd

(

=

5 .

5 V )

Ioutn @

−

( Ioutn

V dd

=

3 .

0

@

V )

V dd

=

3 .

0 V )

×

5 .

100

5

−

3

Typ.

200

150

170

15

5.

Not tested, guaranteed by design.

Max.

500

20

Unit

µA

°C

Figure 3. Typical chip-to-chip accuracy

V

DD

C

4

3.5

3

2.5

2

1.5

1

0.5

0

0 5 10 15 20

I

OUT

(mA)

25 30 35 40

AM13688V1

10/42 DocID024395 Rev 6

LED1642GW Electrical characteristics

+

Cled

Figure 4. Typical application schematic

LED common rail voltage

…..

Supply voltage

Cin

VDD

OUT0 OUT1

OUT15

LED1642GW

R-EXT

GND

Current setting resistor

SDI

CLK

LE

PWCLK

SDO

Data loaded through serial interface

Data output

AM13689V1

DocID024395 Rev 6 11/42

42

Switching characteristics LED1642GW

Symbol

f clk f pwclk tr

(SDO) tf

(SDO) tPLHLE tPLH tPHLLE tPHL tw(CLK) t

W

(PWCLK) tw(L) t gr-d t su(L) t h(L) t su(D) t h(D) tclkr

(3) tclkf

(3)

V

DD

= 3.3 V, T j

= 25 °C, unless otherwise specified.

Table 5. Switching characteristics

(1)

Parameter Conditions

Clock frequency

PWclock frequency

Cascade operation

SDO rise time

SDO fall time

R

EXT

= 11 k

Ω

; I

OUT

= 20 mA

V

OUT

= 0.8 V

VIH = V

DD

; VIL = GND

RL = 3.3 K

Ω

; CL = 10 pF

CFG-0…CFG-5 = “011010”

CFG-6 = “1”

LE - OUTn

(2)

CLK - SDO

CFG-13 = ‘0’

LE - OUTn

(2)

Propagation delay time

(“L to “H”)

CLK - SDO

CFG-13 = ‘0’

CLK

PWCLK

Propagation delay time

(“H” to “L”)

Pulse width

LE

Gradual delay ch-to-ch

Setup time for LE

Hold time for LE

Setup time for SDI

Hold time for SDI

Maximum CLK rise time

Maximum CLK fall time

R

EXT

= 11 k

Ω

; I

OUT

= 20 mA

V

OUT

= 0.8 V

VIH = V

DD

; VIL = GND

RL = 5

0

Ω

; CL = 10 pF

CFG-0…CFG-5 = “011010”

CFG-6 = “1”

I out-ov

Output current turn-on overshoot

V

OUT

= 0.6 to 3 V

CL = 10 pF; I

OUT

= 3 to 36 mA t n-err

Normal error detection minimum output ON time

Min.

Typ.

Max.

Unit

-

-

-

30

30

MHz

-

-

-

8

-

8

10

-

-

5

5

5

20

20

20

-

-

5

5

200

15

100

15

-

10

-

-

-

-

-

-

-

-

-

-

-

5

5

-

-

-

-

-

-

-

-

-

25

-

25

10

1 ns

µs

%

µs

12/42 DocID024395 Rev 6

LED1642GW Switching characteristics

Table 5. Switching characteristics

(1)

Parameter Conditions Symbol Min.

Typ.

Max.

Unit

t shutdown t wakeup

Auto power shutdown time (auto OFF)

Auto-wakeup

From LE falling edge to R

EXT voltage reference at -10%

From LE falling edge to R

EXT voltage reference at 90%

-

100

3 -

-

1.

Not tested in production. All table limits are guaranteed by design.

2.

CFG -11= 0 and CFG -12 = 0 (output tr = 30 ns; output tf = 20 ns); CFG-14=1 (no output gradual delay).

3.

If devices are connected in cascade and tclkr or tclkf is large, it may be critical to achieve the timing required for data transfer between two cascaded devices.

ns

µs

Configuration bits

(CFG-12 - CFG-11)

Table 6. Programmable T

ON

/T

OFF

(output rise and fall time)

Typ . (20% to 80%)

Conditions

Turn-on Turn-off

0 - 0

0 - 1

1 - 0

1 - 1

R

EXT

= 11 k

Ω

; I

OUT

= 20 mA

V

OUT

= 0.8 V

VIH= V

DD

; VIL= GND

RL = 5

0

Ω

; CL=10pF

CFG-0...CFG-5=“011010”

CFG-6 = “1”

30 ns

100 ns

140 ns

180 ns

20 ns

40 ns

80 ns

150 ns

Unit

ns

DocID024395 Rev 6 13/42

42

Switching characteristics LED1642GW

Figure 5. Timing for clock, serial in, serial out, latch enable and outputs

t pLHLE

, t pHLLE

AM13690V1

The correct sampling of the data depends on the stability of the data at SDI on the rising edge of the clock signal and it is assured by a proper data setup and hold time (t

SU(D)

and t h(D)

), as shown in

Figure 5

. The same figure shows the propagation delay from CLK to SDO

(t

PLH

/t

PHL

).

Figure 5

describes also the minimum duration of CLK, LE pulses (t

W(CLK)

) and t

W(L) respectively and the propagation delay from LE to OUT n

(t

PLHLE

and t hypothesis that all channels have already been enabled by PWM counter.

PHLLE

) in the

14/42 DocID024395 Rev 6

LED1642GW

6 Simplified internal block diagram

Simplified internal block diagram

SDI

CLK

LE

V

DD

GND

Figure 6. LED1642GW simplified block diagram

SDO

PWCLK

Control Logic &

Data Registers

PWM counter

UVLO

& POR

Configuration register

Error detection

Thermal shutdown

OUT0

OUT1

OUT2

R-EXT

Current

Ref.

Current gain adjustment

Channel driver

Timing control

Turn ON/OFF

Gradual delay

OUT14

OUT15

6.1

AM13691V1

Equivalent circuits of inputs and outputs

LE and PWCLK input terminals have pull-down and pull-up connection respectively. CLK and SDI must be connected to the external circuit to fix the logic level.

Figure 7. Input and output equivalent circuits

PWCLK terminal LE terminal

CLK, SDI terminal SDO terminal

DocID024395 Rev 6

AM13692V1

15/42

42

Digital blocks LED1642GW

The data input arrives through the serial Interface at each CLK rising edge. The LE signal is used to latch the loaded data and also to address data loading to the appropriate register, thermal flag reading and error detection. The access to the different registers or functions of the device (configuration register, brightness register or current gain, error detection, etc.) is achieved by using different digital keys, defined as a number of CLK pulses during which the

LE signal is asserted. The available digital keys are listed in

Table 7

and

Figure 8

. A typical

channel data input is shown in

Figure 9

.

Table 7. Digital key summary

Number # CLK rising edge when the LE is “1” Command description

3

4

5

1

2

6

7

8

9

10

11

12

1 – 2

3 – 4

5 – 6

7

8

9

10

11

12

13

14

15

Write switch (to turn on/off output channels)

Brightness data latch

Brightness global latch

Write configuration register

Read configuration register

Start open error detection mode

Start short error detection mode

Start combined error detection mode

End error detection mode

Thermal error reading

Reserved

Reserved

16/42 DocID024395 Rev 6

LED1642GW

Figure 8. Digital keys

CLK

LE

LE

LE

LE

LE

LE

LE

LE

LE

LE

Write switch

Data latch

Global latch

Write CR

Read CR

Start open error detection

Start short error detection

Start combined detection

End error detection

Thermal error reading

Figure 9. Channel data and write switch

SDI

CLK

LE

0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00

16-bit data

Digital blocks

AM13693V1

AM13694V1

DocID024395 Rev 6 17/42

42

Configuration register LED1642GW

The configuration register is used to enable or disable some device features, to program some parameters and to change other settings. The access to this register (read or write) is managed to find a description for each bit as described in

Table 8

. The default value of the configuration register (when the device is switched on or after a reset) is "0" for all bits. To change anything in the configuration register, a 16-bit digital word must be sent (CFG - 0 represents LSB, CFG -15 the MSB).

Bit

CFG-0

CFG-1

CFG-2

CFG-3

CFG-4

CFG-5

CFG-6

CFG-7

CFG-8

CFG-9

CFG-10

CFG-11

CFG-12

CFG-13

Definition

Current gain adjustment

R/W

R/W

Table 8. Configuration register

Description

6-bit DAC allows adjusting the device output current in 64 steps for each range (defined by CFG-6)

Current range R/W

Error detection mode

Shorted-LED detection thresholds

Auto OFF shutdown

Output turnon/off time

SDO delay

R/W

R/W

R/W

R/W

R/W

R/W

R/W

”0” low current range

“1” high current range

“0” normal mode

“1” reserved mode

CFG-9 CFG-8 Th. volt.

0 0 1.8 V

Programmable output shorted-LED detection thresholds

0

1

1

0

2.5 V

3 V

1 1

“0” device always ON

”1” auto power shutdown active (auto OFF)

3.5 V

Programmable output rise and fall time (20% to 80%)

0

0

1

CFG-12 CFG-11 Turn-on Turn-off

0 30 ns 20 ns

1

0

100 ns

140 ns

40 ns

80 ns

1 1 180 ns 150 ns

If “0” no delay is present on SDO

If “1” the data are shifted out and they are synchronized with the falling edge of the CLK signal

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

18/42 DocID024395 Rev 6

LED1642GW Configuration register

Bit

CFG-14

CFG-15

Definition

Gradual output delay

12/16 PWM counter

Table 8. Configuration register (continued)

R/W Description

R/W

R/W

“0” a progressive delay is applied to output (10 ns per channel)

”1” no delay is applied to output

“0” to select 16-bit brightness register (65536 grayscale rightness steps).

“1” to select 12-bit brightness register (4096 grayscale brightness steps)

Default

0

0

8.1 Gain control (from CFG 0 to 5) and current ranges (CFG- 6)

The LED current can be programmed using an external resistor connected to GND from

R

EXT

pin and can be fixed using the dedicated bits of the configuration register (from CFG -

0 to CFG - 5 bits define the gain, while CFG - 6 bit defines the current range within the which the gain can be adjusted). The device can regulate the current up to 36 mA and down to 0.5 mA. The accuracy of the LED current depends on the selected range and it is guaranteed in

the ranges indicated in the static electrical characteristics only (see

Table 3

and

9

). When the device is switched on, the selected current range and the resistor connected to the R

EXT pin fix the default LED current:

I

OL

_

default

=

V

REF

R

EXT

⋅

K

Where V

REF

=

1.23 V is the voltage of the R

EXT

pin and K is the mirroring current ratio, whose value depends on the selected current range:

•

K = 28 with low current range selected (CFG - 6 = "0")

•

K = 80 with high current range selected (CFG - 6 = "1")

The relation between the programmed current and the current gain settings is the following:

I

OL

=

(

I

OL

_

default

+

G

⋅ Δ

I ste p

) where G is the current gain value (decimal value) defined by the dedicated bits of the current gain register. The current gain is managed by 6-bits of the configuration register

(CFG - 0 to CFG - 5, CFG - 0 is LSB and CFG - 5 is MSB) and can be adjusted within two ranges (selectable through the bit CFG - 6) over 64 steps. The width of each step depends on the default current (I ol_default

) as well as the selected R

EXT

. Finally, each step is as follows:

DocID024395 Rev 6 19/42

42

Configuration register LED1642GW

Δ

I st e p

=

I

O L

_ d e fa u lt

21

The

Table 9

shows an example of the current setting with an external resistance (R

EXT

K

Ω

:

) = 11

Low range

High range

Table 9. Example of current ranges

R

EXT

[K

Ω

] CFG-6 CFG-0 to CFG-5 LED current

(1)

[mA]

11

11

0

0

000000

111111

3.1 mA

12.5 mA

11

11

1

1

000000

011010

8.9 mA

20 mA

1.

The indicated values may be slightly different on the current device.

Accuracy

± 4% ch-to-ch

-

± 3% ch-to-ch

The

Table 10

shows an example of current setting and gain control with R

EXT

= 11 k

Ω

, see

also

Figure 10

.

Table 10. Gain steps for the current range selected by R

EXT

= 11 k

Ω

CFG-6 CFG(0 to 5) LED current

(1)

[mA]

Low range

High range

1

…

0

1

0

0

…

000000

000001

…

111111

000000

000001

…

1 111111

1.

The indicated values may be slightly different on the current device.

3.131

3.280

…

12.524

8.945

9.371

…

35.78

The external programming resistance must be connected as close as possible to the related device pins (R

EXT

and GND) to reduce as minimum as possible the routing length and prevent reference noise injection and electromagnetic interferences. Moreover, a direct connection to the device GND pin reduces the possible output current variation when the total device ground current changes (load effect).

20/42 DocID024395 Rev 6

LED1642GW

8.2

Configuration register

Figure 10. Channel current vs. gain register value

I

OUT

vs. gain

(R = range selection, R

EXT

= 11 K or 18 K)

40.0

35.0

30.0

25.0

20.0

15.0

10.0

5.0

0.0

0

11 K R=0

11 K R=1

18 K R=0

18 K R=1

5 10 15 20 25 30 35 40 45

Gain register decimal value

50 55 60 65 70

AM13695V1

Error detection mode (CFG-7)

Stopping the normal activity of the display and turning on all driver channels allows the error detection to be performed and failed LED or display defects to be checked.

The error detection is active when the CFG -7 bit of the configuration register is "0". The diagnostics is performed as shown in

Figure 11

:

•

The LED has to be selected turning on the relative channel on the switch register

(powering on or off the output channels); the brightness register value for this channel cannot be zero.

•

The normal error detection has to be selected in the configuration register (CFG-7=

"0"). The appropriate digital key to choose the type of detection (open, short or

combined) must be sent (see

Table 7

).

•

After the error detection starts, the channel under testing has to be turned on at least 1

μ s (the LED is at the nominal current). Please note that, the output power-on depends on PWCLK signal and in several applications this signal is not synchronized with the serial interface clock (CLK pin). Therefore, to be sure that, between the detection start and the detection end, the output power-on is 1

μ s and moreover, that last power-on, in the interval, starts at least 0.5

μ s before the detection end pattern (see

Figure 12

), it is

suggested that the error detection should be performed just after the device startup

(brightness counter reset) with all channels ON, before applying PWCLK signal.

•

The result of the detection ("0" indicates a fault condition) is shifted out SDO, in 16 clock pulses after the "detection end command" is provided, first output bit represents channel 15 (error data can be read in a way similar to configuration register data

reading as shown on

Figure 13

,

14

,

15

and

16

).

Please note that (with SDO delay off) output 15 detection result will be available just after

1st clock pulse rising edge, so it can be sampled on the rising edge of second clock pulse. In the same way output 0 detection result will be available just after 16th clock pulse rising edge, so it can be sampled on the rising edge of 17th CLK pulse.

DocID024395 Rev 6 21/42

42

Configuration register

Figure 11. Error detection action sequence

Normal detection sequence

Select LED to be turned on and

checked in switch register data; brightness for selected channels cannot be zero.

Select normal error detection mode on CFG register (bit 7 = “0”)

Send open, short or combined error detection start command by LE digital keys

Turn on LED by PWCLK pulses for at least 1 µ s

Send error detection end command by LE digital key

Read error detection result on

SDO in 16 clock pulses after detection end command

Figure 12. Error detection power-on timing

x0000 < BRT < xFFFF

Output Current

SPI pattern

Det.

Start

1us

0.5us

Det.

End

It must contain 1us output power ON

LED1642GW

AM13696V1

AM13697V1

22/42 DocID024395 Rev 6

LED1642GW Configuration register

Figure 13. Configuration register reading sequence

C1=CLK

C2=SDI

C3=LE

C4=SDO

First CLK pulse after CFG Reg reading command

CFG Reg programming CFG Reg reading command CFG Reg data

Figure 14. Configuration register reading sequence (zoom)

C1=CLK

C2=SDI

C3=LE

C4=SDO

CFG Reg data

First CLK pulse after CFG Reg reading command

Figure 15. Configuration register reading sequence - SDO delay actives

C1=CLK

C2=SDI

C3=LE

C4=SDO

Sync. change First CLK pulse after CFG Reg reading command

CFG Reg programming CFG Reg reading command CFG Reg data

CFG13=1

Figure 16. Configuration register reading sequence - SDO delay actives (zoom)

C1=CLK

C2=SDI

C3=LE

C4=SDO

CFG Reg data

First CLK pulse after CFG Reg reading command

DocID024395 Rev 6 23/42

42

Configuration register

8.3

LED1642GW

Error detection conditions

During the error detection phases for each channel, the following checks have to be performed:

– The output current in open detection mode (digital key: 9 CLK rising edges when

LE is "1")

– The output voltage in short detection (digital key: 10 CLK rising edges when LE is

"1")

– Both parameters (output voltage and current) in combined error detection mode

(digital key: 11 CLK rising edges when LE is "1").

The thresholds for the error diagnostics are listed in

Table 11

:

Error detection modes

Open detection

Short detection

Table 11. Diagnostic thresholds

Checked malfunction

Open line or output short to GND

Short on LED or short to V-LED

CFG-9 CFG-8

x

0

0

1

1 x

0

1

0

1

1.15

2.25

2.75

3.25

Min.

-

Thresholds (V)

Typ.

I

OUT

≤

0.5 x I

OUT programmed

V

OUT

≥

1.8

V

OUT

≥

2.5

V

OUT

≥

3.0

V

OUT

≥

3.5

Max.

-

2.05

2.75

3.25

3.80

8.4

8.5

Auto-wakeup/auto power shutdown (CFG-10)

This feature reduces the power consumption when all outputs are OFF. It is active when the

CFG -10 bit of configuration register is "1". The auto power shutdown (auto OFF) starts when the data latched is "0" for all channels, and device is active again (wakeup) at the first latched data string including at least one bit = "1" (at least one channel ON). Timings for shutdown and wakeup are present in the dynamics feature table. While the auto power shutdown is active, the device ignores any other command except the channel power-on.

Programmable turn-on/turn-off time (CFG-11/12)

The device gives the possibility to program the turn-on and turn-off time of the current generators. Four different values can be selected using CFG -12 and CFG-11 bits of the

configuration register (see

Table 8

) to fit the application requirements: 30/20 ns (00), 100/40

ns (01), 140/80 ns (10) and 180/150 ns (11). The selected value refers to T

ON

(current rise time) and T

OFF

(current fall time).

24/42 DocID024395 Rev 6

LED1642GW Configuration register

Figure 17. Output T

ON

(current rise time) CFG -

12 = CFG - 11 = 0

Figure 18. Output T

OFF

(current fall time) CFG -

2 = CFG - 11 = 0

AM13698V1

AM13699V1

Figure 19. Output T

ON

(current rise time) CFG -

12 = CFG - 11 = 1

Figure 20. Output T

OFF

(current fall time) CFG -

12 = CFG - 11 = 1

8.6

AM13700V1 AM13701V1

SDO delay (CFG-13)

Usually in SDO terminal, data are shifted out the rising edge of CLK signal (with a propagation delay of about 15 ns - signal (a) in

Figure 21

). The device has the possibility to

shift data out the falling edge of the CLK signal (with few ns of propagation delay - signal (b) in

Figure 21

). This feature is active when CFG -13 bit of the configuration register is "1".

Default setting for this bit is "0" hence the SDO delay is not activated by default. This feature is particularly useful when some devices are connected in daisy chain configuration with mismatched propagation delays, between CLK and SDO data path (board routing).

DocID024395 Rev 6 25/42

42

Configuration register

Figure 21. SDO delay

LED1642GW

(a)

(b)

8.7

(a) Data shifted out of the SDO with the device propagation delay

(b) Data shifted out of the SDO by the falling edge of the CLK

AM13702V1

Gradual output delay (CFG-14)

The gradual output delay consists of turning on gradually the current generators avoiding to turn on all channels at the same time.

When PWM counter enables the device channels, the outputs can be turned on simultaneously or with a progressive delay. Thanks to configuration register CFG -14 bit, the user can decide to put a delay among outputs (10 ns from each channel to the next one, around 150 ns between first and last channel). The typical output timing is shown in

Figure 22

. This feature prevents the inrush current and reduces the bypass capacitor value.

26/42 DocID024395 Rev 6

LED1642GW

Figure 22. Gradual output delay

Configuration register

8.8

AM13703V1

PWM counter setting and brightness register (CFG-15)

The brightness of each channel can be adjusted through a 12/16-bit PWM grayscale brightness control according to the PWM counter selection (configuration register CFG -15 bit). Brightness data is loaded by the SDI pin in a 16-bit shift register. Once 16-bit has been loaded (first input bit of brightness word is MSB, 16 th

bit is LSB), the digital word is moved to the corresponding temporary buffer (first word is the brightness of channel 15, the last one

is for channel 0) using the appropriate key shown in

Table 7

("data latch"). One "data latch" key must follow each 16-bit brightness word except the last one. When the last brightness

word is loaded (channel 0 brightness data), the key indicated as "global latch" in

Table 7

must be used. This action moves the word from the shift register to the temporary buffer through the OUT0 and, at the same time, transfers all data of the 16 temporary buffers (16 x16-bit string) to the corresponding brightness registers (see also

Figure 28

).

The PWM signals are generated by comparing the content of the brightness registers to a

16-bit or 12-bit counter, according to the CFG-15 bit status. The counter's clock source is provided to the PWCLK pin. In case of selection of 12-bit PWM counter, the four most significant bits of each brightness data word are ignored. However, each of sixteen brightness data words must be 16-bit long.The brightness register default value is "0", unless this value is changed, the LED brightness is minimum.

Figure 27

shows this function

in the schematic.

PWCLK must be a square wave signal, duty cycle is not important but the minimum width has to be above 20 ns, max. frequency has to be 30 MHz (pay attention the minimum output

ON time). Just after the device startup (brightness counter reset), before applying PWCLK signal, all channels are in power-on condition if the brightness register values are not zeroed.

DocID024395 Rev 6 27/42

42

Configuration register

Figure 23. PWCLK counter and comparator

LED1642GW

28/42

AM13704V1

Figure 24. Brightness register setting

SDI

CLK

LE

0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02

01

00

Data latch

16-bit Data Word

BRT15 BRT14 BRT13 BRT03 BRT02 BRT01 BRT00

256-bit brightness data stream

MSB

0F 0E 0D 0C 0B 0A

LSB

09 08 07 06 05 04 03 02 01 00

SDI

CLK

LE

Global latch

AM13705V1

DocID024395 Rev 6

LED1642GW Thermal flag

The device has a thermal control logic providing a flag status when the internal temperature exceeds 150 °C (if temperature increases over 170 °C a thermal shutdown protects the device). This status can be read running the digital key "thermal error reading", holding the

LE high for 13 CLK rising edges (see

Figure 25

). If thermal alert is asserted, a 16-bit string =

"1" is sent by SDO. The error data is uploaded into EDR register and this error notification is ready to be streamed through SDO to next 16 CLK rising edges. Hence, thermal flag status can be:

Device temperature

under 150 °C over 150 °C

SDO

“0000 0000 0000 0000”

“1111 1111 1111 1111”

Figure 25. Thermal flag status

13 Clock pulses with LE asserted

Previous data

Thermal

Flag Status

AM13706V1

DocID024395 Rev 6 29/42

42

Dropout voltage LED1642GW

In order to correctly regulate the channel current, a minimum output voltage (V

DROP

) across each current generator must be guaranteed.

The

Figure 26

and

Table 12

show the minimum V

DROP

related to the regulated current; these measurements have been recorded with just one output ON. When more than one output is active the drop voltage increases. At 36 mA per channel, the minimum output voltage must be increased about 200 mV.

A V

DROP

, lower than the minimum recommended, implies the regulation of a current lower than the expected one. However an excess of V

DROP

increases the power dissipation.

Figure 26. Typical channel dropout voltage vs. output current (V

DD

= 3.3 V)

Drop vs. I

OUT

@ V

DD

= 3.3 V, T= 25 °

(only one channel ON)

1200

1000

800

600

400

200

0

0 5 10 15 20 25

I

OUT

[mA]

30 35 40 45 50 55

AM13707V1

Table 12. Minimum dropout voltage for some current values

Output current [mA]

3

9

12

20

36

40

45

50

Minimum V

DROP

@ V

DD

= 3.3 V [mV]

70

180

250

410

730

820

955

1070

30/42 DocID024395 Rev 6

LED1642GW Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at:

www.st.com

.

ECOPACK

®

is an ST trademark.

DocID024395 Rev 6 31/42

42

Package information

11.1 QSOP-24 package information

Figure 27. QSOP-24 package outline

LED1642GW

32/42 DocID024395 Rev 6

LED1642GW Package information

Table 13. QSOP-24 mechanical data mm

Dim.

Min.

A 1.54

A1 0.1

Typ.

1.62

0.15

Max.

1.73

0.25

b 0.31

c 0.254

D 8.56

E 5.8

E1 3.8

0.2

0.17

8.66

6

3.91

8.76

6.2

4.01

L 0.4

h 0.25

0.635

0.33

0.89

0.41

< 8° 0°

DocID024395 Rev 6 33/42

42

Package information

11.2 QFN-24 package information

Figure 28. QFN-24 package outline

LED1642GW

34/42 DocID024395 Rev 6

LED1642GW

Dim.

D

D2

E

E2 e

L

A

A1

A3 b

Table 14. QFN-24 mechanical data mm

Min.

0.80

0

0.18

3.85

2.00

3.85

2.00

0.30

Typ.

4.00

2.15

4.00

2.15

0.50

0.40

0.90

0.02

0.20

0.25

Package information

Max.

1.00

0.05

0.30

4.15

2.25

4.15

2.25

0.50

DocID024395 Rev 6 35/42

42

Package information

Figure 29. TSSOP24 package outline

LED1642GW

36/42

Table 15. TSSOP24 mechanical data mm

Dim.

Min.

Typ. Max.

A 1.1

A1 0.05 0.15

A2 0.9 b 0.19 c 0.09

D 7.7

E 4.3

0.30

0.20

7.9

4.5

H 6.25

K 0°

L 0.50

6.5

8°

0.70

DocID024395 Rev 6

LED1642GW

11.4 TSSOP24 exposed pad package information

Figure 30. TSSOP24 exposed pad outline

Package information

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Package information

Dim.

b c

D

D1

E

A

A1

A2

E1

E2 e

L

L1 k aaa

LED1642GW

Table 16. TSSOP24 exposed pad mechanical data mm

Min.

Typ.

0.80

0.19

0.09

7.70

4.80

6.20

4.30

3.00

0.45

1.00

7.80

5.00

6.40

4.40

3.20

0.65

0.60

1.00

Max.

1.20

0.15

1.05

0.30

0.20

7.90

5.20

6.60

4.50

3.40

0.75

0 8

0.10

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LED1642GW Package information

11.5 TSSOP24 and TSSOP24 exposed pad packing information

Figure 31. TSSOP24 and TSSOP24 exposed pad tape and reel outline

Table 17. TSSOP24 and TSSOP24 exposed pad tape and reel mechanical data mm

Dim.

Min.

Typ.

Max.

A -

C 12.8 -

D 20.2 -

N 60 -

T -

Ao 6.8 -

Bo 8.2 -

Ko 1.7 -

Po 3.9 -

P 11.9 -

330

13.2

22.4

7

8.4

1.9

4.1

12.1

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Ordering information LED1642GW

Order code

LED1642GWPTR

LED1642GWQTR

LED1642GWTTR

LED1642GWXTTR

Table 18. Ordering information

Package

QSOP-24

QFN-24

TSSOP24

TSSOP24 exposed pad

Packing

2500 parts per reel

4000 parts per reel

2500 parts per reel

2500 parts per reel

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LED1642GW Revision history

Date

03-May-2013

06-Jun-2013

19-Aug-2013

18-Mar-2014

16-Jun-2014

16-Nov-2015

Table 19. Document revision history

Revision Changes

1

2

3

4

5

6

Initial release.

Updated Table 2: Absolute maximum ratings, Figure 10:

Channel current vs. gain register value and Section 8.2:

Error detection mode (CFG-7).

Added Figure 13, 14, 15 and 16.

Minor text changes.

Updated the Title, the Features and the Description.

Modified Table 4: Electrical characteristics,

Updated Table 9: Example of current ranges, Table 10:

Gain steps for the current range selected by REXT = 11 kW, Section 8.2: Error detection mode (CFG-7),

Section 8.8: PWM counter setting and brightness register (CFG-15).

Added footnote 1 in Table 5: Switching characteristics and footnote 5 in Table 4: Electrical characteristics.

Updated Table 16: TSSOP24 exposed pad mechanical data.

Minor text changes.

Modified footnote 2 in

Table 3: Thermal characteristics

.

Minor text changes.

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LED1642GW

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