STMicroelectronics STP16CPC26 Datasheet

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STP16CPC26

Low voltage 16-bit constant current LED sink driver

Datasheet - production data

Features



16 constant current output channels



Adjustable output current through external resistor



Output current: 5 mA to 90 mA



±1% typical current accuracy bit to bit



Max clock frequency: 30 MHz



20 V current generators rated voltage



3 - 5.5 V power supply



Thermal shutdown for overtemperature protection

Applications



Video display panel LED driver



Special lighting

Order code

STP16CPC26MTR

STP16CPC26TTR

STP16CPC26XTR

STP16CPC26PTR

Table 1: Device summary

Package

SO-24

TSSOP24

TSSOP24 exposed pad

QSOP-24

Description

The STP16CPC26 is a monolithic, low voltage,

16-bit constant current LED sink driver. The device contains a 16-bit shift register and data latches, which convert serial input data into parallel output format. In the output stage sixteen regulated current generators provide 5 mA to

90 mA constant current to drive LEDs. The current is externally adjusted through a resistor.

LED brightness can be adjusted from 0% to

100% via OE pin.

The STP16CPC26 guarantees a 20 V driving capability, allowing users to connect more LEDs in series to each current source.

The high 30 MHz clock frequency makes the device suitable for high data rate transmission.

The thermal shutdown (170 °C with about 15 °C hysteresis) assures protection from overtemperature events.

The STP16CPC26 is housed in four different packages: QSOP24, SO-24, TSSOP-24 and

HTSSOP-24 (with exposed pad).

Packing

1000 parts per reel

2500 parts per reel

April 2017 DocID18469 Rev 6

This is information on a product in full production.

1/28 www.st.com

Contents

STP16CPC26

1 Pin description ................................................................................ 3

2 Electrical ratings ............................................................................. 4

2.1

2.2

Absolute maximum ratings ................................................................ 4

Thermal data ..................................................................................... 4

3 Electrical characteristics ................................................................ 5

4 Simplified internal block diagram .................................................. 8

5 Typical application circuit ............................................................... 8

6 Equivalent circuit and outputs ....................................................... 9

7 Typical test circuits ....................................................................... 11

8 Timing diagrams ............................................................................ 12

9 Current generators characteristics .............................................. 15

9.1

9.2

9.3

Current setting ................................................................................. 15

Current accuracy ............................................................................. 15

Generators voltage drop ................................................................. 16

10 Thermal shutdown ......................................................................... 16

11 Package information ..................................................................... 17

11.1

QSOP-24 package information ....................................................... 18

11.2

SO-24 package information ............................................................ 20

11.3

TSSOP24 package information ....................................................... 21

11.4

TSSOP24 exposed pad package information ................................. 23

11.5

TSSOP24, TSSOP24 exposed pad and ............................................

SO-24 packing information .............................................................. 25

12 Revision history ............................................................................ 27

2/28 DocID18469 Rev 6

STP16CPC26

1 Pin description

Figure 1: Pin connection

Pin description

The exposed-pad (if present) should be electrically connected to a metal land electrically isolated or connected to ground.

Pin n° Symbol

Table 2: Pin description

Name and function

GND

SDI

CLK

Ground terminal

Serial data input terminal

Clock input terminal

Latch input terminal

5-20 OUT 0-15 Output terminal

SDO

R-EXT

Input terminal of output enable (active low)

Serial data out terminal

Input terminal for an external resistor for constant current programming

Supply voltage terminal

DocID18469 Rev 6 3/28

Electrical ratings

2

2.1

2.2

Electrical ratings

STP16CPC26

GND

ESD f

CLK

Absolute maximum ratings

Stressing the device above the rating listed in the “absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Symbol

Table 3: Absolute maximum ratings

Parameter Value Unit

Supply voltage

Output voltage

Output current

Input voltage

GND terminal current

Electrostatic discharge protection HBM human body model

Clock frequency

0 to 7

-0.5 to 20

-0.4 to V

+0.4

1600

±2

V mA

V mA kV

MHz

Thermal data

Symbol

Table 4: Thermal data

Parameter

Operating free-air temperature range

OPR

Operating temperature range

STG

Storage temperature range

R thJA

Thermal resistance junction-ambient (1)

SO-24

TSSOP24

TSSOP24 (2)

exposed pad

QSOP-24

Notes:

(1)

According with JEDEC standard 51-7.

(2)

The exposed pad should be soldered directly to the PCB to realize the thermal benefits.

Value

-40 to +125

-40 to +150

-55 to +150

37.5

Unit

°C

°C/W

4/28 DocID18469 Rev 6

STP16CPC26 Electrical characteristics

3 Electrical characteristics

Symbol

V dd

ΔI

OL1

ΔI

OL2

OL3

ΔI

OL4

= 3.3 V - 5 V, T

= 25 °C, unless otherwise specified.

Parameter

Table 5: Electrical characteristics

Test conditions Min.

Supply voltage

Input voltage high level

Input voltage low level

Serial data output voltage

(SDO) (1)

0.8*Vdd

GND

-0.4

Output leakage current

Current accuracy

channel to channel (2)(3)

Current accuracy

device to device (2)

= - 1 mA

= + 1 mA

Vo = 20 V,

Outn = OFF

Vds = 0.3 V,

EXT

= 900 W,

= 22 mA

Vds = 0.6 V,

EXT

= 360 W,

= 55 mA

Vds = 0.3 V,

EXT

= 900 W,

= 22 mA

Vds = 0.6 V,

EXT

= 360 W,

= 55 mA

IN(up)

Pull-up resistor for OE pin

IN(down)

Pull-down resistor for LE pin

250

IDD(OFF1)

IDD(OFF2) Supply current (OFF)

IDD(OFF3)

EXT

= OPEN

OUT 0 to 15 = OFF

EXT

= 900 W

OUT 0 to 15 = OFF

EXT

= 360 W

OUT 0 to 15 = OFF

IDD(ON1)

IDD(ON2)

%/dV

Supply current (ON)

Output current vs. output voltage regulation

EXT

= 900 W

OUT 0 to 15 = ON

EXT

= 360 W

OUT 0 to 15 = ON

from 1.0 V to 3.0 V

Io = 22 mA

Io = 55 mA

Typ. Max. Unit

5.5

Vdd

- 0.2*Vdd

0.4

- 0.5 µA

±1

500

±0.1

±3

±6

800

13.5

KW mA

%/V

DocID18469 Rev 6 5/28

Electrical characteristics

Symbol

%/dV

Parameter

Output current vs. supply voltage

regulation (4)

Test conditions

Io = 22 mA;

= 0.3 V

Io = 55 mA;

= 0.6 V

Tsd

Tsd-hy

Thermal shutdown

Thermal shutdown hysteresis (4)

Min.

STP16CPC26

Typ. Max. Unit

±1 - %/V

170

°C

Notes:

(1)

Specification referred to TJ from -40 °C to +125 °C. Specification over the -40 to +125 °C T

temperature range are assured by design, characterization and statistical correlation.

(2)

Tested with just one output ON.

(3) Δ

IOL+

= ((I

OLmax

- I

OLmean

)/ I

OLmean

)*100, D

IOL-

= ((I

OLmin

- I

OLmean

)/ I

OLmean

)*100, where I

OLmean

= (I

OLout1

OLout2

+…+I

OLout16

) /

16.

(4)

Guaranteed by design.

6/28 DocID18469 Rev 6

STP16CPC26

= 3.3 V - 5 V, T j

= 25 °C, unless otherwise specified.

Symbol Parameter

Table 6: Switching characteristics

Conditions t su(D) t h(D)

tr (1) tf (1)

t or1a t or1b t of1a t f clk

Clock frequency t

PLH1

CLK - OUTn t

PLH2

PLH3 t

PLHa

LE - OUTn

– OUTn

Propagation delay time

(“L” to “H”)

CLK - SDO t

PLHb t t t t t t t t w(CLK) t t

PHL1

PHL2

PHL3

PHLa

PHLb w(L) w(OE) su(L) h(L)

CLK - OUTn

Propagation delay time

(“H” to “L”)

LE - OUTn

– OUTn

CLK - SDO

Pulse width CLK

Setup time for LE

Hold time for LE

Setup time for SDI

Hold time for SDI

Maximum CLK rise time

Maximum CLK fall time

Output rise time of Vout

Output fall time of Vout

VDS = 0.8 V

VIH = VDD

VIL = GND

EXT

= 900 Ω

RL = 50 Ω

CL = 10 pF

VDD = 3.3 V

VDD = 5 V

VDD = 3.3 V

VDD = 5 V t of1b t or2a t or2b t of2a t of2b

I out-ov

Output fall time of Vout

Output rise time of Vout

Output fall time of Vout

Output current turn-on overshoot

VIH = VDD,

VIL = GND

VDS = 0.8 V,

RL = 50 Ω

CL = 10 pF

Iout = 22 mA

VIH = VDD,

VIL = GND

VDS = 0.8 V

RL = 50 Ω

CL = 10 pF

Iout = 55 mA

VDS = 0.6 to 3V

CL = 10 pF

Iout = 5 to 60 mA

VDD = 3.3 V

VDD = 5 V

VDD = 3.3 V

VDD = 5 V

VDD = 3.3 V

VDD = 5 V

VDD = 3.3 V

VDD = 5 V

Electrical characteristics

Min. Typ. Max. Unit

100

30 MHz

5000

150

0 ns

Notes:

(1)

If devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer between two cascaded devices.

DocID18469 Rev 6 7/28

Simplified internal block diagram

4 Simplified internal block diagram

Figure 2: STP16CPC26 simplified block diagram

STP16CPC26

5 Typical application circuit

Figure 3: Typical application circuit

8/28 DocID18469 Rev 6

STP16CPC26

6 Equivalent circuit and outputs

Figure 4: OE terminal

Equivalent circuit and outputs

Figure 5: LE terminal

Figure 6: CLK, SDI terminal

DocID18469 Rev 6 9/28

Equivalent circuit and outputs

Figure 7: SDO terminal

STP16CPC26

10/28 DocID18469 Rev 6

STP16CPC26

7

Typical test circuits

Figure 8: "Typical test circuit for electrical characteristics" and Figure 9: "Typical test circuit for switching characteristics" show respectively the typical test circuit used measuring

electrical (e.g. input voltage high/low level, output leakage current, supply current, etc.) and switching characteristics (propagation delays, set-up and hold time, rise and fall time of

OUT

, etc.). The resistor R

and capacitor C

in parallel connected to each output in Figure

8: "Typical test circuit for electrical characteristics" simulate a LED behavior.

Figure 8: Typical test circuit for electrical characteristics

Figure 9: Typical test circuit for switching characteristics

DocID18469 Rev 6 11/28

Timing diagrams

8 Timing diagrams

STP16CPC26

The timing diagram shown in Figure 10: "Timing diagram" and the truth table in Table 7:

"Truth table" explain how to send data to the device. This can be summarized in the

following points:



LE and OE are level sensitive and not synchronized with the CLK signal



When LE is at low level, the latch circuit holds previous data



If LE is high level, data present in the shift register are latched



When OE is at low level, the status of the outputs OUT0 to OUT15 depends on the data in the latch circuits



With OE at high level, all outputs are switched off independently on the data stored in the latch circuits



Every rising edge of the CLK signal, a new data on SDI pin is sampled. This data is loaded into the shift register, whereas a bit is shifted out from SDO

Figure 10: Timing diagram

12/28

Clock LE OE Serial-IN

_|¯

¯|_

Dn + 1

Dn + 2

Dn + 3

Table 7: Truth table

OUT0 ............. OUT7 ................ OUT15 (1)

Dn ..... Dn - 7 ..... Dn -15

No change

Dn + 2 ..... Dn - 5 ..... Dn -13

OFF

Notes:

(1)

OUTn = ON when Dn = H, OUTn = OFF when Dn = L.

SDO

Dn - 15

Dn - 14

Dn - 13

DocID18469 Rev 6

STP16CPC26 Timing diagrams

Figure 11: Timing for clock signal, serial-in and serial out data

The correct sampling of the data depends on the stability of the data at SDI on the rising edge of the clock signal and it is assured by a proper data setup and hold time (t

SETUP1

And t

HOLD

), as shown in Figure 11: "Timing for clock signal, serial-in and serial out data" . The

same figure shows the propagation delay from CLK to SDO (t

PLH

PHL

). Figure 12: "Timing for clock signal serial-in data, latch enable, output enable and outputs" describes the setup

times for LE and OE signals (t

SETUP2

and t

SETUP3

respectively), the minimum duration of these signals (t

WLAT

and t

WENA

respectively) and the propagation delay from CLK to OUT n

LE to OUT n

and OE to OUT n

PLH1

PHL1

, t

PLH2

PHL2

and t

PLH3

PHL3

respectively). Finally

Figure 13: "Outputs" defines the turn-on and turn-off time (t

and t f

) of the current generators.

DocID18469 Rev 6 13/28

Timing diagrams STP16CPC26

Figure 12: Timing for clock signal serial-in data, latch enable, output enable and outputs

Figure 13: Outputs

14/28 DocID18469 Rev 6

STP16CPC26

9

9.1

Current generators characteristics

Current setting

The current of all outputs is programmed through an external resistor connected to R-EXT

pin, as shown in Figure 14: "Resistor for current programming" . The curve in Figure 15:

"Output current vs R-EXT resistor" describes the relation between the current and the resistor connected to R-EXT pin, whereas the Table 8: "Recommended values of Rext for some output current value" shows how to set some typical current values.

Figure 14: Resistor for current programming

Figure 15: Output current vs R-EXT resistor

9.2

Table 8: Recommended values of R ext

for some output current value

Output current [mA] R ext

[Ω] Closer standard value (E24 series) [Ω]

4129

2005

4300

200

999

471

322

217

1000

470

330

220

Current accuracy

A typical current accuracy of ±1% (±3% maximum) between channels is guaranteed at 22

mA and 55 mA output current (refer to Table 6: "Switching characteristics" ) and ± 6%

(maximum) current accuracy between ICs.

DocID18469 Rev 6 15/28

Thermal shutdown

9.3 Generators voltage drop

STP16CPC26

In order to correctly regulate the current, a minimum dropout voltage must be assured across the current generators.

Figure 16: "Dropout voltage vs output current" and Table 9: "Dropout voltage vs output current" provides just an indicative idea about the dropout voltage to assure over the

current range. However it is recommended to use value of V

DROP

slightly higher than those

indicated in Figure 16: "Dropout voltage vs output current" and Table 9: "Dropout voltage vs output current" .

Figure 16: Dropout voltage vs output current

10

Output current [mA]

Table 9: Dropout voltage vs output current

DROP

@ 3.3 V [mV]

170

350

530

820

DROP

@ 5 V [mV]

170

330

500

770

Thermal shutdown

The STP16CPC26 is featured with a thermal shutdown. This protection is triggered if the junction temperature reaches 170 °C. When the thermal shutdown is activated, all outputs are turned off independently on the data latched. Once the temperature decreases (thermal shutdown hysteresis is typically 15 °C), the outputs are enabled again and the device keeps on working.

Once the temperature decreases (thermal shutdown hysteresis is typically 15°C), the outputs are enabled again and the device keeps on working.

16/28 DocID18469 Rev 6

STP16CPC26

11

Package information

Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

ECOPACK ® is an ST trademark.

DocID18469 Rev 6 17/28

Package information

11.1 QSOP-24 package information

Figure 17: QSOP-24 package outline

STP16CPC26

18/28 DocID18469 Rev 6

STP16CPC26

Dim. c

A2 b e

L h

Table 10: QSOP-24 mechanical data mm

Min. Typ.

1.54

0.10

1.62

0.15

1.47

0.20

0.17

8.56

5.80

3.80

0.40

0.25

0°

8.66

6.00

3.91

0.635

0.33

Package information

Max.

1.73

0.25

0.31

0.254

8.76

6.20

4.01

0.89

0.41

8°

DocID18469 Rev 6 19/28

Package information

11.2 SO-24 package information

Figure 18: SO-24 package outline

STP16CPC26

20/28 DocID18469 Rev 6

STP16CPC26

Dim.

E e

C h

L k ddd

Table 11: SO-24 mechanical data mm

Min. Typ.

2.35

0.10

0.33

0.23

15.20

7.40

1.27

10.00

0.25

0.40

11.3 TSSOP24 package information

Figure 19: TSSOP24 package outline

Package information

Max.

2.65

0.30

0.51

0.32

15.60

7.60

10.65

0.75

1.27

0.10

DocID18469 Rev 6 21/28

Package information

Dim. c

E e

A2 b

0.05

0.19

0.09

7.7

4.3

6.25

0°

0.50

Table 12: TSSOP24 mechanical data mm

Min. Typ.

0.9

0.65 BSC

STP16CPC26

Max.

1.1

0.15

0.30

0.20

7.9

4.5

6.5

8°

0.70

22/28 DocID18469 Rev 6

STP16CPC26

11.4 TSSOP24 exposed pad package information

Package information

Figure 20: TSSOP24 exposed pad package outline

DocID18469 Rev 6 23/28

Package information

Dim.

E2 e

L1 k aaa c

A2 b

STP16CPC26

Table 13: TSSOP24 exposed pad mechanical data mm

Min. Typ.

0.80

0.19

0.09

7.70

4.80

6.20

4.30

3.00

0.45

0°

1.00

7.80

5.00

6.40

4.40

3.20

0.65

060

1.00

Max.

1.20

0.15

1.05

0.30

0.20

7.90

5.2

6.60

4.50

3.40

075

8°

0.10

24/28 DocID18469 Rev 6

STP16CPC26 Package information

11.5 TSSOP24, TSSOP24 exposed pad and SO-24 packing information

Figure 21: TSSOP24, TSSOP24 exposed pad and SO-24 reel outline

Table 14: TSSOP24 and TSSOP24 exposed pad tape and reel mechanical data mm

Dim.

Min. Typ. Max.

12.8

20.2

6.8

8.2

1.7

3.9

11.9

330

13.2

22.4

8.4

1.9

4.1

12.1

DocID18469 Rev 6 25/28

Package information

Dim.

Table 15: SO-24 tape and reel mechanical data mm

Min. Typ.

12.8

20.2

10.8

15.7

2.9

3.9

11.9

STP16CPC26

Max.

330

13.2

30.4

11.0

15.9

3.1

4.1

12.1

26/28 DocID18469 Rev 6

STP16CPC26

12

Revision history

Revision history

Date Revision

Table 16: Document revision history

Changes

04-Mar-2011

05-Apr-2011

19-Jul-2012

1-Jun-2014

13-Apr-2017

First release

Updated Table 6

Updated Table 7.

Updated characteristics in Table 5: Electrical characteristics and

Table 6: Switching characteristics.

Minor text changes.

Updated template and value Table 13: TSSOP24 exposed pad mechanical data.

Updated Figure 11: "Timing for clock signal, serial-in and serial out data"

and Figure 12: "Timing for clock signal serial-in data, latch enable, output enable and outputs" ,

Section 11.1: "QSOP-24 package information" .

Minor text changes.

DocID18469 Rev 6 27/28

STP16CPC26

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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

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ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

28/28 DocID18469 Rev 6

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