STMicroelectronics TDA7498 E Dual-BTL class-D audio amplifier Application note
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AN4015
Application note
Dual-BTL class-D audio amplifier demonstration board based on the TDA7498E
Introduction
■
■
■
The purpose of this application note is to describe: how to connect the TDA7498 demonstration board how to evaluate the performance of the demonstration board using the electrical curves how to avoid critical issues in the PCB schematic and layout of the TDA7498E
The TDA7498E represents a new generation of analog input class-D devices from
STMicroelectronics and is housed in a PSSO36 package. It is able to deliver 160 W +160 W in stereo configuration with V
CC
= 36 V and a 4
Ω load
(a)
.
Figure 1.
TDA7498E demonstration board
January 2012 a.
All of the results and graphs included in this document are measured using Audio Precision equipment.
Doc ID 022507 Rev 1 1/22
www.st.com
Contents
Contents
AN4015
Test conditions and connections of the demonstration board . . . . . . . 5
Power supply and interface connection . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Schematic diagram and PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Design guidelines for PCB schematic and layout . . . . . . . . . . . . . . . . 14
Main driver for the selection of components . . . . . . . . . . . . . . . . . . . . . 14
Decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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AN4015
List of figures
List of figures
CC
and THD level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
decoupling electrolytic capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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Overview
1 Overview
AN4015
●
●
●
●
●
●
The following terms used in this application note are defined as follows:
THD+N vs. Pout: Total Harmonic Distortion (THD) plus noise versus output power
THD+N vs. Freq: Total Harmonic Distortion plus noise versus frequency curve
S/N Ratio: Signal-to-noise ratio
DNR: Dynamic range
FFT: Fast Fourier Transform Algorithm (method)
XTalk: Channel separation L to R, or R to L channel crosstalk
●
●
●
●
●
The equipment used includes the following:
Audio Precision 2722A + AES-17 filter + DCX+ AUX-0025 filter
DC power supply
Digital oscilloscope (Tektronix TDS5054B)
Differential voltage probe (LeCroy AP031)
Current probe (Tektronix TCP300)
Reference documents include:
●
●
●
●
TDA7498E datasheet
Schematic diagram
PCB layout
Test curves
4/22 Doc ID 022507 Rev 1
AN4015
2
Test conditions and connections of the demonstration board
Test conditions and connections of the demonstration board
2.1 Power supply and interface connection
1.
Connect PSU to the V
CC
terminal block
2. Connect the analog input cable to the RCA connectors on the demonstration board, the other side must be connected to a signal source such as the Audio Precision analog outputs or a DVD player
The TDA7498E demonstration board has been configured in 2-channel BTL output.
2.3 Connections
The board terminals (top view of demonstration board) are visible in
Figure 2.
TDA7498E demonstration board connections
Left Load Right Load
Gain selection
Single-ended input/differential input mode selection
Analog input
Standby and mute controls
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Schematic diagram and PCB layout
3 Schematic diagram and PCB layout
Figure 3.
TDA7498E schematic
AN4015
6/22 Doc ID 022507 Rev 1
AN4015
Figure 4.
PCB layout - top side
Schematic diagram and PCB layout
Figure 5.
PCB layout - bottom side
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Schematic diagram and PCB layout
Figure 6.
PCB layout - top and bottom sides plus components
AN4015
8/22 Doc ID 022507 Rev 1
AN4015 Electrical characteristics
, the Left (L) and Right (R) channels are the
output for a stereo configuration. V
CC
= +36 V, Gain 23.6 dB; Tamb = 25.5 °C;
InputFreq = 1 kHz; RefLevel = 1 W (0 dBr), Load = 4
Ω (resistive dummy load).
Table 1.
Electrical characteristics
THD+N vs. power Pout = 1 W
I
OCP
SNR
No filter
AW - filter
DNR
Xtalk
No filter
AW - filter
1 kHz
0.0555%
12 A
-74.3 dB
-77.5 dB
-94 dB
-98 dB
-85.9 dB
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Test curves AN4015
10/22
Figure 7.
THD+N vs. power
10
5
2
1
0.5
%
0.2
0.1
0.05
0.02
0.01
1m 2m 5m 10m 20m 50m 100m 500m 1
W
2 5 10 20 50 100 200 400
Sweep Trace Color
1
1
1
3
Red
Blue
Line Style
Solid
Solid
Thick
2
2
Data Axis Comment
Anlr.THD+N Ratio Left
Anlr.THD+N Ratio Left
Vcc=36V; Load=4ohm; 1kHz; Ch L
Vcc=36V; Load=4ohm; 1kHz; Ch R
Figure 8.
THD+N vs. frequency (ref = 1 W at 1 kHz)
1
0.5
0.2
%
0.1
0.05
0.02
0.01
20 50 100 200 500
Hz
1k 2k 5k 10k
Sweep Trace
1
1
1
2
Color
Red
Blue
Line Style
Solid
Solid
Thick
2
2
Data Axis Comment
Anlr.THD+N Ratio Left
Anlr.THD+N Ratio Left
Vcc=36V; 1W@1kHz; Ch L
Vcc=36V; 1W@1kHz; Ch R
20k
Doc ID 022507 Rev 1
AN4015 Test curves
Figure 9.
DNR
d
B
-55
-60
-65
-70
-75
-80
-60
-20
-25
-30
-35
-40
-45
-50
-55 -50 -45 -40 -35 -30 dBr
-25 -20 -15 -10 -5 +0
Sweep Trace
1
1
2
2
1
2
1
2
Color Line Style Thick Data
Red
Blue
Solid
Solid
Green Solid
Black Solid
2
2
2
2
Anlr.THD+N Ratio
Anlr.THD+N Ratio
Anlr.THD+N Ratio
Anlr.THD+N Ratio
Axis
Left
Left
Left
Left
Comment
Vcc=36V_1kHz_4 ohm; Ch L
Vcc=36V_1kHz_4 ohm; Ch R
Vcc=36V_1kHz_4 ohm; Ch R - AW Filter
Vcc=36V_1kHz_4 ohm; Ch L - AW Filter
Figure 10.
FFT (0 dBr at 1 W)
r d
B
A
-30
-40
-50
-60
+0
-10
-20
-70
-80
-90
-100
-110
-120
-130
-140
-150
20 50 100 200 500
Hz
1k 2k 5k 10k
Sweep Trace Color
1
1
1
2
Red
Blue
Line Style
Solid
Solid
Thick
2
2
Data Axis Comment
Fft.Ch.1 Ampl Left Vcc=36V; Ref: 1W@1kHz: Ch L
Fft.Ch.2 Ampl Right Vcc=36V; Ref: 1W@1kHz: Ch R
-30
-40
-50
-60
+0
-10
-20
-70
-80
-90
-100
-110
-120
-130
-140
20k
-150 r d
B
B
Doc ID 022507 Rev 1 11/22
Test curves AN4015
Figure 11.
Crosstalk
+0
-10 d
B
-90
-100
-110
-50
-60
-70
-80
-20
-30
-40
-120
20 50 100 200 500
Hz
1k 2k 5k 10k 20k
Sweep Trace
1
1
1
2
Color
Red
Blue
Line Style
Solid
Solid
Thick
2
2
Data Axis Comment
S2C.Anlr.Crosstalk
Left
S2C.Anlr.Crosstalk
Left
Vcc=36V; 1W; 4ohm; (Ch L on)
Vcc=36V; 1W; 4ohm; (Ch R on)
Figure 12.
Linearity
24
23.5
Gain Linearity
23
22.5
22
21.5
21
20.5
20
0
Left
Right
0.2
0.4
0.6
0.8
1
Input Level [V]
1.2
1.4
1.6
1.8
2
12/22 Doc ID 022507 Rev 1
AN4015 Test curves
Figure 13.
Bandwidth
+1
+0.5
r d
B
A
+0
-0.5
-1
-1.5
-2
-2.5
-3
10 20 50 100 200 500
Hz
1k 2k 5k 10k 20k
Sweep Trace
1
1
1
2
Color
Red
Blue
Line Style
Solid
Solid
Thick
2
2
Data Axis Comment
Anlr.Level A Left Vcc=36V; 1W; Ch L
Anlr.Level B Right Vcc=36V; 1W; Ch R
50k
-3
+1
+0.5
+0
-0.5
-1
-1.5
r d
B
B
-2
-2.5
Figure 14.
Pout vs. V
CC
and THD level
200
180
W
160
140
120
100
80
60
40
20
+10 +12.5
+15 +17.5
+20 +22.5
+25
Vdc
+27.5
+30 +32.5
+35 +37.5
+40
Sweep Trace
3
4
1
2
1
1
1
1
Color Line Style Thick Data
Cyan Solid
Green Solid
Blue
Red
Solid
Solid
2
2
2
2
Axis Comment
Anlr.Level A Left
Anlr.Level A Left
Anlr.Level A Left
Anlr.Level A Left
Pout vs. Vcc; Load=4ohm; THD=1%
Pout vs. Vcc; Load=4ohm; THD=10%
Pout vs. Vcc; Load=4ohm; THD=20%
Pout vs. Vcc; Load=4ohm; THD=30%
Doc ID 022507 Rev 1 13/22
Design guidelines for PCB schematic and layout
6 Design guidelines for PCB schematic and layout
AN4015
6.1 Schematic
6.1.1 Main driver for the selection of components
●
●
●
Absolute maximum rate (input V
CC
supply): 40 V
Bypass capacitor 100 nF in parallel to 1µF for each power V
CC is suggested.
branch. Dielectric X7R
Coil saturation current must be compatible with the peak current of application
There are two different ways to use the decoupling capacitors:
●
●
The decoupling capacitor(s) can be shared among channels; the layout must be designed to implement a "star route" for the V
CC
paths.
One decoupling capacitor can be used for each channel. It is mandatory that each decoupling capacitor be placed as close as possible to the IC pins. This solution is implemented on the TDA7498E demonstration board.
●
●
●
Snubber network: the key function of a snubber network is to absorb energy from the inductive component in the power circuit (the output coils and the speaker). The purpose of the snubber RC network is to dissipate the unnecessary high pulse energy, such as a high voltage spike, in the power circuit which is dangerous to the system.
Main filter (low-pass filter): The purpose of the main filter is to remove the carrier frequency (
≈310 kHz) and to cut off the frequency higher than the audible range of
20 kHz. The LPF filter is implemented by a passive Butterworth topology. In order to have a clean and flat frequency response, it is mandatory to design the filter to fix the cutoff frequency a little bit above 20 kHz.
Damping network: The purpose of the damping network is to avoid the high-frequency oscillation issue on the output circuit. When the load is disconnected from the amplifier, the frequency response of the main filter is not flat and there is the possibility of adding gain in a frequency band. The damping network also improves the THD performance.
The damping network can also avoid the inductive effect of the PCB tracks when the system is working at high frequency with PWM.
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AN4015 Design guidelines for PCB schematic and layout
Snubber filter
The snubber circuit must be optimized for the specific application. Starting values are
330 pF in series to 22 ohm. The power dissipation of this network (resistor) depends on the power supply, frequency and capacitor values using following formula:
P
=
⋅ ⋅ (
2 V
)
2
This power is dissipated on the series resistance.
Figure 15.
Snubber filter - solution 1
INxA
C126
330p
R44
22
INxB
To increase the efficiency, it is possible to use two equal snubber networks toward GND. In this case, the formula to evaluate power is:
P = C f 2 V
2
This power is dissipated on the resistance.
Figure 16.
Snubber filter - solution 2
INxA
C127
330p
R45
22
R46
22
C130
330p
INxB
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Design guidelines for PCB schematic and layout AN4015
Dumping network
The C-R-C is a dumping network. It is mainly intended for high inductive loads and for common-mode noise attenuation.
Figure 17.
Dumping network
PWM output frequency shifting for AM band radio sensitivity improvement
Using a logic control signal (FS) from MCU or from a DSP (3.3 V) it is possible to modify the
PWM output frequency.
(b)
Figure 18.
Frequency shift
16/22 b.
For the PWM frequency calculation formula please refer to the datasheet.
Doc ID 022507 Rev 1
AN4015 Design guidelines for PCB schematic and layout
6.2 Layout
●
●
Solder 100 nF and 1µF bypass ceramic capacitors as close as possible to the related
IC pin
To avoid the effect due to the parasitic inductive coil generated by the copper wires, it is suggested to use the ceramic capacitor to balance the reactance. It's mandatory to place the ceramic capacitor as close as possible to the related pins. The distance between the capacitor to the related pins is recommended to be within 5 mm.
Figure 19.
Decoupling capacitors
Ground pin and Vcc pin of
100 nF and 1
μF capacitors should be connected to the related IC pin directly
● Solder the snubber networks as close as possible to the related IC pin. A high level spike may occur if the snubber network is placed too far from the pins. It's recommended that the distance from the snubber network be within 3 mm which takes into consideration the width of the copper wire.
Figure 20.
Snubber network
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Snubber network
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Design guidelines for PCB schematic and layout AN4015
●
Use electrolytic capacitors first to separate the V
CC
branches. A "star route" for the V
CC supply is suggested to avoid interference between the channels such as when one channel is idle while the other channel is working with a full load. In applications with high output power, another approach is to filter the two channels separately. This solution is implemented in this demonstration board.
Figure 21.
V
CC
decoupling electrolytic capacitors
●
ROSC network: Place the RC filter for the ROSC pin close to the IC
Figure 22.
ROSC - component placement
R-C network for
ROSC
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AN4015 Design guidelines for PCB schematic and layout
●
Place the filter capacitors for SVR, VREF, SVCC, VSS and VDDPW close to the IC.
Figure 23.
Filter capacitors for SVR, VREF, SVCC, VSS and VDDPW
Filter capacitors for
VREF, SVCC and
VSS
Filter capacitor for SVR
Filter capacitors for VDDS and
VDDPW
●
Input signal routing
Figure 24.
Input signal routing
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Design guidelines for PCB schematic and layout AN4015
●
Signal ground and power ground routing: the signal ground should be connected to the bulk capacitor negative terminal via a dedicated copper track; no vias must be present in the connection path.
Figure 25.
Signal ground and power ground routing
20/22 Doc ID 022507 Rev 1
AN4015
Table 2.
Date
09-Jan-2012
Document revision history
Revision
1 Initial release.
Changes
Revision history
Doc ID 022507 Rev 1 21/22
AN4015
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