STMicroelectronics TDA7498E Datasheet
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TDA7498E
Datasheet
160-watt + 160-watt dual BTL class-D audio amplifier
PowerSSO-36 exposed pad up
Maturity status link
TDA7498E
Device summary
Order code
Operating temperature range
TDA7498ETR
0 to 70 °C
Package
Packing
PowerSSO36
(EPU)
Tape and reel
Features
• 160-W + 160-W output power at THD = 10% with R
L
= 4 Ω and V
CC
= 36 V
• 1 x 220 W output power mono parallel BTL at THD = 10% with R
L
= 3 Ω and
V
CC
= 36 V
• Wide-range single-supply operation (14 - 36 V)
• High efficiency (η = 85%)
• Parallel BTL function using the MODE pin
• Four selectable, fixed gain settings of nominally 23.8 dB, 29.8 dB, 33.3 dB and
35.8 dB
• Differential inputs minimize common-mode noise
• Standby and mute features
• Smart protection
• Thermal overload protection
• Small offset less than 20 mV
Description
The TDA7498E is a dual BTL class-D audio amplifier with a single power supply designed for home systems and active speaker applications.
It comes in a 36-pin PowerSSO package with exposed pad up (EPU) to facilitate mounting a separate heatsink.
DS8807 - Rev 4 - June 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
1
TDA7498E
Device block diagram
Device block diagram
The figure below shows the block diagram of one of the two identical channels of the TDA7498E.
Figure 1. Internal block diagram (showing one channel only)
DS8807 - Rev 4 page 2/17
2
2.1
Pin description
Pinout
Figure 2. Pin connections (top view, PCB view)
36 VSS
35 SVCC
34 VREF
33 INNB
32 INPB
31 MODE
30 GAIN
29 SVR
28 DIAG
27 SGND
26 VDDS
25 SYNCLK
24 ROSC
23 INNA
22 INPA
21 MUTE
20 STBY
19 VDDPW
EP, exposed pad
Connect to ground
SUB_GND
OUTPB
OUTPB
PGNDB
PGNDB
PVCCB
PVCCB
OUTNB
OUTNB 9
OUTNA 10
7
8
5
6
OUTNA
PVCCA
11
12
PVCCA 13
PGNDA 14
PGNDA
OUTPA
15
16
OUTPA
PGND
17
18
3
4
1
2
TDA7498E
Pin description
DS8807 - Rev 4 page 3/17
TDA7498E
Pin list
2.2
Pin list
OUTPA
PGND
VDDPW
STBY
MUTE
INPA
INNA
ROSC
SYNCLK
VDDS
SGND
DIAG
SVR
GAIN
MODE
INPB
INNB
VREF
SVCC
VSS
EP
Name
SUB_GND
OUTPB
PGNDB
PVCCB
OUTNB
OUTNA
PVCCA
PGNDA
25
26
27
28
29
30
22
23
24
16,17
18
19
20
21
31
32
33
34
35
36
-
Number
1
2,3
4,5
6,7
8,9
10,11
12,13
14,15
I
I
O
I/O
O
PWR
O
O
I
O
PWR
O
I
I
I
I
I
O
PWR
O
-
Type
PWR
O
PWR
PWR
O
O
PWR
PWR
Table 1. Pin description list
Description
Connect to the frame
Positive PWM for right channel
Power stage ground for right channel
Power supply for right channel
Negative PWM output for right channel
Negative PWM output for left channel
Power supply for left channel
Power stage ground for left channel
Positive PWM output for left channel
Power stage ground
3.3-V (nominal) regulator output referred to ground for power stage
Standby mode control
Mute mode control
Positive differential input of left channel
Negative differential input of left channel
Master oscillator frequency-setting pin
Clock in/out for external oscillator
3.3-V (nominal) regulator output referred to ground for signal blocks
Signal ground
Open-drain diagnostic output
Supply voltage rejection
Gain setting input
Enables stereo or mono BTL mode of operation
Positive differential input of right channel
Negative differential input of right channel
Half VDDS (nominal) referred to ground
Signal power supply
3.3-V (nominal) regulator output referred to power supply
Exposed pad for heatsink, to be connected to ground
DS8807 - Rev 4 page 4/17
3
3.1
3.2
3.3
3.4
TDA7498E
Electrical specifications
Electrical specifications
Absolute maximum ratings
Symbol
V
CC
VI
T j
Top
T stg
Thermal data
Table 2. Absolute maximum ratings
Parameter
DC supply voltage for pins PVCCA, PVCCB, SVCC
Voltage limits for input pins STBY, MUTE, INNA,
INPA, INNB, INPB, GAIN, MODE
Operating junction temperature
Operating ambient temperature
Storage temperature
Value
45
-0.3 to 4.0
0 to 150
0 to 70
-40 to 150
Symbol
R th j-case
Table 3. Thermal data
Parameter
Thermal resistance, junction to case
Min.
-
Recommended operating conditions
Typ.
3.0
Max.
Unit
V
V
°C
°C
°C
Unit
°C/W
Symbol
V
CC
Tamb
Table 4. Recommended operating conditions
Parameter
Supply voltage for pins PVCCA, PVCCB, SVCC
Ambient operating temperature
Min
14
0
Typ
-
-
Max
39
70
Unit
V
°C
Electrical specifications
Unless otherwise stated, the values in the table below are specified for the conditions: V
CC
= 36 V, R
L
= 4 Ω,
R
OSC
= R3 = 39 kΩ, C8 = 100 nF, f = 1 kHz, G
V
= 23.6 dB Tamb = 25 °C.
Symbol
I q
I qSTBY
V
OS
I
OCP
T j
R i
V
UVP
R dsON
Table 5. Electrical specifications
Parameter
Total quiescent current
Condition
No LC filter, no load
Quiescent current in standby
Output offset voltage
-
Vi = 0, Av = 23.6 dB, no load
R
L
= 0 Ω Overcurrent protection threshold
Junction temperature at thermal shutdown
Input resistance
-
Differential input
Undervoltage protection threshold -
Power transistor on-resistance
High side
Min.
-
-
-20
10
140
-
-
150
69
-
0.15
Typ.
60
1
-
11
Max.
20
14
160
-
8
-
Unit mA
µA mV
A
°C kΩ
V
Ω
DS8807 - Rev 4 page 5/17
DS8807 - Rev 4
TDA7498E
Electrical specifications
Symbol
(Continued)
R dsON
(Continued)
Parameter
Power transistor on-resistance
Low side
Condition Min.
-
Typ.
0.15
Max.
-
Unit
(Contin ued)
Ω
P
P
η
THD
G o o
V
Output power
Parallel BTL (mono) output power,
R
L
= 3 ohm, Vcc = 36 V
Efficiency
Total harmonic distortion
Closed-loop gain
THD = 10%
THD = 1%
THD = 10%
THD = 1%
P o
= 1 W
GAIN < 0.25*VDD
0.25*VDD < GAIN < 0.5*VDD
0.5*VDD < GAIN < 0.75*VDD
-
GAIN > 0.75*VDD
-
-
-
-
-
-
160
125
220
170
85
0.05
23.8
29.8
33.3
35.8
-
-
-
-
-
-
-
W
W
%
% dB
ΔG
V
C
T
Vn
SVRR
Gain matching
Crosstalk
Total output noise
Supply voltage rejection ratio
f = 1 kHz, P o
= 1 W
Inputs shorted and to ground,
A Curve
Inputs shorted and to ground, f = 20 Hz to 20 kHz fr = 100 Hz, Vr = 0.5 Vpp,
C
SVR
= 10 µF
-1
50
-
60
231
400
55
1
-
dB dB
µV dB f
T r
, T f f
SW
SWR
Rise and fall times
Switching frequency
Output switching frequency range
Internal oscillator
With internal oscillator by changing
R
OSC
-
240
240
35
310
-
-
400 ns kHz kHz
V inH
V inL
Digital input high (H)
Digital input low (L)
-
2.0
-
-
-
-
0.8
V
Function mode
Standby & mute & play
STBY < 0.5 V; MUTE = X
STBY > 2.5 V; MUTE < L
STBY > 2.5 V; MUTE > H
V
MUTE
< L, V
STBY
= H
Standby
Mute
Play
75 A
MUTE
Mute attenuation dB
1. f
SW
= 10 6 / ((16 * R
OSC
+ 182) * 4) kHz, f
SYNCLK
= 2 * f
SW
with R3 = 39 kΩ (see
Figure 3. Test circuit stereo application and
page 6/17
3.5
Test circuit
Figure 3. Test circuit stereo application and mono BTL mode
C1
1uF
C2
1uF
C3
1nF
C4
1nF
J1
INPUT
3
4
1
2
MONO
INPUT
L-
L+
R-
R+
L+, L- Only
C5
100nF
VDDS
R10
100k
R11
100k
J3
MONO
Config
3V3
J4
PS
J8
For Single-Ended
Input and
MONO Config
C11
R12
100k
1uF
C12
S2
MUTE
1
3
S1
STBY
1
3
2
2
1uF
R4
R19
33k
120k
R2
33k
R8
VCC OUT
1
C29
2.2uF
IC2
L4931CZ33
IN
3
2
GND C9
100nF
6.8k
D1
18V
VDDS
R1
J7
For
Single-Ended
Input
R7
22R
C6
100nF FREQUENCY SHIFT
PS
Q1
KTC3875(S)
R9
180K
R13
1
3
47k
R14
100k
2
C8
100nF
R3
39K
VDDS
47k
SYNC
DIAG
J11
J10
J12
J6
J5
J9
VDDS
C13
1nF
C14
1nF
+ C15
2.2uF
16V
+ C7
2.2uF
16V
C10
100nF
1
22
23
27
SUB_GND
INPA
INNA
SGND
26 VDDS
28 DIAG
19 VDDPW
18
PGND
25 SYNCLK
24
ROSC
30
GAIN
31
MODE
35
SVCC
36 VSS
32 INPB
33 INNB
21 MUTE
20 STBY
3V3 POWER SUPPLY
IC1
TDA7498E
TDA7498E
(PSSO36)
CLASS-D AMPLIFIER
OUTPA
OUTPA
16
17
PGNDA
PGNDA
14
15
D2
D3
R6
22R
PVCCA
PVCCA
12
13
C25
100nF
C30
1uF
C27
330pF
D4 VCC
OUTNA
OUTNA
10
11
D5
OUTPB
OUTPB
PVCCB
PVCCB
3
2
7
6
D7
D6
R5
22R
VCC
PGNDB
PGNDB
5
4
OUTNB
OUTNB
9
8
C19
100nF
C31
1uF
C21
330pF
VCC
D8
D9
VREF 34
SVR 29
C17
10uF
10V
C16
10uF
10V
VCC
L4
L4S
WL+
WR+
MONO
OUT
L3S
L3
C32
2200uF
L1
50V
+
C23
2200uF
+
50V
L1S
WL-
WR-
MONO
OUT
L2
L2S
C28
220nF
C26
1uF
C20
1uF
C24
220nF
C18
220nF
C22
220nF
Optional components or circuitry
MODE SETTING
MODE
STEREO
MONO
JUMPER
J5
J6,J3,J8
R15
8R
C40
220nF
C41
220nF
R16
8R
1
2
VCC
GND
J2
R17
8R
C42
220nF
C43
220nF
R18
8R
LOUTPUT
Load=4 ohm
L+
1
2
L-
J13
R-OUTPUT
Load=4 ohm
R+
2
1
R-
J14
GAIN SETTING
GAIN JUMPER
23.6dB
29.6dB
33.1dB
35.6dB
J9
J10
J11
J12
TDA7498E
Test circuit
DS8807 - Rev 4 page 7/17
4
4.1
TDA7498E
Characterization curves
Characterization curves
Unless otherwise stated the measurements were made under the following conditions:
V
CC
= 36 V, f = 1 kHz, G
V
= 23.6 dB, R
OSC
= 39 kΩ, C
OSC
= 100 nF, Tamb = 25 °C
For R
L
= 4 Ω, stereo configuration
Figure 4. Output power vs. supply voltage
Figure 5. THD vs. output power
Figure 6. THD vs. frequency
Figure 7. FFT performance
Figure 8. Crosstalk vs. frequency
DS8807 - Rev 4 page 8/17
TDA7498E
For RL = 3 Ω, mono BTL configuration
4.2
For R
L
= 3 Ω, mono BTL configuration
Figure 9. Output power vs. supply voltage
Figure 10. THD vs. output power
Figure 11. THD vs. frequency
DS8807 - Rev 4 page 9/17
5
5.1
5.2
5.3
TDA7498E
Application information
Application information
Stereo and mono BTL operation selection using the MODE pin
The TDA7498E can be used in stereo applications or mono BTL applications. Connecting the MODE pin to the
VDDS pin configures the device in mono BTL. The output of the two channels can be paralleled. When the MODE pin is connected to ground or floating (pulled down internally) the device works as a stereo amplifier.
Gain setting
The gain of the TDA7498E is set by GAIN (pin 30).
GAIN
VGAIN < 0.25*VDDS
0.25*VDDS < VGAIN < 0.5*VDDS
0.5*VDDS < VGAIN < 0.75*VDDS
VGAIN > 0.75VDDS
Table 6. Gain settings
Total gain
23.6 dB
29.6 dB
33.1 dB
35.6 dB
Application recommendation
GAIN pin connected to SGND
Rc10 = Rc11 = Rc12 = 100 K max
Rc10 = Rc11 = Rc12 = 100 K max
GAIN pin connected to VDDS
Smart protection
The TDA7498E embeds an overcurrent protection circuitry to protect the device from unwanted current peaks. If
down immediately. The device will recover automatically once the fault is removed.
DS8807 - Rev 4 page 10/17
6
6.1
TDA7498E
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
PowerSSO-36 EPU package information
Figure 12. PowerSSO-36 EPU package outline
DS8807 - Rev 4 page 11/17
DS8807 - Rev 4
Symbol
U
X
Y
Q
S
T k
L
M
N
O e3
F
G
E e
H h
A
A2 a1 b c
D
TDA7498E
PowerSSO-36 EPU package information
0
0.55
-
-
-
-
-
-
10.10
-
-
4.10
6.50
-
-
-
Min.
2.15
2.15
0
0.18
0.23
10.10
7.40
-
Table 7. PowerSSO-36 EPU package mechanical data
-
-
0.10
10.50
0.40
8 degrees
0.85
-
10 degrees
-
-
4.70
7.10
-
-
-
Max.
2.45
2.35
0.10
0.36
0.32
10.50
7.60
-
-
-
4.30
-
1.20
-
0.5
8.5
2.3
-
-
-
-
-
-
mm
Typ.
-
-
0.80
2.90
3.65
1.00
-
-
0
0.022
-
-
-
-
-
-
0.398
-
-
0.161
0.193
-
-
-
Min.
0.085
0.085
0
0.007
0.009
0.398
0.291
-
-
-
0.169
-
0.047
-
0.020
0.335
0.091
-
-
-
-
-
-
inches
Typ.
-
-
0.031
0.114
0.144
0.039
-
-
-
-
0.004
0.413
0.016
8 degrees
0.033
-
10 degrees
-
-
0.185
0.280
-
-
-
Max.
0.096
0.093
0.004
0.014
0.013
0.413
0.299
page 12/17
TDA7498E
Revision history
Date
12-Dec-2011
16-Jun-2015
10-Dec-2018
25-Jun-2020
Revision
1
2
3
4
Table 8. Document revision history
Changes
Initial release.
Updated V
CC
in Table 3: "Absolute maximum ratings" , updated Section 6.3:
"Smart protection", and updated dimension L in Table 8: "PowerSSO-36 EPU package mechanical data".
Updated device summary on the cover page.
Updated
DS8807 - Rev 4 page 13/17
TDA7498E
Contents
Contents
DS8807 - Rev 4 page 14/17
TDA7498E
List of tables
List of tables
DS8807 - Rev 4 page 15/17
TDA7498E
List of figures
List of figures
DS8807 - Rev 4 page 16/17
TDA7498E
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
DS8807 - Rev 4 page 17/17
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