STMicroelectronics TDA7492E Datasheet
The STMicroelectronics TDA7492E is a dual BTL class-D audio amplifier with a single power supply designed for home audio applications. With wide-ranging single-supply operation (7-26 V), it offers high efficiency and can deliver impressive output power. The device's BTL output capabilities range from 61 W + 61 W at 4 Ω to 34 W + 34 W at 8 Ω, with THD of 1%. It also supports a parallel BTL configuration, providing up to 110 W at 3 Ω with THD of 10%.
광고
광고
TDA7492E
79 W + 79 W dual BTL class-D audio amplifier
Datasheet - production data
PowerSSO-36 exposed pad up
Features
•
Wide-range single-supply operation
(7 - 26 V)
•
Possible output configurations:
−
2 x PBTL
−
1 x Parallel BTL
•
BTL output capabilities (V
CC
= 26 V):
− 61 W + 61 W, 4 Ω, THD 1%
− 79 W + 79 W, 4 Ω, THD 10%
− 44 W + 44 W, 6 Ω, THD 1%
− 57 W + 57 W, 6 Ω, THD 10%
− 34 W + 34 W, 8 Ω, THD 1%
− 44 W + 44 W, 8 Ω, THD 10%
•
Parallel BTL output capabilities (V
CC
= 26 V):
−
86
W, 3 Ω, THD 1%
− 110 W, 3 Ω, THD 10%
•
High efficiency
•
Four selectable, fixed-gain settings of nominally 20.8 dB, 26.8 dB, 30 dB and
32.8 dB
•
Differential inputs minimize common-mode noise
•
Standby, mute and play operating modes
•
Short-circuit protection
•
Output power limited by P
LIMIT
function
•
Detection of shorted output pins during startup
•
Thermal overload protection
•
ECOPACK ® environmentally friendly package
Description
The TDA7492E is a dual BTL class-D audio amplifier with single power supply designed for home audio applications.
The device is housed in a 36-pin PowerSSO package with exposed pad up (EPU), and as a result of its high efficiency, a simple heatsink is required.
Order code
Table 1: Device summary
Operating temp. range
Package Packaging
TDA7492ETR -40 to +85°C
PowerSSO-36
EPU
Tape and reel
February 2017 DocID027638 Rev 1
This is information on a product in full production.
1/24 www.st.com
Contents
Contents
TDA7492E
1 Device block diagram ...................................................................... 5
2 Pin description ................................................................................ 6
3 Electrical specifications .................................................................. 8
Absolute maximum ratings ................................................................ 8
Thermal data ..................................................................................... 8
Electrical specifications ..................................................................... 9
Stereo BTL application .................................................................... 10
Parallel BTL (mono) application ...................................................... 10
4 Application information ................................................................ 11
Stereo and mono applications ......................................................... 11
Smart protections ............................................................................ 11
Overcurrent protection (OCP) .......................................................... 11
Thermal protection ............................................................................ 12
Mode selection ................................................................................ 13
5 Schematic diagram ........................................................................ 15
6 Characterization curves ................................................................ 16
Stereo configuration ........................................................................ 16
7 Package information ..................................................................... 20
PowerSSO36 EPU package information ......................................... 20
8 Revision history ............................................................................ 23
2/24 DocID027638 Rev 1
TDA7492E
List of tables
List of tables
DocID027638 Rev 1 3/24
List of figures
List of figures
TDA7492E
4/24 DocID027638 Rev 1
TDA7492E
1
Device block diagram
Device block diagram
Figure 1: "Internal block diagram (showing one channel only)" shows the block diagram of
one of the two identical channels of the TDA7492E.
Figure 1: Internal block diagram (showing one channel only)
GAIN
PLMT
Gain Settings
Power Limit
Gate
Driver
INP
INN
+
-
-
+
VREF
-
+
+
-
+
-
+
-
Gate
Driver
ROSC
SYNCLK
Oscillator
Standby Mute/Play
STANDBY MUTE
Thermal,Undervoltage
Overcurrent protections
DIAG
VDD,VSS Regulators
VDDS VSS
OUTP
OUTN
DocID027638 Rev 1 5/24
Pin description
2
2.1
Pin description
Pinout
Figure 2: Pin connections (top view, PCB view)
TDA7492E
36 VSS
35 SVCC
34 VR EF
33 IN NB
32 IN PB
31 GAIN
30 PLIMIT
29 SVR
28 DIAG
27 SGND
26 VD DS
25 SYNCLK
24 ROSC
23 IN NA
22 IN PA
21 MUTE
20 STBY
19 VD DPW
E P e xpo sed pa d u p
Con ne ct to g ro un d
SUB GN D 1
OUTPB 2
OUTPB 3
PGNDB 4
PGNDB 5
PV CCB 6
PV CCB 7
OUTNB 8
OUTNB 9
OUTNA 10
OUTNA 11
PV CCA 12
PV CCA 13
PGNDA 14
PGNDA 15
OUTPA 16
OUTPA 17
PGN D 18
6/24 DocID027638 Rev 1
TDA7492E
2.2 Pin list
Pin description
Name
SUB_GND
OUTPB
PGNDB
PVCCB
OUTNB
OUTNA
PVCCA
PGNDA
OUTPA
PGND
VDDPW
STBY
MUTE
INPA
INNA
ROSC
SYNCLK
VDDS
SGND
DIAG
SVR
PLIMIT
GAIN
INPB
INNB
VREF
SVCC
VSS
EP
19
20
21
22
23
24
25
Number
1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
16, 17
18
26
32
33
34
35
36
-
27
28
29
30
31
Table 2: Pin description list
Type Description
PWR Connect to the frame
O Positive PWM for right channel
PWR Power stage ground for right channel
PWR Power supply for right channel
O Negative PWM output for right channel
O Negative PWM output for left channel
PWR Power supply for left channel
PWR Power stage ground for left channel
O Positive PWM output for left channel
PWR Power stage ground
O
3.3 V (nominal) regulator output referred to ground for power stage
I
I
Standby mode control
Mute mode control
I
I
O
I/O
Positive differential input of left channel
Negative differential input of left channel
Master oscillator frequency-setting pin
Clock in/out for external oscillator
O
3.3 V (nominal) regulator output referred to ground for signal blocks
PWR Signal ground
O
O
I
I
Open-drain diagnostic output
Supply voltage rejection
Output voltage level setting
Gain setting input
I
I
Positive differential input of right channel
Negative differential input of right channel
O Half VDDS (nominal) referred to ground
PWR Signal power supply
O
-
3.3 V (nominal) regulator output referred to power supply
Exposed pad for heatsink, to be connected to GND
DocID027638 Rev 1 7/24
Electrical specifications
3
3.1
3.2
Electrical specifications
TDA7492E
Absolute maximum ratings
Symbol
Table 3: Absolute maximum ratings
Parameter
V
CC
VI
T op
T j
T stg
DC supply voltage for pins PVCCA, PVCCB, SVCC
Voltage limits for input pins STBY, MUTE, INNA, INPA,
INNB, INPB, GAIN, MODE
Operating temperature
Junction temperature
Storage temperature
Thermal data
Symbol
Table 4: Thermal data
Parameter
R th j-case
Thermal resistance, junction-to-case
Value
30
-0.3 to +4.6
-40 to +85
-40 to +150
-40 to +150
Min. Typ. Max. Unit
- 2.98 °C/W
Unit
V
V
°C
°C
°C
8/24 DocID027638 Rev 1
TDA7492E
3.3 Electrical specifications
Electrical specifications
Unless otherwise stated, the results in Table 5: "Electrical specifications" below are given
for the conditions: V
CC
= 26 V, R
L
= 6 Ω, R
OSC
= 33 kΩ, f = 1 kHz, G
V
= 20.8 dB and
Tamb = 25 °C.
Symbol Parameter
Table 5: Electrical specifications
Condition Min. Typ. Max. Unit
V
CC
I q
I qSTBY
Supply voltage for pins
PVCCA, PVCCB, SVCC
Total quiescent current
Quiescent current in standby
-
Without LC, no load
-
7
-
-
-
40
1
26
-
V mA
µA
V
OS
Output offset voltage
Vi = 0, Av = 20 dB,
no load
20 mV
I
OCP
T j
R i
R dsON
Overcurrent protection threshold
Junction temperature at thermal shutdown
Input resistance
Power transistor on-resistance
R
L
= 0 Ω
-
9 10 13 A
140 150 160 °C
G
V
ΔG
V
CT
SVRR
T r
, T f f
SW f
SWR
V inH
V inL
Closed-loop gain
Gain matching
Crosstalk
Supply voltage rejection ratio
Rise and fall times
Switching frequency
Output switching frequency range
Digital input high (H)
Digital input low (L)
Function mode
Standby, Mute, Play
A
MUTE
Mute attenuation
Differential input
High side
Low side
GAIN < 0.25*Vdd
0.25*Vdd < GAIN < 0.5*Vdd
0.5*Vdd < GAIN < 0.75*Vdd
GAIN1>0.75*Vdd
- f = 1 kHz fr = 100 Hz, Vr = 0.5 V,
C
SVR
= 10 µF
PWM signal 50% duty cycle
Internal oscillator with external Rosc = 33 kΩ
With internal oscillator by
-
-
-
-
-
-
-
-
-
-
-
450
2.0
-
STBY < 0.5 V Mute = 'X'
STBY > 2.5 V Mute < 0.8 V
STBY > 2.5 V Mute > 2.5 V
V
MUTE
= 1 V 60
60
0.2
0.2
20.8
26.8
30
32.8
-
70
60
24
500
-
- -
- 0.8
Standby
Mute
Play
80 -
-
-
-
- kΩ
Ω
-
- dB
-
±1 dB
- dB
-
40
- dB ns kHz
550 kHz
V dB
Notes:
(1) f
SW
= 10
6
/ [(12 * R
OSC
+ 110) * 4] kHz, f
SYNCLK
= 2 * f
SW
(where R
OSC is in kΩ and f
SW
in kHz) with
Rosc = 33 kΩ.
DocID027638 Rev 1 9/24
Electrical specifications
3.4 Stereo BTL application
TDA7492E
All specifications are for V
CC
= 22 V, Rosc =
33 kΩ, f = 1 kHz, Tamb = 25 °C, unless otherwise specified.
Symbol
P o
Parameter
Output power
Table 6: Stereo BTL application
Condition
R
L
= 6 Ω, THD = 10%
R
L
= 6 Ω, THD = 1%
R
L
= 6 Ω, THD = 10%,
V
CC
= 26 V
R
L
= 6 Ω, THD = 1%,
V
CC
= 26 V
THD Total harmonic distortion P o
= 1 W, fin = 1 kHz
VN Total output noise
Inputs shorted and connected to GND,
A curve, G
V
= 20.8 dB
Min. Typ. Max. Unit
-
-
-
-
-
-
41
32
57
44
0.04
150
-
-
-
-
-
-
W
%
µV
3.5 Parallel BTL (mono) application
All specifications are for V
CC
= 22 V, Rosc = 33 kΩ, f = 1 kHz, Tamb = 25 °C, INPB, INNB connected to VDDS, unless otherwise specified.
Symbol
P o
Parameter
Table 7: Stereo BTL (mono) application
Condition Min. Typ. Max. Unit
Output power
R
L
= 3 Ω, THD = 10%
R
L
= 3 Ω, THD = 1%
R
L
= 3 Ω, THD = 10%,
Vcc = 26 V
R
L
= 3 Ω, THD = 1%,
V
CC
= 26V
-
-
-
-
90
70
110
86
-
-
-
-
W
- 0.04 - % THD Total harmonic distortion P o
= 1 W, fin = 1 kHz
VN Total output noise
Inputs shorted and connected to GND,
A curve, G
V
= 20.8 dB
- 150 - µV
10/24 DocID027638 Rev 1
TDA7492E
4
4.1
4.2
Application information
Application information
Gain setting
The four gain settings of the TDA7492E are set by GAIN (pin 31). Internally, gain is set by changing the feedback resistors of the amplifier.
Voltage on GAIN pin
Table 8: Gain settings
Total gain Application recommendations
V
GAIN
< 0.25*VDDS
0.25*VDDS < V
GAIN
< 0.5*VDDS
0.5*VDDS < V
GAIN
< 0.75*VDDS
V
GAIN
> 0.75*VDDS
20.8 dB
26.8 dB
30 dB
32.8 dB
GAIN pin connected to SGND
External resistor divider <100 k
External resistor divider <100 k
GAIN pin connected to VDDS
Stereo and mono applications
The TDA7492E can be used in stereo BTL or in mono BTL configuration. When the input pins, INPB and INNB of the right channel are directly shorted to VDDS (without input
capacitors) the device is in mono configuration as shown in Figure 3: "Mono BTL settings" .
Figure 3: Mono BTL settings
4.3
4.3.1
INPA
INNA
INPB
INNB
IC
OUTPB
OUTPA
OUTNA
OUTNB
LC
Filter
Smart protections
Overcurrent protection (OCP)
If the overcurrent protection threshold is reached, the power stage will be shut down immediately. The device will recover automatically when the fault is removed.
The overcurrent protection scheme is shown in Table 9: "Overcurrent protection" . Two
typical thresholds are as follows.
Table 9: Overcurrent protection
I (Shutdown)
High side (A) 11.2
Low side (A) 10.0
DocID027638 Rev 1 11/24
Application information TDA7492E
The thresholds in MUTE mode are reduced to about 1/2 and two typical thresholds are as follows.
Table 10: Overcurrent protection (mute mode)
I (Shutdown)
High side (A) 6.2
Low side (A) 5.9
4.3.2 Thermal protection
When internal die temperature exceeds 140 °C, the device enters into Mute by pulling the
MUTE pin low first.
When internal die temperature exceeds 150 °C, the device directly shuts down the power stage. The TDA7492E automatically recovers when the temperature become lower than the threshold.
4.3.3 Power limit
A built-in power limit is used to limit the output voltage level below the supply rail by limiting the duty cycle. The limit level is set through the voltage at PLIMIT (pin 30). The pin voltage is set by the following equation:
𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 = 𝑉𝑉
𝐷𝐷𝐷𝐷
�
(𝑅𝑅𝑅𝑅𝑅𝑅//400𝑘𝑘)
(𝑅𝑅𝑅𝑅𝑅𝑅//400𝑘𝑘 + 𝑅𝑅𝑅𝑅𝑅𝑅)
�
Figure 4: Recommended power limit pin connections
VDDS
Rup
PLIMIT
Rdn
Power
Limiter
12/24
It is recommended that external resistors are less than 40 kΩ if a voltage divider is used as
shown in Figure 4: "Recommended power limit pin connections" . The relationship of the
maximum duty cycle (Dmax) and the voltage at P
LIMIT
is:
𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 =
�8.8 ×
𝑉𝑉 𝑐𝑐𝑐𝑐
𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉
𝑅𝑅𝑙𝑙𝑙𝑙𝐷𝐷𝑅𝑅 × 2 × 𝑅𝑅𝑅𝑅
2 𝑐𝑐𝑐𝑐
× 𝑅𝑅𝑅𝑅
+ 1�
Where V
CC
is the power supply voltage, VPLIMIT is the voltage applied at the P
LIMIT
pin, Rs is the series resistance including Rdson of power transistor, output filter resistance and bonding wire resistance. Rload is the load resistance.
DocID027638 Rev 1
TDA7492E Application information
An example of maximum effective control voltage at P
LIMIT
vs. power supply and load
resistance is shown in Table 11: "Max effective voltage of PLIMIT pin vs. power supply and load" .
Table 11: Max effective voltage of PLIMIT pin vs. power supply and load
Power supply
Rload
7 V 13 V 24 V
4 Ω
6 Ω
8 Ω
0.71 V
0.74 V
0.75 V
1.32 V
1.37 V
1.39 V
2.44 V
2.53 V
2.57 V
4.4 Mode selection
The three operating modes of the TDA7492E are set by two inputs: STBY (pin 20) and
MUTE (pin 21).
•
Standby mode: all circuits are turned off, very low current consumption.
•
Mute mode: inputs are connected to ground and the positive and negative PWM outputs are at 50% duty cycle
•
Play mode: the amplifiers are active.
The protection functions of the TDA7492E are implemented by pulling down the voltages of
the STBY and MUTE inputs shown in Figure 5: "Standby and mute circuits" . The input
current of the corresponding pins must be limited to 200 µA.
Mode
Table 12: Mode settings
STBY MUTE
Standby
Mute
Play
H
H
X (don’t care)
L
H
Notes:
(1)
Drive levels defined in Table 5: "Electrical specifications" .
DocID027638 Rev 1 13/24
Application information
0 V
0 V
Figure 5: Standby and mute circuits
Standby
3.3 V
R 2
33 k
Ω
C7
Mute R4
3.3 V
33 k
Ω
C15
2.2 µF
20
STBY
2.2 µF
TDA7492E
21
MUTE
TDA7492E
Figure 6: Turn-on/off sequence for minimizing speaker “pop”
14/24 DocID027638 Rev 1
TDA7492E
5 Schematic diagram
Figure 7: Application circuit
C1
1uF
C2
1uF
C3
1nF
C4
1nF
R6
22R
J1
INPUT
3
L-
4
L+
1
R-
2
R+
MONO
INPUT
L+, L- Only
C5
100nF
J7
For
Single-Ended
Input
FREQUENCY SHIFT
PS
Q1
KTC3875(S)
R9
180K
R13
3
1
C8
100nF
47k
R14
100k
2
R3
39K
R7
22R
C6
100nF
INNB
R1
47k
C25
100nF
C30
1uF
C27
330pF
R5
22R
J3
MONO
Config
3V3
J4
PS
R19
4.7k
R10
R11
INNB
100k
J8
For Single-Ended
Input and
MONO Config
100k
C11
1uF
C12
1uF
R4
S2 MUTE
1
3
2
S1 STBY
1
3
2
33k
R2
750k
R8
VCC OUT
1
IC2 IN
L4931CZ33
3
C29
2.2uF
2 GND C9
100nF
1.2k
J11
J10
INNB
C13
1nF
+
+
C14
1nF
C15
2.2uF
16V
C7
2.2uF
16V
J6
J5
C10
100nF
C19
100nF
TDA7492E CLASS-DAMPLIFIER
C17
4.7uF
10V
C16
10uF
10V
C31
1uF
C21
330pF
L4
22uH
MONO
OUT
L3
22uH
L1
22uH
MONO
OUT
L2
22uH
C28
220nF
C26
*220nF
C24
220nF
C23
2200uF
+
35V
C18
220nF
C20
*220nF
C22
220nF
Schematic diagram
R15
8R
C40
220nF
C41
220nF
R16
8R
L-OUTPUT
Load=6 ohm
L+
1
2
L-
J13
MONO
OUTPUT
L+, L- Only
1
2
VCC
GND
J2
R17
8R
C42
220nF
R-OUTPUT
Load=6 ohm
R+
2
1
R-
J14
C43
220nF
R18
8R
DocID027638 Rev 1 15/24
Characterization curves TDA7492E
6 Characterization curves
Unless otherwise stated, measurements were made under the following conditions:
V
CC
=
22 V, Rl = 6 Ω, f = 1 kHz, Gv = 20.8 dB, R
OSC
= 33 kΩ, T amb
= 25 °C.
Note: Maximum output power must be derated according to case temperature.
6.1 Stereo configuration
The following characterization curves were made using the TDA7492E demonstration
board ( Figure 7: "Application circuit" ). The characterization curves were made under the
following test conditions:
Vs = 7 and 26 V, R l
= 6 Ω, Rosc = 33 kΩ, Cosc = 100 nF, Gain = 20.8 dB and Tamb = 25°C unless otherwise specified.
Figure 8: Output power vs. supply voltage
Figure 9: THD vs. Pout (Vs = 26 V, f = 1 kHz)
10
5
0.2
0.1
0.05
0.02
0.01
0.005
2
1
0.5
Vs=26V, Rl =6
Ω, f=1kHz
0.002
0.001
10m 20m 50m 100m 200m 500m 1 2
Pout (W)
5 10 20 50
Figure 10: THD vs. Pout (Vs = 26 V, f = 100 Hz) Figure 11: THD vs. Pout (Vs = 26 V, f = 6 kHz)
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
Vs=26V, Rl =6 Ω , f=100 Hz
0.002
0.001
10m 20m 50m 100m 200m 500m 1
Pout (W)
2 5 10 20 50
10
5
2
1
0.5
Vs=26V, Rl =6
Ω , f=6kHz
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
10m 20m 50m 100m 200m 500m 1
Pout (W)
2 5 10 20 50
16/24 DocID027638 Rev 1
TDA7492E
Figure 12: THD vs. frequency (Vs = 26 V, Po = 1 W)
10
5
0.2
0.1
0.05
2
1
0.5
0.02
0.01
0.005
0.002
0.001
20
Vs=26V, Rl =6
Ω , Po= 1W
50 100 200 500 1k
Frequency (Hz)
2k 5k 10k 20k
Figure 14: Signal-to-noise ratio (Vs = 26 V, gain =
32.6 dB, not weighted)
+0
-0.5
-1
-1.5
-2
-2.5
-3
+2
+1.5
+1
+0.5
-3.5
-4
-4.5
-5
-5.5
-6
20
Characterization curves
Figure 13: Frequency response Vs = 26 V
50
Rl =6
Ω, Po= 1W
100 200 500 1k
Frequency (Hz)
2k 5k 10k 20k
Figure 15: Signal-to-noise ratio (Vs = 26 V, gain =
20.6 dB, not weighted)
-30
-40
-50
-60
-70
-80
-90
-100
-110
+0
-10
-20
-120
20
Gain = 32.6dB, No -Weight
Vs=26V,Rl=6
Ω ,Po=1W, f=1kHz
50 100 200 500 1k
Frequency (Hz)
2k 5k 10k 20k
-30
-40
-50
+0
-10
-20
-60
-70
-80
-90
-100
-110
-120
20
Gain=20.6dB, No-Weight
Vs=26V, Rl=6 Ω, Po= 1W, f=1kHz
50 100 200 500 1k
Frequency (Hz)
2k 5k 10k 20k
DocID027638 Rev 1 17/24
Characterization curves
Figure 16: Signal-to-noise ratio (Vs = 26 V, gain =
32.6 dB, A-weighted)
TDA7492E
Figure 17: Signal-to-noise ratio (Vs = 26 V, gain =
20.6 dB, A-weighted)
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
20
Gain=20.6dB, A-Weight
Vs=26V, Rl=6
Ω, Po=1W, f=1kHz
50 100 200 500 1k
Frequency (Hz)
2k 5k 10k 20k
-80
-90
-100
-110
-120
-130
-140
+0
-10
-20
-30
-40
-50
-60
-70
-150
20
Figure 18: Crosstalk Vs = 26 V
T
Gain= 32.6dB, Vs=26V,
Rl =6 Ω , Po=1W, f=1kHz
50 100 200 500 1k
Frequency (Hz)
2k 5k 10k 20k
Figure 19: FFT (0 dB) Vs = 26 V
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
20
Gain=32.6dB, Vs=26V,
Rl =6
Ω , Po=1W, f=1kHz
50 100 200 500 1k
Frequency (Hz)
2k 5k 10k 20k
18/24 DocID027638 Rev 1
TDA7492E
Figure 20: FFT (-60 dB) Vs = 26 V
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
20
Gain=32.6dB, Vs=26V,
Rl =6
Ω , Po=1W, f=1kHz
50 100 200 500 1k
Frequency (Hz)
2k 5k 10k 20k
Characterization curves
DocID027638 Rev 1 19/24
Package information
7
7.1
Package information
TDA7492E
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
PowerSSO36 EPU package information
The device comes in a 36-pin PowerSSO package with exposed pad up (EPU).
Figure 21: "PowerSSO-36 EPU package outline"
shows the package outline and Table 13:
"PowerSSO-36 EPU package mechanical data" gives the dimensions.
20/24 DocID027638 Rev 1
TDA7492E
Figure 21: PowerSSO-36 EPU package outline
Package information
DocID027638 Rev 1
7618147_F
21/24
Package information
Symbol h k
L
M e3
F
G
H c
D
E e
A
A2 a1 b
T
U
X
Y
N
O
Q
S
TDA7492E
Table 13: PowerSSO-36 EPU package mechanical data
Dimensions in mm Dimensions in inches
Min. Typ. Max. Min. Typ. Max.
-
-
-
10.10
-
0
0.55
-
2.15
2.15
0
0.18
0.23
10.10
7.40
-
-
-
4.10
4.90
-
-
-
-
8.5
2.3
-
-
-
-
-
4.30
-
-
-
0.5
-
-
-
-
-
1.20
0.80
2.90
3.65
1.00
-
-
-
-
0.10
10.50
0.40
8 degrees
0.85
-
2.45
2.35
0.10
0.36
0.32
10.50
7.60
-
10 degrees
-
-
-
-
-
4.70
7.10
-
-
-
0.398
-
0
0.022
-
0.085
0.085
0
0.007
0.009
0.398
0.291
-
-
-
0.161
0.193
-
-
-
-
0.335
0.091
-
-
-
-
-
0.169
-
-
-
0.020
-
-
-
-
-
0.047
0.031
0.114
0.144
0.039
-
-
-
-
0.004
0.413
0.016
8 degrees
0.033
-
0.096
0.093
0.004
0.014
0.013
0.413
0.299
-
10 degrees
-
-
-
-
-
0.185
0.280
22/24 DocID027638 Rev 1
TDA7492E
8 Revision history
Date
24-Feb-2017
Table 14: Document revision history
Revision Changes
1 Initial release
Revision history
DocID027638 Rev 1 23/24
TDA7492E
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics – All rights reserved
24/24 DocID027638 Rev 1
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