NXP MC68331 32 Bit Microcontroller Reference Manual

Freescale Semiconductor, Inc.

SIM

SYSTEM INTEGRATION MODULE

REFERENCE MANUAL

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MOTOROLA

-2 For More Information On This Product,

Go to: www.freescale.com

PART NUMBER

MANUAL TYPE

Freescale Semiconductor, Inc.

TABLE OF CONTENTS

Title Paragraph

1.1

1.2

1.3

2.1

2.2

3.2

3.3

3.4

3.5

3.6

3.6.1

3.6.2

3.7

3.1

3.1.1

3.1.2

3.1.3

3.1.4

3.1.5

3.1.6

3.1.7

3.8

3.8.1

3.8.2

3.8.3

3.8.4

4.1

4.1.1

4.1.2

4.2

4.3

Page

SECTION 1INTRODUCTION

Module Mapping ........................................................................................ 1-4

Reset Mode Selection ............................................................................... 1-6

CPU-Specific Differences Affecting SIM Operation ................................... 1-7

SECTION 2 SIGNAL AND PIN DESCRIPTIONS

Pin Characteristics .................................................................................... 2-1

Signal Descriptions .................................................................................... 2-3

SECTION 3 SYSTEM CONFIGURATION AND PROTECTION

Module Configuration and Testing ............................................................ 3-2

Module Mapping ................................................................................ 3-2

Privilege Levels ................................................................................. 3-2

Response to FREEZE Assertion ....................................................... 3-2

Interrupt Arbitration Priority ............................................................... 3-3

Factory Test Mode ............................................................................ 3-3

SIM Configuration Register ............................................................... 3-3

SIM Test Registers ............................................................................ 3-4

Internal Bus Monitor .................................................................................. 3-5

Halt Monitor ............................................................................................... 3-5

Spurious Interrupt Monitor ......................................................................... 3-5

Software Watchdog ................................................................................... 3-6

Periodic Interrupt Timer ............................................................................. 3-7

Prescaler and Modulus Counter ........................................................ 3-7

Interrupt Priority and Vectoring .......................................................... 3-8

Low-Power Stop Operation ....................................................................... 3-9

System Protection Registers ..................................................................... 3-9

Software Service Register (SWSR) ................................................. 3-10

Periodic Interrupt Control Register (PICR) ...................................... 3-10

Periodic Interrupt Timer Register (PITR) ......................................... 3-10

System Protection Register (SYPCR) ............................................. 3-11

SECTION 4 SYSTEM CLOCK

Clock Sources ........................................................................................... 4-1

Internal Phase-Locked Loop ............................................................. 4-1

External Clock Signal ........................................................................ 4-3

Clock Synthesizer Operation ..................................................................... 4-4

External Circuit Design .............................................................................. 4-4

SIM

REFERENCE MANUAL

MOTOROLA iii

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

TABLE OF CONTENTS

(Continued)

Title Paragraph Page

4.3.1

4.3.2

4.3.3

4.4

4.4.1

4.4.2

4.4.3

4.4.4

4.5

4.6

4.7

4.8

Conditioning the XTAL and EXTAL Pins ........................................... 4-4

Crystal Tune-up Procedure ............................................................... 4-5

Conditioning the XFC, V

DDSYN

, and V

SSI

Pins .................................. 4-5

System Clock Frequency Control .............................................................. 4-6

Frequency Control with a Reference Frequency of 25–50 kHz ......... 4-6

Frequency Control with a Reference Frequency of 3.2 – 6.4 MHz ... 4-7

Avoiding Frequency Overshoot ......................................................... 4-7

Frequency Control Tables ................................................................. 4-7

External Bus Clock ................................................................................. 4-11

Low-Power Stop Operation ..................................................................... 4-11

Loss of Reference Signal ........................................................................ 4-12

Clock Synthesizer Control Register (SYNCR) ......................................... 4-13

SECTION 5 EXTERNAL BUS INTERFACE

5.3.1

5.3.2

5.3.3

5.3.4

5.4

5.4.1

5.4.2

5.4.3

5.5

5.5.1

5.5.2

5.1

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

5.1.8

5.1.9

5.1.10

5.1.11

5.2

5.2.1

5.2.2

5.3

Bus Signal Descriptions ............................................................................ 5-1

Address Bus ...................................................................................... 5-2

Address Strobe .................................................................................. 5-2

Data Bus ............................................................................................ 5-2

Data Strobe ....................................................................................... 5-2

Read/Write Signal ............................................................................. 5-2

Size Signals ....................................................................................... 5-2

Function Codes ................................................................................. 5-2

Data and Size Acknowledge Signals ................................................. 5-3

Bus Error Signal ................................................................................ 5-3

Halt Signal ......................................................................................... 5-3

Autovector Signal .............................................................................. 5-3

External Bus Cycle Overview .................................................................... 5-4

Bus Cycle Operation ......................................................................... 5-4

Synchronization to CLKOUT ............................................................. 5-5

Dynamic Bus Sizing .................................................................................. 5-6

Size Signal Encoding ........................................................................ 5-6

Data and Size Acknowledge Signal Encoding .................................. 5-6

Operand Alignment ........................................................................... 5-7

Misaligned Operands ........................................................................ 5-8

Data Transfer Operations .......................................................................... 5-8

Read Cycles ...................................................................................... 5-8

Write Cycles .................................................................................... 5-11

Indivisible Read-Modify-Write Sequence ........................................ 5-13

Operand Transfer Cases ......................................................................... 5-15

Byte Operand to 8-Bit Port .............................................................. 5-16

Byte Operand to 16-Bit Port, Even (ADDR0 = 0) ............................ 5-17

MOTOROLA iv

SIM

REFERENCE MANUAL

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

TABLE OF CONTENTS

(Continued)

Title Paragraph Page

6.1

6.2

6.3

6.4

6.4.1

6.4.2

6.4.3

5.5.3

5.5.4

5.5.5

5.5.6

5.5.7

5.5.8

5.5.9

5.5.10

5.5.11

5.6

5.7

5.7.1

5.7.2

5.7.3

5.8

5.8.1

Byte Operand to 16-Bit Port, Odd (ADDR0 = 1) .............................. 5-17

Word Operand to 8-Bit Port, Aligned ............................................... 5-18

Word Operand to 8-Bit Port, Misaligned .......................................... 5-18

Word Operand to 16-Bit Port, Aligned ............................................. 5-19

Word Operand to 16-Bit Port, Misaligned ........................................ 5-20

Long-Word Operand to 8-Bit Port, Aligned ...................................... 5-20

Long-Word Operand to 8-Bit Port, Misaligned ................................ 5-23

Long-Word Operand to 16-Bit Port, Aligned .................................... 5-24

Long-Word Operand to 16-Bit Port, Misaligned .............................. 5-26

Function Codes and Memory Usage ....................................................... 5-27

System Interfacing Examples .................................................................. 5-28

Connecting an 8-Bit Device to the MCU .......................................... 5-28

Connecting a 16-Bit Memory Device to the MCU ............................ 5-29

Connecting Two 8-bit Memory Devices to the MCU ....................... 5-30

CPU Space Cycles .................................................................................. 5-31

Breakpoint Acknowledge Cycle ....................................................... 5-32

5.8.1.1

5.8.1.2

5.8.2

5.9

5.9.1

5.9.2

5.9.3

5.9.4

Software Breakpoints .............................................................. 5-32

Hardware Breakpoints ............................................................. 5-33

LPSTOP Broadcast Cycle ............................................................... 5-38

Bus Error Processing .............................................................................. 5-38

Bus Error Exceptions ....................................................................... 5-40

Double Bus Faults ........................................................................... 5-42

Retry Operation ............................................................................... 5-43

Halt Operation ................................................................................. 5-45

5.10

Bus Arbitration ......................................................................................... 5-47

5.10.1

Bus Request .................................................................................... 5-48

5.10.2

5.10.3

Bus Grant ........................................................................................ 5-48

Bus Grant Acknowledge .................................................................. 5-49

5.10.4

5.10.5

Bus Arbitration Pin State ................................................................. 5-49

Bus Arbitration Control .................................................................... 5-50

5.10.6

Factory Test (Slave) Mode Arbitration ............................................. 5-52

5.11

Show Cycles ............................................................................................ 5-52

SECTION 6 INTERRUPTS

Sources of Interrupt ................................................................................... 6-1

Interrupt Level and Recognition ................................................................ 6-1

Interrupt Arbitration .................................................................................... 6-2

Interrupt Acknowledge Bus Cycles ............................................................ 6-3

Bus Cycle Terminated by DSACK Signals ........................................ 6-5

Bus Cycle Terminated by AVEC Signal ............................................. 6-6

Spurious Interrupt Cycle .................................................................... 6-8

SIM

REFERENCE MANUAL

MOTOROLA v

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

TABLE OF CONTENTS

(Continued)

Title Paragraph Page

6.5

Interrupt Processing Summary .................................................................. 6-8

SECTION 7 CHIP SELECTS

7.7

7.7.1

7.7.2

7.8

7.8.1

7.8.2

7.9

7.9.1

7.1

7.2

7.3

7.4

7.5

7.5.1

7.5.2

7.6

Chip-Select Options .................................................................................. 7-2

Chip-Select Base Addresses ..................................................................... 7-3

Pin Assignments and Discrete Output ....................................................... 7-4

Chip-Select Operation ............................................................................... 7-5

Chip-Select Timing .................................................................................... 7-9

Synchronization with AS or DS ......................................................... 7-9

Synchronization with ECLK ............................................................. 7-10

Chip Selects and Dynamic Bus Sizing .................................................... 7-10

Fast Termination Cycles .......................................................................... 7-11

Fast-Termination Read Cycle .......................................................... 7-12

Fast-Termination Write Cycle .......................................................... 7-13

Using Chip Selects in Interrupt Acknowledge Cycles .............................. 7-13

Using a Chip-Select Pin as an Interrupt Acknowledge Signal ......... 7-14

Generating an Autovector Signal with a Chip-Select Circuit ........... 7-15

Chip-Select Reset Operation ................................................................... 7-15

Pin Assignment ............................................................................... 7-16

7.9.2

7.9.3

CS[10:0] Base and Option Registers .............................................. 7-16

CSBOOT Base Address and Option Registers ............................... 7-17

7.10

Chip-Select Register Diagrams ............................................................... 7-17

7.10.1

Chip-Select Pin Assignment Registers ............................................ 7-17

7.10.2

7.10.3

Chip-Select Base Address Registers .............................................. 7-19

Chip-Select Option Registers .......................................................... 7-19

7.10.4

Port C Data Register (PORTC) ....................................................... 7-21

7.11

Interfacing Example with Chip Selects .................................................... 7-21

7.11.1

7.11.1.1

7.11.1.2

7.11.1.3

7.11.2

7.11.2.1

7.11.2.2

7.11.2.3

Configuring the RAM Chip Selects .................................................. 7-22

Pin Connections ...................................................................... 7-22

Base Address Registers .......................................................... 7-22

Option Registers ..................................................................... 7-23

Configuring the Boot ROM Chip Select ........................................... 7-23

Pin Connections ...................................................................... 7-23

Base Address Register ........................................................... 7-23

Option Registers ..................................................................... 7-23

8.1

8.2

8.2.1

SECTION 8 RESET AND SYSTEM INITIALIZATION

Reset Operation ........................................................................................ 8-1

Sources of Reset ....................................................................................... 8-2

External Reset ................................................................................... 8-3

MOTOROLA vi

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Paragraph

Freescale Semiconductor, Inc.

TABLE OF CONTENTS

(Continued)

Title Page

8.3.1

8.3.2

8.4

8.4.1

8.4.2

8.5

8.6

8.6.1

8.2.2

8.2.3

8.2.4

8.2.5

8.2.6

8.2.7

8.2.8

8.3

8.6.2

8.6.3

8.6.4

8.7

8.8

8.9

9.1

9.2

9.3

Power-On Reset ................................................................................ 8-3

Software Watchdog Reset ................................................................. 8-3

Double Bus Fault Reset .................................................................... 8-3

Loss of Clock Reset .......................................................................... 8-3

System Reset .................................................................................... 8-4

Test Module Reset ............................................................................ 8-4

Reset Status Register ....................................................................... 8-4

Reset Control Flow .................................................................................... 8-5

RESET Assertion by an External Device .......................................... 8-6

Internal Reset Request ...................................................................... 8-6

Power-On Reset ........................................................................................ 8-6

SIM Operation During Power-On Reset ............................................ 8-6

Other Modules During Power-On Reset ............................................ 8-7

Use of the Three-State Control Pin ........................................................... 8-7

Operating Configuration out of Reset ........................................................ 8-8

Data Bus Mode Selection .................................................................. 8-8

Holding Data Bus Pins Low at Reset ................................................ 8-9

Clock Mode Selection ...................................................................... 8-10

Breakpoint Mode Selection ............................................................. 8-10

Pin State During Reset ............................................................................ 8-11

SIM Registers Out of Reset ..................................................................... 8-13

System Initialization ................................................................................. 8-14

SECTION 9GENERAL-PURPOSE I/O

Pin Assignment Registers ......................................................................... 9-1

Data Direction Registers ........................................................................... 9-2

Data Registers ........................................................................................... 9-3

SECTION 10 REDUCED PIN-COUNT SIM

10.1

Optional RPSIM Pins ............................................................................... 10-1

10.2

Address Bus/Chip Select Pins ................................................................. 10-1

10.3

Data Size and Acknowledge Pins ........................................................... 10-1

10.4

RMC Pin .................................................................................................. 10-2

APPENDIX A

ELECTRICAL CHARACTERISTICS

B.1

APPENDIX BMEMORY MAP AND REGISTERS

SIM Memory Map ..................................................................................... B-1

SIM

REFERENCE MANUAL

MOTOROLA vii

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

TABLE OF CONTENTS

(Continued)

Title Paragraph Page

B.2

SIM Registers ........................................................................................... B-3

MOTOROLA viii

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

LIST OF ILLUSTRATIONS

Title Figure Page

1-1

1-2

3-1

3-2

System Integration Module Block Diagram .................................................... 1-2

SIM Input and Output Signals ........................................................................ 1-3

System Configuration and Protection ............................................................. 3-1

Periodic Interrupt Timer and Software Watchdog Timer ................................ 3-7

4-1

4-2

System Clock with 32.768-kHz Reference Crystal ......................................... 4-2

System Clock with 4.194-MHz Reference Crystal .......................................... 4-3

4-3

4-4

5-1

5-2

5-3

5-4

5-5

5-6

5-7

5-8

5-9

Crystal Layout Example ................................................................................. 4-4

Conditioning the XFC and V

DDSYN

Pins ......................................................... 4-6

Input Sample Window .................................................................................... 5-5

Read Cycle Flowchart .................................................................................... 5-9

Read Cycle Timing Diagram ........................................................................ 5-10

Write Cycle Flow Chart ................................................................................. 5-11

Write Cycle Timing Diagram ......................................................................... 5-13

Read-Modify-Write Timing ............................................................................ 5-14

Operand Byte Order ..................................................................................... 5-15

Byte Operand to 8-Bit Port ........................................................................... 5-16

Byte Operand to 16-Bit Port, Even (ADDR0 = 0) ......................................... 5-17

5-10 Byte Operand to 16-Bit Port, Odd (ADDR0 = 1) ........................................... 5-17

5-11 Word Operand to 8-Bit Port, Aligned ............................................................ 5-18

5-12 Word Operand to 8-Bit Port, Misaligned ....................................................... 5-19

5-13 Word Operand to 16-Bit Port, Aligned .......................................................... 5-19

5-14 Word Operand to 16-Bit Port, Misaligned ..................................................... 5-20

5-15 Long-Word Operand to 8-Bit Port, Aligned ................................................... 5-21

5-16 Timing of a Long-Word Read of an 8-Bit Port .............................................. 5-22

5-17 Timing of a Long-Word Write to an 8-Bit Port .............................................. 5-23

5-18 Long-Word Operand to 8-Bit Port, Misaligned ............................................. 5-24

5-19 Long-Word Operand to 16-Bit Port, Aligned ................................................. 5-25

5-20 Timing of Long-Word Read or Write, 16-Bit Port .......................................... 5-26

5-21 Long-Word Operand to 16-Bit Port, Misaligned ........................................... 5-27

5-22 Connecting an 8-Bit Memory Device ............................................................ 5-29

5-23 Connecting a 16-Bit Memory Device ............................................................ 5-30

5-24 Connecting Two 8-bit Memory Devices ........................................................ 5-31

5-25 CPU Space Address Encoding .................................................................... 5-32

5-26 CPU32 Breakpoint Operation Flow .............................................................. 5-34

5-27 CPU16 Breakpoint Operation Flow .............................................................. 5-35

5-28 Breakpoint Acknowledge Cycle Timing — Opcode Returned (CPU32 Only) 5-36

5-29 Breakpoint Acknowledge Cycle Timing — Exception Signaled .................... 5-37

5-30 LPSTOP Interrupt Mask Level ...................................................................... 5-38

5-31 Bus Error Without DSACK ............................................................................ 5-41

5-32 Late Bus Error with DSACK .......................................................................... 5-42

5-33 Retry Sequence ............................................................................................ 5-44

SIM

REFERENCE MANUAL

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA ix

Freescale Semiconductor, Inc.

LIST OF ILLUSTRATIONS

(Continued)

Title Figure Page

6-5

7-1

7-2

7-2

7-2

7-3

7-4

7-5

5-34 Late Retry Sequence .................................................................................... 5-45

5-35 HALT Timing ................................................................................................. 5-46

5-36 Bus Arbitration Flow Chart for Single Request ............................................. 5-48

5-37 Bus Arbitration State Diagram ...................................................................... 5-51

6-1

6-2

6-3

6-4

Interrupt Acknowledge Read Cycles .............................................................. 6-3

Interrupt Acknowledge Cycle Flowchart ......................................................... 6-4

Interrupt Acknowledge Cycle Timing .............................................................. 6-5

External Connections for Interrupt Processing ............................................... 6-6

Autovector Timing .......................................................................................... 6-7

Chip-Select Circuit Block Diagram ................................................................. 7-2

Flow Diagram for Chip Select (Sheet 1 of 3) .................................................. 7-7

Flow Diagram for Chip Select (Sheet 2 of 3) .................................................. 7-8

Flow Diagram for Chip Select (Sheet 3 of 3) .................................................. 7-9

Fast-Termination Timing .............................................................................. 7-12

CPU Space Encoding for Interrupt Acknowledge Cycles ............................. 7-14

System Configuration with Chip Selects ...................................................... 7-22

8-1

8-2

8-3

8-4

A-1

A-2

A-3

A-4

Reset Block Diagram ...................................................................................... 8-2

Reset Control Flow ......................................................................................... 8-5

Power-On Reset Timing ................................................................................. 8-7

Data Bus Signal Conditioning ....................................................................... 8-10

CLKOUT Output Timing Diagram ................................................................... A-7

External Clock Input Timing Diagram ............................................................. A-7

ECLK Output Timing Diagram ........................................................................ A-7

Read Cycle Timing Diagram .......................................................................... A-9

A-5

A-6

A-7

A-8

Write Cycle Timing Diagram ......................................................................... A-11

Show Cycle Timing Diagram ........................................................................ A-13

Reset and Mode Select Timing Diagram ...................................................... A-14

Bus Arbitration Timing Diagram — Active Bus Case ................................... A-15

A-9 Bus Arbitration Timing Diagram — Idle Bus Case ....................................... A-17

A-10 Fast Termination Read Cycle Timing Diagram ............................................ A-18

A-11 Fast Termination Write Cycle Timing Diagram ............................................. A-20

A-12 ECLK Timing Diagram .................................................................................. A-22

A-13 Chip Select Timing Diagram ......................................................................... A-24

MOTOROLA x

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

LIST OF TABLES

Title Table Page

1-1 SIM Address Map............................................................................................ 1-5

1-2 SIM Reset Mode Selection.............................................................................. 1-7

1-3 CPU Differences Affecting SIM Operation ...................................................... 1-8

2-1 SIM Output Driver Types................................................................................. 2-1

2-2 SIM Pin Characteristics ................................................................................... 2-2

2-3 SIM Signal Characteristics .............................................................................. 2-3

2-4 SIM Signal Function ........................................................................................ 2-4

3-1 Bus Monitor Period.......................................................................................... 3-5

3-2 MODCLK Pin and SWP Bit During Reset ....................................................... 3-6

3-3 Software Watchdog Ratio................................................................................ 3-6

3-4 MODCLK Pin and PTP Bit During Reset......................................................... 3-7

3-5 Periodic Interrupt Priority................................................................................. 3-9

4-1 Clock Control Multipliers.................................................................................. 4-8

4-2 System Frequencies from Typical 32.768-kHz or 4.194-MHz Reference ..... 4-10

4-3 Clock Control................................................................................................. 4-12

5-1 Size Signal Encoding ...................................................................................... 5-6

5-2 DSACK Signal Encodings ............................................................................... 5-7

5-3 Operand Transfer Cases............................................................................... 5-16

5-4 Address Space Encoding .............................................................................. 5-28

5-5 DSACK, BERR, and HALT Assertion Results ............................................... 5-39

5-6 Bus Arbitration Pin State ............................................................................... 5-50

7-1 Option Register Function Summary ................................................................ 7-3

7-2 Block Size Encoding........................................................................................ 7-4

7-3 Chip-Select Pin Functions ............................................................................... 7-5

7-4 Pin Assignment Field Encoding....................................................................... 7-5

7-5 BYTE Field Encoding .................................................................................... 7-11

7-6 Reset Pin Function of CS[5:0], CSBOOT ...................................................... 7-16

7-7 Reset Pin Function of CS[10:6] ..................................................................... 7-16

7-8 CSBOOT Base and Option Register Reset Values....................................... 7-17

7-9 CSPAR0 Pin Assignments ............................................................................ 7-18

7-10 CSPAR1 Pin Assignments ............................................................................ 7-18

8-1 Reset Sources................................................................................................. 8-3

8-2 Reset Mode Selection ..................................................................................... 8-8

8-3 SIM Pin Reset States .................................................................................... 8-12

8-4 SIM Registers Out of Reset........................................................................... 8-13

9-1 Port E Pin Assignments................................................................................... 9-2

9-2 Port F Pin Assignments................................................................................... 9-2

10-1 Optional RPSIM Pins..................................................................................... 10-1

A-1 Clock Control Timing ....................................................................................... A-1

A-2 DC Characteristics .......................................................................................... A-2

A-3 AC Timing........................................................................................................ A-4

SIM

REFERENCE MANUAL

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA xi

Freescale Semiconductor, Inc.

LIST OF TABLES

(Continued)

Title Table Page

A-4 ECLK Bus Timing ............................................................................................ A-6

A-5 Key to Figures A-1, A-2, A-3 ........................................................................... A-8

A-6 Key to Figure A-4 .......................................................................................... A-10

A-7 Key to Figure A-5 .......................................................................................... A-12

A-8 Key to Figure A-6 .......................................................................................... A-13

A-9 Key to Figure A-7 .......................................................................................... A-14

A-10 Key to Figure A-8 .......................................................................................... A-16

A-11 Key to Figure A-9 .......................................................................................... A-17

A-12 Key to Figure A-10 ........................................................................................ A-19

A-13 Key to Figure A-11 ........................................................................................ A-21

A-14 Key to Figure A-12 ........................................................................................ A-23

A-15 Key to Figure A-13 ........................................................................................ A-25

B-1 SIM Address Map............................................................................................ B-1

B-2 Port E Pin Assignments................................................................................... B-6

B-3 Port F Pin Assignments................................................................................... B-7

B-4 CSPAR0 Pin Assignments .............................................................................. B-9

B-5 CSPAR1 Pin Assignments .............................................................................. B-9

B-6 Pin Assignment Encodings............................................................................ B-10

MOTOROLA xii

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

PREFACE

This manual describes the capabilities, operation, and functions of the system integration module (SIM), an integral module of Motorola's family of modular microcontrollers.

Documentation for the Modular Microcontroller Family follows the modular construction of the devices in the product line. Each device has a comprehensive user's manual which provides sufficient information for normal operation of the device. The user's manual is supplemented by module reference manuals, including the SIM reference manual, that provide detailed information about module operation and applications.

Refer to Motorola publication Advanced Microcontroller Unit (AMCU) Literature

(BR1116/D) for a complete listing of documentation.

The following conventions are used throughout the manual.

Logic level one is the voltage that corresponds to Boolean true (1) state.

Logic level zero is the voltage that corresponds to Boolean false (0) state.

To set a bit or bits means to establish logic level one on the bit or bits.

To clear a bit or bits means to establish logic level zero on the bit or bits.

A signal that is asserted is in its active logic state. An active low signal changes from logic level one to logic level zero when asserted, and an active high signal changes from logic level zero to logic level one.

A signal that is negated is in its inactive logic state. An active low signal changes from logic level zero to logic level one when negated, and an active high signal changes from logic level one to logic level zero.

LSB means least significant bit or bits. MSB means most significant bit or bits. References to low and high bytes are spelled out.

A specific bit or signal within a range is referred to by mnemonic and number. For example, ADDR15 is bit 15 of the address bus. A range of bits or signals is referred to by mnemonic and the numbers that define the range. For example, DATA[7:0] form the low byte of the data bus.

SIM

REFERENCE MANUAL

PREFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA i

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SECTION 1INTRODUCTION

The system integration module (SIM) is a module on many Motorola 16- and 32-bit modular microcontroller units (MCUs). SIM-based MCUs contain a SIM, a CPU, and some combination of communication, timing, and memory modules. The different modules perform the following tasks:

• The SIM supplies a clock signal to the rest of the microcontroller, provides system protection features, and manages the external bus. In addition, the SIM provides on-chip chip-select signals and (if the pins are not being used for their alternate functions) I/O ports.

• The CPU contains the microcode to process the instructions in its instruction set.

The CPU also works with the SIM to support exception processing (including processing of interrupts and reset requests), system initialization, special CPU bus cycles (including breakpoint-acknowledge cycles), input/output, and separate supervisor and user privilege levels.

• To understand the SIM, it is necessary to be familiar with the microcontroller's

CPU. Use this reference manual in conjunction with the appropriate CPU reference manual. The CPU16 and CPU32 are the CPUs currently used with the SIM.

1.3 CPU-Specific Differences Affecting SIM Operation

summarizes the differences between the CPU32-based SIM and the CPU16-based SIM.

• Communication and timing modules include an analog-to-digital converter (ADC), time-processing unit (TPU), general-purpose timer (GPT), queued serial module

(QSM), and multichannel communications interface (MCCI). These modules are present in different combinations on different MCUs.

• Memory modules include standby RAM, ROM, EEPROM, Flash EEPROM, and standby RAM with TPU-emulation capabilities (TPURAM). These modules are present in different combinations on different MCUs.

The different modules on an MCU communicate with one another and with external components via the intermodule bus (IMB), a standardized bus developed to facilitate design of modular microcontrollers. The IMB supports 24 address and 16 data lines.

NOTE

On CPU16-based MCUs, external address lines ADDR[23:20] follow the state of ADDR19.

The SIM consists of the following functional blocks:

• The system configuration and protection block controls configuration parameters and provides bus and software watchdog monitors. In addition, it provides a periodic interrupt generator to support execution of time-critical control routines.

• The system clock generates clock signals used by the SIM, other IMB modules, and external devices.

• The external bus interface handles the transfer of information between IMB modules and external address space.

SIM

REFERENCE MANUAL

INTRODUCTION

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

1-1

Freescale Semiconductor, Inc.

• The chip-select block provides 12 chip-select signals. Each chip-select signal has an associated base register and option register that contain the programmable characteristics of that chip select. A data port, port C, is available for discrete output on pins not being used for their chip-select function or alternate function as address or function code lines.

• Two data ports, port E and port F, are available for general-purpose input and output if not required for their alternate function. A port data register, data direction register, and pin assignment register are associated with each port.

• The system test block incorporates hardware necessary for testing the MCU. Its use in normal applications is not supported.

NOTE

Some SIM-based MCUs have a reduced pin set due to pin limitations. Some of the chip-select and data port pins described in this manual may not be present on these MCUs. Refer to the user's manual for the particular MCU for a list of the available pins on that device. Refer to

SECTION 10 REDUCED PIN-COUNT SIM

for additional information.

Figure 1-1 is a block diagram of the SIM.

SYSTEM CONFIGURATION

AND PROTECTION

CLOCK SYNTHESIZER

CHIP SELECTS

CLKOUT

EXTAL

MODCLK

UPPER ADDRESS

CHIP SELECTS

EXTERNAL BUS INTERFACE

EXTERNAL BUS

RESET

FACTORY TEST

TSTME

FREEZE/QUOT

SIM BLOCK

Figure 1-1 System Integration Module Block Diagram

MOTOROLA

1-2

INTRODUCTION

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

Figure 1-2 shows the input and output signals associated with each functional block

of the SIM. These signals are described more fully in

SECTION 2 SIGNAL AND PIN

DESCRIPTIONS

and in subsequent sections of the manual.

CHIP

SELECTS

CS[10:0]

FC2

FC1

FC0

BGACK

BG

BR

CSBOOT

ADDR23/CS10

ADDR22/CS9

ADDR21/CS8

ADDR20/CS7

ADDR19/CS6

FC2/CS5

FC1/CS4

FC0/CS3

BGACK/CS2

BG/CS1

BR/CS0

SIM

ADDR[23:0]

EBI

SIZ1

SIZ0

AS

DS

RMC

AVEC

DSACK1

DSACK0

DATA[15:0]

IRQ[7:1]

MODCLK

CLOCK

TSTME/TSC

TEST

QUOT

FREEZE

FROM CPU

Figure 1-2 SIM Input and Output Signals

SIM

REFERENCE MANUAL

INTRODUCTION

For More Information On This Product,

Go to: www.freescale.com

ADDR[18:0]

SIZ1

SIZ0

AS

DS

RMC

AVEC

DSACK1

DSACK0

DATA[15:0]

R/W

RESET

HALT

BERR

IRQ7

IRQ6

IRQ5

IRQ4

IRQ3

IRQ2

IRQ1

MODCLK

CLKOUT

XTAL

EXTAL

XFC

V DDSYN

TSTME/TSC

FREEZE/QUOT

SIM PINOUT

MOTOROLA

1-3

Freescale Semiconductor, Inc.

1.1 Module Mapping

Control registers for all the modules in the microcontroller are mapped into a 4-Kbyte block. The state of the module mapping (MM) bit in the SIM module configuration register (SIMCR) determines where the control register block is located in the system memory map. When MM is equal to zero, register addresses range from $7FF000 to

$7FFFFF. When MM = 1, register addresses range from $FFF000 to $FFFFFF.

CAUTION

On CPU16-based MCUs, ADDR[23:20] follow the logic state of

ADDR19 unless externally driven. If MM is cleared on these MCUs, the SIM maps IMB modules into an address space which is inaccessible to the CPU. Modules remain inaccessible until reset occurs.

The reset state of MM is one, but the bit can be written once. Initialization software should make certain it remains set by writing a one to it.

Table 1-1

is the SIM register map. The column labeled “Access” indicates the privilege level at which the CPU must be operating to access the register. A designation of “S” indicates that supervisor access is required; a designation of “S/U” indicates that the register can be programmed to the desired privilege level. Refer to

3.1 Module Configuration and Testing for information on assigning privilege levels.

NOTE

CPU16-based MCUs do not support separate supervisor and user privilege levels. The CPU16 always operates at the supervisor privilege level.

Table 1-1 provides SIM register addresses relative to the SIM base address. In this

table, the four high-order nibbles of each address are listed as $####. Refer to the user's manual for the specific MCU for the exact location of these registers. Remember that the MSB is determined by the MM bit.

MOTOROLA

1-4

INTRODUCTION

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

S

S

S

S/U

S

S

S/U

S

S

S

S

S

S

S

S

S

S

S

S

S

S

S

S

S/U

S

S

S

S

S

S

S/U

S/U

S/U

S

S/U

S/U

S/U

S

S

Access

S

S

S

S

S

S

S

SIM

REFERENCE MANUAL

Table 1-1 SIM Address Map

$####22

$####24

$####26

$####28

$####2A

$####2C

$####2E

$####30

$####32

$####34

$####36

$####38

$####3A

$####3C

$####3E

$####40

Address 15 8 7 0

$####00 SIM CONFIGURATION REGISTER (SIMCR)

$####02

$####04

SIM TEST REGISTER (SIMTR)

SYNTHESIZER CONTROL REGISTER (SYNCR)

$####06

$####08

$####0A

$####0C

UNUSED

UNUSED

UNUSED

RESET STATUS REGISTER (RSR)

SYSTEM TEST REGISTER E (SIMTRE)

UNUSED

UNUSED

$####0E

$####10

$####12

$####14

$####16

$####18

$####1A

$####1C

$####1E

$####20

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

PORT E DATA (PORTE0)

PORT E DATA (PORTE1)

PORT E DATA DIRECTION (DDRE)

PORT E PIN ASSIGNMENT (PEPAR)

PORT F DATA (PORTF0)

PORT F DATA (PORTF1)

PORT F DATA DIRECTION (DDRF)

PORT F PIN ASSIGNMENT (PFPAR)

SYSTEM PROTECTION CONTROL

(SYPCR)

$####42

$####44

$####46

$####48

$####4A

$####4C

$####4E

$####50

PERIODIC INTERRUPT CONTROL REGISTER (PICR)

PERIODIC INTERRUPT TIMING REGISTER (PITR)

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

SOFTWARE SERVICE (SWSR)

UNUSED

UNUSED

UNUSED

UNUSED UNUSED

TEST MODULE MASTER SHIFT A (TSTMSRA)

TEST MODULE MASTER SHIFT B (TSTMSRB)

TEST MODULE SHIFT COUNT (TSTSC)

TEST MODULE REPETITION COUNTER (TSTRC)

TEST MODULE CONTROL (CREG)

TEST MODULE DISTRIBUTED (DREG)

UNUSED UNUSED

UNUSED

UNUSED

UNUSED

PORT C DATA (PORTC)

UNUSED

CHIP-SELECT PIN ASSIGNMENT REGISTER (CSPAR0)

CHIP-SELECT PIN ASSIGNMENT REGISTER (CSPAR1)

CHIP-SELECT BASE ADDRESS REGISTER BOOT (CSBARBT)

CHIP-SELECT OPTION REGISTER BOOT (CSORBT)

CHIP-SELECT BASE ADDRESS REGISTER 0 (CSBAR0)

CHIP-SELECT OPTION REGISTER 0 (CSOR0)

CHIP-SELECT BASE ADDRESS REGISTER 1 (CSBAR1)

$####52

$####54

CHIP-SELECT OPTION REGISTER 1 (CSOR1)

CHIP-SELECT BASE ADDRESS REGISTER 2 (CSBAR2)

$####56

$####58

$####5A

CHIP-SELECT OPTION REGISTER 2 (CSOR2)

CHIP-SELECT BASE ADDRESS REGISTER 3 (CSBAR3)

CHIP-SELECT OPTION REGISTER 3 (CSOR3)

INTRODUCTION

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

1-5

Freescale Semiconductor, Inc.

S

S

S

S

S

S

S

Access

S

S

S

S

S

S

S

Table 1-1 SIM Address Map

Address 15 8 7 0

$####5C CHIP-SELECT BASE ADDRESS REGISTER 4 (CSBAR4)

$####5E

$####60

CHIP-SELECT OPTION REGISTER 4 (CSOR4)

CHIP-SELECT BASE ADDRESS REGISTER 5 (CSBAR5)

$####62

$####64

$####66

$####68

CHIP-SELECT OPTION REGISTER 5 (CSOR5)

CHIP-SELECT BASE ADDRESS REGISTER 6 (CSBAR6)

CHIP-SELECT OPTION REGISTER 6 (CSOR6)

CHIP-SELECT BASE ADDRESS REGISTER 7 (CSBAR7)

$####6A

$####6C

$####6E

$####70

$####72

$####74

$####76

$####78

$####7A

$####7C

$####7E

CHIP-SELECT OPTION REGISTER 7 (CSOR7)

CHIP-SELECT BASE ADDRESS REGISTER 8 (CSBAR8)

CHIP-SELECT OPTION REGISTER 8 (CSOR8)

CHIP-SELECT BASE ADDRESS REGISTER 9 (CSBAR9)

CHIP-SELECT OPTION REGISTER 9 (CSOR9)

CHIP-SELECT BASE ADDRESS REGISTER 10 (CSBAR10)

CHIP-SELECT OPTION REGISTER 10 (CSOR10)

UNUSED UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

1.2 Reset Mode Selection

The following information is a concise reference to one aspect of system reset. System reset is a complex operation. To understand SIM operation during and after reset, refer to

SECTION 8 RESET AND SYSTEM INITIALIZATION .

The logic states of certain data bus pins during reset determine the function of SIM pins that can be assigned to more than one function. In addition, the state of the

DATA11 pin determines whether test mode is enabled, the state of the MODCLK pin determines the source of the system clock, and the state of the BKPT pin determines

what happens during subsequent breakpoint assertions. Table 1-2 is a summary of re-

set mode selection options.

MOTOROLA

1-6

INTRODUCTION

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

Mode Select Pin

Table 1-2 SIM Reset Mode Selection

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

DATA9

DATA11

MODCLK

BKPT

Default Function

(Pin Left High)

CSBOOT 16-Bit

CS0

CS1

CS2

CS3

CS4

CS5

CS6

CS[7:6]

CS[8:6]

CS[9:6]

CS[10:6]

DSACK0, DSACK1,

AVEC, DS, AS,

SIZE

IRQ[7:1]

MODCLK

Test Mode Disabled

VCO = System Clock

Background Mode Disabled

Alternate Function

(Pin Pulled Low)

CSBOOT 8-Bit

BR

BG

BGACK

FC0

FC1

FC2

ADDR19

ADDR[20:19]

ADDR[21:19]

ADDR[22:19]

ADDR[23:19]

PORTE

PORTF

Test Mode Enabled

EXTAL = System Clock

Background Mode Enabled

1.3 CPU-Specific Differences Affecting SIM Operation

This reference manual can be used with Motorola modular MCUs that contain a system integration module, regardless of whether the chip contains a CPU16 or CPU32.

Certain aspects of SIM operation, however, vary according to which CPU is present.

Whenever a feature being discussed is CPU-dependent, this manual refers the reader to the appropriate CPU reference manual or to the user's manual for a specific MCU.

The major differences between the CPU16 and CPU32 that affect SIM operation are

summarized in Table 1-3 .

SIM

REFERENCE MANUAL

INTRODUCTION

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

1-7

Freescale Semiconductor, Inc.

Table 1-3 CPU Differences Affecting SIM Operation

Feature

Address Bus

Module Mapping

Exception Vector Table

Privilege Levels

Memory Partitions

RMC pin, port E

Misaligned Transfers

Retry Operation

CPU16 Operation

ADDR[23:20] follow state of ADDR19

MM bit in SIMCR must equal 1

Each vector (except reset vector) is one word; vector table is 512 bytes and is not relocatable (there is no vector base register)

CPU always operates at supervisor privilege level; FC2 always = 1

CPU32 Operation

All 24 lines are operational

MM bit in SIMCR can equal 0 or 1

Each vector (except reset vector) is two words; vector table is 1024 bytes and is relocatable (base address is stored in vector base register)

CPU supports supervisor and user privilege levels; FC2 is active according to privilege level

Memory is fully accessible as 16-Mbyte program and data spaces

Memory partitioned into 16 banks of 64

Kbytes; register extension fields sup-port bank switching; separate 1-Mbyte program and data spaces available

Pin may or may not be connected for I/O

(PE3); RMC function not supported for indivisible read-modify-write operations

Misaligned transfers are allowed

Retry operation not supported

Pin connected, port E fully operational,

RMC asserted during indivisible readmodify-write operations

Misaligned transfers are not supported

Assertion of BERR and HALT results in retry sequence

MOTOROLA

1-8

INTRODUCTION

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

SECTION 2 SIGNAL AND PIN DESCRIPTIONS

The tables in this section summarize functional characteristics of SIM pins. For a more detailed discussion of a particular signal, refer to the section of this manual that dis-

cusses the SIM function or submodule involved. Refer to SECTION 8 RESET AND

SYSTEM INITIALIZATION for details on pin state during and after system reset.

NOTE

On MCUs with a reduced pin-count SIM, some of the pins described

in this section may not be available. Refer to SECTION 10 RE-

DUCED PIN-COUNT SIM for additional information. Refer to the us-

er's manual for the particular MCU for a list of the pins on the chip.

2.1 Pin Characteristics

Table 2-1 shows types of output drivers.

Type

A

Aw

B

Table 2-1 SIM Output Driver Types

Description

Output-only signals that are always driven; no external pull-up required

Type A output with weak P-channel pull-up during reset

Output that includes circuitry to pull up output before high-impedance state is established, to ensure rapid rise time. An external holding resistor is required to maintain logic level while the pin is in the high-impedance state. Assertion of TSC always places these pins in a high-impedance state; in addition, many bus control outputs are placed in a high-impedance state when bus is

granted to an external master. Refer to 5.10 Bus Arbitration for details.

Type B output that can be operated in an open-drain mode Bo

Table 2-2 shows all inputs and outputs. Digital inputs and outputs use CMOS logic lev-

els. An entry in the Discrete I/O column indicates that a pin can also be used for general-purpose input, output, or both. I/O port designation is given when it applies. For details on the states of bus control signals when the bus is granted to an external mas-

ter, refer to 5.10 Bus Arbitration.

SIM

REFERENCE MANUAL

SIGNAL AND PIN DESCRIPTIONS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

2-1

Freescale Semiconductor, Inc.

Table 2-2 SIM Pin Characteristics

Pin

Mnemonic

ADDR23/CS10/ECLK

ADDR[22:20]/CS[9:7] 1

ADDR19/CS6

ADDR[18:0]

AS

AVEC 1

Output

Driver

A

A

BERR

BG/CS1

BGACK/CS2

BR/CS0

CLKOUT 3

CSBOOT

DATA[15:0] 2

DS

B

Aw

DSACK1

DSACK0 1

EXTAL 3

B

B

B

—

FC[2:0]/CS[5:3]

HALT 1

A

Bo

IRQ[7:6] B

B

B

B

B

A

A

A

B

B

IRQ[5:1] 1 B

MODCLK 2 B

R/W

RESET

RMC 1

A

Bo

B

SIZ[1:0]

TSTME/TSC

XFC 3

XTAL 3

B

—

—

—

Y

Y

Y

Y

Y

—

—

Y

Y

Y

Y

Y

Input

Synchronized

Y

Y

Y

—

Y

Y

—

Y

Y

Y

Y

—

Y

Y

Y

Y

—

N

Y

N

N

Y

—

—

Y

Y

N

N

N

Input

Hysteresis

N

N

N

—

N

N

—

N

N

N

N

—

N

N

N

N

Special

NOTES

1. These pins may not be implemented on certain MCUs.

2. DATA[15:0] are synchronized during reset only. MODCLK is synchronized only when used as an input port pin.

3. CLKOUT, EXTAL, XFC, and XTAL are clock reference connections.

—

—

I/O

I/O

—

—

—

O

—

I/O

I/O

I/O

Discrete

I/O

O

O

—

—

—

—

—

O

—

I/O

I/O

—

—

I/O

I/O

I/O

—

PC[2:0]

—

PF[7:6]

PF[5:1]

PF0

—

—

PE3

PE[7:6]

—

—

—

Port

Designation

—

PC[6:4]

PC3

—

PE5

PE2

—

—

—

—

—

—

—

PE4

PE1

PE0

—

MOTOROLA

2-2

SIGNAL AND PIN DESCRIPTIONS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

2.2 Signal Descriptions

The following tables are a quick reference to SIM signals. Table 2-3 shows signal

name, type, and active state. Table 2-4 describes signal functions. Both tables are

sorted alphabetically by mnemonic. Since MCU pins often have multiple functions, more than one description may apply to a pin.

Table 2-3 SIM Signal Characteristics

EXTAL

FC[2:0]

FREEZE

HALT

IRQ[7:1]

MODCLK

PC[6:0]

PE[7:0]

PF[7:0]

R/W

RESET

RMC

SIZ[1:0]

TSC

TSTME

XFC

XTAL

Signal

Name

ADDR[23:0]

AS

AVEC

BERR

BG

BGACK

BR

CLKOUT

CS[10:0]

CSBOOT

DATA[15:0]

DS

DSACK[1:0]

Input

Output

Output

Input/Output

Input

Input

Output

Input/Output

Input/Output

Output

Input/Output

Input/Output

Output

Input

Input

Input

Output

Signal

Type

Bus

Output

Input

Input

Output

Input

Input

Output

Output

Output

Bus

Output

Input

(Port)

1/0

0

0

—

—

0

—

—

—

—

1

0

0

—

(Port)

(Port)

0

—

0

0

0

0

—

0

Active

State

—

0

0

0

0

SIM

REFERENCE MANUAL

SIGNAL AND PIN DESCRIPTIONS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

2-3

Freescale Semiconductor, Inc.

Signal Name

Address Bus

Address Strobe

Autovector

Bus Error

Bus Grant

Bus Grant Acknowledge

Breakpoint

Bus Request

Chip Selects

Boot Chip Select

System Clockout

Data Bus

Data Strobe

Halt

Interrupt Request Level

Data and Size Acknowledge

Reset

Test Mode Enable

Crystal Oscillator

Function Codes

Clock Mode Select

Port C

Port E

Port F

Read-Modify-Write

Read/Write

Size

Three-State Control

External Filter Capacitor

Table 2-4 SIM Signal Function

Mnemonic

ADDR[23:0] 24-bit address bus

AS

AVEC

Function

Indicates that a valid address is on the address bus

Requests an automatic vector during interrupt acknowledge

BERR

BG

BGACK

BKPT

Indicates that a bus error has occurred

Indicates that the MCU has relinquished the bus

Indicates that an external device has assumed bus mastership

Signals a hardware breakpoint to the CPU

BR

CS[10:0]

CSBOOT

CLKOUT

Indicates that an external device requires bus mastership

Select external devices at programmed addresses

Chip select for external boot start-up ROM

System clock output

DATA[15:0] 16-bit data bus

DS During a read cycle, indicates that an external device should place valid data on the data bus. During a write cycle, indicates that valid data is on the data bus.

HALT

IRQ[7:1]

Suspend external bus activity

Provides an interrupt priority level to the CPU

DSACK[1:0] Provide asynchronous data transfers and dynamic bus sizing

RESET System reset

TSTME Hardware enable for SIM test mode

EXTAL, XTAL Connections for clock synthesizer circuit reference; a crystal or an external oscillator can be used

FC[2:0]

MODCLK

PC[6:0]

PE[7:0]

PF[7:0]

RMC

R/W

SIZ[1:0]

TSC

XFC

Identify processor state and current address space

Selects the source and type of system clock

SIM digital output port signals

SIM digital I/O port signals

SIM digital I/O port signals

Indicates indivisible read-modify-write cycle (CPU32 test-and-set instruction)

Indicates the direction of data transfer on the bus

Indicates the number of bytes to be transferred during a bus cycle

Places all output drivers in a high-impedance state

Connection for external phase-locked loop filter capacitor

MOTOROLA

2-4

SIGNAL AND PIN DESCRIPTIONS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

SECTION 3 SYSTEM CONFIGURATION AND PROTECTION

The system configuration and protection submodule controls MCU configuration and testing, monitors internal activity, monitors reset status, and provides periodic interrupt generation. Providing these functions on chip reduces the number of external components in a complete control system.

For a discussion of the reset status register, refer to SECTION 8 RESET AND SYS-

TEM INITIALIZATION. Other aspects of system configuration and protection are dis-

cussed in the following paragraphs. Figure 3-1 is a block diagram of the submodule.

MODULE CONFIGURATION

AND TEST

RESET STATUS

HALT MONITOR

BUS MONITOR

RESET REQUEST

BERR

SPURIOUS INTERRUPT MONITOR

CLOCK SOFTWARE WATCHDOG TIMER RESET REQUEST

2

9

PRESCALER

PERIODIC INTERRUPT TIMER IRQ [7:1]

SYS PROTECT BLOCK

Figure 3-1 System Configuration and Protection

SIM

REFERENCE MANUAL

SYSTEM CONFIGURATION AND PROTECTION

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

3-1

Freescale Semiconductor, Inc.

3.1 Module Configuration and Testing

The SIM configuration register (SIMCR) governs the operation of the system protection block and other aspects of system operation. System protection is discussed in detail later in this section. The following paragraphs describe the other aspects of system configuration controlled by the SIMCR.

3.1.1 Module Mapping

Control registers for all the modules in the microcontroller are mapped into a 4-Kbyte block. The state of the module mapping (MM) bit in the SIM module configuration register (SIMCR) determines where the control register block is located in the system memory map. When MM is equal to zero, register addresses range from $7FF000 to

$7FFFFF. When MM = 1, register addresses range from $FFF000 to $FFFFFF.

CAUTION

On CPU16-based MCUs, ADDR[23:20] follow the logic state of

ADDR19. On these MCUs, if MM is cleared, the SIM maps MCU modules into an address space that is inaccessible to the CPU. Modules remain inaccessible until reset occurs. The reset state of MM is one, but the bit can be written once. Initialization software for these

MCUs should make certain MM remains set by writing a one to it.

3.1.2 Privilege Levels

To protect system resources, the processor in CPU32-based MCUs can operate at either the user or supervisor privilege level. On CPU32-based MCUs, access to most

SIM registers is permitted only when the CPU is operating at the supervisor privilege level. The remaining SIM registers are programmable to permit supervisor access only or to permit access when the CPU is operating at either the supervisor or user privilege level.

If the SUPV bit in the SIMCR is set, access to SIM registers is permitted only when the

CPU is operating at the supervisor level. If SUPV is cleared, then access to certain

SIM registers is permitted when the CPU is operating at either the supervisor or user

privilege level. The SIM address map (Table 1-1) indicates which registers are pro-

grammable to allow access from either privilege level.

CPU16-based MCUs, which do not support the user privilege level, always operate at the supervisor level, so that SIM (and all MCU) registers are always accessible. The state of the SUPV bit has no meaning on these MCUs.

3.1.3 Response to FREEZE Assertion

When the CPU enters background debugging mode, it suspends instruction execution and asserts the internal FREEZE signal. The CPU enters background debugging mode if a breakpoint occurs while background mode is enabled. Refer to the appropriate CPU manual for a discussion of background debugging mode.

Two bits in the SIMCR determine how the SIM responds to FREEZE assertion. Setting the freeze bus monitor (FRZBM) bit in the SIMCR disables the bus monitor when

MOTOROLA

3-2

SYSTEM CONFIGURATION AND PROTECTION

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

FREEZE is asserted. Setting the freeze software watchdog (FRZSW) bit disables the software watchdog and the periodic interrupt timer when FREEZE is asserted. If these bits are cleared when FREEZE is asserted, the bus monitor, software watchdog, and periodic interrupt timer continue to operate normally.

FREEZE assertion has no affect on the halt monitor or spurious interrupt monitor: they continue to operate normally.

3.1.4 Interrupt Arbitration Priority

Each module that can generate interrupts, including the SIM, has an IARB (interrupt arbitration number) field in its module configuration register. Each IARB field has a different value. During an interrupt acknowledge cycle, IARB permits arbitration among simultaneous interrupts of the same priority level.

The reset value of IARB in the SIMCR is $F. This prevents SIM interrupts from being discarded. Initialization software must set the IARB field to a lower value in the range

$F (highest priority) to $1 (lowest priority) if lower priority interrupts are to be arbitrated.

Refer to SECTION 6 INTERRUPTS for additional information.

3.1.5 Factory Test Mode

The internal IMB can be slaved to an external master for direct module testing. This mode is reserved for factory testing. Factory test mode is enabled by holding DATA11 low during reset. The factory test (slave) mode enabled (SLVEN) bit is a read-only bit that shows the reset state of DATA11.

3.1.6 SIM Configuration Register

The SIM configuration register (SIMCRS) controls system configuration. It can be read or written at any time. (Refer to the discussion of the MM bit, however, for certain restrictions.)

SIMCR — Module Configuration Register

15 14 13

EXOFF FRZSW FRZBM

RESET:

0 0 0

12

0

0

11

SLVEN

DATA

11

10

0

0

9

0

SHEN

8

0

7 6

SUPV MM

1 1

5

0

0

4

0

0

3

1 1

IARB

$####00

0

1 1

EXOFF — External Clock Off

0 = The CLKOUT pin is driven from an internal clock source.

1 = The CLKOUT pin is placed in a high-impedance state.

FRZSW — Freeze Software Enable

0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters continue to run.

1 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters are disabled, preventing interrupts during software debugging.

SIM

REFERENCE MANUAL

SYSTEM CONFIGURATION AND PROTECTION

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

3-3

Freescale Semiconductor, Inc.

FRZBM — Freeze Bus Monitor Enable

0 = When FREEZE is asserted, the bus monitor continues to operate.

1 = When FREEZE is asserted, the bus monitor is disabled.

SLVEN — Factory Test (Slave) Mode Enabled

0 = IMB is not available to an external tester.

1 = An external tester has direct access to the IMB.

SHEN[1:0] — Show Cycle Enable

This field determines what the external bus interface does with the external bus during

internal transfer operations. Refer to 5.11 Show Cycles for more information.

SHEN

00

01

10

11

Action

Show cycles disabled, external arbitration enabled

Show cycles enabled, external arbitration disabled

Show cycles enabled, external arbitration enabled

Show cycles enabled, external arbitration enabled; internal activity is halted by a bus grant

SUPV — Supervisor/Unrestricted Data Space

0 = Registers with access controlled by this bit are unrestricted

1 = Registers with access controlled by this bit are restricted to supervisor access only.

MM — Module Mapping

0 = Internal modules are addressed from $7FF000 — $7FFFFF.

1 = Internal modules are addressed from $FFF000 — $FFFFFF.

This bit can be written only once. Subsequent attempts to change this bit are ignored.

Address space $7FF000 – $7FFFFF is inaccessible to the CPU16. On CPU16-based microcontrollers, MM must always be set. Initialization software for these MCUs should make certain MM remains set (its reset state) by writing a one to it.

IARB[3:0] — Interrupt Arbitration Field

IARB determines SIM interrupt arbitration priority. The reset value is $F (highest prior-

ity), to prevent SIM interrupts from being discarded during initialization. Refer to 3.1.4

Interrupt Arbitration Priority and SECTION 6 INTERRUPTS for additional informa-

tion.

3.1.7 SIM Test Registers

SIMTRE — System Integration Test Register (ECLK)

The SIMTRE is used for factory test only.

SIMTR — System Integration Test Register

SIMTR is used for factory test only.

$####08

$####02

MOTOROLA

3-4

SYSTEM CONFIGURATION AND PROTECTION

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

3.2 Internal Bus Monitor

The internal bus monitor checks for excessively long response times during normal bus cycles (those terminated by DSACK, or AVEC during autovector cycles). The

monitor asserts internal BERR when response time is excessive. Refer to SECTION

5 EXTERNAL BUS INTERFACE for a discussion of external bus cycles and DSACK

signals. Refer to SECTION 6 INTERRUPTS for a discussion of AVEC signals during

interrupt acknowledge cycles.

DSACK and AVEC response times are measured in clock cycles. Maximum allowable response time can be selected by setting the bus monitor timing (BMT) field in the sys-

tem protection control register (SYPCR). Table 3-1 shows possible periods.

Table 3-1 Bus Monitor Period

BMT

00

01

10

11

Bus Monitor Time-out Period

64 System Clocks

32 System Clocks

16 System Clocks

8 System Clocks

The monitor does not check DSACK response on the external bus unless the CPU initiates a bus cycle. The BME bit in the SYPCR enables the internal bus monitor for internal to external bus cycles. If a system contains external bus masters, an external bus monitor must be implemented, and the internal to external bus monitor option must be disabled.

Refer to 3.8 System Protection Registers for a register diagram of the SYPCR.

3.3 Halt Monitor

The halt monitor responds to an assertion of HALT on the internal bus. Refer to 5.9

Bus Error Processing for more information. Halt monitor reset can be inhibited by the

halt monitor enable (HME) bit in the SYPCR. Refer to 3.8 System Protection Regis-

ters for a register diagram of the SYPCR.

3.4 Spurious Interrupt Monitor

During interrupt exception processing, the CPU normally acknowledges an interrupt request, arbitrates among various sources of interrupt, recognizes the highest priority source, and then acquires a vector or responds to a request for autovectoring. The spurious interrupt monitor asserts the internal bus error signal (BERR) if no interrupt arbitration occurs during interrupt exception processing. The assertion of BERR causes the CPU to load the spurious interrupt exception vector into the program counter.

The spurious interrupt monitor cannot be disabled. Refer to SECTION 6 INTER-

RUPTS for a comprehensive discussion of interrupts and to 5.9 Bus Error Process-

ing for a discussion of bus error exceptions.

SIM

REFERENCE MANUAL

SYSTEM CONFIGURATION AND PROTECTION

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

3-5

Freescale Semiconductor, Inc.

3.5 Software Watchdog

The software watchdog is controlled by the software watchdog enable (SWE) bit in the

SYPCR. When enabled, the watchdog requires that a service sequence be written to the software service register (SWSR) on a periodic basis. If servicing does not take place, the watchdog times out and asserts the reset signal.

Perform a software watchdog service sequence as follows:

• Write $55 to the SWSR.

• Write $AA to the SWSR.

Both writes must occur in the order listed prior to time-out, but any number of instructions can be executed between the two writes.

Watchdog clock rate is affected by the software watchdog prescale (SWP) and software watchdog timing (SWT) fields in the SYPCR.

SWP determines system clock prescaling for the watchdog timer. Either no prescaling or prescaling by a factor of 512 can be selected. During reset, the state of the MOD-

CLK pin determines the value of SWP, as shown in Table 3-2. System software can

change the value of SWP.

Table 3-2 MODCLK Pin and SWP Bit During Reset

MODCLK SWP

0 (External Clock)

1 (Internal Clock)

1

0

Watchdog

Prescaling

÷

512

÷

1

The SWT field, in conjunction with the SWT bit, selects the divide ratio used to establish software watchdog time-out period. Time-out period is given by the following equations.

Time-out Period = 1/(EXTAL Frequency/Divide Ratio) or

Time-out Period = Divide Ratio/EXTAL Frequency

Table 3-3 gives the ratio for each combination of SWP and SWT bits. When SWT[1:0]

are modified, a watchdog service sequence must be performed before the new timeout period can take effect.

Table 3-3 Software Watchdog Ratio

SWP

0

0

0

0

1

1

1

1

SWT Ratio

00

01

10

2 9

2 11

2 13

11

00

01

2 15

2 18

2 20

10

11

2 22

2 24

MOTOROLA

3-6

SYSTEM CONFIGURATION AND PROTECTION

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

Figure 3-2 is a block diagram of the watchdog timer and the clock control for the pe-

riodic interrupt timer.

PITR

SWP

PTP

FREEZE

EXTAL

CLOCK

DISABLE

PRESCALER (2

9

)

PRECLK

CLOCK

MUX

÷

4

PITCLK

8-BIT MODULUS

COUNTER

SWCLK

15 STAGE

DIVIDER CHAIN (2

15

)

PIT

INTERRUPT

RESET

LPSTOP

SWT1

SWT0

SWE

2

9

2

11

2

13

2

15

PIT BLOCK

Figure 3-2 Periodic Interrupt Timer and Software Watchdog Timer

3.6 Periodic Interrupt Timer

The periodic interrupt timer allows a user to generate interrupts of specific priority at predetermined intervals. This capability is often used to schedule control system tasks that must be performed within time constraints. The timer consists of a prescaler, a modulus counter, and registers that determine interrupt timing and priority and vector assignment.

3.6.1 Prescaler and Modulus Counter

The periodic interrupt modulus counter is clocked by a signal derived from the buffered crystal oscillator (EXTAL) input pin unless an external frequency source is used. The value of the periodic timer prescaler (PTP) bit in the periodic interrupt timer register

(PITR) determines system clock prescaling for the watchdog timer. Either no prescaling or prescaling by a factor of 512 can be selected. During reset, the state of the

MODCLK pin (which also determines the source of the system clock) determines the

value of PTP, as shown in Table 3-4. System software can change the PTP value.

Table 3-4 MODCLK Pin and PTP Bit During Reset

MODCLK PTP

0 (External Clock)

1 (Internal Clock)

1

0

Watchdog

Prescaling

÷

512

÷

1

Either clock signal (EXTAL or EXTAL

÷

512) is divided by four before driving the modulus counter (PITCLK). The modulus counter is initialized by writing a value to the periodic timer modulus (PITM) field in the PITR. A zero value turns off the periodic timer.

SIM

REFERENCE MANUAL

SYSTEM CONFIGURATION AND PROTECTION

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

3-7

Freescale Semiconductor, Inc.

When the modulus counter value reaches zero, an interrupt is generated. The modulus counter is then reloaded with the value in PITM and counting repeats. If a new value is written to the PITM field, it is loaded into the modulus counter when the current count is completed.

Use the following equation to calculate timer period with a 32.768-kHz reference frequency (with a 4.194-MHz reference, first divide the EXTAL frequency by 128):

PIT Period = (PIT Modulus)(Prescaler value)(4)/EXTAL Frequency

For example, when a 32.768-kHz crystal reference frequency is being used to generate the system clock and the PIT prescaler is disabled (PTP = 0), PIT period is determined as follows:

PIT Period = (PIT Modulus)(1)(4)/32768

This results in a PIT period ranging from 122

µ s when PITM = $01 to 31.128 ms when

PITM = $FF.

With the same 32.768-kHz reference crystal and the prescaler enabled (PTP = 1),

PIT Period = (PIT Modulus)(512)(4)/32768

= PIT Modulus/16

This results in a PIT period ranging from 62.5 ms when PITM = $01 to 15.94 s when

PITM = $FF.

For fast calculation of periodic timer period using a 32.768-kHz crystal reference frequency, the following equations can be used. With prescaler disabled,

PIT Period = (PIT Modulus)(122

µ s)

With prescaler enabled,

PIT Period = (PIT Modulus)(62.5 ms)

To use the periodic interrupt timer as a real-time clock interrupt, rearrange the periodic timer period equation to solve for the desired count value. For a timer period of one second, for example, with the prescaler enabled,

PIT Modulus = (PIT Period)(EXTAL)(Prescaler)(4)

= (1)(32768)/(512)(4)

= 16

Therefore, the PITR should be loaded with a value of $10 (16 decimal), with the prescaler enabled, to generate interrupts at a 1-s rate.

3.6.2 Interrupt Priority and Vectoring

Interrupt priority and vectoring are determined by the values of the periodic interrupt request level (PIRQL) and periodic interrupt vector (PIV) fields in the periodic interrupt control register (PICR).

MOTOROLA

3-8

SYSTEM CONFIGURATION AND PROTECTION

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

The content of PIRQL is compared to the CPU interrupt priority mask to determine

whether the interrupt is recognized. Table 3-5 shows the priority of PIRQL values. Due

to SIM hardware prioritization, a PIT interrupt is serviced before an external interrupt request of the same priority. The periodic timer continues to run when the interrupt is disabled.

Table 3-5 Periodic Interrupt Priority

PIRQL

000

001

010

011

100

101

110

111

Priority Level

Periodic Interrupt Disabled

Interrupt Priority Level 1

Interrupt Priority Level 2

Interrupt Priority Level 3

Interrupt Priority Level 4

Interrupt Priority Level 5

Interrupt Priority Level 6

Interrupt Priority Level 7

The PIV field contains the periodic interrupt vector. The vector is placed on the IMB when an interrupt request is made. The method for calculating the vector address from the vector number depends on the CPU. Refer to the appropriate CPU reference man-

ual or to the user manual for the particular MCU for this information. Refer to SECTION

6 INTERRUPTS of this manual for additional details concerning interrupt exception

processing.

Reset value of the PIV field is $0F, which generates the uninitialized interrupt vector.

3.7 Low-Power Stop Operation

When the CPU executes the LPSTOP instruction, the current interrupt priority mask is stored in the clock control logic, and internal clocks are disabled according to the state of the STSIM bit in the SYNCR. The bus monitor, halt monitor, and spurious interrupt monitor are all inactive during low-power stop.

During low power stop, the clock input to the software watchdog timer is disabled, and the timer stops. The software watchdog begins to run again on the first rising clock edge after low power stop ends. The watchdog is not reset by low power stop; a service sequence must be performed to reset the timer.

The periodic interrupt timer does not respond to the LPSTOP instruction. It continues to run at the same frequency as EXTAL during LPSTOP. A periodic timer interrupt can bring the MCU out of low power stop if it has a higher priority than the interrupt mask value stored in the clock control logic when low power stop is initiated. To stop the periodic interrupt timer, the PITR must be loaded with a zero value before the LPSTOP instruction is executed.

3.8 System Protection Registers

The following registers are involved in system protection: the SIMCR, the SWSR, the

PICR, the PITR, and the SYPCR. A register diagram of the SIMCR is provided in 3.1

Module Configuration and Testing. Register diagrams of the other registers are pro-

vided in the following paragraphs.

SIM

REFERENCE MANUAL

SYSTEM CONFIGURATION AND PROTECTION

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

3-9

Freescale Semiconductor, Inc.

3.8.1 Software Service Register (SWSR)

When the software watchdog is enabled, a service sequence must be written to the

SWSR within a specific interval. When read, the SWSR returns all zeros. The register is shown with the read value.

SWSR — Software Service Register

15 14 13 12

NOT USED

11 10 9

RESET

8 7

0

6

0

5

0

4

0

3

0

2

0

$####26

1

0

0

0

0 0 0 0 0 0 0 0

3.8.2 Periodic Interrupt Control Register (PICR)

The PICR contains the interrupt request level and vector number for the periodic interrupt timer. PICR[10:0] can be read or written at any time. PICR[15:11] are unimplemented and always return zero.

PICR — Periodic Interrupt Control Register

15

0

RESET:

14

0

0 0

13

0

0

12

0

0

11

0

0

10

0

9

PIRQP

0

8

0

7

0

6

0

5

0

4

PIB

3

0 1

2

1

$####22

1

1

0

1

PIRQL[2:0] — Periodic Interrupt Request Level

This field determines the priority of periodic interrupt requests.

PIV[7:0] — Periodic Interrupt Vector

The bits of this field contain the periodic interrupt vector number supplied by the SIM when the CPU acknowledges an interrupt request.

3.8.3 Periodic Interrupt Timer Register (PITR)

The PITR contains the count value for the periodic timer. This register can be read or written at any time.

PITR — Periodic Interrupt Timer Register

15

0

RESET:

14

0

0 0

13

0

0

12

0

0

11

0

0

10

0

0

9

0

0

8

PTP

MODCLK

7 6

0 0

PTP — Periodic Timer Prescaler Control

0 = Periodic timer clock not prescaled

1 = Periodic timer clock prescaled by a value of 512

5

0

4

PITM

3

0 0 0

2

$####24

1 0

0 0

MOTOROLA

3-10

SYSTEM CONFIGURATION AND PROTECTION

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

PITM[7:0] — Periodic Interrupt Timing Modulus

This is the 8-bit timing modulus used to determine periodic interrupt rate. Use the following expression to calculate timer period.

PIT Period = [(PIT Modulus)(Prescaler value)(4)]/EXTAL Frequency

3.8.4 System Protection Register (SYPCR)

The system protection control register controls system monitor functions, software watchdog clock prescaling, and bus monitor timing. This register can be written only once following power-on or external reset, but can be read at any time.

SYPCR — System Protection Control Register

15 14 13 12

NOT USED

11 10 9 8 7 6

SWE SWP

RESET:

1

SWE — Software Watchdog Enable

0 = Software watchdog disabled

1 = Software watchdog enabled

SWP — Software Watchdog Prescale

0 = Software watchdog clock not prescaled

1 = Software watchdog clock prescaled by 512

SWT[1:0] — Software Watchdog Timing

This field selects software watchdog time-out period.

5

SWT

4

0 0

3 2

HME BME

0 0

SWP

0

0

0

0

1

1

1

1

Software Watchdog Ratio

SWT Ratio

00

01

10

2 9

2 11

2 13

11

00

01

10

11

2 15

2 18

2 20

2 22

2 24

HME — Halt Monitor Enable

0 = Disable halt monitor function

1 = Enable halt monitor function

BME — Bus Monitor External Enable

0 = Disable bus monitor function for an internal-to-external bus cycle.

1 = Enable bus monitor function for an internal-to-external bus cycle.

$####20

1 0

BMT

0 0

SIM

REFERENCE MANUAL

SYSTEM CONFIGURATION AND PROTECTION

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

3-11

Freescale Semiconductor, Inc.

BMT[1:0] — Bus Monitor Timing

This field selects bus monitor time-out period.

BMT

00

01

10

11

Bus Monitor Period

Bus Monitor Time-Out Period

64 System Clocks

32 System Clocks

16 System Clocks

8 System Clocks

MOTOROLA

3-12

SYSTEM CONFIGURATION AND PROTECTION

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

SECTION 4 SYSTEM CLOCK

The system clock provides timing signals for the IMB modules and for an external peripheral bus. Because the MCU is a fully static design, register and memory contents are not affected when the clock rate changes. An internal phase-locked loop can synthesize the clock from a reference frequency, or the clock signal can be input from an external source.

4.1 Clock Sources

The state of the clock mode (MODCLK) pin during reset determines the source of the system clock. When MODCLK is held high during reset, the clock synthesizer generates a clock signal from the reference frequency. The reference signal is the EXTAL

input to the phase-locked loop. (Refer to 4.2 Clock Synthesizer Operation.) Fre-

quency control bits in the clock synthesizer control register (SYNCR) determine the operating frequency.

When MODCLK is held low during reset and an external clock signal is applied to the

EXTAL pin, the clock synthesizer is bypassed. SYNCR frequency control bits have no effect in this case.

CAUTION

When using the MODCLK pin for I/O (PF0), be sure the external circuitry is designed so that during reset MODCLK is held at the logic level that selects the desired clock mode. After reset, the PF0 bit in the port F data register can be assigned the desired value for I/O.

4.1.1 Internal Phase-Locked Loop

To generate a clock signal with the phase-locked loop (PLL), connect a clock reference to the EXTAL pin and hold MODCLK high during reset. The clock reference can be created by connecting a crystal circuit across the EXTAL and XTAL pins or by connecting an external reference to the EXTAL pin. In the latter case, the XTAL pin must be left floating.

The frequency of the external reference depends on the MCU. Refer to the user's manual for the particular MCU for the range of reference frequencies that can be used with the part. Possible frequency ranges include 25 to 50 kHz and 3.2 to 6.4 MHz. For frequencies in the latter range, the reference frequency is divided internally by 128 be-

fore it is supplied to the PLL. (Refer to 4.2 Clock Synthesizer Operation.) With a

4.194-MHz reference frequency, a signal of 32.768 kHz is provided to the PLL. Clock

synthesizer specifications in Table A-1 of APPENDIX A ELECTRICAL CHARAC-

TERISTICS are based upon a 32.768-kHz or 4.194-MHz reference frequency.

SIM

REFERENCE MANUAL

SYSTEM CLOCK

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

4-1

Freescale Semiconductor, Inc.

Figure 4-1 is a block diagram of the clock submodule and external circuitry with a

Daishinku DMX-38 32.768-kHz crystal providing the reference signal. Figure 4-2

shows the clock submodule with a Daishinku KDS041 4.194-MHz crystal. Resistor and capacitor values depend on the crystal type. Refer to vendor documentation for

recommended values. In addition, refer to 4.3.2 Crystal Tune-up Procedure.

22 pF

2

V SSI

EXTAL

330 k

10M

XTAL

22 pF

2

V SSI

CRYSTAL

OSCILLATOR

PHASE

COMPARATOR

XFC PIN

XFC

1

V DDSYN

0.1

µ

F

0.1

µ

F

V DDSYN

.01

µ

F

LOW-PASS

FILTER

VCO

V SSI

FEEDBACK DIVIDER

W

Y

X

SYSTEM CLOCK CONTROL

SYSTEM

CLOCK

1. Must be low-leakage capacitor (insulation resistance 30,000 M

Ω

or greater).

2. Resistance and capacitance based on a test circuit constructed with a DAISHINKU DMX-38 32.768-kHz crystal.

Specific components must be based on crystal type. Contact crystal vendor for exact circuit.

CLKOUT

SYS CLOCK

BLOCK 32KHZ

Figure 4-1 System Clock with 32.768-kHz Reference Crystal

MOTOROLA

4-2

SYSTEM CLOCK

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

4.194 MHz

22 pF

2

V SSI

EXTAL

1.5 k

1M

22 pF

V SSI

2

CRYSTAL

OSCILLATOR

XTAL

÷

128

3

PHASE

COMPARATOR

XFC PIN

LOW-PASS

FILTER

XFC

1

V DDSYN

0.1

µ

F

0.1

µ

F

V DDSYN

.01

µ

F

VCO

V SSI

FEEDBACK DIVIDER

W

Y

X

CLKOUT

SYSTEM CLOCK CONTROL

SYSTEM

CLOCK

1. Must be low-leakage capacitor (insulation resistance 30,000 M

Ω

or greater).

2. Resistance and capacitance based on a test circuit constructed with a KDS041-18 4.194 MHz crystal.

Specific components must be based on crystal type. Contact crystal vendor for exact circuit.

3. 4 MHz divided to 32 kHz.

16 SYS CLOCK

BLOCK 4MHZ

Figure 4-2 System Clock with 4.194-MHz Reference Crystal

4.1.2 External Clock Signal

To use an external clock source with the MCU, apply the clock signal to the EXTAL pin, and leave the XTAL pin floating. Hold the MODCLK pin low during reset, signaling the MCU to bypass the frequency synthesizer and VCO. SYNCR frequency control bits have no effect in this case.

When an external system clock signal is applied, the duty cycle of the input is critical, especially at operating frequencies close to the maximum. The relationship between the duty cycle of an external clock signal and the clock signal period is expressed as follows:

Minimum external clock period = minimum external clock high/low time

----------------------------------------------------------------------------------------------------------------------------------------------------------------

50% – percentage variation of external clock input duty cycle

Refer to Table A-3 in APPENDIX A ELECTRICAL CHARACTERISTICS for the min-

imum external clock high/low time. The external system clock signal frequency must be less than or equal to the maximum specified system clock frequency.

SIM

REFERENCE MANUAL

SYSTEM CLOCK

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

4-3

Freescale Semiconductor, Inc.

4.2 Clock Synthesizer Operation

When MODCLK is held high during reset, a voltage-controlled oscillator (VCO) in the phase-locked loop generates the system clock signal. A portion of the clock signal is fed back to a divider/counter. The divider controls the frequency of one input to a phase comparator. The other phase comparator input is the reference signal. The comparator generates a control signal proportional to the difference in phase between its two inputs. The signal is low-pass filtered and used to correct VCO output frequency.

The synthesizer locks when VCO frequency is equal to reference frequency (or reference frequency divided by 128, if the reference frequency is a 4.194-MHz crystal).

Lock time is affected by the filter time constant and by the amount of difference between the two comparator inputs. Whenever a comparator input changes, the synthesizer must relock. Lock status is shown by the SLOCK bit in the SYNCR. The MCU does not come out of the reset state until the synthesizer locks.

4.3 External Circuit Design

The following paragraphs discuss design issues relating to the oscillator circuit and external filter circuit.

4.3.1 Conditioning the XTAL and EXTAL Pins

As in all crystal oscillator designs, all leads should be kept as short as possible. It is also good practice to route V

SSI

paths as shown in Figure 4-3. These paths isolate

the oscillator input from the output and the oscillator from adjacent circuitry, only adding capacitance in parallel capacitors C1 and C2.

CRYSTAL

MOTOROLA

4-4

C2 C1

R f

MCU PINS

XTAL EXTAL

SMT XTAL LAYOUT

Figure 4-3 Crystal Layout Example

SYSTEM CLOCK

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

4.3.2 Crystal Tune-up Procedure

The following tune-up procedure applies to crystals with frequencies below 1 MHz. At higher crystal frequencies, because R

S

(the resistance between the external oscillator and the XTAL pin) is normally 0

Ω

, this procedure is not needed. For more specific tuning instructions, contact the crystal manufacturer.

The value of R

S

can be determined experimentally by using the final PCB and an MCU of the exact type that will be used in the final application. The MCU need not have the final software in place. Because of the number of variables involved, use components with the exact properties of those that will be used in production. For example, do not use a ceramic-packaged MCU prototype for the experiment when a plastic-packaged

MCU will be used in production. An emulator version of the part will also have slightly different electrical properties from the masked ROM version of the same part.

To determine the optimum value for R

S

, observe the operating current (I

DDSYN

) of the

MCU as a function of R

S

. The MCU should have only V

DDSYN

powered throughout this procedure because operating current variations when the MCU is running are much greater than the current variations due to varying R

S

. Normally, a dip in current will occur. This dip is not sharp as in many LC circuits, but is rather very broad. As the shape of this curve suggests, the exact value of R

S

is not critical.

Finally, verify that the maximum operating supply voltage does not overdrive the crystal. Observe the output frequency as a function of V

DDSYN

at the buffered CLKOUT output with the device powered up in reset. Under proper operating conditions, the frequency should increase a few parts per million as supply voltage increases. If the crystal is overdriven, an increase in supply voltage will cause a decrease in frequency, or the frequency will become unstable. If frequency problems arise, supply voltage must be decreased, or the values of R

S

and the two capacitors should be increased to reduce the crystal drive.

4.3.3 Conditioning the XFC, V

DDSYN

, and V

SSI

Pins

The XFC, V

DDSYN

, and V

SSI

input lines should be made as free of noise as possible.

Noise on these lines will cause frequency shifts in CLKOUT. Guard ring the XFC line with V

DDSYN

, and guard ring V

DDSYN

with V

SSI

, wherever possible. The XFC filter capacitor and the V

DDSYN

bypass capacitors should be kept as close to the XFC and

V

DDSYN

pins as possible, with no digital logic coupling to either XFC or V

DDSYN

. The ground for the V

DDSYN

bypass capacitors should be tied directly to the V

SSI

ground plane. If possible, route V

DDSYN

and V

SSI

as separate supply runs or planes.

V

DDSYN

may require an inductive or resistive filter to control supply noise.

Figure 4-4 shows the external circuit for the XFC and V

DDSYN

pins.

SIM

REFERENCE MANUAL

SYSTEM CLOCK

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

4-5

Freescale Semiconductor, Inc.

XFC

*

V DDSYN

0.1

µ

F

0.1

µ

F .01

µ

F

V DDSYN V SSI MCU PINS

*

Must be low-leakage capacitor (insulation resistance 30,000 M

Ω

or greater).

XFC VDDSYN CONN

Figure 4-4 Conditioning the XFC and V

DDSYN

Pins

A V

DDSYN

resistive filter would consist of a 100- to 500-ohm resistor from V

DD

to

V

DDSYN

and a 0.1-

µ

F bypass capacitor from V

DDSYN

to V

SSI

. The proper values for the resistor and capacitor can be determined by examining the frequency of the

V

DDSYN

noise. The RC time constant needs to be large enough to filter the supply noise. An inductive filter would replace the resistor with an inductor.

The low-pass filter requires an external low-leakage capacitor (e.g., polypropylene), typically 0.1

µ

F with an insulation resistance specification of 30,000 M

Ω

or greater, connected between the XFC and V

DDSYN

pins.

4.4 System Clock Frequency Control

When the clock synthesizer is used, bits [15:8] of the synthesizer control register

(SYNCR) determine the operating frequency. The W bit controls a prescaler tap in the synthesizer feedback loop. The Y field determines the modulus for a modulo down counter. Y contains a value from 0 to 63; input to the modulo counter is divided by a value of Y

+

1. Both W and Y affect the value of the feedback divider input to the VCO.

Consequently, changing either of these values results in a time delay before the VCO locks in to the new frequency.

The SYNCR X bit controls a divide-by-two prescaler that is not in the synthesizer feedback loop. Setting X doubles the clock speed without changing the VCO speed. Consequently, there is no VCO relock delay.

In order for the device to perform correctly, the clock frequency selected by the W, X,

and Y bits must be within the limits specified in Table A-1 of APPENDIX A ELECTRI-

CAL CHARACTERISTICS. As Table 4-1 and Table 4-2 indicate, with either a 32.768-

kHz or a 4.194-MHz reference frequency, W and X must not both be set when the count modulus is greater than Y = %001111.

4.4.1 Frequency Control with a Reference Frequency of 25–50 kHz

With a reference frequency between 25 and 50 kHz (such as a 32.768-kHz crystal), clock frequency is determined by SYNCR bit settings as follows:

MOTOROLA

4-6

SYSTEM CLOCK

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

F

SYSTEM

= F

REFERENCE

[ (

+ 1

) (

2

2W + X ) ]

The internal VCO frequency is twice the system clock frequency if X = 1 or four times the system clock frequency if X = 0.

The reset state of SYNCR ($3F00) produces a modulus-64 count. The W and X bits are both zero, so that system frequency is 256 times the reference frequency.

4.4.2 Frequency Control with a Reference Frequency of 3.2 – 6.4 MHz

With a reference frequency between 3.2 and 6.4 MHz (such as a 4.194-MHz crystal), the reference frequency is divided by 128 before it is passed to the PLL system. The system clock frequency is determined by SYNCR bit settings as follows:

F

SYSTEM

=

F

REFERENCE

-------------------------------

128

[ (

+ 1

) (

2

2W + X ) ]

The internal VCO frequency is twice the system clock frequency if X = 1 or four times the system clock frequency if X = 0.

The reset state of SYNCR ($3F00) produces a modulus-64 count.

4.4.3 Avoiding Frequency Overshoot

When the W and Y fields in the SYNCR are changed to increase the operating frequency, a frequency overshoot of up to 30% can occur. This overshoot can be avoided by following these procedures:

1. Determine the values for the W and Y fields which will result in the desired frequency when the X bit is set.

2. With the X bit cleared, write these values for the W and Y fields to the SYNCR.

3. After the VCO locks, set the X bit in the SYNCR. This changes the clock frequency to the desired frequency.

For example, follow these procedures to change the clock frequency from 8 to 13 MHz after reset using a 32.768-kHz crystal:

1. Determine the values for the W and Y fields: W = %0, Y = %110100

2. Clear the X bit.

3. Write the values to the SYNCR: W = %0, Y = %110100

4. When the VCO locks, set the X bit.

4.4.4 Frequency Control Tables

Table 4-1 shows how to compute system clock frequency for various combinations of

SYNCR bits. Table 4-2 shows actual clock frequencies for the same combinations of

SYNCR bits. The frequencies in Table 4-2 are valid for typical values of 32.768-kHz

and 4.194-MHz crystal references.

SIM

REFERENCE MANUAL

SYSTEM CLOCK

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

4-7

Freescale Semiconductor, Inc.

Table 4-1 Clock Control Multipliers

To obtain the clock frequency, find the counter modulus in the leftmost column, then multiply the reference frequency by the value in the appropriate prescaler cell. (For 4.194-MHz reference crystals, first divide by 128.) Shaded cells contain values that exceed specifications.

96

100

104

108

112

116

120

124

80

84

88

92

64

68

72

76

48

52

56

60

32

36

40

44

[W:X] = 00

4

8

12

16

20

24

28

128

132

136

140

144

148

152

156

160

164

168

172

176

001101

001110

001111

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

Modulus

Y

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

011101

011110

011111

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

304

312

320

328

336

344

352

240

248

256

264

272

280

288

296

176

184

192

200

208

216

224

232

112

120

128

136

144

152

160

168

[W:X] = 01

8

Prescalers

[W:X] = 10

16

16

24

32

40

32

48

64

80

80

88

96

104

48

56

64

72

96

112

128

144

160

176

192

208

352

368

384

400

416

432

448

464

224

240

256

272

288

304

320

336

608

624

640

656

672

688

704

480

496

512

528

544

560

576

592

768

800

832

864

896

928

960

992

512

544

576

608

640

672

704

736

[W:X] = 11

32

64

96

128

160

192

224

256

288

320

352

384

416

448

480

1024

1056

1088

1120

1152

1184

1216

1248

1280

1312

1344

1376

1408

MOTOROLA

4-8

SYSTEM CLOCK

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

Table 4-1 Clock Control Multipliers (Continued)

To obtain the clock frequency, find the counter modulus in the leftmost column, then multiply the reference frequency by the value in the appropriate prescaler cell. (For 4.194-MHz reference crystals, first divide by 128.) Shaded cells contain values that exceed specifications.

110101

110110

110111

111000

111001

111010

111011

111100

111101

111110

111111

Modulus

Y

101100

101101

101110

101111

110000

110001

110010

110011

110100

[W:X] = 00

180

184

188

192

196

200

204

208

212

216

220

224

228

232

236

240

244

248

252

256

432

440

448

456

464

472

480

488

496

504

512

[W:X] = 01

360

Prescalers

[W:X] = 10

720

368

376

384

392

400

408

416

424

736

752

768

784

800

816

832

848

864

880

896

912

928

944

960

976

992

1008

1024

[W:X] = 11

1440

1472

1504

1536

1568

1600

1632

1664

1696

1728

1760

1792

1824

1856

1888

1920

1952

1984

2016

2048

SIM

REFERENCE MANUAL

SYSTEM CLOCK

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

4-9

Freescale Semiconductor, Inc.

j

Table 4-2 System Frequencies from Typical 32.768-kHz or 4.194-MHz Reference

To obtain the clock frequency, find the counter modulus in the leftmost column, then look in the appropriate prescaler cell. Values are in kilohertz. Shaded cells represent values that exceed maximum system frequency specification.

3146

3277

3408

3539

3670

3801

3932

4063

2097

2228

2359

2490

2621

2753

2884

3015

[W:X] = 00

131 kHz

262

393

524

655

786

918

1049

1180

1311

1442

1573

1704

1835

1966

4194

4325 kHz

4456

4588

4719

4850

4981

5112

5243

5374

5505

5636

001101

001110

001111

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

Modulus

Y

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

011101

011110

011111

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

7864

8126

8389

8651 kHz

8913

9175

9437

9699

9961

10224

10486

10748

11010

11272

5767

6029

6291

6554

6816

7078

7340

7602

3670

3932

4194

4456

4719

4981

5243

5505

[W:X] = 01

262 kHz

Prescaler

[W:X] = 10

524 kHz

524

786

1049

1311

1049

1573

2097

2621

1573

1835

2097

2359

2621

2884

3146

3408

3146

3670

4194

4719

5243

5767

6291

6816

11534

12059

12583

13107

13631

14156

14680

15204

7340

7864

8389

8913

9437

9961

10486

11010

15729

16253

16777

17302 kHz

17826

18350

18874

19399

19923

20447

20972

21496

22020

22544

25166

26214

27263

28312

29360

30409

31457

32506

16777

17826

18874

19923

20972

22020

23069

24117

[W:X] = 11

1049 kHz

2097

3146

4194

5243

6291

7340

8389

9437

10486

11534

12583

13631

14680

15729

33554

34603 kHz

35652

36700

37749

38797

39846

40894

41943

42992

44040

45089

MOTOROLA

4-10

SYSTEM CLOCK

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

Table 4-2 System Frequencies from Typical 32.768-kHz or 4.194-MHz Reference (Continued)

To obtain the clock frequency, find the counter modulus in the leftmost column, then look in the appropriate prescaler cell. Values are in kilohertz. Shaded cells represent values that exceed maximum system frequency specification.

110100

110101

110110

110111

111000

111001

111010

111011

111100

111101

111110

111111

Modulus

Y

101011

101100

101101

101110

101111

110000

110001

110010

110011

[W:X] = 00

5767

5898

6029

6160

6291

6423

6554

6685

6816

6947

7078

7209

7340

7471

7602

7733

7864

7995

8126

8258

8389

[W:X] = 01

11534

11796

12059

12321

12583

12845

13107

13369

13631

13894

14156

14418

14680

14942

15204

15466

15729

15991

16253

16515

16777

Prescaler

[W:X] = 10

23069

23593

24117

24642

25166

25690

26214

26739

27263

27787

28312

28836

29360

2988

30409

30933

31457

31982

32506

33030

33554

[W:X] = 11

46137

47186

48234

49283

50332

51380

52428

53477

54526

55575

56623

57672

58720

59769

60817

61866

62915

63963

65011

66060

67109

4.5 External Bus Clock

The state of the external clock division bit (EDIV) in the SYNCR determines the clock rate for the external bus clock signal (ECLK) available on pin ADDR23. ECLK is a bus clock for MC6800 devices and peripherals. ECLK frequency can be set to the system clock frequency divided by eight or system clock frequency divided by sixteen. The clock is enabled by the CS10 field in chip select pin assignment register 1 (CSPAR1).

The operation of the external bus clock during low-power stop is described below. Re-

fer to SECTION 7 CHIP SELECTS for more information on the external bus clock.

4.6 Low-Power Stop Operation

To reduce overall microcontroller power consumption to a minimum, the CPU can execute the LPSTOP instruction, which causes the SIM to turn off the system clock to most of the MCU.

When the CPU executes LPSTOP, a special CPU space bus cycle writes a copy of the current interrupt mask into the clock control logic. The SIM brings the MCU out of low-power operation when either an interrupt of higher priority than the stored mask or

a reset occurs. Refer to 5.8.2 LPSTOP Broadcast Cycle for more information.

SIM

REFERENCE MANUAL

SYSTEM CLOCK

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

4-11

Freescale Semiconductor, Inc.

During low-power stop, SIM clock control logic and the SIM clock signal (SIMCLK) continue to operate. The periodic interrupt timer and input logic for the RESET and

IRQ pins are clocked by SIMCLK. The SIM can also continue to generate the CLKOUT signal while in low-power mode.

The STSIM (stop mode SIM clock) and STEXT (stop mode external clock) bits in the

SYNCR determine clock operation during low-power stop. Table 4-3 summarizes the

sources of SIMCLK and CLKOUT for different combinations of clock mode, STSIM, and STEXT during low-power stop and normal operation. MODCLK value is the logic level on the MODCLK pin during the last reset prior to LPSTOP execution. Any clock in the off state is held low.

Mode

LPSTOP

No

Yes

Yes

Yes

Yes

No

Yes

Yes

Yes

Yes

Table 4-3 Clock Control

MODCLK

Pins

EXTAL

0

0

External

Clock

External

Clock

0

0

0

1

External

Clock

External

Clock

External

Clock

Crystal/

Reference

1

1

1

1

Crystal/

Reference

Crystal/

Reference

Crystal/

Reference

Crystal/

Reference

SYNCR Bits

STSIM STEXT

X X

0

0

1

1

X

0

0

1

1

0

1

0

1

X

0

1

0

1

Clock Source

SIMCLK CLKOUT

External

Clock

External

Clock

External

Clock

Off

External

Clock

External

Clock

External

Clock

VCO

External

Clock

Off

External

Clock

VCO

Crystal/

Reference

Crystal/

Reference

VCO

Off

Crystal/

Reference

Off

VCO VCO

4.7 Loss of Reference Signal

The state of the reset enable (RSTEN) bit in the SYNCR determines what happens when clock logic detects a reference failure.

When RSTEN is cleared (the default state out of reset), the clock synthesizer is forced into an operating condition referred to as limp mode. Limp mode frequency varies from device to device, but maximum limp frequency does not exceed one half maximum system when X = 0, or maximum system clock frequency when X = 1.

When RSTEN is set, the SIM generates a reset when clock logic detects a reference

failure. Refer to SECTION 8 RESET AND SYSTEM INITIALIZATION for more infor-

mation on reset procedures.

MOTOROLA

4-12

SYSTEM CLOCK

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

4.8 Clock Synthesizer Control Register (SYNCR)

The SYNCR determines system clock operating frequency and mode of operation.

Bits with reset states labeled “U” are unaffected by reset.

SYNCR — Clock Synthesizer Control Register

13 12 11 10 9 8 15

W

RESET:

14

X

0 0 1 1 1

Y

1 1 1

7

EDIV

0

6

0

0

5

0

0

$####04

4 3 2 1 0

SLIMP SLOCK RSTEN STSIM STEXT

U U 0 0 0

W — Frequency Control (VCO)

0 = Base VCO frequency

1 = VCO frequency multiplied by four

Refer to 4.4 System Clock Frequency Control for additional information.

X — Frequency Control Bit (Prescale)

0 = Base system clock frequency

1 = System clock frequency multiplied by two

Refer to 4.4 System Clock Frequency Control for additional information.

Y[5:0] — Frequency Control (Counter)

The Y field is the initial value for the modulus 64 down counter in the synthesizer feed-

back loop. Values range from 0 to 63. Refer to 4.4 System Clock Frequency Control

for additional information.

EDIV — ECLK Divide Rate

0 = ECLK is system clock divided by 8.

1 = ECLK is system clock divided by 16.

Refer to 4.5 External Bus Clock for additional information.

SLIMP — Limp Mode Status

0 = MCU is operating normally.

1 = Loss of reference signal — MCU operating in limp mode.

Refer to 4.7 Loss of Reference Signal for additional information.

SLOCK — Synthesizer Lock

0 = VCO is enabled, but has not locked.

1 = VCO has locked on the desired frequency or system clock is external.

RSTEN — Reset Enable

0 = Loss of clock causes the MCU to operate in limp mode.

1 = Loss of clock causes system reset.

Refer to 4.7 Loss of Reference Signal for additional information.

STSIM — Stop Mode SIM Clock

0 = SIM clock driven by the external reference signal and the VCO is turned off during low-power stop.

1 = SIM clock driven by VCO during low-power stop.

This bit has an effect only if the PLL is configured to supply the clock signal (MODCLK

held high during reset). 4.6 Low-Power Stop Operation has additional information.

SIM

REFERENCE MANUAL

SYSTEM CLOCK

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

4-13

Freescale Semiconductor, Inc.

STEXT — Stop Mode External Clock

0 = CLKOUT held low during low-power stop.

1 = CLKOUT driven from SIM clock during low-power stop.

Refer to 4.6 Low-Power Stop Operation for additional information.

MOTOROLA

4-14

SYSTEM CLOCK

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

SECTION 5 EXTERNAL BUS INTERFACE

The external bus interface (EBI) transfers information between the internal MCU bus and external devices. The external bus has 24 address lines and 16 data lines.

NOTE

On 16-bit MCUs, ADDR[19:0] are normal address outputs, and AD-

DR[23:20] follow the output state of ADDR19.

A three-line handshaking interface performs external bus arbitration. The interface supports byte, word, and long-word transfers. The EBI performs dynamic sizing for data accesses.

The maximum number of bits transferred during an access is referred to as port width.

Widths of eight and sixteen bits can be accessed by means of asynchronous bus cycles controlled by the size (SIZ0 and SIZ1) and the data and size acknowledge

(DSACK0 and DSACK1) signals. Multiple bus cycles may be required for a dynamical-

ly-sized transfer. Refer to 5.3 Dynamic Bus Sizing for more information on data align-

ment and port width. 5.7 System Interfacing Examples provides example system

configurations for different port widths.

NOTE

Some MCUs with reduced pin-count SIMs do not include a DSACK0

pin. Refer to SECTION 10 REDUCED PIN-COUNT SIM for details on

handshaking with these MCUs.

The SIM contains 12 chip-select circuits that can simplify the interface to memory and

peripherals. These chip selects are described in SECTION 7 CHIP SELECTS. The

discussion of the EBI in this section is useful both as a background for understanding chip-select operation and as a guide to interfacing to external devices without the use of SIM chip selects.

NOTE

MCUs with reduced pin count SIMs may contain fewer than 12 chip-

select pins. Refer to SECTION 10 REDUCED PIN-COUNT SIM and

to the user's manual for the particular MCU for details.

5.1 Bus Signal Descriptions

The address bus provides addressing information to external devices. The data bus transfers 8-bit and 16-bit data between the MCU and external devices. Strobe signals, one for the address bus and another for the data bus, indicate the validity of an address and provide timing information for data.

SIM

REFERENCE MANUAL

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

5-1

Freescale Semiconductor, Inc.

Control signals indicate the availability of an address on the bus (AS), validity of data on the bus (DS), the address space where the bus cycle is to occur (FC[2:0]), the size of the transfer (SIZ[1:0]), and the type of cycle (R/W). External devices decode these signals and respond by transferring data and terminating the bus cycle.

5.1.1 Address Bus

Bus signals ADDR[23:0] define the address of the most significant byte to be transferred during a bus cycle. The MCU places the address on the bus at the beginning of a bus cycle. The address is valid while AS is asserted.

5.1.2 Address Strobe

Address strobe (AS) is a timing signal that indicates the validity of an address on the address bus and of many control signals. It is asserted one-half clock after the beginning of a bus cycle.

5.1.3 Data Bus

Bus signals DATA[15:0] comprise a bidirectional, nonmultiplexed parallel bus that transfers data to or from the MCU. A read or write operation can transfer 8 or 16 bits of data in one bus cycle. During a read cycle, the MCU latches the data on the last falling clock edge of the bus cycle. During a write cycle, the MCU places the data on the data bus one half clock cycle after AS is asserted.

5.1.4 Data Strobe

For a read cycle, the MCU asserts data strobe (DS) to signal an external device to place data on the bus. DS is asserted at the same time as AS during a read cycle. For a write cycle, DS signals an external device that data on the bus is valid. The MCU asserts DS one full clock cycle after the assertion of AS during a write cycle.

5.1.5 Read/Write Signal

The read/write (R/W) signal determines the direction of the transfer during a bus cycle.

This signal changes state, when required, at the beginning of a bus cycle, and is valid while AS is asserted. R/W changes state only when a write cycle is preceded by a read cycle or vice versa. The signal may remain low for two consecutive write cycles.

5.1.6 Size Signals

The size signals (SIZ[1:0]) indicate the number of bytes remaining to be transferred during an operand cycle. They are valid while the address strobe (AS) is asserted. Re-

fer to 5.3 Dynamic Bus Sizing for information on SIZ1 and SIZ0 encoding and on us-

ing the SIZ0 and SIZ1 pins in dynamic bus allocation.

5.1.7 Function Codes

The CPU generates function code signals FC[2:0]. The function codes can be considered address extensions that designate which of eight external address spaces is ac-

cessed during a bus cycle. Refer to 5.6 Function Codes and Memory Usage for

information on function code signal encoding and usage.

MOTOROLA

5-2

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

5.1.8 Data and Size Acknowledge Signals

During normal (asynchronous) bus transfers, external devices assert one of the data and size acknowledge signals (DSACK1 and DSACK0) to indicate port width to the

MCU. During a read cycle, these signals also tell the MCU to terminate the bus cycle and to latch data. During a write cycle, they indicate that an external device has suc-

cessfully stored data and that the cycle may terminate. Refer to 5.3 Dynamic Bus Siz-

ing for information on DSACK encoding and dynamic bus sizing.

DSACK1 and DSACK0 can also be supplied internally by chip-select logic. Refer to

SECTION 7 CHIP SELECTS for more information on internally generated DSACK[1:0]

signals.

The designation DSACK is used in this manual as a generic reference to one or both of these signals.

NOTE

Some MCUs with reduced pin-count SIMs do not include a DSACK0

pin. Refer to SECTION 10 REDUCED PIN-COUNT SIM for details on

handshaking with these MCUs.

5.1.9 Bus Error Signal

The bus error (BERR) signal is asserted in the absence of DSACK assertion to indicate a bus error condition. It can also be asserted in conjunction with DSACK to indicate a bus error condition, provided it meets the appropriate timing requirements.

Refer to 5.9 Bus Error Processing for more information.

An external bus master must provide its own BERR generation and drive the BERR

pin. Refer to 5.10 Bus Arbitration for more information.

5.1.10 Halt Signal

An external device can assert the halt signal (HALT) to cause single bus cycle operation. Additionally, on certain MCUs BERR and HALT can be asserted simultaneously

to indicate a retry termination. 5.9 Bus Error Processing provides additional informa-

tion on the HALT signal.

5.1.11 Autovector Signal

The autovector signal (AVEC) can be used to terminate external interrupt acknowledge cycles resulting from interrupts from external IRQ pins. Assertion of AVEC causes the CPU to generate vector numbers to locate an interrupt handler routine. Refer

to SECTION 6 INTERRUPTS for more information. for external interrupt requests can

also be supplied internally by chip-select logic. Refer to SECTION 7 CHIP SELECTS

for more information.

SIM

REFERENCE MANUAL

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

5-3

Freescale Semiconductor, Inc.

5.2 External Bus Cycle Overview

Data transfer operations with external devices consist of one or more external bus cycles. This subsection describes individual bus cycles during each of these transfer op-

erations. 5.3 Dynamic Bus Sizing explains the use of the DSACK[1:0] and SIZ[1:0]

signals and the placement of operands on the data bus. 5.5 Operand Transfer Cases

provides additional details of bus cycle operation for each combination of operand size and port width.

External bus cycles are normally asynchronous, using handshaking between the MCU and external peripherals to indicate transfer size and the availability of data. These accesses typically require a minimum of three system clock cycles. (Two-clock accesses are possible with the chip select fast termination option.) Internal microcontroller modules, in contrast, are typically accessed in two system clock cycles.

The SIM contains 12 chip-select circuits. These on-chip circuits decode EBI address lines and control signals (R/W, SIZ[1:0], AS, DS, and FC[2:0]), reducing the need for external glue logic. Chip-select circuits can also generate the following types of external bus cycles:

• Bus cycles with internally generated DSACK signals.

• Fast termination (two-clock) cycles.

• Bus cycles that are synchronous to the ECLK signal, rather than asynchronous.

(Asynchronous cycles are always terminated with DSACK signals.)

These features are discussed in SECTION 7 CHIP SELECTS. The paragraphs that

follow describe asynchronous external bus cycles that require a minimum of three clock cycles, decode address and control signals externally, and use externally generated DSACK signals.

Bus cycles normally occur in user or supervisor space. Bus cycles that occur in CPU space, which follow most of the protocol of regular external bus cycles, are described

in 5.8 CPU Space Cycles. The interrupt acknowledge cycle, a type of CPU space cy-

cle, is described in SECTION 6 INTERRUPTS.

5.2.1 Bus Cycle Operation

To initiate a transfer, the MCU asserts the appropriate address and SIZ[1:0] signals.

The SIZ[1:0] signals and ADDR0 are externally decoded to select the active portion of

the data bus. (Refer to 5.3 Dynamic Bus Sizing.) The remaining address lines are

decoded to select the peripheral and address within the peripheral.

When AS, DS, and R/W are valid, a peripheral device either places data on the bus during a read cycle or latches data from the bus during a write cycle, then asserts the appropriate DSACK signal to indicate port size.

DSACK signals can be asserted before the data from a peripheral device is valid on a read cycle. To ensure that valid data is latched into the MCU, a maximum period be-

tween DSACK assertion and DS assertion is specified. (Refer to Table A-3 in APPEN-

DIX A ELECTRICAL CHARACTERISTICS.)

MOTOROLA

5-4

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

There is no specified maximum for the period between AS assertion and DSACK assertion. Although the MCU can transfer data in a minimum of three clock cycles when the cycle is terminated with DSACK, the MCU inserts wait cycles in clock period increments until either DSACK signal goes low.

NOTE

The SIM bus monitor asserts BERR when response time exceeds a predetermined limit. Bus monitor period is determined by the BMT field in the system protection control register (SYPCR). The bus monitor cannot be disabled; maximum monitor period is 64 system clock cycles.

If no peripheral responds to an access or if an access is invalid, external logic should assert the BERR signal to abort the bus cycle. If BERR or bus termination signals are not asserted within the specified bus monitor time-out period, the bus monitor, if enabled for internal to external bus cycles, terminates the cycle.

5.2.2 Synchronization to CLKOUT

All external asynchronous input signals must be synchronized to the MCU clock before being acted upon. The CLKOUT (system clock output) signal enables external devices to synchronize DSACK and other signals with the MCU system clock.

For all inputs, the MCU latches the level of the input during a sample window around

the falling edge of CLKOUT. (Refer to Figure 5-1.) To ensure that an input signal is

recognized on a specific falling edge of the clock, that input must be stable during the sample window. If an input makes a transition during the window time period, the level recognized by the MCU is not predictable; however, the MCU always resolves the latched level to a logic high or low before using it.

t su t h

CLKOUT

EXT

SAMPLE WINDOW

Figure 5-1 Input Sample Window

INPUT SAMPLE TIM

SIM

REFERENCE MANUAL

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

5-5

Freescale Semiconductor, Inc.

When the specifications for asynchronous setup and hold time are met, the MCU is guaranteed to recognize the appropriate signal on a specific edge of the CLKOUT signal. For a read cycle, when assertion of DSACK is recognized on a particular falling edge of the clock, valid data is latched into the MCU on the next falling clock edge, provided that the data meets the data setup time.

When a system asserts DSACK for the required window around the falling edge of

state 2 (see 5.4.1 Read Cycles and 5.4.2 Write Cycles) and obeys the bus protocol

by maintaining DSACK until and throughout the clock edge that negates AS, no wait states are inserted. The bus cycle runs at the maximum speed of three clocks per cycle.

5.3 Dynamic Bus Sizing

Dynamic bus sizing allows the MCU to move byte, word, or long-word data to either an 8-bit or 16-bit memory or peripheral system.

The MCU and target device use the SIZ[1:0], DSACK[1:0], and ADDR0 signals to indicate the operand and port size and operand alignment (even or odd address). Based on this information, the MCU places the data on or reads the data from the appropriate byte or bytes of the data bus.

5.3.1 Size Signal Encoding

When the MCU starts to perform an access to an external device, it uses the SIZ[1:0]

pins to inform the external device of the size of the intended data transfer. Table 5-1

shows the encodings for the size signals.

Table 5-1 Size Signal Encoding

SIZ1

0

1

1

0

SIZ0

1

0

1

0

Transfer Size

Byte

Word

3 Byte

Long Word

If a transfer operation requires more than one bus cycle, the MCU automatically updates the SIZ[1:0] pins at the start of each cycle to reflect the number of remaining bytes to be transferred. For example, a word write to an 8-bit port requires two bus cycles. During the first cycle, the MCU drives 1 and 0 on the SIZ1 and SIZ0 pins, respectively. During the second cycle, the MCU drives 0 and 1 on these pins.

5.3.2 Data and Size Acknowledge Signal Encoding

The external device signals its port size and indicates completion of the bus cycle to the MCU through the use of the DSACK inputs. If the processor attempts to write a word to an 8-bit port, for example, the DSACK pins inform the processor that the port is only 8 bits wide, and the processor initiates a second bus cycle to write the remaining byte.

Table 5-2 shows DSACK encodings.

MOTOROLA

5-6

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

DSACK1

1

1

0

0

Table 5-2 DSACK Signal Encodings

DSACK0

1

0

1

0

Result

Insert Wait States — in Current Bus Cycle

Complete Cycle — Data Bus Port Size is 8 Bits

Complete Cycle — Data Bus Port Size is 16 Bits

Reserved (Defaults to 16-bit Port)

NOTE

Some MCUs with reduced pin count SIMs do not contain a DSACK0

pin. Refer to SECTION 10 REDUCED PIN-COUNT SIM for details on

handshaking with these MCUs.

Chip-select logic can generate data and size acknowledge signals for an external de-

vice. Refer to SECTION 7 CHIP SELECTS for details on generating DSACK signals

with chip selects.

5.3.3 Operand Alignment

Operand alignment on the data bus is determined by the ADDR0, SIZ[1:0], and

DSACK[1:0] signals. To understand operand alignment more fully, refer to the individ-

ual cases described in 5.5 Operand Transfer Cases. The following paragraphs sum-

marize the procedure the EBI follows for aligning operands.

The EBI dynamically determines the port size of the target device during each bus cycle. The EBI begins each bus cycle by assuming a 16-bit port and then determines the actual state of affairs based on the DSACK signals returned by the target device.

During a write cycle, the EBI routes the bytes of the operand to the bytes of the data bus so that both 8- and 16-bit devices can retrieve the data. The EBI signals the location of the data to the target device through the SIZ[1:0] and ADDR0 pins.

This scheme implies that in some cases both bytes of the data bus are copies of the same byte of the operand and that in some cases one of the bytes of the data bus will be unused by the target device.

During a read cycle, the EBI uses the encoding of the DSACK[1:0] pins to determine the location of the valid data on the data bus. This method implies that in some cases, the EBI must reroute a byte of data internally to the operand latch, and that sometimes a byte of data is ignored.

Table 5-3 indicates the location of valid data for each combination of operand size,

port size, and even or odd address for read and write cycles.

Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular port size be fixed. A 16-bit port must be connected to data bus bits

[15:0], and an 8-bit port must be connected to data bus bits [15:8]. This minimizes the number of bus cycles needed to transfer data and ensures that the MCU transfers valid data.

SIM

REFERENCE MANUAL

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

5-7

Freescale Semiconductor, Inc.

The largest amount of data that can be transferred by a single bus cycle is an aligned word. If the MCU transfers a long-word operand via a 16-bit port, the most significant operand word is transferred on the first bus cycle and the least significant operand word on a following bus cycle.

5.3.4 Misaligned Operands

For external bus cycles, the basic operand size of both the CPU16 and CPU32 processors is 16 bits. An operand is misaligned when it overlaps a word boundary. When

ADDR0 = 0, indicating an even address, the address is on a word and byte boundary.

When ADDR0 = 1, indicating an odd address, the address is on a byte boundary only.

A byte operand is aligned at any address; a word or long-word operand is misaligned at an odd address.

NOTE

The CPU16 can perform misaligned word transfers. This capability makes it compatible with the M68HC11 CPU. The CPU16 treats misaligned long-word transfers as two misaligned word transfers. The

CPU32, however, does not support misaligned word transfers. Refer to the user's manual for the specific MCU or CPU for additional information.

5.4 Data Transfer Operations

The following paragraphs provide detailed descriptions of read and write bus cycles.

Following these descriptions is a discussion of the CPU32 indivisible read-modifywrite operation, which consists of one or more read cycles followed by one or more write cycles.

5.4.1 Read Cycles

During a read operation, the MCU transfers data from an external memory or peripheral device. A read operation consists of one or more read cycles. If the instruction specifies a long-word or word operation, the MCU attempts to read two bytes per cycle. For a byte operation, the MCU reads one byte. The portion of the data bus from which each byte is read depends on operand size, peripheral address, and peripheral

port size. Refer to 5.3 Dynamic Bus Sizing for more information. Figure 5-2 is a flow

chart of a word read cycle.

MOTOROLA

5-8

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

MCU

ADDRESS DEVICE (S0)

1) SET R/W TO READ

2) DRIVE ADDRESS ON ADDR[23:0]

3) DRIVE FUNCTION CODE ON FC[2:0]

4) DRIVE SIZ[1:0] FOR OPERAND SIZE

PERIPHERAL

ASSERT AS AND DS (S1)

DECODE DSACK (S3)

LATCH DATA (S4)

PRESENT DATA (S2)

1) DECODE ADDR, R/W, SIZ[1:0], DS

2) PLACE DATA ON DATA[15:0] OR

DATA[15:8] IF 8-BIT DATA

3) DRIVE DSACK SIGNALS

NEGATE AS AND DS (S5) TERMINATE CYCLE (S5)

1) REMOVE DATA FROM DATA BUS

2) NEGATE DSACK

START NEXT CYCLE (S0)

RD CYC FLOW

Figure 5-2 Read Cycle Flowchart

A read cycle consists of the following states. The designation “state” refers to the logic level of the clock signal, and does not correspond to any implemented machine state.

A clock cycle consists of two successive states.

State 0 (S0) — The read cycle starts. The MCU places an address on ADDR[23:0] and function codes on FC[2:0]. (On CPU16-based MCUs, ADDR[23:20] always follow the state of ADDR19, and FC2 is always equal to one.) The MCU drives R/W high for a read cycle. SIZ[1:0] become valid, indicating the number of bytes to be read.

State 1 (S1) — The MCU asserts AS, indicating that the address on the address bus is valid. The MCU also asserts DS, signaling the peripheral to place data on the bus.

State 2 (S2) — External logic decodes ADDR[23:0], FC[1:0], R/W, SIZ[1:0], and DS.

One or both of DATA[15:8] and DATA[7:0] are selected, and the responding device places data on that portion of the bus. Concurrently, the device asserts the appropriate

DSACK signals. For the MCU to be guaranteed to latch the data in minimum cycle time, at least one DSACK signal must be recognized as asserted by the end of S2.

(That is, it must meet the input setup time requirement preceding the falling edge of

S2.) For wait states to be guaranteed to be inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and hold times at the end of

S2.

SIM

REFERENCE MANUAL

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

5-9

Freescale Semiconductor, Inc.

State 3 (S3) — When a change in one or both of the DSACK signals has been recognized, the MCU latches data from the bus on the next falling edge of the clock (S4), and the cycle terminates (S5). If neither DSACK signal is recognized as asserted by the start of S3, the MCU inserts wait states instead of proceeding to S4 and S5. While wait states are added, the MCU continues to sample the DSACK signals on falling edges of the clock until a change in one or more is recognized. In effect, S3 and S4 repeat until a change in the DSACK signals is detected.

State 4 (S4) — If a change in the DSACK signals is detected by the beginning of S3, the MCU latches data on the falling edge at the end of S4. If not, S3 and S4 repeat until a change in the DSACK signals is detected.

State 5 (S5) — The MCU negates AS and DS, but holds the address valid to provide address hold time for memory systems. R/W, SIZ[1:0], and FC[2:0] also remain valid throughout S5. The external device must maintain data and assert the DSACK signals until it detects the negation of either AS or DS. The external device must remove the data and negate DSACK within approximately one clock period after sensing the negation of AS or DS. Signals that remain asserted beyond this limit can be prematurely detected during the next bus cycle.

Figure 5-3 is a timing diagram of a read cycle.

S0 S2 S4 S0

CLKOUT

ADDR[23:0]

FC[2:0]

SIZ[1:0]

R/W

AS

DS

DSACK

DATA[15:0]

READ

RD-MOD-WR RD TIM

Figure 5-3 Read Cycle Timing Diagram

MOTOROLA

5-10

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

5.4.2 Write Cycles

During a write operation, the MCU transfers data to an external memory or peripheral device. A write operation consists of one or more write cycles. If the instruction specifies a long-word or word operation, the MCU attempts to write two bytes per cycle. For a byte operation, the MCU writes one byte. The portion of the data bus to which each byte is written depends on operand size, peripheral address, and peripheral port size.

Refer to 5.3 Dynamic Bus Sizing for more information. Figure 5-4 is a flow chart of

a write cycle for a word transfer.

MCU

ADDRESS DEVICE (S0)

1) SET R/W TO WRITE

2) DRIVE ADDRESS ON ADDR[23:0]

3) DRIVE FUNCTION CODE ON FC[2:0]

4) DRIVE SIZ[1:0] FOR OPERAND SIZE

PERIPHERAL

ASSERT AS (S1)

PLACE DATA ON DATA[15:0] (S2)

ASSERT DS AND WAIT FOR DSACK (S3)

OPTIONAL STATE (S4)

NO CHANGE

ACCEPT DATA (S2 + S3)

1) DECODE ADDRESS

2) LATCH DATA FROM DATA BUS

3) ASSERT DSACK SIGNALS

TERMINATE OUTPUT TRANSFER (S5)

1) NEGATE AS AND DS

2) REMOVE DATA FROM DATA BUS

TERMINATE CYCLE

1) NEGATE DSACK

START NEXT CYCLE

WR CYC FLOW

Figure 5-4 Write Cycle Flow Chart

State 0 (S0) — The MCU places an address on ADDR[23:0] and function codes on

FC[2:0]. (On CPU16-based MCUs, ADDR[23:20] always follow the state of ADDR19, and FC2 is always equal to one.) The MCU drives R/W low for a write cycle. SIZ[1:0] become valid, indicating the number of bytes to be written.

SIM

REFERENCE MANUAL

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

5-11

Freescale Semiconductor, Inc.

State 1 (S1) — The MCU asserts AS, indicating that the address on the address bus is valid.

State 2 (S2) — The MCU places the data on DATA[15:0], then begins to sample the

DSACK signals. External logic decodes the address lines, FC[1:0], R/W, SIZ[1:0], and

AS. One or both of DATA[15:8] and DATA[7:0] are selected, and appropriate DSACK signals are asserted. For the MCU to be guaranteed to latch the data in minimum cycle time, the MCU must recognize a change in at least one DSACK signal by the end of

S2 (that is, the DSACK signal must meet the input setup and hold time requirements).

For wait states to be guaranteed to be inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and hold times at the end of

S2.

State 3 (S3) — The MCU asserts DS to indicate that data is stable on the data bus, and the selected peripheral latches the data. When a change in one or both of the

DSACK signals has already been recognized, S4 elapses, and the cycle terminates during S5. If neither DSACK signal changes state by the start of S3, the MCU inserts wait states instead of proceeding to S4 and S5. While wait states are added, the MCU continues to sample the DSACK signals on falling edges of the clock until a change in one or more is recognized. In effect, S3 repeats until a change in the DSACK signals is detected.

State 4 (S4) — The MCU issues no new control signals during S4.

State 5 (S5) — The MCU negates AS and DS, but holds the address and data valid to provide address hold time for memory systems. R/W, SIZ[1:0], and FC[2:0] also remain valid throughout S5. The external device must assert the DSACK signals until it detects the negation of either AS or DS. It must negate DSACK within approximately one clock period after sensing the negation of AS or DS. Signals that remain asserted beyond this limit can be prematurely detected during the next bus cycle.

Figure 5-5 is a timing diagram of a write cycle.

MOTOROLA

5-12

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

S0 S2 S4 S0

CLKOUT

ADDR[23:0]

FC[2:0]

SIZ[1:0]

R/W

AS

DS

DSACK

DATA[15:0]

WRITE

RD-MOD-WR WR TIM

Figure 5-5 Write Cycle Timing Diagram

5.4.3 Indivisible Read-Modify-Write Sequence

The indivisible read-modify-write sequence provides semaphore capabilities for multiprocessor systems. This sequence performs a read, conditionally modifies the data in the arithmetic logic unit, and may write the data out to memory. During the entire readmodify-write sequence, the MCU asserts the RMC signal to indicate that an indivisible operation is occurring. The MCU does not issue a bus grant (BG) signal in response to a bus request (BR) signal during this operation.

The CPU32 test-and-set (TAS) instruction is the only instruction that generates an indivisible read-modify-write memory cycle. Refer to the CPU32 Reference Manual

(CPU32RM/AD) for information on this instruction.

NOTE

The CPU16 does not support the RMC signal or the TAS instruction.

Figure 5-6 is an example of a functional timing diagram of a read-modify-write instruc-

tion specified in terms of clock periods.

SIM

REFERENCE MANUAL

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

5-13

Freescale Semiconductor, Inc.

CLKOUT

ADDR[23:0]

FC[2:0]

SIZ[1:0]

R/W

RMC

AS

DS

DSACK

S0 S2 S4

DATA[15:0]

READ

S0 S2 S4 S0

WRITE

INDIVISIBLE

CYCLE

RD-MOD-WR TIM

Figure 5-6 Read-Modify-Write Timing

The read-modify-write sequence consists of one or more read cycles, followed by idle states, followed by one or more write cycles. The read and write cycles are similar to those previously described. The differences are summarized as follows:

Read Cycles. If more than one read cycle is required to read the operand, S0–S5 are repeated for each read cycle. In S0, the MCU asserts RMC to identify a read-modifywrite cycle. When finished reading in S5, the MCU holds the address, R/W, and

FC[2:0] valid in preparation for the write portion of the cycle.

Idle States. The MCU does not assert any new control signals during the idle states between the read and write cycles, but it may internally begin the modify portion of the cycle at this time. If a write cycle is required, the R/W signal continues to signal a read operation until state 0 of the write cycle to prevent bus conflicts with the preceding read portion of the cycle.

Write Cycle. The write cycle is omitted if it is not required. If more than one write cycle is required, S0–S5 are repeated for each write cycle. During S0, the MCU drives R/W low for a write cycle. Depending on the write operation to be performed, the address

MOTOROLA

5-14

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

lines may change during S0. Function code and size signals do not change.

5.5 Operand Transfer Cases

Table 5-3 summarizes operand alignment for various types of transfers. Subsequent

subsections discuss each allowable transfer case in detail.

In Table 5-3, operand bytes are designated as shown in Figure 5-7. OP0 – OP3 rep-

resent the order of access. For instance, OP0 is the most significant byte of a longword operand, and is accessed first, while OP3, the least significant byte, is accessed last. The two bytes of a word-length operand are OP0 (most significant) and OP1. The single byte of a byte-length operand is OP0.

Operand

Long Word

Three Byte

Word

Byte

31

OP0

24 23

Byte Order

16 15

OP1 OP2

OP0 OP1

OP0

8 7

OP3

OP2

OP1

OP0

0

Figure 5-7 Operand Byte Order

In Table 5-3, an X in a column means that the state of the signal has no effect. Blank

entries in the data bus columns represent bytes of the data bus that the CPU ignores during read cycles. Operands in parentheses are placed on the data bus but ignored by the peripheral during write cycles. The “Next Cycle” column indicates the number of the transfer case for the next bus cycle of the transfer operation. A blank in the “Next

Cycle” column indicates that the transfer is complete.

SIM

REFERENCE MANUAL

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

5-15

Freescale Semiconductor, Inc.

Num Transfer Case

1 Byte to 8-bit Port

(Even/Odd)

2 Byte to 16-bit Port (Even)

3 Byte to 16-bit Port (Odd)

4 Word to 8-bit Port

(Aligned)

5 Word to 8-bit Port

(Misaligned) 1

6 Word to 16-bit Port

(Aligned)

7 Word to 16-bit Port

(Misaligned) 1

8 Long Word to 8-bit Port

(Aligned)

9 Long Word to 8-bit Port

(Misaligned) 1,3

10 Long Word to 16-bit Port

(Aligned)

11 Long Word to 16-bit Port

(Misaligned) 1,3

12 3 Byte to 8-bit Port

(Aligned) 2

13 3 Byte to 8-bit Port

(Misaligned) 2

Table 5-3 Operand Transfer Cases

SIZ[1:0] ADDR0 DSACK[1:0] Read

DATA

[15:8]

01 X 10 OP0

Cycles

DATA

[7:0]

—

Write

DATA

[15:8]

OP0

Cycles

DATA

[7:0]

OP0

Next

Cycle

—

01

01

10

10

10

10

00

10

00

10

11

11

0

1

0

1

0

1

0

1

0

1

0

1

01

01

10

10

01

01

10

10

01

01

10

10

OP0

—

OP0

OP0

OP0

—

OP0

OP0

OP0

—

OP0

OP0

— OP0 (OP0)

OP0 (OP0) OP0

— OP0 (OP1)

—

OP1

OP0 (OP0) OP0

—

—

OP1

—

—

OP0 (OP0)

OP0 OP1

—

—

1

1

—

2

OP0 (OP1) 13

OP0 (OP0) 12

OP0 OP1

OP0 (OP0) OP0

OP0 (OP1)

OP0 (OP0)

6

2

5

4

NOTES:

1. The CPU32 does not support misaligned transfers.

2. Three-byte transfer cases occur only as a result of a long word to byte transfer.

3. The CPU16 treats misaligned long-word transfers as two misaligned-word transfers.

5.5.1 Byte Operand to 8-Bit Port

For an eight-bit port, consecutive bytes of data can be read from and written to consecutive byte addresses in the memory system. To initiate a transfer, the MCU places the desired address on the address bus and drives the size pins to indicate a singlebyte operand. Since bytes of data can be written to either odd or even addresses,

ADDR0 can be either zero or one. The MCU also drives the function code and R/W pins to appropriate values.

Operand

Data Bus

Cycle 1

7

15

OP0

OP0

0

8 7

(OP0)

0 SIZ1

0

SIZ0

1

ADDR0

X

DSACK1 DSACK0

1 0

Figure 5-8 Byte Operand to 8-Bit Port

MOTOROLA

5-16

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

For a read operation, the 8-bit peripheral responds by placing OP0 on DATA[15:8] and asserting DSACK0. The MCU reads OP0 from DATA[15:8] and ignores DATA[7:0].

For a write operation, the MCU drives OP0 on both bytes of the data bus. The peripheral determines the operand size and transfers the data from the upper byte of the data bus to the specified address, then asserts DSACK0 to terminate the bus cycle.

5.5.2 Byte Operand to 16-Bit Port, Even (ADDR0 = 0)

To initiate a transfer, the MCU places the desired address on the address bus and drives the size pins to indicate a single-byte operand. The MCU also drives the function code and R/W pins to appropriate values.

Operand

Data Bus

Cycle 1

7

OP0

15

OP0

0

8 7

(OP0)

0 SIZ1

0

SIZ0

1

ADDR0

0

DSACK1 DSACK0

0 1

Figure 5-9 Byte Operand to 16-Bit Port, Even (ADDR0 = 0)

For a read operation, the 16-bit peripheral responds by placing OP0 on DATA[15:8] and asserting DSACK1. The MCU reads the data from DATA[15:8] and ignores DA-

TA[7:0].

For a write operation, the MCU drives OP0 onto both bytes of the data bus. The peripheral determines operand size and transfers the data from the upper byte of the data bus to the specified address, then asserts DSACK1 to terminate the bus cycle.

In order to read or write to individual bytes of a 16-bit memory, the memory must con-

sist of 8-bit banks with individual chip selects. Refer to 5.7 System Interfacing Exam-

ples for a description of such a configuration.

5.5.3 Byte Operand to 16-Bit Port, Odd (ADDR0 = 1)

To initiate a transfer, the MCU places the desired address on the address bus and drives the size pins to indicate a single-byte operand. The MCU also drives the function code and R/W pins to appropriate values.

Operand

Data Bus

Cycle 1

7 0

OP0

15

OP0

8 7

(OP0)

0 SIZ1

0

SIZ0

1

ADDR0

1

DSACK1 DSACK0

0 1

Figure 5-10 Byte Operand to 16-Bit Port, Odd (ADDR0 = 1)

SIM

REFERENCE MANUAL

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

5-17

Freescale Semiconductor, Inc.

For a read operation, the 16-bit peripheral responds to the address and size signals by placing OP0 on DATA[7:0] and asserting DSACK1. The MCU then reads the data from DATA[7:0] and ignores DATA[15:8].

For a write operation, the MCU drives OP0 on both bytes of the data bus. The peripheral determines operand size and transfers OP0 from the lower byte of the data bus to the specified address, then asserts DSACK1 to terminate the bus cycle.

In order to read or write to individual bytes of a 16-bit memory, the memory must be

divided into 8-bit banks with individual chip selects. Refer to 5.7 System Interfacing

Examples for a description of such a configuration.

5.5.4 Word Operand to 8-Bit Port, Aligned

To initiate a transfer, the MCU places the desired address on the address bus and drives the size pins to indicate a word operand. The MCU also drives the function code and R/W pins to appropriate values.

Operand

Data Bus

Cycle 1

Cycle 2

15

OP0

15

OP0

OP1

8 7

8 7

OP1

(OP1)

(OP1)

0

0 SIZ1

1

0

SIZ0

0

1

ADDR0

0

1

DSACK1 DSACK0

1 0

1 0

Figure 5-11 Word Operand to 8-Bit Port, Aligned

For a read operation, the 8-bit peripheral responds to the address and size signals by placing OP0 on DATA[15:8] and asserting DSACK0. The MCU reads OP0 from DA-

TA[15:8] and ignores DATA[7:0], then decrements the transfer size counter, increments the address, and waits for the peripheral to place OP1 on the upper byte of the data bus for the second cycle of the transfer (a byte read of an 8-bit port).

For a write operation, the MCU drives OP0 on DATA[15:8] and OP1 on DATA [7:0].

The 8-bit peripheral transfers OP0 from DATA[15:8] to the specified address, then asserts DSACK0 to indicate that the first byte has been transferred. The MCU then decrements the transfer size counter, increments the address, and transfers OP1 to bits

[15:8] of the data bus for the second cycle of the transfer (a byte write to an 8-bit port).

For both reads and writes, refer to 5.5.1 Byte Operand to 8-Bit Port for details on the

second cycle of the data transfer.

5.5.5 Word Operand to 8-Bit Port, Misaligned

To initiate a transfer, the MCU places the desired address on the address bus and drives the size pins to indicate a word operand. The MCU also drives the function code and R/W pins to appropriate values.

MOTOROLA

5-18

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

NOTE

The CPU32 does not support misaligned operand transfers.

Operand

Data Bus

Cycle 1

Cycle 2

15 8 7 0

OP0

15

OP1

OP0

OP1

8 7

(OP0)

(OP1)

0 SIZ1

1

0

SIZ0

0

1

ADDR0

1

0

DSACK1 DSACK0

1

1

0

0

Figure 5-12 Word Operand to 8-Bit Port, Misaligned

For a read operation, the 8-bit peripheral responds by placing OP0 on DATA[15:8] and asserting DSACK0. The MCU reads the upper operand byte from DATA[15:8] and ignores DATA[7:0]. The MCU then decrements the transfer size counter, increments the address, and waits for the peripheral to place OP1 on the upper byte of the data bus for the second cycle of the transfer (a byte read of an 8-bit port).

For a write operation, the MCU drives OP0 on DATA[15:8] and OP1 on DATA[7:0].

The 8-bit peripheral transfers OP0 to the specified address, then asserts DSACK0 to indicate that the first byte of word data has been received. The MCU then decrements the transfer size counter, increments the address, and transfers OP1 to the upper byte of the data bus for the second cycle of the transfer (a byte write to an 8-bit port).

For both reads and writes, refer to 5.5.1 Byte Operand to 8-Bit Port for details on the

second cycle of the data transfer.

5.5.6 Word Operand to 16-Bit Port, Aligned

To initiate a transfer, the MCU places the desired address on the address bus and drives the size pins to indicate a word operand. The MCU also drives the function code and R/W pins to appropriate values.

Operand

Data Bus

Cycle 1

15

OP0

15

OP0

8 7

8 7

OP1

OP1

0

0 SIZ1

1

SIZ0

0

ADDR0

0

DSACK1 DSACK0

0 1

Figure 5-13 Word Operand to 16-Bit Port, Aligned

For a read operation, the peripheral responds by placing OP0 on DATA[15:8] and OP1 on DATA[7:0], then asserts DSACK1 to indicate a 16-bit port. When DSACK1 is asserted, the MCU reads DATA[15:0] and terminates the cycle.

SIM

REFERENCE MANUAL

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

5-19

Freescale Semiconductor, Inc.

For a write operation, the MCU drives the word operand on DATA[15:0]. The peripheral device then reads the entire operand from DATA[15:0] and asserts DSACK1 to terminate the bus cycle.

5.5.7 Word Operand to 16-Bit Port, Misaligned

To initiate a transfer, the MCU places the desired address on the address bus and drives the size pins to indicate a word operand. The MCU also drives the function code and R/W pins to appropriate values.

NOTE

The CPU32 does not support transfers of misaligned operands.

Operand

Data Bus

Cycle 1

Cycle 2

15 8 7 0

OP0

OP1

15

(OP0)

OP1

8 7

OP0

(OP1)

0 SIZ1

1

0

SIZ0

0

1

ADDR0

1

0

DSACK1 DSACK0

0

0

1

1

Figure 5-14 Word Operand to 16-Bit Port, Misaligned

For a read operation, the peripheral responds by placing OP0 on DATA[7:0] and asserting DSACK1 to indicate a 16-bit port. When DSACK1 is asserted, the MCU reads

OP0 from DATA[7:0], decrements the transfer size counter, increments the address, and waits for the peripheral to place OP1 on the upper byte of the data bus for the second cycle of the transfer (a byte read of a 16-bit port).

For a write operation, the MCU drives OP0 on both bytes of the data bus. The peripheral device reads OP0 from DATA[7:0] and asserts DSACK1. The MCU decrements the transfer size counter, increments the address, and places OP1 on both bytes of the data bus for the second cycle of the transfer (a byte write to a 16-bit port).

For both reads and writes, refer to 5.5.2 Byte Operand to 16-Bit Port, Even (ADDR0

= 0) for details on the second cycle of the data transfer.

5.5.8 Long-Word Operand to 8-Bit Port, Aligned

The MCU drives the address bus with the desired address and the size pins to indicate a long word operand. The MCU also drives the function code and R/W pins to appropriate values.

MOTOROLA

5-20

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

Operand

Data Bus

Cycle 1

Cycle 2

Cycle 3

Cycle 4

15

15

OP0

OP1

OP0

OP1

OP2

OP3

8 7

8 7

OP1

OP3

(OP1)

(OP1)

(OP2)

(OP3)

0

0 SIZ1

0

1

1

0

SIZ0

0

1

0

1

ADDR0

0

1

0

1

DSACK1 DSACK0

1

1

0

0

1

1

0

0

Figure 5-15 Long-Word Operand to 8-Bit Port, Aligned

For a read operation, the peripheral places OP0 on DATA[15:8] and asserts DSACK0 to indicate an 8-bit port. The MCU reads OP0 from DATA[15:8] and ignores DA-

TA[7:0]. The MCU then decrements the transfer size counter, increments the address, and waits for the peripheral to place OP1 on the upper byte of the data bus for the second cycle of the transfer (a three-byte read of an 8-bit port). The process is repeated for OP2 in the third cycle (aligned word to 8-bit port transfer) and OP3 in the fourth cycle (byte to 8-bit port transfer).

For a write operation, the MCU drives OP0 on DATA[15:8] and OP1 on DATA[7:0].

The peripheral device then reads only OP0 from DATA[15:8] and asserts DSACK0 to indicate an 8-bit port. The MCU then decrements the transfer size counter, increments the address, and writes OP1 to DATA[15:8] during the second cycle (a three-byte to

8-bit port transfer). The process is repeated for OP2 in the third cycle (aligned word to

8-bit port transfer) and OP3 in the fourth cycle (byte to 8-bit port transfer).

Figure 5-16 and Figure 5-17 are timing diagrams for long-word read and write oper-

ations, respectively, to an eight-bit port.

SIM

REFERENCE MANUAL

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

5-21

Freescale Semiconductor, Inc.

CLKOUT

ADDR[23:0]

FC[2:0]

R/W

AS

DS

SIZ0

SIZ1

DSACK0

DSACK1

DATA[15:8]

DATA[7:0]

S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S2 S4

4 BYTES

OP0

3 BYTES

OP1

2 BYTES

OP2

1 BYTE

OP3

BYTE

READ

BYTE

READ

BYTE

READ

LONG-WORD OPERAND READ FROM 8-BIT BUS

BYTE

READ

LONG WORD RD TIM

Figure 5-16 Timing of a Long-Word Read of an 8-Bit Port

MOTOROLA

5-22

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S2 S4

DS

SIZ0

SIZ1

DSACK0

DSACK1

DATA[15:8]

DATA[7:0]

CLKOUT

ADDR[23:0]

FC[2:0]

R/W

AS

4 BYTES 3 BYTES 2 BYTES 1 BYTE

OP0

WRITE

(OP1)

OP1 OP2

(OP1) (OP3)

WRITE WRITE

LONG-WORD OPERAND WRITE TO 8-BIT BUS

OP3

WRITE

(OP3)

LONG WORD WR TIM

Figure 5-17 Timing of a Long-Word Write to an 8-Bit Port

5.5.9 Long-Word Operand to 8-Bit Port, Misaligned

The CPU16 treats misaligned long words as two misaligned words. The MCU drives the address bus with the desired address and the size pins to indicate a word operand.

The MCU also drives the function code and R/W pins to appropriate values.

NOTE

The CPU32 does not support transfers of misaligned operands.

SIM

REFERENCE MANUAL

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

5-23

Freescale Semiconductor, Inc.

Operand

Data Bus

Cycle 1

Cycle 2

Cycle 3

Cycle 4

15 8 7

OP1

OP3

15

OP0

OP1

OP2

OP3

8 7

OP0

OP2

(OP0)

(OP1)

(OP2)

(OP3)

0

0 SIZ1

1

0

1

0

SIZ0

0

1

0

1

ADDR0

1

0

1

0

DSACK1 DSACK0

1 0

1

1

1

0

0

0

Figure 5-18 Long-Word Operand to 8-Bit Port, Misaligned

For a read operation, the 8-bit peripheral responds by placing OP0 on DATA[15:8] and asserting DSACK0. The MCU reads OP0 from DATA[15:8] and ignores DATA[7:0].

The MCU then decrements the transfer size counter, increments the address, and waits for the peripheral to place OP1 on the upper byte of the data bus during the second cycle (a byte read of an 8-bit port). When the second cycle is finished, one misaligned word has been read. The MCU then reads a second misaligned word (OP2 and OP3) from the 8-bit port during the third and fourth cycles.

For a write operation, the MCU drives OP0 on DATA[15:8] and OP1 on DATA [7:0].

The 8-bit peripheral transfers OP0 to the specified address, then asserts DSACK0 to indicate that the first byte of word data has been received. The MCU then decrements the transfer size counter, increments the address, and places OP1 on the upper half of the data bus for the second cycle of the transfer (a byte write to an 8-bit port). After this second cycle, one misaligned word has been written. The MCU then writes a second misaligned word (OP2 and OP3) to the 8-bit port during the third and fourth cycles of the transfer.

5.5.10 Long-Word Operand to 16-Bit Port, Aligned

The MCU drives the address bus with the desired address and drives the size pins to indicate a long-word operand. The MCU also drives the function code and R/W pins to appropriate values.

MOTOROLA

5-24

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

Operand

Data Bus

Cycle 1

Cycle 2

15

15

OP0

OP2

OP0

OP1

8 7

8 7

OP1

OP3

(OP0)

(OP1)

0

0 SIZ1

0

1

SIZ0

0

0

ADDR0

0

0

DSACK1 DSACK0

0

0

1

1

Figure 5-19 Long-Word Operand to 16-Bit Port, Aligned

For a read operation, the 16-bit peripheral responds by placing OP0 on DATA[15:8] and OP1 on DATA[7:0], then asserts DSACK1 to indicate a 16-bit port. The MCU reads OP0 and OP1 from DATA[15:0]. The MCU increments the address bus by two, drives SIZ1 to 1 and SIZ0 to 0, and waits for the peripheral to place OP2 and OP3 on the data bus during the second cycle of the transfer (an aligned word read of a 16-bit port).

For a write operation, the MCU drives OP0 on DATA[15:8] and OP1 on DATA[7:0].

The peripheral device reads OP0 and OP1 from DATA[15:0] and asserts DSACK1 to indicate a 16-bit port. The MCU increments the address bus by two, drives SIZ1 to 1 and SIZ0 to 0, and places OP2 and OP3 on the data bus during the second cycle of the transfer (an aligned word write to a 16-bit port).

Figure 5-20 is a timing diagram for a long-word read or write operation involving a 16-

bit port.

SIM

REFERENCE MANUAL

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

5-25

Freescale Semiconductor, Inc.

CLKOUT

S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S2 S4 S0 S2 S4

ADDR[23:0]

FC[2:0]

R/W

AS

DS

SIZ0

SIZ1

4 BYTES 2 BYTES 2 BYTES 4 BYTES 2 BYTES 2 BYTES

DSACK0

DSACK1

DATA[15:8]

DATA[7:0]

OP0 OP2 OP0

OP1

LONG-WORD READ

FROM 16-BIT BUS

OP3 OP1

WORD READ

FROM

16-BIT BUS

OP0

OP1

LONG-WORD WRITE TO

16-BIT BUS

OP2

OP3

OP0

OP1

WORD

WRITE TO

16-BIT BUS

LONG WORD R/W TIM

Figure 5-20 Timing of Long-Word Read or Write, 16-Bit Port

5.5.11 Long-Word Operand to 16-Bit Port, Misaligned

The CPU16 treats misaligned long-word transfers as two misaligned word transfers.

The MCU drives the address bus with the desired address and drives the size pins to indicate a word operand. The MCU also drives the function code and R/W pins to appropriate values.

NOTE

The CPU32 does not support transfers of misaligned operands.

MOTOROLA

5-26

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

Operand

Data Bus

Cycle 1

Cycle 2

Cycle 3

Cycle 4

15 8 7 0

OP1

OP3

OP0

OP2

15

(OP0)

OP1

(OP2)

OP3

8 7

OP0

(OP1)

OP2

(OP3)

0 SIZ1

1

0

1

0

SIZ0

0

1

0

1

ADDR0

1

0

1

0

DSACK1 DSACK0

0 1

0

0

0

1

1

1

Figure 5-21 Long-Word Operand to 16-Bit Port, Misaligned

For a read operation, the peripheral responds by placing OP0 on DATA[7:0] and asserting DSACK1 to indicate a 16-bit port. When DSACK1 is asserted, the MCU reads

OP0 from DATA[7:0], decrements the transfer size counter, increments the address, and waits for the peripheral to place OP1 on the upper byte of the data bus during the second cycle of the transfer (a byte read of an 8-bit port). When the second cycle is finished, one misaligned word has been read. The MCU then reads a second misaligned word (OP2 and OP3) from the 16-bit port during the third and fourth cycles of the transfer.

For a write operation, the MCU first drives OP0 on DATA[7:0] and duplicates it on DA-

TA[15:8]. The peripheral device reads OP0 from DATA[7:0] and asserts DSACK1. The

MCU decrements the transfer size counter, increments the address, and places OP1 on both bytes of the data bus during the second cycle of the transfer. When the second cycle is finished, one misaligned word has been written. The MCU then writes a second misaligned word (OP2 and OP3) to the 16-bit port during the third and fourth cycles of the transfer.

5.6 Function Codes and Memory Usage

The CPU generates function code output signals FC[2:0] to indicate the type of activity occurring on the data or address bus. These signals can be considered address extensions that can be externally decoded to determine which of eight external address spaces is accessed during a bus cycle.

Address space 7 is designated CPU space. CPU space is used for control information not normally associated with read or write bus cycles. Function codes are valid while

AS is asserted.

Table 5-4 shows address space encoding.

SIM

REFERENCE MANUAL

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

5-27

Freescale Semiconductor, Inc.

1

1

0

1

1

FC2

0

0

0

Table 5-4 Address Space Encoding

0

1

1

0

1

FC1

0

0

1

1

0

1

0

1

FC0

0

1

0

Address Space

Reserved

User Data Space

User Program Space

Reserved

Reserved

Supervisor Data Space

Supervisor Program Space

CPU Space

The supervisor bit in the status register determines whether the CPU is operating in supervisor or user mode. Addressing mode and the instruction being executed determine whether a memory access is to program or data space.

NOTE

Because the CPU16 always operates in supervisor mode (FC2 = 1), it does not use address spaces 0 to 3.

The SIM chip select circuits can be programmed to respond to the type of memory access: CPU space, user space, supervisor space, or user/supervisor space. Refer to

SECTION 7 CHIP SELECTS for more information.

5.7 System Interfacing Examples

This section provides examples of interfacing the MCU to 8- and 16-bit memory devices. For purposes of illustration, the examples that follow decode EBI signals externally. In practice, it is more efficient to use SIM chip selects for most applications. For

configurations using SIM chip selects, refer to 7.11 Interfacing Example with Chip

Selects.

5.7.1 Connecting an 8-Bit Device to the MCU

When connecting an 8-bit memory device or peripheral to the MCU, connect the upper eight bits of the data bus (DATA[15:8]) to the eight data lines of the external device.

Connect high-order address lines to the external chip select and lower-order address

lines to the corresponding address lines of the memory or peripheral. Figure 5-22

shows the basic configuration.

MOTOROLA

5-28

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

MCU

FC[2:0]

SIZ[1:0]

AS

DS

R/W

ADDR[23:(x+1)]

DSACK0

ADDR[x:0]

DATA[15:8]

DATA[7:0]

Freescale Semiconductor, Inc.

8-BIT MEMORY

DEVICE

CHIP

SELECT

LOGIC

DSACK

GENERATOR

CS

ADDR[x:0]

DATA[7:0]

8-BIT MEM CONN

Figure 5-22 Connecting an 8-Bit Memory Device

5.7.2 Connecting a 16-Bit Memory Device to the MCU

When connecting a 16-bit memory system to the MCU, connect DATA[15:0] of the

MCU to the sixteen data lines of the memory. Since the memory is arranged in words

(16 bits) rather than bytes, the address bus is incremented by two bytes with each successive access. To accommodate this, connect ADDR1 of the MCU to ADDR0 of the memory, ADDR2 of the MCU to ADDR1 of the memory, and so on. Do not connect

ADDR0 of the MCU to the address bus of the memory system.

This method precludes writes to individual bytes: all memory accesses are 16 bits wide. To be able to write to individual bytes of the memory, construct the memory sys-

tem as outlined in 5.7.3 Connecting Two 8-bit Memory Devices to the MCU, or use

chip selects as explained in 7.11 Interfacing Example with Chip Selects.

Figure 5-23 illustrates connecting a 16-bit memory device to the MCU.

SIM

REFERENCE MANUAL

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

5-29

MCU

FC[2:0]

SIZ[1:0]

AS

DS

R/W

ADDR[23:(x+1)]

DSACK1

ADDR[x:1]

ADDR0

DATA[15:0]

Freescale Semiconductor, Inc.

CHIP

SELECT

LOGIC

16-BIT MEMORY

DEVICE

CS

DSACK

GENERATOR

ADDR[(x-1):0]

DATA[15:0]

16-BIT MEM CONN

Figure 5-23 Connecting a 16-Bit Memory Device

5.7.3 Connecting Two 8-bit Memory Devices to the MCU

A 16-bit memory can be implemented using two 8-bit banks. This configuration allows both byte and word memory accesses. To implement this method, individual chip selects must be used for each bank of memory. The upper bank of memory is selected when ADDR0 = 1 and the lower bank is selected when ADDR0 = 0. ADDR0 is thus

connected to the chip selects, rather than to the address lines of the memory. Figure

5-24 illustrates this configuration.

MOTOROLA

5-30

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

MCU

FC[2:0]

SIZ[1:0]

AS

DS

R/W

ADDR[23:(x+1)]

ADDR0

DSACK1

DSACK0

ADDR[x:1]

DATA[15:8]

DATA[7:0]

CHIP

SELECT

LOGIC

CS0

CS1

DSACK

GENERATOR

8-BIT MEMORY

DEVICE

CS

ADDR[(x-1):0]

DATA[15:8]

8-BIT MEMORY

DEVICE

CS

ADDR[(x-1):0]

DATA[7:0]

8/8-BIT MEM CONN

Figure 5-24 Connecting Two 8-bit Memory Devices

The SIM chip-select circuitry can be programmed to individually select upper and low-

er bytes of a 16-bit memory system using two 8-bit banks. Refer to 7.11 Interfacing

Example with Chip Selects for an example of such a configuration.

5.8 CPU Space Cycles

Function code signals FC[2:0] designate which of eight external address spaces is accessed during a bus cycle. Address space 7 is designated CPU space. CPU space is used for control information not normally associated with read or write bus cycles. Re-

fer to 5.6 Function Codes and Memory Usage for more information on function

codes.

During a CPU space access, ADDR[19:16] are encoded to reflect the type of access

being made. The three encodings are shown in Figure 5-25. These encodings repre-

sent breakpoint acknowledge (type $0) cycles, low power stop broadcast (Type $3) cycles, and interrupt acknowledge (type $F) cycles. Type 0 and type 3 cycles are

discussed in the following paragraphs. Refer to SECTION 6 INTERRUPTS for a com-

prehensive discussion of interrupt acknowledge bus cycles.

SIM

REFERENCE MANUAL

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

5-31

Freescale Semiconductor, Inc.

CPU SPACE CYCLES

BREAKPOINT

ACKNOWLEDGE

FUNCTION

CODE

2 0

1 1 1

ADDRESS BUS

23 19 16

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

4 2 1 0

BKPT# T 0

LOW POWER

STOP BROADCAST

2 0

1 1 1

23 19 16 0

0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0

INTERRUPT

ACKNOWLEDGE

2 0

1 1 1

23 19 16

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0

LEVEL 1

CPU SPACE

TYPE FIELD

CPU SPACE CYC TIM

Figure 5-25 CPU Space Address Encoding

5.8.1 Breakpoint Acknowledge Cycle

Breakpoints are used to stop program execution at a predefined point during system development. Breakpoints can be used alone or in conjunction with the background debugging mode. The following paragraphs discuss breakpoint processing when background debugging mode is not enabled. Refer to the appropriate CPU reference manual for information on exception processing and background debugging mode.

On CPU32-based MCUs, both hardware and software can initiate breakpoints;

CPU16-based MCUs support hardware-initiated breakpoints only. Refer to the appropriate CPU reference manual for details. The following paragraphs discuss both types of breakpoints.

5.8.1.1 Software Breakpoints

The CPU32 BKPT instruction allows the user to insert breakpoints through software.

The CPU responds to this instruction by initiating a breakpoint-acknowledge read cycle in CPU space. It places the breakpoint acknowledge (%0000) code in AD-

DR[19:16], the breakpoint number (bits [2:0] of the BKPT opcode) in ADDR[4:2], and

%0 (indicating a software breakpoint) in ADDR1.

NOTE

The CPU16 does not support the BKPT instruction.

The external breakpoint circuitry decodes the function code and address lines and responds by either asserting BERR or placing an instruction word on the data bus and asserting DSACK.

If the bus cycle is terminated by DSACK, the CPU32 reads the instruction on the data bus and inserts the instruction into the pipeline. (For eight-bit ports, this instruction fetch may require two read cycles.)

MOTOROLA

5-32

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

If the bus cycle is terminated by BERR, the CPU32 then performs illegal-instruction exception processing: it acquires the number of the illegal-instruction exception vector, computes the vector address from this number, loads the content of the vector address into the PC, and jumps to the exception handler routine at that address.

5.8.1.2 Hardware Breakpoints

A hardware breakpoint is initiated by assertion of the BKPT input. The CPU responds by initiating a breakpoint-acknowledge read cycle in CPU space. It places $00001E on the address bus. (The breakpoint acknowledge code of %0000 is placed in AD-

DR[19:16], the breakpoint number value of %111 is placed in ADDR[4:2], and ADDR1 is set to one, indicating a hardware breakpoint.)

With CPU16-based MCUs, the external breakpoint circuitry decodes the function code and address lines, places an instruction word on the data bus, and asserts either

BERR or DSACK. The CPU16 then performs hardware breakpoint exception processing: it acquires the number of the hardware breakpoint exception vector, computes the vector address from this number, loads the content of the vector address into the PC, and jumps to the exception handler routine at that address.

With CPU32-based MCUs, the external breakpoint circuitry decodes the function code and address lines, places an instruction word on the data bus, and asserts BERR. The

CPU32 then performs hardware breakpoint exception processing: it acquires the number of the hardware breakpoint exception vector, computes the vector address from this number, loads the content of the vector address into the PC, and jumps to the exception handler routine at that address. If the external device asserts DSACK rather than BERR, the CPU32 ignores the breakpoint and continues processing.

Refer to the appropriate CPU reference manual for additional details.

When BKPT assertion is synchronized with an instruction prefetch, processing of the breakpoint exception occurs at the end of that instruction. The prefetched instruction is “tagged” with the breakpoint when it enters the instruction pipeline, and the breakpoint exception occurs after the instruction executes. If the pipeline is flushed before the tagged instruction is executed, no breakpoint occurs. When BKPT assertion is synchronized with an operand fetch, exception processing occurs at the end of the instruction during which BKPT is latched.

Breakpoint operation flow for CPU32-based MCUs is shown in Figure 5-26; Figure 5-

27 shows breakpoint flow for CPU16-based MCUs. Figure 5-28 is the timing diagram

for the breakpoint acknowledge cycle for the CPU32 BKPT instruction. Figure 5-29

shows the timing (for both CPU16- and CPU32-based MCUs) for breakpoint acknowledge cycles initiated by a low signal on the BKPT pin.

SIM

REFERENCE MANUAL

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

5-33

Freescale Semiconductor, Inc.

CPU32

ACKNOWLEDGE BREAKPOINT

IF BREAKPOINT INSTRUCTION EXECUTED:

1) SET R/W TO READ

2) SET FUNCTION CODE TO CPU SPACE

3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16]

4) PLACE BREAKPOINT NUMBER ON ADDR[4:2]

5) SET T-BIT (ADDR1) TO ZERO

6) SET SIZE TO WORD

7) ASSERT AS AND DS

IF BKPT PIN ASSERTED:

1) SET R/W TO READ

2) SET FUNCTION CODE TO CPU SPACE

3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16]

4) PLACE ALL ONES ON ADDR[4:2]

5) SET T-BIT (ADDR1) TO ONE

6) SET SIZE TO WORD

7) ASSERT AS AND DS

BREAKPOINT OPERATION FLOW

PERIPHERAL

IF BKPT INSTRUCTION EXECUTED:

1) PLACE REPLACEMENT OPCODE ON DATA BUS

2) ASSERT DSACK

OR:

1) ASSERT BERR TO INITIATE EXCEPTION PROCESSING

IF BKPT ASSERTED:

1) ASSERT DSACK

OR:

1) ASSERT BERR TO INITIATE EXCEPTION PROCESSING

IF BREAKPOINT INSTRUCTION EXECUTED AND

DSACK IS ASSERTED:

1) LATCH DATA

2) NEGATE AS AND DS

3) GO TO (A)

IF BKPT PIN ASSERTED AND

DSACK IS ASSERTED:

1) NEGATE AS AND DS

2) GO TO (A)

IF BERR ASSERTED:

1) NEGATE AS AND DS

2) GO TO (B)

(A) (B)

IF BKPT INSTRUCTION EXECUTED:

1) PLACE LATCHED DATA IN INSTRUCTION PIPELINE

2) CONTINUE PROCESSING

IF BKPT PIN ASSERTED:

1) CONTINUE PROCESSING

IF BKPT INSTRUCTION EXECUTED:

1) INITIATE ILLEGAL INSTRUCTION PROCESSING

IF BKPT PIN ASSERTED:

1) INITIATE HARDWARE BREAKPOINT PROCESSING

1) NEGATE DSACK OR BERR

1110A

Figure 5-26 CPU32 Breakpoint Operation Flow

MOTOROLA

5-34

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

PERIPHERAL CPU16

ACKNOWLEDGE BREAKPOINT

1) SET R/W TO READ

2) SET FUNCTION CODE TO CPU SPACE

3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16]

4) PLACE ALL ONES ON ADDR[4:2]

5) SET ADDR1 TO ONE

6) SET SIZE TO WORD

7) ASSERT AS AND DS

NEGATE AS AND DS

NEGATE DSACK OR BERR

ASSERT DSACK OR BERR TO INITIATE EXCEPTION

PROCESSING

INITIATE HARDWARE BREAKPOINT PROCESSING

Figure 5-27 CPU16 Breakpoint Operation Flow

CPU16 BKPT FLOW

SIM

REFERENCE MANUAL

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

5-35

Freescale Semiconductor, Inc.

DATA[7:0]

DATA[15:8]

BERR

HALT

BKPT

AS

DS

R/W

DSACK

CLKOUT

ADDR[23:20]

S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 S0

BREAKPOINT ENCODING (0000) ADDR[19:16]

ADDR[4:1] BREAKPOINT NUMBER/T-BIT

ADDR[15:5], ADDR0

FC[2:0]

SIZ0

CPU SPACE

SIZ1

BREAKPOINT

OCCURS

READ

BREAKPOINT

ACKNOWLEDGE

INSTRUCTION WORD FETCHED

FETCHED

INSTRUCTION

EXECUTION

BKPT (OP RET) TIM

Figure 5-28 Breakpoint Acknowledge

Cycle Timing — Opcode Returned (CPU32 Only)

MOTOROLA

5-36

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

DATA[7:0]

DATA[15:8]

BERR

HALT

BKPT

AS

DS

R/W

DSACK

CLKOUT

ADDR[23:20]

S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 S0

BREAKPOINT ENCODING (0000) ADDR[19:16]

ADDR[4:1] BREAKPOINT NUMBER/T-BIT

ADDR[15:5], ADDR0

FC[2:0]

SIZ0

CPU SPACE

SIZ1

BREAKPOINT

OCCURS

READ

BREAKPOINT

ACKNOWLEDGE:

BERR ASSERTED (CPU32)

OR

DSACK OR BERR

ASSERTED (CPU16)

EXCEPTION

STACKING

CPU16/32 BKPT TIM

Figure 5-29 Breakpoint Acknowledge Cycle Timing — Exception Signaled

SIM

REFERENCE MANUAL

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

5-37

Freescale Semiconductor, Inc.

5.8.2 LPSTOP Broadcast Cycle

When the CPU executes the LPSTOP instruction, an LPSTOP broadcast cycle is generated. During an LPSTOP broadcast cycle, the CPU performs a CPU space write to address $3FFFE. This write puts a copy of the interrupt mask value in the clock control

logic. The mask is encoded on the data bus as shown in Figure 5-30. The CPU space

cycle is shown externally (if the bus is available) as an indication to external devices that the MCU is going into low power stop mode. The SIM provides an internally generated DSACK response to this cycle. The timing of this bus cycle is the same as for a fast write cycle.

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

Figure 5-30 LPSTOP Interrupt Mask Level

3

0

2 1

IP MASK

0

The SIM brings the MCU out of low-power mode when either an interrupt of higher priority than the stored mask or a reset occurs. Refer to the appropriate CPU reference manual for more information.

5.9 Bus Error Processing

An external device or a chip-select circuit must assert at least one of the DSACK[1:0] signals or the AVEC signal to terminate a bus cycle normally. Bus error processing occurs when bus cycles are not terminated in the expected manner. The internal bus monitor can be used to generate BERR internally, causing a bus error exception to be taken. Bus cycles can also be terminated by assertion of the external BERR or HALT signal, or by assertion of the two signals simultaneously.

Acceptable bus cycle termination sequences are summarized as follows. The case

numbers refer to Table 3-5, which indicates the results of each type of bus cycle ter-

mination.

Normal Termination

DSACK is asserted; BERR and HALT remain negated (case 1).

Halt Termination

HALT is asserted at the same time, or before DSACK, and BERR remains negated

(case 2).

Bus Error Termination

BERR is asserted in lieu of, at the same time as, or before DSACK (case 3), or after

DSACK (case 4), and HALT remains negated; BERR is negated at the same time or after DSACK.

Retry Termination

HALT and BERR are asserted in lieu of, at the same time as, or before DSACK

(case 5) or after DSACK (case 6); BERR is negated at the same time or after

DSACK; HALT may be negated at the same time or after BERR.

MOTOROLA

5-38

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

NOTE

On CPU16-based MCUs, assertion of BERR results in a bus error exception regardless of the state of the HALT signal. These CPUs do not support the retry termination sequence. Refer to the appropriate

CPU manual or to the user manual for the specific device for details.

Table 5-5 shows various combinations of control signal sequences and the resulting

bus cycle terminations.

Table 5-5 DSACK, BERR, and HALT Assertion Results

Case

Number

1

2

3

4

5

6

Control Signal Asserted on

Rising Edge of

State

N N + 2

DSACK

BERR

HALT

DSACK

BERR

HALT

A

NA

NA

A

NA

A/S

S

NA

X

S

NA

S

Normal termination.

Result

Halt termination: normal cycle terminate and halt.

Continue when HALT is negated.

Bus error termination: terminate and take bus error exception, possibly deferred.

DSACK

BERR

HALT

DSACK

BERR

HALT

DSACK

BERR

HALT

DSACK

BERR

HALT

NA/A

A

NA

A

A

NA

NA/A

A

A/S

A

NA

NA

X

A

A

X

S

S

X

S

X

X

S

NA

Bus error termination: terminate and take bus error exception, possibly deferred.

Retry termination: terminate and retry when HALT is negated. (The result is a bus error termination, rather than retry termination, on CPU16-based MCUs.)

Retry termination: terminate and retry when HALT is negated. (The result is a bus error termination, rather than retry termination, on CPU16-based MCUs.)

NOTES:

N= The number of current even bus state (S2, S4, etc.).

A= Signal is asserted in this bus state.

NA= Signal is not asserted in this state.

X= Don't care.

S= Signal was asserted in previous state and remains asserted in this state.

To properly control termination of a bus cycle for a retry or a bus error condition,

DSACK, BERR, and HALT must be asserted and negated with the rising edge of the

MCU clock. This ensures that when two signals are asserted simultaneously, the required setup time and hold time for both of them are met for the same falling edge of

the MCU clock. (Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for timing

requirements.) External circuitry that provides these signals must be designed with these constraints in mind, or else the internal bus monitor must be used.

DSACK, BERR, and HALT may be negated after AS is negated.

SIM

REFERENCE MANUAL

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

5-39

Freescale Semiconductor, Inc.

WARNING

If DSACK or BERR remain asserted into S2 of the next bus cycle, that cycle may be terminated prematurely.

5.9.1 Bus Error Exceptions

The CPU treats bus errors as a type of exception. Bus error exception processing begins when the CPU detects assertion of the IMB BERR signal (by the internal bus monitor or an external source) while the HALT signal remains negated.

NOTE

On CPU16-based MCUs, assertion of BERR results in a bus error exception regardless of the state of the HALT signal.

BERR takes precedence over DSACK, provided it meets the timing constraints de-

scribed in APPENDIX A ELECTRICAL CHARACTERISTICS.

WARNING

If BERR does not meet these constraints, it may cause unpredictable operation of the MCU. If BERR remains asserted into the next bus cycle, it may cause incorrect operation of that cycle.

BERR assertions do not force immediate exception processing. The signal is synchronized with normal bus cycles and is latched into the CPU at the end of the bus cycle in which it was asserted. Since bus cycles can overlap instruction boundaries, bus error exception processing may not occur at the end of the instruction in which the bus cycle begins. Timing of BERR detection and acknowledgment depends on several factors:

• Which bus cycle of an instruction is terminated by assertion of BERR.

• The number of bus cycles in the instruction during which BERR is asserted.

• The number of bus cycles in the instruction following the instruction in which

BERR is asserted.

• Whether BERR is asserted during a program space access or a data space access.

Because of these factors, it is impossible to predict precisely how long after occurrence of a bus error the bus error exception will be processed.

CAUTION

The external bus interface does not latch data when an external bus cycle is terminated by a bus error. When this occurs during an instruction prefetch, the IMB precharge state (bus pulled high, or $FF) is latched into the CPU instruction register, with indeterminate results.

The instruction prefetch mechanism requests instruction words from the bus controller before it is ready to execute them. If a bus error occurs on an instruction fetch, the CPU does not take the exception until it attempts to use that instruction word. Should an in-

MOTOROLA

5-40

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

tervening instruction cause a branch, or should a task switch occur, the bus error exception does not occur.

When the MCU recognizes a bus error condition, it terminates the current bus cycle in

the normal way. Figure 5-31 shows the timing of a bus error for the case in which

DSACK is not asserted. Figure 5-32 shows the timing for a bus error that is asserted

after DSACK. Exceptions are taken in both cases. Refer to the appropriate CPU reference manual for details of bus error exception processing.

When BERR is asserted after DSACK, BERR must be asserted within the time spec-

ified (refer to APPENDIX A ELECTRICAL CHARACTERISTICS) for purely asynchro-

nous operation, or it must be asserted and remain stable during the sample window around the next falling edge of the clock after DSACK is recognized.

WARNING

If BERR is not stable at the specified time, the MCU may exhibit erratic behavior.

When BERR is asserted after DSACK, data may be present on the bus but not be valid. This sequence may be used by systems that have memory error detection and correction logic and by external cache memories.

CLKOUT

S0 S2 SW SW S4

ADDR[23:0]

FC[2:0]

R/W

AS

DS

DSACK

DATA[15:0]

BERR

READ CYCLE WITH BUS

ERROR

S0 S2 S4

INTERNAL

PROCESSING

STACK

WRITE

BERR W/O DSACK TIM

Figure 5-31 Bus Error Without DSACK

SIM

REFERENCE MANUAL

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

5-41

Freescale Semiconductor, Inc.

S0 S2 S4 S0 S2 S4

CLKOUT

ADDR[23:0]

FC[2:0]

R/W

AS

DS

DSACK

DATA[15:0]

BERR

WRITE

CYCLE

INTERNAL

PROCESSING

STACK

WRITE

Figure 5-32 Late Bus Error with DSACK

BERR W/ DSACK TIM

5.9.2 Double Bus Faults

Exception processing for bus error exceptions follows the standard exception processing sequence. However, a special case of bus error, called double bus fault, can abort exception processing.

BERR assertion is not detected until an instruction is complete. The BERR latch is cleared by the first instruction of the BERR exception handler. Double bus faults may occur under the following conditions, depending on the CPU:

• Bus error exception processing begins and a second BERR is detected before the first instruction of the first exception handler is executed.

• One or more bus errors occur before the first instruction after a reset exception is executed.

• A bus error occurs while the CPU is loading information from a bus error stack frame during a return from exception (RTE) instruction (CPU32-based MCUs only).

Multiple bus errors within a single instruction which can generate multiple bus cycles cause a single bus error exception after the instruction has executed.

MOTOROLA

5-42

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

Immediately after assertion of a second BERR signal, the MCU halts and drives the

HALT line low. Only a reset can restart a halted MCU. However, bus arbitration can

still occur. (Refer to 5.10 Bus Arbitration.) A bus error or address error that occurs

after exception processing has completed (during the execution of the exception handler routine, or later) does not cause a double bus fault. A bus cycle that is retried does not constitute a bus error or cause a double bus fault. The MCU continues to retry the same bus cycle as long as the external hardware requests it.

5.9.3 Retry Operation

When an external device asserts BERR and HALT during a bus cycle, the MCU enters

the retry sequence, shown in Figure 5-33.

NOTE

On CPU16-based MCUs, assertion of BERR and HALT results in a bus error exception, rather than a retry sequence. The retry sequence is not available with these CPUs. Refer to the appropriate

CPU manual or to the user's manual for the specific device for details.

A delayed retry (Figure 5-34), similar to the delayed bus error signal described previ-

ously, can also occur. The MCU terminates the bus cycle, places the AS and DS signals in their inactive state, and does not begin another bus cycle until the BERR and

HALT signals are negated by external logic. After a synchronization delay, the MCU retries the previous cycle using the same address, function codes, data (for a write), and control signals. The BERR signal should be negated before S2 of the read cycle to ensure correct operation of the retried cycle.

If BR, BERR, and HALT are all asserted on the same cycle, the EBI will enter the rerun sequence but first relinquishes the bus to an external master. Once the external master returns the bus and negates BERR and HALT, the EBI runs the previous bus cycle.

This feature allows an external device to correct the problem that caused the bus error

(e.g., swap in a new page of memory) and then try the bus cycle again.

The MCU retries any read or write cycle of an indivisible read-modify-write operation separately; RMC remains asserted during the entire retry sequence. The MCU will not relinquish the bus while RMC is asserted. Any device that requires the MCU to give up the bus and retry a bus cycle during a read-modify-write cycle must assert BERR and

BR only (HALT must remain negated). The bus error handler software should examine the read-modify-write bit in the special status word and take the appropriate action to resolve this type of fault when it occurs. (Refer to the CPU32 reference manual for details on the special status word. The CPU16 does not use this word.)

SIM

REFERENCE MANUAL

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

5-43

Freescale Semiconductor, Inc.

CLKOUT

ADDR[23:0]

FC[2:0]

R/W

AS

DS

DSACK

DATA[15:0]

BERR

HALT

S0 S2 SW SW S4

DATA IGNORED

READ CYCLE WITH

RETRY

HALT

S0 S2 S4

Figure 5-33 Retry Sequence

READ

RERUN

BERR RETRY TIM

MOTOROLA

5-44

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

S0 S2 S4 S0 S2 S4

CLKOUT

ADDR[23:0]

FC[2:0]

R/W

AS

DS

DSACK

DATA[15:0]

BERR

HALT

WRITE

CYCLE

HALT

WRITE

RERUN

BERR LATE RETRY TIM

Figure 5-34 Late Retry Sequence

5.9.4 Halt Operation

When HALT is asserted (and BERR is not asserted, on MCUs that support the retry sequence), the MCU halts external bus activity after negation of DSACK. The MCU may complete the current word transfer in progress. For a long-word to byte transfer, this could be after S2 or S4. For a word to byte transfer, activity ceases after S2 (refer

to Figure 5-35).

Negating and reasserting HALT in accordance with timing requirements provides single-step (bus cycle to bus cycle) operation. The HALT signal affects external bus cycles only, so that a program which does not use the external bus can continue executing. During dynamically-sized 8-bit transfers, external bus activity may not stop at the next cycle boundary.

Occurrence of a bus error while HALT is asserted causes the CPU to either process a bus error exception (on CPU16-based MCUs) or initiate a retry sequence (on CPU32based MCUs). In the latter case, retry cycles must be anticipated while debugging in single-cycle mode. In dynamically sized 8-bit transfers, external bus activity may not stop at the next cycle boundary.

SIM

REFERENCE MANUAL

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

5-45

Freescale Semiconductor, Inc.

When the MCU completes a bus cycle while the HALT signal is asserted, the data bus goes to high-impedance state and the AS and DS signals are driven to their inactive states. Address, function code, size, and read/write signals remain in the same state.

The halt operation has no effect on bus arbitration. (Refer to 5.10 Bus Arbitration.)

However, when external bus arbitration occurs while the MCU is halted, address and control signals go to a high-impedance state. If HALT is still asserted when the MCU regains control of the bus, address, function code, size, and read/write signals revert to the previous driven states. The MCU cannot service interrupt requests while halted.

S0 S2 S4 S0 S2 S4 S0

CLKOUT

ADDR[23:0]

FC[2:0]

R/W

AS

DS

DSACK

DATA[15:0]

HALT

BR

BG

BGACK

READ READ HALT

(ARBITRATION PERMITTED

WHILE THE PROCESSOR IS

HALTED)

HALT TIM

Figure 5-35 HALT Timing

MOTOROLA

5-46

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

5.10 Bus Arbitration

MCU bus design provides for a single bus master at any one time. Either the MCU or an external device can be master. Bus arbitration protocols determine when an external device can become bus master. Bus arbitration requests are recognized during normal processing, during HALT assertion, and when the CPU has halted due to a double bus fault.

The bus controller in the MCU manages bus arbitration signals so that the MCU has the lowest priority. Systems that include several devices that can become bus master require external circuitry to assign priorities to the devices, so that when two or more external devices attempt to become bus master at the same time, the one having the highest priority becomes bus master first.

External devices that need to obtain the bus must assert bus arbitration signals in the following sequence:

• An external device asserts the bus request signal (BR).

• The MCU asserts the bus grant signal (BG) to indicate that the bus is available.

• An external device asserts the bus grant acknowledge (BGACK) signal to indicate that it has assumed bus mastership.

BR may be issued any time during a bus cycle or between cycles. BG is asserted in response to BR. To guarantee operand coherency, BG is only asserted at the end of operand transfer. Additionally, BG is not asserted until the end of an indivisible readmodify-write operation (when RMC is negated), on CPU32-based MCUs. (CPU16based MCUs do not provide an RMC signal.)

If more than one external device can be bus master, required external arbitration must begin when a requesting device receives BG. An external device must assert BGACK when it assumes mastership and must maintain BGACK assertion as long as it is bus master.

Two conditions must be met for an external device to assume bus mastership. The device must receive BG through the arbitration process, and BGACK must be inactive, indicating that no other bus master is active. This technique allows processing of bus requests during data transfer cycles.

BG is negated a few clock cycles after an external device asserts BGACK. However, if bus requests are still pending after BG is negated, the MCU asserts BG again within a few clock cycles. This additional BG assertion allows external arbitration circuitry to select the next bus master before the current master has released the bus.

Figure 5-36 is a flow chart of bus arbitration for a single device.

SIM

REFERENCE MANUAL

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

5-47

Freescale Semiconductor, Inc.

MCU

GRANT BUS ARBITRATION

1) ASSERT BUS GRANT (BG)

TERMINATE ARBITRATION

1) NEGATE BG (AND WAIT FOR

BGACK TO BE NEGATED)

REQUESTING DEVICE

REQUEST THE BUS

1) ASSERT BUS REQUEST (BR)

ACKNOWLEDGE BUS MASTERSHIP

1) EXTERNAL ARBITRATION DETERMINES

NEXT BUS MASTER

2) NEXT BUS MASTER WAITS FOR BGACK

TO BE NEGATED

3) NEXT BUS MASTER ASSERTS BGACK

TO BECOME NEW MASTER

4) BUS MASTER NEGATES BR

OPERATE AS BUS MASTER

1) PERFORM DATA TRANSFERS (READ AND

WRITE CYCLES) ACCORDING TO THE

SAME RULES THE PROCESSOR USES

RE-ARBITRATE OR RESUME PROCESSOR

OPERATION

RELEASE BUS MASTERSHIP

1) NEGATE BGACK

BUS ARB FLOW

Figure 5-36 Bus Arbitration Flow Chart for Single Request

5.10.1 Bus Request

External devices capable of becoming bus masters request the bus by asserting the

BR signal. In a system with a number of devices capable of bus mastership, a wired-

OR connection can connect the bus request line from each device to the MCU. After it has completed the current operand transfer, the MCU asserts BG, then releases the bus when BGACK; is asserted.

If no acknowledge signal is received, the MCU remains bus master. This prevents interference with ordinary processing if the arbitration circuitry responds to noise or if an external device negates a request after mastership has been granted.

5.10.2 Bus Grant

The bus arbitration protocol supports operand coherency. When an operand transfer requires multiple bus cycles, the MCU does not release the bus until the entire transfer is complete. The assertion of bus grant is subject to the following constraints:

• The minimum time for BG assertion after BR assertion depends on internal syn-

chronization (as specified in APPENDIX A ELECTRICAL CHARACTERISTICS).

• During an external transfer, the MCU does not assert BG until after the last cycle of the transfer (determined by SIZ[1:0] and DSACK[1:0] signals).

MOTOROLA

5-48

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

• During an external transfer, the MCU does not assert BG as long as RMC is asserted.

• When SHEN bits are both set and the CPU is making internal accesses, the MCU does not assert BG until the CPU finishes the internal transfers.

When a device is granted the bus and asserts BGACK, it must also negate BR. If BR remains asserted after assertion of BGACK, the MCU assumes that another device is requesting the bus and prepares to assert BG again.

Externally, the BG signal can be routed through a daisy-chained network or a priorityencoded network. The MCU is not affected by the method of arbitration as long as the protocol is obeyed.

5.10.3 Bus Grant Acknowledge

When bus protocols are obeyed, a device becomes the active bus master when it asserts BGACK. An external device cannot request and be granted the bus while another device is the active bus master. A device remains the bus master until it negates

BGACK. BGACK must not be negated until all required bus cycles are completed.

NOTE

On MCUs with a reduced pin-count SIM, the BGACK pin may not be

supported. Refer to SECTION 10 REDUCED PIN-COUNT SIM and

to the user's manual for the particular MCU for additional information.

When a device receives the bus and asserts BGACK, it must also negate BR. If BR remains asserted after BGACK assertion, the MCU assumes that another device is requesting the bus and prepares to issue another BG.

Since external devices have priority, the MCU cannot regain control of the external bus until all pending external bus requests have been satisfied.

5.10.4 Bus Arbitration Pin State

Table 5-6 indicates the states of bus control pins when an external master has control of the bus. For pins with multiple functions, Table 5-6 applies if the pin is configured

for its bus control function, shown in the second column. Output bus control signals not used when an external master has control of the bus are placed in a disabled, highimpedance state, and inactive signals are placed in an inactive state.

SIM

REFERENCE MANUAL

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

5-49

Freescale Semiconductor, Inc.

Table 5-6 Bus Arbitration Pin State

Pin Mnemonic

ADDR23/CS10/ECLK

ADDR[22:19]/CS[9:6]/PC[6:3]

ADDR[18:0]

AS/PE5

AVEC/PE2

BERR

BG/CS1

BGACK/CS2

BR/CS0

DATA[15:0]

DS/PE4

DSACK[1:0]/PE[1:0]

FC[2:0]/CS[5:3]/[PC[2:0]

R/W

RMC/PE3

SIZ[1:0]/PE[7:6]

Bus Control Signal

ADDR23

ADDR[22:19]

ADDR[18:0]

AS

AVEC

BERR

BG

BGACK

BR

DATA[15:0]

DS

DSACK[1:0]

FC[2:0]

R/W

RMC

SIZ[1:0]

Pin Direction

Output

Output

Output

Output

Input

Input

Output

Input

Input

Depends on R/W

Output

Input

Output

Output

Output

Output

Pin State when Bus

Granted Away

High Impedance

High Impedance

High Impedance

High Impedance

Inactive

Inactive

Active

Active

Active

High Impedance

High Impedance

Inactive

High Impedance

High Impedance

High Impedance

High Impedance

5.10.5 Bus Arbitration Control

The bus arbitration control unit in the MCU is implemented with a finite-state machine.

All asynchronous inputs to the MCU are internally synchronized in a maximum of two

CLKOUT cycles. Figure 5-37 is the bus arbitration state diagram. Input signals labeled

R and A are internal versions of the bus request and bus grant acknowledge signals that are internally synchronized to the system clock. The bus grant output is labeled G and the internal high-impedance control signal is labeled T. If T is true, the address, data, and control buses are placed in the high-impedance state after the next rising edge following the negation of AS and RMC.

MOTOROLA

5-50

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

R A B

G T V

STATE 0

R A

R A

A B

G T V

STATE 3

G T V

STATE 2

R A

R A + A

R A

G T V

STATE 5

R A

R

G T V

STATE 6

R

R A

R - BUS REQUEST

A - BUS GRANT ACKNOWLEDGE

B - BUS CYCLE IN PROGRESS

G - BUS GRANT

T - THREE-STATE SIGNAL TO BUS CONTROL

V - BUS AVAILABLE TO BUS CONTROL

NOTE: All figures are shown in positive logic (active high) regardless of their active state.

Figure 5-37 Bus Arbitration State Diagram

BUS ARB STATE

State changes occur on the next rising edge of CLKOUT after the internal signal is valid. The BG signal transitions on the falling edge of the clock after a state is reached during which G changes. The bus control signals (controlled by T) are driven by the

MCU immediately following a state change, when bus mastership is returned to the

MCU. State 0, in which G and T are both negated, is the state of the bus arbiter while the MCU is bus master. Request R and acknowledge A keep the arbiter in state 0 as long as they are both negated.

SIM

REFERENCE MANUAL

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

5-51

Freescale Semiconductor, Inc.

5.10.6 Factory Test (Slave) Mode Arbitration

This mode is used for factory production testing of internal modules. It is not supported for customer use, due to abnormal operating conditions that result. Factory test mode is enabled by holding DATA11 low during reset. In this mode, when BG is asserted, the MCU is slaved to an external tester that has full access to all internal registers.

5.11 Show Cycles

The MCU normally performs internal data transfers without affecting the external bus, but it is possible to “show” these transfers during debugging. AS is not asserted externally during show cycles.

Show cycles are controlled by the SHEN field in the SIMCR. (Refer to 3.1.6 SIM Con-

figuration Register.) This field is cleared by reset. When show cycles are disabled,

the address bus, function codes, size, and read/write signals reflect internal bus activity, but AS and DS are not asserted externally and external data bus pins are in highimpedance state during internal accesses.

When show cycles are enabled, DS is asserted externally during internal cycles, and internal data is driven out on the external data bus during writes. Since internal cycles normally continue to run when the external bus is granted away, one SHEN encoding halts internal bus activity while there is an external master.

SIZ[1:0] signals reflect bus allocation during show cycles. Only the appropriate portion of the data bus is valid during the cycle. During a byte write to an internal address, the portion of the bus that represents the byte that is not written reflects internal bus conditions, and is indeterminate. During a byte write to an external address, the data multiplexer in the SIM causes the value of the byte that is written to be driven out on both bytes of the data bus.

State 0 (S0) — Address and function codes become valid, R/W is driven to indicate a show read or write cycle, and the size pins indicate the number of bytes to transfer.

During a read, the addressed peripheral drives the data bus, and the user must take care to avoid bus conflicts.

State 41 (S41) — DS is asserted to indicate that address information is valid.

State 42 (S42) — No change. The bus controller remains in S42 until the internal read cycle is complete.

State 43 (S43) — DS is negated to indicate that show data is valid on the next falling edge of CLKOUT. External data bus drivers are enabled so that data becomes valid on the external bus as soon as it is available on the internal bus.

State 0 (S0) — ADDR[23:0], FC[2:0], R/W, and SIZ[1:0] pins change state to begin the next cycle. Data from the preceding cycle is valid through S0.

MOTOROLA

5-52

EXTERNAL BUS INTERFACE

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

SECTION 6 INTERRUPTS

Interrupt recognition and servicing involve complex interaction between the system integration module, the central processing unit, and a device or module requesting interrupt service. This discussion provides an overview of the entire interrupt process.

Chip-select logic can also be used to respond to interrupt requests from external de-

vices. Refer to SECTION 7 CHIP SELECTS for more information.

The CPU handles interrupts as a type of asynchronous exception. An exception is an event that preempts normal processing. Each exception has an assigned vector that points to an associated handler routine. During exception processing, the CPU fetches the vector assigned to the exception and executes the exception routine to which the vector points. Refer to the appropriate CPU manual for additional information on exception processing.

6.1 Sources of Interrupt

External devices or microcontroller modules can assert interrupt request signals. The

SIM includes two sources of interrupt requests: the periodic interrupt timer and the external bus interface. The external bus interface routes external interrupt requests (i.e., requests received from the interrupt request pins IRQ[7:1]) to the CPU. During inter-

rupt arbitration (see 6.3 Interrupt Arbitration), the CPU treats external interrupt re-

quests as though they come from the SIM.

NOTE

MCUs with a reduced pin-count SIM may not have all the interruptrequest pins mentioned above. Refer to the user's manual for the specific MCU for details.

When the CPU receives simultaneous interrupt requests of the same level (see 6.2 In-

terrupt Level and Recognition) from an interrupt request pin and the PIT, the PIT is

given priority. The interrupt from the interrupt request pin remains pending until the next allowable interrupt time.

6.2 Interrupt Level and Recognition

Each of the interrupt request signals IRQ[7:1] corresponds to an interrupt priority level.

IRQ1 has the lowest priority and IRQ7 the highest. For periodic timer interrupts, the

PIRQ field in the periodic interrupt control register (PICR) determines the priority level.

A priority level of 0 in the PICR means that PIT interrupts are inactive.

Interrupt recognition is based on the interrupt priority level and the interrupt priority mask value. The interrupt priority mask consists of three bits in the CPU status register

(on CPU32-based MCUs) or condition code register (on CPU16-based MCUs). Binary values %000 to %111 provide eight priority masks. Masks prevent an interrupt request of a priority less than or equal to the mask value from being recognized and processed.

SIM

REFERENCE MANUAL

INTERRUPTS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

6-1

Freescale Semiconductor, Inc.

IRQ7, however, is always recognized, even if the mask value is %111. If simultaneous interrupt requests of different levels are made, the CPU recognizes the higher-level request.

IRQ[7:1] are active-low level-sensitive inputs. The level on the pin must remain asserted until an interrupt acknowledge cycle corresponding to that level is detected.

IRQ7 is transition-sensitive as well as level-sensitive: a level-7 interrupt is not detected unless a falling edge transition is detected on the IRQ7 line. This prevents redundant servicing and stack overflow. A nonmaskable interrupt is generated each time IRQ7 is asserted as well as each time the priority mask changes from %111 to a lower number while IRQ7 is asserted.

Interrupt requests are sampled on consecutive falling edges of the system clock. Interrupt request input circuitry has hysteresis: to be valid, a request signal must be asserted for at least two consecutive clock periods. Valid requests do not cause immediate exception processing, but are left pending. Pending requests are processed at instruction boundaries or when exception processing of higher-priority exceptions is complete.

The CPU does not latch the priority of a pending interrupt request. If an interrupt source of higher priority makes a service request while a lower priority request is pending, the higher priority request is serviced. If an interrupt request with a priority equal to or lower than the current IP mask value is made, the CPU does not recognize the occurrence of the request.

6.3 Interrupt Arbitration

When the CPU detects one or more interrupt requests of a priority higher than the interrupt priority mask value, it places the interrupt request level on the address bus and initiates a CPU space read cycle. The request level serves two purposes: it is decoded by modules that have requested interrupt service to determine whether the current interrupt acknowledge cycle pertains to them, and it is latched into the interrupt priority mask field in the CPU status register (on CPU32-based MCUs) or condition code register (on CPU16-based MCUs) in order to mask lower-priority interrupts during exception processing.

Modules that have requested interrupt service decode the interrupt priority mask value placed on the address bus at the beginning of the interrupt acknowledge cycle. If a module's request is at the specified priority mask level, it enters interrupt arbitration.

Arbitration between simultaneous requests of the same level is performed by means of serial contention between module interrupt arbitration (IARBI) field bit values. Each module that can make an interrupt service request, including the SIM, has an IARB field in its configuration register. An IARB field can be assigned a value from %0001

(lowest priority) to %1111 (highest priority). A value of %0000 in an IARB field causes the CPU to process a spurious interrupt exception when an interrupt from that module is recognized.

MOTOROLA

6-2

INTERRUPTS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

Because the EBI manages external interrupt requests, the SIM IARB value is used for arbitration between internal and external interrupt requests. The reset value of IARB for the SIM is %1111, and the reset IARB value for all other modules is %0000. Initialization software must assign different IARB values in order to implement an arbitration scheme.

WARNING

Do not assign the same level and arbitration priority to more than one module. When two or more IARB fields have the same nonzero value, the CPU interprets multiple vector numbers simultaneously, with unpredictable consequences.

Arbitration must always take place, even when a single source is requesting service.

This point is important for two reasons: the EBI does not transfer the CPU interrupt acknowledge cycle to the external bus unless the SIM wins contention, and failure to contend causes the interrupt acknowledge bus cycle to be terminated early, by a bus error.

When arbitration is complete, the module that wins contention must place an interrupt vector number on the data bus and terminate the bus cycle by asserting DSACK. Alternately, an external device that wins arbitration can assert the autovector (AVEC) signal to request that the CPU supply a vector number. The process is described in

6.4 Interrupt Acknowledge Bus Cycles.

6.4 Interrupt Acknowledge Bus Cycles

The MCU acknowledges an interrupt request by performing a read cycle in CPU space to obtain the interrupt vector number. The interrupt acknowledge cycle differs from the

read cycle described in 5.4.1 Read Cycles in the following ways:

• FC[2:0] are set to %111, the CPU space encoding.

• ADDR[19:16] (the CPU space type field) are set to %1111, the interrupt acknowledge encoding.

• ADDR[3:1] are set to the interrupt request level.

• All remaining address bits are set.

• SIZ[1:0] and R/W are driven to indicate a single-byte read cycle.

Figure 6-1 shows the encoding of the address and function code lines for an interrupt

acknowledge read cycle.

INTERRUPT

ACKNOWLEDGE

FUNCTION

CODE

2 0

1 1 1

ADDRESS BUS

23 19 16

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LEVEL

0

1

CPU SPACE

TYPE FIELD

CPU SPACE IACK TIM

Figure 6-1 Interrupt Acknowledge Read Cycles

SIM

REFERENCE MANUAL

INTERRUPTS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

6-3

Freescale Semiconductor, Inc.

Interrupting devices must decode ADDR[3:1] to determine which device or devices enter interrupt arbitration. The responding devices must also decode SIZ[1:0] for dynamic bus allocation.

An interrupt acknowledge cycle is completed in one of three ways:

• When arbitration is complete, the module or device that wins contention places an interrupt vector number on the data bus and terminates the bus cycle with the appropriate DSACK signal.

• When arbitration is complete, an external device that wins contention asserts the autovector (AVEC) signal.

• If no device or module enters interrupt arbitration, or if the device winning arbitration does not respond in time, the EBI bus monitor, if enabled, asserts the bus error signal (BERR), and a spurious interrupt exception is taken.

Chip-select logic can be programmed to decode the interrupt acknowledge bus cycle, generate an interrupt acknowledge signal to the external device, and generate a

DSACK response. Alternately, the chip-select circuit can be programmed to generate

an AVEC response. Refer to SECTION 7 CHIP SELECTS for more information.

Figure 6-2 is a flow chart of the interrupt acknowledge cycle.

INTERRUPTING DEVICE

REQUEST INTERRUPT

PROVIDE VECTOR NUMBER

1) PLACE VECTOR NUMBER ON LEAST

SIGNIFICANT BYTE OF DATA BUS

2) ASSERT DSACK (OR AVEC IF NO VECTOR NUMBER)

RELEASE

1) NEGATE DSACK

CPU

GRANT INTERRUPT

1) SYNCHRONIZE IRQ[7:1]

2) COMPARE IRQ[7:1] TO MASK LEVEL AND

WAIT FOR INSTRUCTION TO COMPLETE

3) PLACE INTERRUPT LEVEL ON ADDR[3:1];

TYPE FIELD (ADDR[19:16]) = $F

4) SET R/W TO READ

5) SET FC[2:0] TO 111

6) DRIVE SIZ[1:0] TO INDICATE SIZE OF TRANSFER

7) ASSERT AS AND DS

ACQUIRE VECTOR NUMBER

1) LATCH VECTOR NUMBER

2) NEGATE AS AND DS

START NEXT CYCLE

IACK FLOW

Figure 6-2 Interrupt Acknowledge Cycle Flowchart

MOTOROLA

6-4

INTERRUPTS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

6.4.1 Bus Cycle Terminated by DSACK Signals

If an external device with a vector number register wins arbitration, the device places the vector number on the data bus and asserts the appropriate DSACK signal to terminate the interrupt acknowledge cycle. The device must place its vector number on the least significant byte of its data port. A device with an 8-bit port must drive the vector number on DATA[15:8]; a device with a 16-bit port must drive the vector number on DATA[7:0].

Figure 6-3 shows the timing for an interrupt acknowledge cycle terminated with

DSACK.

S0 S2 S4 S0 S21 S22 S23 S24 S1 S2 S4 S0 S2

R/W

AS

DS

DSACK

DATA[7:0]

DATA[15:8]

IRQ[7:1]

CLKOUT

ADDR[23:4]

ADDR[3:1]

ADDR0

FC[2:0]

SIZ0

SIZ1

INTERRUPT LEVEL

1 BYTE

VECTOR FROM 16-BIT PORT

VECTOR FROM 8-BIT PORT

READ

CYCLE

INTERNAL

ARBITRATION

INTERRUPT ACKNOWLEDGE CYCLE

Figure 6-3 Interrupt Acknowledge Cycle Timing

SIM

REFERENCE MANUAL

INTERRUPTS

For More Information On This Product,

Go to: www.freescale.com

WRITE

STACK

IACK TIM

MOTOROLA

6-5

Freescale Semiconductor, Inc.

Figure 6-4 indicates possible pin connections and external logic connecting the SIM

and an interrupting external device that provides a vector number. The design shown

in Figure 6-4 can be simplified by using SIM chip selects to decode the function code

and address lines and supply the interrupt acknowledge signal. Refer to 7.8 Using

Chip Selects in Interrupt Acknowledge Cycles.

MCU

FC2

FC1

FC0

ADDR23

1

1

1

1

ADDR20

ADDR19

ADDR18

ADDR17

ADDR16

ADDR15

1

1

1

1

1

1

CPU SPACE

INTERRUPT x:x:x

ACKNOWLEDGED

3

ADDR4

ADDR3

ADDR2

ADDR1

ADDR0

1 x x

1 x x x x

IACK

E

2

1

0

4

3

7

6

5

IACK7

IACK6

IACK5

IACK4

IACK3

IACK2

IACK1

NO ACK

ACKNOWLEDGE

VECTOR NUMBER

INTERRUPTING

DEVICE AND

GLUE LOGIC

BERR

DSACK

BUS TIME OUT

CIRCUITRY

IACK CONN

Figure 6-4 External Connections for Interrupt Processing

6.4.2 Bus Cycle Terminated by AVEC Signal

An external interrupting device requests an automatically generated vector (autovector) by asserting the AVEC signal to terminate an interrupt acknowledge cycle. DSACK signals must not be asserted during an interrupt acknowledge cycle terminated by

AVEC. If the AVEC pin is permanently wired low (asserted), the CPU generates an autovector whenever an interrupt (of any priority, from any external source) is acknowledged.

When AVEC is asserted, the CPU ignores the state of the data bus and generates a vector number. Refer to the appropriate CPU manual for information on determining the vector number and vector address. Seven autovectors are available, one for each of the seven interrupt request signals.

Figure 6-5 shows the timing for an autovector operation.

MOTOROLA

6-6

INTERRUPTS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

CLKOUT

ADDR[23:4]

ADDR[3:1]

ADDR0

FC[2:0]

SIZ0

SIZ1

R/W

AS

DS

DSACK

DATA[15:0]

AVEC

IRQ[7:1]

Freescale Semiconductor, Inc.

Chip-select logic can be programmed to decode this bus cycle and generate an internal AVEC response when an external interrupt request is made. The interrupting device does not have to respond in this case. Chip-select logic is typically used to generate an internal autovector signal when the corresponding chip-select pin is used

for an alternate function or for general-purpose output. Refer to 7.8 Using Chip Se-

lects in Interrupt Acknowledge Cycles for more information.

S0 S2 S4 S0 S21 S22 S23 S24 S1 S2 S4 S0 S2

INTERRUPT LEVEL

1 BYTE

READ

CYCLE

INTERNAL

ARBITRATION

INTERRUPT ACKNOWLEDGE CYCLE

Figure 6-5 Autovector Timing

WRITE

STACK

AVEC IACK TIM

SIM

REFERENCE MANUAL

INTERRUPTS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

6-7

Freescale Semiconductor, Inc.

6.4.3 Spurious Interrupt Cycle

When an interrupt request is made, but no IARB field value is asserted in response to the interrupt acknowledge cycle, the spurious interrupt monitor asserts the BERR signal internally to prevent vector acquisition. When a responding device does not terminate an interrupt acknowledge cycle with AVEC or DSACK, the bus monitor asserts

BERR internally. The CPU automatically generates the spurious interrupt vector number ($F) in both cases.

6.5 Interrupt Processing Summary

A summary of the entire interrupt processing sequence follows. When the sequence begins, a valid interrupt service request has been detected and is pending.

A. The CPU finishes higher priority exception processing or reaches an instruction boundary.

B. The processor state is stacked. On CPU16-based MCUs, the PK extension field in the condition code register is cleared. On CPU32-based MCUs, the S bit in the status register is set, establishing supervisor access level, and bits T1 and T0 are cleared, disabling tracing.

C. The interrupt acknowledge cycle begins:

1. FC[2:0] are driven to %111 (CPU space) encoding.

2. The address bus is driven as follows: ADDR[23:20] = %1111; ADDR[19:16]

= %1111, which indicates that the cycle is an interrupt acknowledge CPU space cycle; ADDR[15:4] = %111111111111; ADDR[3:1] = the priority of the interrupt request being acknowledged; and ADDR0 = %1.

3. The request level is latched from the address bus into the interrupt priority mask field in the status or condition code register.

D. Modules or external peripherals that have requested interrupt service decode the priority value in ADDR[3:1]. Each module or device with a request level equal to the value in ADDR[3:1] enters interrupt arbitration. When there is no arbitration, the spurious interrupt monitor asserts BERR, and a spurious interrupt exception is processed.

E. After arbitration, the interrupt acknowledge cycle is completed in one of three ways:

1. The interrupt source that wins arbitration supplies a vector number and

DSACK signals appropriate to the access. The CPU acquires the vector number.

2. The AVEC signal is asserted (the external interrupt source can assert the signal, or the pin can be tied low), and the CPU generates an autovector number corresponding to the interrupt priority level.

3. The bus monitor or external device asserts BERR, and the CPU generates the spurious interrupt vector number.

F. The vector number is converted to a vector address.

G. The content of the vector address is loaded into the PC, and the processor transfers control to the exception handler routine.

MOTOROLA

6-8

INTERRUPTS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

SECTION 7 CHIP SELECTS

Typical microcontrollers require additional hardware to provide external chip-select and address decode signals. The SIM includes 12 programmable chip-select circuits that can provide 2-clock-cycle (fast termination) to 16-clock-cycle (13-wait-state) access to external memory and peripherals. Address block sizes of 2 Kbytes to 1 Mbyte

(on CPU32-based MCUs) or 2 Kbytes to 512 Kbytes (on CPU16-based MCUs) can be selected.

NOTE

MCUs with reduced pin-count SIMs may not have all 12 chip-select pins available. Consult the user's manual for the particular MCU for details.

Chip-select assertion can be synchronized with bus control signals to provide output enable, read/write strobe, or interrupt acknowledge signals. Chip select logic can generate DSACK and AVEC signals internally. Each signal can also be synchronized with the ECLK signal available as a programming option on ADDR23.

Chip-select registers include two global pin assignment registers, a base address register and option register for each chip-select circuit, and a data register. The pin assignment registers assign pins individually for chip-select operation, discrete output, or alternate functions. The pin data register controls the state of pins programmed as discrete outputs. The base address registers define the base address and block size to which the chip select responds. The option registers determine timing of and conditions for assertion of chip-select signals.

7.11 Interfacing Example with Chip Selects provides a diagram of a basic system

that uses chip selects. Figure 7-1 is a functional diagram of a single chip-select circuit.

SIM

REFERENCE MANUAL

CHIP SELECTS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

7-1

Freescale Semiconductor, Inc.

INTERNAL

SIGNALS

ADDRESS

BUS CONTROL

BASE ADDRESS REGISTER

ADDRESS COMPARATOR

OPTION COMPARE

OPTION REGISTER

TIMING

AND

CONTROL

1 OF 12

PIN

AVEC

DSACK

AVEC

GENERATOR

DSACK

GENERATOR

PIN

ASSIGNMENT

REGISTER

PIN

DATA

REGISTER

CHIP SEL BLOCK

Figure 7-1 Chip-Select Circuit Block Diagram

7.1 Chip-Select Options

Chip-select option registers determine timing of and conditions for assertion of chipselect signals. Constraints set by fields in the option register and in the base address register must all be satisfied in order to assert a chip-select signal, and to provide

DSACK or autovector support.

The following fields in the option registers specify the conditions for assertion of the chip-select signal. These conditions must all be satisfied before chip-select logic will respond:

• The BYTE field determines whether to assert the chip select for an upper-byte access, lower-byte access, both, or neither (disabled).

• The R/W field specifies whether to assert the chip select during a read cycle, write cycle, or both.

• The SPACE field specifies whether to assert the chip select during a user-space access, supervisor-space access, user or supervisor access, or CPU-space access.

The following fields specify chip-select assertion timing:

• DSACK specifies the number of wait states to insert before the chip-select circuit asserts DSACK, or specifies that the external device must provide the DSACK signal.

• STRB specifies whether chip select assertion is synchronous with AS or DS. (This bit applies only when MODE = 0.)

• MODE determines whether the chip-select cycle is synchronous with ECLK or emulates an asynchronous external bus cycle.

MOTOROLA

7-2

CHIP SELECTS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

The following fields determine chip-select operation during interrupt acknowledge cycles:

• AVEC determines whether to generate AVEC internally when match conditions specified in SPACE and IPL fields and base address register are satisfied.

• IPL specifies the interrupt priority level to which the chip select responds.

• SPACE must be set to %00 (CPU space) for the chip-select circuit to respond to interrupt acknowledge cycles.

Table 7-1 is a summary of option register functions.

Table 7-1 Option Register Function Summary

MODE BYTE R/W STRB DSACK

0 = Async.* 00 = Disable 00 = Rsvd 0 = AS 0000 = 0 wait states

1 = Sync.

01 = Lower 01 = Read 1 = DS 0001 = 1 wait state

10 = Upper 10 = Write 0010 = 2 wait states

*11 = Both 11 = Both 0011 = 3 wait states

0100 = 4 wait states

0101 = 5 wait states

0110 = 6 wait states

0111 = 7 wait states

1000 = 8 wait states

1001 = 9 wait states

1010 = 10 wait states

1011 = 11 wait states

1100 = 12 wait states

1101 = 13 wait states

1110 = Fast terminate

1111 = External

SPACE

00 = CPU

IPL

000 = All*

AVEC

0 = Off*

01 = User 001 = Level 1 1 = On

10 = Supv 010 = Level 2

11 = S/U* 011 = Level 3

100 = Level 4

101 = Level 5

110 = Level 6

111 = Level 7

*Use this value when function is not required for chip-select operation.

For additional information on the MODE and STRB fields, refer to 7.5 Chip-Select

Timing. For more information on the BYTE field, refer to 7.6 Chip Selects and Dy-

namic Bus Sizing. For information on the DSACK field, see 7.5 Chip-Select Timing

and 7.7 Fast Termination Cycles. For details on the IPL, AVEC, and SPACE fields,

refer to 7.8 Using Chip Selects in Interrupt Acknowledge Cycles. Diagrams of the

chip-select option registers are provided in 7.10 Chip-Select Register Diagrams.

7.2 Chip-Select Base Addresses

Each chip select has an associated base address register. The base address register specifies the base address and block size of the memory or peripheral enabled by the chip select. A base address is the lowest address in the block of addresses enabled by a chip select. Block size is the extent of the address block above the base address.

Block sizes of 2 Kbytes to 1 Mbyte can be selected. Address blocks for separate chipselect functions can overlap.

SIM

REFERENCE MANUAL

CHIP SELECTS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

7-3

Freescale Semiconductor, Inc.

NOTE

On CPU16-based MCUs, because the logic states of ADDR[23:20] follow that of ADDR19, a 1-Mbyte block size encoding is not supported. In addition, on these MCUs be sure that the ADDR[23:20] bits in the base address register have the same value as ADDR19, to conform with the logic states of the corresponding address bus pins.

The BLKSZ field determines which bits in the base address field are compared to corresponding bits on the address bus during an access. Provided other constraints determined by option register fields are also satisfied, when a match occurs, the

associated chip-select signal is asserted. Table 7-2 shows BLKSZ encoding.

BLKSZ[2:0]

000

001

010

011

100

101

110

111

Table 7-2 Block Size Encoding

Block Size

2 K

8 K

16 K

64 K

128 K

256 K

512 K

1 M *

Address Lines Compared

ADDR[23:11]

ADDR[23:13]

ADDR[23:14]

ADDR[23:16]

ADDR[23:17]

ADDR[23:18]

ADDR[23:19]

ADDR[23:20]

*Maximum block size = 512 Kbytes on CPU16-based MCUs, in which

ADDR[23:20] = ADDR19

The address compare logic uses only the most significant bits to match an address within a block. The value of the base address must be a multiple of block size. Base address register diagrams show how base register bits correspond to address lines.

(See 7.10 Chip-Select Register Diagrams.)

After reset, the MCU fetches initialization vectors from word addresses beginning at memory location $000000. To support bootstrap operation from reset, the base address field in chip-select base address register boot (CSBARBT) has a reset value of all zeros. A memory device containing initialization can be automatically enabled by

CSBOOT after a reset. The block size field in CSBARBT has a reset value of 512

Kbytes. Refer to 7.9 Chip-Select Reset Operation for more information.

When programming a chip-select circuit to respond to interrupt acknowledge cycles, program the base address field (bits [15:3]) in the base address register to all ones.

Refer to 7.8 Using Chip Selects in Interrupt Acknowledge Cycles for more infor-

mation.

7.3 Pin Assignments and Discrete Output

The chip-select pin assignment registers (CSPAR1–0) contain 12 two-bit fields

(CS[10:0] and CSBOOT) that determine the functions of the chip-select pins. Each pin

has two or three possible functions, as shown in Table 7-3.

MOTOROLA

7-4

CHIP SELECTS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

Table 7-3 Chip-Select Pin Functions

16-Bit

Chip Select

CSBOOT

CS0

CS1

CS2

CS3

CS4

CS5

CS6

CS7

CS8

CS9

CS10

8-Bit

Chip Select

CSBOOT

CS0

CS1

CS2

CS3

CS4

CS5

CS6

CS7

CS8

CS9

CS10

Alternate

Function

CSBOOT

BR

BG

BGACK

FC0

FC1

FC2

ADDR19

ADDR20

ADDR21

ADDR22

ADDR23

Discrete Output or

ECLK

—

—

—

—

PC0

PC1

PC2

PC3

PC4

PC5

PC6

ECLK

Table 7-4 shows pin assignment field encoding. Pins that have no discrete output or

ECLK function do not use the %00 encoding.

Table 7-4 Pin Assignment Field Encoding

Bit Field

00

01

10

11

Description

Discrete Output or ECLK

Alternate Function

Chip Select (8-Bit Port)

Chip Select (16-Bit Port)

Port size is involved in dynamic bus sizing and determines which DSACK signal the

chip-select circuit asserts during a bus cycle. Refer to 7.6 Chip Selects and Dynamic

Bus Sizing for more information.

A pin programmed as a discrete output drives an external signal to the value specified in the port C data register. No discrete output function is available on pins CSBOOT,

BR, BG, or BGACK. ADDR23 provides ECLK output rather than a discrete output signal.

When a pin is programmed for discrete output or alternate function, internal chip-select logic still functions and can be used to generate DSACK or AVEC internally on an ad-

dress and control signal match. Refer to 7.8 Using Chip Selects in Interrupt Ac-

knowledge Cycles for additional information.

Refer to 7.9 Chip-Select Reset Operation for information on pin assignments at re-

set.

7.4 Chip-Select Operation

Pins come out of reset assigned to their chip select function. Before a chip select (other than CSBOOT) can respond to a memory access, however, its option register and base address register must be programmed. The BYTE fields in the option registers for CS[10:0] are cleared during reset. These fields must be set to nonzero values to

SIM

REFERENCE MANUAL

CHIP SELECTS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

7-5

Freescale Semiconductor, Inc.

enable the associated chip selects. However, CSBOOT is made active out of reset so

that it can be used as a chip select for the initialization memory. (See 7.9 Chip-Select

Reset Operation for information on the initial states of the CSBOOT base address

and option registers.)

Disabling the chip selects prevents chip-select signal assertion, even when all other constraints are satisfied. The associated pin is driven high, and internal chip-select logic cannot assert associated signals, such as DSACK or AVEC, internally.

Alternate functions for chip-select pins are enabled if appropriate data bus pins are

held low at the release of the reset signal. (Refer to 7.9 Chip-Select Reset Operation

for more information.)

When the MCU makes a memory access, each enabled chip-select circuit compares the following items:

1. Appropriate ADDR bits to the base address field in the base address register.

2. Function code signals to the SPACE field in the option register.

3. Read/write status to R/W field in the option register.

4. ADDR0 or SIZ bits to the BYTE field in the option register (16-bit ports only).

5. Priority of the interrupt being acknowledged (ADDR[3:1]) to the IPL field in the option register (when the access is an interrupt acknowledge cycle).

When a match occurs, the chip-select signal is asserted. The signal is asserted at the same time as) or DS assertion if MODE = 0 in the chip-select option register; chip-select assertion is synchronized with ECLK if MODE = 1. Chip-select signals are active low.

If a chip-select function is given the same address as an internal microcontroller module or an internal memory array, access to the internal module or array has priority.

The chip-select signal is not asserted, and no external bus cycle occurs.

Figure 7-2 is a flow diagram for the assertion of chip select.

MOTOROLA

7-6

CHIP SELECTS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

BEGIN

ADDRESS

SPACE

FC[2:0]

?

MATCH

BASE

ADDR BITS 3-15

(DEPENDING ON

BLOCK SIZE)

?

MATCH

NO MATCH

NO MATCH

INTERRUPT

ACKNOWLEDGE

CYCLE

?

NO

YES

READ/WRITE

?

MATCH

MATCH OR

NO CHECK INTERRUPT

PRIORITY LEVEL

?

NO MATCH

NO MATCH

16-BIT

PORT SIZE

?

8-BIT

UPPER/LOWER

?

MATCH

NO MATCH

END

1

CS IACK FLOW 1

Figure 7-2 Flow Diagram for Chip Select (Sheet 1 of 3)

SIM

REFERENCE MANUAL

CHIP SELECTS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

7-7

Freescale Semiconductor, Inc.

1

MODE = 0/1

?

MODE = 0

MODE = 1

ASSERTS CS SYNCHRONIZED

WITH AS OR DS

FALLING

EDGE OF ECLK

OCCURS AFTER AS

ASSERTED

?

YES

ASSERTS CS DURING THE

ECLK CYCLE

NO

IACK ENABLED

?

YES

NO

AVEC ENABLED

?

YES

ASSERTS AVEC

NO

3 2

CS IACK FLOW 2

MOTOROLA

7-8

Figure 7-2 Flow Diagram for Chip Select (Sheet 2 of 3)

CHIP SELECTS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

3 2

MODE = 0/1

?

MODE = 0

MODE = 1

DSACK

GENERATOR

INTERNAL OR

EXTERNAL

?

INTERNAL

EXTERNAL

GENERATES DSACK INTERNALLY

WITH WAIT STATES OR

FAST TERMINATE

TERMINATES THE BUS CYCLE

AT THE END OF ECLK CYCLE

NEGATES CS AFTER AS OR DS

END

CS IACK FLOW 3

Figure 7-2 Flow Diagram for Chip Select (Sheet 3 of 3)

7.5 Chip-Select Timing

The MODE bit in the chip-select option register determines whether chip-select operation emulates asynchronous bus operation or is synchronized to the M6800-type bus

clock signal (ECLK) available on ADDR23. (Refer to SECTION 4 SYSTEM CLOCK

for more information on ECLK.) When the MODE bit is programmed to emulate asynchronous bus operation, the DSACK and STRB fields further define chip-select timing.

7.5.1 Synchronization with AS or DS

When MODE = 0 in the associated chip-select option register, chip-select operation emulates asynchronous external bus operation. The chip-select signal is asserted at the same time as AS or DS, depending on the value in the STRB field in the option register. As in an asynchronous bus cycle, the chip-select cycle must be terminated by a data and size acknowledge (DSACK) signal or by an autovector (AVEC) signal.

The value of the DSACK field in the associated chip-select option register determines whether DSACK is generated internally. If it is, the DSACK field determines the number of wait states inserted before internal DSACK assertion.

SIM

REFERENCE MANUAL

CHIP SELECTS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

7-9

Freescale Semiconductor, Inc.

A wait state has a duration of one clock cycle. The wait states are inserted beginning with S3 of the external bus cycle. An encoding of zero wait states corresponds to a three-clock-cycle bus.

Fast termination encoding corresponds to a two-clock-cycle bus access. MCU modules typically respond at this rate; the fast termination encoding is used to access fast external devices. With fast termination encoding, the bus cycle can be terminated at

S3. (Refer to 7.7 Fast Termination Cycles.)

Cycles are terminated by the first DSACK signal that occurs. If an external DSACK signal occurs during internal wait state generation, the bus cycle terminates immediately.

If the externally generated acknowledge option is selected, the MCU waits indefinitely for external DSACK assertion.

If multiple chip selects are to be used to provide control signals to a single device and match conditions can occur simultaneously, all of the associated DSACK fields should be programmed for the same number of wait states. (Alternately, all but one of the associated DSACK fields can be programmed for external DSACK generation, and the remaining DSACK field to the desired number of wait states.) This prevents a conflict on the internal bus when the wait states are loaded into the DSACK counter shared by all chip selects.

7.5.2 Synchronization with ECLK

When MODE = 1 in the associated chip-select option register, chip-select assertion is synchronized to the MCU ECLK output. When a match condition occurs, the chip-select circuit signals the EBI that an ECLK cycle is pending. When the EBI determines that bus timing constraints are satisfied, the chip-select signal is asserted. Transfers of word and long-word data to an 8-bit port are performed consecutively, without insertion of additional ECLK cycles. The bus monitor time-out period must be longer than

the number of clock cycles required for two ECLK cycles. (Refer to SECTION 3 SYS-

TEM CONFIGURATION AND PROTECTION for more information.) Because chip-se-

lect cycles synchronized to ECLK are not terminated by data and size acknowledge signals, the DSACK field has no effect in this mode. The AVEC bit must not be used, since autovector response timing can vary due to ECLK synchronization with the internal system clock.

7.6 Chip Selects and Dynamic Bus Sizing

Chip-select logic works with the external bus interface to perform dynamic bus sizing.

Pin assignment fields (in the pin assignment registers) assign port sizes of 8 or 16 bits

to the devices assigned to the chip selects. (Refer to 7.3 Pin Assignments and Dis-

crete Output for pin assignment field encoding.) Port size assignment determines

which signal the chip-select logic asserts (DSACK1 or DSACK0) after the specified number of wait states elapse during a chip-select access.

Chip select logic also decodes the internal SIZ[1:0] signals to determine which byte or bytes of the data bus to use during a data transfer. In addition, for 16-bit ports, the

BYTE field (in the chip-select option register) determines whether the chip select is as-

serted for upper byte accesses, lower byte accesses, or both. Table 7-5 shows BYTE

field encoding.

MOTOROLA

7-10

CHIP SELECTS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

Table 7-5 BYTE Field Encoding

BYTE[1:0]

00

01

10

11

Meaning

Disable

Assert when ADDR = 0 (lower byte)

Assert when ADDR = 1 (upper byte)

Assert when ADDR = 0 or 1 (either byte)

BYTE field encoding options are used to generate chip-select signals for word and single-byte transfers to 16-bit ports. For example, two chip-select lines can be used to select 8-bit banks in a 16-bit memory. To do this, program two chip-select base address registers with the same base address, then set up the individual lines for byte access.

Program both option registers identically except for the BYTE fields: use the upper byte option for one line and the lower byte option for the other.

Refer to 7.11 Interfacing Example with Chip Selects for an illustration of dynamic

bus sizing using chip selects.

7.7 Fast Termination Cycles

With an external device that has a fast access time, the chip-select circuit fast-termination option can provide a two-cycle external bus transfer. Select this option by assigning a value of %1110 to the field in the appropriate chip-select option register. Fast termination cycles are only available in conjunction with chip selects.

If multiple chip selects are to be used to select the same device that can support fast termination, and match conditions can occur simultaneously, select the fast-termination option in the DSACK field of each associated chip-select option register. Alternately, select fast termination in one of the DSACK fields for external termination.

Fast termination cycles use internal handshaking signals generated by the chip-select logic. To initiate a transfer, the CPU asserts an address and the SIZ[1:0] signals. When

AS, DS, and R/W are valid, a peripheral device places data on the bus during a read cycle or latches data from the bus during a write cycle. At the appropriate time, chipselect logic asserts data and size acknowledge signals. Two clock states (S2 and S3) that are normally required for external handshaking are eliminated during fast termination cycles.

To use the fast-termination option, an external device should be fast enough to have data ready, within the specified setup time, by the falling edge of S4.

When using the fast-termination option, data strobe is asserted only in a read cycle and not in a write cycle. The STRB field in the chip-select option register used must be programmed to address strobe in order to assert the chip select during a fast-termination write cycle.

Figure 7-3 shows the DSACK timing for a read cycle with two wait states, followed by

a fast-termination read cycle and a fast-termination write cycle.

SIM

REFERENCE MANUAL

CHIP SELECTS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

7-11

Freescale Semiconductor, Inc.

CLKOUT

S0 S1 S2 S3 SW SW

*

SW SW

*

S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S0

AS

DS

R/W

DSACK

DATA[15:0]

TWO WAIT STATES IN READ FAST

TERMINATION

READ

*

DSACK only internally asserted for fast termination.

FAST

TERMINATION

WRITE

FAST TERM TIM

Figure 7-3 Fast-Termination Timing

7.7.1 Fast-Termination Read Cycle

A fast-termination read cycle takes place in much the same way as a regular read cycle, except that the clock states for external handshaking are omitted.

State 0 (S0) — The read cycle starts. The CPU places an address on ADDR[23:0] and function codes on FC[2:0]. The CPU drives R/W high for a read cycle. Size signals

SIZ[1:0]; become valid, indicating the number of bytes to be read.

State 1 (S1) — The CPU asserts AS indicating that the address on the address bus is valid. The CPU also asserts DS, indicating to external devices that data can be placed on the data bus. SIM chip-select logic decodes the appropriate address lines, FC[1:0],

R/W, and SIZ[1:0]. One or both of DATA[15:8] and DATA[7:0] are selected, and the responding device places data on that portion of the bus.

State 4 (S4) — Appropriate internal DSACK signals are generated and the CPU latches data on the falling edge of S4.

State 5 (S5) — The CPU negates AS and DS, but holds the address valid to provide address hold time for memory systems. R/W, SIZ[1:0], and FC[2:0] also remain valid throughout S5. The external device must maintain data until either AS or DS is negated. It must remove the data within approximately one clock period after sensing the negation of AS or DS. Signals that remain asserted beyond this limit can be prematurely detected during the next bus cycle.

MOTOROLA

7-12

CHIP SELECTS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

7.7.2 Fast-Termination Write Cycle

A fast-termination write cycle takes place in much the same way as a regular write cycle, except that the clock states for external handshaking are omitted.

State 0 (S0) — The CPU places an address on ADDR[23:0] and function codes on

FC[2:0]. The CPU drives R/W low for a write cycle. Size signals SIZ[1:0] become valid, indicating the number of bytes to be written.

State 1 (S1) — The CPU asserts AS, indicating that the address on the address bus is valid. SIM chip-select logic decodes the appropriate address lines, FC[1:0], R/W,

SIZ[1:0], and AS.

State 4 (S4) — Data driven onto DATA[15:0] becomes valid, and the selected peripheral latches the data. Appropriate internal DSACK signals are generated.

State 5 (S5) — The MCU negates AS but holds the address and data valid to provide address hold time for memory systems. R/W, SIZ[1:0], and FC[2:0] also remain valid throughout S5.

7.8 Using Chip Selects in Interrupt Acknowledge Cycles

Chip-select circuits can be programmed to respond during interrupt acknowledge cycles initiated by assertion of an external IRQ pin. Any chip-select circuit can be programmed so that the chip-select pin is asserted during an interrupt acknowledge cycle when match conditions are met. Alternately, the chip-select circuit can be programmed to generate autovector (AVEC) signals internally.

To configure a chip select to respond during an interrupt acknowledge cycle, bits [15:3] of the base register must be set to all ones to match ADDR[23:11], since the address

is compared to an address generated by the CPU. (See Figure 7-4.) In the chip-select

option register, set the SPACE field to %00 for CPU space, and set the R/W field to read only.

During an interrupt acknowledge cycle, the interrupt priority on ADDR[3:1] is compared to the value of IPL in the chip-select option register. If the values are the same

(and other option register constraints are satisfied), a chip select signal is asserted.

Encoding %000 causes a chip-select signal to be asserted regardless of the interrupt level on ADDR[3:1], provided all other constraints are met.

Figure 7-4 shows CPU space encoding for an interrupt acknowledge cycle. FC[2:0]

are set to %111, designating CPU space access. ADDR[3:1] indicate interrupt priority, and the space type field (ADDR[19:16]) is set to %1111, the interrupt acknowledge code. The rest of the address lines are set to one.

SIM

REFERENCE MANUAL

CHIP SELECTS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

7-13

Freescale Semiconductor, Inc.

INTERRUPT

ACKNOWLEDGE

FUNCTION

CODE

2 0

1 1 1

ADDRESS BUS

23 19 16

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LEVEL

0

1

CPU SPACE

TYPE FIELD

CPU SPACE IACK TIM

Figure 7-4 CPU Space Encoding for Interrupt Acknowledge Cycles

When the chip-select base and option registers are programmed to respond during an interrupt acknowledge cycle, they must not be programmed to select an external device for reading or writing. Normal data accesses occur in supervisor or user data space, but interrupt acknowledge cycles occur in CPU space. To select the device for reading or writing, a separate chip select is needed from the one programmed to respond during interrupt acknowledge cycles. If a chip-select circuit is used for AVEC support, however, the associated pin can still be used for discrete output or its alternate function.

NOTE

If chip-select base and option registers are programmed to generate an AVEC or DSACK signal internally in response to a given interrupt level, and an internal module generates an interrupt request of that level, the internal module will supply an internal DSACK signal to terminate the interrupt acknowledge cycle. The chip-select circuit generates AVEC or DSACK signals only in response to interrupt requests from external IRQ pins.

7.8.1 Using a Chip-Select Pin as an Interrupt Acknowledge Signal

Follow these steps to use a chip-select pin as an interrupt acknowledge signal.

1. Configure the pin as a chip select to an 8- or 16-bit port in the appropriate chipselect pin assignment register.

2. In the base address register, program the base address field (bits [15:3]) to all ones. Program the block size to no more than 64 Kbytes so that the address comparator checks address lines ADDR[19:16] against the corresponding bits in the base address register. (The CPU places the CPU space type on AD-

DR[19:16].)

3. Program the chip-select options register as follows:

• Program MODE to zero to emulate asynchronous bus cycles.

• Set the R/W field to read only. An interrupt acknowledge cycle is performed as a read cycle.

• Program the BYTE field to lower byte when using a 16-bit port, since the external vector for a 16-bit port is fetched from the lower byte. Program the

BYTE field to upper byte when using an 8-bit port.

MOTOROLA

7-14

CHIP SELECTS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

• Program STRB to synchronize with AS.

• Program the DSACK field to the desired number of wait states. Select the

%1111 option if the external device will generate DSACK signals.

• Program IPL to respond to the desired interrupt request level, or to %000 to respond to all request levels.

• Program the AVEC bit to 0 to disable autovector generation. (Generating an autovector signal with chip selects is described in the following subsection.)

7.8.2 Generating an Autovector Signal with a Chip-Select Circuit

If the AVEC bit in the chip-select option register is set to one, chip-select circuitry generates an internal automatic vector signal in response to an interrupt acknowledge cycle initiated by an IRQ pin, provided the match conditions in the base address and option registers are met. The AVEC signal causes the CPU to use a predetermined set of vectors to service the interrupt.

If the AVEC bit is set to zero, the device requesting interrupt service must either assert the AVEC pin or supply the vector and terminate the cycle by asserting DSACK.

The AVEC bit must not be set when the MODE bit is set (chip select assertion synchronized to ECLK), since autovector response timing can vary due to ECLK synchronization.

To generate an autovector signal with a chip-select circuit, follow these steps:

1. For most applications, program the appropriate chip-select pin assignment register to configure the pin for either discrete output or its alternate function. This prevents the pin from being asserted during interrupt acknowledge cycles.

2. In the base address register, program the base address field (bits [15:3]) to all ones. Program the block size to no more than 64 Kbytes so that the address comparator checks address lines ADDR[19:16] against the corresponding bits in the base address register. (The CPU places the CPU space type on AD-

DR[19:16].)

3. Program the chip-select options register as follows:

• Program MODE to zero to emulate asynchronous bus cycles.

• Set the R/W field to read/write.

• Program the BYTE field to both bytes.

• Program STRB to synchronize with AS.

• Program the DSACK field to any value. When the AVEC bit is set, fast termination is automatically selected.

• Program IPL to respond to the desired interrupt request level, or to %000 to respond to all request levels.

• Program the AVEC bit to 1 to enable autovector generation.

7.9 Chip-Select Reset Operation

Chip-select pin assignment at reset and the reset values in the base and option registers are discussed in the following paragraphs.

SIM

REFERENCE MANUAL

CHIP SELECTS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

7-15

Freescale Semiconductor, Inc.

7.9.1 Pin Assignment

Out of reset, chip-select pin functions are determined by the logic levels on pins DA-

TA[7:0]. Data pins have weak internal pull-up drivers, but external devices can hold

the pins low. Refer to SECTION 8 RESET AND SYSTEM INITIALIZATION for sug-

gestions for holding pins low during reset and to APPENDIX A ELECTRICAL CHAR-

ACTERISTICS for drive requirements.

The least significant bit of each of the 2-bit CS[10:0] pin assignment fields in CSPAR0 and CSPAR1 has a reset value of one. The reset value of the most significant bit of each field is determined by the states of DATA[7:1] during reset. An encoding of %11 configures the pin as a chip select for a 16-bit port. An encoding of %01 selects the alternate function for the pin.

DATA[2:0] determine the reset setting of CSPAR0, which controls pins CS[5:0] and

CSBOOT. (See Table 7-6.)

Table 7-6 Reset Pin Function of CS[5:0], CSBOOT

Mode Select Pin

DATA0

DATA1

DATA2

Default Function

(Pin Left High)

CSBOOT 16-Bit

CS0

CS1

CS2

CS3

CS4

CS5

Alternate Function

(Pin Pulled Low)

CSBOOT 8-Bit

BR

BG

BGACK

FC0

FC1

FC2

DATA[7:3] determine the reset setting of CSPAR1, which controls pins CS[10:6]. If an external device pulls one of these data pins low, the associated chip-select pin and lower-numbered pins controlled by CSPAR1 are configured as address pins coming out of reset. For example, if DATA6 is pulled low during reset, pins CS[9:6]/AD-

DR[22:19] are configured as address lines. Table 7-7 summarizes the reset operation

of pins controlled by CSPAR1.

DATA7

1

1

1

1

1

0

Table 7-7 Reset Pin Function of CS[10:6]

Data Bus Pins at Reset

DATA6 DATA5 DATA4

1

1

1

1

0

X

1

0

1

1

X

X

0

X

1

1

X

X

DATA3

X

X

1

0

X

X

Chip-Select/Address Bus Pin Function

CS10/

ADDR23

CS9/

ADDR22

CS8/

ADDR21

CS7/

ADDR20

CS6/

ADDR19

CS10

CS10

CS10

CS10

CS9

CS9

CS9

CS9

CS8

CS8

CS8

ADDR21

CS7

CS7

ADDR20

ADDR20

CS6

ADDR19

ADDR19

ADDR19

CS10 ADDR22 ADDR21 ADDR20 ADDR19

ADDR23 ADDR22 ADDR21 ADDR20 ADDR19

7.9.2 CS[10:0] Base and Option Registers

Base address and option registers for CS[10:0] have reset values of all zeros. This means that the chip selects are disabled out of reset. Assigning a nonzero value in the

BYTE field of the option register enables the associated chip select.

MOTOROLA

7-16

CHIP SELECTS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

7.9.3 CSBOOT Base Address and Option Registers

The CSBOOT assignment field in CSPAR0 is configured differently from the other pin assignment fields. The MSB (bit 1) of the CSBOOT assignment field in CSPAR0, has a reset value of one. This enables the CSBOOT signal to select a boot ROM containing initialization firmware. The LSB value, determined by the logic level of DATA0 during reset, selects boot ROM port size. When DATA0 is held low, port size is 8 bits.

When DATA0 is held high (either by the weak internal pull-up driver or by an external pull-up device), port size is 16 bits.

After reset, the MCU fetches initialization vectors beginning at word address $000000.

To support bootstrap operation from reset, the base address field in chip-select base address register boot (CSBARBT) has a reset value of all zeros. A ROM device containing a reset vector beginning at its base address can be enabled by CSBOOT after a reset.

Table 7-8 shows the reset values in the base and option registers for CSBOOT.

Table 7-8 CSBOOT Base and Option

Register Reset Values

Field

Base Address

Block Size

Timing Mode

Upper/Lower Byte

Read/Write

Strobe (AS/DS)

DSACK

Address Space

IPL

Autovector

Reset Value

$000000

1 Mbyte *

Emulates Asynchronous Bus Cycles

Both Bytes

Read/Write

AS

13 Wait States

Supervisor/User Space

Any Level

Interrupt Vector Externally

*Default block size is effectively 512 Kbyte on CPU16-based MCUs since values of ADDR[23:20] follow ADDR19.

7.10 Chip-Select Register Diagrams

Chip-select registers include two pin assignment registers, two base address registers, twelve option registers, and a discrete output data register.

7.10.1 Chip-Select Pin Assignment Registers

The pin assignment registers contain 12 two-bit fields (CS[10:0] and CSBOOT) that determine the functions of the chip-select pins. Each pin has two or three possible functions, as shown below. Pins that have no discrete output function do not use the

%00 encoding.

Bit Field

00

01

10

11

Description

Discrete Output

Alternate Function

Chip Select (8-Bit Port)

Chip Select (16-Bit Port)

SIM

REFERENCE MANUAL

CHIP SELECTS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

7-17

Freescale Semiconductor, Inc.

NOTE

On MCUs with a reduced pin-count SIM, some chip-select pins may not be available. Refer to the user's manual for the particular MCU for details.

Pin assignments at reset are determined by the states of the data bus pins indicated

in the following register diagrams. Refer to 7.9 Chip-Select Reset Operation for ad-

ditional information on pin assignments at reset.

CSPAR0 — Chip-Select Pin Assignment Register 0

15

0

RESET:

14

0

0 0

13 12

CSPA0[6]

DATA2 1

11 10

CSPA0[5]

DATA2 1

9

CSPA0[4]

8

DATA2 1

7

CSPA0[3]

6

DATA1 1

5

CSPA0[2]

4

DATA1 1

3

CSPA0[1]

2

DATA1 1

$####44

1

CSBOOT

0

1 DATA0

CSPAR0 contains seven two-bit fields that determine the functions of corresponding chip-select pins. CSPAR0[15:14] are not used. These bits always read zero; writes have no effect. CSPAR0 bit 1 always reads one; writes to CSPAR0 bit 1 have no effect.

CSPAR0 Field

CSPA0[6]

CSPA0[5]

CSPA0[4]

CSPA0[3]

CSPA0[2]

CSPA0[1]

CSBOOT

Table 7-9 CSPAR0 Pin Assignments

Chip Select Signal

CS5

CS4

CS3

CS2

CS1

CS0

CSBOOT

Alternate Signal

FC2

FC1

FC0

BGACK

BG

BR

—

Discrete Output

PC2

PC1

PC0

—

—

—

—

CSPAR1 — Chip-Select Pin Assignment Register 1 $####46

15

0

RESET:

14

0

0 0

13

0

12

0

11

0

10

0

9

CSPA1[4]

8 7

CSPA1[3]

6 5

CSPA1[2]

4 3

CSPA1[1]

2 1

CSPA1[0]

0

0 0 0 0 DATA7 1 DATA6 1 DATA5 1 DATA4 1 DATA3 1

CSPAR1contains five two-bit fields that determine the functions of corresponding chipselect pins. CSPAR1[15:10] are not used. These bits always read zero; writes have no effect.

CSPAR0 Field

CSPA1[4]

CSPA1[3]

CSPA1[2]

CSPA1[1]

CSPA1[0]

Table 7-10 CSPAR1 Pin Assignments

Chip Select Signal

CS10

CS9

CS8

CS7

CS6

Alternate Signal

ADDR23

ADDR22

ADDR21

ADDR20

ADDR19

Discrete Output

ECLK

PC6

PC5

PC4

PC3

MOTOROLA

7-18

CHIP SELECTS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

7.10.2 Chip-Select Base Address Registers

CSBARBT contains the base address for selection of a bootstrap peripheral memory device. Bit and field definition for CSBARBT and CSBAR[10:0] are the same, but reset

block sizes differ. Refer to 7.2 Chip-Select Base Addresses for more information.

CSBARBT — Chip-Select Base Address Register Boot ROM

15

ADDR

23

RESET:

14

ADDR

22

0 0

13

ADDR

21

0

12

ADDR

20

0

11

ADDR

19

0

10

ADDR

18

0

9

ADDR

17

0

8

ADDR

16

0

7

ADDR

15

0

6

ADDR

14

0

5

ADDR

13

0

4

ADDR

12

0

3

ADDR

11

0

2

1

$####48

1

BLKSZ

1

0

1

CSBAR[10:0] — Chip-Select Base Address Registers

15

ADDR

23

RESET:

14

ADDR

22

0 0

13

ADDR

21

0

12

ADDR

20

0

11

ADDR

19

0

10

ADDR

18

0

9

ADDR

17

0

8

ADDR

16

0

7

ADDR

15

0

6

ADDR

14

0

5

ADDR

13

0

4

ADDR

12

$####4C–$####74

3

ADDR

11

2 1

BLKSZ

0

0 0 0 0 0

ADDR[15:3] — Base Address Field

This field sets the starting address of a particular address space.

BLKSZ — Block Size Field

This field determines the size of the block above the base address that is enabled by the chip select.

7.10.3 Chip-Select Option Registers

Option register fields determine timing of and conditions for assertion of chip-select signals. CSORBT contains parameters that support bootstrap operations from peripheral memory devices. Bit and field definitions for CSORBT and CSOR[10:0] are the same, but their reset settings differ.

CSORBT — Chip Select Option Register Boot ROM

15

MODE

RESET:

14

BYTE

13

0 1 1

12

1

R/W

11

1

10

STRB

0

9

1

8

DSACK

7

1 0

6

1

CSOR[10:0] — Chip Select Option Registers

15

MODE

RESET:

14

BYTE

13

0 0 0

12

0

R/W

11

0

10

STRB

0

9

0

8

DSACK

7

0 0

6

0

5

SPACE

4

1

0

1

5

SPACE

4

0

3

0

0

2

IPL

$####4A

1 0

AVEC

0 0 0

3

$####4E–$####76

2

IPL

1 0

AVEC

0 0 0

SIM

REFERENCE MANUAL

CHIP SELECTS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

7-19

Freescale Semiconductor, Inc.

MODE — Timing Mode

The MODE bit determines whether chip-select operation emulates asynchronous bus operation or is synchronized to the M6800-type bus clock signal (ECLK) available on

ADDR23. Refer to 7.5 Chip-Select Timing for additional information.

0 = Emulate asynchronous bus operation

1 = Synchronize chip-select assertion to ECLK

BYTE — Upper/Lower Byte Option

This field enables or disables the chip-select circuit and, for 16-bit ports, determines which combinations of size and ADDR0 pins will cause the chip select to be asserted.

Refer to 7.6 Chip Selects and Dynamic Bus Sizing for more information.

00 = Disable

01 = Lower byte

10 = Upper byte

11 = Both Bytes

R/W — Read/Write

This field causes a chip select to be asserted only for a read, only for a write, or for both read and write.

00 = Reserved

01 = Read only

10 = Write only

11 = Read/Write

STRB — Address Strobe/Data Strobe

The STRB bit controls the timing of a chip-select assertion in asynchronous mode.

This bit has no effect in synchronous mode.

0 = Synchronize chip select assertion with address strobe

1 = Synchronize chip select assertion with data strobe

DSACK — Data and Size Acknowledge

This field specifies the source of DSACK when chip-select cycles emulate asynchro-

nous bus cycles, and controls wait state insertion. Refer to 7.6 Chip Selects and Dy-

namic Bus Sizing for details.

SPACE — Address Space Select

The SPACE field determines the address space in which a chip select is asserted. An access must have the space type represented by SPACE encoding in order for a chip-

select signal to be asserted. Refer to 7.8 Using Chip Selects in Interrupt Acknowl-

edge Cycles for additional information.

00 = CPU space

01 = User space

10 = Supervisor space

11 = Supervisor or user space

MOTOROLA

7-20

CHIP SELECTS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

IPL — Interrupt Priority Level

This field selects the interrupt level when a chip select is used for interrupt acknowl-

edge. Refer to 7.8 Using Chip Selects in Interrupt Acknowledge Cycles for addi-

tional information.

000 = Any Level

001 = Level 1

010 = Level 2

011 = Level 3

100 = Level 4

101 = Level 5

110 = Level 6

111 = Level 7

AVEC — Autovector Enable

This field specifies whether to generate an internal AVEC signal during an interrupt acknowledge cycle initiated by assertion of an IRQ pin when match conditions are met.

Refer to 7.8 Using Chip Selects in Interrupt Acknowledge Cycles for additional in-

formation.

0 = Disable AVEC generation

1 = Enable AVEC generation

7.10.4 Port C Data Register (PORTC)

The port C data register latches data for pins programmed as discrete outputs. When a pin is assigned as a discrete output, the value in this register appears at the output.

PC[6:0] correspond to CS[9:3]. This is a read/write register. Bit 7 is not used. Writing

to this bit has no effect, and a read returns zero. Refer to 7.3 Pin Assignments and

Discrete Output for more information on this register.

PORTC — Port C Data Register

15 14 13 12

NOT USED

11 10

RESET:

9 8 7

0

6

PC6

5

PC5

4

PC4

3

PC3

2

PC2

$####40

1

PC1

0

PC0

1 1 1 1 1 1 1 1

7.11 Interfacing Example with Chip Selects

Figure 7-5 shows a system configuration in which SIM chip-select pins are connected

to a boot ROM module and a 16-bit memory consisting of two banks of 8-bit memory.

The following paragraphs discuss connecting the pins and programming the base and option registers for the connected chip selects.

SIM

REFERENCE MANUAL

CHIP SELECTS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

7-21

MCU

ADDR[15:0]

DATA[15:0]

Freescale Semiconductor, Inc.

DATA ADDR

RAM

8K X 8

DATA ADDR

RAM

8K X 8

DATA ADDR

ROM

64K X 16

R/W E R/W E E

R/W

CS0

CS1

CSBOOT

UPPER BYTE ENABLE

LOWER BYTE ENABLE

ROM ENABLE

MIN SYS BLOCK

Figure 7-5 System Configuration with Chip Selects

7.11.1 Configuring the RAM Chip Selects

The following paragraphs describe the configuration of the RAM chip selects in the ex-

ample configuration (Figure 7-5).

7.11.1.1 Pin Connections

The upper and lower memory banks are connected to CS0 and CS1, respectively. AD-

DR[13:1] are connected to ADDR[12:0] of each memory bank. ADDR0 of the MCU is not connected to the memory chips; instead, the chip-select logic in each circuit uses the value of ADDR0 on the internal address bus and the value of the BYTE field in the associated chip-select option register to determine whether a match occurs.

No DSACK lines are connected, since the chip selects are configured to generate

DSACK signals internally. No function code lines are connected; in this example, chipselect logic is used to specify supervisor/user space.

7.11.1.2 Base Address Registers

The base address registers are programmed as follows:

CSBAR0 = $1001

CSBAR1 = $1001

This selects a block size of 16 Kbytes starting at address $100000.

MOTOROLA

7-22

CHIP SELECTS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

7.11.1.3 Option Registers

The option registers (CSOR0 and CSOR1) are programmed as follows:

MODE = %0. This causes chip select operation to emulate asynchronous bus operation. (Bus cycles are terminated with DSACK.)

BYTE = %10 in CSOR0 and BYTE = %01 in CSOR1. This assigns the memory bank connected to CS0 as the upper byte and the bank connected to CS1 as the lower byte.

R/W = %11. This configures the memory for both reads and writes.

STRB = %0. This causes the chip select to be asserted with AS.

DSACK = %0000. This causes DSACK signals to be generated internally by the

SIM chip-select circuitry, with zero wait states inserted.

SPACE = %11. This selects the memory for both supervisor and user access.

IPL, AVEC = %0000. Since the chip selects are not being used during interrupt acknowledge cycles, the interrupt fields are set to zeros.

7.11.2 Configuring the Boot ROM Chip Select

The following paragraphs describe the configuration of the boot ROM chip select in

Figure 7-5.

7.11.2.1 Pin Connections

The boot ROM chip is connected to CSBOOT. ADDR[16:1] are connected to AD-

DR[15:0] of the ROM chip. ADDR0 of the MCU is not connected to the ROM in this example.

As with the RAM chips, no DSACK lines are connected, since the chip selects are configured to generate DSACK signals internally. No function code lines are connected; in this example, chip-select logic is used to specify supervisor/user space.

7.11.2.2 Base Address Register

CSBARBT comes out of reset with a base address of $000000 and a block size of 1

Mbyte. The register is reassigned this value:

CSBARBT = $0003

This selects a block size of 128 Kbytes starting at address $000000.

7.11.2.3 Option Registers

The option register (CSORBT) is reprogrammed as follows:

MODE = %0. This causes chip select operation to emulate asynchronous bus operation. (Bus cycles are terminated with DSACK.)

BYTE = %11. This assigns the ROM to be a 16-bit port.

SIM

REFERENCE MANUAL

CHIP SELECTS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

7-23

Freescale Semiconductor, Inc.

R/W = %01. This configures the memory as read only.

STRB = %0. This causes the chip select to be asserted with AS.

DSACK = %0010. This causes DSACK signals to be generated internally by the

SIM chip-select circuitry, with two wait states inserted.

SPACE = %11. This selects the memory for both supervisor and user access.

IPL, AVEC = %0000. For read/write cycles, the interrupt fields are set to zeros.

MOTOROLA

7-24

CHIP SELECTS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

SECTION 8 RESET AND SYSTEM INITIALIZATION

Reset procedures handle system initialization and recovery from catastrophic failure.

The MCU performs resets with a combination of hardware and software. The SIM determines whether a reset is valid, synchronizes the reset if necessary to the completion of the current bus cycle, asserts the appropriate internal signals, performs basic system configuration and boot ROM selection based on hardware mode-select inputs, and then passes control to the CPU.

The CPU handles a reset as the highest-priority exception. Each exception has an assigned vector that points to an associated handler routine. During exception processing, the CPU fetches the vector assigned to the exception and executes the exception routine to which the vector points.

Exception vectors are stored in a vector table. Out of reset, the table is located beginning at address $000000. The reset vector occupies the first four words of the vector table. The CSBOOT chip-select signal, which responds to memory accesses starting at $000000 coming out of reset, can be used to select the boot ROM chip with the system initialization routine.

The size of the vector table, the size of each exception vector, and whether the table can be relocated depend on the CPU. Refer to the appropriate CPU reference manual for additional information on exception vectors and exception processing.

8.1 Reset Operation

Sources of reset include external reset, power-on reset, software watchdog, double bus fault, loss of crystal, and system (the CPU32 RESET instruction). The reset status register (RSR) contains a status bit for every reset source in the SIM.

Reset control logic determines the cause of reset, synchronizes reset assertion if necessary to the completion of the current bus cycle, and asserts the appropriate reset lines.

Reset control logic can drive four different internal signals:

• EXTRST (external reset) drives the external reset pin.

• CLKRST (clock reset) resets the clock module.

• MSTRST (master reset) goes to all other internal circuits.

• SYSRST (system reset) indicates to internal circuits that the CPU has executed a RESET instruction.

Figure 8-1 indicates the different sources of reset and the reset lines that the reset

control logic asserts for each type of reset request.

SIM

REFERENCE MANUAL

RESET AND SYSTEM INITIALIZATION

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

8-1

Freescale Semiconductor, Inc.

RESET REQUEST

SYSTEM

SOFTWARE WATCHDOG

DOUBLE BUS FAULT

LOSS OF CLOCK

TEST

RESET

CONTROL

LOGIC

RESET LINE

MSTRST

CLKRST

EXTRST

SYSRST

POWER-ON RESET

RESET LOGIC BLOCK

Figure 8-1 Reset Block Diagram

All resets are gated by CLKOUT. Resets are classified as synchronous or asynchronous. An asynchronous reset can occur on any CLKOUT edge. Reset sources that cause an asynchronous reset usually indicate a catastrophic failure; thus the reset control logic responds by asserting reset to the system immediately. (A system reset, however, caused by the CPU32 RESET instruction, is asynchronous but does not in-

dicate any type of catastrophic failure; see 8.2 Sources of Reset for more informa-

tion.)

A synchronous reset occurs at the end of a bus cycle. For synchronous resets, only single-byte or aligned-word writes on the IMB are guaranteed to be completed without data corruption. Long-word writes, misaligned operand writes, and read cycles are not guaranteed to be completed. External writes are also guaranteed to be completed, provided the external configuration logic on the data bus is conditioned by R/W as

shown in Figure 8-4 later in this section.

The internal bus monitor is automatically enabled whenever the reset control logic must synchronize reset to the end of the bus cycle. When a bus cycle does not terminate normally, the bus monitor terminates it based on the length of time programmed

in the BMT field of the system protection control register. Refer to 3.2 Internal Bus

Monitor for additional information.

8.2 Sources of Reset

Sources of reset include external reset requests, the power-on reset circuit, the software watchdog monitor, the double bus fault monitor, the loss-of-crystal circuitry, and the CPU32 RESET instruction (system reset). The reset status register (RSR) contains a status bit for every reset source in the EBI.

NOTE

The RESET instruction is a CPU32 instruction; the CPU16 does not support it.

Table 8-1 is a summary of reset sources.

MOTOROLA

8-2

RESET AND SYSTEM INITIALIZATION

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

Type

External

Power Up

Software Watchdog

Double Bus Fault

Loss of Clock

Test

System

Table 8-1 Reset Sources

Source

External

EBI

Timing

Synch

Asynch

Cause

External Signal

V

DD

Lines Asserted by

Reset Controller

MSTRST CLKRST EXTRST

MSTRST CLKRST EXTRST

SW Monitor Asynch

DBF Monitor Asynch

Clock

Test

CPU32

Synch

Synch

Asynch

Time Out

Double Bus Fault

Loss of Reference

Test Mode

RESET Instruction

MSTRST

MSTRST

MSTRST

MSTRST

—

CLKRST

CLKRST

CLKRST

—

—

EXTRST

EXTRST

EXTRST

EXTRST

EXTRST

8.2.1 External Reset

When the EXT bit in the RSR is set, the most recent was caused by an external device asserting RESET. External resets are synchronous.

NOTE

Since this pin is bidirectional, a conflict exists when the CPU32 executes a RESET instruction and an external device asserts the RE-

SET line. On CPU32-based MCUs, to guarantee that an external reset is recognized by the EBI, RESET must be held for at least 520 cycles so that it overlaps the 512 cycles of the CPU32 RESET instruction.

8.2.2 Power-On Reset

When the POW bit in the RSR is set, the most recent reset state was caused by the power-on reset circuit in the reset controller. A power-on reset is asynchronous. Refer

to 8.4 Power-On Reset for more information.

8.2.3 Software Watchdog Reset

When the SW bit in the RSR is set, the most recent reset was caused by the software watchdog circuit in the system protection module. A software watchdog reset indicates that the CPU is no longer executing the desired code. A software watchdog reset is asynchronous.

8.2.4 Double Bus Fault Reset

When the DBF bit in the RSR is set, the most recent reset was caused by a double bus fault detected by the system protection module. This type of reset is asynchronous.

8.2.5 Loss of Clock Reset

When the LOC bit in the RSR is set, the most recent reset was caused by a loss of clock reference signal. This reset condition can exist only if the RSTEN bit in the synthesizer control register (SYNCR) is set and the VCO is being used. This type of reset is synchronous.

SIM

REFERENCE MANUAL

RESET AND SYSTEM INITIALIZATION

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

8-3

Freescale Semiconductor, Inc.

8.2.6 System Reset

When the SYS bit in the RSR is set, the most recent reset was caused by the CPU32

RESET instruction. (The CPU16 does not support this instruction.) This type of reset does not load a reset vector or affect CPU registers or SIM configuration registers, but does assert the RESET line, thus resetting external devices and internal modules other than the CPU. (Not all internal modules respond to system reset. Refer to the reference manuals for the individual modules to determine how they respond to this instruction.) System reset thus allows software to reset the system to a known state and then continue processing with the next instruction.

Since the CPU32 is in control during a RESET instruction, it is not normally necessary to read the RSR to determine the source of reset. The SYS bit is provided, however, for the sake of completeness.

8.2.7 Test Module Reset

When the TST bit in the RSR is set, the most recent reset was caused by the test submodule. This condition occurs during system testing only.

8.2.8 Reset Status Register

The reset status register (RSR) contains a bit for each reset source in the MCU. When a reset occurs, a bit corresponding to the reset type is set. When multiple causes of reset occur at the same time, more than one bit in RSR may be set. The reset status register is updated by the reset control logic when the RESET signal is released. This register can be read at any time. A write has no effect.

RSR — Reset Status Register

15 14 13 12

NOT USED

11 10 9 8 7 6

EXT POW

5

SW

4

DBF

3

0

2

LOC

$####06

1

SYS

0

TST

EXT — External Reset

Reset was caused by an external signal.

POW — Power-On Reset

Reset was caused by the power-on reset circuit.

SW — Software Watchdog Reset

Reset was caused by the software watchdog circuit.

DBF — Double Bus Fault Reset

Reset was caused by a double bus fault.

LOC — Loss of Clock Reset

Reset was caused by loss of clock reference signal.

SYS — System Reset

Reset was caused by the CPU32 RESET instruction. The CPU16 does not support this instruction.

TST — Test Submodule Reset

Reset was caused by the test submodule. This bit is set during system test only.

MOTOROLA

8-4

RESET AND SYSTEM INITIALIZATION

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

8.3 Reset Control Flow

The following paragraphs describe reset control flow after the SIM receives a reset re-

quest. Refer to 8.4 Power-On Reset for additional details of reset timing during power-

on reset. Figure 8-2 is a reset control flow diagram.

POWER-ON RESET

ASSERT EXTERNAL RESET

NO VCO

LOCKED

?

YES

512-CLOCK COUNTDOWN

ASSERT EXTERNAL RESET

LATCH DATA BUS CONFIGURATION

AND RECONFIGURE

ASSERT EXTERNAL RESET

12-CLOCK COUNTDOWN

EXTERNAL RESET NOT DRIVEN

YES EXTERNAL

RESET ASSERTED

?

NO

FETCH RESET VECTOR AND RUN

CODE UNTIL RESET IS ASSERTED

FROM ANY SOURCE

EXTERNAL RESET NOT DRIVEN

NO

YES

EXTERNAL

RESET ASSERTED

?

SOFTWARE

RESET

?

YES

512-CLOCK COUNTDOWN

ASSERT EXTERNAL RESET

NO

12-CLOCK COUNTDOWN

EXTERNAL RESET NOT DRIVEN

EXTERNAL

RESET ASSERTED

?

NO

YES

CONTINUE RUNNING CODE

UNTIL RESET IS ASSERTED FROM

ANY SOURCE

EXTERNAL RESET NOT DRIVEN

SIM RESET FLOW

Figure 8-2 Reset Control Flow

SIM

REFERENCE MANUAL

RESET AND SYSTEM INITIALIZATION

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

8-5

Freescale Semiconductor, Inc.

8.3.1 RESET Assertion by an External Device

When an external device requests reset by asserting RESET for at least four CLKOUT cycles, reset control logic clocks the signal into an internal latch. The control logic drives the RESET pin low for an additional 512 CLKOUT cycles after it detects that the

RESET signal is no longer being externally driven, to guarantee this length of reset to the entire system.

After 512 cycles have elapsed, allowing the weak pull-up devices on the data bus configuration pins to pull the pins up to logic level one, the RESET pin goes to a disabled

(high-impedance) state for 10 cycles. At the end of this 10-cycle period, the data bus pin configuration is latched, and the state of the RESET pin is tested. If the pin state is logic level one (negated), reset exception processing begins. If, however, the pin state is logic level zero (asserted), the reset control logic drives the pin low for another

512 cycles, on the assumption that an external device is driving the pin low. At the end of this period, the pin again goes to a high-impedance state for 10 cycles, and then is tested again. The process repeats until RESET goes high.

Refer to parameters 77 and 78 in Table A-3 in APPENDIX A ELECTRICAL CHAR-

ACTERISTICS for additional timing details regarding RESET assertion and negation.

8.3.2 Internal Reset Request

When reset is requested by any source other than an external device driving the RE-

SET pin low, the reset control logic asserts RESET for a minimum of 512 cycles, allowing the weak pull-up devices on the data bus configuration pins to pull the pins up to logic level one. If the reset signal is still asserted at the end of 512 cycles, the control logic continues to assert RESET until the internal reset signal is negated.

8.4 Power-On Reset

When the SIM clock synthesizer is used to generate the system clock, power-on reset involves special circumstances related to the application of system and clock synthesizer power. Regardless of clock source, voltage must be applied to clock synthesizer power input pin V

DDSYN

in order for the MCU to operate. The following discussion assumes that V

DDSYN

is applied before and during reset, minimizing crystal start-up time. When this is not the case, start-up time includes crystal cold start-up time in addition to the delays listed in the following paragraphs. Crystal start-up time without

V

DDSYN

applied is affected by specific crystal parameters and by oscillator circuit design.

8.4.1 SIM Operation During Power-On Reset

During power-on reset, an internal circuit in the SIM drives the IMB internal (MSTRST) and external (EXTRST) reset lines. The power-on reset circuit releases the internal reset line as V

DD

ramps up to the minimum operating voltage (refer to Table A-4 in AP-

PENDIX A ELECTRICAL CHARACTERISTICS), and SIM pins are initialized to the

values shown in Table 8-3. When V

DD

reaches the minimum operating voltage, the clock synthesizer VCO begins operation. Clock frequency ramps up to the specified limp mode frequency (F

LIMP

). The external RESET signal remains asserted until the clock synthesizer PLL locks and 512 CLKOUT cycles elapse.

MOTOROLA

8-6

RESET AND SYSTEM INITIALIZATION

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

Figure 8-3 is a timing diagram of power-on reset. It shows the relationships between

RESET, V

DD

, and bus signals.

CLKOUT

VCO

LOCK

VDD

RESET

BUS

CYCLES

BUS STATE

UNKNOWN

NOTES:

1. Internal start-up time.

2. First instruction fetched (CPU32).

3. First instruction fetched (CPU16).

512 CLOCKS

ADDRESS AND

CONTROL SIGNALS

THREE-STATED

10 CLOCKS

1 2 3

POR TIM

Figure 8-3 Power-On Reset Timing

8.4.2 Other Modules During Power-On Reset

The clock synthesizer in the SIM provides clock signals to other MCU modules. After the clock is running and the internal reset signal (MSTRST) is asserted for at least four clock cycles, these modules are reset. V

DD ramp time and VCO frequency ramp time determine how long these four cycles take. Worst case is approximately 15 milliseconds.

During this period, input/output and output-only port pins on modules other than the

SIM may be in an indeterminate state. Input/output pins on these modules may be in output mode for a short time, which may create a conflict with external input drive logic.

If a known state on input/output or output-only pins is required before this 15-ms period, external reset control logic must condition these lines. Active drivers require highimpedance buffers or isolation resistors to prevent conflict.

Input-only pins can be placed in a known state by means of external pull-up resistors.

8.5 Use of the Three-State Control Pin

Asserting the three-state control (TSC) input causes the MCU to put all output drivers in a disabled, high-impedance state. The signal must remain asserted for approximately 10 clock cycles in order for drivers to change state.

When the internal clock synthesizer is used (MODCLK held high during reset), synthesizer ramp-up time affects how long the 10 cycles take. Worst case is approximately

20 milliseconds from TSC assertion.

SIM

REFERENCE MANUAL

RESET AND SYSTEM INITIALIZATION

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

8-7

Freescale Semiconductor, Inc.

When an external clock signal is applied (MODCLK held low during reset), pins go to high-impedance state as soon after TSC assertion as approximately 10 clock pulses have been applied to the EXTAL pin.

NOTE

When TSC assertion takes effect, internal signals are forced to values that can cause inadvertent mode selection. Once the output drivers change state, the MCU must be powered down and restarted before normal operation can resume.

8.6 Operating Configuration out of Reset

The logic states of certain data bus pins during reset determine SIM operating configuration. In addition, the state of the MODCLK pin determines the system clock source, and the state of the BKPT pin determines what happens during subsequent breakpoint

assertions. Table 8-2 is a summary of reset mode selection options. Subsequent para-

graphs explain these options in detail.

Mode Select Pin

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

DATA9

DATA11

MODCLK

BKPT

Table 8-2 Reset Mode Selection

Default Function

(Pin Left High)

CSBOOT 16-Bit

CS0

CS1

CS2

CS3

CS4

CS5

CS6

CS[7:6]

CS[8:6]

CS[9:6]

CS[10:6]

DSACK0, DSACK1,

AVEC, DS, AS,

SIZE

IRQ[7:1]

MODCLK

Test Mode Disabled

VCO = System Clock

Background Mode Disabled

Alternate Function

(Pin Pulled Low)

CSBOOT 8-Bit

BR

BG

BGACK

FC0

FC1

FC2

ADDR19

ADDR[20:19]

ADDR[21:19]

ADDR[22:19]

ADDR[23:19]

PORTE

PORTF

Test Mode Enabled

EXTAL = System Clock

Background Mode Enabled

8.6.1 Data Bus Mode Selection

All data lines have weak internal pull-up drivers during reset. When pins are held high by the internal drivers, the MCU uses a default operating configuration. However, specific lines can be held low externally to achieve an alternate configuration.

NOTE

External bus loading can overcome the weak internal pull-up drivers on data bus lines and hold pins low during reset.

MOTOROLA

8-8

RESET AND SYSTEM INITIALIZATION

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

DATA0 determines the function of the boot ROM chip-select signal CSBOOT. Unlike other chip-select signals, CSBOOT is active at the release of reset. During reset exception processing, the MCU fetches initialization vectors beginning at address

$000000 in supervisor program space. After a reset, an external memory device containing the reset vector can be enabled by CSBOOT, which is assigned at reset to a memory block beginning at $000000. The logic level of DATA0 during reset selects boot ROM port size. When DATA0 is held low, port size is 8 bits; when DATA0 is held high, either by the weak internal pull-up driver or by an external pull-up, port size is 16

bits. Refer to 7.9 Chip-Select Reset Operation for more information.

DATA1 and DATA2 determine the functions of CS[2:0] and CS[5:3], respectively. DA-

TA[7:3] determine the functions of an associated chip select and all lower-numbered chip-selects down through CS6. For example, if DATA5 is pulled low during reset,

CS[8:6] are assigned alternate function as ADDR[21:19], and CS[10:9] remain chip selects. (On some MCUs, ADDR[23:20] follow the state of ADDR19, and DATA[7:4]

have limited use.) Refer to 7.9 Chip-Select Reset Operation for more information.

DATA8 determines the function of the DSACK0, DSACK1, AVEC, DS, AS, and

SIZ[1:0] pins. If DATA8 is held low during reset, these pins are used for discrete I/O

(port E).

DATA9 determines the function of interrupt request pins (IRQ[7:0]) and the clock mode select pin (MODCLK). When DATA9 is held low during reset, these pins are used for discrete I/O (port F).

DATA11 determines whether the SIM operates in test mode out of reset. This capability is used for factory testing of the MCU.

8.6.2 Holding Data Bus Pins Low at Reset

To avoid conflicts on the data bus during reset, use an active device to hold data bus lines low. The data bus configuration logic must be released prior to the first bus cycle after reset in order to prevent conflict with external memory devices. The first bus cycle occurs 14 CLKOUT cycles after RESET is released. If external mode selection logic causes a conflict with external memory devices, an isolation resistor on the driven lines

may be required. Figure 8-4 shows a recommended method for conditioning data bus

pins that are held low at reset.

SIM

REFERENCE MANUAL

RESET AND SYSTEM INITIALIZATION

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

8-9

Freescale Semiconductor, Inc.

MODE SELECT

LINES

••

••

••

DATA15

DATA1

DATA0

V DD V DD

••

••

••

* * *

RESET

• • • • • •

DS

R/W

*

Optional, to prevent conflict on RESET negation.

DATA BUS MODE DECODE

Figure 8-4 Data Bus Signal Conditioning

If conflicts on the data bus during reset are not a concern, a diode in series with a 1k

Ω

resistor can be used in place of an active device to hold a data bus pin low.

8.6.3 Clock Mode Selection

The state of the clock mode (MODCLK) pin during reset determines which clock source the MCU uses. When MODCLK is held high during reset, the clock signal is generated from a reference frequency. When MODCLK is held low during reset, the clock synthesizer is disabled, and an external system clock signal must be applied.

Refer to SECTION 4 SYSTEM CLOCK for more information.

NOTE

If the MODCLK pin is also used as a parallel port pin, make certain that bus loading does not overcome the weak internal pull-up driver during reset and cause inadvertent clock mode selection.

8.6.4 Breakpoint Mode Selection

The MCU uses internal and external breakpoint (BKPT) signals. During reset exception processing, at the release of the RESET signal, the CPU samples these signals to determine how to handle breakpoints.

If either BKPT signal is at logic level zero when sampled, an internal BDM flag is set, and the CPU enters background debugging mode whenever either BKPT input is subsequently asserted.

If both BKPT inputs are at logic level one when sampled, breakpoint exception processing begins whenever either BKPT signal is subsequently asserted.

MOTOROLA

8-10

RESET AND SYSTEM INITIALIZATION

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

Refer to the appropriate CPU manual for more information on background debugging

mode and exceptions. Refer to 5.8 CPU Space Cycles for information concerning

breakpoint acknowledge bus cycles.

8.7 Pin State During Reset

While the MCU is held in reset, the data bus pins are configured as inputs. Function code pins are driven high. Bus control pins AS, DS, SIZ[1:0], and RMC are driven high

if configured for their bus control function (see Table 8-3). Any bus control pins con-

figured for I/O (ports E and F) are configured as inputs when the SIM comes out of reset.

NOTE

Pins that are not used should either be configured as outputs or (if configured as inputs) pulled to the appropriate inactive state. This decreases additional I

DD

caused by digital inputs floating near mid-supply level.

After RESET is released, mode selection occurs, and reset exception processing begins. Pins configured as inputs during reset become active high-impedance loads after

RESET is released. Inputs must be driven to the desired active state; pull-up or pulldown circuitry may be necessary. Pins configured as outputs begin to function after

RESET is released.

Table 8-3 is a summary of SIM pin states during reset.

SIM

REFERENCE MANUAL

RESET AND SYSTEM INITIALIZATION

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

8-11

Freescale Semiconductor, Inc.

Table 8-3 SIM Pin Reset States

Mnemonic

CS10/ADDR23

CS[9:6]/ADDR[22:19]/

PC[6:3]

ADDR[18:0]

AS/PE5

AVEC/PE2

BERR

CS1/BG

CS2/BGACK

CS0/BR

CLKOUT

CSBOOT

DATA[15:0]

DS/PE4

DSACK0/PE0

DSACK1/PE1

CS[5:3]/FC[2:0]/

PC[2:0]

HALT

IRQ[7:1]/PF[7:1]

MODCLK/PF0

R/W

RESET

RMC/PE3

SIZ[1:0]/PE[7:6]

TSTME/TSC

Pin State

While

RESET

Asserted

1

1

Default Function

Pin State

CS10

CS[9:6]

High-Z Output ADDR[18:0]

See Note 1

Inactive Input

AS

AVEC

Inactive Input

1

1

1

Output

1

Mode Select

See Note 1

Inactive Input

Inactive Input

1

Inactive Input

Inactive Input

Mode Select

High-Z Output

Asserted

See Note 1

See Note 1

Mode Select

BERR

CS1

CS2

CS0

CLKOUT

CSBOOT

DATA[15:0]

DS

DSACK0

DSACK1

CS[5:3]

HALT

Pin State After RESET Released

Pin Function

1

1

Unknown

Output

Input

Input

1

1

1

Output

0

Input

Output

Input

Input

1

Input

IRQ[7:1] Input

MODCLK Input

R/W

RESET

RMC

SIZ[1:0]

TSC

Output

Input

Output

Unknown

Input

Alternate Function

Pin State

ADDR23

ADDR[22:19]

ADDR[18:0]

PE5

PE2

BERR

BG

BGACK

BR

CLKOUT

CSBOOT

DATA[15:0]

PE4

PE0

PE1

FC[2:0]

HALT

PF[7:1]

PF0

R/W

RESET

PE3

PE[7:6]

TSC

Pin Function

Unknown

Unknown

Unknown

Input

Input

Input

1

Input

Input

Output

0

Input

Input

Input

Input

Unknown

Input

Input

Input

Output

Input

Input

Input

Input

NOTES:

1. The state of these bus control/port E pins during reset depends on the state of DATA8. If DATA8 is high during reset (the default), these pins are driven high during reset and come out of reset as bus control outputs. If DATA8 is held low during reset, these pins are inactive, high-impedance inputs during reset and come out of reset as port

E inputs.

MOTOROLA

8-12

RESET AND SYSTEM INITIALIZATION

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

8.8 SIM Registers Out of Reset

Table 8-4 summarizes the reset values of bits and fields in the SIM registers. Bits not

included in the table are unimplemented and have reset values of zero.

Register

SIMCR

SYPCR

SYNCR

PICR

PITR

PORTE

DDRE

PEPAR

PORTF

DDRF

PFPAR

PORTC

CSPAR1

CSPAR0

CSBARBT

CSBAR[10:0]

6:0

9:0

13:0

15:3

2:0

15:3

2:0

7:0

7:0

7:0

7:0

7:0

7:0

7:0

3:0

7

6

5:4

3

2

1:0

15:8

Bits

15

14

13

11

9:8

7

6

1

0

10:8

7:0

8

3

2

7

4

Table 8-4 SIM Registers Out of Reset

IARB

SWE

SWP

SWT

HME

BME

BMT

W,X,Y

Name

EXOFF

FRZSW

FRZBM

SLVEN

SHEN

SUPV

MM

EDIV

SLIMP

SLOCK

RSTEN

STSIM

STEXT

PIRQL

PIV

PTP

PITM

PE

DDE

PEPA

PF

DDF

PFPA

PC

Value

0

1

1

Meaning

CLKOUT enabled

Disable watchdog and PIT when FREEZE asserted

Disable bus monitor when FREEZE asserted

DATA11 Slave mode enabled if DATA11 low

00 Show cycles disabled

1

1

Supervisor access only

Module registers begin at $FFF000

1111

1

SIM interrupts have highest priority

Software watchdog enabled

MODCLK Software watchdog prescaled by 512 if MODCLK low

00 Software watchdog time-out set to minimum

0

0

Disable halt monitor

Disable internal-to-external bus monitor

00 Bus monitor time-out = 64 system clocks

00111111 System clock frequency = Source frequency

∑

256

0 ECLK = System clock

≥

8

Unchanged Limp mode flag unaffected by reset

Unchanged Synthesizer lock flag unaffected by reset

0 Loss of crystal causes limp mode (not reset)

0

0

If LPSTOP, disable system clock

If LPSTOP, disable external clock

000 Periodic interrupt disabled

00001111 Vector number = $F (uninitialized interrupt vector)

MODCLK If MODCLK is low, PTP = 1 (PIT prescaled by 512)

If MODCLK is high, PTP = 0 (PIT not prescaled)

00000000 Periodic timer disabled

Unchanged Port E data register is unaffected by reset

00000000 Port E pins are configured for input

DATA8 If DATA8 = 0, pins configured for G/P I/O

If DATA8 = 1, pins configured for bus control

Unchanged Port F data register is unaffected by reset

00000000 Port F pins are configured for input

DATA9 If DATA9 = 0, pins configured for G/P I/O

If DATA9 = 1, pins configured for interrupt request

(MODCLK for PF0)

1111111 Port C data register bits [6:0] set to 1

See Table 7-7

$0

See Table 7-6

Base address = 0 AD-

DR[23:11]

BLKSZ

AD-

DR[23:11]

BLKSZ

111

$0

000

Block size = 1 Mbyte

Base address = 0

Block size = 2 Kbytes

SIM

REFERENCE MANUAL

RESET AND SYSTEM INITIALIZATION

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

8-13

Freescale Semiconductor, Inc.

Register

CSORBT

CSOR[10:0]

Table 8-4 SIM Registers Out of Reset (Continued)

Bits

15

14:13

12:11

10

9:6

5:4

3:1

0

Name

MODE

BYTE

R/W

STRB

DSACK

SPACE

IPL

AVEC

Value

0

11

11

0

1101

11

000

0

Meaning

Asynchronous mode

Both bytes

Assert chip select for both reads and writes

Chip select synchronized with AS

13 wait states

Supervisor/user space

Assert chip select on any level interrupt

Autovector disabled

Disabled (BYTE field = 0)

8.9 System Initialization

During system initialization, a hardware initialization sequence occurs. Following hardware initialization, the MCU performs the initialization routine fetched from the exception vector table. This initialization routine normally defines constants, addresses, and other data values needed by the program.

The following steps summarize procedures for initializing the SIM. Initialize the SIM before initializing other MCU modules.

1. Program the SIMCR to set the SIM arbitration level, base address of the module registers, and privilege level of assignable SIM registers, and to enable or disable the external clock, the software watchdog and bus monitor, and show cycles.

2. Program the SYNCR to set the system clock frequency, ECLK divide rate, to enable or disable loss-of-crystal reset, and to assign STOP mode clock operation.

3. Program the SYPCR to enable or disable the software watchdog, halt monitor, and bus monitor, and to assign the timing for the software watchdog and bus monitor.

4. Program the PICR and PITR to set the periodic interrupt request level and establish the timing for the periodic timer.

5. Program the chip-select pin assignment, base address, and options registers to assign pin function, initialize chip selects, and assign base addresses and options.

6. Initialize the port E and port F data registers. Then program the port E and port

F data direction and pin assignment registers, if necessary, to change the reset values. (Initializing the data registers first guarantees that the desired logic level is output on the pins that are configured as outputs.)

MOTOROLA

8-14

RESET AND SYSTEM INITIALIZATION

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

SECTION 9GENERAL-PURPOSE I/O

Sixteen of the SIM pins can be configured for general-purpose discrete input and output. Although these pins are organized into two ports, port E and port F, function assignment is by individual pin. Pin assignment registers, data direction registers, and data registers are used to implement discrete I/O.

In addition to the sixteen pins in ports E and F, the seven pins in port C can be config-

ured as discrete outputs. Port C is discussed in SECTION 7 CHIP SELECTS. The fol-

lowing paragraphs describe ports E and F.

NOTE

On MCUs with a reduced pin-count SIM, some of the pins that comprise ports E and F may not be available. Refer to the user's manual for the particular MCU for a list of the pins on the chip.

9.1 Pin Assignment Registers

Bits in the port E and port F pin assignment registers (PEPAR and PFPAR) control the functions of the pins in each port. Any bit cleared to zero defines the corresponding pin to be an I/O pin. Any bit set to one configures the corresponding pin for its alternate function.

NOTE

On CPU16-based MCUs, the RMC signal is not implemented, and the RMC/PE3 pin may be left unconnected. When the pin is left unconnected, PEPA3 always returns one when read, and writes have no effect.

The states of the DATA8 and DATA9 pins control the reset state of PEPAR and PF-

PAR, respectively. When DATA8 is high during reset, PEPAR is set to $FF, defining all port E pins to be bus control signals. When DATA8 is low during reset, PEPAR is set to $00, defining all port E pins to be I/O pins. In a similar fashion, DATA9 determines the reset state of PFPAR.

PEPAR — Port E Pin Assignment Register

15 14 13 12

NOT USED

11 10 9 8

RESET:

$####16

7 6 5 4 3 2 1 0

PEPA7 PEPA6 PEPA5 PEPA4 PEPA3 PEPA2 PEPA1 PEPA0

DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8

Any bit cleared to zero defines the corresponding pin to be an I/O pin. Any bit set to one defines the corresponding pin to be a bus control signal.

SIM

REFERENCE MANUAL

GENERAL-PURPOSE I/O

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

9-1

Freescale Semiconductor, Inc.

Table 9-1 Port E Pin Assignments

PEPAR Bit

PEPA7

PEPA6

PEPA5

PEPA4

PEPA3

PEPA2

PEPA1

PEPA0

Port E Signal

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

Bus Control Signal

SIZ1

SIZ0

AS

DS

RMC*

AVEC

DSACK1

DSACK0

*On CPU16-based MCUs, when PEPA3 is set, the PE3 pin, if connected, goes to logic level one. The CPU16 does not support the RMC function for this pin.

PFPAR — Port F Pin Assignment Register

15 14 13 12

NOT USED

11 10 9 8

RESET:

$####1E

7 6 5 4 3 2 1 0

PFPA7 PFPA6 PFPA5 PFPA4 PFPA3 PFPA2 PFPA1 PFPA0

DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 DATA9

Any bit cleared to zero defines the corresponding pin to be an I/O pin. Any bit set to one defines the corresponding pin to be an interrupt request signal or MODCLK.

Table 9-2 Port F Pin Assignments

PFPAR Field

PFPA7

PFPA6

PFPA5

PFPA4

PFPA3

PFPA2

PFPA1

PFPA0

Port F Signal

PF7

PF6

PF5

PF4

PF3

PF2

PF1

PF0

Alternate Signal

IRQ7

IRQ6

IRQ5

IRQ4

IRQ3

IRQ2

IRQ1

MODCLK

9.2 Data Direction Registers

Bits in the port E and port F data direction registers (DDRE and DDRF) control the direction of the pin drivers when the pins are configured for I/O. Any bit in a register set to one configures the corresponding pin as an output. Any bit in a register cleared to zero configures the corresponding pin as an input. These registers can be read or written at any time. In MCUs in which the RMC pin is not implemented, DDE3 always returns one when read, and writes have no effect.

MOTOROLA

9-2

GENERAL-PURPOSE I/O

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

DDRE — Port E Data Direction Register

15 14 13 12

NOT USED

11 10 9

RESET:

8

$####14

7 6 5 4 3 2 1 0

DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0

DDRF — Port F Data Direction Register

15 14 13 12

NOT USED

11 10 9

RESET:

8

0 0 0 0 0 0 0 0

$####1C

7 6 5 4 3 2 1 0

DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0

0 0 0 0 0 0 0 0

9.3 Data Registers

A write to the port E and port F data registers (PORTE and PORTF) is stored in an internal data latch, and if any pin in the corresponding port is configured as an output, the value stored for that bit is driven out on the pin. A read of a data register returns the value at the pin only if the pin is configured as a discrete input. Otherwise, the value read is the value stored in the register. Both data registers can be accessed in two locations. They can be read or written at any time.

PORTE and PORTF are unaffected by reset.

PORTE0, PORTE1 — Port E Data Register

15 14 13 12

NOT USED

11 10 9 8

RESET:

7

PE7

U

6

PE6

5

PE5

4

PE4

$####10, $####12

3

PE3

2

PE2

1

PE1

U U U U U U

NOTE

On CPU16-based MCUs, the RMC signal is not implemented, and

PE3 may not be connected to a pin. On CPU16-based MCUs, the value read from PE3 depends on the particular MCU. Refer to the appropriate MCU user's manual. Writes to PE3 have no effect when the

RMC/PE3 pin is not available.

0

PE0

U

PORTF0, PORTF1 — Port F Data Register

15 14 13 12

NOT USED

11 10 9 8

RESET:

7

PF7

6

PF6

5

PF5

U U U

4

PF4

$####18, $####1A

3

PF3

2

PF2

1

PF1

0

PF0

U U U U U

SIM

REFERENCE MANUAL

GENERAL-PURPOSE I/O

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

9-3

Freescale Semiconductor, Inc.

MOTOROLA

9-4

GENERAL-PURPOSE I/O

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

SECTION 10 REDUCED PIN-COUNT SIM

Some Motorola MCUs contain a version of the SIM with a reduced pin count. MCUs with a reduced pin-count SIM (RPSIM) always contain the SIM pins that are most basic to MCU operation; some SIM pins, however, are not included on these chips. The set of pins that are not connected depends on the MCU, but it is always a subset of the pins listed in this section. This section lists the pins that may be omitted from RPSIMbased MCUs and discusses how the omission of these pins affects SIM operation.

10.1 Optional RPSIM Pins

Table 10-1 lists the pins that are optionally not included on MCUs with a reduced pin-

count SIM. RPSIM-based MCUs may still have some of these pins available, depending on the requirements of the particular microcontroller. Refer to the user's manual for the specific MCU for a list of the pins on a given chip.

Table 10-1 Optional RPSIM Pins

Description Pin

Mnemonic

ADDR[22:20]/CS[9:7]

AVEC

CSBOOT

DSACK0

HALT

IRQ[5:1]

RMC

Address Bus/Chip Selects

Autovector

Boot Chip Select

Data and Size Acknowledge

Halt

Interrupt Request Level

Read-Modify-Write Cycle

Port

Designation

PC[6:4]

PE2

—

PE0

—

PF[5:1]

PE3

10.2 Address Bus/Chip Select Pins

Up to three address bus/chip select pins (ADDR[22:20]/CS[9:7]/PC[6:4]) are optionally not included on MCUs with a reduced pin-count SIM. On MCUs that lack these pins,

ADDR[22:20] follow the logic level of ADDR19, and the chip-select and discrete output functions for these pins are unavailable.

10.3 Data Size and Acknowledge Pins

On MCUs with both DSACK[1:0] pins, an external device asserts the appropriate

DSACK signal to indicate port size and the availability of data. On some MCUs with a reduced pin-count SIM, no DSACK0 pin is provided. With these MCUs, an external device indicates the availability of data by asserting DSACK1, regardless of port size. All accesses thus appear to be word accesses.

When connecting an 8-bit device with an 8-bit port to an MCU with no DSACK0 pin, connect the peripheral to DATA[15:8] as usual. The peripheral asserts DSACK1, rather than DSACK0, to indicate completion of the cycle, and the read or write operation terminates after the first bus cycle.

SIM

REFERENCE MANUAL

REDUCED PIN-COUNT SIM

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

10-1

Freescale Semiconductor, Inc.

Connecting an 8-bit device with a 16-bit port (e.g., a 16-bit timer) to an MCU with no

DSACK0 pin requires one of the following work-arounds.

For CPU16-based products, connect the peripheral to DATA[15:8]. Use long word load and store instructions (LDED and STED) and arrange the upper bytes of accumulators E and D into a word.

For CPU32-based products, use the MOVEP (move peripheral data) instruction to move data to and from even addresses. Refer to the CPU32 reference manual for details.

10.4 RMC Pin

The CPU32 asserts the RMC signal to indicate that the current bus cycle is part of an indivisible read-modify-write instruction. The CPU16 does not support this signal. On

CPU16-based MCUs, the pin may or may not be available for discrete I/O (PE3). If the pin is not available, a read of PE3 will always return either zero or one, depending on the particular MCU. Refer to the user's manual for the particular CPU16-based MCU to determine how PE3 is implemented.

MOTOROLA

10-2

REDUCED PIN-COUNT SIM

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

APPENDIX AELECTRICAL CHARACTERISTICS

Table A-1 Clock Control Timing

(V

DD

and V

DDSYN

= 5.0 Vdc

±

10%, V

SS

= 0 Vdc

32.768 kHz or 4.194 MHz reference)

Characteristic

PLL Reference Frequency Range

System Frequency

1

On-Chip PLL System Frequency

External Clock Operation

PLL Lock Time

2

Limp Mode Clock Frequency

3

SYNCR X bit = 0

SYNCR X bit = 1

CLKOUT Stability

4, 5

Short term

Long term

Symbol f f f t ref sys lpll limp

Min

25 dc

0.131

dc

—

—

— f f

Max sys

50

16.78

16.78

16.78

20 max/2 sys max

Unit kHz

MHz ms

MHz

C stab

–1.0

–0.5

1.0

0.5

%

NOTES:

1. All internal registers retain data at 0 Hz.

2. Assumes that stable V

DDSYN is applied, that an external filter capacitor with a value of 0.1

µ

F is attached to the

XFC pin, and that the crystal oscillator is stable.

Lock time is measured from power-up to RESET release. This specification also applies to the period required for PLL lock after changing the W and Y frequency control bits in the synthesizer control register (SYNCR) while the PLL is running, and to the period required for the clock to lock after LPSTOP.

3. Determined by the internal reference voltage applied to the on-chip VCO. The X bit in SYNCR controls a divide by two prescaler on the system clock output.

4. Short-term CLKOUT stability is the average deviation from programmed frequency measured over a 2

µ s interval at maximum f sys

. Long-term CLKOUT stability is the average deviation from programmed frequency measured over a 1 ms interval at maximum f sys

. Stability is measured with a stable external clock input applied — variation in crystal oscillator frequency is additive to this figure.

5. This parameter is periodically sampled rather than 100% tested.

SIM

REFERENCE MANUAL

ELECTRICAL CHARACTERISTICS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

A-1

Freescale Semiconductor, Inc.

Table A-2 DC Characteristics

(V

DD

and V

DDSYN

= 5.0 Vdc

±

10%, V

SS

= 0 Vdc

Characteristic Symbol

Input High Voltage

Input Low Voltage

Input Hysteresis

1

Input Leakage Current

2

V in

= V

DD or V

SS

High Impedance (Off-State) Leakage Current

2

Input-only pins

= V

DD

or V

SS

CMOS Output High Voltage

2, 3

I

V in

OH

= –10.0

µ

A

All input/output and output pins

Group 1, 2 input/output and all output pins

CMOS Output Low Voltage

2

I

OL

= 10.0

µ

A

Output High Voltage

2, 3

Group 1, 2 input/output and all output pins

Group 1, 2 input/output and all output pins I

OH

= –0.8 mA

Output Low Voltage

2

I

I

OL

I

OL

OL

= 1.6 mA

= 5.3 mA

= 12 mA

Group 1 I/O Pins, CLKOUT, FREEZE/QUOT

Group 2 I/O Pins, CSBOOT, BG/CS

Group 3

V

V

IH

I

V

V

V

V

V

I

IL

HYS in

OZ

OH

OL

OH

OL

Three State Control Input High Voltage V

IHTSC

Data Bus Mode Select Pull-up Current

5

V in

V in

= V

IL

= V

IH

V

DD

Supply Current

6

RUN

4

DATA[15:0]

DATA[15:0]

LPSTOP, 32.768 kHz or 4.194 MHz crystal, VCO Off (STSIM = 0)

LPSTOP (External clock input frequency = maximum f sys

)

I

MSP

I

DD

S

IDD

S

IDD

Clock Synthesizer Operating Voltage V

DDSYN

V

DDSYN

Supply Current

6

32.768 kHz or 4.194 MHz crystal, VCO on, maximum f sys

External Clock, maximum f sys

LPSTOP, 32.768 kHz or 4.194 MHz crystal, VCO off (STSIM = 0)

32.768 kHz or 4.194 MHz crystal, V

DD powered down

Power Dissipation

7

Input Capacitance

2, 8

I

I

S

I

DDSYN

DDSYN

IDDSYN

DDSYN

P

D

C in

All input-only pins

All input/output pins

Load Capacitance

2

Group 1 I/O Pins and CLKOUT, FREEZE/QUOT

Group 2 I/O Pins and CSBOOT, BG/CS

Group 3 I/O pins

C

L

Min Max

0.7

(

V

DD

) V

DD

+ 0.3

V

SS

– 0.3

0.2

(

V

DD

)

0.5

—

–2.5

2.5

–2.5

V

DD

– 0.2

—

V

DD

– 0.8

—

—

—

1.6 (V

DD

)

—

–15

—

—

—

—

—

—

—

—

—

—

4.5

—

—

—

2.5

—

0.2

—

0.4

0.4

0.4

9.1

–120

—

124

350

5

5.5

1

5

150

100

690

10

20

90

100

130

V

µ

A mA mA

µ

A

µ

A mW pF

Unit

V

V

V

µ

A

µ

A

V

V

V

V mA

µ

A mA

V pF

MOTOROLA

A-2

ELECTRICAL CHARACTERISTICS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

NOTES:

1. Applies to:

Port D [7:0]

Port E [7:3]

Port F [7:0]

TSTME/TSC, BKPT, RESET

2. Input-Only Pins:TSTME/TSC, BKPT

Output-Only Pins: CSBOOT, BG/CS, CLKOUT, FREEZE/QUOT

Input/Output Pins:

Group 1: DATA[15:0]

Group 2: Port C (ADDR23/ECLK, ADDR[22:19]/CS[9:6], FC[2:0]/CS[5:3])

Port E (DSACK[1:0], AVEC, RMC, DS, AS, SIZ[1:0])

Port F (IRQ[7:1], MODCLK)

Group 3: HALT, RESET

3. Does not apply to HALT and RESET because they are open drain pins.

4. Current measured at system clock frequency of 16.78 MHz.

5. Use of an active pulldown device is recommended.

6. Total operating current is the sum of the appropriate V

DD

supply and V

DDSYN supply current.

7. Power dissipation measured with system clock frequency of 16.78 MHz. Power dissipation is calculated using the following expression:

P

D

= Maximum V

DD

(

I

DDSYN

+ I

DD

)

8. Input capacitance is periodically sampled rather than 100% tested.

SIM

REFERENCE MANUAL

ELECTRICAL CHARACTERISTICS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

A-3

Freescale Semiconductor, Inc.

Table A-3 AC Timing

(V

DD

and V

DDSYN

= 5.0 Vdc

±

10%, V

SS

= 0 Vdc)

Num

F1

2

Characteristic

Frequency of Operation (32.768 kHz or 4.194 MHz crystal)

1

1A

1B

3

Clock Period

ECLK Period

External Clock Input Period

2, 3 Clock Pulse Width

2A, 3A ECLK Pulse Width

2B, 3B

3

External Clock Input High/Low Time

4, 5 Clock Rise and Fall Time

4A, 5A Rise and Fall Time — All Outputs except CLKOUT

4B, 5B External Clock Rise and Fall Time

6

14

Clock High to Address, FC, SIZE, RMC Valid

7

14

8

14

Clock High to Address, Data, FC, SIZE, RMC High Impedance

Clock High to Address, FC, SIZE, RMC Invalid

9

9A

4

11

14

Clock Low to AS, DS, CS Asserted

AS to DS or CS Asserted (Read)

Address, FC, SIZE, RMC Valid to AS, CS Asserted

12

13

Clock Low to AS, DS, CS Negated

AS, DS, CS Negated to

Address, FC, SIZE Invalid (Address Hold)

16

17

18

20

14 AS, CS Width Asserted

14A DS, CS Width Asserted (Write)

14B AS, CS Width Asserted (Fast Write Cycle)

15

5

AS, DS, CS Width Negated

Clock High to AS, DS, R/W High Impedance

AS, DS, CS Negated to R/W High

Clock High to R/W High

Clock High to R/W Low

21

22

23

24

28

29

6

29A

6, 7

30

6

30A

6

31

8

33

35

9,14

R/W High to AS, CS Asserted

R/W Low to DS, CS Asserted (Write)

Clock High to Data Out Valid

Data Out Valid to Negating Edge of AS, CS

25

26

DS, CS Negated to Data Out Invalid (Data Out Hold)

Data Out Valid to DS, CS Asserted (Write)

27 Data In Valid to Clock Low (Data Setup)

27A Late BERR, HALT Asserted to Clock Low (Setup Time)

AS, DS Negated to DSACK, BERR, HALT, AVEC Negated

DS, CS Negated to Data In Invalid (Data In Hold)

DS, CS Negated to Data In High Impedance

CLKOUT Low to Data In Invalid (Fast Cycle Hold)

CLKOUT Low to Data In High Impedance

DSACK Asserted to Data In Valid

Clock Low to BG Asserted/Negated

BR Asserted to BG Asserted (RMC Not Asserted)

37

39

BGACK Asserted to BG Negated

BG Width Negated

39A BG Width Asserted

46 R/W Width Asserted (Write or Read)

46A R/W Width Asserted (Fast Write or Read Cycle)

Symbol f t

XCrf t

CHAV t

CHAZx t

CHAZn t

CLSA t

STSA t

AVSA t cyc t

Ecyc t

Xcyc t

CW t

ECW t

XCHL t

Crf t rf t

CLSN t

SNAI t

SNDN t

SNDI t

SHDI t

CLDI t

CLDH t

DADI t

CLBAN t

BRAGA t

GAGN t

GH t

GA t

RWA t

RWAS t

RAAA t

RASA t

CHDO t

DVASN t

SNDOI t

DVSA t

DICL t

BELCL t

SWA t

SWAW t

SWDW t

SN t

CHSZ t

SNRN t

CHRH t

CHRL

0

0

2

–15

15

—

—

—

0

Min

0.13

59.6

476

59.6

24

236

29.8

2

15

—

—

—

1

0

0

—

15

1

2

1

150

90

15

15

5

20

15

70

—

15

—

15

0

0

100

45

40

40

59

—

25

15

—

5

8

5

29

Max Unit

16.78

MHz

—

— ns ns

—

—

—

— ns ns ns ns ns ns ns ns ns ns ns ns ns

29

— ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t cyc t cyc t cyc t cyc ns ns ns ns ns ns

90

50

29

—

80

—

55

—

2

—

—

—

—

—

—

—

—

—

—

29

—

59

—

29

29

—

—

—

—

MOTOROLA

A-4

ELECTRICAL CHARACTERISTICS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

Table A-3 AC Timing

(V

DD

and V

DDSYN

= 5.0 Vdc

±

10%, V

SS

= 0 Vdc)

73

74

75

76

57

70

71

72

77

78

47A Asynchronous Input Setup Time

BR, BGACK, DSACK, BERR, AVEC, HALT

47B Asynchronous Input Hold Time

48

10

DSACK Asserted to BERR, HALT Asserted

53

54

55

56

Data Out Hold from Clock High

Clock High to Data Out High Impedance

R/W Asserted to Data Bus Impedance Change

RESET Pulse Width (Reset Instruction)

BERR Negated to HALT Negated (Rerun)

Clock Low to Data Bus Driven (Show)

Data Setup Time to Clock Low (Show)

Data Hold from Clock Low (Show)

BKPT Input Setup Time

BKPT Input Hold Time

Mode Select Setup Time

Mode Select Hold Time

RESET Assertion Time

11

RESET Rise Time

12 t

AIST t

SCLDS t

SCLDH t

BKST t

BKHT t

MSS t

MSH t

RSTA t

RSTR t

AIHT t

DABA t

DOCH t

CHDH t

RADC t

HRPW t

BNHN t

SCLDD

5

15

—

0

—

40

512

0

0

15

10

15

10

20 —

0

4

—

—

—

30

—

28

—

—

—

29

—

—

—

—

—

—

10 ns

NOTES:

1. All AC timing is shown with respect to 20% V

DD

and 70% V

DD

levels unless otherwise noted.

2. Minimum system clock frequency is four times the crystal frequency, subject to specified limits.

3. Minimum external clock high and low times are based on a 50% duty cycle. The minimum allowable t

XCYC

period will be reduced when the duty cycle of the external clock signal varies. The relationship between external clock input duty cycle and minimum t

XCYC

is expressed:

Minimum t

XCYC

period = minimum t

XCHL

/ (50% – external clock input duty cycle tolerance).

To achieve maximum operating frequency (f sys

) while using an external clock input, adjust clock input duty cycle to obtain a 50% duty cycle on CLKOUT.

4. Specification 9A is the worst-case skew between AS and DS or CS. The amount of skew depends on the relative loading of these signals. When loads are kept within specified limits, skew will not cause AS and DS to fall outside the limits shown in specification 9.

5. If multiple chip selects are used, CS width negated (specification 15) applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select. The CS width negated specification between multiple chip selects does not apply to chip selects being used for synchronous ECLK cycles.

6. These hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast cycle reads. The user is free to use either hold time.

7. Maximum value is equal to (t cyc

/ 2) + 25 ns.

8. If the asynchronous setup time (specification 47A) requirements are satisfied, the DSACK low to data setup time

(specification 31) and DSACK low to BERR low setup time (specification 48) can be ignored. The data must only satisfy the data-in to clock low setup time (specification 27) for the following clock cycle. BERR must satisfy only the late BERR low to clock low setup time (specification 27A) for the following clock cycle.

9. To ensure coherency during every operand transfer, BG will not be asserted in response to BR until after all cycles of the current operand transfer are complete and RMC is negated.

10. In the absence of DSACK, BERR is an asynchronous input using the asynchronous setup time (specification 47A).

11. After external RESET negation is detected, a short transition period (approximately 2 t cyc drives low for 512 t cyc

.

) elapses, then the SIM

12. External logic must pull RESET high during this period in order for normal MCU operation to begin.

13. Address access time = (2.5 + WS) t cyc

– t

CHAV

– t

DICL

Chip select access time = (2 + WS) t cyc

– t

CLSA

– t

DICL

Where: WS = number of wait states. When fast termination is used (2 clock bus) WS = –1.

14. RMC signal is not supported on CPU16-based MCUs.

ns t cyc ns t cyc t cyc ns ns ns ns ns ns ns ns ns t cyc ns

SIM

REFERENCE MANUAL

ELECTRICAL CHARACTERISTICS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

A-5

Freescale Semiconductor, Inc.

Table A-4 ECLK Bus Timing

(V

DD

= 5.0 Vdc

±

10%, V

SS

= 0 Vdc)

Num

E1

E2

E3

E4

E5

E6

E7

E8

E9

2

E10

E11

E12

E15

4

E16

ECLK Low to Address Valid

ECLK Low to Address Hold

ECLK Low to CS Valid (CS delay)

ECLK Low to CS Hold

CS Negated Width

Read Data Setup Time

Read Data Hold Time

ECLK Low to Data High Impedance

CS Negated to Data Hold (Read)

CS Negated to Data High Impedance

ECLK Low to Data Valid (Write)

ECLK Low to Data Hold (Write)

E13 CS Negated to Data Hold (Write)

E14

3

Address Access Time (Read)

Chip Select Access Time (Read)

Address Setup Time

Characteristic Symbol t

ECDH t

ECDZ t

EDDW t

EDHW t

ECHW t

EACC t

EACS t

EAS t

EAD t

EAH t

ECSD t

ECSH t

ECSN t

EDSR t

EDHR t

EDHZ

Min

—

10

—

15

100

30

15

—

0

—

—

5

0

386

326

—

—

—

—

—

1/2

115

—

1

2

—

—

—

—

Max

60

—

120

NOTES:

1. All AC timing is shown with respect to 20% V

DD

and 70% V

DD

levels unless otherwise noted.

2. When the previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low.

3. Address access time = t

Ecyc

– t

EAD

– t

EDSR

4. Chip select access time = t

Ecyc

– t

ECSD

– t

EDSR ns ns t cyc t cyc ns ns ns ns t cyc ns ns ns ns

Unit ns ns ns

MOTOROLA

A-6

ELECTRICAL CHARACTERISTICS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

4 2

CLKOUT

5

NOTE: Timing shown with respect to 20% and 70% VDD.

1

3

Figure A-1 CLKOUT Output Timing Diagram

68300 CLKOUT TIM

1B

4B 2B

EXTAL

5B

NOTE: Timing shown with respect to 20% and 70% VDD.

Pulse width shown with respect to 50% VDD.

3B

Figure A-2 External Clock Input Timing Diagram

68300 EXT CLK INPUT TIM

4A 2A

ECLK

5A

NOTE: Timing shown with respect to 20% and 70% VDD.

1A

3A

Figure A-3 ECLK Output Timing Diagram

68300 ECLK OUTPUT TIM

SIM

REFERENCE MANUAL

ELECTRICAL CHARACTERISTICS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

A-7

Freescale Semiconductor, Inc.

Table A-5 Key to Figures A-1, A-2, A-3

(Abstracted from Table A-3; see table for complete notes)

Num

1 Clock Period

Characteristic

1A ECLK Period

1B

3

External Clock Input Period

2, 3 Clock Pulse Width

2A, 3A ECLK Pulse Width

2B,3B

3

External Clock Input High/Low Time

4, 5 Clock Rise and Fall Time

4A, 5A ECLK Rise and Fall Time

4B, 5B External Clock Rise and Fall Time

Symbol t cyc t

Ecyc t

Xcyc t

CW t

ECW t

XCHL t

Crf t

Erf t

XCrf

Min

59.6

476

59.6

24

236

29.8

—

—

—

Max Units

— ns

—

—

—

—

—

5

8

5 ns ns ns ns ns ns ns ns

NOTES:

1. All AC timing is shown with respect to 20% V

DD

and 70% V

DD

levels unless otherwise noted.

3. Minimum external clock high and low times are based on a 50% duty cycle. The minimum allowable t

XCYC

period will be reduced when the duty cycle of the external clock signal varies. The relationship between external clock input duty cycle and minimum t

XCYC

is expressed:

Minimum t

XCYC

period = minimum t

XCHL

/ (50% – external clock input duty cycle tolerance).

To achieve maximum operating frequency (f sys to obtain a 50% duty cycle on CLKOUT.

) while using an external clock input, adjust clock input duty cycle

MOTOROLA

A-8

ELECTRICAL CHARACTERISTICS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

S0 S1 S2 S3 S4 S5

CLKOUT

ADDR[23:20]

FC[2:0]

SIZ[1:0]

AS

11

9

DS

CS

18

R/W

9A

6

21

14

12

8

DSACK0

DSACK1

DATA[15:0]

31

27

46

47A

BERR

HALT

48

73

27A

BKPT

ASYNCHRONOUS

INPUTS

47A

47B

74

28

29

29A

20

15

13

SIM RD CYC TIM

Figure A-4 Read Cycle Timing Diagram

SIM

REFERENCE MANUAL

ELECTRICAL CHARACTERISTICS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

A-9

Freescale Semiconductor, Inc.

Table A-6 Key to Figure A-4

(Abstracted from Table A-3; see table for complete notes)

Num

6

14

8

14

9

9A

4

11

14

Characteristic

Clock High to Address, FC, SIZE, RMC Valid

Clock High to Address, FC, SIZE, RMC Invalid

Clock Low to AS, DS, CS Asserted

AS to DS or CS Asserted (Read)

A

DD

R, FC, SIZ, RMC Valid to AS, CS Asserted

12 Clock Low to AS, DS, CS Negated

13 AS, DS, CS Negated to Address, FC, SIZE Invalid

(Address Hold)

Symbol t

CHAV t

CHAZn t t

CLSA t

STSA t

AVSA t

CLSN

SNAI

14

15

18

20

5

AS, CS Width Asserted

AS, DS, CS Width Negated

Clock High to R/W High

Clock High to R/W Low t

SWA t

SN t

CHRH t

CHRL

21

27

R/W High to AS, CS Asserted

Data In Valid to Clock Low (Data Setup) t

RAAA t

DICL

27A

47A

Late BERR, HALT Asserted to Clock Low (Setup Time)

Asynchronous Input Setup Time

BR, BGACK, DSACK, BERR, AVEC, HALT t

BELCL

28 AS, DS Negated to DSACK, BERR, HALT, AVEC Negated t

SNDN

29

6

DS, CS Negated to Data In Invalid (Data In Hold) t

SNDI

29A

6, 7

DS, CS Negated to Data In High Impedance t

SHDI

31

8

DSACK Asserted to Data In Valid t

DADI

46 R/W Width Asserted (Write or Read) t

RWA t

AIST

47B

48

10

73

74

Asynchronous Input Hold Time

DSACK Asserted to BERR, HALT Asserted

BKPT Input Setup Time

BKPT Input Hold Time t

AIHT t

DABA t

BKST t

BKHT

NOTES:

Min

0

0

2

–15

15

2

15

100

40

0

0

15

5

20

0

0

—

—

150

5

15

—

15

10

Max Units

29

—

25

15

—

29

—

—

—

29

29

—

—

—

80

—

55

50

—

—

—

30

—

— ns ns ns ns ns ns ns ns ns ns ns

1. All AC timing is shown with respect to 20% V

DD

and 70% V

DD

levels unless otherwise noted.

4. This is the worst-case skew between AS and DS or CS. The amount of skew depends on the relative loading of these signals. When loads are kept within specified limits, skew will not cause AS and DS to fall outside the limits shown in specification 9. ns ns ns ns ns ns ns ns ns ns ns ns ns

5. If multiple chip selects are used, CS width negated (#15) applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select. The CS width negated specification between multiple chip selects does not apply to chip selects used for ECLK cycles.

6. These hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on synchronous reads. The user is free to use either hold time.

7. Maximum value is equal to (t cyc

/ 2) + 25 ns.

8. If the asynchronous setup time (#47A) requirements are satisfied, the DSACK low to data setup time (#31) and

DSACK low to BERR low setup time (#48) can be ignored. The data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle. BERR must satisfy only the late

BERR low to clock low setup time (#27A) for the following clock cycle.

10. In the absence of DSACK, BERR is an asynchronous input using the asynchronous setup time (47A).

14. RMC signal is not supported on CPU16-based MCUs.

MOTOROLA

A-10

ELECTRICAL CHARACTERISTICS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

CLKOUT

ADDR[23:20]

FC[2:0]

S0 S1 S2 S3 S4 S5

6 8

DSACK0

DSACK1

DATA[15:0]

BERR

HALT

BKPT

SIZ[1:0]

AS

DS

CS

20

R/W

11

9

9

14

12

55

23

22

46

47A

14A 17

48

73

26

27A

74

28

25

53

54

15

13

SIM WR CYC TIM

Figure A-5 Write Cycle Timing Diagram

SIM

REFERENCE MANUAL

ELECTRICAL CHARACTERISTICS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

A-11

Freescale Semiconductor, Inc.

Table A-7 Key to Figure A-5

(Abstracted from Table A-3; see table for complete notes)

Num

6

14

8

14

Characteristic

Clock High to Address, FC, SIZE, RMC Valid

Clock High to Address, FC, SIZE, RMC Invalid

9 Clock Low to AS, DS, CS Asserted

11

14

Address, FC, SIZE, RMC Valid to AS, CS Asserted

12 Clock Low to AS, DS, CS Negated

Symbol t

CHAV t

CHAZn t

CLSA t

AVSA

13 AS, DS, CS Negated to Address, FC, SIZE Invalid

(Address Hold) t

CLSN t

SNAI

14

14A

15

17

20

22

23

25

5

AS, CS Width Asserted

DS, CS Width Asserted Write

AS, DS, CS Width Negated

AS, DS, CS Negated to R/W High

Clock High to R/W Low

R/W Low to DS, CS Asserted (Write)

Clock High to Data Out Valid

DS, CS Negated to Data Out Invalid (Data Out Hold)

26

27A

Data Out Valid to DS, CS Asserted (Write)

Late BERR, HALT Asserted to Clock Low (Setup Time)

28 AS, DS Negated to DSACK, BERR, HALT, AVEC Negated t

SNDN

46 R/W Width Asserted (Write or Read) t

RWA

47A

48

10

53

Asynchronous Input Setup Time

BR, BGACK, DSACK, BERR, AVEC, HALT

DSACK Asserted to BERR, HALT Asserted

Data Out Hold from Clock High t

DVSA t

BELCL t t

AIST

DABA t

DOCH

54 Clock High to Data Out High Impedance

73

74

BKPT Input Setup Time

BKPT Input Hold Time t

CHDH t

BKST t

BKHT t

SWA t

SWAW t

SN t

SNRN t

CHRL t

RASA t

CHDO t

SNDOI

Min

0

0

2

15

2

15

100

45

40

15

0

70

—

15

15

20

0

150

5

—

0

—

15

10

Max Units

29

—

25

—

29

—

—

—

—

—

29

—

29

—

—

—

80

—

—

30

—

28

—

— ns ns ns ns ns ns ns ns ns ns ns

NOTES:

1. All AC timing is shown with respect to 20% V

DD

and 70% V

DD

levels unless otherwise noted.

5. If multiple chip selects are used, CS width negated (specification 15) applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select. The CS width negated specification between multiple chip selects does not apply to chip selects being used for synchronous ECLK cycles.

10. In the absence of DSACK, BERR is an asynchronous input using the asynchronous setup time (specification

47A).

14. RMC signal is not supported on CPU16-based MCUs.

ns ns ns ns ns ns ns ns ns ns ns ns ns

MOTOROLA

A-12

ELECTRICAL CHARACTERISTICS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

S0 S41 S42 S43 S0 S1 S2

CLKOUT

6 8

ADDR[23:0]

18

R/W

20

AS

12

9 15

DS

71

70 72

DATA[15:0]

73

74

BKPT

SHOW CYCLE

START OF

EXTERNAL CYCLE

68300 SHW CYC TIM

Figure A-6 Show Cycle Timing Diagram

Table A-8 Key to Figure A-6

(Abstracted from Table A-3; see table for complete notes)

Num

6

8

14

14

9

Characteristic

Clock High to Address, FC, SIZE, RMC Valid

Clock High to Address, FC, SIZE, RMC Invalid

Clock Low to AS, DS, CS Asserted

12 Clock Low to AS, DS, CS Negated

15

5

AS, DS, CS Width Negated

18 Clock High to R/W High

20 Clock High to R/W Low

70 Clock Low to Data Bus Driven (Show)

71 Data Setup Time to Clock Low (Show)

72 Data Hold from Clock Low (Show)

73 BKPT Input Setup Time

74 BKPT Input Hold Time

Symbol t

CHAV t

CHAZn t

CLSA t

CLSN t

SN t

CHRH t

CHRL t

SCLDD t

SCLDS t

SCLDH t

BKST t

BKHT

Min

0

0

2

2

40

0

0

0

15

10

15

10

Max Units

29 ns

—

25

29

—

29

29

29

—

—

—

— ns ns ns ns ns ns ns ns ns ns ns

NOTES:

1. All AC timing is shown with respect to 20% V

DD

and 70% V

DD

levels unless otherwise noted.

5. If multiple chip selects are used, CS width negated (specification 15) applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select. The CS width negated specification between multiple chip selects does not apply to chip selects being used for synchronous ECLK cycles.

14. RMC signal is not supported on CPU16-based MCUs.

SIM

REFERENCE MANUAL

ELECTRICAL CHARACTERISTICS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

A-13

Freescale Semiconductor, Inc.

77 78

RESET

75

DATA[15:0]

Figure A-7 Reset and Mode Select Timing Diagram

76

68300 RST/MODE SEL TIM

Table A-9 Key to Figure A-7

(Abstracted from Table A-3; see table for complete notes)

Num

75

76

77

78

Characteristic

Mode Select Setup Time

Mode Select Hold Time

RESET Assertion Time

11

RESET Rise Time

12

Symbol t

MSS t

MSH t

RSTA t

RSTR

Min

4

—

Max Units

20 —

0 —

—

10 t cyc ns t cyc t cyc

NOTES:

1. All AC timing is shown with respect to 20% V

DD

and 70% V

DD

levels unless otherwise noted.

11. After external RESET negation is detected, a short transition period (approximately 2 t cyc

) elapses, then the SIM drives low for 512 t cyc

.

12. External logic must pull RESET high during this period in order for normal MCU operation to begin.

MOTOROLA

A-14

ELECTRICAL CHARACTERISTICS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

S0 S1 S2 S3 S4 S5 S98 A5 A5 A2

CLKOUT

ADDR[23:0]

DATA[15:0]

AS

DS

R/W

DSACK0

7

16

DSACK1

47A

BR

35 39A

BG

33 33

BGACK

37

68300 BUS ARB TIM

Figure A-8 Bus Arbitration Timing Diagram — Active Bus Case

SIM

REFERENCE MANUAL

ELECTRICAL CHARACTERISTICS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

A-15

Freescale Semiconductor, Inc.

Table A-10 Key to Figure A-8

(Abstracted from Table A-3; see table for complete notes)

Num

7

14

Characteristic

Clock High to Address, Data, FC, SIZE, RMC High

Impedance

16 Clock High to AS, DS, R/W High Impedance

33 Clock Low to BG Asserted/Negated

35

9

BR Asserted to BG Asserted (RMC Not Asserted)

37 BGACK Asserted to BG Negated

39A BG Width Asserted

47A Asynchronous Input Setup Time

BR, BGACK, DSACK, BERR, AVEC, HALT

Symbol t t t t t

CHAZx t

CHSZ

CLBA

BRAGA

GAGN t

GA

AIST

Min

0

—

—

1

1

1

5

Max

59

59

29

—

2

—

—

Units ns ns ns t cyc t cyc t cyc ns

NOTES:

1. All AC timing is shown with respect to 20% V

DD

and 70% V

DD

levels unless otherwise noted.

9. To ensure coherency during every operand transfer, BG will not be asserted in response to BR until after all cycles of the current operand transfer are complete and RMC is negated.

14. RMC signal is not supported on CPU16-based MCUs.

MOTOROLA

A-16

ELECTRICAL CHARACTERISTICS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

A0 A5 A5 A2 A3 A0

CLKOUT

ADDR[23:0]

DATA[15:0]

AS

BR

47A

BG

BGACK

35

33

47A

37

33

47A

Figure A-9 Bus Arbitration Timing Diagram — Idle Bus Case

68300 BUS ARB TIM IDLE

Table A-11 Key to Figure A-9

(Abstracted from Table A-3; see table for complete notes)

Num Characteristic

33 Clock Low to BG Asserted/Negated

35

9

BR Asserted to BG Asserted (RMC Not Asserted)

37 BGACK Asserted to BG Negated

47A Asynchronous Input Setup Time

BR, BGACK, DSACK, BERR, AVEC, HALT

Symbol t

CLBA t

BRAGA t

GAGN t

AIST

Min

—

1

1

5

Max Units

29

—

2

— ns t cyc t cyc ns

NOTES:

1. All AC timing is shown with respect to 20% V

DD

and 70% V

DD

levels unless otherwise noted.

9. To ensure coherency during every operand transfer, BG will not be asserted in response to BR until after all cycles of the current operand transfer are complete and RMC is negated.

SIM

REFERENCE MANUAL

ELECTRICAL CHARACTERISTICS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

A-17

Freescale Semiconductor, Inc.

CLKOUT

ADDR[23:0]

6

S0 S1 S4 S5 S0

8

FC[2:0]

SIZ[1:0]

AS

14B

9 12

DS

CS

20

R/W

18

27

46A

30

30A

DATA[15:0]

73

29A

29

BKPT

74

68300 FAST RD CYC TIM

Figure A-10 Fast Termination Read Cycle Timing Diagram

MOTOROLA

A-18

ELECTRICAL CHARACTERISTICS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

Table A-12 Key to Figure A-10

(Abstracted from Table A-3; see table for complete notes)

Num

6

14

8

14

9

Characteristic

Clock High to Address, FC, SIZE, RMC Valid

Clock High to Address, FC, SIZE, RMC Invalid

Clock Low to AS, DS, CS Asserted

12 Clock Low to AS, DS, CS Negated

14B AS, CS Width Asserted

18 Clock High to R/W High

20 Clock High to R/W Low

27 Data In Valid to Clock Low (Data Setup)

30

6

CLKOUT Low to Data In Invalid

30A

6

46A

73

74

CLKOUT Low to Data In High Impedance

R/W Width Asserted

BKPT Input Setup Time

BKPT Input Hold Time

Symbol t

CHAV t

CHAZn t

CLSA t

CLSN t

SWDW t

CHRH t

CHRL t

DICL t

CLDI t

CLDH t

RWAS t

BKST t

BKHT

Min

0

0

2

2

40

0

0

5

15

—

90

15

10

Max Units

29 ns

—

25

29

—

29

29

—

—

90

—

—

— ns ns ns ns ns ns ns ns ns ns ns ns

NOTES:

1. All AC timing is shown with respect to 20% V

DD

and 70% V

DD

levels unless otherwise noted.

6. These hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on synchronous reads. The user is free to use either hold time.

14. RMC signal is not supported on CPU16-based MCUs.

SIM

REFERENCE MANUAL

ELECTRICAL CHARACTERISTICS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

A-19

Freescale Semiconductor, Inc.

CLKOUT

ADDR[23:0]

6

S0 S1 S4 S5 S0

8

FCP2:0]

SIZ[1:0]

AS

DS

9

14B

12

CS

20 46A

R/W

24 18

DATA[15:0]

23 25

BKPT

73 74

68300 FAST WR CYC TIM

Figure A-11 Fast Termination Write Cycle Timing Diagram

MOTOROLA

A-20

ELECTRICAL CHARACTERISTICS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

Table A-13 Key to Figure A-11

(Abstracted from Table A-3; see table for complete notes)

Num

6

14

8

14

9

74

Characteristic

Clock High to Address, FC, SIZE, RMC Valid

Clock High to Address, FC, SIZE, RMC Invalid

Clock Low to AS, DS, CS Asserted

12 Clock Low to AS, DS, CS Negated

14B AS, CS Width Asserted

18 Clock High to R/W High

20 Clock High to R/W Low

23 Clock High to Data Out Valid

24 Data Out Valid to Negating Edge of AS, CS

25 DS, CS Negated to Data Out Invalid (Data Out Hold)

46A R/W Width Asserted

73 BKPT Input Setup Time

BKPT Input Hold Time

Symbol t

CHAV t

CHAZn t

CLSA t

CLSN t

SWDW t

CHRH t

CHRL t

CHDO t

DVASN t

SNDOI t

RWAS t

BKST t

BKHT

NOTES:

1. All AC timing is shown with respect to 20% V

DD

and 70% V

DD

levels unless otherwise noted.

14. RMC signal is not supported on CPU32-based MCUs.

—

15

15

90

15

10

2

40

0

0

Min

0

0

2

29

—

—

—

—

—

29

—

29

29

Max Units

29 ns

—

25 ns ns ns ns ns ns ns ns ns ns ns ns

SIM

REFERENCE MANUAL

ELECTRICAL CHARACTERISTICS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

A-21

CLKOUT

ECLK

R/W

ADDR[23:0]

CS

DATA[15:0]

DATA[15:0]

Freescale Semiconductor, Inc.

S0 S2

2A

WS WS WS WS

3A

1A

E1

E15 E3

E16

E14

E11

WRITE

S4 S0 S2 WS

E6

E2

E4

READ

E7

E13

E8

E9

E5

E10

WRITE

E12

68300 E CYCLE TIM

Figure A-12 ECLK Timing Diagram

MOTOROLA

A-22

ELECTRICAL CHARACTERISTICS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

Table A-14 Key to Figure A-12

(Abstracted from Tables A-3 and A-4; see tables for complete notes)

Num

1A ECLK Period

Characteristic

2A, 3A ECLK Pulse Width

4A, 5A Rise and Fall Time — All Outputs except CLKOUT

E1

2

ECLK Low to Address and R/W Valid

E2 ECLK Low to Address and R/W Hold

E3 ECLK Low to CS Valid (CS delay)

E4 ECLK Low to CS Hold

E5 CS Negated Width

E6 Read Data Setup Time

E7 Read Data Hold Time

E8 ECLK Low to Data High Impedance

E9 CS Negated to Data Hold (Read)

E10 CS Negated to Data High Impedance

E11 ECLK Low to Data Valid (Write)

E12 ECLK Low to Data Hold (Write)

E13 CS Negated to Data Hold (Write)

E14

3

Address Access Time (Read)

E15

4

Chip Select Access Time (Read)

E16 Address Setup Time

Symbol t

EDSR t

EDHR t

EDHZ t

ECDH t

ECDZ t

EDDW t

EDHW t

ECHW t

Ecyc t

ECW t

Erf t

EAD t

EAH t

ECSD t

ECSH t

ECSN t

EACC t

EACS t

EAS

Min

476

236

—

—

10

—

15

100

30

15

—

0

—

—

5

0

386

326

—

Max Units

— ns

—

8 ns ns

60

—

120

—

—

—

—

115

—

1

2

—

—

—

—

1/2 ns ns ns ns ns ns ns ns ns t cyc t cyc ns ns ns ns t cyc

NOTES:

1. All AC timing is shown with respect to 20% V

DD

and 70% V

DD

levels unless otherwise noted.

2. When the previous bus cycle is not a synchronous ECLK bus cycle, the address may be valid before ECLK goes low.

3. Address access time = t

Ecyc

– t

EAD

– t

EDSR

4. Chip select access time = t

Ecyc

– t

ECSD

– t

EDSR

14. RMC signal is not supported on CPU16-based MCUs.

SIM

REFERENCE MANUAL

ELECTRICAL CHARACTERISTICS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

A-23

Freescale Semiconductor, Inc.

CLKOUT

ADDR[23:0]

6

S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5

6 8

FC[2:0]

SIZ[1:0]

AS

DS

11

9

14 11

9

14

9

12

12

CS

18

R/W

DATA[15:0]

46

27

29

20

55

29A

46

23

14A

25

53

15

18

13

54

68300 CHIP SEL TIM

Figure A-13 Chip Select Timing Diagram

MOTOROLA

A-24

ELECTRICAL CHARACTERISTICS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

Table A-15 Key to Figure A-13

(Abstracted from Table A-3; see table for complete notes)

Num

6

14

8

14

Characteristic

Clock High to Address, FC, SIZE, RMC Valid

9

11

14

Clock High to Address, FC, SIZE, RMC Invalid

Clock Low to AS, DS, CS Asserted

Address, FC, SIZE, RMC Valid to AS, CS Asserted

12 Clock Low to AS, DS, CS Negated

13 AS, DS, CS Negated to Address, FC, SIZE Invalid

(Address Hold)

14 AS, CS Width Asserted

14A

15

5

DS, CS Width Asserted Write

AS, DS, CS Width Negated

18 Clock High to R/W High

20 Clock High to R/W Low

23 Clock High to Data Out Valid

25 DS, CS Negated to Data Out Invalid (Data Out Hold)

29

6

DS, CS Negated to Data In Invalid (Data In Hold)

29A

6, 7

46

53

54

55

DS, CS Negated to Data In High Impedance

R/W Width Asserted (Write or Read)

Data Out Hold from Clock High

Clock High to Data Out High Impedance

R/W Asserted to Data Bus Impedance Change

Symbol t

CHAV t

CHAZn t

CLSA t

AVSA t

CLSN t

SNAI t

SWA t

SWAW t

SN t

CHRH t

CHRL t

CHDO t

SNDOI t

SNDI t

SHDI t

RWA t

DOCH t

CHDH t

RADC

Min

0

0

2

15

2

15

100

45

40

0

0

—

15

0

—

150

0

—

40

Max Units

29 ns

—

25

—

29

—

—

—

—

29

29

29

—

—

55

—

—

28

— ns ns ns ns ns

NOTES:

1. All AC timing is shown with respect to 20% V

DD

and 70% V

DD

levels unless otherwise noted.

5. If multiple chip selects are used, CS width negated (specification 15) applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select. The CS width negated specification between multiple chip selects does not apply to chip selects being used for synchronous ECLK cycles.

6. These hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on synchronous reads. The user is free to use either hold time.

7. Maximum value is equal to (t cyc

/ 2) + 25 ns.

14. RMC signal is not supported on CPU16-based MCUs.

ns ns ns ns ns ns ns ns ns ns ns ns ns

SIM

REFERENCE MANUAL

ELECTRICAL CHARACTERISTICS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

A-25

Freescale Semiconductor, Inc.

MOTOROLA

A-26

ELECTRICAL CHARACTERISTICS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

APPENDIX BMEMORY MAP AND REGISTERS

S/U

S

S

S/U

S

S

S

S

S

S

S

S

S

S

S

S

S/U

S

S

S

S

S

S

S/U

S/U

S/U

S

S/U

S/U

S/U

S

S

Access

S

S

S

S

S

S

S

B.1 SIM Memory Map

Table B-1 SIM Address Map

####22

####24

####26

####28

####2A

####2C

####2E

####30

####32

####34

####36

####38

####3A

####3C

####3E

####40

Address 15 8 7 0

####00 SIM CONFIGURATION REGISTER (SIMCR)

####02

####04

SIM TEST REGISTER (SIMTR)

SYNTHESIZER CONTROL REGISTER (SYNCR)

####06

####08

####0A

####0C

UNUSED

UNUSED

UNUSED

RESET STATUS REGISTER (RSR)

SYSTEM TEST REGISTER E (SIMTRE)

UNUSED

UNUSED

####0E

####10

####12

####14

####16

####18

####1A

####1C

####1E

####20

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

PORT E DATA (PORTE0)

PORT E DATA (PORTE1)

PORT E DATA DIRECTION (DDRE)

PORT E PIN ASSIGNMENT (PEPAR)

PORT F DATA (PORTF0)

PORT F DATA (PORTF1)

PORT F DATA DIRECTION (DDRF)

PORT F PIN ASSIGNMENT (PFPAR)

SYSTEM PROTECTION CONTROL

(SYPCR)

####42

####44

####46

####48

####4A

####4C

PERIODIC INTERRUPT CONTROL REGISTER (PICR)

PERIODIC INTERRUPT TIMING REGISTER (PITR)

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

SOFTWARE SERVICE (SWSR)

UNUSED

UNUSED

UNUSED

UNUSED UNUSED

TEST MODULE MASTER SHIFT A (TSTMSRA)

TEST MODULE MASTER SHIFT B (TSTMSRB)

TEST MODULE SHIFT COUNT (TSTSC)

TEST MODULE REPETITION COUNTER (TSTRC)

TEST MODULE CONTROL (CREG)

TEST MODULE DISTRIBUTED (DREG)

UNUSED UNUSED

UNUSED

UNUSED

UNUSED

PORT C DATA (PORTC)

UNUSED

CHIP-SELECT PIN ASSIGNMENT REGISTER (CSPAR0)

CHIP-SELECT PIN ASSIGNMENT REGISTER (CSPAR1)

CHIP-SELECT BASE ADDRESS REGISTER BOOT (CSBARBT)

CHIP-SELECT OPTION REGISTER BOOT (CSORBT)

CHIP-SELECT BASE ADDRESS REGISTER 0 (CSBAR0)

SIM

REFERENCE MANUAL

MEMORY MAP AND REGISTERS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

B-1

S

S

S

S

S

S

S

S

Access

S

S

S

S

S

S

S

S

S

S

S

S

S

Freescale Semiconductor, Inc.

Table B-1 SIM Address Map (Continued)

####6A

####6C

####6E

####70

####72

####74

####76

####78

####7A

####7C

####7E

Address 15 8 7 0

####4E

####50

CHIP-SELECT OPTION REGISTER 0 (CSOR0)

CHIP-SELECT BASE ADDRESS REGISTER 1 (CSBAR1)

####52

####54

####56

####58

CHIP-SELECT OPTION REGISTER 1 (CSOR1)

CHIP-SELECT BASE ADDRESS REGISTER 2 (CSBAR2)

CHIP-SELECT OPTION REGISTER 2 (CSOR2)

CHIP-SELECT BASE ADDRESS REGISTER 3 (CSBAR3)

####5A

####5C

####5E

####60

####62

####64

####66

####68

CHIP-SELECT OPTION REGISTER 3 (CSOR3)

CHIP-SELECT BASE ADDRESS REGISTER 4 (CSBAR4)

CHIP-SELECT OPTION REGISTER 4 (CSOR4)

CHIP-SELECT BASE ADDRESS REGISTER 5 (CSBAR5)

CHIP-SELECT OPTION REGISTER 5 (CSOR5)

CHIP-SELECT BASE ADDRESS REGISTER 6 (CSBAR6)

CHIP-SELECT OPTION REGISTER 6 (CSOR6)

CHIP-SELECT BASE ADDRESS REGISTER 7 (CSBAR7)

CHIP-SELECT OPTION REGISTER 7 (CSOR7)

CHIP-SELECT BASE ADDRESS REGISTER 8 (CSBAR8)

CHIP-SELECT OPTION REGISTER 8 (CSOR8)

CHIP-SELECT BASE ADDRESS REGISTER 9 (CSBAR9)

CHIP-SELECT OPTION REGISTER 9 (CSOR9)

CHIP-SELECT BASE ADDRESS REGISTER 10 (CSBAR10)

CHIP-SELECT OPTION REGISTER 10 (CSOR10)

UNUSED UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

MOTOROLA

B-2

MEMORY MAP AND REGISTERS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

B.2 SIM Registers

SIMCR — Module Configuration Register

15 14 13

EXOFF FRZSW FRZBM

RESET:

0 0 0

12

0

0

11

SLVEN

DATA

11

10

0

0

9

0

SHEN

8

0

7 6

SUPV MM

1 1

5

0

0

4

0

0

3

1 1

IARB

$####00

0

1 1

EXOFF — External Clock Off

0 = The CLKOUT pin is driven from an internal clock source.

1 = The CLKOUT pin is placed in a high-impedance state.

FRZSW — Freeze Software Enable

0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters continue to run.

1 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters are disabled, preventing interrupts during software debugging.

FRZBM — Freeze Bus Monitor Enable

0 = When FREEZE is asserted, the bus monitor continues to operate.

1 = When FREEZE is asserted, the bus monitor is disabled.

SLVEN — Factory Test (Slave) Mode Enabled

0 = IMB is not available to an external tester.

1 = An external tester has direct access to the IMB.

SHEN[1:0] — Show Cycle Enable

This field determines what the external bus interface does with the external bus during

internal transfer operations. Refer to 5.11 Show Cycles for more information.

SHEN

00

01

10

11

Action

Show cycles disabled, external arbitration enabled

Show cycles enabled, external arbitration disabled

Show cycles enabled, external arbitration enabled

Show cycles enabled, external arbitration enabled; internal activity is halted by a bus grant

SUPV — Supervisor/Unrestricted Data Space

0 = Registers with access controlled by this bit are unrestricted

1 = Registers with access controlled by this bit are restricted to supervisor access only.

MM — Module Mapping

0 = Internal modules are addressed from $7FF000 — $7FFFFF.

1 = Internal modules are addressed from $FFF000 — $FFFFFF.

This bit can be written only once. Subsequent attempts to change this bit are ignored.

Address space $7FF000 – $7FFFFF is inaccessible to the CPU16. On CPU16-based microcontrollers, MM must always be set. Initialization software for these MCUs should make certain MM remains set (its reset state) by writing a one to it.

SIM

REFERENCE MANUAL

MEMORY MAP AND REGISTERS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

B-3

Freescale Semiconductor, Inc.

IARB[3:0] — Interrupt Arbitration Field

IARB determines SIM interrupt arbitration priority. The reset value is $F (highest prior-

ity), to prevent SIM interrupts from being discarded during initialization. Refer to 3.1.4

Interrupt Arbitration Priority and SECTION 6 INTERRUPTS for additional informa-

tion.

SIMTR — System Integration Test Register

SIMTR is used for factory test only.

$####02

SYNCR — Clock Synthesizer Control Register

13 12 11 10 9 8 15

W

RESET:

14

X

0 0 1 1 1

Y

1 1 1

7

EDIV

0

6

0

0

5

0

0

$####04

4 3 2 1 0

SLIMP SLOCK RSTEN STSIM STEXT

U U 0 0 0

W — Frequency Control (VCO)

0 = Base VCO frequency.

1 = VCO frequency multiplied by four.

Refer to 4.4 System Clock Frequency Control for additional information.

X — Frequency Control Bit (Prescale)

0 = Base system clock frequency.

1 = System clock frequency multiplied by two.

Refer to 4.4 System Clock Frequency Control for additional information.

Y[5:0] — Frequency Control (Counter)

The Y field is the initial value for the modulus 64 down counter in the synthesizer feed-

back loop. Values range from 0 to 63. Refer to 4.4 System Clock Frequency Control

for additional information.

EDIV — ECLK Divide Rate

0 = ECLK is system clock divided by 8.

1 = ECLK is system clock divided by 16.

Refer to 4.5 External Bus Clock for additional information.

SLIMP — Limp Mode Status

0 = MCU is operating normally.

1 = Loss of reference signal — MCU operating in limp mode.

Refer to 4.7 Loss of Reference Signal for additional information.

SLOCK — Synthesizer Lock

0 = VCO is enabled, but has not locked.

1 = VCO has locked on the desired frequency or system clock is external.

RSTEN — Reset Enable

0 = Loss of clock causes the MCU to operate in limp mode.

1 = Loss of clock causes system reset.

Refer to 4.7 Loss of Reference Signal for additional information.

MOTOROLA

B-4

MEMORY MAP AND REGISTERS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

STSIM — Stop Mode SIM Clock

0 = SIM clock driven by the external reference signal and the VCO is turned off during low-power stop.

1 = SIM clock driven by VCO during low-power stop.

This bit has an effect only if the PLL is configured to supply the clock signal (MODCLK

held high during reset). Refer to 4.6 Low-Power Stop Operation for additional infor-

mation.

STEXT — Stop Mode External Clock

0 = CLKOUT held low during low-power stop.

1 = CLKOUT driven from SIM clock during low-power stop.

Refer to 4.6 Low-Power Stop Operation for additional information.

RSR — Reset Status Register

15 14 13 12

NOT USED

11 10 9 8 7 6

EXT POW

5

SW

4

DBF

3

0

2

LOC

$####06

1

SYS

0

TST

EXT — External Reset

Reset was caused by an external signal.

POW — Power-On Reset

Reset was caused by the power-on reset circuit.

SW — Software Watchdog Reset

Reset was caused by the software watchdog circuit.

DBF — Double Bus Fault Reset

Reset was caused by a double bus fault.

LOC — Loss of Clock Reset

Reset was caused by loss of clock reference signal.

SYS — System Reset

Reset was caused by the CPU32 RESET instruction. The CPU16 does not support this instruction.

TST — Test Submodule Reset

Reset was caused by the test submodule. This bit is set during system test only.

SIMTRE — System Integration Test Register (ECLK)

The SIMTRE is used for factory test only.

$####08

PORTE0, PORTE1 — Port E Data Register

15 14 13 12

NOT USED

11 10 9 8

RESET:

7

PE7

U

6

PE6

5

PE5

4

PE4

U U U

$####10, $####12

3

PE3

2

PE2

1

PE1

0

PE0

U U U U

SIM

REFERENCE MANUAL

MEMORY MAP AND REGISTERS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

B-5

Freescale Semiconductor, Inc.

DDRE — Port E Data Direction Register

15 14 13 12

NOT USED

11 10 9

RESET:

8

$####14

7 6 5 4 3 2 1 0

DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0

0 0 0 0 0 0 0 0

PEPAR — Port E Pin Assignment Register $####16

15 14 13 12

NOT USED

11 10 9 8 7 6 5 4 3 2 1 0

PEPA7 PEPA6 PEPA5 PEPA4 PEPA3 PEPA2 PEPA1 PEPA0

RESET:

DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8

Any bit cleared to zero defines the corresponding pin to be an I/O pin. Any bit set to one defines the corresponding pin to be a bus control signal.

Table B-2 Port E Pin Assignments

PEPAR Bit

PEPA7

PEPA6

PEPA5

PEPA4

PEPA3

PEPA2

PEPA1

PEPA0

Port E Signal

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

Bus Control Signal

SIZ1

SIZ0

AS

DS

RMC*

AVEC

DSACK1

DSACK0

*On CPU16-based MCUs, when PEPA3 is set, the PE3 pin, if connected, goes to logic level one. The CPU16 does not support the RMC function for this pin.

PORTF0, PORTF1 — Port F Data Register

15 14 13 12

NOT USED

11 10 9 8

RESET:

7

PF7

6

PF6

5

PF5

4

PF4

$####18, $####1A

3

PF3

2

PF2

1

PF1

0

PF0

U U U U U U U U

DDRF — Port F Data Direction Register

15 14 13 12

NOT USED

11 10 9

RESET:

8

$####1C

7 6 5 4 3 2 1 0

DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0

0 0 0 0 0 0 0 0

PFPAR — Port F Pin Assignment Register

15 14 13 12

NOT USED

11 10 9 8

RESET:

$####1E

7 6 5 4 3 2 1 0

PFPA7 PFPA6 PFPA5 PFPA4 PFPA3 PFPA2 PFPA1 PFPA0

DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 DATA9

MOTOROLA

B-6

MEMORY MAP AND REGISTERS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

Any bit cleared to zero defines the corresponding pin to be an I/O pin. Any bit set to one defines the corresponding pin to be an interrupt request signal or MODCLK.

Table B-3 Port F Pin Assignments

PFPAR Field

PFPA7

PFPA6

PFPA5

PFPA4

PFPA3

PFPA2

PFPA1

PFPA0

Port F Signal

PF7

PF6

PF5

PF4

PF3

PF2

PF1

PF0

Alternate Signal

IRQ7

IRQ6

IRQ5

IRQ4

IRQ3

IRQ2

IRQ1

MODCLK

SYPCR — System Protection Control Register

15 14 13 12

NOT USED

11 10 9 8 7 6

SWE SWP

RESET:

1

SWE — Software Watchdog Enable

0 = Software watchdog disabled

1 = Software watchdog enabled

SWP — Software Watchdog Prescale

0 = Software watchdog clock not prescaled

1 = Software watchdog clock prescaled by 512

SWT[1:0] — Software Watchdog Timing

This field selects software watchdog time-out period.

5

SWT

4

0 0

SWP

0

0

0

0

1

1

1

1

Software Watchdog Ratio

SWT Ratio

00 2

9

01

10

2

11

2

13

11

00

01

10

11

2

15

2

18

2

20

2

22

2

24

3 2

HME BME

$####20

1 0

BMT

0 0 0 0

HME — Halt Monitor Enable

0 = Disable halt monitor function

1 = Enable halt monitor function

SIM

REFERENCE MANUAL

MEMORY MAP AND REGISTERS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

B-7

Freescale Semiconductor, Inc.

BME — Bus Monitor External Enable

0 = Disable bus monitor function for an internal-to-external bus cycle.

1 = Enable bus monitor function for an internal-to-external bus cycle.

BMT[1:0] — Bus Monitor Timing

This field selects bus monitor time-out period.

BMT

00

01

10

11

Bus Monitor Period

Bus Monitor Time-out Period

64 System Clocks

32 System Clocks

16 System Clocks

8 System Clocks

PICR — Periodic Interrupt Control Register

15

0

RESET:

14

0

0 0

13

0

0

12

0

0

11

0

0

10

0

9

PIRQL

0

8

0

7

0

6

0

5

0

4

0

PIV

3

1

2

1

$####22

1

1

0

1

PIRQL[2:0] — Periodic Interrupt Request Level

This field determines the priority of periodic interrupt requests.

PIV[7:0] — Periodic Interrupt Vector

The bits of this field contain the periodic interrupt vector number supplied by the SIM when the CPU acknowledges an interrupt request.

PITR — Periodic Interrupt Timer Register

15

0

RESET:

14

0

0 0

13

0

0

12

0

0

11

0

0

10

0

0

9

0

0

8

PTP

MODCLK

7

0

6

0

5

0

4

PITM

3

0 0

2

0

$####24

1

0

0

0

PTP — Periodic Timer Prescaler Control

1 = Periodic timer clock prescaled by a value of 512

0 = Periodic timer clock not prescaled

PITM[7:0] — Periodic Interrupt Timing Modulus

This is the 8-bit timing modulus used to determine periodic interrupt rate. Use the following expression to calculate timer period.

PIT Period = [(PIT Modulus)(Prescaler value)(4)]/EXTAL Frequency

SWSR — Software Service Register

15 14 13 12

NOT USED

11 10 9

RESET:

8 7

0

0

6

0

0

5

0

0

4

0

0

3

0

0

2

0

0

$####26

1

0

0

0

0 0

MOTOROLA

B-8

MEMORY MAP AND REGISTERS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

PORTC — Port C Data Register

15 14 13 12

NOT USED

11 10

RESET:

9 8 7

0

6

PC6

5

PC5

4

PC4

3

PC3

2

PC2

$####40

1

PC1

0

PC0

1 1 1 1 1 1 1 1

CSPAR0 — Chip Select Pin Assignment Register 0 $####44

15

0

RESET:

14

0

13 12

CSPA0[6]

11 10

CSPA0[5]

9

CSPA0[4]

8 7

CSPA0[3]

6 5

CSPA0[2]

4 3

CSPA0[1]

2 1

CSBOOT

0

0 0 DATA2 1 DATA2 1 DATA2 1 DATA1 1 DATA1 1 DATA1 1 1 DATA0

CSPAR0 contains seven two-bit fields that determine the functions of corresponding chip-select pins. CSPAR0[15:14] are not used. These bits always read zero; writes have no effect. CSPAR0 bit 1 always reads one; writes to CSPAR0 bit 1 have no effect.

CSPAR0 Field

CSPA0[6]

CSPA0[5]

CSPA0[4]

CSPA0[3]

CSPA0[2]

CSPA0[1]

CSBOOT

Table B-4 CSPAR0 Pin Assignments

Chip Select Signal

CS5

CS4

CS3

CS2

CS1

CS0

CSBOOT

Alternate Signal

FC2

FC1

FC0

BGACK

BG

BR

—

Discrete Output

PC2

PC1

PC0

—

—

—

—

CSPAR1 — Chip Select Pin Assignment Register 1

15

0

RESET:

14

0

0 0

13

0

0

12

0

0

11

0

0

10

0

0

9

CSPA1[4]

8

DATA7 1

7

CSPA1[3]

6

DATA6 1

5

CSPA1[2]

4 3

CSPA1[1]

2

$####46

1

CSPA1[0]

0

DATA5 1 DATA4 1 DATA3 1

CSPAR1 contains five two-bit fields that determine the functions of corresponding chip-select pins. CSPAR1[15:10] are not used. These bits always read zero; writes have no effect.

Table B-5 CSPAR1 Pin Assignments

CSPAR0 Field

CSPA1[4]

CSPA1[3]

CSPA1[2]

CSPA1[1]

CSPA1[0]

Chip Select Signal Alternate Signal Discrete Output

CS10 ADDR23 ECLK

CS9

CS8

ADDR22

ADDR21

PC6

PC5

CS7

CS6

ADDR20

ADDR19

PC4

PC3

SIM

REFERENCE MANUAL

MEMORY MAP AND REGISTERS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

B-9

Freescale Semiconductor, Inc.

Table B-6 Pin Assignment Encodings

Bit Field

00

01

10

11

Description

Discrete Output

Alternate Function

Chip Select (8-Bit Port)

Chip Select (16-Bit Port)

CSBARBT — Chip Select Base Address Register Boot ROM

15

ADDR

23

RESET:

14

ADDR

22

0 0

13

ADDR

21

0

12

ADDR

20

0

11

ADDR

19

0

10

ADDR

18

0

9

ADDR

17

0

8

ADDR

16

0

7

ADDR

15

0

6

ADDR

14

0

5

ADDR

13

0

4

ADDR

12

0

3

ADDR

11

0

2

1

$####48

1

BLKSZ

1

0

1

CSBAR[10:0] — Chip Select Base Address Registers

15

ADDR

23

RESET:

14

ADDR

22

0 0

13

ADDR

21

0

12

ADDR

20

0

11

ADDR

19

0

10

ADDR

18

0

9

ADDR

17

0

8

ADDR

16

0

7

ADDR

15

0

6

ADDR

14

0

5

ADDR

13

0

4

ADDR

12

$####4C–$####74

3

ADDR

11

2 1

BLKSZ

0

0 0 0 0 0

ADDR[15:3] — Base Address Field

This field sets the starting address of a particular address space.

BLKSZ — Block Size Field

This field determines the size of the block above the base address that is enabled by the chip select.

CSORBT — Chip Select Option Register Boot ROM

15

MODE

RESET:

14

BYTE

13

0 1 1

12

1

R/W

11

1

10

STRB

0

9

1

8

DSACK

7

1 0

6

1

5

SPACE

4

1 1

3

0

2

IPL

0

$####4A

1 0

0 0

CSOR[10:0] — Chip Select Option Registers

15

MODE

RESET:

14

BYTE

13

0 0 0

12

0

R/W

11

0

10

STRB

0

9

0

8

DSACK

7

0 0

6 5

SPACE

4 3

$####4E–$####76

2

IPL

1 0

0 0 0 0 0 0 0

MODE — Timing Mode

The MODE bit determines whether chip-select operation emulates asynchronous bus operation or is synchronized to the M6800-type bus clock signal (ECLK) available on

ADDR23. Refer to 7.5 Chip-Select Timing for additional information.

0 = Emulate asynchronous bus operation

1 = Synchronize chip-select assertion to ECLK

MOTOROLA

B-10

MEMORY MAP AND REGISTERS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

BYTE — Upper/Lower Byte Option

This field enables or disables the chip-select circuit and, for 16-bit ports, determines which combinations of size and ADDR0 pins will cause the chip select to be asserted.

Refer to 7.6 Chip Selects and Dynamic Bus Sizing for more information.

00 = Disable

01 = Lower byte

10 = Upper byte

11 = Both Bytes

R/W — Read/Write

This field causes a chip select to be asserted only for a read, only for a write, or for both read and write.

00 = Reserved

01 = Read only

10 = Write only

11 = Read/Write

STRB — Address Strobe/Data Strobe

The STRB bit controls the timing of a chip-select assertion in asynchronous mode.

This bit has no effect in synchronous mode.

0 = Synchronize chip select assertion with address strobe

1 = Synchronize chip select assertion with data strobe

DSACK — Data and Size Acknowledge

This field specifies the source of DSACK when chip-select cycles emulate asynchro-

nous bus cycles, and controls wait state insertion. Refer to 7.8 Using Chip Selects in

Interrupt Acknowledge Cycles for details.

SPACE — Address Space Select

The SPACE field determines the address space in which a chip select is asserted. An access must have the space type represented by SPACE encoding in order for a chip-

select signal to be asserted. Refer to 7.8 Using Chip Selects in Interrupt Acknowl-

edge Cycles for additional information.

00 = CPU space

01 = User space

10 = Supervisor space

11 = Supervisor or user space

IPL — Interrupt Priority Level

This field selects the interrupt level when a chip select is used for interrupt acknowl-

edge. Refer to 7.8 Using Chip Selects in Interrupt Acknowledge Cycles for addi-

tional information.

000 = Any Level

001 = Level 1

010 = Level 2

011 = Level 3

100 = Level 4

101 = Level 5

110 = Level 6

111 = Level 7

SIM

REFERENCE MANUAL

MEMORY MAP AND REGISTERS

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

B-11

Freescale Semiconductor, Inc.

AVEC — Autovector Enable

This field specifies whether to generate an internal AVEC signal during an interrupt acknowledge cycle initiated by assertion of an IRQ pin when match conditions are met.

Refer to 7.8 Using Chip Selects in Interrupt Acknowledge Cycles for additional in-

formation.

0 = Disable AVEC generation

1 = Enable AVEC generation

MOTOROLA

B-12

MEMORY MAP AND REGISTERS

For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

INDEX

–A–

AC timing A-4

Access levels 1-4, 3-2

ADDR[23:0] 5-2, 7-19

and interrupts 6-3

and RPSIM 10-1

Address

map, SIM 1-5

strobe (AS) 5-2

Alignment, operand 5-7

AS 5-2

Asynchronous resets 7-9

AVEC (autovector) 5-3, 6-6

bit 7-3, 7-15, 7-21

–B–

Background debugging mode (BDM) 3-2

Base address registers, chip select 7-19

CSBAR[10:0] 7-19

CSBARBT 7-4, 7-17, 7-19

BDM 3-2

BERR 3-5, 5-3, 5-38, 5-40, 6-4

and breakpoints 5-33

BG 5-48, 5-51, 5-52

BGACK 5-47, 5-49

BKPT 5-33, 8-10

BLKSZ 7-19

Block diagram

reset 8-2

SIM 1-2

system configuration and protection 3-1

Block size (BLKSZ) 7-19

BME 3-5, 3-11

BMT 3-5, 3-12

BR 5-47, 5-48, 5-49

Breakpoints

acknowledge cycle 5-32

hardware 5-33

mode selection 8-10

signal (BKPT) 5-33, 8-10 software 5-33

Bus

arbitration 5-48, 5-50

control 5-50

timing diagrams A-15, A-17

cycles

CPU space 5-31

external 5-4

SIM

REFERENCE MANUAL

interrupt acknowledge 6-3

read 5-8

write 5-11

error

double bus fault 5-42

exceptions 5-40

processing 5-38

grant (BG) 5-48, 5-51, 5-52

acknowledge (BGACK) 5-47, 5-49

intermodule 1-1

master 5-48, 5-49

monitor 3-5 external enable (BME) 3-5, 3-11 timing (BMT) 3-5, 3-12

request (BR) 5-47, 5-48, 5-49

BYTE field 7-2, 7-6, 7-10, 7-20

Byte transfer

16-bit port 5-17, 5-18

8-bit port 5-16

–C–

Chip selects 7-1

asynchronous emulation 7-9

base address 7-3

registers 7-17, 7-19 boot (CSBOOT) 7-17

dynamic bus sizing 7-10

interfacing example 7-22

enabling 7-6

fast termination 7-11

interrupt acknowledge cycles 7-13

operation 7-6

option registers 7-2, 7-16, 7-19

CSOR[10:0] 7-19

CSORBT 7-19

pin assignment registers 7-16, 7-17

CSPAR0 7-18

CSPAR1 7-18

register diagrams 7-17

reset operation 7-15

timing 7-9

diagram A-24

wait states 7-10

CLKOUT 3-3

and resets 7-5

output timing diagram A-7

synchronization to 5-5

Clock, system 4-1

control

multipliers 4-8

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

I-1

timing A-1

external 4-3

circuit 4-4

frequency control 4-6

loss of 4-12

mode selection 8-10

sources 4-1 synthesizer 4-1, 4-4

Configuration, system 3-1

CPU

and SIM interaction 1-7

space cycles 5-31

CPU16 1-7

CPU32 1-7

Crystal oscillator 4-5 tune-up 4-5

CSBAR[10:0] 7-19

CSBARBT 7-4, 7-17, 7-19

CSBOOT 7-17

CSOR[10:0] 7-19

CSORBT 7-19

CSPA0 7-18

CSPA1 7-18

CSPAR0 7-18

CSPAR1 7-18

–D–

Data

and size acknowledge (DSACK) 5-3, 5-6, 6-5

bus (DATA[15:0]) 5-2

mode selection with 1-6, 1-7, 8-8

signal conditioning 8-10

direction registers (DDRE, DDRF) 9-2

strobe (DS) 5-2, 5-52

DBF 8-3, 8-4

DC characteristics A-2

DDRE 9-3

DDRF 9-3

Debugging

and HALT 5-45

show cycles 5-52

Discrete

I/O 9-1

output 7-21

Double bus fault 5-42

reset flag (DBF) 8-3, 8-4

DS 5-2, 5-52

DSACK 5-3, 5-6, 6-5

and RPSIM 10-1

field 7-2, 7-9, 7-20

Dynamic bus sizing 5-6

and chip selects 7-10

–E–

EBI 5-1

ECLK 4-11, 7-1, 7-10 divide rate (EDIV) 4-11, 4-13

Freescale Semiconductor, Inc.

timing diagrams A-7

timing diagrams A-3 A-22

EDIV 4-11, 4-13

Exceptions

bus error 5-42

EXOFF 3-3

EXT 8-3, 8-4

EXTAL 3-7, 3-8, 4-1, 4-3, 4-4

External

bus arbitration 5-47

bus clock (ECLK) 4-11, 7-1, 7-10

bus cycles 5-4

synchronization to CLKOUT 5-5

bus interface (EBI) 5-1

clock 4-3

input timing diagram A-7

off (EXOFF) 3-3

devices, interfacing to 5-28

filter capacitor (XFC) 4-5

reset flag (EXT) 8-3, 8-4

–F–

Factory test (slave) mode 3-3

arbitration 5-52

Fast termination cycles 7-11

read 7-12

timing diagram A-18

write 7-13

timing diagram A-20

FC[2:0] 5-2, 5-27

and interrupts 6-3

FREEZE 3-2

Freeze

bus monitor (FRZBM) 3-2, 3-4

software watchdog (FRZSW) 3-3

Frequency control, system clock 4-6

avoiding overshoot 4-7 tables 4-7

FRZBM 3-2, 3-4

FRZSW 3-3

Function codes (FC[2:0]) 5-2, 5-27

and interrupts 6-3

–G–

General-purpose I/O 9-1

–H–

HALT 3-5, 5-3, 5-38, 5-45, 5-46, 5-47

timing 5-46

Halt

monitor 3-5 enable (HME) 3-5, 3-11

operation 5-47

Hardware breakpoints 5-33

HME 3-5, 3-11

MOTOROLA

I-2 For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

Freescale Semiconductor, Inc.

–I–

IARB 3-3, 3-4, 6-3

IMB 1-1

Initialization, system 8-14

Input sample window 5-5

Input/output, discrete 9-1

Interfacing, system, examples 5-28

with chip selects 7-22

Intermodule bus (IMB) 1-1

Internal bus monitor 3-5

Interrupts 6-1

acknowledge cycles 6-3, 6-5

and chip selects 7-13

arbitration 3-3, 6-2 number (IARB) 3-3, 3-4, 6-3

level and recognition 6-1, 6-2

PIT 3-9

priority level, chip selects (IPL) 7-3, 7-21, 7-23

priority mask 6-2

recognition 6-1 request signals (IRQ[7:1]) 6-1, 7-13 sources 6-1

vectors 6-4

IPL 7-3, 7-23

IRQ[7:1] 6-1, 7-13

–L–

Late retry sequence 5-45

Limp mode 4-13 status flag (SLIMP) 4-13

LOC (loss-of-clock reset flag) 8-3, 8-4

Loss of reference signal 4-12

LPSTOP (low-power stop) 3-9, 4-11

broadcast cycle 5-38

–M–

Mask value, interrupt 6-2

MCU 1-1

Memory map, SIM 1-5

Misaligned operands 5-8, 5-18, 5-23, 5-26

MM 1-4, 3-2, 3-4

MODCLK 3-6, 3-7, 4-1, 4-4, 8-10

MODE 7-2, 7-9, 7-10, 7-20

Mode selection with DATA pins 1-6, 1-7, 8-8

Module mapping (MM) 1-4, 3-2, 3-4

–O–

Operands

alignment 5-7

byte order 5-15

misaligned 5-8, 5-18, 5-20, 5-23, 5-26

transfer cases 5-15

Option registers, chip select 7-19

Output driver types 2-1

Output, discrete 7-4, 7-21

SIM

REFERENCE MANUAL For More Information On This Product,

Go to: www.freescale.com

–P–

PEPA 9-1

PEPAR 9-1

Periodic interrupt

control register (PICR) 3-8, 3-10 request level (PIRQL) 3-8, 3-10 vector (PIV) 3-8, 3-10

PFPA 9-2

PFPAR 9-1, 9-2

Phase-locked loop (PLL) 4-1

PICR 3-8, 3-10

Pin assignment

chip selects, at reset 7-16

registers

chip select 7-4, 7-17

ports E and F 9-1

Pins, SIM 2-1 characteristics 2-1, 2-2 output driver types 2-1

state during reset 8-11

PIRQL 3-8, 3-10

PIT 3-7, 3-8, 6-1

modulus counter (PITM) 3-8, 3-11

prescaler (PTP) 3-7, 3-10

priority 3-9 vector 3-9

PITCLK (PIT clock) 3-8

PITM (PIT modulus) 3-8, 3-11

PITR (PIT register) 3-7, 3-10

PIV 3-8, 3-10

PLL 4-1, 4-7

Port C data register (PORTC) 7-21

Ports E and F 9-1

data direction registers 9-2

data register 9-3

pin assignment register 9-1, 9-2

POW (power-on reset flag) 8-3, 8-4

Power-on reset 8-3, 8-6

Privilege levels 1-4, 3-2

protection, system 3-1

registers 3-9

PTP 3-7, 3-10

–R–

R/W 5-2

and interrupts 6-3

bit 7-2, 7-20

Read cycles 5-8

and RPSIM 10-2

fast termination 7-12

modify-write (RMC) 5-13, 5-43, 5-47

timing diagram A-9

Reduced pin-count SIM (RPSIM) 10-1

Registers

address map 1-5

diagrams B-1

reset state 8-13

MOTOROLA

I-3

Freescale Semiconductor, Inc.

RESET instruction 8-4

Resets 8-1

and chip selects 7-15

and mode select, timing diagram A-14

block diagram 8-2

double bus fault 8-3

enable (RSTEN) 4-12, 4-13

external 8-3 loss of clock 8-3

mode selection 1-6

operating configuration 8-8

pin state 8-11

power on 8-3, 8-6

SIM registers 8-13

software watchdog 8-3

sources 8-2

status register (RSR) 8-3, 8-4

system 8-4 timing 8-4

Retry

sequence 5-44

termination 5-38

Return from exception (RTE) 5-42

RMC 5-13, 5-43, 5-47

and RPSIM 10-2

RPSIM 10-1

RSR 8-3, 8-4

RSTEN 4-12, 4-13

RTE 5-42

–S–

SHEN 3-4, 5-52

Show cycles 5-52

enable (SHEN) 3-4, 5-52

timing diagram A-13

Signals, SIM 2-1, 2-3

characteristics 2-3

function 2-4

SIM

address map 1-5

block diagram 1-2

clock (SIMCLK) 4-12

configuration register (SIMCR) 3-2, 3-3

reduced pin count 10-1

signals and pins 2-1

SIMCLK 4-12

SIMCR 3-2, 3-3

SIZ[1:0] 5-2, 5-6, 5-52

and interrupts 6-3

Slave (factory test) mode 3-3 enable (SLVEN) 3-3, 3-4

SLIMP 4-13

SLOCK 4-13

SLVEN 3-3, 3-4

Software

breakpoints 5-32

watchdog 3-6, 3-7 enable (SWE) 3-6, 3-11 prescaler (SWP) 3-6, 3-11 ratio 3-6

reset flag (SW) 8-3, 8-4

service register (SWSR) 3-6, 3-10 timing (SWT) 3-6, 3-11

SPACE 7-2, 7-3, 7-20

Spurious interrupt monitor 3-5

STEXT (stop mode external clock) 4-12, 4-14

Stop, low power 3-9

STRB (strobe) 7-2, 7-11, 7-20

STSIM (stop mode SIM clock) 3-9, 4-12, 4-13

Supervisor privilege level 1-1, 1-4, 1-8, 3-2

SUPV 3-4

SW 8-3, 8-4

SWE 3-6, 3-11

SWP 3-6, 3-11

SWSR 3-6, 3-10

SWT 3-6, 3-11

Synchronous resets 8-2

SYNCR 4-1, 4-6, 4-12, 4-13

Synthesizer

lock (SLOCK) 4-13

SYPCR 3-6, 3-11

SYS 8-4

System

configuration 3-1

initialization 8-1, 8-14

protection 3-1

control register (SYPCR) 3-5, 3-11

reset flag (SYS) 8-4

–T–

TAS (test and set) 5-13

Test

mode 3-3

registers 3-4

reset flag (TST) 8-4

TSC (three-state control) 8-7

TST 8-4

–U–

User privilege level 1-1, 1-4, 1-8, 3-2

–V–

V<st-subscript>DDSYN 4-5

V<st-subscript>SSI 4-5

VCO 4-4

Vector, interrupt 6-4

W bit 4-6, 4-7, 4-13

Wait states 5-6

and chip selects 7-10

Word transfer

16-bit port 5-20

–W–

MOTOROLA

I-4 For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL

8-bit port 5-18

Write cycles 5-11

fast termination 7-13

timing diagram A-11

–X–

X bit 4-6, 4-7, 4-13

XFC 4-5

XTAL 4-1, 4-3, 4-4

–Y–

Y field 4-6, 4-7, 4-13

Freescale Semiconductor, Inc.

SIM

REFERENCE MANUAL For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

I-5

Freescale Semiconductor, Inc.

MOTOROLA

I-6 For More Information On This Product,

Go to: www.freescale.com

SIM

REFERENCE MANUAL