NXP MC68336 32 Bit Microcontroller User Guide
NXP MC68336
The NXP MC68336 is powerful and versatile device that offers a wide range of capabilities for embedded system design. With its advanced features, the MC68336 is ideal for applications such as industrial control, automotive systems, and medical devices.
Some of the key features of the MC68336 include:
- High-performance 32-bit CPU core
- Integrated memory controller with support for up to 16 MB of external memory
- Flexible clock control system with support for multiple clock sources
- Comprehensive set of peripherals, including timers, serial ports, and A/D converters
- Advanced power management features for extended battery life
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Freescale Semiconductor, Inc. APPENDIX A ELECTRICAL CHARACTERISTICS This appendix contains electrical specification tables and reference timing diagrams for MC68336 and MC68376 microcontroller units. Table A-1 Maximum Ratings Freescale Semiconductor, Inc... Num Rating Symbol Value Unit 1 Supply Voltage1, 2, 7 VDD – 0.3 to + 6.5 V 2 Input Voltage 11, 22, 3, 55, 77 Vin – 0.3 to + 6.5 V 3 Instantaneous Maximum Current ID 25 mA – 500 to 500 µA Single pin limit (applies to all pins)11, 55, 66, 77 4 Operating Maximum Current Digital Input Disruptive Current 4, 5, 6, 7, 8 ≅ – 0.3 V V NEGCLMAP V 5 6 POSCLAMP IID ≅ VDD + 0.3 Operating Temperature Range MC68336/376 “C” Suffix MC68336/376 “V” Suffix MC68336/376 “M” Suffix Storage Temperature Range TA TL to TH – 40 to 85 – 40 to 105 – 40 to 125 °C Tstg – 55 to 150 °C NOTES: 1. Permanent damage can occur if maximum ratings are exceeded. Exposure to voltages or currents in excess of recommended values affects device reliability. Device modules may not operate normally while being exposed to electrical extremes. 2. Although sections of the device contain circuitry to protect against damage from high static voltages or electrical fields, take normal precautions to avoid exposure to voltages higher than maximum-rated voltages. 3. All pins except TSTME/TSC. 4. All functional non-supply pins are internally clamped to VSS. All functional pins except EXTAL and XFC are internally clamped to VDD. Does not include QADC pins (refer to Table A-11). 5. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 6. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. 7. This parameter is periodically sampled rather than 100% tested. 8. Total input current for all digital input-only and all digital input/output pins must not exceed 10 mA. Exceeding this limit can cause disruption of normal operation. MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-1 Freescale Semiconductor, Inc. Table A-2 Typical Ratings Freescale Semiconductor, Inc... Num Rating Symbol Value Unit 1 Supply Voltage VDD 5.0 V 2 Operating Temperature TA 25 °C 3 VDD Supply Current RUN LPSTOP, VCO off LPSTOP, External clock, maxi f sys IDD 113 125 3.75 mA µA mA 4 Clock Synthesizer Operating Voltage VDDSYN 5.0 V 5 VDDSYN Supply Current VCO on, maximum fsys External Clock, maximum f sys LPSTOP, VCO off VDD powered down IDDSYN 1.0 5.0 100 50 mA mA µA µA 6 RAM Standby Voltage VSB 3.0 V 7 RAM Standby Current Normal RAM operation Standby operation ISB 7.0 40 µA µA 8 Power Dissipation PD 570 mW Symbol Value Unit θJA 37 °C/W Table A-3 Thermal Characteristics Num 1 Rating Thermal Resistance Plastic 160-Pin Surface Mount The average chip-junction temperature (TJ) in C can be obtained from: T J = T + (P × Θ ) A D JA (1) where: TA = Ambient Temperature, °C ΘJA = Package Thermal Resistance, Junction-to-Ambient, °C/W PD = PINT + PI/O PINT = IDD × VDD, Watts — Chip Internal Power PI/O = Power Dissipation on Input and Output Pins — User Determined For most applications P I/O < P INT and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: P D = K ÷ ( T J + 273°C ) (2) Solving equations 1 and 2 for K gives: K = P D + ( T + 273°C ) + Θ ×P A JA D (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-2 Freescale Semiconductor, Inc. Table A-4 Clock Control Timing (VDD and VDDSYN = 5.0 Vdc ± 5%, V SS = 0 Vdc, T A = TL to TH, 4.194 MHz reference) Num Symbol Min Max Unit fref 4.194 5.243 MHz System Frequency On-Chip PLL System Frequency External Clock Operation fsys dc fref/32 dc 20.97 20.97 20.97 MHz 3 PLL Lock Time2, 3, 4, 5 tlpll — 20 ms 4 VCO Frequency6 fVCO — 2 (fsys max) MHz 5 Limp Mode Clock Frequency SYNCR X bit = 0 SYNCR X bit = 1 flimp — — fsys max/2 fsys max MHz CLKOUT Jitter2, 3, 4, 7 Short term (5 µs interval) Long term (500 µs interval) Jclk –0.625 –0.0625 –0.625 –0.0625 % 1 Freescale Semiconductor, Inc... 2 6 Characteristic PLL Reference Frequency Range 1 NOTES: 1. All internal registers retain data at 0 Hz. 2. This parameter is periodically sampled rather than 100% tested. 3. Assumes that a low-leakage external filter network is used to condition clock synthesizer input voltage. Total external resistance from the XFC pin due to external leakage must be greater than 15 MΩ to guarantee this specification. Filter network geometry can vary depending upon operating environment. 4. Proper layout procedures must be followed to achieve specifications. 5. Assumes that stable VDDSYN is applied, and that the crystal oscillator is stable. Lock time is measured from the time VDD and VDDSYN are valid until RESET is released. This specification also applies to the period required for PLL lock after changing the W and Y frequency control bits in the synthesizer control register (SYNCR) while the PLL is running, and to the period required for the clock to lock after LPSTOP. 6. Internal VCO frequency (fVCO ) is determined by SYNCR W and Y bit values. The SYNCR X bit controls a divide-by-two circuit that is not in the synthesizer feedback loop. When X = 0, the divider is enabled, and f sys = fVCO ÷ 4. When X = 1, the divider is disabled, and fsys = fVCO ÷ 2. X must equal one when operating at maximum specified fsys. 7. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDSYN and VSS and variation in crystal oscillator frequency increase the Jclk percentage for a given interval. When jitter is a critical constraint on control system operation, this parameter should be measured during functional testing of the final system. MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-3 Freescale Semiconductor, Inc. Table A-5 DC Characteristic s (VDD and VDDSYN = 5.0 Vdc ±5%, VSS = 0 Vdc, T A = TL to TH) Num Characteristic Symbol 1 Input High Voltage V 2 Input Low Voltage V 1 3 Input Hysteresis 4 Input Leakage Current Vin = VDD or VSS Input-only pins 5 High Impedance (Off-State) Leakage Current22 V = V or V All input/output and output pins IH IL Min 0.7 (V V SS DD Max ) V DD Unit + 0.3 – 0.3 0.2 (V DD ) V V 0.5 — V I –2.5 2.5 µA IOZ –2.5 2.5 µA — V 0.2 V — V V HYS 2 Freescale Semiconductor, Inc... in DD in SS 3 CMOS Output High Voltage22, I = –10.0 µA Group 1, 2, 4 input/output and all output pins V 7 CMOS Output Low Voltage22 IOL = 10.0 µA Group 1, 2, 4 input/output and all output pins V 8 Output High Voltage22, 33 IOH = –0.8 mA Group 1, 2, 4 input/output and all output pins V 6 OH OH V – 0.2 — OL OH DD V DD – 0.8 Output Low Voltage 22 I = 1.6 mA Group 1 I/O Pins, CLKOUT, FREEZE/QUOT, IPOL 9 IPE I = 5.3 mA Group 2 and Group 4 I/O Pins, CSBOOT, BG/CS I Group 3 OL 10 OL = 12 mA Three State Control Input High Voltage — — — 0.4 0.4 0.4 1.6 (VDD) 9.1 V — –15 –120 — µA I DD I DD SIDD SIDD — — — — 140 150 3 7 mA mA mA mA I DD I DD S IDD S — — — — 150 160 3 7 mA mA mA mA VDDSYN 4.75 5.25 V IDDSYN I DDSYN S IDDSYN I — — — — 3 5 3 3 mA mA mA mA V OL VIHTSC V 4 11 Data Bus Mode Select Pull-up Current V =V DATA[15:0] in IL V =V in IH MC68336 V I MSP DATA[15:0] 5 DD Supply Current 6 RUN RUN, TPU emulation mode LPSTOP, 4.194 MHz crystal, VCO Off (STSIM = 0) LPSTOP (External clock input frequency = maximum fsys) 12A MC68376 V DD Supply Current5 RUN 6 RUN, TPU emulation mode LPSTOP, 4.194 MHz crystal, VCO Off (STSIM = 0) LPSTOP (External clock input frequency = maximum f 12B ) sys 13 Clock Synthesizer Operating Voltage V DDSYN Supply Current55 4.194 MHz crystal, VCO on, maximum f 14 External Clock, maximum f sys sys LPSTOP, 4.194 MHz crystal, VCO off (STSIM = 0) 4.194 MHz crystal, V powered down DD MC68336/376 USER’S MANUAL IDD DDSYN ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-4 Freescale Semiconductor, Inc. Table A-5 DC Characteristics (Continued) (VDD and VDDSYN = 5.0 Vdc ±5%, VSS = 0 Vdc, T A = TL to TH) Num Characteristic Symbol Min Max Unit 0.0 3.0 5.25 5.25 V ISB — — — 10 3 100 µA mA µA 17A MC68336 Power Dissipation9 PD — 756 mW 17B MC68376 Power Dissipation9 PD — 809 mW Cin — — 10 20 pF — — — — 90 100 130 200 7 15 RAM Standby Voltage Specified V applied V DD V DD SB =V SS 8 16 RAM Standby Current55, 77, Normal RAM operationVDD > VSB – 0.5 V Transient condition VSB – 0.5 V ≥ VDD ≥ VSS + 0.5 V Freescale Semiconductor, Inc... Standby operation VDD < VSS + 0.5 V 10 18 Input Capacitance22, 19 Load Capacitance22 Group 1 I/O Pins and CLKOUT, FREEZE/QUOT, IPIPE Group 2 I/O Pins and CSBOOT, BG/CS Group 3 I/O pins Group 4 I/O pins All input-only pins All input/output pins CL pF NOTES: 1. Applies to : Port E[7:4] — SIZ[1:0], AS, DS Port F[7:0] — IRQ[7:1], MODCLK Port QS[7:0] — TXD, PCS[3:1], PCS0/SS, SCK, MOSI, MISO TPUCH[15:0], T2CLK, CPWM[8:5], CTD[4:3], CTD[10:9], CTM2C BKPT/DSCLK, IFETCH, RESET, RXD, TSTME/TSC EXTAL (when PLL enabled) 2. Input-Only Pins: EXTAL, TSTME/TSC, BKPT, PAI, T2CLK, RXD, CTM2C Output-Only Pins: CSBOOT, BG/CS, CLKOUT, FREEZE/QUOT, IPIPE Input/Output Pins: Group 1: DATA[15:0], IFETCH, TPUCH[15:0], CPWM[8:5], CTD[4:3], CTD[10:9] Group 2: Port C[6:0] — ADDR[22:19]/CS[9:6], FC[2:0]/CS[5:3] Port E[7:0] — SIZ[1:0], AS, DS, AVEC, RMC, DSACK[1:0] Port F[7:0] — IRQ[7:1], MODCLK Port QS[7:3] — TXD, PCS[3:1], PCS0/SS ADDR23/CS10/ECLK, ADDR[18:0], R/W, BERR, BR/CS0, BGACK/CS2 Group 3: HALT, RESET Group 4: MISO, MOSI, SCK Pin groups do not include QADC pins. See Tables A-11 through A-14 for information concerning the QADC. 3. Does not apply to HALT and RESET because they are open drain pins. Does not apply to port QS[7:0] (TXD, PCS[3:1], PCS0/SS, SCK, MOSI, MISO) in wired-OR mode. 4. Use of an active pulldown device is recommended. 5. Total operating current is the sum of the appropriate IDD, IDDSYN, and ISB values. IDD values include supply currents for device modules powered by VDDE and VDDI pins. 6. Current measured at maximum system clock frequency, all modules active. 7. The SRAM module will not switch into standby mode as long as VSB does not exceed VDD by more than 0.5 volts. The SRAM array cannot be accessed while the module is in standby mode. 8. When VDD is transitioning during power-up or power down sequence, and VSB is applied, current flows between the VSTBY and VDD pins, which causes standby current to increase toward the maximum transient condition specification. System noise on the VDD and VSTBY pins can contribute to this condition. 9. Power dissipation measured at system clock frequency, all modules active. Power dissipation can be calculated using the following expression: PD = Maximum VDD (Run IDD + IDDSYN + ISB) + Maximum V DDA (IDDA) 10. This parameter is periodically sampled rather than 100% tested. MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-5 Freescale Semiconductor, Inc. Table A-6 AC Timin g (VDD and V DDSYN = 5.0 Vdc ±5%, VSS = 0 Vdc, TA = TL to TH)1 Num Characteristic F1 Frequency of 1 Clock Period 1A ECLK Period Operation2 1B External Clock Input 2, 3 Clock Pulse Width Period 3 2A, 3A ECLK Pulse Width Freescale Semiconductor, Inc... 2B, 3B External Clock Input High/Low 3, 4 Time 3 Clock Rise and Fall Time 4A, 5A Rise and Fall Time — All Outputs except CLKOUT 4B, 5B External Clock Rise and Fall Time 4 Symbol Min Max Unit fsys — 20.97 MHz tcyc 47.7 — ns tEcyc 381 — ns tXcyc 47.7 — ns tCW 18.8 — ns tECW 183 — ns tXCHL 23.8 — ns tCrf — 5 ns trf — 8 ns tXCrf — 5 ns 4 Clock High to Address, FC, SIZE, RMC Valid tCHAV 0 23 ns 5 Clock High to Address, Data, FC, SIZE, RMC High Impedance tCHAZx 0 47 ns 6 Clock High to Address, FC, SIZE, RMC Invalid5 tCHAZn 0 — ns 7 Clock Low to AS, DS, CS Asserted tCLSA 0 23 ns 8A AS to DS or CS Asserted (Read)6 tSTSA –10 10 ns 8C Clock Low to IFETCH, IPIPE Asserted tCLIA 2 22 ns 11 Address, FC, SIZE, RMC Valid to AS, CS Asserted tAVSA 10 — ns 12 Clock Low to AS, DS, CS Negated tCLSN 2 23 ns Clock Low to IFETCH, IPIPE Negated tCLIN 2 22 ns 13 AS, DS, CS Negated to Address, FC, SIZE Invalid (Address Hold) tSNAI 10 — ns 14 AS, CS Width Asserted tSWA 80 — ns 12A 14A DS, CS Width Asserted (Write) tSWAW 36 — ns 14B AS, CS Width Asserted (Fast Write Cycle) tSWDW 32 — ns tSN 32 — ns tCHSZ — 47 ns Negated7 15 AS, DS, CS Width 16 Clock High to AS, DS, R/W High Impedance 17 AS, DS, CS Negated to R/ W Negated tSNRN 10 — ns 18 Clock High to R/W High tCHRH 0 23 ns 20 Clock High to R/W Low tCHRL 0 23 ns 21 R/W Asserted to AS, CS Asserted tRAAA 10 — ns 22 R/W Low to DS, CS Asserted (Write) tRASA 54 — ns 23 Clock High to Data Out Valid tCHDO — 23 ns 24 Data Out Valid to Negating Edge of AS, CS tDVASN 10 — ns 25 DS, CS Negated to Data Out Invalid (Data Out Hold) tSNDOI 10 — ns 26 Data Out Valid to DS, CS Asserted (Write) tDVSA 10 — ns tDICL 5 — ns 27 27A Data In Valid to Clock Low (Data Setup)5 Late BERR, HALT Asserted to Clock Low (Setup Time) tBELCL 15 — ns 28 AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated tSNDN 0 60 ns 29 DS, CS Negated to Data In Invalid (Data In Hold)8 tSNDI 0 — ns MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-6 Freescale Semiconductor, Inc. Table A-6 AC Timing (Continued) (VDD and V DDSYN = 5.0 Vdc ±5%, VSS = 0 Vdc, TA = TL to TH)1 Num 29A 30 Freescale Semiconductor, Inc... 30A Characteristic Symbol Min Max Unit DS, CS Negated to Data In High Impedance tSHDI — 48 ns CLKOUT Low to Data In Invalid (Fast Cycle Hold)88 tCLDI 10 — ns CLKOUT Low to Data In High Impedance88 tCLDH — 72 ns tDADI — 46 ns tCLBAN — 23 ns tBRAGA 1 — tcyc tGAGN 1 2 tcyc tGH 2 — tcyc 88, 9 10 31 DSACK[1:0] Asserted to Data In Valid 33 Clock Low to BG Asserted/Negated 35 BR Asserted to BG Asserted (RMC Not Asserted) 37 BGACK Asserted to BG Negated 39 BG Width Negated 39A BG Width Asserted 11 tGA 1 — tcyc R/W Width Asserted (Write or Read) tRWA 115 — ns 46A R/W Width Asserted (Fast Write or Read Cycle) tRWAS 70 — ns 47A Asynchronous Input Setup Time BR, BGACK, DSACK[1:0], BERR, AVEC, HALT tAIST 5 — ns 47B Asynchronous Input Hold Time tAIHT 12 — ns 48 DSACK[1:0] Asserted to BERR, HALT Asserted12 tDABA — 30 ns 53 Data Out Hold from Clock High tDOCH 0 — ns 54 Clock High to Data Out High Impedance tCHDH — 23 ns 55 R/W Asserted to Data Bus Impedance Change tRADC 32 — ns 56 RESET Pulse Width (Reset Instruction) tHRPW 512 — tcyc 57 BERR Negated to HALT Negated (Rerun) tBNHN 0 — ns 70 Clock Low to Data Bus Driven (Show) tSCLDD 0 23 ns 71 Data Setup Time to Clock Low (Show) tSCLDS 10 — ns 72 Data Hold from Clock Low (Show) tSCLDH 10 — ns 73 BKPT Input Setup Time tBKST 10 — ns 74 BKPT Input Hold Time tBKHT 10 — ns 75 Mode Select Setup Time tMSS 20 — tcyc 76 Mode Select Hold Time tMSH 0 — ns tRSTA 4 — tcyc tRSTR — 10 tcyc 46 13 77 RESET Assertion Time 78 RESET Rise Time14, 15 NOTES: 1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted. 2. The base configuration of the MC68336/376 requires a 20.97 MHz crystal reference. 3. When an external clock is used, minimum high and low times are based on a 50% duty cycle. The minimum allowable tXcyc period is reduced when the duty cycle of the external clock signal varies. The relationship between external clock input duty cycle and minimum tXcyc is expressed: Minimum tXcyc period = minimum tXCHL / (50% –external clock input duty cycle tolerance). 4. Parameters for an external clock signal applied while the internal PLL is disabled (MODCLK pin held low during reset). Does not pertain to an external VCO reference applied while the PLL is enabled (MODCLK pin held high during reset). When the PLL is enabled, the clock synthesizer detects successive transitions of the reference signal. If transitions occur within the correct clock period, rise/fall times and duty cycle are not critical. 5. Address access time = (2.5 + WS) tcyc – tCHAV – tDICL Chip select access time = (2 + WS) tcyc – tLSA – tDICL Where: WS = number of wait states. When fast termination is used (2 clock bus) WS = –1. MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-7 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. 6. Specification 9A is the worst-case skew between AS and DS or CS. The amount of skew depends on the relative loading of these signals. When loads are kept within specified limits, skew will not cause AS and DS to fall outside the limits shown in specification 9. 7. If multiple chip selects are used, CS width negated (specification 15) applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select. The CS width negated specification between multiple chip selects does not apply to chip selects being used for synchronous ECLK cycles. 8. Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast cycle reads. The user is free to use either hold time. 9. Maximum value is equal to (tcyc / 2) + 25 ns. 10. If the asynchronous setup time (specification 47A) requirements are satisfied, theDSACK[1:0] low to data setup time (specification 31) and DSACK[1:0] low to BERR low setup time (specification 48) can be ignored. The data must only satisfy the data-in to clock low setup time (specification 27) for the following clock cycle. BERR must satisfy only the late BERR low to clock low setup time (specification 27A) for the following clock cycle. 11. To ensure coherency during every operand transfer, BG will not be asserted in response to BR until after all cycles of the current operand transfer are complete and RMC is negated. 12. In the absence of DSACK[1:0], BERR is an asynchronous input using the asynchronous setup time (specification 47A). 13. After external RESET negation is detected, a short transition period (approximately 2 tcyc) elapses, then the SIM drives RESET low for 512 tcyc. 14. External assertion of the RESET input can overlap internally-generated resets. To insure that an external reset is recognized in all cases, RESET must be asserted for at least 590 CLKOUT cycles. 15. External logic must pull RESET high during this period in order for normal MCU operation to begin. 1 2 4 3 CLKOUT 5 68300 CLKOUT TIM Figure A-1 CLKOUT Output Timing Diagram 1B 2B 4B 3B EXTAL 5B NOTE: TIMING SHOWN WITH RESPECT TO 20% AND 70% VDD . PULSE WIDTH SHOWN WITH RESPECT TO 50% VDD . 68300 EXT CLK INPUT T Figure A-2 External Clock Input Timing Diagram MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-8 Freescale Semiconductor, Inc. 1A 2A 4A 3A ECLK 5A NOTE: TIMING SHOWN WITH RESPECT TO 20% AND 70% VDD. 68300 ECLK OUTPUT TI Freescale Semiconductor, Inc... Figure A-3 ECLK Output Timing Diagram MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-9 Freescale Semiconductor, Inc. S0 S1 S2 S3 S4 S5 CLKOUT 8 6 ADDR[23:20] FC[2:0] SIZ[1:0] 11 15 14 AS 13 Freescale Semiconductor, Inc... 9 DS 9A 12 CS 17 18 20 21 R/W 46 DSACK0 47A 28 DSACK1 29 31 DATA[15:0] 27 29A BERR 48 27A HALT 9C 12A 12A IFETCH 73 74 BKPT 47A 47B ASYNCHRONOUS INPUTS 68300 RD CYC TIM Figure A-4 Read Cycle Timing Diagram MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-10 Freescale Semiconductor, Inc. S0 S1 S2 S3 S4 S5 CLKOUT 6 8 ADDR[23:20] FC[2:0] SIZ[1:0] 11 15 14 AS 13 Freescale Semiconductor, Inc... 9 DS 21 9 12 CS 20 22 14A 17 R/W 46 DSACK0 47A 28 DSACK1 55 25 DATA[15:0] 23 26 54 53 BERR 48 27A HALT 74 73 BKPT 68300 WR CYC TIM Figure A-5 Write Cycle Timing Diagram MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-11 Freescale Semiconductor, Inc. S0 S1 S4 S5 S0 CLKOUT 8 6 ADDR[23:0] FC[2:0] SIZ[1:0] 14B AS 12 9 Freescale Semiconductor, Inc... DS CS 20 18 R/W 46A 30 27 30A DATA[15:0] 29A 73 29 BKPT 74 68300 FAST RD CYC TIM Figure A-6 Fast Termination Read Cycle Timing Diagram MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-12 Freescale Semiconductor, Inc. S0 S1 S4 S5 S0 CLKOUT 6 8 ADDR[23:0] FC[2:0] SIZ[1:0] 14B AS Freescale Semiconductor, Inc... 9 12 DS CS 46A 20 R/W 23 24 18 DATA[15:0] 73 25 BKPT 74 68300 FAST WR CYC TIM Figure A-7 Fast Termination Write Cycle Timing Diagram MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-13 Freescale Semiconductor, Inc. S0 S1 S2 S3 S4 S5 S98 A5 A5 A2 CLKOUT ADDR[23:0] 7 DATA[15:0] AS Freescale Semiconductor, Inc... 16 DS R/W DSACK0 DSACK1 47A BR 39A 35 BG 33 33 BGACK 37 68300 BUS ARB TIM Figure A-8 Bus Arbitration Timing Diagram — Active Bus Case MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-14 Freescale Semiconductor, Inc. A0 A5 A5 A2 A3 A0 CLKOUT ADDR[23:0] DATA[15:0] AS 47A 47A Freescale Semiconductor, Inc... BR 35 37 BG 33 33 47A BGACK 68300 BUS ARB TIM IDL Figure A-9 Bus Arbitration Timing Diagram — Idle Bus Case MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-15 Freescale Semiconductor, Inc. S0 S41 S42 S43 S0 S1 S2 CLKOUT 6 8 ADDR[23:0] 18 R/W 20 AS 9 12 15 DS Freescale Semiconductor, Inc... 71 72 70 DATA[15:0] 73 74 BKPT SHOW CYCLE START OF EXTERNAL CYCLE NOTE: Show cycles can stretch during clock phase S42 when bus accesses take longer than two cycles due to IMB module wait-state insertion. 68300 SHW CYC TIM Figure A-10 Show Cycle Timing Diagram MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-16 Freescale Semiconductor, Inc. S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 CLKOUT 6 8 6 ADDR[23:0] FC[2:0] SIZ[1:0] 14 11 11 14 13 AS 15 Freescale Semiconductor, Inc... 9 9 DS 9 17 17 21 12 21 12 CS 20 18 18 14A 46 R/W 46 29 25 55 DATA[15:0] 27 29A 53 23 54 68300 CHIP SEL TIM Figure A-11 Chip-Select Timing Diagram 77 78 RESET 75 DATA[15:0] 76 68300 RST/MODE SEL T Figure A-12 Reset and Mode Select Timing Diagram MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-17 Freescale Semiconductor, Inc. Table A-7 Background Debug Mode Timing (VDD = 5.0 Vdc ±5%, VSS = 0 Vdc, TA = T L to TH)1 Freescale Semiconductor, Inc... Num Characteristic Symbol Min Max Unit B0 DSI Input Setup Time tDSISU 15 — ns B1 DSI Input Hold Time tDSIH 10 — ns B2 DSCLK Setup Time tDSCSU 15 — ns B3 DSCLK Hold Time tDSCH 10 — ns B4 DSO Delay Time tDSOD — 25 ns B5 DSCLK Cycle Time tDSCCYC 2 — tcyc B6 CLKOUT Low to FREEZE Asserted/Negated tFRZAN — 50 ns B7 CLKOUT High to IFETCH High Impedance tIPZ — TBD ns tIP — TBD ns tDSCLO 1 — tcyc B8 CLKOUT High to IFETCH Valid B9 DSCLK Low Time NOTES: 1. All AC timing is shown with respect to 20% VDD and 70% V DD levels unless otherwise noted. CLKOUT FREEZE B3 B2 BKPT/DSCLK B9 B5 B1 B0 IFETCH/DSI B4 IPIPE/DSO 68300 BKGD DBM SER COM T Figure A-13 Background Debugging Mode Timing — Serial Communication CLKOUT B6 FREEZE B7 B6 IFETCH/DSI B8 68300 BDM FRZ TIM Figure A-14 Background Debugging Mode Timing — Freeze Assertion MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-18 Freescale Semiconductor, Inc. Table A-8 ECLK Bus Timing (VDD = 5.0 Vdc ±5%, V SS = 0 Vdc, TA = TL to T H)1 Freescale Semiconductor, Inc... Num Characteristic Symbol Min Max Unit tEAD — 48 ns 10 — ns Valid2 E1 ECLK Low to Address E2 ECLK Low to Address Hold tEAH E3 ECLK Low to CS Valid (CS delay) tECSD — 120 ns E4 ECLK Low to CS Hold tECSH 10 — ns E5 CS Negated Width tECSN 25 — ns E6 Read Data Setup Time tEDSR 25 — ns E7 Read Data Hold Time tEDHR 5 — ns E8 ECLK Low to Data High Impedance tEDHZ — 48 ns E9 CS Negated to Data Hold (Read) tECDH 0 — ns E10 CS Negated to Data High Impedance tECDZ — 1 tcyc E11 ECLK Low to Data Valid (Write) tEDDW — 2 tcyc E12 ECLK Low to Data Hold (Write) tEDHW 10 — ns E13 Address Access Time (Read)3 tEACC 308 — ns tEACS 236 — ns tEAS 1/2 — tcyc E14 Chip Select Access Time E15 Address Setup Time (Read)4 NOTES: 1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted. 2. When the previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low. 3. Address access time = tEcyc – tEAD – tEDSR. 4. Chip select access time = tEcyc – tECSD – tEDSR. MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-19 Freescale Semiconductor, Inc. CLKOUT 2A 3A ECLK 1A R/W E1 E2 ADDR[23:0] E3 E14 Freescale Semiconductor, Inc... CS E5 E4 E6 E15 E9 E13 DATA[15:0] READ WRITE E7 E8 E11 DATA[15:0] E10 WRITE E12 68300 E CYCLE TIM Figure A-15 ECLK Timing Diagram MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-20 Freescale Semiconductor, Inc. Table A-9 QSPI Timing (VDD and VDDSYN = 5.0 Vdc ± 5%, V SS = 0 Vdc, TA = TL to TH 200 pF load on all QSPI pins) 1 Num 1 2 3 Freescale Semiconductor, Inc... 4 5 Symbol Min Max Unit Operating Frequency Master Slave Function fQSPI DC DC 1/4 1/4 fsys fsys Cycle Time Master Slave tqcyc 4 4 510 — tcyc tcyc Enable Lead Time Master Slave tlead 2 2 128 — tcyc tcyc Enable Lag Time Master Slave tlag — 2 1/2 — SCK tcyc tsw 2 tcyc – 60 2 tcyc – n 255 tcyc — ns ns Sequential Transfer Delay Master Slave (Does Not Require Deselect) ttd 17 13 8192 — tcyc tcyc Data Setup Time (Inputs) Master Slave tsu 30 20 — — ns ns Data Hold Time (Inputs) Master Slave thi 0 20 — — ns ns Clock (SCK) High or Low Time Master Slave2 6 7 8 9 Slave Access Time ta — 1 tcyc 10 Slave MISO Disable Time tdis — 2 tcyc 11 Data Valid (after SCK Edge) Master Slave tv — — 50 50 ns ns Data Hold Time (Outputs) Master Slave tho 0 0 — — ns ns Rise Time Input Output tri tro — — 2 30 µs ns Fall Time Input Output tfi tfo — — 2 30 µs ns 12 13 14 NOTES: 1. All AC timing is shown with respect to 20% V DD and 70% VDD levels unless otherwise noted. 2. For high time, n = External SCK rise time; for low time, n = External SCK fall time. MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-21 Freescale Semiconductor, Inc. 3 2 PCS[3:0] OUTPUT 5 13 12 SCK CPOL=0 OUTPUT 4 1 SCK CPOL=1 OUTPUT 6 12 4 13 7 Freescale Semiconductor, Inc... MISO INPUT MSB IN DATA LSB IN 11 MOSI OUTPUT PD MSB OUT MSB IN 10 DATA LSB OUT PORT DATA 13 MSB OUT 12 QSPI MAST CPHA0 Figure A-16 QSPI Timing — Master, CPHA = 0 3 2 PCS[3:0] OUTPUT 5 13 12 1 SCK CPOL=0 OUTPUT 4 1 7 SCK CPOL=1 OUTPUT 12 4 13 6 MISO INPUT DATA MSB IN 11 MOSI OUTPUT PORT DATA MSB OUT LSB IN MSB 10 DATA LSB OUT 13 PORT DATA MSB 12 QSPI MAST CPHA1 Figure A-17 QSPI Timing — Master, CPHA = 1 MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-22 Freescale Semiconductor, Inc. 3 2 SS INPUT 5 13 12 SCK CPOL=0 INPUT 4 1 SCK CPOL=1 INPUT 12 4 Freescale Semiconductor, Inc... MISO OUTPUT 13 MSB OUT 11 10 11 8 DATA 9 LSB OUT PD MSB OUT 13 7 6 MOSI INPUT MSB IN DATA LSB IN MSB IN QSPI SLV CPHA0 Figure A-18 QSPI Timing — Slave, CPHA = 0 SS INPUT 5 1 13 4 12 SCK CPOL=0 INPUT 4 2 3 SCK CPOL=1 INPUT 12 13 10 10 8 MISO OUTPUT PD MSB OUT 9 11 DATA SLAVE LSB OUT PD 12 7 6 MOSI INPUT MSB IN DATA LSB IN QSPI SLV CPHA1 Figure A-19 QSPI Timing — Slave, CPHA = 1 MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-23 Freescale Semiconductor, Inc. Table A-10 Time Processor Unit Timing (VDD and VDDSYN = 5.0 Vdc ± 5%, VSS = 0 Vdc, TA = TL to TH, f sys = 20.97 MHz) 1, 2 Num 1 2 3 Rating Valid3, 4 CLKOUT High to TPU Output Channel CLKOUT High to TPU Output Channel Hold TPU Input Channel Pulse Width Symbol Min Max Unit tCHTOV 2 18 ns tCHTOH tTIPW 0 4 15 — ns tcyc Freescale Semiconductor, Inc... NOTES: 1. AC timing is shown with respect to 20% VDD and 70% V DD levels. 2. Timing not valid for external T2CLK input. 3. Maximum load capacitance for CLKOUT pin is 90 pF. 4. Maximum load capacitance for TPU output pins is 100 pF. CLKOUT 2 1 TPU OUTPUT TPU INPUT 3 TPU I/O TIM Figure A-20 TPU Timing Diagram MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-24 Freescale Semiconductor, Inc. Table A-11 QADC Maximum Ratings Freescale Semiconductor, Inc... Num Parameter Symbol Min Max Unit 1 Analog Supply, with reference to VSSA VDDA – 0.3 6.5 V 2 Internal Digital Supply, with reference to VSSI VDDI – 0.3 6.5 V 3 Reference Supply, with reference to VRL VRH – 0.3 6.5 V 4 VSS Differential Voltage VSSI – VSSA – 0.1 0.1 V 5 VDD Differential Voltage VDDI – VDDA – 6.5 6.5 V 6 VREF Differential Voltage VRH – VRL – 6.5 6.5 V 7 VRH to VDDA Differential Voltage VRH – VDDA – 6.5 6.5 V 8 VRL to VSSA Differential Voltage VRL – VSSA – 6.5 6.5 V 9 Disruptive Input Current1, 2, 3, 4, 5, 6, 7 VNEGCLAMP = – 0.3 V VPOSCLAMP = 8 V INA – 500 500 µA 10 Positive Overvoltage Current Coupling Ratio1, 5, 6, 8 PQA PQB KP 2000 2000 — — 11 Negative Overvoltage Current Coupling Ratio1, 5, 6, 8 PQA PQB KN 125 500 — — 12 Maximum Input Current3, 4, 6 VNEGCLAMP = – 0.3 V VPOSCLAMP = 8 V IMA – 25 25 mA NOTES: 1. Below disruptive current conditions, the channel being stressed has conversion values of $3FF for analog inputs greater than VRH and $000 for values less than VRL. This assumes that VRH ≤ VDDA and VRL ≥ VSSA due to the presence of the sample amplifier. Other channels are not affected by non-disruptive conditions. 2. Input signals with large slew rates or high frequency noise components cannot be converted accurately. These signals also affect the conversion accuracy of other channels. 3. Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do not affect device reliability or cause permanent damage. 4. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values using positive and negative clamp values, then use the larger of the calculated values. 5. This parameter is periodically sampled rather 100% tested. 6. Condition applies to one pin at a time. 7. Determination of actual maximum disruptive input current, which can affect operation, is related to external system component values. 8. Current coupling is the ratio of the current induced from overvoltage (positive or negative, through an external series coupling resistor), divided by the current induced on adjacent pins. A voltage drop may occur across the external source impedances of the adjacent pins, impacting conversions on these adjacent pins. MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-25 Freescale Semiconductor, Inc. Table A-12 QADC DC Electrical Characteristics (Operating) (VSSI and V SSA = 0Vdc, fQCLK = 2.1 MHz, TA = TL to TH) Freescale Semiconductor, Inc... Num Parameter Symbol Min Max Unit 1 Analog Supply1 VDDA 4.5 5.5 V 2 Internal Digital Supply 1 VDDI 4.5 5.5 V 3 VSS Differential Voltage VSSI – VSSA – 1.0 1.0 mV 4 VDD Differential Voltage VDDI – VDDA – 1.0 1.0 V 5 Reference Voltage Low2 VRL VSSA — V 6 Reference Voltage High2 VRH — VDDA V VRH – VRL 4.5 5.5 V 3 7 VREF Differential Voltage 8 Mid-Analog Supply Voltage VDDA/2 2.25 2.75 V 9 Input Voltage VINDC VSSA VDDA V 10 Input High Voltage, PQA and PQB VIH 11 Input Low Voltage, PQA and PQB VIL Hysteresis 4 12 Input 13 Output Low Voltage, PQA5 IOL = 5.3 mA 0.7 (VDDA) VDDA + 0.3 VSSA – 0.3 0.2 (VDDA) V V VHYS 0.5 — V VOL — — 0.4 0.2 V IDDA — — 1.0 10.0 mA µA IREF — 150 µA CL — 90 pF nA IOL = 10.0 µA Analog Supply Current 14 Normal Operation 6 Low-Power Stop 15 Reference Supply Current 16 Load Capacitance, PQA 17 Input Current, Channel Off 7 PQA PQB IOFF — — 250 150 18 Total Input Capacitance 8 PQA Not Sampling PQA Sampling PQB Not Sampling PQB Sampling CIN — — — — 15 20 10 15 pF NOTES: 1. Refers to operation over full temperature and frequency range. 2. To obtain full-scale, full-range results, VSSA ≤ VRL ≤ VINDC ≤ VRH ≤ VDDA. 3. Accuracy tested and guaranteed at VRH – VRL = 5.0V ± 10%. 4. Parameter applies to the following pins: Port A: PQA[7:0]/AN[59:58]/ETRIG[2:1] Port B: PQB[7:0]/AN[3:0]/AN[51:48]/AN[Z:W] 5. Open drain only. 6. Current measured at maximum system clock frequency with QADC active. 7. Maximum leakage occurs at maximum operating temperature. Current decreases by approximately one-half for each 10° C decrease from maximum temperature. 8. This parameter is periodically sampled rather than 100% tested. MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-26 Freescale Semiconductor, Inc. Table A-13 QADC AC Electrical Characteristics (Operating) (VDDI and V DDA = 5.0 Vdc ± 5%, VSSI and VSSA = 0Vdc, TA = TL to TH) Num Parameter Symbol Min Max Unit 1 QADC Clock (QCLK) Frequency1 fQCLK 0.5 2.1 MHz 2 QADC Clock Duty Cycle2, 3 High Phase Time (tPSL ≤ tPSH) tPSH 500 — ns 3 Conversion Cycles4 CC 18 32 QCLK cycles 18.0 32 Conversion Time2,4,5 fQCLK = 0.999 MHz6 Min = CCW/IST = %00 Max = CCW/IST = %11 Freescale Semiconductor, Inc... 4 fQCLK = 2.097 MHz1, 7 Min = CCW/IST = %00 Max = CCW/IST = %11 5 Stop Mode Recovery Time µs tCONV tSR 8.58 15.24 — 10 µs NOTES: 1. Conversion characteristics vary with fQCLK rate. Reduced conversion accuracy occurs at max fQCLK rate. 2. Duty cycle must be as close as possible to 75% to achieve optimum performance. 3. Minimum applies to 1.0 MHz operation. 4. Assumes that short input sample time has been selected (IST = 0). 5. Assumes that fsys = 20.97 MHz. 6. Assumes fQCLK = 0.999 MHz, with clock prescaler values of: QACR0: PSH = %01111, PSA = %1, PSL = 100) CCW: BYP = %0 7. Assumes fQCLK = 2.097 MHz, with clock prescaler values of: QACR0: PSH = %00110, PSA = %1, PSL = 010) CCW: BYP = %0 MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-27 Freescale Semiconductor, Inc. Table A-14 QADC Conversion Characteristics (Operating) (VDDI and VDDA = 5.0 Vdc ± 5%, V SSI and V SSA = 0 Vdc, TA = TL to TH, 0.5 MHz ≤ fQCLK ≤ 2.1 MHz, 2 clock input sample time) Freescale Semiconductor, Inc... Num Parameter Symbol Min Typ Max Unit 1 Count — 5 — mV Differential nonlinearity2 DNL — — ± 0.5 Counts 3 Integral nonlinearity INL — — ± 2.0 Counts 4 Absolute error2, 3, 4 fQCLK = 0.999 MHz5 PQA PQB fQCLK = 2.097 MHz6 PQA PQB AE — — — — ± 2.5 ± 2.5 Counts — — — — ± 4.0 ± 4.0 Source impedance at input7 RS — 20 — 1 Resolution 2 5 1 k¾ NOTES: 1. At V RH – VRL = 5.12 V, one count = 5 mV. 2. This parameter is periodically sampled rather than 100% tested. 3. Absolute error includes 1/2 count (2.5 mV) of inherent quantization error and circuit (differential, integral, and offset) error. Specification assumes that adequate low-pass filtering is present on analog input pins — capacitive filter with 0.01 µF to 0.1 µF capacitor between analog input and analog ground, typical source isolation impedance of 20 kΩ. 4. Assumes fsys = 20.97 MHz. 5. Assumes clock prescaler values of: QACR0: PSH = %01111, PSA = %1, PSL = 100) CCW: BYP = %0 6. Assumes clock prescaler values of: QACR0: PSH = %00110, PSA = %1, PSL = 010) CCW: BYP = %0 7. Maximum source impedance is application-dependent. Error resulting from pin leakage depends on junction leakage into the pin and on leakage due to charge-sharing with internal capacitance. Error from junction leakage is a function of external source impedance and input leakage current. In the following expression, expected error in result value due to junction leakage is expressed in voltage (Verrj): Verrj = RS X IOFF where IOFF is a function of operating temperature. Refer to Table A-12. Charge-sharing leakage is a function of input source impedance, conversion rate, change in voltage between successive conversions, and the size of the decoupling capacitor used. Error levels are best determined empirically. In general, continuous conversion of the same channel may not be compatible with high source impedance. MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-28 Freescale Semiconductor, Inc. Table A-15 FCSM Timing Characteristics (VDD = 5.0 Vdc ± 5%, Vss = 0 Vdc, TA = TL to TH) Freescale Semiconductor, Inc... Num Parameter 1 Symbol Min Max Unit 1 Input pin frequency fPCNTR 0 fsys/4 MHz 2 Input pin low time1 tPINL 2.0/fsys — µs 3 Input pin high time1 tPINH 2.0/fsys — µs 4 Clock pin to counter increment tPINC 4.5/fsys 6.5/fsys µs 5 Clock pin to new TBB value tPTBB 5.0/fsys 7.0/fsys µs 6 Clock pin to COF set ($FFFF) tPCOF 4.5/fsys 6.5/fsys µs 7 Pin to IN bit delay tPINB 1.5/fsys 2.5/fsys µs 8 Flag to IMB interrupt request tFIRQ 1.0/fsys 1.0/fsys µs 9 Counter resolution tCRES — 2.0/fsys µs 2 NOTES: 1. Value applies when using external clock. 2. Value applies when using internal clock. Minimum counter resolution depends on prescaler divide ratio selection. Table A-16 MCSM Timing Characteristics (VDD = 5.0 Vdc ± 5%, VSS = 0Vdc, TA = TL to T H) Num Parameter 1 Symbol Min Max Unit 1 Input pin frequency fPCNTR 0 fsys/4 MHz 2 Input pin low time1 tPINL 2.0/fsys — µs 3 Input pin high time1 tPINH 2.0/fsys — µs 4 Clock pin to counter increment tPINC 4.5/fsys 6.5/fsys µs 5 Clock pin to new TBB value tPTBB 5.0/fsys 7.0/fsys µs 6 Clock pin to COF set ($FFFF) tPCOF 4.5/fsys 6.5/fsys µs 7 Load pin to new counter value tPLOAD 2.5/fsys 3.5/fsys µs 8 Pin to IN bit delay tPINB 1.5/fsys 2.5/fsys µs 9 Flag to IMB interrupt request tFIRQ 1.0/fsys 1.0/fsys µs 10 Counter resolution tCRES — 2.0/fsys µs 2 NOTES: 1. Value applies when using external clock. 2. Value applies when using internal clock. Minimum counter resolution depends on prescaler divide ratio selection. MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-29 Freescale Semiconductor, Inc. Table A-17 SASM Timing Characteristics (VDD = 5.0 Vdc ± 5%, VSS = 0Vdc, TA = TL to T H) Freescale Semiconductor, Inc... Num Parameter 1 Input pin low time 2 Input pin high time 1 Symbol Min Max Unit tPINL 2.0/fsys — µs tPINH 2.0/fsys — µs 3 Input capture resolution tRESCA — 2.0/fsys µs 4 Pin to input capture delay tPCAPT 2.5/fsys 4.5/fsys µs 5 Pin to FLAG set tPFLAG 2.5/fsys 4.5/fsys µs 6 Pin to IN bit delay tPINB 1.5/fsys 2.5/fsys µs 7 OCT output pulse tOCT 2.0/fsys — µs 2.0/fsys µs resolution1 8 Compare 9 TBB change to FLAG set 10 TBB change to pin change 11 FLAG to IMB interrupt request2 tRESCM 2 tCFLAG 1.5/fsys 1.5/fsys µs tCPIN 1.5/fsys 1.5/fsys µs tFIRQ 1.0/fsys 1.0/fsys µs NOTES: 1. Minimum resolution depends on counter and prescaler divide ratio selection. 2. Time given from when new value is stable on time base bus. Table A-18 DASM Timing Characteristics (VDD = 5.0 Vdc ± 5%, V SS = 0 Vdc, T A = T L to T H) Num Parameter 1 Input pin low time 2 Input pin high time 1 Symbol Min Max Unit tPINL 2.0/fsys — µs tPINH 2.0/fsys — µs 3 Input capture resolution tRESCA — 2.0/fsys µs 4 Pin to input capture delay tPCAPT 2.5/fsys 4.5/fsys µs 5 Pin to FLAG set tPFLAG 2.5/fsys 4.5/fsys µs 6 Pin to IN bit delay tPINB 1.5/fsys 2.5/fsys µs 7 OCT output pulse tOCT 2.0/fsys — µs 8 Compare resolution1 tRESCM — 2.0/fsys µs 9 TBB change to FLAG set tCFLAG 1.5/fsys 1.5/fsys µs 10 TBB change to pin change tCPIN 1.5/fsys 1.5/fsys µs 11 FLAG to IMB interrupt request2 tFIRQ 1.0/fsys 1.0/fsys µs 2 NOTES: 1. Minimum resolution depends on counter and prescaler divide ratio selection. 2. Time given from when new value is stable on time base bus. MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-30 Freescale Semiconductor, Inc. Table A-19 PWMSM Timing Characteristics (VDD = 5.0Vdc ± 5%, VSS = 0 Vdc, TA = TL to T H) Freescale Semiconductor, Inc... Num Parameter Symbol Min Max Unit tPWMR — — µs 2 tPWMO 2.0/fsys — µs 3 1 1 PWMSM output resolution 2 PWMSM output pulse 3 PWMSM output pulse tPWMO 2.0/fsys 2.0/fsys µs 4 CPSM enable to output set PWMSM enabled before CPSM , DIV23 = 0 PWMSM enabled before CPSM , DIV23 = 1 tPWMP 3.5/fsys 6.5/fsys — µs 5 PWM enable to output set PWMSM enabled before CPSM , DIV23 = 0 PWMSM enabled before CPSM , DIV23 = 1 tPWME 3.5/fsys 5.5/fsys 4.5/fsys 6.5/fsys µs 6 FLAG to IMB interrupt request tFIRQ 1.5/fsys 2.5/fsys µs NOTES: 1. Minimum output resolution depends on counter and prescaler divide ratio selection. 2. Excluding the case where the output is always zero. 3. Excluding the case where the output is always zero. MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-31 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MC68336/376 USER’S MANUAL ELECTRICAL CHARACTERISTICS Rev. 15 Oct 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-32 ">
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