NXP MC68331 32 Bit Microcontroller Data Sheet
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Freescale Semiconductor
MC68331
User’s Manual
© MOTOROLA, INC. 1996
© Freescale Semiconductor, Inc., 2004. All rights reserved.
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TABLE OF CONTENTS
Title Paragraph Page
SECTION 1INTRODUCTION
SECTION 2NOMENCLATURE
SECTION 3OVERVIEW
System Integration Module (SIM) ........................................................... 3-1
Central Processing Unit (CPU32) ........................................................... 3-1
Queued Serial Module (QSM) ................................................................ 3-1
General-Purpose Timer (GPT) ............................................................... 3-2
System Block Diagram and Pin Assignment Diagrams .................................. 3-2
Address Space Maps ........................................................................... 3-10
SIM Reset Mode Selection ................................................................... 3-16
MCU Module Pin Function During Reset ............................................. 3-17
SECTION 4 SYSTEM INTEGRATION MODULE
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Title Paragraph Page
Low-Power STOP Operation .................................................................. 4-8
Clock Synthesizer Operation ................................................................ 4-10
Low-Power Operation ........................................................................... 4-15
Loss of Reference Signal ..................................................................... 4-16
Address Bus ................................................................................. 4-18
Address Strobe ............................................................................ 4-18
Data Bus ...................................................................................... 4-18
Data Strobe .................................................................................. 4-18
Read/Write Signal ........................................................................ 4-18
Size Signals ................................................................................. 4-18
Function Codes ............................................................................ 4-19
Data and Size Acknowledge Signals ........................................... 4-19
Bus Error Signal ........................................................................... 4-19
Autovector Signal ......................................................................... 4-20
Misaligned Operands ........................................................................... 4-21
Operand Transfer Cases ...................................................................... 4-22
Synchronization to CLKOUT ................................................................ 4-23
Read Cycle ................................................................................... 4-24
Write Cycle ................................................................................... 4-25
Fast Termination Cycles ....................................................................... 4-25
Breakpoint Acknowledge Cycle .................................................... 4-27
LPSTOP Broadcast Cycle ............................................................ 4-30
Bus Exception Control Cycles .............................................................. 4-30
Bus Errors .................................................................................... 4-32
Double Bus Faults ........................................................................ 4-32
Retry Operation ............................................................................ 4-33
Halt Operation .............................................................................. 4-33
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Title Paragraph Page
Slave (Factory Test) Mode Arbitration ......................................... 4-35
Show Cycles ................................................................................ 4-35
Reset Exception Processing ................................................................ 4-36
Reset Mode Selection .......................................................................... 4-37
Data Bus Mode Selection ............................................................. 4-38
Clock Mode Selection .................................................................. 4-40
Breakpoint Mode Selection .......................................................... 4-40
MCU Module Pin Function During Reset ............................................. 4-40
Reset States of SIM Pins ............................................................. 4-41
Reset States of Pins Assigned to Other MCU Modules ............... 4-42
Reset Processing Summary ................................................................. 4-44
Interrupt Exception Processing ............................................................ 4-45
Interrupt Priority and Recognition ......................................................... 4-45
Interrupt Acknowledge and Arbitration ................................................. 4-46
Interrupt Processing Summary ............................................................. 4-47
Interrupt Acknowledge Bus Cycles ....................................................... 4-48
Chip-Select Pin Assignment Registers ........................................ 4-51
Chip-Select Base Address Registers ........................................... 4-52
Chip-Select Option Registers ....................................................... 4-52
PORTC Data Register .................................................................. 4-54
Using Chip-Select Signals for Interrupt Acknowledge .......................... 4-54
Chip-Select Reset Operation ................................................................ 4-55
Pin Assignment Registers .................................................................... 4-57
Data Direction Registers ...................................................................... 4-57
SECTION 5 CENTRAL PROCESSING UNIT
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Title Paragraph Page
Status Register ............................................................................... 5-6
Alternate Function Code Registers ................................................ 5-6
Vector Base Register (VBR) ................................................................... 5-7
M68000 Family Compatibility ............................................................... 5-14
Special Control Instructions .................................................................. 5-14
Low Power Stop (LPSTOP) ......................................................... 5-14
Table Lookup and Interpolate (TBL) ............................................ 5-14
Exception Processing Sequence .......................................................... 5-17
M68000 Family Development Support ................................................. 5-17
Background Debugging Mode .............................................................. 5-18
Enabling BDM .............................................................................. 5-19
BDM Sources ............................................................................... 5-19
Entering BDM ............................................................................... 5-20
BDM Commands .......................................................................... 5-21
Background Mode Registers ........................................................ 5-21
Returning from BDM .................................................................... 5-22
Serial Interface ............................................................................. 5-22
Recommended BDM Connection ................................................. 5-24
Deterministic Opcode Tracking ............................................................ 5-24
On-Chip Breakpoint Hardware ............................................................. 5-25
SECTION 6QUEUED SERIAL MODULE
QSM Registers and Address Map .................................................................. 6-2
Low-Power Stop Operation ............................................................ 6-2
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Freeze Operation ........................................................................... 6-3
QSM Interrupts ............................................................................... 6-3
QSM Pin Control Registers .................................................................... 6-4
Control Registers ........................................................................... 6-7
Status Register ............................................................................... 6-7
Receive RAM ................................................................................. 6-8
Transmit RAM ................................................................................ 6-8
Command RAM .............................................................................. 6-8
QSPI Operating Modes ........................................................................ 6-10
Master Mode ................................................................................ 6-17
Master Wraparound Mode ........................................................... 6-19
Slave Mode .................................................................................. 6-20
Slave Wraparound Mode ............................................................. 6-21
Control Registers ......................................................................... 6-22
Status Register ............................................................................. 6-25
Data Register ............................................................................... 6-25
Definition of Terms ....................................................................... 6-26
Serial Formats .............................................................................. 6-26
Baud Clock ................................................................................... 6-26
Parity Checking ............................................................................ 6-27
Transmitter Operation .................................................................. 6-27
Receiver Operation ...................................................................... 6-29
Idle-Line Detection ....................................................................... 6-29
Receiver Wakeup ......................................................................... 6-30
Internal Loop ................................................................................ 6-31
SECTION 7GENERAL-PURPOSE TIMER
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Title Paragraph Page
Low-Power Stop Mode ........................................................................... 7-3
Input Capture/Output Compare Pin (IC4/OC5) ...................................... 7-6
Output Compare Pins (OC[1:4]) ............................................................. 7-6
Pulse Accumulator Input Pin (PAI) ......................................................... 7-7
Pulse-Width Modulation (PWMA, PWMB) .............................................. 7-7
Auxiliary Timer Clock Input (PCLK) ........................................................ 7-7
Input Capture Functions ....................................................................... 7-11
Output Compare Functions .................................................................. 7-12
Output Compare 1 ........................................................................ 7-13
Forced Output Compare .............................................................. 7-13
Input Capture 4/Output Compare 5 .............................................................. 7-13
APPENDIX A ELECTRICAL CHARACTERISTICS
APPENDIX B MECHANICAL DATA AND ORDERING INFORMATION
APPENDIX CDEVELOPMENT SUPPORT
M68MMDS1632 Modular Development System ...................................... C-1
M68MEVB1632 Modular Evaluation Board .............................................. C-2
APPENDIX D REGISTER SUMMARY
CPU32 Register Model ..................................................................... D-2
— Status Register ............................................................................ D-3
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GPTMCR — GPT Module Configuration Register ............................ D-4
GPTMTR — GPT Module Test Register (Reserved) ........................ D-5
ICR — GPT Interrupt Configuration Register .................................... D-5
DDRGP — Port GP Data Direction Register..................................... D-6
OC1M— OC1 Action Mask Register ................................................. D-6
TCNT — Timer Counter Register ..................................................... D-6
PACTL — Pulse Accumulator Control Register ................................ D-7
TIC[1:3] — Input Capture Registers 1–3 .......................................... D-8
TOC[1:4] — Output Compare Registers 1–4 ................................... D-8
TI4/O5 — Input Capture 4/Output Compare 5 Register .................... D-8
TCTL1/TCTL2 — Timer Control Registers 1 and 2........................... D-8
TMSK1/TMSK2 — Timer Interrupt Mask Registers 1 and 2 ............. D-9
TFLG1/TFLG2 — Timer Interrupt Flag Registers 1 and 2.............. D-10
CFORC — Compare Force Register............................................... D-10
PWMA/PWMB — PWM Registers A/B ........................................... D-12
PWMCNT — PWM Count Register ............................................... D-12
PWMBUFA — PWM Buffer Register A .......................................... D-12
PRESCL — GPT Prescaler ............................................................ D-12
System Integration Module ..................................................................... D-13
SIMCR — Module Configuration Register ...................................... D-14
SIMTR — System Integration Test Register ................................... D-15
SYNCR — Clock Synthesizer Control Register ............................. D-15
RSR — Reset Status Register ....................................................... D-16
SIMTRE — System Integration Test Register (ECLK) .................... D-17
PORTE0/PORTE1 — Port E Data Register .................................... D-17
DDRE — Port E Data Direction Register ........................................ D-17
PEPAR — Port E Pin Assignment Register .................................... D-17
PORTF0/PORTF1 — Port F Data Register..................................... D-18
DDRF — Port F Data Direction Register......................................... D-18
PFPAR — Port F Pin Assignment Register..................................... D-18
SYPCR — System Protection Control Register .............................. D-19
PICR — Periodic Interrupt Control Register.................................... D-20
PITR — Periodic Interrupt Timer Register ...................................... D-20
SWSR — Software Service Register .............................................. D-21
TSTMSRA — Master Shift Register A............................................. D-21
TSTMSRB — Master Shift Register B............................................. D-21
TSTSC — Test Module Shift Count ................................................ D-21
TSTRC — Test Module Repetition Count ....................................... D-21
CREG — Test Submodule Control Register .................................. D-21
DREG — Distributed Register......................................................... D-21
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PORTC — Port C Data Register ..................................................... D-21
CSPAR0 — Chip Select Pin Assignment Register 0....................... D-21
CSPAR1 — Chip Select Pin Assignment Register 1....................... D-22
CSBARBT — Chip Select Base Address Register Boot ROM ....... D-23
CSORBT — Chip Select Option Register Boot ROM...................... D-23
QSMCR — QSM Configuration Register ........................................ D-25
QTEST — QSM Test Register ........................................................ D-26
QILR — QSM Interrupt Level Register............................................ D-26
SCCR0 — SCI Control Register 0 .................................................. D-27
SCCR1 — SCI Control Register 1................................................... D-27
SCSR — SCI Status Register ......................................................... D-29
SCDR — SCI Data Register............................................................ D-30
PORTQS — Port QS Data Register ............................................... D-30
PQSPAR — PORT QS Pin Assignment Register ........................... D-30
SPCR0 — QSPI Control Register 0 ................................................ D-32
SPCR1 — QSPI Control Register 1 ............................................... D-33
SPCR2 — QSPI Control Register 2 ............................................... D-34
SPCR3 — QSPI Control Register 3 ............................................... D-34
RR[0:F] — Receive Data RAM........................................................ D-35
TR[0:F] — Transmit Data RAM ...................................................... D-35
CR[0:F] — Command RAM............................................................. D-36
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LIST OF ILLUSTRATIONS
Title Figure Page
Pin Assignments for 132-Pin Package ............................................................ 3-4
Pin Assignments for 144-Pin Package ............................................................ 3-5
Separate Supervisor and User Space Map................................................... 3-13
Supervisor Space (Separate Program/Data Space) Map ............................. 3-14
User Space (Separate Program/Data Space) Map ....................................... 3-15
System Integration Module Block Diagram ..................................................... 4-2
Periodic Interrupt Timer and Software Watchdog Timer ................................. 4-7
4-19 CPU Space Encoding for Interrupt Acknowledge.......................................... 4-55
Supervisor Programming Model Supplement.................................................. 5-3
Address Organization in Address Registers.................................................... 5-5
Common In-Circuit Emulator Diagram .......................................................... 5-18
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LIST OF ILLUSTRATIONS
(Continued)
Title Figure Page
Flowchart of QSPI Initialization Operation..................................................... 6-11
Flowchart of QSPI Master Operation (Part 1) ............................................... 6-12
Flowchart of QSPI Master Operation (Part 2) ............................................... 6-13
Flowchart of QSPI Master Operation (Part 3) ............................................... 6-14
Flowchart of QSPI Slave Operation (Part 1) ................................................. 6-15
Flowchart of QSPI Slave Operation (Part 2) ................................................. 6-16
Capture/Compare Unit Block Diagram .......................................................... 7-10
CLKOUT Output Timing Diagram.................................................................. A-12
External Clock Input Timing Diagram............................................................ A-12
Fast Termination Read Cycle Timing Diagram ............................................. A-15
Fast Termination Write Cycle Timing Diagram.............................................. A-16
Bus Arbitration Timing Diagram — Active Bus Case .................................... A-17
Bus Arbitration Timing Diagram — Idle Bus Case ........................................ A-18
A-13 Background Debugging Mode Timing Diagram—Serial Communication...... A-21
A-14 Background Debugging Mode Timing Diagram —Freeze Assertion............. A-21
132-Pin Plastic Surface Mount Package Pin Assignments ............................. B-2
144-Pin Plastic Surface Mount Package Pin Assignments ............................. B-3
Supervisor Programming Model Supplement..................................................D-2
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LIST OF TABLES
Table Title Page
MODCLK Pin and SWP Bit During Reset ...................................................... 4-6
MODCLK Pin and PTP Bit at Reset ............................................................... 4-7
System Frequencies from 32.768-kHz Reference ....................................... 4-14
4-14 DSACK, BERR, and HALT Assertion Results ............................................. 4-31
4-23 Chip Select Base and Option Register Reset Values .................................. 4-56
4-24 CSBOOT Base and Option Register Reset Values ..................................... 4-57
Background Mode Command Summary ...................................................... 5-21
CPU Generated Message Encoding ............................................................ 5-24
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LIST OF TABLES
(Continued)
Title Table Page
Effect of Parity Checking on Data Size .........................................................6-27
PWM Frequency Ranges Using 16.78-MHz/20.97-MHz System Clocks ......7-17
Typical Ratings, 16.78 MHz Operation .......................................................... A-2
Typical Ratings, 20.97 MHz Operation ......................................................... A-2
Background Debugging Mode Timing .......................................................... A-20
D-10 CSPAR0 and CSPAR1 Pin Assignment Field Encoding .............................. D-22
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SECTION 1INTRODUCTION
The MC68331, a highly-integrated 32-bit microcontroller, combines high-performance data manipulation capabilities with powerful peripheral subsystems. The MCU is built up from standard modules that interface through a common intermodule bus (IMB).
Standardization facilitates rapid development of devices tailored for specific applications.
The MCU incorporates a 32-bit CPU (CPU32), a system integration module (SIM), a general-purpose timer (GPT), and a queued serial module (QSM).
The MCU can either synthesize an internal clock signal from an external reference or use an external clock input directly. Operation with a 32.768-kHz reference frequency is standard. Because MCU operation is fully static, register and memory contents are not affected by a loss of clock.
High-density complementary metal-oxide semiconductor (HCMOS) architecture makes the basic power consumption of the MCU low. Power consumption can be minimized by stopping the system clock. The CPU32 instruction set includes a low-power stop (LPSTOP) command that efficiently implements this capability.
Documentation for the Modular Microcontroller Family follows the modular construction of the devices in the product line. Each microcontroller has a comprehensive user's manual that provides sufficient information for normal operation of the device. The user's manual is supplemented by module reference manuals that provide detailed information about module operation and applications. Refer to
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Advanced Microcontroller Unit (AMCU) Literature (BR1116/D) for a complete listing of documentation.
1
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1-2
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SECTION 2NOMENCLATURE
The following nomenclature is used throughout the manual. Nomenclature used only in certain sections, such as register bit mnemonics, is defined in those sections.
2.1 Symbols and Operators
>
<
=
≥
≤
≠
+
−
∗
/
— Addition
— Subtraction or negation (two's complement)
— Multiplication
— Division
— Greater
— Less
— Equal
— Equal or greater
— Equal or less
— Not equal
• — AND
✛
⊕
— Inclusive OR (OR)
— Exclusive OR (EOR)
NOT — Complementation
:
— Concatenation
⇒
⇔
±
— Transferred
— Exchanged
— Sign bit; also used to show tolerance
« — Sign extension
% — Binary value
$ — Hexadecimal value
2
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2.2 CPU32 Registers
2
A6–A0 — Address registers (index registers)
A7 (SSP) — Supervisor Stack Pointer
A7 (USP) — User Stack Pointer
CCR — Condition code register (user portion of SR)
D7–D0 — Data Registers (index registers)
DFC — Alternate function code register
PC — Program counter
SFC — Alternate function code register
SR — Status register
VBR — Vector base register
X — Extend indicator
N — Negative indicator
Z — Zero indicator
V — Two's complement overflow indicator
C — Carry/borrow indicator
2-2
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2.3 Pin and Signal Mnemonics
ADDR[23:0] — Address Bus
AS — Address Strobe
AVEC — Autovector
BERR — Bus Error
BG — Bus Grant
BGACK — Bus Grant Acknowledge
BKPT — Breakpoint
BR — Bus Request
CLKOUT — System Clock
CS[10:0] — Chip Selects
CSBOOT — Boot ROM Chip Select
DATA[15:0] — Data Bus
DS — Data Strobe
DSACK[1:0] — Data and Size Acknowledge
DSCLK — Development Serial Clock
DSI — Development Serial Input
DSO — Development Serial Output
EXTAL — External Crystal Oscillator Connection
FC[2:0] — Function Codes
FREEZE — Freeze
HALT — Halt
IC[4:1] — Input Capture
IFETCH — Instruction Fetch
IPIPE — Instruction Pipeline
IRQ[7:1] — Interrupt Request
MISO — Master In Slave Out
MODCLK — Clock Mode Select
MOSI — Master Out Slave In
OC[5:1] — Output Compare
PAI — Pulse Accumulator Input
PC[6:0] — SIM I/O Port C
PCLK — Pulse Accumulator Clock
PCS[3:0] — Peripheral Chip Selects
PE[7:0] — SIM I/O Port E
PF[7:0] — SIM I/O Port F
PGP[7:0] — GPT I/O Port
PQS[7:0] — QSM I/O Port
PWMA, PWMB — Pulse Width Modulator Output
QUOT — Quotient Out
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R/W — Read/Write
RESET — Reset
RMC — Read-Modify-Write Cycle
RXD — SCI Receive Data
SCK — QSPI Serial Clock
SIZ[1:0] — Size
SS — Slave Select
TSC — Three-State Control
TXD — SCI Transmit Data
XFC — External Filter Capacitor
XTAL — External Crystal Oscillator Connection
2-4
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2.4 Register Mnemonics
CFORC — GPT Compare Force Register
CREG — Test Control Register C
CR[0:F] — QSM Command RAM
CSBARBT — Chip-Select Base Address Register Boot ROM
CSBAR[0:10] — Chip-Select Base Address Registers [0:10]
CSORBT — Chip-Select Option Register Boot ROM
CSOR[0:10] — Chip-Select Option Register [0:10]
CSPAR[0:1] — Chip-Select Pin Assignment Registers [0:1]
DDRE — Port E Data Direction Register
DDRF — Port F Data Direction Register
DDRGP — Port GP Data Direction Register
DDRQS — Port QS Data Direction Register
DREG — SIM Test Module Distributed Register
GPTMCR — GPT Module Configuration Register
ICR — GPT Interrupt Configuration Register
OC1D — Output Compare 1 Action Data Register
OC1M — Output Compare 1 Action Mask Register
PACNT — Pulse Accumulator Counter
PACTL — Pulse Accumulator Control Register
PEPAR — Port E Pin Assignment Register
PFPAR — Port F Pin Assignment Register
PICR — Periodic Interrupt Control Register
PITR — Periodic Interrupt Timer Register
PORTC — Port C Data Register
PORTE — Port E Data Register
PORTF — Port F Data Register
PORTGP — Port GP Data Register
PORTQS — Port QS Data Register
PQSPAR — Port QS Pin Assignment Register
PRESCL — GPT Prescaler Register
PWMA — PWM Control Register A
PWMB — PWM Control Register B
PWMBUFA — PWM Buffer Register A
PWMBUFB — PWM Buffer Register B
PWMC — PWM Control Register C
PWMCNT — PWM Counter
QILR — QSM Interrupt Level Register
QIVR — QSM Interrupt Vector Register
QSMCR — QSM Configuration Register
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2
QTEST — QSM Test Register
RR[0:F] — QSM Receive Data RAM
RSR — Reset Status Register
SCCR[0:1] — SCI Control Registers [0:1]
SCDR — SCI Data Register
SCSR — SCI Status Register
SIMCR — SIM Module Configuration Register
SIMTR — System Integration Test Register
SIMTRE — System Integration Test Register (ECLK)
SPCR[0:3] — QSPI Control Registers [0:3]
SPSR — QSPI Status Register
SWSR — Software Watchdog Service Register
SYNCR — Clock Synthesizer Control Register
SYPCR — System Protection Control Register
TCNT — Timer Counter Register
TCTL[1:2] — Timer Control Registers [1:2]
TFLG[1:2] — Timer Interrupt Flag Registers [1:2]
TI4/O5 — Timer Input Capture 4/Output Compare 5 Register
TIC[1:3] — Timer Input Capture Registers [1:3]
TMSK[1:2] — Timer Interrupt Mask Register [1:2]
TOC[1:4] — Timer Output Compare Registers [1:4]
TR[0:F] — QSM Transmit Data RAM
TSTMSRA — Test Module Master Shift Register A
TSTMSRB — Test Module Master Shift Register B
TSTRC — Test Module Repetition Count Register
TSTSC — Test Module Shift Count Register
2.5 Conventions
Logic level one
is the voltage that corresponds to a Boolean true (1) state.
Logic level zero
is the voltage that corresponds to a Boolean false (0) state.
Set refers specifically to establishing logic level one on a bit or bits.
Clear refers specifically to establishing logic level zero on a bit or bits.
Asserted means that a signal is in active logic state. An active low signal changes
from logic level one to logic level zero when asserted, and an active high signal changes from logic level zero to logic level one.
Negated means that an asserted signal changes logic state. An active low signal
changes from logic level zero to logic level one when negated, and an active high signal changes from logic level one to logic level zero.
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A specific mnemonic within a range is referred to by mnemonic and number. A15 is
bit 15 of accumulator A; ADDR7 is line 7 of the address bus; CSOR0 is chip-select option register 0. A range of mnemonics is referred to by mnemonic and the numbers that define the range. AM[35:30] are bits 35 to 30 of accumulator M; CSOR[0:5] are the first six option registers.
Parentheses are used to indicate the content of a register or memory location, rather
than the register or memory location itself. (A) is the content of accumulator A. (M
:
M
+
1) is the content of the word at address M.
LSB means least significant bit or bits. MSB means most significant bit or bits. Refer-
ences to low and high bytes are spelled out.
LSW means least significant word or words. MSW means most significant word or
words.
ADDR is the address bus. ADDR[7:0] are the eight LSB of the address bus.
DATA is the data bus. DATA[15:8] are the eight MSB of the data bus.
2
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SECTION 3OVERVIEW
This section contains information about the entire modular microcontroller. It lists the features of each module, shows device functional divisions and pin assignments, summarizes signal and pin functions, discusses the intermodule bus, and provides system memory maps. Timing and electrical specifications for the entire microcontroller and
for individual modules are provided in APPENDIX A ELECTRICAL CHARACTERIS-
TICS. Comprehensive module register descriptions and memory maps are provided
in APPENDIX D REGISTER SUMMARY.
3.1 MCU Features
The following paragraphs highlight capabilities of each of the microcontroller modules.
Each module is discussed separately in a subsequent section of this user's manual.
3.1.1 System Integration Module (SIM)
• External Bus Support
• Programmable Chip-Select Outputs
• System Protection Logic
• Watchdog Timer, Clock Monitor, and Bus Monitor
• System Protection Logic
• PLL System Clock for Low Power Operation
• Background Debugging Mode
3.1.2 Central Processing Unit (CPU32)
• Instruction Set Supports Controller Applications
• 32-Bit Architecture
• Virtual Memory Implementation
• Loop Mode of Instruction Execution
• Table Lookup and Interpolate Instruction
• Improved Exception Handling for Controller Applications
• Trace on Change of Flow
• Hardware Breakpoint Signal, Background Mode
• Fully Static Operation
3.1.3 Queued Serial Module (QSM)
• Serial Communication Interface (SCI), Enhanced Universal Asynchronous Receiver Transmitter (UART) with Modulus Baud Rate, Parity
• Queued Serial Peripheral Interface (SPI), High Speed Bidirectional Interface, 80-
Byte RAM, Up to 16 Automatic Transfers
• Dual Function I/O Ports
• Continuous Cycling, 8 to 16 Bits per Transfer
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3.1.4 General-Purpose Timer (GPT)
• Two 16-Bit Free-Running Counters With One Nine-Stage Prescaler
• Three Input Capture Channels
• Four Output Compare Channels
• One Input Capture/Output Compare Channel
• One Pulse Accumulator/Event Counter Input
• Two Pulse-Width Modulation Outputs
• Optional External Clock Input
3.2 System Block Diagram and Pin Assignment Diagrams
Figure 3-1 is a functional diagram of the MCU. Although diagram blocks represent the
relative size of the physical modules, there is not a one-to-one correspondence between location and size of blocks in the diagram and location and size of integrated-
circuit modules. Figure 3-2 shows the pin assignments of the 132-pin plastic surface-
mount package. Figure 3-3 shows the pin assignments of the 144-pin plastic surface-
mount package. Refer to APPENDIX B MECHANICAL DATA AND ORDERING IN-
FORMATION for package dimensions. All pin functions and signal names are shown
in this drawing. Refer to subsequent paragraphs in this section for pin and signal descriptions.
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PWMA
PWMB
PCLK
PAI
PGP7/IC4/OC5/OC1
PGP6/OC4/OC1
PGP5/OC3/OC1
PGP4/OC2/OC1
PGP3/OC1
PGP2/IC3
PGP1/IC2
PGP0/IC1
RXD
PQS7/TXD
PQS6/PCS3
PQS5/PCS2
PQS4/PCS1
PQS3/PCS0/SS
PQS2/SCK
PQS1/MOSI
PQS0/MISO
BKPT/DSCLK
IFETCH/DSI
IPIPE/DSO
Freescale Semiconductor, Inc.
PWMA
PWMB
PCLK
PAI
PGP7/IC4/OC5/OC1
PGP6/OC4/OC1
PGP5/OC3/OC1
PGP4/OC2/OC1
PGP3/OC1
PGP2/IC3
PGP1/IC2
PGP0/IC1
GPT
IMB
CHIP
SELECTS
BR
BG
BGACK
CS[10:0]
FC2
FC1
FC0
ADDR[23:0]
EBI
SIZ1
SIZ0
DS
AS
RMC
AVEC
DSACK1
DSACK0
DATA[15:0]
TXD
PCS3
PCS2
PCS1
PCS0/SS
SCK
MOSI
MISO
QSM CPU32
IRQ[7:1]
MODCLK
CLOCK
TSC
TEST
QUOT
Figure 3-1 MCU Block Diagram
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CSBOOT
ADDR23/CS10
PC6/ADDR22/CS9
PC5/ADDR21/CS8
PC4/ADDR20/CS7
PC3/ADDR19/CS6
PC2/FC2/CS5
PC1/FC1/CS4
PC0/FC0/CS3
BGACK/CS2
BG/CS1
BR/CS0
ADDR[18:0]
PE7/SIZ1
PE6/SIZ0
PE5/DS
PE4/AS
PE3/RMC
PE2/AVEC
PE1/DSACK1
PE0/DSACK0
3
DATA[15:0]
R/W
RESET
HALT
BERR
PF7/IRQ7
PF6/IRQ6
PF5/IRQ5
PF4/IRQ4
PF3/IRQ3
PF2/IRQ2
PF1/IRQ1
PF0/MODCLK
CLKOUT
XTAL
EXTAL
TSC
FREEZE/QUOT
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3
ADDR16
V
DD
V
SS
ADDR17
ADDR18
PQS0/MISO
PQS1/MOSI
PQS2/SCK
PQS3/PCS0/SS
PQS4/PCS1
PQS5/PCS2
PQS6/PCS3
V
DD
ADDR7
ADDR8
V
DD
V
SS
ADDR9
ADDR10
ADDR11
ADDR12
V
SS
ADDR13
ADDR14
ADDR15
V
DD
NC
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
41
42
43
44
37
38
39
40
45
46
47
48
49
50
33
34
35
36
29
30
31
32
25
26
27
28
21
22
23
24
18
19
20
MC68331
Figure 3-2 Pin Assignments for 132-Pin Package
V
DD
BGACK/CS2
BG/CS1
BR/CS0
CSBOOT
DATA0
DATA1
DATA2
DATA3
V
DD
V
SS
DATA4
DATA5
DATA6
DATA7
V
SS
DATA8
DATA9
DATA10
DATA11
V
DD
V
SS
DATA12
DATA13
DATA14
DATA15
ADDR0
PE0/DSACK0
PE1/DSACK1
PE2/AVEC
PE3/RMC
PE5/DS
V
DD
91
90
89
88
95
94
93
92
87
86
85
84
99
98
97
96
103
102
101
100
107
106
105
104
111
110
109
108
116
115
114
113
112
331 132-PIN QFP
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NC
V
SS
FC0/CS3
FC1/CS4
FC2/CS5
ADDR19/CS6
ADDR20/CS7
ADDR21/CS8
ADDR22/CS9
ADDR23/CS10
V
V
DD
SS
PCLK
PWMB
PWMA
NC
NC
V
NC
V
DD
SS
NC
PAI
GP7/IC4/OC5/OC1
PGP6/OC4
V
DD
V
SS
NC
PGP5/OC3/OC1
PGP4/OC2/OC1
PGP3/OC1
PGP2/IC3
PGP1/IC2
PGP0/IC1
V
NC
SS
NC
29
30
31
32
25
26
27
28
33
34
35
36
21
22
23
24
17
18
19
20
13
14
15
16
9
10
11
12
7
8
5
6
3
4
1
2
MC68331
331 144-PIN QFP
Figure 3-3 Pin Assignments for 144-Pin Package
3.3 Pin Descriptions
The following tables are a summary of the functional characteristics of MCU pins. Ta-
ble 3-1 shows types of output drivers. Table 3-2 shows all inputs and outputs. Digital
inputs and outputs use CMOS logic levels. An entry in the Discrete I/O column indicates that a pin can also be used for general-purpose input, output, or both. The I/O
port designation is given when it applies. Table 3-3 shows characteristics of power
pins. Refer to Figure 3-1 for port organization.
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3-5
81
80
79
78
85
84
83
82
77
76
75
74
73
89
88
87
86
93
92
91
90
101
100
99
98
97
96
95
94
109
108
107
106
105
104
103
102
NC
V
SS
PE4/AS
PE6/SIZ0
PE7/SIZ1
R/W
PF0/MODCLK
PF1/IRQ1
PF2/IRQ2
PF3/IRQ3
PF4/IRQ4
PF5/IRQ5
PF6/IRQ6
PF7/IRQ7
BERR
HALT
RESET
V
SS
CLKOUT
V
DD
NC
XFC
V
DD
EXTAL
V
DD
XTAL
V
SS
FREEZE/QUOT
TSC
BKPT/DSCLK
IFETCH/DSI
IPIPE/DSO
RXD
PQS7/TXD
V
SS
NC
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3-6
Type
A
Aw
B
Bo
Table 3-1 MCU Driver Types
I/O Description
O Output-only signals that are always driven; no external pull-up required
O Type A output with weak P-channel pull-up during reset
O Three-state output that includes circuitry to pull up output before high impedance is established, to ensure rapid rise time. An external holding resistor is required to maintain logic level while the pin is in the high-impedance state.
O Type B output that can be operated in an open-drain mode
Table 3-2 MCU Pin Characteristics
Pin
Mnemonic
ADDR23/CS10/ECLK
ADDR[22:19]/CS[9:6]
ADDR[18:0]
AS
AVEC
BERR
BG/CS1
BGACK/CS2
BKPT/DSCLK
BR/CS0
CLKOUT
CSBOOT
DATA[15:0]1
DS
DSACK1
DSACK0
DSI/IFETCH
DSO/IPIPE
EXTAL2
FC[2:0]/CS[5:3]
FREEZE/QUOT
IC4/OC5
IC[3:1]
HALT
A
Bo
IRQ[7:1] B
MISO
MODCLK
1
Bo
B
MOSI Bo
A
A
B
B
—
A
A
A
A
—
—
OC[4:1]
PAI
2
PCLK
2
PCSO/SS
PCS[3:1]
PWMA, PWMB
R/W
RESET
RMC
Bo
Bo
A
A
Bo
B
A
B
Aw
B
B
B
—
B
Output
Driver
A
A
B
B
A
B
Y
Y
Y
Y
Y
Y
Y
Y
Y
—
Y
—
Y
Y
Y
Y
—
Input
Synchronized
Y
Y
Y
Y
Y
Y
—
—
Y
Y
—
Y
Y
Y
Y
Y
Y
Y
Y
—
Y
Y
N
Y
Y
Y
Y
Y
N
N
N
Y
—
Special
N
—
Y
Input
Hysteresis
N
N
N
N
N
N
—
—
N
N
—
N
Y
N
N
Y
N
Y
Y
—
I/O
I/O
I/O
I
I
I/O
—
I/O
I/O
—
O
—
I/O
I/O
I/O
—
—
—
—
—
I/O
—
—
—
—
Discrete
I/O
O
O
—
I/O
I/O
—
I/O
I/O
O
—
—
I/O
PE1
PE0
—
—
—
PC[2:0]
—
GP4
GP[7:5]
—
PF[7:1]
PQS0
PF0
PQS1
GP[3:0]
—
—
Port
Designation
—
PC[6:3]
—
PE5
PE2
—
—
—
—
PE4
—
—
—
—
PQS3
PQS[6:4]
—
—
—
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Table 3-2 MCU Pin Characteristics (Continued)
Pin
Mnemonic
RXD
SCK
SIZ[1:0]
TSC
TXD
XFC
3
XTAL
3
Output
Driver
—
Bo
B
—
Bo
—
—
Input
Synchronized
N
Y
Y
Y
Y
—
—
Input
Hysteresis
N
Y
N
Y
Y
—
—
Discrete
I/O
—
I/O
I/O
—
I/O
Special
Special
Port
Designation
—
PQS2
PE[7:6]
—
PQS7
—
—
1. DATA[15:0] are synchronized during reset only. MODCLK is synchronized only when used as an input port pin.
2. EXTAL, XFC, and XTAL are clock reference connections.
3. PAI and PCLK can be used for discrete input, but are not part of an I/O port.
Table 3-3 MCU Power Connections
Pin Mnemonic
V
DDSYN
V
SSE
/V
DDE
V
SS
I/V
DDI
Description
Clock Synthesizer Power
External Periphery Power (Source and Drain)
Internal Module Power (Source and Drain)
3.4 Signal Descriptions
The following tables define MCU signals. Table 3-4 shows signal origin, type, and ac-
tive state. Table 3-5 describes signal functions. Both tables are sorted alphabetically
by mnemonic. MCU pins often have multiple functions. More than one description can apply to a pin.
3
Signal
Name
ADDR[23:0]
AS
AVEC
BERR
BG
BGACK
BKPT
BR
CLKOUT
CS[10:0]
CSBOOT
DATA[15:0]
DS
DSACK[1:0]
DSCLK
DSI
DSO
EXTAL
Table 3-4 Signal Characteristics
MCU
Module
SIM
SIM
SIM
SIM
SIM
SIM
CPU32
SIM
SIM
SIM
SIM
SIM
SIM
SIM
CPU32
CPU32
CPU32
SIM
Input
Input
Output
Output
Output
Bus
Output
Input
Signal
Type
Bus
Output
Input
Input
Output
Input
Input
Input
Output
Input
0
—
0
0
0
0
—
0
Active
State
—
0
0
0
0
0
Serial Clock
(Serial Data)
(Serial Data)
—
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Signal Name
Address Bus
Address Strobe
Autovector
Bus Error
Bus Grant
Bus Grant Acknowledge
Breakpoint
Bus Request
System Clockout
Chip Selects
Boot Chip Select
Data Bus
Table 3-4 Signal Characteristics (Continued)
PCS[3:0]
PE[7:0]
PF[7:0]
PGP[7:0]
PQS[7:0]
PCLK
PWMA, PWMB
QUOT
RESET
RMC
R/W
RXD
SCK
SIZ[1:0]
SS
TSC
TXD
XFC
XTAL
Signal
Name
FC[2:0]
FREEZE
HALT
IC[4:1]
IFETCH
IPIPE
IRQ[7:1]
MISO
MODCLK
MOSI
OC[5:1]
PAI
PC[6:0]
SIM
SIM
SIM
QSM
QSM
SIM
QSM
SIM
QSM
SIM
SIM
GPT
QSM
GPT
GPT
SIM
QSM
SIM
SIM
MCU
Module
SIM
SIM
SIM
GPT
CPU32
CPU32
SIM
QSM
SIM
QSM
GPT
GPT
SIM
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
Output
Output
Input/Output
Output
Output
Input
Input/Output
Output
Input
Input
Output
Input
Output
Signal
Type
Output
Output
Input/Output
Input
Output
Output
Input
Input/Output
Input
Input/Output
Output
Input
Output
—
—
0
—
0
0
1/0
—
—
(Port)
(Port)
(Port)
(Port)
—
—
—
—
—
—
—
0
—
—
—
—
—
(Port)
Active
State
—
1
0
—
—
Table 3-5 Signal Function
Mnemonic Function
ADDR[23:0] 24-bit address bus
AS Indicates that a valid address is on the address bus
AVEC
BERR
BG
BGACK
Requests an automatic vector during interrupt acknowledge
Indicates that a bus error has occurred
Indicates that the MCU has relinquished the bus
Indicates that an external device has assumed bus mastership
BKPT
BR
CLKOUT
CS[10:0]
Signals a hardware breakpoint to the CPU
Indicates that an external device requires bus mastership
System clock output
Select external devices at programmed addresses
CSBOOT Chip select for external boot start-up ROM
DATA[15:0] 16-bit data bus
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Table 3-5 Signal Function (Continued)
Freeze
Halt
Signal Name
Data Strobe
Mnemonic
DS
Data and Size Acknowledge
Development Serial In, Out, Clock
DSACK[1:0] Provide asynchronous data transfers and dynamic bus sizing
DSI, DSO,
DSCLK
Serial I/O and clock for background debugging mode
Crystal Oscillator
Function Codes
EXTAL, XTAL Connections for clock synthesizer circuit reference; a crystal or an external oscillator can be used
FC[2:0] Identify processor state and current address space
Input Capture
FREEZE
HALT
IC[3:1]
IC4/OC5
Function
During a read cycle, indicates when it is possible for an external device to place data on the data bus. During a write cycle, indicates that valid data is on the data bus.
Indicates that the CPU has entered background mode
Suspend external bus activity
When a specified transition is detected on an input capture pin, the value in an internal GPT counter is latched
Can be configured for either an input capture or output compare Input Capture 4/
Output Compare 5
Instruction Pipeline
Interrupt Request Level
Master In Slave Out
Clock Mode Select
Master Out Slave In
Output Compare
IPIPE, IFETCH Indicate instruction pipeline activity
IRQ[7:1] Provides an interrupt priority level to the CPU
MISO Serial input to QSPI in master mode; serial output from QSPI in slave mode
MODCLK Selects the source and type of system clock
MOSI
OC[5:1]
Serial output from QSPI in master mode; serial input to QSPI in slave mode
Change state when the value of an internal GPT counter matches a value stored in a GPT control register
Pulse Accumulator Input
Port C
Auxiliary Timer Clock Input
Peripheral Chip Select
Port E
Port F
Port GP
Port QS
PAI
PC[6:0]
PCLK
PCS[3:0]
PE[7:0]
PF[7:0]
PGP[7:0]
PQS[7:0]
Signal input to the pulse accumulator
SIM digital output port signals
External clock dedicated to the GPT
QSPI peripheral chip selects
SIM digital I/O port signals
SIM digital I/O port signals
GPT digital I/O port signals
QSM digital I/O port signals
Pulse-Width Modulation
Quotient Out
Reset
Read-Modify-Write Cycle
Read/Write
SCI Receive Data
QSPI Serial Clock
Size
Slave Select
Three-State Control
SCI Transmit Data
External Filter Capacitor
PWMA, PWMB Output for PWM
QUOT Provides the quotient bit of the polynomial divider
RESET
RMC
System reset
Indicates an indivisible read-modify-write instruction
R/W
RXD
SCK
SIZ[1:0]
SS
Indicates the direction of data transfer on the bus
Serial input to the SCI
Clock output from QSPI in master mode; clock input to QSPI in slave mode
Indicates the number of bytes to be transferred during a bus cycle
TSC
TXD
XFC
Causes serial transmission when QSPI is in slave mode; causes mode fault in master mode
Places all output drivers in a high-impedance state
Serial output from the SCI
Connection for external phase-locked loop filter capacitor
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3.5 Intermodule Bus
The intermodule bus (IMB) is a standardized bus developed to facilitate both design and operation of modular microcontrollers. It contains circuitry to support exception processing, address space partitioning, multiple interrupt levels, and vectored interrupts. The standardized modules in the MCU communicate with one another and with external components through the IMB. The IMB in the MCU uses 24 address and 16 data lines.
3.6 System Memory Map
Figure 3-4, Figure 3-5, Figure 3-6, Figure 3-7, and Figure 3-8 are MCU memory
maps. Figure 3-4 shows IMB addresses of internal registers. Figure 3-5 through Fig-
ure 3-8 show system memory maps that use different external decoding schemes.
3.6.1 Internal Register Map
In Figure 3-4, IMB ADDR[23:20] are represented by the letter Y. The value represent-
ed by Y determines the base address of MCU module control registers. In M68300 microcontrollers, Y is equal to M111, where M is the logic state of the module mapping
(MM) bit in the system integration module configuration register (SIMCR).
3.6.2 Address Space Maps
Figure 3-5 shows a single memory space. Function codes FC[2:0] are not decoded
externally so that separate user/supervisor or program/data spaces are not provided.
In Figure 3-6, FC2 is decoded, resulting in separate supervisor and user spaces.
FC[1:0] are not decoded, so that separate program and data spaces are not provided.
In Figure 3-7 and Figure 3-8, FC[2:0] are decoded, resulting in four separate memory
spaces: supervisor/program, supervisor/data, user/program and user/data.
All exception vectors are located in supervisor data space, except the reset vector, which is located in supervisor program space. Only the initial reset vector is fixed in the processor's memory map. Once initialization is complete, there are no fixed assignments. Since the vector base register (VBR) provides the base address of the vec-
tor table, the vector table can be located anywhere in memory. Refer to SECTION 5
CENTRAL PROCESSING UNIT for more information concerning memory manage-
ment, extended addressing, and exception processing. Refer to SECTION 4 SYSTEM
INTEGRATION MODULE for more information concerning function codes and ad-
dress space types.
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$YFF000
$YFF900
$YFF93F
GPT
$YFFA00
$YFFA7F
$YFFA80
$YFFAFF
SIM
RESERVED
$YFFC00
QSM
$YFFDFF
$YFFFFF
Y = M111, where M is the state of the module mapping (MM) bit in the SIM configuration register.
331 ADDRESS MAP
Figure 3-4 Internal Register Memory Map
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$
000000
COMBINED
SUPERVISOR
AND USER
SPACE
$7FF000
INTERNAL REGISTERS (MM = 0)
VECTOR
NUMBER
12
13
14
15
16–23
24
25
26
27
28
29
30
31
32–47
48–58
59–63
64–255
6
7
4
5
2
3
0
1
8
9
10
11
VECTOR
OFFSET
0030
0034
0038
003C
0040–005C
006C
0064
0068
006C
0070
0074
0078
007C
0080–00BC
00C0–00EB
00EC–00FC
0100–03FC
0000
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028
002C
TYPE OF
EXCEPTION
RESET — INITIAL STACK POINTER
RESET — INITIAL PC
BUS ERROR
ADDRESS ERROR
ILLEGAL INSTRUCTION
ZERO DIVISION
CHK, CHK2 INSTRUCTIONS
TRAPcc, TRAPV INSTRUCTIONS
PRIVILEGE VIOLATION
TRACE
LINE 1010 EMULATOR
LINE 1111 EMULATOR
HARDWARE BREAKPOINT
(RESERVED COPROCESSOR PROTOCOL VIOLATION)
FORMAT ERROR AND UNINITIALIZED INTERRUPT
FORMAT ERROR AND UNINITIALIZED INTERRUPT
(UNASSIGNED, RESERVED)
SPURIOUS INTERRUPT
LEVEL 1 INTERRUPT AUTOVECTOR
LEVEL 2 INTERRUPT AUTOVECTOR
LEVEL 3 INTERRUPT AUTOVECTOR
LEVEL 4 INTERRUPT AUTOVECTOR
LEVEL 5 INTERRUPT AUTOVECTOR
LEVEL 6 INTERRUPT AUTOVECTOR
LEVEL 7 INTERRUPT AUTOVECTOR
TAP INSTRUCTION VECTORS (0–15)
(RESERVED, COPROCESSOR)
(UNASSIGNED, RESERVED)
USER-DEFINED VECTORS
$XX0000
$XX03FC
$YFF000
$YFF900
GPT
$YFF93F
$YFFA00
RESERVED
$YFFA7F
$YFFA80
$YFFAFF
QSM
$YFFC00
$YFFDFF
$FF0000
$FFFFFF
INTERNAL REGISTERS (MM = 1)
$YFFFFF
NOTES:
1. Location of the exception vector table is determined by the vector base register. The vector address is the sum of the vector base register and the vector offset.
2. Location of the module control registers is determined by the state of the module mapping (MM) bit in the SIM configuration register.
Y = M111, where M is the state of the MM bit.
3. Unused addresses within the internal register block are mapped externally. "RESERVED" blocks are not mapped externally.
331 S/U COMB MAP
Figure 3-5 Overall Memory Map
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$000000
SUPERVISOR
SPACE
$7FF000
INTERNAL REGISTERS
VECTOR
NUMBER
12
13
14
15
16–23
24
25
26
27
28
29
30
31
32–47
48–58
59–63
64–255
6
7
4
5
2
3
0
1
8
9
10
11
VECTOR
OFFSET
0030
0034
0038
003C
0040–005C
006C
0064
0068
006C
0070
0074
0078
007C
0080–00BC
00C0–00EB
00EC–00FC
0100–03FC
0000
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028
002C
TYPE OF
EXCEPTION
RESET — INITIAL STACK POINTER
RESET — INITIAL PC
BUS ERROR
ADDRESS ERROR
ILLEGAL INSTRUCTION
ZERO DIVISION
CHK, CHK2 INSTRUCTIONS
TRAPcc, TRAPV INSTRUCTIONS
PRIVILEGE VIOLATION
TRACE
LINE 1010 EMULATOR
LINE 1111 EMULATOR
HARDWARE BREAKPOINT
(RESERVED COPROCESSOR PROTOCOL VIOLATION)
FORMAT ERROR AND UNINITIALIZED INTERRUPT
FORMAT ERROR AND UNINITIALIZED INTERRUPT
(UNASSIGNED, RESERVED)
SPURIOUS INTERRUPT
LEVEL 1 INTERRUPT AUTOVECTOR
LEVEL 2 INTERRUPT AUTOVECTOR
LEVEL 3 INTERRUPT AUTOVECTOR
LEVEL 4 INTERRUPT AUTOVECTOR
LEVEL 5 INTERRUPT AUTOVECTOR
LEVEL 6 INTERRUPT AUTOVECTOR
LEVEL 7 INTERRUPT AUTOVECTOR
TAP INSTRUCTION VECTORS (0–15)
(RESERVED, COPROCESSOR)
(UNASSIGNED, RESERVED)
USER-DEFINED VECTORS
$XX0000
$XX03FC
$YFF000
$YFF900
GPT
$YFF93F
$YFFA00
RESERVED
$YFFA7F
$YFFA80
$YFFAFF
USER
SPACE
$000000
INTERNAL REGISTERS
$7FF000
4
QSM
$YFFC00
$YFFDFF
$FF0000
$FFFFFF
INTERNAL REGISTERS $YFFFFF INTERNAL REGISTERS
$FF0000
4
$FFFFFF
NOTES:
1. Location of the exception vector table is determined by the vector base register. The vector address is the sum of the vector base register and the vector offset.
2. Location of the module control registers is determined by the state of the module mapping (MM) bit in the SIM configuration register.
Y = M111, where M is the state of the MM bit.
3. Unused addresses within the internal register block are mapped externally. "RESERVED" blocks are not mapped externally.
4. Some internal registers are not available in user space.
331 S/U SEP MAP
Figure 3-6 Separate Supervisor and User Space Map
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$000000
SUPERVISOR
DATA
SPACE
$7FF000
INTERNAL REGISTERS
VECTOR
OFFSET
0000
0004
VECTOR
NUMBER
0
1
EXCEPTION VECTORS LOCATED
IN SUPERVISOR PROGRAM SPACE
RESET — INITIAL STACK POINTER
RESET — INITIAL PC
$XX0000
$XX0004
VECTOR
NUMBER
12
13
14
15
16–23
24
25
26
27
28
29
30
31
32–47
48–58
59–63
64–255
6
7
4
5
2
3
0
1
8
9
10
11
VECTOR
OFFSET
0030
0034
0038
003C
0040–005C
006C
0064
0068
006C
0070
0074
0078
007C
0080–00BC
00C0–00EB
00EC–00FC
0100–03FC
0000
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028
002C
EXCEPTION VECTORS LOCATED
IN SUPERVISOR DATA SPACE
RESET — INITIAL STACK POINTER
RESET — INITIAL PC
BUS ERROR
ADDRESS ERROR
ILLEGAL INSTRUCTION
ZERO DIVISION
CHK, CHK2 INSTRUCTIONS
TRAPcc, TRAPV INSTRUCTIONS
PRIVILEGE VIOLATION
TRACE
LINE 1010 EMULATOR
LINE 1111 EMULATOR
HARDWARE BREAKPOINT
(RESERVED COPROCESSOR PROTOCOL VIOLATION)
FORMAT ERROR AND UNINITIALIZED INTERRUPT
FORMAT ERROR AND UNINITIALIZED INTERRUPT
(UNASSIGNED, RESERVED)
SPURIOUS INTERRUPT
LEVEL 1 INTERRUPT AUTOVECTOR
LEVEL 2 INTERRUPT AUTOVECTOR
LEVEL 3 INTERRUPT AUTOVECTOR
LEVEL 4 INTERRUPT AUTOVECTOR
LEVEL 5 INTERRUPT AUTOVECTOR
LEVEL 6 INTERRUPT AUTOVECTOR
LEVEL 7 INTERRUPT AUTOVECTOR
TAP INSTRUCTION VECTORS (0–15)
(RESERVED, COPROCESSOR)
(UNASSIGNED, RESERVED)
USER-DEFINED VECTORS
$XX0000
$XX03FC
$YFF000
$YFF900
GPT
$YFF93F
$YFFA00
RESERVED
$YFFA7F
$YFFA80
$YFFAFF
SUPERVISOR
PROGRAM
SPACE
$000000
QSM
$YFFC00
$YFFDFF
$FF0000
$FFFFFF
INTERNAL REGISTERS $YFFFFF
$FFFFFF
NOTES:
1. Location of the exception vector table is determined by the vector base register. The vector address is the sum of the vector base register and the vector offset.
2. Location of the module control registers is determined by the state of the module mapping (MM) bit in the SIM configuration register.
Y = M111, where M is the state of the MM bit.
3. Unused addresses within the internal register block are mapped externally. "RESERVED" blocks are not mapped externally.
4. Some internal registers are not available in user space.
331 SUPER P/D MAP
Figure 3-7 Supervisor Space (Separate Program/Data Space) Map
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$000000
USER
PROGRAM
SPACE
USER
DATA
SPACE
$7FF000
INTERNAL REGISTERS
$YFF000
$YFF900
GPT
$YFF93F
$YFFA00
RESERVED
$YFFA7F
$YFFA80
$YFFAFF
QSM
$YFFC00
$YFFDFF
$FF0000
$FFFFFF
INTERNAL REGISTERS $YFFFFF
$FFFFFF
NOTES:
1. Location of the module control registers is determined by the state of the module mapping (MM) bit in the SIM configuration register. Y = M111, where M is the state of the MM bit.
2. Unused addresses within the internal register block are mapped externally. "RESERVED" blocks are not mapped externally.
3. Some internal registers are not available in user space.
Figure 3-8 User Space (Separate Program/Data Space) Map
331 USER P/D MAP
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3.7 System Reset
The following information is a concise reference only. System reset is a complex op-
eration. To understand operation during and after reset, refer to SECTION 4 SYSTEM
INTEGRATION MODULE, paragraph 4.6 Reset for a more complete discussion of the
reset function.
3.7.1 SIM Reset Mode Selection
The logic states of certain data bus pins during reset determine SIM operating configuration. In addition, the state of the MODCLK pin determines system clock source and the state of the BKPT pin determines what happens during subsequent breakpoint as-
sertions. Table 3-6 is a summary of reset mode selection options.
Mode Select Pin
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA11
MODCLK
BKPT
Table 3-6 SIM Reset Mode Selection
Default Function
(Pin Left High)
CSBOOT 16-Bit
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS[7:6]
CS[8:6]
CS[9:6]
CS[10:6]
DSACK0, DSACK1,
AVEC, DS, AS,
SIZ[1:0]
IRQ[7:1], MODCLK
Test Mode Disabled
VCO = System Clock
Background Mode Disabled
Alternate Function
(Pin Pulled Low)
CSBOOT 8-Bit
BRBG
BGACK
FC0FC1FC2
ADDR19
ADDR[20:19]
ADDR[21:19]
ADDR[22:19]
ADDR[23:19]
PORTE
PORTF
Test Mode Enabled
EXTAL = System Clock
Background Mode Enabled
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3.7.2 MCU Module Pin Function During Reset
Generally, pins associated with modules other than the SIM default to port functions, and input/output ports are set to input state. This is accomplished by disabling pin functions in the appropriate control registers, and by clearing the appropriate port data direction registers. Refer to individual module sections in this manual for more infor-
mation. Table 3-7 is a summary of module pin function out of reset.
Module
CPU32
GPT
QSM
Table 3-7 Module Pin Functions
Pin Mnemonic
DSI/IFETCH
DSO/IPIPE
BKPT/DSCLK
PGP7/IC4/OC5
PGP[6:3]/OC[4:1]
PGP[2:0]/IC[3:1]
PAI
PCLK
PWMA, PWMB
PQS7/TXD
PQS[6:4]/PCS[3:1]
PQS3/PCS0/SS
PQS2/SCK
PQS1/MOSI
PQS0/MISO
RXD
Function
DSI/IFETCH
DSO/IPIPE
BKPT/DSCLK
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Output
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
RXD
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SECTION 4 SYSTEM INTEGRATION MODULE
This section is an overview of SIM function. Refer to the
SIM Reference Manual (SIM-
RM/AD) for a comprehensive discussion of SIM capabilities. Refer to APPENDIX D
REGISTER SUMMARY for information concerning the SIM address map and register
structure.
4.1 General
The system integration module (SIM) consists of five functional blocks. Figure 4-1 is
a block diagram of the SIM.
The system configuration and protection block controls configuration parameters and provides bus and software watchdog monitors. In addition, it provides a periodic interrupt generator to support execution of time-critical control routines.
The system clock generates clock signals used by the SIM, other IMB modules, and external devices.
The external bus interface handles the transfer of information between IMB modules and external address space. EBI pins can also be configured for use as general-purpose I/O ports E and F.
The chip-select block provides 12 chip-select signals. Each chip-select signal has an associated base register and option register that contain the programmable characteristics of that chip select. Chip-select pins can also be configured for use as generalpurpose output port C.
The system test block incorporates hardware necessary for testing the MCU. It is used to perform factory tests, and its use in normal applications is not supported.
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SYSTEM CONFIGURATION
AND PROTECTION
CLOCK SYNTHESIZER
CLKOUT
EXTAL
MODCLK
CHIP SELECTS CHIP SELECTS
4
EXTERNAL BUS INTERFACE
EXTERNAL BUS
RESET
FACTORY TEST
TSC
FREEZE/QUOT
S(C)IM BLOCK
Figure 4-1 System Integration Module Block Diagram
4.2 System Configuration and Protection
The system configuration and protection functional block controls module configuration, preserves reset status, monitors internal activity, and provides periodic interrupt
generation. Figure 4-2 is a block diagram of the submodule.
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MODULE CONFIGURATION
AND TEST
RESET STATUS
HALT MONITOR RESET REQUEST
BUS MONITOR BERR
SPURIOUS INTERRUPT MONITOR
CLOCK SOFTWARE WATCHDOG TIMER RESET REQUEST
2
9
PRESCALER
PERIODIC INTERRUPT TIMER
IRQ [7:1]
SYS PROTECT BLOCK
Figure 4-2 System Configuration and Protection
4.2.1 Module Mapping
Control registers for all the modules in the microcontroller are mapped into a 4-Kbyte block. The state of the module mapping bit (MM) in the SIM module configuration register (SIMCR) determines where the control register block is located in the system memory map. When MM = 0, register addresses range from $7FF000 to $7FFFFF; when MM = 1, register addresses range from $FFF000 to $FFFFFF.
4.2.2 Interrupt Arbitration
Each module that can generate interrupt requests has an interrupt arbitration (IARB) field. Arbitration between interrupt requests of the same priority is performed by serial contention between IARB field bit values. Contention must take place whenever an interrupt request is acknowledged, even when there is only a single request pending.
For an interrupt to be serviced, the appropriate IARB field must have a non-zero value.
If an interrupt request from a module with an IARB field value of %0000 is recognized, the CPU32 processes a spurious interrupt exception.
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Because the SIM routes external interrupt requests to the CPU32, the SIM IARB field value is used for arbitration between internal and external interrupts of the same priority. The reset value of IARB for the SIM is %1111, and the reset IARB value for all other modules is %0000, which prevents SIM interrupts from being discarded during
initialization. Refer to 4.7 Interrupts for a discussion of interrupt arbitration.
4.2.3 Show Internal Cycles
A show cycle allows internal bus transfers to be monitored externally. The SHEN field in the SIMCR determines what the external bus interface does during internal transfer
operations. Table 4-1 shows whether data is driven externally, and whether external
bus arbitration can occur. Refer to 4.5.6.2 Show Cycles for more information.
4
SHEN
00
01
10
11
Table 4-1 Show Cycle Enable Bits
Action
Show cycles disabled, external arbitration enabled
Show cycles enabled, external arbitration disabled
Show cycles enabled, external arbitration enabled
Show cycles enabled, external arbitration enabled; internal activity is halted by a bus grant
4.2.4 Factory Test Mode
The internal IMB can serve as slave to an external master for direct module testing.
This test mode is reserved for factory test. Slave mode is enabled by holding DATA11 low during reset. The slave enabled (SLVEN) bit is a read-only bit that shows the reset state of DATA11.
4.2.5 Register Access
The CPU32 can operate at either of two privilege levels. Supervisor level is more privileged than user level — all instructions and system resources are available at supervisor level, but access is restricted at user level. Effective use of privilege level can protect system resources from uncontrolled access. The state of the S bit in the CPU status register determines access level, and whether the user or supervisor stack pointer is used for stacking operations. The SUPV bit places SIM global registers in either supervisor or user data space. When SUPV = 0, registers with controlled access are accessible from either the user or supervisor privilege level; when SUPV = 1, registers with controlled access are restricted to supervisor access only.
4.2.6 Reset Status
The reset status register (RSR) latches internal MCU status during reset. Refer to
4.6.9 Reset Status Register for more information.
4.2.7 Bus Monitor
The internal bus monitor checks data and size acknowledge (DSACK) or autovector
(AVEC) signal response times during normal bus cycles. The monitor asserts the internal bus error (BERR) signal when the response time is excessively long.
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DSACK and AVEC response times are measured in clock cycles. Maximum allowable response time can be selected by setting the bus monitor timing (BMT) field in the sys-
tem protection control register (SYPCR). Table 4-2 shows the periods allowed.
Table 4-2 Bus Monitor Period
BMT
00
01
10
11
Bus Monitor Time-Out Period
64 System Clocks
32 System Clocks
16 System Clocks
8 System Clocks
The monitor does not check DSACK response on the external bus unless the CPU32 initiates a bus cycle. The BME bit in SYPCR enables the internal bus monitor for internal to external bus cycles. If a system contains external bus masters, an external bus monitor must be implemented and the internal-to-external bus monitor option must be disabled.
When monitoring transfers to an 8-bit port, the bus monitor does not reset until both byte accesses of a word transfer are completed. Monitor time-out period must be at least twice the number of clocks that a single byte access requires.
4.2.8 Halt Monitor
The halt monitor responds to an assertion of the HALT signal on the internal bus. Refer
to 4.5.5.2 Double Bus Faults for more information. Halt monitor reset can be inhibited
by the halt monitor (HME) bit in SYPCR.
4.2.9 Spurious Interrupt Monitor
During interrupt exception processing, the CPU32 normally acknowledges an interrupt request, recognizes the highest priority source, and then acquires a vector or responds to a request for autovectoring. The spurious interrupt monitor asserts the internal bus error signal (BERR) if no interrupt arbitration occurs during interrupt exception processing. The assertion of BERR causes the CPU32 to load the spurious interrupt exception vector into the program counter. The spurious interrupt monitor
cannot be disabled. Refer to 4.7 Interrupts for further information. For detailed infor-
mation about interrupt exception processing, refer to SECTION 5 CENTRAL PRO-
CESSING UNIT.
4.2.10 Software Watchdog
The software watchdog is controlled by the software watchdog enable (SWE) bit in
SYPCR. When enabled, the watchdog requires that a service sequence be written to software service register SWSR on a periodic basis. If servicing does not take place, the watchdog times out and asserts the reset signal.
Perform a software watchdog service sequence as follows:
1. Write $55 to SWSR.
2. Write $AA to SWSR.
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Both writes must occur before time-out in the order listed, but any number of instructions can be executed between the two writes.
Watchdog clock rate is affected by the software watchdog prescale (SWP) and software watchdog timing (SWT) fields in SYPCR.
SWP determines system clock prescaling for the watchdog timer and determines that one of two options, either no prescaling or prescaling by a factor of 512, can be selected. The value of SWP is affected by the state of the MODCLK pin during reset, as
shown in Table 4-3. System software can change SWP value.
Table 4-3 MODCLK Pin and SWP Bit During Reset
MODCLK SWP
0 (External Clock)
1 (Internal Clock)
1 (
÷
512)
0 (
÷
1)
The SWT field selects the divide ratio used to establish software watchdog time-out period. Time-out period is given by the following equations.
Time-out Period = or
Time-out Period =
EXTAL Frequency
Table 4-4 shows the ratio for each combination of SWP and SWT bits. When SWT[1:0]
are modified, a watchdog service sequence must be performed before the new timeout period can take effect.
Table 4-4 Software Watchdog Ratio
SWP
0
0
0
0
1
1
1
1
SWT Ratio
00
01
10
2
9
2
11
2
13
11
00
01
2
15
2
18
2
20
10
11
2
22
2
24
Figure 4-3 is a block diagram of the watchdog timer and the clock control for the pe-
riodic interrupt timer.
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PITR
SWP
PTP
FREEZE
8-BIT MODULUS
COUNTER
PIT
INTERRUPT
EXTAL
PRESCALER (2
9
)
PRECLK
CLOCK
MUX
÷
4
PITCLK
CLOCK
DISABLE
RESET
SWCLK
15 STAGE
DIVIDER CHAIN (2
15
)
LPSTOP
SWT1
SWT0
SWE
2
9
2
11
2
13
2
15
Figure 4-3 Periodic Interrupt Timer and Software Watchdog Timer
PIT BLOCK
4.2.11 Periodic Interrupt Timer
The periodic interrupt timer allows the generation of interrupts of specific priority at predetermined intervals. This capability is often used to schedule control system tasks that must be performed within time constraints. The timer consists of a prescaler, a modulus counter, and registers that determine interrupt timing, priority and vector as-
signment. Refer to SECTION 5 CENTRAL PROCESSING UNIT for further information
about interrupt exception processing.
The periodic interrupt modulus counter is clocked by a signal derived from the buffered crystal oscillator (EXTAL) input pin unless an external frequency source is used. The value of the periodic timer prescaler (PTP) bit in the periodic interrupt timer register
(PITR) determines system clock prescaling for the watchdog timer. One of two options, either no prescaling, or prescaling by a factor of 512, can be selected. The value
of PTP is affected by the state of the MODCLK pin during reset, as shown in Table 4-
5. System software can change PTP value.
4
Table 4-5 MODCLK Pin and PTP Bit at Reset
MODCLK PTP
0 (External Clock)
1 (Internal Clock)
1 (
÷
512)
0 (
÷
1)
Either clock signal (EXTAL or EXTAL
÷
512) is divided by four before driving the modulus counter (PITCLK). The modulus counter is initialized by writing a value to the periodic timer modulus timer modulus (PITM) field in the PITR. A zero value turns off the periodic timer. When the modulus counter value reaches zero, an interrupt is generated. The modulus counter is then reloaded with the value in PITM and counting repeats.
If a new value is written to PITR, it is loaded into the modulus counter when the current count is completed.
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Use the following expression to calculate timer period.
PIT Period
=
(
PIT Modulus
) (
Prescaler Value
)
4
----------------------------------------------------------------------------------------------
EXTAL Frequency
Interrupt priority and vectoring are determined by the values of the periodic interrupt request level (PIRQL) and periodic interrupt vector (PIV) fields in the periodic interrupt control register (PICR).
Content of PIRQL is compared to the CPU32 interrupt priority mask to determine
whether the interrupt is recognized. Table 4-6 shows priority of PIRQL values. Be-
cause of SIM hardware prioritization, a PIT interrupt is serviced before an external interrupt request of the same priority. The periodic timer continues to run when the interrupt is disabled.
4
Table 4-6 Periodic Interrupt Priority
PIRQL
000
001
010
011
100
101
110
111
Priority Level
Periodic Interrupt Disabled
Interrupt Priority Level 1
Interrupt Priority Level 2
Interrupt Priority Level 3
Interrupt Priority Level 4
Interrupt Priority Level 5
Interrupt Priority Level 6
Interrupt Priority Level 7
The PIV field contains the periodic interrupt vector. The vector is placed on the IMB when an interrupt request is made. The vector number used to calculate the address of the appropriate exception vector in the exception vector table. Reset value of the
PIV field is $0F, which corresponds to the uninitialized interrupt exception vector.
4.2.12 Low-Power STOP Operation
When the CPU32 executes the LPSTOP instruction, the current interrupt priority mask is stored in the clock control logic, internal clocks are disabled according to the state of the STSIM bit in the SIMCR, and the MCU enters low-power stop mode. The bus monitor, halt monitor, and spurious interrupt monitor are all inactive during low-power stop.
During low-power stop, the clock input to the software watchdog timer is disabled and the timer stops. The software watchdog begins to run again on the first rising clock edge after low-power stop ends. The watchdog is not reset by low-power stop. A service sequence must be performed to reset the timer.
The periodic interrupt timer does not respond to the LPSTOP instruction, but continues to run during LPSTOP. To stop the periodic interrupt timer, PITR must be loaded with a zero value before the LPSTOP instruction is executed. A PIT interrupt, or an external interrupt request, can bring the MCU out of the low-power stop condition if it has a higher priority than the interrupt mask value stored in the clock control logic when lowpower stop is initiated. LPSTOP can be terminated by a reset.
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4.2.13 Freeze Operation
The FREEZE signal halts MCU operations during debugging. FREEZE is asserted internally by the CPU32 if a breakpoint occurs while background mode is enabled. When
FREEZE is asserted, only the bus monitor, software watchdog, and periodic interrupt timer are affected. The halt monitor and spurious interrupt monitor continue to operate normally. Setting the freeze bus monitor (FRZBM) bit in the SIMCR disables the bus monitor when FREEZE is asserted, and setting the freeze software watchdog
(FRZSW) bit disables the software watchdog and the periodic interrupt timer when
FREEZE is asserted. When FRZSW is set, FREEZE assertion must be at least two times the PIT clock source period to ensure an accurate number of PIT counts.
4.3 System Clock
The system clock in the SIM provides timing signals for the IMB modules and for an external peripheral bus. Because the MCU is a fully static design, register and memory contents are not affected when the clock rate changes. System hardware and software support changes in clock rate during operation.
The system clock signal can be generated in one of three ways. An internal phaselocked loop can synthesize the clock from either an internal reference or an external reference, or the clock signal can be input from an external frequency source. Keep
these clock sources in mind while reading the rest of this section. Figure 4-4 is a block
diagram of the system clock. Refer to APPENDIX A ELECTRICAL CHARACTERIS-
TICS for clock specifications.
4
EXTAL XTAL
CRYSTAL
OSCILLATOR
PHASE
COMPARATOR
XFC
LOW-PASS
FILTER
FEEDBACK DIVIDER
SYSTEM CLOCK CONTROL
W
Y
X
V
DDSYN
VCO
SYSTEM
CLOCK
CLKOUT
32 PLL BLOCK
Figure 4-4 System Clock Block Diagram
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4.3.1 Clock Sources
The state of the clock mode (MODCLK) pin during reset determines clock source.
When MODCLK is held high during reset, the clock synthesizer generates a clock signal from either an internal or an external reference frequency — the clock synthesizer control register (SYNCR) determines operating frequency and mode of operation.
When MODCLK is held low during reset, the clock synthesizer is disabled and an external system clock signal must be applied — SYNCR control bits have no effect.
To generate a reference frequency using the internal oscillator a reference crystal
must be connected between the EXTAL and XTAL pins. Figure 4-5 shows a recom-
mended circuit.
4
C1
22 pF
*
R1
330k
R2
10M
XTAL
EXTAL
V
SSI
C2
22 pF
*
*
Resistance and capacitance based on a test circuit constructed with a DAISHINKU DMX-38 32.768-kHz crystal.
Specific components must be based on crystal type. Contact crystal vendor for exact circuit.
32 OSCILLATOR
Figure 4-5 System Clock Oscillator Circuit
If an external reference signal or an external system clock signal is applied via the EX-
TAL pin, the XTAL pin must be left floating. External reference signal frequency must be less than or equal to maximum specified reference frequency. External system clock signal frequency must be less than or equal to maximum specified system clock frequency.
When an external system clock signal is applied (PLL disabled, MODCLK = 0 during reset), the duty cycle of the input is critical, especially at operating frequencies close to maximum. The relationship between clock signal duty cycle and clock signal period is expressed:
Minumum External Clock Period
= ----------------------------------------------------------------------------------------------------------------------------------------------------------------------
50%
–
Percentage Variation of External Clock Input Duty Cycle
4.3.2 Clock Synthesizer Operation
V
DDSYN
is used to power the clock circuits when either an internal or an external reference frequency is applied. A separate power source increases MCU noise immunity and can be used to run the clock when the MCU is powered down. A quiet power supply must be used as the V
DDSYN
source. Adequate external bypass capacitors should be placed as close as possible to the V
DDSYN
pin to assure stable operating frequen-
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cy. When an external system clock signal is applied and the PLL is disabled, V
DDSYN should be connected to the V
DD
supply. Refer to the SIM Reference Manual (SIMRM/
AD) for more information regarding system clock power supply conditioning.
A voltage controlled oscillator (VCO) generates the system clock signal. To maintain a 50% clock duty cycle, VCO frequency is either two or four times system clock frequency, depending on the state of the X bit in SYNCR. A portion of the clock signal is fed back to a divider/counter. The divider controls the frequency of one input to a phase comparator. The other phase comparator input is a reference signal, either from the crystal oscillator or from an external source. The comparator generates a control signal proportional to the difference in phase between the two inputs. The signal is lowpass filtered and used to correct VCO output frequency.
Filter geometry can vary, depending upon the external environment and required clock
stability. Figure 4-6 shows two recommended filters. XFC pin leakage must be as
specified in APPENDIX A ELECTRICAL CHARACTERISTICS to maintain optimum
stability and PLL performance.
An external filter network connected to the XFC pin is not required when an external system clock signal is applied and the PLL is disabled. The XFC pin must be left floating in this case.
4
C3
0.1
µ
F
C1
0.1
µ
F
C3
0.1
µ
F
C1
0.1
µ
F
R1
18k
Ω
XFC
1
V
DDSYN
V
SSI
C4
0.01
µ
F
V
SSI
C4
0.01
µ
F
C2
0.01
µ
F
NORMAL OPERATING
ENVIRONMENT
HIGH-STABILITY OPERATING
ENVIRONMENT
1. Maintain low-leakage on the XFC node. See Appendix A electrical characteristics for more information.
2. Recommended loop filter for reduced sensitivity to low-frequency noise.
XFC
1, 2
V
DDSYN
16/32 XFC CONN
Figure 4-6 System Clock Filter Networks
The synthesizer locks when VCO frequency is equal to EXTAL frequency. Lock time is affected by the filter time constant and by the amount of difference between the two comparator inputs. Whenever comparator input changes, the synthesizer must relock.
Lock status is shown by the SLOCK bit in SYNCR. During power-up, the MCU does not come out of reset state until the synthesizer locks. Crystal type, characteristic frequency, and layout of external oscillator circuitry affect lock time.
When the clock synthesizer is used, control register SYNCR determines operating frequency and various modes of operation. The SYNCR W bit controls a three-bit prescaler in the feedback divider. Setting W increases VCO speed by a factor of four. The
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SYNCR Y field determines the count modulus for a modulo 64 down counter, causing it to divide by a value of Y + 1. When W or Y values change, VCO frequency changes, and there is a VCO relock delay. The SYNCR X bit controls a divide-by-two circuit that is not in the synthesizer feedback loop. When X = 0 (reset state), the divider is enabled, and system clock frequency is one-fourth VCO frequency; setting X disables the divider, doubling clock speed without changing VCO speed. There is no relock delay when clock speed is changed by the X bit.
Clock frequency is determined by SYNCR bit settings as follows:
F
SYSTEM
=
F
REFERENCE
[ (
+
1
) (
2
2W
+
X
) ]
The reset state of SYNCR ($3F00) produces a modulus-64 count.
For the device to perform correctly, system clock and VCO frequencies selected by the W, X, and Y bits must be within the limits specified for the MCU. Do not use a combination of bit values that selects either an operating frequency or a VCO frequency
greater than the maximum specified values in APPENDIX A ELECTRICAL CHARAC-
TERISTICS.
Table 4-7 shows clock control multipliers for all possible combinations of SYNCR bits.
Table 4-8 shows clock frequencies available with a 32.768-kHz reference and a max-
imum specified clock frequency of 20.97 MHz.
Table 4-7 Clock Control Multipliers
To obtain clock frequency in kilohertz, find counter modulus in the left column, then multiply reference frequency by value in appropriate prescaler cell.
Modulus
Y
000000
000001
000010
011111
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
48
52
56
60
32
36
40
44
[W:X] = 00
4
8
12
16
20
24
28
64
68
72
76
80
84
[W:X] = 01
8
16
24
32
40
48
56
96
104
112
120
64
72
80
88
128
136
144
152
160
168
Prescalers
128
144
160
176
192
208
224
240
[W:X] = 10
16
32
48
64
80
96
112
256
272
288
304
320
336
[W:X] = 11
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
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Table 4-7 Clock Control Multipliers (Continued)
To obtain clock frequency in kilohertz, find counter modulus in the left column, then multiply reference frequency by value in appropriate prescaler cell.
172
176
180
184
188
192
196
200
140
144
148
152
156
160
164
168
[W:X] = 00
88
92
96
100
104
108
112
116
120
124
128
132
136
236
240
244
248
252
256
204
208
212
216
220
224
228
232
011101
011110
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
Modulus
Y
010100
010101
010110
010111
011000
011001
011010
011011
011100
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
344
352
360
368
376
384
392
400
280
288
296
304
312
320
328
336
[W:X] = 01
176
184
192
200
208
216
224
232
240
248
256
264
272
472
480
488
496
504
512
408
416
424
432
440
448
456
464
Prescalers
688
704
720
736
752
768
784
800
560
576
592
608
624
640
656
672
[W:X] = 10
352
368
384
400
416
432
448
464
480
496
512
528
544
944
960
976
992
1008
1024
816
832
848
864
880
896
912
928
1376
1408
1440
1472
1504
1536
1568
1600
1120
1152
1184
1216
1248
1280
1312
1344
[W:X] = 11
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1888
1920
1952
1984
2016
2048
1632
1664
1696
1728
1760
1792
1824
1856
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4
Table 4-8 System Frequencies from 32.768-kHz Reference
To obtain clock frequency in kilohertz, find counter modulus in the left column, then look in appropriate prescaler cell.
Shaded cells contain values that exceed specified maximum system frequency.
3146
3277
3408
3539
3670
3801
3932
4063
2097
2228
2359
2490
2621
2753
2884
3015
[W:X] = 00
131
262
393
524
655
786
918
1049
1180
1311
1442
1573
1704
1835
1966
5243
5374
5505
5636
5767
5898
4194
4325
4456
4588
4719
4850
4981
5112
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
Modulus
Y
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
011101
011110
011111
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
6291
6554
6816
7078
7340
7602
7864
8126
4194
4456
4719
4981
5243
5505
5767
6029
[W:X] = 01
262
524
786
1049
1311
1573
1835
2097
2359
2621
2884
3146
3408
3670
3932
8389
8651
8913
9175
9437
9699
9961
10224
10486
10748
11010
11272
11534
11796
Prescaler
12583
13107
13631
14156
14680
15204
15729
16253
8389
8913
9437
9961
10486
11010
11534
12059
[W:X] = 10
524
1049
1573
2097
2621
3146
3670
4194
4719
5243
5767
6291
6816
7340
7864
16777
17302
17826
18350
18874
19399
19923
20447
20972
21496
22020
22544
23069
23593
25166
26214
27263
28312
29360
30409
31457
32506
16777
17826
18874
19923
20972
22020
23069
24117
[W:X] = 11
1049
2097
3146
4194
5243
6291
7340
8389
9437
10486
11534
12583
13631
14680
15729
33554
34603
35652
36700
37749
38797
39846
40894
41943
42992
44040
45089
46137
47186
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Table 4-8 System Frequencies from 32.768-kHz Reference (Continued)
To obtain clock frequency in kilohertz, find counter modulus in the left column, then look in appropriate prescaler cell.
Shaded cells contain values that exceed specified maximum system frequency.
Modulus
Y
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
[W:X] = 00
6029
6160
6291
6423
6554
6685
6816
6947
7078
7209
7340
7471
7602
7733
7864
7995
8126
8258
8389
[W:X] = 01
12059
12321
12583
12845
13107
13369
13631
13894
14156
14418
14680
14942
15204
15466
15729
15991
16253
16515
16777
Prescaler
[W:X] = 10
24117
24642
25166
25690
26214
26739
27263
27787
28312
28836
29360
2988
30409
30933
31457
31982
32506
33030
33554
[W:X] = 11
48234
49283
50332
51380
52428
53477
54526
55575
56623
57672
58720
59769
60817
61866
62915
63963
65011
66060
67109
4.3.3 External Bus Clock
The state of the external clock division bit (EDIV) in SYNCR determines clock rate for the external bus clock signal (ECLK) available on pin ADDR23. ECLK is a bus clock for MC6800 devices and peripherals. ECLK frequency can be set to system clock frequency divided by eight or system clock frequency divided by sixteen. The clock is enabled by the CS10 field in chip select pin assignment register 1 (CSPAR1). ECLK
operation during low-power stop is described in the following paragraph. Refer to 4.8
Chip Selects for more information about the external bus clock.
4.3.4 Low-Power Operation
Low-power operation is initiated by the CPU32. To reduce power consumption selectively, the CPU can set the STOP bits in each module configuration register. To minimize overall microcontroller power consumption, the CPU can execute the LPSTOP instruction, which causes the SIM to turn off the system clock.
When individual module STOP bits are set, clock signals inside each module are turned off, but module registers are still accessible.
When the CPU executes LPSTOP, a special CPU space bus cycle writes a copy of the current interrupt mask into the clock control logic. The SIM brings the MCU out of low-power operation when either an interrupt of higher priority than the stored mask or
a reset occurs. Refer to 4.5.4.2 LPSTOP Broadcast Cycle and SECTION 5 CEN-
TRAL PROCESSING UNIT for more information.
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During a low-power stop, unless the system clock signal is supplied by an external source and that source is removed, the SIM clock control logic and the SIM clock signal (SIMCLK) continue to operate. The periodic interrupt timer and input logic for the
RESET and IRQ pins are clocked by SIMCLK. The SIM can also continue to generate the CLKOUT signal while in low-power mode.
The stop mode system integration module clock (STSIM) and stop mode external
clock (STEXT) bits in SYNCR determine clock operation during low-power stop. Table
4-9 is a summary of the effects of STSIM and STEXT. MODCLK value is the logic level
on the MODCLK pin during the last reset before LPSTOP execution. Any clock in the off state is held low. If the synthesizer VCO is turned off during LPSTOP, there is a
PLL relock delay after the VCO is turned back on.
4
Mode
LPSTOP
No
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Table 4-9 Clock Control
MODCLK
Pins
0
0
0
0
0
1
EXTAL
External
Clock
External
Clock
External
Clock
External
Clock
External
Clock
Crystal or
Reference
1
1
1
1
Crystal or
Reference
Crystal or
Reference
Crystal or
Reference
Crystal or
Reference
SYNCR Bits
STSIM STEXT
X X
0
0
1
1
X
0
0
1
1
0
1
0
1
X
0
1
0
1
SIMCLK
External
Clock
External
Clock
External
Clock
External
Clock
External
Clock
VCO
Crystal or
Reference
Crystal or
Reference
VCO
VCO
Clock Status
CLKOUT
External
Clock
Off
External
Clock
Off
External
Clock
VCO
Off
Crystal/
Reference
Off
VCO
4.3.5 Loss of Reference Signal
The state of the reset enable (RSTEN) bit in SYNCR determines what happens when clock logic detects a reference failure.
When RSTEN is cleared (default state out of reset), the clock synthesizer is forced into an operating condition referred to as limp mode. Limp mode frequency varies from device to device, but maximum limp frequency does not exceed one half maximum system clock when X = 0, or maximum system clock frequency when X = 1.
When RSTEN is set, the SIM resets the MCU.
The limp status bit (SLIMP) in SYNCR indicates whether the synthesizer has a reference signal. It is set when a reference failure is detected.
ECLK
External
Clock
Off
External
Clock
Off
External
Clock
VCO
Off
Off
Off
VCO
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4.4 External Bus Interface
The external bus interface (EBI) transfers information between the internal MCU bus
and external devices. Figure 4-7 shows a basic system with external memory and pe-
ripherals.
FC
1
SIZ
CLKOUT
AS
DSACK
DS
CS3
CS5
IRQ
ADDR[23:0]
DATA[15:0]
ASYNC BUS
PERIPHERAL
SIZ
CLK
AS
DSACK
DS
CS
IACK
IRQ
ADDR[15:0]
2
DATA[15:0]
MCU
CSBOOT
R/W
MEMORY
ADDR[23:0]
2
DATA[15:8]
CS
R/W
4
MEMORY
ADDR[23:0]
2
DATA[7:0]
CS
R/W
1. Can be decoded to provide additional address space.
2. Varies depending upon peripheral memory size.
32 EXAMPLE SYS BLOCK
Figure 4-7 MCU Basic System
The external bus has 24 address lines and 16 data lines. The EBI provides dynamic sizing between 8-bit and 16-bit data accesses. It supports byte, word, and long-word transfers. Ports are accessed through the use of asynchronous cycles controlled by the data transfer (SIZ1 and SIZ0) and data size acknowledge pins (DSACK1 and
DSACK0). Multiple bus cycles may be required for a transfer to or from an 8-bit port.
The maximum number of bits transferred during an access is referred to as port width.
Widths of eight and sixteen bits can be accessed by asynchronous bus cycles controlled by the data size (SIZ[1:0]) and the data and size acknowledge (DSACK[1:0]) signals. Multiple bus cycles may be required for a dynamically-sized transfer.
To add flexibility and minimize the necessity for external logic, MCU chip-select logic
can be synchronized with EBI transfers. Refer to 4.8 Chip Selects for more informa-
tion.
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4.4.1 Bus Signals
The address bus provides addressing information to external devices. The data bus transfers 8-bit and 16-bit data between the MCU and external devices. Strobe signals, one for the address bus and another for the data bus, indicate the validity of an address and provide timing information for data.
Control signals indicate the beginning of each bus cycle, the address space it is to take place in, the size of the transfer, and the type of cycle. External devices decode these signals and respond to transfer data and terminate the bus cycle. The EBI operates in an asynchronous mode for any port width.
4.4.1.1 Address Bus
Bus signals ADDR[23:0] define the address of the byte (or the most significant byte) to be transferred during a bus cycle. The MCU places the address on the bus at the beginning of a bus cycle. The address is valid while AS is asserted.
4.4.1.2 Address Strobe
Address strobe AS is a timing signal that indicates the validity of an address on the address bus and of many control signals. It is asserted one-half clock after the beginning of a bus cycle.
4.4.1.3 Data Bus
Signals DATA[15:0 form a bidirectional, nonmultiplexed parallel bus that transfers data to or from the MCU. A read or write operation can transfer eight or sixteen bits of data in one bus cycle. During a read cycle, the data is latched by the MCU on the last falling edge of the clock for that bus cycle. For a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. The MCU places the data on the data bus one-half clock cycle after AS is asserted in a write cycle.
4.4.1.4 Data Strobe
Data strobe (DS) is a timing signal. For a read cycle, the MCU asserts DS to signal an external device to place data on the bus. DS is asserted at the same time as AS during a read cycle. For a write cycle, DS signals an external device that data on the bus is valid. The MCU asserts DS one full clock cycle after the assertion of AS during a write cycle.
4.4.1.5 Read/Write Signal
The read/write signal (R/W determines the direction of the transfer during a bus cycle.
This signal changes state, when required, at the beginning of a bus cycle, and is valid while AS is asserted. R/W only transitions when a write cycle is preceded by a read cycle or vice versa. The signal may remain low for two consecutive write cycles.
4.4.1.6 Size Signals
Size signals (SIZ[1:0]) indicate the number of bytes remaining to be transferred during
an operand cycle. They are valid while the address strobe (AS) is asserted. Table 4-
10 shows SIZ0 and SIZ1 encoding.
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Table 4-10 Size Signal Encoding
SIZ1
0
1
1
0
SIZ0
1
0
1
0
Transfer Size
Byte
Word
3 Byte
Long Word
4.4.1.7 Function Codes
The CPU generates function code output signals FC[2:0] to indicate the type of activity occurring on the data or address bus. These signals can be considered address extensions that can be externally decoded to determine which of eight external address spaces is accessed during a bus cycle.
Address space 7 is designated CPU space. CPU space is used for control information not normally associated with read or write bus cycles. Function codes are valid while
AS is asserted.
Table 4-11 shows address space encoding.
Table 4-11 Address Space Encoding
FC2
0
0
1
1
0
0
1
1
FC1
0
0
0
0
1
1
1
1
FC0
0
1
0
1
0
1
0
1
Address Space
Reserved
User Data Space
User Program Space
Reserved
Reserved
Supervisor Data Space
Supervisor Program Space
CPU Space
The supervisor bit in the status register determines whether the CPU is operating in supervisor or user mode. Addressing mode and the instruction being executed determine whether a memory access is to program or data space.
4.4.1.8 Data and Size Acknowledge Signals
During normal bus transfers, external devices assert the data and size acknowledge signals (DSACK[1:0]) to indicate port width to the MCU. During a read cycle, these signals tell the MCU to terminate the bus cycle and to latch data. During a write cycle, the signals indicate that an external device has successfully stored data and that the cycle can terminate. DSACK[1:0] can also be supplied internally by chip-select logic. Refer
to 4.8 Chip Selects for more information.
4.4.1.9 Bus Error Signal
The bus error signal BERR is asserted when a bus cycle is not properly terminated by
DSACK or AVEC assertion. BERR can also be asserted at the same time as DSACK,
provided the appropriate timing requirements are met. Refer to 4.5.5 Bus Exception
Control Cycles for more information.
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The internal bus monitor can generate the BERR signal for internal and internal-to-external transfers. An external bus master must provide its own BERR generation and drive the BERR pin, because the internal BERR monitor has no information about
transfers initiated by an external bus master. Refer to 4.5.6 External Bus Arbitration
for more information.
4.4.1.10 Halt Signal
The halt signal (HALT) can be asserted by an external device for debugging purposes to cause single bus cycle operation or (in combination with BERR) a retry of a bus cycle in error. The HALT signal affects external bus cycles only, so a program not requiring the use of external bus may continue executing, unaffected by the HALT signal.
When the MCU completes a bus cycle with the HALT signal asserted, DATA[15:0] is placed in the high-impedance state, and bus control signals are driven inactive; the address, function code, size, and read/write signals remain in the same state. If HALT is still asserted once bus mastership is returned to the MCU, the address, function code, size, and read/write signals are again driven to their previous states. The MCU does
not service interrupt requests while it is halted. Refer to 4.5.5 Bus Exception Control
Cycles for further information.
4.4.1.11 Autovector Signal
The autovector signal AVEC can be used to terminate external interrupt acknowledge cycles. Assertion of AVEC causes the CPU32 to generate vector numbers to locate an interrupt handler routine. If it is continuously asserted, autovectors are generated for all external interrupt requests. AVEC is ignored during all other bus cycles. Refer to
4.7 Interrupts for more information. AVEC for external interrupt requests can also be
supplied internally by chip-select logic. Refer to 4.8 Chip Selects for more information.
The autovector function is disabled when there is an external bus master. Refer to
4.5.6 External Bus Arbitration for more information.
4.4.2 Dynamic Bus Sizing
The MCU dynamically interprets the port size of an addressed device during each bus cycle, allowing operand transfers to or from 8-bit and 16-bit ports.
During an operand transfer cycle, an external device signals its port size and indicates completion of the bus cycle to the MCU through the use of the DSACK inputs, as
shown in Table 4-12. Chip-select logic can generate data and size acknowledge sig-
nals for an external device. Refer to 4.8 Chip Selects for further information.
Table 4-12 Effect of DSACK Signals
DSACK1
1
1
0
0
DSACK0
1
0
1
0
Result
Insert Wait States in Current Bus Cycle
Complete Cycle — Data Bus Port Size is 8 Bits
Complete Cycle — Data Bus Port Size is 16 Bits
Reserved
If the CPU is executing an instruction that reads a long-word operand from a 16-bit port, the MCU latches the 16 bits of valid data and then runs another bus cycle to ob-
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tain the other 16 bits. The operation for an 8-bit port is similar, but requires four read cycles. The addressed device uses the DSACK signals to indicate the port width. For instance, a 16-bit device always returns DSACK for a 16-bit port (regardless of whether the bus cycle is a byte or word operation).
Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular port size be fixed. A 16-bit port must reside on data bus bits [15:0], and an 8-bit port must reside on data bus bits [15:8]. This minimizes the number of bus cycles needed to transfer data and ensures that the MCU transfers valid data.
The MCU always attempts to transfer the maximum amount of data on all bus cycles.
For a word operation, it is assumed that the port is 16 bits wide when the bus cycle begins.
Operand bytes are designated as shown in Figure 4-8. OP[0:3] represent the order of
access. For instance, OP0 is the most significant byte of a long-word operand, and is accessed first, while OP3, the least significant byte, is accessed last. The two bytes of a word-length operand are OP0 (most significant) and OP1. The single byte of a bytelength operand is OP0.
4
Operand
Long Word
Three Byte
Word
Byte
31
OP0
24 23
Byte Order
16 15
OP1 OP2
OP0 OP1
OP0
8 7
OP3
OP2
OP1
OP0
0
Figure 4-8 Operand Byte Order
4.4.3 Operand Alignment
The EBI data multiplexer establishes the necessary connections for different combinations of address and data sizes. The multiplexer takes the two bytes of the 16-bit bus and routes them to their required positions. Positioning of bytes is determined by the size and address outputs. SIZ1 and SIZ0 indicate the remaining number of bytes to be transferred during the current bus cycle. The number of bytes transferred is equal to or less than the size indicated by SIZ1 and SIZ0, depending on port width.
ADDR0 also affects the operation of the data multiplexer. During an operand transfer,
ADDR[23:1] indicate the word base address of the portion of the operand to be accessed, and ADDR0 indicates the byte offset from the base.
4.4.4 Misaligned Operands
CPU32 architecture uses a basic operand size of 16 bits. An operand is misaligned when it overlaps a word boundary. This is determined by the value of ADDR0. When
ADDR0 = 0 (an even address), the address is on a word and byte boundary. When
ADDR0 = 1 (an odd address), the address is on a byte boundary only. A byte operand is aligned at any address; a word or long-word operand is misaligned at an odd address.
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4
The largest amount of data that can be transferred by a single bus cycle is an aligned word. If the MCU transfers a long-word operand through a 16-bit port, the most significant operand word is transferred on the first bus cycle and the least significant operand word is transferred on a following bus cycle.
4.4.5 Operand Transfer Cases
Table 4-13 is a summary of how operands are aligned for various types of transfers.
OPn entries are portions of a requested operand that are read or written during a bus cycle and are defined by SIZ1, SIZ0, and ADDR0 for that bus cycle. The following paragraphs discuss all the allowable transfer cases in detail.
Table 4-13 Operand Transfer Cases
Num Transfer Case SIZ
[1:0]
01 1 Byte to 8-Bit Port (Even/Odd)
2
3
Byte to 16-Bit Port (Even)
Byte to 16-Bit Port (Odd)
4 Word to 8-Bit Port (Aligned)
5 Word to 8-Bit Port (Misaligned)
1
6 Word to 16-Bit Port (Aligned)
7 Word to 16-Bit Port (Misaligned)
1
10
10
8 Long Word to 8-Bit Port (Aligned) 00
9 Long Word to 8-Bit Port (Misaligned)
1
10
10 Long Word to 16-Bit Port (Aligned) 00
11 Long Word to 16-Bit Port (Misaligned)
1
10
12 3 Byte to 8-Bit Port (Aligned)
2
13 3 Byte to 8-Bit Port (Misaligned)
2
11
11
01
01
10
10
0
1
0
1
0
1
0
1
ADDR0 DSACK
[1:0]
X 10
0
1
0
1
01
01
10
10
01
01
10
10
11
01
10
10
Read Cycles
DATA
[15:8]
OP0
DATA
[7:0]
—
OP0
—
OP0
OP0
OP0
—
OP0
OP0
OP0
—
OP0
OP0
—
—
—
OP1
OP0
—
—
Write Cycles
DATA
[15:8]
OP0
(OP0)
OP0
OP0
DATA
[7:0]
OP0 (OP0)
OP0 (OP0)
OP0 (OP0) OP0
OP0
OP0
(OP1)
(OP0)
OP1 OP0 OP1
OP0 (OP0) OP0
—
—
OP0
OP0
(OP1)
(OP0)
OP1
OP0
(OP1)
(OP0)
1. The CPU32 does not support misaligned transfers.
2. Three-byte transfer cases occur only as a result of a long word to byte transfer.
5
4
6
2
—
2
13
12
Next
Cycle
—
—
—
1
1
4.5 Bus Operation
Internal microcontroller modules are typically accessed in two system clock cycles, with no wait states. Regular external bus cycles use handshaking between the MCU and external peripherals to manage transfer size and data. These accesses take three system clock cycles, again with no wait states. During regular cycles, wait states can
be inserted as needed by bus control logic. Refer to 4.5.2 Regular Bus Cycles for
more information.
Fast-termination cycles, which are two-cycle external accesses with no wait states, use chip-select logic to generate handshaking signals internally. Chip-select logic can also be used to insert wait states before internal generation of handshaking signals.
Refer to 4.5.3 Fast Termination Cycles and 4.8 Chip Selects for more information.
Bus control signal timing, as well as chip-select signal timing, are specified in APPEN-
DIX A ELECTRICAL CHARACTERISTICS. Refer to the SIM Reference Manual (SIM-
RM/AD) for more information about each type of bus cycle.
The MCU is responsible for de-skewing signals it issues at both the start and the end of a cycle. In addition, the MCU is responsible for de-skewing acknowledge and data signals from peripheral devices.
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4.5.1 Synchronization to CLKOUT
External devices connected to the MCU bus can operate at a clock frequency different from the frequencies of the MCU as long as the external devices satisfy the interface signal timing constraints. Although bus cycles are classified as asynchronous, they are interpreted relative to the MCU system clock output (CLKOUT).
Descriptions are made in terms of individual system clock states, labeled {S0, S1,
S2,..., SN}. The designation “state” refers to the logic level of the clock signal, and does not correspond to any implemented machine state. A clock cycle consists of two
successive states. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for
more information.
Bus cycles terminated by DSACK assertion normally require a minimum of three CLK-
OUT cycles. To support systems that use CLKOUT to generate DSACK and other inputs, asynchronous input setup time and asynchronous input hold times are specified.
When these specifications are met, the MCU is guaranteed to recognize the appropriate signal on a specific edge of the CLKOUT signal.
For a read cycle, when assertion of DSACK is recognized on a particular falling edge of the clock, valid data is latched into the MCU on the next falling clock edge, provided that the data meets the data setup time. In this case, the parameter for asynchronous operation can be ignored.
When a system asserts DSACK for the required window around the falling edge of S2 and obeys the bus protocol by maintaining DSACK and BERR or HALT until and throughout the clock edge that negates AS, no wait states are inserted. The bus cycle runs at the maximum speed of three clocks per cycle.
To ensure proper operation in a system synchronized to CLKOUT when either BERR, or BERR and HALT is asserted after DSACK, BERR (or BERR and HALT) assertion must satisfy the appropriate data-in setup and hold times before the falling edge of the clock cycle after DSACK is recognized.
4.5.2 Regular Bus Cycles
The following paragraphs contain a discussion of cycles that use external bus control
logic. Refer to 4.5.3 Fast Termination Cycles for information about fast cycles.
To initiate a transfer, the MCU asserts an address and the SIZ[1:0] signals. The SIZ signals and ADDR0 are externally decoded to select the active portion of the data bus
(refer to 4.4.2 Dynamic Bus Sizing). When AS, DS, and R/W are valid, a peripheral
device either places data on the bus (read cycle) or latches data from the bus (write cycle), then asserts a DSACK[1:0] combination that indicates port size.
The DSACK[1:0] signals can be asserted before the data from a peripheral device is valid on a read cycle. To ensure valid data is latched into the MCU, a maximum period between DSACK assertion and DS assertion is specified.
There is no specified maximum for the period between the assertion of AS and
DSACK. Although the MCU can transfer data in a minimum of three clock cycles when
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the cycle is terminated with DSACK, the MCU inserts wait cycles in clock period increments until either DSACK signal goes low.
NOTE
The SIM bus monitor asserts BERR when response time exceeds a predetermined limit. Bus monitor period is determined by the BMT field in SYPCR. The bus monitor cannot be disabled; maximum monitor period is 64 system clock cycles.
If no peripheral responds to an access, or if an access is invalid, external logic should assert the BERR or HALT signals to abort the bus cycle (when BERR and HALT are asserted simultaneously, the CPU32 acts as though only BERR is asserted). If bus termination signals are not asserted within a specified period, the bus monitor terminates the cycle.
4.5.2.1 Read Cycle
During a read cycle, the MCU transfers data from an external memory or peripheral device. If the instruction specifies a long-word or word operation, the MCU attempts to read two bytes at once. For a byte operation, the MCU reads one byte. The portion of the data bus from which each byte is read depends on operand size, peripheral ad-
dress, and peripheral port size. Figure 4-9 is a flowchart of a word read cycle. Refer
to 4.4.2 Dynamic Bus Sizing, 4.4.4 Misaligned Operands, and the
SIM Reference
Manual (SIMRM/AD) for more information.
MCU
ADDRESS DEVICE (S0)
1) SET R/W TO READ
2) DRIVE ADDRESS ON ADDR[23:0]
3) DRIVE FUNCTION CODE ON FC[2:0]
4) DRIVE SIZ[1:0] FOR OPERAND SIZE
PERIPHERAL
4-24
ASSERT AS AND DS (S1)
DECODE DSACK (S3)
LATCH DATA (S4)
PRESENT DATA (S2)
1) DECODE ADDR, R/W, SIZ[1:0], DS
2) PLACE DATA ON DATA[15:0] OR
DATA[15:8] IF 8-BIT DATA
3) DRIVE DSACK SIGNALS
NEGATE AS AND DS (S5) TERMINATE CYCLE (S5)
1) REMOVE DATA FROM DATA BUS
2) NEGATE DSACK
START NEXT CYCLE (S0)
Figure 4-9 Word Read Cycle Flowchart
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4.5.2.2 Write Cycle
During a write cycle, the MCU transfers data to an external memory or peripheral device. If the instruction specifies a long-word or word operation, the MCU attempts to write two bytes at once. For a byte operation, the MCU writes one byte. The portion of the data bus upon which each byte is written depends on operand size, peripheral address, and peripheral port size.
Refer to 4.4.2 Dynamic Bus Sizing and 4.4.4 Misaligned Operands for more infor-
mation. Figure 4-10 is a flowchart of a write-cycle operation for a word transfer. Refer
to the SIM Reference Manual (SIMRM/AD) for more information.
MCU
ADDRESS DEVICE (S0)
1) SET R/W TO WRITE
2) DRIVE ADDRESS ON ADDR[23:0]
3) DRIVE FUNCTION CODE ON FC[2:0]
4) DRIVE SIZ[1:0] FOR OPERAND SIZE
PERIPHERAL
4
ASSERT AS (S1)
PLACE DATA ON DATA[15:0] (S2)
ASSERT DS AND WAIT FOR DSACK (S3) ACCEPT DATA (S2 + S3)
1) DECODE ADDRESS
2) LATCH DATA FROM DATA BUS
3) ASSERT DSACK SIGNALS
OPTIONAL STATE (S4)
NO CHANGE
TERMINATE OUTPUT TRANSFER (S5)
1) NEGATE DS AND AS
2) REMOVE DATA FROM DATA BUS
TERMINATE CYCLE
1) NEGATE DSACK
START NEXT CYCLE
Figure 4-10 Write Cycle Flowchart
WR CYC FLOW
4.5.3 Fast Termination Cycles
When an external device has a fast access time, the chip-select circuit fast-termination option can provide a two-cycle external bus transfer. Because the chip-select circuits
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are driven from the system clock, the bus cycle termination is inherently synchronized with the system clock.
If multiple chip selects are to be used to select the same device that can support fast termination, and match conditions can occur simultaneously, program the DSACK field in each associated chip-select option register for fast termination. Alternately, program one DSACK field for fast termination and the remaining DSACK fields for external termination.
Fast termination cycles use internal handshaking signals generated by the chip-select logic. To initiate a transfer, the MCU asserts an address and the SIZ[1:0] signals.
When AS, DS, and R/W are valid, a peripheral device either places data on the bus
(read cycle) or latches data from the bus (write cycle). At the appropriate time, chipselect logic asserts data and size acknowledge signals.
The DSACK option fields in the chip-select option registers determine whether internally generated DSACK or externally generated DSACK are used. For fast termination
cycles, the F-term encoding (%1110) must be used. Refer to 4.8.1 Chip-Select Reg-
isters for information about fast-termination setup.
To use fast-termination, an external device must be fast enough to have data ready,
within the specified setup time, by the falling edge of S4. Refer to APPENDIX A ELEC-
TRICAL CHARACTERISTICS for tabular information about fast termination timing.
When fast termination is in use, DS is asserted during read cycles but not during write cycles. The STRB field in the chip-select option register used must be programmed with the address strobe encoding to assert the chip select signal for a fast-termination write.
4.5.4 CPU Space Cycles
Function code signals FC[2:0] designate which of eight external address spaces is accessed during a bus cycle. Address space 7 is designated CPU space. CPU space is used for control information not normally associated with read or write bus cycles.
Function codes are valid only while AS is asserted. Refer to 4.4.1.7 Function Codes
for more information on codes and encoding.
During a CPU space access, ADDR[19:16] are encoded to reflect the type of access
being made. Figure 4-11 shows the three encodings used by 68300 family microcon-
trollers. These encodings represent breakpoint acknowledge (Type $0) cycles low power stop broadcast (Type $3) cycles, and interrupt acknowledge (Type $F) cycles.
Refer to 4.7 Interrupts for information about interrupt acknowledge bus cycles.
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BREAKPOINT
ACKNOWLEDGE
FUNCTION
CODE
2 0
1 1 1
CPU SPACE CYCLES
ADDRESS BUS
23 19 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4 2
BKPT#
1 0
T 0
LOW POWER
STOP BROADCAST
2 0
1 1 1
23 19 16 0
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
INTERRUPT
ACKNOWLEDGE
2 0
1 1 1
23 19 16
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0
LEVEL 1
CPU SPACE
TYPE FIELD
CPU SPACE CYC TIM
Figure 4-11 CPU Space Address Encoding
4.5.4.1 Breakpoint Acknowledge Cycle
Breakpoints stop program execution at a predefined point during system development.
Breakpoints can be used alone or in conjunction with the background debugging mode. The following paragraphs discuss breakpoint processing when background de-
bugging mode is not enabled. See SECTION 5 CENTRAL PROCESSING UNIT for
more information on exception processing and the background debugging mode.
In M68300 microcontrollers, both hardware and software can initiate breakpoints.
4.5.4.1.1 Software Breakpoints
The CPU32 BKPT instruction allows the user to insert breakpoints through software.
The CPU responds to this instruction by initiating a breakpoint-acknowledge read cycle in CPU space. It places the breakpoint acknowledge (%0000) code on AD-
DR[19:16], the breakpoint number (bits [2:0] of the BKPT opcode) in ADDR[4:2], and
%0 (indicating a software breakpoint) on ADDR1.
The external breakpoint circuitry decodes the function code and address lines and responds by either asserting BERR or placing an instruction word on the data bus and asserting DSACK.
If the bus cycle is terminated by DSACK, the CPU32 reads the instruction on the data bus and inserts the instruction into the pipeline. (For 8-bit ports, this instruction fetch may require two read cycles.)
If the bus cycle is terminated by BERR, the CPU32 then performs illegal-instruction exception processing: it acquires the number of the illegal-instruction exception vector, computes the vector address from this number, loads the content of the vector address into the PC, and jumps to the exception handler routine at that address.
4.5.4.1.2 Hardware Breakpoints
Assertion of the BKPT input initiates a hardware breakpoint. The CPU responds by initiating a breakpoint-acknowledge read cycle in CPU space. It places $00001E on the
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address bus. (The breakpoint acknowledge code of %0000 is placed on ADDR[19:16], the breakpoint number value of %111 is placed on ADDR[4:2], and ADDR1 is set to 1, indicating a hardware breakpoint.)
The external breakpoint circuitry decodes the function code and address lines, places an instruction word on the data bus, and asserts BERR. The CPU then performs hardware breakpoint exception processing: it acquires the number of the hardware breakpoint exception vector, computes the vector address from this number, loads the content of the vector address into the PC, and jumps to the exception handler routine at that address. If the external device asserts DSACK rather than BERR, the CPU ignores the breakpoint and continues processing.
When BKPT assertion is synchronized with an instruction prefetch, processing of the breakpoint exception occurs at the end of that instruction. The prefetched instruction is “tagged” with the breakpoint when it enters the instruction pipeline, and the breakpoint exception occurs after the instruction executes. If the pipeline is flushed before the tagged instruction is executed, no breakpoint occurs. When BKPT assertion is synchronized with an operand fetch, exception processing occurs at the end of the instruction during which BKPT is latched.
Refer to the CPU32 Reference Manual (CPU32RM/AD) and the SIM Reference Manual (SIMRM/AD) for additional information.
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CPU32
ACKNOWLEDGE BREAKPOINT
IF BREAKPOINT INSTRUCTION EXECUTED:
1) SET R/W TO READ
2) SET FUNCTION CODE TO CPU SPACE
3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16]
4) PLACE BREAKPOINT NUMBER ON ADDR[4:2]
5) CLEAR T-BIT (ADDR1) TO ZERO
6) SET SIZE TO WORD
7) ASSERT AS AND DS
IF BKPT PIN ASSERTED:
1) SET R/W TO READ
2) SET FUNCTION CODE TO CPU SPACE
3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16]
4) PLACE ALL ONES ON ADDR[4:2]
5) SET T-BIT (ADDR1) TO ONE
6) SET SIZE TO WORD
7) ASSERT AS AND DS
BREAKPOINT OPERATION FLOW
PERIPHERAL
IF BKPT INSTRUCTION EXECUTED:
1) PLACE REPLACEMENT OPCODE ON DATA BUS
2) ASSERT DSACK
OR:
1) ASSERT BERR TO INITIATE EXCEPTION PROCESSING
IF BKPT ASSERTED:
1) ASSERT DSACK
OR:
1) ASSERT BERR TO INITIATE EXCEPTION PROCESSING
IF BREAKPOINT INSTRUCTION EXECUTED AND
DSACK IS ASSERTED:
1) LATCH DATA
2) NEGATE AS AND DS
3) GO TO (A)
IF BKPT PIN ASSERTED AND
DSACK IS ASSERTED:
1) NEGATE AS AND DS
2) GO TO (A)
IF BERR ASSERTED:
1) NEGATE AS AND DS
2) GO TO (B)
(A)
(B)
4
IF BKPT INSTRUCTION EXECUTED:
1) PLACE LATCHED DATA IN INSTRUCTION PIPELINE
2) CONTINUE PROCESSING
IF BKPT PIN ASSERTED:
1) CONTINUE PROCESSING
IF BKPT INSTRUCTION EXECUTED:
1) INITIATE ILLEGAL INSTRUCTION PROCESSING
IF BKPT PIN ASSERTED:
1) INITIATE HARDWARE BREAKPOINT PROCESSING
1) NEGATE DSACK OR BERR
1110A
Figure 4-12 Breakpoint Operation Flowchart
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4.5.4.2 LPSTOP Broadcast Cycle
the STOP bits in each module configuration register or the SIM can turn off system clocks after execution of the LPSTOP instruction. When the CPU executes LPSTOP, the LPSTOP broadcast cycle is generated. The SIM brings the MCU out of low-power mode when either an interrupt of higher priority than the stored mask or a reset occurs.
Refer to 4.3.4 Low-Power Operation and SECTION 5 CENTRAL PROCESSING
UNIT for more information.
During an LPSTOP broadcast cycle, the CPU performs a CPU space write to address
$3FFFE. This write puts a copy of the interrupt mask value in the clock control logic.
The mask is encoded on the data bus as shown in Figure 4-13. The LPSTOP CPU
space cycle is shown externally (if the bus is available) as an indication to external devices that the MCU is going into low-power stop mode. The SIM provides an internally generated DSACK response to this cycle. The timing of this bus cycle is the same as for a fast write cycle.
4
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
Figure 4-13 LPSTOP Interrupt Mask Level
3
0
2 1
IP MASK
0
4.5.5 Bus Exception Control Cycles
An external device or a chip-select circuit must assert at least one of the DSACK[1:0] signals or the AVEC signal to terminate a bus cycle normally. Bus error processing occurs when bus cycles are not terminated in the expected manner. The internal bus monitor can be used to generate BERR internally, causing a bus error exception to be taken. Bus cycles can also be terminated by assertion of the external BERR or HALT signal, or by assertion of the two signals simultaneously.
Acceptable bus cycle termination sequences are summarized as follows. The case
numbers refer to Table 4-14, which indicates the results of each type of bus cycle ter-
mination.
Normal Termination
DSACK is asserted; BERR and HALT remain negated (case 1).
Halt Termination
HALT is asserted at the same time or before DSACK, and BERR remains negated
(case 2).
Bus Error Termination
BERR is asserted in lieu of, at the same time as, or before DSACK (case 3), or after
DSACK (case 4), and HALT remains negated; BERR is negated at the same time or after DSACK.
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Retry Termination
HALT and BERR are asserted in lieu of, at the same time as, or before DSACK
(case 5) or after DSACK (case 6); BERR is negated at the same time or after
DSACK; HALT may be negated at the same time or after BERR.
Table 4-14 shows various combinations of control signal sequences and the resulting
bus cycle terminations.
Table 4-14 DSACK, BERR, and HALT Assertion Results
Case
Number
1
2
3
4
5
6
Control
Signal
DSACK
BERR
HALT
DSACK-
BERR
HALT
DSACK-
BERR
HALT
DSACK-
BERR
HALT
DSACK-
BERR
HALT
DSACK-
BERR
HALT
NA/A
A
NA
A
A
NA
NA/A
A
A/S
A
NA
NA
Asserted on
Rising Edge of State
N N + 2
A
NA
NA
A
NA
A/S
S
NA
X
S
NA
S
X
A
A
X
S
S
X
S
X
X
S
NA
Normal termination.
Result
Halt termination: normal cycle terminate and halt.
Continue when HALT is negated.
Bus error termination: terminate and take bus error exception, possibly deferred.
Bus error termination: terminate and take bus error exception, possibly deferred.
Retry termination: terminate and retry when HALT is negated.
Retry termination: terminate and retry when HALT is negated.
NOTES:
N = The number of current even bus state (S2, S4, etc.).
A = Signal is asserted in this bus state.
NA = Signal is not asserted in this state.
X = Don't care.
S = Signal was asserted in previous state and remains asserted in this state.
To properly control termination of a bus cycle for a retry or a bus error condition,
DSACK, BERR, and HALT must be asserted and negated with the rising edge of the
MCU clock. This ensures that when two signals are asserted simultaneously, the required setup time and hold time for both of them are met for the same falling edge of
the MCU clock. (Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for timing
requirements.) External circuitry that provides these signals must be designed with these constraints in mind, or else the internal bus monitor must be used.
DSACK, BERR, and HALT may be negated after AS is negated.
WARNING
If DSACK or BERR remain asserted into S2 of the next bus cycle, that cycle may be terminated prematurely.
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4.5.5.1 Bus Errors
The CPU32 treats bus errors as a type of exception. Bus error exception processing begins when the CPU detects assertion of the IMB BERR signal (by the internal bus monitor or an external source) while the HALT signal remains negated.
BERR assertions do not force immediate exception processing. The signal is synchronized with normal bus cycles and is latched into the CPU32 at the end of the bus cycle in which it was asserted. Because bus cycles can overlap instruction boundaries, bus error exception processing may not occur at the end of the instruction in which the bus cycle begins. Timing of BERR detection/acknowledge is dependent upon several factors:
• Which bus cycle of an instruction is terminated by assertion of BERR.
• The number of bus cycles in the instruction during which BERR is asserted.
• The number of bus cycles in the instruction following the instruction in which
BERR is asserted.
• Whether BERR is asserted during a program space access or a data space access.
Because of these factors, it is impossible to predict precisely how long after occurrence of a bus error the bus error exception is processed.
CAUTION
The external bus interface does not latch data when an external bus cycle is terminated by a bus error. When this occurs during an instruction prefetch, the IMB precharge state (bus pulled high, or $FF) is latched into the CPU32 instruction register, with indeterminate results.
4.5.5.2 Double Bus Faults
Exception processing for bus error exceptions follows the standard exception process-
ing sequence. Refer to SECTION 5 CENTRAL PROCESSING UNIT for more informa-
tion about exceptions. However, a special case of bus error, called double bus fault, can abort exception processing.
BERR assertion is not detected until an instruction is complete. The BERR latch is cleared by the first instruction of the BERR exception handler. Double bus fault occurs in two ways:
1. When bus error exception processing begins and a second BERR is detected before the first instruction of the first exception handler is executed.
2. When one or more bus errors occur before the first instruction after a RESET exception is executed.
3. A bus error occurs while the CPU32 is loading information from a bus error stack frame during a return from exception (RTE) instruction.
Multiple bus errors within a single instruction that can generate multiple bus cycles cause a single bus error exception after the instruction has been executed.
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Immediately after assertion of a second BERR, the MCU halts and drives the HALT line low. Only a reset can restart a halted MCU. However, bus arbitration can still occur
(refer to 4.5.6 External Bus Arbitration). A bus error or address error that occurs after
exception processing has been completed (during the execution of the exception handler routine, or later) does not cause a double bus fault. The MCU continues to retry the same bus cycle as long as the external hardware requests it.
4.5.5.3 Retry Operation
BERR and HALT during a bus cycle, the MCU enters the retry sequence. A delayed retry can also occur. The MCU terminates the bus cycle, places the AS and DS signals in their inactive state, and does not begin another bus cycle until the BERR and HALT signals are negated by external logic. After a synchronization delay, the MCU retries the previous cycle using the same address, function codes, data (for a write), and control signals. The BERR signal should be negated before S2 of the read cycle to ensure correct operation of the retried cycle.
If BR, BERR, and HALT are all asserted on the same cycle, the EBI will enter the rerun sequence but first relinquishes the bus to an external master. Once the external master returns the bus and negates BERR and HALT, the EBI runs the previous bus cycle.
This feature allows an external device to correct the problem that caused the bus error and then try the bus cycle again.
The MCU retries any read or write cycle of an indivisible read-modify-write operation separately; RMC remains asserted during the entire retry sequence. The MCU will not relinquish the bus while RMC is asserted. Any device that requires the MCU to give up the bus and retry a bus cycle during a read-modify-write cycle must assert BERR and
BR only (HALT must remain negated). The bus error handler software should examine the read-modify-write bit in the special status word and take the appropriate action to resolve this type of fault when it occurs.
4.5.5.4 Halt Operation
When HALT is asserted while BERR is not asserted, the MCU halts external bus activity after negation of DSACK. The MCU may complete the current word transfer in progress. For a long-word to byte transfer, this could be after S2 or S4. For a word to byte transfer, activity ceases after S2.
Negating and reasserting HALT according to timing requirements provides single-step
(bus cycle to bus cycle) operation. The HALT signal affects external bus cycles only, so that a program that does not use external bus can continue executing. During dynamically-sized 8-bit transfers, external bus activity may not stop at the next cycle boundary. Occurrence of a bus error while HALT is asserted causes the CPU32 to initiate a retry sequence.
When the MCU completes a bus cycle while the HALT signal is asserted, the data bus goes to high-impedance state and the AS and DS signals are driven to their inactive states. Address, function code, size, and read/write signals remain in the same state.
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The halt operation has no effect on bus arbitration (refer to 4.5.6 External Bus Arbi-
tration). However, when external bus arbitration occurs while the MCU is halted, ad-
dress and control signals go to high-impedance state. If HALT is still asserted when the MCU regains control of the bus, address, function code, size, and read/write signals revert to the previous driven states. The MCU cannot service interrupt requests while halted.
4.5.6 External Bus Arbitration
MCU bus design provides for a single bus master at any one time. Either the MCU or an external device can be master. Bus arbitration protocols determine when an external device can become bus master. Bus arbitration requests are recognized during normal processing, HALT assertion, and when the CPU has halted due to a double bus fault.
The bus controller in the MCU manages bus arbitration signals so that the MCU has the lowest priority. External devices that need to obtain the bus must assert bus arbitration signals in the sequences described in the following paragraphs.
Systems that include several devices that can become bus master require external circuitry to assign priorities to the devices, so that when two or more external devices attempt to become bus master at the same time, the one having the highest priority becomes bus master first. The protocol sequence is:
1. An external device asserts bus request signal (BR);
2. The MCU asserts the bus grant signal (BG) to indicate that the bus is available;
3. An external device asserts the bus grant acknowledge (BGACK) signal to indicate that it has assumed bus mastership.
BR can be asserted during a bus cycle or between cycles. BG is asserted in response to BR. To guarantee operand coherency, BG is only asserted at the end of operand transfer. Additionally, BG is not asserted until the end of an indivisible read-modifywrite operation (when RMC is negated).
If more than one external device can be bus master, required external arbitration must begin when a requesting device receives BG. An external device must assert BGACK when it assumes mastership, and must maintain BGACK assertion as long as it is bus master.
Two conditions must be met for an external device to assume bus mastership. The device must receive BG through the arbitration process, and BGACK must be inactive, indicating that no other bus master is active. This technique allows the processing of bus requests during data transfer cycles.
BG is negated a few clock cycles after BGACK transition. However, if bus requests are still pending after BG is negated, the MCU asserts BG again within a few clock cycles.
This additional BG assertion allows external arbitration circuitry to select the next bus master before the current master has released the bus.
Refer to Figure 4-14, which shows bus arbitration for a single device. The flowchart
shows BR negated at the same time BGACK is asserted.
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MCU
GRANT BUS ARBITRATION
1) ASSERT BUS GRANT (BG)
TERMINATE ARBITRATION
1) NEGATE BG (AND WAIT FOR
BGACK TO BE NEGATED)
RE-ARBITRATE OR RESUME PROCESSOR
OPERATION
REQUESTING DEVICE
REQUEST THE BUS
1) ASSERT BUS REQUEST (BR)
ACKNOWLEDGE BUS MASTERSHIP
1) EXTERNAL ARBITRATION DETERMINES
NEXT BUS MASTER
2) NEXT BUS MASTER WAITS FOR BGACK
TO BE NEGATED
3) NEXT BUS MASTER ASSERTS BGACK
TO BECOME NEW MASTER
4) BUS MASTER NEGATES BR
OPERATE AS BUS MASTER
1) PERFORM DATA TRANSFERS (READ AND
WRITE CYCLES) ACCORDING TO THE
SAME RULES THE PROCESSOR USES
RELEASE BUS MASTERSHIP
1) NEGATE BGACK
BUS ARB FLOW
Figure 4-14 Bus Arbitration Flowchart for Single Request
State changes occur on the next rising edge of CLKOUT after the internal signal is valid. The BG signal transitions on the falling edge of the clock after a state is reached during which G changes. The bus control signals (controlled by T) are driven by the
MCU immediately following a state change, when bus mastership is returned to the
MCU. State 0, in which G and T are both negated, is the state of the bus arbiter while the MCU is bus master. Request R and acknowledge A keep the arbiter in state 0 as long as they are both negated.
4.5.6.1 Slave (Factory Test) Mode Arbitration
This mode is used for factory production testing of internal modules. It is not supported as a user operating mode. Slave mode is enabled by holding DATA11 low during reset. In slave mode, when BG is asserted, the MCU is slaved to an external master that has full access to all internal registers.
4.5.6.2 Show Cycles
The MCU normally performs internal data transfers without affecting the external bus, but it is possible to show these transfers during debugging. AS is not asserted externally during show cycles.
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Show cycles are controlled by the SHEN field in the SIMCR (refer to 4.2.3 Show In-
ternal Cycles). This field is cleared by reset. When show cycles are disabled, the ad-
dress bus, function codes, size, and read/write signals reflect internal bus activity, but
AS and DS are not asserted externally and external data bus pins are in high-impedance state during internal accesses.
When show cycles are enabled, DS is asserted externally during internal cycles, and internal data is driven out on the external data bus. Because internal cycles normally continue to run when the external bus is granted, one SHEN encoding halts internal bus activity while there is an external master.
SIZ[1:0] signals reflect bus allocation during show cycles. Only the appropriate portion of the data bus is valid during the cycle. During a byte write to an internal address, the portion of the bus that represents the byte that is not written reflects internal bus conditions, and is indeterminate. During a byte write to an external address, the data multiplexer in the SIM causes the value of the byte that is written to be driven out on both bytes of the data bus.
4.6 Reset
Reset occurs when an active low logic level on the RESET pin is clocked into the SIM.
The RESET input is synchronized to the system clock. If there is no clock when RE-
SET is asserted, reset does not occur until the clock starts. Resets are clocked to allow completion of write cycles in progress at the time RESET is asserted.
Reset procedures handle system initialization and recovery from catastrophic failure.
The MCU performs resets with a combination of hardware and software. The system integration module determines whether a reset is valid, asserts control signals, performs basic system configuration and boot ROM selection based on hardware modeselect inputs, then passes control to the CPU32.
4.6.1 Reset Exception Processing
The CPU32 processes resets as a type of asynchronous exception. An exception is an event that preempts normal processing, and can be caused by internal or external events. Exception processing makes the transition from normal instruction execution to execution of a routine that deals with an exception. Each exception has an assigned vector that points to an associated handler routine. These vectors are stored in the vector base register (VBR). The VBR contains the base address of a 1024-byte exception vector table, which consists of 256 exception vectors. The CPU32 uses vector
numbers to calculate displacement into the table. Refer to SECTION 5 CENTRAL
PROCESSING UNIT for more information concerning exceptions.
Reset is the highest-priority CPU32 exception. Unlike all other exceptions, a reset occurs at the end of a bus cycle, and not at an instruction boundary. Handling resets in this way prevents write cycles in progress at the time the reset signal is asserted from being corrupted. However, any processing in progress is aborted by the reset exception, and cannot be restarted. Only essential reset tasks are performed during exception processing. Other initialization tasks must be accomplished by the exception
handler routine. 4.6.8 Reset Processing Summary contains details of exception pro-
cessing.
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4.6.2 Reset Control Logic
SIM reset control logic determines the cause of a reset, synchronizes reset assertion if necessary to the completion of the current bus cycle, and asserts the appropriate reset lines. Reset control logic can drive four different internal signals.
1. EXTRST (external reset) drives the external reset pin.
2. CLKRST (clock reset) resets the clock module.
3. MSTRST (master reset) goes to all other internal circuits.
4. SYSRST (system reset) indicates to internal circuits that the CPU has executed a RESET instruction.
All resets are gated by CLKOUT. Resets are classified as synchronous or asynchronous. An asynchronous reset can occur on any CLKOUT edge. Reset sources that cause an asynchronous reset usually indicate a catastrophic failure; thus the reset control logic responds by asserting reset to the system immediately. (A system reset, however, caused by the CPU32 RESET instruction, is asynchronous but does not indicate any type of catastrophic failure).
Synchronous resets are timed (CLKOUT) to occur at the end of bus cycles. The internal bus monitor is automatically enabled for synchronous resets. When a bus cycle does not terminate normally, the bus monitor terminates it.
Refer to Table 4-15 for a summary of reset sources.
4
Table 4-15 Reset Source Summary
Type
External
Power Up
Source
External
EBI
Software Watchdog Monitor
HALT Monitor
Loss of Clock
Test
System
Clock
Test
CPU32
Timing
Synch
Asynch
Asynch
Asynch
Synch
Synch
Asynch
Cause
External Signal
V
DD
Time Out
Internal HALT Assertion
(e.g. Double Bus Fault)
Loss of Reference
Test Mode
RESET Instruction
Reset Lines Asserted by Controller
MSTRST CLKRST EXTRST
MSTRST CLKRST EXTRST
MSTRST
MSTRST
CLKRST
CLKRST
EXTRST
EXTRST
MSTRST
MSTRST
—
CLKRST
—
—
EXTRST
EXTRST
EXTRST
Internal single byte or aligned word writes are guaranteed valid for synchronous resets. External writes are also guaranteed to complete, provided the external configu-
ration logic on the data bus is conditioned as shown in Figure 4-15.
4.6.3 Reset Mode Selection
The logic states of certain data bus pins during reset determine SIM operating configuration. In addition, the state of the MODCLK pin determines system clock source and the state of the BKPT pin determines what happens during subsequent breakpoint as-
sertions. Table 4-16 is a summary of reset mode selection options.
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4
Mode Select Pin
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA11
MODCLK
BKPT
Table 4-16 Reset Mode Selection
Default Function
(Pin Left High)
CSBOOT 16-Bit
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS[7:6]
CS[8:6]
CS[9:6]
CS[10:6]
DSACK[1:0],
AVEC, DS, AS,
SIZE
IRQ[7:1]
MODCLK
Test Mode Disabled
VCO = System Clock
Background Mode Disabled
Alternate Function
(Pin Pulled Low)
CSBOOT 8-Bit
BR
BG
BGACK
FC0
FC1
FC2
ADDR19
ADDR[20:19]
ADDR[21:19]
ADDR[22:19]
ADDR[23:19]
PORTE
PORTF
Test Mode Enabled
EXTAL = System Clock
Background Mode Enabled
4.6.3.1 Data Bus Mode Selection
All data lines have weak internal pull-up drivers. When pins are held high by the internal drivers, the MCU uses a default operating configuration. However, specific lines can be held low externally to achieve an alternate configuration.
NOTE
External bus loading can overcome the weak internal pull-up drivers on data bus lines, and hold pins low during reset.
Use an active device to hold data bus lines low. Data bus configuration logic must release the bus before the first bus cycle after reset to prevent conflict with external memory devices. The first bus cycle occurs ten CLKOUT cycles after RESET is released. If external mode selection logic causes a conflict of this type, an isolation re-
sistor on the driven lines may be required. Figure 4-15 shows a recommended method
for conditioning the mode select signals.
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MODE SELECT
LINES
••
••
••
DATA15
DATA1
DATA0
V
DD
V
DD
••
••
••
* * *
RESET
• • • • • •
DS
R/W
*
Optional, to prevent conflict on RESET negation.
Figure 4-15 Data Bus Mode Select Conditioning
DATA BUS MODE DECODE
Data bus mode select current is specified in APPENDIX A ELECTRICAL CHARAC-
TERISTICS. Do not confuse pin function with pin electrical state. Refer to 4.6.5 Pin
State During Reset for more information.
DATA0 determines the function of the boot ROM chip-select signal (CSBOOT). Unlike other chip-select signals, CSBOOT is active at the release of reset. During reset exception processing, the MCU fetches initialization vectors beginning at address
$000000 in supervisor program space. An external memory device containing vectors located at these addresses can be enabled by CSBOOT after a reset. The logic level of DATA0 during reset selects boot ROM port size for dynamic bus allocation. When
DATA0 is held low, port size is eight bits; when DATA0 is held high, either by the weak
internal pull-up driver or by an external pull-up, port size is 16 bits. Refer to 4.8.4 Chip-
Select Reset Operation for more information.
DATA1 and DATA2 determine the functions of CS[2:0] and CS[5:3], respectively. DA-
TA[7:3] determine the functions of an associated chip select and all lower-numbered chip-selects down through CS6. For example, if DATA5 is pulled low during reset,
CS[8:6] are assigned alternate function as ADDR[21:19], and CS[10:9] remain chip-
selects. Refer to 4.8.4 Chip-Select Reset Operation for more information.
DATA8 determines the function of the DSACK[1:0], AVEC, DS, AS, and SIZE pins. If
DATA8 is held low during reset, these pins are assigned to I/O port E.
DATA9 determines the function of interrupt request pins IRQ[7:0] and the clock mode select pin (MODCLK). When DATA9 is held low during reset, these pins are assigned to I/O port F.
DATA11 determines whether the SIM operates in test mode out of reset. This capability is used for factory testing of the MCU.
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4.6.3.2 Clock Mode Selection
The state of the clock mode (MODCLK) pin during reset determines what clock source the MCU uses. When MODCLK is held high during reset, the clock signal is generated from a reference frequency. When MODCLK is held low during reset, the clock syn-
thesizer is disabled, and an external system clock signal must be applied. Refer to 4.3
System Clock for more information.
NOTE
The MODCLK pin can also be used as parallel I/O pin PF0. To prevent inadvertent clock mode selection by logic connected to port F, use an active device to drive MODCLK during reset.
4.6.3.3 Breakpoint Mode Selection
The MCU uses internal and external breakpoint (BKPT) signals. During reset exception processing, at the release of the RESET signal, the CPU32 samples these signals to determine how to handle breakpoints.
If either BKPT signal is at logic level zero when sampled, an internal BDM flag is set, and the CPU32 enters background debugging mode whenever either BKPT input is subsequently asserted.
If both BKPT inputs are at logic level one when sampled, breakpoint exception processing begins whenever either BKPT signal is subsequently asserted.
Refer to SECTION 5 CENTRAL PROCESSING UNIT for more information on back-
ground debugging mode and exceptions. Refer to 4.5.4 CPU Space Cycles for infor-
mation concerning breakpoint acknowledge bus cycles.
4.6.4 MCU Module Pin Function During Reset
Usually, module pins default to port functions, and input/output ports are set to input state. This is accomplished by disabling pin functions in the appropriate control registers, and by clearing the appropriate port data direction registers. Refer to individual
module sections in this manual for more information. Table 4-17 is a summary of mod-
ule pin function out of reset. Refer to APPENDIX D REGISTER SUMMARY for register
function and reset state.
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Module
CPU32
GPT
QSM
Table 4-17 Module Pin Functions
Pin Mnemonic
DSI/IFETCH
DSO/IPIPE
BKPT/DSCLK
PGP7/IC4/OC5
PGP[6:3]/OC[4:1]
PGP[2:0]/IC[3:1]
PAI
PCLK
PWMA, PWMB
PQS7/TXD
PQS[6:4]/PCS[3:1]
PQS3/PCS0/SS
PQS2/SCK
PQS1/MOSI
PQS0/MISO
RXD
Function
DSI/IFETCH
DSO/IPIPE
BKPT/DSCLK
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Output
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
RXD
4.6.5 Pin State During Reset
It is important to keep the distinction between pin function and pin electrical state clear.
Although control register values and mode select inputs determine pin function, a pin driver can be active, inactive or in high-impedance state while reset occurs. During
power-up reset, pin state is subject to the constraints discussed in 4.6.7 Power-On
Reset.
NOTE
Pins that are not used should either be configured as outputs, or (if configured as inputs) pulled to the appropriate inactive state. This decreases additional I
DD
caused by digital inputs floating near mid-supply level.
4.6.5.1 Reset States of SIM Pins
Generally, while RESET is asserted, SIM pins either go to an inactive high-impedance state or are driven to their inactive states. After RESET is released, mode selection occurs, and reset exception processing begins. Pins configured as inputs during reset become active high-impedance loads after RESET is released. Inputs must be driven to the desired active state. Pull-up or pull-down circuitry may be necessary. Pins con-
figured as outputs begin to function after RESET is released. Table 4-18 is a summary
of SIM pin states during reset.
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4
Mnemonic
CS10/ADDR23
CS[9:6]/ADDR[22:19]/PC[6:3]
ADDR[18:0]
AS/PE5
AVEC/PE2
BERR
CSM/BG
CSE/BGACK
CS0/BR
CLKOUT
CSBOOT
DATA[15:0]
DS/PE4
DSACK0/PE0
DSACK1/PE1
CS5/FC2/PC2
FC1/PC1
CS3/FC0/PC0
HALT
IRQ[7:1]/PF[7:1]
MODCLK/PF0
R/W
RESET
RMC
SIZ[1:0]/PE[7:6]
TSC
Table 4-18 SIM Pin Reset States
State While
RESET
Asserted
1
1
Pin
Function
Pin State After RESET Released
Pin State Pin
Function
Pin State
CS10
CS[9:6]
1
1
ADDR23
ADDR[22:19]
Unknown
Unknown
High-Z Output ADDR[18:0] Unknown ADDR[18:0] Unknown
High-Z Output AS Output PE5 Input
Disabled AVEC
Disabled BERR
1
1
CSM
CSE
Input
Input
1
1
PE2
BERR
BG
BGACK
Input
Input
1
Input
1
Output
1
Mode Select
CS0
CLKOUT
CSBOOT
DATA[15:0]
Disabled DS
Disabled DSACK0
Disabled DSACK1
1 CS5
1
Output
0
Input
Output
Input
Input
1
BR
CLKOUT
CSBOOT
DATA[15:0]
PE4
PE0
PE1
FC2
Input
Output
0
Input
Input
Input
Input
Unknown
1
1
FC1
CS3
1
1
Disabled HALT Input
Disabled IRQ[7:1] Input
Mode Select
Disabled
Asserted
Disabled
MODCLK
R/W
RESET
RMC
Disabled SIZ[1:0]
Mode Select TSC
Input
Output
Input
Output
Unknown
Input
FC1
FC0
HALT
PF[7:1]
PF0
R/W
RESET
PE3
PE[7:6]
TSC
Unknown
Unknown
Input
Input
Input
Output
Input
Input
Input
Input
4.6.5.2 Reset States of Pins Assigned to Other MCU Modules
As a rule, module pins that are assigned to general-purpose I/O ports go to active highimpedance state following reset. Other pin states are determined by individual module control register settings. Refer to sections concerning modules for details. However, during power-up reset, module port pins may be in an indeterminate state for a short
period. Refer to 4.6.7 Power-On Reset for more information.
4.6.6 Reset Timing
The RESET input must be asserted for a specified minimum period for reset to occur.
External RESET assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus monitor time-out period) in order to protect write cycles from being aborted by reset. While RESET is asserted, SIM pins are either in an inactive, high impedance state or are driven to their inactive states.
When an external device asserts RESET for the proper period, reset control logic clocks the signal into an internal latch. The control logic drives the RESET pin low for an additional 512 CLKOUT cycles after it detects that the RESET signal is no longer being externally driven, to guarantee this length of reset to the entire system.
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If an internal source asserts a reset signal, the reset control logic asserts RESET for a minimum of 512 cycles. If the reset signal is still asserted at the end of 512 cycles, the control logic continues to assert RESET until the internal reset signal is negated.
After 512 cycles have elapsed, the reset input pin goes to an inactive, high-impedance state for ten cycles. At the end of this 10-cycle period, the reset input is tested. When the input is at logic level one, reset exception processing begins. If, however, the reset input is at logic level zero, the reset control logic drives the pin low for another 512 cycles. At the end of this period, the pin again goes to high-impedance state for ten cycles, then it is tested again. The process repeats until RESET is released.
4.6.7 Power-On Reset
When the SIM clock synthesizer is used to generate system clocks, power-on reset involves special circumstances related to application of system and clock synthesizer power. Regardless of clock source, voltage must be applied to clock synthesizer power input pin V
DDSYN
for the MCU to operate. The following discussion assumes that
V
DDSYN
is applied before and during reset, which minimizes crystal start-up time.
When V
DDSYN
is applied at power-on, start-up time is affected by specific crystal parameters and by oscillator circuit design. V
DD
ramp-up time also affects pin state dur-
ing reset. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for voltage and
timing specifications.
During power-on reset, an internal circuit in the SIM drives the IMB internal (MSTRST) and external (EXTRST) reset lines. The circuit releases MSTRST as V
DD
ramps up to
the minimum specified value, and SIM pins are initialized as shown in Table 4-19. As
V
DD
reaches specified minimum value, the clock synthesizer VCO begins operation and clock frequency ramps up to specified limp mode frequency. The external RESET line remains asserted until the clock synthesizer PLL locks and 512 CLKOUT cycles elapse line remains asserted until the clock synthesizer PLL locks and 512 CLKOUT cycles elapse.
The SIM clock synthesizer provides clock signals to the other MCU modules. After the clock is running and MSTRST is asserted for at least four clock cycles, these modules reset. V
DD
ramp time and VCO frequency ramp time determine how long the four cycles take. Worst case is approximately 15 milliseconds. During this period, module port pins may be in an indeterminate state. While input-only pins can be put in a known state by external pull-up resistors, external logic on input/output or output-only pins during this time must condition the lines. Active drivers require high-impedance buffers or isolation resistors to prevent conflict.
Figure 4-16 is a timing diagram of power-up reset. It shows the relationships between
RESET, V
DD
, and bus signals.
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CLKOUT
VCO
LOCK
VDD
RESET
BUS
CYCLES
BUS STATE
UNKNOWN
NOTES:
1. Internal start-up time.
2. SSP fetched.
3. PC fetched.
4. First instruction fetched.
512 CLOCKS
10 CLOCKS
ADDRESS AND
CONTROL SIGNALS
THREE-STATED
1 2 3
4
Figure 4-16 Power-On Reset
4.6.8 Reset Processing Summary
To prevent write cycles in progress from being corrupted, a reset is recognized at the end of a bus cycle, and not at an instruction boundary. Any processing in progress at the time a reset occurs is aborted. After SIM reset control logic has synchronized an internal or external reset request, it asserts the MSTRST signal.
The following events take place when MSTRST is asserted.
A. Instruction execution is aborted.
B. The status register is initialized.
1. The T0 and T1 bits are cleared to disable tracing.
2. The S bit is set to establish supervisor privilege level.
3. The interrupt priority mask is set to $7, disabling all interrupts below priority
7.
C. The vector base register is initialized to $000000.
The following events take place when MSTRST is negated after assertion.
A. The CPU32 samples the BKPT input.
B. The CPU32 fetches the reset vector:
1. The first long word of the vector is loaded into the interrupt stack pointer.
2. The second long word of the vector is loaded into the program counter.
Vectors can be fetched from internal RAM or from external ROM enabled by the CSBOOT signal.
C. The CPU32 fetches and begins decoding the first instruction to be executed.
4
32 POR TIM
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4.6.9 Reset Status Register
The reset status register (RSR) contains a bit for each reset source in the MCU. When a reset occurs, a bit corresponding to the reset type is set. When multiple causes of reset occur at the same time, more than one bit in RSR may be set. The reset status register is updated by the reset control logic when the RESET signal is released. Refer
to APPENDIX D REGISTER SUMMARY.
4.7 Interrupts
Interrupt recognition and servicing involve complex interaction between the system integration module, the central processing unit, and a device or module requesting interrupt service. This discussion provides an overview of the entire interrupt process.
Chip-select logic can also be used to respond to interrupt requests. Refer to 4.8 Chip
Selects for more information.
4.7.1 Interrupt Exception Processing
The CPU32 processes resets as a type of asynchronous exception. An exception is an event that preempts normal processing. Each exception has an assigned vector in an exception vector table that points to an associated handler routine. The CPU uses vector numbers to calculate displacement into the table. During exception processing, the CPU fetches the appropriate vector and executes the exception handler routine to which the vector points.
Out of reset, the exception vector table is located beginning at address $000000. This value can be changed by programming the vector base register (VBR) with a new val-
ue, and multiple vector tables can be used. Refer to SECTION 5 CENTRAL PRO-
CESSING UNIT for more information concerning exceptions.
4.7.2 Interrupt Priority and Recognition
The CPU32 provides eight levels of interrupt priority. All interrupts with priorities less than seven can be masked by the interrupt priority (IP) field in status register.
There are seven interrupt request signals (IRQ[7:1]). These signals are used internally on the IMB, and are corresponding pins for external interrupt service requests. The
CPU treats all interrupt requests as though they come from internal modules — external interrupt requests are treated as interrupt service requests from the SIM. Each of the interrupt request signals corresponds to an interrupt priority level. IRQ1 has the lowest priority and IRQ7 the highest.
Interrupt recognition is determined by interrupt priority level and interrupt priority mask value, interrupt recognition is determined by interrupt priority level and interrupt priority mask value. The interrupt priority mask consists of three bits in the CPU32 status register. Binary values %000 to %111 provide eight priority masks. Masks prevent an interrupt request of a priority less than or equal to the mask value from being recognized and processed. IRQ7, however, is always recognized, even if the mask value is %111.
IRQ[7:1] are active-low level-sensitive inputs. The low on the pin must remain asserted until an interrupt acknowledge cycle corresponding to that level is detected.
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IRQ7 is transition-sensitive as well as level-sensitive: a level-7 interrupt is not detected unless a falling edge transition is detected on the IRQ7 line. This prevents redundant servicing and stack overflow. A nonmaskable interrupt is generated each time IRQ7 is asserted as well as each time the priority mask changes from %111 to a lower number while IRQ7 is asserted.
Interrupt requests are sampled on consecutive falling edges of the system clock. Interrupt request input circuitry has hysteresis: to be valid, a request signal must be asserted for at least two consecutive clock periods. Valid requests do not cause immediate exception processing, but are left pending. Pending requests are processed at instruction boundaries or when exception processing of higher-priority exceptions is complete.
The CPU32 does not latch the priority of a pending interrupt request. If an interrupt source of higher priority makes a service request while a lower priority request is pending, the higher priority request is serviced. If an interrupt request with a priority equal to or lower than the current IP mask value is made, the CPU32 does not recognize the occurrence of the request. If simultaneous interrupt requests of different priorities are made, and both have a priority greater than the mask value, the CPU32 recognizes the higher-level request.
4.7.3 Interrupt Acknowledge and Arbitration
When the CPU32 detects one or more interrupt requests of a priority higher than the interrupt priority mask value, it places the interrupt request level on the address bus and initiates a CPU space read cycle. The request level serves two purposes: it is decoded by modules or external devices that have requested interrupt service, to determine whether the current interrupt acknowledge cycle pertains to them, and it is latched into the interrupt priority mask field in the CPU32 status register, to preclude further interrupts of lower priority during interrupt service.
Modules or external devices that have requested interrupt service must decode the interrupt priority mask value placed on the address bus during the interrupt acknowledge cycle and respond if the priority of the service request corresponds to the mask value.
However, before modules or external devices respond, interrupt arbitration takes place.
Arbitration is performed by means of serial contention between values stored in individual module interrupt arbitration (IARB) fields. Each module that can make an interrupt service request, including the SIM, has an IARB field in its configuration register.
IARB fields can be assigned values from %0000 to %1111. In order to implement an arbitration scheme, each module that can initiate an interrupt service request must be assigned a unique, non-zero IARB field value during system initialization. Arbitration priorities range from %0001 (lowest) to %1111 (highest) — if the CPU recognizes an interrupt service request from a source that has an IARB field value of %0000, a spurious interrupt exception is processed.
WARNING
Do not assign the same arbitration priority to more than one module.
When two or more IARB fields have the same nonzero value, the
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CPU32 interprets multiple vector numbers at the same time, with unpredictable consequences.
Because the EBI manages external interrupt requests, the SIM IARB value is used for arbitration between internal and external interrupt requests. The reset value of IARB for the SIM is %1111, and the reset IARB value for all other modules is %0000.
Although arbitration is intended to deal with simultaneous requests of the same priority, it always takes place, even when a single source is requesting service. This is important for two reasons: the EBI does not transfer the interrupt acknowledge read cycle to the external bus unless the SIM wins contention, and failure to contend causes the interrupt acknowledge bus cycle to be terminated early, by a bus error.
When arbitration is complete, the module with the highest arbitration priority must terminate the bus cycle. Internal modules place an interrupt vector number on the data bus and generate appropriate internal cycle termination signals. In the case of an external interrupt request, after the interrupt acknowledge cycle is transferred to the external bus, the appropriate external device must decode the mask value and respond with a vector number, then generate data and size acknowledge (DSACK) termination signals, or it must assert the autovector (AVEC) request signal. If the device does not respond in time, the EBI bus monitor asserts the bus error signal BERR, and a spurious interrupt exception is taken.
Chip-select logic can also be used to generate internal AVEC or DSACK signals in re-
sponse to interrupt requests from external devices (refer to 4.8.3 Using Chip-Select
Signals for Interrupt Acknowledge). Chip-select address match logic functions only
after the EBI transfers an interrupt acknowledge cycle to the external bus following
IARB contention. If a module makes an interrupt request of a certain priority, and the appropriate chip-select registers are programmed to generate AVEC or DSACK signals in response to an interrupt acknowledge cycle for that priority level, chip-select logic does not respond to the interrupt acknowledge cycle, and the internal module supplies a vector number and generates internal cycle termination signals.
For periodic timer interrupts, the PIRQ field in the periodic interrupt control register (PI-
CR) determines PIT priority level. A PIRQ value of %000 means that PIT interrupts are inactive. By hardware convention, when the CPU32 receives simultaneous interrupt requests of the same level from more than one SIM source (including external devices), the periodic interrupt timer is given the highest priority, followed by the IRQ pins.
4.7.4 Interrupt Processing Summary
A summary of the entire interrupt processing sequence follows. When the sequence begins, a valid interrupt service request has been detected and is pending.
A. The CPU finishes higher priority exception processing or reaches an instruction boundary.
B. The processor state is stacked. The S bit in the status register is set, establishing supervisor access level, and bits T1 and T0 are cleared, disabling tracing.
C. The interrupt acknowledge cycle begins:
1. FC[2:0] are driven to %111 (CPU space) encoding.
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2. The address bus is driven as follows: ADDR[23:20] = %1111; ADDR[19:16]
= %1111, which indicates that the cycle is an interrupt acknowledge CPU space cycle; ADDR[15:4] = %111111111111; ADDR[3:1] = the priority of the interrupt request being acknowledged; and ADDR0 = %1.
3. The request level is latched from the address bus into the interrupt priority mask field in the status or condition code register.
D. Modules that have requested interrupt service decode the priority value in AD-
DR[3:1]. If request priority is the same as acknowledged priority, arbitration by
IARB contention takes place.
E. After arbitration, the interrupt acknowledge cycle is completed in one of the following ways:
1. When there is no contention (IARB = %0000), the spurious interrupt monitor asserts BERR, and the CPU generates the spurious interrupt vector number.
2. The dominant interrupt source supplies a vector number and DSACK signals appropriate to the access. The CPU acquires the vector number.
3. The AVEC signal is asserted (the signal can be asserted by the dominant interrupt source or the pin can be tied low), and the CPU generates an autovector number corresponding to interrupt priority.
4. The bus monitor asserts BERR and the CPU32 generates the spurious interrupt vector number.
F. The vector number is converted to a vector address.
G. The content of the vector address is loaded into the PC, and the processor transfers control to the exception handler routine.
4.7.5 Interrupt Acknowledge Bus Cycles
Interrupt acknowledge bus cycles are CPU32 space cycles that are generated during exception processing. For further information about the types of interrupt acknowledge
bus cycles determined by AVEC or DSACK, refer to APPENDIX A ELECTRICAL
CHARACTERISTICS and the
SIM Reference Manual (SIMRM/AD).
4.8 Chip Selects
Typical microcontrollers require additional hardware to provide external select and address decode signals. The MCU includes 12 programmable chip-select circuits that can provide 2- to 20-clock-cycle access to external memory and peripherals. Address
block sizes of two Kbytes to one Mbyte can be selected. Figure 4-17 is a diagram of
a basic system that uses chip selects.
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FC
1
SIZ
CLKOUT
AS
DSACK
DS
CS3
CS5
IRQ
ADDR[23:0]
DATA[15:0]
ASYNC BUS
PERIPHERAL
SIZ
CLK
AS
DSACK
DS
CS
IACK
IRQ
ADDR[15:0]
2
DATA[15:0]
MCU
CSBOOT
R/W
MEMORY
ADDR[23:0]
2
DATA[15:8]
CS
R/W
MEMORY
ADDR[23:0]
2
DATA[7:0]
CS
R/W
1. Can be decoded to provide additional address space.
2. Varies depending upon peripheral memory size.
32 EXAMPLE SYS BLOCK
Figure 4-17 Basic MCU System
Chip-select assertion can be synchronized with bus control signals to provide output enable, read/write strobe, or interrupt acknowledge signals. Chip select logic can also generate DSACK and AVEC signals internally. Each signal can also be synchronized with the ECLK signal available on ADDR23.
When a memory access occurs, chip-select logic compares address space type, address, type of access, transfer size, and interrupt priority (in the case of interrupt acknowledge) to parameters stored in chip-select registers. If all parameters match, the appropriate chip-select signal is asserted. Select signals are active low. If a chip-select function is given the same address as a microcontroller module or an internal memory array, an access to that address goes to the module or array, and the chip-select signal is not asserted. The external address and data buses do not reflect the internal access.
All chip-select circuits are configured for operation out of reset. However, all chip-select signals except CSBOOT are disabled, and cannot be asserted until the BYTE field in the corresponding option register is programmed to a nonzero value, selecting a
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transfer size. The chip-select option must not be written until a base address has been written to a proper base address register. CSBOOT is automatically asserted out of reset. Alternate functions for chip-select pins are enabled if appropriate data bus pins
are held low at the release of the reset signal (refer to 4.6.3.1 Data Bus Mode Selec-
tion for more information). Figure 4-18 is a functional diagram of a single chip-select
circuit.
INTERNAL
SIGNALS
ADDRESS
BUS CONTROL
BASE ADDRESS REGISTER
ADDRESS COMPARATOR
OPTION COMPARE
OPTION REGISTER
TIMING
AND
CONTROL
PIN
4
AVEC
DSACK
AVEC
GENERATOR
DSACK
GENERATOR
PIN
ASSIGNMENT
REGISTER
PIN
DATA
REGISTER
CHIP SEL BLOCK
Figure 4-18 Chip-Select Circuit Block Diagram
4.8.1 Chip-Select Registers
Each chip-select pin can have one or more functions. Ship-select pin assignment registers (CSPAR[0:1]) determine functions of the pins. Pin assignment registers also determine port size (8- or 16-bit) for dynamic bus allocation. A pin data register (PORTC) latches data for chip-select pins that are used for discrete output.
Blocks of addresses are assigned to each chip-select function. Block sizes of two
Kbytes to one Mbyte can be selected by writing values to the appropriate base address register (CSBAR[0:10], CSBARBT). Address blocks for separate chip-select functions can overlap.
Chip select option registers (CSOR[0:10], CSORBT) determine timing of and conditions for assertion of chip-select signals. Eight parameters, including operating mode, access size, synchronization, and wait state insertion can be specified.
Initialization software usually resides in a peripheral memory device controlled by the chip-select circuits. A set of special chip-select functions and registers (CSORBT, CS-
BARBT) is provided to support bootstrap operation.
Comprehensive address maps and register diagrams are provided in APPENDIX D
REGISTER SUMMARY.
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4.8.1.1 Chip-Select Pin Assignment Registers
The pin assignment registers contain twelve 2-bit fields (CS[10:0] and CSBOOT) that determine the functions of the chip-select pins. Each pin has two or three possible
functions, as shown in Table 4-19.
Table 4-19 Chip-Select Pin Functions
16-Bit
Chip Select
CSBOOT
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CS8
CS9
CS10
8-Bit
Chip Select
CSBOOT
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CS8
CS9
CS10
Alternate
Function
CSBOOT
BR
BG
BGACK
FC0
FC1
FC2
ADDR19
ADDR20
ADDR21
ADDR22
ADDR23
Discrete
Output
—
—
—
—
PC0
PC1
PC2
PC3
PC4
PC5
PC6
ECLK
Table 4-20 shows pin assignment field encoding. Pins that have no discrete output
function do not use the %00 encoding.
4
Table 4-20 Pin Assignment Field Encoding
Bit Field
00
01
10
11
Description
Discrete Output
Alternate Function
Chip Select (8-Bit Port)
Chip Select (16-Bit Port)
Port size determines the way in which bus transfers to an external address are allocated. Port size of eight bits or sixteen bits can be selected when a pin is assigned as a chip select. Port size and transfer size affect how the chip-select signal is asserted.
Refer to 4.8.1.3 Chip-Select Option Registers for more information.
Out of reset, chip-select pin function is determined by the logic level on a corresponding data bus pin. These pins have weak internal pull-up drivers, but can be held low
by external devices. (Refer to 4.6.3.1 Data Bus Mode Selection for more informa-
tion.) Either 16-bit chip-select function (%11) or alternate function (%01) can be selected during reset. All pins except the boot ROM select pin (CSBOOT) are disabled out of reset. There are twelve chip-select functions and only eight associated data bus
pins. There is not a one-to-one correspondence. Refer to 4.8.4 Chip-Select Reset
Operation for more detailed information.
The CSBOOT signal is normally enabled out of reset. The state of the DATA0 line during reset determines what port width CSBOOT uses. If DATA0 is held high (either by the weak internal pull-up driver or by an external pull-up device), 16-bit width is selected. If DATA0 is held low, 8-bit port size is selected.
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A pin programmed as a discrete output drives an external signal to the value specified in the pin data register. No discrete output function is available on pins CSBOOT, BR,
BG, or BGACK. ADDR23 provides ECLK output rather than a discrete output signal.
When a pin is programmed for discrete output or alternate function, internal chip-select logic still functions and can be used to generate DSACK or AVEC internally on an address and control signal match.
4.8.1.2 Chip-Select Base Address Registers
Each chip select has an associated base address register. A base address is the lowest address in the block of addresses enabled by a chip select. Block size is the extent of the address block above the base address. Block size is determined by the value contained in a BLKSZ field. Block addresses for different chip selects can overlap.
The BLKSZ field determines which bits in the base address field are compared to corresponding bits on the address bus during an access. Provided other constraints determined by option register fields are also satisfied, when a match occurs, the
associated chip-select signal is asserted. Table 4-21 shows BLKSZ encoding.
4
Table 4-21 Block Size Encoding
BLKSZ[2:0]
000
001
010
011
100
101
110
111
Block Size
2 Kbyte
8 Kbyte
16 Kbyte
64 Kbyte
128 Kbyte
256 Kbyte
512 Kbyte
1 Mbyte
Address Lines Compared
ADDR[23:11]
ADDR[23:13]
ADDR[23:14]
ADDR[23:16]
ADDR[23:17]
ADDR[23:18]
ADDR[23:19]
ADDR[23:20]
The chip-select address compare logic uses only the most significant bits to match an address within a block. The value of the base address must be a multiple of block size.
Base address register diagrams show how base register bits correspond to address lines.
After reset, the MCU fetches the initialization routine from the address contained in the reset vector, located beginning at address $000000 of program space. To support bootstrap operation from reset, the base address field in chip-select base address register boot (CSBARBT) has a reset value of all zeros. A memory device containing the reset vector and initialization routine can be automatically enabled by CSBOOT after a reset. The block size field in CSBARBT has a reset value of 512 Kbytes. Refer to
4.8.4 Chip-Select Reset Operation for more information.
4.8.1.3 Chip-Select Option Registers
Option register fields determine timing of and conditions for assertion of chip-select signals. To assert a chip-select signal, and to provide DSACK or autovector support, other constraints set by fields in the option register and in the base address register
must also be satisfied. Table 4-22 is a summary of option register functions.
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Table 4-22 Option Register Function Summary
MODE BYTE R/W STRB DSACK SPACE
0 = ASYNC* 00 = Disable 00 = Rsvd 0 = AS 0000 = 0 WAIT 00 = CPU SP
1 = SYNC 01 = Lower
10 = Upper
01 = Read
10 = Write
1 = DS 0001 = 1 WAIT 01 = User SP
IPL
000 = All*
001 = Priority 1
0010 = 2 WAIT 10 = Supv SP 010 = Priority 2
AVEC
0 = Off*
1 = On
*11 = Both 11 = Both 0011 = 3 WAIT 11 = S/U SP* 011 = Priority 3
0100 = 4 WAIT 100 = Priority 4
0101 = 5 WAIT
0110 = 6 WAIT
101 = Priority 5
110 = Priority 6
111 = Priority 7 0111 = 7 WAIT
1000 = 8 WAIT
1001 = 9 WAIT
1010 = 10 WAIT
1011 = 11 WAIT
1100 = 12 WAIT
1101 = 13 WAIT
1110 = F term
1111 = External
*Use this value when function is not required for chip-select operation.
The MODE bit determines whether chip-select assertion simulates an asynchronous bus cycle, or is synchronized to the M6800-type bus clock signal (ECLK) available on
ADDR23 (refer to 4.3 System Clock for more information on ECLK).
The BYTE field controls bus allocation for chip-select transfers. Port size, set when a chip select is enabled by a pin assignment register, affects signal assertion. When an
8-bit port is assigned, any BYTE field value other than %00 enables the chip select signal. When a 16-bit port is assigned, however, BYTE field value determines when the chip select is enabled. The BYTE fields for CS[10:0] are cleared during reset. However, both bits in the boot ROM option register (CSORBT) BYTE field are set (%11) when the reset signal is released.
The R/W field causes a chip-select signal to be asserted only for a read, only for a write, or for both read and write. Use this field in conjunction with the STRB bit to generate asynchronous control signals for external devices.
The STRB bit controls the timing of a chip-select assertion in asynchronous mode. Selecting address strobe causes a chip-select signal to be asserted synchronized with the address strobe. Selecting data strobe causes a chip-select signal to be asserted synchronized with the data strobe. This bit has no effect in synchronous mode.
The DSACK field specifies the source of data strobe acknowledge signals used in asynchronous mode. It also allows the user to optimize bus speed in a particular application by controlling the number of wait states that are inserted.
The SPACE field determines the address space in which a chip select is asserted. An access must have the space type represented by SPACE encoding in order for a chipselect signal to be asserted.
The IPL field contains an interrupt priority mask that is used when chip-select logic is set to trigger on external interrupt acknowledge cycles. When the SPACE field is set
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to %00 (CPU space), interrupt priority (ADDR[3:1]) is compared to IPL value. If the values are the same, and other option register constraints are satisfied, a chip select signal is asserted. This field only affects the response of chip selects and does not affect interrupt recognition by the CPU. Encoding %000 causes a chip-select signal to be asserted regardless of interrupt acknowledge cycle priority, provided all other constraints are met.
The AVEC bit selects one of two methods of acquiring an interrupt vector during an external interrupt acknowledge cycle. The internal autovector signal is generated only in response to interrupt requests from the SIM IRQ pins.
4.8.1.4 PORTC Data Register
The PORTC data register latches data for PORTC pins programmed as discrete outputs. When a pin is assigned as a discrete output, the value in this register appears at the output. PC[6:0] correspond to CS[9:3]. Bit 7 is not used. Writing to this bit has no effect, and it always reads zero.
4.8.2 Chip-Select Operation
When the MCU makes an access, enabled chip-select circuits compare the following items:
1. Function codes to SPACE fields, and to the IPL field if the SPACE field encoding is not for CPU32 space.
2. Appropriate ADDR bits to base address fields.
3. Read/write status to R/W fields.
4. ADDR0 and/or SIZ bits to the BYTE field (16-bit ports only).
5. Priority of the interrupt being acknowledged (ADDR[3:1]) to IPL fields (when the access is an interrupt acknowledge cycle).
When a match occurs, the chip-select signal is asserted. Assertion occurs at the same time as AS or DS assertion in asynchronous mode. Assertion is synchronized with
ECLK in synchronous mode. In asynchronous mode, the value of the DSACK field determines whether DSACK is generated internally. DSACK also determines the number of wait states inserted before internal DSACK assertion.
The speed of an external device determines whether internal wait states are needed.
Normally, wait states are inserted into the bus cycle during S3 until a peripheral asserts DSACK. If a peripheral does not generate DSACK, internal DSACK generation must be selected and a predetermined number of wait states can be programmed into the chip-select option register.
Refer to the SIM Reference Manual (SIMRM/AD) for further information.
4.8.3 Using Chip-Select Signals for Interrupt Acknowledge
Ordinary I/O bus cycles use supervisor space access, but interrupt acknowledge bus
cycles use CPU space access. Refer to 4.5.4 CPU Space Cycles for more informa-
tion. There are no differences in flow for chip selects in each type of space, but base and option registers must be properly programmed for each type of external bus cycle.
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During a CPU space cycle, bits [15:3] of the appropriate base register must be configured to match ADDR[23:11], as the address is compared to an address generated by the CPU.
Figure 4-19 shows CPU space encoding for an interrupt acknowledge cycle. FC[2:0]
are set to %111, designating CPU space access. ADDR[3:1] indicate interrupt priority, and the space type field (ADDR[19:16]) is set to %1111, the interrupt acknowledge code. The rest of the address lines are set to one.
INTERRUPT
ACKNOWLEDGE
FUNCTION
CODE
2 0
1 1 1
ADDRESS BUS
23 19 16
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LEVEL
0
1
CPU SPACE
TYPE FIELD
CPU SPACE IACK TIM
Figure 4-19 CPU Space Encoding for Interrupt Acknowledge
Because address match logic functions only after the EBI transfers an interrupt acknowledge cycle to the external address bus following IARB contention, chip-select logic generates AVEC or DSACK signals only in response to interrupt requests from external IRQ pins. If an internal module makes an interrupt request of a certain priority, and the chip-select base address and option registers are programmed to generate
AVEC or DSACK signals in response to an interrupt acknowledge cycle for that priority level, chip-select logic does not respond to the interrupt acknowledge cycle, and the internal module supplies a vector number and generates an internal DSACK signal to terminate the cycle.
Perform the following operations before using a chip select to generate an interrupt acknowledge signal.
1. Program the base address field to all ones.
2. Program block size to no more than 64 Kbytes, so that the address comparator checks ADDR[19:16] against the corresponding bits in the base address register. (The CPU32 places the CPU32 space type on ADDR[19:16].)
3. Set the R/W field to read only. An interrupt acknowledge cycle is performed as a read cycle.
4. Set the BYTE field to lower byte when using a 16-bit port, as the external vector for a 16-bit port is fetched from the lower byte. Set the BYTE field to upper byte when using an 8-bit port.
If an interrupting device does not provide a vector number, an autovector acknowledge must be generated. Asserting AVEC, either by asserting the AVEC pin or by generating AVEC internally using the chip-select option register, terminates the bus cycle.
4.8.4 Chip-Select Reset Operation
The least significant bits of each of the 2-bit CS[10:0] pin assignment fields in CSPAR0 and CSPAR1 each have a reset value of one. The reset values of the most significant
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bits of each field are determined by the states of DATA[7:1] during reset. There are weak internal pull-up drivers for each of the data lines, so that chip-select operation will be selected by default out of reset. However, the internal pull-up drivers can be overcome by bus loading effects — to insure a particular configuration out of reset, use an active device to put the data lines in a known state during reset. The base address fields in chip-select base address registers CSBAR[0:10] and chip select option regis-
ters CSOR[0:10] have the reset values shown in Table 4-23. The BYTE fields of
CSOR[0:10] have a reset value of “disable”, so that a chip-select signal cannot be asserted until the base and option registers are initialized.
Table 4-23 Chip Select Base and Option Register Reset Values
Fields
Base Address
Block Size
Async/Sync Mode
Upper/Lower Byte
Read/Write
AS/DS
DSACK
Address Space
IPL
Autovector
Reset Values
$000000
2 Kbyte
Asynchronous Mode
Disabled
Reserved
AS
No Wait States
CPU Space
Any Level
External Interrupt Vector
Following reset, the MCU fetches initial stack pointer and program counter values from the exception vector table, beginning at $000000 in supervisor program space. The
CSBOOT chip-select signal is used to select an external boot ROM mapped to a base address of $000000. In order to do this, the reset values of the fields that control CS-
BOOT must be different from those of other chip select signals.
The MSB of the CSBOOT field in CSPAR0 has a reset value of one, so that chip-select function is selected by default out of reset. The BYTE field in option register CSORBT has a reset value of “both bytes” so that the select signal is enabled out of reset. The
LSB value of the CSBOOT field, determined by the logic level of DATA0 during reset, selects boot ROM port size. When DATA0 is held low during reset, port size is eight bits. When DATA0 is held high during reset, port size is 16 bits. DATA0 has a weak internal pull-up driver, so that a 16-bit port will be selected by default out of reset. However, the internal pull-up driver can be overcome by bus loading effects — to insure a particular configuration out of reset, use an active device to put DATA0 in a known state during reset.
The base address field in chip-select base address register boot (CSBARBT) has a reset value of all zeros, so that when the initial access to address $000000 is made, an address match occurs, and the CSBOOT signal is asserted. The block size field in
CSBARBT has a reset value of 1 Mbyte. Table 4-24 shows CSBOOT reset values.
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Table 4-24 CSBOOT Base and Option Register Reset Values
Fields
Base Address
Block Size
Async/Sync Mode
Upper/Lower Byte
Read/Write
AS/DS
DSACK
Address Space
IPL
Autovector
Reset Values
$000000
1 Mbyte
Asynchronous Mode
Both Bytes
Read/Write
AS
13 Wait States
Supervisor/User Space
Any Level
Interrupt Vector Externally
4.9 Parallel Input/Output Ports
Fifteen SIM pins can be configured for general-purpose discrete input and output. Although these pins are organized into two ports, port E and port F, function assignment is by individual pin. Pin assignment registers, data direction registers, and data registers are used to implement discrete I/O.
4.9.1 Pin Assignment Registers
Bits in the port E and port F pin assignment registers (PEPAR and PFPAR) control the functions of the pins in each port. Any bit set to one defines the corresponding pin as a bus control signal. Any bit cleared to zero defines the corresponding pin as an I/O pin.
4.9.2 Data Direction Registers
Bits in the port E and port F data direction registers (DDRE and DDRF) control the direction of the pin drivers when the pins are configured as I/O. Any bit in a register set to one configures the corresponding pin as an output. Any bit in a register cleared to zero configures the corresponding pin as an input. These registers can be read or written at any time. Writes have no effect.
4.9.3 Data Registers
A write to the port E and port F data registers (PORTE and PORTF) is stored in an internal data latch, and if any pin in the corresponding port is configured as an output, the value stored for that bit is driven out on the pin. A read of a data register returns the value at the pin only if the pin is configured as a discrete input. Otherwise, the value read is the value stored in the register. Both data registers can be accessed in two locations. Registers can be read or written at any time.
4.10 Factory Test
The test submodule supports scan-based testing of the various MCU modules. It is integrated into the SIM to support production test. Test submodule registers are intended for
Freescale
use only. Register names and addresses are provided in APPENDIX
D REGISTER SUMMARY to show the user that these addresses are occupied. The
QUOT pin is also used for factory test.
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SECTION 5 CENTRAL PROCESSING UNIT
The CPU32, the instruction processing module of the M68300 family, is based on the industry-standard MC68000 processor. It has many features of the MC68010 and
MC68020, as well as unique features suited for high-performance controller applications. This section is an overview of the CPU32. For detailed information concerning
CPU operation, refer to the
CPU32 Reference Manual (CPU32RM/AD).
5.1 General
Ease of programming is an important consideration in using a microcontroller. The
CPU32 instruction format reflects a philosophy emphasizing register-memory interaction. There are eight multifunction data registers and seven general-purpose addressing registers.
All data resources are available to all operations requiring those resources. The data registers readily support 8-bit (byte), 16-bit (word), and 32-bit (long-word) operand lengths for all operations. Word and long-word operations support address manipulation. Although the program counter (PC) and stack pointers (SP) are special-purpose registers, they are also available for most data addressing activities. Ease of program checking and diagnosis is further enhanced by trace and trap capabilities at the instruction level.
A block diagram of the CPU32 is shown in Figure 5-1. The major blocks operate in a
highly independent fashion that maximizes concurrence of operation while managing the essential synchronization of instruction execution and bus operation. The bus controller loads instructions from the data bus into the decode unit. The sequencer and control unit provide overall chip control, managing the internal buses, registers, and functions of the execution unit.
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STAGE
C
DECODE
STAGE
B
INSTRUCTION PIPELINE
BUFFER
STAGE
A
CONTROL STORE
CONTROL LOGIC
MICROSEQUENCER AND CONTROL
PROGRAM
COUNTER
SECTION
EXECUTION UNIT
DATA
SECTION
5
WRITE PENDING
BUFFER
MICROBUS
CONTROLLER
PREFETCH
CONTROLLER
ADDRESS
BUS
BUS CONTROL
SIGNALS
DATA
BUS
1127A
Figure 5-1 CPU32 Block Diagram
5.2 CPU32 Registers
The CPU32 programming model consists of two groups of registers that correspond to the user and supervisor privilege levels. User programs can use only the registers of the user model. The supervisor programming model, which supplements the user programming model, is used by CPU32 system programmers who wish to protect sensitive operating system functions. The supervisor model is identical to that of the
MC68010 and later processors.
The CPU32 has eight 32-bit data registers, seven 32-bit address registers, a 32-bit program counter, separate 32-bit supervisor and user stack pointers, a 16-bit status register, two alternate function code registers, and a 32-bit vector base register (see
Figure 5-2 and Figure 5-3).
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31
31
31
31
31
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16 15
16 15
16 15
8 7
7
0
D0
D1
D2
D3
D4
D5
D6
D7
DATA REGISTERS
0
ADDRESS REGISTERS
0
0
A7 (USP) USER STACK POINTER
PC PROGRAM COUNTER
0
A0
A1
A2
A3
A4
A5
A6
CCR CONDITION CODE REGISTER
Figure 5-2 User Programming Model
16 15
15 8 7
(CCR)
0
0
A7’ (SSP) SUPERVISOR STACK POINTER
SR STATUS REGISTER
0
VBR VECTOR BASE REGISTER
2 0
SFC
DFC
ALTERNATE FUNCTION
CODE REGISTERS
Figure 5-3 Supervisor Programming Model Supplement
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5.2.1 Data Registers
The eight data registers can store data operands of 1,8, 16, 32, and 64 bits and addresses of 16 or 32 bits. The following data types are supported:
• Bits
• Packed Binary-Coded Decimal Digits
• Byte Integers (8 bits)
• Word Integers (16 bits)
• Long-Word Integers (32 bits)
• Quad-Word Integers (64 bits)
Each of data registers D7–D0 is 32 bits wide. Byte operands occupy the low-order 8 bits; word operands, the low-order 16 bits; and long-word operands, the entire 32 bits.
When a data register is used as either a source or destination operand, only the appropriate low-order byte or word (in byte or word operations, respectively) is used or changed; the remaining high-order portion is unaffected. The least significant bit (LSB) of a long-word integer is addressed as bit zero, and the most significant bit (MSB) is
addressed as bit 31. Figure 5-4 shows the organization of various types of data in the
data registers.
Quad-word data consists of two long words and represents the product of 32-bit multiply or the dividend of 32-bit divide operations (signed and unsigned). Quad-words may be organized in any two data registers without restrictions on order or pairing.
There are no explicit instructions for the management of this data type, although the
MOVEM instruction can be used to move a quad-word into or out of the registers.
Binary-coded decimal (BCD) data represents decimal numbers in binary form. CPU32
BCD instructions use a format in which a byte contains two digits. The four LSB contain the least significant digit, and the four MSB contain the most significant digit. The
ABCD, SBCD, and NBCD instructions operate on two BCD digits packed into a single byte.
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31
MSB
30 1
LSB
0
BYTE
31
HIGH-ORDER BYTE
24 23
MIDDLE HIGH BYTE
16 15
MIDDLE LOW BYTE
8 7
LOW-ORDER BYTE
0
16-BIT WORD
31
HIGH-ORDER WORD
LONG WORD
31
16 15
LOW-ORDER WORD
0
0
LONG WORD
QUAD-WORD
63
MSB
31
62
ANY Dx
1
32
0
ANY Dy LSB
Figure 5-4 Data Organization in Data Registers
5.2.2 Address Registers
Each address register and stack pointer is 32 bits wide and holds a 32-bit address. Address registers cannot be used for byte-sized operands. Therefore, when an address register is used as a source operand, either the low-order word or the entire long-word operand is used, depending upon the operation size. When an address register is used as the destination operand, the entire register is affected, regardless of the operation size. If the source operand is a word size, it is sign-extended to 32 bits. Address registers are used primarily for addresses and to support address computation.
The instruction set includes instructions that add to, subtract from, compare, and move
the contents of address registers. Figure 5-5 shows the organization of addresses in
address registers.
31 16 15 0
SIGN EXTENDED 16-BIT ADDRESS OPERAND
31 0
FULL 32-BIT ADDRESS OPERAND
Figure 5-5 Address Organization in Address Registers
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5.2.3 Program Counter
The PC contains the address of the next instruction to be executed by the CPU32. During instruction execution and exception processing, the processor automatically increments the contents of the PC or places a new value in the PC as appropriate.
5.2.4 Control Registers
The control registers described in this section contain control information for supervisor functions and vary in size. With the exception of the condition code register (the user portion of the status register), they are accessed only by instructions at the supervisor privilege level.
5.2.4.1 Status Register
The status register (SR) stores the processor status. It contains the condition codes that reflect the results of a previous operation and can be used for conditional instruction execution in a program. The condition codes are extend (X), negative (N), zero
(Z), overflow (V), and carry (C). The user (low-order) byte containing the condition codes is the only portion of the SR information available at the user privilege level; it is referenced as the condition code register (CCR) in user programs.
At the supervisor privilege level, software can access the full status register. The upper byte of this register includes the interrupt priority (IP) mask (three bits), two bits for placing the processor in one of two tracing modes or disabling tracing, and the supervisor/user bit for placing the processor at the desired privilege level.
Undefined bits in the status register are reserved by
Freescale
for future definition. The undefined bits are read as zeros and should be written as zeros for future compatibility.
All operations to the SR and CCR are word-size operations, but for all CCR operations, the upper byte is read as all zeros and is ignored when written, regardless of privilege level.
Refer to APPENDIX D REGISTER SUMMARY for bit/field definitions and a diagram
of the status register.
5.2.4.2 Alternate Function Code Registers
Alternate function code registers (SFC and DFC) contain 3-bit function codes. Function codes can be considered extensions of the 24-bit linear address that optionally provide as many as eight 16-Mbyte address spaces. The processor automatically generates function codes to select address spaces for data and programs at the user and supervisor privilege levels and to select a CPU address space used for processor functions (such as breakpoint and interrupt acknowledge cycles).
Registers SFC and DFC are used by the MOVES instruction to specify explicitly the function codes of the memory address. The MOVEC instruction is used to transfer values to and from the alternate function code registers. This is a long-word transfer; the upper 29 bits are read as zeros and are ignored when written.
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5.2.5 Vector Base Register (VBR)
The VBR contains the base address of the 1024-byte exception vector table, consisting of 256 exception vectors. Exception vectors contain the memory addresses of rou-
tines that begin execution at the completion of exception processing. Refer to 5.9
Exception Processing for more information on the VBR and exception processing.
5.3 Memory Organization
Memory is organized on a byte-addressable basis in which lower addresses correspond to higher order bytes. For example, the address N of a long-word data item corresponds to the address of the most significant byte of the highest order word. The address of the most significant byte of the low-order word is N + 2, and the address of the least significant byte of the long word is N + 3. The CPU32 requires long-word and
word data and instructions to be aligned on word boundaries (refer to Figure 5-6).
Data misalignment is not supported.
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5-8
15
MSB
15
MSB
15
MSB
15
MSB
ADDRESS 0
ADDRESS 1
ADDRESS 2
MSB = Most Significant Bit
LSB = Least Significant Bit
15
BCD 0
BCD 4
MSD = Most Significant Digit
LSD = Least Significant Digit
12 11
MSD
LONG WORD 0
LONG WORD 1
LONG WORD 2
BYTE 0
BYTE 2
7 6 5
BIT DATA
1 BYTE = 8 BITS
4 3 2 1 0
INTEGER DATA
1 BYTE = 8 BITS
8 7
LSB BYTE 1
BYTE 3
WORD = 16 BITS
WORD 0
WORD 1
WORD 2
LONG WORD = 32 BITS
HIGH ORDER
LOW ORDER
ADDRESS 1
ADDRESS = 32 BITS
HIGH ORDER
LOW ORDER
BCD 1
BCD 5
DECIMAL DATA
BCD DIGITS = 1 BYTE
8 7
LSD BCD 2
BCD 6
4 3
BCD 3
BCD 7
0
LSB
0
LSB
0
LSB
0
0
1125A
Figure 5-6 Memory Operand Addressing
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5.4 Virtual Memory
The full addressing range of the CPU32 on the MC68331 is 16 Mbytes in each of eight address spaces. Even though most systems implement a smaller physical memory, the system can be made to appear to have a full 16 Mbytes of memory available to each user program by using virtual memory techniques.
A system that supports virtual memory has a limited amount of high-speed physical memory that can be accessed directly by the processor and maintains an image of a much larger virtual memory on a secondary storage device. When the processor attempts to access a location in the virtual memory map that is not resident in physical memory, a page fault occurs. The access to that location is temporarily suspended while the necessary data is fetched from secondary storage and placed in physical memory. The suspended access is then restarted or continued.
The CPU32 uses instruction restart, which requires that only a small portion of the internal machine state be saved. After correcting the fault, the machine state is restored, and the instruction is fetched and started again. This process is completely transparent to the application program.
5.5 Addressing Modes
Addressing in the CPU32 is register-oriented. Most instructions allow the results of the specified operation to be placed either in a register or directly in memory. There is no need for extra instructions to store register contents in memory.
There are seven basic addressing modes:
• Register Direct
• Register Indirect
• Register Indirect with Index
• Program Counter Indirect with Displacement
• Program Counter Indirect with Index
• Absolute
• Immediate
The register indirect addressing modes include postincrement, predecrement, and offset capability. The program counter indirect mode also has index and offset capabilities. In addition to these addressing modes, many instructions implicitly specify the use of the status register, stack pointer, and/or program counter.
5.6 Processing States
The processor is always in one of four processing states: normal, exception, halted, or background. The normal processing state is associated with instruction execution; the bus is used to fetch instructions and operands and to store results.
The exception processing state is associated with interrupts, trap instructions, tracing, and other exception conditions. The exception may be internally generated explicitly by an instruction or by an unusual condition arising during the execution of an instruction. Exception processing can be forced externally by an interrupt, a bus error, or a reset.
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The halted processing state is an indication of catastrophic hardware failure. For example, if during the exception processing of a bus error another bus error occurs, the processor assumes that the system is unusable and halts.
The background processing state is initiated by breakpoints, execution of special instructions, or a double bus fault. Background processing is enabled by pulling BKPT low during RESET. Background processing allows interactive debugging of the system via a simple serial interface.
5.7 Privilege Levels
The processor operates at one of two levels of privilege: user or supervisor. Not all instructions are permitted to execute at the user level, but all instructions are available at the supervisor level. Effective use of privilege level can protect system resources from uncontrolled access. The state of the S bit in the status register determines the privilege level and whether the user stack pointer (USP) or supervisor stack pointer
(SSP) is used for stack operations.
5.8 Instructions
The CPU32 instruction set is summarized in Table 5-1. The instruction set of the
CPU32 is very similar to that of the MC68020. Two new instructions have been added to facilitate controller applications: low-power stop (LPSTOP) and table lookup and interpolate (TBLS, TBLSN, TBLU, TBLUN).
The following MC68020 instructions are not implemented on the CPU32:
BFxxx — Bit Field Instructions (BFCHG, BFCLR, BFEXTS, BFEXTU,
BFFFO, BFINS, BFSET, BFTST)
CALLM, RTM — Call Module, Return Module
CAS, CAS2 — Compare and Swap (Read-Modify-Write Instructions) cpxxx — Coprocessor Instructions (cpBcc, cpDBcc, cpGEN, cpRESTORE, cpSAVE, cpScc, cpTRAPcc)
PACK, UNPK — Pack, Unpack BCD Instructions
Memory — Memory Indirect Addressing Modes
The CPU32 traps on unimplemented instructions or illegal effective addressing modes, allowing user-supplied code to emulate unimplemented capabilities or to define special purpose functions. However,
Freescale
reserves the right to use all currently unimplemented instruction operation codes for future M68000 core enhancements.
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BRA
BSET
BSR
BTST
CHK
CHK2
CLR
CMP
CMPA
CMPI
CMPM
CMP2
DBcc
DIVS/DIVU
Instruction
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ANDI to CCR
ANDI to SR
1
ASL
ASR
Bcc
BCHG
BCLR
BGND
BKPT #<data>
Table 5-1 Instruction Set Summary
Syntax
Dn, Dn–
(An), – (An)
Dn, <ea>
<ea>, Dn
<ea>, An
#<data>, <ea>
#<data>, <ea>
Dn, Dn–
(An), – (An)
<ea>, Dn
Dn, <ea>
#<data>, <ea>
#<data>, CCR
#<data>, SR
Dn, Dn
#<data>, Dn
<ea>
Dn, Dn
#<data>, Dn
<ea>
<label>
Dn, <ea>
#<data>, <ea>
Dn, <ea>
#<data>, <ea> none
<label>
Dn, <ea>
#<data>, <ea>
<label>
Dn, <ea>
#<data>, <ea>
<ea>, Dn
<ea>, Rn
Operand Size
8
8
8, 16, 32
8, 16, 32
16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8
16
8, 16, 32
8, 16, 32
16
8, 16, 32
8, 16, 32
16
8, 16, 32
8, 32
8, 32
8, 32
8, 32 none none
8, 16, 32
8, 32
8, 32
8, 16, 32
8, 32
8, 32
16, 32
8, 16, 32
Operation
Source
10
+ Destination
10
+ X
⇒
Destination
Source + Destination
⇒
Destination
Source + Destination
⇒
Destination
Immediate data + Destination
⇒
Destination
Immediate data + Destination
⇒
Destination
Source + Destination + X
⇒
Destination
Source · Destination
⇒
Destination
Data · Destination
⇒
Destination
Source · CCR
⇒
CCR
Source · SR
⇒
SR
If condition true, then PC + d
⇒
PC
(<bit number> of destination
⇒
Z
⇒ bit of destination
(<bit number> of destination
⇒
Z;
0
⇒
bit of destination
If background mode enabled, then enter background mode, else format/vector offset
⇒
– (SSP);
PC
⇒
– (SSP); SR
⇒
– (SSP); (vector)
⇒
PC
If breakpoint cycle acknowledged, then execute returned operation word, else trap as illegal instruction.
PC + d
⇒
PC
(<bit number> of destination
⇒
Z;
1
⇒
bit of destination
SP – 4
⇒
SP; PC
⇒
(SP); PC + d
⇒
PC
(<bit number> of destination
⇒
Z
<ea>
<ea>, Dn
<ea>, An
#<data>, <ea>
(An) +, (An) +
<ea>, Rn
Dn, <label>
<ea>, Dn
8, 16, 32
8, 16, 32
16, 32
8, 16, 32
8, 16, 32
8, 16, 32
16
32/16
⇒
16: 16
If Dn < 0 or Dn < (ea), then CHK exception
If Rn < lower bound or Rn > upper bound, then
CHK exception
0
⇒
Destination
(Destination – Source), CCR shows results
(Destination – Source), CCR shows results
(Destination – Data), CCR shows results
(Destination – Source), CCR shows results
Lower bound Rn Upper bound, CCR shows result
If condition false, then Dn – 1
⇒
PC; if Dn
≠
(– 1), then PC + d
⇒
PC
Destination / Source
⇒
Destination
(signed or unsigned)
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Instruction
DIVSL/DIVUL
EOR
EORI
EORI to CCR
EORI to SR
1
EXG
EXT
EXTB
ILLEGAL
JMP
JSR
LEA
LINK
LPSTOP 1
LSL
LSR
MOVE
MOVEA
MOVEA 1
MOVE from CCR
MOVE to CCR
MOVE from SR
1
MOVE to SR
1
MOVE USP
1
MOVEC
1
MOVEM
MOVEP
MOVEQ
MOVES
1
MULS/MULU
NBCD
⟨ ea
⟩
⟨ ea
⟩
⟨ ea
⟩
, An
An, #
⟨ d
⟩
#
⟨ data
⟩
Dn, Dn
#
⟨ data
⟩,
Dn
⟨ ea
⟩
Dn, Dn
#
⟨ data
⟩,
Dn
⟨ ea
⟩
⟨ ea
⟩
,
⟨ ea
⟩
⟨ ea
⟩
, An
USP, An
An, USP
CCR,
⟨ ea
⟩
⟨ ea
⟩
, CCR
SR,
⟨ ea
⟩
<ea>, SR
USP, An
An, USP
Rc, Rn
Rn, Rc list, <ea>
<ea>, list
Dn, (d
16
, An)
(d
16
, An), Dn
Table 5-1 Instruction Set Summary (Continued)
Syntax
⟨ ea
⟩
, Dr : Dq
⟨ ea
⟩
, Dq
⟨ ea
⟩
, Dr : Dq
Dn,
⟨ ea
⟩
#
⟨ data
⟩, ⟨ ea
⟩
#
⟨ data
⟩
, CCR
#
⟨ data
⟩
, SR
Rn, Rn
Dn
Dn
Dn none
Operand Size
64/32
⇒
32 : 32
32/32
⇒
32
32/32
⇒
32 : 32
8, 16, 32
8, 16, 32
8
16
32
8
⇒
16
16
⇒
32
8
⇒
32 none
Operation
Destination / Source
⇒
Destination
(signed or unsigned)
Source
⊕
Destination
⇒
Destination
Data
⊕
Destination
⇒
Destination
Source
⊕
CCR
⇒
CCR
Source
⊕
SR
⇒
SR
Rn
⇒
Rn
Sign extended Destination
⇒
Destination
Sign extended Destination
⇒
Destination
SSP – 2
⇒
SSP; vector offset
⇒
(SSP);
SSP – 4
⇒
SSP; PC
⇒
(SSP);
SSP – 2
⇒
SSP; SR
⇒
(SSP); illegal instruction vector address
⇒
PC
Destination
⇒
PC
SP – 4
⇒
SP; PC
⇒
(SP); destination
⇒
PC
⟨ ea
⟩ ⇒
An
SP – 4
⇒
SP, An
⇒
(SP); SP
⇒
An, SP + d
⇒
SP
Data
⇒
SR; interrupt mask
⇒
EBI; STOP
#<data>, Dn
Rn, <ea>
<ea>, Rn
<ea>, Dn
<ea>, Dl
<ea>, Dh : Dl
<ea> none none
32
16, 32 none
8, 16, 32
8, 16, 32
16
8, 16, 32
8, 16, 32
16
8, 16, 32
16, 32
⇒
32
32
32
16
16
16
16
32
32
32
32
16, 32
16, 32
⇒
32
16, 32
8
⇒
32
8, 16, 32
16 * 16
⇒
32
32 * 32
⇒
32
32 * 32
⇒
64
8
8
Source
⇒
Destination
Source
⇒
Destination
USP
⇒
An
An
⇒
USP
CCR
⇒
Destination
Source
⇒
CCR
SR
⇒
Destination
Source
⇒
SR
USP
⇒
AnAn
⇒
USP
Rc
⇒
RnRn
⇒
Rc
Listed registers
⇒
Destination
Source
⇒
Listed registers
Dn [31 : 24]
⇒
(An + d); Dn [23 : 16]
⇒
(An + d + 2);
Dn [15 : 8]
⇒
(An + d + 4); Dn [7 : 0]
⇒
(An + d + 6)
(An + d)
⇒
Dn [31 : 24]; (An + d + 2)
⇒
Dn [23 : 16];
(An + d + 4)
⇒
Dn [15 : 8]; (An + d + 6)
⇒
Dn [7 : 0]
Immediate data
⇒
Destination
Rn
⇒
Destination using DFC
Source using SFC
⇒
Rn
Source * Destination
⇒
Destination
(signed or unsigned)
0 – Destination
10
– X
⇒
Destination
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Instruction
NEG
NEGX
NOP
NOT
OR
ORI
ORI to CCR
ORI to SR
1
PEA
RESET
1
ROL
ROR
ROXL
ROXR
RTD
RTE
1
RTR
RTS
SBCD
Scc
STOP
1
SUB
SUBA
SUBI
SUBQ
SUBX
SWAP
TBLS/TBLU
TBLSN/TBLUN
TRAP
Table 5-1 Instruction Set Summary (Continued)
Syntax
<ea>
<ea> none
<ea>
<ea>, Dn
Dn, <ea>
#<data>, <ea>
#<data>, CCR
#<data>, SR
<ea> none
Dn, Dn
#<data>, Dn
<ea>
Dn, Dn
#<data>, Dn
<ea>
Dn, Dn
#<data>,
Dn<ea>
Dn, Dn
#<data>, Dn
<ea>
#<d> none none none
Dn, Dn
– (An), – (An)
<ea>
Operand Size
8, 16, 32
8, 16, 32 none
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
16
16
32 none
8, 16, 32
8, 16, 32
16
8, 16, 32
8, 16, 32
16
8, 16, 32
8, 16, 32
16
8, 16, 32
8, 16, 32
16
16 none none none
88
8
16
8, 16, 32
Operation
0 – Destination
⇒
Destination
0 – Destination – X
⇒
Destination
PC + 2
⇒
PC
Destination
⇒
Destination
Source; Destination
⇒
Destination
Data; Destination
⇒
Destination
Source; CCR
⇒
SR
Source; SR
⇒
SR
SP – 4
⇒
SP; <ea>
⇒
SP
Assert RESET line
(SP)
⇒
PC; SP + 4 + d
⇒
SP
(SP)
⇒
SR; SP + 2
⇒
SP; (SP)
⇒
PC;
SP + 4
⇒
SP; restore stack according to format
(SP)
⇒
CCR; SP + 2
⇒
SP; (SP)
⇒
PC;
SP + 4
⇒
SP
(SP)
⇒
PC; SP + 4
⇒
SP
Destination
10
– Source
10
– X
⇒
Destination
If condition true, then destination bits are set to 1; else, destination bits are cleared to 0
Data
⇒
SR; STOP
Destination – Source
⇒
Destination
#<data>
<ea>, Dn
Dn, <ea>
<ea>, An
#<data>, <ea>
#<data>, <ea>
Dn, Dn
– (An), – (An)
Dn
<ea>, Dn
Dym : Dyn, Dn
<ea>, Dn
Dym : Dyn, Dn
#<data>
16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
16
8, 16, 32
8, 16, 32 none
Destination – Source
⇒
Destination
Destination – Data
⇒
Destination
Destination – Data
⇒
Destination
Destination – Source – X
⇒
Destination
Dyn – Dym
⇒
Temp
(Temp * Dn [7 : 0])
⇒
Temp
(Dym * 256) + Temp
⇒
Dn
Dyn – Dym
⇒
Temp
(Temp * Dn [7 : 0]) / 256
⇒
Temp
Dym + Temp
⇒
Dn
SSP – 2
⇒
SSP; format/vector offset
⇒
(SSP);
SSP – 4
⇒
SSP; PC
⇒
(SSP); SR
⇒
(SSP); vector address
⇒
PC
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Table 5-1 Instruction Set Summary (Continued)
Instruction
TRAPcc
TRAPV
TST
UNLK
NOTE:
1. Privileged instruction
Syntax
none
#<data> none
<ea>
An
Operand Size
none
16, 32 none
8, 16, 32
32
Operation
If cc true, then TRAP exception
If V set, then overflow TRAP exception
Source – 0, to set condition codes
An
⇒
SP; (SP)
⇒
An, SP + 4
⇒
SP
5.8.1 M68000 Family Compatibility
It is the philosophy of the M68000 family that all user-mode programs can execute unchanged on a more advanced processor, and supervisor-mode programs and exception handlers should require only minimal alteration.
The CPU32 can be thought of as an intermediate member of the M68000 Family. Object code from an MC68000 or MC68010 may be executed on the CPU32, and many of the instruction and addressing mode extensions of the MC68020 are also supported. Refer to the CPU32 reference manual for a detailed comparison of the CPU32 and
MC68020 instruction set.
5.8.2 Special Control Instructions
Low power stop (LPSTOP) and table lookup and interpolate (TBL) instructions have been added to the MC68000 instruction set for use in controller applications.
5.8.2.1 Low Power Stop (LPSTOP)
In applications where power consumption is a consideration, the CPU32 forces the device into a low power standby mode when immediate processing is not required. The low power stop mode is entered by executing the LPSTOP instruction. The processor remains in this mode until a user-specified (or higher) interrupt level or reset occurs.
5.8.2.2 Table Lookup and Interpolate (TBL)
To maximize throughput for real-time applications, reference data is often precalculated and stored in memory for quick access. Storage of many data points can require an inordinate amount of memory. The table instruction requires that only a sample of data points be stored, reducing memory requirements. The TBL instruction recovers intermediate values using linear interpolation. Results can be rounded with a roundto-nearest algorithm.
5.9 Exception Processing
Exception processing is a special condition that preempts normal processing. Exception processing is the transition from normal mode program execution to execution of a routine that deals with an exception.
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5.9.1 Exception Vectors
An exception vector is the address of a routine that handles an exception. The vector base register (VBR) contains the base address of a 1024-byte exception vector table, which consists of 256 exception vectors. Sixty-four vectors are defined by the processor, and 192 vectors are reserved for user definition as interrupt vectors. Except for the reset vector, each vector in the table is one long word in length. The reset vector
is two long words in length. Refer to Table 5-2 for information on vector assignment.
CAUTION
Because there is no protection on the 64 processor-defined vectors, external devices can access vectors reserved for internal purposes.
This practice is strongly discouraged.
All exception vectors, except the reset vector, are located in supervisor data space.
The reset vector is located in supervisor program space. Only the initial reset vector is fixed in the processor memory map. When initialization is complete, there are no fixed assignments. Since the VBR stores the vector table base address, the table can be located anywhere in memory. It can also be dynamically relocated for each task executed by an operating system.
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Table 5-2 Exception Vector Assignments
10
11
12
13
8
9
6
7
Vector
Number
0
1
4
5
2
3
14
15
16–23
27
28
29
30
24
25
26
31
32–47
48–58
59–63
64–255
116
120
124
128
188
192
232
236
252
256
1020
56
60
64
92
96
100
104
108
112
40
44
48
52
24
28
32
36
8
12
16
20
Dec
Vector Offset
Hex Space
0
4
000
004
SP
SP
008
00C
010
014
SD
SD
SD
SD
018
01C
020
024
028
02C
030
034
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
074
078
07C
080
0BC
0C0
0E8
0EC
0FC
100
3FC
038
03C
040
05C
060
064
068
06C
070
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
Assignment
Reset: Initial Stack Pointer
Reset: Initial Program Counter
Bus Error
Address Error
Illegal Instruction
Zero Division
CHK, CHK2 Instructions
TRAPcc, TRAPV Instructions
Privilege Violation
Trace
Line 1010 Emulator
Line 1111 Emulator
Hardware Breakpoint
(Reserved, Coprocessor Protocol Violation)
Format Error and Uninitialized Interrupt
Format Error and Uninitialized Interrupt
(Unassigned, Reserved)
Spurious Interrupt
Level 1 Interrupt Autovector
Level 2 Interrupt Autovector
Level 3 Interrupt Autovector
Level 4 Interrupt Autovector
Level 5 Interrupt Autovector
Level 6 Interrupt Autovector
Level 7 Interrupt Autovector
Trap Instruction Vectors (0–15)
(Reserved, Coprocessor)
(Unassigned, Reserved)
User Defined Vectors (192)
Each vector is assigned an 8-bit number. Vector numbers for some exceptions are obtained from an external device; others are supplied by the processor. The processor multiplies the vector number by four to calculate vector offset, then adds the offset to the contents of the VBR. The sum is the memory address of the vector.
5.9.2 Types of Exceptions
An exception can be caused by internal or external events.
An internal exception can be generated by an instruction or by an error. The TRAP,
TRAPcc, TRAPV, BKPT, CHK, CHK2, RTE, and DIV instructions can cause exceptions during normal execution. Illegal instructions, instruction fetches from odd addresses, word or long-word operand accesses from odd addresses, and privilege violations also cause internal exceptions.
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Sources of external exception include interrupts, breakpoints, bus errors, and reset requests. Interrupts are peripheral device requests for processor action. Breakpoints are used to support development equipment. Bus error and reset are used for access control and processor restart.
5.9.3 Exception Processing Sequence
For all exceptions other than a reset exception, exception processing occurs in the fol-
lowing sequence. Refer to 4.6 Reset for details of reset processing.
As exception processing begins, the processor makes an internal copy of the status register. After the copy is made, the processor state bits in the status register are changed — the S bit is set, establishing supervisor access level, and bits T1 and T0 are cleared, disabling tracing. For reset and interrupt exceptions, the interrupt priority mask is also updated.
Next, the exception number is obtained. For interrupts, the number is fetched from
CPU space $F (the bus cycle is an interrupt acknowledge). For all other exceptions, internal logic provides a vector number.
Next, current processor status is saved. An exception stack frame is created and placed on the supervisor stack. All stack frames contain copies of the status register and the program counter for use by RTE. The type of exception and the context in which the exception occurs determine what other information is stored in the stack frame.
Finally, the processor prepares to resume normal execution of instructions. The exception vector offset is determined by multiplying the vector number by four, and the offset is added to the contents of the VBR to determine displacement into the exception vector table. The exception vector is loaded into the program counter. If no other exception is pending, the processor will resume normal execution at the new address in the PC.
5.10 Development Support
The following features have been implemented on the CPU32 to enhance the instrumentation and development environment:
• M68000 Family Development Support
• Background Debugging Mode
• Deterministic Opcode Tracking
• Hardware Breakpoints
5.10.1 M68000 Family Development Support
All M68000 Family members include features to facilitate applications development.
These features include the following:
Trace on Instruction Execution — M68000 Family processors include an instructionby-instruction tracing facility as an aid to program development. The MC68020,
MC68030, MC68040, and CPU32 also allow tracing only of those instructions
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causing a change in program flow. In the trace mode, a trace exception is generated after an instruction is executed, allowing a debugger program to monitor the execution of a program under test.
Breakpoint Instruction — An emulator may insert software breakpoints into the target code to indicate when a breakpoint has occurred. On the MC68010, MC68020,
MC68030, and CPU32, this function is provided via illegal instructions, $4848–
$484F, to serve as breakpoint instructions.
Unimplemented Instruction Emulation — During instruction execution, when an attempt is made to execute an illegal instruction, an illegal instruction exception occurs. Unimplemented instructions (F-line, A-line,...) utilize separate exception vectors to permit efficient emulation of unimplemented instructions in software.
5.10.2 Background Debugging Mode
Microcomputer systems generally provide a debugger, implemented in software, for system analysis at the lowest level. The background debugging mode (BDM) on the
CPU32 is unique in that the debugger has been implemented in CPU microcode.
BDM incorporates a full set of debugging options: registers can be viewed or altered, memory can be read or written to, and test features can be invoked.
A resident debugger simplifies implementation of an in-circuit emulator. In a common
setup (see Figure 5-7), emulator hardware replaces the target system processor. A
complex, expensive pod-and-cable interface provides a communication path between the target system and the emulator.
By contrast, an integrated debugger supports use of a bus state analyzer (BSA) for in-
circuit emulation. The processor remains in the target system (see Figure 5-8) and the
interface is simplified. The BSA monitors target processor operation and the on-chip debugger controls the operating environment. Emulation is much “closer” to target hardware, and many interfacing problems (e.g., limitations on high-frequency operation, AC and DC parametric mismatches, and restrictions on cable length) are minimized.
TARGET
SYSTEM
IN-CIRCUIT
EMULATOR
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TARGET
MCU
1128A
Figure 5-7 Common In-Circuit Emulator Diagram
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TARGET
SYSTEM
BUS STATE
ANALYZER
TARGET
MCU
1129A
Figure 5-8 Bus State Analyzer Configuration
5.10.2.1 Enabling BDM
Accidentally entering BDM in a non-development environment can lock up the CPU32 when the serial command interface is not available. For this reason, BDM is enabled during reset via the breakpoint (BKPT) signal.
BDM operation is enabled when BKPT is asserted (low), at the rising edge of RESET.
BDM remains enabled until the next system reset. A high BKPT signal on the trailing edge of RESET disables BDM. BKPT is latched again on each rising transition of RE-
SET. BKPT is synchronized internally, and must be held low for at least two clock cycles prior to negation of RESET.
BDM enable logic must be designed with special care. If hold time on BKPT extends into the first bus cycle following reset, the bus cycle could inadvertently be tagged with a breakpoint. Refer to the SIM Reference Manual (SIMRM/AD) for timing information.
5.10.2.2 BDM Sources
When BDM is enabled, any of several sources can cause the transition from normal mode to BDM. These sources include external breakpoint hardware, the BGND instruction, a double bus fault, and internal peripheral breakpoints. If BDM is not enabled
when an exception condition occurs, the exception is processed normally. Table 5-3
summarizes the processing of each source for both enabled and disabled cases. As
shown in Table 5-3, the BKPT instruction never causes a transition into BDM.
5
Source
BKPT
Double Bus Fault
BGND Instruction
BKPT Instruction
Table 5-3 BDM Source Summary
BDM Enabled
Background
Background
Background
Opcode Substitution/
Illegal Instruction
BDM Disabled
Breakpoint Exception
Halted
Illegal Instruction
Opcode Substitution/
Illegal Instruction
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5.10.2.2.1 External BKPT Signal
Once enabled, BDM is initiated whenever assertion of BKPT is acknowledged. If BDM is disabled, a breakpoint exception (vector $0C) is acknowledged. The BKPT input has the same timing relationship to the data strobe trailing edge as does read cycle data.
There is no breakpoint acknowledge bus cycle when BDM is entered.
5.10.2.2.2 BGND Instruction
An illegal instruction, $4AFA, is reserved for use by development tools. The CPU32 defines $4AFA (BGND) to be a BDM entry point when BDM is enabled. If BDM is disabled, an illegal instruction trap is acknowledged.
5.10.2.2.3 Double Bus Fault
The CPU32 normally treats a double bus fault, or two bus faults in succession, as a catastrophic system error, and halts. When this condition occurs during initial system debug (a fault in the reset logic), further debugging is impossible until the problem is corrected. In BDM, the fault can be temporarily bypassed, so that the origin of the fault can be isolated and eliminated.
5.10.2.2.4 Peripheral Breakpoints
CPU32 peripheral breakpoints are implemented in the same way as external breakpoints — peripherals request breakpoints by asserting the BKPT signal. Consult the appropriate peripheral user's manual for additional details on the generation of peripheral breakpoints.
5.10.2.3 Entering BDM
When the processor detects a breakpoint or a double bus fault, or decodes a BGND instruction, it suspends instruction execution and asserts the FREEZE output. This is the first indication that the processor has entered BDM. Once FREEZE has been asserted, the CPU enables the serial communication hardware and awaits a command.
The CPU writes a unique value indicating the source of BDM transition into temporary register A (ATEMP) as part of the process of entering BDM. A user can poll ATEMP
and determine the source (see Table 5-4) by issuing a read system register command
(RSREG). ATEMP is used in most debugger commands for temporary storage — it is imperative that the RSREG command be the first command issued after transition into
BDM.
5-20
Table 5-4 Polling the BDM Entry Source
Source
Double Bus Fault
BGND Instruction
Hardware Breakpoint
ATEMP[31:16]
SSW*
$0000
$0000
ATEMP[15:0]
$FFFF
$0001
$0000
*Special status word (SSW) is described in detail in the CPU32 Reference Manual (CPU32RM/AD).
A double bus fault during initial stack pointer/program counter (SP/PC) fetch sequence is distinguished by a value of $FFFFFFFF in the current instruction PC. At no other time will the processor write an odd value into this register.
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5.10.2.4 BDM Commands
Commands consist of one 16-bit operation word and can include one or more 16-bit extension words. Each incoming word is read as it is assembled by the serial interface.
The microcode routine corresponding to a command is executed as soon as the command is complete. Result operands are loaded into the output shift register to be shifted out as the next command is read. This process is repeated for each command until
the CPU returns to normal operating mode. Table 5-5 is a summary of background
mode commands.
Command
Read D/A Register
Write D/A Register
Read System Register
Write System Register
Read Memory Location
Write Memory Location
Dump Memory Block
Fill Memory Block
Patch User Code
Reset Peripherals
No Operation
Table 5-5 Background Mode Command Summary
Resume Execution
Mnemonic Description
RDREG/RAREG Read the selected address or data register and return the results via the serial interface.
WDREG/WAREG The data operand is written to the specified address or data register.
RSREG The specified system control register is read. All registers that can be read in supervisor mode can be read in background mode.
WSREG
READ
The operand data is written into the specified system control register.
Read the sized data at the memory location specified by the long-word address. The source function code register (SFC) determines the address space accessed.
WRITE
DUMP
FILL
GO
Write the operand data to the memory location specified by the long-word address. The destination function code (DFC) register determines the address space accessed.
Used in conjunction with the READ command to dump large blocks of memory. An initial READ is executed to set up the starting address of the block and retrieve the first result. Subsequent operands are retrieved with the DUMP command.
Used in conjunction with the WRITE command to fill large blocks of memory. An initial WRITE is executed to set up the starting address of the block and supply the first operand. Subsequent operands are written with the FILL command.
The pipe is flushed and re-filled before resuming instruction execution at the current PC.
CALL
RST
NOP
Current program counter is stacked at the location of the current stack pointer. Instruction execution begins at user patch code.
Asserts RESET for 512 clock cycles. The CPU is not reset by this command. Synonymous with the
CPU RESET instruction.
NOP performs no operation and may be used as a null command.
5.10.2.5 Background Mode Registers
BDM processing uses three special purpose registers to keep track of program context during development. A description of each follows.
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5.10.2.5.1 Fault Address Register (FAR)
The FAR contains the address of the faulting bus cycle immediately following a bus or address error. This address remains available until overwritten by a subsequent bus cycle. Following a double bus fault, the FAR contains the address of the last bus cycle.
The address of the first fault (if there was one) is not visible to the user.
5.10.2.5.2 Return Program Counter (RPC)
The RPC points to the location where fetching will commence after transition from background mode to normal mode. This register should be accessed to change the flow of a program under development. Changing the RPC to an odd value will cause an address error when normal mode prefetching begins.
5.10.2.5.3 Current Instruction Program Counter (PCC)
The PCC holds a pointer to the first word of the last instruction executed prior to transition into background mode. Due to instruction pipelining, the instruction pointed to may not be the instruction which caused the transition. An example is a breakpoint on a released write. The bus cycle may overlap as many as two subsequent instructions before stalling the instruction sequencer. A breakpoint asserted during this cycle will not be acknowledged until the end of the instruction executing at completion of the bus cycle. PCC will contain $00000001 if BDM is entered via a double bus fault immediately out of reset.
5.10.2.6 Returning from BDM
BDM is terminated when a resume execution (GO) or call user code (CALL) command is received. Both GO and CALL flush the instruction pipeline and refetch instructions from the location pointed to by the RPC.
The return PC and the memory space referred to by the status register SUPV bit reflect any changes made during BDM. FREEZE is negated prior to initiating the first prefetch. Upon negation of FREEZE, the serial subsystem is disabled, and the signals revert to IPIPE/IFETCH functionality.
5.10.2.7 Serial Interface
Communication with the CPU32 during BDM occurs via a dedicated serial interface,
which shares pins with other development features. Figure 5-9 is a block diagram of
the interface. The BKPT signal becomes the serial clock (DSCLK); serial input data
(DSI) is received on IFETCH, and serial output data (DSO) is transmitted on IPIPE.
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CPU
INSTRUCTION
REGISTER BUS
16
RCV DATA LATCH
0
DEVELOPMENT SYSTEM
DATA
16
COMMAND LATCH
STATUS
EXECUTION
UNIT
SYNCHRONIZE
MICROSEQUENCER
SERIAL IN
PARALLEL OUT
PARALLEL IN
SERIAL OUT
16
CONTROL
LOGIC
M
DSI
PARALLEL IN
SERIAL OUT
DSO
SERIAL IN
PARALLEL OUT
DSCLK
STATUS
RESULT LATCH
16
DATA
CONTROL
LOGIC
SERIAL
CLOCK
5
32 DEBUG I/O BLOCK
Figure 5-9 Debug Serial I/O Block Diagram
The serial interface uses a full-duplex synchronous protocol similar to the serial peripheral interface (SPI) protocol. The development system serves as the master of the serial link since it is responsible for the generation of DSCLK. If DSCLK is derived from the CPU32 system clock, development system serial logic is unhindered by the operating frequency of the target processor. Operable frequency range of the serial clock is from DC to one-half the processor system clock frequency.
The serial interface operates in full-duplex mode —data is transmitted and received simultaneously by both master and slave devices. In general, data transitions occur on the falling edge of DSCLK and are stable by the following rising edge of DSCLK. Data is transmitted MSB first, and is latched on the rising edge of DSCLK.
The serial data word is 17 bits wide — 16 data bits and a status/control bit. Bit 16 in-
dicates the status of CPU-generated messages as shown in Table 5-6.
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DATA FIELD
0 16 15
⇑
S/C
STATUS CONTROL BIT
Figure 5-10 BDM Serial Data Word
5
Table 5-6 CPU Generated Message Encoding
Bit 16
0
0
1
1
1
Data
xxxx
Message Type
Valid Data Transfer
FFFF Command Complete; Status OK
0000 Not Ready with Response; Come Again
0001 BERR Terminated Bus Cycle; Data Invalid
FFFF Illegal Command
Command and data transfers initiated by the development system should clear bit 16.
The current implementation ignores this bit; however,
Freescale
reserves the right to use this bit for future enhancements.
5.10.2.8 Recommended BDM Connection
In order to provide for use of development tools when an MCU is installed in a system,
Freescale recommends that appropriate signal lines be routed to a male Berg connector or double-row header installed on the circuit board with the MCU, as shown in the following figure.
DS 1
GND
GND
RESET
3
5
7
V
DD
9
2
4
6
BERR
BKPT/DSCLK
FREEZE
8 IFETCH/DSI
10 IPIPE/DSO
32 BERG
Figure 5-11 BDM Connector Pinout
5.10.3 Deterministic Opcode Tracking
CPU32 function code outputs are augmented by two supplementary signals to monitor the instruction pipeline. The instruction pipe (IPIPE) output indicates the start of each new instruction and each mid-instruction pipeline advance. The instruction fetch
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(IFETCH) output identifies the bus cycles in which the operand is loaded into the instruction pipeline. Pipeline flushes are also signaled with IFETCH. Monitoring these two signals allows a bus analyzer to synchronize itself to the instruction stream and monitor its activity.
5.10.4 On-Chip Breakpoint Hardware
An external breakpoint input and on-chip breakpoint hardware allow a breakpoint trap on any memory access. Off-chip address comparators preclude breakpoints unless show cycles are enabled. Breakpoints on instruction prefetches that are ultimately flushed from the instruction pipeline are not acknowledged; operand breakpoints are always acknowledged. Acknowledged breakpoints initiate exception processing at the address in exception vector number 12, or alternately enter background mode.
5.11 Loop Mode Instruction Execution
The CPU32 has several features that provide efficient execution of program loops.
One of these features is the DBcc looping primitive instruction. To increase the performance of the CPU32, a loop mode has been added to the processor. The loop mode is used by any single word instruction that does not change the program flow. Loop
mode is implemented in conjunction with the DBcc instruction. Figure 5-12 shows the
required form of an instruction loop for the processor to enter loop mode.
5
ONE WORD INSTRUCTION
DBCC
DBCC DISPLACEMENT
$FFFC = – 4
1126A
Figure 5-12 Loop Mode Instruction Sequence
The loop mode is entered when the DBcc instruction is executed, and the loop displacement is –4. Once in loop mode, the processor performs only the data cycles associated with the instruction and suppresses all instruction fetches. The termination condition and count are checked after each execution of the data operations of the looped instruction. The CPU32 automatically exits the loop mode on interrupts or other exceptions. All single word instructions that do not cause a change of flow can be looped.
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SECTION 6QUEUED SERIAL MODULE
This section is an overview of queued serial module (QSM) function. Refer to the
QSM
Reference Manual (QSMRM/AD) for complete information about the QSM.
6.1 General
The QSM contains two serial interfaces, the queued serial peripheral interface (QSPI)
and the serial communication interface (SCI). Figure 6-1 is a block diagram of the
QSM.
QSPI
MISO/PQS0
MOSI/PQS1
SCK/PQS2
PCS0/SS/PQS3
PCS1/PQS4
PCS2/PQS5
PCS3/PQS6
PORT QS
IMB
INTERFACE
LOGIC
SCI
TXD/PQS7
RXD
Figure 6-1 QSM Block Diagram
The QSPI provides easy peripheral expansion or interprocessor communication through a full-duplex, synchronous, three-line bus. Four programmable peripheral chip selects can select up to 16 peripheral devices. A self-contained RAM queue allows up to sixteen serial transfers of eight to sixteen bits each or transmission of a 256-bit data stream without CPU intervention. A special wraparound mode supports continuous sampling of a serial peripheral, with automatic QSPI RAM updating, for efficient interfacing to A/D converters.
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The SCI provides a standard nonreturn to zero (NRZ) mark/space format. It will operate in either full- or half-duplex mode. There are separate transmitter and receiver enable bits and dual data buffers. A modulus-type baud rate generator provides rates from 64 to 524 kbaud with a 16.78-MHz system clock, or 110 to 655 kbaud with a
20.97-MHz system clock. Word length of either eight or nine bits can be selected. Optional parity generation and detection provide either even or odd parity check capability. Advanced error detection circuitry catches glitches of up to 1/16 of a bit time in duration. Wakeup functions allow the CPU to run uninterrupted until meaningful data is available.
6.2 QSM Registers and Address Map
There are four types of QSM registers: QSM global registers, QSM pin control registers, QSPI registers, and SCI registers. Global registers and pin control registers are
discussed in 6.2.1 QSM Global Registers and 6.2.2 QSM Pin Control Registers.
QSPI and SCI registers are discussed in 6.3 Queued Serial Peripheral Interface and
6.4 Serial Communication Interface. Writes to unimplemented register bits have no
meaning or effect, and reads from unimplemented bits always return a logic zero value.
The QSM address map includes the QSM registers and the QSPI RAM. The module mapping (MM) bit in the SIM configuration register (SIMCR) defines the most significant bit (ADDR23) of the IMB address for each module in the MCU.
Refer to APPENDIX D REGISTER SUMMARY for a QSM address map and register
bit/field definitions. SECTION 4 SYSTEM INTEGRATION MODULE contains more in-
formation about how the state of MM affects the system.
6.2.1 QSM Global Registers
The QSM configuration register (QSMCR) contains parameters for interfacing to the
CPU32 and the intermodule bus. The QSM test register (QTEST) is used during factory test of the QSM. The QSM interrupt level register (QILR) interrupt level register
(QILR) determines the priority of interrupts requested by the QSM and the vector used when an interrupt is acknowledged. The QSM interrupt vector register (QIVR) interrupt vector register (QIVR) contains the interrupt vector for both QSM submodules. QILR
and QIVR are 8-bit registers located at the same word address. Refer to APPENDIX
D REGISTER SUMMARY for register bit and field definitions.
6.2.1.1 Low-Power Stop Operation
When the STOP bit in the QSMCR is set, the system clock input to the QSM is disabled and the module enters a low-power operating state. QSMCR is the only register guaranteed to be readable while STOP is asserted. The QSPI RAM is not readable, but writes to RAM or any register are guaranteed valid while STOP is asserted. STOP can be set by the CPU and by reset.
System software must stop the QSPI and SCI before asserting STOP to prevent data corruption and simplify restart. Disable both SCI receiver and transmitter after transfers in progress are complete. Halt the QSPI by setting the HALT bit in SPCR3 and
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then setting STOP after the HALTA flag is set. Refer to SECTION 4 SYSTEM INTE-
GRATION MODULE for more information about low-power operation.
6.2.1.2 Freeze Operation
The freeze (FRZ[1:0]) bits in the QSMCR are used to determine what action is taken by the QSM when the IMB FREEZE signal is asserted. FREEZE is asserted when the
CPU enters background debugging mode. At the present time, FRZ0 has no effect; setting FRZ1 causes the QSPI to halt on the first transfer boundary following FREEZE
assertion. Refer to SECTION 5 CENTRAL PROCESSING UNIT for more information
about background debugging mode.
6.2.1.3 QSM Interrupts
Both the QSPI and SCI can make interrupt requests on the IMB. Each has a separate interrupt request priority register, but a single vector register is used to generate exception vector numbers.
The values of the ILQSPI and ILSCI fields in the QILR determine the priority of QSPI and SCI interrupt requests. The values in these fields correspond to internal interrupt request signals IRQ[7:1]. A value of %111 causes IRQ7 to be asserted when a QSM interrupt request is made; lower field values cause corresponding lower-numbered interrupt request signals to be asserted. Setting field value to %000 disables interrupts.
If ILQSPI and ILSCI have the same nonzero value, and the QSPI and SCI make simultaneous interrupt requests, the QSPI has priority.
When the CPU32 acknowledges an interrupt request, it places the value in the interrupt priority (IP) mask in the CPU status register on the address bus. The QSM compares IP mask value to request priority to determine whether it should contend for arbitration priority. Arbitration priority is determined by the value of the IARB field in the
QSMCR. Each module that generates interrupts must have a nonzero IARB value. Arbitration is performed by means of serial assertion of IARB field bit values.
When the QSM wins interrupt arbitration, it responds to the CPU interrupt acknowledge cycle by placing an interrupt vector number on the data bus. The vector number is used to calculate displacement into the CPU32 exception vector table. SCI and
QSPI vector numbers are generated from the value in the QIVR INTV field. The values of bits INTV[7:1] are the same for QSPI and SCI, but the value of INTV0 is supplied by the QSM when an interrupt request is made. INTV0 = 0 for SCI interrupt requests;
INTV0 = 1 for QSPI requests.
At reset, INTV is initialized to $0F, the uninitialized interrupt vector number. To enable interrupt-driven serial communication, a user-defined vector number ($40–$FF) must be written to QIVR, and interrupt handler routines must be located at the addresses pointed to by the corresponding vector. CPU writes to INTV0 have no meaning or effect. Reads of INTV0 return a value of one.
Refer to SECTION 5 CENTRAL PROCESSING UNIT and SECTION 4 SYSTEM IN-
TEGRATION MODULE for more information about exceptions and interrupts.
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6.2.2 QSM Pin Control Registers
The QSM uses nine pins. Eight of the pins can be used for serial communication or for parallel I/O. Clearing a bit in the port QS pin assignment register (PQSPAR) assigns the corresponding pin to general-purpose I/O; setting a bit assigns the pin to the QSPI.
PQSPAR does not affect operation of the SCI.
The port QS data direction register (DDRQS) determines whether pins are inputs or outputs. Clearing a bit makes the corresponding pin an input; setting a bit makes the pin an output. DDRQS affects both QSPI function and I/O function. DDQS1 determines the direction of the TXD pin only when the SCI transmitter is disabled. When the
SCI transmitter is enabled, the TXD pin is an output. PQSPAR and DDRQS are 8-bit
registers located at the same word address. Table 6-1 is a summary of QSM pin func-
tions.
The port QS data register (PORTQS) latches I/O data. Writes to PORTQS drive pins defined as outputs. PORTQS reads return data present on the pins when the read is made. To avoid driving undefined data, first write PORTQS, then configure DDRQS.
Table 6-1 QSM Pin Function
QSM Pin
MISO
MOSI
SCK
1
PCS0/SS
PCS[3:1]
TXD
2
RXD
Mode
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Transmit
Receive
DDRQS Bit
DDQS0
DDQS1
DDQS2
DDQS3
DDQS[4:6]
DDQS7
None
1
0
1
0
1
0
1
0
Bit
State
0
1
0
1
0
1
0
1
0
1
0
1
X
NA
Pin Function
Serial Data Input to QSPI
Disables Data Input
Disables Data Output
Serial Data Output from QSPI
Disables Data Output
Serial Data Output from QSPI
Serial Data Input to QSPI
Disables Data Input
Disables Clock Output
Clock Output from QSPI
Clock Input to QSPI
Disables Clock Input
Assertion Causes Mode Fault
Chip-Select Output
QSPI Slave Select Input
Disables Select Input
Disables Chip-Select Output
Chip-Select Output
Inactive
Inactive
Serial Data Output from SCI
Serial Data Input to SCI
1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE in SPCR1 set), in which case it becomes the SPI serial clock SCK.
2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE in SCCR1 set), in which case it becomes
SCI serial output TXD and DDRQS has no effect.
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6.3 Queued Serial Peripheral Interface
The queued serial peripheral interface (QSPI) communicates with external devices through a synchronous serial bus. The QSPI is fully compatible with SPI systems found on other Freescale products, but has enhanced capabilities. The QSPI can perform full duplex three-wire or half duplex two-wire transfers. A variety of transfer rate, clocking, and interrupt-driven communication options are available.
Serial transfer of any number of bits from eight to sixteen can be specified. Programmable transfer length simplifies interfacing to a number of devices that require different data lengths.
An inter-transfer delay of 17 to 8192 system clocks can be specified (default is 17 system clocks). Programmable delay simplifies the interface to a number of devices that require different delays between transfers.
A dedicated 80-byte RAM is used to store received data, data to be transmitted, and a queue of commands. The CPU can access these locations directly. Serial peripherals can be treated like memory-mapped parallel devices.
The command queue allows the QSPI to perform up to 16 serial transfers without CPU intervention. Each queue entry contains all the information needed by the QSPI to independently complete one serial transfer.
A pointer identifies the queue location containing the command for the next serial transfer. Normally, the pointer address is incremented after each serial transfer, but the CPU can change the pointer value at any time. Multiple-task support can be provided by segmenting the queue.
The QSPI has four peripheral chip-select pins. Chip-select signals simplify interfacing by reducing CPU intervention. If chip-select signals are externally decoded, 16 independent select signals can be generated. Each chip-select pin can drive up to four independent peripherals, depending on loading.
Wraparound operating mode allows continuous execution of queued commands. In wraparound mode, newly received data replaces previously received data in receive
RAM. Wraparound can simplify the interface with A/D converters by continuously updating conversion values stored in the RAM.
Continuous transfer mode allows simultaneous transfer of an uninterrupted bit stream.
Any number of bits in a range from 8 to 256 can be transferred without CPU intervention. Longer transfers are possible, but minimal CPU intervention is required to prevent loss of data. A standard delay of 17 system clocks is inserted between each queue entry transfer.
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6
QUEUE CONTROL
BLOCK
QUEUE
POINTER
COMPARATOR
END QUEUE
POINTER
CONTROL
LOGIC
STATUS
REGISTER
CONTROL
REGISTERS
DELAY
COUNTER
4
DONE
4
ADDRESS
REGISTER
4
4
CHIP SELECT
COMMAND
80-BYTE
QSPI RAM
PROGRAMMABLE
LOGIC ARRAY
MSB LSB
8/16-BIT SHIFT REGISTER
Rx/Tx DATA REGISTER
3
M
S
M
S
MOSI
MISO
PCS0/SS
PCS [3:1]
SCK
BAUD RATE
GENERATOR
QSPI BLOCK
Figure 6-2 QSPI Block Diagram
6.3.1 QSPI Registers
The programmer's model for the QSPI consists of the QSM global and pin control registers, four QSPI control registers (SPCR[0:3]), a status register (SPCR), and the 80byte QSPI RAM.
Registers and RAM can be read and written by the CPU. Refer to APPENDIX D REG-
ISTER SUMMARY for register bit and field definitions.
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6.3.1.1 Control Registers
Control registers contain parameters for configuring the QSPI and enabling various modes of operation. The CPU has read and write access to all control registers, but the QSM has read-only access to all bits except the SPE bit in SPCR1. Control registers must be initialized before the QSPI is enabled to ensure defined operation.
SPCR1 must be written last because it contains the QSPI enable bit (SPE).
Writing a new value to any control register except SPCR2 while the QSPI is enabled disrupts operation. SPCR2 is buffered. New SPCR2 values become effective after completion of the current serial transfer. Rewriting NEWQP in SPCR2 causes execution to restart at the designated location. Reads of SPCR2 return the current value of the register, not of the buffer.
Writing the same value into any control register except SPCR2 while the QSPI is enabled has no effect on QSPI operation.
6.3.1.2 Status Register
The QSPI status register (SPSR) contains information concerning the current serial transmission. Only the QSPI can set the bits in this register. The CPU reads the SPSR to obtain QSPI status information and writes it to clear status flags.
6.3.2 QSPI RAM
The QSPI contains an 80-byte block of dual-access static RAM that can be accessed by both the QSPI and the CPU. The RAM is divided into three segments: receive data
RAM, transmit data RAM, and command control data RAM. Receive data is information received from a serial device external to the MCU. Transmit data is information stored by the CPU for transmission to an external device. Command control data is
used to perform transfers. Refer to Figure 6-3, which shows RAM organization.
6
D00
D1E
RR0
RR1
RR2
RECEIVE
RAM
RRD
RRE
RRF
WORD
D20
D3E
TR0
TR1
TR2
TRANSMIT
RAM
TRD
TRE
TRF
WORD
D40
D4F
CR0
CR1
CR2
COMMAND
RAM
CRD
CRE
CRF
BYTE
QSPI RAM MAP
Figure 6-3 QSPI RAM
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6.3.2.1 Receive RAM
Data received by the QSPI is stored in this segment. The CPU reads this segment to retrieve data from the QSPI. Data stored in receive RAM is right-justified. Unused bits in a receive queue entry are set to zero by the QSPI upon completion of the individual queue entry. The CPU can access the data using byte, word, or long-word addressing.
The CPTQP value in SPSR shows which queue entries have been executed. The CPU uses this information to determine which locations in receive RAM contain valid data before reading them.
6.3.2.2 Transmit RAM
Data that is to be transmitted by the QSPI is stored in this segment. The CPU normally writes one word of data into this segment for each queue command to be executed.
Information to be transmitted must be written to transmit RAM in a right-justified format. The QSPI cannot modify information in the transmit RAM. The QSPI copies the information to its data serializer for transmission. Information remains in transmit RAM until overwritten.
6.3.2.3 Command RAM
Command RAM is used by the QSPI in master mode. The CPU writes one byte of control information to this segment for each QSPI command to be executed. The QSPI cannot modify information in command RAM.
Command RAM consists of 16 bytes. Each byte is divided into two fields. The peripheral chip-select field enables peripherals for transfer. The command control field provides transfer options.
A maximum of 16 commands can be in the queue. Queue execution by the QSPI proceeds from the address in NEWQP through the address in ENDQP (both of these fields are in SPCR2).
6.3.3 QSPI Pins
The QSPI uses seven pins. These pins can be configured for general-purpose I/O when not needed for QSPI application. When used for QSPI functions, the MOSI, MI-
SO, and SS pins should have pull-up resistors.
Table 6-2 shows QSPI input and output pins and their functions.
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Pin/Signal Name
Master In Slave Out
Master Out Slave In
Serial Clock
Peripheral Chip Selects
Slave Select
Peripheral Chip Select 0
Table 6-2 QSPI Pin Function
Mnemonic
MISO
MOSI
SCK
PCS[3:1]
SS
PCS0
Mode
Master
Slave
Master
Slave
Master
Slave
Master
Master
Slave
Master
Function
Serial Data Input to QSPI Serial
Data Output from QSPI
Serial Data Output from QSPI
Serial Data Input to QSPI
Clock Output from QSPI
Clock Input to QSPI
Select Peripherals
Causes Mode Fault
Initiates Serial Transfer
Selects Peripherals
6.3.4 QSPI Operation
The QSPI uses a dedicated 80-byte block of static RAM accessible by both the QSPI and the CPU to perform queued operations. The RAM is divided into three segments.
There are 16 command control bytes, 16 transmit data words, and 16 receive data words. QSPI RAM is organized so that one byte of command control data, one word of transmit data, and one word of receive data correspond to one queue entry, $0–$F.
The CPU initiates QSPI operation by setting up a queue of QSPI commands in command RAM, writing transmit data into transmit RAM, then enabling the QSPI. The
QSPI executes the queued commands, sets a completion flag (SPIF), and then either interrupts the CPU or waits for CPU intervention.
There are four queue pointers. The CPU can access three of them through fields in
QSPI registers. The new queue pointer (NEWQP), in SPCR2, points to the first command in the queue. An internal queue pointer points to the command currently being executed. The completed queue pointer (CPTQP), in SPSR, points to the last command executed. The end queue pointer (ENDQP), contained in SPCR2, points to the final command in the queue.
The internal pointer is initialized to the same value as NEWQP. During normal operation, the command pointed to by the internal pointer is executed, the value in the internal pointer is copied into CPTQP, the internal pointer is incremented, and then the sequence repeats. Execution continues at the internal pointer address unless the
NEWQP value is changed. After each command is executed, ENDQP and CPTQP are compared. When a match occurs, the SPIF flag is set and the QSPI stops unless wraparound mode is enabled.
At reset, NEWQP is initialized to $0. When the QSPI is enabled, execution begins at queue address $0 unless another value has been written into NEWQP. ENDQP is initialized to $0 at reset, but should be changed to show the last queue entry before the
QSPI is enabled. NEWQP and ENDQP can be written at any time. When the NEWQP value changes, the internal pointer value also changes. However, if NEWQP is written while a transfer is in progress, the transfer is completed normally. Leaving NEWQP and ENDQP set to $0 causes a single transfer to occur when the QSPI is enabled.
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6.3.5 QSPI Operating Modes
The QSPI operates in either master or slave mode. Master mode is used when the
MCU originates data transfers. Slave mode is used when an external device initiates serial transfers to the MCU through the QSPI. Switching between the modes is controlled by MSTR in SPCR0. Before either mode is entered, appropriate QSM and QSPI registers must be initialized properly.
In master mode, the QSPI executes a queue of commands defined by control bits in each command RAM queue entry. Chip-select pins are activated, data is transmitted from transmit RAM and received by the receive RAM.
In slave mode, operation proceeds in response to SS pin activation by an external bus master. Operation is similar to master mode, but no peripheral chip selects are generated, and the number of bits transferred is controlled in a different manner. When the
QSPI is selected, it automatically executes the next queue transfer to exchange data with the external device correctly.
Although the QSPI inherently supports multimaster operation no special arbitration mechanism is provided. A mode fault flag (MODF) indicates a request for SPI master arbitration. System software must provide arbitration. Note that unlike previous SPI systems, MSTR is not cleared by a mode fault being set nor are the QSPI pin output drivers disabled. The QSPI and associated output drivers must be disabled by clearing
SPE in SPCR1.
Figure 6-4 shows QSPI initialization; Figure 6-5 and Figure 6-6 show QSPI master
and slave operation. The CPU must initialize the QSM global and pin registers and the
QSPI control registers before enabling the QSPI for either mode of operation (refer to
6.5 QSM Initialization). The command queue must be written before the QSPI is en-
abled for master mode operation. Any data to be transmitted should be written into transmit RAM before the QSPI is enabled. During wraparound operation, data for subsequent transmissions can be written at any time.
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BEGIN
CPU INITIALIZES
QSM GLOBAL REGISTERS
CPU INITIALIZES
QSM PIN REGISTERS
CPU INITIALIZES
QSPI CONTROL REGISTERS
CPU INITIALIZES
QSPI RAM
INITIALIZATION OF
QSPI BY THE CPU
CPU ENABLES QSPI
YES
MSTR = 1
?
NO
A2
A1
QSPI FLOW 1
Figure 6-4 Flowchart of QSPI Initialization Operation
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QSPI CYCLE BEGINS
(MASTER MODE)
A1
IS QSPI
DISABLED
?
NO
YES
HAS NEWQP
BEEN WRITTEN
?
NO
YES
READ COMMAND CONTROL
AND TRANSMIT DATA
FROM RAM USING QUEUE
POINTER ADDRESS
ASSERT PERIPHERAL
CHIP-SELECT(S)
WORKING QUEUE POINTER
CHANGED TO NEWQP
IS PCS TO
SCK DELAY
PROGRAMMED
?
NO
EXECUTE STANDARD DELAY
YES
EXECUTE PROGRAMMED DELAY
EXECUTE SERIAL TRANSFER
STORE RECEIVED DATA
IN RAM USING QUEUE
POINTER ADDRESS
B1
QSPI FLOW 2
Figure 6-5 Flowchart of QSPI Master Operation (Part 1)
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QSPI CYCLE BEGINS
(SLAVE MODE)
A2
IS QSPI
DISABLED
?
NO
YES
HAS NEWQP
BEEN WRITTEN
?
NO
YES
READ TRANSMIT DATA
FROM RAM USING QUEUE
POINTER ADDRESS
IS SLAVE
SELECT PIN
ASSERTED
?
NO
YES
QUEUE POINTER
CHANGED TO NEWQP
EXECUTE SERIAL TRANSFER
WHEN SCK RECEIVED
STORE RECEIVED DATA
IN RAM USING QUEUE
POINTER ADDRESS
WRITE QUEUE POINTER TO
CPTQP STATUS BITS
B2
QSPI FLOW 3
Figure 6-5 Flowchart of QSPI Master Operation (Part 2)
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B1
WRITE QUEUE POINTER
TO CPTQP STATUS BITS
IS CONTINUE
BIT ASSERTED
?
NO
NEGATE PERIPHERAL
CHIP-SELECT(S)
YES
IS DELAY
AFTER TRANSFER
ASSERTED
?
NO
YES
EXECUTE STANDARD DELAY
EXECUTE PROGRAMMED DELAY
C
QSPI FLOW 4
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B2
IS QSPI
DISABLED
?
NO
YES
HAS NEWQP
BEEN WRITTEN
?
NO
YES
READ TRANSMIT DATA
FROM RAM USING QUEUE
POINTER ADDRESS
IS SLAVE
SELECT PIN
ASSERTED
?
NO
YES
QUEUE POINTER
CHANGED TO NEWQP
EXECUTE SERIAL TRANSFER
WHEN SCK RECEIVED
STORE RECEIVED DATA
IN RAM USING QUEUE
POINTER ADDRESS
WRITE QUEUE POINTER TO
CPTQP STATUS BITS
C
QSPI FLOW 5
Figure 6-6 Flowchart of QSPI Slave Operation (Part 1)
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C
IS THIS THE
LAST COMMAND
IN THE QUEUE
?
NO
YES
INCREMENT WORKING
QUEUE POINTER
ASSERT SPIF
STATUS FLAG
IS INTERRUPT
ENABLE BIT SPIFIE
ASSERTED
?
NO
YES
INTERRUPT CPU
IS WRAP
ENABLE BIT
ASSERTED
?
NO
DISABLE QSPI
YES
RESET WORKING QUEUE
POINTER TO NEWQP OR $0000
A1
IS HALT
OR FREEZE
ASSERTED
?
NO
YES
HALT QSPI AND
ASSERT HALTA
IS INTERRUPT
ENABLE BIT HMIE
ASSERTED
?
NO
YES
IS HALT
OR FREEZE
ASSERTED
?
NO
YES
INTERRUPT CPU
A2
Figure 6-6 Flowchart of QSPI Slave Operation (Part 2)
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Normally, the SPI bus performs synchronous bidirectional transfers. The serial clock on the SPI bus master supplies the clock signal (SCK) to time the transfer of data. Four possible combinations of clock phase and polarity can be specified by the CPHA and
CPOL bits in SPCR0.
Data is transferred with the most significant bit first. The number of bits transferred per command defaults to eight, but can be set to any value from eight to sixteen bits by writing a value into the BITSE field in command RAM.
Typically, SPI bus outputs are not open-drain unless multiple SPI masters are in the system. If needed, the WOMQ bit in SPCR0 can be set to provide wired-OR, opendrain outputs. An external pull-up resistor should be used on each output line. WOMQ affects all QSPI pins regardless of whether they are assigned to the QSPI or used as general-purpose I/O.
6.3.5.1 Master Mode
Setting the MSTR bit in SPCR0 selects master mode operation. In master mode, the
QSPI can initiate serial transfers, but cannot respond to externally initiated transfers.
When the slave select input of a device configured for master mode is asserted, a mode fault occurs.
Before QSPI operation is initiated, QSM register PQSPAR must be written to assign necessary pins to the QSPI. The pins necessary for master mode operation are MISO and MOSI, SCK, and one or more of the chip-select pins. MISO is used for serial data input in master mode, and MOSI is used for serial data output. Either or both may be necessary, depending on the particular application. SCK is the serial clock output in master mode.
Before master mode operation is initiated, QSM register DDRQS must be written to direct the data flow on the QSPI pins used. Configure the SCK, MOSI and appropriate chip-select pins PCS[3:0]/SS as outputs. The MISO pin must be configured as an input.
After pins are assigned and configured, write appropriate data to the command queue.
If data is to be transmitted, write the data to transmit RAM. Initialize the queue pointers as appropriate.
Data transfer is synchronized with the internally-generated serial clock (SCK). Control bits, CPHA and CPOL, in SPCR0, control clock phase and polarity. Combinations of
CPHA and CPOL determine upon which SCK edge to drive outgoing data from the
MOSI pin and to latch incoming data from the MISO pin.
Baud rate is selected by writing a value from 2 to 255 into the SPBR field in SPCR0.
The QSPI uses a modulus counter to derive SCK baud rate from the MCU system clock.
The following expressions apply to SCK baud rate:
SCK Baud Rate
=
System Clock
------------------------------------
2
×
SPBR
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or
SPBR
=
(
2
×
SCK
)
System Clock
× (
Baud Rate Desired
)
Giving SPBR a value of zero or one disables the baud rate generator. SCK is disabled and assumes its inactive state value.
The DSCK field in command RAM determines the delay period from chip-select assertion until the leading edge of the serial clock. The DSCKL field in SPCR1 determines the period of delay before the assertion of SCK. The following expression determines the actual delay before SCK:
PCS to SCK Delay
=
DSCKL
------------------------------------------------------------------
System Clock Frequency where DSCKL equals {1, 2, 3,..., 127}.
When DSCK equals zero, DSCKL is not used. Instead, the PCS valid-to-SCK transition is one-half the DSCK period.
There are two transfer length options. The user can choose a default value of eight bits, or a programmed value of eight to sixteen bits, inclusive. The programmed value must be written into the BITS field in SPCR0. The BITSE field in command RAM determines whether the default value (BITSE = 0) or the BITS value (BITSE = 1) is used.
Table 6-3 shows BITS field encoding.
Table 6-3 BITS Encoding
0111
1000
1001
1010
1011
1100
1101
1110
1111
BITS
0000
0001
0010
0011
0100
0101
0110
Bits per Transfer
16
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
8
9
10
11
12
13
14
15
Delay after transfer can be used to provide a peripheral deselect interval. A delay can also be inserted between consecutive transfers to allow serial A/D converters to complete conversion. There are two transfer delay options. The user can choose to delay a standard period after serial transfer is complete or can specify a delay period. Writing a value to the DTL field in SPCR1 specifies a delay period. The DT bit in command
RAM determines whether the standard delay period (DT = 0) or the specified delay pe-
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riod (DT = 1) is used. The following expression is used to calculate the delay:
Delay after Transfer
=
32
×
DTL
------------------------------------------------------------------
System Clock Frequency where DTL equals {1, 2, 3,..., 255}.
A zero value for DTL causes a delay-after-transfer value of 8192/system clock.
Standard Delay after Transfer
=
17
------------------------------------
System Clock
Adequate delay between transfers must be specified for long data streams because the QSPI requires time to load a transmit RAM entry for transfer. Receiving devices need at least the standard delay between successive transfers. If the system clock is operating at a slower rate, the delay between transfers must be increased proportionately.
Operation is initiated by setting the SPE bit in SPCR1. Shortly after SPE is set, the
QSPI executes the command at the command RAM address pointed to by NEWQP.
Data at the pointer address in transmit RAM is loaded into the data serializer and transmitted. Data that is simultaneously received is stored at the pointer address in receive RAM.
When the proper number of bits have been transferred, the QSPI stores the working queue pointer value in CPTQP, increments the working queue pointer, and loads the next data for transfer from transmit RAM. The command pointed to by the incremented working queue pointer is executed next, unless a new value has been written to
NEWQP. If a new queue pointer value is written while a transfer is in progress, that transfer is completed normally.
When the CONT bit in command RAM is set, PCS pins are continuously driven in specified states during and between transfers. If the chip-select pattern changes during or between transfers, the original pattern is driven until execution of the following transfer begins. When CONT is cleared, the data in register PORTQS is driven between transfers.
When the QSPI reaches the end of the queue, it sets the SPIF flag. If the SPIFIE bit in SPCR2 is set, an interrupt request is generated when SPIF is asserted. At this point, the QSPI clears SPE and stops unless wraparound mode is enabled.
6.3.5.2 Master Wraparound Mode
Wraparound mode is enabled by setting the WREN bit in SPCR2. The queue can wrap to pointer address $0 or to the address pointed to by NEWQP, depending on the state of the WRTO bit in SPCR2.
In wraparound mode, the QSPI cycles through the queue continuously, even while the
QSPI is requesting interrupt service. SPE is not cleared when the last command in the queue is executed. New receive data overwrites previously received data in receive
RAM. Each time the end of the queue is reached, the SPIF flag is set. SPIF is not automatically reset. If interrupt-driven SPI service is used, the service routine must clear the SPIF bit to abort the current request. Additional interrupt requests during servicing
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can be prevented by clearing SPIFIE, but SPIFIE is buffered. Clearing it does not abort a current request.
There are two recommended methods of exiting wraparound mode: clearing the
WREN bit or setting the HALT bit in SPCR3. Exiting wraparound mode by clearing
SPE is not recommended, as clearing SPE may abort a serial transfer in progress. The
QSPI sets SPIF, clears SPE, and stops the first time it reaches the end of the queue after WREN is cleared. After HALT is set, the QSPI finishes the current transfer, then stops executing commands. After the QSPI stops, SPE can be cleared.
6.3.5.3 Slave Mode
Clearing the MSTR bit in SPCR0 selects slave mode operation. In slave mode, the
QSPI is unable to initiate serial transfers. Transfers are initiated by an external bus master. Slave mode is typically used on a multi-master SPI bus. Only one device can be bus master (operate in master mode) at any given time.
Before QSPI operation is initiated, QSM register PQSPAR must be written to assign necessary pins to the QSPI. The pins necessary for slave mode operation are MISO and MOSI, SCK, and PCS0/SS. MISO is used for serial data output in slave mode, and
MOSI is used for serial data input. Either or both may be necessary, depending on the particular application. SCK is the serial clock input in slave mode. Assertion of the active-low slave select signal (SS) initiates slave mode operation.
Before slave mode operation is initiated, DDRQS must be written to direct data flow on the QSPI pins used. Configure the MOSI, SCK and PCS0/SS pins as inputs. The
MISO pin must be configured as an output.
After pins are assigned and configured, write data to be transmitted into transmit RAM.
Command RAM is not used in slave mode and does not need to be initialized. Unused portions of QSPI RAM can be used by the CPU as general-purpose RAM. Initialize the queue pointers as appropriate.
When SPE is set and MSTR is clear, a low state on the slave select (PCS0/SS) pin begins slave mode operation at the address indicated by NEWQP. Data that is received is stored at the pointer address in receive RAM. Data is simultaneously loaded into the data serializer from the pointer address in transmit RAM and transmitted.
Transfer is synchronized with the externally generated SCK. The CPHA and CPOL bits determine on which SCK edge to latch incoming data from the MISO pin and to drive outgoing data from the MOSI pin.
Because the command control segment is not used, the command control bits and peripheral chip-select codes have no effect in slave mode operation. The PCS0/SS pin is used only as an input.
The SPBR, DT and DSCK bits are not used in slave mode. The QSPI drives neither the clock nor the chip-select pins and thus cannot control clock rate or transfer delay.
Because the BITSE option is not available in slave mode, the BITS field specifies the number of bits to be transferred for all transfers in the queue. When the number of bits
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designated by BITS has been transferred, the QSPI stores the working queue pointer value in CPTQP, increments the working queue pointer, and loads new transmit data from transmit RAM into the data serializer. The working queue pointer address is used the next time PCS0/SS is asserted, unless the CPU writes to NEWQP first.
The QSPI shifts one bit for each pulse of SCK until the slave select input goes high. If
SS goes high before the number of bits specified by the BITS field is transferred, the
QSPI resumes operation at the same pointer address the next time SS is asserted.
The maximum value that the BITS field can have is 16. If more than 16 bits are transmitted before SS is negated, pointers are incremented and operation continues. The
QSPI transmits as many bits as it receives at each queue address, until the BITS value is reached or SS is negated. SS does not need to go high between transfers as the
QSPI transfers data until reaching the end of the queue, whether SS remains low or is toggled between transfers.
When the QSPI reaches the end of the queue, it sets the SPIF flag. If the SPIFIE bit in SPCR2 is set, an interrupt request is generated when SPIF is asserted. At this point, the QSPI clears SPE and stops unless wraparound mode is enabled.
6.3.5.4 Slave Wraparound Mode
Slave wraparound mode is enabled by setting the WREN bit in SPCR2. The queue can wrap to pointer address $0 or to the address pointed to by NEWQP, depending on the state of the WRTO bit in SPCR2. Slave wraparound operation is identical to master wraparound operation.
6.3.6 Peripheral Chip Selects
Peripheral chip-select signals are used to select an external device for serial data transfer. Chip-select signals are asserted when a command in the queue is executed.
Signals are asserted at a logic level corresponding to the value of the PCS bits in the command. More than one chip-select signal can be asserted at a time, and more than one external device can be connected to each PCS pin, provided proper fanout is observed. PCS0 shares a pin with the slave select (SS) signal, which initiates slave mode serial transfer. If SS is taken low when the QSPI is in master mode, a mode fault occurs.
To set up a chip-select function, set the appropriate bit in PQSPAR, then configure the chip-select pin as an output by setting the appropriate bit in DDRQS. The value of the bit in PORTQS that corresponds to the chip-select pin determines the base state of the chip-select signal. If base state is zero, chip-select assertion must be active high
(PCS bit in command RAM must be set); if base state is one, assertion must be active low (PCS bit in command RAM must be cleared). PORTQS bits are cleared during reset. If no new data is written to PORTQS before pin assignment and configuration as an output, base state of chip-select signals is zero and chip-select pins are configured for active-high operation.
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6.4 Serial Communication Interface
The serial communication interface (SCI) communicates with external devices through an asynchronous serial bus. The SCI uses a standard nonreturn to zero (NRZ) transmission format. The SCI is fully compatible with other Freescale SCI systems, such as
those in M68HC11 and M68HC05 devices. Figure 6-7 is a block diagram of the SCI
transmitter; Figure 6-8 is a block diagram of the SCI receiver.
6.4.1 SCI Registers
The SCI programming model includes the QSM global and pin control registers, and four SCI registers. There are two SCI control registers (SCCR0 and SCCR1), one sta-
tus register (SCSR), and one data register (SCDR). Refer to APPENDIX D REGIS-
TER SUMMARY for register bit and field definition.
6.4.1.1 Control Registers
SCCR0 contains the baud rate selection field. Baud rate must be set before the SCI is enabled. The CPU can read and write this register at any time.
SCCR1 contains a number of SCI configuration parameters, including transmitter and receiver enable bits, interrupt enable bits, and operating mode enable bits. The CPU can read and write this register at any time. The SCI can modify the RWU bit under certain circumstances.
Changing the value of SCI control bits during a transfer operation may disrupt operation. Before changing register values, allow the SCI to complete the current transfer, then disable the receiver and transmitter.
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TRANSMITTER
BAUD RATE
CLOCK
SCDR Tx BUFFER
10 (11) - BIT
Tx SHIFT REGISTER
H (8) 7 6 5 4 3 2 1 0 L
(WRITE-ONLY)
MDDR7
MDDR5
PIN BUFFER
AND CONTROL
TxD
PARITY
GENERATOR
TRANSMITTER
CONTROL LOGIC
FORCE PIN
DIRECTION
(OUT)
6
15 SCCR1 (CONTROL REGISTER 1) 0 15 SCSR (STATUS REGISTER) 0
TDRE
TC
SCI Rx
REQUESTS
SCI INTERRUPT
REQUEST
Figure 6-7 SCI Transmitter Block Diagram
INTERNAL
DATA BUS
68300 SCI TX BLOCK
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RECEIVER
BAUD RATE
CLOCK
RxD PIN BUFFER
DATA
RECOVERY
÷
16
10 (11) - BIT
Rx SHIFT REGISTER
H
(8) 7 6 5 4 3 2 1 0
L
MSB ALL ONES
PARITY
DETECT
WAKEUP
LOGIC
6
15 SCCR1 (CONTROL REGISTER 1) 0
SCDR Rx BUFFER
(READ-ONLY)
15 SCSR (STATUS REGISTER) 0
SCI Tx
REQUESTS
SCI INTERRUPT
REQUEST
Figure 6-8 SCI Receiver Block Diagram
INTERNAL
DATA BUS
68300 SCI RX BLOCK
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6.4.1.2 Status Register
The SCI status register (SCSR) contains flags that show SCI operating conditions.
These flags are cleared either by SCI hardware or by a read/write sequence. In general, flags are cleared by reading the SCSR, then reading (receiver status bits) or writing (transmitter status bits) the SCDR. A long-word read can consecutively access both the SCSR and SCDR. This action clears receive status flag bits that were set at the time of the read, but does not clear TDRE or TC flags.
If an internal SCI signal for setting a status bit comes after the CPU has read the asserted status bits, but before the CPU has written or read the SCDR, the newly set status bit is not cleared. The SCSR must be read again with the bit set, and the SCDR must be written or read before the status bit is cleared.
Reading either byte of the SCSR causes all 16 bits to be accessed, and any status bit already set in either byte is cleared on a subsequent read or write of the SCDR.
6.4.1.3 Data Register
The SCDR contains two data registers at the same address. The RDR is a read-only register that contains data received by the SCI serial interface. The data comes into the receive serial shifter and is transferred to the RDR. The TDR is a write-only register that contains data to be transmitted. The data is first written to the TDR, then transferred to the transmit serial shifter, where additional format bits are added before transmission. R[7:0]/T[7:0] contain either the first eight data bits received when the SCDR is read, or the first eight data bits to be transmitted when the SCDR is written. R8/T8 are used when the SCI is configured for 9-bit operation. When it is configured for 8-bit operation, they have no meaning or effect.
6.4.2 SCI Pins
Two unidirectional pins, TXD (transmit data) and RXD (receive data), are associated with the SCI. TXD can be used by the SCI or for general-purpose I/O. Function is assigned by the port QS pin assignment register (PQSPAR). The receive data (RXD) pin
is dedicated to the SCI. Table 6-4 shows SCI pin function.
6
Pin Names
Receive Data
Transmit Data
Mnemonics
RXD
TXD
Table 6-4 SCI Pin Function
Mode
Receiver Disabled
Receiver Enabled
Transmitter Disabled
Transmitter Enabled
Function
Not Used
Serial Data Input to SCI
General-Purpose I/O
Serial Data Output from SCI
6.4.3 SCI Operation
SCI status flags in the SPSR support polled operation, or interrupt-driven operation can be employed by the interrupt enable bits in SCCR1.
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6.4.3.1 Definition of Terms
Bit-Time — The time required to transmit or receive one bit of data; one cycle of the baud frequency.
Start Bit — One bit-time of logic zero that indicates the beginning of a data frame. A start bit must begin with a one-to-zero transition and be preceded by at least three receive time (RT) samples of logic one.
Stop Bit — One bit-time of logic one that indicates the end of a data frame.
Frame — A complete unit of serial information. The SCI can use 10-bit or 11-bit frames.
Data Frame — A start bit, a specified number of data or information bits, and at least one stop bit.
Idle Frame — A frame that consists of consecutive ones. An idle frame has no start bit.
Break Frame — A frame that consists of consecutive zeros. A break frame has no stop bits.
6.4.3.2 Serial Formats
All data frames must have a start bit and at least one stop bit. Receiving and transmitting devices must use the same data frame format. The SCI provides hardware support for both ten-bit and eleven-bit frames. The serial mode (M) bit in SCI control register one (SCCR1) specifies the number of bits per frame.
The most common ten-bit data frame format for NRZ serial interface consists of one start bit, eight data bits (LSB first), and one stop bit. The most common eleven-bit data frame contains one start bit, eight data bits, a parity or control bit, and one stop bit.
Ten-bit and eleven-bit frames are shown in Table 6-5.
Start
1
1
1
Start
1
1
Table 6-5 Serial Frame Formats
Data
7
7
8
Data
7
8
10-Bit Frames
Parity/Control
—
1
—
11-Bit Frames
Parity/Control
1
1
Stop
2
1
1
Stop
2
1
6.4.3.3 Baud Clock
The SCI baud clock is programmed by writing a 13-bit value to the baud rate (SCBR) field in SCI control register zero (SCCR0). Baud clock is derived from the MCU system clock by a modulus counter. Writing a value of zero to SCBR disables the baud rate generator. Baud clock rate is calculated as follows:
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SCI Baud Clock Rate
=
System Clock
------------------------------------
32
×
SCBR where SCBR is in the range {1, 2, 3,..., 8191}.
The SCI receiver operates asynchronously. An internal clock is necessary to synchronize with an incoming data stream. The SCI baud clock generator produces a receive time (RT) sampling clock with a frequency 16 times that of the SCI baud clock. The
SCI determines the position of bit boundaries from transitions within the received waveform, and adjusts sampling points to the proper positions within the bit period.
6.4.3.4 Parity Checking
The parity type (PT) bit in SCCR1 selects either even (PT = 0) or odd (PT = 1) parity.
PT affects received and transmitted data. The parity enable (PE) bit in SCCR1 determines whether parity checking is enabled (PE = 1) or disabled (PE = 0). When PE is set, the MSB of the data in a frame is used for the parity function. For transmitted data, a parity bit is generated; for received data, the parity bit is checked. When parity checking is enabled, the parity flag (PF) in the SCI status register (SCSR) is set if a parity error is detected.
Enabling parity affects the number of data bits in a frame, which can in turn affect
frame size. Table 6-6 shows possible data and parity formats.
6
Table 6-6 Effect of Parity Checking on Data Size
M
0
0
1
1
PE
0
1
0
1
Result
8 Data Bits
7 Data Bits, 1 Parity Bit
9 Data Bits
8 Data Bits, 1 Parity Bit
6.4.3.5 Transmitter Operation
The transmitter consists of a serial shifter and a parallel data register (TDR) located in the SCI data register (SCDR). The serial shifter cannot be directly accessed by the
CPU. The transmitter is double-buffered, which means that data can be loaded into the TDR while other data is shifted out. The transmitter enable (TE) bit in SCCR1 enables (TE = 1) and disables (TE = 0) the transmitter.
Shifter output is connected to the TXD pin while the transmitter is operating (TE = 1, or TE = 0 and transmission in progress). Wired-OR operation should be specified when more than one transmitter is used on the same SCI bus. The wired-OR mode select bit (WOMS) in SCCR1 determines whether TXD is an open-drain (wired-OR) output or a normal CMOS output. An external pull-up resistor on the TXD pin is necessary for wired-OR operation. WOMS controls TXD function whether the pin is used for SCI transmissions (TE = 1) or as a general-purpose I/O pin.
Data to be transmitted is written to TDR, then transferred to the serial shifter. The transmit data register empty (TDRE) flag in SCSR shows the status of TDR. When
TDRE = 0, TDR contains data that has not been transferred to the shifter. Writing to
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TDR again overwrites the data. TDRE is set when the data in TDR is transferred to the shifter. Before new data can be written to TDR, however, the processor must clear
TDRE by writing to SCSR. If new data is written to TDR without first clearing TDRE, the data will not be transmitted.
The transmission complete (TC) flag in SCSR shows transmitter shifter state. When
TC = 0, the shifter is busy. TC is set when all shifting operations are completed. TC is not automatically cleared. The processor must clear it by first reading SCSR while TC is set, then writing new data to TDR.
The state of the serial shifter is checked when the TE bit is set. If TC = 1, an idle frame is transmitted as a preamble to the following data frame. If TC = 0, the current operation continues until the final bit in the frame is sent, then the preamble is transmitted.
The TC bit is set at the end of preamble transmission.
The send break (SBK) bit in SCCR1 is used to insert break frames in a transmission.
A nonzero integer number of break frames is transmitted while SBK is set. Break transmission begins when SBK is set, and ends with the transmission in progress at the time either SBK or TE are cleared. If SBK is set while a transmission is in progress, that transmission finishes normally before the break begins. To assure the minimum break time, toggle SBK quickly to one and back to zero. The TC bit is set at the end of break transmission. After break transmission, at least one bit-time of logic level one
(mark idle) is transmitted to ensure that a subsequent start bit can be detected.
If TE remains set, after all pending idle, data and break frames are shifted out, TDRE and TC are set and TXD is held at logic level one (mark).
When TE is cleared, the transmitter is disabled after all pending idle, data and break frames are transmitted. The TC flag is set, and the TXD pin reverts to control by PQS-
PAR and DDRQS. Buffered data is not transmitted after TE is cleared. To avoid losing data in the buffer, do not clear TE until TDRE is set.
Some serial communication systems require a mark on the TXD pin even when the transmitter is disabled. Configure the TXD pin as an output (DDRQS), then write a one to PORTQS bit 7. When the transmitter releases control of the TXD pin, it reverts to driving a logic one output.
To insert a delimiter between two messages, to place nonlistening receivers in wakeup mode between transmissions, or to signal a retransmission by forcing an idle line, clear and then set TE before data in the serial shifter has shifted out. The transmitter finishes the transmission, then sends a preamble. After the preamble is transmitted, if TDRE is set, the transmitter will mark idle. Otherwise, normal transmission of the next sequence will begin.
Both TDRE and TC have associated interrupts. The interrupts are enabled by the transmit interrupt enable (TIE) and transmission complete interrupt enable (TCIE) bits in SCCR1. Service routines can load the last byte of data in a sequence into the TDR, then terminate the transmission when a TDRE interrupt occurs.
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6.4.3.6 Receiver Operation
The receiver enable (RE) bit in SCCR1 enables (RE = 1) and disables (RE = 0) the transmitter. The receiver contains a receive serial shifter and a parallel receive data register (RDR) located in the SCI data register (SCDR). The serial shifter cannot be directly accessed by the CPU. The receiver is double-buffered, allowing data to be held in RDR while other data is shifted in.
Receiver bit processor logic drives a state machine that determines the logic level for each bit-time. This state machine controls when the bit processor logic is to sample the RXD pin and also controls when data is to be passed to the receive serial shifter.
A receive time (RT) clock is used to control sampling and synchronization. Data is shifted into the receive serial shifter according to the most recent synchronization of the RT clock with the incoming data stream. From this point on, data movement is synchronized with the MCU system clock. Operation of the receiver state machine is detailed in the QSM Reference Manual (QSMRM/AD).
The number of bits shifted in by the receiver depends on the serial format. However, all frames must end with at least one stop bit. When the stop bit is received, the frame is considered to be complete, and the received data in the serial shifter is transferred to the RDR. The receiver data register flag (RDRF) is set when the data is transferred.
Noise errors, parity errors, and framing errors can be detected while a data stream is being received. Although error conditions are detected as bits are received, the noise flag (NF), the parity flag (PF), and the framing error (FE) flag in SCSR are not set until data is transferred from the serial shifter to RDR.
RDRF must be cleared before the next transfer from the shifter can take place. If
RDRF is set when the shifter is full, transfers are inhibited and the overrun error (OR) flag in the SCSR is set. OR indicates that the CPU needs to service RDR faster. When
OR is set, the data in RDR is preserved, but the data in the serial shifter is lost. Because framing, noise, and parity errors are detected while data is in the serial shifter,
FE, NF, and PF cannot occur at the same time as OR.
When the CPU reads the SCSR and the SCDR in sequence, it acquires status and data, and also clears the status flags. Reading the SCSR acquires status and arms the clearing mechanism. Reading the SCDR acquires data and clears the SCSR.
When RIE in SCCR1 is set, an interrupt request is generated whenever RDRF is set.
Because receiver status flags are set at the same time as RDRF, they do not have separate interrupt enables.
6.4.3.7 Idle-Line Detection
During a typical serial transmission, frames are transmitted isochronously and no idle time occurs between frames. Even when all the data bits in a frame are logic ones, the start bit provides one logic zero bit-time during the frame. An idle line is a sequence of contiguous ones equal to the current frame size. Frame size is determined by the state of the M bit in SCCR1.
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The SCI receiver has both short and long idle-line detection capability. Idle-line detection is always enabled. The idle line type (ILT) bit in SCCR1 determines which type of detection is used. When an idle line condition is detected, the IDLE flag in SCSR is set.
For short idle-line detection, the receiver bit processor counts contiguous logic one bittimes whenever they occur. Short detection provides the earliest possible recognition of an idle line condition, because the stop bit and contiguous logic ones before and after it are counted. For long idle-line detection, the receiver counts logic ones after the stop bit is received. Only a complete idle frame causes the IDLE flag to be set.
In some applications, CPU overhead can cause a bit-time of logic level one to occur between frames. This bit-time does not affect content, but if it occurs after a frame of ones when short detection is enabled, the receiver flags an idle line.
When the idle line interrupt enable (ILIE) bit in SCCR1 is set, an interrupt request is generated when the IDLE flag is set. The flag is cleared by reading SCSR and SCDR in sequence. IDLE is not set again until after at least one frame has been received
(RDRF = 1). This prevents an extended idle interval from causing more than one interrupt.
6.4.3.8 Receiver Wakeup
The receiver wakeup function allows a transmitting device to direct a transmission to a single receiver or to a group of receivers by sending an address frame at the start of a message. Hardware activates each receiver in a system under certain conditions.
Resident software must process address information and enable or disable receiver operation.
A receiver is placed in wakeup mode by setting the receiver wakeup (RWU) bit in
SCCR1. While RWU is set, receiver status flags and interrupts are disabled. Although the CPU can clear RWU, it is normally cleared by hardware during wakeup.
The WAKE bit in SCCR1 determines which type of wakeup is used. When WAKE = 0, idle-line wakeup is selected. When WAKE = 1, address-mark wakeup is selected. Both types require a software-based device addressing and recognition scheme.
Idle-line wakeup allows a receiver to sleep until an idle line is detected. When an idleline is detected, the receiver clears RWU and wakes up. The receiver waits for the first frame of the next transmission. The byte is received normally, transferred to register
RDR, and the RDRF flag is set. If software does not recognize the address, it can set
RWU and put the receiver back to sleep. For idle-line wakeup to work, there must be a minimum of one frame of idle line between transmissions. There must be no idle time between frames within a transmission.
Address-mark wakeup uses a special frame format to wake up the receiver. When the
MSB of an address-mark frame is set, that frame contains address information. The first frame of each transmission must be an address frame. When the MSB of a frame is set, the receiver clears RWU and wakes up. The byte is received normally, transferred to register RDR, and the RDRF flag is set. If software does not recognize the address, it can set RWU and put the receiver back to sleep. Address-mark wakeup al-
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lows idle time between frames and eliminates idle time between transmissions. However, there is a loss of efficiency because of an additional bit-time per frame.
6.4.3.9 Internal Loop
The LOOPS bit in SCCR1 controls a feedback path on the data serial shifter. When
LOOPS is set, SCI transmitter output is fed back into the receive serial shifter. TXD is asserted (idle line). Both transmitter and receiver must be enabled before entering loop mode.
6.5 QSM Initialization
After reset, the QSM remains in an idle state until initialized. A general sequence guide for initialization follows.
A. Global
1. Configuration register (QSMCR) a. Write an interrupt arbitration priority value into the IARB field. b. Clear the FREEZE and/or STOP bits for normal operation.
2. Interrupt vector and interrupt level registers (QIVR and QILR) a. Write QSPI/SCI interrupt vector into QIVR. b. Write QSPI (ILSPI) and SCI (ILSCI) interrupt priorities into QILR.
3. Port data and data direction registers (PORTQS and DDRQS) a. Write a data word to PORTQS. b. Establish direction of QSM pins used for I/O by writing to DDRQS.
4. Assign pin functions by writing to the pin assignment register (PQSPAR)
B. Queued Serial Peripheral Interface
1. Write appropriate values to QSPI command RAM.
2. QSPI control register zero (SPCR0) a. Write a transfer rate value into the BR field. b. Determine clock phase (CPHA), and clock polarity (CPOL). c. Determine number of bits to be transferred in a serial operation (BIT).
d. Select master or slave operating mode (MSTR). e. Enable or disable wired-OR operation (WOMQ).
3. QSPI control register one (SPCR1) a. Establish a delay following serial transfer by writing to the DTL field. b. Establish a delay before serial transfer by writing to the DSCKL field.
4. QSPI control register two (SPCR2) a. Write an initial queue pointer value into the NEWQP field. b. Write a final queue pointer value into the ENDQP field. c. Enable or disable queue wraparound (WREN).
d. Write wraparound address into the WRTO field.
e. Enable or disable QSPI flag interrupt (SPIFIE).
5. QSPI control register three (SPCR3) a. Enable or disable halt at end of queue (HALT).
b. Enable or disable halt and mode fault interrupts (HMIE). c. Enable or disable loopback (LOOPQ).
6. To enable the QSPI, set the SPE bit in SPCR1.
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C. Serial Communication Interface (SCI)
1. SCI control register zero (SCCR0) a. Write a transfer rate (baud) value into the BR field.
2. SCI control register one (SCCR1) a. Select serial mode (M) b. Enable use (PE) and type (PT) of parity check. c. Select use (RWU) and type (WAKE) of receiver wakeup.
d. Enable idle-line detection (ILT) and interrupt (ILIE). e. Enable or disable wired-OR operation (WOMS). f.
Enable or disable break transmission (BK).
3. To receive a. Set the receiver (RE) and receiver interrupt (RIE) bits in SCCR1.
4. To transmit a. Set transmitter (TE) and transmitter interrupt (TIE). b. Clear the transmitter data register empty (TDRE) and transmit complete
(TC) indicators by reading the serial communication interface status register (SCSR). c. Write transmit data to the serial communication data register (SCDR).
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SECTION 7GENERAL-PURPOSE TIMER
This section is an overview of GPT function. Refer to the
GPT Reference Manual (GP-
TRM/AD) for complete information about the GPT module.
7.1 General
The 11-channel general-purpose timer (GPT) is used in systems where a moderate level of CPU control is required. The GPT consists of a capture/compare unit, a pulse accumulator, and two pulse-width modulators. A bus interface unit connects the GPT to the intermodule bus (IMB).
The capture/compare unit features three input capture channels, four output compare channels, and one channel that can be selected as an input capture or output compare channel. These channels share a 16-bit free-running counter which derives its clock from a nine-stage prescaler or from the external clock input signal, PCLK.
Pulse accumulator channel logic includes an 8-bit counter; the pulse accumulator can operate in either event counting mode or gated time accumulation mode.
Pulse-width modulator outputs are periodic waveforms whose duty cycles can be independently selected and modified by user software. The PWM circuits share a 16-bit free-running counter that can be clocked by the same nine-stage prescaler used by the capture/compare unit or by the PCLK input.
All GPT pins can also be used for general-purpose input/output. The input capture and output compare pins form a bidirectional 8-bit parallel port (PORTGP). PWM pins are outputs only. PAI and PCLK pins are inputs only.
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IC1/PGP0
IC2/PGP1
IC3/PGP2
CAPTURE/COMPARE UNIT
PULSE ACCUMULATOR
OC1/PGP3
OC2/OC1/PGP4
OC3/OC1/PGP5
OC4/OC1/PGP6
IC4/OC5/OC1/PGP7
PAI
PRESCALER PCLK
PWMA
PWMB
PWM UNIT
BUS INTERFACE
7
IMB
GPT BLOCK
Figure 7-1 GPT Block Diagram
7.2 GPT Registers and Address Map
The GPT programming model consists of a configuration register (GPTMCR), parallel
I/O registers (DDRGP, PORTGP), capture/compare registers (TCNT, TCTL1, TCTL2,
TIC[1:3], TOC[1:4], TI4/O5, CFORC), pulse accumulator registers (PACNT, PACTL), pulse-width modulation registers (PWMA, PWMB, PWMC, PWMCNT, PWMBUFA,
PWMBUFB), status registers (TFLG1, TFLG2) and interrupt control registers (TMSK1,
TMSK2). Functions of the module configuration register are discussed in 7.3 Special
Modes of Operation and 7.4 Polled and Interrupt-Driven Operation. Other register
functions are discussed in the appropriate sections.
All registers can be accessed using byte or word operations. Certain capture/compare registers and pulse-width modulation registers must be accessed by word operations to ensure coherency. If byte accesses are used to read a register such as the timer counter register (TCNT), there is a possibility that data in the byte not being accessed will change while the other byte is read. Both bytes must be accessed at the same time.
The modmap (MM) bit in the system integration module configuration register (SIM-
CR) defines the most significant bit (ADDR23) of the IMB address for each register in the MCU.
Refer to APPENDIX D REGISTER SUMMARY for a GPT address map and register
bit/field descriptions. SECTION 4 SYSTEM INTEGRATION MODULE contains more
information about how the state of MM affects the system.
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7.3 Special Modes of Operation
The GPT module configuration register (GPTMCR) module configuration register
(GPTMCR) is used to control special GPT operating modes. These include low-power stop mode, freeze mode, single-step mode, and test mode. Normal GPT operation can
be polled or interrupt-driven. Refer to 7.4 Polled and Interrupt-Driven Operation for
more information.
7.3.1 Low-Power Stop Mode
Low-power stop operation is initiated by setting the STOP bit in GPTMCR. In stop mode the system clock to the module is turned off. The clock remains off until STOP is negated or a reset occurs. All counters and prescalers within the timer stop counting while the STOP bit is set. Only the module configuration register (GPTMCR) and the interrupt configuration register (ICR) should be accessed while in the stop mode. Accesses to other GPT registers cause unpredictable behavior. Low-power stop can also be used to disable module operation during debugging.
7.3.2 Freeze Mode
The freeze (FRZ[1:0]) bits in GPTMCR are used to determine what action is taken by the GPT when the IMB FREEZE signal is asserted. FREEZE is asserted when the
CPU enters background debugging mode. At the present time, FRZ1 has no effect;
setting FRZ0 causes the GPT to enter freeze mode. Refer to SECTION 5 CENTRAL
PROCESSING UNIT for more information on background debugging mode.
Freeze mode freezes the current state of the timer. The prescaler and the pulse accumulator do not increment and changes to the pins are ignored (input pin synchronizers are not clocked). All of the other timer functions that are controlled by the CPU will operate normally; for example, registers can be written to change pin directions, force output compares, and read or write I/O pins.
While the FREEZE signal is asserted, the CPU has write access to registers and bits that are normally read-only, or write-once. The write-once bits can be written to as often as needed. The prescaler and the pulse accumulator remain stopped and the input pins are ignored until the FREEZE signal is negated (the CPU is no longer in BDM), the FRZ0 bit is cleared, or the MCU is reset.
Activities that are in progress prior to FREEZE assertion are completed. For example, if an input edge on an input capture pin is detected just as the FREEZE signal is asserted, the capture occurs and the corresponding interrupt flag is set.
7.3.3 Single-Step Mode
Two bits in GPTMCR support GPT debugging without using BDM. When the STOPP bit is asserted, the prescaler and the pulse accumulator stop counting and changes at input pins are ignored. Reads of the GPT pins return the state of the pin when STOPP was set. After STOPP is set, the INCP bit can be set to increment the prescaler and clock the input synchronizers once. The INCP bit is self-negating after the prescaler is incremented. INCP can be set repeatedly. The INCP bit has no effect when the
STOPP bit is not set.
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7.3.4 Test Mode
Test mode is used during Freescale factory testing. The GPT has no dedicated testmode control register; all GPT testing is done under control of the system integration module.
7.4 Polled and Interrupt-Driven Operation
Normal GPT function can be polled or interrupt-driven. All GPT functions have an associated status flag and an associated interrupt. The timer interrupt flag registers
(TFLG1 and TFLG2) contain status flags used for polled and interrupt-driven operation. The timer mask registers (TMSK1 and TMSK2) contain interrupt control bits. Control routines can monitor GPT operation by polling the status registers. When an event occurs, the control routine transfers control to a service routine that handles that event.
If interrupts are enabled for an event, the GPT requests interrupt service when the event occurs. Using interrupts does not require continuously polling the status flags to see if an event has taken place. However, status flags must be cleared after an interrupt is serviced, in order to disable the interrupt request.
7.4.1 Polled Operation
When an event occurs in the GPT, that event sets a status flag in TFLG1 or TFLG2.
The GPT sets the flags; they cannot be set by the CPU. TFLG1 and TFLG2 are 8-bit registers that can be accessed individually or as one 16-bit register. The registers are
initialized to zero at reset. Table 7-1 shows status flag assignment.
Table 7-1 GPT Status Flags
Flag
Mnemonic
IC1F
IC2F
IC3F
OC1F
OC2F
OC3F
OC4F
I4/O5F
TOF
PAOVF
PAIF
Register
Assignment
TFLG1
TFLG1
TFLG1
TFLG1
TFLG1
TFLG1
TFLG1
TFLG1
TFLG2
TFLG2
TFLG2
Source
Input Capture 1
Input Capture 2
Input Capture 3
Output Compare 1
Output Compare 2
Output Compare 3
Output Compare 4
Input Capture 4/Output Compare 5
Timer Overflow
Pulse Accumulator Overflow
Pulse Accumulator Input
For each bit in TFLG1 and TFLG2 there is a corresponding bit in TMSK1 and TMSK2 in the same bit position. If a mask bit is set and an associated event occurs, a hardware interrupt request is generated.
To re-enable a status flag after an event occurs, the status flags must be cleared. Status registers are cleared in a particular sequence. The register must first be read for set flags, then zeros must be written to the flags that are to be cleared. If a new event occurs between the time that the register is read and the time that it is written, the associated flag is not cleared.
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7.4.2 GPT Interrupts
The GPT has 11 internal sources that can cause it to request interrupt service (refer
to Table 7-2). Setting bits in TMSK1 and TMSK2 enables specific interrupt sources.
TMSK1 and TMSK2 are 8-bit registers that can be addressed individually or as one
16-bit register. The registers are initialized to zero at reset. For each bit in TMSK1 and
TMSK2 there is a corresponding bit in TFLG1 and TFLG2 in the same bit position.
TMSK2 also controls the operation of the timer prescaler. Refer to 7.7 Prescaler for
more information.
The value of the interrupt level (IRL) field in the interrupt control register (ICR) determines the priority of GPT interrupt requests. IRL values correspond to MCU interrupt request signals IRQ[7:1]. IRQ7 is the highest priority interrupt request signal; IRQ1 is the lowest-priority signal. A value of %111 causes IRQ7 to be asserted when a GPT interrupt request is made; lower field values cause corresponding lower-priority interrupt request signals to be asserted. Setting field value to %000 disables interrupts.
Table 7-2 GPT Interrupt Sources
Name
—
IC1
IC2
IC3
OC1
OC2
OC3
OC4
IC4/OC5
TO
PAOV
PAI
Source
Number
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
Source
Adjusted Channel
Input Capture 1
Input Capture 2
Input Capture 3
Output Compare 1
Output Compare 2
Output Compare 3
Output Compare 4
Input Capture 4/Output Compare 5
Timer Overflow
Pulse Accumulator Overflow
Pulse Accumulator Input
Vector
Number
IVBA : 0000
IVBA : 0001
IVBA : 0010
IVBA : 0011
IVBA : 0100
IVBA : 0101
IVBA : 0110
IVBA : 0111
IVBA : 1000
IVBA : 1001
IVBA : 1010
IVBA : 1011
The CPU32 recognizes only interrupt request signals of a priority greater than the status register interrupt priority (IP) mask value. When the CPU acknowledges an interrupt request, the priority of the acknowledged request is written to the IP mask and driven out on the IMB address lines.
When the IP mask value driven out on the address lines is the same as the IRL value, the GPT contends for arbitration priority. GPT arbitration priority is determined by the value of the IARB field in GPTMCR. Each MCU module that can make interrupt requests must be assigned a nonzero IARB value in order to implement an arbitration scheme. Arbitration is performed by means of serial assertion of IARB field bit values.
When the GPT wins interrupt arbitration, it responds to the CPU interrupt acknowledge cycle by placing an interrupt vector number on the data bus. The vector number is used to calculate displacement into the CPU32 exception vector table. Vector numbers are formed by concatenating the value in the ICR IVBA field with a 4-bit value supplied by the GPT when an interrupt request is made. Hardware prevents the vector number from changing while it is being driven out on the IMB. Vector number assign-
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At reset, IVBA is initialized to $0. To enable interrupt-driven timer operation, the upper nibble ($4–$F) of a user-defined vector number ($40–$FF) must be written to IVBA, and interrupt handler routines must be located at the addresses pointed to by the corresponding vector. Note that IVBA must be written before GPT interrupts are enabled, or the GPT could supply a vector number ($00 to $0F) that corresponds to an assigned or reserved exception vector.
The internal GPT interrupt priority hierarchy is shown in Table 7-2. The lower the in-
terrupt source number, the higher the priority. A single GPT interrupt source can be given priority over all other GPT interrupt sources by assigning the priority adjust field
(PAB) in the ICR a value equal to its source number.
Interrupt requests are asserted until associated status flags are cleared. Status flags must be cleared in a particular sequence. The status register must first be read for set flags, then zeros must be written to the flags that are to be cleared. If a new event occurs between the time that the register is read and the time that it is written, the associated flag is not cleared.
Refer to SECTION 5 CENTRAL PROCESSING UNIT and SECTION 4 SYSTEM IN-
TEGRATION MODULE for more information about exceptions and interrupts.
7.5 Pin Descriptions
The GPT uses 12 pins. Each pin can perform more than one function. Descriptions of
GPT pins divided into functional groups follow.
7.5.1 Input Capture Pins (IC[1:3])
Each of these pins is associated with a single GPT input capture function. Each pin has hysteresis. Any pulse longer than two system clocks is guaranteed to be valid and any pulse shorter than one system clock is ignored. Each pin has an associated 16-bit capture register that holds the captured counter value. These pins can also be used
for general-purpose I/O. Refer to 7.8.2 Input Capture Functions for more informa-
tion.
7.5.2 Input Capture/Output Compare Pin (IC4/OC5)
This pin can be configured for use by either an input capture or an output compare function. It has an associated 16-bit register that is used for holding either the input capture value or the output match value. When used for input capture the pin has the same hysteresis as other input capture pins. The pin can be used for general-purpose
I/O. Refer to 7.8.2 Input Capture Functions and 7.8.3 Output Compare Functions
for more information.
7.5.3 Output Compare Pins (OC[1:4])
These pins are used for GPT output compare functions. Each pin has an associated
16-bit compare register and a 16-bit comparator. Pins OC2, OC3, and OC4 are associated with a specific output compare function. The OC1 function can affect the output of all compare pins. If the OC1 pin is not needed for an output compare function it can
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be used to output the clock selected for the timer counter register. Any of these pins
can also be used for general-purpose I/O. Refer to 7.8.3 Output Compare Functions
for more information.
7.5.4 Pulse Accumulator Input Pin (PAI)
The PAI pin connects a discrete signal to the pulse accumulator for timed or gated pulse accumulation. PAI has hysteresis. Any pulse longer than two system clocks is guaranteed to be valid and any pulse shorter than one system clock is ignored. It can
be used as a general-purpose input pin. Refer to 7.10 Pulse Accumulator for more
information.
7.5.5 Pulse-Width Modulation (PWMA, PWMB)
PWMA and PWMB pins carry pulse-width modulator outputs. The modulators can be programmed to generate a periodic waveform of variable frequency and duty cycle.
PWMA can be used to output the clock selected as the input to the PWM counter.
These pins can also be used for general-purpose output. Refer to 7.11 Pulse-Width
Modulation Unit for more information.
7.5.6 Auxiliary Timer Clock Input (PCLK)
PCLK connects an external clock to the GPT. The external clock can be used as the clock source for the capture/compare unit or the PWM unit in place of one of the prescaler outputs. PCLK has hysteresis. Any pulse longer than two system clocks is guaranteed to be valid and any pulse shorter than one system clock is ignored. This pin
can also be used as a general-purpose input pin. Refer to 7.7 Prescaler for more in-
formation.
7.6 General-Purpose I/O
Any GPT pin can be used for general-purpose I/O when it is not used for another purpose. Capture/compare pins are bidirectional, others can be used only for output or input. I/O direction is controlled by a data direction bit in the port GP data direction register (DDRGP).
Parallel data is read from and written to the port GP data register (PORTGP). Pin data can be read even when pins are configured for a timer function. Data read from PORT-
GP always reflects the state of the external pin, while data written to PORTGP may not always affect the external pin.
Data written to PORTGP does not immediately affect pins used for output compare functions, but the data is latched. When an output compare function is disabled, the last data written to PORTGP is driven out on the associated pin if it is configured as an output. Data written to PORTGP can cause input captures if the corresponding pin is configured for input capture function.
The pulse accumulator input (PAI and the external clock input (PCLK) pins provide general-purpose input. The state of these pins can be read by accessing the PAIS and
PCLKS bits in the pulse accumulator control register (PACTL).
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Pulse-width modulation A and B (PWMA/PWMB) output pins can serve as generalpurpose outputs. The force PWM value (FPWMx) and the force logic one (F1x) bits in the compare force (CFORC) and PWM control (PWMC) registers, respectively, control their operation.
7.7 Prescaler
Capture/compare and PWM units have independent 16-bit free-running counters as a main timing component. These counters derive their clocks from the prescaler or from
the PCLK input. Figure 7-2 is a prescaler block diagram.
In the prescaler, the system clock is divided by a nine-stage divider chain. Prescaler outputs equal to system clock divided by 2, 4, 8, 16, 32, 64, 128, 256 and 512 are provided. Connected to these outputs are two multiplexers, one for the capture/compare unit, the other for the PWM unit.
Multiplexers can each select one of seven prescaler taps or an external input from the
PCLK pin. Multiplexer output for the timer counter (TCNT) is selected by bits CPR[2:0] in timer interrupt mask register 2 (TMSK2). Multiplexer output for the PWM counter
(PWMCNT) is selected by bits PPR[2:0] in PWM control register C (PWMC).
After reset, the GPT is configured to use system clock divided by four for TCNT and system clock divided by two for PWMCNT. Initialization software can change the division factor. The PPR bits can be written at any time but the CPR bits can only be written once after reset unless the GPT is in test or freeze mode.
The prescaler can be read at any time. In freeze mode the prescaler can also be written. Word accesses must be used to ensure coherency. If coherency is not needed byte accesses can be used. The prescaler value is contained in bits [8:0] while bits
[15:9] are unimplemented and are read as zeros.
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SYSTEM CLOCK
DIVIDER
÷
512
EXT.
TO PULSE ACCUMULATOR
TO PULSE ACCUMULATOR
TO PULSE ACCUMULATOR
CPR2 CPR1 CPR0
÷
256
÷
128
÷
64
÷
32
÷
16
÷
8
÷
4
EXT.
SELECT
TO CAPTURE/
COMPARE
TIMER
PCLK
PIN
÷
128
÷
64
÷
32
÷
16
÷
8
÷
4
÷
2
EXT.
SELECT
TO
PWM UNIT
SYNCHRONIZER AND
DIGITAL FILTER
PPR2 PPR1 PPR0
Figure 7-2 Prescaler Block Diagram
GPT PRESCALER BLOCK
Multiplexer outputs (including the PCLK signal) can be connected to external pins) can be connected to external pins. The CPROUT bit in the TMSK2 register configures the
OC1 pin to output the TCNT clock and the PPROUT bit in the PWMC register configures the PWMA pin to output the PWMC clock. CPROUT and PPROUT can be written at any time. Clock signals on OC1 and PWMA do not have a 50% duty cycle. They have the period of the selected clock but are high for only one system clock time.
The prescaler also supplies three clock signals to the pulse accumulator clock select mux. These are the system clock divided by 512, the external clock signal from the
PCLK pin and the capture/compare clock signal.
7.8 Capture/Compare Unit
The capture/compare unit contains the timer counter (TCNT), the input capture (IC)
functions and the output compare (OC) functions. Figure 7-3 is a block diagram of the
capture/compare unit.
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7
PCLK
SYSTEM
CLOCK
7-10
PRESCALER–DIVIDE BY
4, 8, 16, 32, 64, 128, OR 256
1 OF 8 SELECT
CPR2 CPR1 CPR0
16-BIT TIMER BUS
TFLG1
IC1F
TCNT (HI) TCNT (LO)
16-BIT FREE-RUNNING
COUNTER
TOI
TOF
TMSK1
IC1I
9
INTERRUPT
REQUESTS
1
BIT-0
PIN
FUNCTIONS
PGP0
IC1
16-BIT LATCH CLK
TIC1 (HI) TIC1 (LO)
IC2I
2
16-BIT LATCH CLK
TIC2 (HI) TIC2 (LO)
IC2F
BIT-1
PGP1
IC2
IC3I
3
16-BIT LATCH CLK
TIC3 (HI) TIC3 (LO)
IC3F
BIT-2
PGP2
IC3
OC1I
4
CFORC
16-BIT COMPARATOR =
TOC1 (HI) TOC1 (LO)
OC1F
FOC1
BIT-3
PGP3
OC1
OC2I
5
16-BIT COMPARATOR =
TOC2 (HI) TOC2 (LO)
OC2F
FOC2
BIT-4
PGP4
OC2/
OC1
OC3I
6
16-BIT COMPARATOR =
TOC3 (HI) TOC3 (LO)
OC3F
FOC3
BIT-5
PGP5
OC3/
OC1
OC4I
7
16-BIT COMPARATOR =
TOC4 (HI) TOC4 (LO)
OC4F
FOC4
BIT-6
PGP6
OC4/
OC1
I4/O5I
8
16-BIT COMPARATOR =
TI4/O5 (HI) TI4/O5 (LO)
16-BIT LATCH CLK
OC5
I4/O5F
IC4
I4/O5
STATUS
FLAGS
FOC5
FORCE
OUTPUT
COMPARE
INTERRUPT
ENABLES
BIT-7
PGP7
IC4/
OC5/
OC1
PARALLEL
PORT PIN
CONTROL
16/32 CC BLOCK
Figure 7-3 Capture/Compare Unit Block Diagram
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7.8.1 Timer Counter
The timer counter (TCNT) is the key timing component in the capture/compare unit.
The timer counter is a 16-bit free-running counter that starts counting after the processor comes out of reset. The counter cannot be stopped during normal operation. After reset, the GPT is configured to use the system clock divided by four as the input to the counter. The prescaler divides the system clock and provides selectable input frequencies. User software can configure the system to use one of seven prescaler outputs or an external clock.
The counter can be read any time without affecting its value. Because the GPT is interfaced to the IMB and the IMB supports a 16-bit bus, a word read gives a coherent value. If coherency is not needed, byte accesses can be made. The counter is set to
$0000 during reset and is normally a read-only register. In test mode and freeze mode, any value can be written to the timer counter.
When the counter rolls over from $FFFF to $0000, the timer overflow flag (TOF) in timer interrupt flag register 2 (TFLG2) is set. An interrupt can be enabled by setting the corresponding interrupt enable bit (TOI) in timer interrupt mask register 2 (TMSK2).
Refer to 7.4.2 GPT Interrupts for more information.
7.8.2 Input Capture Functions
All GPT input capture functions use the same 16-bit timer counter (TCNT). Each input capture pin has a dedicated 16-bit latch and input edge-detection/selection logic. Each input capture function has an associated status flag, and can cause the GPT to make an interrupt service request.
When a selected edge transition occurs on an input capture pin, the associated 16-bit latch captures the content of TCNT and sets the appropriate status flag. An interrupt request can be generated when the transition is detected.
Edge-detection logic consists of control bits that enable edge detection and select a transition to detect. The EDGxA and EDGxB bits in timer control register 2 (TCTL2) determine whether the input capture functions detect rising edges only, falling edges only, or both rising and falling edges. Clearing both bits disables the input capture function. Input capture functions operate independently of each other and can capture the same TCNT value if individual input edges are detected within the same timer count cycle.
Input capture interrupt logic includes a status flag, which indicates that an edge has been detected, and an interrupt enable bit. An input capture event sets the ICxF bit in the timer interrupt flag register 1 (TFLG1) and causes the GPT to make an interrupt request if the corresponding ICxI bit is set in the timer interrupt mask register 1
(TMSK1). If the ICxI bit cleared, software must poll the status flag to determine that an
event has occurred. Refer to 7.4 Polled and Interrupt-Driven Operation for more in-
formation.
Input capture events are generally asynchronous to the timer counter. Because of this, input capture signals are conditioned by a synchronizer and digital filter. Events are
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synchronized with the system clock so that latching of TCNT content and counter incrementation occur on opposite half-cycles of the system clock. Inputs have hysteresis. Capture of any transition longer than two system clocks is guaranteed; any transition shorter than one system clock has no effect.
Figure 7-4 shows the relationship of system clock to synchronizer output. The value
latched into the capture register is the value of the counter several system clock cycles after the transition that triggers the edge detection logic. There can be up to one clock cycle of uncertainty in latching of the input transition. Maximum time is determined by the system clock frequency.
The input capture register is a 16-bit register. A word access is required to ensure coherency. If coherency is not required, byte accesses can be used to read the register.
Input capture registers can be read at any time without affecting their values.
7
F
SYS
(PH1)
CAPTURE/COMPARE
CLOCK
TCNT
EXTERNAL PIN
SYNCHRONIZER
OUTPUT
CAPTURE REGISTER
$0101 $0102
$0102
ICF FLAG
1153A
Figure 7-4 Input Capture Timing Example
7-12
An input capture occurs every time a selected edge is detected, even when the input capture status flag is set. This means that the value read from the input capture register corresponds to the most recent edge detected, which may not be the edge that caused the status flag to be set.
7.8.3 Output Compare Functions
Each GPT output compare pin has an associated 16-bit compare register and a 16-bit comparator. Each output compare function has an associated status flag, and can cause the GPT to make an interrupt service request. Output compare logic is designed to prevent false compares during data transition times.
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When the programmed content of an output compare register matches the value in
TCNT, an output compare status flag (OCxF) bit in TFLG1 is set. If the appropriate interrupt enable bit (OCxI) in TMSK1 is set, an interrupt request is made when a match
occurs. Refer to 7.4.2 GPT Interrupts for more information.
Operation of output compare 1 differs from that of the other output compare functions.
OC1 control logic can be programmed to make state changes on other OC pins when an OC1 match occurs. Control bits in the timer compare force register (CFORC) allow for early forced compares.
7.8.3.1 Output Compare 1
Output compare 1 can affect any or all of OC[1:5] when an output match occurs. In addition to allowing generation of multiple control signals from a single comparison operation, this function makes it possible for two or more output compare functions to control the state of a single OC pin. Output pulses as short as one timer count can be generated in this way.
The OC1 action mask register (OC1M) and the OC1 action data register (OC1D) control OC1 function. Setting a bit in OC1M selects a corresponding bit in the GPT parallel data port. Bits in OC1D determine whether selected bits are to be set or cleared when an OC1 match occurs. Pins must be configured as outputs in order for the data in the register to be driven out on the corresponding pin. If an OC1 match and another output match occur at the same time and both attempt to alter the same pin, the OC1 function controls the state of the pin.
7.8.3.2 Forced Output Compare
Timer compare force register (CFORC) is used to make forced compares. The action taken as a result of a forced compare is the same as when an output compare match occurs, except that status flags are not set. Forced channels take programmed actions immediately after the write to CFORC.
The CFORC register is implemented as the upper byte of a 16-bit register which also contains the PWM control register C (PWMC). It can be accessed as eight bits or a word access can be used. Reads of force compare bits (FOC) have no meaning and always return zeros. These bits are self-negating.
7.9 Input Capture 4/Output Compare 5
The IC4/OC5 pin can be used for input capture, output compare, or general-purpose
I/O. A function enable bit (I4/O5) in the pulse accumulator control register (PACTL) configures the pin for input capture (IC4) or output compare function (OC5). Both bits are cleared during reset, configuring the pin as an input, but also enabling the OC5 function. IC4/OC5 I/O functions are controlled by the I4/O5 bit in the port GP data direction register (DDRGP).
The 16-bit register (TI4/O5) used with the IC4/OC5 function acts as an input capture register or as an output compare register depending on which function is selected.
When used as the input capture 4 register, it cannot be written except in test or freeze mode.
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7.10 Pulse Accumulator
The pulse accumulator counter (PACNT) is an 8-bit read/write up-counter. PACNT can
operate in external event counting or gated time accumulation modes. Figure 7-5 is a
block diagram of the pulse accumulator.
In event counting mode, the counter increments each time a selected transition of the pulse accumulator input (PAI) pin is detected. The maximum clocking rate is the system clock divided by four.
In gated time accumulation mode a clock increments PACNT while the PAI pin is in the active state. There are four possible clock sources.
Two bits in the TFLG2 register show pulse accumulator status. The pulse accumulator flag (PAIF) indicates that a selected edge has been detected at the PAI pin. The pulse accumulator overflow flag (PAOVF) indicates that the pulse accumulator count has rolled over from $FF to $00. This can be used to extend the range of the counter beyond eight bits.
An interrupt request can be made when each of the status flags is set. However, operation of the PAI interrupt depends on operating mode. In event counting mode, an interrupt is requested when the edge being counted is detected. In gated mode, the request is made when the PAI input changes from active to inactive state. Interrupt requests are enabled by the PAOVI and PAII bits in the TMSK2 register.
Bits in the pulse accumulator control register (PACTL) control the operation of PACNT.
The PAMOD bit selects event counting or gated operation. In event counting mode, the PEDGE control bit determines whether a rising or falling edge is detected; in gated mode, PEDGE specifies the active state of the gate signal. Bits PACLK[1:0] select the clock source used in gated mode.
PACTL and PACNT are implemented as one 16-bit register, but can be accessed with byte or word access cycles. Both registers are cleared at reset, but the PAIS and
PCLKS bits show the state of the PAI and PCLK pins.
The PAI pin can also be used for general-purpose input. The logic state of the PAIS bit in PACTL shows the state of the pin.
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10
INTERRUPT
REQUESTS
11
TMSK2 TFLG2
PAI
SYNCHRONIZER
&
DIGITAL FILTER
EDGE
DETECT
LOGIC
2:1
MUX
OVERFLOW
PACNT
8-BIT COUNTER
ENABLE
PACTL
INTERNAL
DATA BUS
PCLK
TCNT OVERFLOW
CAPTURE/COMPARE CLK
PRESCALER
÷
512
MUX
16/32 PLS ACC BLOCK
Figure 7-5 Pulse Accumulator Block Diagram
7.11 Pulse-Width Modulation Unit
The pulse-width modulation (PWM) unit has two output channels, PWMA and PWMB.
A single clock output from the prescaler multiplexer drives a 16-bit counter that is used
to control both channels. Figure 7-6 is a block diagram of the pulse-width modulation
unit.
The PWM unit has two operational modes. Fast mode uses a clocking rate equal to 1/
256 of the prescaler output rate; slow mode uses a rate equal to 1/32768 of the prescaler output rate. The duty cycle ratios of the two PWM channels can be individually controlled by software. The PWMA pin can also output the clock that drives the PWM counter. PWM pins can also be used as output pins.
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16-BIT DATA BUS
PWMA REGISTER PWMB REGISTER
7
PWMA
PIN
F1A
BIT
R
LATCH
S
ZERO DETECTOR
PWMBUFA REGISTER PWMBUFB REGISTER
COMPARATOR A COMPARATOR B
R
LATCH
S
ZERO DETECTOR
PWMB
PIN
F1B
BIT
SFA
BIT
MULTIPLEXER A MULTIPLEXER B
SFB
BIT
16-BIT COUNTER
16-BIT TIMER BUS
FROM
PRESCALER
16/32 PWM BLOCK
Figure 7-6 PWM Block Diagram
7.11.1 PWM Counter
The 16-bit counter in the PWM unit is similar to the timer counter in the capture/compare unit. During reset, the GPT is configured to use the system clock divided by two to drive the counter. Initialization software can reconfigure the counter to use one of seven prescaler outputs or an external clock input from the PCLK pin.
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The PWM count register (PWMCNT) can be read at any time without affecting its value. A read must be a word access to ensure coherence, but byte accesses can be made if coherence is not needed. The counter is cleared to $0000 during reset and is a read-only register except in freeze or test mode.
Fifteen of the sixteen counter bits are output to multiplexers A and B. The multiplexers provide the fast and slow modes of the PWM unit. Mode for PWMA is selected by the
SFA bit in the PWM control register C (PWMC). Mode for PWMB is selected by the
SFB bit in the same register.
PWMA, PWMB, and PPR[2:0] bits in PWMC control PWM output frequency. In fast mode, bits [7:0] of PWMCNT are used to clock the PWM logic; in slow mode, bits [14:7] are used. The period of a PWM output in is 128 times longer than the fast mode period.
Table 7-3 shows a range of PWM output frequencies using a 16.78-MHz system clock
and 20.97-MHz system clock.
Table 7-3 PWM Frequency Ranges
Using 16.78-MHz/20.97-MHz System Clocks
PPR Prescaler Tap
[2:0] 16.78 MHz
20.97 MHz
000 Div 2 = 8.39 MHz Div 2 = 10.5 MHz
001 Div 4 = 4.19 MHz Div 4 = 5.25 MHz
SFA/B = 0
16.78 MHz
32.8 kHz
16.4 kHz
20.97 MHz
41 kHz
20.5 kHz
010 Div 8 = 2.10 MHz Div 8 = 2.62 MHz 8.19 kHz
011 Div 16 = 1.05 MHz Div 16 = 1.31 MHz 4.09 kHz
100 Div 32 = 524 kHz Div 32 = 655 kHz
101 Div 64 = 262 kHz Div 64 = 328 kHz
2.05 kHz
1.02 kHz
110 Div 128 = 131 kHz Div 128 = 164 kHz
111 PCLK PCLK
512 Hz
PCLK/256
10.2 kHz
5.15 kHz
2.56 kHz
1.28 kHz
SFA/B = 1
16.78 MHz 20.97 MHz
256 Hz 320 Hz
128 Hz
64.0 Hz
32.0 Hz
16.0 Hz
8.0 Hz
160 Hz
80.0 Hz
40.0 Hz
20.0 Hz
10.0 Hz
641 Hz 4.0 Hz 5.0 Hz
PCLK/256 PCLK/32768 PCLK/32768
7.11.2 PWM Function
The pulse width values of the PWM outputs are determined by control registers PWMA and PWMB. PWMA and PWMB are 8-bit registers implemented as two bytes of a 16bit register. PWMA and PWMB can be accessed as separate bytes or as one 16-bit register. A value of $00 loaded into either register causes the corresponding output pin to output a continuous logic level zero signal. A value of $80 causes the corresponding output signal to have a 50% duty cycle, and so on, to the maximum value of $FF, which corresponds to an output which is at logic level one for 255/256 of the cycle.
Setting the F1A (for PWMA) or F1B (for PWMB) bits in the register causes the corresponding pin to output a continuous logic level one signal. The logic level of the associated pin does not change until the end of the current cycle. F1A and F1B are the lower two bits of CFORC, but can be accessed at the same word address as PWMC.
Data written to PWMA and PWMB is not used until the end of a complete cycle. This prevents spurious short or long pulses when register values are changed. The current duty cycle value is stored in the appropriate PWM buffer register (PWMBUFA or PW-
MBUFB). The new value is transferred from the PWM register to the buffer register at the end of the current cycle.
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Registers PWMA, PWMB, and PWMC are reset to $00 during reset. These registers may be written or read at any time. PWMC is implemented as the lower byte of a 16bit register. The upper byte is the CFORC register. The buffer registers, PWMBUFA and PWMBUFB, are read-only at all times and may be accessed as separate bytes or as one 16-bit register.
Pins PWMA and PWMB can also be used for general-purpose output. The values of the F1A and F1B bits in PWMC are driven out on the corresponding PWM pins when normal PWM operation is disabled. When read, the F1A and F1B bits reflect the states of the PWMA and PWMB pins.
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APPENDIX A ELECTRICAL CHARACTERISTICS
This appendix contains electrical specification tables and reference timing diagrams.
Table A-1 Maximum Ratings
Num
1
2
3
Supply Voltage
1,2 , 7
Input Voltage
Rating
1, 2, 3, 5, 7
Instantaneous Maximum Current
Symbol
V
DD
V in
I
D
Value
–0.3 to +6.5
–0.3 to +6.5
25
Unit
V
V mA
4
5
Single pin limit (applies to all pins)
1, 5, 6, 7
Operating Maximum Current
Digital Input Disruptive Current
4,5,6,7,8
V
V
NEGCLMAP
≅
– 0.3 V
POSCLAMP
≅
V
DD
+ 0.3
Operating Temperature Range
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MC68331 “V” Suffix
MC68331 “M” Suffix
Storage Temperature Range
I
T
ID
A
–500 to 500
T
L
to T
0 to 70
H
–40 to 85
–40 to 105
–40 to 125
–55 to 150
µ
°
A
C
6 T stg
°
C
1. Permanent damage can occur if maximum ratings are exceeded. Exposure to voltages or currents in excess of recommended values affects device reliability. Device modules may not operate normally while being exposed to electrical extremes.
2. Although sections of the device contain circuitry to protect against damage from high static voltages or electrical fields, take normal precautions to avoid exposure to voltages higher than maximum-rated voltages.
3. All pins except
TSTME
/TSC
4. All functional non-supply pins are internally clamped to V
SS
TAL and XFC are internally clamped to V
DD
.
. All functional pins except EX-
5. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.
6. Power supply must maintain regulation within operating V
DD
range during instantaneous and operating maximum current conditions.
7. This parameter is periodically sampled rather than 100% tested.
8. Total input current for all digital input-only and all digital input/output pins must not exceed
10 mA. Exceeding this limit can cause disruption of normal operation.
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Table A-2 Typical Ratings, 16.78 MHz Operation
Num
1 Supply Voltage
Rating
2 Operating Temperature
3 V
DD
Supply Current
RUN
LPSTOP, VCO off
LPSTOP, External clock, maxi f sys
4 Clock Synthesizer Operating Voltage
5 V
DDSYN
Supply Current
VCO on, maximum f sys
External Clock, maximum f sys
LPSTOP, VCO off
V
DD
powered down
6 Power Dissipation
Symbol
V
DD
T
A
I
DD
V
DDSYN
I
DDSYN
P
D
Value
5.0
25
75
125
3
5.0
1.0
4.0
100
50
455
Unit
V
°
C mA
µ
A mA
V mA mA
µ
A
µ
A mW
Table A-2a Typical Ratings, 20.97 MHz Operation
Num
1 Supply Voltage
Rating
2 Operating Temperature
3 V
DD
Supply Current
RUN
LPSTOP, VCO off
LPSTOP, External clock, maxi f sys
4 Clock Synthesizer Operating Voltage
5 V
DDSYN
Supply Current
VCO on, maximum f sys
External Clock, maximum f sys
LPSTOP, VCO off
V
DD
powered down
6 Power Dissipation
Symbol
V
DD
T
A
I
DD
V
DDSYN
I
DDSYN
P
D
Value
5.0
25
113
125
3.75
5.0
1.0
5.0
100
50
570
Unit
V
°
C mA
µ
A
µ
A
V mA mA
µ
A
µ
A mW
A-2
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Table A-3 Thermal Characteristics
Num
Rating
1 Thermal Resistance
Plastic 132-Pin Surface Mount
Plastic 144-Pin Surface Mount
Thin Plastic 144-Pin Surface Mount
Symbol
Θ
ϑΑ
Value
°
Unit
C/W
38
46
49
NOTES:
The average chip-junction temperature (T
T
J
= T
J
) in C can be obtained from:
A
+ (P
D
× Θ
ϑΑ
) where
(1)
T
A
Θ
ϑΑ
P
D
P
INT
= Package Thermal Resistance, Junction-to-Ambient,
= P
= I
+ P
V
I/O
, Watts — Chip Internal Power
°
C/W
P
I/O
= Power Dissipation on Input and Output Pins — User Determined
For most applications P
I/O
< P
INT
and can be neglected. An approximate relationship between P
D
and
T
J
(if P
I/O
is neglected) is:
P
D
= K
÷
(T
J
+ 273
°
C) (2)
Solving equations 1 and 2 for K gives:
K = P
D
+ (T
A
+ 273
°
C) +
Θ
ϑΑ
×
P
D
2
(3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring P
D
(at equilibrium) for a known T
A
. Using this value of K, the values of P
D
and T
J
can be obtained by solving equations (1) and (2) iteratively for any value of T
A
.
Table A-4 16.78 MHz Clock Control Timing
(V
DD and V
DDSYN
= 5.0 Vdc
±
10%, V
SS
= 0 Vdc, T
A
= T
L
32.768 kHz reference) to T
H,
Num Characteristic
1 PLL Reference Frequency Range
2 System Frequency
1
On-Chip PLL System Frequency
External Clock Operation
3 PLL Lock Time
2,3,4,5
4 VCO Frequency
6
5 Limp Mode Clock Frequency
SYNCR X bit = 0
SYNCR X bit = 1
6 CLKOUT Stability
2,3,4,7
Short term (5
µ s interval)
Long term (500
µ s interval)
Symbol
f ref f sys t lpll f
VCO f limp
C stab
Min
25 dc
0.131
dc
—
—
—
–0.5
–0.05
Max
50
16.78
16.78
Unit
kHz
MHz
16.78
20 ms
2 (f sys max) MHz
MHz f sys max/2 f sys max
%
0.5
0.05
A
MC68331
USER’S MANUAL
ELECTRICAL CHARACTERISTICS
For More Information On This Product,
Go to: www.freescale.com
A-3
A
Freescale Semiconductor, Inc.
Table A-4a 20.97 MHz Clock Control Timing
(V
DD and V
DDSYN
= 5.0 Vdc
±
5%, V
SS
= 0 Vdc, T
32.768 kHz reference)
A
= T
L to T
H,
Num Characteristic
1 PLL Reference Frequency Range
2 System Frequency
1
On-Chip PLL System Frequency
External Clock Operation
3 PLL Lock Time
2,3,4,5
4 VCO Frequency
6
5 Limp Mode Clock Frequency
SYNCR X bit = 0
SYNCR X bit = 1
6 CLKOUT Stability
2,3,4,7
Short term (5
µ s interval)
Long term (500
µ s interval)
Symbol
f f
C f f t ref sys lpll
VCO limp stab
Min
25 dc
0.131
dc
—
—
—
—
Max
50
20.97
20.97
Unit
kHz
MHz
20.97
20 ms
2 (f sys max) MHz
MHz f sys max/2 f sys max
%
0.5
0.05
–0.5
–0.05
Notes for Tables A–4 and A–4a
1. All internal registers retain data at 0 Hz
2 This parameter is periodically sampled rather than 100% tested.
3. Assumes that a low-leakage external filter network is used to condition clock synthesizer input voltage. Total external resistance from the XFC pin due to external leakage must be greater than 15 M
∫
to guarantee this
specification. Filter network geometry can vary depending upon operating environment (See 4.3 System
4. Proper layout procedures must be followed to achieve specifications.
5. Assumes that stable V
DDSYN is applied, and that the crystal oscillator is stable.
Lock time is measured from the time V
DD
and V
DDSYN
are valid until RESET is released. This specification also applies to the period required for PLL lock after changing the W and Y frequency control bits in the synthesizer control register
(SYNCR) while the PLL is running, and to the period required for the clock to lock after LPSTOP.
6. Internal VCO frequency (f
VCO
) is determined by SYNCR W and Y bit values. The SYNCR X bit controls a divide-by-two circuit that is not in the synthesizer feedback loop. When X = 0, the divider is enabled, and f sys
= f
VCO
÷
4. When X = 1, the divider is disabled, and f sys
= f
VCO
÷
2. X must equal one when operating at maximum specified f sys
.
7. Stability is the average deviation from the programmed frequency measured over the specified interval at maximum f sys
. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via V oscillator frequency increase the C stab
DDSYN
and V
SS
and variation in crystal
percentage for a given interval. When clock stability is a critical constraint on control system operation, this parameter should be measured during functional testing of the final system.
A-4
ELECTRICAL CHARACTERISTICS
For More Information On This Product,
Go to: www.freescale.com
MC68331
USER’S MANUAL
Freescale Semiconductor, Inc.
Table A-5 16.78 MHz DC Characteristics
(V
DD and V
DDSYN
= 5.0 Vdc
±
10%, V
SS
= 0 Vdc, T
A
= T
L to T
H
)
Num
1 Input High Voltage
Characteristic
2 Input Low Voltage
3 Input Hysteresis
1
4 Input Leakage Current
2
V in
= V
DD or V
SS
5 High Impedance (Off-State) Leakage Current
2
Input-only pins
V in
= V
DD
or V
SS
All input/output and output pins
6 CMOS Output High Voltage
2, 3
I
OH
= –10.0
µ
A Group 1, 2, 4 input/output and all output pins
7 CMOS Output Low Voltage
2
I
OL
= 10.0
µ
A Group 1, 2, 4 input/output and all output pins
8 Output High Voltage
2, 3
I
OH
= –0.8 mA
9 Output Low Voltage
2
Group 1, 2, 4 input/output and all output pins
I
OL
I
OL
I
OL
= 1.6 mA Group 1 I/O Pins, CLKOUT, FREEZE/QUOT, IPIPE
= 5.3 mA
= 12 mA
Group 2 and Group 4 I/O Pins, CSBOOT, BG/CS
Group 3
Symbol
V
IH
V
IL
V
HYS
I in
I
V
V
V
V
OZ
OH
OL
OH
OL
10 Three State Control Input High Voltage
11 Data Bus Mode Select Pull-up Current
5
V in
= V
IL
V in
= V
IH
12 V
DD
Supply Current
6
RUN
4
DATA[15:0]
DATA[15:0]
LPSTOP, 32.768 kHz crystal, VCO Off (STSIM = 0)
LPSTOP (External clock input frequency = maximum f sys
)
13 Clock Synthesizer Operating Voltage
14 V
DDSYN
Supply Current
6
32.768 kHz crystal, VCO on, maximum f sys
External Clock, maximum f sys
LPSTOP, 32.768 kHz crystal, VCO off (STSIM = 0)
32.768 kHz crystal, V
DD powered down
15 Power Dissipation
8
16 Input Capacitance
2, 9
All input-only pins
All input/output pins
17 Load Capacitance
2
Group 1 I/O Pins and CLKOUT, FREEZE/QUOT, IPIPE
Group 2 I/O Pins and CSBOOT, BG/CS
Group 3 I/O pins
Group 4 I/O pins
V
V
I
IHTSC
MSP
I
DD
S
IDD
S
IDD
DDSYN
I
DDSYN
I
DDSYN
S
IDDSYN
I
DDSYN
P
D
C in
C
L
Min Max
0.7
(
V
DD
) V
DD
+ 0.3
V
SS
– 0.3
0.2
(
V
DD
)
0.5
—
–2.5
2.5
–2.5
V
DD
– 0.2
—
V
DD
– 0.8
—
—
—
1.6 (V
DD
)
—
–15
—
—
—
—
—
—
—
—
—
—
4.5
—
—
—
—
2.5
—
0.2
—
0.4
0.4
0.4
9.1
–120
—
124
350
5
5.5
1
5
150
100
690
10
20
90
100
130
200
Unit
V
V
V
µ
A
µ
A
V
V
V
V
V
µ
A mA
µ
A mA
V pF mA mA
µ
A
µ
A mW pF
A
MC68331
USER’S MANUAL
ELECTRICAL CHARACTERISTICS
For More Information On This Product,
Go to: www.freescale.com
A-5
Freescale Semiconductor, Inc.
A
Table A-5a 20.97 MHz DC Characteristics
(V
DD and V
DDSYN
= 5.0 Vdc
±
5%, V
SS
= 0 Vdc, T
A
= T
L to T
H
)
Num
1 Input High Voltage
Characteristic
2 Input Low Voltage
3 Input Hysteresis
1
4 Input Leakage Current
2
V in
= V
DD or V
SS
5 High Impedance (Off-State) Leakage Current
2
Input-only pins
V in
= V
DD
or V
SS
All input/output and output pins
6 CMOS Output High Voltage
2, 3
I
OH
= –10.0
µ
A Group 1, 2, 4 input/output and all output pins
7 CMOS Output Low Voltage
2
I
OL
= 10.0
µ
A Group 1, 2, 4 input/output and all output pins
8 Output High Voltage
2, 3
I
OH
= –0.8 mA
9 Output Low Voltage
2
Group 1, 2, 4 input/output and all output pins
I
OL
I
OL
I
OL
= 1.6 mA Group 1 I/O Pins, CLKOUT, FREEZE/QUOT, IPIPE
= 5.3 mA
= 12 mA
Group 2 and Group 4 I/O Pins, CSBOOT, BG/CS
Group 3
Symbol
V
IH
V
IL
V
HYS
I in
I
V
V
V
V
OZ
OH
OL
OH
OL
10 Three State Control Input High Voltage
11 Data Bus Mode Select Pull-up Current
5
V in
= V
IL
V in
= V
IH
12 V
DD
Supply Current
6
RUN
4
DATA[15:0]
DATA[15:0]
LPSTOP, 32.768 kHz crystal, VCO Off (STSIM = 0)
LPSTOP (External clock input frequency = maximum f sys
)
13 Clock Synthesizer Operating Voltage
14 V
DDSYN
Supply Current
6
32.768 kHz crystal, VCO on, maximum f sys
External Clock, maximum f sys
LPSTOP, 32.768 kHz crystal, VCO off (STSIM = 0)
32.768 kHz crystal, V
DD powered down
15 Power Dissipation
7
16 Input Capacitance
2, 8
All input-only pins
All input/output pins
17 Load Capacitance
2
Group 1 I/O Pins and CLKOUT, FREEZE/QUOT, IPIPE
Group 2 I/O Pins and CSBOOT, BG/CS
Group 3 I/O pins
Group 4 I/O pins
V
V
I
IHTSC
MSP
I
DD
S
IDD
S
IDD
DDSYN
I
DDSYN
I
DDSYN
S
IDDSYN
I
DDSYN
P
D
C in
C
L
Min Max
0.7
(
V
DD
) V
DD
+ 0.3
V
SS
– 0.3
0.2
(
V
DD
)
0.5
—
–2.5
2.5
–2.5
V
DD
– 0.2
—
V
DD
– 0.8
—
—
—
1.6 (V
DD
)
—
–15
—
—
—
4.75
—
—
—
—
—
—
—
—
—
—
—
2.5
—
0.2
—
0.4
0.4
0.4
9.1
–120
—
140
350
5
5.25
2
6
150
100
766
10
20
90
100
130
200
Unit
V
V
V
µ
A
µ
A
V
V
V
V
V
µ
A mA
µ
A mA
V pF mA mA
µ
A
µ
A mW pF
A-6
ELECTRICAL CHARACTERISTICS
For More Information On This Product,
Go to: www.freescale.com
MC68331
USER’S MANUAL
Freescale Semiconductor, Inc.
Notes for Tables A–5 and A–5a
1. Applies to:
Port E [7:4] — SIZ[1:0], AS, DS
Port F [7:0] — IRQ[7:1], MODCLK
Port GP [7:0] — IC4/OC5/OC1, IC[3:1], OC[4:1]/OC1
Port QS [7:0] — TXD, PCS[3:1],ÊPCS0/SS, SCK, MOSI, MISO
BKPT/DSCLK, IFETCH, RESET, RXD, TSTME/TSC
EXTAL (when PLL enabled)
2. Input-Only Pins: EXTAL, TSTME/TSC, BKPT, RXD
Output-Only Pins: CSBOOT, BG/CS, CLKOUT, FREEZE/QUOT, IPIPE
Input/Output Pins:
Group 1: Port GP [7:0] — IC4/OC5/OC1, IC[3:1], OC[4:1]/OC1
DATA[15:0], IFETCH
Group 2 : Port C [6:0] — ADDR[22:19]/CS[9:6], FC[2:0]/CS[5:3]
Port E [7:0] — SIZ[1:0], AS, DS, AVEC, RMC, DSACK[1:0]
Port F [&:0] — IRQ[7:1], MODCLK
Port QS [7:3] — TXD, PCS[3:1],ÊPCS0/SS
ADDR23/CS10/ECLK, ADDR[18:0], R/W, BERR, BR/CS0, BGACK/CS2
Group 3: HALT, RESET
Group 4: MISO, MOSI, SCK
3. Does not apply to HALT and RESET because they are open drain pins. Does not apply to Port QS [7:0] (TXD,
PCS[3:1],ÊPCS0/SS, SCK, MOSI, MISO) in wired-OR mode.
4. Current measured with system clock frequency of 16.78 MHz, all modules active.
5. Use of an active pulldown device is recommended.
6. Total operating current is the sum of the appropriate I
DD
and I
DDSYN
values. I
DD
values include supply currents for device modules powered by V
DDE
and V
DDI
pins.
7. Power dissipation measured at specified system clock frequency, all modules active. Power dissipation can be calculated using the expression:
P
D
=
Maximum V
DD
(I
DD
+ I
DDSYN
)
I
DD
includes supply currents for all device modules powered by V
DDE
and V
DDI
pins.
8. This parameter is periodically sampled rather than 100% tested.
A
MC68331
USER’S MANUAL
ELECTRICAL CHARACTERISTICS
For More Information On This Product,
Go to: www.freescale.com
A-7
Freescale Semiconductor, Inc.
A
Table A-6 16.78 MHz AC Timing
(V
DD and V
DDSYN
= 5.0 Vdc
±
10%, V
SS
= 0 Vdc, T
A
= T
L to T
H
)
Num Characteristic
F1 Frequency of Operation (32.768 kHz crystal)
2
12A Clock Low to IFETCH, IPIPE Negated
13 AS, DS, CS Negated to
Address, FC, SIZE Invalid (Address Hold)
Symbol
f
1
1A
1B External Clock Input Period
2, 3
9C
11
Clock Period
ECLK Period
Clock Pulse Width
Address, FC, SIZE, RMC Valid to AS, CS Asserted
3
Clock Low to IFETCH, IPIPE Asserted t cyc t
Ecyc t
Xcyc t
CW
2A, 3A ECLK Pulse Width
2B, 3B External Clock Input High/Low Time
4, 5 Clock Rise and Fall Time
3 t
ECW t
XCHL t
Crf t rf
4A, 5A Rise and Fall Time — All Outputs except CLKOUT
4B, 5B External Clock Rise and Fall Time
6
7
8
4
Clock High to Address, FC, SIZE, RMC Valid t
XCrf t
CHAV
Clock High to Address, Data, FC, SIZE, RMC High Impedance t
CHAZx
Clock High to Address, FC, SIZE, RMC Invalid t
CHAZn
9 Clock Low to AS, DS, CS Asserted
9A AS to DS or CS Asserted (Read)
5 t t
CLSA
STSA t
CLIA t
AVSA
12 Clock Low to AS, DS, CS Negated t
CLSN t
CLIN t
SNAI
14
14A
14B
16
17
18
20
AS, CS Width Asserted
DS, CS Width Asserted (Write)
AS, CS Width Asserted (Fast Write Cycle)
15 AS, DS, CS Width Negated
6
Clock High to AS, DS, R/W High Impedance
AS, DS, CS Negated to R/W Negated
Clock High to R/W High
Clock High to R/W Low
21
22
23
24
37
R/W Asserted to AS, CS Asserted
R/W Low to DS, CS Asserted (Write)
Clock High to Data Out Valid
Data Out Valid to Negating Edge of AS, CS
BGACK Asserted to BG Negated t
RAAA t
RASA t
CHDO t
DVASN
25
26
27
27A
DS, CS Negated to Data Out Invalid (Data Out Hold)
Data Out Valid to DS, CS Asserted (Write)
Data In Valid to Clock Low (Data Setup)
Late BERR, HALT Asserted to Clock Low (Setup Time) t
SNDOI t
DVSA t
DICL t
BELCL
28 AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated t
SNDN
29 DS, CS Negated to Data In Invalid (Data In Hold)
7 t
SNDI
29A DS, CS Negated to Data In High Impedance
7, 8 t
SHDI
30 CLKOUT Low to Data In Invalid (Fast Cycle Hold)
7 t
CLDI
30A CLKOUT Low to Data In High Impedance
7 t
CLDH
31 DSACK[1:0] Asserted to Data In Valid
9 t
DADI
33 Clock Low to BG Asserted/Negated
35 BR Asserted to BG Asserted (RMC Not Asserted)
10 t t
CLBAN
BRAGA t
GAGN t
SWA t
SWAW t
SWDW t
SN t
CHSZ t
SNRN t
CHRH t
CHRL
0
2
0
0
29.8
—
—
—
Min
0.13
59.6
476
59.6
24
236
–15
2
15
2
2
15
15
15
5
20
15
70
—
15
—
15
0
0
100
45
40
40
—
—
—
1
1
0
0
—
15
A-8
ELECTRICAL CHARACTERISTICS
For More Information On This Product,
Go to: www.freescale.com
ns ns ns ns ns ns ns ns
Unit
MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t cyc t cyc ns ns ns ns
MC68331
USER’S MANUAL
29
59
—
25
—
5
8
5
Max
16.78
—
—
—
—
—
15
22
—
29
22
—
—
—
—
—
—
—
29
—
59
—
29
29
—
—
—
—
90
50
29
—
2
80
—
55
—
Freescale Semiconductor, Inc.
Table A-6 16.78 MHz AC Timing, (Continued)
(V
DD and V
DDSYN
= 5.0 Vdc
±
10%, V
SS
= 0 Vdc, T
A
= T
L to T
H
)
Num
39 BG Width Negated
39A BG Width Asserted
Characteristic
46 R/W Width Asserted (Write or Read)
46A R/W Width Asserted (Fast Write or Read Cycle)
47A Asynchronous Input Setup Time
BR, BGACK, DSACK[1:0], BERR, AVEC, HALT
47B Asynchronous Input Hold Time
48 DSACK[1:0] Asserted to BERR, HALT Asserted
11
53 Data Out Hold from Clock High
54 Clock High to Data Out High Impedance
55 R/W Asserted to Data Bus Impedance Change
56 RESET Pulse Width (Reset Instruction)
57 BERR Negated to HALT Negated (Rerun)
70 Clock Low to Data Bus Driven (Show)
71 Data Setup Time to Clock Low (Show)
72 Data Hold from Clock Low (Show)
73 BKPT Input Setup Time
74 BKPT Input Hold Time
75 Mode Select Setup Time
76 Mode Select Hold Time
77 RESET Assertion Time
12
78 RESET Rise Time
13
Symbol
t
GH t
GA t
RWA t
RWAS t
AIST t
SCLDS t
SCLDH t
BKST t
BKHT t
MSS t
MSH t
RSTA t
RSTR t
AIHT t
DABA t
DOCH t
CHDH t
RADC t
HRPW t
BNHN t
SCLDD
Min
2
1
150
90
5
15
—
0
—
40
512
0
0
15
10
15
10 —
20 —
0
4
—
—
—
10
29
—
—
—
28
—
—
—
—
30
—
Max
—
—
—
—
—
Table A-6a 20.97 MHz AC Timing
(V
DD and V
DDSYN
= 5.0 Vdc
±
5%, V
SS
= 0 Vdc, T
A
= T
L to T
H
)
Num Characteristic
F1 Frequency of Operation (32.768 kHz crystal)
2
12
12A
Clock Low to AS, DS, CS Negated
Clock Low to IFETCH, IPIPE Negated
Symbol
f
1
1A
1B External Clock Input Period
2, 3
9C
11
Clock Period
ECLK Period
Clock Pulse Width
Address, FC, SIZE, RMC Valid to AS, CS Asserted
3
Clock Low to IFETCH, IPIPE Asserted t cyc t
Ecyc t
Xcyc t
CW
2A, 3A ECLK Pulse Width
2B, 3B External Clock Input High/Low Time
4, 5 Clock Rise and Fall Time
3 t
ECW t
XCHL t
Crf t rf
4A, 5A Rise and Fall Time — All Outputs except CLKOUT
4B, 5B External Clock Rise and Fall Time
6
7
8
4
Clock High to Address, FC, SIZE, RMC Valid t
XCrf t
CHAV
Clock High to Address, Data, FC, SIZE, RMC High Impedance t
CHAZx
Clock High to Address, FC, SIZE, RMC Invalid t
CHAZn
9 Clock Low to AS, DS, CS Asserted
9A AS to DS or CS Asserted (Read)
5 t t
CLSA
STSA t
CLIA t
AVSA
13 AS, DS, CS Negated to
Address, FC, SIZE Invalid (Address Hold) t
CLSN t
CLIN t
SNAI
0
0
0
–10
—
—
—
0
2
10
Min
0.13
47.7
381
47.7
18.8
183
23.8
2
2
10
23
22
—
47
—
23
10
5
8
5
23
22
—
Max
20.97
—
—
—
—
—
—
MC68331
USER’S MANUAL
ELECTRICAL CHARACTERISTICS
For More Information On This Product,
Go to: www.freescale.com
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Unit
MHz ns ns ns ns ns ns ns ns ns ns t cyc ns t cyc t cyc ns ns ns ns ns t cyc ns
Unit
t cyc t cyc ns ns ns
A-9
A
Freescale Semiconductor, Inc.
A
Table A-6a 20.97 MHz AC Timing, (Continued)
(V
DD and V
DDSYN
= 5.0 Vdc
±
5%, V
SS
= 0 Vdc, T
A
= T
L to T
H
)
Num Characteristic Symbol
14
14A
14B
16
17
18
20
AS, CS Width Asserted (Fast Write Cycle)
15 AS, DS, CS Width Negated
6
21
22
23
24
37
39
R/W Asserted to AS, CS Asserted
R/W Low to DS, CS Asserted (Write)
Clock High to Data Out Valid
Data Out Valid to Negating Edge of AS, CS
BGACK Asserted to BG Negated
BG Width Negated t
RAAA t
RASA t
CHDO t
DVASN
25
26
27
27A
DS, CS Negated to Data Out Invalid (Data Out Hold)
Data Out Valid to DS, CS Asserted (Write)
Data In Valid to Clock Low (Data Setup)
Late BERR, HALT Asserted to Clock Low (Setup Time) t
SNDOI t
DVSA t
DICL t
BELCL
28 AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated t
SNDN
29 DS, CS Negated to Data In Invalid (Data In Hold)
7 t
SNDI
29A DS, CS Negated to Data In High Impedance
7, 8 t
SHDI
30 CLKOUT Low to Data In Invalid (Fast Cycle Hold)
7 t
CLDI
30A CLKOUT Low to Data In High Impedance
7 t
CLDH
31 DSACK[1:0] Asserted to Data In Valid
9 t
DADI
33 Clock Low to BG Asserted/Negated
35 BR Asserted to BG Asserted (RMC Not Asserted)
10 t t
CLBAN
BRAGA t
GAGN t
GH
39A BG Width Asserted
46
46A
47A
AS, CS Width Asserted
DS, CS Width Asserted (Write)
Clock High to AS, DS, R/W High Impedance
AS, DS, CS Negated to R/W Negated
Clock High to R/W High
Clock High to R/W Low
R/W Width Asserted (Write or Read)
R/W Width Asserted (Fast Write or Read Cycle)
Asynchronous Input Setup Time
BR, BGACK, DSACK[1:0], BERR, AVEC, HALT t
SWA t
SWAW t
SWDW t
SN t
CHSZ t
SNRN t
CHRH t
CHRL t
GA t
RWA t
RWAS t
AIST
47B Asynchronous Input Hold Time
48 DSACK[1:0] Asserted to BERR, HALT Asserted
11
53
54
55
56
57
70
71
72
73
74
75
Data Out Hold from Clock High
Clock High to Data Out High Impedance
R/W Asserted to Data Bus Impedance Change
RESET Pulse Width (Reset Instruction)
BERR Negated to HALT Negated (Rerun)
Clock Low to Data Bus Driven (Show)
Data Setup Time to Clock Low (Show)
Data Hold from Clock Low (Show)
BKPT Input Setup Time
BKPT Input Hold Time
Mode Select Setup Time
76 Mode Select Hold Time
77 RESET Assertion Time
12
78 RESET Rise Time
13,14 t
SCLDS t
SCLDH t
BKST t
BKHT t
MSS t
MSH t
RSTA t
RSTR t
AIHT t
DABA t
DOCH t
CHDH t
RADC t
HRPW t
BNHN t
SCLDD
32
512
0
0
12
—
0
—
10
10
10
10
20 —
0 —
4
—
—
10
—
—
—
—
—
—
—
23
—
30
—
23
1
115
70
5
—
1
1
2
—
10
—
—
5
15
0
0
—
10
10
10
0
0
10
54
Min
80
36
32
32
—
10
—
—
—
—
23
—
2
—
48
—
72
46
—
—
60
—
23
—
—
—
23
23
—
—
Max
—
—
—
—
47
— ns ns ns ns ns ns ns ns ns t cyc t cyc t cyc t cyc ns ns ns ns ns ns ns ns ns ns ns
Unit
ns ns ns ns ns ns ns ns ns ns t cyc ns t cyc t cyc ns ns ns ns ns t cyc ns ns
A-10
ELECTRICAL CHARACTERISTICS
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USER’S MANUAL
Freescale Semiconductor, Inc.
Notes for Tables A–6 and A–6a:
1. All AC timing is shown with respect to 20% V
DD
and 70% V
DD
levels unless otherwise noted.
2. Minimum system clock frequency is four times the crystal frequency, subject to specified limits.
3. When an external clock is used, minimum high and low times are based on a 50% duty cycle. The minimum allowable t
Xcyc
period is reduced when the duty cycle of the external clock signal varies. The relationship between external clock input duty cycle and minimum t
Xcyc
is expressed:
Minimum t
Xcyc
period = minimum t
XCHL
/ (50% – external clock input duty cycle tolerance).
4. Parameters for an external clock signal applied while the internal PLL is disabled (MODCLK pin held low during reset). Does not pertain to an external VCO reference applied while the PLL is enabled (MODCLK pin held high during reset). When the PLL is enabled, the clock synthesizer detects successive transitions of the reference signal. If transitions occur within the correct clock period, rise/fall times and duty cycle are not critical.
5. Specification 9A is the worst-case skew between AS and DS or CS. The amount of skew depends on the relative loading of these signals. When loads are kept within specified limits, skew will not cause AS and DS to fall outside the limits shown in specification 9.
6. If multiple chip selects are used, CS width negated (specification 15) applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select. The CS width negated specification between multiple chip selects does not apply to chip selects being used for synchronous ECLK cycles.
7. Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast cycle reads. The user is free to use either hold time.
8. Maximum value is equal to (t cyc
/ 2) + 25 ns.
9. If the asynchronous setup time (specification 47A) requirements are satisfied, the DSACK[1:0] low to data setup time (specification 31) and DSACK[1:0] low to BERR low setup time (specification 48) can be ignored. The data must only satisfy the data-in to clock low setup time (specification 27) for the following clock cycle. BERR must satisfy only the late BERR low to clock low setup time (specification 27A) for the following clock cycle.
10. To ensure coherency during every operand transfer, BG will not be asserted in response to BR until after all cycles of the current operand transfer are complete and RMC is negated.
11. In the absence of DSACK[1:0], BERR is an asynchronous input using the asynchronous setup time (specification 47A).
12. After external RESET negation is detected, a short transition period (approximately 2 t cyc drives RESET low for 512 t cyc
.
) elapses, then the SIM
13. External assertion of the RESET input can overlap internally-generated resets. To insure that an external reset is recognized in all cases, RESET must be asserted for at least 590 CLKOUT cycles.
14. External logic must pull RESET high during this period in order for normal MCU operation to begin.
15. Address access time = (2.5 + WS) t cyc
– t
CHAV
– t
DICL
Chip select access time = (2 + WS) t cyc
– t
CLSA
– t
DICL
Where: WS = number of wait states. When fast termination is used (2 clock bus) WS = –1.
A
MC68331
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A-11
Freescale Semiconductor, Inc.
1
4 2
3
CLKOUT
5
NOTE: Timing shown with respect to 20% and 70% VDD.
NOTE: Timing shown with respect to 20% and 70% V
DD
.
Figure A-1 CLKOUT Output Timing Diagram
68300 CLKOUT TIM
A
1B
4B 2B 3B
EXTAL
5B
68300 EXT CLK INPUT TIM
NOTE: Timing shown with respect to 20% and 70% V
DD
. Pulse width shown with respect to 50% V
DD
.
Figure A-2 External Clock Input Timing Diagram
1A
4A 2A
3A
ECLK
5A
NOTE: Timing shown with respect to 20% and 70% V
DD
.
Figure A-3 ECLK Output Timing Diagram
68300 ECLK OUTPUT TIM
A-12
ELECTRICAL CHARACTERISTICS
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CLKOUT
A20–A23
FC0–FC2
SIZ0, SIZ1
11
AS
9
DS
CS
20
R/W
21
S0 S1 S2 S3 S4 S5
6 8
9
22
14
12
14A
DSACK0
DSACK1
D0–D15
BERR
HALT
55
23
17
46
47A
48
73
26
27A
74
28
25
53
54
15
13
BKPT
Figure A-4 Read Cycle Timing Diagram
68300 RD CYC TIM
A
MC68331
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A-13
A
Freescale Semiconductor, Inc.
CLKOUT
A20–A23
FC0–FC2
SIZ0, SIZ1
11
AS
9
DS
CS
20
R/W
21
S0 S1 S2 S3 S4 S5
6 8
9
22
14
12
14A
DSACK0
DSACK1
D0–D15
BERR
HALT
55
23
17
46
47A
48
73
26
27A
74
28
25
53
54
15
13
BKPT
Figure A-5 Write Cycle Timing Diagram
68300 WR CYC TIM
A-14
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Freescale Semiconductor, Inc.
CLKOUT
A0–A23
6
S0 S1 S4 S5 S0
8
FC0–FC2
SIZ0, SIZ1
AS
14B
9 12
DS
CS
20
R/W
18
27
46A
D0–D15
30
30A
29A
29
73
BKPT
74
68300 FAST RD CYC TIM
Figure A-6 Fast Termination Read Cycle Timing Diagram
A
MC68331
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A-15
A
Freescale Semiconductor, Inc.
CLKOUT
A0–A23
6
S0 S1 S4 S5 S0
8
FC0–FC2
SIZ0, SIZ1
AS
DS
9
14B
12
CS
20 46A
R/W
24 18
D0–D15
23 25
BKPT
73 74
68300 FAST WR CYC TIM
Figure A-7 Fast Termination Write Cycle Timing Diagram
A-16
ELECTRICAL CHARACTERISTICS
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S0 S1 S2 S3 S4 S5 S98 A5 A5 A2
CLKOUT
A0–A23
D0–D15
AS
DS
R/W
7
16
DSACK0
DSACK1
47A
BR
35 39A
BG
33 33
BGACK
37
68300 BUS ARB TIM
Figure A-8 Bus Arbitration Timing Diagram — Active Bus Case
A
MC68331
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A-17
Freescale Semiconductor, Inc.
A0 A5 A5 A2 A3 A0
A
CLKOUT
A0–A23
D0–D15
AS
BR
47A
BG
BGACK
47A
35 37
33 47A
33
Figure A-9 Bus Arbitration Timing Diagram — Idle Bus Case
68300 BUS ARB TIM IDLE
S0 S41 S42 S43 S0 S1 S2
CLKOUT
6 8
A0–A23
18
R/W
20
AS
12
9 15
DS
71
70 72
D0–D15
73
74
BKPT
SHOW CYCLE
START OF
EXTERNAL CYCLE
68300 SHW CYC TIM
NOTE: Show cycles can stretch during S42 when bus accesses take longer than two cycles due to wait-state insertion by IMB modules.
Figure A-10 Show Cycle Timing Diagram
A-18
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CLKOUT
A0–A23
6
S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5
6
8
FC0–FC2
SIZ0, SIZ1
11
14 11 14
AS
9
9 9
12
DS
17
21
12 21
CS
18 20
46
R/W
46
29
55
D0–D15
29A
27
23
NOTE: AS and DS timing shown for reference only.
Figure A-11 Chip Select Timing Diagram
14A
25
53
15
18
13
17
54
68300 CHIP SEL TIM
A
77 78
RESET
D0–D15
75
Figure A-12 Reset and Mode Select Timing Diagram
76
68300 RST/MODE SEL TIM
MC68331
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A-19
Freescale Semiconductor, Inc.
A
Table A-7 Background Debugging Mode Timing
(V
DD
= 5.0 Vdc
±
10%, V
SS
= 0 Vdc, T
A
= T
L to T
H
)
Num
B0 DSI Input Setup Time
B1 DSI Input Hold Time
B2 DSCLK Setup Time
B3 DSCLK Hold Time
B4 DSO Delay Time
B5 DSCLK Cycle Time
B6
B7
B8
B9
B10
CLKOUT High to FREEZE Asserted/Negated
CLKOUT High to IFETCH High Impedance
CLKOUT High to IFETCH Valid
DSCLK Low Time
Characteristic
FREEZE Asserted to IFETCH Valid
Symbol
t
DSISU t
DSIH t
DSCSU t
DSCH t
DSOD t
DSCCYC t
FRZAN t
IFZ t
IF t
DSCLO t
FRZIF
Min
15
10
15
10
—
—
—
1
TBD
Notes:
1. All AC timing is shown with respect to 20% V
DD
and 70% V
DD
levels unless otherwise noted.
Max
—
—
—
—
— 25
2 —
50
50
50
—
—
Unit
ns ns ns ns ns t cyc ns ns ns t cyc t cyc
A-20
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CLKOUT
FREEZE
BKPT/DSCLK
IFETCH/DSI
IPIPE/DSO
B2
B0
B3
B5
B9
B1 B4
68300 BKGD DBM SER COM TIM
Figure A-13 Background Debugging Mode Timing Diagram —
Serial Communication
CLKOUT
B6
FREEZE
IFETCH/DSI
B7 B10 B6
B8
B10
68300 BKGD DBM FRZ TIM
Figure A-14 Background Debugging Mode Timing Diagram —Freeze Assertion
A
MC68331
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A-21
Freescale Semiconductor, Inc.
A
Table A-8 16.78 MHz ECLK Bus Timing
(V
DD
= 5.0 Vdc
±
10%, V
SS
= 0 Vdc, T
A
= T
L to T
H
)
Num Characteristic
E1 ECLK Low to Address Valid
2
E2 ECLK Low to Address Hold
E3 ECLK Low to CS Valid (CS delay)
E4 ECLK Low to CS Hold
E5 CS Negated Width
E6 Read Data Setup Time
E7 Read Data Hold Time
E8 ECLK Low to Data High Impedance
E9 CS Negated to Data Hold (Read)
E10 CS Negated to Data High Impedance
E11 ECLK Low to Data Valid (Write)
E12 ECLK Low to Data Hold (Write)
E13 Address Access Time (Read)
3
E14 Chip Select Access Time (Read)
4
E15 Address Setup Time
—
—
—
—
60
—
1
2
—
—
—
—
Max
60
—
150
15
386
296
1/2
—
0
—
—
15
30
30
5
Min
—
15
—
Symbol
t
ECDH t
ECDZ t
EDDW t
EDHW t
EACC t
EACS t
EAS t
EAD t
EAH t
ECSD t
ECSH t
ECSN t
EDSR t
EDHR t
EDHZ
Table A-8a 20.97 MHz ECLK Bus Timing
(V
DD
= 5.0 Vdc
±
5%, V
SS
= 0 Vdc, T
A
= T
L to T
H
)
Num
E1
E2
E3
E4
E5
E6
E7
E8
Characteristic
ECLK Low to Address Valid
ECLK Low to Address Hold
2
ECLK Low to CS Valid (CS delay)
ECLK Low to CS Hold
CS Negated Width
Read Data Setup Time
Read Data Hold Time
ECLK Low to Data High Impedance
Symbol
t
EAD t
EAH t
ECSD t
ECSH t
ECSN t
EDSR t
EDHR t
EDHZ
Min
—
10
—
10
25
25
5
—
Max
48
—
120
—
—
—
—
48
E9
E10
E11
CS Negated to Data Hold (Read)
CS Negated to Data High Impedance
ECLK Low to Data Valid (Write) t
ECDH t
ECDZ t
EDDW t
EDHW
0
—
—
—
1
2
E12 ECLK Low to Data Hold (Write)
E13 Address Access Time (Read)
E14
3
Chip Select Access Time (Read)
4 t
EACC t
EACS
10
308
236
—
—
—
E15 Address Setup Time t
EAS
1/2 —
Notes for Tables A–8 and A–8a:
1. All AC timing is shown with respect to 20% V
DD
and 70% V
DD
levels unless otherwise noted.
2. When the previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low.
3. Address access time = t
Ecyc
– t
EAD
– t
EDSR
.
4. Chip select access time = t
Ecyc
– t
ECSD
– t
EDSR
.
ns ns ns t cyc t cyc ns ns ns t cyc
Unit
ns ns ns ns ns ns ns ns t cyc t cyc ns ns ns t cyc ns ns ns ns
Unit
ns ns ns
A-22
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CLKOUT
2A 3A
ECLK
1A
R/W
E2
E1
A0–A23
E14
E3 E4
E6
CS
E15
E9
E5
E13
D0–D15
WRITE READ
E7
E11
E8
D0–D15
WRITE
E12
NOTE: Shown with ECLK = system clock/8 — EDIV bit in clock synthesizer control register (SYNCR) = 0.
E10
68300 E CYCLE TIM
A
Figure A-15 ECLK Timing Diagram
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A-23
Freescale Semiconductor, Inc.
A
Table A-9 QSPI Timing
(V
DD
= 5.0 V dc
±
10%, V
SS
= 0 Vdc, T
A
= T
L to T
H
, 200 pF load on all QSPI pins)
Num Function
Operating Frequency
Master
Slave
1 Cycle Time
Master
Slave
2 Enable Lead Time
Master
Slave
3 Enable Lag Time
Master
Slave
4 Clock (SCK) High or Low Time
Master
Slave
2
5 Sequential Transfer Delay
Master
Slave (Does Not Require Deselect)
6 Data Setup Time (Inputs)
Master
Slave
7 Data Hold Time (Inputs)
Master
Slave
8 Slave Access Time
9 Slave MISO Disable Time
10 Data Valid (after SCK Edge)
Master
Slave
11 Data Hold Time (Outputs)
Master
Slave
12 Rise Time
Input
3
Output
13 Fall Time
Input
3
Output
Symbol
t t f op qcyc t t t lead t t t t t lag t t t sw td su hi a dis v ho ri ro
2 t
2 t
Min
DC
DC
4
4
2
2
—
2 cyc cyc
17
13
30
20
0
20
—
—
—
—
0
0
—
—
– 60
– n
Max
1/4
1/4
510
—
128
—
1/2
—
255 t
—
—
—
1
2 cyc
8192
—
—
—
50
50
—
—
2
30
Unit
System Clock Frequency
System Clock Frequency
SCK t t t t t t t t t cyc cyc cyc cyc cyc ns ns cyc cyc ns ns ns ns cyc cyc ns ns ns ns
µ s ns t fi t fo
—
—
2
30
µ s ns
Notes:
1 All AC timing is shown with respect to 20% V
DD
and 70% V
DD
levels unless otherwise noted.
2. In formula, n = External SCK rise + External SCK fall time
3. Data can be recognized properly with longer transition times as long as MOSI/MISO signals from external sources are at valid V
OH
/V
OL
prior to SCK transitioning between valid V
OL
and V
OH
. Due to process variation, logic decision point voltages of the data and clock signals can differ, which can corrupt data if slower transition times are used.
A-24
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3 2
PCS0–PCS3
OUTPUT
13 5
12
SCK
CPOL=0
OUTPUT
4
1
SCK
CPOL=1
OUTPUT
6
MISO
INPUT
7
MSB IN
4
MOSI
OUTPUT
PD MSB OUT
13
12
11
DATA
DATA
LSB IN
13
10
LSB OUT PORT DATA
12
MSB IN
MSB OUT
68300 QSPI T MAST CPHA0
Figure A-16 QSPI Timing — Master, CPHA = 0
3 2
PCS0–PCS3
OUTPUT
13
5
1 12
SCK
CPOL=0
OUTPUT
4 1
7
SCK
CPOL=1
OUTPUT
MISO
INPUT
MOSI
OUTPUT
PORT DATA
4
MSB IN
MSB OUT
13
12
11
DATA
DATA
13
6
LSB IN
10
LSB OUT
MSB IN
PORT DATA MSB OUT
12
68300 QSPI T MAST CPHA1
Figure A-17 QSPI Timing — Master, CPHA = 1
A
MC68331
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A-25
A
Freescale Semiconductor, Inc.
3
SS
INPUT
13
SCK
CPOL=0
INPUT
4
SCK
CPOL=1
INPUT
MISO
OUTPUT
MOSI
INPUT
6
8
MSB OUT
MSB IN
4
7
11
12
10
DATA
DATA
1
LSB OUT
12
LSB IN
12
13
5
2
PD
13
11
9
MSB OUT
MSB IN
68300 QSPI T SLV CPHA0
Figure A-18 QSPI Timing — Slave, CPHA = 0
SS
INPUT
SCK
CPOL=0
INPUT
SCK
CPOL=1
INPUT
MISO
OUTPUT
2
MOSI
INPUT
4
1
12
4
8
PD
6
10
MSB
OUT
MSB IN
7
10
13
DATA
DATA
13
12
3
11
SLAVE
LSB OUT
12
LSB IN
9
5
PD
68300 QSPI T SLV CPHA1
Figure A-19 QSPI Timing — Slave, CPHA = 1
A-26
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APPENDIX B MECHANICAL DATA AND ORDERING INFORMATION
This section contains detailed information to be used as a guide when ordering.
MC68331 is available in either a 132-pin or 144-pin plastic surface mount package.
This appendix provides package pin assignment drawings and ordering information.
B
MC68331
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B-1
Freescale Semiconductor, Inc.
B
ADDR16
VDD
VSS
ADDR17
ADDR18
PQS0/MISO
PQS1/MOSI
PQS2/SCK
PQS3/PCS0/SS
PQS4/PCS1
PQS5/PCS2
PQS6/PCS3
VDD
ADDR7
ADDR8
VDD
VSS
ADDR9
ADDR10
ADDR11
ADDR12
VSS
ADDR13
ADDR14
ADDR15
VDD
NC
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
41
42
43
44
37
38
39
40
45
46
47
48
49
50
33
34
35
36
29
30
31
32
25
26
27
28
21
22
23
24
18
19
20
MC68331
VDD
BGACK/CS2
BG/CS1
BR/CS0
CSBOOT
DATA0
DATA1
DATA2
DATA3
VDD
VSS
DATA4
DATA5
DATA6
DATA7
VSS
DATA8
DATA9
DATA10
DATA11
VDD
VSS
DATA12
DATA13
DATA14
DATA15
ADDR0
PE0/DSACK0
PE1/DSACK1
PE2/AVEC
PE3/RMC
PE5/DS
VDD
91
90
89
88
95
94
93
92
87
86
85
84
99
98
97
96
103
102
101
100
107
106
105
104
111
110
109
108
116
115
114
113
112
B-2
Figure B-1 132-Pin Plastic Surface Mount Package Pin Assignments
331 132-PIN QFP
MECHANICAL DATA AND ORDERING INFORMATION
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MC68331
USER’S MANUAL
Freescale Semiconductor, Inc.
28
29
30
31
24
25
26
27
32
33
34
35
20
21
22
23
16
17
18
19
12
13
14
15
8
9
10
11
6
7
4
5
1
2
3
36
NC
VSS
FC0/CS3
FC1/CS4
FC2/CS5
ADDR19/CS6
ADDR20/CS7
ADDR21/CS8
ADDR22/CS9
ADDR23/CS10
VDD
VSS
PCLK
PWMB
PWMA
NC
NC
NC
VDD
VSS
NC
PAI
GP7/IC4/OC5/OC1
PGP6/OC4
VDD
VSS
NC
PGP5/OC3/OC1
PGP4/OC2/OC1
PGP3/OC1
PGP2/IC3
PGP1/IC2
PGP0/IC1
NC
VSS
NC
MC68331
DD V SS DD V SS
Figure B-2 144-Pin Plastic Surface Mount Package Pin Assignments
331 144-PIN QFP
81
80
79
78
85
84
83
82
77
76
75
74
73
89
88
87
86
93
92
91
90
101
100
99
98
97
96
95
94
109
108
107
106
105
104
103
102
NC
VSS
PE4/AS
PE6/SIZ0
PE7/SIZ1
R/W
PF0/MODCLK
PF1/IRQ1
PF2/IRQ2
PF3/IRQ3
PF4/IRQ4
PF5/IRQ5
PF6/IRQ6
PF7/IRQ7
BERR
HALT
RESET
VSS
CLKOUT
VDD
NC
XFC
VDD
EXTAL
VDD
XTAL
VSS
FREEZE/QUOT
TSC
BKPT/DSCLK
IFETCH/DSI
IPIPE/DSO
RXD
PQS7/TXD
VSS
NC
B
MC68331
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MECHANICAL DATA AND ORDERING INFORMATION
For More Information On This Product,
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B-3
Freescale Semiconductor, Inc.
B
Table B-1 MCU Ordering Information
Package Type Temperature Frequency
(MHz)
Package
Order
Quantity
2 pc tray
Order Number
132-Pin PQFP
144-Pin QFP
144-Pin TQFP
–40 to +85
–40 to +105
–40 to +125
–40 to +85
–40 to +105
–40 to +125
–40 to +85
–40 to +105
–40 to +125
°
°
°
°
°
°
°
°
°
C
C
C
C
C
C
C
C
C
16 MHz
20 MHz
16 MHz
20 MHz
16 MHz
20 MHz
16 MHz
20 MHz
16 MHz
20 MHz
16 MHz
20 MHz
16 MHz
20 MHz
16 MHz
20 MHz
16 MHz
20 MHz
36 pc tray
2 pc tray
36 pc tray
2 pc tray
36 pc tray
2 pc tray
36 pc tray
2 pc tray
36 pc tray
2 pc tray
36 pc tray
2 pc tray
44 pc tray
2 pc tray
44 pc tray
2 pc tray
44 pc tray
2 pc tray
44 pc tray
2 pc tray
44 pc tray
2 pc tray
44 pc tray
2 pc tray
60 pc tray
2 pc tray
60 pc tray
2 pc tray
60 pc tray
2 pc tray
60 pc tray
2 pc tray
60 pc tray
2 pc tray
SPAKMC331CFC16
MC68331CFC16*
SPAKMC331CFC20
MC68331CFC20*
SPAKMC331VFC16
MC68331VFC16*
SPAKMC331VFC20
MC68331VFC20*
SPAKMC331MFC16
MC68331MFC16*
SPAKMC331MFC20
MC68331MFC20*
SPAKMC331CFV16
MC68331CFV16*
SPAKMC331CFV20
MC68331CFV20*
SPAKMC331VFV16
MC68331VFV16*
SPAKMC331VFV20
MC68331VFV20*
SPAKMC331MFV16
MC68331MFV16*
SPAKMC331MFV20
MC68331MFV20*
SPAKMC331CPV16
MC68331CPV16*
SPAKMC331CPV20
MC68331CPV20*
SPAKMC331VPV16
MC68331VPV16*
SPAKMC331VPV20
MC68331VPV20*
SPAKMC331MPV16
MC68331MPV16*
SPAKMC331MPV20
60 pc tray MC68331MPV20*
*Quantity orders are available as shown in Table B–2. Contact your
Freescale
representative for ordering numbers.
Table B-2 Quantity Order Suffix
FC
36
180
360
FV
44
220
440
PV
60
300
600
B-4
MECHANICAL DATA AND ORDERING INFORMATION
For More Information On This Product,
Go to: www.freescale.com
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USER’S MANUAL
Freescale Semiconductor, Inc.
APPENDIX CDEVELOPMENT SUPPORT
This section serves as a brief reference to Freescale development tools for the
MC68331 microcontroller. Information provided is complete as of the time of publication, but new systems and software are continually being developed. In addition, a growing number of third-party tools are available. The Freescale
MCU Tool Box
(MCUTLBX/D Rev. C) provides an up-to-date list of development tools. Contact your
Freescale representative for further information.
Table C-1 MC68331 Development Tools
Microcontroller Part
Number
MC68331
Modular Development
System
M68MMDS1632
Modular Evaluation
System
M68MEVB1632
C.1 M68MMDS1632 Modular Development System
M68MMDS1632 Freescale Modular Development System (MMDS) is a development tool for evaluating M68HC16 and M68300 MCU-based systems. The MMDS1632 is an emulator, bus state analyzer, and control station for debugging hardware and software. A separately purchased active probe completes MMDS functionality with regard to a particular MCU or MCU family. The many active probes available let your MMDS emulate a variety of different MCUs. Contact your Freescale sales representative, who will assist you in selecting and configuring the modular system that fits your needs. A full-featured development system, the MMDS provides both in-circuit emulation and bus analysis capabilities, including:
C
• Real-time in-circuit emulation at maximum speed of 20 MHz (can be upgraded to
33 MHz)
• Built-in emulation memory
— 1 Mbyte main emulation memory (fast termination, 2 bus cycle)
— 4 Kbytes dual-port emulation memory
• Real-time bus analysis
— Instruction disassembly
— State-machine-controlled triggering
• Four hardware breakpoints, bitwise masking
• Analog/digital emulation
• Synchronized signal output
• Built-in AC power supply, 85–264 V, 50–60 Hz, FCC and EC EMI compliant
• RS-232 connection to host capable of communicating at 1200, 2400, 4800, 9600,
19200, 38400, or 57600 baud
MC68331
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C-1
Freescale Semiconductor, Inc.
C
C.2 M68MEVB1632 Modular Evaluation Board
M68MEVB1632 Modular Evaluation Board (MEVB) is a development tool for evaluating M68HC16 and M68300 MCU-based systems. The MEVB consists of the
M68HC16MPFB modular platform board, an MCU personality board (MPB), an in-circuit debugger printed circuit board (ICD16 or ICD32), and development software.
MEVB features include:
• An economical means of evaluating target systems incorporating M68HC16 and
M68300 HCMOS MCU devices.
• Expansion memory sockets for installing RAM, EPROM, or EEPROM.
— Data RAM: 32K X 16, 128K X 16, or 512K X 16
— EPROM/EEPROM: 32K X 16, 64K X 16, 128K X 16, 256K X 16, or 512K X 16
— Fast RAM: 32K X 16 or 128K X 16
• Background-mode operation, for detailed operation from a personal computer platform without an on-board monitor.
• Integrated assembly/editing/evaluation/programming environment for easy development.
• As many as seven software breakpoints.
• Re-usable ICD hardware for your target application debug or control.
• Two RS-232C terminal input/output (I/O) ports for user evaluation of the serial communication interface.
• Logic analyzer pod connectors.
• Port replacement unit (PRU) to rebuild I/O ports lost to address/data/control.
• On-board V
PP
(+12 Vdc) generation for MCU and flash EEPROM programming.
C-2
DEVELOPMENT SUPPORT
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USER’S MANUAL
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APPENDIX D REGISTER SUMMARY
This appendix contains address maps, register diagrams, and bit/field definitions for the MCU. More detailed information about register function is provided in the appropriate sections of the manual.
Except for central processing unit resources, information is presented in the intermod-
ule bus address order shown in Table D-1.
Table D-1 Module Address Map
Module
GPT
SIM
QSM
Size (Bytes)
64
128
512
Base Address
$YFF900
$YFFA00
$YFFC00
Control registers for all the modules in the microcontroller are mapped into a 4-Kbyte block. The state of the module mapping (MM) bit in the SIM configuration register
(SIMCR) determines where the control registers block is located in the system memory map. When MM = 0, register addresses range from $7FF000 to $7FFFFF; when
MM = 1, register addresses range from $FFF000 to $FFFFFF.
In the module memory maps in this appendix, the “Access” column specifies which registers are accessible at the supervisor privilege level only and which registers can be assigned to either the supervisor or user privilege level.
D
D.1 Central Processing Unit
CPU32 registers are not part of the module address map. The following diagram is a functional representation of CPU resources.
MC68331
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D-1
D
Freescale Semiconductor, Inc.
D.1.1 CPU32 Register Model
31
31
31
31
16 15
16 15
16 15
8 7
7
0
DATA REGISTERS
0
ADDRESS REGISTERS
0
A7 (USP) USER STACK POINTER
0
A3
A4
A5
A6
A0
A1
A2
PC PROGRAM COUNTER
0
D4
D5
D6
D7
D0
D1
D2
D3
CCR CONDITION CODE REGISTER
Figure D-1 User Programming Model
D-2
31
31
16 15
15 8 7
(CCR)
0
A7 (SSP) SUPERVISOR STACK POINTER
0
SR STATUS REGISTER
0
VBR VECTOR BASE REGISTER
2 0
SFC
DFC
ALTERNATE FUNCTION
CODE REGISTERS
Figure D-2 Supervisor Programming Model Supplement
REGISTER SUMMARY
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D.1.2 — Status Register
15
T[1:0]
RESET:
14
0 0
13
S
1
12
0
0
11
0
0
10
1
IP
1
8
1
7
0
0
6
0
0
5
0
0
4
X
U
3
N
U
2
Z
U
1
V
U
0
C
U
The status register (SR) contains condition codes, an interrupt priority mask, and three control bits. The condition codes are contained in the condition code register (CCR), the lower byte of the SR. (The lower and upper bytes of the status register are also referred to as the user and system bytes, respectively.) At the user privilege level, only the CCR is available. At the supervisor level, software can access the full status register.
T[1:0] — Trace Enable
00 = No tracing
01 = Trace on change of flow
10 = Trace on instruction execution
11 = Undefined; reserved
S — Supervisor/User State
0 = CPU operates at user privilege level
1 = CPU operates at supervisor privilege level
IP[2:0] — Interrupt Priority Mask
The priority value in this field (0 to 7) is used to mask interrupts.
X — Extend Flag
Used in multiple-precision arithmetic operations. In many instructions it is set to the same value as the C bit.
N — Negative Flag
Set when the MSB of a result register is set.
Z — Zero Flag
Set when all bits of a result register are zero.
V — Overflow Flag
Set when two's complement overflow occurs as the result of an operation.
C — Carry Flag
Set when a carry or borrow occurs during an arithmetic operation. Also used during shift and rotate instructions to facilitate multiple word operations.
D
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D-3
Freescale Semiconductor, Inc.
D.2 General-Purpose Timer
Table D-2 displays the GPT address map. The column labeled “Access” indicates the
privilege level at which the CPU must be operating to access the register. A designation of “S” indicates that supervisor access is required: a designation of “S/U” indicates that the register can be programmed to the desired privilege level.
D
Table D-2 GPT Address Map
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
Access
S
S
S
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
Address 15 8 7
$YFF900 GPT MODULE CONFIGURATION (GPTMCR)
$YFF902
$YFF904
(RESERVED FOR TEST)
INTERRUPT CONFIGURATION (ICR)
$YFF906 PGP DATA DIRECTION (DDRGP)
$YFF908 OC1 ACTION MASK (OC1M)
$YFF90A
$YFF90C
PGP DATA (PORTGP)
OC1 ACTION DATA (OC1D)
TIMER COUNTER (TCNT)
PA CONTROL (PACTL) PA COUNTER (PACNT)
$YFF90E
$YFF910
$YFF912
$YFF914
$YFF916
$YFF918
$YFF91A
$YFF91C
INPUT CAPTURE 1 (TIC1)
INPUT CAPTURE 2 (TIC2)
INPUT CAPTURE 3 (TIC3)
OUTPUT COMPARE 1 (TOC1)
OUTPUT COMPARE 2 (TOC2)
OUTPUT COMPARE 3 (TOC3)
OUTPUT COMPARE 4 (TOC4)
INPUT CAPTURE 4/OUTPUT COMPARE 5 (TI4/O5)
$YFF91E
$YFF920
$YFF922
$YFF924
$YFF926
$YFF928
$YFF92A
$YFF92C
$YFF92E –
$YFF93F
TIMER CONTROL 1 (TCTL1)
TIMER MASK 1 (TMSK1)
TIMER FLAG 1 (TFLG1)
FORCE COMPARE (CFORC)
TIMER CONTROL 2 (TCTL2)
TIMER MASK 2 (TMSK2)
TIMER FLAG 2 (TFLG2)
PWM CONTROL C (PWMC)
PWM CONTROL A (PWMA) PWM CONTROL B (PWMB)
PWM COUNT (PWMCNT)
PWMA BUFFER (PWMBUFA) PWMB BUFFER (PWMBUFB)
GPT PRESCALER (PRESCL)
NOT USED
0
Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR.
D.2.1 GPTMCR — GPT Module Configuration Register
$YFF900
15 14 13 12 11
STOP FRZ1 FRZ0 STOPP INCP
RESET:
0 0 0 0 0
10
0
0
9
0
0
8
0
0
7
SUPV
1
6
0
0
5
0
0
4
0
0
3
0
GPTMCR bits control freeze, low-power stop, and single-step modes.
STOP — Stop Clocks
0 = Internal clocks not shut down
1 = Internal clocks shut down
0
IARB
0
0
0
D-4
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FRZ[1:0] — FREEZE Response
FRZ1 is not used; FRZ0 encoding determines response to the IMB FREEZE signal.
0 = Ignore IMB FREEZE signal
1 = Freeze the current state of the GPT
STOPP — Stop Prescaler
0 =Normal operation
1 =Stop prescaler and pulse accumulator from incrementing. Ignore changes to input pins.
INCP — Increment Prescaler
0 =Has no meaning
1 =If STOPP is asserted, increment prescaler once and clock input synchronizers once.
SUPV — Supervisor/Unrestricted Data Space
0 =Registers with access controlled by the SUPV bit are accessible from either the user or supervisor privilege level.
1 =Registers with access controlled by the SUPV bit are restricted to supervisor access only.
IARB[3:0] — Interrupt Arbitration
Each module that generates interrupts must have an IARB value. IARB values are used to arbitrate between interrupt requests of the same priority.
D
D.2.2 GPTMTR — GPT Module Test Register (Reserved)
$YFF902
This address is currently unused and returns zeros when read. It is reserved for GPT factory test.
D.2.3 ICR — GPT Interrupt Configuration Register
$YFF904
15
0
RESET:
0
IPA
0
12
0
11
0
0
10
0
IPL
0
8
0
7
0 0
IVBA
0
4
0
3
0
0
2
0
0
1
0
0
0
0
0
ICR fields determine internal and external interrupt priority, and provide the upper nibble of the interrupt vector number supplied to the CPU when an interrupt is acknowledged.
IPA — Interrupt Priority Adjust
Specifies which of the 11 internal GPT interrupt sources is assigned highest priority.
IPL — Interrupt Priority Level
Specifies the priority level of GPT interrupt requests.
IVBA — Interrupt Vector Base Address
Contains the most significant nibble of interrupt vector numbers supplied by the GPT.
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Freescale Semiconductor, Inc.
D.2.4 DDRGP — Port GP Data Direction Register
PORTGP — Port GP Data Register
$YFF906
$YFF907
15 8 7 0
DDRGP PORTGP
0
RESET:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
When GPT pins are used as an 8-bit port, DDRGP determines whether pins are input or output and PORTGP holds the 8-bit data.
DDRGP[7:0] — Parallel Data Direction Register
0 = Input only
1 = Output
PORTGP[7:0] — Parallel Data Register
D
D.2.5 OC1M— OC1 Action Mask Register
OC1D — OC1 Action Data Register
$YFF908
$YFF909
15
OC1M
11 10
0
9
0
8
0
7
OC1D
3 2
0
1
0
0
0
0
RESET:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
All OC outputs can be controlled by the action of OC1. OC1M contains a mask that determines which pins are affected. OC1D determines what outputs are affected.
OC1M[5:1] — OC1 Mask
0 = Corresponding output compare pin is not affected by OC1 compare.
1 = Corresponding output compare pin is affected by OC1 compare.
OC1M[5:1] correspond to OC[5:1].
OC1D[5:1] — OC1 Data
0 =If OC1 mask bit is set, clear corresponding output compare pin on OC1 match.
1 =If OC1 mask bit is set, set corresponding output compare pin on OC1 match.
OC1D[5:1] correspond to OC[5:1].
D.2.6 TCNT — Timer Counter Register $YFF90A
TCNT is the 16-bit free-running counter associated with the input capture, output compare, and pulse accumulator functions of the GPT module.
D-6
REGISTER SUMMARY
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D.2.7 PACTL — Pulse Accumulator Control Register
PACNT — Pulse Accumulator Counter
$YFF90C
$YFF90D
15
PAIS
RESET:
U
14 13 12 11 10
PAEN PAMOD PEDGE PCLKS I4/O5
0 0 0 U 0
9
PACLK
8
0 0
7
0 0 0 0
PACNT
0 0 0
0
0
PACTL enables the pulse accumulator and selects either event counting or gated mode. In event counting mode, PACNT is incremented each time an event occurs. In gated mode, it is incremented by an internal clock.
PAIS — PAI Pin State (Read Only)
PAEN — Pulse Accumulator Enable
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
PAMOD — Pulse Accumulator Mode
0 = External event counting
1 = Gated time accumulation
PEDGE — Pulse Accumulator Edge Control
The effects of PEDGE and PAMOD are shown in the following table.
D
PAMOD
0
0
1
1
PCLKS — PCLK Pin State (Read Only)
PEDGE
0
1
0
1
Effect
PAI Falling Edge Increments Counter
PAI Rising Edge Increments Counter
Zero on PAI Inhibits Counting
One on PAI Inhibits Counting
I4/O5 — Input Capture 4/Output Compare 5
0 = Output compare 5 enabled
1 = Input capture 4 enabled
PACLK[1:0] — Pulse Accumulator Clock Select (Gated Mode)
PACLK[1:0]
00
01
10
11
Pulse Accumulator Clock Selected
System Clock Divided by 512
Same Clock Used to Increment TCNT
TOF Flag from TCNT
External Clock, PCLK
PACNT — Pulse Accumulator Counter
Eight-bit read/write counter used for external event counting or gated time accumulation.
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D.2.8 TIC[1:3] — Input Capture Registers 1–3
$YFF90E–$YFF912
The input capture registers are 16-bit read-only registers used to latch the value of
TCNT when a specified transition is detected on the corresponding input capture pin.
They are reset to $FFFF.
D.2.9 TOC[1:4] — Output Compare Registers 1–4 $YFF914–$YFF91A
The 16-bit read/write output compare registers can be used as output waveform controls or as elapsed time indicators. For output compare functions, they are written to a desired match value and compared against TCNT to control specified pin actions.
They are reset to $FFFF.
D.2.10 TI4/O5 — Input Capture 4/Output Compare 5 Register
$YFF91C
This register serves either as input capture register 4 or output compare register 5, depending on the state of I4/O5 in PACTL.
$YFF91E
D
D.2.11 TCTL1/TCTL2 — Timer Control Registers 1 and 2
15
OM5
RESET:
14
OL5
0 0
13
OM4
0
12
OL4
11
OM3
10
OL3
9
OM2
8
OL2
7
EDGE4
6 5
EDGE3
4 3
EDGE2
2 1
EDGE1
0
0 0 0 0 0 0 0 0 0 0 0 0 0
TCTL1 determines output compare mode and output logic level. TCTL2 determines the type of input capture to be performed.
OM/OL[5:2] — Output Compare Mode Bits and Output Compare Level Bits
Each pair of bits specifies an action to be taken when output comparison is successful.
OM/OL[5:2]
00
01
10
11
Action Taken
Timer Disconnected from Output Logic
Toggle OCx Output Line
Clear OCx Output Line to zero
Set OCx Output Line to one
EDGE[4:1] — Input Capture Edge Control
Each pair of bits configures input sensing logic for the corresponding input capture.
EDGE[4:1]
00
01
10
11
Configuration
Capture Disabled
Capture on Rising Edge Only
Capture on Falling Edge Only
Capture on Any (Rising or Falling) Edge
D-8
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D.2.12 TMSK1/TMSK2 — Timer Interrupt Mask Registers 1 and 2
$YFF920
15
I4/O5I
RESET:
14
0 0 0
OCI
0
11
0
10
0
ICI
0
8
0
7
TOI
0
6
0
0
5 4 3
PAOVI PAII CPROUT
2
0 0 0 0
CPR
0
0
0
TMSK1 enables OC and IC interrupts. TMSK2 controls pulse accumulator interrupts and TCNT functions.
I4/O5I — Input Capture 4/Output Compare 5 Interrupt Enable
0 = IC4/OC5 interrupt disabled
1 = IC4/OC5 interrupt requested when I4/O5F flag in TFLG1 is set
OCI[4:1] — Output Compare Interrupt Enable
0 = OC interrupt disabled
1 = OC interrupt requested when OC flag set
OCI[4:1] correspond to OC[4:1].
ICI[3:1] — Input Capture Interrupt Enable
0 = IC interrupt disabled
1 = IC interrupt requested when IC flag set
ICI[3:1] correspond to IC[3:1].
TOI — Timer Overflow Interrupt Enable
0 = Timer overflow interrupt disabled
1 = Interrupt requested when TOF flag is set
PAOVI — Pulse Accumulator Overflow Interrupt Enable
0 = Pulse accumulator overflow interrupt disabled
1 = Interrupt requested when PAOVF flag is set
PAII — Pulse Accumulator Input Interrupt Enable
0 = Pulse accumulator interrupt disabled
1 = Interrupt requested when PAIF flag is set
CPROUT — Capture/Compare Unit Clock Output Enable
0 = Normal operation for OC1 pin
1 = TCNT clock driven out OC1 pin
CPR[2:0] — Timer Prescaler/PCLK Select Field
This field selects one of seven prescaler taps or PCLK to be TCNT input.
D
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D.2.13 TFLG1/TFLG2 — Timer Interrupt Flag Registers 1 and 2
$YFF922
D
15
I4/O5F
RESET:
0
14
0 0
OCF
0
11
0
10
0
ICF
0
8
0
7
TOF
0
6
0
0
5 4
PAOVF PAIF
0 0
3
0
0
2
0
0
1
0
0
0
0
0
These registers show condition flags that correspond to GPT events. If the corresponding interrupt enable bit in TMSK1/TMSK2 is set, an interrupt occurs.
I4/O5F — Input Capture 4/Output Compare 5 Flag
When I4/O5 in PACTL is zero, this flag is set each time TCNT matches the TOC5 value in TI4/O5. When I4/O5 in PACTL is one, the flag is set each time a selected edge is detected at the I4/O5 pin.
OCF[4:1] — Output Compare Flags
An output compare flag is set each time TCNT matches the corresponding TOC register. OCF[4:1] correspond to OC[4:1].
ICF[3:1] — Input Capture Flags
A flag is set each time a selected edge is detected at the corresponding input capture pin. ICF[3:1] correspond to IC[3:1].
TOF — Timer Overflow Flag
This flag is set each time TCNT advances from a value of $FFFF to $0000.
PAOVF — Pulse Accumulator Overflow Flag
This flag is set each time the pulse accumulator counter advances from a value of $FF to $00.
PAIF — Pulse Accumulator Flag
In event counting mode, this flag is set when an active edge is detected on the PAI pin.
In gated time accumulation mode, it is set at the end of the timed period.
D.2.14 CFORC — Compare Force Register
PWMC — PWM Control Register C
$YFF924
$YFF925
15
FOC
11 10
0
9 8 7
FPWMA FPWMB PPROUT
6
PPR
4 3
SFA
2
SFB
1
F1A
0
F1B
0
RESET:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Setting a bit in CFORC causes a specific output on OC or PWM pins. PWMC sets
PWM operating conditions.
FOC[5:1] — Force Output Compare
0 = Has no meaning.
1 = Causes pin action programmed for corresponding OC pin, but the OC flag is not set.
FOC[5:1] correspond to OC[5:1].
D-10
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FPWMA — Force PWMA Value
0 = Normal PWMA operation.
1 = The value of F1A is driven out on the PWMA pin, regardless of the state of
PPROUT.
FPWMB — Force PWMB Value
0 = Normal PWMB operation.
1 = The value of F1B is driven out on the PWMB pin.
PPROUT — PWM Clock Output Enable
0 = Normal PWM operation on PWMA.
1 = TCNT clock driven out PWMA pin.
PPR[2:0] — PWM Prescaler/PCLK Select
This field selects one of seven prescaler taps or PCLK to be PWMCNT input.
PPR[2:0]
000
001
010
011
100
101
110
111
System Clock
Divide-by Factor
2
4
8
16
32
64
128
PCLK
SFA — PWMA Slow/Fast Select
0 = PWMA period is 256 PWMCNT increments long.
1 = PWMA period is 32768 PWMCNT increments long.
SFB — PWMB Slow/Fast Select
0 = PWMB period is 256 PWMCNT increments long.
1 = PWMB period is 32768 PWMCNT increments long.
The following table shows a range of PWM output frequencies using a 16.78-MHz system clock and 20.97 system clock.
D
PPR
[2:0]
000
001
010
011
100
101
110
111
Prescaler Tap
16.78 MHz 20.97 MHz
Div 2 = 8.39 MHz Div 2 = 10.5 MHz
Div 4 = 4.19 MHz Div 4 = 5.25 MHz
Div 8 = 2.10 MHz Div 8 = 2.62 MHz
Div 16 = 1.05 MHz Div 16 = 1.31 MHz
Div 32 = 524 kHz Div 32 = 655 kHz
Div 64 = 262 kHz Div 64 = 328 kHz
Div 128 = 131 kHz Div 128 = 164 kHz
PCLK PCLK
SFA/B = 0
16.78 MHz
32.8 kHz
20.97 MHz
41 kHz
16.4 kHz
8.19 kHz
4.09 kHz
2.05 kHz
20.5 kHz
10.2 kHz
5.15 kHz
2.56 kHz
1.02 kHz
512 Hz
PCLK/256
SFA/B = 1
16.78 MHz
256 Hz
128 Hz
64.0 Hz
32.0 Hz
16.0 Hz
20.97 MHz
320 Hz
160 Hz
80.0 Hz
40.0 Hz
20.0 Hz
1.28 kHz
641 Hz
8.0 Hz
4.0 Hz
10.0 Hz
5.0 Hz
PCLK/256 PCLK/32768 PCLK/32768
F1A — Force Logic Level One on PWMA
0 = Force logic level zero output on PWMA pin.
1 = Force logic level one output on PWMA pin.
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F1B — Force Logic Level One on PWMB
0 = Force logic level zero output on PWMB pin.
1 = Force logic level one output on PWMB pin.
The value in these registers determines pulse width of the corresponding PWM output.
A value of $00 corresponds to continuously low output; a value of $80 to 50% duty cycle. Maximum value ($FF) selects an output that is high for 255/256 of the period.
Writes to these registers are buffered by PWMBUFA and PWMBUFB.
D.2.16 PWMCNT — PWM Count Register $YFF928
PWMCNT is the 16-bit free-running counter used for GPT PWM functions.
D
D.2.17 PWMBUFA — PWM Buffer Register A $YFF92A
$YFF92B
To prevent glitches when PWM duty cycle is changed, the contents of PWMA and
PWMB are transferred to these read-only registers at the end of each duty cycle. Reset state is $0000.
D.2.18 PRESCL — GPT Prescaler $YFF92C
The 9-bit prescaler value can be read from bits [8:0] at this address. Bits [15:9] always read as zeros. Reset state is $0000.
D-12
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D.3 System Integration Module
Table D-3 displays the SIM address map. The column labeled “Access” indicates the
privilege level at which the CPU must be operating to access the register. A designation of “S” indicates that supervisor access is required. A designation of “S/U” indicates that the register can be programmed to the desired privilege level.
S/U
S
S
S
S
S
S
S
S
S
S
S
S/U
S
S
S
S
S
S
S
S
S
S/U
S/U
S/U
S
S/U
S/U
Access
S
S
S
S
S
S
S/U
S
S
Table D-3 SIM Address Map
Address 15 8 7 0
$YFFA00
$YFFA02
SIM CONFIGURATION (SIMCR)
FACTORY TEST (SIMTR)
$YFFA04
$YFFA06
$YFFA08
$YFFA0A
CLOCK SYNTHESIZER CONTROL (SYNCR)
NOT USED RESET STATUS REGISTER (RSR)
MODULE TEST E (SIMTRE)
NOT USED NOT USED
$YFFA0C
$YFFA0E
$YFFA10
$YFFA12
$YFFA14
$YFFA16
$YFFA18
$YFFA1A
$YFFA1C
$YFFA1E
$YFFA20
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
PORT E DATA (PORTE0)
PORT E DATA (PORTE1)
PORT E DATA DIRECTION (DDRE)
PORT E PIN ASSIGNMENT (PEPAR)
PORT F DATA (PORTF0)
PORT F DATA (PORTF1)
PORT F DATA DIRECTION (DDRF)
PORT F PIN ASSIGNMENT (PFPAR)
NOT USED SYSTEM PROTECTION CONTROL
(SYPCR)
PERIODIC INTERRUPT CONTROL (PICR) $YFFA22
$YFFA24
$YFFA26
$YFFA28
$YFFA2A
$YFFA2C
$YFFA2E
PERIODIC INTERRUPT TIMING (PITR)
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
SOFTWARE SERVICE (SWSR)
NOT USED
NOT USED
NOT USED
NOT USED
TEST MODULE MASTER SHIFT A (TSTMSRA)
TEST MODULE MASTER SHIFT B (TSTMSRB)
$YFFA30
$YFFA32
$YFFA34
$YFFA36
$YFFA38
$YFFA3A
$YFFA3C
$YFFA3E
TEST MODULE SHIFT COUNT (TSTSC)
TEST MODULE REPETITION COUNTER (TSTRC)
TEST MODULE CONTROL (CREG)
TEST MODULE DISTRIBUTED REGISTER (DREG)
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
PORT C DATA (PORTC)
NOT USED
$YFFA40
$YFFA42
$YFFA44
$YFFA46
$YFFA48
$YFFA4A
$YFFA4C
$YFFA4E
CHIP-SELECT PIN ASSIGNMENT (CSPAR0)
CHIP-SELECT PIN ASSIGNMENT (CSPAR1)
CHIP-SELECT BASE BOOT (CSBARBT)
CHIP-SELECT OPTION BOOT (CSORBT)
CHIP-SELECT BASE 0 (CSBAR0)
CHIP-SELECT OPTION 0 (CSOR0)
D
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D
Table D-3 SIM Address Map
S
S
S
S
S
S
S
S
Access
S
S
S
S
S
S
S
S
S
S
S
S
$YFFA6A
$YFFA6C
$YFFA6E
$YFFA70
$YFFA72
$YFFA74
$YFFA76
$YFFA78
$YFFA7A
$YFFA7C
$YFFA7E
Address 15 8 7 0
$YFFA50 CHIP-SELECT BASE 1 (CSBAR1)
$YFFA52
$YFFA54
$YFFA56
$YFFA58
CHIP-SELECT OPTION 1 (CSOR1)
CHIP-SELECT BASE 2 (CSBAR2)
CHIP-SELECT OPTION 2 (CSOR2)
CHIP-SELECT BASE 3 (CSBAR3)
$YFFA5A
$YFFA5C
$YFFA5E
$YFFA60
$YFFA62
$YFFA64
$YFFA66
$YFFA68
CHIP-SELECT OPTION 3 (CSOR3)
CHIP-SELECT BASE 4 (CSBAR4)
CHIP-SELECT OPTION 4 (CSOR4)
CHIP-SELECT BASE 5 (CSBAR5)
CHIP-SELECT OPTION 5 (CSOR5)
CHIP-SELECT BASE 6 (CSBAR6)
CHIP-SELECT OPTION 6 (CSOR6)
CHIP-SELECT BASE 7 (CSBAR7)
CHIP-SELECT OPTION 7 (CSOR7)
NOT USED
NOT USED
NOT USED
CHIP-SELECT BASE 8 (CSBAR8)
CHIP-SELECT OPTION 8 (CSOR8)
CHIP-SELECT BASE 9 (CSBAR9)
CHIP-SELECT OPTION 9 (CSOR9)
CHIP-SELECT BASE 10 (CSBAR10)
CHIP-SELECT OPTION 10 (CSOR10)
NOT USED NOT USED
NOT USED
NOT USED
NOT USED
Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR
D.3.1 SIMCR — Module Configuration Register
$YFFA00
15 14 13
EXOFF FRZSW FRZBM
RESET:
0 0 0
12
0
0
11
SLVEN
DATA11
10
0
0
9
SHEN
8
0 0
7 6
SUPV MM
1 1
5
0
0
4
0
0
3
1 1
IARB
1
0
1
SIMCR controls system configuration. SIMCR can be read or written at any time, except for the module mapping (MM) bit, which can only be written once.
EXOFF — External Clock Off
0 = The CLKOUT pin is driven from an internal clock source.
1 = The CLKOUT pin is placed in a high-impedance state.
FRZSW — Freeze Software Enable
0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters continue to run.
1 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters are disabled, preventing interrupts during software debug.
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FRZBM — Freeze Bus Monitor Enable
0 = When FREEZE is asserted, the bus monitor continues to operate.
1 = When FREEZE is asserted, the bus monitor is disabled.
SLVEN — Factory Test Mode Enabled
0 = IMB is not available to an external master.
1 = An external bus master has direct access to the IMB.
SHEN[1:0] — Show Cycle Enable
This field determines what the EBI does with the external bus during internal transfer operations.
SUPV — Supervisor/Unrestricted Data Space
The SUPV bit places the SIM global registers in either supervisor or user data space.
0 = Registers with access controlled by the SUPV bit are accessible from either the user or supervisor privilege level.
1 = Registers with access controlled by the SUPV bit are restricted to supervisor access only.
MM — Module Mapping
0 = Internal modules are addressed from $7FF000 – $7FFFFF.
1 = Internal modules are addressed from $FFF000 – $FFFFFF.
IARB[3:0] — Interrupt Arbitration Field
Determines SIM interrupt arbitration priority. The reset value is $F (highest priority), to prevent SIM interrupts from being discarded during initialization.
D
$YFFA02
D.3.2 SIMTR — System Integration Test Register
SIMTR is used for factory test only.
D.3.3 SYNCR — Clock Synthesizer Control Register
$YFFA04
15
W
RESET:
14
X
0 0
13
1 1 1
Y
1 1
8
1
7
EDIV
0
6
0
0
5
0
0
4 3 2
SLIMP SLOCK RSTEN
1
STSIM
0
STEXT
U U 0 0 0
SYNCR determines system clock operating frequency and mode of operation.
Clock frequency is determined by SYNCR bit settings as follows: .
W — Frequency Control (VCO)
0 = Base VCO frequency
1 = VCO frequency multiplied by four
X — Frequency Control Bit (Prescale)
0 = VCO frequency divided by four (base system clock frequency)
1 = VCO frequency divided by two (system clock frequency doubles)
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D
Y[5:0] — Frequency Control (Counter)
The Y field is the initial value for the modulus 64 down counter in the synthesizer feedback loop. Values range from 0 to 63.
EDIV — ECLK Divide Rate
0 = ECLK is system clock divided by 8
1 = ECLK is system clock divided by 16
SLIMP — Limp Mode
0 = External crystal is VCO reference
1 = Loss of crystal reference
SLOCK — Synthesizer Lock
0 = VCO is enabled, but has not locked.
1 = VCO has locked on the desired frequency or system clock is external.
RSTEN — Reset Enable
0 = Loss of reference causes the MCU to operate in limp mode.
1 = Loss of reference causes system reset.
STSIM — Stop Mode System Integration Clock
0 = SIM clock driven by an external source and VCO off during low-power stop.
1 = SIM clock driven by VCO during low-power stop.
STEXT — Stop Mode External Clock
0 = CLKOUT held low during low-power stop.
1 = CLKOUT driven from SIM clock during low-power stop.
D.3.4 RSR — Reset Status Register
$YFFA07
15
NOT USED
8 7 6
EXT POW
5
SW
4
HLT
3
0
2
LOC
1
SYS
0
TST
RSR contains a status bit for each reset source in the MCU. RSR is updated when the
MCU comes out of reset. A set bit indicates what type of reset occurred. If multiple sources assert reset signals at the same time, more than one bit in RSR may be set.
This register can be read at any time; a write has no effect.
EXT — External Reset
Reset caused by an external signal.
POW — Power-Up Reset
Reset caused by the power-up reset circuit.
SW — Software Watchdog Reset
Reset caused by the software watchdog circuit.
HLT — Halt Monitor Reset
Reset caused by the halt monitor.
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LOC — Loss of Clock Reset
Reset caused by loss of clock frequency reference.
SYS — System Reset
Reset caused by a RESET instruction.
TST — Test Submodule Reset
Reset caused by the test submodule. Used during system test only.
D.3.5 SIMTRE — System Integration Test Register (ECLK)
Register is used for factory test only.
D.3.6 PORTE0/PORTE1 — Port E Data Register
$YFFA08
$YFFA11, $YFFA13
15
NOT USED
8 7
PE7
6
PE6
5
PE5
4
PE4
3
PE3
2
PE2
1
PE1
0
PE0
RESET:
U U U U U U U U
PORTE is an internal data latch that can be accessed at two locations. PORTE can be read or written at any time. If a pin in I/O port E is configured as an output, the corresponding bit value is driven out on the pin. When a pin is configured for output, a read of PORTE returns the latched bit value; when a pin is configured for input, a read returns the pin logic level.
D
D.3.7 DDRE — Port E Data Direction Register
$YFFA15
15
NOT USED
8 7 6 5 4 3 2 1 0
DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0
RESET:
0 0 0 0 0 0 0 0
Bits in this register control the direction of the port E pin drivers when pins are configured for I/O. Setting a bit configures the corresponding pin as an output; clearing a bit configures the corresponding pin as an input. This register can be read or written at any time.
D.3.8 PEPAR — Port E Pin Assignment Register
$YFFA17
15
NOT USED
8 7 6 5 4 3 2 1 0
PEPA7 PEPA6 PEPA5 PEPA4 PEPA3 PEPA2 PEPA1 PEPA0
RESET:
DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8
Bits in this register determine the function of port E pins. Setting a bit assigns the corresponding pin to a bus control signal; clearing a bit assigns the pin to I/O port E.
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Table D-4 Port E Pin Assignments
PEPAR Bit
PEPA7
PEPA6
PEPA5
PEPA4
PEPA3
PEPA2
PEPA1
PEPA0
Port E Signal
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
Bus Control Signal
SIZ1
SIZ0
AS
DS
RMC
AVEC
DSACK1
DSACK0
D.3.9 PORTF0/PORTF1 — Port F Data Register
$YFFA19, $YFFA1B
D
15
NOT USED
8 7
PF7
6
PF6
5
PF5
4
PF4
3
PF3
2
PF2
1
PF1
0
PF0
RESET:
U U U U U U U U
PORTF is an internal data latch that can be accessed at two locations. It can be read or written at any time. If a pin in I/O port F is configured as an output, the corresponding bit value is driven out on the pin. When a pin is configured for output, a read of PORTF returns the latched bit value; when a pin is configured for input, a read returns the pin logic level.
D.3.10 DDRF — Port F Data Direction Register
$YFFA1D
15
NOT USED
8 7 6 5 4 3 2 1 0
DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0
RESET:
0 0 0 0 0 0 0 0
Bits in this register control the direction of the port F pin drivers when pins are configured for I/O. Setting a bit configures the corresponding pin as an output; clearing a bit configures the corresponding pin as an input. This register can be read or written at any time.
D.3.11 PFPAR — Port F Pin Assignment Register
$YFFA1F
15
NOT USED
8 7
PFPA7
6
PFPA6
5
PFPA5
4
PFPA4
3
PFPA3
2
PFPA2
1
PFPA1
0
PFPA0
RESET:
DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 DATA9
Bits in this register determine the function of port F pins. Setting a bit assigns the corresponding pin to a control signal; clearing a bit assigns the pin to port F.
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Table D-5 Port F Pin Assignments
PFPAR Field Port F Signal Control Signal
PFPA7 PF7 IRQ7
PFPA6
PFPA5
PF6
PF5
IRQ6
IRQ5
PFPA4
PFPA3
PFPA2
PFPA1
PFPA0
PF4
PF3
PF2
PF1
PF0
IRQ4
IRQ3
IRQ2
IRQ1
MODCLK
D.3.12 SYPCR — System Protection Control Register
$YFFA21
15
NOT USED
8 7
SWE
6
SWP
5
SWT
4 3 2
HME BME
1
BMT
0
RESET:
1 MODCLK 0 0 0 0 0 0
SYPCR controls system monitor functions, software watchdog clock prescaling, and bus monitor timing. This register can be written once following power-on or reset.
SWE — Software Watchdog Enable
0 = Software watchdog disabled
1 = Software watchdog enabled
SWP — Software Watchdog Prescale
0 = Software watchdog clock not prescaled
1 = Software watchdog clock prescaled by 512
SWT[1:0] — Software Watchdog Timing
This field selects software watchdog time-out period.
Table D-6 Software Watchdog Ratio
SWP
0
0
1
1
0
0
1
1
SWT Ratio
00 2
9
01
10
2
11
2
13
11
00
01
10
11
2
15
2
18
2
20
2
22
2
24
HME — Halt Monitor Enable
0 = Disable halt monitor function
1 = Enable halt monitor function
D
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BME — Bus Monitor External Enable
0 = Disable bus monitor function for an internal to external bus cycle.
1 = Enable bus monitor function for an internal to external bus cycle.
BMT[1:0] — Bus Monitor Timing
This field selects bus monitor time-out period.
Table D-7 Bus Monitor Period
BMT
00
01
10
11
Bus Monitor Time-out Period
64 System Clocks
32 System Clocks
16 System Clocks
8 System Clocks
D.3.13 PICR — Periodic Interrupt Control Register
$YFFA22
D
15
0
RESET:
14
0
0 0
13
0
0
12
0
0
11
0
0
10
0
PIRQL
0
8
0
7
0 0 0 0
PIV
1 1 1
0
1
Contains information concerning periodic interrupt priority and vectoring. PICR[10:0] can be read or written at any time. PICR[15:11] are unimplemented and always return zero.
PIRQL[2:0] — Periodic Interrupt Request Level
This field determines the priority of periodic interrupt requests.
PIV[7:0] — Periodic Interrupt Vector
The bits of this field contain the periodic interrupt vector number supplied by the SIM when the CPU acknowledges an interrupt request.
D.3.14 PITR — Periodic Interrupt Timer Register $YFFA24
15
0
RESET:
14
0
0 0
13
0
0
12
0
0
11
0
0
10
0
0
9
0
0
8
PTP
MODCLK
7
0 0 0 0
PITM
0 0 0
0
0
Contains the count value for the periodic timer. This register can be read or written at any time.
PTP — Periodic Timer Prescaler Control
0 = Periodic timer clock not prescaled
1 = Periodic timer clock prescaled by a value of 512
PITM[7:0] — Periodic Interrupt Timing Modulus
This is the 8-bit timing modulus used to determine periodic interrupt rate. Use the following expression to calculate timer period.
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D.3.15 SWSR — Software Service Register
$YFFA27
15
NOT USED
8 7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
RESET:
0 0 0 0 0 0 0 0
When the software watchdog is enabled, a service sequence must be written to this register within a specific interval. When read, SWSR always returns $00. Register shown with read value.
$YFFA30
D.3.16 TSTMSRA — Master Shift Register A
Register is used for factory test only.
D.3.17 TSTMSRB — Master Shift Register B
Register is used for factory test only.
D.3.18 TSTSC — Test Module Shift Count
Register is used for factory test only.
D.3.19 TSTRC — Test Module Repetition Count
Register is used for factory test only.
$YFFA32
$YFFA34
D
$YFFA36
D.3.20 CREG — Test Submodule Control Register $YFFA38
Register is used for factory test only.
D.3.21 DREG — Distributed Register
Register is used for factory test only.
$YFFA3A
D.3.22 PORTC — Port C Data Register
$YFFA41
15
NOT USED
8 7
0
6
PC6
5
PC5
4
PC4
3
PC3
2
PC2
RESET:
0 1 1 1 1 1
PORTC latches data for chip-select pins that are used for discrete output.
1
PC1
1
0
PC0
1
D.3.23 CSPAR0 — Chip Select Pin Assignment Register 0
$YFFA44
15
0
RESET:
14
0
0 0
13
CSPA0[6]
12 11
CSPA0[5]
10 9
CSPA0[4]
8 7
CSPA0[3]
6 5
CSPA0[2]
4 3
CSPA0[1]
2
DATA2 1 DATA2 1 DATA2 1 DATA1 1 DATA1 1 DATA1 1
1 0
CSBOOT
1 DATA0
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Table D-8 CSPAR0 Pin Assignments
CSPAR0 Field
CSPA0[6]
CSPA0[5]
CSPA0[4]
CSPA0[3]
CSPA0[2]
CSPA0[1]
CSBOOT
CSPAR0 Signal
CS5
CS4
CS3
CS2
CS1
CS0
CSBOOT
Alternate Signal
FC2
FC1
FC0
BGACK
BG
BR
—
Discrete Output
PC2
PC1
PC0
—
—
—
—
Contains seven 2-bit fields, CSPA0[6:1] and CSBOOT, that determine the functions of corresponding chip-select pins. CSPAR0[15:14] are not used. These bits always read zero; write has no effect. CSPAR0 bit 1 always reads one; writes to CSPAR0 bit 1 have no effect. The alternate functions can be enabled by data bus mode selection during reset.
$YFFA46
D
D.3.24 CSPAR1 — Chip Select Pin Assignment Register 1
15
0
0
RESET:
0
14 13 12 11 10
0 0 0 0 0
0 0 0 0
9
CSPA1[4]
DATA7
8
1
7
CSPA1[3]
6 5
CSPA1[2]
4
DATA6 1 DATA5 1
3
CSPA1[1]
2
DATA4 1
1
CSPA1[0]
0
DATA3 1
Table D-9 CSPAR1 Pin Assignments
CSPAR1 Field
CSPA1[4]
CSPA1[3]
CSPA1[2]
CSPA1[1]
CSPA1[0]
CSPAR1 Signal
CS10
CS9
CS8
CS7
CS6
Alternate Signal Discrete Output
ADDR23 ECLK
ADDR22
ADDR21
PC6
PC5
ADDR20
ADDR19
PC4
PC3
Contains five 2-bit fields (CSPA1[4:0]) that determine the functions of corresponding chip-select pins. CSPAR1[15:10] are not used. These bits always read zero; write has no effect. The CSPAR1 pin assignments table shows alternate functions that can be enabled by data bus mode selection during reset.
Table D-10 CSPAR0 and CSPAR1 Pin Assignment Field Encoding
Bit Field
00
01
10
11
Description
Discrete Output*
Alternate Function*
Chip Select (8-Bit Port)
Chip Select (16-Bit Port)
*Does not apply to the CSBOOT field
D-22
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D.3.25 CSBARBT — Chip Select Base Address Register Boot ROM $YFFA48
15
ADDR
23
RESET:
14
ADDR
22
0 0
13
ADDR
21
12
ADDR
20
0 0
11
ADDR
19
10
ADDR
18
0 0
9
ADDR
17
8
ADDR
16
7
ADDR
15
6
ADDR
14
5
ADDR
13
4
ADDR
12
3
ADDR
11
0 0 0 0 0 0 0
2
0
BLKSZ
0
0
0
Each chip-select pin has an associated base address register. A base address is the lowest address in the block of addresses enabled by a chip select. CSBARBT contains the base address for selection of a bootstrap peripheral memory device. Bit and field definition for CSBARBT and CSBAR[0:10] are the same, but reset block sizes differ.
ADDR[23:11] — Base Address
This field sets the starting address of a particular address space.
BLKSZ — Block Size
This field determines the size of the block above the base address that is enabled by the chip select.
Table D-11 Block Size Encoding
BLKSZ[2:0]
000
001
010
011
100
101
110
111
Block Size
2 K
8 K
16 K
64 K
128 K
256 K
512 K
1 M
Address Lines Compared
ADDR[23:11]
ADDR[23:13]
ADDR[23:14]
ADDR[23:16]
ADDR[23:17]
ADDR[23:18]
ADDR[23:19]
ADDR[23:20]
D
D.3.26 CSORBT — Chip Select Option Register Boot ROM
CSOR[0:10] — Chip Select Option Registers
$YFFA4A
$YFFA4E–$YFFA76
15
MODE
RESET:
14
BYTE
13
0 0 0
12
R/W
11 10
STRB
9
DSACK
6 5
SPACE
4 3
IPL
1 0
AVEC
0 0 0 0 0 0 0 0 0 0 0 0 0
Contain parameters that support bootstrap operations from peripheral memory devices. Bit and field definitions for CSORBT and CSOR[0:10] are the same.
MODE — Asynchronous Bus/Synchronous E-clock Mode
Synchronous mode cannot be used with internally generated autovectors.
0 = Asynchronous mode selected
1 = Synchronous mode selected
BYTE — Upper/Lower Byte Option
The value in this field determines whether a select signal can be asserted.
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R/W — Read/Write
This field causes a chip select to be asserted only for a read, only for a write, or for both read and write.
STRB — Address Strobe/Data Strobe
0 = Address strobe
1 = Data strobe
DSACK — Data Strobe Acknowledge
This field specifies the source of DSACK in asynchronous bus mode and controls wait state insertion.
SPACE — Address Space Select
This field selects an address space to be used by the chip-select logic.
IPL — Interrupt Priority Level
This field determines interrupt priority level when a chip select is used for interrupt acknowledge. It does not affect CPU interrupt recognition.
AVEC — Autovector Enable
Do not enable autovector support when in synchronous mode.
0 = External interrupt vector enabled
1 = Autovector enabled
Table D-12 Option Register Function Summary
MODE BYTE R/W STRB DSACK SPACE
0 = ASYNC 00 = Disable 00 = Rsvd 0 = AS 0000 = 0 WAIT 00 = CPU SP
IPL
000 = All
1 = SYNC 01 = Lower 01 = Read 1 = DS 0001 = 1 WAIT 01 = User SP 001 = Priority 1 1 = On
10 = Upper 10 = Write 0010 = 2 WAIT 10 = Supv SP 010 = Priority 2
11 = Both 11 = Both 0011 = 3 WAIT
0100 = 4 WAIT
11 = S/U SP 011 = Priority 3
100 = Priority 4
AVEC
0 = Off
0101 = 5 WAIT
0110 = 6 WAIT
0111 = 7 WAIT
1000 = 8 WAIT
101 = Priority 5
110 = Priority 6
111 = Priority 7
1001 = 9 WAIT
1010 = 10 WAIT
1011 = 11 WAIT
1100 = 12 WAIT
1101 = 13 WAIT
1110 = F term
1111 = External
D-24
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D.4 Queued Serial Module
Table D-13 displays the QSM address map. The column labeled “Access” indicates
the privilege level at which the CPU must be operating to access the register. A designation of “S” indicates that supervisor access is required: a designation of “S/U” indicates that the register can be programmed to the desired privilege level.
Table D-13 QSM Address Map
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
Access
S
S
S
S/U
S/U
S/U
S/U
S/U
QUEUE RAM
S/U
QUEUE RAM
S/U
QUEUE RAM
Address
$YFFC00
$YFFC02
$YFFC04
$YFFC06
$YFFC08
$YFFC0A
$YFFC0C
$YFFC0E
$YFFC10
$YFFC12
$YFFC14
$YFFC16
$YFFC18
$YFFC1A
$YFFC1C
$YFFC1E
$YFFC20–
$YFFCFF
$YFFD00–
$YFFD1F
$YFFD20–
$YFFD3F
$YFFD40–
$YFFD4F
15 8 7
QSM MODULE CONFIGURATION (QSMCR)
QSM TEST (QTEST)
QSM INTERRUPT LEVEL (QILR) QSM INTERRUPT VECTOR (QIVR)
NOT USED
SPI CONTROL 3 (SPCR3)
NOT USED
SCI CONTROL 0 (SCCR0)
SCI CONTROL 1 (SCCR1)
SCI STATUS (SCSR)
SCI DATA (SCDR)
NOT USED
NOT USED
NOT USED
Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR.
PQS DATA (PORTQS)
PQS PIN ASSIGNMENT (PQSPAR) PQS DATA DIRECTION (DDRQS)
SPI CONTROL 0 (SPCR0)
SPI CONTROL 1 (SPCR1)
SPI CONTROL 2 (SPCR2)
SPI STATUS (SPSR)
RECEIVE RAM (RR[0:F])
TRANSMIT RAM (TR[0:F])
COMMAND RAM (CR[0:F])
0
D.4.1 QSMCR — QSM Configuration Register
$YFFC00
D
15 14 13
STOP FRZ1 FRZ0
RESET:
0 0 0
12
0
0
11
0
0
10
0
0
9
0
0
8
0
0
7
SUPV
1
6
0
0
5
0
0
4
0
0
3
0 0
IARB
0
0
0
QSMCR bits enable stop and freeze modes, and determine the arbitration priority of
QSM interrupt requests.
STOP — Stop Enable
0 = Normal QSM clock operation
1 = QSM clock operation stopped
When STOP is set, the QSM enters low-power stop mode. System clock input to the module is disabled. While STOP is asserted, only QSMCR reads are guaranteed to be
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D
valid, but writes to QSPI RAM or any register are guaranteed valid. STOP is set during reset. The SCI receiver and transmitter must be disabled before STOP is set. To stop the QSPI, set the HALT bit in SPCR3, wait until the HALTA flag is set, then set STOP.
FRZ[1:0] — Freeze Control
0 = Ignore the FREEZE signal on the IMB
1 = Halt the QSPI (on a transfer boundary)
FRZ1 determines what action is taken by the QSPI when the FREEZE signal of the
IMB is asserted. FREEZE is asserted whenever the CPU enters background mode.
FRZ0 is reserved for future use.
SUPV — Supervisor/Unrestricted
0 = Supervisor access
1 = User access
IARB — Interrupt Arbitration
Each module that generates interrupts must have an IARB value. IARB values are used to arbitrate between interrupt requests of the same priority.
$YFFC02
D.4.2 QTEST — QSM Test Register
Used for factory test only.
D.4.3 QILR — QSM Interrupt Level Register
QIVR — QSM Interrupt Vector Register
$YFFC04
$YFFC05
15
0
RESET:
14
0
0 0
13
0
ILQSPI
0
11
0
10
0
ILSCI
0
8
0
7
0 0 0 0
INTV
1 1 1
0
1
The values of the ILQSPI and ILSCI fields in QILR determine the priority of QSPI and
SCI interrupt requests. QIVR determines the value of the interrupt vector number the
QSM supplies when it responds to an interrupt acknowledge cycle. At reset, QIVR is initialized to vector number $0F, the uninitialized interrupt vector number. To use interrupt-driven serial communication, a user-defined vector number must be written to
QIVR.
ILQSPI — Interrupt Level for QSPI
When an interrupt request is made, ILQSPI value determines which of the interrupt request signals is asserted; when a request is acknowledged, the QSM compares this value to a mask value supplied by the CPU32 to determine whether to respond. ILQS-
PI must have a value in the range $0 (lowest priority) to $7 (highest priority).
ILSCI — Interrupt Level for SCI
When an interrupt request is made, ILSCI value determines which of the interrupt request signals is asserted. When a request is acknowledged, the QSM compares this value to a mask value supplied by the CPU32 to determine whether to respond. The field must have a value in the range $0 (lowest priority) to $7 (highest priority).
If ILQSPI and ILSCI have the same nonzero value, and both submodules simultaneously request interrupt service, the QSPI has priority.
D-26
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INTV[7:0] — Interrupt Vector Number
The values of INTV[7:1] are the same for both QSPI and SCI interrupt requests; the value of INTV0 used during an interrupt acknowledge cycle is supplied by the QSM.
INTV0 is at logic level zero during an SCI interrupt and at logic level one during a QSPI interrupt. A write to INTV0 has no effect. Reads of INTV0 return a value of one.
D.4.4 SCCR0 — SCI Control Register 0 $YFFC08
15
0
RESET:
14
0
0 0
13
0
0
12
0 0 0 0 0 0
SCBR
0 0 0 0 1 0
0
0
SCCR0 contains the SCI baud rate selection field. Baud rate must be set before the
SCI is enabled. The CPU32 can read and write SCCR0 at any time. Changing the value of SCCR0 bits during a transfer operation can disrupt operation.
SCBR — SCI Baud Rate
SCI baud rate is programmed by writing a 13-bit value to this field. Writing a value of zero to SCBR disables the baud rate generator. Baud clock rate is calculated as follows:
D
D.4.5 SCCR1 — SCI Control Register 1
$YFFC0A
15
0
14 13
LOOPS WOMS
RESET:
0 0 0
12
ILT
0
11 10 9
PT PE M
0 0 0
8
WAKE
0
7
TIE
0
6
TCIE
0
5
RIE
0
4
ILIE
0
3
TE
0
2
RE
0
1
RWU
0
SBK
0 0
SCCR1 contains SCI configuration parameters, including transmitter and receiver enable bits, interrupt enable bits, and operating mode enable bits. The CPU can read and write SCCR0 at any time. The SCI can modify the RWU bit under certain circumstances. Changing the value of SCCR1 bits during a transfer operation can disrupt operation.
LOOPS — Loop Mode
0 = Normal SCI operation, no looping, feedback path disabled
1 = Test SCI operation, looping, feedback path enabled
WOMS — Wired-OR Mode for SCI Pins
0 = If configured as an output, TXD is a normal CMOS output.
1 = If configured as an output, TXD is an open-drain output.
ILT — Idle-Line Detect Type
0 = Short idle-line detect (start count on first one)
1 = Long idle-line detect (start count on first one after stop bit(s))
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PT — Parity Type
0 = Even parity
1 = Odd parity
PE — Parity Enable
0 = SCI parity disabled
1 = SCI parity enabled
M — Mode Select
0 = 10-bit SCI frame
1 = 11-bit SCI frame
WAKE — Wakeup by Address Mark
0 = SCI receiver awakened by idle-line detection
1 = SCI receiver awakened by address mark (last bit set)
TIE — Transmit Interrupt Enable
0 = SCI TDRE interrupts inhibited
1 = SCI TDRE interrupts enabled
TCIE — Transmit Complete Interrupt Enable
0 = SCI TC interrupts inhibited
1 = SCI TC interrupts enabled
RIE — Receiver Interrupt Enable
0 = SCI RDRF and OR interrupts inhibited
1 = SCI RDRF and OR interrupts enabled
ILIE — Idle-Line Interrupt Enable
0 = SCI IDLE interrupts inhibited
1 = SCI IDLE interrupts enabled
TE — Transmitter Enable
0 = SCI transmitter disabled (TXD pin can be used as I/O)
1 = SCI transmitter enabled (TXD pin dedicated to SCI transmitter)
RE — Receiver Enable
0 = SCI receiver disabled (status bits inhibited)
1 = SCI receiver enabled
RWU — Receiver Wakeup
0 = Normal receiver operation (received data recognized)
1 = Wakeup mode enabled (received data ignored until awakened)
SBK — Send Break
0 = Normal operation
1 = Break frame(s) transmitted after completion of current frame
D-28
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D.4.6 SCSR — SCI Status Register
$YFFC0C
15
NOT USED
9 8
TDRE
7
TC
6 5 4
RDRF RAF IDLE
3
OR
2
NF
1
FE
0
PF
RESET:
1 1 0 0 0 0 0 0 0
SCSR contains flags that show SCI operating conditions. These flags are cleared either by SCI hardware or by a CPU32 read/write sequence. The sequence consists of reading SCSR, then reading or writing SCDR.
If an internal SCI signal for setting a status bit comes after the CPU32 has read the asserted status bits, but before the CPU has written or read SCDR, the newly set status bit is not cleared. SCSR must be read again with the bit set and SCDR must be written or read before the status bit is cleared.
A long-word read can consecutively access both SCSR and SCDR. This action clears receive status flag bits that were set at the time of the read, but does not clear TDRE or TC flags. Reading either byte of SCSR causes all 16 bits to be accessed, and any status bit already set in either byte are cleared on a subsequent read or write of register SCDR.
TDRE — Transmit Data Register Empty
0 = Register TDR still contains data to be sent to the transmit serial shifter.
1 = A new character can now be written to register TDR.
TC — Transmit Complete
0 = SCI transmitter is busy.
1 = SCI transmitter is idle.
RDRF — Receive Data Register Full
0 = Register RDR is empty or contains previously read data.
1 = Register RDR contains new data.
RAF — Receiver Active
0 = SCI receiver is idle.
1 = SCI receiver is busy.
IDLE — Idle-Line Detected
0 = SCI receiver did not detect an idle-line condition.
1 = SCI receiver detected an idle-line condition.
OR — Overrun Error
0 = RDRF is cleared before new data arrives.
1 = RDRF is not cleared before new data arrives.
NF — Noise Error Flag
0 = No noise detected on the received data
1 = Noise occurred on the received data.
D
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FE — Framing Error
0 = No framing error on the received data
1 = Framing error or break occurred on the received data.
PF — Parity Error
0 = No parity error on the received data
1 = Parity error occurred on the received data.
D.4.7 SCDR — SCI Data Register
$YFFC0E
D
15
0
RESET:
14
0
0 0
13
0
12
0
11
0
10
0
9
0
8 7 6 5 4 3 2 1 0
R8/T8 R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0
0 0 0 0 0 U U U U U U U U U
SCDR consists of two data registers located at the same address. RDR is a read-only register that contains data received by the SCI serial interface. Data comes into the receive serial shifter and is transferred to RDR. TDR is a write-only register that contains data to be transmitted. Data is first written to TDR, then transferred to the transmit serial shifter, where additional format bits are added before transmission. R[7:0]/T[7:0] contain either the first eight data bits received when SCDR is read, or the first eight data bits to be transmitted when SCDR is written. R8/T8 are used when the SCI is configured for 9-bit operation. When the SCI is configured for 8-bit operation, R8/T8 have no meaning or effect.
D.4.8 PORTQS — Port QS Data Register
$YFFC15
15
NOT USED
8 7 6 5 4 3 2 1 0
PQS7 PQS6 PQS5 PQS4 PQS3 PQS2 PQS1 PQS0
0
RESET:
0 0 0 0 0 0 0
PORTQS latches I/O data. Writes drive pins defined as outputs. Reads return data present on the pins. To avoid driving undefined data, first write a byte to PORTQS, then configure DDRQS.
D.4.9 PQSPAR — PORT QS Pin Assignment Register
DDRQS — PORT QS Data Direction Register
$YFFC16
$YFFC17
15
0
RESET:
14 13 12 11
PQSPA6 PQSPA5 PQSPA4 PQSPA3
0 0 0 0 0
10
0
9 8 7 6 5 4 3 2 1 0
PQSPA1 PQSPA0 DDQS7 DDQS6 DDQS5 DDQS4 DDQS3 DDQS2 DDQS1 DDQS0
0 0 0 0 0 0 0 0 0 0 0
Clearing a bit in PQSPAR assigns the corresponding pin to general-purpose I/O; setting a bit assigns the pin to the QSPI. PQSPAR does not affect operation of the SCI.
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Table D-14 PQSPAR Pin Assignments
PQSPAR Field
PQSPA0
PQSPA1
PQSPA2
PQSPA3
PQSPA4
PQSPA5
PQSPA6
PQSPA7
PQSPAR Bit
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Pin Function
PQS0
MISO
PQS1
MOSI
PQS2
1
SCK
PQS3
PCS0/SS
PQS4
PCS1
PQS5
PCS2
PQS6
PCS3
PQS7
2
TXD
1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE in SPCR1 set), in which case it becomes SPI serial clock SCK.
2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE in SCCR1 = 1), in which case it becomes SCI serial output TXD.
DDRQS determines whether pins are inputs or outputs. Clearing a bit makes the corresponding pin an input; setting a bit makes the pin an output. DDRQS affects both
QSPI function and I/O function.
D
Table D-15 Effect of DDRQS on PORTQS Pins
Pin
PQS0
PQS1
PQS2
PQS2
PQS3
PQS4
PQS5
PQS6
PQS7
DDRQS Bit
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Pin Function
Digital Input
Digital Output
Digital Input
Digital Output
Digital Input
Digital Output
Digital Input
Digital Output
Digital Input
Digital Output
Digital Input
Digital Output
Digital Input
Digital Output
Digital Input
Digital Output
Digital Input
Digital Output
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D
Table D-16 Effect of DDRQS on QSM Pin Function
QSM Pin
MISO
MOSI
SCK
PCS0/SS
PCS[3:1]
TXD
RXD
1
2
Mode
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
DDRQS
Bit
DDQS0
DDQS1
DDQS2
DDQS3
DDQS
[4:6]
Transmit DDQS7
Receive None
Bit
State
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
1
0 Inactive
Inactive
Pin Function
Serial Data Input to QSPI
Disables Data Input
Disables Data Output
Serial Data Output from QSPI
Disables Data Output
Serial Data Output from QSPI
Serial Data Input to QSPI
Disables Data Input
Disables Clock Output
Clock Output from QSPI
Clock Input to QSPI
Disables Clock Input
Assertion Causes Mode Fault
Chip-Select Output
QSPI Slave Select Input
Disables Select Input
Disables Chip-Select Output
Chip-Select Output
Serial Data Output from SCI
NA Serial Data Input to SCI
1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE in SPCR1 set), in which case it becomes SPI serial clock SCK.
2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE in SCCR1 =1), in which case it becomes SCI serial output TXD.
DDRQS determines the direction of the TXD pin only when the SCI transmitter is disabled. When the SCI transmitter is enabled, the TXD pin is an output.
D.4.10 SPCR0 — QSPI Control Register 0
$YFFC18
15
MSTR
RESET:
0
14
WOMQ
0
13
BITS
10 9 8
CPOL CPHA
7
SP
0
0 0 0 0 0 1 0 0 0 0 0 1 0 0
SPCR0 contains parameters for configuring the QSPI and enabling various modes of operation. The CPU has read/write access to SPCR0, but the QSM has read access only. SPCR0 must be initialized before QSPI operation begins. Writing a new value to
SPCR0 while the QSPI is enabled disrupts operation.
MSTR — Master/Slave Mode Select
0 = QSPI is a slave device.
1 = QSPI is system master.
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WOMQ — Wired-OR Mode for QSPI Pins
0 = Outputs have normal MOS drivers.
1 = Pins designated for output by DDRQS have open-drain drivers.
BITS — Bits Per Transfer
The BITS field determines the number of serial data bits transferred.
CPOL — Clock Polarity
0 = The inactive state value of SCK is logic level zero.
1 = The inactive state value of SCK is logic level one.
CPHA — Clock Phase
0 =Data captured on the leading edge of SCK and changed on the following edge of SCK.
1 =Data is changed on the leading edge of SCK and captured on the following edge of SCK.
SPBR — Serial Clock Baud Rate
QSPI baud rate is selected by writing a value from 2 to 255 into SPBR. Giving BR a value of zero or one disables SCK (disable state determined by CPOL).
$YFFC1A
D
D.4.11 SPCR1 — QSPI Control Register 1
15
SPE
RESET:
14
0 0 0 0
DSCKL
0 1 0
8
0
7
0 0 0 0
DTL
0 1 0
0
0
SPCR1 enables the QSPI and specified transfer delays. The CPU32 has read/write access to SPCR1, but the QSM has read access only to all bits but enable bit SPE.
SPCR1 must be written last during initialization because it contains SPE. Writing a new value to SPCR1 while the QSPI is enabled disrupts operation.
SPE — QSPI Enable
0 = QSPI is disabled. QSPI pins can be used for general-purpose I/O.
1 = QSPI is enabled. Pins allocated by PQSPAR are controlled by the QSPI.
DSCKL — Delay before SCK
When the DSCK bit in command RAM is set, this field determines the length of delay from PCS valid to SCK transition. PCS can be any of the four peripheral chip-select pins.
DTL — Length of Delay after Transfer
When the DT bit in command RAM is set, this field determines the length of delay after serial transfer.
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D.4.12 SPCR2 — QSPI Control Register 2
$YFFC1C
D
15
SPIFIE
RESET:
14
WREN
0 0
13
WRTO
0
12
0
0
11
0 0
ENDQP
0
8
0
7
0
0
6
0
0
5
0
0
4
0
0
3
0 0
NEWQP
0
0
0
SPCR2 contains QSPI queue pointers, wraparound mode control bits, and an interrupt enable bit. The CPU32 has read/write access to SPCR2, but the QSM has read access only. SPCR2 is buffered. New SPCR2 values become effective only after completion of the current serial transfer. Rewriting NEWQP in SPCR2 causes execution to restart at the designated location. SPCR2 reads return the value of the register, not the buffer.
SPIFIE — SPI Finished Interrupt Enable
0 = QSPI interrupts disabled
1 = QSPI interrupts enabled
WREN — Wrap Enable
0 = Wraparound mode disabled
1 = Wraparound mode enabled
WRTO — Wrap To
0 = Wrap to pointer address $0
1 = Wrap to address in NEWQP
ENDQP — Ending Queue Pointer
This field contains the last QSPI queue address.
NEWQP — New Queue Pointer Value
This field contains the first QSPI queue address.
D.4.13 SPCR3 — QSPI Control Register 3
SPSR — QSPI Status Register
$YFFC1E
$YFFC1F
15
0
RESET:
14
0
0 0
13
0
12
0
11
0
10 9 8 7
LOOPQ HMIE HALT SPIF
6
MODF
5
HALTA
4
0
3
CPTQP
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPCR3 contains the loop mode enable bit, halt and mode fault interrupt enables, and the halt control bit. The CPU has read/write access to SPCR3, but the QSM has read access only. SPCR3 must be initialized before QSPI operation begins. Writing a new value to SPCR3 while the QSPI is enabled disrupts operation. SPSR contains information concerning the current serial transmission. Only the QSPI can set bits in SPSR.
The CPU reads SPSR to obtain QSPI status information and writes it to clear status flags.
D-34
REGISTER SUMMARY
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LOOPQ — QSPI Loop Mode
0 = Feedback path disabled
1 = Feedback path enabled
HMIE — HALTA and MODF Interrupt Enable
0 = HALTA and MODF interrupts disabled
1 = HALTA and MODF interrupts enabled
HALT — Halt
0 = Halt not enabled
1 = Halt enabled
SPIF — QSPI Finished Flag
0 = QSPI not finished
1 = QSPI finished
MODF — Mode Fault Flag
0 =Normal operation
1 =Another SPI node requested to become the network SPI master while the QSPI was enabled in master mode (SS input taken low).
HALTA — Halt Acknowledge Flag
0 = QSPI not halted
1 = QSPI halted
CPTQP — Completed Queue Pointer
CPTQP points to the last command executed. It is updated when the current command is complete. When the first command in a queue is executing, CPTQP contains either the reset value ($0) or a pointer to the last command completed in the previous queue.
D
D.4.14 RR[0:F] — Receive Data RAM
$YFFD00–$YFFD0E
Data received by the QSPI is stored in this segment. The CPU32 reads this segment to retrieve data from the QSPI. Data stored in receive RAM is right-justified. Unused bits in a receive queue entry are set to zero by the QSPI upon completion of the individual queue entry. The CPU can access the data using byte, word, or long-word addressing.
D.4.15 TR[0:F] — Transmit Data RAM $YFFD20–$YFFD3E
Data that is to be transmitted by the QSPI is stored in this segment. The CPU32 normally writes one word of data into this segment for each queue command to be executed.
Information to be transmitted must be written to transmit data RAM in a right-justified format. The QSPI cannot modify information in the transmit data RAM. The QSPI copies the information to its data serializer for transmission. Information remains in transmit RAM until overwritten.
MC68331
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D-35
Freescale Semiconductor, Inc.
D.4.16 CR[0:F] — Command RAM
$YFFD40–$YFFD4F
7
CONT
—
CONT
6
BITSE
—
BITSE
5
DT
—
DT
4
DSCK
—
DSCK
3
PCS3
—
PCS3
2
PCS2
—
PCS2
1
PCS1
—
PCS1
0
PCS0*
—
PCS0*
D
COMMAND CONTROL PERIPHERAL CHIP SELECT
*The PCS0 bit represents the dual-function PCS0/SS.
Command RAM is used by the QSPI when in master mode. The CPU32 writes one byte of control information to this segment for each QSPI command to be executed.
The QSPI cannot modify information in command RAM.
Command RAM consists of 16 bytes. Each byte is divided into two fields. The peripheral chip-select field enables peripherals for transfer. The command control field provides transfer options.
A maximum of 16 commands can be in the queue. Queue execution proceeds from the address in NEWQP through the address in ENDQP (both of these fields are in
SPCR2).
CONT — Continue
0 = Control of chip selects returned to PORTQS after transfer is complete.
1 = Peripheral chip selects remain asserted after transfer is complete.
BITSE — Bits per Transfer Enable
0 = Eight bits
1 = Number of bits set in BITS field of SPCR0
DT — Delay after Transfer
The QSPI provides a variable delay at the end of serial transfer to facilitate interfacing with peripherals that have a latency requirement. The delay between transfers is determined by the SPCR1 DTL field.
DSCK — PCS to SCK Delay
0 = PCS valid to SCK transition is one-half SCK.
1 = SPCR1 DSCKL field specifies delay from PCS valid to SCK.
PCS[3:0] — Peripheral Chip Select
Peripheral chip-select bits are used to select an external device for serial data transfer.
More than one peripheral chip select may be activated at a time, and more than one peripheral chip can be connected to each PCS pin, provided proper fanout is observed. PCS0 shares a pin with the slave select (SS) signal, which initiates slave mode serial transfer. If SS is taken low when the QSPI is in master mode, a mode fault occurs.
D-36
REGISTER SUMMARY
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USER’S MANUAL
Freescale Semiconductor, Inc.
S
S/U
S/U
S/U
S
S/U
S/U
S/U
S
S
Access
S
S
S
S
S
S
S
S
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
Access
S
S
S
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
Table D-17 MC68331 Module Address Map
(Assumes SIMCR MM = 1)
$FFFA0A
$FFFA0C
$FFFA0E
$FFFA10
$FFFA12
$FFFA14
$FFFA16
$FFFA18
$FFFA1A
$FFFA1C
$FFFA1E
$FFFA20
GPT
Address 15 8 7 0
$FFF900 GPT MODULE CONFIGURATION (GPTMCR)
$FFF902
$FFF904
$FFF906
$FFF908
(RESERVED FOR TEST)
INTERRUPT CONFIGURATION (ICR)
PGP DATA DIRECTION (DDRGP)
OC1 ACTION MASK (OC1M)
PGP DATA (PORTGP)
OC1 ACTION DATA (OC1D)
$FFF90A
$FFF90C
$FFF90E
$FFF910
$FFF912
$FFF914
$FFF916
$FFF918
TIMER COUNTER (TCNT)
PA CONTROL (PACTL) PA COUNTER (PACNT)
INPUT CAPTURE 1 (TIC1)
INPUT CAPTURE 2 (TIC2)
INPUT CAPTURE 3 (TIC3)
OUTPUT COMPARE 1 (TOC1)
OUTPUT COMPARE 2 (TOC2)
OUTPUT COMPARE 3 (TOC3)
$FFF91A
$FFF91C
$FFF91E
$FFF920
$FFF922
$FFF924
$FFF926
$FFF928
OUTPUT COMPARE 4 (TOC4)
INPUT CAPTURE 4/OUTPUT COMPARE 5 (TI4/O5)
TIMER CONTROL 1 (TCTL1)
TIMER MASK 1 (TMSK1)
TIMER CONTROL 2 (TCTL2)
TIMER MASK 2 (TMSK2)
TIMER FLAG 1 (TFLG1)
FORCE COMPARE (CFORC)
TIMER FLAG 2 (TFLG2)
PWM CONTROL C (PWMC)
PWM CONTROL A (PWMA) PWM CONTROL B (PWMB)
PWM COUNT (PWMCNT)
$FFF92A
$FFF92C
$FFF92E –
$FFF93F
PWMA BUFFER (PWMBUFA) PWMB BUFFER (PWMBUFB)
GPT PRESCALER (PRESCL)
NOT USED
SIM
Address 15 8 7 0
$FFFA00 MODULE CONFIGURATION (SIMCR)
$FFFA02
$FFFA04
$FFFA06
$FFFA08
FACTORY TEST (SIMTR)
CLOCK SYNTHESIZER CONTROL (SYNCR)
NOT USED RESET STATUS (RSR)
MODULE TEST E (SIMTRE)
$FFFA22
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
PORTE DATA (PORTE0)
PORTE DATA (PORTE1)
PORTE DATA DIRECTION (DDRE)
PORTE PIN ASSIGNMENT (PEPAR)
PORTF DATA (PORTF0)
NOT USED
NOT USED
NOT USED
NOT USED
PORTF DATA (PORTF1)
PORTF DATA DIRECTION (DDRF)
PORTF PIN ASSIGNMENT (PFPAR)
SYSTEM PROTECTION CONTROL
(SYPCR)
PERIODIC INTERRUPT CONTROL (PICR)
D
MC68331
USER’S MANUAL
REGISTER SUMMARY
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D-37
D
Freescale Semiconductor, Inc.
S/U
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
Access
S
S
S
S
S
S
S
S
S
S
S
S/U
Table D-17 MC68331 Module Address Map, (Continued)
(Assumes SIMCR MM = 1)
$FFFA5E
$FFFA60
$FFFA62
$FFFA64
$FFFA66
$FFFA68
$FFFA6A
$FFFA6C
$FFFA6E
$FFFA70
$FFFA72
$FFFA74
$FFFA76
$FFFA78
$FFFA7A
$FFFA7C
$FFFA7E
$FFFA3E
$FFFA40
$FFFA42
$FFFA44
$FFFA46
$FFFA48
$FFFA4A
$FFFA4C
$FFFA4E
$FFFA50
$FFFA52
$FFFA54
$FFFA56
$FFFA58
$FFFA5A
$FFFA5C
SIM (Continued)
Address 15 8 7 0
$FFFA24 PERIODIC INTERRUPT TIMING (PITR)
$FFFA26
$FFFA28
$FFFA2A
$FFFA2C
NOT USED
NOT USED
NOT USED
NOT USED
SOFTWARE SERVICE (SWSR)
NOT USED
NOT USED
NOT USED
$FFFA2E
$FFFA30
$FFFA32
$FFFA34
$FFFA36
$FFFA38
$FFFA3A
$FFFA3C
NOT USED NOT USED
TEST MODULE MASTER SHIFT A (TSTMSRA)
TEST MODULE MASTER SHIFT B (TSTMSRB)
TEST MODULE SHIFT COUNT (TSTSC)
TEST MODULE REPETITION COUNTER (TSTRC)
TEST MODULE CONTROL (CREG)
TEST MODULE DISTRIBUTED (DREG)
NOT USED NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
PORT C DATA (PORTC)
NOT USED
CHIP-SELECT PIN ASSIGNMENT (CSPAR0)
CHIP-SELECT PIN ASSIGNMENT (CSPAR1)
CHIP-SELECT BASE BOOT (CSBARBT)
CHIP-SELECT OPTION BOOT (CSORBT)
CHIP-SELECT BASE 0 (CSBAR0)
CHIP-SELECT OPTION 0 (CSOR0)
CHIP-SELECT BASE 1 (CSBAR1)
CHIP-SELECT OPTION 1 (CSOR1)
CHIP-SELECT BASE 2 (CSBAR2)
CHIP-SELECT OPTION 2 (CSOR2)
CHIP-SELECT BASE 3 (CSBAR3)
CHIP-SELECT OPTION 3 (CSOR3)
CHIP-SELECT BASE 4 (CSBAR4)
CHIP-SELECT OPTION 4 (CSOR4)
CHIP-SELECT BASE 5 (CSBAR5)
CHIP-SELECT OPTION 5 (CSOR5)
CHIP-SELECT BASE 6 (CSBAR6)
CHIP-SELECT OPTION 6 (CSOR6)
CHIP-SELECT BASE 7 (CSBAR7)
CHIP-SELECT OPTION 7 (CSOR7)
CHIP-SELECT BASE 8 (CSBAR8)
CHIP-SELECT OPTION 8 (CSOR8)
CHIP-SELECT BASE 9 (CSBAR9)
CHIP-SELECT OPTION 9 (CSOR9)
CHIP-SELECT BASE 10 (CSBAR10)
CHIP-SELECT OPTION 10 (CSOR10)
NOT USED NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
D-38
REGISTER SUMMARY
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MC68331
USER’S MANUAL
Freescale Semiconductor, Inc.
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
Access
S
S
S
S/U
S/U
S/U
S/U
Table D-17 MC68331 Module Address Map, (Continued)
(Assumes SIMCR MM = 1)
QSM
Address 15 8 7 0
$FFFC00 QSM MODULE CONFIGURATION (QSMCR)
$FFFC02
$FFFC04
$FFFC06
$FFFC08
QSM TEST (QTEST)
QSM INTERRUPT LEVEL (QILR) QSM INTERRUPT VECTOR (QIVR)
NOT USED
SCI CONTROL 0 (SCCR0)
$FFFC0A
$FFFC0C
$FFFC0E
$FFFC10
$FFFC12
$FFFC14
$FFFC16
$FFFC18
$FFFC1A
$FFFC1C
$FFFC1E
$FFFC20–
$FFFCFF
$FFFD00–
$FFFD1F
NOT USED
SCI CONTROL 1 (SCCR1)
SCI STATUS (SCSR)
SCI DATA (SCDR)
NOT USED
NOT USED
PQS PIN ASSIGNMENT (PQSPAR)
NOT USED
PQS DATA (PORTQS)
PQS DATA DIRECTION (DDRQS)
SPI CONTROL 0 (SPCR0)
SPI CONTROL 1 (SPCR1)
SPI CONTROL 2 (SPCR2)
SPI CONTROL 3 (SPCR3) SPI STATUS (SPSR)
RECEIVE RAM (RR[0:F]) S/U
QUEUE
RAM
S/U
QUEUE
RAM
S/U
QUEUE
RAM
$FFFD20–
$FFFD3F
$FFFD40–
$FFFD4F
TRANSMIT RAM (TR[0:F])
COMMAND RAM (CR[0:F])
D
MC68331
USER’S MANUAL
REGISTER SUMMARY
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D-39
D
D-40
Freescale Semiconductor, Inc.
Table D-18 Register Bit and Field Mnemonics
CSPA0[6:1]
CSPA1[4:0]
CSBOOT
DDE[7:0]
DDF[7:0]
DDRGP[7:0]
DDQS[7:0]
DSACK
DSCK
DSCKL
DT
DTL
EDGE[4:1]
EDIV
ENDQP
EXOFF
Mnemonic
ADDR[23:11]
AVEC
BITS
BITSE
BLKSZ
BME
BMT[1:0]
BYTE
C
CONT
CPHA
CPOL
CPROUT
CPR[2:0]
CPTQP
EXT
F1A
F1B
FE
FOC[5:1]
FPWMA
FPWMB
FRZBM
FRZSW
FRZ[1:0]
FRZ[1:0]
HALT
HALTA
HLT
HME
HMIE
Name
Base Address
Autovector Enable
Bits Per Transfer
Bits Per Transfer Enable
Block Size
Bus Monitor External Enable
Bus Monitor Timing
Upper/Lower Byte Option
Carry Flag
Continue
Clock Phase
Clock Polarity
Capture/Compare Clock Output Enable
Timer Prescaler/PCLK Select Field
Completed Queue Pointer
Chip-Select [6:1]
Chip-Select [4:0]
Boot ROM Chip Select
Port E Data Direction
Port F Data Direction
Port GP Data Direction
Port QS Data Direction
Data Strobe Acknowledge
PCS to SCK Delay
Delay Before SCK
Delay After Transfer
Length of Delay After Transfer
Input Capture Edge Control
ECLK Divide Rate
Ending Queue Pointer
External Clock Off
External Reset
Force Logic Level One on PWMA
Force Logic Level One on PWMB
Framing Error
Force Output Compare
Force PWMA Value
Force PWMB Value
Freeze Bus Monitor Enable
Freeze Software Enable
Freeze Response
Freeze1
Halt
Halt Acknowledge Flag
Halt Monitor Reset
Halt Monitor Enable
HALTA and MODF Interrupt Enable
Register Location
CSBAR[0:10], CSBARBT
CSOR[0:10], CSORBT
SPCR0
CR[0:F]
CSBAR[0:10], CSBARBT
SYPCR
SYPCR
CSOR[0:10], CSORBT
CCR
CR[0:F]
SPCR0
SPCR0
TMSK2
TMSK2
SPSR
CSPAR0
CSPAR1
CSPAR0
DDRE
DDRF
DDRGP
DDRQS
CSOR[0:10], CSORBT
CR[0:F]
SPCR1
CR[0:F]
SPCR1
TCTL2
SYNCR
SPCR2
SIMCR
RSR
PWMC
PWMC
SCSR
CFORC
CFORC
CFORC
SIMCR
SIMCR
GPTMCR
QSMCR
SPCR3
SPSR
RSR
SYPCR
SPCR3
REGISTER SUMMARY
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MC68331
USER’S MANUAL
Freescale Semiconductor, Inc.
LOC
LOOPQ
LOOPS
M
MM
MODE
MODF
MSTR
N
NEWQP
NF
OC1D[5:1]
OC1M[5:1]
OCF[4:1]
OCI[4:1]
OM[5:2]
OL[5:2]
OR
PACLK[1:0]
I4/O5I
IARB[3:0]
ICF[3:1]
ICI[3:1]
IDLE
ILIE
ILQSPI
ILSCI
ILT
INCP
INTV[7:0]
IP[2:0]
IPA
IPL
IVBA
Table D-18 Register Bit and Field Mnemonics, (Continued)
Mnemonic
I4/O5
I4/O5F
PACNT
PAEN
PAIF
PAII
PAIS
PAMOD
PAOVF
PAOVI
PC[6:0]
Name
Input Capture 4/Output Compare 5
Input Capture 4/Output Compare 5
Flag
I4/O5 Interrupt Enable
Interrupt Arbitration
Input Capture Flags
Input Capture Interrupt Enable
Idle-Line Detected
Idle-Line Interrupt Enable
Interrupt Level for QSPI
Interrupt Level for SCI
Idle-Line Detect Type
Increment Prescaler
Interrupt Vector Number
Interrupt Priority Mask
Interrupt Priority Adjust
Interrupt Priority Level
Interrupt Vector Base Address
Loss of Clock Reset
QSPI Loop Mode
Loop Mode
Mode Select
Module Mapping
Asynchronous/Synchronous Mode
Mode Fault Flag
Master/Slave Mode Select
Negative Flag
New Queue Pointer Value
Noise Error
OC1 Data
OC1 Mask
Output Compare Flags
Output Compare Interrupt Enable
Output Compare Mode Bits
Output Compare Level Bits
Overrun Error
Pulse Accumulator Clock Select
(Gated Mode)
Pulse Accumulator Counter
Pulse Accumulator Enable
Pulse Accumulator Flag
Pulse Accumulator Input Interrupt
Enable
PAI Pin State (Read Only)
Pulse Accumulator Mode
Pulse Accumulator Overflow Flag
Pulse Accumulator Overflow Interrupt
Enable
Port C Data
Register Location
PACNT
TFLG1
PACNT
PACNT
TFLG2
TMSK2
PACNT
PACNT
TFLG2
TMSK2
PORTC
TMSK1
GPTMCR, QSMCR, SIMCR
TFLG1
TMSK1
SCSR
SCCR1
QILR
QILR
SCCR1
GPTMCR
QIVR
SR
ICR
CSOR[0:10], CSORBT, ICR
ICR
RSR
SPCR3
SCCR1
SCCR1
SIMCR
CSOR[0:10], CSORBT
SPSR
SPCR0
CCR
SPCR2
SCSR
OC1D
OC1M
TFLG1
TMSK1
TCTL1
TCTL1
SCSR
PACNT
MC68331
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D-41
D
D
D-42
Freescale Semiconductor, Inc.
Table D-18 Register Bit and Field Mnemonics, (Continued)
POW
PPROUT
PPR[2:0]
PQS[7:0]
PQSPA[6:0]
PT
PTP
RAF
RDRF
RE
RIE
RR[0:F]
RSTEN
R/W
RWU
R[8:0]/T[8:0]
Mnemonic
PCLKS
PCS[3:0]
PE
PE[7:0]
PEDGE
PEPA[7:0]
PF
PF[7:0]
PFPA[7:0]
PORTGP[7:0]
PIRQL[2:0]
PITM[7:0]
PIV[7:0]
S
SBK
SCBR
SFA
SFB
SHEN[1:0]
SLIMP
SLOCK
SLVEN
SPACE
SPBR
SPE
SPIF
SPIFIE
STEXT
STOP
STOP
STOPP
STRB
Name
PCLK Pin State (Read Only)
Peripheral Chip Select
Parity Enable
Port E Data
Pulse Accumulator Edge Control
Port E Pin Assignment
Parity Error
Port F Data
Port F Pin Assignment
Port GP Data
Periodic Interrupt Request Level
Periodic Interrupt Timing Modulus
Periodic Interrupt Vector
Power-Up Reset
PWM Clock Output Enable
PWM Prescaler/PCLK Select
Port QS Data
Port QS Pin Assignment
Parity Type
Periodic Timer Prescaler Control
Receiver Active
Receive Data Register Full
Receiver Enable
Receiver Interrupt Enable
Receive Data RAM
Reset Enable
Read/Write
Receiver Wakeup
SCI Receive/Transmit Data
Supervisor/User State
Send Break
SCI Baud Rate
PWMA Slow/Fast Select
PWMB Slow/Fast Select
Show Cycle Enable
LIMP Mode
Synthesizer Lock
Factory Test Mode Enabled
Address Space Select
Serial Clock Baud Rate
QSPI Enable
QSPI Finished Flag
SPI Finished Interrupt Enable
Stop Mode External Clock
Stop Clocks
Stop Enable
Stop Prescaler
Address Strobe/Data Strobe
Register Location
PACNT
CR[0:F]
SCCR1
PORTE
PACNT
PEPAR
SCSR
PORTF
PFPAR
PORTGP
PICR
PITR
PICR
RSR
PWMC
PWMC
PORTQS
PQSPAR
SCCR1
PITR
SCSR
SCSR
SCCR1
SCCR1
QSPI RAM
SYNCR
CSOR[0:10], CSORBT
SCCR1
SCDR
SR
SCCR1
SCCR0
PWMC
PWMC
SIMCR
SYNCR
SYNCR
SIMCR
CSOR[0:10], CSORBT
SPCR0
SPCR1
SPSR
SPCR2
SYNCR
GPTMCR
QSMCR
GPTMCR
CSOR[0:10], CSORBT
REGISTER SUMMARY
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MC68331
USER’S MANUAL
Freescale Semiconductor, Inc.
Table D-18 Register Bit and Field Mnemonics, (Continued)
TOF
TOI
TR[0:F]
TST
V
W
WAKE
WOMQ
WOMS
WREN
WRTO
X
X
Y[5:0]
Z
Mnemonic
STSIM
SUPV
SW
SWE
SWP
SWT[1:0]
SYS
T[1:0]
TC
TCIE
TDRE
TE
TIE
Name
Stop Mode System Integration Clock
Supervisor/Unrestricted
Software Watchdog Reset
Software Watchdog Enable
Software Watchdog Prescale
Software Watchdog Timing
System Reset
Trace Enable
Transmit Complete
Transmit Complete Interrupt Enable
Transmit Data Register Empty
Transmitter Enable
Transmit Interrupt Enable
Timer Overflow Flag
Timer Overflow Interrupt Enable
Transmit Data RAM
Test Submodule Reset
Overflow Flag
Frequency Control (VCO)
Wakeup by Address Mark
Wired-OR Mode for QSPI Pins
Wired-OR Mode for SCI Pins
Wrap Enable
Wrap To
Extend
Frequency Control Bit (Prescale)
Frequency Control (Counter)
Zero Flag
Register Location
SYNCR
GPTMCR, QSMCR, SIMCR
RSR
SYPCR
SYPCR
SYPCR
RSR
SR
SCSR
SCCR1
SCSR
SCCR1
SCCR1
TFLG2
TMSK2
QSPI RAM
RSR
CCR
SYNCR
SCCR1
SPCR0
SCCR1
SPCR2
SPCR2
CCR
SYNCR
SYNCR
CCR
D
MC68331
USER’S MANUAL
REGISTER SUMMARY
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D-43
D
Freescale Semiconductor, Inc.
D-44
REGISTER SUMMARY
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MC68331
USER’S MANUAL
Freescale Semiconductor, Inc.
INDEX
MC68331
USER’S MANUAL
INDEX
For More Information On This Product,
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I-1
Freescale Semiconductor, Inc.
I-2
INDEX
For More Information On This Product,
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MC68331
USER’S MANUAL
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