STMicroelectronics L99MM70XP Datasheet
Reklama
Reklama
L99MM70XP
Integrated microprocessor driven device intended for LIN controlled exterior mirrors
Features
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5 V low-drop voltage regulator (150 mA max.)
Embedded LIN transceiver: 2.0/2.1 compliant and SAEJ2602 compatible
Independent control of mirror adjustment motors
One full bridge for 3 A load (R on
= 300 m
)
Two (three) half bridges for 0.5 A load
(R on
= 1.6
)
One configurable high-side driver for up to
1.5 A load (R on
= 500 m
/ 10 Watt bulb control, or 1600 m
/ LED control)
Two high-side driver for 0.5 A load
(R on
= 1600 m
)
One low-side driver 0.5 A load
(R on
= 1600 m
) used as half bridge with highside driver for independent mirror axis control
One high-side driver for 6 A load
(R on
= 90 m
)
One high-side driver for 0.5 A load
(R on
= 1600 m
) to supply an external
MOSFET to drive an EC-glass
Integrated EC glass control via an external
MOSFET with fast discharge path: EC-glass can be discharged to GND or to -1 V
Programmable soft start function to drive loads with higher inrush currents (>6 A, >1.5 A)
Very low current consumption modes
All outputs short-circuit and overtemperature protected
Two thermal shutdown thresholds and early temperature warning
Current monitor output for all high-side drivers
Open-load diagnostic for all outputs
Overload diagnostic for all outputs
3 PWM control signals for all outputs
PowerSSO-36
■
■
■
Charge pump output for active reverse polarity protection via an external N-channel MOSFET
STM standard serial peripheral interface for control and diagnosis
INH input for external CAN transceiver
Applications
■ LIN controlled mirror
Description
The L99MM70XP is a microcontroller driven multifunctional system ASSP dedicated for LIN controlled wing mirror applications. The device contains a voltage regulator to supply the microcontroller and a LIN2.1 physical layer. Up to
3 DC motors and five grounded resistive loads can independently be driven with four (five) half bridges and five high-side driver. The EC-glass control block provides overvoltage protection with a fast discharge path versus GND and a negative discharge path for future EC-glass characteristics.
The integrated ST SPI controls all operation modes (forward, reverse, brake and highimpedance) and provides all the diagnostic information.
Table 1.
Package
Device summary
Order codes
Tube Tape and reel
PowerSSO-36 L99MM70XP L99MM70XPTR
September 2013 Doc ID 022637 Rev 2 1/68 www.st.com
1
Contents
Contents
L99MM70XP
Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power control in operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functional overview (truth table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Output drivers OUT1 … OUT9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Cross current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Programmable soft start function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Controller for electrochromic glass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Wake-up (from LIN bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Serial peripheral interface (ST SPI standard) . . . . . . . . . . . . . . . . . . . . . . 23
Protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/68 Doc ID 022637 Rev 2
L99MM70XP
Contents
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 28
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Supply and supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SREG
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
CC
supervision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Current monitor output CM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Charge pump output CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Outputs OUT1 – OUT9, ECV, ECFD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Electrochrome control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Input PWM2 for Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SPI control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Doc ID 022637 Rev 2 3/68
Contents
L99MM70XP
Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SPI communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Operation code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Package and packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
PowerSSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4/68 Doc ID 022637 Rev 2
L99MM70XP
List of tables
List of tables
SREG
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
supervision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Doc ID 022637 Rev 2 5/68
List of tables L99MM70XP
6/68 Doc ID 022637 Rev 2
L99MM70XP
List of figures
List of figures
Electrochrome mirror driver with mirror referenced to ECFD for negative discharge . . . . . 42
Doc ID 022637 Rev 2 7/68
Block diagram L99MM70XP
Figure 1.
Block diagram
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8/68 Doc ID 022637 Rev 2
L99MM70XP
2 Pin definitions and functions
Pin definitions and functions
Table 2.
Pin
Pin definition and functions
Symbol Function
1, 18,
19, 36
2, 7, 32 V
S
(Power1)
22
3, 4
GND
V
S
(Power2)
OUT9
Ground: reference potential
Note: For the capability of driving the full current at the outputs all pins of GND must be externally connected!
Power supply voltage for outputs OUTX and ECFD (external reverse protection required): for this input a ceramic capacitor as close as possible to GND is recommended.
Note: For the capability of driving the full current at the outputs all pins of V
S
must be externally connected! Pins 2, 7 and 32 are internally connected, too. Pin 22 is the power supply for outputs OUT4, 5 and 6.
High-side driver output 9: the output is built by a high-side switch and is intended for resistive loads, hence the internal reverse diode from GND to the output is missing.For ESD reason a diode to GND is present but the energy which can be dissipated is limited. The high-side driver is a power DMOS transistor with an internal parasitic reverse diode from the output to V
S
(bulk-drain-diode). The output is overcurrent and open-load protected.
Note: For the capability of driving the full current at the outputs both pins of OUT9 must be externally connected!
35, 5,
6, 21,
20
OUT1, OUT2,
OUT3, OUT4,
OUT5
Half bridge outputs 1,2,3,4,5: the output is built by a high-side and a low-side switch, which are internally connected.
The output stage of both switches is a power DMOS transistor.
Each driver has an internal parasitic reverse diode (bulk drain diode: high-side driver from output to V
S
, low-side driver from GND to output). This output is overcurrent and openload protected.
8
9
CSN
CM
Chip select not input: this input is low active and requires CMOS logic levels. The serial data transfer between the L99MM70XP and the microcontroller is enabled by pulling the input CSN to low-level.
Current monitor output: depending on the selected multiplexer bits of the control register this output sources an image of the instant current through the corresponding high-side driver with a ratio of
1/10000 or 1/2000.
10
11
DO
DI
Serial data output: the diagnosis data is available via the SPI and this 3-state output. The output remains in
3-state, if the chip is not selected by the input CSN (CSN = high).
Serial data input: the input requires CMOS logic levels and receives serial data from the microcontroller.
The data is a 24 bit control word and the most significant bit (MSB, bit 23) is transferred first.
12
13
14
15
CLK
VCC
RXD
TXD
Serial clock input: this input controls the internal shift register of the SPI and requires CMOS logic levels.
Voltage regulator output:
5 V supply e.g. microcontroller, CAN transceiver.
Receiver output of the LIN 2.1 transceiver.
Transmitter input of the LIN 2.1 transceiver
Doc ID 022637 Rev 2 9/68
Pin definitions and functions L99MM70XP
Table 2.
Pin
16
17
23
24
25
26
27
28
29
30
31
33
34
Pin definition and functions (continued)
Symbol
V
S
(Reg)
LIN
OUT6
INH/PWM3
CP
PWM1
NRES
PWM2
ECDR
OUT8
OUT7/EC
ECFD
ECV
Function
Power supply voltage (external reverse protection required): for this input a ceramic capacitor as close as possible to GND and an electrolytic capacitor to buffer the voltage during negative transients is recommended.
LIN bus line
High-side driver output 6:
The output is built by a high-side switch and is intended for resistive loads; hence the internal reverse diode from GND to the output is missing. For ESD reason a diode to GND is present but the energy which can be dissipated is limited.
The high-side driver is a power DMOS transistor with an internal parasitic reverse diode from the output to V
S
(bulk-drain-diode). The output is overcurrent and open-load protected.
Inhibit input: wake-up from external CAN transceiver. This pin has a second functionality. The microcontroller can use the INH signal to provide a third PWM input for the output OUT8.
Charge pump output:
This output is provided to drive the gate of an external n-channel power MOS used for
reverse polarity protection (see Figure 1 ).
PWM1 input:
This input signal can be used to control the drivers OUT1-OUT5, OUT7, and OUT9 by an external PWM signal.
Low active reset output to the microcontroller: internal pull up of typ. 100k
PWM2 input:
This input signal can be used to control the driver OUT6 by an external PWM signal.
ECDR: using the device in EC control mode this pin is used to control the gate of an external MOSFET.
High-side driver output 8: see OUT6
Note: This output can be configured to supply a bulb with low on-resistance or a LED with higher on-resistance in a different application.
High-side driver output 7: see OUT6
Note: Beside the bit 8 in control register 2 this output can be switched on setting bit 0 for electrochrome control mode with higher priority.
ECFD: using the device in EC control mode this pin is used as “virtual GND” for the EC-glass. For
EC-glasses, that require a negative discharge voltage, this supplies the fast discharge voltage. If no EC-glass is used, this pin must be connected to ground.
ECV:
Using the device in EC control mode this pin is used as voltage monitor input. For fast discharge an additional low-side-switch is implemented.
This pin can be used as “stand alone” low-side as well. This output is intended for resistive loads only
10/68 Doc ID 022637 Rev 2
L99MM70XP
Figure 2.
Pin connection (top view)
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Doc ID 022637 Rev 2 11/68
Description
3 Description
L99MM70XP
The L99MM70XP contains a fully protected low drop voltage regulator, which is designed for very fast transient response.
The output voltage is stable with load capacitors > 220 nF.
The voltage regulator provides 5 V supply voltage and up to 100 mA continuous load current for the external digital logic (microcontroller, etc...). In addition the regulator V
CC
drives the
L99MM70XP internal 5 V loads. The voltage regulator is protected against overload and overtemperature. An external reverse current protection has to be provided by the application circuitry to prevent the input capacitor from being discharged by negative transients or low input voltage. The output voltage precision is better than ±2 % (incl. temperature drift and line-/load regulation) for operating mode; respectively ±3 % during low current mode. Current limitation of the regulator ensures fast charge of external bypass capacitors. The output voltage is stable for ceramic load capacitors > 220 nF.
If device temperature exceeds TSD1 threshold, all outputs (OUTx, LIN) are deactivated except V
CC
. Hence the microcontroller has the possibility for interaction or error logging. In case of exceeding TSD2 threshold (TSD2 > TSD1), also V
CC
).
A timer is started and the voltage regulator is deactivated for t
TSD
= 1 s.
During this time, all other wake-up sources (LIN) are disabled. After 1 s, the voltage regulator tries to restart automatically. If the restart fails 6 times without clearing and thermal shutdown condition still exists, the L99MM70XP enters the V
BAT-standby
mode.
In case of short to GND at V
CC
after initial turn on (V
CC
< 2 V for at least 4 ms) the
L99MM70XP enters the V
BAT-standby
mode. Reactivation (wake-up) of the device can be achieved with signals from LIN or INH.
12/68 Doc ID 022637 Rev 2
L99MM70XP
Figure 3.
Voltage regulator operation
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3.2 Power control in operating modes
The L99MM70XP can be operated in 4 different operating modes:
●
●
●
●
Active
Flash
V
V
CC-standby
BAT-standby
All functions are available. After at most 300 µs, the outputs can be enabled.
To disable the watchdog feature a Flash program mode is available. The mode can be entered if the following condition occurs:
V
PWM2
V
Flash
Watchdog is disabled but all other functions are the same as in active mode.
Doc ID 022637 Rev 2 13/68
Description L99MM70XP
Note: “High” level for flash mode selection is V
PWM2
V
Flash standard 5 V logic signals are required.
. For all other operation modes,
3.2.3 V
CC-standby
mode
Outputs and internal loads are switched off. To supply the microcontroller in a low power mode, the voltage regulator (V
CC
) remains active. The intention of the V
CC-standby
mode is to preserve the RAM contents.
A LIN wake-up event sets the device into the active mode and forces the RXD pin to the low-level.
A wake-up over INH switches device in active mode and start the watchdog.
The wake-up via SPI switches device in active mode. A status bit indicates the wake-up source.
During the V
CC-standby
mode, the current at V
CC
is monitored.
The transition from active mode to V
CC-standby
mode is controlled by SPI.
3.2.4 V
BAT-standby
mode
To achieve minimum current consumption during V
BAT-standby functions are switched off.
mode, all L99MM70XP
In V
BAT-standby
mode the current consumption of the L99MM70XP is reduced to 8 µA.
The transition from active mode to V
BAT-standby
mode is controlled by SPI.
14/68
●
●
●
A wake-up from standby mode switches the device to active mode. This can be initiated by one or more of the following sources:
Change of the LIN state at LIN bus interfaces
SPI access in V
CC-standby
mode (CSN is low and first rising edge on CLK)
A current at the INH pin (I > 120 µA) controlled by the CAN-transceiver (the CAN transceiver is not a part of the IC).
Table 3.
Wake-up events
Wake-up source
LIN
INH
V
CC
I
CMP
SPI access
Description
Always active
Always active
Device remains in V
CC-standby
mode with watchdog enabled (If I
CMP
= 0) and V
CC
goes into high current mode (increased current consumption). No interrupt is generated.
Always active (except in V
BAT-standby
mode)
LIN wake-up events in V
CC-standby
mode generate a low-pulse at RXD for 56 µs.
Wake-up from V
CC-standby
by SPI access might be used to check the interrupt service handler.
Doc ID 022637 Rev 2
L99MM70XP
3.4
Description
Functional overview (truth table)
Table 4.
Functional overview (truth table)
Operating modes
Function
Voltage regulator, V
NRES
Window watchdog
CC
Comments
V
V
OUT
CC
= 5 V
monitor
Active mode
On
On
On
V
CC-standby static mode
On
(1)
On
Off (ON if I
CC
> I
CMP and I
CMP
= 0)
Off
(2)
V
BAT-standby static mode
Off
Off
Off
LIN LIN 2.1
On Off
(2)
1.
Supply the processor in low current mode.
2.
The bus state is internally stored when going to standby mode. A change of bus state leads to a wake-up after exceeding of internal filter time.
Doc ID 022637 Rev 2 15/68
Description
Figure 4.
Operating modes, main states
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3.5 Interrupt
In case of V
CC-standby
mode and (I
CC
> I
CMPris
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V
CC
regulator switches to high current mode and the watchdog is started. No interrupt is generated.
16/68 Doc ID 022637 Rev 2
L99MM70XP Description
If bit NINTEN (CR1/Bit5, default value is set) is set, the RXD pin works also as interrupt output in case of wake-up by LIN or INH or SPI in V
CC-standby
mode. This pin is pulled down for 56 µs.
If it is not set, RXD is pulled down for 56us only for LIN wake-up.
During normal operation, the watchdog monitors the microcontroller within a 100 ms trigger cycle.
In V
BAT-standby
and flash program modes, the watchdog circuit is automatically disabled.
After power on or standby mode, the watchdog is started immediately with the normal cycle time (100 ms). The microcontroller has to run its own setup and then to trigger the watchdog via the SPI. The trigger is finally accepted when the CSN input becomes high after the transmission of the SPI word.
Writing ‘1’ to the watchdog trigger bit restarts the watchdog. Subsequently, the microcontroller has to serve the watchdog by alternating the watchdog trigger bit within the safe trigger area (refer to
). A correct watchdog trigger signal immediately starts the next cycle.
If the micro does not serve the watchdog in time, the watchdog pulls low the NRES output for 2 ms. At the same time, the watchdog failure counter (WDFAIL) is incremented by 1 and the device enters passive mode.
After 8 watchdog failures in sequence, the V
CC
regulator is switched off for 200 ms. If subsequently, 7 additional watchdog failures occur, the V
CC
regulator is completely turned off and the device goes into V
BAT-standby
mode until a wake-up occurs.
In case of a watchdog failure, the outputs (OUTx) are switched off and the device enters passive mode (i.e. all control registers are set to default values).
Doc ID 022637 Rev 2 17/68
Description
Figure 5.
Watchdog state diagram
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3.8
L99MM70XP enters passive mode in case of:
●
●
●
●
Watchdog failure
V
CC
under voltage (NRES)
Thermal shutdown TSD2
SPI data in stuck at 0 or 1
In passive mode all control registers (except the reset level bit RSTLVL) and the configuration register are set to default so that all outputs are switched off. The PASSIVE bit inside the global status byte is set to “1”. The first valid SPI frame after entering the passive mode resets the PASSIVE bit to “0” and leaves passive.
Reset output (NRES)
If V
CC
is turned on and the voltage exceeds the V
CC
reset threshold, the reset output NRES is pulled up by internal pull up resistor to V
CC
voltage after a 2 ms reset delay time. This is necessary for a defined start of the microcontroller when the application is switched on.
A low active reset pulse (2 ms) is generated in case of:
●
●
V
CC
drops below V rth
Watchdog failure
(configurable by SPI) for more than 8 µs (V
CC
under voltage)
18/68 Doc ID 022637 Rev 2
L99MM70XP Description
If NRES is pulled low, all control registers (except the reset level bit RSTLVL) and the configuration register are set to default. In both cases, the device enters passive mode.
3.9 V
CC
fail
The V
CC
regulator output voltage is monitored.
In case of a drop below the V
CC
fail threshold (V
CC
< 2 V typ. for t > 2 µs), the V latched. The fail bit is cleared by a dedicated SPI command.
CC
fail bit is
If 4 ms after turn on of the regulator the V
CC
voltage is below the V
CC
fail threshold, the
L99MM70XP identifies a short circuit condition at the regulator output and switch it off.
In case of V
CC
short to GND failure the device enters V
BAT-standby
mode automatically.
3.10 Output drivers OUT1 … OUT9
Each half bridge is built by internally connected high-side and low-side power DMOS transistors. Due to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs OUT1 to OUT5 without external free-wheeling diodes. The drivers
OUT6, OUT7, OUT8, OUT9, ECV and ECFD are intended to drive resistive loads. Therefore only a limited energy (E < 1 mJ) can be dissipated by the internal ESD-diodes in freewheeling condition. For inductive loads (L > 100 µH) an external free wheeling diode connected between GND and the corresponding output is required.
The current monitor output sources a current image at the current monitor output, which has two fixed ratios of the instantaneous current of the selected high-side driver. Outputs with a resistance of 500 m
and higher have a ratio of 1/2000 and those with a lower resistance of
1/10000. The signal at output CM is blanked after switching on the driver until correct settlement of the circuitry (at least for 32 µs). The bits 0 to 3 of the control register 3 define which of the outputs are multiplexed to the current monitor output CM. The current monitor output allows a more precise analysis of the actual state of the load rather than the detection of an open-load or overload condition. For example, it can be used to detect the motor state
(starting, free running, stalled). Moreover, it is possible to control the power of the defroster more precisely by measuring the load current.
Each driver has a corresponding PWM enable bit, which can be programmed by the SPI interface. If the PWM enable bit is set in control register 2 or 3, the output is controlled by the logically AND-combination of the PWM signal and the output control bit in control register 0 or 1. The outputs OUT1-5, 7, 9, ECV are controlled by the PWM1 input, the output OUT6 is controlled by the input PMW2 and output OUT8 is controlled by INH/PWM3. Thus, the three
PWM inputs can be used to dim three lamps independently by external PWM signals.
Switching off the outputs, a delay of maximum 300 µs is introduced (see also Table 18
in
Section 8.9.2: Switching times ), hence the off time of the PWM input signal should be at
least 300 µs.
Doc ID 022637 Rev 2 19/68
Description L99MM70XP
3.10.4 Cross current protection
The half bridges of the device are cross current protected by an internal delay time. If one driver (LS or HS) is turned off, the activation of the other driver of the same half bridge is automatically delayed by the cross current protection time. After the cross current protection time is expired, the slew-rate limited switch off phase of the driver is changed to a fast turnoff phase and the opposite driver is turned on with slew-rate limitation. Due to this behavior, it is always guaranteed that the previously activated driver is completely turned off before the opposite driver starts to conduct.
3.10.5 Programmable soft start function
Loads with startup currents higher than the overcurrent limits (e.g. inrush current of lamps, start current of motors and cold resistance of heaters) can be driven by using the programmable soft start function (i.e. overcurrent recovery mode). Each driver has a corresponding overcurrent recovery bit. If this bit is set, the device automatically switches the outputs on again after a programmable recovery time. The duty cycle in overcurrent condition can be programmed by the SPI interface to about 12 % or 25 %. The PWM modulated current provides sufficient average current to power-up the load (e.g. heat up the bulb) until the load reaches operating condition. The PWM frequency settles at 1.7 kHz and
3 kHz.
The device itself cannot distinguish between a real overload and a non-linear load like a light bulb. A real overload condition can only be qualified by time. As an example, the microcontroller can switch on the light bulbs by setting the overcurrent recovery bit for the first 50 ms. After clearing the recovery bit, the output is automatically switched off, if the overload condition remains.
Figure 6.
Example of programmable soft start function for inductive loads
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20/68 Doc ID 022637 Rev 2
L99MM70XP Description
3.11 Controller for electrochromic glass
The voltage of an electrochromic element connected at pin ECV can be controlled to a target value, which is set by the bits EC<5:0> (Control register 2, bits 6 down to 1). Setting bit ECON (control register 2, bit 0) enables this function. An on-chip differential amplifier and an external MOS source follower, with its gate connected to pin ECDR, and which drives the electrochrome mirror voltage at pin ECV, form the control loop. The drain of the external
MOS transistor is supplied by OUT7. A diode from pin ECV (anode) to pin ECDR (cathode) has been placed on the chip to protect the external MOS source follower. A capacitor of at least 5 nF has to be added to pin ECDR for loop-stability. The target voltage is binary coded with a full-scale range of 1.5 V. If bit ECVL (control register 3, bit 5) is set to '1', the maximum controller output voltage is clamped to 1.2 V without changing the resolution of bits
EC<5:0>. When programming the ECVLS driver to on-state, the voltage at pin ECV is pulled to ground by a 1.6 Ohm low-side switch until the voltage at pin ECV is less than dV
ECVhi higher than the target voltage (fast discharge).
The status of the voltage control loop is reported via SPI. Bit ECVO (status register 3, bit 4) is set, if the voltage at pin ECV is higher, whereas bit ECVNR (status register 3, bit 5) is set, if the voltage at pin ECV is lower than the target value. Both status bits are valid, if the voltage is stable for at least the ECVO/ECVNR filter time and are not latched.
Since OUT7 is the output of a high-side driver, it contains the same diagnose functions as the other high-side drivers (e.g. during an overcurrent detection, the control loop is switched off). In electrochrome mode, OUT10 cannot be controlled by PWM mode. For EMS reasons the loop capacitor at pin ECDR as well as the capacitor between ECV and GND have to be placed to the respective pins as close as possible (see
for details).
If the electrochrome element is connected between the pins ECV and ECFD instead between ECV and ground, a negative voltage can be applied to the device by pulling ECFD to a higher value than ECV, which is connected to ground by a 1.6 Ohm low-side switch. In this mode the voltage at pin ECFD is controlled to the target value defined by the register
EC<5:0>. This is done using an on-chip source-follower transistor (see Figure 14 for
details). The negative discharge is enabled by setting bit ECND (control register 2, bit 7) to
‘1’.
During normal (positive) voltage control the low-side driver at pin ECFD must be switched on to connect the electrochrome element to ground.
Pin ECDR is pulled resistively (R
ECDRDIS
) to ground while not in electrochrome mode.
Doc ID 022637 Rev 2 21/68
Description
3.12 LIN bus interface
L99MM70XP
●
●
●
●
●
●
●
●
●
●
●
Speed communication up to 20 kbit/s
High speed Flash mode 100 kbit/s
LIN 2.1 compliant (SAEJ2602 compatible) transceiver
Function range from +40 V to -18 V DC at LIN pin
GND disconnection fail safe at module level
Off mode: does not disturb network
GND shift operation at system level
Microcontroller Interface with CMOS compatible I/O pins
Pull up internal resistor
ESD: immunity against automotive transients per ISO7637 specification
Matched output slopes and propagation delay
In order to further reduce the current consumption in standby mode, the integrated LIN bus interface offers an ultra low current consumption.
Note:
The L99MM70XP provides the following 3 error handling features which are not described in the LIN Specifications V2.1, but are realized in different stand alone LIN transceivers/microcontrollers to switch the application back to normal operation mode.
Dominant TXD time out
A permanent low-level on pin TXD would force the bus into a permanent dominant state, blocking all network communication. If pin TXD remains at low-level for longer than the TXD dominant timeout t dom(TXD)
, the transmitter is disabled. The status bit is latched and can be read and optionally cleared by SPI. The transmitter remains disabled until the status register is cleared. This feature can be disabled via SPI.
LIN BUS permanent recessive
If TXD changes to low-level but the bus does not follow within t rec(LIN)
, the transmitter is disabled. The status bit is latched and can be read and optionally cleared by SPI. The transmitter remains disabled until the status register is cleared.
LIN BUS permanent dominant
If a dominant state on the bus persists for longer than t dom(LIN)
a permanent dominant status is detected. The status bit is latched and can be read and optionally cleared by SPI. The transmitter of the transceiver is not disabled.
A wake-up caused by a message on the bus starts the voltage regulator and the microcontroller to switch the application back to normal operation mode.
3.12.3 Wake-up (from LIN bus)
In standby mode the L99MM70XP can receive a wake-up from LIN bus. For the wake-up feature the L99MM70XP logic differentiates two different conditions.
22/68 Doc ID 022637 Rev 2
L99MM70XP Description
Normal wake-up
Normal wake-up can occur when the L99MM70XP was set in standby mode while a recessive (state was present on the bus. A dominant level at LIN for t > t linbus
, switches the
L99MM70XP to active mode. An interrupt is generated at the RXD/NINT pin.
Wake-up from short to GND condition
If the L99MM70XP was set in standby mode while LIN was in dominant (low) state, recessive level at LIN for t linbus
, switches the L99MM70XP to active mode. An interrupt is generated at the RXD/NINT pin.
3.13 Serial peripheral interface (ST SPI standard)
Note:
A 24 bit ST-SPI is used for bi-directional communication with the microcontroller.
●
●
●
●
During active mode, the SPI
Triggers the watchdog
Controls the modes and status of all L99MM70XP modules (incl. input and output drivers)
Provides driver output diagnostic
Provides L99MM70XP diagnostic (incl. overtemperature warning, L99MM70XP operation status)
During standby modes, the SPI is generally deactivated.
The SPI can be driven by a microcontroller with its SPI peripheral running in following mode:
CPOL = 0 and CPHA = 0.
For this mode, input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK.
This device is not limited to microcontroller with a build-in SPI. Only three CMOS-compatible output pins and one input pin are needed to communicate with the device. A fault condition can be detected by setting CSN to low. If CSN = 0, the DO pin reflects the global error flag
(fault condition) of the device (see
Figure 7 ). This operation does not cause the
communication error bit in the global status byte to be set.
Doc ID 022637 Rev 2 23/68
Description
Figure 7.
SPI global error information output
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Chip Select Not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the output pin (DO) is in high impedance state. A low signal activates the output driver and a serial communication can be started. The state during CSN = 0 is called a communication frame.
Serial Data In (DI)
The input pin is used to transfer data serially into the device. The data applied to the DI are sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register.
At the rising edge of the CSN signal the contents of the shift register is transferred to data input register. The writing to the selected data input register is only enabled if exactly 24 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame is ignored. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame.
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected IC's is recommended.
24/68 Doc ID 022637 Rev 2
L99MM70XP Description
Serial Data Out (DO)
The data output driver is activated by a logical low-level at the CSN input and goes from high impedance to a low or high-level depending on the global error flag (fault condition). The first rising edge of the CLK input after a high to low transition of the CSN pin transfers the content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK shifts out the next bit.
Serial Clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The Data Input
(DI) is sampled at the rising edge of the CLK and the Data Output (DO) changes with the falling edge of the CLK signal.
Doc ID 022637 Rev 2 25/68
Protection and diagnosis
4 Protection and diagnosis
L99MM70XP
4.1 Power supply fail
Overvoltage and undervoltage detection on V
S
(Power1).
4.1.1 Overvoltage
If the supply voltage V
S
rises above the overvoltage threshold (V
SOV
) for more than 56 µs
(typ.)
● The outputs OUT1-9, ECV, ECFD and LIN are switched to high impedance state (load protection). Electrochrome mode is switched off. If the bit OVUVR is set to 0, the outputs are re-enabled automatically if the overvoltage condition is removed. If it is set to 1, then the overvoltage bit has to be cleared to re-enable the outputs. LIN is always automatically re-enabled.
● The overvoltage bit is set and can be cleared with a “read and clear” command.
4.1.2 Undervoltage
If the supply voltage V
S
drops below the under voltage threshold voltage (V
SUV
) for more than 56 µs (typ.)
● The outputs OUT1-9, ECV, ECFD and LIN are switched to high impedance state.
Electrochrome mode is switched off. If the bit OVUVR is set to 0, the outputs are reenabled automatically if the under voltage condition is removed. If it is set to 1, then the under voltage bit has to be cleared to re-enable the outputs. LIN is always automatically re-enabled.
● The under voltage bit is set and can be cleared with the “read and clear” command.
26/68 Doc ID 022637 Rev 2
L99MM70XP Protection and diagnosis
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Digital diagnosis features are provided by SPI:
V
CC
reset (threshold programmable)
Overtemperature including pre warning
Open-load status separately for each output OUT1-9, ECV, ECFD
Overload status separately for each output OUT1-9, ECV, ECFD
V
S-supply
V
CC
overvoltage undervoltage
fail bit
Chip reset bit (start from power-on reset)
Number of unsuccessful V
Passive mode
SPI communication error
CC
Number of sequential watchdog failures
LIN diagnosis (permanent recessive/dominant, dominant TXD)
Device state (wake-up from V
Forced V
restarts after thermal shutdown
CC-standby
or V
BAT-standby
)
BAT-standby
after WD-fail, forced V
BAT-standby
after overtemperature
Watchdog timer state (diagnosis of watchdog)
Doc ID 022637 Rev 2 27/68
Protection and diagnosis
Figure 8.
Thermal shutdown protection and diagnosis
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4.4
28/68
Temperature warning and thermal shutdown
.
Half bridge outputs
The device provides a total of 5 half bridge outputs OUT1,2,3,4,5 to drive inductive loads
(e.g. motor).
●
●
●
The half bridges are protected against
Overvoltage and undervoltage
Overload (short circuit)
Overtemperature with pre warning
Doc ID 022637 Rev 2
L99MM70XP Protection and diagnosis
If the output current exceeds the current shutdown threshold the output transistor is turned off and the corresponding diagnosis bit of the output is latched. The status can be read and cleared from SPI. If the overcurrent recovery mode is set for this output, the output is switched on again in order to provide a soft start function (see
Programmable soft start function
) and the status bit is cleared automatically. Otherwise the output stays off until the status bit is cleared.
The outputs are automatically switched off in case of passive mode, V
S
undervoltage, V
S overvoltage, thermal shutdown (TSD1 and TSD2) or stuck at 1/0 condition at DI.
4.5
Note:
High-side driver outputs
The device provides a total of 4 high-side outputs OUT6,7,8,9 to drive LED or defroster.
●
●
●
The high-side outputs are protected against
Overvoltage and undervoltage (can be masked by SPI)
Overload (short circuit)
Overtemperature with pre warning
If the output current exceeds the current shutdown threshold the output transistor is turned off and the corresponding diagnosis bit of the output is latched. The status can be read and cleared from SPI. If the overcurrent recovery mode is set for this output, the output is switched on again in order to provide a soft start function (see
Programmable soft start function
) and the status bit is cleared automatically. Otherwise the output stays off until the status bit is cleared.
The outputs are automatically switched off in case of passive mode, V
S
undervoltage, V
S overvoltage, thermal shutdown (TSD1 and TSD2) or stuck at 1/0 condition at DI.
Loss of ground or ground shift with externally grounded loads: ESD structures are configured for nominal currents only. If external loads are connected to different grounds, the current load must be limited to this nominal current.
Doc ID 022637 Rev 2 29/68
Absolute maximum ratings
5 Absolute maximum ratings
Note:
L99MM70XP
Table 5.
Absolute maximum ratings
Symbol Parameter/test condition
Value
[DC voltage]
DC supply voltage/jump start -0.3 to +28
V
S
Load dump
V
CC
Stabilized supply voltage, logic supply
V
S
< 5.2 V
V
S
> 5.2 V
I
V
DI
, V
CLK
, V
TXD
,
V
CSN
, V
DO
,
V
RXD
, V
NRES
,
V
CM
, V
PWM1
Logic input/output voltage range
Logic input voltage V
PWM2
, V
PWM3
V
CP
Charge pump output
V
OUTn,ECDR,ECV,
ECFD
I
OUT2,3,4,6,7,ECV,
ECFD
, I
VS(REG)
I
OUT1,5,8,9
,
I
VS(Power)
,I
GND
Static output voltage (n = 1 to 9)
Output current
Output current
(1)
(1)
Pin to Pin
Maximum output current between pin 2 and 32 or 7 and 32
(1)
-0.3 to +40
-0.3 to V
S
+ 0.3
-0.3 to 5.5
-0.3 to V
-0.3 to V
S
+ 0.3
-25 to 39
-0.3 to V
CC
±5
±1
S
±1.25
+ 0.3
+ 0.3
V
LIN
LIN bus I/O voltage range -20 to +40
1.
Values for the absolute maximum current through bond wire. It doesn’t consider maximum power dissipation or other limits.
Unit
V
V
V
V
A
A
A
V
V
V
V
V
All maximum ratings are absolute ratings. Exceeding the limitation of any of these values may cause an irreversible damage of the integrated circuit!
30/68 Doc ID 022637 Rev 2
L99MM70XP ESD protection
Table 6.
ESD protection
Parameter Value Unit
All pins
(1)
All output pins
(2)
(OUT1-OUT9, ECV, ECFD)
All pins (charge device model)
(4)
±2
±4
±8
(3) kV kV kV
±500 V
Corner pins (charge device model)
±750 V
1.
HBM (human body model, 100 pF, 1.5 k
) according to MIL 883C, Method 3015.7 or EIA/JESD22A114-A.
2.
HBM with all unzapped pins grounded.
3.
With external components.
4.
According charged device model: JEDEC JESD22-C101D.
For detailed information please see EMC report from IBEE Zwickau (available on request).
Doc ID 022637 Rev 2 31/68
Thermal data L99MM70XP
Note:
Table 7.
Symbol
T j
Operating junction temperature
Parameter
Operating junction temperature
Value
-40 to 150
Unit
°C
R thjA, typical value, without PCB.
Table 8.
Symbol
Temperature warning and thermal shutdown
Parameter
T
W ON
T
SD1 OFF
Thermal overtemperature warning threshold
Thermal shutdown junction temperature 1
T
SD2 OFF
Thermal shutdown junction temperature 2
1.
Non-overlapping.
T j
(1)
T j
T j
Min.
130
140
150
Typ.
Max.
Unit
140
150
160
150
160
170
°C
°C
°C
Figure 9.
Thermal data of PowerSSO-36 and PowerSO-36
32/68 Doc ID 022637 Rev 2
GAPGM S 00013
L99MM70XP Electrical characteristics
8.1 Supply and supply monitoring
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V
V
S
18 V; all outputs open; T amb
= -40 °C...125 °C, unless otherwise specified.
Table 9.
Symbol
Supply and supply monitoring
Parameter Test condition
I
V
SUV ON
V
SUV OFF
V
SUV hyst
V
SOV OFF
V
SOV ON
V
SOV hyst
I
VS(act)
VSREG(act)
I
I
VS(BAT)
VS(BAT)
V
S
undervoltage threshold voltage V
S
increasing
V
S
undervoltage threshold voltage V
S
decreasing
V
S
undervoltage hysteresis V
SUV ON
- V
SUV OFF
V
S
overvoltage threshold voltage
V
S
overvoltage threshold voltage
V
V
S
S
increasing
decreasing
V
S
overvoltage hysteresis V
SOV OFF
- V
SOV ON
Current consumption in active mode V
S
= 13.5 V, TXD LIN high
(1)(2)
Current consumption in active mode
I
V
SREG
VCC
= 13.5 V, TXD LIN high
= 0
Current consumption in V
BAT-standby mode
V
S
= 13.5 V
Current consumption in V
BAT-standby mode
V
S
= 13.5 V
I
VSREG(BAT)
Current consumption in V
BAT-standby mode
V
SREG
I
VSREG(BAT)
Current consumption in V
BAT-standby mode
V
SREG
I
I
I
VS(VBAT) wupend
VS(VCC) wupend
VS(VCC)
Current consumption in V
BAT-standby mode with a pending wake-up request
V
S
, V
SREG
= 13.5 V,
2 V < LIN < V
S
- 3.5 V
Current consumption in V
CC-standby mode with a pending wake-up request
V
S
, V
SREG
= 13.5 V,
2 V < LIN < V
S
- 3.5 V
Current consumption in V
CC-standby mode
V
S
= 13.5 V, voltage regulator V active, no wake-up request
CC
I
I
VSREG(VCC)
VSREG(VCC)
Current consumption in V
CC-standby mode
I
V
S
= 13.5 V, voltage regulator V active, no wake-up request,
CC
VCC
= 0
Current consumption in V
CC-standby mode
I
V
S
= 13.5 V, voltage regulator V active, no wake-up request,
CC
VCC
= 0
1.
OUT1 – OUT9, ECDR ECV, ECFD floating.
2.
T
Test
= -40 °C, 25 °C.
3.
T
Test
= 85 °C. This parameter is guaranteed by design.
Min.
Typ.
Max.
Unit
5.7
5.5
18.1
17.5
1
2
10
15
0.5
1
7
6
1
2
8
12
800
800
1
45
67
7.2
6.9
24.5
23.5
20
12
16
24
1200
1200
70
105
V
V
V
V
V
V mA mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
Doc ID 022637 Rev 2 33/68
Electrical characteristics
8.2
L99MM70XP
Oscillator
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4.5 V
V
S
28 V; all outputs open; T amb
= -40 °C...125 °C, unless otherwise specified.
Table 10.
Oscillator
Symbol Parameter f
CLK
Oscillation frequency
Test condition Min.
1.6
Typ.
Max.
Unit
2.0
2.70
MHz
8.3 Power-on reset (V
SREG
)
All outputs open; T amb
= -40 °C...125 °C, unless otherwise specified (see
Table 11.
Power-on reset (V
SREG
)
Symbol Parameter
V
POR
V
POR
threshold
Test condition
V
SREG
increasing
V
SREG
decreasing
Min.
2.8
Typ.
Max.
Unit
3.8
3.2
4.5
V
V
8.4 Voltage regulator V
CC
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V
V
SREG
28 V; T amb
= -40 °C...125 °C, unless otherwise specified.
Table 12.
Voltage regulator V
CC
Symbol Parameter Test condition Min. Typ. Max. Unit
V
CC
Output voltage
V
V
V
CC hc
STB
Output voltage tolerance active mode
Output voltage tolerance active mode, high current
Output voltage tolerance
V
CC-standby
mode
I
LOAD
V
SREG
= 6 mA...50 mA,
= 13.5 V
I
LOAD
V
SREG
= 50 mA...100 mA,
= 13.5 V
I
LOAD
V
SREG
= 0 µA...6 mA,
= 13.5 V
I
LOAD
= 50 mA, V
SREG
= 4.5 V
V
DP
Drop-out voltage
I
LOAD
= 100 mA, V
SREG
= 4.5 V
I
CC
Output current in active mode Max. continuous load current
I
CCmax
Short circuit output current
Cload1 Load capacitor1
Current limitation
Ceramic
I t
TSD
CMPris
V
CC
deactivation time after thermal shutdown
Current consumption rising threshold
Rising current (deactivated current monitor)
-2.5
±2
±2.5
3.5
0.4
0.5
V
%
%
%
V
V
100 mA
400 600 950 mA
0.22
µF
1.6
5.0
0.2
0.3
1
3.2
5.2
s mA
34/68 Doc ID 022637 Rev 2
L99MM70XP
Table 12.
Voltage regulator V
CC
(continued)
Symbol Parameter Test condition
I
CMPfal
I
CMPhys
V
CCfail
Current consumption falling threshold
Current consumption hysteresis
V
CC
fail threshold
Falling current (deactivated current monitor)
V
CC
forced
Electrical characteristics
Min. Typ. Max. Unit
1.3
2.7
mA
0.5
2 mA
V
8.5 Reset output (V
CC
supervision)
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4 V
V
S
28 V; T amb
= -40 °C...125 °C, unless otherwise specified.
Table 13.
Reset output (V
CC
supervision)
Symbol Parameter Test condition
V
VCC
increasing
CR1/Bit4 = 0
(1)
V
RT1
Reset threshold voltage1
V
VCC
decreasing
CR1/Bit4 = 0
V
RT1HYST
Threshold voltage 1 hysteresis
V
VCC
increasing
CR1/Bit4 = 1
V
RT2
Reset threshold voltage2
V
VCC
decreasing
CR1/Bit4 = 1
V
RT2HYST
Threshold voltage 2 hysteresis
V
R
NRES
NRES t
RR
Reset Pin low output voltage V
CC
> 1 V, I
NRES
= 1 mA
Reset pull up int. resistor V
NRES
= 4 V
Reset reaction time
I
C
NRES
NRES
= 100 pF,
= 1 mA
1.
Delay time see t
WDR
below (
).
Min.
Typ. Max.
Unit
4.6
4.7
4.85
V
4.5
4.6
4.7
0.1
3.6
3.7
3.9
3.0
3.3
3.5
0.4
0.2
0.4
V
60 110 204 k
40
V
V
V
V
V
µs
8.6 Watchdog
4.5 V
V
S
28 V; T amb
= -40 °C...125 °C, unless otherwise specified, see
and
Table 14.
Watchdog
Symbol Parameter t
LW t
WDR
Watchdog cycle time
Watchdog reset pulse time
Test condition Min.
100
1.5
Typ.
Max.
Unit
134
2.3
180
2.9
ms ms
Doc ID 022637 Rev 2 35/68
Electrical characteristics
Figure 10.
Watchdog timing
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Watchdog late and safe window
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8.7 Current monitor output CM
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 8 V
V
S
16 V; T amb
= -40 °C...125 °C, unless otherwise specified.
Table 15.
Current monitor output CM
Symbol Parameter Min.
Typ.
Max.
Unit
I
CM r
Current monitor output ratio:
I
CM
/I
OUT1,5,9 and 8 (low on-resistance)
I
CM
/I
OUT2,3,4,6,7 and 8 (high onresistance)
0 V
V
CM
V
CC
- 1 V —
—
1/10000
1/2000
36/68 Doc ID 022637 Rev 2
L99MM70XP
Table 15.
Current monitor output CM (continued)
Symbol Parameter
I
CM acc
Current monitor accuracy accI
CMOUT1,5,9 and 8 (low on-res.) accI
CMOUT2,3,4,6,7 and 8 (high on-res.)
I
0 V
V
CM
OUTmin
V
CC
- 1 V;
= 500 mA;
I
I
OUT9max
OUT8max
= 5.9 A;
I
OUT1,5max
= 2.9 A;
= 1.3 A
I
0 V
V
CM
OUT.min
V
CC
- 1 V;
= 100 mA;
I
I
OUT2,3,4,6,7max
OUTXmax
= 0.6 A;
= 0.3 A
1.
FS(full scale) = I
OUTmax
* I
CM r
8.8
Min.
Typ.
—
—
Electrical characteristics
Max.
Unit
4% + 1%
FS
(1)
8% + 2%
FS
(1)
Charge pump output CP
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 8 V
V
S
16 V; T amb
= -40 °C...125 °C, unless otherwise specified.
Table 16.
Charge pump output CP
Symbol Parameter
V
CP
I
CP
V
S
= 8 V, I
CP
= -60 µA
Charge pump output voltage V
S
= 10 V, I
CP
= -80 µA
V
S
12 V, I
CP
= -100 µA
Charge pump output current
V
CP
V
S
= V
S
+ 10 V,
= 13.5 V
Min.
Typ.
Max.
Unit
V
S
+ 6
V
S
+ 8
V
S
+ 10
V
V
V
S
S
S
+ 13
+ 13
+ 13
V
V
V
95 150 300 µA
8.9 Outputs OUT1 – OUT9, ECV, ECFD
8.9.1 On-resistance
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 8 V
V
S
16 V; T amb
= -40 °C...125 °C, unless otherwise specified.
Table 17.
On-resistance
Symbol Parameter
R
ON OUT1,5
R
ON OUT2,3,4
On-resistance to supply or GND
I
V
S
= 13.5 V, T amb
OUT1,5
= ±1.5 A
= +25 °C
I
V
S
= 13.5 V, T amb
OUT1,5
= ±1.5 A
= +125 °C
On-resistance to supply or GND
I
V
S
= 13.5 V, T amb
OUT2,3,4
= ±0.4 A
= +25 °C
V
S
= 13.5 V, T amb
= +125 °C
I
OUT2,3,4
= ±0.4 A
Min.
Typ.
300
450
1600
2500
Max.
Unit
400
600 m
m
2200 m
3400 m
Doc ID 022637 Rev 2 37/68
Electrical characteristics L99MM70XP
Table 17.
On-resistance (continued)
Symbol Parameter
R
ON OUT6,7
R
R
ON OUT8
ON OUT9
R
ON ECV,ECFD
I
QLH
V
S
= 13.5 V, T amb
= +25 °C
I
OUT6,7
= -0.4 A
On-resistance to supply
On-resistance to supply in low resistance mode
I
V
S
= 13.5 V, T amb
OUT6,7
= -0.4 A
= +125 °C
V
S
= 13.5 V, T amb
= +25 °C
I
OUT8
= -3.0 A
I
V
S
= 13.5 V, T amb
OUT8
= -3.0 A
= +125 °C
On-resistance to supply in high
I
OUT8
= -0.8 A resistance mode
V
S
= 13.5 V, T amb
= +25 °C
I
V
S
= 13.5 V, T amb
OUT8
= -0.8 A
= +125 °C
On-resistance to supply
On-resistance to GND
I
V
S
= 13.5 V, T amb
OUT9
= -3.0 A
= +25 °C
V
S
= 13.5 V, T amb
= +125 °C
I
OUT9
= -3.0 A
I
V
S
= 13.5 V, T amb
OUTECV,ECFD
= +25 °C
= +0.4 A
V
S
= 13.5 V, T amb
= +125 °C
I
OUTECV,ECFD
= +0.4 A
Switched-off output current high-side drivers of OUT1-9
V
OUT
= 0 V, standby mode
V
OUT
= 0 V, active mode
Switched-off output current low-side drivers of OUT1-5
V
OUT
= V
S
, standby mode
V
OUT
= V
S
, active mode
V
OUT
= V
S
, standby mode
I
QLL
Switched-off output current low-side drivers of ECV
Switched-off output current low-side drivers of ECFD
V
OUT
= V
S
, active mode
V
OUT
= 4V, standby mode
V
OUT
= 4V, active mode
Min.
Typ.
1600
Max.
Unit
2200 m
2500 3400 m
500
700
700
950 m
m
1800 2400 m
2500 3400 m
90
130
130
180 m
m
1600 2200 m
-5
-10.5
2500
-2
-7
80
-7 -10
-15
-10
-10
-7
80
-7
3400 m
120
15
120
µA
µA
µA
µA
µA
µA
µA
µA
38/68
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 8 V
V
S
16 V; T amb
= -40 °C...125 °C, unless otherwise specified.
Table 18.
Switching times
Symbol Parameter Min.
Typ. Max.
Unit t d ON H t d OFF H
Output delay time high-side driver on
V
S
= 13.5 V, corresponding low-side driver is not active
(1)(2)(3)
Output delay time high-side driver off
V
S
20 40 80 µs
45 150 300 µs
Doc ID 022637 Rev 2
L99MM70XP Electrical characteristics
Table 18.
Switching times (continued)
Symbol Parameter Min.
Typ. Max.
Unit t d ON L
Output delay time low-side driver on
V
S
= 13.5 V, corresponding low-side
15 30 70 µs t d OFF L
Output delay time low-side driver off
V
S
t t d HL d LH dV
OUT
/dt
Cross current protection time
Slew rate of OUTx t cc ONLS_OFFHS
– t d OFF H
(4) t cc ONHS_OFFLS
– t d OFF L
V
S
1.
R load
= 16 at OUT1,5 and OUT8 in low on-resistance mode.
2.
R load
= 4 at OUT9.
3.
R load
= 64 at OUT2,3,4,6,7, ECV, ECFD and OUT8 in high on-resistance mode.
4.
t
CC
is the switch-on delay time if complement in half bridge has to switch off.
80 150
200
300
410
µs
µs
0.1
0.2
0.6
V/µs
Figure 12.
Output switching times
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Doc ID 022637 Rev 2 39/68
Electrical characteristics L99MM70XP
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 8 V
V
S
16 V; T amb
= -40 °C...125 °C, unless otherwise specified.
Table 19.
Current monitoring
Symbol Parameter
|I
OC1
|, |I
OC5
|
|I
OC2
|,
|I
OC3
|, |I
OC4
|
Overcurrent threshold to supply or
GND
|I
OC6
|, |I
OC7
| Overcurrent threshold to supply
Overcurrent threshold to supply in low on-resistance mode
|I
OC8
|
Overcurrent threshold to supply in high on-resistance mode
|I
OC9
|
|I
OCECV
|,
|I
OCECFD
|
Overcurrent threshold to supply
Output current limitation to GND
V
V
V
V
V
V
S
S
S
S
S
S
= 13.5 V, sink and source
= 13.5 V, source
= 13.5 V, source
= 13.5 V, source
= 13.5 V, source
= 13.5 V, sink t
FOC
Filter time of overcurrent signal
Duration of overcurrent condition to set the status bit f f rec0 rec1
Recovery frequency for OC recovery duty cycle bit = 0
Recovery frequency for OC recovery duty cycle bit = 1
|I
OLD1
|,
|I
OLD5
|
|I
OLD2
|,
|I
OLD3
|,
|I
OLD4
|
|I
OLD6
|,
|I
OLD7
| t
FOL
Under-current threshold to supply or
GND
Under-current threshold to supply
V
S
= 13.5 V, sink and source
|I
OLD8
|
Under-current threshold to supply in low on-resistance mode
V
S
= 13.5 V, source
Under-current threshold to supply in high on-resistance mode
|I
OLD9
|
|I
OLDECV
|,
|I
OLDECFD
|
Under-current threshold to supply
Under-current threshold to GND V
S
= 13.5 V, sink
Filter time of under-current signal
Duration of under-current condition to set the status bit
Min.
Typ.
Max.
Unit
3 5 A
0.75
0.75
1.5
0.35
6
0.72
10
1
2
9
10
10
15
5
30
10
0.5
55
30
20
20
40
10
150
20
2.0
1.25
1.25
2.5
0.65
10
1.25
100
4
6
80
30
30
60
15
300
30
3.0
A
A
A
A
A
A
µs kHz kHz mA mA mA mA mA mA mA ms
40/68 Doc ID 022637 Rev 2
L99MM70XP Electrical characteristics
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 8 V
V
S
16 V; T amb
= -40 °C...125 °C, unless otherwise specified.
Table 20.
Electrochrome control
Symbol Parameter
V
CTRLmax
Maximum EC-control voltage
ECVL = ‘1’
(1)
ECVL = ‘0’
(1)
DNL
|dV dV dV
ECV
ECV
|
ECVnr
ECVhi
Differential non linearity
Voltage deviation between target and ECV
Difference voltage between target and ECV sets flag if V
ECV
is below it above it dV
ECV
|I
ECDR
= V target
| < 1 µA
(3)
- V
ECV
, dV
ECV
= V target
(3)
- V
ECV
Toggle bit5 = 1 Status reg. 3 dV
ECV
= V target
(3)
- V
ECV
Toggle bit4 = 1 Status reg. 3 t
FECVNR
ECVNR filter time t
FECO
ECVO filter time
V
ECDRminHIGH
V
ECDRmaxLOW
I
R
ECDR ecdrdis
Output voltage range
Current into ECDR
I
ECDR
= -10 µA
I
ECDR
= 10 µA
V
V target
(3)
ECDR
> V
ECV
= 3.5 V
+ 500 mV,
V target
(3)
< V
ECV
- 500 mV,
V
ECDR
V
ECV
= 1.0 V; V
= 0.5 V target
= 0 V,
Pull down resistance at ECDR in fast discharge mode and while EC-mode is off
V
ECDR
= 0.7 V, ECON = ‘1’,
EC<5:0> = 0 or ECON = ‘0’
DNL
ECFD
Differential non linearity
|dV dV
ECFDnr
(4) dV
ECFD
ECFDhi
|
Voltage deviation between target and ECFD
Difference voltage between target and ECFD sets flag if V
ECFD
is below it above it
I dV
ECFD
ECFD
= V target
(3)
= 100 µA
- V
ECFD
, dV
ECFD
= V target
(3)
- V
ECFD toggle status bit ECVNR = ’1’ dV
ECFD
= V target
(3)
- V
ECFD toggle status bit ECVO = ‘1’
Min.
Typ.
Max.
Unit
1.4
1.12
-1
-5% -
1LSB
(2)
4.1
0
-100
10
-1
-5% -
1LSB
(2)
120
-120
32
32
120
-120
1.6
V
1.28
1
+5% +
1LSB
(2)
V
LSB
(2) mV
5.5
0.7
-10
100
10
µs
V
V
1
+5% +
1LSB
(2)
LSB
(2) mV
1.
Bit ECVL = ‘1’ or ‘0’: ECV voltage, where I
ECDR
can change sign.
2.
1 LSB (Least Significant Bit) = 23.8 mV.
3.
V target
is set by bits EC <5:0> and bit ECVL; tested for each individual bit.
4.
Not tested since pulling pin ECFD to a low voltage against the internal source follower may lead to an overcurrent at pin
ECFDHS or thermal shutdown. mV mV
µs
µA
µA k
mV mV
Doc ID 022637 Rev 2 41/68
Electrical characteristics L99MM70XP
Figure 13.
Electrochrome mirror driver with mirror referenced to ground
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Electrochrome mirror driver with mirror referenced to ECFD for negative discharge
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42/68 Doc ID 022637 Rev 2
L99MM70XP Electrical characteristics
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 8 V
V
S
16 V; T amb
= -40 °C...125 °C, unless otherwise specified.
Table 21.
INH/PWM3 input
Symbol Parameter
I
INHth
I
INHPd
I
INHhys t
WU
Wake-up activate threshold current
INH pull down current
Wake-up current hysteresis
Minimum time for wake-up
V
INH
= 13.5 V
Min.
Typ.
Max.
Unit
30
30
50
75
70
10
64
120 µA
120 µA
20 µA
77 µs
8.10 LIN
Compatible to LIN 2.1 for baud rates up to 20 kBit/s
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 7 V
V
S
18 V; T amb
= -40 °C...125 °C, unless otherwise specified.
Table 22.
LIN
Symbol Parameter Min.
Typ.
Max.
Unit
LIN transmit data input: pin TXD
V
V
TXDLOW
TXDHIGH
Input voltage dominant level
Input voltage recessive level
V
TXDHIGH
- V
TXDLOW
Active mode
Active mode
V
R
TXDHYS
TXDPU
TXD pull up resistor
Active mode
Active mode, V
S
0 < V
CSN
< 0.7 V
= 13.5 V,
CC
LIN receive data output: pin RXD
V
V
RXDLOW
RXDHIGH
Output voltage dominant level
Output voltage recessive level
LIN transmitter and receiver: pin LIN
Active mode, I
RXD
= 2 mA
Active mode, I
RXD
= 2 mA
V
V
THdom
THrec
Receiver threshold voltage recessive to dominant state
Receiver threshold voltage dominant to recessive state
0.7 V
CC
500
50
0.7 V
CC
0.4 V
S
0.5 V
S
100
0.45 V
S
0.55 V
S
0.3 V
CC
150
0.3 V
CC
0.5 V
S
0.6 V
S
V
V mV k
V
V
V
V
Doc ID 022637 Rev 2 43/68
Electrical characteristics L99MM70XP
Table 22.
LIN (continued)
Symbol Parameter Min.
Typ.
Max.
Unit
V
V
V t
V
THhys
THcnt
THwkup
THwkdwn
LINBUS
Receiver threshold hysteresis:
V
THrec
- V
THdom
Receiver tolerance center value:
(V
THrec
+ V
THdom
) / 2
Receiver wake-up rising threshold voltage
Receiver wake-up falling threshold voltage
Dominant time for wake-up via bus
Sleep mode edge: recessivedominant
0.07 V
0.475 V
V
S
1.0
I
BUS_LIM
Current limitation in dominant state
V
TXD
= 0 V, V
LIN
= V
SMAX
= 18 V
I
BUS_PAS_dom
Input leakage current at the receiver (incl. pull up resistor)
V
TXD
= 5 V, V
LIN
= 0 V
,
V
S
= 13.5 V
I
BUS_PAS_rec
Transmitter input current in recessive state
V
V
TXD
LIN
= 5 V, 8 V
V
S
V
LIN,
V
S
18 V,
40
-1
I
BUS_NO_GND
Transceiver input current if loss of GND at device
GND = V
S
, 0 V < V
LIN
V
S
= 13.5 V
< 18 V,
R
LINup
LIN output pull up resistor
V
TXD
= 5 V; V
LIN
= 0 V
-1
I
BUS_NO_BAT
V
V
LINdom
LINrec
Input current if loss of
V
BAT
at Device
V
S
= GND, 0 V < V
LIN
< 18 V
LIN voltage level in dominant state I
Active mode; V
TXD
LIN
= 40 mA
= 0 V;
LIN voltage level in recessive state
Active mode; V
TXD
= 5 V; I
LIN
= 10 µA 0.8 V
S
20
S
S
- 3.5 V
0.1 V
0.5 V
S
1.5
S
S
0.175 V
0.525 V
- 2.5
V
S
64*T
OSC
100
40
V
2
S
S
S
- 1.5
V
180
20
1
100
1.3
60
µs mA mA
µA mA
µA k
V
V
V
V
V
LIN transceiver timing t
RXDpd t
RXDpd_sym
Receiver propagation delay time
Active Mode; t t
RXDpd
RXpdf
= max(t
= t(0.5 V
RXDpdr
RXD
, t
RXDpdf
) - t(0.45 V
);
LIN
) t
RXpdr
= t(0.5 V
RXD
) - t(0.55 V
LIN
)
V
R
S
= 13.5 V; C
RXD
BUS
= 1 k
, C
BUS
= 20 pF;
= 1 nF;
Symmetry of receiver propagation delay time (rising vs. falling edge) t
RXDpd_sym
= t
RXDpdr
- t
RXDpdf
-2
6
2
µs
µs
44/68 Doc ID 022637 Rev 2
L99MM70XP Electrical characteristics
Table 22.
LIN (continued)
Symbol Parameter
D1
D2
D3
D4
Duty cycle 1
Duty cycle 2
Duty cycle 3
Duty cycle 4
TH
Rec
(max) = 0.744 * V
S
;
TH
Dom
(max) = 0.581 * V
S
;
V
S
= 7 to 18 V, t bit
= 50 µs;
D1 = t
BUS_rec
(min) / (2 * t
R
R
R
BUS
BUS
BUS
= 1 k
, C
BUS
= 660
, C
= 500
, C
= 1 nF;
BUS
BUS bit
);
= 6.8 nF;
= 10 nF
TH
Rec
(min) = 0.422*V
S
;
TH
Dom
(min) = 0.284*V
S
;
V
S
= 7.6 to 18 V, t bit
= 50 µs;
D2 = t
BUS_rec
(max)/(2*t bit
R
R
R
BUS
BUS
BUS
= 1 k
, C
BUS
= 660
, C
= 500
, C
= 1 nF;
BUS
BUS
);
= 6.8 nF;
= 10 nF
TH
Rec
(max) = 0.778*V
S
;
TH
Dom
(max) = 0.616*V
S
;
V
S
= 7 to 18V, t bit
= 96µs,
D3 = t
R
R
R
BUS
BUS
BUS
BUS_rec
(min)/(2*t
= 1 k
, C
= 660
BUS
, C
= 500
, C bit
)
= 1 nF;
BUS
BUS
= 6.8 nF;
= 10 nF
TH
Rec
(min) = 0.389*V
S
;
TH
Dom
(min) = 0.251*V
S
;
V
S
= 7.6 to 18V, t bit
= 96µs;
D4 = t
BUS_rec
(max)/(2*t bit
R
R
R
BUS
BUS
BUS
= 1 k
, C
BUS
= 660
, C
= 500
, C
= 1 nF;
BUS
BUS
)
= 6.8 nF;
= 10 nF t t dom(TXD) t dom(LIN) rec(LIN)
TXD dominant timeout
BUS dominant timeout
BUS recessive timeout
LIN Flash mode
SR
FLASH
LIN slew rate falling edge in Flash mode
Active mode; LIN slew rate (80% to
20% V
S
); V
S
R
BUS
= 13.5 V,
= 150
, C
BUS
= 1 nF
Min.
0.396
0.417
Typ.
13
12
12
40
Max.
Unit
0.581
0.590
V/µs ms ms
µs
Doc ID 022637 Rev 2 45/68
Electrical characteristics
Figure 15.
LIN transmit and receive timing
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7;SGI
9
7['
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7;SGU
L99MM70XP
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9
/,1UHF
9
/,1
9
7+UHF
9
7+GRP
9
/,1GRP
9
5['
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5;SGI
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8.11 SPI and PWM inputs
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V
V
S
18 V; all outputs open; T amb
= -40 °C...125 °C, unless otherwise specified.
Table 23.
DC characteristics
Symbol Parameter Test condition Min.
Typ.
Max.
Unit
Inputs: CSN, CLK, DI, PWM1, PWM2, PWM3
V
IL
V
IH
V
IHYS
R
CSN in
R
CLK in
R
DI in
R
PWM1 in
R
PWM2 in
Input voltage low-level
Input voltage high-level
Input hysteresis
CSN pull up resistor
CLK pull down resistor
DI pull down resistor
PWM1 pull down resistor
PWM2 pull down resistor
PWM3
V
S
= 13.5 V
V
S
= 13.5 V
V
S
= 13.5 V
V
S
= 13.5 V, 0 < V
CSN
< 0.7 V
CC
V
S
= 13.5 V, V
CLK
= 1.5 V
0.7 V
500
30
30
CC
120
60
V
S
= 13.5 V, V
DI
= 1.5 V
V
S
= 13.5 V, V
PWM1
= 1.5 V
30
30
60
60
V
S
= 13.5 V, V
PWM2
= 1.5 V 30 60
See Section 8.9.5: INH/PWM3 input
0.3 V
CC
250
150
150
150
150
Output: DO
V
OL
V
OH
Output voltage low-level
Output voltage high-level I
I
OL
OH
= 5 mA, V
= -5mA, V
S
S
= 13.5 V
= 13.5 V 0.7 V
CC
0.3 V
CC
V
V mV k
k
k
k
k
V
V
46/68 Doc ID 022637 Rev 2
L99MM70XP Electrical characteristics
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V
V
S
18 V; all outputs open; T amb
= -40 °C...125 °C, unless otherwise specified.
Table 24.
AC characteristics
Parameter Symbol
C
OUT
(1)
Output capacitance (DO)
C
IN
(1)
Input capacitance (DI, CSN,
CLK, PWM1, PWM2, PWM3)
Test condition Min.
—
—
Typ.
Max.
Unit
—
—
1.
Value of input capacity is not measured in production test. Parameter guaranteed by design.
10
10 pF pF
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V
V
S
18 V; all outputs open; T amb
= -40 °C...125 °C, unless otherwise specified.
For definition of the parameters please see Figure 16
and
.
Table 25.
Dynamic characteristics
Symbol Parameter Test condition Min. Typ. Max. Unit t t
CSNQVL
CSNQVH
DO enable from 3-state to low-level
DO enable from 3-state to high-level
C
DO
= 100 pF, I
DO up load to V
CC
, V
S
= 1 mA, pull
= 13.5 V
C
DO
= 100 pF, I
DO
= -1 mA, pull down load to GND, V
S
= 13.5 V t
CSNQTL
DO disable from low-level to
3-state
C
DO
= 100 pF, I
DO up load to V
CC
, V
S
= 4 mA, pull
= 13.5 V t
CSNQTH
DO disable from high-level to
3-state
C
DO
= 100 pF, I
DO
= -4 mA, pull down load to GND, V
S
= 13.5 V t t
CLKQV
SCSN t t
SDI
HDI
CLK falling until DO valid
V
DO
< 0.3 V
CC
or V
DO
> 0.7 V
CC
C
DO
= 5 pF, V
S
= 13.5 V
V
DO
< 0.3 V
CC
or V
DO
> 0.7 V
CC
C
DO
= 100 pF, V
S
= 13.5 V
CSN setup time, CSN low before rising edge of CLK
V
S
= 13.5 V
DI setup time, DI stable before rising edge of CLK
V
S
= 13.5 V
DI hold time, DI stable after rising edge of CLK
V
S
= 13.5 V t
HCLK minimum CLK high time V
S
= 13.5 V t
LCLK t
HCSN minimum CLK low time minimum CSN high time
V
V
S
S
= 13.5 V
= 13.5 V t
SCLK
CLK setup time before CSN rising
V
S
= 13.5 V
400
200
200
115
115
4
400
100
100
380
380
50
250
250
450
450
250 ns ns ns ns ns ns ns ns ns ns ns
µs ns
Doc ID 022637 Rev 2 47/68
Electrical characteristics
Table 25.
Dynamic characteristics (continued)
Symbol Parameter Test condition t r DO t f DO t r in t f in
DO rise time
DO fall time rise time of input signal DI,
CLK, CSN fall time of input signal DI,
CLK, CSN
C
DO
= 100 pF, V
S
= 13.5 V
C
DO
= 100 pF, V
S
= 13.5 V
V
S
= 13.5 V
V
S
= 13.5 V
Figure 16.
SPI timing parameters
W
+&61
L99MM70XP
Min. Typ. Max. Unit
80 140 ns
50 100 ns
100 ns
100 ns
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W
&6149
'2
W
6&61
'DWDRXW
W
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W
&6147
'DWDRXW
W
6&/.
&/.
',
W
6',
W
+&/.
'DWDLQ
W
/&/.
'DWDLQ
*$3*06
48/68 Doc ID 022637 Rev 2
L99MM70XP
Figure 17.
SPI input and output timing parameters
W
U'2
'2
ORZWRKLJK
W
I'2
'2
KLJKWRORZ
Electrical characteristics
9
9
9
&&
&&
&&
9
&&
W
ILQ
',
&/.
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Figure 18.
SPI maximum clock frequency
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6&.ULVH
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6&.ILOW
6&.
0LFUR&RQWUROOHU
0DVWHU
0,62
W
VHWXS
Doc ID 022637 Rev 2
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ULQ
9
&&
9
&&
*$3*06
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6&.49
6ODYH
*$3*06
49/68
Electrical characteristics L99MM70XP
The maximum SPI clock frequency can be calculated as follows (see Figure 18 ):
t
CLKQV
(total) = t
CLKrise
(µC) + t
CLKfilt
(PCB) + t
CLKQV
(slave) + t setup
(µC) f
CLK
(max) < ½ x t
CLKQV
(total)
Example: t
CLKQV
= 25 ns + 100 ns + 250 ns + 25 ns = 400 ns f
CLK
(max) < 1.25 MHz
8.12 Input PWM2 for Flash mode
The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V
V
S
18 V; all outputs open; T amb
= -40 °C...125 °C, unless otherwise specified.
Table 26.
Input PWM2 for Flash mode
Symbol Parameter Test condition
V flashL
Input low-level (PWM2 falling)
(1)
V
S
= 13.5 V
V flashH
Input high-level (PWM2 rising)
V
S
= 13.5 V, V
BAT-standby mode, V
CC
switches on
V flashHYS Input voltage hysteresis
V
S
= 13.5 V
1.
Parameter guaranteed by design.
Min.
6.1
7.4
0.6
Typ.
Max.
Unit
7.25
8.4
0.8
8.4
9.4
1.0
V
V
V
50/68 Doc ID 022637 Rev 2
L99MM70XP
9 SPI control and status registers
SPI control and status registers
9.1 Functional description of the SPI
For a general description of the SPI please refer to chapter Serial peripheral interface (ST
At the beginning of each communication the master can read the contents of the <SPIframe-ID> register (ROM address 3Eh) of the slave device. This 8 bit register indicates the
SPI frame length (24 bit) and the availability of additional features.
Each communication frame consists of a command byte which is followed by 2 data bytes.
The data returned on DO within the same frame always starts with the <Global Status
Byte>. It provides general status information about the device. It is followed by 2 data bytes
(i.e. “in-frame-response”).
For write cycles the <Global Status Byte> is followed by the previous content of the addressed register.
Table 27.
Command byte
Command byte Data byte 1 Data byte 2
Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name OC1 OC0 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
OCx: operation code
Ax: address
Dx: data bit
Each communication frame starts with a command byte. It consists of an operating code which specifies the type of operation (<Read>, <Write>, <Read and Clear>, <Read Device
Information>) and a 6 bit address. If less than 6 bits are required, the remaining bits are unused but are reserved.
Table 28.
Operation code definition
OC1 OC0
0
0
1
1
0
1
0
1
<Write Mode>
<Read Mode>
<Read and Clear Mode>
<Read Device Information>
Meaning
Doc ID 022637 Rev 2 51/68
SPI control and status registers L99MM70XP
The <Write Mode> and <Read Mode> operations allow access to the RAM of the device.
A <Read and Clear Mode> operation is used to read a status register and subsequently clear its content.
The <Read Device Information> allows access to the ROM area which contains device related information such as <ID-Header>, <Product Code>, <Silicon Version> and <SPIframe-ID>.
Table 29.
Global status byte
Global status byte
Bit
Name
Reset
7
GL_ER
1
6
CO_ER
0
5
NRECE
0
4 3 2 1 0
TSD TW_OL UV_OV_OC V
CC
_FAIL PASSIVE
0 0 0 0 0
GL_ER
CO_ER
Global error flag.
Failures of Bits 0-6 are always linked to the global error flag. This flag is generated by an OR combination of all failure events of the device. If the TW_OL_MSK bit is set in the configuration register, TW_OL is not used as an input to this bit.
GL_ER is reflected via the DO pin while CSN is held low and no clock signal is available. The flag remains as long as CSN is low. This operation does not cause the communication error bit in the
<Global status byte> to be set.
Communication error.
If the number of clock pulses within the previous frame is not 24, the frame is ignored, and this bit is set.
CO_ER is not set, if CSN is held low without any clock to check the GL_ER bit.
Chip reset (C_RESET) = Registers have been set to default.
NRECE = NOT
(C_RESET OR
CO_ER)
After power on NRECE is ‘0’ and is set to ‘1’ by a valid SPI communication.
NRECE is also ‘0’ if there was a communication error or if there was a reset due to stuck-at-0 or stuck-at-1 at the SPIDI input.
When NRECE is active (‘0’), the gate drivers are switched off (resistive path to source). The gate drivers can only be activated after NRECE has been reset with an SPI command.
TSD
Thermal shut down due to an internal sensor. All the gate drivers and the charge pump are switched off (resistive path to source). The TSD bit has to be cleared through a software reset to reactivate the gate drivers and the charge pump.
TW_OL Thermal warning OR open-load.
UV_OV_OC Under voltage OR overvoltage OR overcurrent
V
CC_FAIL
PASSIVE
V
CC
fail
Device in passive mode.
This bit is set if the device enters passive mode (due to watchdog failure, V
CC
under voltage, thermal shutdown TSD2 or SPI data in stuck at 0 or 1)
The bit is reset when the micro sends the first correct SPI frame after entering passive mode.
52/68 Doc ID 022637 Rev 2
L99MM70XP SPI control and status registers
Table 30.
RAM memory map
Address Name Access
01h
02h
03h
04h
11h
12h
13h
14h
3Fh
Content
Control register 1 Read/write Bridge control, watchdog trigger
Control register 2 Read/write High/low-side control, EC control
Control register 3 Read/write Bridge recovery mode, bridge PWM mode, LIN
Control register 4 Read/write
HS recovery and PWM mode, LS recovery and PWM mode, current monitor
Status register 1 Read/clear Overcurrent diagnosis
Status register 2 Read/clear Open-load diagnosis
Status register 3 Read/clear WD status, supply voltage and EC diagnosis,
Status register 4 Read/clear LIN diagnosis, thermal status
Configuration register
Read/write
Table 31.
ROM memory map
Address
00h
01h
02h
03h
3Eh
Name
ID Header
Version
Product code 1
Product code 2
SPI frame ID
Access Content
Read only 4300h (ASSP ST_SPI)
Read only 0000h (engineering sample)
Read only 4800h (dec. 72)
Read only 4800h (ASCII ‘H’)
Read only 4200h (watchdog available, 24 bit ST-SPI)
Doc ID 022637 Rev 2 53/68
SPI control and status registers L99MM70XP
Table 32.
Control registers 1
Bit
Reset state
Name
Control register 1 (01h)
15 14 13 12 11 10 9 8 7 6 5
0 0 0 0 0 0 0 0 0 0 1
OUT5
HS
OUT5
LS
OUT4
HS
OUT4
LS
OUT3
HS
OUT3
LS
OUT2
HS
OUT2
LS
OUT1
HS
OUT1
LS
NINT
EN
4
0
RST
LEV
3
0
ICMP
2
0
Stby
Sel
1
0
Go
Stby
0
0
WD
Trig
Table 33.
Control registers 1, bits
Bit name Comment
OUT5HS
OUT5LS
OUT4HS
OUT4LS
OUT3HS
OUT3LS
OUT2HS
OUT2LS
OUT1HS
OUT1LS
If a bit is set, the selected output driver is switched on. If the corresponding PWM enable bit is set also, the driver is activated only if the associated PWM input signal is high.
The outputs of OUT1 – OUT5 are half bridges. If the bits of the HS and LS drivers of the same half bridge are set, both drivers are deactivated and the output is set to high impedance.
NINTEN
RSTLEV
I
CMP
STBYSEL
GOSTBY
WDTRIG
Enable NINT output
0: RXD output has only RXD functionality
1: RXD output can work also as NINT output
Select V
CC
reset level
0: 4.7 V
1: 3.5 V
Monitor the I
CC
current consumption during V
CC-standby
mode
0: watchdog disabled only if I
CC
< I
CMP
1: watchdog disabled
Standby select
0: V
BAT-standby
1: V
CC-standby
This bit is a one-shot bit, it is read always 0
1: execute standby mode
This bit is a one-shot bit, it is read always 0
Watchdog trigger
This bit has to be toggled regularly if the watchdog is active. The watchdog can be triggered either by this bit or by bit 0 of the configuration register.
54/68 Doc ID 022637 Rev 2
L99MM70XP SPI control and status registers
Table 34.
Control registers 2
Control register 2 (02h)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset state
Name
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reserved ECFDLS ECVLS OUT9 OUT8HS2 OUT8HS1 OUT7 OUT6 ECND EC5 EC4 EC3 EC2 EC1 EC0 ECON
Table 35.
Control registers 2, bits
Bit name Comment reserved Reserved bit, has always to be written to 0 and reads always 0
ECFDLS
1: switch on the ECFD LS driver
0: switch off the ECFD LS driver
ECVLS
OUT9
1: switch on the ECV LS driver
0: switch off the ECV LS driver
If the ECVPWM1 bit (CR4/Bit4) is also set, then the ECV output is controlled by the PWM1 input
1: switch on the OUT9 HS driver
0: switch off the OUT9 HS driver
If the OUT9PWM1 bit (CR4/Bit11) is also set, then the OUT9 output is controlled by the PWM1 input
OUT8HS2 11: switch off the OUT8 HS driver
OUT8HS1
10: switch on the OUT8 HS driver (high current mode)
01: switch on the OUT8 HS driver (low current mode)
00: switch off the OUT8 HS driver
If the OUT8PWM3 bit (CR4/Bit10) is also set, then the OUT8 output is controlled by the PWM3 input
OUT7
1: switch on the OUT7 HS driver
0: switch off the OUT7 HS driver
If the OUT7PWM1 bit (CR4/Bit9) is also set, then the OUT7 output is controlled by the PWM1 input
This bit is disabled if ECON = 1. In this case OUT7 is switched on permanently.
OUT6
ECND
1: switch on the OUT6 HS driver
0: switch off the OUT6 HS driver
If the OUT6PWM2 bit (CR4/Bit8) is also set, then the OUT6 output is controlled by the PWM2 input
EC negative discharge:
0: EC negative discharge off
1: EC negative discharge on
EC5
EC4
EC3
EC2
EC1
EC0
Reference value for difference voltage amplifier at pin ECV, binary coded. The full scale value is set in
ECVL (CR3/Bit5). If all EC bits are set to zero, the reference value is 0V.
ECON
1: EC control enabled
0: EC control disabled
If the EC control is enabled, the output OUT7 is switched on permanently.
Doc ID 022637 Rev 2 55/68
SPI control and status registers L99MM70XP
Table 36.
Control register 3
Control register 3 (03h)
Bit
Reset state
Name
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
1
5
0
4
0
3
0
2
0
1
0
0
0 reserved
OCR
Freq
OVUVR
OUT5
OR
OUT4
OR
OUT3
OR
OUT2
OR
OUT1
OR
LIN
Flash
LIN
TXD
Tout
ECVL
OUT5
PWM1
OUT4
PWM1
OUT3
PWM1
OUT2
PWM1
OUT1
PWM1
Table 37.
Control register 3, bits
Bit name Comment reserved
OCRFREQ
OVUVR
Reserved bit, has always to be written to 0 and reads always 0
OCR frequency:
This bit defines the overcurrent recovery frequency of a driver in overcurrent recovery mode
0: 1.7 kHz
1: 3 kHz
Overvoltage/undervoltage recovery:
1: clear status register to enable the outputs after an overvoltage/undervoltage event
0: outputs are enabled automatically after an overvoltage/undervoltage event
OUT5OR
OUT4OR
OUT3OR
OUT2OR
OUT1OR
Overcurrent recovery enable:
1: the output is automatically reactivated after a delay time with programmable duty cycle
(CR3/Bit14)
0: clear status register to enable the output after an overcurrent event
LINFLASH
LINTXDTout
LIN flash mode:
0: 20 kbit/s
1: 100 kbit/s
Dominant TxD time-out for the LIN interface:
1: enable the dominant TXD time-out for the LIN interface
0: disable the dominant TXD time-out for the LIN interface
ECVL
EC voltage limit:
0: max EC voltage = 1.2V
1: max EC voltage = 1.5V
OUT5PWM1
OUT4PWM1
OUT3PWM1
If the PWM enable bit is set and the output is enabled, the output is switched on only if the PWM1 input is high, and switched off if the PWM1 input is low.
OUT2PWM1
OUT1PWM1
56/68 Doc ID 022637 Rev 2
L99MM70XP SPI control and status registers
Table 38.
Control register 4
Control register 4 (04h)
Bit
Reset state
Name
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
OUT9
OR
OUT8
OR
OUT7
OR
OUT6
OR
OUT9
PWM1
OUT8
PWM3
OUT7
PWM1
OUT6
PWM2 reserved
ECV
OR reserved
ECV
PWM1
CM3 CM2 CM1 CM0
Table 39.
Control register 4, bits
Bit name Comment
OUT9OR
OUT8OR
OUT7OR
OUT6OR
Overcurrent recovery enable:
1: the output is automatically reactivated after a delay time with programmable duty cycle
(CR3/Bit14)
0: clear status register to enable the output after an overcurrent event
OUT9PWM1
OUT8PWM3
OUT7PWM1
If the PWM1/2/3 enable bit is set and the output is enabled, the output is switched on only if the
PWM1/2/3 input is high, and switched off if the PWM1/2/3 input is low.
OUT8 is controlled by PWM3, OUT7 is controlled by PWM1 and OUT6 is controlled by PWM2.
OUT6PWM2 reserved Reserved bit, has always to be written to 0 and reads always 0
ECVOR
Overcurrent recovery enable:
1: the output is automatically reactivated after a delay time with programmable duty cycle
(CR3/Bit14)
0: clear status register to enable the output after an overcurrent event reserved Reserved bit, has always to be written to 0 and reads always 0
ECVPWM1
If the PWM1 enable bit is set and the output is enabled, the output is switched on only if the PWM1 input is high, and switched off if the PWM1 input is low.
Doc ID 022637 Rev 2 57/68
SPI control and status registers L99MM70XP
Table 39.
Control register 4, bits (continued)
Bit name
CM3
CM2
CM1
CM0
Comment
Current monitor: the current image of the selected high-side output is multiplexed to the CM output (see table below).
CM3 CM2 CM1 CM0 Current image of
1
1
0
1
1
0
0
1
0
1
1
0
1
0
0
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CM deactivated
CM HS1 active
CM HS2 active
CM HS3 active
CM HS4 active
CM HS5 active
CM HS6 active
CM HS7 active
CM HS8 active
CM HS9 active reserved reserved reserved reserved reserved reserved
58/68 Doc ID 022637 Rev 2
L99MM70XP SPI control and status registers
Table 40.
Configuration register
Bit
Reset state
Name
7
0
6
0
ECV
ECFD
OUT7
OLMASK
5
0
Configuration register (3Fh)
4
0
3
0
2
0
OUT1HS
OLMASK
OUT1LS
OLMASK
TW_OL
MASK
1
0
0
0
WD
TRIG
Table 41.
Bit name
Configuration register, bits
Comment
The bits 15 to 8 of the configuration register have to be written to 0, and read always 0
ECV
ECFD
OUT7
OLMASK
Mask the ECV, ECFD (HS and LS) and OUT7 open-load diagnostics bits (status reg. 2, bits 11, 14,
15): an open-load event is not considered in the open-load bit (TW_OL) of the global status register
OUT1HS
OLMASK
OUT1LS
OLMASK
TW_OL
MASK
WDTRIG
Mask the OUTHS1 open-load diagnostic bit (status reg. 1/bit 1): an open-load event (under-current status bit of OUT1HS) is not considered in open-load bit (TW_OL) of the global status register.
Mask the OUTLS1 open-load diagnostic bit (status reg. 1/bit 0): an open-load event (under-current status bit of OUT1LS) is not considered in open-load bit (TW_OL) of the global status register.
Mask the TW_OL bit in global status byte: a temperature warning or open-load event is not considered in the “global error flag”
Trigger the watchdog.
This bit has to be toggled regularly if the watchdog is active. The watchdog can be triggered either by this bit or by bit 0 of the Control Register 1.
Doc ID 022637 Rev 2 59/68
SPI control and status registers L99MM70XP
Table 42.
Status register 1
Bit
Reset state
Name
15
0
ECFDLS
14
0
13
0
12
0
11
0
10
0
Status register 1 (11h)
9 8 7 6
0 0 0 0
5
0
4
0
3
0
2
0
1
0
0
0
ECV
LS
OUT
9HS
OUT
8HS
OUT
7HS
OUT
6HS
OUT5
HS
OUT5
LS
OUT4
HS
OUT4
LS
OUT3
HS
OUT3
LS
OUT2
HC
OUT2
LS
OUT1
HS
OUT1
LS
Table 43.
Status register 1, bits
Bit name Comment
ECFDLSOC
ECVLSOC
OUT9HSOC
OUT8HSOC
OUT7HSOC
OUT6HSOC
OUT5HSOC
OUT5LSOC
OUT4HSOC
OUT4LSOC
OUT3HSOC
OUT3LSOC
OUT2HSOC
OUT2LSOC
OUT1HSOC
OUT1LSOC
Overcurrent diagnosis:
In case of an overcurrent event the corresponding status bit is set and the output driver is disabled.
If the overcurrent recovery enable bit is set, the output is automatically reactivated after a delay time resulting in a PWM modulated current with a programmable duty cycle.
If the overcurrent recovery bit is not set, the microcontroller has to clear the overcurrent bit to reactivate the output driver.
60/68 Doc ID 022637 Rev 2
L99MM70XP SPI control and status registers
Table 44.
Status register 2
Bit
Reset state
Name
Status register 2 (12h)
15
0
ECFD
LS
14
0
ECV
LS
13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
OUT9 OUT8 OUT7 OUT6
OUT5
HS
OUT5
LS
OUT4
HS
OUT4
LS
OUT3
HS
OUT3
LS
OUT2
HS
OUT2
LS
OUT1
HS
OUT1
LS
Table 45.
Status register 2, bits
Bit name Comment
ECFDLSOL
ECVLSOL
OUT9OL
OUT8OL
OUT7OL
OUT6OL
OUT5HSOL
OUT5LSOL
OUT4HSOL
OUT4LSOL
OUT3HSOL
OUT3LSOL
The open-load detection monitors the load current in each activated output stage. If the load current is below the under current detection threshold for at least t dOL
= 2ms, the corresponding open-load bit is set. Due to the mechanical / electrical inertia of typical loads a short activation of the outputs
(e.g. 3 ms) can be used to test the open-load status without changing the mechanical / electrical state of the loads.
The open-load detection of OUT1 HS and OUT1 LS can be masked by the configuration register
(Bit 4/5).
The open-load detection of ECFDLS, ECVLS and OUT7 can be masked by the configuration register (Bit 6).
OUT2HSOL
OUT2LSOL
OUT1HSOL
OUT1LSOL
Maskable by the configuration register: an open-load event is not considered in open-load bit (TW_OL) of global status register.
Doc ID 022637 Rev 2 61/68
SPI control and status registers L99MM70XP
Table 46.
Status register 3
Bit
Reset state
Name
15
0
LIN perm dom
14
0
LIN
TXD dom
Status register 3 (13h)
9 8 7 6 13 12 11 10
0 0
LIN prem rec
VCC fail
0 0
UV OV
0
WD timer state
0
WD timer state
0 0
5
0
4
0
ECFD
HSOC
ECFD
HSOL
ECV
NR
ECVO
3
0
2
0
1
0
TSD2 TSD1 TW
0
0
Table 47.
Status register 3, bits
Bit name Comment
LIN perm dom
If the bus state is dominant (low) for more than 12 ms a permanent dominant status is detected.
The status bit is set.
LIN TXD dom If TXD is in dominant state (low) for more than 12 ms, the transmitter is disabled and this bit is set.
LIN perm rec
V
CCFail
UV
OV
WDTIM1
If TXD changes to dominant (low) state but RXD signal does not follow within 40 µs, the transmitter is disabled and this bit is set.
V
CCFail
:
V
CC
< 2 V for more than 2 µs
V
S
undervoltage detected
V
S
overvoltage detected
If an over/under voltage event is detected, the outputs are disabled and one of these bits is set.
If the OVUVR bit is 0, the outputs are enabled automatically after an over/under voltage event and the UV/OV bit is reset.
If the OVUVR bit is 1, the outputs are enabled after clearing the
UV/OV bit by SPI command (read and clear operation)
Watchdog state:
Display which part of the total WD time (100 ms) has been elapsed:
WDTIM1 WDTIM0 Elapsed time
WDTIM0
0
0
1
0
1
1
< 1/3 of the total WD time
< 2/3 of the total WD time
< 3/3 of the total WD time
ECFDHSOC
ECFDHSOL
ECVNR
ECVO
TSD2
TSD1
TW
Overcurrent diagnosis:
In case of an overcurrent event on ECFDHS the status bit is set and the output driver is disabled.
The open-load detection monitors the load current in the ECFDHS. If the load current is below the under current detection threshold for at least t dOL
= 2 ms, the open-load bit is set.
ECV voltage not reached
ECV voltage too high
Two comparators monitor the voltage at pin ECV in electrochrome mode. If this voltage is below / above the programmed target, these bits signal the difference after at least 32 µs. The bits are not latched and may toggle after at least 32 µs, if the ECV voltage has not yet reached the target.
Thermal shutdown 2 (> 160 °C)
Thermal shutdown 1 (> 150 °C)
Thermal warning (> 140 °C)
62/68 Doc ID 022637 Rev 2
L99MM70XP SPI control and status registers
All bits except the WDTIM1, WDTIM0, ECVNR and ECVO bits can be reset by a read and clear operation on SR4.
Table 48.
Status register 4
Status register 4 (14h)
Bit
Reset state
Name
15
0
WD fail
14
0
WD fail
13
0
WD fail
12
0
WD fail
11 10 9
0 0 0
Forced
SleepWD
Forced
SleepTSD
Dev
State
8
0
Dev
State
7
0
6 5 4 3 2 1 0
0 0 0 1 0 0 0
VCC
Restart
VCC
Restart
VCC
Restart
NOT
RDY
SPI
Wake
LIN
Wake
INH
Wake
Table 49.
Status register 4, bits
Bit name
WDFAIL3
WDFAIL2
WDFAIL1
WDFAIL0
Nr of watchdog fails
These bits are not clearable, are cleared with a proper watchdog trigger or if the chip is sent to V
BAT-standby
by the watchdog.
Forced sleep
WD
Forced sleep
TSD
This bit is set if the chip has been set to V
BAT-standby by the watchdog
mode
This bit is set if the chip has been set to V
BAT-standby by a thermal shutdown
mode
These bits are latched until a “read and clear” access on SR4.
DEVSTATE1 Signal device state:
DEV
STATE1
DEV
STATE2
State
DEVSTATE0
0
0
1
1
0
1
0
1
Comment
Active
V
CC-standby
V
BAT
standby or POR
Flash
These bits are latched until a “read and clear” access on SR 4.
The device state is updated with any state transition and with a read and clear command on status register 4.
Therefore, the first read operation after entering active mode or flash mode reads the last device state. Read operations after a read and clear operation reads the current device state. After power-on reset, the device state is V
BAT-standby
.
VCCRestart2
VCCRestart1 Nr of TSD restart trials
These bits are latched until a “read and clear access” on SR 4.
VCCRestart0
NOTRDY
Not ready: This bit is set for 200µs after switching from standby to active mode. It is cleared automatically. While the bit is set, the output drivers are disabled.
This bit is not clearable, it is cleared automatically.
Doc ID 022637 Rev 2 63/68
SPI control and status registers L99MM70XP
Table 49.
Status register 4, bits (continued)
Bit name Comment
SPIWake
LINWake
Indicates wake-up from V
CC-standby
mode via SPI
Indicates wake-up from V
CC-standby
mode via LIN
INHWake Indicates wake-up from V
CC-standby
mode via INH
These bits are latched until a “read and clear” access on SR4.
64/68 Doc ID 022637 Rev 2
L99MM70XP
10
Package and packaging information
Package and packaging information
10.1 ECOPACK
®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
10.2 PowerSSO-36 package information
Figure 19.
PowerSSO-36 package dimensions
AG00066V1
Doc ID 022637 Rev 2 65/68
Package and packaging information
U
X
Y
Q
S
T h k
L
M
N
O e e3
F
G
G1
H
A
A2 a1 b c
D
1
E
1
Table 50.
PowerSSO-36 mechanical data
Symbol
Min.
-
4.3
6.9
-
-
-
-
0°
0.55
-
-
-
-
-
-
-
-
10.1
2.15
2.15
0
0.18
0.23
10.10
7.4
Note:
L99MM70XP
Millimeters
Typ.
1
-
-
0.8
2.9
3.65
-
-
-
4.3
-
1.2
0.5
8.5
2.3
-
-
-
-
-
-
-
-
-
-
Max.
-
5.2
7.5
-
-
-
0.4
8°
0.85
-
10°
-
-
-
-
0.1
0.06
10.5
2.45
2.35
0.10
0.36
0.32
10.50
7.6
“D” and “E” do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.15 mm per side.
66/68 Doc ID 022637 Rev 2
L99MM70XP
Table 51.
Document revision history
Date Revision
04-Jan-2012
19-Sep-2013
1
2
Initial release.
Updated Disclaimer.
Changes
Revision history
Doc ID 022637 Rev 2 67/68
L99MM70XP
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