STMicroelectronics L9951 Datasheet

PDF

Belge

Reklam

L9951

L9951XP

Rear door actuator driver

Features

Type

L9951

L9951XP

Outputs

(1)

OUT1

OUT2

OUT3

OUT4

OUT5

R on

(2)

150 m Ω

200 m Ω

800 m

800 m Ω

OUT

7.4 A

5 A

1.25 A

28 V

See block diagram.

Typical values.

■

One half bridge for 7.4 A load (R on

= 150 m Ω )

Two half bridges for 5 A load (R on

= 200 m Ω )

Two highside drivers for 1.25 A load

(R on

= 800 m Ω )

Programmable softstart function to drive loads with higher inrush currents (i.e.current > 7.4A,

>5A, >1.25A)

Very low current consumption in standby mode

< 3µA, typ. T j

≤ 85°C)

All outputs short circuit protected

Current monitor output for all highside drivers

All outputs over temperature protected

Open-load diagnostic for all outputs

Overload diagnostic for all outputs

Programmable PWM control of all outputs

Charge pump output for reverse polarity protection

Table 1.

Device summary

Package

PowerSO-36

PowerSSO-36

PowerSO-36 PowerSSO-36

Tube

L9951

L9951XP

Applications

■ Rear door actuator driver with bridges for door lock and safe lock and two 5W or 10W - light bulbs.

Description

The L9951 and L9951XP are microcontroller driven, multifunctional rear door actuator drivers for automotive applications. Up to two DC motors and two grounded resistive loads can be driven with three half bridges and two hide side drivers.

The integrated standard serial peripheral interface

(SPI) controls all operation modes (forward, reverse, brake and high impedance). All diagnostic information is available via the SPI.

Order codes

Tape and reel

L9951TR

L9951XPTR

September 2013 Doc ID 14173 Rev 9 1/36 www.st.com

Contents

2/36

L9951 / L9951XP

Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2

ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4

Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 10

2.5

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.6

SPI - electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1

Dual power supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2

Standby - mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.3

Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.4

Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.5

Over-voltage and under-voltage detection . . . . . . . . . . . . . . . . . . . . . . . . 20

3.6

Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 20

3.7

Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.8

Over load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.9

Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.10

PWM input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.11

Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.12

Programmable softstart function to drive loads with higher inrush current 21

Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.1

Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.2

Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3

Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.4

Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.5

Serial clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.6

Input data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.7

Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Doc ID 14173 Rev 9

L9951 / L9951XP

Contents

4.8

Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.1

ECOPACK

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.2

PowerSO-36™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.3

PowerSSO-36™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.4

PowerSO-36™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.5

PowerSSO-36™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Doc ID 14173 Rev 9 3/36

List of tables

List of tables

L9951 / L9951XP

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Overvoltage and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 9.

Current monitor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 10.

Charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 11.

OUT 1 - OUT 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 12.

Delay time from standby to active mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 13.

Inputs: CSN, CLK, PWM1/2 and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 14.

DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 15.

DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 16.

DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 17.

EN, CSN timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 18.

Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 19.

SPI - Input data and status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 20.

SPI - Input data and status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 21.

PowerSO-36™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 22.

PowerSSO-36™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 23.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4/36 Doc ID 14173 Rev 9

L9951 / L9951XP

List of figures

List of figures

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2.

Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3.

SPI - transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 4.

SPI - input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 5.

SPI - DO valid data delay time and valid time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 6.

SPI - DO enable and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 7.

SPI - driver turn-on/off timing, minimum CSN HI time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 8.

SPI - timing of status bit 0 (fault condition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 9.

Example of programmable softstart function for inductive loads . . . . . . . . . . . . . . . . . . . . 21

Figure 10.

Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 11.

PowerSO-36™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 12.

PowerSSO-36™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 13.

PowerSO-36

tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 14.

PowerSO-36

tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 15.

PowerSSO-36

tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 16.

PowerSSO-36

tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Doc ID 14173 Rev 9 5/36

Block diagram and pin description

1 Block diagram and pin description

Figure 1.

Block diagram

* Note: Value of capacitor has to be choosen carefully to limit the VS voltage below absolute maximum ratings in case of an unexpected freewheeling condition of inductive loads (e.g. TSD, POR)

Reverse

Polarity

Protection

VREG

VCC

100µF

100nF

100

EMC

Optimization

100nF

CLK

CSN

VCC

Charge

Pump

100k

µC

BAT

OUT1

OUT2

OUT3

Lock

Safe Lock

OUT4

Exterior Light

OUT5

Safety Light

L9951 / L9951XP

CM / PWM

MUX

GND ** Note: Resistors between µC and L9951 are recommended to limit currents for negative voltage transients at VBAT (e.g. ISO type 1 pulse)

+ Note: Using a ferrite instead of 10ohm will additionally improve EMC behavior

6/36 Doc ID 14173 Rev 9

L9951 / L9951XP Block diagram and pin description

Table 2.

Pin

1, 18, 19,

6, 7, 14,

15, 23, 24,

29, 32

3, 4, 34

Pin definitions and functions

Symbol

GND

OUT1

CM/PWM

CSN

VCC

CLK

Function

Ground .

Reference potential.

Note: For the capability of driving the full current at the outputs all pins of

GND must be externally connected.

Power supply voltage (external reverse protection required).

For EMI reason a ceramic capacitor as close as possible to GND is recommended.

Note: for the capability of driving the full current at the outputs all pins of

VS must be externally connected.

Half-bridge output 1.

The output is built by a high side and a low side switch, which are internally connected. The output stage of both switches is a power

DMOS transistor. Each driver has an internal reverse diode (bulk-draindiode: high side driver from output to VS, low side driver from GND to output). This output is over-current and open-load protected.

Note: for the capability of driving the full current at the outputs all pins of

OUT1 must be externally connected.

Serial data input.

The input requires CMOS logic levels and receives serial data from the microcontroller. The data is a 16bit control word and the least significant bit (LSB, bit 0) is transferred first.

Current monitor output/PWM input.

Depending on the selected multiplexer bits (bit 9, 10, 11) of Input Data

Register this output sources an image of the instant current through the corresponding high side driver with a ratio of 1/10.000. This pin is bidirectional. The microcontroller can overwrite the current monitor signal to provide a PWM input for all outputs.

Testmode:

If CSN is raised above 7.5V the device will enter the test mode. In test mode this output can be used to measure some internal signals (see

Table 18

Chip select not input / Testmode .

This input is low active and requires CMOS logic levels. The serial data transfer between L9951 and micro controller is enabled by pulling the input CSN to low level. If an input voltage of more than 7.5V is applied to

CSN pin the L9951 will be switched into a test mode.

Serial data output .

The diagnosis data is available via the SPI and this tristate-output. The output will remain in tristate, if the chip is not selected by the input CSN

(CSN = high).

Logic supply voltage .

For this input a ceramic capacitor as close as possible to GND is recommended.

Serial clock input .

This input controls the internal shift register of the SPI and requires

CMOS logic levels.

Doc ID 14173 Rev 9 7/36

Block diagram and pin description L9951 / L9951XP

Table 2.

Pin

Pin definitions and functions (continued)

Symbol Function

16, 17

20, 21

OUT2

OUT3

Half-bridge output 2 (see OUT1 - pin 3, 4).

Note: for the capability of driving the full current at the outputs all pins of

OUT2 must be externally connected.

Half-bridge output 3 (see OUT1 - pin 3, 4).

Note: for the capability of driving the full current at the outputs all pins of

OUT3 must be externally connected.

Charge Pump Output .

This output is provided to drive the gate of an external n-channel power

MOS used for reverse polarity protection (see

Figure 1

27 EN

Enable input.

If Enable input is forced to GND the device will enter Standby-Mode. The outputs will be switched off and all registers will be cleared

33, 35 OUT4, OUT5

High side driver output 4, 5 .

The output is built by a high side switch and is intended for resistive loads, hence the internal reverse diode from GND to the output is missing. For ESD reason a diode to GND is present but the energy which can be dissipated is limited. The high side driver is a power DMOS transistor with an internal reverse diode from the output to VS (bulkdrain-diode). The output is over-current and open-load protected.

Figure 2.

Configuration diagram (top view)

VS .

8/36 Doc ID 14173 Rev 9

L9951 / L9951XP Electrical specifications

Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics sure program and other relevant quality document

Table 3.

Absolute maximum ratings

Symbol Parameter

DC supply voltage

DI,

CLK

CSN,

OUT1,2,3

OUT4,5

Single pulse t max

< 400ms

Stabilized supply voltage, logic supply

Digital input / output voltage

Current monitor output

Charge pump output

Output current

Value

-0.3 to 28

-0.3 to 5.5

-0.3 to V

+ 0.3

-0.3 to V

+ 0.3

-25 to V

+ 11

±10

±5

Unit

Table 4.

ESD protection

Parameter

All pins

Output pins: OUT1 - OUT5

HBM according to CDF-AEC-Q100-002.

HBM with all unzapped pins grounded.

Table 5.

Symbol

T j

Thermal data

Parameter

Operating junction temperature

Value

± 4

(1)

(2)

Unit kV kV

Value

-40 to 150

Unit

°C

Doc ID 14173 Rev 9 9/36

10/36

Electrical specifications

2.4

L9951 / L9951XP

Temperature warning and thermal shutdown

Table 6.

Symbol

Temperature warning and thermal shutdown

Parameter

T jTW ON

Temperature warning threshold junction temperature

T jTW OFF

Temperature warning threshold junction temperature

T jTW HYS

Temperature warning hysteresis

T jSD ON

Thermal shutdown threshold junction temperature

T jSD OFF

Thermal shutdown threshold junction temperature

T jSD HYS

Thermal shutdown hysteresis

T j increasing

T j decreasing

T j increasing

T j decreasing

Min.

Typ.

Max.

Unit

130

150

150 °C

°C

°K

170 °C

°C

°K

= 8 to 16 V, V

= 4.5 to 5.3 V, T j

= - 40 to 150 °C, unless otherwise specified.

The voltages are referred to GND and currents are assumed positive, when the current flows into the pin.

Table 7.

Symbol

Supply

Parameter Test condition

Operating supply voltage range

DC supply current

quiescent supply current

= 13V, V

= 5.0V

active mode

OUT1 - OUT5 floating

= 13V, V

= 0V standby mode

OUT1 - OUT5 floating

T test

=-40°C, 25°C

T test

= 130°C

Min.

Typ.

Max.

Unit

V mA

µA

Doc ID 14173 Rev 9

L9951 / L9951XP

Table 7.

Symbol

Supply (continued)

Parameter

DC supply current

quiescent supply current

+ I

Sum quiescent supply current

Test condition

= 13V, V

= 5.0V

CSN = V

CC active mode

= 13V, V

= 5.0V

CSN = V

CC standby mode

OUT1 - OUT5 floating

= 13V, V

= 5.0V

CSN = V

CC standby mode

OUT1 - OUT5 floating

Electrical specifications

Min.

Typ.

Max.

Unit

1 3 mA

1 3 µA

7 23 µA

Table 8.

Symbol

Overvoltage and undervoltage detection

Parameter Test condition

SUV ON

SUV OFF

VS UV-threshold voltage

SUV hyst

VS UV-hysteresis

SOV OFF

SOV ON

VS OV-threshold voltage

increasing

decreasing

SUV ON

- V

SUV OFF

increasing

decreasing

SOV hyst

POR OFF

VS OV-hysteresis

Power-on-reset threshold

POR ON

POR hyst

Power-on-reset threshold

SOV OFF

- V

SOV ON

increasing

decreasing

Power-on-reset hysteresis V

POR OFF

- V

POR ON

Min.

Typ.

Max.

Unit

6.0

5.4

7.2

6.5

17.5

3.1

0.55

0.5

0.3

24.5

4.4

Table 9.

Symbol

CM,r

CM acc

Current monitor output

Parameter Test condition

Functional voltage range V

= 5V

Current monitor output ratio:

/ I

OUT1,2,3,4,5

0V ≤ V

≤ 4V, VCC=5V

Current monitor accuracy

0V ≤ VCM ≤ 4V,

=5V,

OUT1-5,low

=500mA

OUT1,high

=6A

OUT2,3,high

=4.9A

OUT4,5,high

=1.2A

(FS=full scale=600 μ A)

Min.

Typ.

Max.

Unit

4 V

1:10000

4% +

1%FS

8% +

2%FS

Doc ID 14173 Rev 9 11/36

Electrical specifications L9951 / L9951XP

Table 10.

Charge pump output

Symbol Parameter

Charge pump output voltage

Charge pump output current

Test condition

=8V, I

= -60µA

=10V, I

= -80µA

≥

12V, I

= -100µA

= V

+10V

=13.5V

Min.

100

Typ.

Max.

Unit

150 300 µA

Table 11.

OUT 1 - OUT 5

Symbol Parameter

R r r

ON OUT4,

ON OUT5 t

ON OUT1

ON OUT2

ON OUT3 d ON H

On-resistance to supply or GND

Output delay time, highside driver on

Test condition

= 13.5 V, T j

= 25 °C,

OUT1

= ± 3 A

= 13.5 V, T j

= 125 °C,

OUT1

= ± 3 A

= 8.0 V, T j

= 25 °C,

OUT1

= ± 3 A

= 13.5 V, T j

= 25 °C,

OUT2,3

= ± 3 A

= 13.5 V, T j

= 125 °C,

OUT2,3

= ± 3 A

= 8.0 V, T j

= 25 °C,

OUT2,3

= ± 3 A

VS = 13.5 V, T j

= 25 °C,

OUT4,5

= ± 0.8 A

= 13.5 V, T j

= 125 °C,

OUT4,5

= ± 0.8 A

= 8.0 V, T j

= 25 °C,

OUT4,5

= ± 0.8 A

= 13.5 V, corresponding lowside driver is not active

Min.

OUT1

Output current limitation to supply or GND

OUT2

OUT3

OUT4

OUT5

Output current limitation to supply or GND

Output current limitation to GND

Sink and source

7.4

5.0

Source 1.25

20 t d OFF H

Output delay time, highside driver off

= 13.5 V 80 t d ON L

Output delay time, lowside driver on

= 13.5 V, corresponding highside driver is not active

Typ.

Max.

Unit

150 200 m Ω

225

150

200

300

200

800

1250 1700

800

200

300

200

270

400

270

1100

15.5

10.5

2.6

300

80 m Ω m Ω m Ω m Ω m Ω m Ω m Ω m Ω

µs

12/36 Doc ID 14173 Rev 9

L9951 / L9951XP Electrical specifications

Table 11.

OUT 1 - OUT 5 (continued)

Symbol Parameter Test condition Min.

t d OFF L

I t t

D HL

D LH

QLH

QLL

OLD1

Output delay time, lowside driver off

Cross current protection time, source to sink

Cross current protection time, sink to source t t

= 13.5 V d ON L d ON H

- t

- t d OFF H, d OFF L

Switched-off output current highside drivers of

OUT1-5

OUT1-5 mode

= 0V, standby

OUT1-5

= 0V, active mode -40

Switched-off output current lowside drivers of

OUT1-3

OUT1-3 mode

= V

, standby

OUT1-3

= V

, active mode -40

Open-load detection current of OUT1

OLD23

OLD45 t dOL

Open-load detection current of OUT2, OUT3

Open-load detection current of OUT4 and

OUT5

Minimum duration of open-load condition to set the status bit t

ISC

Minimum duration of over-current condition to switch off the driver dV

OUT1

/dt Slew rate of OUT1

=13.5 V

I load

= ±1.5 A dV

OUT23

/dt Slew rate of OUT2, OUT3

= 13.5 V

I load

= ±1.5 A dV

OUT45

/dt Slew rate of OUT4, OUT5

= 13.5 V

I load

= - 0.8 A

500

0.1

Typ.

Max.

Unit

150

200

-2

-15

160

0.2

300

400

-5

100

240

3000

100

0.4

µs

µs mA mA

µs

V/µs

µA

µA mA

Doc ID 14173 Rev 9 13/36

Electrical specifications

2.6

L9951 / L9951XP

SPI - electrical characteristics

= 8 to 16 V, V

= 4.5 to 5.3 V, T j

= - 40 to 150 °C, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin).

Table 12.

Delay time from standby to active mode

Symbol Parameter Test condition t set

Internal startup time

Switching from standby to active mode. Time until not Ready Bit goes low.

Min. Typ.

Max.

Unit

80 300 µs

Table 13.

Inputs: CSN, CLK, PWM1/2 and DI

Symbol Parameter Test condition

V inL

V inH

V inHyst

CSN in

CLK in

DI in

EN in

Input low level

Input high level

Input hysteresis

Pull up current at input CSN

Pull down current at input CLK

Pull down current at input DI

Pull down resistance at input

Input capacitance at input

CLK, DI and PWM

= 5V

1.5

0.5

CSN

= 3.5V V

= 5V -50

CLK

= 1.5V

= 0 to 5.3V

100

Min. Typ.

Max.

Unit

2.0

3.0

3.5

-25

-10

µA

210

480

15 k Ω pF

Note: Value of input capacity is not measured in production test. Parameter guaranteed by design.

Table 14.

DI timing

(1)

Symbol Parameter t t t t

CLK

CLKH

CLKL set CSN

Clock period

Clock high time

Clock low time

CSN setup time, CSN low before rising edge of CLK t set CLK

CLK setup time, CLK high before rising edge of CSN

DI setup time t set DI t hold time

DI hold time

Test condition

= 5V

Min. Typ.

Max.

Unit

1000

400

400 ns ns ns

400

200

200 ns ns ns ns

14/36 Doc ID 14173 Rev 9

L9951 / L9951XP

Table 14.

DI timing

(1)

(continued)

Symbol Parameter t t r in f in

Rise time of input signal DI,

CLK, CSN

Fall time of input signal DI,

CLK, CSN

See Figure 3

and

Figure 4

Note:

Test condition

= 5V

Electrical specifications

Min. Typ.

Max.

Unit

100 ns

DI timing parameters tested in production by a passed/failed test:

Tj= -40°C/+25°C: SPI communication @2MHZ.

Tj= +125°C: SPI communication @1.25MHZ.

Table 15.

Symbol Parameter Test condition Min.

Typ.

Max.

Unit

V V

DOL

DOH

Output low level

Output high level

VCC = 5 V, I

= -4mA

= 4 mA

-0.4

0.2

-0.2

DOLK

(1)

Tristate leakage current

Tristate input capacitance

CSN

= V

0V < V

< V

CSN

= V

0V < V

< 5.3V

-10

Value of input capacity is not measured in production test. Parameter guaranteed by design.

0.4

µA pF

Table 16.

DO timing

(1)

Symbol Parameter Test condition t t t t t r DO f DO en DO tri L dis DO L tri en DO tri H

DO rise time C

= 100 pF, I load

= -1mA

DO fall time

DO enable time from tristate to low level

= 100 pF, I load

= 1mA

= 100 pF, I load

= 1mA pull-up load to V

DO disable time from low level to tristate

= 100 pF, I load

= 4 mA pull-up load to V

DO enable time from tristate to high level

=100 pF, I load

= -1mA pull-down load to GND t dis DO H tri t d DO

DO disable time from high level to tristate

= 100 pF, I load

= -4mA pull-down load to GND

DO delay time

< 0.3 V

, V

> 0.7V

= 100pF

See

Figure 5 and Figure 6

Min.

Typ.

Max.

Unit

140

100

100 250

380 450

100 250

380 450

250 ns ns ns ns ns ns ns

Doc ID 14173 Rev 9 15/36

Electrical specifications L9951 / L9951XP

Table 17.

EN, CSN timing

(1)

Symbol Parameter t

EN_CSN_LO

Minimum EN high before sending first SPI frame, i.e.

CSN going low t

CSN_HI,min

Minimum CSN HI time between two SPI frames

See

Figure 7

Test condition

Transfer of SPI-command to input register

Min.

Typ.

Max.

Unit

µs

Figure 3.

SPI - transfer timing diagram

CSN high to low: DO enabled

CSN time

CLK

DO 0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

DI: data will be accepted on the rising edge of CLK signal actual data

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

DO: data will change on the falling edge of CLK signal

1 2 3 status information

4 5 6 7 8 9 10 11 12 13 14 15 fault bit CSN low to high: actual data is transfered to output power switches old data e.g.OUT1

Figure 4.

SPI - input timing

0 1 time new data

0 1 time

0 1 time actual data time

CSN 0.8 VCC

0.2 VCC t set CSN t

CLKH t set CLK

CLK

0.8 VCC

0.2 VCC

DI t set DI t hold DI

Valid t

CLKL

Valid

0.8 VCC

0.2 VCC

16/36 Doc ID 14173 Rev 9

L9951 / L9951XP

Figure 5.

SPI - DO valid data delay time and valid time t f in t r in

Electrical specifications

CLK

0.8 VCC

0.5 VCC

0.2 VCC t r DO

(low to high)

0.8 VCC

0.2 VCC t d DO t f DO

(high to low)

0.8 VCC

0.2 VCC

Figure 6.

SPI - DO enable and disable time t f in

CSN t r in

0.8 VCC

50%

0.2 VCC

DO pull-up load to VCC

50% t en DO tri L t dis DO L tri

50% DO pull-down load to GND

C = 100 pF t en DO tri H t dis DO H tri

Doc ID 14173 Rev 9 17/36

Electrical specifications

Figure 7.

SPI - driver turn-on/off timing, minimum CSN HI time

CSN low to high: data from shift register is transferred to output power switches t r in t

CSN_HI,min t f in

L9951 / L9951XP

CSN

80%

50%

20% t dOFF output current of a driver

ON state OFF state

80%

50%

20% t dON t

OFF t

ON output current of a driver

OFF state ON state

80%

50%

20%

Figure 8.

SPI - timing of status bit 0 (fault condition)

CSN high to low and CLK stays low: status information of data bit 0 (fault condition) is transfered to DO

CSN

CLK time time

DI time

DI: data is not accepted

DO: status information of data bit 0 (fault condition) will stay as long as CSN is low time

18/36 Doc ID 14173 Rev 9

L9951 / L9951XP Application information

3.1 Dual power supply: V

S

and V

CC

The power supply voltage V

supplies the half bridges and the high side drivers. An internal charge-pump is used to drive the high side switches. The logic supply voltage V

(stabilized 5V) is used for the logic part and the SPI of the device. Due to the independent logic supply voltage the control and status information will not be lost, if there are temporary spikes or glitches on the power supply voltage. In case of power-on (V

increases from under voltage to V

POR OFF

= 4.0V, typical) the circuit is initialized by an internally generated power-on-reset (POR).

If the voltage V

decreases under the minimum threshold (V

POR ON

=3.6V, typical), the outputs are switched to tristate (high impedance) and the status registers are cleared.

The standby mode of the L9951 is activated by switching the EN input do GND. All latched data will be cleared and the inputs and outputs are switched to high impedance. In the standby mode the current at V

) is less than 3 µA (1µA) for CSN = high (DO in tristate).

If EN is switched to 5V the device will enter the active mode. In the active mode the chargepump and the supervisor functions are activated.

Each half bridge is built by an internally connected high side and a low side power DMOS transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs OUT1 to OUT3 without external free-wheeling diodes. The high side drivers OUT4 to OUT5 are intended to drive resistive loads. Hence only a limited energy

(E<0.5mJ) can be dissipated by the internal ESD-diodes in freewheeling condition. For inductive loads (L > 50µH) an external free-wheeling diode connected to GND and the corresponding output is needed.

All diagnostic functions (over/open-load, power supply over-/undervoltage, temperature warning and thermal shutdown) are internally filtered and the condition has to be valid for at least 32µs (open-load: 1ms, respectively) before the corresponding status bit in the status registers will be set. The filters are used to improve the noise immunity of the device. Openload and temperature warning function are intended for information purpose and will not change the state of the output drivers. On contrary, the over load and thermal shutdown condition will disable the corresponding driver (over load) or all drivers (thermal shutdown), respectively. Without setting the over-current recovery bit in the Input Data Register to logic high, the microcontroller has to clear the over-current status bit to reactivate the corresponding driver. Each driver has a corresponding over-current recovery bit. If this bit is set, the device will automatically switch-on the outputs again after a short recovery time. The duty cycle in over-current condition can be programmed by the SPI interface (12% or 25%).

With this feature the device can drive loads with start-up currents higher than the overcurrent limits (e.g. inrush current of lamps, cold resistance of motors and heaters).

Doc ID 14173 Rev 9 19/36

Application information

3.5

L9951 / L9951XP

Over-voltage and under-voltage detection

If the power supply voltage V

rises above the over-voltage threshold V

SOV OFF

(typical

21V), the outputs OUT1 to OUT5 are switched to high impedance state to protect the load and the internal charge-pump is turned-off. When the voltage V

drops below the undervoltage threshold V

SUV OFF

(UV-switch-OFF voltage), the output stages are switched to the high impedance to avoid the operation of the power devices without sufficient gate driving voltage (increased power dissipation). If the supply voltage V

recovers to normal operating voltage the output stages return to the programmed state (input register 0: bit

12=0). If the undervoltage / overvoltage recovery disable bit is set, the automatic turn-on of the drivers is deactivated. The microcontroller needs to clear the status bits to reactivate the drivers.

3.6 Temperature warning and thermal shutdown

If junction temperature rises above T j TW

a temperature warning flag is set and is detectable via the SPI. If junction temperature increases above the second threshold T j SD

, the thermal shutdown bit will be set and power DMOS transistors of all output stages are switched off to protect the device. In order to reactivate the output stages the junction temperature must decrease below T jSD

- T microcontroller.

jSD HYS

and the thermal shutdown bit has to be cleared by the

The open-load detection monitors the load current in each activated output stage. If the load current is below the open-load detection threshold for at least 1 ms (t dOL

) the corresponding open-load bit is set in the status register. Due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3ms) can be used to test the open-load status without changing the mechanical/electrical state of the loads.

3.8 Over detection

In case of an over-current condition a flag is set in the status register in the same way as open-load detection. If the over-current signal is valid for at least t

ISC

=32µs, the over-current flag is set and the corresponding driver is switched off to reduce the power dissipation and to protect the integrated circuit. If the over-current recovery bit of the output is zero the microcontroller has to clear the status bits to reactivate the corresponding driver.

20/36

The current monitor output sources a current image at the current monitor output which has a fixed ratio (1/10000) of the instantaneous current of the selected high side driver. The bits

9, 10 and 11 of the input data register 0 control which of the outputs OUT1 to OUT5 will be multiplexed to the current monitor output. The current monitor output allows a more precise analysis of the actual state of the load rather than the detection of an open- or overload condition. For example this can be used to detect the motor state (starting, free-running, stalled). Moreover, it is possible to regulate the power of the defroster more precise by measuring the monitor current.

Doc ID 14173 Rev 9

L9951 / L9951XP Application information

Each driver has a corresponding PWM enable bit which can be programmed by the SPI interface. If the PWM enable bit is set, the outputs OUT1 to OUT5 are controlled by the logically AND-combination of the signal applied to the PWM input and the output control bit in input data register1.

The three half-brides of the device are cross-current protected by an internal delay time. If one driver (LS or HS) is turned-off the activation of the other driver of the same half bridge will be automatically delayed by the cross-current protection time. After the cross-current protection time is expired the slew-rate limited switch-off phase of the driver will be changed to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. Due to this behavior it is always guaranteed that the previously activated driver is totally turned-off before the opposite driver will start to conduct.

3.12 Programmable softstart function to drive loads with higher inrush current

Loads with start-up currents higher than the over-current limits (e.g. inrush current of lamps, start current of motors and cold resistance of heaters) can be driven by using the programmable softstart function (i.e. overcurrent recovery mode). Each driver has a corresponding over-current recovery bit. If this bit is set, the device will automatically switchon the outputs again after a programmable recovery time. The duty cycle in over-current condition can be programmed by the SPI interface to be about 12% or 25%. The PWM modulated current will provide sufficient average current to power up the load (e.g. heat up the bulb) until the load reaches operating condition.

The device itself cannot distinguish between a real overload and a non linear load like a light bulb. A real overload condition can only be qualified by time. As an example the microcontroller can switch on light bulbs by setting the over-current Recovery bit for the first

50ms. After clearing the recovery bit the output will be automatically disabled if the overload condition still exits.

Figure 9.

Example of programmable softstart function for inductive loads

Doc ID 14173 Rev 9 21/36

Functional description of the SPI

4 Functional description of the SPI

4.1

Note:

4.2

L9951 / L9951XP

Serial Peripheral Interface (SPI)

This device uses a standard SPI to communicate with a microcontroller. The SPI can be driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0 and

CPHA = 0.

For this mode, input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK.

This device is not limited to microcontroller with a build-in SPI. Only three CMOS-compatible output pins and one input pin will be needed to communicate with the device. A fault condition can be detected by setting CSN to low. If CSN = 0, the DO-pin will reflect the status bit 0 (fault condition) of the device which is a logical-or of all bits in the status registers

0 and 1. The microcontroller can poll the status of the device without the need of a full SPIcommunication cycle.

In contrast to the SPI-standard the least significant bit (LSB) will be transferred first (see

Figure 3 ).

Chip Select Not (CSN)

The input pin is used to select the serial interface of this device. When CSN is high, the output pin (DO) will be in high impedance state. A low signal will activate the output driver and a serial communication can be started.

The state when CSN is going low until the rising edge of CSN will be called a communication frame. If the CSN-input pin is driven above 7.5V, the L9951 will go into a test mode. In the test mode the DO will go from tristate to active mode.

4.3

Note:

Serial Data In (DI)

The input pin is used to transfer data serial into the device. The data applied to the DI will be sampled at the rising edge of the CLK signal and shifted into an internal 16 bit shift register.

At the rising edge of the CSN signal the contents of the shift register will be transferred to

Data Input Register.

The writing to the selected Data Input Register is only enabled if exactly 16 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame will be ignored. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame.

Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended.

22/36 Doc ID 14173 Rev 9

L9951 / L9951XP

4.4

Functional description of the SPI

Serial Data Out (DO)

The data output driver is activated by a logical low level at the CSN input and will go from high impedance to a low or high level depending on the status bit 0 (fault condition). The first rising edge of the CLK input after a high to low transition of the CSN pin will transfer the content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK will shift the next bit out.

4.6

The CLK input is used to synchronize the input and output serial bit streams. The data input

(DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the falling edge of the CLK signal.

Input data register

The device has two input registers. The first bit (bit 0) at the DI-input is used to select one of the two input registers. All bits are first shifted into an input shift register. After the rising edge of CSN the contents of the input shift register will be written to the selected input data register only if a frame of exact 16 data bits are detected. Depending on bit 0 the contents of the selected status register will be transferred to DO during the current communication frame. Bit 1-8 control the behavior of the corresponding driver. The bits 9,10 and 11 are used to control the current monitor multiplexer. Bit 15 is used to reset all status bits in both status registers. The bits in the status registers will be cleared after the current communication frame (rising edge of CSN).

This devices uses two status registers to store and to monitor the state of the device. Bit 0 is used as a fault bit and is a logical-NOR combination of bits 1-14 in both status registers. The state of this bit can be polled by the microcontroller without the need of a full SPI-

communication cycle (see Figure 8.

). If one of the over-current bits is set, the corresponding

driver will be disabled. If the over-current recovery bit of the output is not set the microcontroller has to clear the over-current bit to enable the driver. If the thermal shutdown bit is set, all drivers will go into a high impedance state. Again the microcontroller has to clear the bit to enable the drivers.

The test mode can be entered by rising the CSN input to a voltage higher than 7.5V. In the test mode the inputs CLK, DI, PWM and the internal 2MHz CLK can be multiplexed to data output DO for testing purpose. Furthermore the over-current thresholds are reduced by a factor of 4 to allow EWS testing at lower current. The internal logic prevents that the Hi-Side and Low-Side driver of the same half-bridge can be switched-on at the same time. In the test mode this combination is used to multiplex the desired signals to the CM output according to table 18 and 19.

Doc ID 14173 Rev 9 23/36

Functional description of the SPI L9951 / L9951XP

Table 18.

Test mode

LS1 HS1 LS2 HS2 LS3 HS3 DO LS1 HS1 LS2 HS2 LS3 HS3 CM

! (both HI) ! (both HI) ! (both HI) NoError ! (both HI) ! (both HI) ! (both HI) both HI ! (both HI) ! (both HI) DI both HI ! (both HI) ! (both HI)

N.C

Tsense1

! (both HI) both HI ! (both HI) both HI both HI ! (both HI)

CLK

INT_CLK

! (both HI) ! (both HI) both HI PWM

! (both HI) both HI

! (both HI) both HI both HI

! (both HI)

! (both HI) both HI

Tsense2

Tsense3

Tsense4 both HI ! (both HI)

! (both HI) both HI both HI both HI both HI both HI both HI

N.C

5µA Iref

Vbandgap

Table 19.

SPI - Input data and status register 0

Input register 0 (write) Status register 0 (read)

Bit

Name Comment Name Comment

Reset bit

Disable openload

Overvoltage/ under-voltage recovery disable

If reset bit is set both status registers will be cleared after rising edge of CSN input.

Always 1

If the disable open-load bit is set, the open-load status bits will be ignored for the

NonErrorBit calculation.

S over-voltage

A broken VCC-or SPIconnection of the L9951 can be detected by the microcontroller, because all 16 bits low or high is not a valid frame.

In case of an over-voltage or undervoltage event the corresponding bit is set and the outputs are deactivated.

OC recovery duty cycle

0: 12% 1: 25%

This bit defines in combination with the overcurrent recovery bit (input register 1) the duty cycle in over-current condition of an activated driver. If temperature warning bit is set, L9951 will always use the lower duty cycle

S undervoltage

If VS voltage recovers to normal operating conditions outputs are reactivated automatically.

If this bit is set the microcontroller has to clear the status register after undervoltage/overvoltage event to enable the outputs.

Thermal shutdown

In case of an thermal shutdown all outputs are switched off. The microcontroller has to clear the

TSD bit by setting the reset bit to reactivate the outputs.

24/36 Doc ID 14173 Rev 9

L9951 / L9951XP Functional description of the SPI

Table 19.

SPI - Input data and status register 0 (continued)

Input register 0 (write) Status register 0 (read)

Bit Name

Comment

Following current image

(1/10.000) of the HS driver will be multiplexed to CM output:

Name Comment

Temperature warning

This bit is for information purpose only. It can be used for a thermal management by the microcontroller to avoid a thermal shutdown.

Current monitor select bits

Bit 11 Bit 10 Bit 9 Output

0 0 0 OUT1

OUT2

OUT3

OUT4

OUT5

Not ready bit

After switching the device from standby mode to active mode an internal timer is started to allow charge pump to settle before the outputs can be activated. This bit is cleared automatically after start up time has finished. Since this bit is controlled by internal clock it can be used for synchronizing testing events (e.g. measuring filter times).

OUT5 - HS on/off

OUT4 - HS on/off

OUT3 - HS on/off

OUT3 - LS on/off

OUT2 - HS on/off

OUT2 - LS on/off

OUT1 - HS on/off

OUT1 - LS on/off

No error bit

Not used

OUT5-HS over - current

If a bit is set the selected output driver is switched on.

If the corresponding PWM enable bit is set (Input

OUT1-OUT3 are half bridges. If the bits of HS- and LS-driver of the same half bridge are set, the internal logic prevents that both drivers of this output stage can be switched on simultaneously in order to avoid a high internal current from VS to GND.

OUT4-HS over - current

OUT3-HS over - current

OUT3-LS over - current

OUT2-HS over - current

OUT2-LS over - current

OUT1-HS over - current

OUT1-LS over - current

In case of an over-current event the corresponding status bit is set and the output driver is disabled. If the over-current recovery enable bit is set

(Input Register 1) the output will be automatically reactivated after a delay time resulting in a PWM modulated current with a programmable duty cycle (Bit 13).

If the over-current recovery bit is not set the microcontroller has to clear the over-current bit

(reset bit) to reactivate the output driver.

A logical NOR-combination of all bits 1 to 14 in both status registers. If bit 14 (disable open-load) is set, the openload status will be ignored.

Doc ID 14173 Rev 9 25/36

Functional description of the SPI L9951 / L9951XP

Table 20.

SPI - Input data and status register 1

Input register 1 (write)

Bit Name

Not used

Comment

Status register 1 (read)

Name Comment

Always 1

A broken VCC-or SPIconnection of the L9951 can be detected by the microcontroller, because all

16 bits low or high is not a valid frame.

over-voltage

In case of an over-voltage or undervoltage event the corresponding bit is set and the outputs are deactivated.

undervoltage

In case of an over-voltage or undervoltage event the corresponding bit is set and the outputs are deactivated.

Thermal shutdown

Temperature warning

In case of an thermal shutdown all outputs are switched off. The microcontroller has to clear the TSD bit by setting the reset bit to reactivate the outputs.

This bit is for information purpose only. It can be used for a thermal management by the microcontroller to avoid a thermal shutdown.

26/36 Doc ID 14173 Rev 9

L9951 / L9951XP Functional description of the SPI

Table 20.

SPI - Input data and status register 1 (continued)

Input register 1 (write) Status register 1 (read)

Bit Name

Comment

OUT5 OC recovery enable

OUT4 OC recovery enable

In case of an over-current event the over-current status bit (status register

0) is set and the output is switched off. If the overcurrent recovery enable bit is set the output will be automatically reactivated after a delay time resulting in a PWM modulated current with a programmable duty cycle

(Bit 13 of Input data register 1).

OUT3 OC recovery enable

OUT2 OC recovery enable

OUT1 OC recovery enable

Depending on occurrence of overcurrent event and internal clock phase it is possible that one recovery cycle is executed even if this bit is set to zero.

OUT5 PWM enable

OUT4 PWM enable

OUT3 PWM enable

OUT2 PWM enable

OUT1 PWM enable

If the PWM enable bit is set and the output is enabled (input register 0) the output is switched on if

PWM input is high and switched off if PWM input is low.

Name

Not ready bit

Comment

Since this bit is controlled by internal clock it can be used for synchronizing testing events(e.g. measuring filter times).

OUT5-HS open-load

OUT4-HS open-load

OUT3-HS open-load

OUT3-LS open-load

OUT2-HS open-load

OUT2-LS open-load

OUT1-HS open-load

OUT1-LS open-load

Not used.

The open-load detection monitors the load current in each activated output stage. If the load current is below the open-load detection threshold for at least 1 ms (t dOL

) the corresponding open-load bit is set. Due to mechanical

/electrical inertia of typical loads a short activation of the outputs (e.g. 3ms) can be used to test the open-load status without changing the mechanical/electrical state of the loads.

0 1 No error bit

A logical NOR-combination of all bits 1 to 14 in both status registers. If bit 14 (Disable

Open-Load) is set, the openload status will be ignored

Doc ID 14173 Rev 9 27/36

Packages thermal data

5 Packages thermal data

Figure 10.

Packages thermal data

L9951 / L9951XP

28/36 Doc ID 14173 Rev 9

L9951 / L9951XP

6

Package and packing information

Package and packing information

6.1 ECOPACK

®

packages

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

ECOPACK

is an ST trademark.

6.2 PowerSO-36™ package information

Figure 11.

PowerSO-36™ package dimensions

Table 21.

PowerSO-36™ mechanical data

Symbol

Min.

A a1 a2 a3 b c

0.10

0.22

0.23

Millimeters

Typ.

Doc ID 14173 Rev 9

Max.

3.60

0.30

3.30

0.10

0.38

0.32

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Package and packing information

Table 21.

PowerSO-36™ mechanical data (continued)

Millimeters

Symbol

Min.

Typ.

R s

E3 e e3

D *

E1 *

15.80

9.40

13.90

10.90

5.80

15.50

0.8

0.65

11.05

L9951 / L9951XP

0.10

15.90

1.10

10 deg

8 deg

Max.

16.00

9.80

14.5

11.10

2.90

6.20

30/36 Doc ID 14173 Rev 9

L9951 / L9951XP

Figure 12.

PowerSSO-36™ package dimensions

Package and packing information

H h k e e3

N b c

D *

E *

A2 a1

Table 22.

PowerSSO-36™ mechanical data

Symbol

Min.

2.15

0.18

0.23

10.10

7.4

10.1

0°

0.55

Millimeters

Typ.

0.5

8.5

2.3

Doc ID 14173 Rev 9

Max.

2.45

2.35

0.1

0.36

0.32

10.50

7.6

0.1

0.06

10.5

0.4

8°

0.85

10 deg

31/36

Package and packing information

Table 22.

PowerSSO-36™ mechanical data (continued)

Millimeters

Symbol

Min.

Typ.

4.3

6.9

6.4 PowerSO-36™ packing information

Figure 13.

PowerSO-36 TM tube shipment (no suffix)

L9951 / L9951XP

Max.

5.2

7.5

32/36 Doc ID 14173 Rev 9

L9951 / L9951XP Package and packing information

Figure 14.

PowerSO-36 TM tape and reel shipment (suffix “TR”)

TAPE DIMENSIONS

15.20 ± 0.1

16.60 ± 0.1

3.90 ± 0.1

3.50 ± 0.1

11.50 ± 0.1

24.00 ± 0.1

24.00 ± 0.3

All dimensions are in mm.

REEL DIMENSIONS

Base Qty

Bulk Qty

A (max)

B (min)

C (±0.2)

D (min)

G (+2 / -0)

N (min)

T (max)

600

330

1.5

20.2

24.4

30.4

Doc ID 14173 Rev 9 33/36

Package and packing information L9951 / L9951XP

Figure 15.

PowerSSO-36 TM tube shipment (no suffix)

Base Qty

Bulk Qty

Tube length (±0.5)

C (±0.1)

All dimensions are in mm.

1225

532

3.5

13.8

0.6

Figure 16.

PowerSSO-36 TM tape and reel shipment (suffix “TR”)

REEL DIMENSIONS

Base Qty

Bulk Qty

A (max)

B (min)

C (±0.2)

G (+2 / -0)

N (min)

T (max)

1000

330

1.5

20.2

24.4

100

30.4

TAPE DIMENSIONS

According to Electronic Industries Association

(EIA) Standard 481 rev. A, Feb. 1986

Tape width

Tape Hole Spacing

Component Spacing

Hole Diameter

Hole Position

Compartment Depth

Hole Spacing

P0 (±0.1)

D1 (min)

F (±0.1)

K (max)

P1 (±0.1)

P 12

D (±0.05) 1.55

1.5

11.5

2.85

All dimensions are in mm.

End

Top cover tape

No components Components

500mm min 500mm min

Empty components pockets sealed with cover tape.

Start

No components

User direction of feed

34/36 Doc ID 14173 Rev 9

L9951 / L9951XP Revision history

Table 23.

Document revision history

Date Revision

Mar-2004

Jun-2005

Jul-2005

Sep-2005

Feb-2006

15-Nov-2007

24-Jun-2009

14-May-2010

22-Sep-2013

Description of changes

First issue

Added

PowerSO-36™ package information , PowerSO-36™ package information .

Updated

Figure 1.: Block diagram

Note 1 removal;

Updated

Figure 10.: Packages thermal data .

Updated

Table 4.: ESD protection .

Document restructured and reformatted.

Added

PowerSO-36™ packing information

and PowerSSO-36™ packing information

Table 22: PowerSSO-36™ mechanical data

– Deleted A (min) value

– Changed A (max) value from 2.47 to 2.45

– Changed A2 (max) value from 2.40 to 2.35

– Changed a1 (max) value from 0.075 to 0.1

– Added F and k rows

Table 22: PowerSSO-36™ mechanical data

– Changed X: minimum value from 4.1 to 4.3 and maximum value from 4.7 to 5.2

– Changed Y: minimum value from 6.5 to 6.9 and maximum value from 7.1 to 7.5

Updated Disclaimer.

Doc ID 14173 Rev 9 35/36

L9951 / L9951XP

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36/36 Doc ID 14173 Rev 9