STMicroelectronics L5983 Datasheet
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L5983
1.5 A step-down switching regulator
VFQFPN8 3 x 3 mm
Datasheet
-
production data
Industrial: chargers, PLD, PLA, FPGA
Networking: XDSL, modems, DC-DC modules
Computer: optical storage, hard disk drive, printers, audio/graphic cards
LED driving
Features
Description
1.5 A DC output current
2.9 V to 18 V input voltage
Output voltage adjustable from 0.6 V
250 kHz switching frequency, programmable up to 1 MHz
Internal soft-start and inhibit
Low dropout operation: 100% duty cycle
Voltage feedforward
Zero load current operation
Overcurrent and thermal protection
VFQFPN8 3 x 3 mm package
The L5983 is a step-down switching regulator with a 2.0 A (min.) current limited embedded
Power MOSFET, so it is able to deliver an output current in excess of 1.5 A DC to the load.
The input voltage can range from 2.9 V to 18 V, while the output voltage can be set starting from
0.6 V to V
IN
. Having a minimum input voltage of
2.9 V, the device is suitable also for a 3.3 V bus.
Requiring a minimum set of external components, the device includes an internal 250 kHz switching frequency oscillator that can be externally adjusted up to 1 MHz.
The VFQFPN package with an exposed pad allows reducing the R thJA
down to approximately
60 °C/W.
Applications
Consumer: STB, DVD, DVD recorder, car audio, LCD TV and monitors
Figure 1. Application circuit
May 2014
This is information on a product in full production.
DocID13005 Rev 8 1/41
www.st.com
Contents
Contents
L5983
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/41 DocID13005 Rev 8
L5983
Contents
DocID13005 Rev 8 3/41
41
Pin settings
Figure 2. Pin connection (top view)
L5983
4/41
3
4
5
6
7
8
No.
1
2
Type
OUT
SYNCH
INH
COMP
FB
F
SW
GND
V
CC
Table 1. Pin description
Description
Regulator output
Master/slave synchronization. When it is left floating, a signal with a phase shift of half a period with respect to the power turn-on is present at the pin. When connected to an external signal at a frequency higher than the internal one, then the device is synchronized by the external signal, with zero phase shift.
Connecting together the SYNCH pin of two devices, the one with the higher frequency works as a master and the other as a slave; so the turnon of the two power switches has a phase shift of half a period.
A logical signal (active high) disables the device. With INH higher than
1.9 V the device is OFF and with INH lower than 0.6 V the device is ON.
Error amplifier output to be used for loop frequency compensation
Feedback input. Connecting the output voltage directly to this pin the output voltage is regulated at 0.6 V. To have higher regulated voltages an external resistor divider is required from the Vout to the FB pin.
The switching frequency can be increased connecting an external resistor from the FSW pin and ground. If this pin is left floating the device works at its free running frequency of 250 kHz.
Ground
Unregulated DC input voltage
DocID13005 Rev 8
L5983 Maximum ratings
2.1 Absolute maximum ratings
Symbol
Table 2. Absolute maximum ratings
Parameter
V
CC
OUT
Input voltage
Output DC voltage
F
SW
, COMP, SYNCH Analog pin
INH Inhibit pin
FB
P
TOT
T
J
T stg
Feedback voltage
Power dissipation at T
A
< 60 °C
Junction temperature range
Storage temperature range
Value
20
-0.3 to V
CC
-0.3 to 4
-0.3 to V
CC
-0.3 to 1.5
1.5
-40 to 150
-55 to 150
Unit
V
W
°C
°C
Symbol
Table 3. Thermal data
Parameter
R thJA
Maximum thermal resistance junction ambient
(1)
VFQFPN
1. Package mounted on demonstration board.
Value
60
Unit
°C/W
DocID13005 Rev 8 5/41
41
Electrical characteristics L5983
Symbol
T
J
= 25 °C, V
CC
= 12 V, unless otherwise specified.
Table 4. Electrical characteristics
Parameter Test condition
V
CC
V
CCON
V
CCHYS
Operating input voltage range
Turn-on V
CC
threshold
V
CC
UVLO hysteresis
R
DS(on)
MOSFET on resistance
I
LIM
Oscillator
Maximum limiting current
(1)
(1)
(1)
(1)
F
SW
Switching frequency
V
FSW
D
FSW pin voltage
Duty cycle
F
ADJ
Adjustable switching frequency
Dynamic characteristics
V
FB
Feedback voltage
I
I
Q
QST-BY
Inhibit
DC characteristics
Quiescent current
Total standby quiescent current
INH threshold voltage
INH current
Soft-start
T
SS
Soft-start duration
Error amplifier
V
CH
V
CL
I
FB
High level output voltage
Low level output voltage
Bias source current
(1)
R
FSW
= 33 k
2.9 V < V
CC
< 18 V
(1)
Duty cycle = 0, V
FB
= 0.8 V
Device ON level
Device OFF level
INH = 0
FSW pin floating
F
SW
= 1 MHz, R
FSW
= 33 k
V
FB
< 0.6 V
V
FB
> 0.6 V
V
FB
= 0 V to 0.8 V
Min.
2.9
0.175
2.0
Values
Typ.
Max.
140
140
2.3
18
2.9
0.3
170
220
2.6
Unit
V m
A
225
220
0
0.593
0.6
0.607
1.9
7.4
3
250
1.254
1000
20
7.5
8.2
2
1
275
275
100
2.4
30
0.6
10
9.1
0.1
V mA
A
V
A ms
V
A kHz
V
% kHz
6/41 DocID13005 Rev 8
L5983 Electrical characteristics
Table 4. Electrical characteristics (continued)
Values
Symbol Parameter Test condition Unit
I
O SOURCE
I
O SINK
G
V
Source COMP pin
Sink COMP pin
Open loop voltage gain
Synchronization function
High input voltage
Low input voltage
Slave sink current
Master output amplitude
Output pulse width
Input pulse width
Protection
V
FB
= 0.5 V, V
COMP
= 1 V
V
FB
= 0.7 V, V
COMP
= 1 V
(2)
V
SYNCH
= 2.9 V
I
SOURCE
= 4.5 mA
SYNCH floating
Min.
2
2.0
70
Typ.
Max.
20
25
100
0.7
110
3.3
1
0.9
mA mA dB
V mA
V ns
I
FBDISC
T
SHDN
(2)
FB disconnection source current
Thermal shutdown
Hysteresis
1
150
30
1. Specification referred to T
J
from -40 to +125 °C. Specifications in the -40 to +125 °C temperature range are assured by design, characterization and statistical correlation.
2. Guaranteed by design.
A
°C
DocID13005 Rev 8 7/41
41
Functional description L5983
The L5983 device is based on a “voltage mode”, constant frequency control. The output voltage V
OUT
is sensed by the feedback pin (FB) compared to an internal reference (0.6 V) providing an error signal that, compared to a fixed frequency sawtooth, controls the ON and
OFF time of the power switch.
The main internal blocks are shown in the block diagram in
. They are:
A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the synchronization signal. Its switching frequency can be adjusted by an external resistor.
The voltage and frequency feedforward are implemented.
The soft-start circuitry to limit inrush current during the startup phase
The voltage mode error amplifier
The pulse width modulator and the relative logic circuitry necessary to drive the internal power switch
The high-side driver for embedded P-channel Power MOSFET switch
The peak current limit sensing block, to handle overload and short-circuit conditions
A voltage regulator and internal reference. It supplies internal circuitry and provides a fixed internal reference.
A voltage monitor circuitry (UVLO) that checks the input and internal voltages.
A thermal shutdown block, to prevent thermal runaway.
Figure 3. Block diagram
8/41 DocID13005 Rev 8
L5983 Functional description
4.1 Oscillator synchronization
shows the block diagram of the oscillator circuit. The internal oscillator provides
a constant frequency clock. Its frequency depends on the resistor externally connected to the FSW pin. In case the FSW pin is left floating the frequency is 250 kHz; it can be
by the external resistor connected to ground.
To improve the line transient performance, keeping the PWM gain constant versus the input voltage, the voltage feedforward is implemented by changing the slope of the sawtooth
according to the input voltage change (see
.a).
The slope of the sawtooth also changes if the oscillator frequency is increased by the external resistor. In this way a frequency feedforward is implemented (
keep the PWM gain constant versus the switching frequency (see
for PWM gain expression).
The synchronization signal is generated on the SYNCH pin. This signal has a phase shift of
180° with respect to the clock. This delay is useful when two devices are synchronized connecting the SYNCH pins together. When SYNCH pins are connected, the device with a higher oscillator frequency works as a master, so the slave device switches at the frequency of the master but with a delay of half a period. This minimizes the RMS current flowing through the input capacitor (see the L5988D datasheet: “4 A continuous (more than
5 A pulsed) step-down switching regulator with synchronous rectification”).
Figure 4. Oscillator circuit block diagram
The device can be synchronized to work at a higher frequency feeding an external clock signal. The synchronization changes the sawtooth amplitude, changing the PWM gain
(
.c). This change has to be taken into account when the loop stability is studied. To
minimize the change of the PWM gain, the free running frequency should be set (with a resistor on the FSW pin) only slightly lower than the external clock frequency. This preadjusting of the frequency changes the sawtooth slope in order to render the truncation of sawtooth negligible, due to the external synchronization.
DocID13005 Rev 8 9/41
41
Functional description L5983
Figure 5. Sawtooth: voltage and frequency feedforward; external synchronization
Figure 6. Oscillator frequency vs. FSW pin resistor
10/41 DocID13005 Rev 8
L5983 Functional description
4.2 Soft-start
The soft-start is essential to assure a correct and safe startup of the step-down converter. It avoids inrush current surge and makes the output voltage increase monotonically.
The soft-start is performed by a staircase ramp on the non-inverting input (V
REF amplifier. So the output voltage slew rate is:
) of the error
Equation 1
SR
OUT
= SR
VREF
1 +
R1
R2
where SR
VREF
is the slew rate of the non-inverting input, while R1 and R2 is the resistor divider to regulate the output voltage (see
). The soft-start staircase consists of
64 steps of 9.5 mV each, from 0 V to 0.6 V. The time base of one step is of 32 clock cycles.
So the soft-start time and then the output voltage slew rate depend on the switching frequency.
Figure 7. Soft-start scheme
Soft-start time results:
Equation 2
SS
TIME
=
Fsw
For example, with a switching frequency of 250 kHz the SS
TIME
is 8 ms.
DocID13005 Rev 8 11/41
41
Functional description
4.3 Error amplifier and compensation
L5983
The error amplifier (E/A) provides the error signal to be compared with the sawtooth to perform the pulse width modulation. Its non-inverting input is internally connected to a 0.6 V voltage reference, while its inverting input (FB) and output (COMP) are externally available for feedback and frequency compensation. In this device the error amplifier is a voltage mode operational amplifier so with high DC gain and low output impedance.
The uncompensated error amplifier characteristics are the following:
Table 5. Uncompensated error amplifier characteristics
Error amplifier Value
Low frequency gain
GBWP
Slew rate
Output voltage swing
Maximum source/sink current
100 dB
4.5 MHz
7 V/
s
0 to 3.3 V
25 mA/40 mA
In continuous conduction mode (CCM), the transfer function of the power section has two poles due to the LC filter and one zero due to the ESR of the output capacitor. Different kinds of compensation networks can be used depending on the ESR value of the output capacitor. In case the zero introduced by the output capacitor helps to compensate the double pole of the LC filter a type II compensation network can be used. Otherwise, a type III compensation network has to be used (see
the compensation network selection).
However, the methodology to compensate the loop is to introduce zeros to obtain a safe phase margin.
12/41 DocID13005 Rev 8
L5983 Functional description
The L5983 device implements the overcurrent protection sensing current flowing through the Power MOSFET. Due to the noise created by the switching activity of the Power
MOSFET, the current sensing is disabled during the initial phase of the conduction time.
This avoids an erroneous detection of a fault condition. This interval is generally known as
“masking time” or “blanking time”. The masking time is about 200 ns.
When the overcurrent is detected, two different behaviors are possible depending on the operating condition.
1.
Output voltage in regulation. When the overcurrent is sensed, the Power MOSFET is switched off and the internal reference (V
REF
), that biases the non-inverting input of the error amplifier, is set to zero and kept in this condition for a soft-start time (T
SS
, 2048 clock cycles). After this time, a new soft-start phase takes place and the internal
.a).
2. Soft-start phase. If the overcurrent limit is reached, the Power MOSFET is turned off implementing the pulse by pulse overcurrent protection. During the soft-start phase, under the overcurrent condition, the device can skip pulses in order to keep the output current constant and equal to the current limit. If, at the end of the “masking time”, the current is higher than the overcurrent threshold, the Power MOSFET is turned off and it skips one pulse. If, at the next switching on at the end of the “masking time”, the current is still higher than the threshold, the device skips two pulses. This mechanism is repeated and the device can skip up to seven pulses. While, if at the end of the
“masking time” the current is lower than the overcurrent threshold, the number of skipped cycles is decreased by one unit. At the end of the soft-start phase the output voltage is in regulation and if the overcurrent persists, the behavior explained above takes place (see
So the overcurrent protection can be summarized as a “hiccup” intervention when the output is in regulation and a constant current during the soft-start phase.
If the output is shorted to ground when the output voltage is in regulation, the overcurrent is triggered and the device starts cycling with a period of 2048 clock cycles between the
“hiccup” (Power MOSFET off and no current to the load) and “constant current” with very short ON time and with reduced switching frequency (up to one eighth of normal switching frequency). See
for short-circuit behavior.
DocID13005 Rev 8 13/41
41
Functional description
Figure 8. Overcurrent protection strategy
L5983
14/41
The inhibit feature allows the device to be put into standby mode. With the INH pin higher than 1.9 V, the device is disabled and the power consumption is reduced to less than 30
A.
With the INH pin lower than 0.6 V, the device is enabled. If the INH pin is left floating, an internal pull-up ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also V
CC
compatible.
The thermal shutdown block generates a signal that turns off the power stage if the junction temperature goes above 150 °C. Once the junction temperature goes back to about 130 °C, the device restarts in normal operation. The sensing element is very close to the PDMOS area, therefore ensuring an accurate and fast temperature detection.
DocID13005 Rev 8
L5983 Application information
5.1 Input capacitor selection
The capacitor connected to the input must be able to support the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR, affecting the overall system efficiency.
So the input capacitor must have an RMS current rating higher than the maximum RMS input current and an ESR value compliant with the expected efficiency.
The maximum RMS input current flowing through the capacitor can be calculated as:
Equation 3
I
RMS
= I
O
D –
2
--------------+
D
2
-------
2 where I
O
is the maximum DC output current, D is the duty cycle,
is the efficiency.
Considering
this function has a maximum at D = 0.5 and it is equal to I
O
/2.
In a specific application the range of possible duty cycles must be considered in order to find out the maximum RMS input current. The maximum and minimum duty cycles can be calculated as:
Equation 4
D
MAX
=
V
V
INMIN
+
–
V
V
F
SW and
Equation 5
D
MIN
=
V
V
INMAX
+
–
V
V
SW where V
F
is the forward voltage on the freewheeling diode and V
SW
is voltage drop across the internal PDMOS.
In
some multi-layer ceramic capacitors suitable for this device are reported.
Manufacturer
MURATA
TDK
Table 6. Input capacitors
Series Cap value (
F)
GRM31
GRM55
C3225
10
10
10
Rated voltage (V)
25
25
25
DocID13005 Rev 8 15/41
41
Application information L5983
16/41
The inductance value fixes the current ripple flowing through the output capacitor. So the minimum inductance value, in order to have the expected current ripple, must be selected.
The rule to fix the current ripple value is to have a ripple at 20% - 40% of the output current.
The inductance value can be calculated by the following equation:
Equation 6
I
L
=
V
IN
–
L
V
OUT
ON
=
V
L
OFF where T
ON
fixed V
OUT
is the conduction time of the internal high-side switch and T
OFF
time of the external diode [in CCM, F
SW
= 1 / (T
ON
, is obtained at maximum T
OFF calculate minimum duty). So fixing
I
L
+ T
OFF
is the conduction
)]. The maximum current ripple, at
that is at minimum duty cycle (see
minimum inductance value can be calculated as:
to
= 20% to 40% of the maximum output current, the
Equation 7
L
MIN
=
V
OUT
I
+
MAX
V
----------------------------
1 D
F
MIN
SW where F
SW
is the switching frequency, 1 / (T
ON
+ T
OFF
).
For example, for V
OUT
= 3.3 V, V
IN inductance value to have
I
L
= 12 V, I
O
= 30% of I
O
= 1.5 A and F
is about 21
H.
SW
= 250 kHz, the minimum
The peak current through the inductor is given by:
Equation 8
I
So if the inductor value decreases, the peak current (which must be lower than the current limit of the device) increases. The higher the inductor value, the higher the average output current that can be delivered, without reaching the current limit.
In
some inductor part numbers are listed.
= I
O
+
I
L
Manufacturer
Wurth
Coilcraft
Coiltronics
BI
SUMIDA
Table 7. Inductors
Series Inductor value (
H)
Saturation current (A)
PD
MSS1038
MSS7341
CD1
UP2.8B
HM76-3
CDRH8D28
CDRH8D28/HP
3.3 to 6.8
15 to 18
3.3 to 6.2
15 to 22
4.7 to 10
15 to 33
4.7 to 10
15 to 22
2.75 to 4.2
3.2 to 3.6
2.5 to 3.5
2.9 to 3.6
2.7 to 3.9
2.5 to 3.7
2.5 to 3.4
2.5 to 2.8
DocID13005 Rev 8
L5983
5.3
Application information
Output capacitor selection
The current in the capacitor has a triangular waveform which generates a voltage ripple across it. This ripple is due to the capacitive component (charge and discharge of the output capacitor) and the resistive component (due to the voltage drop across its ESR). So the output capacitor must be selected in order to have a voltage ripple compliant with the application requirements.
The amount of the voltage ripple can be calculated starting from the current ripple obtained by the inductor selection.
Equation 9
V
OUT
= ESR
I
MAX
+
I
MAX
OUT
f
SW
Usually the resistive component of the ripple is much higher than the capacitive one, if the output capacitor adopted is not a multi-layer ceramic capacitor (MLCC) with very low ESR value.
The output capacitor is important also for loop stability: it fixes the double LC filter pole and the zero due to its ESR. In
, how to consider its effect in the system stability is
illustrated.
For example, with V order to have a
V
OUT
= 3.3 V, V
IN
OUT
= 0.01·V
OUT
= 12 V,
I
L
= 0.5 A (resulting from the inductor value), in
, if the multi-layer ceramic capacitor is adopted, 10
F is needed and the ESR effect on the output voltage ripple can be neglected. In case of not negligible ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into account its ESR value.
So in case of 100
F with ESR = 40 m, the resistive component of the drop dominates and the voltage ripple is 20 mV.
The output capacitor is also important to sustain the output voltage when a load transient with high slew rate is required by the load. When the load transient slew rate exceeds the system bandwidth, the output capacitor provides the current to the load. So if the high slew rate load transient is required by the application, the output capacitor and system bandwidth must be chosen in order to sustain the load transient.
In
some capacitor series are listed.
Manufacturer
MURATA
PANASONIC
SANYO
TDK
Series
GRM32
GRM31
ECJ
EEFCD
TPA/B/C
C3225
Table 8. Output capacitors
Cap value (
F)
Rated voltage (V)
22 to 100
10 to 47
10 to 22
10 to 68
100 to 470
22 to 100
6.3 to 25
6.3 to 25
6.3
6.3
4 to 16
6.3
ESR (m
)
< 5
< 5
< 5
15 to 55
40 to 80
< 5
DocID13005 Rev 8 17/41
41
Application information L5983
The compensation network has to assure stability and good dynamic performance. The loop of the L5983 device is based on the voltage mode control. The error amplifier is a voltage operational amplifier with high bandwidth. So, by selecting the compensation network the
E/A is considered as ideal, that is, its bandwidth is much larger than that of the system.
The transfer functions of the PWM modulator and the output LC filter are studied (see
). The transfer function of the PWM modulator, from the error amplifier output
(COMP pin) to the OUT pin, results:
Equation 10
G
PW0
=
V
V s where V
S
is the sawtooth amplitude. As seen in
, the voltage feedforward generates a sawtooth amplitude directly proportional to the input voltage, that is:
Equation 11
V
S
=
IN
In this way the PWM modulator gain results constant and equal to:
Equation 12
G
PW0
=
V
V s
=
1
K
= 9
The synchronization of the device with an external clock provided trough the SYNCH pin can modify the PWM modulator gain (see
to understand how this gain changes
and how to keep it constant in spite of the external synchronization).
The transfer function on the LC filter is given by:
Equation 13
G
LC
=
1 +
2
f
1 +
s
2
Q f
LC
+
2 s
f
LC
2 where:
Equation 14
f
LC
=
2
L C
OUT
1 +
R
OUT
f zESR
=
2
1
OUT
18/41 DocID13005 Rev 8
L5983 Application information
Equation 15
Q =
R
OUT
+
OUT
OUT
R
R
OUT
OUT
+
E SR
ESR
, R
OUT
=
V
OUT
OUT
, two different kinds of network can compensate the loop.
In the two following paragraphs the guidelines to select the type II and type III compensation network are illustrated.
Figure 9. Error amplifier, PWM modulator and LC output filter
5.4.1 Type III compensation network
The methodology to stabilize the loop consists of placing two zeros to compensate the effect of the LC double pole, therefore increasing phase margin; then to place one pole in the origin to minimize the DC error on regulated output voltage; finally to place other poles far from the zero dB frequency.
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a frequency higher than the desired bandwidth (that is: 2
* ESR * C
OUT
< 1 /BW), the type III compensation network is needed. Multi-layer ceramic capacitors (MLCC) have very low ESR (< 1 m
), with very high frequency zero, so a type III network is adopted to compensate the loop.
the type III compensation network is shown. This network introduces two zeros
(f
Z1
, f
Z2
) and three poles (f
P0
, f
P1
, f
P2
). They are expressed as:
Equation 16
f
Z1
=
2
3
1
R
1
R
3
f
Z2
=
4
4
Equation 17
f
P0
= 0
f
P1
=
2
1
R
3
C
3
f
P2
=
2
R
4
C
C
4
4
+
C
5
C
5
DocID13005 Rev 8 19/41
41
Application information
Figure 10. Type III compensation network
L5983
In
the Bode diagram of the PWM and LC filter transfer function [G
PW0 and the open loop gain [G
LOOP
(f) = G
PW0
· G
LC
(f) · G
TYPEIII
(f)] is given.
· G
LC
(f)]
Figure 11. Open loop gain: module Bode diagram
20/41
The guidelines for positioning the poles and the zeros and for calculating the component values can be summarized as follows:
1.
Choose a value for R
1
, usually between 1 k
and 5 k.
2. Choose a gain (R
4
/R
1
) in order to have the required bandwidth (BW), that means:
Equation 18
R
4
= f
LC
1 where K is the feedforward constant and 1 / K is equal to 9.
DocID13005 Rev 8
L5983 Application information
4
by placing the zero at 50% of the output filter double pole frequency (f
LC
):
Equation 19
C
4
=
R
1
4
LC
5
by placing the second pole at four times the system bandwidth (BW):
Equation 20
C
5
=
C
--------------------------------------------------------------
4 4
–
1
5. Set the first pole also at four times the system bandwidth and also the second zero at the output filter double pole:
Equation 21
R
3
=
R
---------------------------
f
LC
C
3
=
3
1
4 BW
The suggested maximum system bandwidth is equal to the switching frequency divided by
3.5 (F
SW
/ 3.5), but lower than 100 kHz if the F
SW
is set higher than 500 kHz.
For example, with V
OUT
= 3.3 V, V
IN
= 12 V, I
O
= 1.5 A, L = 22
ESR < 1 m
, the type III compensation network is:
H, C
OUT
= 22
F,
R
1
= 4.99k
R
2
= 1.1k
R
3
= 120
R
4
= 4.99k
C
3
= 4.7nF
C
4
= 10nF
C
5
= 68pF
DocID13005 Rev 8 21/41
41
Application information L5983
In
the module and phase of the open loop gain is shown. The bandwidth is about
77 kHz and the phase margin is 47°.
Figure 12. Open loop gain Bode diagram with ceramic output capacitor
22/41 DocID13005 Rev 8
L5983 Application information
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a frequency lower than the desired bandwidth (that is: 2
* ESR * C
OUT
> 1 / BW), this zero helps stabilize the loop. Electrolytic capacitors show not negligible ESR (> 30 m
), so with this kind of the output capacitor the type II network combined with the zero of the ESR allows the loop to be stabilized.
In
Figure 13. Type II compensation network
The singularities of the network are:
Equation 22
f
Z1
=
2
1
R
4
C
4
f
P0
=
0
f
P1
=
2
R
4
C
C
4
+
C
C
5
DocID13005 Rev 8 23/41
41
Application information L5983
In
the Bode diagram of the PWM and LC filter transfer function [G
PW0 and the open loop gain [G
LOOP
(f) = G
PW0
· G
LC
(f) · G
TYPEII
(f)] is given.
· G
LC
(f)]
Figure 14. Open loop gain: module Bode diagram
24/41
The guidelines for positioning the poles and the zeros and for calculating the component values can be summarized as follows:
1.
Choose a value for R
1
, usually between 1 k
and 5 k, in order to have values of C4 and C5 not comparable with parasitic capacitance of the board.
2. Choose a gain (R
4
/R
1
) in order to have the required bandwidth (BW), that means:
Equation 23
R
4
=
f
------------
LC
2
f
ESR
V
S
V
IN
1 where f
ESR
is the ESR zero:
Equation 24
f
ESR
=
2
1
OUT and V
S
is the sawtooth amplitude. The voltage feedforward keeps the ratio V
S
/V
IN
constant.
4
by placing the zero one decade below the output filter double pole:
Equation 25
C
4
=
4
LC
DocID13005 Rev 8
L5983 Application information
3
in order to place the second pole at four times the system bandwidth
(BW):
Equation 26
C
5
=
2
R
4
C
C
4
4
–
For example, with V
OUT
= 3.3 V, V
IN
= 12 V, I
O m
the type II compensation network is:
= 1.5 A, L = 22
H, C
OUT
= 330
F, ESR = 50
R
1
=
1.1k
R
2
=
249
R
4
=
10k
C
4
=
6.8nF
C
5
=
68pF
DocID13005 Rev 8 25/41
41
Application information L5983
In
the module and phase of the open loop gain is shown. The bandwidth is about
30 kHz and the phase margin is 45°.
Figure 15. Open loop gain Bode diagram with electrolytic/tantalum output capacitor
26/41 DocID13005 Rev 8
L5983 Application information
The thermal design is important to prevent the thermal shutdown of the device if junction temperature goes above 150 °C. The three different sources of losses within the device are: a) Conduction losses due to the not negligible R
DS(on) equal to:
of the power switch; these are
Equation 27
P
ON
=
R
DS on
I
OUT
2
D where D is the duty cycle of the application and the maximum R
DS(on)
is 220 m
.
Note that the duty cycle is theoretically given by the ratio between V
OUT
and V
IN
, but actually it is quite higher to compensate the losses of the regulator. So the conduction losses increase compared with the ideal case.
b) Switching losses due to Power MOSFET turn-on and -off; these can be calculated as:
Equation 28
P
SW
= V
IN
I
OUT
T
+
2
T
FALL
= V
IN
I
OUT
T
SW
F
SW where T
RISE
and T
FALL
are the overlap times of the voltage across the power switch (V
DS and the current flowing into it during turn-on and turn-off phases, as shown in
.
)
T
SW
is the equivalent switching time.
For this device the typical value for the equivalent switching time is 50 ns.
Equation 29
P
Q
= V
IN
I
Q where I
Q
is the quiescent current. (I
Q
= 2.4 mA).
The junction temperature T
J
can be calculated as:
Equation 30
T
J
= T
A
+ Rth
JA
P
TOT where T
A
is the ambient temperature and P
TOT
is the sum of the power losses just seen.
Rth
JA
is the equivalent thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient.
For this device the path through the exposed pad is the one conducting the largest amount of heat. The Rth
JA
, measured on the demonstration board described in
Section 5.6: Layout considerations
DocID13005 Rev 8 27/41
41
Application information
Figure 16. Switching losses
L5983
28/41
The PC board layout of the switching DC/DC regulator is very important to minimize the noise injected in high impedance nodes and interferences generated by the high switching current loops.
In a step-down converter the input loop (including the input capacitor, the Power MOSFET and the freewheeling diode) is the most critical one. This is due to the fact that the high value pulsed current is flowing through it. In order to minimize the EMI, this loop must be as short as possible.
To filter the high frequency noise, a small capacitor can be added as close as possible to the input voltage pin of the device.
The feedback pin (FB) connection to the external resistor divider is a high impedance node, so the interferences can be minimized placing the routing of the feedback node as far as possible from the high current paths. To reduce the pick up noise the resistor divider has to be placed very close to the device.
Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal resistance junction to ambient; so a large ground plane enhances the thermal performance of the converter allowing high power conversion.
DocID13005 Rev 8
L5983
In
Figure 17. Layout example
Application information
DocID13005 Rev 8 29/41
41
Application information
In
the demonstration board application circuit is shown.
Figure 18. Demonstration board application circuit
L5983
30/41
Reference
C5
C6
R1
R2
C1
C2
C3
C4
R3
R4
R5
L1
D1
Table 9. Component list
Part number Description
GRM31CR61E106KA12
GRM31CR61C226KE15B
7447779006
STPS2L25V
10
F, 25 V
22
F, 16 V
2.2 nF, 50 V
10 nF, 50 V
220 pF, 50 V
68 nF, 25 V
4.99 k
, 1%, 0.1 W 0603
1.1 k
, 1%, 0.1 W 0603
330
, 1%, 0.1 W 0603
2.99 k
, 1%, 0.1 W 0603
100 k
, 1%, 0.1 W 0603
6.8
H, 30%, 2.91 A
2 A, 25 V
Manufacturer
MURATA
MURATA
Coilcraft
STMicroelectronics
DocID13005 Rev 8
L5983 Application information
Figure 19. PCB layout (component side)
Figure 20. PCB layout (bottom side)
Figure 21. PCB layout (front side)
DocID13005 Rev 8 31/41
41
Application information L5983
Figure 22. Junction temperature vs. output current - V
CC
= 5 V
Figure 23. Junction temperature vs. output current - V
CC
= 12 V
Figure 24. Junction temperature vs. output current - V
CC
= 18 V
Figure 25. Efficiency vs. output current
- V
CC
= 12 V
95
90
85
80
75
70
0.0
0.2
0.4
VCC=12V,
F
SW
=250kHz
0.6
0.8
Io [A]
1.0
Vo=5V
Vo=3.3V
Vo=2.5V
1.2
1.4
1.6
1.8
Figure 26. Efficiency vs. output current
- V
CC
= 5 V
94
92
90
88
86
84
82
80
78
76
0 0.2
0.4
VCC=5V,
F
SW
=250kHz
0.6
0.8
Io [A]
1 1.2
Vo=3.3V
Vo=2.5V
Vo=1.8V
1.4
1.6
1.8
95
Figure 27. Efficiency vs. output current
- V
CC
= 3.3 V
Vo=2.5V
90
85
Vo=1.8V
80
75
70
0
Vo=1.2V
0.2
0.4
VCC=3.3V,
F
SW
=250kHz
0.6
0.8
Io [A]
1 1.2
1.4
1.6
1.8
32/41 DocID13005 Rev 8
L5983
Figure 28. Load regulation
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
0.2
0.4
0.6
0.8
I
O
[A]
1
V
CC
=5V
V
CC
=12V
V
CC
=18V
1.2
1.4
Figure 30. Load transient: from 300 mA to 1.3 A
Application information
Figure 29. Line regulation
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
-0.05
2 4 6
Io=1A
8 10
VCC [V]
12 14 16 18
Figure 31. Soft-start
V
0.5V/div
L=6.8uH
F =500kHz
I I I I
I I I
0.5A/div
V
200mV/div
Figure 32. Short-circuit behavior
OUT
10V/div
I I
DocID13005 Rev 8 33/41
41
Application ideas L5983
The L5983 device can implement the step-up/down converter with a positive output voltage.
shows the schematic: one Power MOSFET and one Schottky diode are added to the standard buck topology to provide 12 V output voltage with input voltage from 2.9 V to
18 V.
Figure 33. Positive buck-boost regulator
34/41
The relationship between input and output voltage is:
Equation 31
V
OUT
= V
IN
so the duty cycle is:
Equation 32
D =
V
OUT
OUT
+ V
IN
The output voltage is not limited by the maximum operating voltage of the device (18 V), because the output voltage is sensed only through the resistor divider. The external Power
MOSFET maximum drain to source voltage, must be higher than output voltage; the maximum gate to source voltage must be higher than the input voltage (in
, if V
IN higher than 16 V, the gate must be protected through a Zener diode and a resistor).
is
The current flowing through the internal Power MOSFET is transferred to the load only during the OFF time, so according to the maximum DC switch current (1.5 A), the maximum output current for the buck-boost topology can be calculated from the following equation.
Equation 33
I
SW
=
I
------------- 1.5 A where I
SW
is the average current in the embedded Power MOSFET in the ON time.
DocID13005 Rev 8
L5983 Application ideas
To chose the right value of the inductor and to manage transient output current, which for a short time can exceed the maximum output current calculated by
Equation 33
, the peak current in the Power MOSFET must also be calculated. The peak current, shown in
Equation 34
, must be lower than the minimum current limit (2.0 A).
Equation 34
I
SW,PK
=
I
OUT
1 D
1 +
2
2.0A
r =
I
------------------------------------
OUT
V
OUT
L F
SW
–
2 where r is defined as the ratio between the inductor current ripple and the inductor DC current.
Therefore, in the buck-boost topology the maximum output current depends on the application conditions (firstly input and output voltage, secondly switching frequency and inductor value).
the maximum output current for the above configuration is depicted varying the
input voltage from 2.9 V to 18 V.
The dashed line considers a more accurate estimation of the duty cycles given by
Equation
35
, where power losses across diodes, the external Power MOSFET, and the internal Power
MOSFET are taken into account.
Figure 34. Maximum output current according to max DC switch current (1.5 A):
V
O
= 12 V
Equation 35
D =
V
IN
– V
SW
V
– V
+
SWE
+
D
V
OUT
+ 2 V
D where V
D
is the voltage drop across the diodes, and V external Power MOSFET.
SW
and V
SWE
across the internal and
DocID13005 Rev 8 35/41
41
Application ideas L5983
The L5983 device can implement the step-up/down converter with a negative output voltage.
shows the schematic to regulate -5 V: no further external components are added to the standard buck topology.
The relationship between input and output voltage is:
Equation 36
V
OUT
= – V
IN
so the duty cycle is:
Equation 37
D
=
V
OUT
V
OUT
V
IN
As in the positive one, in the inverting buck-boost the current flowing through the Power
MOSFET is transferred to the load only during the OFF time. So according to the maximum
DC switch current (1.5 A), the maximum output current can be calculated from
Equation 33
, where the duty cycle is given by
Equation 37
.
Figure 35. Inverting buck-boost regulator
36/41
The GND pin of the device is connected to the output voltage so, given the output voltage, the input voltage range is limited by the maximum voltage, the device can withstand across
V
CC
and GND (18 V). Therefore, if the output is -5 V, the input voltage can range from 2.9 V to 13 V.
As in the positive buck-boost, the maximum output current according to application conditions is shown in
. The dashed line considers a more accurate estimation of the duty cycles given by
Equation 38
, where power losses across diodes and the internal
Power MOSFET are taken into account:
DocID13005 Rev 8
L5983 Application ideas
Equation 38
D =
– V
IN
–
V
V
OUT
SW
+
–
V
V
OUT
– V
D
Figure 36. Maximum output current according to max DC switch current (1.5 A):
V
O
=-5 V
DocID13005 Rev 8 37/41
41
Package information L5983
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST registered trademark.
Figure 37. VFQFPN8 (3 x 3 x 1.08 mm) package outline
38/41 DocID13005 Rev 8
L5983
b
D
D2
A1
A2
A3 e
L
E
E2 ddd
Package information
Symbol
A
Table 10. VFQFPN8 (3 x 3 x 1.08 mm) package mechanical data
Dimensions
Min.
0.80
mm
Typ.
0.90
Max.
1.00
Min.
0.0315
inch
Typ.
0.0354
Max.
0.0394
0.05
0.0020
0.18
2.95
2.23
2.95
1.65
0.35
0.02
0.70
0.20
0.23
3.00
2.38
3.00
1.70
0.50
0.40
0.30
3.05
2.48
3.05
1.75
0.45
0.08
0.0071
0.1161
0.0878
0.1161
0.0649
0.0137
0.0008
0.0276
0.0079
0.0091
0.1181
0.0937
0.1181
0.0669
0.0197
0.0157
0.0118
0.1200
0.0976
0.1200
0.0689
0.0177
0.0031
DocID13005 Rev 8 39/41
41
Order codes
Order codes
L5983TR
Table 11. Order codes
Package
VFQFPN8 (3 x 3 x 1.08 mm)
Packaging
Tape and reel
L5983
Date
21-Dec-2006
16-Oct-2007
27-May-2008
16-Sep-2008
28-Jan-2009
15-Jun-2009
29-Nov-2010
12-May-2014
Revision
Table 12. Document revision history
Changes
4
5
6
1
2
3
7
8
Initial release
Document status promoted from preliminary data to datasheet
,
,
,
,
Updated:
Equation 18
Updated
,
Numbered
Added V
CC
.
values to titles from
Updated
Section 7: Package information on page 38
(updated titles,
Updated
related to the VFQFPN8 in tube, updated “Packaging” of the
L5983TR order code).
Updated cross-references throughout document.
Minor modifications throughout document.
40/41 DocID13005 Rev 8
L5983
Please Read Carefully:
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41
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