AMS AS3607 Datasheet
Advertisement
Advertisement
austriamicrosystems AG is now ams AG
The technical content of this austriamicrosystems datasheet is still valid.
Contact information:
Headquarters:
ams AG
Tobelbaderstrasse 30
8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0 e-Mail: [email protected]
Please visit our website at
www.ams.com
Data Sheet
AS3606 AS3607
System PMU with HV Back Light Driver
1 General Description
HV Backlight Driver
Step up for 30V backlight with internal transistor
The AS3606/07 is an ultra compact System PMU with integrated battery charger and HV back light driver.
The device offers advanced power management functions. All necessary ICs and peripherals in a battery powered mobile device are supplied by the AS3606/07. It features 3 DCDC converters as well as 5 low noise LDOs. The different regulated supply voltages are programmable via the serial control interface.
The step-up converter for the backlight can operate up to 30V. Both constant voltage (OLED supply) as well as constant current (white
LED backlight) operations with 2 current sinks are possible. An internal voltage protection is limiting the output voltage in the case of external component failures.
AS3606/07 also contains a Li-Ion battery charger with constant current and constant voltage. The maximum charging current is 1A.
An integrated battery switch and an optional external switch are separating the battery during charging or whenever an external power supply is present. With this switch it is also possible to operate with no or deeply discharged batteries. A programmable current limit can be used to control the maximum current used from a USB supply.
Voltage control mode and over-voltage protection
2 programmable current sink (max. 38mA)
Max. 20mA@50V (with ext. transistor) or 500mA@5V
Possible external PWM dimming input
Battery Charger
Prog. trickle charging (25-265mA)
Prog. constant current charging (94-1060mA)
Prog. constant voltage charging (3.9V-4.25V)
Charger time-out and temperature supervision
Selectable current limitation for USB mode
Integrated battery switch & ideal diode
AG still
Battery and Temperature Supervisor valid
The single supply voltage may vary from 2.7V to 5.5V.
2 Key Features
Power Management
Voltage Generation
3 DCDC step down regulators
ams
Status output for: charger, low battery, power good and power-
Programmable start-up sequence
Applicable for LDO 1-4 and DCDC 1-3
- DVM (0.61V-3.3V, 700mA)
- 50µA quiescent current
2 or 4 General Purpose IOs
10bit general purpose ADC input
PWM dimming input or wake-up input
Control Interface
- Selectable switching frequency (2 or 1MHz)
I2C control lines, including watchdog
- 1.4A with combined DCDC 2 & 3
1 LDO low noise 2.7V (2.3-3.5V), 100mA Power-Up input
3 or 4 LDOs low noise Interrupt output
Bidirectional reset, with selectable delay
Low power standby mode, 160µA with LDO5 on
- 1.2-3.5V; 150/250mA
- 30µA quiescent current (low power mode)
Power supply supervision (LDO5)
4sec and 8sec emergency shut-down
Technical
Power-On Reset Circuit
Packaging
QFN32 5x5mm or QFN36 6x6mm, 0.5mm pitch
3 Application
The devices are ideal for Portable Media Players and Portable
Navigation Devices, e-Books, Tablet PCs, etc www.austriamicrosystems.com
Revision 1.03
1 - 70
AS3606 AS3607 2v2
Data Sheet - A p p l i c a t i o n
Figure 1. AS3606 Block Diagram
Figure 2. AS3607 Block Diagram
AG still valid
Technical
www.austriamicrosystems.com
Revision 1.03
2 - 70
AS3606 AS3607 2v2
Data Sheet - C o n t e n t s
Contents
1 General Description ..................................................................................................................................................................
1
2 Key Features.............................................................................................................................................................................
1
3 Application ................................................................................................................................................................................
1
4 Pin Assignments .......................................................................................................................................................................
5
4.1 Pin Descriptions....................................................................................................................................................................................
6
5 Absolute Maximum Ratings ......................................................................................................................................................
8
6 Electrical Characteristics...........................................................................................................................................................
9
7 Typical Operating Characteristics ...........................................................................................................................................
11
8 Detailed Description - Power Management Functions............................................................................................................
8.1 Low Drop Out Regulators...................................................................................................................................................................
valid
8.1.2 LDO 1, LDO2, LDO3 & LDO4.................................................................................................................................................... 13
8.1.3 Parameter.................................................................................................................................................................................. 13
8.2 DCDC Step-Down Converter..............................................................................................................................................................
15
8.2.1 Functional Description ............................................................................................................................................................... 16
8.2.2 Parameter.................................................................................................................................................................................. 17
AG still
19
8.3.1 Voltage Feedback and OV Protection ....................................................................................................................................... 19
8.3.2 Voltage Feedback...................................................................................................................................................................... 19
8.3.3 DLS & Dimming ......................................................................................................................................................................... 20
8.3.4 Current Sinks ............................................................................................................................................................................. 20
8.3.5 Parameter.................................................................................................................................................................................. 20
ams
22
8.4.4 Battery Temperature Supervision .............................................................................................................................................. 23
8.4.6 Charger Modes .......................................................................................................................................................................... 24
9 Detailed Description - SYSTEM Functions
www.austriamicrosystems.com
Revision 1.03
3 - 70
AS3606 AS3607 2v2
Data Sheet - C o n t e n t s
9.7 2-Wire-Serial Control Interface
11.1 Pad Cells
.......................................................................................................................................................................................... 62
11.2 Application Schematics
.................................................................................................................................................................... 63
12 Package Drawings and Markings
valid
AG still
Technical
www.austriamicrosystems.com
Revision 1.03
4 - 70
AS3606 AS3607 2v2
Data Sheet - P i n A s s i g n m e n t s
4 Pin Assignments
Figure 3. Pin Assignments (Top View)
AG still valid
Technical
www.austriamicrosystems.com
Revision 1.03
5 - 70
AS3606 AS3607 2v2
Data Sheet - P i n A s s i g n m e n t s
4.1 Pin Descriptions
Note:
Pin description may change in preliminary data sheets.
Table 1. Pin Description for AS3606/07
Pin Name Type Description if not used
VBATSW
VSUPSW
Pin Number
AS3606 AS3607
-
1
1
2
SUP IO
Battery Switch Terminal to be connected to the Li-Ion battery open
SUP IO Battery Switch Terminal to be connected to system supplies VSUPx always needed
VUSB
BATTEMP
EXTBATSW
VDD27
PVDD4
VSUP5
PVDD3
PVDD2
PVDD1
VSUP4
VSUP1
LXC1
CVDD1
CURR2
CURR1
LXSU
FBSU
GPIO4
GPIO2
GPIO1
17
-
18
19
13
14
15
16
9
10
11
12
7
8
-
6
3
5
2
4
19
20
21
22
15
16
17
18
11
12
13
14
9
10
7
8
5
6
3
4
SUP IN
Charger or USB Bus Power Input
ANA IO
Li-Ion Charger Battery Temp. Sensor Input
ANA OUT
External Battery Switch Gate Driver Output
SUP IO LDO5 Output default 2.7V
ANA OUT
LDO4 Output
ANA OUT LDO2 Output
ANA OUT
LDO1 Output
SUP IN
SUP IN
AG
DIG OUT CVDD1 Step Down Switch Output to Coil
ANA IN
CVDD1 and Feedback Pin open open open open open
valid
SUP IN
LDO3/4 & LDO5 Pos. Supply Terminal, connect to VSUPSW
ANA OUT
LDO3 Output always needed
still
open open open always needed always needed open
ANA IO
Load Current Sink2 Terminal
ANA IO
DIG OUT
ANA IN
ANA IO
ANA IO
ams
ANA IO General Purpose IO 1
ANA IO
General Purpose IO 3 open open open open open open open open
DIG IN
2-wire SERIF Clock Input
DIG IO
2-wire SERIF Data I/O open open
GPIO3
CSCL
CSDA
PWRUP
-
20
21
22
23
24
25
26 DIG IN Power Up Input
XIRQ
XRES
23
24
27
28
DIG OUT
Interrupt Request Output
DIG IO
Reset Output
SUP IN
Digital Periphery Pos. Supply Terminal
DVDD 25 29
VSUP3
LXC3
CVDD3
CVDD2
26
27
28
29
30
31
32
33
SUP IN CVDD3 Step Down Pos. Supply Terminal
DIG OUT
CVDD3 Step Down Switch Output to Coil
ANA IN
CVDD3 and Feedback Pin
ANA IN
CVDD2 and Feedback Pin open open open always needed
VSUPx open open open www.austriamicrosystems.com
Revision 1.03
6 - 70
AS3606 AS3607 2v2
Data Sheet - P i n A s s i g n m e n t s
Table 1. Pin Description for AS3606/07
Pin Name
LXC2
VSUP2
VBATSW
VSS
Pin Number
AS3606 AS3607
30
31
32
33
34
35
36
37
Type Description
DIG OUT
CVDD2 Step Down Switch Output to Coil
SUP IN
CVDD2 Step Down Pos. Supply Terminal
SUP IO
Battery Switch Terminal to be connected to the Li-Ion battery
SUP IO Exposed Pad: Neg. Supply Terminal for all blocks
AG if not used
open always needed open always needed
still valid
Technical
www.austriamicrosystems.com
Revision 1.03
7 - 70
AS3606 AS3607 2v2
Data Sheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
maximum rating conditions for extended periods may affect device reliability. The device should be operated under recommended operating conditions.
Table 2. Absolute Maximum Ratings
Parameter
5V pins
3V pins
30V pins
5V pins with protection to VSUPx
3V pins with protection to VDD27
3V pins with protection to DVDD
3V pins with protection to VSUPx
Input Current (latch-up immunity)
Continuous Power Dissipation (T
A
= +85ºC)
Continuous power dissipation
Min
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-100
Electrostatic Discharge
Electrostatic Discharge HBM
Temperature Ranges and Storage Conditions
Junction Temperature
Storage Temperature Range
ams
-55
5
±1.5
+110
+125
85
Humidity non-condensing
Temperature (soldering)
Max Units Comments
7.0
V
Applicable for pins VBATSW, VSUPSW, VSUP1/
2/3/4/5, PWRUP, GPIO1/2/3/4, VBUS
5.0
32
7.0
VSUPx+0.5
V
V
V
V
Applicable for pins DVDD
Applicable for pin LXSU, CURR1/2
Applicable for pins EXTBATSW, FBSU
valid
Applicable for pins BATTEMP
5.0
VDD27
V
5.0
DVDD+0.5
5.0
VSUPx+0.5
1
100
V
AG
W
Applicable for pins XIRQ, XRES, CSCL, CSDA
still
Norm: JEDEC 78
P
T
1
for QFN32/36 package (R
TH
~ 30K/W) kV
%
Norm: JEDEC JESD22-A114C
Package Body Temperature
260 ºC
Norm IPC/JEDEC J-STD-020
2
The lead finish for Pb-free leaded packages is matte tin (100% Sn)
Represents a max. floor live time of 168h Moisture Sensitive Level 3
1. Depending on actual PCB layout and PCB used
2. The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity
Classification for Nonhermetic Solid State Surface Mount Devices”
Technical
www.austriamicrosystems.com
Revision 1.03
8 - 70
AS3606 AS3607 2v2
Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
VSUPx=+2.7V...+5.5V, T
A
=-40ºC...+85ºC. Typical values are at VSUPx=+3.6V, T
A
=+25ºC, unless otherwise specified.
Table 3. Electrical Characteristics
Symbol
VBATSW
Parameter
Battery Supply Voltage
Condition
operation, VBUS > 2.7V
operation from battery
Min
0
2.7
Typ
3.6
3.6
Max
5.5
5.5
Unit
V
V
VSUPx 2.7
3.6
5.5
V
Supply Voltage
VSUPSW, VSUP1/2/3/4/5
VBUS
DVDD
VDD27
V
DELTA
+
T
AMB
I
SD
I q
IO Pins
VID
3V
USB VBUS Voltage
Digital Periphery Supply Voltage
Analog Supply Voltage
Difference of Positive Supplies
Operating Temperature Range
Shut-down current
Quiescent current
3V digital input pins
XRES, CSCL, CSDA operating, VSUP5 > 2.7V
charging
VDD27-VSUPx
@ VBATSW = 4.2V
All regulators off
AG
0
4.5
1.8
2.6
-40
0
VIA
3V
VI
5V
VI
5V
VI
30V
3V input pin
BATTEMP
5V input pins
GPIO1/2/3/4
5V input pin
FBSU
20V analiog input pins
LXSU, CURR1/2
0
ams
0
content
POR & Watchdog
V
POR_ON
Power-on Reset Activation Level
Power-on Reset activation level when
VDD27 decreases
V
POR_OFF
Power-on Reset Release Level
Power-on Reset release when VDD27 increases
V
POR_HY
PWRUP
Power-on Hysteresis t
ON_DELAY
Delay Time of pin PWRUP
Minimum key press time
V
V
PWRUP_L
PWRUP_H
Input Level LOW
Input Level HIGH
Pin PWRUP, VSUP5>3V
Pin PWRUP, VSUP5>3V
Pin PWRUP, VSUP5<=3V
I
PWRUP
Internal Pull-down Current Source
Pin PWRUP; @2.7V
60
VSUP5/3
1
10
2.15
2.0
100
20
5.0
5.0
2.7
5.5
5.5
3.6
3.5
0
600
160
+85
still
3.6V or
DVDD
+0.5
ºC nA
µA
V
V
V
V
V
valid
V
3.6V or
VDD27
+0.5
5.5V
5.5V or
VSUP5
+0.5
30
0.5
30
V
V
V
V
V
V mV ms
V
V
V
µA www.austriamicrosystems.com
Revision 1.03
9 - 70
AS3606 AS3607 2v2
Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 3. Electrical Characteristics (Continued)
Symbol
Digital Inputs/Outputs
V
DO_DL
Parameter
Digital Output Driver Capability
(drive LOW)
V
I
I
PU
PD
DI_L
Condition
Internal Pull-up Current Source
Internal Pull-down Current Source
Digital Input Level LOW
Pins XRES, XIRQ, GPIOx @ 6mA, open drain mode
Pins XIRQ @ 0V
Pins CSDA, CSCL @ 0V
Pins GPIOx @ 2.7V
Pin GPIOx
V
DI_H
Digital Input Level HIGH
Pin GPIOx
Min
8
AG
Typ Max Unit
V
20%
DVDD
13
100
13
µA
µA
µA 20
30%
DVDD
70%
DVDD
still
V
V
valid
Technical
www.austriamicrosystems.com
Revision 1.03
10 - 70
AS3606 AS3607 2v2
Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
7 Typical Operating Characteristics
VSUPx = +3.6V, TA = +25ºC, unless otherwise specified.
AG still valid
Technical
www.austriamicrosystems.com
Revision 1.03
11 - 70
AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s
8 Detailed Description - Power Management Functions
8.1 Low Drop Out Regulators
These LDOs are designed to supply sensitive analog circuits, audio devices, AD and DA converters, micro-controller and other peripheral devices. The design is optimized to deliver the best compromise between quiescent current and regulator performance for battery powered devices.
Stability is guaranteed with ceramic output capacitors of 1µF ±20% (X5R) or 2.2µF +100/-50% (Z5U). The low ESR of these caps ensures low output impedance at high frequencies. Regulation performance is excellent even under low dropout conditions, when the power transistor has to operate in linear mode. Power supply rejection is high enough to suppress high ripple on the battery at the output. The low noise performance allows direct connection of noise sensitive circuits without additional filtering networks. The low impedance of the power device enables the device to deliver up to 150mA even at nearly discharged batteries without any decrease of performance.
Figure 4. LDO Block Diagram
valid
AG still
8.1.1 LDO5
This LDO generates the digital supply voltage used for the PMU itself.
Input Voltage is VSUP5
Output Voltage is VDD27 (typ. 2.7V), this LDO always starts at the beginning of the start-up sequence as it is needed for all further operation. The default voltage cannot be changed in the boot ROM.
Driver strength: 100mA, can be programmed to 200mA
It is set to a default output voltage of 2.7V, 100mA max
. It supplies the analog and digital part of the PMU. Additional external loads are possible but must not exceed the supply ratings in total together with the operating internal blocks. Further, the external load must not induce noise to the
VDD27.
Technical
www.austriamicrosystems.com
Revision 1.03
12 - 70
AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s
8.1.2 LDO 1, LDO2, LDO3 & LDO4
These LDOs can be used to generate the periphery voltage for the digital processor or other external components (e.g. ext. DAC, USB-PHY, SD-
Cards, NAND-Flashes, FM-Tuner …). LDO4 is only available on AS3607.
Input Voltage VSUP5 for LDO3 and LDO4, and VSUP4 for LDO2 and LDO1
Output Voltage is PVDD1, PVDD2, PVDD3 & PVDD4 (1.2V to 3.5V)
Default value at start-up is defined by the boot ROM, when the boot ROM is not programmed the LDOs will not start-up
Driver strength: 150mA, can be programmed to 250mA
8.1.3 Parameter
VSUPx=3.6V, T
A
= 25ºC, unless otherwise specified.
Table 4. LDO Parameter
Symbol
R
ON
Parameter
On resistance
PSRR
I
OFF
I
VDD
Noise t start
V out_tol
V
LineReg
V
LoadReg
I
LIMIT
Condition
Power supply rejection ratio f=1kHz f=100kHz
Shut down current
Supply current
Output noise
Startup time
Output voltage tolerance
Line regulation
Load regulation without load
AG
minimum ±50mV
ams
Static
Transient; Slope: t r
=10µs
Static
Transient; Slope: t r
=10µs has to be enabled via register
Current limitation
-2.5%
Min Typ
70
40
still
50
200
Max
1 nA
μ A
μ A
µV
Unit
Ω dB
valid
rms
µs
2.5% mV
<1
<10
<1
<10
190
350 mV mV mA
Technical
www.austriamicrosystems.com
Revision 1.03
13 - 70
AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s
Figure 5. LDO Characteristics
Load Regulation
Output Noise transient load: 1mA – 100mAslope: 1µs
Load Regulation
AG
Output load: 150mA
Load Regulation
still valid
output load: 10mA transient input voltage ripple: 500mV
Technical
www.austriamicrosystems.com
Revision 1.03
output load: 150mA transient input voltage ripple: 500mV
14 - 70
AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s
8.2 DCDC Step-Down Converter
These converters are meant to convert the battery voltage down to voltages which fit to the core and peripheral supply voltage requirements for microprocessors.
Input Voltage VSUP1/2/3 (usually connected to VSUPSW)
Output Voltage CVDD1 & CVDD2 & CVDD3
Output voltage levels can be programmed independently form 0.61V to 3.35V
The default value at start-up is defined by the boot ROM
DVM for all three outputs with selectable timings
Driver strength 700mA, DCDC2 & 3 can be combined together to double the output current
Under- and over-voltage detection
High efficiency current force mode
1MHz or 2MHz switching frequency
Fast regulation mode
Figure 6. DCDC Step-Down Block Diagram
AG still valid
Technical
www.austriamicrosystems.com
Revision 1.03
15 - 70
AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s
8.2.1 Functional Description
The step-down converter is a high efficiency fixed frequency current mode regulator. By using low resistance internal PMOS and NMOS switches efficiency up to 97% can be achieved. The fast switching frequency allows using small inductors, without increasing the current ripple. The unique feedback and regulation circuit guarantees optimum load and line regulation over the whole output voltage range, up to an output current of 700mA, with an output capacitor of only 10µF. The implemented current limitation protects the DCDC and the coil during overload condition.
To achieve optimized performance in different applications, adjustable settings allow to compromise between high efficiency and low input, output ripple:
Low Ripple, Low Noise Operation (current force mode = OFF).
In this mode there is no minimum coil current necessary before switching off the PMOS. As result, the ON time of the PMOS will be reduced down to tmin_on at no or light load conditions, even if the coil current is very small or the coil current is inverted. This results in a very low ripple and noise, but decreased efficiency, at light loads, especially at low input to output voltage differences. In the case of an inverted coil current the regulator will not operate in pulse skip mode.
Figure 7. DCDC Buck with Disabled Current Force / Pulse Skip Mode
valid
AG
1: LXC1 voltage
still
3: Output voltage
High Efficiency Operation (current force mode = ON).
content
Figure 8. DCDC Buck with Enabled Current Force / Pulse Skip Mode
Technical
It’s also possible to switch between these two modes dynamically during operation.
www.austriamicrosystems.com
Revision 1.03
1: LXC1 voltage
2: Coil current (1mV=1mA)
3: Output voltage
16 - 70
AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s
DVM (Dynamic Voltage Management).
To minimize the over-/undershoot during a change of the output voltage, the DVM can be enabled.
With DVM the output voltage will ramp up/down with a selectable slope after the new value was written to the registers. Without DVM the slew rate of the output voltage is only determined by external components like the coil and load capacitor as well as the load current.
Fast Regulation Mode.
This mode can be used to react faster on sudden load changes and thus minimize the over-/undershoot of the output voltage. FRM needs an 22uF output capacitor instead the 10uF one to guarantee the stability of the regulator.
Low Frequency Operation.
Especially for very low load conditions, e.g. during a sleep mode of a processor, the switching frequency can be reduced to achieve a higher efficiency.
100% PMOS ON Mode for Low Dropout Regulation.
For low input to output voltage difference the DCDC converter can use 100% duty cycle for the PMOS transistor, which is than in LDO mode.
8.2.2 Parameter
VSUP=3.6, T
A
= 25ºC, unless otherwise specified.
Table 5. DCDC Parameter
Symbol
V
IN
V
OUT
V
OUT_tol
I load
I
LIMIT
R
PSW
R
NSW
Parameter
Input voltage
Regulated output voltage
Output voltage tolerance
Maximum Load current
Current limit
P-Switch ON resistance
N-Switch ON resistance
Condition
VSUPx minimum ±50mV
AG
VSUPx=3.0V
Min Typ
1000
0.5
Max
2.7
0.6125
-3%
600
5.5
3.35
still
0.7
V mV mA mA
Unit
V
valid
Ω
0.5
0.7
Ω f
SW f
SWsc
C out
Lx
η eff
I
VDD t
MIN_ON
Switching frequency
Switching frequency
Output capacitor
Inductor
Efficiency
Current consumption
Minimum on time
Minimum off time depending on DCDC_Cntr settings
ams
in shortcut case
Ceramic, ±10% tolerance
±10% tolerance
content
1/2
0.6
10
2.2
97
65
0.1
80
40
MHz
MHz
µF
µH
%
µA ns ns t
MIN_OFF
Static 2 mV
V
LineReg
Line regulation
Transient; Slope: t r
=10µs, 100mV step, 200mA load
Static
10
5 mV
Load regulation
V
LoadReg
Transient; Slope: t r
100mA step
=10µs, 50
Technical
www.austriamicrosystems.com
Revision 1.03
17 - 70
AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s
1,225
1,215
1,205
1,195
1,185
1,175
0
Figure 9. DCDC Step-down Performance Characteristics
DCDC buck Efficiency @2MHz, 3.6V VSUPx
100,00
95,00
90,00
85,00
80,00
75,00
70,00
65,00
60,00
1
CVDD1 @ 1,2V Vout
CVDD1 @ 1,8V Vout
CVDD1 @ 3V Vout
10 100
Output Current [mA]
1000
Output voltage vs. Output Current
50
Line Regulation still
1,21
100
OUTPUT CURRENT [mA] ams
200
V
IN
=3.6V
250
1,205
1,195
3 3,4 3,8 4,2
INPUT VOLTAGE [V]
150
I
OUT
=0mA
I
OUT
=125mA
I
OUT
=250mA
4,6
V
OUT
=1.2V
5
valid
Technical
www.austriamicrosystems.com
Revision 1.03
18 - 70
AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s
8.3 30V Step-Up DCDC Converter
The integrated Step-Up DC/DC Converter is a high efficiency current-mode PWM regulator, providing an output voltage up to 30V. A constant switching-frequency results in a low noise on supply and output voltages.
It has two programmable high voltage current sinks (0 to 38.25mA) for driving e.g. white LEDs as back-light. It can drive also unbalanced strings due to the internal automatic feedback selection.
A voltage feedback mode allows generating constant supply voltages for e.g. OLEDs. The output voltage is set by an external resistor divider and an internal current sink.
An internal protection circuit will shut down the regulator if the voltage on FBSU exceeds the over voltage threshold. No more external protection has to be used to avoid an exceeding of the operation conditions in a no load situation.
Figure 10. DCDC15 Block Diagram
AG still valid
8.3.1 Voltage Feedback
= 0 enables voltage feedback at pin FBSU.
The output voltage is regulated to a constant value, given by (Bit
should be set to 1 in this configuration)
U
Step up_out
= (R
1
+R
2
)/R
2
*1.25 + I
FB
* R
1
If R2 is not used, the output voltage is by (Bit
should be set to 0 in this configuration)
Where:
U
R
R
1
2
Technical
I
FB
= Tuning current at pin FBSU; 0 to 31µA
U
Step up_out
= 1.25 + I
FB
* R
1
www.austriamicrosystems.com
Revision 1.03
(EQ 1)
(EQ 2)
19 - 70
AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s
Table 6. Voltage Feedback Example Values
IDCDC_FB
µA
0
1
2
U
Step up_out
R1 = 1M
Ω
, R2 not used
-
-
-
U
Step up_out
R1 = 500k
Ω
, R2 = 50k
Ω
13.75
14.25
14.75
3
4
5
6
7
8
9
10
11
12
13
14
-
-
6.25
7.25
8.25
9.25
10.25
11.25
12.25
13.25
14.25
15.25
AG
15.25
15.75
16.25
16.75
17.25
17.75
18.25
still
19.75
20.25
20.75
valid
15 16.25
21.25
…
30
31
ams
Note:
The voltage on CURR1 and CURR2 must not exceed 30V.
…
31.25
32.25
…
28.75
29.25
8.3.2 Over Voltage Protection (OVP) content
= 1 enables feedback via the current sink pins. The voltage on the current sink pin is regulated to
selection of the current sink with the larger load is done automatically. The pin FBSU acts as an overvoltage protection in this mode. Please be sure to set the voltage to a higher level than needed to drive the longer LED string. the calculation of the resistor can be done the same as described in the chapter above.
8.3.3 DLS & Dimming
AS3606/07 feature external dimming inputs via CURR1, CURR2, GPIO1 or GPIO2 by directly connecting a PWM output of e.g. the display controller for DLS (dynamic luminance scaling). Manual dimming can be done at any time by setting the sink current via I2C commands.
8.3.4 Current Sinks
The current sinks work independent from each other and can also be used without the booster, or can act as a dimming input if they are not needed as a sink.
Technical
www.austriamicrosystems.com
Revision 1.03
20 - 70
AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s
8.3.5 Parameter
VSUPx=3.6V, T
A
= 25ºC, unless otherwise specified.
Table 7. DCDC Parameter
Symbol
V
SW
I
VDD
Parameter
High Voltage Pin
Quiescent Current
Condition
Pin FBSU
Pulse Skipping mode
Min
0
Typ
140
Max
30
Unit
V
µA
V
FB
Feedback Voltage, Transientt
Pin CURR1 or CURR2
Pin FBSU
0
0
30
5
V
V
V
FBSU
V
CURR
I
DCDC_FB
R
SW
I
LOAD
F
SW
C
OUT
Feedback Voltage, for voltage regulation
Feedback Voltage, for current sink regulation
Additional Tuning Current at Pin
DCDC_FB and over voltage protection
Accuracy of Feedback Current at full scale
Switch Resistance
Load Current
Fixed Switching Frequency
Output Capacitor
Pin FBSU
Pin CURR1 or CURR2
Adjustable by software using Register DCDC control1
1µA step size (0-31µA)
V
PROTECT
= 1.25V +
IDCDC_FB * R
1
SU_FREQU = 0
Ceramic, ±20%. Use nominal 4.7µF capacitors to obtain at least 0.7µF under all conditions
(voltage dependence of capacitors)
L t
MIN_ON
MDC
Inductor
Minimum On-Time
Maximum Duty Cycle
Figure 11. 30V Step-Up Performance Characteristics
Use inductors with small C
PARASITIC for high efficiency
(<100pF)
Guaranteed per design
content
DCDC Boost 6 LEDs
84
90,00
7
0
-6
0
1.2
0.4
0.7
1.25
0.5
1.3
0.6
31
still
1
6
1
50
%
Ω mA
V
V
µA
valid
MHz
4.7
µF
10
100
90
13
190
µH ns
%
85,00
80,00
75,00
70,00
65,00
60,00
1 10
Output Current [mA]
100 www.austriamicrosystems.com
Revision 1.03
21 - 70
AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s
8.4 Charger
This block can be used to charge a 4V Li-Ion accumulator. It supports constant current and constant voltage charging modes with adjustable charging currents (94 to 1000mA) and maximum charging voltage (3.9 to 4.25V).
The charger consists basically of a pre-regulator, which limits the current from e.g. the USB input and provides a constant VSUP after reaching
EOC (end of charge) and the battery switch, which is controlling the current into the battery.
Input Voltage of the pre-regulator: VUSB
Output of the pre-regulator and input for the battery switch and system supply: VSUPSW
Output of the battery switch and battery terminal: VBATSW
CVM (constant voltage), CCM (constant current) and trickle charging
Adjustable EOC voltage and EOC current limit
Selectable input -, trickle- and charging-current limit
Auto-resume with selectable resume voltage level
Charger time-out supervision with selectable time-out setting
Battery temperature supervision supporting two levels (45 or 50ºC) and 100k or 10k NTC types
No battery detection
Status register and interrupt generation
Per default the USB current limit is set to 470mA and the charger is switched off.
Figure 12. Charger Block Diagram
AG still valid
Technical
www.austriamicrosystems.com
Revision 1.03
22 - 70
AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s
Figure 13. Charger States
still valid
AG
8.4.1 Soft Charge/Trickle Charge
265mA. After reaching the 3V level the charger switches to the constant current mode with the programmed charging current.
8.4.2 End of Charge Detection content
8.4.3 VSUPSW and Temperature Supervision
The charger will automatically reduce the charging current if VSUPSW drops below the selected level. It will automatically stop charging when the chip temperature gets too to hot. The charger will return to normal operation as defined in the charger registers if VSUPSW and the chip temperature return to their normal operating range.
8.4.4 Battery Temperature Supervision
This charger block also features a supply for an external NTC resistor to measure the battery temperature while charging. If the temperature is
too high (voltage on BATTEMP pin is below
) the charger will stop operation. If needed an interrupt can be generated based on
this event. When the battery temperature drops the charger the voltage on BATTEMP pin will rise above
and the charger will start charging again. This is forming a temperature hysteresis of about 3 to 5°C to avoid an oscillation of the charger.
The levels for switching off the charger (45ºC or 55ºC) as well as the type of NTC (10k or 100k) can be selected via register settings. The battery
temperature supervision via the NTC can be switched off (
Technical
If the charger state machine reaches EOC 2 times within a very short period it assumes that there is no battery connected to the VBATSW terminal.
After this a sensing current of 1uA is applied to the BATTEMP pin to detect if a battery is reconnected.
www.austriamicrosystems.com
Revision 1.03
23 - 70
AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s
8.4.6 Charger Modes
Figure 14. Charger Modes
AG still valid
8.4.7 Parameter
VDD27=2.7, T
A
= 25ºC, unless otherwise specified.
Table 8. Charger Parameter
Symbol Parameter
I
CHG
(0-7) Charging Current
Condition
@ 470mA
V
CHG
(0-7)
V
V
ON_ABS
ON_REL
Charging Voltage
Technical
V
OFF_REL end of charge is true rising edge on VUSB start rising edge on VUSB end
VUSB-VBATSW
VUSB-VBATSW
Battery Temp. high level
(45 or 55ºC)
VSUP >3V
NTC beta
=4200
V
BATTEMP_ON www.austriamicrosystems.com
Revision 1.03
Min
I
NOM
-8%
V
NOM
-50mV
3.5V
I
Typ
NOM
V
NOM
Max
I
NOM
+8%
V
NOM
+33mV
0.8
Unit
mA
170
50
610 or
400
240
V
V
V mV mV mV
24 - 70
AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s
Table 8. Charger Parameter
Symbol
V
BATTEMP_OFF
Parameter
Battery Temp. low level
(42 or 50ºC)
I
BATTEMP
NTC Bias Current
I
CHG_OFF
I
REV_OFF
R
ON_BATSW
End Of Charge current level
Reverse current shut down
Battery Switch On-resistance
Condition
VSUP >3V
NTC beta
=4200
100k
10k
VSUP >3V
VSUPSW = 5V, VUSB open
AG
Min Max Unit Typ
700 or
500 mV
µA
15
150
I
8%
10%
15%
20%
NOM mA
<1
0.15
still
µA
Ω
valid
Technical
www.austriamicrosystems.com
Revision 1.03
25 - 70
AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s
9 Detailed Description - SYSTEM Functions
9.1 SYSTEM
The system block handles the power up, power down and regulator voltage settings of the PMU.
9.1.1 Power Up/Down Conditions
The chip powers up when one of the following conditions is true:
Table 9. Power UP Conditions
# Source Description
9
5
6
7
8
4
1
2
PWRUP PwUp
VBUS PwUp
Table 10. Power DOWN Conditions
#
1
2
3
Source
SERIF MAJOR PwDn
Emergency PwDn
SERIF Watch-Dog PwDn
ON_KEY High Level at PWRUP pin of >= 1/3 VBATSW
USB Plug-In …. High level at VBUS pin of >= 4.5V and >2.7V on VSUP5
The chip automatically shuts off if one of the following conditions arises:
valid
Description
Power-Down
by SERIF writing 0h to register 20h
Power-Down
if PWRUP pin is HIGH for 8sec.
This has to be enabled in register 21h, per default a reset cycle is initiated. It can also be changed to 4s.
Power-Down
Power-Down
AG
This threshold can be lowered with bits <4:0> in reg 21h.
This supervisor can be disabled with bit 2 in reg. 20h.
still
Junction-Temp PwDn
VDD27 LOW PwDn
CVDD1 LOW PwDn
CVDD2 LOW PwDn
CVDD3 LOW PwDn
Power-Down
if VDD27 LDO5 has 10% under-voltage for more than 680µs.
This supervisor can get disabled with bit 6 in reg. 21h.
ams
CVDD2 DCDC has 10% under-voltage for more than 680µs.
Power-Down
if enabled with bit 3 in reg. 23h and
Power-Down
if VSUPx goes below the defined level in Reg22h (bits <3:1>)
This supervisor has to be enabled with bit 4 in reg. 22h.
VSUP LOW PwDn
9.1.2 Start-up Sequence
The start-up sequence is defined in the boot ROM and will be fixed during the production test.
The sequence and voltage of the regulators can be freely chosen for the start-up sequence with the following limitations:
VDD27 will always start-up, after a ~5ms delay the sequencer will start-up the other chosen regulators with either 0, 1 or 4ms delay each.
A maximum of 6 regulators (no matter of DCDC or LDO) or 5 regulators and a changed GPIO configuration can be chosen for the start-up.
On a 7th time-slot PVDD2 can be started-up, but has reduced setting on the output voltage
PWRGOOD will be activated ~3ms after the last regulator.
Technical
www.austriamicrosystems.com
Revision 1.03
26 - 70
AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s
9.2 Hibernation
Hibernation allows shutting down a part or the complete system. Hibernation can be terminated by every possible interrupt of the PMU. The interrupt has to be enabled before going to hibernation.
Table 11. Hibernation
State
Enter via GPIO
Description
To enter hibernation mode the following settings have to be done:
- Enable just these IRQ sources which should lead to leave hibernation mode.
- Make sure that IRQ is inactive (IRQ flags get cleared by Reg 23h-26h readings.
- Set the GPIO to input
- Select the GPIO for hibernation control (
- Enable hibernation via GPIO (
)
17h-4. This register MUST NOT be read back!!!
- Drive the selected GPIO to LOW.
Note that hibernation will shutdown regulators which are not in the keep list of the mentioned Reg 17h-4 writing and are part of the power-up sequence.
Enter via SW
To enter hibernation mode the following settings have to be done:
- Enable just these IRQ sources which should lead to leave hibernation mode.
- Make sure that IRQ is inactive (IRQ flags get cleared by Reg 23h-26h readings.
- Set a delay for entering hibernation if needed (
are part of the power-up sequence.
AG
VDD27 chip supply is kept ON
still
Note that hibernation will shutdown regulators which are not in the keep list of the mentioned Reg 17h-4 writing and
Hibernation
Leave
9.3 Supervisor
All other regulators are switched OFF dependent on the KEEP-Bits
XRES goes active (can be disabled in the boot ROM) and PWRGOOD goes inactive
- IRQ activation or
- GPIO control
ams
This supervisor function can be used for automatic detection of VSUP brown out or junction over-temperature condition.
9.3.1 VSUP Supervision
The VSUP supervision has a selectable level. If the shutdown is not enabled an interrupt can be generated.
9.3.2 VDD27 Supervision
If VDD27 reaches the “programmed level of VDD27” -10% for typ. 3ms, the PMU shuts down automatically. If the shutdown is not enabled an interrupt can be generated.
9.3.3 Junction Temperature Supervision
The temperature supervision level can also be set by 5 bits (120 to –15ºC). If the temperature reaches this level, an interrupt can be generated.
The over-temperature shutdown level is always 20ºC higher. This shutdown can be disabled in Reg. 20h.
Technical
www.austriamicrosystems.com
Revision 1.03
27 - 70
AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s
9.4 Interrupt Generation
All interrupt sources can get enabled or disabled by corresponding bits in the 4 IRQ-bytes. By default no interrupt source is enabled.
The XIRQ pin can be configured to operate in push/pull (2 different driver strengths), open-drain mode or to be tri-state. The signal polarity can be defined as active-low or active-high. Default state is open-drain active-low.
9.4.1 IRQ Source Interpretation
There are 3 different modules to process interrupt sources:
LEVEL.
The IRQ output is kept active as long as the interrupt source is present and this IRQ-Bit is enabled.
EDGE.
The IRQ gets active with a high going edge of this source. The IRQ stays active until the corresponding IRQ-Register gets read.
STATUS CHANGE.
The IRQ gets active when the source-state changes. The change bit and the status can be read to notice which interrupt was the source. The IRQ stays active until the corresponding interrupt register gets read.De-bouncer
There is a de-bounce function implemented, a de-bounce time of 3ms is selected per default in the IRQ_ENRD_3 register (26h).
valid
9.4.2 Interrupt Sources
These IRQ events will activate the XIRQ pin:
10bit ADC end of conversion
Charger end of charge, connect/disconnect, no battery
Battery temperature high (at 45ºC or 50ºC with 100/10k
Ω
NTC)
Junction temperature high
still
Battery low (Brown-out voltage reached)
AG
Power-up key (pin PWRUP) pressed
Current sink low voltage
Power rail monitor: over-voltage CVDD1, CVDD2, CVDD3
content
Technical
www.austriamicrosystems.com
Revision 1.03
28 - 70
AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s
9.5 10-Bit ADC
This general purpose ADC can be used for measuring several voltages and currents to perform functions like battery monitor, temperature supervision, button press detection, etc.
9.5.1 Input Sources
Table 12. ADC10 Input Sources
#
0
Source
VSUP
Range
5.120V
LSB
5mV
Description
check main system supply voltage
1 GPIO3 5.120V
5mV
2
3
4
5
6
GPIO4
VBATSW
VUSB
BATTEMP
5.120V
5.120V
5.120V
5.120V
2.048V
5mV
5mV
5mV
5mV
2mV check battery voltage of 4V Li-Ion accumulator check USB/charger input voltage
Source defined by DC_TEST in register 18h check battery charging temperature
7
8
9
A
B
C
D
E
F
VBE_2µA
9.5.2 Parameter
Table 13. ADC10 Parameter
1.024
VDD27=2.7, T
A
= 25ºC, unless otherwise specified.
1mV
ams
reserved reserved
content
Condition Min Symbol
ADC
GPIO1
GPIO2
PWRUP
VBE_1µA
5.120V
5.120V
5.120V
1.024
Parameter
ADC Full Scale Range
5mV
5mV
5mV
2mV
2mV
1mV
AG
reserved reserved
still
Tj = (674 - ADC10<9:0>) / 2 measuring basis-emitter voltage of temperature sense transistor;
Tj = (694 - ADC10<9:0>) / 2
Typ Max
FS
2.16
Unit
V
valid
Conversion Time
T
CON
34 50 µs
Technical
www.austriamicrosystems.com
Revision 1.03
29 - 70
AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s
9.6 GPIO Pins
AS3607 features 4 GPIO pins, AS3606 has 2 GPIO pins.
If not re-configured in the start-up sequence GPIO1, GPIO3 and GPIO4 are input per default.GPIO2 is set to output and the pin is driven to low right at the beginning of the startup sequence. GPIO3/4 have one state defined as input and three states as output. The following table shows the different input/output options.
Table 14. GPIO Configuration
00
GPIO1
xCharging (1Hz pulses)
GPIO2
LOW
GPIO4/3
HiZ / HiZ (input)
01
10
11
When configured as input the following functionality is available:
ADC input, to measure external voltage sources
Wake-up input to return from hibernation
Hibernation enable input (GPIO1/2/3 only)
PWM dimming input (GPIO1/2/3 only)
Table 15. GPIO Output Functions
Function
xCharger_active xEOC xPWRUP
PWRGOOD xVSUP_low
HIGH xVSUP_low xPWRUP
PWRGOOD xCharging (1Hz pulses) xVSUP_low
HIGH xCharging (1Hz pulses)
xVSUP_low / xCharging (1Hz pulses)
xPWRUP / PWRGOOD xEOC / xCharger_active
valid still
Description
The output will be high when the charger is no active. The output toggles between high and low as long as the charging is on going. If EOC, a timeout or overtempertur event stops the charger the output stops toggling.
The output will be high when the charger is no active or in EOC; it will be low if the charger is active.
ams
The output will be high about 3ms after the start-up seuence is finished. It will be low during the sequence. Please be sure to configure the GPIO before the pull-up voltage, otherwise the output
The output will get low if the VSUP undervoltage level is reached.
The output will be high.
LOW The output will be low.
Please note that all GPIO pins are open-drain outputs. They can only output a logic “high” if a pull-up and the corresponding pull-up voltage is present.
Technical
www.austriamicrosystems.com
Revision 1.03
30 - 70
AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s
9.7 2-Wire-Serial Control Interface
There is an I2C slave block implemented to have access to 64 byte of setting information.
The I2C address is: Adr_Group8 - audio processors
8Ch_write
8Dh_read
9.7.1 Protocol
Table 16. 2-Wire Serial Symbol Definition
Symbol
S
Sr
DW
DR
WA
A
N reg_data data (n)
P
WA++
Figure 15. Byte Write
Definition
Start condition after stop
Repeated start
Device address for write
Device address for read
Word address
RW
R
R
R
R
R
Acknowledge
No Acknowledge
Register data/write
Register data/read
Stop condition
Increment word address internally
AS3606 AS3607 (=slave) receives data
AG
R
R
W
R
R
W
AS3606 AS3607 (=slave) transmits data
ams
WA A reg_data A P S DW A
Note
1 bit
1 bit
1000 1100b (8Ch)
1000 1101b (8Dh)
8 bit
8 bit
8 bit
1 bit during acknowledge
valid
write register
WA++
Technical
www.austriamicrosystems.com
Revision 1.03
31 - 70
AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s
Figure 16. Page Write
A reg_data 1 A reg_data 2 A reg_data n A P S DW A WA ...
write register
WA++ write register
WA++ write register
WA++ write address is followed by the word address. After the word address any number of data bytes can be sent to the slave. The word address is incremented internally, in order to write subsequent data bytes on subsequent address locations.
Figure 17. Random Read
AG valid
Byte Write and Page Write formats are used to write data to the slave.
The transmission begins with the START condition, which is generated by the master when the bus is in IDLE state (the bus is free). The device-
still
followed by the device-read address, or simply with a new transmission START followed by the device-read address, when the bus is in IDLE state. The device-read address is always followed by the 1st register byte transmitted from the slave. In Read Mode any number of subsequent
S DW Sr DR
WA++ data P
Random Read and Sequential Read are combined formats. The repeated START condition is used to change the direction after the data transfer from the master.
The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START condition is followed by the device-write address and the word address.
In order to change the data direction a repeated START condition is issued on the 1st SCL pulse after the acknowledge bit of the word address transfer. After the reception of the device-read address, the slave becomes the transmitter. In this state the slave transmits register data located by the previous received word address vector. The master responds to the data byte with a not-acknowledge, and issues a STOP condition on the bus.
Technical
www.austriamicrosystems.com
Revision 1.03
32 - 70
AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s
Figure 18. Sequential Read
S DW A WA A Sr DR A read register
WA++ data A reg_data 2 read register
WA++
A read register
WA++
...
reg_data n N P
Random Read, for a sequential read the transferred register-data bytes are responded by an acknowledge from the master. The number of data bytes transferred in one sequence is unlimited (consider the behavior of the word-address counter). To terminate the transmission the master has to send a not-acknowledge following the last data byte and generate the STOP condition subsequently.
Figure 19. Current Address Read
S DR A read register
WA++ data
WA++
A read register reg_data 2
AG
read register
WA++
...
reg_data n N P
still
The bus is idle and the master issues a START condition followed by the Device-Read address. Analogous to Random Read, a single byte
content
Technical
www.austriamicrosystems.com
Revision 1.03
33 - 70
AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s
9.7.2 Parameter
Figure 20. 2-Wire Serial Timing
T
HD
T
L
TS T
SU
T
H
T
PD
V
CSH
T
H
T
SU
CSDA
CSCL
1-7
Start
Condition
Address R/W
DVDD =2.9V, T amb
=25ºC, unless otherwise specified.
Table 17. 2-Wire Serial Parameter
Symbol
V
CSL
HYST
V
OL
Tsp
T
L
Parameter
CSCL, CSDA Low Input Level
9
ACK
1-7
Data
9
ACK
AG
Condition
(max 30%DVDD)
1-7
Data
CSCL, CSDA High Input Level
CSCL, CSDA Input Hysteresis
CSDA Low Output Level
Spike insensitivity
Clock high time
Clock low time
CSCL, CSDA (min 70%DVDD)
ams
at 3mA
content
CSDA has to change Tsetup before rising edge of CSCL
2.03
200
-
50
500
500
250
Min
0
9
ACK Stop
Condition
still valid
Typ
450
100
-
-
-
-
Max
0.87
5.5
800
0.4
-
-
Unit
V
V mV
V ns ns ns ns
No hold time needed for CSDA relative to rising edge of CSCL
T
HD
0 ns
TS
CSDA H hold time relative to CSDA edge for start/stop/rep_start
CSDA prop delay relative to lowgoing edge of
CSCL
200 ns
T
PD
50 ns
Technical
www.austriamicrosystems.com
Revision 1.03
34 - 70
10 Register Definition
Table 18. I2C Register Overview
Addr
PMU Register
Name
17h-1 CVDD1
17h-2 CVDD2
17h-3 CVDD3
17h-4 Hibernation
17h-5 DCDC_Cntr
17h-7 GPIO_Cntr
18h-1 PVDD1
18h-2 PVDD2
18h-3 PVDD3
b7 b6 b5 b4 b3 b2 b1 b0
-
0: Cext=10µF
1: Cext=22µF
0: Cext=10µF
1: Cext=22µF
0: Cext=10µF
1: Cext=22µF
0: pulse skip on
1: pulse skip off
0 … OFF
0x01 – 0x40: 0.6V + VSEL * 12.5mV -> (0.6125V – 1.400V)
0x41 – 0x70: 1.4V + (VSEL-0x40) * 25mV ->(1.425V – 2.600V)
0x71 – 0x7F: 2.6V + (VSEL-0x70) * 50mV -> (2.650V – 3.350V)
0 … OFF
0x01 – 0x40: 0.6V + VSEL * 12.5mV -> (0.6125V – 1.400V)
0x41 – 0x70: 1.4V + (VSEL-0x40) * 25mV ->(1.425V – 2.600V)
0x71 – 0x7F: 2.6V + (VSEL-0x70) * 50mV -> (2.650V – 3.350V)
0 … OFF
0x01 – 0x40: 0.6V + VSEL * 12.5mV -> (0.6125V – 1.400V)
AG
0x71 – 0x7F: 2.6V + (VSEL-0x70) * 50mV -> (2.650V – 3.350V)
KEEP_PVDD4 KEEP_PVDD3 KEEP_PVDD2 KEEP_PVDD1
0: pulse skip on
1: pulse skip off
0: HiZ/HiZ; 1: xVSUP_low/xCharging;
2: xPWRUP/PWRGOOD;
3: xEOC/xCharger_active
1: HiZ
0: 2MHz
1: 1MHz
ams
0: opend drain
0: immediate;
1: 42µs/step;
1: 1MHz
2: 166µs/step;
3: 666µs/step
2: HIGH; 3: xCharging
0: HiZ
1: opend drain
still valid
0: immediate;
1: 42µs/step;
2: 166µs/step;
3: 666µs/step
0: xCharging; 1: xVSUP_low;
2: xPWRUP; 3: PWRGOOD
0: 150mA
1: 250mA
0: 150mA
1: 250mA
0: 150mA
1: 250mA
0: normal mode
1: low power mode
0: normal mode
1: low power mode
0: normal mode
1: low power mode
0x00 – 0x0F: 1.2V + VSEL * 50mV
→
(1.2V – 1.95V)
0x10 – 0x1F: 2.0V + (VSEL-0x10) * 100mV
→
(2.0V – 3.5V)
0x00 – 0x0F: 1.2V + VSEL * 50mV
→
(1.2V – 1.95V)
0x10 – 0x1F: 2.0V + (VSEL-0x10) * 100mV
→
(2.0V – 3.5V)
0x00 – 0x0F: 1.2V + VSEL * 50mV
→
(1.2V – 1.95V)
0x10 – 0x1F: 2.0V + (VSEL-0x10) * 100mV
→
(2.0V – 3.5V)
Technical
Table 18. I2C Register Overview
Addr Name
18h-4 PVDD4
18h-5 VDD27
19h-0 CHG_Cntr
19h-1 CHG_VCntr
19h-2 CHG_ICntr
19h-3 CHG_Conf
19h-4 CHG_NTC
19h-5 CHG_TIME
19h-6 CHG_STAT1
19h-7 CHG_STAT2
1Ah-1 Out_Cntr
1Ah-2 Clk_Cntr
1Bh-1 Boost_Cntr1
1Bh-2 Boost_Cntr2
b7 b6
0: 150mA
1: 250mA
b5
0: normal mode
1: low power mode
b1 b0
b4 b3 b2
0x00 – 0x0F: 1.2V + VSEL * 50mV
→
(1.2V – 1.95V)
0x10 – 0x1F: 2.0V + (VSEL-0x10) * 100mV
→
(2.0V – 3.5V)
-
-
-
0: boot ROM
1:register defined
0: 100mA
1: 200mA
-
0x0 – 0x2: 2.3V
0x3 – 0xF: 2.0V + VSEL* 100mV
→
(2.3V – 3.5V)
0: 94mA; 1: 141mA; 2: 189mA; 3: 237mA; 4: 285mA; 5: 332mA; 6: 380mA; 7:
428mA; 8: 470mA; 9: 517mA; A: 599mA; B: 760mA; C: 882mA; D: 1060mA;
valid
E-F: not defined
-
0: 3.85V; 1: 3.9V; 2: 3.95V; 3: 4.0V;
4: 4.05V; 5: 4.1V; 6:4.15V; 7: 4.2V
0: 3.9V; 1: 3.6V;
0: 94mA; 1: 141mA; 2: 189mA; 3: 237mA; 4: 285mA; 5: 332mA; 6: 380mA; 7:
428mA; 8: 470mA; 9: 517mA; A: 599mA; B: 760mA; C: 882mA; D: 1060mA;
E-F: not defined
2: 4.2V; 3: 4.5V
0: 8%; 1: 15%;
AG
still
8: 118mA; 9: 129mA; A: 150mA; B: 190mA; C: 221mA; D: 265mA; E-F: not defined
0: 4.3V; 1: 4.4V; 2: 4.5V; 3: 4.6V;
2: 10%; 3: 20%
ams
0:disabled; 1: 0.5h; 2: 1h; 3: 1,5h; 4: 2h; 5: 2.5h; 6: 3h; 7: 3.5h;
4: 4.7V; 5: 4.8V; 6: 4.9V; 7: 5.0V
0: 55°C; 1: 45°C
0: 6mA OD; 1: 6mA PP;
0: 100k; 1: 10K;
0: XIRQ; 1: CLKINT1; 0: 0ms; 1: 8ms;
2: 16ms; 3: 32ms 2: 1mA PP; 3: HiZ 2: CLKINT2; 3: IRQ
0: LOW; 1: CLK1Hz (charger);
2: do not use; 3: HIGH
-
0: 2MHz; 1: 1MHz;
2: 1kHz; 3: 125Hz
0: tbd
1: tbd
0x00 - 0x1F: 1µA * SU_IFB;
Technical
0: LOW; 1: GPIO1;
2: GPIO2; 3: GPIO3
0: no dimm; 1: CURR1;
2: CURR2; 3: GPIO1/2/3
-
Table 18. I2C Register Overview
2Fh
2Eh
Addr Name b5 b4 b3 b2 b1 b0
1Bh-3 CURR1
b7
0x00 - 0xFF: 150µA * ICURR;
b6
1Bh-4 CURR2
1Ch
System Register
20h
21h
22h
23h
24h
25h
26h
PMU_Enable
SYSTEM
SUPERVISOR1
0: open; 1: PVDD1; 2: PVDD2;
3: PVDD3; 4: PVDD4; 5: VDD27;
6: CVDD1; 7: CVDD2; 8: CVDD3;
9-F: not defined
0: XRES; 1: -;
2: SD; 3: SD
SUPERVISOR2 -
IRQENRD_0
IRQENRD_1
IRQENRD_2
IRQENRD_3
0x00 - 0xFF: 150µA * ICURR;
-
0: 8s;
1: 4s
SubRegister addresses for registers:
0x17: DCDC regulators
0x18: LDOs regulators
0x19: Charger
valid
0x1A: IO_clock_control
-
AG
0x1B: BackLight_DCDC
→
VSUPlow_SD_ON VSUPlow_SUP<2:0>
→
(140ºC...5ºC)
(120ºC...-15ºC)
-
-
CHG_TEMP_IRQ CHG_EOC_IRQ CHG_NoBAT_IRQ CHG_DET_IRQ -
ams
0: 3ms; 1: off;
ADC10_0
0: VSUP; 1: GPIO3; 2: GPIO4; 3: VSUPSW; 4: VUSB
5: DC_TEST; 6: BATTEMP; 7: GPIO1; 8: GPIO2; 9: PWRUP; A,B: -;
C: VBE_1µA; D: VBE_2µA; E,F: -
-
ADC10_1
Technical
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Bit
7
6:0
Table 20. CVDD2 Register
Name
CVDD2
Bit
7
6:0
Table 19. CVDD1 Register
Name
CVDD1
Offset: 17h-1
Bit Name
CVDD1_fast
VSEL_CVDD1<6:0>
Offset: 17h-2
Bit Name
CVDD2_fast
VSEL_CVDD2<6:0>
Base
2-wire serial
Default
00h
CVDD1 DC/DC Buck Regulator Control Register
This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Default Access Bit Description
0
000000
R/W
R/W
Selects a faster regulation mode for CVDD1 suitable for larger load changes.
0: normal mode, Cext=10µF
1: fast mode, Cext=22µF required
The voltage select bits set the DC/DC output voltage level and power the
DC/DC converter down.
00h: DC/DC powered down
01h-40h: CVDD1=0.6V+VSEL_CVDD1*12.5mV
valid
41h-70h: CVDD1=1.4V+(VSEL_CVDD1-40h)*25mV
71h-7Fh: CVDD1=2.6V+(VSEL_CVDD1-70h)*50mV
Base
AG
CVDD2 DC/DC Buck Regulator Control Register still
00h
This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Default
0
Access ams
Bit Description
000000 R/W
0: normal mode, Cext=10µF
1: fast mode, Cext=22µF required
content
01h-40h: CVDD1=0.6V+VSEL_CVDD1*12.5mV
41h-70h: CVDD1=1.4V+(VSEL_CVDD1-40h)*25mV
71h-7Fh: CVDD1=2.6V+(VSEL_CVDD1-70h)*50mV
Technical
www.austriamicrosystems.com
Revision 1.03
38 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 21. CVDD3 Register
Name
CVDD3
Bit
7
6:0
Offset: 17h-3
VSEL_CVDD3<6:0>
Table 22. Hibernation Register
Name
Hibernation
Bit
7
6
5
4
3
2
1
0
Bit Name
CVDD3_fast
Offset: 17h-4
Bit Name
-
KEEP_PVDD4
KEEP_PVDD3
KEEP_PVDD2
KEEP_PVDD1
KEEP_CVDD3
KEEP_CVDD2
Base
2-wire serial
Default
00h
CVDD3 DC/DC Buck Regulator Control Register
This is an extended register and needs to be enabled by writing 011b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Default Access Bit Description
0 R/W Selects a faster regulation mode for CVDD3 suitable for larger load changes.
000000 R/W
0: normal mode, Cext=10uF
1: fast mode, Cext=22uF required
The voltage select bits set the DC/DC output voltage level and power the
DC/DC converter down.
00h: DC/DC powered down
01h-40h: CVDD1=0.6V+VSEL_CVDD1*12.5mV
valid
41h-70h: CVDD1=1.4V+(VSEL_CVDD1-40h)*25mV
71h-7Fh: CVDD1=2.6V+(VSEL_CVDD1-70h)*50mV
Base
AG still
This is an extended register and needs to be enabled by writing 100b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input. This register MUST NOT be read back!!!
0
Bit Description Default
0
0
0
Access ams
W
Keeps the programmed PVDD4 level during hibernation.
0: power down PVDD4 content
Keeps the programmed PVDD2 level during hibernation.
W
0: power down PVDD2
1: keep PVDD2
0 W
0
0
0
W
W
W
Keeps the programmed PVDD1 level during hibernation.
0: power down PVDD1
1: keep PVDD1
Keeps the programmed CVDD3 level during hibernation.
0: power down CVDD3
1: keep CVDD3
Keeps the programmed CVDD2 level during hibernation.
0: power down CVDD2
1: keep CVDD2
Keeps the programmed CVDD1 level during hibernation.
0: power down CVDD1
1: keep CVDD1 www.austriamicrosystems.com
Revision 1.03
39 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 23. DCDC_Cntr Register
Name
DCDC_Cntr
Bit
7
6
5
4
3:2
1:0
Offset: 17h-5
Bit Name
CFM_CVDD23_OFF
CFM_CVDD1_OFF
CVDD23_FREQ
CVDD1_FREQ
DVM_CVDD23<1:0>
DVM_CVDD1<1:0>
Base
2-wire serial
DC/DC Step Down Control Register
Default
00h
This is an extended register and needs to be enabled by writing 101b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Default
0
0
0
0
00
00
Access Bit Description
R/W
R/W
R/W
R/W
R/W
Disables pulse skip mode for DCDC2 and DCDC3
0: current force mode / pulse skip enabled
1: current force mode / pulse skip disable
Disables pulse skip mode for DCDC1
0: current force mode / pulse skip enabled
1: current force mode / pulse skip disable
Selects the switching frequency for DCDC2 and DCDC 3
0: 2MHz
1: 1MHz
Selects the switching frequency for DCDC1
0: 2MHz
1: 1MHz
AG
00: immediate change of the output voltage
01: 32µs/step
still valid
R/W
10: 128µs/step
11: 512µs/step
Configures the dynamic voltage management (output voltage slope) for
CVDD1
00: immediate change of the output voltage
01: 32µs/step
10: 128µs/step
11: 512µs/step
Technical
www.austriamicrosystems.com
Revision 1.03
40 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 24. GPIO_Cntr Register
Name
GPIO_Cntr
Bit
7:6
5
4:3
2
1:0
Table 25. PVDD1 Register
Name
PVDD1
Bit
7
6
5
4:0
Offset: 17h-7
Bit Name
MUX_GPIO43<1:0>
DRIVE_GPIO2
MUX_GPIO2<1:0>
DRIVE_GPIO1
MUX_GPIO1<1:0>
Offset: 18h-1
Bit Name
PVDD1_ON
ILIM_H_PVDD1
VSEL_PVDD1<4:0>
Base
2-wire serial
Default
00h
GPIO Control Register
This is an extended register and needs to be enabled by writing 111b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Default
00
0
00
0
Access
R/W
R/W
R/W
R/W
Bit Description
Configures GPIO4 and GPIO3
00: HiZ / HiZ (GPIOs are inputs)
01: xVSUP_low / xCharging
10: xPWRUP / PWRGOOD
11: xEOC / xCharger_active
Configures GPIO2 as input or output
0: open drain (output)
1: HiZ (input)
Configures GPIO2 output mode
00: LOW
10: HIGH
11: xCharging
AG
0: HiZ (input)
1: open drain (output)
still valid
00 R/W Configures GPIO1 output mode
00: xCharging ams
2-wire serial
PVDD1 Control Register
Default
00h
This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Default
0
0
0
00000
Access
R/W
R/W
R/W
R/W
Bit Description
Enables PVDD1 regulator
0: PVDD1 switched off
1: PVDD1 switched on
Selects the higher current limit for PVDD1
0: default mode, 150mA
1: 250mA mode
Selects the low power mode for PVDD1
0: PVDD1 is in normal operation
1: PVDD1 supply current is reduced
Sets the LDO output voltage in register control mode (default voltage of the regulator is selected by boot ROM
0x00-0x0F: 1.2V+VSEL*50mV
→
(1.2V - 1.95V)
0x10-0x1F: 2.0V + (VSEL-0x10)*100mV → (2.0V-3.5V) www.austriamicrosystems.com
Revision 1.03
41 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 26. PVDD2 Register
Offset: 18h-2
Name
PVDD2
Base
2-wire serial
Default
00h
PVDD2 Control Register
This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
7
6
5
4:0
Bit
7
6
5
4:0
Bit Name
PVDD2_ON
ILIM_H_PVDD2
LP_PVDD2
VSEL_PVDD2<4:0>
Table 27. PVDD3 Register
Offset: 18h-3
Name
PVDD3
Bit Name
PVDD3_ON
ILIM_H_PVDD3
LP_PVDD3
VSEL_PVDD3<4:0>
Default Access Bit Description
0
0
0
00000
R/W
R/W
R/W
R/W
Enables PVDD2 regulator
0: PVDD2 switched off
1: PVDD2 switched on
Selects the higher current limit for PVDD2
0: default mode, 150mA
1: 250mA mode
1: PVDD2 supply current is reduced
0x00-0x0F: 1.2V+VSEL*50mV
→
(1.2V - 1.95V)
Base
AG
Default valid
Selects the low power mode for PVDD2
0: PVDD2 is in normal operation
Sets the LDO output voltage in register control mode (default voltage of the regulator is selected by the boot ROM
still
0x10-0x1F: 2.0V + (VSEL-0x10)*100mV
→
(2.0V-3.5V)
ams
2-wire serial
PVDD3 Control Register
00h
This is an extended register and needs to be enabled by writing 011b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Default Access
R/W Enables PVDD3 regulator 0
0: PVDD1 switched off
1: PVDD1 switched on
0 R/W
0
00000
R/W
R/W
Selects the higher current limit for PVDD3
0: default mode, 150mA
1: 250mA mode
Selects the low power mode for PVDD3
0: PVDD3 is in normal operation
1: PVDD3 supply current is reduced
Sets the LDO output voltage in register control mode (default voltage of the regulator is selected by the boot ROM
0x00-0x0F: 1.2V+VSEL*50mV
→
(1.2V - 1.95V)
0x10-0x1F: 2.0V + (VSEL-0x10)*100mV
→
(2.0V-3.5V)
Technical
www.austriamicrosystems.com
Revision 1.03
42 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 28. PVDD4 Register
Offset: 18h-4
Name
PVDD4
Base
2-wire serial
Default
00h
PVDD4 Control Register
This is an extended register and needs to be enabled by writing 100b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
7
6
5
4:0
Table 29. VDD27 Register
Bit
7
6
5
5
3:0
Bit Name
PVDD4_ON
ILIM_H_PVDD4
LP_PVDD4
VSEL_PVDD4<4:0>
Offset: 18h-5
Name
VDD27
Bit Name
PRG_VDD27
ILIM_H_VDD27
LP_VDD27
-
VSEL_VDD27<3:0>
Default Access Bit Description
0
0
0
00000
R/W
R/W
R/W
R/W
Enables PVDD4 regulator
0: PVDD4 switched off
1: PVDD4 switched on
Selects the higher current limit for PVDD4
0: default mode, 150mA
1: 250mA mode
1: PVDD4 supply current is reduced
0x00-0x0F: 1.2V+VSEL*50mV
→
(1.2V - 1.95V)
Base
AG
Default valid
Selects the low power mode for PVDD4
0: PVDD4 is in normal operation
Sets the LDO output voltage in register control mode (default voltage of the regulator is selected by the boot ROM
still
0x10-0x1F: 2.0V + (VSEL-0x10)*100mV
→
(2.0V-3.5V)
ams
2-wire serial
VDD27 Control Register
00h
This is an extended register and needs to be enabled by writing 101b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Default Access
n/a Selects the output voltage control mode for VDD27 0
0:VDD27 is in default mode
1: VDD27 is register controlled (Reg. 18-5h)
0 R/W
0 R/W
Selects the higher current limit for VDD27
0: default mode, 100mA
1: 200mA mode
Selects the low power mode for VDD27
0: VDD27 is in normal operation
1: VDD27 supply current is reduced
0
0000 n/a
R/W Sets the LDO output voltage in register control mode (default voltage of the regulator is 2.7V)
0x0-0x2: 2.3V
0x3-0xF: 2.0V + VSEL*100mV
→
(2.3V-3.5V)
Technical
www.austriamicrosystems.com
Revision 1.03
43 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 30. CHG_Cntr Register
Name
CHG_Cntr
Bit
7
6
5
4:1
0
Offset: 19h-0
Bit Name
BAT_DET_OFF
AUTO_RESUME
BAT_CHARGE_ON
USB_CURRLIM
<3:0>
USB_PREREG_ON
Base
2-wire serial
Default
C9h
Charger Control Register
This is an extended register but does not need to be enabled as Reg. 1Ch is 000b per default.
This register is reset at a VDD27-POR or XRES input.
Default Access Bit Description
1
1
1
0
1000
R/W
R/W
R/W
R/W
Disables the battery detection
0: Battery detection switched on
1: Battery detection switched off
Defines the behavior after end of charge (EOC)
0: auto resume is disabled
1: auto resume enabled, charger will start charging when VBATSW drops below the resume level
Enables the battery charging
0: VSUP is supplied via USB pre-regulator, but the battery switch is open
1: normal battery charging operation from USB pre-regulator
0x1: 141mA
AG
0x2: 189mA
0x3: 237mA
still valid
0x4: 285mA
0x5: 332mA
ams
0xB: 760mA
0xC: 882mA
0xD: 1060mA
0xE, 0xF: do not use
R/W Enables the USB pre-regulator and current limiter
0: USB pre-regulator is switched off
1: USB pre-regulator supplies VSUP from VUSB input
Technical
www.austriamicrosystems.com
Revision 1.03
44 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 31. CHG_VCntr Register
Name
CHG_VCntr
Bit
7:5
4:3
2:0
Offset: 19h-1
Bit Name
CHG_V_RESUME
<2:0>
VSUP_MIN<1:0>
CHG_V_EOC
<2:0>
Base
2-wire serial
Default
36h
Charger Voltage Control Register
This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Default
001
10
110
R/W
R/W
Bit Description Access
R/W Sets the charger auto resume voltage threshold
000: 3.85V
001: 3.90V
010: 3.95V
011: 4.00V
100: 4.05V
101: 4.10V
110: 4.15V
111: 4.20V
Defines the minimum VSUP voltage during trickle or constant current charging. The charging current will be reduced if VSUP would drop below this threshold.
00: 3.9V
01: 3.6V
10: 4.2V
11: 4.5V
AG
Sets the charger end of charge voltage threshold
still valid
000: 3.90V
001: 3.95V
011: 4.05V
100: 4.10V
content
Technical
www.austriamicrosystems.com
Revision 1.03
45 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 32. CHG_ICntr Register
Name
CHG_VCntr
Bit
7:4
3:0
Offset: 19h-2
Bit Name
CHG_I_CONSTANT
<3:0>
CHG_I_TRICKLE
<3:0>
Base
2-wire serial
Default
21h
Charger Current Control Register
This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Default Access Bit Description
0010 R/W
0001 R/W
Sets the current during constant current charging
0x0: 94mA
0x1: 141mA
0x2: 189mA
0x3: 237mA
0x4: 285mA
0x5: 332mA
0x6: 380mA
0x7: 428mA
0x8: 470mA
0x9: 517mA
0xA: 599mA
0xB: 760mA
0xC: 882mA
0xD: 1060mA
AG
0xE, 0xF: do not use
Sets the current during constant current charging
still valid
0x0: 24mA
0x1: 35mA ams
0x6: 95mA
0x7: 107mA
0x9: 129mA
0xA: 150mA
0xB: 190mA
0xC: 221mA
0xD: 265mA
0xE, 0xF: do not use
Technical
www.austriamicrosystems.com
Revision 1.03
46 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 33. CHG_Config Register
Name
CHG_Config
Bit
7:5
4:3
2:0
Offset: 19h-3
Bit Name
-
CHG_I_EOC<1:0>
VSUP_EOC
<2:0>
Base
2-wire serial
Default
15h
Charger Configuration Register
This is an extended register and needs to be enabled by writing 011b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Default
000
10
Access
n/a
R/W
Bit Description
101 R/W
Configures the end of charge current threshold. Charging will be stopped if the current drops below the threshold.
00: 8% of constant current setting
01: 15%
valid
10: 10%
11: 20%
Defines VSUP voltage after EOC and isolated battery.
000: 4.3V
001: 4.4V
010: 4.5V
011: 4.6V
100: 4.7V
101: 4.8V
110: 4.9V
111: 5.0V
AG still
Table 34. CHG_NTC Register
Bit
7:3
2
1
0
Name
CHG_NTC
Offset: 19h-4
Bit Name
-
NTC_MODE
NTC_10K
NTC_ON
Default ams
Access
Base
2-wire serial
Charger NTC Control Register content
Default
01h
This is an extended register and needs to be enabled by writing 100b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
0000 0 n/a
0 R/W
0
1
R/W
R/W
Defines the temperature level for the battery temperature supervisor to stop charging. (for beta of NTC = 4250)
0: 55ºC
1: 45ºC
Defines the type of NTC used for battery temperature supervisor.
0: 100k
Ω
1: 10k
Ω
Enables the battery temperature supervisor via NTC resistor.
0: NTC battery temp supervision disabled
1: NTC battery temp supervision enabled
Technical
www.austriamicrosystems.com
Revision 1.03
47 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 35. CHG_TIME Register
Name
CHG_TIME
Bit
7:5
4
3:0
Offset: 19h-5
Bit Name
-
TMAX_TIMER
Table 36. CHG_STAT1 Register
Name
CHG_STAT1
Bit
7
6
5
CHG_TIMEOUT
<3:0>
Offset: 19h-6
Bit Name
NO_BAT
EOC
Base
2-wire serial
Default
07h
Charger Time Control Register
This is an extended register and needs to be enabled by writing 101b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Default Access Bit Description
0000 0
0
0111 n/a
R
W
R/W
0: -
Returns the time-out supervision status
0: no time-out reached
1: charger time-out reached, charging stopped
Resets the charger time supervision
1: resets time-out counter
Sets the current during constant current charging
0x0: charger timer disabled
0x1: 0.5h
0x2: 1h
0x3: 1.5h
0x4: 2h
0x5: 2.5h
0x6: 3h
AG still valid
0x7: 3.5h
0x8: 4h
0x9: 4.5h
ams
0xE: 7h
0xF: 7.5h
Base Default
2-wire serial xxh
Charger Status Register 1
This is an extended register and needs to be enabled by writing 110b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Default
x x x
Access
R
R
R
Bit Description
Status if a battery is detected to the system, by measuring the NTC value on
BATTEMP pin.
0: battery detected
1: no battery detected
Only valid if a charger is deducted.
0: battery temperature o.k.
1: battery temperature higher 55ºC/45ºC (seed
0: end of charge not reached. Bit is cleared automatically if
entered
is cleared or resume state is
1: end of charge reached www.austriamicrosystems.com
Revision 1.03
48 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 36. CHG_STAT1 Register
Name
CHG_STAT1
2
1
0
Bit
4
3
Bit Name
CV
TRICKLE
RESUME
CC
CHG_DET
Table 37. CHG_STAT2 Register
Name
CHG_STAT2
Bit
7:3
1:0
Offset: 19h-6
Offset: 19h-7
Bit Name
-
BATSW_MODE
<1:0>
Base
2-wire serial
Default xxh
Charger Status Register 1
This is an extended register and needs to be enabled by writing 110b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Default Access Bit Description
x x x x x
R
R
R
R
R
1: if charger is in constant voltage (top-off charge) mode
1: if charger is in trickle charging mode
1: if VBATSW dropped below resume threshold
1: if charger is in constant current charging mode
1: if a charger adapter is detected on VUSB pin
valid
Base
x
Default Access
2-wire serial
Charger Status Register 2
AG
Bit Description
xxxx xx n/a
R Shows the battery switch operation mode
00: battery switch open, no ideal diode operation (just for charger start-up)
01: battery switch open, ideal diode operation (charger connected but EOC
11: battery switch closed (charger disconnected)
content
Technical
www.austriamicrosystems.com
Revision 1.03
49 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 38. Out_Cntr Register
Bit
7
6
5:4
3:2
1:0
Bit
7:6
5:4
Name
Out_Cntr
Offset: 1Ah-1
Bit Name
DCDC23_1.4A
GPIO_HBN_ON
HBN_DELAY<1:0>
DRIVE_XIRQ<1:0>
MUX_XIRQ<1:0>
Table 39. Clk_Cntr Register
Name
Clk_Cntr
Offset: 1Ah-2
Bit Name
CLKINT2<1:0>
Base
2-wire serial
Default
00h
DCDC mode and XIRQ Output Control Register
This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Default Access Bit Description
0
0
00
00
00
R/W
R/W
R/W
R/W
Combines DCDC2 and DCDC3 to one regulator for 1.4A output currents
0: DCDC2 and DCDC3 working independent
1: DCDC2 & DCDC3 combined for 1.4A (DCDC3 registers have no effect)
0: Hibernation enable via GPIOs disabled
1: Hibernation enalbe via GPIOs enabled
valid
Sets the delay time for going into hibernation after writing to register 17-4h
00: 0ms
01: 8ms
10: 16ms
11: 32ms
AG
01: 6mA push-pull output
10: 1mA push-pull output
still
R/W
11: HiZ, tri-state
Multiplexes various digital signals to the XIRQ output pin
ams
2-wire serial
Default
00h
Clock Control Register
This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Default
00
Access
R/W
Technical
Bit Description
Selects the CLKINT2 input source. Note, this is an internal clock, which can be multiplexed to the XRES output.
00: LOW, drives the signal to logic “0”
01: CLK1Hz charger
10: do not use
11: HIGH, drives the signal to logic “1”
Selects the CLKINT1 frequency. Note, this is an internal clock, which can be multiplexed to XIRQ output.
00: 2MHz
01: 1MHz
10: 1kHz
11: 125Hz www.austriamicrosystems.com
Revision 1.03
50 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 39. Clk_Cntr Register
Name
Clk_Cntr
Offset: 1Ah-2
Bit Bit Name
3:2 GPIO_DIMM_HBN_SEL
<1:0>
1:0 -
Base
2-wire serial
Default
00h
Clock Control Register
This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Default
00
Access
R/W
Bit Description
Selects input for external dimming or hibernation control
00: disable dimming or hibernation via GPIO
01: GPIO1
10: GPIO2
11: GPIO3
00 n/a
valid
Table 40. BOOST_Cntr1 Register
Bit
7
6
5
4:3
2
1
0
Name
BOOST_Cntr1
Offset: 1Bh-1
Bit Name
SU_ON
-
SU_SLOWDIM
SU_EXTDIM<1:0>
Base
2-wire serial
AG
00h
Default Access Bit Description
0
0
0
R/W n/a
R/W
Enables the DCDC step-up regulator
0: SU switched off
1: SU switched on (will be reset if VFB exceeds the maximum and the current drops to zero)
Selects the DCDC step-up regulator external dimming mode
0: for dimming frequencies <1kHz
1: for dimming frequencies >1kHz
00 R/W
SU_OVP_OFF 0 R/W
Selects the DCDC step-up external PWM dimming input
00: no ext. dimming
01: CURR1 controlled
10: CURR2 controlled
11: GPIO1/2/3 controlled (selected via
)
Disables the DCDC step-up over-voltage protection
0: SU OVP switched on
1: SU OVP switched off
SU_CURR_FB 0 R/W
SU_FASTSKIP 0 R/W
Technical
Selects the DCDC step-up feedback mode
0: voltage FB via pin FBSU
1: current feedback via CURR1 or CURR2 (automatic select)
Defines the DCDC step-up regulator output voltage at low loads, when pulse skipping is active
0: Accurate output voltage, more ripple
1: Elevated output voltage, less ripple www.austriamicrosystems.com
Revision 1.03
51 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Bit
7:3
2
1
0
Table 41. BOOST_Cntr2 Register
Name
BOOST_Cntr2
Offset: 1Bh-2
Base
2-wire serial
Default
00h
DCDC step-up Control Register 2
This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit Name
SU_IFB<4:0>
Default
0 0000
Access
R/W
SU_CURRLIM
SU_GAIN
SU_FREQ
0
0
00
R/W
R/W
R/W
Bit Description
Defines the tuning current at pin FBSU.
0x00: 0µA
0x01: 1µA
0x02: 2µA
...
0x1F: 31µA
Selects the DCDC step-up converter coil current limit
0: normal current limit
1: current limit increased by about 50%
DCDC step-up converter feedback gain is selected automatically depending on current or voltage feedback mode. Setting this bit to “1” will choose the alternative feedback gain setting.
Defines the DCDC step-up switching frequency
0: 1MHz still valid
1: 500kHz
Table 42. CURR1 Register
Name
CURR1
Bit
7:0
Offset: 1Bh-3
Bit Name
ICURR1<7:0>
ams
Base
2-wire serial
Default
This is an extended register and needs to be enabled by writing 011b to Reg. 1Ch first.
00h
This register is reset at a VDD27-POR or XRES input.
Default
0x00
Access
R/W
Bit Description
Sets the current for current sink 1 in 255 steps with 140.626µA stepsize
0x00: Current sink 1 switched off
0x01: 0.15 mA
0x02: 0.30 mA
0x03: 0.45 mA
..
0xFE: 38,10 mA
0xFF: 38.25 mA
Technical
www.austriamicrosystems.com
Revision 1.03
52 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 43. CURR2 Register
Name
CURR2
Bit
7:0
Offset: 1Bh-4
Bit Name
ICURR2<7:0>
Base
2-wire serial
Default
00h
Current Sink 2 Register
This is an extended register and needs to be enabled by writing 100b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Default
0x00
Access
R/W
Bit Description
Sets the current for current sink 2 in 255 steps with 140.626µA stepsize
0x00: Current sink 2 switched off
0x01: 0.141 mA
0x02: 0.281 mA
0x03: 0.422 mA
..
0xFE: 35,72 mA
valid
0xFF: 35.86 mA
Table 44. PMU_Enable Register
Bit
7:4
3
2:0
Offset: 1Ch
Name
PMU_Enable
Bit Name
DC_TEST_MUX
<3:0>
PMU_GATE
PMU_ENABLE
Base
AG
00h
sets the ADC10 multiplexer to measure various regulator voltages
This register is reset at a VDD27-POR or XRES input.
Bit Description Default
0000
Access ams
0x1: PVDD1
0x2: PVDD2
0x4: PVDD4
0x5: VDD27
0x6: CVDD1
0x7: CVDD2
0x8: CVDD3
0x9-0xF: n/a
0 R/W
000 R/W
<2:0>
Technical
Enables all settings made in registers 17h to 1Bh at once. If this bit is set, changes are activated as soon as they are written to the related register.
0: no change
1: change at once
Selects extended registers 17h to 1Bh for the next read or write. This register has to be set before every read or write even if the selection is not changing.
0: 19h-0 selected
1: 17h-1 to 1Bh-1 selected
2: 17h-2 to 1Bh-2 selected
...
7: 17h-7 to 1Bh-7 selected www.austriamicrosystems.com
Revision 1.03
53 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 45. SYSTEM Register
Offset: 20h
Name
SYSTEM
Base
2-wire serial
SYSTEM Register
This register is reset at a VDD27-POR or XRES input.
Default
51h
Bit
5
4:0
Bit Name
JTEMP_SUP<4:0>
Default
0
Access
R/W
Bit Description
7:4
3
2
1
0
Design_Version<3:0>
-
JTEMP_SUP_OFF
I2C_WD_ON
PWR_HOLD
Table 46. SUPERVISOR1 Register
Bit
7:6
Name
SUPERVISOR1
Offset: 21h
Bit Name
PWRUP_SD_XRES
<1:0>
0101
0
0
0
1
R n/a
R/W
R/W
R/W
Number to identify the design version
0101: for chip version 2v2
Junction temperature supervision (level can be set in register 21h)
0: temperature supervision enabled
1: temperature supervision disabled
2-wire serial interface watchdog
To reset the watchdog counter a 2-wire serial read operation has to be performed at least every 500ms. If the watchdog counter is not reset, the
PMU will be powered down.
0: watchdog is disabled
AG still valid
This register is reset at a VDD27-POR or XRES input.
Default
00
Access
R/W
Base
2-wire serial
SUPERVISOR Register 1
Default
00h
Applying a high signal on PWRUP pin for about 8s will
00: perform a reset cycle
01: have no effect
10: initiate a shut-down
11: initiate a shut-down
SD_XRES_TIME 0 R/W Halfs the time from pulling PWRUP high to XRES or SD
0: 8s
1: 4s
Sets the threshold for junction temperature emergency shutdown and junction temperature interrupt
Invoke shutdown at: JTemp_SD=140-JTEMP_Sup*5ºC
Invoke interrupt at: JTemp_IRQ=120-JTEMP_Sup*5ºC
Technical
JT_Sup IRQ Shutdown
00000
00001
.
.
11110
11111
120°C
115°C
.
.
-30°C
-35°C
140°C
135°C
.
.
-10°C
-15°C www.austriamicrosystems.com
Revision 1.03
54 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Bit
7:6
5
4
3:1
0
Table 47. SUPERVISOR2 Register
Name
SUPERVISOR2
Offset: 22h
Base
2-wire serial
SUPERVISOR Register 2
This register is reset at a VDD27-POR or XRES input.
Bit Description Bit Name
-
VDD27low_SD_OFF
Default
00
0
Access
n/a
R/W
VSUPlow_SD_ON
VSUPlow_SUP<2:0>
VSUPlow_SUP_OFF
0
000
0
R/W
R/W
R/W
Default
00h
0: VDD27low (VDD27 -10%) shut down enabled
1: VDD27low shut down disabled
0: VSUPlow shut down enabled
1: VSUPlow shut down disabled
Sets the threshold for VSUP supervisor
000: 2.7V
001: 2.9V
010: 3.1V
011: 3.2V
100: 3.3V
101: 3.4V
110: 3.5V
111: 3.6V
AG
1: VSUPlow supervision disabled
still valid
Technical
www.austriamicrosystems.com
Revision 1.03
55 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 48. First Interrupt Register
Name
IRQENRD_0
Bit
7
6
5
4
3
2
1:0
Offset: 23h
Bit Name
CVDD1_SD
CVDD1_under
CVDD1_IRQ
CVDD1_over
CVDD2_SD
CVDD2_under
CVDD2_IRQ
CVDD2_over
CVDD3_SD
CVDD3_under
CVDD3_IRQ
CVDD3_over
-
Base
2-wire serial
First Interrupt Register
Default
00h
Please be aware that writing to this register will enable/disable the corresponding interrupts, while reading gets the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a VDD27-POR or XRES input.
Default
0 x
0 x
0
Access
W
R
W
R
W
0: disable
1: enable
Bit Description
Invokes shut-down of the PMU when a –10% under-voltage spike at CVDD1 occurs
valid
This bit is set when a –5% under-voltage at CVDD1 occurs
Enables interrupt for over-voltage/under-voltage supervision of CVDD1
0: disable
1: enable
This bit is set when a +8% over-voltage at CVDD1 occurs
Invokes shut-down of the PMU when a –10% under-voltage spike at CVDD2 occurs
0: disable
1: enable
AG still
This bit is set when a –5% under-voltage at CVDD2 occurs x R
0 x
0 x
00 x
0
R n/a
R
W
W
R
W
Enables interrupt for over-voltage/under-voltage supervision of CVDD2
0: disable
This bit is set when a +8% over-voltage at CVDD2 occurs
content
This bit is set when a –5% under-voltage at CVDD3 occurs
Enables interrupt for over-voltage/under-voltage supervision of CVDD3
0: disable
1: enable
This bit is set when a +8% over-voltage at CVDD3 occurs
Technical
www.austriamicrosystems.com
Revision 1.03
56 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 49. Second Interrupt Register
Name
IRQENRD_1
Bit
7
6
5
4
3
2:0
Offset: 24h
Bit Name
PWRUP_IRQ
GPIO1_IRQ
GPIO2_IRQ
GPIO3_IRQ
GPIO4_IRQ
-
Base
2-wire serial
Second Interrupt Register
Default
00h
Please be aware that writing to this register will enable/disable the corresponding interrupts, while reading gets the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a VDD27-POR or XRES input.
Default
0 x
0 x
0 x
0 x
0
Access
W
R
W
R
W
0: disable
1: enable
Bit Description
Enables interrupt which is invoked whenever a high signal at the PWRUP input pin occurs
valid
This bit is set whenever a high level of min. VSUP/3 at the PWRUP input pin occurs (PWRUP pin is commonly connected to the power-up button)
Enables interrupt which is invoked whenever a high signal at the GPIO1 input pin occurs
0: disable
1: enable occurs
AG still
This bit is set whenever a high level of min. tbd at the GPIO1 input pin
Enables interrupt which is invoked whenever a high signal at the GPIO2 input pin occurs
0: disable
R
W
R
W
1: enable
This bit is set whenever a high level of min. tbd at the GPIO2 input pin occurs
Enables interrupt which is invoked whenever a high signal at the GPIO3
content
occurs
Enables interrupt which is invoked whenever a high signal at the GPIO4 input pin occurs
0: disable
1: enable x R This bit is set whenever a high level of min. tbd at the GPIO4 input pin occurs
000 n/a
Technical
www.austriamicrosystems.com
Revision 1.03
57 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 50. Third Interrupt Register
Name
IRQENRD_2
Base
2-wire serial
Third Interrupt Register
Default
00h
6
5
4
3
2
Bit
7
Offset: 25h
Bit Name
CHG_TEMP_IRQ
(status change)
CHG_TEMP
CHG_EOC_IRQ
(status change)
CHG_EOC
CHG_NoBAT_IRQ
(status change)
CHG_NoBat
CHG_DET_IRQ
(status change)
CHG_DET
-
ICURR_LV_IRQ
(level)
Please be aware that writing to this register will enable/disable the corresponding interrupts, while reading gets the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a VDD27-POR or XRES input.
Default
0 x
0 x
Access
W
R
W
R
Battery over-temperature interrupt setting
0: disable
threshold
Bit Description
Battery over-temperature status reading
0: battery temperature below off-threshold
1: battery temperature was too high and the charger was turned off. The charger will be turned on again, when the temperature gets below the on-
Charger end of charge interrupt setting.
0: disable
Charger end of charge status reading
0: battery charging in progress
1: charging is complete, charging current is below selected level of nominal current, charger was turned off.
valid
x
0 x
0
W
R
Charger no battery interrupt setting
0: disable ams
W Charger detect interrupt setting.
0: disable
R Charger detect status reading
0:charger disconnected
1: charger connected
0
0 n/a
W x R
Current sink undervoltage interrupt setting.
0: disable
1: enable interrupt if the outputvoltage of one of the current sinks gets below the target regulation voltage
Current sink undervoltage status reading
0: normal voltage on ICURR1 and ICURR2
1: voltage at ICURR1 or ICURR2 dropped below target voltage
Technical
www.austriamicrosystems.com
Revision 1.03
58 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 50. Third Interrupt Register
Name
IRQENRD_2
Bit
1
0
Offset: 25h
Bit Name
VSUP_LOW_IRQ
(level)
VDD27_LOW_IRQ
(level)
Base
2-wire serial
Default
00h
Third Interrupt Register
Please be aware that writing to this register will enable/disable the corresponding interrupts, while reading gets the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a VDD27-POR or XRES input.
Default
0
Access
W x
0 x
R
W
R
Bit Description
VSUP under-voltage supervisor interrupt setting
0: disable
1: enable
VSUP supervisor interrupt reading
0: VSUP is above brown out level
1: VSUP has reached brown out level
The threshold can be set with
in SUPERVISOR2 register (22h). If the shutdown is enabled the interrupt will not occur.
VDD27 undervoltage supervisor interrupt setting
0: disable
1: enable
AG still
If the shutdown is enabled the interrupt will not occur.
valid
Technical
www.austriamicrosystems.com
Revision 1.03
59 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 51. Fourth Interrupt Register
Name
IRQENRD_3
Bit
7:6
5
4:3
2
1
0
Offset: 26h
Bit Name
-
T_DEB<1:0>
-
JTEMP_HIGH
(level)
-
ADC_EOC
(edge)
Base
2-wire serial
Fourth Interrupt Register
Default
00h
Please be aware that writing to this register will enable/disable the corresponding interrupts, while reading gets the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a VDD27-POR or XRES input.
Default
00
0
00
0 x
0
Access
R/W
R/W
R/W
W
R
R/W
Bit Description
Sets the de-bounce time all interrupt inputs:
0: 3ms
1: off
Supervisor junction over-temperature interrupt setting
0: disable
1: enable
AG still
The threshold can be set in the SUPERVISOR register (21h)
valid
0 x
W
R
ADC end of conversion interrupt setting
0: disable ams
Technical
www.austriamicrosystems.com
Revision 1.03
60 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 52. ADC10_0 Register
Name
ADC10_0
Bit
7:4
Offset: 2Eh
Bit Name
ADC10_MUX<3:0>
3:2
1:0
-
ADC10<9:8>
Table 53. ADC10_1 Register
Name
ADC10_1
Offset: 2Fh
Bit
7:0
Bit Name
ADC10<7:0>
Base
2-wire serial
First 10-bit ADC Register
Writing to this register will start the measurement of the selected source.
This register is reset at a VDD27-POR, exception are bit 0 and 1
Default
0000 00xxb
Default
0000
Access
R/W
Bit Description
Selects ADC input source
0000: VSUP
0001: GPIO3
0010: GPIO4
0011: VBATSW
0100: VUSB
0101: defined by DC_TEST in register 0x1C
0110: BATTEMP
0111: GPIO1
1000: GPIO2
1001:PWRUP
AG
1110: reserved
1101: reserved
still valid
00 xx n/a
R
ams
ADC result bit 9 to 8
Base
2-wire serial
Second 10-bit ADC Register
This register is reset at a VDD27-POR.
Default xxh
Bit Description Default
00h
Access
R ADC results bits 7 to 0
Technical
www.austriamicrosystems.com
Revision 1.03
61 - 70
AS3606 AS3607 2v2
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
11 Application Information
11.1 Pad Cells
Figure 21. Pad Cells Equivalant Circuit
AG still valid
Technical
www.austriamicrosystems.com
Revision 1.03
62 - 70
AS3606 AS3607 2v2
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
11.2 Application Schematics
Figure 22. Typical AS3606 Application Schematic
C19 10uF
CVDD1
CVDD2
CVDD3
U1 A
C3 10uF
C2 10uF
C1 10uF
L1 2.2uH
C6 2.2uF
C5 2.2uF
C4 2.2uF
LX2
LX3
13
12
11
30
31
29
27
26
28
CVDD2
LXC2
LXC3
VSUP3
CVDD3
C7 10uF
D6 ON
ON
R6 100R
Os PRG
DVDD
2
1
VSS
PWRUP
XIRQ
GPIO
XRES
CSDA
CSCL
24
21
23
20
25
18
33
19
22
GPIO2
GPIO1
0V SU 3
Q1 FDC602
DCDC
CURR1
15
14
content
R5 910k R7 100k
Q2 NDT014
CURR2
PWRUP
CSCL
CSDA
XRES
XRIQ
still valid
C16 2.2uF
Technical
C8 10uF www.austriamicrosystems.com
Revision 1.03
63 - 70
AS3606 AS3607 2v2
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 23. Typical AS3607 Application Schematic
R6 100R
D6 ON
CVDD1
CVDD2
CVDD3
C3 10uF
C2 10uF
C1 10uF
L1 2.2uH
C19 10uF
LX2
LX3
C6 2.2uF
C5 2.2uF
C4 2.2uF
30
31
32
* A
VSUP3
3 LXC
CVDD3
Os PRG
3
4
2
GPIO
GPIO
VSS
GPIO
23
20
37
21
22
GPIO4
GPIO3
GPIO2
GPIO1
13
14
15
35
34
33
PWRUP
26
CVDD2
XIRQ
27
2 LXC
XRES
28
VSUP2
C7 10uF
CSCL
CSDA
24
25
VSUP1
1 LXC
CVDD1
ams
Charger
Q1 FDC602
0V SU 3
CURR2
16 DCDC
CURR1
17
content
Q2 NDT014
R5 910k R7 100k
CURR1
XRIQ
XRES
CSDA
CSCL
PWRUP
still valid
C16 2.2uF
Technical
C8 1u www.austriamicrosystems.com
Revision 1.03
64 - 70
AS3606 AS3607 2v2
Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
12 Package Drawings and Markings
Figure 24. AS3606 QFN32, 0.5mm Pitch
AG still valid
Technical
www.austriamicrosystems.com
Revision 1.03
65 - 70
AS3606 AS3607 2v2
Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
Figure 25. AS3607 QFN36, 0.5mm Pitch
AG still valid
Technical
www.austriamicrosystems.com
Revision 1.03
66 - 70
AS3606 AS3607 2v2
Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
Figure 26. QFN Marking
Table 54. Package Code YYWWZZZ
YY
year
Table 55. Start-up Revision Code
xx
FF
00 xx
WW
working week assembly / packaging
AG
X
plant identifier free choice engineering samples, no sequence programmed or sequence programmed on request default sequence (no sequence programmed) customer specified sequence programmed during production test
content valid
Technical
www.austriamicrosystems.com
Revision 1.03
67 - 70
AS3606 AS3607 2v2
Data Sheet - R e v i s i o n H i s t o r y
Revision History
Revision
1.00
1.01
1.02
1.03
Date
7.2010
9.2010
11.2010
3.2011
Owner
pkm pkm pkm pkm
Description
first official release corrected GPIO2 bit description & GPIO hibernation description updated package drawings corrected charger block diagram, updated package drawings added NTC supply description, added USB rising edge specification
Note:
Typos may not be explicitly mentioned under revision history.
AG still valid
Technical
www.austriamicrosystems.com
Revision 1.03
68 - 70
AS3606 AS3607 2v2
Data Sheet - O r d e r i n g I n f o r m a t i o n
13 Ordering Information
The devices are available as the standard products shown in
Table 56. Ordering Information
Ordering Code
AS3606-BQFP-FF
Marking
R2v2-FF
Sequence
sequence programmable on request
Description Delivery Form
System PMU with HV Backlight Tape & Reel dry pack
Package
QFN32 5x5 0.5mm pitch
AS3606-BQFP-00 R2v2-00 default sequence QFN32 5x5 0.5mm pitch System PMU with HV Backlight Tape & Reel dry pack
AS3606-BQFP-xx
AS3607-BQFP-FF
AS3607-BQFP-00
AS3607-BQFP-xx
R2v2-xx customer specified
R2v2-FF
R2v2-00 sequence programmable on request default sequence
R2v2-xx customer specified
System PMU with HV Backlight Tape & Reel dry pack
System PMU with HV Backlight Tape & Reel dry pack
Note:
All products are RoHS compliant and austriamicrosystems green.
Buy our products or get free samples online at ICdirect:
Technical Support is found at
AG
For further information and requests, please contact us mailto:[email protected]
QFN32 5x5 0.5mm pitch
valid
System PMU with HV Backlight Tape & Reel dry pack
System PMU with HV Backlight Tape & Reel dry pack
QFN36 6x6 0.5mm pitch
still
or find your local distributor at http://www.austriamicrosystems.com/distributor
content
Technical
www.austriamicrosystems.com
Revision 1.03
69 - 70
AS3606 AS3607 2v2
Data Sheet - C o p y r i g h t
Copyright
Copyright © 1997-2010, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®.
All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100
valid
parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services.
AG still
Contact Information
Headquarters
austriamicrosystems AG
Tobelbaderstrasse 30
A-8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01 http://www.austriamicrosystems.com/contact www.austriamicrosystems.com
Revision 1.03
70 - 70
Download
Public link updated
The public link to your chat has been updated. You may view and manage your chat links after registration here.
Document public link
Advertisement
