AMS AS7265x Light Sensor Datasheet
AMS AS7265x is a compact 18-channel spectrometry chip-set solution that can be used for spectral identification in a range from visible to NIR. It consists of three sensor devices with 6 independent on-device optical filters each, resulting in a total of 18 channels with a spectral response from 410nm to 940nm. The device has a UART or I²C slave digital interface and integrates Gaussian filters into standard CMOS silicon via nano-optic deposited interference filter technology. It also features programmable LED drivers and built-in apertures to control the light entering the sensor array.
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General Description
AS7265x
Smart 18-Channel VIS to NIR Spectral_
ID 3-Sensor Chipset with Electronic
Shutter
The AS7265x chipset consists of three sensor devices AS72651 with master capability, AS72652 and AS72653. The multispectral sensors can be used for spectral identification in a range from visible to NIR. Every of the three sensor devices has 6 independent on-device optical filters whose spectral response is defined in a range from 410nm to 940nm with FWHM of 20nm.
The AS72651, combined with the AS72652 (spectral response from 560nm to 940nm) and the AS72653 (spectral response from 410nm to 535nm) form an AS7265x 18-channel multi-spectral sensor chip-set. Using the AS7265x chipset requires the use of firmware. It must be loaded into a serial flash via a UART interface. The list of
ams
tested serial flash memories can be found in
Figure 56 . The components AS72651, AS72652
and AS72653 are pre-calibrated with a specific light source. The information about the conditions of the performed calibration
(for example light source, gain, integration time) can be found in the table of optical characteristics of the respective component. Any operation other than these conditions might require a new calibration in the application.
Each AS7265x device has two integrated LED drivers with programmable current and can be timed for electronic shutter applications.
The device family integrates Gaussian filters into standard
CMOS silicon via nano-optic deposited interference filter technology in LGA packages that also provide built-in apertures to control the light entering the sensor array.
and
Content Guide appear at end of
datasheet.
Key Benefits & Features
The benefits and features of AS7265x, Smart 18-Channel VIS to
NIR Spectral_ID 3-Sensor Chipset with Electronic Shutter are listed below:
ams Datasheet
[v1-04] 2018-Jul-09
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AS7265x −
General Description
Figure 1:
AS7265x Chip-Set Benefits and Features
Benefits
•
Compact 18-channel spectrometry chip-set solution
•
No additional signal conditioning required
•
Small, robust package, with built-in aperture
Features
•
3 chip set including master device delivering 18 visible and NIR channels from 410nm to 940nm each with 20nm FWHM
•
UART or I²C slave digital Interface
•
Visible filter set realized by silicon interference filters
•
16-bit ADC with digital access
•
Programmable LED drivers
•
2.7V to 3.6V with I²C interface
•
20-pin LGA package 4.5mm x 4.7mm x 2.5mm
-40°C to 85°C temperature range
Applications
The AS7265x applications include:
•
Product/Brand authentication
•
Anti-counterfeiting
•
Portable spectroscopy
•
Product safety/adulteration detection
•
Horticultural and specialty lighting
•
Material analysis
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AS7265x −
General Description
Block Diagram
The functional blocks of this device are shown below:
Figure 2:
AS7265x Chip-Set Block Diagram
AS72652
SCL_S
SDA_S
Communication
VDD
I
2
C Slave
RESN
Micro
Controller
Unit (MCU)
VDD1 VDD2
I2C_ENB
RX / SCL_S
TX / SDA_S
INT
AS72651
Communication
VDD
UART or
I
2
C Slave
VDD
I
2
C Master
SDA_M
SCL_M
SLV1_RESN
SLV2_RESN
RESN
VDD1
VDD2
Spectral_ID
Sensor
VDD
LED Drivers
Current
Control
R
U
S
V
T
W
°C
OSC
16MHz
VDD
Firmware Interface
SPI
Master
GND
LED_IND
LED_DRV
MISO
MOSI
SCK
CSN
Serial Flash
Memory
VDD1 VDD2
Spectral_ID
Sensor
G
J
H
K
I
L
LED Drivers
VDD
Current
Control
°C
OSC
16MHz
GND
LED_IND
LED_DRV
AS72653
SCL_S
SDA_S
Communication
VDD
I
2
C Slave
RESN
Spectral_ID
Sensor
A
D
B
E
C
F
LED Drivers
VDD
Current
Control
°C
OSC
16MHz
GND
LED_IND
LED_DRV
Note(s):
1. Refer to the Application Diagram in
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Pin Assignments
AS7265x −
Pin Assignments
The device pin assignments are described below.
Figure 3:
Pin Diagram of AS7265x (Top View)
20 16
1
15
5
11
6 10
Figure 4:
AS72651 Pin Description
Pin No.
Pin Name
1
Pin Type
SLV1_RESN Digital Input and Output
2
5
6
3
4
7
8
9
RESN
SCK
MOSI
MISO
CSN
NC
I2C_ENB
SCL_M
Digital Input
Digital Output
Digital Input and Output
Digital Input and Output
Digital Output
Digital Input
Digital Output
10 SDA_M Digital Input and Output
Description
Reset pin for Slave 1 e.g. AS72652, active low
Reset pin, active low (with internal pull-up to
VDD)
SPI serial clock
SPI MOSI
SPI MISO
Chip select for external flash
Not functional, no connect
Selects UART (low) or I²C (high) operation
I²C master clock for communication with
AS72652 and AS72653
I²C master data for communication with AS72652 and AS72653
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AS7265x −
Pin Assignments
Pin No.
Pin Name
11
Pin Type
RX / SCL_S Digital Input and Output
12
17
18
19
20
13
14
15
16
TX / SDA_S
INT
VDD2
LED_DRV
GND
Digital Input and Output
Digital Output
Voltage Supply
Analog Output
Supply
VDD1
LED_IND
Voltage Supply
Analog Output
NC
SLV2_RESN Digital Output
Note(s):
1. Pin out is valid for firmware versions from 11 and later.
Figure 5:
AS72652 and AS72653 Pin Description
Pin No.
Pin Name
1 NC
2
5
6
3
4
7
8
9
RESN
NC
NC
NC
NC
NC
NC
SCL_S
Pin Type
Digital Input
Digital Input and Output
10 SDA_S Digital Input and Output
Description
RX (UART) or SCL_S (I²C slave) depending on
I2C_ENB setting
TX (UART) or SDA_S (I²C slave) depending on
I2C_ENB setting
INT is active low
Voltage supply
LED driver output for driver LED, current sink
Ground
Voltage supply
LED driver output for indicator LED, current sink
Not functional, no connect
Reset pin for slave 2 e.g. AS72653, active low
Description
Not functional, no connect
Reset pin, active low (with internal pull-up to
VDD)
Not functional, no connect
Not functional, no connect
Not functional, no connect
Not functional, no connect
Not functional, no connect
Not functional, no connect
I²C slave clock for communication with master
AS72651
I²C slave data for communication with master
AS72651
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Pin No.
Pin Name
15
16
17
18
11
12
13
14
19
20
NC
NC
INT
VDD2
LED_DRV
GND
VDD1
LED_IND
NC
NC
Pin Type
Digital Output
Voltage Supply
Analog Output
Supply
Voltage Supply
Analog Output
AS7265x −
Pin Assignments
Description
Not functional, no connect
Not functional, no connect
INT is active low
Voltage supply
LED driver output for driver LED, current sink
Ground
Voltage supply
LED driver output for indicator LED, current sink
Not functional, no connect
Not functional, no connect
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AS7265x −
Absolute Maximum Ratings
Absolute Maximum Ratings
Stresses beyond those listed under
Absolute Maximum Ratings of AS7265x
may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The device is not designed for high energy UV
(ultraviolet) environments, including upward looking outdoor applications, which could affect long term optical performance.
Figure 6:
Absolute Maximum Ratings of AS7265x
Symbol
V
DD1_MAX
V
DD2_MAX
V
DD_IO
I
SCR
ESD
HBM
ESD
CDM
T
STRG
T
BODY
RH
NC
MSL
Parameter Min Max
Electrical Parameters
-0.3
5
Unit Comments
Supply Voltage VDD1
Supply Voltage VDD2
V
V
Pin VDD1 to GND
Pin VDD2 to GND -0.3
5
Input/Output Pin Voltage
Input Current (latch-up immunity)
-0.3
VDD+0.3
± 100
Electrostatic Discharge
Electrostatic Discharge HBM
Electrostatic Discharge CDM
±1000
±500
V mA
V
V
Temperature Ranges and Storage Conditions
Storage Temperature Range -40 85 °C
Input/Output Pin to GND
JESD78D
JS-001-2014
JESD22-C101F
Package Body Temperature 260 °C
IPC/JEDEC J-STD-020. The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC
J-STD-020 “Moisture/Reflow
Sensitivity Classification for
Non-hermetic Solid State
Surface Mount Devices”
Relative Humidity
(non-condensing)
5 85 %
Moisture Sensitivity Level 3
Represents a 168 hour max. floor lifetime
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AS7265x −
Electrical Characteristics
Electrical Characteristics
All limits are guaranteed with VDD = VDD1 = VDD2 = 3.3V,
T
AMB
= 25
°
C. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality
Control) methods.
VDD1 and VDD2 should be sourced from the same power supply output.
Figure 7:
Electrical Characteristics of AS7265x
Symbol
VDD1
/VDD2
VDD1
/VDD2
T
AMB
I
VDD
F
OSC t
JITTER
(1)
D
TEMP
I
IND
I
ACC
V
LED
I
LED1
I
ACC
V
LED
Parameter
Voltage Operating
Supply
Voltage Operating
Supply
Operating Temperature
Operating Current
Conditions
General Operating Conditions
Min
UART Interface
I²C Interface
2.97
2.7
-40
Internal RC Oscillator
Internal RC Oscillator
Frequency
Internal Clock Jitter
15.7
@25°C
Temperature Sensor
Absolute Accuracy of the
Internal Temperature
Measurement
-8.5
Indicator LED
LED Current
Accuracy of Current
Voltage Range of
Connected LED
Vds of current sink
1
-30
0.3
LED_DRV
LED Current
Accuracy of Current
Voltage Range of
Connected LED
Vds of current sink
12.5
-10
0.3
Typ
3.3
3.3
25
16
Max
3.6
3.6
85
5
16.3
1.2
8.5
8
30
VDD
100
10
VDD
Unit
V
MHz ns mA
%
V mA
%
V
V
°C mA
°C
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AS7265x −
Electrical Characteristics
Symbol
I
IH
, I
IL
V
IH
Parameter Conditions Min
Logic Input Current
CMOS Logic High Input
Digital Inputs and Outputs
Vin=0V or VDD -1
0.7*
VDD
V
IL
CMOS Logic Low Input 0
V
OH
V
OL t
t
FALL
CMOS Logic High Output I=1mA
CMOS Logic Low Output I=1mA
Current Rise Time C(Pad)=30pF
Current Fall Time C(Pad)=30pF
Note(s):
1. Guaranteed by design, not tested in production.
Typ Max
1
VDD
0.3*
VDD
VDD-
0.4
0.4
5
5
Unit
V
V ns ns
μ
A
V
V
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AS7265x −
Electrical Characteristics
Figure 8:
AS7265x I²C Slave Timing Characteristics
Timing Characteristics
t
HS:STA t
LOW t
HIGH t
SU:STA t
HS:DAT t
SU:DAT t
R t
F t
SU:STO
Symbol
f
SCLK t
BUF
C
B
C
I/O
Parameter Conditions
I²C Interface
SCL Clock Frequency
Bus Free Time Between a STOP and
START
Hold Time (Repeated) START
LOW Period of SCL Clock
HIGH Period of SCL Clock
Setup Time for a Repeated START
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL
Fall Time of Both SDA and SCL
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
CB - total capacitance of one bus line in pF
I/O Capacitance (SDA, SCL)
Min Typ Max Unit
0
1.3
0
100
20
20
0.6
0.6
1.3
0.6
0.6
400
10 pF pF
400
0.9
300
300 kHz
μs
μs ns ns ns
μs
μs
μs
μs
μs
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AS7265x −
Electrical Characteristics
Figure 9:
I²C Slave Timing Diagram
SCL
P
SDA t
BUF
Stop Start
S t
HD:STA
V
IH
V
IL t
R t
F t
LOW t
HD:DAT t
HIGH t
SU:DAT t
SU:STA
S t
SU:STO
P
Figure 10:
AS72651 SPI Timing Characteristics
Symbol
f
SCK t
SCK_H t
SCK_L t
SCK_RISE t
SCK_FALL
Clock Frequency
Clock High Time
Clock Low Time
SCK Rise Time
SCK Fall Time t
CSN_S t
CSN_H
Parameter
CSN Setup Time
CSN Hold Time t
CSN_DIS t
DO_S t
DO_H t
DI_V
CSN Disable Time
Data-Out Setup Time
Data-Out Hold Time
Data-In Valid
Conditions
SPI Interface
Min
Time between CSN high-low transition to first SCK high transition
Time between last SCK falling edge and CSN low-high transition
50
100
0
40
40
5
5
100
5
5
10
Typ Max
16
Unit
ns ns ns ns ns ns
MHz ns ns ns ns
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Figure 11:
SPI Master Write Timing Diagram
CSN t
CSN_S
SCK
MOSI
MISO
HI-Z t
DO_S
MSB t
DO_H t
SCK_RISE t
SCK_FALL
Figure 12:
SPI Master Read Timing Diagram
CSN_xx
SCK
MOSI
MISO t
SCK_H t
SCK_L t
DI_V
Dont care
MSB
AS7265x −
Electrical Characteristics t
CSN_H t
CSN_DIS
LSB
HI-Z
LSB
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AS7265x −
Typical Operating Characteristics
Typical Operating
Characteristics
Optical Characteristics
All optical characteristics are optimized for diffused light. When using a point light source or collimated light on the sensor, the sensor opening must be covered by a lambertian diffuser with achromatic characteristics. Diffusor of Tsujiden like D121UP have been successfully tested at
ams
. If in the application diffused light, e.g. used by a reflective surface, no additional diffuser is required.
Figure 13:
AS7265x LGA Average Field of View
Diffused Light
A=0.75mm
H=2.5mm
Lens
α = 12°
LGA Package Substrate
Figure 14:
AS7265x 18-Channel Spectral Responsivity
18 Channel Spectral Response
AS72651 + AS72652 + AS72653
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Wavelength (λ, nm)
410nm
435nm
460nm
485nm
510nm
535nm
560nm
585nm
610nm
645nm
680nm
705nm
730nm
760nm
810nm
860nm
900nm
940nm
T
U
V
W
S
J
I
R
K
L
E
F
G
H
A
B
C
D
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AS7265x −
Typical Operating Characteristics
Figure 15:
AS72651 Spectral Responsivity
AS72651, 6-Channel Spectral Response
R
610
S
680
T
730
U
760
V
810
W
860
1.2
1
0.8
0.6
0.4
0.2
0
Wavelength (λ, nm)
Figure 16:
Optical Characteristics of AS72651 (Pass Band)
Symbol Parameter Test Conditions
Channel
(nm)
Min
R
S
T
U
V
Channel R
Channel S
Channel T
Channel U
Channel V
Incandescent
Incandescent
Incandescent
Incandescent
Incandescent
W Channel W
FWHM
Wacc
Full Width Half
Max
Wavelength
Accuracy
Incandescent
610
680
730
760
810
860
+10
Typ Max
20
Unit
counts/
(μW/cm
2
) counts/
(μW/cm
2
) counts/
(μW/cm
2
) counts/
(μW/cm
2
) counts/
(μW/cm
2
) counts/
(μW/cm
2
) nm
-10 nm
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AS7265x −
Typical Operating Characteristics
Symbol Parameter Test Conditions
Channel
(nm)
Min
dark
AFOV
Dark Channel
Counts
GAIN=64,
T
AMB
=25°C t int
=165ms
Average Field of View
Typ
±20.5
Max
5
Unit
counts deg
Note(s):
1. Calibration and measurements are made using diffused light.
2. Each channel is tested with GAIN = 16x, Integration Time (INT_T) = 166ms and VDD = VDD1 = VDD2 = 3.3V, T
AMB
=25°C.
3. The accuracy of the channel counts/μW/cm
2
is ±12%.
4. The light source is an incandescent light with an irradiance of ~1500μW/cm
2
(300-1000nm).
Figure 17:
AS72652 Spectral Responsivity
AS72652, 6-Channel Spectral Response
(w/AS72651 as Controller)
G
560
H
585
I
645
J
705
K
900
L
940
1.2
1
0.8
0.6
0.4
0.2
0
Wavelength (λ, nm)
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AS7265x −
Typical Operating Characteristics
Figure 18:
Optical Characteristics of AS72652 (Pass Band)
Symbol
G
H
I
J
K
Parameter
Channel I
Channel J
Conditions
Channel G
3300K White LED
Channel H
3300K White LED
3300K White LED
3300K White LED
Channel K
Channel
(nm)
560
585
645
705
900
Min Typ Max
20
Unit
counts/
(μW/cm
2
) counts/
(μW/cm
2
) counts/
(μW/cm
2
) counts/
(μW/cm
2
) counts/
(μW/cm
2
) counts/
(μW/cm
2
) nm
L
FWHM
Wacc dark
AFOV
Channel L
Full Width
Half Max
Wavelength
Accuracy
Dark
Channel
Counts
Average
Field of View
GAIN=64, T
AMB
=25°C t int
= 165ms
940
-10
±20.5
+10
5
Note(s):
1. Calibration and measurements are made using diffused light.
2. Each channel is tested with GAIN = 16x, Integration Time (INT_T) = 166ms and VDD = VDD1 = VDD2 = 3.3V, T
AMB
=25°C.
3. The accuracy of the channel counts/μW/cm
2
is ±12%.
nm counts deg
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AS7265x −
Typical Operating Characteristics
Figure 19:
AS72653 Spectral Responsivity
0.6
0.4
0.2
0
1.2
1
0.8
AS72653, 6-Channel Spectral Response
(w/AS72651 as controller)
A
410
B
435
C
460
D
485
E
510
F
535
Wavelength (λ, nm)
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AS7265x −
Typical Operating Characteristics
Figure 20:
Optical Characteristics of AS72653 (Pass Band)
Symbol
A
B
C
D
E
Parameter
Channel A
Channel B
Channel C
Channel D
Channel E
Conditions
395nm
415nm
428nm
5600K white
F
FWHM
Wacc dark
AFOV
Channel F
Full Width
Half Max
Wavelength
Accuracy
Dark Channel
Counts
Average Field of View
GAIN=64, T
AMB
=25°C t int
= 165ms
Channel
(nm)
Min Typ Max
410
35
435
460
485
510
535
35
35
35
35
35
20
Unit
counts/
(μW/cm
2
) counts/
(μW/cm
2
) counts/
(μW/cm
2
) counts/
(μW/cm
2
) counts/
(μW/cm
2
) counts/
(μW/cm
2
) nm
-10
±20.5
+10
5 nm counts deg
Note(s):
1. Calibration and measurements are made using diffused light.
2. Each channel is tested with GAIN = 16x, Integration Time (INT_T) = 166ms and VDD = VDD1 = VDD2 = 3.3V, T
AMB
=25°C.
3. The accuracy of the channel counts/μW/cm
2
is ±12%.
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AS7265x −
Detailed Description
Detailed Description
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AS7265x 18-Channel
Spectral_ID
Detector
Overview
Each of the three AS7265x
Spectral_ID
devices are next-generation digital 6-channel spectral sensor devices. Each of the 6 channels has a Gaussian filter characteristic with a full width half maximum (FWHM) bandwidth of 20nm. The filters use an interference topology design providing high stability in terms of drift in time and temperature. The drifts are so small that it is undetectable in the measurement. The temperature drift of the device is largely determined by the drift of the sensor and the electronics. To compensate for the temperature drift in the application, every device of the AS7265x chipset includes an integrated temperature sensor.
Filter accuracy will be affected by the angle of incidence which itself is limited by integrated aperture and internal micro-lens structure. The aperture-limited average field of view is ±20.5° to deliver specified accuracy. All optical characteristics are optimized for using diffused light.
Each device contains an analog-to-digital converter (16-bit resolution ADC) which integrates the current from each channel’s photodiode. Upon completion of the conversion cycle, the integrated result is transferred to the corresponding data registers. The transfers are double-buffered to ensure data integrity is maintained.
The external MCU interface control via I²C registers or AT commands, transparently controls the AS72652 and/or AS72653.
A serial flash is a required operating companion for this device and enables factory calibration/normalization of the filters.
Supported device types are noted in
Ordering & Contact Information
at the end of this document.
Required operating code can be downloaded at download.ams.com
.
Channel Data Conversion of the AS7265x
Devices
All three of these 6 channel devices use conversion implemented via two photodiode banks in each device. Refer to
. Bank 1 consists of register data from 4 of the 6 photodiodes, with 2 registers zeroed and Bank 2 consists of data from a different set of 4 of the 6 photodiodes, with
2 different registers zeroed. Spectral conversion requires the integration time (IT in ms) set to complete. If both photodiode banks are required to complete the conversion, the 2 nd
bank requires an additional IT ms. Minimum IT for a single bank conversion is 2.8 ms. If data is required from all 6 photodiodes then the device must perform 2 full conversions (2 x Integration
Time).
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AS7265x −
Detailed Description
This spectral data conversion process operates continuously, new data is available after each IT ms period.
The conversion process is controlled with BANK Mode settings in the AS72651 as follows:
BANK Mode 0 Registers:
AS72651 data will be in S, T, U & V registers (R & W will be zero)
AS72652 data will be in G, H, K & I registers (J & L will be zero)
AS72653 data will be in A, B, E & C registers (D & F will be zero)
BANK Mode 1 Registers:
AS72651 data will be in R, T, U & W registers (S & V will be zero)
AS72652 data will be in G, H, J & L registers (I & K will be zero)
AS72653 data will be in F, A, B & D registers (C & E will be zero)
BANK Mode 2 Registers:
AS72651 data will be in S, T, U, V, R & W registers
AS72652 data will be in G, H, K, I, J & L registers
AS72653 data will be in A, B, C, D, E & F registers
For BANK Mode 2, care should be taken to assure prompt interrupt servicing so integration values from both banks are all derived from the same spectral conversion cycle.
Figure 21:
AS7265x Photo Diode Arrays
AS72651 Photo Diode Array AS72652 Photo Diode Array AS72653 Photo Diode Array
T U S G H I A B C
R V W J K L D E F
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AS7265x −
Detailed Description
Figure 22:
Bank Mode and Data Conversion
BANK Mode 0
One Conversion
Integration Time
BANK Mode 1
One Conversion
Integration Time
BANK Mode 2
1st Conversion
Integration Time
S, T, U, V, I, G, H, K,
R, T, U, W,
C, A, B, E
L, G, H, J, F, A, B, D
S, T, U, V, I, G, H, K, C, A, B, E
2nd Conversion
Integration Time
R, T, U, W, L, G, H, J, F, A, B, D
RC Oscillator
The timing generation circuit consists of on-chip 16MHz, temperature compensated oscillators, which provide the individual master clocks of the AS7625x devices
Temperature Sensor
The AS7265x internal temperature sensors are constantly measuring on-chip temperature to enable temperature compensation procedures, and can be read via I²C registers or AT commands in the AS72651.
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AS7265x −
Detailed Description
Reset
Pulling down the RESN pin for longer than 100ms resets the
AS72651 which proceed to reset the AS72562 and the same
RESN signal shown below can be used directly to reset the
AS72653.
Figure 23:
Reset Circuit
Spectral_ID
Engine
AS72651
Reset
VDD
RESN
Push > 100ms
AS7265x LED_IND Controls
There are LED_IND pins on all AS7265x devices. An LED connected to LED_IND can be used as a general power indicator and will automatically be used to indicate a Flash firmware update is occurring.
The LED_IND can then be setup as needed. Each AS7265x LED_
IND source can be turned on/off via AT commands or I²C register control, and LED_IND sink current is programmable to 1mA,
2mA, 4mA or 8mA. This LED_IND control can also be used in applications just like the LED_DRV control (described below), if the lower current sink of the LED_IND control is appropriate.
Electronic Shutter with AS7265x LED_DRV
Driver Control
There are LED_DRV pins on all AS7265x devices. The LED_DRV pin can be used to control external LED sources as needed for sensor applications. LED_DRV can sink a programmable current of 12.5mA, 25mA, 50mA or 100mA. The control can be turned on/off via I²C registers or AT commands, and as such it provides the AS7265x device with an electronic shutter.
Interrupt Operation
Interrupt operation is only needed for AS72651 as it transparently controls data collection from the AS72652 (if used) or
AS72653 (if used).
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Detailed Description
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If BANK is set in the AS72651 to Mode 0 or Mode 1, data is ready after the 1 st
integration time. If BANK is set to Mode 2, data is ready after two integration times.
For interrupt operation using I²C registers, if interrupts are enabled and data is ready, the INT pin is set low and DATA_RDY is set to 1. Reading the raw or calibration data releases (returns high) the interrupt. For multi-byte sensor data (2 or 4 bytes), after the 1st byte is read the remaining bytes are shadow protected in case an integration cycle completes just after the 1st byte is read. The sensors continue to gather information at the rate of the integration time, hence if the sensor registers are not read when the interrupt line goes low, it will stay low and the next cycle’s sensor data will be available in the registers at the end of the next integration cycle.
For interrupt operation using AT Commands, if interrupts are enabled and data is ready the INT pin is set low and is released
(returns high) after any sensor data is read.
Required Flash Memory
Serial flash is a required operating companion for this device, and enables the I²C and UART interfaces, as well as enabling calibrated data results. Supported device types are noted in
Ordering & Contact Information
at the end of this document.
Required operating code can be downloaded at download.ams.com
.
I²C Slave Interface
If selected by the I2C_ENB pin setting, interface and control can be accomplished through an I²C compatible slave interface to a set of registers that provide access to device control functions and output data. These registers on the AS72651 are, in reality, implemented as
virtual
registers in software. The actual I²C slave hardware registers number only three and are described in the table below. The steps necessary to access the virtual registers defined in the following are explained in pseudocode for external I²C master writes and reads below.
I²C Feature List
•
Fast mode (400kHz).
•
7+1-bit addressing mode.
•
Write format: Byte.
•
Read format: Byte.
•
SDA input delay and SCL spike filtering by integrated
RC-components.
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AS7265x −
Detailed Description
Figure 24:
I²C Slave Device Address and Physical Registers
Entity Description
Device Slave Address 8-bit slave address
STATUS Register
I²C slave interface STATUS register. Read-only.
WRITE Register
READ Register
I²C slave interface WRITE register. Write-only.
I²C slave interface
READ register. Read-only.
Note
Byte = 1001001x (device address = 49 hex)
•
x= 1 for Master Read (byte = 93 hex)
•
x= 0 for Master Write (byte = 92 hex)
Register Address = 0x00
Bit 1: TX_VALID
•
0 - New data may be written to WRITE register
•
1 -WRITE register occupied. Do NOT write.
Bit 0: RX_VALID
•
0 -No data is ready to be read in READ register.
•
1 -Data byte available in READ register.
Register Address = 0x01
•
8-Bits of data written by the I²C Master intended for receipt by the I²C slave. Used for both
virtual
register addresses and write data.
Register Address = 0x02
•
8-Bits of data to be read by the I²C Master.
I²C Virtual Register Write Access
I²C Virtual Resister Byte Write, detailed below, shows the pseudocode necessary to write virtual registers on the
AS72651. Note that, because the actual registers of interest are realized as virtual registers, a means of indicating whether there is a pending read or write operation of a given virtual register is needed. To convey this information, the most significant bit of the virtual register address is used as a marker. If it is 1, then a write is pending, otherwise the slave is expecting a virtual read operation. The pseudocode illustrates the proper technique for polling of the I²C slave status register to ensure the slave is ready for each transaction.
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Detailed Description
I²C Virtual Register Byte Write
Pseudocode
Poll I²C slave STATUS register;
If TX_VALID bit is 0, a write can be performed on the interface;
Send a virtual register address and set the MSB of the register address to 1 to indicate the pending write;
Poll I²C slave STATUS register;
If TX_VALID bit is 0, the virtual register address for the write has been received and the data may now be written;
Write the data.
Sample Code:
#define I2C_AS72XX_SLAVE_STATUS_REG 0x00
#define I2C_AS72XX_SLAVE_WRITE_REG
#define I2C_AS72XX_SLAVE_READ_REG
#define I2C_AS72XX_SLAVE_TX_VALID
#define I2C_AS72XX_SLAVE_RX_VALID
0x01
0x02
0x02
0x01
{ void i2cm_AS72xx_write(uint8_t virtualReg, uint8_t d) volatile uint8_tstatus;
{ while (1)
// Read slave I²C status to see if the write buffer is ready.
status = i2cm_read(I2C_AS72XX_SLAVE_STATUS_REG); if ((status & I2C_AS72XX_SLAVE_TX_VALID) == 0)
// No inbound TX pending at slave. Okay to write now.
break ;
}
// Send the virtual register address (enabling bit 7 to indicate a write). i2cm_write(I2C_AS72XX_SLAVE_WRITE_REG, (virtualReg | 0x80)) ;
{ while (1)
// Read the slave I²C status to see if the write buffer is ready.
status = i2cm_read(I2C_AS72XX_SLAVE_STATUS_REG) ; if ((status & I2C_AS72XX_SLAVE_TX_VALID) == 0)
// No inbound TX pending at slave. Okay to write data now.
break ;
}
// Send the data to complete the operation.
i2cm_write(I2C_AS72XX_SLAVE_WRITE_REG, d) ;
}
I²C Virtual Register Read access
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}
AS7265x −
Detailed Description
I²C Virtual Register Byte Read, detailed below, shows the pseudocode necessary to read virtual registers on the AS72651.
Note that in this case, reading a virtual register, the register address is not modified.
I²C Virtual Register Byte Read
Pseudocode
Poll I²C slave STATUS register;
If TX_VALID bit is 0, the virtual register address for the read may be written;
Send a virtual register address;
Poll I²C slave STATUS register;
If RX_VALID bit is 1, the read data is ready;
Read the data.
Sample Code
{ uint8_t i2cm_AS72xx_read(uint8_t virtualReg) volatile uint8_t status, d;
{ while (1)
// Read slave I²C status to see if the read buffer is ready.
status = i2cm_read(I2C_AS72XX_SLAVE_STATUS_REG) ; if ((status & I2C_AS72XX_SLAVE_TX_VALID) == 0)
// No inbound TX pending at slave. Okay to write now.
break;
}
// Send the virtual register address (disabling bit 7 to indicate a read).
i2cm_write(I2C_AS72XX_SLAVE_WRITE_REG, virtualReg);
{ while (1)
// Read the slave I²C status to see if our read data is available.
status = i2cm_read(I2C_AS72XX_SLAVE_STATUS_REG); if ((status & I2C_AS72XX_SLAVE_RX_VALID)!= 0)
// Read data is ready.
break;
}
// Read the data to complete the operation.
d = i2cm_read(I2C_AS72XX_SLAVE_READ_REG) ; return d;s
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The details of the i2cm_read() and i2cm_write() functions in previous figures are dependent upon the nature and implementation of the external I²C master device.
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AS7265x −
Detailed Description
4-Byte Floating-Point (FP) Registers
Several 4 byte registers (hex) are used by the AS72651. Here is an example of how these registers are used to represent floating point data (based on the IEEE 754 standard).
Figure 25:
Example of the IEEE 754 Standard
byte 3
3E (hex) byte 2
20 (hex) byte 1
00 (hex) byte 0
00 (hex)
0 0 1 1 1 1 1 0
31
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
24 23 16 15 8 7 0 sign exponent (8 bits) fraction (23 bits)
0 0 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31 30 23 22 0
= 0.15625
The floating point (FP) value assumed by 32 bit
binary32 data
with a biased exponent
e
(the 8 bit unsigned integer) and a
23 bit fraction
is (for the above example):
(EQ1)
FPvalue = sign
⋅
1 +
23
b
⋅
2
–
i
⋅
2
( e 127 )
FPvalue =
0
⋅
1 +
23
b
⋅
2
– i
⋅
2
(
FPvalue = 1
⋅ (
+
– 2
) ⋅
2
– 3
= 0.15625
)
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AS7265x −
Detailed Description
I²C Virtual Register Set
The figure below provides a summary of the AS72651 I²C register set for the AS72651 which serves as the master interface of the 3 device AS7265x set. Figures after that provide additional register details. All register data is hex, and all multi-byte entities are Big Endian (most significant byte is situated at the lowest register address).
Multiple byte registers (2 byte integer, or, 4 byte floating point) must be read in the order of ascending register addresses (low to high) and if capable of being written to, must also be written in the order ascending register addresses.
Figure 26:
AS72651 I²C Master Device Virtual Register Set Overview
0x0C
0x0D
0x0E
0x0F
0x08
0x09
0x0A
0x0B
0x10
0x11
0x12
0x13
Addr
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
Name
HW Version
FW Version
Configuration
Integration Time
Temperature
LED
Configuration
RAW value R, G, A
RAW value R, G, A
RAW value S, H, B
RAW value S, H, B
RAW value T, I, C
RAW value T, I, C
RAW value U, J, D
RAW value U, J, D
RAW value V, K, E
RAW value V, K, E
RAW value W, L, F
RAW value W, L, F
<D7> <D6> <D5> <D4> <D3> <D2> <D1> <D0>
SRST
READ_
ERR
INT
LED_
DRV
HW Version H
HW Version L
FW Version H
FW Version L
GAIN BANK
Integration Time
Temperature
ENA-
BLELED
_DRV
RAW value H
RAW value L
RAW value H
RAW value L
RAW value H
RAW value L
RAW value H
RAW value L
RAW value H
RAW value L
RAW value H
RAW value L
DATA_RDY
LED_INT
FRST
ENABL
E LED_
INT
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Detailed Description
Addr
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
Name
Calibrated value channel T, I, C
Calibrated value channel T, I, C
Calibrated value channel T, I, C
Calibrated value channel T, I, C
Calibrated value channel U, J, D
Calibrated value channel U, J, D
Calibrated value channel U, J, D
Calibrated value channel U, J, D
Calibrated value channel R, G, A
Calibrated value channel R, G, A
Calibrated value channel R, G, A
Calibrated value channel R, G, A
Calibrated value channel S, H, B
Calibrated value channel S, H, B
Calibrated value channel S, H, B
Calibrated value channel S, H, B
Calibrated value channel V, K, E
Calibrated value channel V, K, E
Calibrated value channel V, K, E
<D7> <D6> <D5> <D4> <D3> <D2> <D1> <D0>
CAL CHAN0_0
CAL CHAN0_1
CAL CHAN0_2
CAL CHAN0_3
CAL CHAN0_0
CAL CHAN0_1
CAL CHAN0_2
CAL CHAN0_3
CAL CHAN0_0
CAL CHAN0_1
CAL CHAN0_2
CAL CHAN0_3
CAL CHAN0_0
CAL CHAN0_1
CAL CHAN0_2
CAL CHAN0_3
CAL CHAN0_0
CAL CHAN0_1
CAL CHAN0_2
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AS7265x −
Detailed Description
0x50
0x51
0x52
0x53
0x54
0x55
Addr
0x27
0x28
0x29
0x2A
0x2B
0x48
0x49
0x4A
0x4B
0x4F
Name
Calibrated value channel V, K, E
Calibrated value channel W, L, F
Calibrated value channel W, L, F
Calibrated value channel W, L, F
Calibrated value channel W, L, F
<D7> <D6> <D5> <D4> <D3> <D2> <D1> <D0>
CAL CHAN0_3
CAL CHAN0_0
CAL CHAN0_1
CAL CHAN0_2
CAL CHAN0_3
FW control
FW byte count
FW byte count
FW payload
DEV SEL
COEF DATA
COEF DATA
COEF DATA
COEF DATA
COEF READ
COEF WRITE
START STOP
BYTES_
TRANSF
ERRED
LOCK
SWITC
H
Second
Slave
FW_BYTE_COUNT_H
FW_BYTE_COUNT_L
HW version H
First
Slave
BANK1 ERROR
CHKSU
M
SELECT DATA
COEF_DATA_0
COEF_DATA_1
COEF_DATA_2
COEF_DATA_3
COEF_READ
COEF_WRITE
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Detailed Description
Detailed Register Descriptions
Figure 27:
HW Version Registers
Addr: 0x00,0x01
Bit Bit Name
15:8
7:0
HW version H
HW version L
Default Access
0x40
0x41
R
R
HW Version
Bit Description
Device type
HW version
Figure 28:
FW Version Registers
Addr: 0x02,0x03
Bit Bit Name
15:8 FW version H
7:0 FW version L
Default Access
0 R/W
0 R/W
FW Version
Bit Description
Set register 0x02, 0x03 to 0x01 to 0x03 to get each firmware positions high byte
0x01: MAJOR version [15..8]
0x02: PATCH version [15..8]
0x03: BUILD version [15..8]
Figure 29:
Configuration Register
Bit
Addr: 0x04
Bit Name
7:0
6
SRST
INT
5:4 GAIN
3:2
1
0
BANK
DATA_RDY
FRST
Default Access
0
0
01
10
0
0
W
R/W
R/W
R/W
R
W
Configuration
Bit Description
[W] software reset [R] gain error
Enable interrupt pin
Gain configuration: b00=1x; b01=3.7x; b10=16x; b11=64x
Measurement mode: b00=Mode 0: 4 channels b01=Mode 1: 4 channels b10=Mode 2: All 6 channels b11=Mode 3: One-Shot operation of mode 2
Data ready to read
Factory reset
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AS7265x −
Detailed Description
The maximum sensitivity value depends on the integration time. For every 2.78ms of integration time, the maximum sensitivity value increases by 1024 counts. This means that to be able to reach the full sensitivity scale, the sensitivity has to be at least 64*2.78ms.
Figure 30:
Integration Time Register
Bit
Addr: 0x05
Bit Name
7:0
INTEGRATION_
TIME
Default
20
Access
R/W
Integration Time
Bit Description
0x00
0x01
...
0x11
Integration time = <value> * 2.8ms (applies to all channels); value: 1-255;Return 0 - read error
Value
Integration
Cycles
Integration
Time
Maximum
ADC
Value
1
2
...
18
2.78ms
5.56ms
...
50ms
1023
2047
...
18431
0x40
...
0xFF
65
...
256
181ms
...
711ms
65535
...
65535
Figure 31:
Temperature Register
Bit
Addr: 0x06
Bit Name
7:0 Temperature
Default
-
Access
R
Temperature
Bit Description
Temperature of the device in °C
Read value from every device in dependency of register DEV_SEL
From -127 to 127
Return -128: Means error
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Detailed Description
Figure 32:
LED Configuration Register
Bit
7
5:4
3
2:1
0
Addr: 0x07
Bit Name
READ_ERR
LED_DRV
ENABLE LED_
DRV
LED_INT
ENABLE LED_
INT
Default Access
0 R
00
0
01
0
R/W
R/W
R/W
R/W
LED Configuration
Bit Description
Error while reading status
LED_DRV current limit: b00=12.5mA; b01=25mA; b10=50mA; b11=100mA
Device depends on register DEV_SEL
Enable LED DRV
Device depends on register DEV_SEL
Current limit: b00=1mA; b01=2mA; b10=4mA; b11=8mA
Device depends on register DEV_SEL
Enable LED IND
Device depends on register DEV_SEL
Figure 33:
RAW Value Channel R,G,A Register
Addr: 0x08,0x09
Bit Bit Name
15:8
7:0
RAW value H
Raw value L
Default
-
-
Figure 34:
RAW Value Channel S,H,B Register
Addr: 0x0A,0x0B
Bit Bit Name
15:8
7:0
RAW value H
Raw value L
Default
-
-
Access
R
R
R
R
RAW Value Channel R,G,A
Bit Description
Channel R or J or D depends on register DEV_SEL
RAW Value Channel S,H,B
Access Bit Description
Channel S or I or C depends on register DEV_SEL
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AS7265x −
Detailed Description
Figure 35:
RAW Value Channel T,I,C Register
Addr: 0x0C/0x0D
Bit Bit Name
15:8
7:0
RAW value H
Raw value L
Default
-
-
Figure 36:
RAW Value Channel U,J,D Register
Addr: 0x0E,0x0F
Bit Bit Name
15:8
7:0
RAW value H
Raw value L
Default
-
-
Figure 37:
RAW Value Channel V,K,E Register
Addr: 0x10,0x011
Bit Bit Name
15:8
7:0
RAW value H
Raw value L
Default
-
-
Figure 38:
RAW Value Channel W,L,F Register
Addr: 0x12,0x013
Bit Bit Name
15:8
7:0
RAW value H
Raw value L
Default
-
-
RAW Value Channel T,I,C
Access Bit Description
R
R
Channel T or G or A depends on register DEV_
SEL
RAW Value Channel U,J,D
Access Bit Description
R
R
Channel U or H or B depends on register DEV_
SEL
RAW Value Channel V,K,E
Access Bit Description
R
R
Channel V or K or E depends on register DEV_SEL
RAW Value Channel W,L,F
Access Bit Description
R
R
Channel W or L or F depends on register DEV_
SEL
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Detailed Description
Figure 39:
Calibrated Value Channel R,G,A Register
Addr:
0x17,0x016,0x15,0x014
Bit Bit Name
31:24
23:16
15:8
7:0
CAL CHAN0_3
CAL CHAN0_2
CAL CHAN0_1
CAL CHAN0_0
Default
FF
FF
FF
FF
Calibrated Value Channel R,G,A
Access
R
R
R
R
Bit Description
Channel R or J or D depends on register DEV_
SEL
Figure 40:
Calibrated Value Channel S, H, B Register
Addr:
0x1B,0x01A,0x19,0x018
Bit Bit Name
31:24
23:16
15:8
7:0
CAL CHAN1_3
CAL CHAN1_2
CAL CHAN1_1
CAL CHAN1_0
Default
FF
FF
FF
FF
Calibrated Value Channel S,H,B
Access
R
R
R
R
Bit Description
Channel S or I or C depends on register DEV_
SEL
Figure 41:
Calibrated Value Channel T, I, C Register
Addr:
0x1F,0x01E,0x1D,0x01C
Bit Bit Name
31:24
23:16
15:8
7:0
CAL CHAN2_3
CAL CHAN2_2
CAL CHAN2_1
CAL CHAN2_0
Default
FF
FF
FF
FF
Calibrated Value Channel T,I,C
Access
R
R
R
R
Bit Description
Channel T or G or A depends on register DEV_
SEL
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AS7265x −
Detailed Description
Figure 42:
Calibrated Value Channel U, J, D Register
Addr:
0x23,0x022,0x21,0x20
Bit Bit Name
31:24
23:16
15:8
7:0
CAL CHAN3_3
CAL CHAN3_2
CAL CHAN3_1
CAL CHAN3_0
Default
FF
FF
FF
FF
Calibrated Value Channel U,J,D
Access
R
R
R
R
Bit Description
Channel U or H or B depends on register DEV_
SEL
Figure 43:
Calibrated Value Channel V, K, E Register
Addr:
0x27,0x026,0x25,0x24
Bit Bit Name
31:24
23:16
15:8
7:0
CAL CHAN4_3
CAL CHAN4_2
CAL CHAN4_1
CAL CHAN4_0
Default
FF
FF
FF
FF
Calibrated Value Channel V,K,E
Access
R
R
R
R
Bit Description
Channel V or K or E depends on register DEV_
SEL
Figure 44:
Calibrated Value Channel W, L, F Register
Addr:
0x2B,0x02A,0x29,0x28
Bit Bit Name
31:24
23:16
15:8
7:0
CAL CHAN5_3
CAL CHAN5_2
CAL CHAN5_1
CAL CHAN5_0
Default
FF
FF
FF
FF
Calibrated Value Channel W,L,F
Access
R
R
R
R
Bit Description
Channel W or L or F depends on register DEV_
SEL
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Detailed Description
Figure 45:
FW Control Register
2
1
4
3
0
Bit
Addr: 0x48
Bit Name
7
6
5
START
STOP
BYTES_
TRANSFERRED
LOCK
SWITCH
BANK1
ERROR
CHKSUM
Default
Figure 46:
FW Byte Count Register
Addr: 0x49,0x4A
Bit Bit Name
15:8
7:0
FW_BYTE_
COUNT_H
FW_BYTE_
COUNT_L
Default
0
Figure 47:
FW Payload Register
Bit
Addr:0x4B
Bit Name
7:0 HW version H
Default
0
Access
R/W
W
R
R/W
W
R
R
R
FW Control
Bit Description
Set bit once to configure the device update
Reset firmware update state machine
All 56kbytes are transferred
Lock this firmware for the next start
Switch between both firmware
Set if bank 1 is active, else bank 2
Error occurred while firmware update
Checksum of other bank is valid
Access
FW Byte Count
Bit Description
R
Byte counter of transferred image
R
Access
R/W
FW Payload
Bit Description
Transfer of firmware byte
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AS7265x −
Detailed Description
Figure 48:
DEV SEL Register
Bit
Addr: 0x4F
Bit Name
5
5
SECOND
SLAVE
FIRST SLAVE
Default
0
0
1:0 SELECT DATA 00
Access
R
R
R/W
DEV SEL
Bit Description
Second slave Available
First slave available
0x00: Select master data
0x01: Select first slave data
0x02: Select second slave data
Figure 49:
COEF DATA Register
Addr:
0x53,0x52,0x51,0x50
Bit Bit Name
31:24
23:16
15:8
7:0
COEF_DATA_
3
COEF_DATA_
2
COEF_DATA_
1
COEF_DATA_
0
Default
Figure 50:
COEF READ Register
Bit
Addr:0x54
Bit Name
7:0 COEF_READ
Default
Access
R/W
R/W
R/W
R/W
COEF DATA
Bit Description
Data heap to read and write calibration data
Access
R/W
COEF READ
Bit Description
Set sub addresses to read different calibration data from COEF_DATA register
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AS7265x −
Detailed Description
Figure 51:
COEF WRITE Register
Bit
Addr:0x55
Bit Name Default
7:0 COEF_WRITE
Access
R/W
COEF WRITE
Bit Description
Set sub addresses to write different calibration data from COEF_DATA register to persistent memory
AS72651 I
2
C Firmware (FW) Update Procedure
•
In the FW Update Control register set the Start_XFR bit to
1.
•
Write 56k of data to the FW Download register starting with the first byte in the ams file, then proceed the end of the ams 56k file with consecutive writes.
•
If desired read the FW Byte Count registers to see which byte is expected to be written next into the FW Download register.
•
When the download file is completely written, confirm the action by using the FW Update Control register bit XFR_
56k (should =1 if 56k has been downloaded).
•
In the FW Update Control register, set the Toggle bit to 1 which will reboot the AS72651 with the new FW after checking the new FW for correct CRC. If the CRC is incorrect the toggle bit will not change and the new FW will not be used.
Figure 52:
Firmware Byte Count High Byte
Addr: 0x60/0xE0
Bit
5
4
7
6
3
2:0
Bit Name
Start_XFR
Kill_XFR
XFR_56K
Reserved
Toggle
Reserved
Default Access
0
0
0
R/W
R/W
R
0 R/W
Control_Setup
Bit Description
Set to 1 to start firmware update
Set to 1 to stop firmware update.
Set to 1 when 56k bytes have been downloaded.
Reserved, do not use.
Set to 1 to toggle firmware image partition.
Reserved, do not use.
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AS7265x −
Detailed Description
Figure 53:
Firmware Byte Count, High Byte Register
Addr: 0x61/0xE1
Bit Bit Name
7:0 FWBC_HIGH
Firmware Byte Count, High Byte
Default Access Bit Description
R
Firmware byte address to be downloaded next, High
Byte
Figure 54:
Firmware Byte Count, Low Byte Register
Addr: 0x62/0xE2
Bit
7:0
Bit Name
FWBC_LOW
Firmware Byte Count, Low Byte
Default Access Bit Description
R
Firmware byte address to be downloaded next, Low
Byte
Figure 55:
Firmware Download Register
Addr: 0x63/0xE3
Bit Bit Name
7:0 FWLOAD
Default Access
R/W
Firmware Download
Bit Description
Firmware byte to be downloaded
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AS7265x −
Detailed Description
UART Command Interface
If selected by the I2C_ENB pin setting, the UART module implements the TX and RX signals as defined in the RS-232 / V.24 standard communication protocol. Serial flash EPROM is a required operating companion device to enable the UART command interface.
Figure 56:
Flash Memory Overview
Serial Flash
AT25SF041xx
AT25DF041xx
MX25L4006ExxI-12G
SST25PF040C
W25X40CLSNIG
LE25U40CMD
Manufacturer
Adesto Technologies
Adesto Technologies
Macronix
Microchip Technology
Winbond Electronics
ON Semiconductor
Note(s):
1. Where xx= alternative packages.
UART Feature List
•
Full duplex operation (independent serial receive and transmit registers).
•
Factory set to 115.2k Baud
•
Supports serial frames with 8 Data Bits, no Parity and 1
Stop Bit.
Operation
Transmission
If data is available in the transmit FIFO, it will be moved into the output shift register and the data will be transmitted at the configured Baud Rate, starting with a Start Bit (logic zero) and followed by a Stop Bit (logic one).
Reception
At any time, with the receiver being idle, if a falling edge of a start bit is detected on the input, a byte will be received and stored in the receive FIFO. The following Stop Bit will be checked to be logic one.
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AS7265x −
Detailed Description
Figure 57:
UART Protocol
TX
Start Bit
Always Low
D0
D1 D2 D3
T bit
=1/Baude Rate
Data Bits
D4 D5 D6
D7
Stop Bit Next Start
Always High
D0
RX
D0
D1 D2
Start Bit detected
After T bit
/2: Sampling of Start Bit
After T bit
: Sampling of Data
D3 D4 D5 D6
D7 D0
Sample Points
AT Command Interface
The microprocessor interface to control the AS72651
Spectral_
ID
sensor(s) is via AT Commands across the UART interface. The
AS72651 provides a text-based serial command interface borrowed from the “AT Command” model used in early Hayes modems.
For example:
Read DATA value: ATDATA
→
<data>OK
Set the gain of the sensor to 1x: ATGAIN=0
→
OK
The AT Command Interface, shown below provides access to the
Spectral_ID
engine’s control and configuration functions.
Figure 58:
AT Command Interface Block Diagram
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MCU
AT Commands
RX
TX
AT
Command
Interface
Spectral_ID
Engine
AS72651 ams Datasheet
[v1-04] 2018-Jul-09
AS7265x −
Detailed Description
In the AT Commands figure below, numeric values may be specified with no leading prefix, in which case they will be interpreted as decimals, or with a leading “0x” to indicate that they are hexadecimal numbers. The commands are loosely grouped into functional areas. Texts appearing between angle brackets
(‘<‘and ‘>‘) are commands or response arguments. A carriage return character, a linefeed character, or both may terminate commands and responses. Note that any command that encounters an error will generate the “ERROR” response shown, for example, in the NOP command at the top of the first table, but has been omitted elsewhere in the interest of readability and clarity.
Note(s):
The
shows the complete list of all AS7265x
AT commands.
Figure 59:
AS7265x AT Commands
Commands
AT
ATVERSW
ATVERHW
ATTEMP
ATDATA
ATCDATA
Direction
R
R
R
R
R
R
Description
Status
NOP
Return the current software version number
Returns the system hardware as a HEX value of the form
PRDTx where
P=PartID and
R=ChipRevision and
DT= DeviceType
Read the current device temperature in degrees Celsius
Format
-
DEC
HEX
DEC
Read all six raw vales per device(<65535)
DEC
Value Range
-
<MAJOR.PATCH.
BUILD>
<0xPRDT>
PR = 40
DT = 15
Send three temperature values (Format:
A, B, C)
< R, S, T, U, V, W, G, H,
I, J, K, L, A, B, C, D, E,
F>
Read all six calibrated values per device.
Returns comma- separated 32-bit floating point values.
DEC
< R, S, T, U, V, W, G, H,
I, J, K, L, A, B, C, D, E,
F>
Default
-
-
0x4041
-
-
-
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AS7265x −
Detailed Description
Commands
ATINTTIME
ATGAIN
ATINTRP
ATTCSMD
ATINTRVL
Direction
R/W
R/W
R/W
R/W
R/W
Description
Control
Set sensor integration time.
Integration time =
<value> * ~2.8ms.
Set sensor gain: 0=1x gain, 1=3.7x, 2=16x,
3=64x
Format
DEC
DEC
Value Range
1-255
0-3
Enable/Disable interrupt pin
Set measurement mode
DEC
DEC
0 - Disable
1 - Enable Interrupt pin functionality
0: Captures bank0 (1 integration period)
1: Captures bank1 (1 integration period)
2: Captures bank0+ bank1(2 integration period)
3:Captures bank0+ bank1 in one shot mode (2 integration period)
Set the sampling interval as an integer multiple of the integration time. The
<value> is an integer between [1...255].
A sampling interval=1 implies a sampling rate of 1x the current integration time.
A sampling interval=255 implies a slow sampling rate of 255 times the current integration time
DEC 1…255
Default
20
1
0
2
1
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AS7265x −
Detailed Description
Commands
ATBURST
ATLED0
ATLED1
ATLED2
ATLED3
ATLED4
ATLED5
ATLEDC
Direction
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Sends a number of calibrated data without separate requests second parameter for the burst mode is optionally format:
Send: ATBURST=10,0 or ATBURST=10
Read: ATBURST
≥
10,0 OK
Format
DEC
Value Range
BURST NUMBER:
0 - Burst mode is deactivated
1-254 - Number of burst transfers
255 - Send unlimited bursts (stops with
ATBURST=0)
Default
0
DEC
DEC
BURST MODE:
0 - Raw values
(default, like
ATDATA)
1 - Calibrated values
(like ATCDATA)
0 - LED off
1 - LED on
0 - LED off
1 - LED on
1
0
Enables or disables the indication LED
Enables or disables the driver LED
Enables or disables the indication LED for first I
2
C slave
Enables or disables the driver LED for first
I
2
C slave
Enables or disables the indication LED for second I
2
C slave
Enables or disables the driver LED for second I
2
C slave
DEC
DEC
DEC
DEC
0 - LED off
1 - LED on
0 - LED off
1 - LED on
0 - LED off
1 - LED on
0 - LED off
1 - LED on
1
0
1
0
Sets LED_IND and
LED_DRV current
(for master only)
HEX
[1...0] LED_IND: b00=1mA; b01=2mA; b10=4mA; b11=8mA
[5...4] LED_DRV: b00=12.5mA; b01=25mA; b10=50mA; b11=100mA
0x00
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AS7265x −
Detailed Description
Commands
ATLEDD
ATLEDE
ATFRST
ATSRST
ATSCLx
ATFWU
ATFW
Direction
R/W
R/W
W
W
R/W
W
W
Description
Sets LED_IND and
LED_DRV current for first I
2
C slave
Sets LED_IND and
LED_DRV current for second I
2
C slave
Factory Reset. Stored values are reset to
‘Factory’ defaults.
Afterwards a software reset is started.
Software reset
Calibration Values
-
-
Read/Write scalar for the raw values
(x=0...17)
Firmware Update
DEC
Starts firmware update process and transfer the bin file checksum
Download new firmware.
Up to 7 bytes of FW image at a time (14 hex bytes with no leading or trailing 0x).
Repeat command till all 56kBytes of firmware are downloaded
-
-
Format
HEX
HEX
Value Range
[1...0] LED_IND: b00=1mA; b01=2mA; b10=4mA; b11=8mA
[5...4] LED_DRV: b00=12.5mA; b01=25mA; b10=50mA; b11=100mA
[1...0] LED_IND: b00=1mA; b01=2mA; b10=4mA; b11=8mA
[5...4] LED_DRV: b00=12.5mA; b01=25mA; b10=50mA; b11=100mA
-
-
-
HEX STRING
(without 0x), max. 7 bytes
Default
0x00
0x00
-
p2ram value
-
-
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AS7265x −
Detailed Description
Commands
ATFWS
ATFWL
ATFWC
ATFWA
Direction
W
W
Description
Tests the checksum on the non-active FW partition and, if correct, switches active partition. This is a toggle and used to toggle between the 2 FW partitions.
Note: The first 5 bytes in page 0 are not touched. It is only a temporary switch and must be used to check the new firmware whether the communication works!
This command locks the current firmware to starts on power cycles. It rewrites the first five bytes in page0!
Format
-
-
Value Range
-
-
R
This command gives information about the current firmware state
-
Bit0 - Checksum of non-active firmware
OK
Bit1 - Error occurred
Bit2 - Bank 1 active
Bit3 - Not used
Bit4 - Current firmware is locked
Bit5 - 56kBytes transferred
Bit6 - Not used
Bit7 - Firmware update active
W
Only for backward compatibility to support old firmware, update mechanism.
Always returns with
OK. Because of flash devices, it is not possible to increment the address separately (page erase necessary!)
-
Default
-
-
-
-
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AS7265x −
Application Information
Application Information
Figure 60:
Typical AS7265x 18-Channel Application Circuit
+5V 3V3
R11
200R
D9
LED
C7
100nF
GND
C8
1u0
3V3
RESN TP9
R10
10k
D11
GRN
RESN
GND
LED_651
LED_IND
15
18
17
14
16
2
U3
VDD1
VDD2
RESN
GND
LED_DRV
LED_IND
--->
<---
TP10
COMM_RX
COMM_TX
INT
INT
11
12
13
RX/SCL_S
TX/SDA_S
INT
AS72651
+5V 3V3
R19
200R
D12
LED
C10
100nF
GND
C11
1u0
SLV1_RESN
16
2
17
14
U4
VDD1
VDD2
RESN
GND
GND
LED_652
15
18
LED_DRV
LED_IND
11
12
13
NC
NC
INT
AS72652
+5V 3V3
R23
200R
D13
LED
C12
100nF
GND
C13
1u0
SLV2_RESN
GND
LED_653
U5
16
2
17
14
VDD1
VDD2
RESN
GND
15
18
LED_DRV
LED_IND
11
12
13
NC
NC
INT
AS72653
CSN_EE
SPI_MOSI
SPI_SCK
SPI_MISO
FLASH 3V3 C9
1u0
5
6
2
3
1
U6
CS
DI
CLK
DO
WP
7
HOLD
AT25SF041
GND
GND
AS72651
AS72652
AS72653
NC
NC
NC
NC
NC
NC
NC
NC
NC
SDA_S
SCL_S
10
9
19
20
1
5
4
3
8
7
6
NC
CSN
MISO
MOSI
SCK
I2C_ENB
NC
SLV2_RESN
SLV1_RESN
SDA_M
SCL_M
10
9
19
20
1
4
3
8
7
6
5
3V3
R17
10k
CSN_EE
SPI_MISO
SPI_MOSI
SPI_SCK
I2C_ENA
R18
0R
GND
SLV2_RESN
TP11 TP12
SLV1_RESN
SLV2_RESN
SLV1_RESN
NOTE
R18 placed - UART (default)
R18 not placed - I
²
C
3V3
R13
10k
R14
10k
R15
2k2
R16
2k2
SDA
SCL
TP13
TP14
SDA
SCL
SDA_S
SCL_S
NC
NC
NC
NC
NC
NC
NC
NC
NC
19
20
1
10
9
5
4
3
8
7
6
SDA
SCL
3V3
GND
Sensorinterface
ESP Board
SDA
SCL
J3
SQT4RATHF
1
2
3
4
D6 D7 D8
GND
CSN_EE
SPI_MISO
SPI_SCK
SPI_MOSI
RESN
Programming header for FLASH
3V3
6
5
4
8
7
3
2
1
J2
FH34S-8S-0.5SH(50)
GND
SDA
SCL
SPI_MISO
SPI_SCK
CSN_EE
Alternative programming header for FLASH (NEW)
7427927161
600R/250mA
L1
VDD_PROG
J4
1 2
3 4
5 6
TC2030-NL
SPI_MOSI
GND
C17
100nF
GND
Q1
DTC113ZUA
GND
RESN
Note(s):
1. For each AS7265x device, orientation of the device aperture to any light source(s) will determine spectral content to be measured.
For example with the proper orientation, sensors on the AS72651 can be used to measure light from the LEDs on the AS72652 and/or
AS76253.
2. The AS72651 is required while the AS72652 and AS72653 are both optional for a total solution of 6, 12 or 18 channels.
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AS7265x −
Package Drawings & Markings
Package Drawings & Markings
Figure 61:
Package Drawing
RoHS
Green
Note(s):
1. All dimensions are in millimeters.
2. XXXXX = tracecode.
3. Unless otherwise specified tolerances are: Angular (±.5°), Two Place Decimal (±.1), Three Place Decimal (±.05).
4. Contact finish is Au.
5. This package contains no lead (Pb).
6. This drawing is subject to change without notice.
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PCB Pad Layout
AS7265x −
PCB Pad Layout
Suggested PCB pad layout guidelines for the LGA device are shown. Flash Gold is recommended as a surface finish for the landing pads.
Figure 62:
Recommended PCB Pad Layout (Top View)
Unit: mm
0.65
1
0.40
0.55
5
4.05
Note(s):
1. Unless otherwise specified, all dimensions are in millimeters.
2. Add 0.05mm all around the nominal lead width and length for the PCB pad land pattern.
3. This drawing is subject to change without notice.
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AS7265x −
PCB Pad Layout
In order to prevent interference, avoid trace routing feedthroughs with exposure directly under the AS7265x devices. An example routing is illustrated in the
Figure 63:
Typical Layout Routing ams Datasheet
[v1-04] 2018-Jul-09
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Mechanical Data
Figure 64:
Tape & Reel Information
AS7265x −
Mechanical Data
Note(s):
1. All dimensions in millimeters unless of otherwise stated.
2. Measured from centreline of sprocket hole to centreline of pocket.
3. Cumulative tolerance of 10 sprocket holes is ±0.20.
4. Measured from centreline of sprocket hole to centreline of pocket.
5. Other material available.
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AS7265x −
Soldering & Storage Information
Soldering & Storage
Information
Figure 65:
Solder Reflow Profile
Parameter
Average temperature gradient in preheating
Soak time
Time above 217
°
C(T
1
)
Time above 230
°
C(T
2
)
Time above T peak
- 10
°
C(T
3
)
Peak temperature in reflow
Temperature gradient in cooling
Soldering Information
The module has been tested and has demonstrated an ability to be reflow soldered to a PCB substrate. The solder reflow profile describes the expected maximum heat exposure of components during the solder reflow process of product on a PCB.
Temperature is measured on top of component. The components should be limited to a maximum of three passes through this solder reflow profile.
Reference
t
SOAK t
1 t
2 t
3
T peak
Device
2.5
°
C/s
2 to 3 minutes
Max 60s
Max 50s
Max 10s
260
°
C
Max -5
°
C/s
Figure 66:
Solder Reflow Profile Graph ams Datasheet
[v1-04] 2018-Jul-09
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AS7265x −
Soldering & Storage Information
Manufacturing Process Considerations
The AS72651,AS72652 and AS72653 packages are compatible with standard reflow no-clean and cleaning processes including aqueous, solvent or ultrasonic techniques. However, as an open-aperture device, precautions must be taken to avoid particulate or solvent contamination as a result of any manufacturing processes, including pick and place, reflow, cleaning, integration assembly and/or testing. Temporary covering of the aperture is allowed. To avoid degradation of accuracy or performance in the end product, care should be taken that any temporary covering and associated sealants/debris are thoroughly removed prior to any optical testing or final packaging.
Storage Information
Moisture Sensitivity
Optical characteristics of the device can be adversely affected during the soldering process by the release and vaporization of moisture that has been previously absorbed into the package.
To ensure the package contains the smallest amount of absorbed moisture possible, each device is baked prior to being dry packed for shipping.
Devices are dry packed in a sealed aluminized envelope called a moisture-barrier bag with silica gel to protect them from ambient moisture during shipping, handling, and storage before use.
Shelf Life
The calculated shelf life of the device in an unopened moisture barrier bag is 12 months from the date code on the bag when stored under the following conditions:
•
Shelf Life: 12 months
•
Ambient Temperature: <40°C
•
Relative Humidity: <90%
Rebaking of the devices will be required if the devices exceed the 12 month shelf life or the Humidity Indicator Card shows that the devices were exposed to conditions beyond the allowable moisture region.
ams Datasheet
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AS7265x −
Soldering & Storage Information
Floor Life
The module has been assigned a moisture sensitivity level of
MSL 3. As a result, the floor life of devices removed from the moisture barrier bag is 168 hours from the time the bag was opened, provided that the devices are stored under the following conditions:
Floor Life: 168 hours
Ambient Temperature: <30°C
Relative Humidity: <60%
If the floor life or the temperature/humidity conditions have been exceeded, the devices must be rebaked prior to solder reflow or dry packing.
Rebaking Instructions
When the shelf life or floor life limits have been exceeded, rebake at 50°C for 12 hours.
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AS7265x −
Ordering & Contac t Information
Ordering & Contact Information
Figure 67:
Ordering Information
Ordering
Code
Package Marking
AS72651-BLGT 20-pin LGA
AS72652-BLGT 20-pin LGA
AS72653-BLGT 20-pin LGA
Description
AS7265
AS7266
AS7267
Smart 6-Channel NIR Spectral_ID
Sensor with Electronic Shutter and 18-Channel AS7265x Master
Capability
Smart 6-Channel NIR Spectral_ID
Sensor with Electronic Shutter
Smart 6-Channel Spectral_ID
Sensor with Electronic Shutter
Delivery Form
Delivery
Quantity
Tape & Reel
Tape & Reel
Tape & Reel
2000 pcs/reel
2000 pcs/reel
2000 pcs/reel
Note(s):
1. The AS72651 is required for operation of either the AS72652 or AS72653.
2. A companion flash memory is required for functionality and should be ordered from the flash memory supplier or their authorized channels. See approved flash memory manufacturers in
Figure 56 . For latest update of the flash memory list contact regional FAE
support.
3. AS72651 flash memory software is available from
ams
.
Buy our products or get free samples online at: www.ams.com/Products
Technical Support is available at: www.ams.com/Technical-Support
Provide feedback about this document at: www.ams.com/Document-Feedback
For further information and requests, e-mail us at: [email protected]
For sales offices, distributors and representatives, please visit: www.ams.com/Contact
Headquarters
ams AG
Tobelbader Strasse 30
8141 Premstaetten
Austria, Europe
Tel: +43 (0) 3136 500 0
Website: www.ams.com
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AS7265x −
RoHS Compliant & ams Green Statement
RoHS Compliant & ams Green
Statement
RoHS:
The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed
0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes.
ams Green (RoHS compliant and no Sb/Br):
ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants
(Br or Sb do not exceed 0.1% by weight in homogeneous material).
Important Information:
The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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Copyrights & Disclaimer
AS7265x −
Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten,
Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of
Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed.
ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services.
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Document Status
Document Status
Document Status
Product Preview
Preliminary Datasheet
Datasheet
Datasheet (discontinued)
Product Status
Pre-Development
Pre-Production
Production
Discontinued
Definition
Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice
Information in this datasheet is based on products in the design, validation or qualification phase of development.
The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice
Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of
Trade
Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of
Trade, but these products have been superseded and should not be used for new designs
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AS7265x −
Revision Information
Revision Information
Changes from 1-03 (2017-Oct-17) to current revision 1-04 (2018-Jul-09)
Updated text under General Description
Updated text under Key Benefits & Features
Updated Figure 2 (AS7265x Chip- Set Block Diagram)
Renamed Figure 3 to “Pin Diagram of AS72651,AS72652 and AS72653 (Top View)”
Updated Figure 4 (AS72651 pin description)
Added Figure 5 (AS72652 and AS72653 pin description)
Updated text under “Absolute Maximum Ratings”
(replaced AS72651 with AS7265x)
Updated titles names in Figure 6,8 to AS7265x
Updated title name in Figure 7 and notes under it
Updated text under Optical Characteristics
Moved Figure “AS7265x LGA Average Field of View” under “Optical Characteristics”
Updated Figure 14
Updated Figure 16
Updated Figure 18
Updated Figure 19
Updated title name in figure 20 and notes under it
Updated text under AS7265x 18-Channel Spectral_ID Detector Overview
Updated text under AS7265x LED_IND Controls
Updated text under Interrupt Operation
Updated text under Required Flash Memory
Updated text under I²C Feature List
Updated I²C Virtual Register Byte Write
Updated I²C Virtual Register Byte Read
Updated Figure 26
Updated text under Detailed Register Descriptions including Figure 27 to 51
Updated text under UART Command Interface
Added Figure 56(List of ams approved flash manufacturer)
Updated text under Figure 58
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AS7265x −
Revision Information
Changes from 1-03 (2017-Oct-17) to current revision 1-04 (2018-Jul-09)
Updated Figure 59 (AS7265x AT Commands) and text above it
Updated Figure 60 (Typical AS7265x 18-Channel Application Circuit)
Updated text under Manufacturing Process Considerations
(replaced AS72651 with AS72651, AS72652,AS72653)
Updated note under Figure 67
Note(s):
1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
2. Correction of typographical errors is not explicitly mentioned.
Page
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Content Guide
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AS7265x −
Content Guide
1 General Description
4 Pin Assignments
7 Absolute Maximum Ratings
8 Electrical Characteristics
13 Typical Operating Characteristics
19 Detailed Description
19 AS7265x 18-Channel Spectral_ID Detector
19 Channel Data Conversion of the AS7265x
22 Electronic Shutter with AS7265x LED_DRV Driver Control
23 I²C Feature List
24 I²C Virtual Register Write Access
25 I²C Virtual Register Byte Write
26 I²C Virtual Register Byte Read
27 4-Byte Floating-Point (FP) Registers
31 Detailed Register Descriptions
39 AS72651 I2C Firmware (FW) Update Procedure
41 UART Feature List
41 Operation
41 Transmission
41 Reception
42 AT Command Interface
48 Application Information
49 Package Drawings & Markings
50 PCB Pad Layout
52 Mechanical Data
53 Soldering & Storage Information
54 Manufacturing Process Considerations
54 Moisture Sensitivity
55 Rebaking Instructions
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Content Guide
56 Ordering & Contact Information
57 RoHS Compliant & ams Green Statement
58 Copyrights & Disclaimer
59 Document Status
60 Revision Information
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Key features
18-channel spectrometry chip-set solution
Compact design
Spectral range from 410nm to 940nm
Programmable LED drivers
Built-in apertures
UART or I²C slave digital interface
Gaussian filters integrated into standard CMOS silicon
Frequently asked questions
The spectral range of the AS7265x is from 410nm to 940nm.
The AS7265x has 18 channels.
The AS7265x has a UART or I²C slave digital interface.
Yes, the AS7265x has programmable LED drivers.
The AS7265x comes in a 20-pin LGA package measuring 4.5mm x 4.7mm x 2.5mm.