Power control (PWR) RM0471
Stop1 mode
Mode entry
Mode exit
Wakeup latency
Table 29. Stop1 mode
Description
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP bit is set in Cortex System control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = “001” in PWR_CR1 and/or PWR_C2CR1 or higher
On Return from ISR while:
– SLEEPDEEP bit is set in Cortex System control register
– SLEEPONEXIT = 1
– No interrupt is pending
– LPMS = “001” in PWR_CR1 and/or PWR_C2CR1 or higher
Note: To enter Stop1 mode, all EXTI line pending bits (in EXTI pending register
(EXTI_PR1)
, and EXTI pending register (EXTI_PR2) ), and the peripheral
flags generating wakeup interrupts must be cleared. Otherwise, the Stop1 mode entry procedure is ignored and program execution continues.
If WFI or Return from ISR was used for entry:
Any EXTI line configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC). The interrupt source can be external
interrupts or peripherals with wakeup capability. Refer to Table 54: CPU1 vector table
and Table 55: CPU2 vector table
.
If WFE was used for entry and SEVONPEND = 0:
Any EXTI line configured in event mode. Refer to Section 13.5: Interrupt list .
If WFE was used for entry and SEVONPEND = 1:
Any EXTI line configured in Interrupt mode (even if the corresponding EXTI
Interrupt vector is disabled in the NVIC). The interrupt source can be external
interrupts or peripherals with wakeup capability. Refer to Table 54: CPU1 vector table
and Table 55: CPU2 vector table
.
Wakeup event: refer to Section 13.5: Interrupt list .
Longest wakeup time between: MSI or HSI16 wakeup time and regulator wakeup time from Low-power mode + Flash memory wakeup time from Stop1 mode.
Note:
The Stop2 mode is based on the CPU deepsleep mode combined with peripheral clock gating. In Stop2 mode, all clocks in the V
CORE
HSI16 and the HSE oscillators are disabled.
domain are stopped, the PLL, the MSI, the
SRAM1, SRAM2 and register contents are preserved.
The BOR is always available in Stop2 mode. The consumption is increased when thresholds higher than V
BOR0
are used.
The comparators, LPUART and LPTIM1 outputs are forced to low speed (OSPEEDy = 00) during the Stop2 mode.
I/O states in Stop2 mode
In the Stop2 mode, all I/O pins keep the same state as in the Run mode.
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RM0471 Power control (PWR)
Entering Stop2 mode
The Stop2 mode is entered as described in
Section 6.4.3
, when the SLEEPDEEP bit in the
Cortex System control register is set (see Table 30
).
Stop2 mode can only be entered from Run mode. It is not possible to enter Stop2 mode from the Low-power run mode.
If Flash memory programming is ongoing, the Stop2 mode entry is delayed until the memory access is finished.
If an access to the APB domain is ongoing, The Stop2 mode entry is delayed until the APB access is finished.
In Stop2 mode, the following features can be selected by programming individual control bits:
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a Reset. See
Section 25.3: IWDG functional description
.
real-time clock (RTC): this is configured by the RTCEN bit in the
RCC backup domain control register (RCC_BDCR)
Internal RC oscillator (LSI): this is configured by the LSIxON bit in the RCC control/status register (RCC_CSR) .
External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the RCC backup domain control register (RCC_BDCR)
.
Some peripherals can be used in Stop2 mode and add consumption if they are enabled and clocked by LSI or LSE, or when they request the HSI16 clock, namely LPTIM1.
The PVD can be used in Stop2 mode. If not needed, it must be disabled by software to reduce power consumption.
The ADC and the temperature sensor can consume power during Stop2 mode, unless they are disabled before entering this mode.
All the peripherals that cannot be enabled in Stop2 mode must be either disabled by clearing the Enable bit in the peripheral itself, or put under reset state by setting the corresponding bit in the
RCC AHB1 peripheral reset register (RCC_AHB1RSTR)
RCC AHB2 peripheral reset register (RCC_AHB2RSTR)
RCC AHB3 and AHB4 peripheral reset register (RCC_AHB3RSTR)
RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1)
RCC APB1 peripheral reset register 2 (RCC_APB1RSTR2)
RCC APB2 peripheral reset register (RCC_APB2RSTR)
RCC APB3 peripheral reset register (RCC_APB3RSTR)
Exiting Stop2 mode
The Stop2 mode is exit according
Section 6.4.4
(see
Table 30 ).
When exiting Stop2 mode by issuing an interrupt or a wakeup event, the HSI16 oscillator is
selected as system clock if the bit STOPWUCK is set in RCC clock configuration register
(RCC_CFGR)
. The MSI oscillator is selected as system clock if the bit STOPWUCK is cleared. The wakeup time is shorter when HSI16 is selected as wakeup system clock. The
MSI selection allows wakeup at higher frequency, up to 48 MHz.
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