Option bytes programming. STMicroelectronics Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4, STM32WB50CG, STM32WB30CE

PDF

Документ

RM0471

3.4.2

Note:

Embedded Flash memory (FLASH)

Option bytes programming

After reset, the options related bits in the Flash memory control register (FLASH_CR)

and

Flash memory CPU2 control register (FLASH_C2CR)

are write-protected. To run any operation on the option bytes page, the option lock bit OPTLOCK in the

Flash memory control register (FLASH_CR) must be cleared. The following sequence is used to unlock

this register:

Unlock the FLASH_CR with the LOCK clearing sequence (refer to Unlocking the Flash memory )

2. Write OPTKEY1= 0x08192A3B in the

Flash memory option key register

(FLASH_OPTKEYR)

3. Write OPTKEY2 = 0x4C5D6E7F in the Flash memory option key register

(FLASH_OPTKEYR)

Any wrong sequence locks up the Flash memory option registers until the next system reset. In the case of a wrong key sequence, a bus error is detected and a hard fault interrupt is generated.

The User options can be protected against unwanted erase/program operations by setting the OPTLOCK bit by software.

If LOCK is set by software, OPTLOCK is automatically set as well.

In a multi-CPU system it is good practice to use semaphores to manage option programming, and prevent simultaneous option programming by the CPUs.

Modifying User options

The option bytes are programmed differently from a main memory user address.

To modify the value of User options follow the procedure below:

Clear OPTLOCK option lock bit with the clearing sequence described above

2. Write the desired options value in the options registers.

3. Check that no Flash memory operation is on going by checking the BSY bit in the

Flash memory status register (FLASH_SR) or

Flash memory CPU2 status register

(FLASH_C2SR)

Check that Flash program and erase operation is allowed by checking the PESD bit in the

Flash memory status register (FLASH_SR)

or Flash memory CPU2 status register

(FLASH_C2SR)

(these checks are recommended even if status may change due to

Flash operation requests by the other CPU, to limit the risk of receiving a bus error when modifying User options).

4. Set the Options start bit OPTSTRT in the Flash memory control register (FLASH_CR) .

5. Wait for the BSY bit to be cleared.

Any modification of the value of one option is automatically performed by erasing User option bytes pages first, and then programming all the option bytes with the values contained in the Flash memory option registers.

Secure User options

The secure option bytes Secure Flash memory start address register (FLASH_SFR) and

Flash memory secure SRAM2 start address and CPU2 reset vector register

(FLASH_SRRVR) can only be written by the secure CPU2.

RM0471 Rev 5 85/1202

116

Embedded Flash memory (FLASH) RM0471

Option byte loading

After the BSY bit is cleared, all new options are updated into the Flash memory, but not applied to the system. A read from the option registers returns the last loaded option byte values, the new options have effect on the system only after they are loaded.

Option bytes loading is performed in two cases:

– when OBL_LAUNCH bit is set in the

Flash memory control register (FLASH_CR)

– after a power reset (BOR reset or exit from Standby/Shutdown modes)

Option byte loader performs a read of the options block and stores the data into internal option registers. These internal registers configure the system and can be read by software.

Setting OBL_LAUNCH generates a reset so the option byte loading is performed under system reset.

Each option bit has also its complement in the same double word. During option loading, a verification of the option bit and its complement allows to check the loading has correctly taken place.

During option byte loading, the options are read by double word. ECC on option words is not taken into account during OBL, but only during direct SW read of option area.

If the word and its complement are matching, the option word/byte is copied into the option register.

If the comparison between the word and its complement fails, a status bit OPTVERR is set.

Mismatch values are forced into the option registers:

– for USR OPT option, the value of mismatch is all options at ‘1’, except for

BOR_LEV that is “000” (lowest threshold)

– for WRP option, the value of mismatch is the default value “No protection”

– for RDP option, the value of mismatch is the default value “Level 1”

– for PCROP, the value of mismatch is “all memory protected”

– for FSD and SFSA option, the value of mismatch is “all memories (Flash, SRAM2a and SRAM2b) secured”

– for BRSD, SBRSA, NBRSD and SNBRASA options, the value of mismatch is

“SRAM2 memory part secured”

– for DDS option, the value of mismatch is “CPU2 debug disabled”