UM1575
User manual
Spice model tutorial for Power MOSFETs
Introduction
This document describes ST’s Spice model versions available for Power MOSFETs. This is a guide designed to support user choosing the best model for his goals. In fact, it explains the features of different model versions both in terms of static and dynamic characteristics and simulation performance, in order to find the right compromise between the computation time and accuracy. For example, the self-heating model (V3 version), which accurately reproduces the thermal response of all electrical parameters, requires a considerable simulation effort.
Finally, an example shows how the self-heating model works.
Spice models describe the characteristics of typical devices and don't guarantee the absolute representation of product specifications and operating characteristics; the datasheet is the only document providing product specifications.
Although simulation is a very important tool to evaluate the device’s performance, the exact device’s behavior in all situations is not predictable, therefore the final laboratory test is necessary.
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Spice model versions
1 Spice model versions
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ST provides 6 model versions on each part number:
• partnumber_V1C
• partnumber_V1T
• partnumber_V2
• partnumber_V3
• partnumber_V4
• partnumber_TN
V1C version
It is the basic model (LEVEL =3) enclosing C oss
and C rss
modeling through capacitance profile tables. It is an empirical model, and it assumes a 27 °C constant temperature.
V1T version
It comes directly from V1C version and it also includes the package thermal modeling through a thermal equivalent network and presents two additional external thermal nodes T j and T case
. This version hasn't the dynamic link between Power MOSFET temperature and internal parameters.
V2 version
It is more advanced than V1C, in fact it takes into account the temperature dependence and capacitance profiles too. It allows the static and dynamic behavior to be reproduced by user at fixed temperatures. By using this version, the simulation of self-heating effects isn't possible.
V3 version
It comes directly from V2 version and includes the package thermal model through a thermal equivalent network and presents two additional external thermal nodes: T j
and
T case
. In this version, during each transient, the current power dissipation is calculated and a current proportional to this power is fed into the thermal network. In this way, the voltage at
T j
node contains all the information about the junction temperature, which changes internal device’s parameters. Since it is a monitoring node, usually T j
pin is not connected (however, to avoid warning messages on this node, the user has to add a floating wire - see
Figure 1
).
On contrary, T case
node has to be connected, either to a constant voltage source Vdc representing the ambient temperature or to a heat sink modeled by its own thermal network
(
Figure 1
).
V4 version
It comes directly from V3 version considering the device sited in free air. It includes the package thermal modeling through a thermal equivalent network and presents three additional external thermal nodes: T j
, T case
and T amb
. The voltage at T j
node and T case
node contains all the information about the junction temperature and case temperature which change internal device’s parameters. Since they are monitoring nodes, usually T j
and T case pins are not connected (however, to avoid warning messages on this node, the user has to
add a floating wire - see
Figure 1
). Conversely, T amb
node has to be connected: to a constant voltage source Vdc, representing the ambient temperature.
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UM1575 Spice model versions
TN version
It includes the RC thermal network only, which represents the thermal model of the package.
Its symbol has two pins: T j
and T case
.
Figure 1. Self-heating model (V3 version)
Note:
G
D
S
Zth
TJ
Tcase
25
Tamb
G
D
S
Zth
TJ
Tcase
R1
C1
R2
C2 Tamb
25
0 0
GIPD081020130954FSR
T j is a monitoring node and it is not connected; T case
is connected either by using a Vdc, representing the ambient temperature (on the left-side), or by heat-sink thermal network (on the right-side).
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Spice model symbol
2 Spice model symbol
For each model version, ST provides the appropriate symbol as shown below:
V1C version
Figure 2. Model symbols
V2 version V4 version
G
D
S
Zth
TJ
Tcase
Tamb
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V1T version
TJ
Tcase
V3 version
G
D
S
Zth
TJ
Tcase
TN version
1
TJ TCASE
2
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3
Spice models - instructions to simulate
Spice models - instructions to simulate
In Spice simulator, user has to upload the device symbol (.OLB file) and the Spice model
(.LIB file) to simulate transistors in the schematic.
3.1 Installation
In the package model, there are the following files:
•
• name.lib text file representing the model library written as a Spice code; name.olb symbol file to use the model into Orcad capture user interface.
In Capture open the menu dialog window "Pspice" "Edit Simulation Profile". Go to
"Configuration Files" tab and "Library" category. Select the library (*.lib) path by "Browse…"
button and click to "Add to Design" (see
Figure 3
)
Figure 3. Capture dialog window to select the library (*.lib)
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To include the symbol *.olb in the schematic view, open the menu dialog window "Place"
"Part" (or simply pressing "P" key in keyboard) and click the "Add Library…" button (or pressing Alt+"A") to select the file (see figure below).
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Spice models - instructions to simulate
Figure 4. Capture dialog window to include the symbol (*.olb)
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3.2
Note:
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Finally, you can simulate your circuit choosing the simulation type and parameters.
Typical simulation parameters / options
As our models contain many non-linear elements, the standard simulation parameters are often not suitable.
The following values can facilitate convergence (set them in dialog window "Pspice" "Edit
Simulation Profile" "Options" tab):
ABSTOL= 1nA
CHGTOL= 1 pC..10 pC
ITL1= 150
ITL2= 20...150
ITL4= 20...150
(best accuracy of currents)
(best accuracy of charges)
(DC and bias 'blind' iteration limit)
(DC and bias 'best guess' iteration limit)
(transient time point iteration limit)
RELTOL= 0.001...0.01
(relative accuracy of voltages and currents)
If the following error message appears during the simulation of one of device models:
==> INTERNAL ERROR -- Overflow in device..... <== you have to edit the 'PSPICE.INI' file by inserting the following line behind the headline
[PSPICE] as follows:
[PSPICE]
MathExceptions = off
......
DO NOT CHANGE ANY OTHER LINES ALREADY PRESENT
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A brief description of self-heating model (V3 version)
A brief description of self-heating model (V3 version)
Power MOSFET’s Spice models are behavioral and achieved by fitting simulated data with static and dynamic characterization results.
The behavioral model is the best approach because it reproduces the electrical and thermal behavior of the power device through a simplified physical description of the device consisting in a set of equations ruling its behavior at terminal level.
The self-heating model (V3 version) includes different analog behavioral models (ABM) to describe resistors, voltage and current generator, which are temperature-dependent.
A curve fit optimization algorithm extracts the mathematical expression for ABM, which yields a good representation of Power MOSFET’s static and dynamic characteristics.
In
Figure 5
, the self-heating spice model (V3 version) schematic is shown.
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A brief description of self-heating model (V3 version)
Figure 5. Power MOSFET self-heating model schematic
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2 1
1 2
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UM1575 A brief description of self-heating model (V3 version)
Thermal impedance network represents the basic element, which is featured inside the macro-model. It is used to transform the power dissipated inside the junction into a voltage representing the temperature (T j
).
Figure 6. Physical structure
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The voltage drop across the network is detected and used as emitter value inside behavioral equations used to model other parameters.
Thermal impedance is the experimental data required to obtain the Cauer model (see
Figure 6
).
Figure 7. Thermal impedance profile and Cauer model
.
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A brief description of self-heating model (V3 version) UM1575
4.2 Experimental data used to fit the model
The model implementation requires the following experimental data:
•
Typ. output characteristics at different temperatures
•
Typ. transfer characteristics at different temperatures
•
Typ. drain source breakdown voltage at different temperatures
•
Typ. drain source on state resistance vs temperature
•
Typ. gate threshold voltage vs temperature
•
Typ. forward diode characteristics
•
Typ. capacitances profile vs VDS
•
Typ. gate charge
•
Typ. switching on resistive load
•
Typ. switching on inductive load
•
Typ. free-wheeling diode characteristics
•
Unclamped inductive switching
•
Switching losses vs gate resistance
•
Equivalent capacitance time related (C o(tr)
)
•
Equivalent capacitance energy related (C o(er)
)
•
Max. transient thermal impedance
Figure 8. Simulated and measured output characteristics
Figure 9. Simulated curves at V
GS
= 10 V
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UM1575 A brief description of self-heating model (V3 version)
Figure 10. Normalized R
DS(on)
vs temperature Figure 11. Normalized gate threshold voltage vs temperature
AM06484v1 AM06483v1
R
DS(on)
(norm)
2.1
I
D
=2.5A
V
GS(th)
(norm)
1.10
I
D
=250µA
1.9
1.00
1.7
1.5
1.3
1.1
0.90
0.9
0.7
0.5
-50 -25 0 25 50 75 100 T
J
(°C)
0.80
0.70
-50 -25 0 25 50 75 100 T
J
(°C)
4.3 C
OSS
and C
RSS
model
Charge and current formulas for a linear capacitor are:
Q
=
C
•
V i t
=
C
• d V
------d t
For a non linear (voltage-dependent) time-independent capacitor these formulas become:
Q
=
C V d V i t
= ( ) • d V
------d t
The C(V) function is obtained by lookup table.
Figure 12. Capacitance profiles
C
(pF)
AM06481v1
1000
Ciss
100
Coss
10
1
0.1
1 10 100
Crss
V
DS
(V)
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A brief description of self-heating model (V3 version)
4.4 Example of dynamic characteristics
Figure 13. Gate charge - schematic
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Rload1
Vdd1
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R127
0 0 0
Figure 14. Gate charge - simulated waveforms
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UM1575 A brief description of self-heating model (V3 version)
Figure 15. Gate charge - experimental waveforms
4.4.2 Switching on inductive load
Figure 16. Switching on inductive load - schematic
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Iload1
Lpar1
R127
Vdd1
Vpulse1
Rgate1
0
L33
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A brief description of self-heating model (V3 version)
Figure 17. Switching on inductive load - simulated waveforms
UM1575
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Figure 18. Switching on inductive load - experimental waveforms
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4.4.3 E off
vs R gate
A brief description of self-heating model (V3 version)
Figure 19. E off
vs R gate
- schematic
Iload1
Lpar1
R127
Vdd1
Vpulse1
Rgate1
L33
0
Figure 20. E off
vs R gate
- experimental waveforms
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A brief description of self-heating model (V3 version) UM1575
R
G
( Ω )
Table 1. E off
(comparison simulated/measured)
Measured E off
(µJ) Simulated E off
(µJ)
4.7
4.1
3.9
10
47
200
4.31
6.8
27
4.4
7.1
29
Figure 21. Recovery diode - schematic
Iload1
Lpar1
R127
Vdd1
Vpulse1
Rgate1
0
L33
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UM1575 A brief description of self-heating model (V3 version)
Figure 22. Recovery diode - simulated waveforms
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A brief description of self-heating model (V3 version) UM1575
Test
1
2
Table 2. Simulated test conditions
T
C
Energy I drain
110 °C 0.3 J 83 A
110 °C 0.3 J 203 A
Figure 23. Unclamped inductive switching - schematic
Δ
T j
83 °C
133 °C
-PBE
7EE
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(
3
%
4
5+
;UI
5DBTF
5DBTF
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Figure 24. Unclamped inductive switching - simulated waveforms (test 1)
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Figure 25. Unclamped inductive switching - simulated waveforms (test 2)
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Figure 26. Unclamped inductive switching - experimental waveforms
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A brief description of self-heating model (V3 version)
Figure 27. Short-circuit test - schematic
-PBE
7EE
3HBUF
(
3
%
4
;UI
5+
5DBTF
5DBTF
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Figure 28. Short-circuit test - waveforms
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4.4.7
A brief description of self-heating model (V3 version)
Flyback simulated by self-heating model
Figure 29. Flyback simulated by self-heating model - schematic
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A brief description of self-heating model (V3 version) where:
•
•
•
Blue line = (Tx current sec)/10
Black line = (Tx current Pri)
Red line = MOSFET drain current
If you have further questions, feel free to contact us via our local sale offices.
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Date
25-Nov-2013
Revision
Table 3. Document revision history
Changes
1 Initial release.
Revision history
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