Intel S5000PAL, S5000XAL Data Sheet
Reklama
Reklama
ii
Intel® Server Board S5000PAL /
S5000XAL
Technical Product Specification
Intel order number: D31979-010
Revision 1.9
March 2009
Enterprise Platforms and Services Division – Marketing
Revision 1.9
Intel order number: D31979-010
Intel® Server Board S5000PAL / S5000XAL TPS
April 2006
June 2006
August 2006
January 2007
May 2007
August 2007
October 2007
February 2008
November 2008
March 2009
Revision History
Revision History
Revision
Number
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
Modifications
First external release.
Updated theoretical memory bandwidth performance numbers.
Added Platform Control sections.
Memory RAS is now available.
Updated Snoop Filter Section.
Updated Figures #16 and #25.
Updated Table 44 BMC sensor.
Updated CMOS clear and password reset usage procedures.
Updated regulatory tables.
Removed platform control information that can be found in the Intel
®
Server Board Family Datasheet.
S5000
Updated processor support section.
Updated Table 44 BMC sensor.
Updated Processor support section
Updated Internal USB Connector Pin-out
Update the BIOS Select Jumper section.
Revision 1.9
Intel order number: D31979-010 iii
Disclaimers Intel® Server Board S5000PAL / S5000XAL TPS
Disclaimers
Information in this document is provided in connection with Intel
®
products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked
"reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® Server Board S5000PAL and the Intel
®
Server Board S5000XAL may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Intel Corporation server baseboards support peripheral components and contain a number of highdensity VLSI and power delivery components that need adequate airflow to cool. Intel’s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together. It is the responsibility of the system integrator that chooses not to use
Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental conditions. Intel
Corporation can not be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non-operating limits.
Intel, Pentium, Itanium, and Xeon are trademarks or registered trademarks of Intel Corporation.
*Other brands and names may be claimed as the property of others.
Copyright © Intel Corporation 2008. iv Revision 1.9
Intel order number: D31979-010
Intel® Server Board S5000PAL / S5000XAL TPS Table of Contents
Table of Contents
1.
Introduction ........................................................................................................................ 12
1.1
Chapter Outline...................................................................................................... 12
1.2
Server Board Use Disclaimer ................................................................................ 12
2.
Product Overview ............................................................................................................... 13
2.1
Intel® Server Board S5000PAL / S5000XAL Feature Set ..................................... 13
2.2
Server Board Layout.............................................................................................. 14
2.2.1
Connector and Component Locations ................................................................... 15
2.2.2
Light Guided Diagnostic LED Locations ................................................................ 17
2.2.3
External I/O Connector Locations.......................................................................... 18
2.2.4
Server Board Mechanical Drawings ...................................................................... 19
3.
Functional Architecture ..................................................................................................... 24
3.1
Intel ® 5000P and 5000X Memory Controller Hubs (MCH) ..................................... 25
3.1.1
System Bus Interface............................................................................................. 25
3.1.2
Processor Support ................................................................................................. 25
3.1.3
Memory Sub-system.............................................................................................. 26
3.1.4
Snoop Filter (5000X MCH only)............................................................................. 32
3.2
ESB-2 IO Controller ............................................................................................... 32
3.2.1
PCI Sub-system..................................................................................................... 33
3.2.2
Serial ATA Support ................................................................................................ 35
3.2.3
Parallel ATA (PATA) Support ................................................................................ 36
3.2.4
USB 2.0 Support.................................................................................................... 36
3.3
Video Support ........................................................................................................ 36
3.4
Network Interface Controller (NIC) ........................................................................ 38
3.4.1
Intel ® I/O Acceleration Technology ........................................................................ 38
3.4.2
MAC Address Definition......................................................................................... 38
3.5
Super I/O ............................................................................................................... 39
4.
Platform Management ........................................................................................................ 42
5.
Connector / Header Locations and Pin-outs.................................................................... 43
5.1
Board Connector Information................................................................................. 43
5.2
Power Connectors ................................................................................................. 44
5.3
System Management Headers .............................................................................. 45
5.3.1
Intel ® Remote Management Module (RMM) Connector ........................................ 45
5.3.2
Intel ® RMM NIC Connector .................................................................................... 46
5.3.3
LCP/AUX IPMB Header ......................................................................................... 47
5.3.4
IPMB Header ......................................................................................................... 47
Revision 1.9
Intel order number: D31979-010 v
Table of Contents Intel® Server Board S5000PAL / S5000XAL TPS
5.4
5.5
5.6
5.7
Riser Card Slots..................................................................................................... 47
SSI Control Panel Connector................................................................................. 52
Bridge Board Connector ........................................................................................ 52
I/O Connector Pin-out Definition ............................................................................ 54
5.7.1
VGA Connector...................................................................................................... 54
5.7.2
NIC Connectors ..................................................................................................... 54
5.7.3
IDE Connector ....................................................................................................... 55
5.7.4
Intel ® I/O Expansion Module Connector ................................................................ 55
5.7.5
SATA Connectors .................................................................................................. 56
5.7.6
Serial Port Connectors........................................................................................... 57
5.7.7
Keyboard and Mouse Connector ........................................................................... 57
5.7.8
USB 2.0 Connectors .............................................................................................. 58
5.8
Fan Headers .......................................................................................................... 59
6.
Jumper Block Settings ...................................................................................................... 60
6.1
Recovery Jumper Blocks ....................................................................................... 60
6.1.1
CMOS Clear and Password Reset Usage Procedure ........................................... 61
6.1.2
BMC Force Update Procedure .............................................................................. 61
6.2
BIOS Select Jumper .............................................................................................. 62
6.3
External RJ45 Serial Port Jumper Block................................................................ 63
7.
Light Guided Diagnostics .................................................................................................. 64
7.1
7.2
5-Volt Standby LED ............................................................................................... 64
System ID LED and System Status LED ............................................................... 65
7.2.1
System Status LED – BMC Initialization................................................................ 66
7.3
DIMM Fault LEDs .................................................................................................. 67
7.4
7.5
Processor Fault LED.............................................................................................. 67
Post Code Diagnostic LEDs .................................................................................. 68
8.
Power and Environmental Specifications ........................................................................ 69
8.1
Intel® Server Board S5000PAL / S5000XAL Design Specifications ..................... 69
8.2
Server Board Power Requirements ....................................................................... 70
8.2.1
Processor Power Support...................................................................................... 70
8.2.2
Power Supply Output Requirements...................................................................... 71
8.2.3
Turn On No Load Operation .................................................................................. 71
8.2.4
Grounding .............................................................................................................. 72
8.2.5
Standby Outputs .................................................................................................... 72 vi
8.2.6
Remote Sense ....................................................................................................... 72
8.2.7
Voltage Regulation ................................................................................................ 72
8.2.8
Dynamic Loading ................................................................................................... 73
8.2.9
Capacitive Loading ................................................................................................ 73
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Intel® Server Board S5000PAL / S5000XAL TPS Table of Contents
8.2.10
Closed-Loop Stability............................................................................................. 73
8.2.11
Common Mode Noise ............................................................................................ 73
8.2.12
Ripple / Noise ........................................................................................................ 74
8.2.13
Soft Starting ........................................................................................................... 74
8.2.14
Timing Requirements............................................................................................. 74
8.2.15
Residual Voltage Immunity in Standby Mode ........................................................ 77
9.
Regulatory and Certification Information......................................................................... 78
9.1
Product Regulatory Compliance ............................................................................ 78
9.1.1
Product Safety & Electromagnetic (EMC) Compliance.......................................... 78
9.2
Electromagnetic Compatibility Notices .................................................................. 79
9.2.1
FCC Verification Statement (USA) ........................................................................ 79
9.2.2
ICES-003 (Canada) ............................................................................................... 79
9.2.3
Europe (CE Declaration of Conformity) ................................................................. 79
9.2.4
BSMI (Taiwan) ....................................................................................................... 80
9.2.5
RRL (Korea)........................................................................................................... 80
9.3
Product Ecology Compliance................................................................................. 81
9.4
Other Markings ...................................................................................................... 82
Appendix A: Integration and Usage Tips................................................................................ 83
Appendix B: BMC Sensor Tables ............................................................................................ 84
Appendix C: POST Code Diagnostic LED Decoder ............................................................. 100
Appendix D: POST Error Messages and Handling .............................................................. 104
Appendix E: Supported Intel
®
Server Chassis ..................................................................... 107
Glossary................................................................................................................................... 110
Reference Documents ............................................................................................................ 113
Revision 1.9
Intel order number: D31979-010 vii
List of Figures Intel® Server Board S5000PAL / S5000XAL TPS
List of Figures
Figure 1. Components & Connector Location Diagram .............................................................. 16
Figure 2. Light Guided Diagnostic LED Location Diagram ......................................................... 17
Figure 3. Intel® Server Board S5000PAL / S5000XAL ATX I/O Layout ..................................... 18
Figure 4. Intel® Server Board S5000PAL / S5000XAL – Hole and Component Positions (1 of 2)19
Figure 5. Intel® Server Board S5000PAL / S5000XAL – Hole and Component Positions (2 of 2)20
Figure 6. Intel® Server Board S5000PAL / S5000XAL – Restricted Areas on Side 1 ................ 21
Figure 7. Intel® Server Board S5000PAL / S5000XAL – Restricted Areas on Side 2 ................ 22
Figure 8. Intel® Server Board S5000PAL / S5000XAL - Primary Side Duct and VR Restrictions23
Figure 9. Server Board Functional Block Diagram...................................................................... 24
Figure 10. CEK Processor Mounting .......................................................................................... 26
Figure 11. Memory Layout .......................................................................................................... 27
Figure 12. Recommended Minimum Two DIMM Memory Configuration .................................... 29
Figure 13. Recommended Four DIMM Configuration ................................................................. 30
Figure 14. Single Branch Mode Sparing DIMM Configuration .................................................... 31
Figure 15. Serial Port Configuration Jumper Location ................................................................ 40
Figure 16. SMBUS Block Diagram.............................................................................................. 42
Figure 17. Recovery Jumper Blocks (J1D1, J1D2, J1D3) ......................................................... 60
Figure 18. BIOS Select Jumper (J3H1) ...................................................................................... 62
Figure 19. External RJ45 Serial Port Configuration Jumper ....................................................... 63
Figure 20. 5V Standby Status LED Location .............................................................................. 64
Figure 21. System ID LED and System Status LED Locations................................................... 65
Figure 22. DIMM Fault LED Locations........................................................................................ 67
Figure 23. Processor Fault LED Location ................................................................................... 67
Figure 24. POST Code Diagnostic LED Location ....................................................................... 68
Figure 25. Power Distribution Block Diagram ............................................................................. 70
Figure 26. Output Voltage Timing ............................................................................................... 75
Figure 27. Turn On/Off Timing (Power Supply Signals).............................................................. 76
Figure 28. Diagnostic LED Placement Diagram ....................................................................... 100
Figure 29. 1U – Intel ® Server Chassis SR1500 Overview ........................................................ 107
Figure 30. 1U – Intel ® Server Chassis SR1550 Overview ........................................................ 108
Figure 31. 2U – Intel ® Server Chassis SR2500 Overview ........................................................ 109 viii Revision 1.9
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Intel® Server Board S5000PAL / S5000XAL TPS List of Tables
List of Tables
Table 1. I 2 C Addresses for Memory Module SMB ..................................................................... 27
Table 2. Maximum 8 DIMM System Memory Configuration – x8 Single Rank ........................... 28
Table 3. Maximum 8 DIMM System Memory Configuration – x4 Dual Rank .............................. 28
Table 4. PCI Bus Segment Characteristics................................................................................. 33
Table 5. Video Modes ................................................................................................................. 37
Table 6. NIC2 Status LED........................................................................................................... 38
Table 7. Serial A Header Pin-out ................................................................................................ 39
Table 8. Rear Serial B Port Adapter Pin-out ............................................................................... 40
Table 9. Board Connector Matrix ................................................................................................43
Table 10. Power Connector Pin-out (J3K3) ................................................................................ 44
Table 11. 12V Power Connector Pin-out (J3K4)......................................................................... 44
Table 12. Power Supply Signal Connector Pin-out (J1K1) ......................................................... 44
Table 13. Intel ® RMM Connector Pin-out (J1C5) ........................................................................ 45
Table 14. 30-pin Intel ® RMM NIC Module Connector Pin-out (J1B2) ......................................... 46
Table 15. LPC/AUX IPMB Header Pin-out (J1C2) ...................................................................... 47
Table 16. IPMB Header Pin-out (J1C3) ...................................................................................... 47
Table 17. Low-profile Riser Slot Pin-out (J5B1).......................................................................... 47
Table 18. Full-height Riser Slot Pin-out (J4F1)........................................................................... 48
Table 19. Front Panel SSI Standard 24-pin Connector Pin-out (J3H2) ...................................... 52
Table 20. 120-pin Bridgeboard Connector Pin-out (J4G1) ......................................................... 52
Table 21. VGA Connector Pin-out (J6A1)................................................................................... 54
Table 22. RJ-45 10/100/1000 NIC Connector Pin-out (JA8A1, JA8A2)...................................... 54
Table 23. 44-pin IDE Connector Pin-out (J3G1) ......................................................................... 55
Table 24. 50-pin Intel ® I/O Expansion Module Connector Pin-out (J3B1)................................... 56
Table 25. SATA Connector Pin-out (J1H1, J1G2, J1G1, J1F2, J1E3) ....................................... 56
Table 26. External RJ-45 Serial ‘B’ Port Pin-out (J9A2) ............................................................. 57
Table 27. Internal 9-pin Serial ‘A’ Header Pin-out (J1B1) ........................................................... 57
Table 28. Stacked PS/2 Keyboard and Mouse Port Pin-out (J9A1) ........................................... 57
Table 29. External USB Connector Pin-out (J5A1, J6A2)........................................................... 58
Table 30. Internal USB Connector Pin-out (J1J1)....................................................................... 58
Table 31. SSI Fan Connector Pin-out (J9K1,J5K1,J3K1,J3K2,J7A2,J7A1) ............................... 59
Table 32. Recovery Jumpers (J1D1, J1D2, J1D3) ..................................................................... 60
Table 33: Server Board Design Specifications ........................................................................... 69
Table 34. Dual-Core Intel ® Xeon ® Processor 5000 Sequence TDP Guidelines per processor .. 70
Table 35. 600W Load Ratings .................................................................................................... 71
Revision 1.9
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List of Tables Intel® Server Board S5000PAL / S5000XAL TPS
Table 36: No load operating range ........................................................................................... 71
Table 37. Voltage Regulation Limits ........................................................................................... 72
Table 38. Transient Load Requirements..................................................................................... 73
Table 39. Capacitive Loading Conditions ................................................................................... 73
Table 40. Ripple and Noise......................................................................................................... 74
Table 41. Output Voltage Timing ................................................................................................ 75
Table 42. Turn On/Off Timing ..................................................................................................... 76
Table 43. BMC Sensors.............................................................................................................. 86
Table 44: POST Progress Code LED Example ........................................................................ 100
Table 45. Diagnostic LED POST Code Decoder ...................................................................... 101
Table 46. POST Error Messages and Handling........................................................................ 104
Table 47. POST Error Beep Codes .......................................................................................... 106
Table 48. BMC Beep Codes ..................................................................................................... 106 x Revision 1.9
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Intel® Server Board S5000PAL / S5000XAL TPS
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List of Tables
Revision 1.9
Intel order number: D31979-010 xi
Introduction Intel
®
Server Board S5000PAL / S5000XAL TPS
1. Introduction
This Technical Product Specification (TPS) provides board specific information detailing the features, functionality, and high level architecture of the Intel® Server Board S5000PAL and Intel
S5000XAL. The Intel
®
® Server Board
S5000 Series Chipsets Server Board Family Datasheet should also be referenced for more in depth detail of various board sub-systems including chipset, BIOS, System Management, and
System Management software.
In addition, design level information for specific sub-systems can be obtained by ordering the External
Product Specifications (EPS) or External Design Specifications (EDS) for a given sub-system. EPS and
EDS documents are not publicly available. They are only made available under NDA with Intel and must be ordered through your local Intel representative.
The Intel® Server Board S5000PAL/XAL may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Refer to the Intel® Server Board
S5000PAL/XAL Specification Update for published errata.
This document is divided into the following chapters
• Chapter
• Chapter 2 – Server Board Overview
• Chapter 3 – Functional Architecture
• Chapter 4 – Platform Management
• Chapter 5 – Connector & Header Location and Pin-out
• Chapter 6 – Configuration Jumpers
• Chapter 7 – Light Guided Diagnostics
• Chapter 8 – Power and Environmental Specifications
• Chapter 9 – Regulatory and Certification Information
• Appendix A – Integration and Usage Tips
• Appendix B – BMC Sensor Tables
• Appendix C – POST Code Diagnostic LED Decoder
• Appendix D – Post Code Errors
• Appendix E – Supported Intel
®
Server Chassis
1.2 Server Board Use Disclaimer
Intel Corporation server boards support add-in peripherals and contain a number of high-density VLSI and power delivery components that need adequate airflow to cool. Intel ensures through its own chassis development and testing that when Intel server building blocks are used together, the fully integrated system will meet the intended thermal requirements of these components. It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental conditions. Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or nonoperating limits.
12 Revision 1.9
Intel order number: D31979-010
Intel
®
Server Board S5000PAL / S5000XAL TPS Product Overview
The Intel® Server Board S5000PAL and Intel ® Server Board S5000XAL are monolithic printed circuit boards with features that were designed to support the high-density 1U and 2U server markets.
2.1 Intel® Server Board S5000PAL / S5000XAL Feature Set
Feature
Processors
Description
771-pin LGA sockets supporting 1 or 2 Dual-Core Intel ® Xeon ® with system bus speeds of 667 MHz, 1066 MHz, or 1333 MHz
processors 5000 sequence,
Memory 8 Keyed DIMM slots supporting fully buffered DIMM technology (FBDIMM) memory. 240-pin
DDR2-533 and DDR2-677 FBDIMMs must be used.
Chipset Intel ® 5000 Chipset Family which includes the following components:
Intel ® 5000P Memory Controller Hub or Intel ® 5000X Memory Controller Hub
On-board
Connectors/Headers
Add-in PCI, PCI-X*, PCI
Express* Cards
On-board Video
On-board Hard Drive
Controller
Intel ® 6321ESB I/O Controller Hub1
Note: Intel will only make available an OEM SKU of this server board using the Intel ® 5000X
Memory Controller Hub.
External connections:
Stacked PS/2* ports for keyboard and mouse
RJ45 Serial B port
Two RJ45 NIC connectors for 10/100/1000 Mb connections
Two USB 2.0 ports
Video Connector
Internal connectors/headers:
One USB port header, capable of providing two USB 2.0 ports
One DH10 Serial A header
Six SATA ports via the ESB-2 and integrated SW RAID 0/1/10 support
One 44pin (power + I/O) ATA/100 connector for optical drive support
One Intel optional)
® Remote Management Module (Intel ® RMM) connector (Intel ® RMM use is
One Intel ® I/O Expansion Module Connector supporting:
Dual GB NIC Intel ® I/O Expansion Module (Optional)
External SAS Intel ® I/O Expansion Module (Optional)
Infiniband* I/O Expansion Module (Optional)
SSI-compliant 24-pin control panel header
SSI-compliant 24-pin main power connector, supporting the ATX-12V standard on the first
20 pins
8-Pin +12V Processor Power Connector
One low profile riser slot supporting 1U or 2U PCIe* riser cards
One full height riser slot supporting 1U or 2U PCI-X* and PCIe* riser cards
ATI* ES1000 video controller with 16MB DDR SDRAM
Six ESB-2 SATA ports.
Intel ® Embedded Server RAID Technology II with SW RAID levels 0/1/10.
LAN
System Fans
System Management
Optional support for SW RAID 5 with activation key.2
Two 10/100/1000 Intel ® 82563EB PHYs supporting Intel ® I/O Acceleration Technology
Six 4-pin Fan Headers supporting two processor fans, and four system fans
Support for Intel ® System Management Software
1
For the remainder of this document, the Intel
®
2
6321ESB I/O Controller Hub will be refferred to as ESB-2.
Onboard SATA SW RAID 5 support provided as a post-launch product feature.
Revision 1.9
Intel order number: D31979-010
13
Product Overview
2.2 Server Board Layout
Intel
®
Server Board S5000PAL / S5000XAL TPS
14 Revision 1.9
Intel order number: D31979-010
Intel
®
Server Board S5000PAL / S5000XAL TPS Product Overview
2.2.1 Connector and Component Locations
The following figure shows the board layout of the server board. Each connector and major component is identified by a number or letter, and a description is given below the figure.
A B C D E F G H I
PP
GG
FF
EE
DD
CC
BB
AA
OO
NN
LL
MM
KK
JJ
II
HH
Z
M
N
J
K
L
O
P
Q
Y X W V U T S R
TP02071
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Product Overview Intel
®
Server Board S5000PAL / S5000XAL TPS
Description
A BIOS Bank Select Jumper
B Intel
®
ESB-2 IO Controller Hub
C IO Module Option Connector
D POST Code Diagnostic LEDs
E Intel
®
Adaptive Slot – Full Height
F PCI Express* Riser Slot – Low Profile
G System Identification LED - Blue
H External IO Connectors
I Status LED – Green / Amber
J Serial ‘B’ Port Configuration Jumper
K System Fan #4 Header
L System Fan #3 Header
M FBDIMM Slots
N Intel
®
Intel
®
5000P Memory Controller Hub (MCH) or
5000X Memory Controller Hub (MCH)
O CPU #1 Connector
P CPU #2 Connector
V
Description
System Fan #2 Header
W CPU Power Connector
X Main Power Connector
Y Battery
Z Power Supply Management Connector
AA Dual Port USB 2.0 Header
BB System Fan #1 Header
CC SSI 24-pin Control Panel Header
DD SATA 0
EE SATA 1
FF SATA 2
GG SATA 3
HH SATA 4
Q CPU #1 Fan Header
R Voltage Regulator Heat Sink
S CPU #2 Fan Header
T Bridge Board Connector
U ATA-100 Optical Drive Connector (Power+IO)
JJ SATA SW RAID 5 Activation Key Connector
KK Intel ® Remote Management Module (RMM)
Connector
LL System Recovery Jumper Block
MM Chassis Intrusion Switch Header
NN 3-pin IPMB Header
OO Intel ® Local Control Panel Header
PP Serial ‘A’ Header
QQ Intel
®
RMM NIC Connector
Figure 1. Components & Connector Location Diagram
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Intel
®
Server Board S5000PAL / S5000XAL TPS
2.2.2 Light Guided Diagnostic LED Locations
A B
C
Product Overview
I J K L D M N O P
TP02317
Description
A Post Code Diagnostic LEDs
Description
E CPU Fault LED
B System Identification LED – Blue F CPU Fault LED
C System Status LED – Green / Amber G 5-Volt Stand-by Present
LED
D DIMM Fault LEDs
Figure 2. Light Guided Diagnostic LED Location Diagram
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Intel order number: D31979-010
17
Product Overview Intel
®
Server Board S5000PAL / S5000XAL TPS
2.2.3 External I/O Connector Locations
The drawing below shows the layout of the rear I/O components for the server board.
A
B C D E F G H
TP02296
A PS/2 Mouse
C Serial Port B
D NIC port 1 (1 Gb)
E NIC port 2 (1 Gb)
F Video
G USB port 1
H USB port 2
Figure 3. Intel® Server Board S5000PAL / S5000XAL ATX I/O Layout
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Intel
®
Server Board S5000PAL / S5000XAL TPS
2.2.4 Server Board Mechanical Drawings
Product Overview
10.16 [0.400]
2 x 0.00 [0.000]
0.91 [0.036]
15.24 [0.600]
21.59 [0.850]
Lotes B2515BB2M
6012A0019603
45.59 [1.795]
2 x 49.35 [1.943]
62.66 [2.467]
67.31 [2.650]
Molex 22-44-7031
6012A0099701-HDR4P
Molex 22-44-7031
6012A0099701
9 x Ø 0.125 [3.18] Typ.
124.26 [4.892]
127.43 [5.017]
152.40 [6.000]
6 x Betterment
BTM-PP02.2F1611.007X
6012B0018302
227.33 [8.950]
228.60 [9.000]
Lotes B2515BB2M
6012A0019603
0.16 [0.006]
AMP 177983-5
6012A0103201
FCI 10027747-114101
6012A0105001
Molex 877715-3205
6012A0100101
22.86 [0.900]
7 x Ø 3.96 [0.156]
5 x Ø 8.00 [0.315]
Silkscreen on secondary side for spacer
2 x 101.60 [4.000]
Lotes AAA-PCI-033-K02
6012B0051002
4 x 187.93 [7.399]
Lotes B4L60BB2L
6012A0105401
8 x Ø 10.16 [0.400]
3 x 312.42 [12.300]
320.04 [12.600]
38.10
[1.500] Typ.
TP02316
Figure 4. Intel® Server Board S5000PAL / S5000XAL – Hole and Component Positions (1 of 2)
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Intel order number: D31979-010
19
Product Overview Intel
®
Server Board S5000PAL / S5000XAL TPS
143.00 [5.630]
160.77 [6.330]
174.17 [6.857]
178.56 [7.030]
196.33 [7.730]
211.02 [8.308]
214.12 [8.430]
214.63 [8.450]
230.38 [9.070]
231.89 [9.130]
243.83 [9.600]
265.41 [10.449]
10.16 [0.400]
5 x 6.99 [0.275]
0.00 [0.000]
3.45 [0.136]
2 x 1.83 [0.072]
11.96 [0.471]
19.76 [0.778]
30.91 [1.217]
35.05 [1.380]
49.68 [1.956]
62.99 [2.480]
67.39 [2.653]
76.45 [3.010]
86.11 [3.390]
1st Pin
119.16 [4.692]
119.59 [4.708]
297.84 [11.726]
308.74 [12.155]
1st Pin
1st Pin
6.27 [0.247]
2.67 [0.105]
3.35 [0.132]
8.64 [0.340]
35.28 [1.389]
8 x 40.39 [1.590]
7 x 10.67 [0.420]
298.51 [11.752]
309.042 [12.167]
R1.52 [0.060]
TP02292
Figure 5. Intel® Server Board S5000PAL / S5000XAL – Hole and Component Positions (2 of 2)
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Intel order number: D31979-010
Intel
®
Server Board S5000PAL / S5000XAL TPS
H < 30 mm [1.181"]
PCI BKT Drop Down
No Components Allowed for Retention Pins
H < 3.5 mm [0.138"] for Three Boards
2 x 5.08 [0.200]
10.16 [0.400]
3 x 5.08 [0.200]
0.00 [0.000]
2 x 3.07 [0.121]
21.23 [0.836]
28.17 [1.109]
41.96 [1.652]
53.34 [2.100]
60.15 [2.368]
9 x No Components 5.0 dia. on Top
No Components 3.5 dia. on Bottom
H < 12.4 mm [0.488"]
Under Riser PCIe Conn.
130.00 [5.118]
H < 26 mm [1.023"]
Under Riser PCI-X Conn.
169.98 [6.692]
177.47 [6.987]
180.92 [7.123]
188.72 [7.430]
H < 11.8 mm [0.465"]
Under Riser Card
H < 15.2 mm [0.600"]
Under FH PCI Option Card
234.75 [9.242]
264.97 [10.432]
316.00 [12.441]
320.04 [12.600]
H < 9.5 mm [0.374"]
Under Bridge Board
120.85 [4.758] 125.27 [4.932]
4 x 7.62 [0.300]
Product Overview
H < 11.65 mm [0.459"]
Under Rear Panel Tab
H < 5 mm [0.196"]
PCI BKT Drop Down
H < 12.7 mm [0.499"]
Under LP PCI Option Card
3.81 [0.150]
0.18 [0.007]
10.80 [0.425]
18.97 [0.747]
46.76 [1.841]
102.77 [4.046]
H < 10mm [0.394"]
PCI BKT DROP DOWN
170.64 [6.718]
184.12 [7.249]
H < 3mm [0.118"]
PCI BKT DROP DOWN
273.02 [10.749]
REF ONLY
H < 7 mm [0.275"]
Under Heat Sink
REF ONLY
H < 11 mm [0.433"]
Under Heat Sink
Figure 6. Intel® Server Board S5000PAL / S5000XAL – Restricted Areas on Side 1
TP02293
Revision 1.9
Intel order number: D31979-010
21
Product Overview
5.08 [0.200] Typ.
20.32 [0.800] Typ.
Limited Height 1.27 mm
[0.05"] on Side 2
320.04 [12.600]
Intel
®
Server Board S5000PAL / S5000XAL TPS
3 Ground Pad on Side 2
10.16 [0.400]
0.00 [0.000]
10.13 [0.399]
H < 2 mm
[0.078]
15.24 [0.600] Typ.
Ø 2.000 [50.8 mm] Typ.
2 X 5.00 [0.197]
3 X 3.99 [0.157]
3.00 [0.118]
H < 1.47 mm [0.058"] Typ.
No Components or
Surface Layer Traces in this Zone.
Ø 29.46 [1.160] Typ.
Backside Spring Area.
No Motherboard Component
Placement Allowed.
180.34 [7.100]
200.03 [7.875]
0.200" [5.08 mm Max] Keep IN for 2U and above Platforms.
0.100" [2.54 mm Max] Keep IN for 1U Platforms on Side 2.
257.73 [10.147]
4 x 4.45 [0.175]
276.86 [10.900]
Limited Height 1.27 mm [0.05"] on Side 2, Dia. 29.5 mm [1.160"]
TP02294
Figure 7. Intel® Server Board S5000PAL / S5000XAL – Restricted Areas on Side 2
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Intel
®
Server Board S5000PAL / S5000XAL TPS
10.16 [0.400]
0.00 [0.000]
Product Overview
NO Components Allowed for Duct
182.83 [7.198]
143.51 [5.650]
2 x 173.99 [6.850]
H < 10.0 mm [0.394"]
Under Duct
H < 0.8 mm [0.310"]
Under VR
H < 1.5 mm [0.059"]
Under VR
256.54 [10.100]
3 x 274.32 [10.800]
298.51 [11.753]
2 x 77.22 [3.040]
5.52 [0.217]
4.83 [0.190]
5.08 [0.200] H < 27 mm [1.063"]
Under Duct
NO Components Allowed
TP02295
Figure 8. Intel® Server Board S5000PAL / S5000XAL - Primary Side Duct and VR Restrictions
Revision 1.9
Intel order number: D31979-010
23
Functional Architecture Intel
®
Server Board S5000PAL / S5000XAL TPS
The architecture and design of the Intel® Server Board S5000PAL / S5000XAL is based on the Intel ®
5000 Chipset Family. The chipset is designed for systems based on the Dual-Core Intel
®
Xeon
® processor 5000 sequence with system bus speeds of 667 MHz, 1066 MHz, and 1333 MHz. The chipset is made up of two main components: the Memory Controller Hub (MCH) for the host bridge and the ESB-
2 I/O controller hub for the I/O subsystem. This chapter provides a high-level description of the functionality associated with each chipset component and the architectural blocks that make up this server board. For more in depth detail of the functionality for each of the chipset components and each of the functional architecture blocks, see the Intel
®
S5000 Server Board Family Datasheet.
Figure 9. Server Board Functional Block Diagram
Note: The diagram above uses the Intel
®
5000P MCH as a general reference designator for both MCH components supported on this server board.
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Intel
®
Server Board S5000PAL / S5000XAL TPS Functional Architecture
3.1 Intel
®
5000P and 5000X Memory Controller Hubs (MCH)
This section will describe the general functionality of the memory controller hub as it is implemented on this server board. Depending on the version of the server board in use, it may support either the Intel
®
5000P MCH or the Intel
®
5000X MCH. Features that are unique to a particular MCH will be so referenced.
The Memory Controller Hub (MCH) is a single 1432 pin FCBGA package which includes the following core platform functions:
• System Bus Interface for the processor sub-system
• Memory
• PCI Express* Ports including the Enterprise South Bridge Interface (ESI)
• FBD Thermal Management
• SMBUS
Additional information about MCH functionality can be obtained from the Intel
®
S5000 Series Chipsets
Server Board Family Datasheet, the Intel
®
5000P Memory Controller Hub External Design Specification
(Yellow Cover), or the Intel
®
5000X Memory Controller Hub External Design Specification (Yellow Cover).
Note: Yellow Cover documents can only be obtained under NDA with Intel and ordered through an Intel representative.
3.1.1 System Bus Interface
The MCH is configured for symmetric multi-processing across two independent front side bus interfaces that connect to the Dual-Core Intel
®
Xeon
®
processors 5000 sequence. Each front side bus on the MCH uses a 64-bit wide 1066 or 1333 MHz data bus. The 1333 MHz data bus is capable of transferring data at up to 10.66 GB/s. The MCH supports a 36-bit wide address bus, capable of addressing up to 64 GB of memory. The MCH is the priority agent for both front side bus interfaces, and is optimized for one processor on each bus.
The server board supports the following processors:
•
One or two Dual-Core Intel ® Xeon ® processors 5000 or 5100 sequence with a 677-, 1066-, or
1333-MHz front side bus.
•
Up to two Quad-Core Intel ® Xeon ® processors 5300 sequence with a 1066- or 1333-MHz front side bus.
•
Up to two 45nm 2P Dual-Core Intel ® Xeon ® processors. Systems based on S5000PALR or
S5000XALR only.
•
Up to two 45nm next generation Quad-Core Intel
®
Xeon
® processors. Systems based on
S5000PALR or S5000XALR only.
Previous generations of the Intel
®
Xeon
®
processor are not supported on the server board. See http://support.intel.com/support/motherboards/server/s5000pal/ for a complete updated list of supported processors. ( http://support.intel.com/support/motherboards/server/sb/CS-022346.htm/ is sub-directory of above S5000PAL URL that reflects supported processor list)
Note: Only Dual-Core Intel
®
Xeon
®
processors 5000 sequence, that support system bus speeds of 667
MHz, 1066 MHz, and1333 MHz are supported on this server board.
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25
Functional Architecture Intel
®
Server Board S5000PAL / S5000XAL TPS
3.1.2.1 Processor Population Rules
When two processors are installed, both must be of identical revision, core voltage, and bus/core speed.
Mixed processor steppings is supported. However, the stepping of one processor cannot be greater than one stepping back of the other. When only one processor is installed, it must be in the socket labeled
CPU1. The other socket must be empty.
The board is designed to provide up to 130A of current per processor. Processors with higher current requirements are not supported.
No terminator is required in the second processor socket when using a single processor configuration.
3.1.2.2 Common Enabling Kit (CEK) Design Support
The server board complies with Intel’s Common Enabling Kit (CEK) processor mounting and heat sink retention solution. The server board ships with a CEK spring snapped onto the underside of the server board, beneath each processor socket. The heat sink attaches to the CEK, over the top of the processor and the thermal interface material (TIM). See the figure below for the stacking order of the chassis, CEK spring, server board, TIM, and heat sink.
The CEK spring is removable, allowing for the use of non-Intel heat sink retention solutions.
Note: The processor heat sink and CEK spring shown in the following diagram are for reference purposes only. The actual processor heat sink and CEK solutions compatible with this generation server board may be of a different design.
Heatsink assembly
Thermal interface material (TIM)
Server board
CEK spring
Chassis
Figure 10. CEK Processor Mounting
On the Intel® Server Board S5000PAL / S5000XAL, the MCH provides four channels of Fully Buffered
DIMM (FB-DIMM) memory. Each channel can support up to 2 Dual Ranked FB-DIMM DDR2 DIMMs. FB-
DIMM memory channels are organized in to two branches for support of RAID 1 (mirroring). The MCH can support up to 8 DIMMs or a maximum memory size of 32 GB physical memory in non-mirrored mode and 16 GB physical memory in a mirrored configuration. The read bandwidth for each FB-DIMM channel is 4.25 GB/s for DDR2 533 FB-DIMM memory which gives a total read bandwidth of 17 GB/s for four FB-
DIMM channels. Thus, this provides 8.5 GB/s of write memory bandwidth for four FB-DIMM channels.
The read bandwidth for each FB-DIMM channel is 5.3GB/s for DDR2 667 FB-DIMM memory which gives
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Intel
®
Server Board S5000PAL / S5000XAL TPS Functional Architecture a total read bandwidth of 21GB/s for four FB-DIMM channels. Thus, this provides 10.7 GB/s of write memory bandwidth for four FB-DIMM channels. The total bandwidth is based on read bandwidth thus the total bandwidth is 17 GB/s for 533 and 21.0 GB/s for 667.
On the Intel® Server Board S5000PAL / S5000XAL, a pair of channels becomes a branch where Branch
0 consists of channels A and B, and Branch 1 consists of channels C and D. FBD memory channels are organized into two branches for support of RAID 1(mirroring).
Channel B
Channel A
Channel C
Channel D
MCH
DIMM A1
DIMM A2
DIMM B1
DIMM B2
DIMM C1
DIMM C2
DIMM D1
DIMM D2
Branch 0
Branch 1
TP02299
Figure 11. Memory Layout
To boot the system, the system BIOS on the server board uses a dedicated I addresses for each DIMM slot.
2
C bus to retrieve DIMM information needed to program the MCH memory registers. The following table provides the I
2
C
Table 1. I
2
C Addresses for Memory Module SMB
Device Address
DIMM A1 0xA0
DIMM A2
DIMM B1
0xA2
0xA0
DIMM B2
DIMM C1
0xA2
0xA0
DIMM C2
DIMM D1
DIMM D2
0xA2
0xA0
0xA2
Features i
The MCH supports several memory RASUM (Reliability, Availability, Serviceability, Usability, and
Manageability) features. These features include the Intel
®
x4 Single Device Data Correction (Intel
®
x4
SDDC) for memory error detection and correction, Memory Scrubbing, Retry on Correctable Errors,
Memory Built In Self Test, DIMM Sparing, and Memory Mirroring. See the Intel
Server Board Family Datasheet for more information describing these features.
®
S5000 Series Chipsets
The server board supports up to eight DDR2-533 or DDR2-667 Fully Buffered DIMMs (FBD memory).
The following tables show the maximum memory configurations supported using the specified memory technology.
Revision 1.9 27
Intel order number: D31979-010
Functional Architecture Intel
®
Server Board S5000PAL / S5000XAL TPS
Table 2. Maximum 8 DIMM System Memory Configuration – x8 Single Rank
DRAM Technology x8
Single Rank
256 Mb
512 Mb
1024 Mb
2048 Mb
Maximum Capacity
Mirrored Mode
1 GB
2 GB
4 GB
8 GB
Maximum Capacity
Non-Mirrored Mode
2 GB
4 GB
8 GB
16 GB
Table 3. Maximum 8 DIMM System Memory Configuration – x4 Dual Rank
DRAM Technology x4
Dual Rank
256 Mb
512 Mb
1024 Mb
2048 Mb
Maximum Capacity
Mirrored Mode
4 GB
8 GB
16 GB
16 GB
Maximum Capacity
Non-Mirrored Mode
8 GB
16 GB
32 GB
32 GB
Note : DDR2 DIMMs that are not fully buffered are NOT supported on this server board. See the Intel®
Server Board S5000PAL / S5000XAL Tested Memory List for a complete list of supported memory for this server board.
3.1.3.3 DIMM Population Rules and Supported DIMM Configurations
DIMM population rules depend on the operating mode of the memory controller, which is determined by the number of DIMMs installed. DIMMs must be populated in pairs. DIMM pairs are populated in the following DIMM slot order: A1 & B1, C1 & D1, A2 & B2, C2 & D2. DIMMs within a given pair must be identical with respect to size, speed, and organization. However, DIMM capacities can be different between different DIMM pairs.
For example, a valid mixed DIMM configuration may have 512MB DIMMs installed in DIMM Slots A1 &
B1, and 1GB DIMMs installed in DIMM slots C1 & D1.
Intel supported DIMM configurations for this server board are shown in the following table.
Supported and Validated configuration : Slot is populated
Supported but not validated configuration : Slot is populated
Slot is not populated
Mirroring: Y = Yes. Indicates that configuration supports Memory Mirroring.
Sparing: Y(x) = Yes. Indicates that configuration supports Memory Sparing.
Where x = 0 : Sparing supported on Branch0 only
1 : Sparing supported on Branch1 only
0,1 : Sparing supported on both branches
Branch 0 Branch 1
Channel A Channel B Channel C Channel D
DIMM_A1 DIMM_A2 DIMM_B1 DIMM B2 DIMM C1 DIMM C2 DIMM D1 DIMM D2
Mirroring
Possible
Sparing
Possible
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Intel
®
Server Board S5000PAL / S5000XAL TPS Functional Architecture
Y
Y (0)
Y (0)
Y Y (0, 1)
Notes:
- Single channel mode is only tested and supported with a 512MB x8 FBDIMM installed in DIMM
Slot A1.
- The supported memory configurations must meet population rules defined above.
- For best performance, the number of DIMMs installed should be balanced across both memory branches. For Example: a four DIMM configuration will perform better than a two
DIMM configuration and should be installed in DIMM Slots A1, B1, C1, and D1. An eight
DIMM configuration will perform better then a six DIMM configuration.
- Although mixed DIMM capacities between channels is supported, Intel does not validate DIMMs in mixed DIMM configurations.
3.1.3.3.1 Minimum Non-Mirrored Mode Configuration
The server board is capable of supporting a minimum of one DIMM installed. However, for system performance reasons, Intel’s recommendation is that at least 2 DIMMs be installed.
The following diagram shows the recommended minimum DIMM memory configuration. Populated DIMM slots are shown in Grey .
Channel B
Channel A
Channel C
Channel D
MCH
DIMM A1
DIMM A2
DIMM B1
DIMM B2
DIMM C1
DIMM C2
DIMM D1
DIMM D2
Branch 0
Branch 1
TP02300
Figure 12. Recommended Minimum Two DIMM Memory Configuration
Note: The server board supports single DIMM mode operation. Intel will only validate and support this configuration with a single 512MB x8 FBDIMM installed in DIMM slot A1.
Revision 1.9
Intel order number: D31979-010
29
Functional Architecture Intel
®
Server Board S5000PAL / S5000XAL TPS
3.1.3.4 Non-mirrored mode memory upgrades
The minimum memory upgrade increment is two DIMMs per branch. The DIMMs must cover the same slot position on both channels. DIMMs pairs must be identical with respect to size, speed, and organization. DIMMs that cover adjacent slot positions do not need to be identical.
When adding two DIMMs to the configuration shown in Figure 12, the DIMMs should be populated in
DIMM slots C1 and D1 as shown in the following diagram. Populated DIMM slots are shown in Grey .
Channel B
Channel A
Channel C
Channel D
MCH
DIMM A1
DIMM A2
DIMM B1
DIMM B2
DIMM C1
DIMM C2
DIMM D1
DIMM D2
Branch 0
Branch 1
TP02301
Figure 13. Recommended Four DIMM Configuration
Functionally, DIMM slots A2 and B2 could also have been populated instead of DIMM slots C1 and D1.
However, your system will not achieve equivalent performance. Figure 13 shows the supported DIMM configuration that is recommended because it allows both memory branches from the MCH to operate independently and simultaneously. FBD bandwidth is doubled when both branches operate in parallel.
3.1.3.4.1 Mirrored Mode Memory Configuration
When operating in mirrored mode, both branches operate in lock step. In mirrored mode, branch 1 contains a replicate copy of the data in branch 0. The minimum DIMM configuration to support memory mirroring is four DIMMs, populated as shown in Figure 13 above. All four DIMMs must be identical with respect to size, speed, and organization.
To upgrade a four DIMM mirrored memory configuration, four additional DIMMs must be added to the system. All four DIMMs in the second set must be identical to the first with the exception of speed. The
MCH will adjust to the lowest speed DIMM.
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Intel
®
Server Board S5000PAL / S5000XAL TPS Functional Architecture
3.1.3.4.2 DIMM Sparing Mode Memory Configuration
The MCH provides DIMM sparing capabilities. Sparing is a RAS feature that involves configuring a DIMM to be placed in reserve so it can be use to replace a DIMM that fails. DIMM sparing occurs within a given bank of memory and is not supported across branches.
There are two supported Memory Sparing configurations.
Slot 2 DIMM_A2
Slot 1 DIMM_A1
DIMM_B2
DIMM_B1
Channel A
Branch 0
Channel B
DIMM_C2
DIMM_C1
DIMM_D2
DIMM_D1
Channel C
Branch 1
Channel D
Intel® 5000P/5000X Memory Controller Hub
Figure 14. Single Branch Mode Sparing DIMM Configuration
• DIMM_A1 and DIMM_B1 must be identical in organization, size and speed.
• DIMM_A2 and DIMM_B2 must be identical in organization, size and speed.
• DIMM_A1 and DIMM_A2 need not be identical in organization, size and speed.
• DIMM_B1 and DIMM_B2 need not be identical in organization, size and speed.
• Sparing should be enabled in BIOS setup.
• BIOS
• The larger of the pairs {DIMM_A1, DIMM_B1} and {DIMM_A2, DIMM_B2} will be selected as the spare pair unit.
Revision 1.9
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31
Functional Architecture Intel
®
Server Board S5000PAL / S5000XAL TPS
3.1.3.4.2.2 Dual Branch Mode Sparing
Dual branch mode sparing requires that all eight DIMM slots be populated and must comply with the following population rules.
• DIMM_A1 and DIMM_B1 must be identical in organization, size and speed.
• DIMM_A2 and DIMM_B2 must be identical in organization, size and speed.
• DIMM_C1 and DIMM_D1 must be identical in organization, size and speed.
• DIMM_C2 and DIMM_D2 must be identical in organization, size and speed.
• DIMM_A1 and DIMM_A2 need not be identical in organization, size and speed.
• DIMM_B1 and DIMM_B2 need not be identical in organization, size and speed.
• DIMM_C1 and DIMM_C2 need not be identical in organization, size and speed.
• DIMM_D1 and DIMM_D2 need not be identical in organization, size and speed.
• Sparing should be enabled in BIOS setup.
• BIOS
• The larger of the pairs {DIMM_A1, DIMM_B1} and {DIMM_A2, DIMM_B2} and {DIMM_C1,
DIMM_D1} and {DIMM_C2, DIMM_D2} will be selected as the spare pair units.
3.1.4 Snoop Filter (5000X MCH only)
The 5000X version of the MCH includes a snoop filter. Depending on the application of the server, this feature can be used to enhance the performance of the server by eliminating unnecessary traffic on the system bus. By removing the excess traffic from the snooped bus, the full bandwidth is available for other operations.
3.2 ESB-2 IO Controller
The ESB-2 is a multi-function device that provides four distinct functions: an IO Controller, a PCI-X*
Bridge, a Gigabit Ethernet Controller, and a Baseboard Management Controller (BMC). Each function within the ESB-2 has its own set of configuration registers. Once configured, each appears to the system as a distinct hardware controller.
A primary role of the ESB-2 is to provide the gateway to all PC-compatible I/O devices and features. The server board uses the following ESB-2 features:
• PCI-X* interface
• Six Channel SATA interface w/SATA Busy LED Control
• Dual MAC
• Baseboard Management Controller (BMC)
• Single ATA interface, with Ultra DMA 100 capability
• Universal Serial Bus 2.0 (USB) interface
• Removable Drives
• LPC interface
• PC-compatible timer/counter and DMA controllers
• APIC and 8259 interrupt controller
• Power
• System
• General purpose I/O
32 Revision 1.9
Intel order number: D31979-010
Intel
®
Server Board S5000PAL / S5000XAL TPS Functional Architecture
This section describes the function of most of the listed features as they pertain to this server board. For more detail information, see the Intel
Intel
®
®
S5000 Series Chipsets Server Board Family Datasheet
Enterprise South Bridge-2 External Design Specification (Yellow Cover)
or the
The primary I/O buses for the server board are PCI, PCI Express*, and PCI-X*, with six independent PCI bus segments. The PCI buses comply with the PCI Local Bus Specification , Revision 2.3. The table below lists the characteristics of the PCI bus segments. Details about each bus segment follow the table.
Table 4. PCI Bus Segment Characteristics
PCI Bus Segment Voltage Width Speed
PCI32
ESB-2
3.3V 32 bit 33MHz
PXA
ESB-2
PE1
ESB-2 PCIe* Port2
3.3V x4 10Gb/S
PE2
ESB-2 PCIe Port3
PE4, PE5
BNB PCIe Ports
4,5
PE6, PE7
BNB PCIe Ports
6,7
Type
PCI
On-board Device Support
Used internally for video controller
Full height riser slot, up to three slots on riser card
PCIe* Used for Intel chassis for mid-plane IOP
Mezzanine connector for Intel
®
Module
I/O Expansion
3.2.1.1 PCI32: 33-MHz PCI Bus Segment
All 32-bit, 33-MHz PCI I/O is directed through the ESB-2 ICH6. The 32-bit, 33-MHz PCI segment created by the ESB-2-ICH6 is known as the PCI32 segment. The PCI32 segment supports the following embedded devices:
• 2D Graphics Accelerator: ATI* ES1000 Video Controller
3.2.1.2 PXA: 64-bit, 133MHz PCI-X* Bus Segment
One 64-bit PCI-X* bus segment is directed through the ESB-2 ICH6. This PCI-X segment, PXA, can support up to three add-in cards on a riser card plugged into the full height riser card slot (J4F1).
3.2.1.3 PE1: One x4 PCI Express* Bus Segment
One x4 PCI Express* bus segment is directed through the ESB-2. This PCI Express segment, PE1, supports the optional Active SAS Midplane IOP as used in supported Intel chassis for this server board.
3.2.1.4 PE2: One x4 PCI Express* Bus Segment
One x4 PCI Express* bus segment is directed through the ESB-2. This PCI Express segment, PE2, supports one x4 PCI Express segment to the proprietary Intel
®
I/O Expansion Module mezzanine connector (J3B1).
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33
Functional Architecture
3.2.1.5
Intel
®
Server Board S5000PAL / S5000XAL TPS
PE4, PE5: Two x4 PCI Express* Bus Segments
Two x4 PCI Express* bus segments are directed through the MCH. These PCI Express segments, PE4 and PE5, support one x8 or two x4 PCI Express segments to the low profile riser slot (J5B1).
3.2.1.6 PE6, PE7: Two x4 PCI Express* Bus Segments
Two x4 PCI Express* bus segments are directed through the MCH. These PCI Express segments, PE6 and PE7, support one x8 or two x4 PCI Express segments to the full height riser slot (J4F1).
3.2.1.7 PCI Riser Slots
The server board has two riser slots capable of supporting riser cards for both 1U and 2U system configurations. Because of board placement resulting in different pin orientations, and expanded technology support associated with the full-height riser, the riser slots are not the same and require different riser cards.
The low profile riser slot (J5B1) utilizes a 98-pin connector. It is capable of supporting one x8 (1U) or two x4 (2U) low profile PCI Express* add-in cards. The x8 PCI Express* bus can support bus speeds of up to
20 Gb/S. The following table provides the supported bus throughput for the given riser card used and the number of add-in cards installed.
Low Profile Riser
1U – 1 add-in card slot
2U – 2 add-in card slots
1 add-in card populated 2 add-in cards populated x8 or x4 x4
NA x4
Note: There are no population rules for installing a single low profile add-in card in the 2U LP riser card; a single add in card can be installed in either PCI Express* slot. While each slot can accommodate a x8 card, each slot will only support x4 bus speeds.
The full height riser slot (J4F1) implements Intel
®
Adaptive Slot Technology. This 280-pin connector is capable of supporting riser cards that meet either the PCI-X* or PCI Express* technology specifications.
The following tables show the maximum bus speed supported with different add-in card populations for each supported riser card.
Full Height PCI-X* 1 add-in card populated 2 add-in cards populated 3 add-in cards populated
(Passive) Riser
1U – 1 add-in card slot Up to 133MHz
2U – 3 add-in card slots Up to 100MHz in top PCI slot
NA
Up to 100MHz using top and middle slots
NA
66MHz
Note: For the 2U PCI-X* (passive) riser card, add-in cards should be installed starting with the top slot first, followed by the middle, and then the bottom. Any add-in card populated in the bottom PCI slot will cause the bus to operate at 66MHz.
Full Height PCI-X* 1 add-in card populated 2 add-in cards populated 3 add-in cards populated
(Active) Riser
2U – 3 add-in card slots Up to 133MHz Up to 133MHz Up to 133MHz
Note: Each PCI slot on the 2U PCI-X* (active) riser card operates on an independent PCI bus. Therefore, using an add-in card that operates below 133MHz will not affect the bus speed of the other PCI slots.
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Intel
®
Server Board S5000PAL / S5000XAL TPS
Full Height PCI Express* 1 add-in card populated
Riser
1U – 1 add-in card slot x4 or x8
2U – 3 add-in card slots Single PCIe* x4 in either slot or x8 in middle slot
Or
PCI-X* – Up to 133MHz in bottom slot
2 add-in cards populated
NA
Single PCIe* – x4 in either slot or x8 in middle slot and
PCI-X* – Up to 133MHz
Or
Dual PCIe – x4
Functional Architecture
3 add-in cards populated
NA
Dual PCIe* – x4
And
PCI-X* – Up to 133MHz
The ESB-2 has an integrated Serial ATA (SATA) controller that supports independent DMA operation on six ports and supports data transfer rates of up to 3.0 Gb/s. The six SATA ports on the server board are numbered SATA-0 thru SATA-5. The SATA ports can be enabled/disabled and/or configured by accessing the BIOS Setup Utility during POST.
3.2.2.1 Intel
®
Embedded Server RAID Technology II Support
The onboard storage capability of this server board includes support for Intel
®
Embedded Server RAID
Technology which provides three standard software RAID levels: data stripping (RAID Level 0), data mirroring (RAID Level 1), and data stripping with mirroring (RAID Level 10). For higher performance, data stripping can be used to alleviate disk bottlenecks by taking advantage of the dual independent DMA engines that each SATA port offers. Data mirroring is used for data security. Should a disk fail, a mirrored copy of the failed disk is brought on-line. There is no loss of either PCI resources (request/grant pair) or add-in card slots.
With the addition of an optional Intel RAID Activation Key, Intel
®
Embedded Server RAID Technology is also capable of providing fault tolerant data stripping (software RAID Level 5), such that if a SATA hard drive should fail, the lost data can be restored on a replacement drive from the other drives that make up the RAID 5 pack.
See Figure 1. Components & Connector Location Diagram for the location of Intel RAID Activation Key connector location.
Note: Availability of the Intel RAID Activation Key to support software RAID 5 will be deferred until after product launch of this server board.
Intel ® Embedded Server RAID Technology functionality requires the following items:
• Intel
®
ESB-2 IO Controller Hub
• Intel
®
Embedded Server RAID Technology Option ROM
• Intel ® Application Accelerator RAID Edition drivers, most recent revision
• At least two SATA hard disk drives
Intel
®
Embedded Server RAID Technology is not available in the following configurations:
• The SATA controller in compatible mode
• Intel
®
Embedded Server RAID Technology has been disabled
Revision 1.9
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35
Functional Architecture Intel
®
Server Board S5000PAL / S5000XAL TPS
3.2.2.2 Intel
®
Embedded Server RAID Technology Option ROM
The Intel ® Embedded Server RAID Technology for SATA Option ROM provides a pre-OS user interface for the Intel ® Embedded Server RAID Technology implementation and provides the ability for an Intel ®
Embedded Server RAID Technology volume to be used as a boot disk as well as to detect any faults in the Intel
®
Embedded Server RAID Technology volume(s) attached to the Intel
®
RAID controller.
3.2.3 Parallel ATA (PATA) Support
The integrated IDE controller of the ESB-2 ICH6 provides one IDE channel. It redefines signals on the
IDE cable to allow both host and target throttling of data and transfer rates of up to 100MB/s. For this server board, the IDE channel was designed to provide Slim-line Optical Drive support to the platform.
The BIOS initializes and supports ATAPI devices such as CDROM, CD-RW and DVD. The IDE channel is accessed through a single high density 44-pin connector ((J3G1) which provides both power and IO signals. The ATA channel can be configured and enabled or disabled by accessing the BIOS Setup Utility during POST.
Note: The IDE connector on this server board is NOT a standard 40 IDE connector. Instead, this connector has an additional 4 power pins over and above the standard 40 I/O pins. The design intent of this connector is to provide support for a slim-line optical drive only.
3.2.4 USB 2.0 Support
The USB controller functionality integrated into ESB-2 provides the server board with the interface for up to eight USB 2.0 ports. Two external connectors are located on the back edge of the server board. One internal 2x5 header is provided, capable of supporting two optional USB 2.0 ports. Three USB ports are routed through the bridge board connector providing optional USB support for a system Control Panel or other USB requirements. An additional USB port is dedicated to the Intel ® Remote Management Module
(Intel
®
RMM) connector.
The server board provides an ATI* ES1000 PCI graphics accelerator, along with 16MB of video DDR
SDRAM and support circuitry for an embedded SVGA video sub-system. The ATI ES1000 chip contains an SVGA video controller, clock generator, 2D engine, and RAMDAC in a 359-pin BGA. One 4Mx16x4 bank DDR SDRAM chip provides 16MB of video memory.
The SVGA sub-system supports a variety of modes, up to 1024 x 768 resolution in 8 / 16 / 32bpp modes under 2D. It also supports both CRT and LCD monitors up to a 100 Hz vertical refresh rate.
Video is accessed using a standard 15-pin VGA connector found on the back edge of the server board.
Video signals are also made available through the 120-pin bridgeboard connector which provides signals for an optional video connector to be present on the platform’s control panel. Video is routed to both the rear video connector and a control panel video connector. Video is present at both connectors simultaneously and cannot be disabled at either connector individually. Hot plugging the video while the system is still running is supported.
On-board video can be disabled using the BIOS Setup Utility or when an add-in video card is installed.
System BIOS also provides the option for dual video operation when an add-in video card is configured in the system.
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Intel
®
Server Board S5000PAL / S5000XAL TPS Functional Architecture
The ATI ES1000 chip supports all standard IBM* VGA modes. The following table shows the 2D modes supported for both CRT and LCD.
Table 5. Video Modes
2D Mode Refresh Rate (Hz)
640x480
800x600
60, 72, 75, 85, 90,
100, 120, 160, 200
60, 70, 72, 75, 85,
90, 100, 120,160
70,
75,85,90,100
1152x864 43,47,60,70,75,80,85
1280x1024 60,70,74,75
1600x1200 52
2D Video Mode Support
8 bpp 16 bpp 32 bpp
Supported Supported Supported
Supported Supported Supported
Supported Supported Supported
Supported Supported Supported
Supported Supported Supported
Supported Supported Supported
The memory controller sub-system of the ES1000 arbitrates requests from the direct memory interface, the VGA graphics controller, the drawing co-processor, the display controller, the video scalar, and the hardware cursor. Requests are serviced in a manner that ensures display integrity and maximum
CPU/co-processor drawing performance.
The server board supports a 16MB (4Meg x 16-bit x 4 banks) DDR SDRAM device for video memory.
The BIOS supports single and dual video modes. The dual video mode is enabled by default.
• In single mode (Dual Monitor Video = Disabled), the on-board video controller is disabled when an add-in video card is detected.
• In dual mode (On-board Video = Enabled, Dual Monitor Video = Enabled), the on-board video controller is enabled and will be the primary video device. The external video card will be allocated resources and is considered the secondary video device. BIOS Setup provides user options to configure the feature as follows.
On-board Video
Dual Monitor Video
Enabled
Disabled
Enabled
Disabled
Shaded if on-board video is set to "Disabled"
Revision 1.9
Intel order number: D31979-010
37
Functional Architecture Intel
®
Server Board S5000PAL / S5000XAL TPS
3.4 Network Interface Controller (NIC)
Network interface support is provided from the built in Dual GbE MAC features of the ESB-2 in conjunction with the Intel ® 82563EB compact Physical Layer Transceiver (PHY). Together, they provide the server board with support for dual LAN ports designed for 10/100/1000 Mbps operation.
The 82563EB device is based upon proven PHY technology integrated into the Intel
®
Gigabit Ethernet
Controllers. The physical layer circuitry provides a standard IEEE 802.3 Ethernet interface for 1000BASE-
T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). The 82563EB device is capable of transmitting and receiving data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps
Each Network Interface Controller (NIC) drives two LEDs located on each network interface connector.
The link/activity LED (to the right of the connector) indicates network connection when on, and
Transmit/Receive activity when blinking. The speed LED (to the left of the connector) indicates 1000-
Mbps operation when amber, 100-Mbps operation when green, and 10-Mbps when off. The table below provides an overview of the LEDs.
LED Color
Green/Amber (Left)
Table 6. NIC2 Status LED
Off
Green
LED State
10 Mbps
100 Mbps
NIC State
Green (Right)
Blinking Transmit / Receive activity
3.4.1 Intel
®
I/O Acceleration Technology
Intel ® I/O Acceleration Technology moves network data more efficiently through Dual-Core Intel ® Xeon ® processor 5000 sequence-based servers for improved application responsiveness across diverse operating systems and virtualized environments. Intel
®
I/OAT improves network application responsiveness by unleashing the power of Dual-Core Intel
®
Xeon
®
processors 5000 sequence through more efficient network data movement and reduced system overhead. Intel multi-port network adapters with Intel ® I/OAT provide high-performance I/O for server consolidation and virtualization via stateless network acceleration that seamlessly scales across multiple ports and virtual machines. Intel
®
I/OAT provides safe and flexible network acceleration through tight integration into popular operating systems & virtual machine monitors, avoiding the support risks of 3rd-party network stacks and preserving existing network requirements such as teaming and failover.
Each Intel® Server Board S5000PAL / S5000XAL has four MAC addresses assigned to it at the Intel factory. During the manufacturing process, each server board will have a white MAC address sticker placed on the board. The sticker will display the MAC address in both bar code and alpha numeric formats. The printed MAC address is assigned to NIC 1 on the server board. NIC 2 is assigned the NIC 1
MAC address + 1.
Two additional MAC addresses are assigned to the Baseboard Management Controller (BMC) embedded in the ESB-2. These MAC addresses are used by the BMC’s embedded network stack to enable IPMI remote management over LAN. BMC LAN Channel 1 is assigned the NIC1 MAC address + 2, and BMC
LAN Channel 2 is assigned the NIC1 MAC address + 3.
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Intel order number: D31979-010
Intel
®
Server Board S5000PAL / S5000XAL TPS Functional Architecture
Legacy I/O support is provided by using a National Semiconductor* PC87427 Super I/O device. This chip contains all of the necessary circuitry to support the following functions:
• GPIOs
• Two ports
• Keyboard and mouse support
• Wake control
• System health support
The server board provides two serial ports: an external RJ45 serial port, and an internal DH10 serial header.
Serial A is an optional port accessed through a 9-pin internal DH-10 header. A standard DH10 to DB9 cable can be used to direct the Serial A port to the rear of a chassis. The Serial A interface follows the standard RS232 pin-out as defined in the following table.
Table 7. Serial A Header Pin-out
Pin Signal Name Serial Port A Header Pin-out
1 DCD
2 DSR
3 RX
4 RTS
5 TX
6 CTS
7 DTR
8 RI
9 GND
The rear RJ45 Serial B port is a fully functional serial port that can support any standard serial device.
Using an RJ45 connector for a serial port allows direct support for serial port concentrators, which typically use RJ45 connectors and are widely used in the high-density server market. For server applications that use a serial concentrator to access the system management features of the server board, a standard 8-pin CAT-5 cable from the serial concentrator is plugged directly into the rear RJ45 serial port.
To allow support for either of two serial port configuration standards, a jumper block located directly behind the rear RJ45 serial port must be configured appropriately according to the desired standard. For serial concentrators that require a DCD signal, the jumper block must be configured with the serial port jumper over pins 1 and 2. For serial concentrators that require a DSR signal (Default), the jumper block must be configured with the serial port jumper over pins 3 and 4. Pin 1 on the jumper is identified by “ * ”.
Note: By default, the rear RJ45 serial port is configured to support a DSR signal. This configuration is compatible with the Cisco* standard.
Revision 1.9
Intel order number: D31979-010
39
Functional Architecture
J8A3
2
Intel
®
Server Board S5000PAL / S5000XAL TPS
3 4
1-2: DCD to DTR 3-4: DSR to DTR
(factory default)
TP02303
Figure 15. Serial Port Configuration Jumper Location
Pins
1-2
3-4
What happens at system reset…
Serial port is configured for DCD to DTR
Serial port is configured for DSR to DTR (default)
For server applications that require a DB9 serial connector, an 8-pin RJ45-to-DB9 adapter must be used.
The following table provides the pin-out required for the adapter to provide RS232 support. A standard
DH10-to-DB9 cable and 8-pin RJ45 to DB9 DCD and DSR adapters are available from Intel in the Serial
Port Accessory Kit, product code: AXXRJ45DB92.
Table 8. Rear Serial B Port Adapter Pin-out
RJ45
1
2
Signal
Request to Send
Abbreviation
RTS
Data Terminal Ready DTR
7
4
3
DB9
4 Signal SGND 5
5 Ring RI 9
6 Received RD
7 DCD or DSR DCD/DSR
8 Clear To Send CTS
2
1 or 6 (see note)
8
Note: The RJ45-to-DB9 adapter should match the configuration of the serial device used. One of two pinout configurations is used, depending on whether the serial device requires a DSR or DCD signal. The final adapter configuration should also match the desired pin-out of the RJ45 connector, as it can also be configured to support either DSR or DCD.
3.5.1.2 Floppy Disk Controller
The server board does not support a floppy disk controller (FDC) interface. However, the system BIOS does recognize USB floppy devices.
3.5.1.3 Keyboard and Mouse Support
Dual stacked PS/2 ports, located on the back edge of the server board, are provided for keyboard and mouse support. Either port can support a mouse or keyboard. Neither port supports hot plugging.
40 Revision 1.9
Intel order number: D31979-010
Intel
®
Server Board S5000PAL / S5000XAL TPS Functional Architecture
The super I/O contains functionality that allows various events to power-on and power-off the system.
3.5.1.5 System Health Support
The super I/O provides an interface via GPIOs for BIOS and Server Management Firmware to activate the Diagnostic LEDs, the FRU fault indicator LEDs for processors, DIMMs, fans and the system status
LED. Refer to Figure 2. Light Guided Diagnostic LED Location Diagram for the location of the LEDs on the baseboard.
The super I/O also provides PMW fan control to the system fans, monitors tach and presence signals for the system fans and monitors baseboard and control panel temperature.
Revision 1.9
Intel order number: D31979-010
41
Platform Management Intel
®
Server Board S5000PAL / S5000XAL TPS
The platform management sub-system on the server board is based on the integrated Baseboard
Management Controller (BMC) features of the ESB-2. The on board platform management subsystem consists of communication buses, sensors, system BIOS, and server management firmware. The following diagram provides an overview of the Server Management Bus (SMBUS) architecture used on this server board.
See Appendix B for onboard sensor data.
For more detailed platform management information, see the Intel
®
S5000 Server Board Family
Datasheet.
Figure 16. SMBUS Block Diagram
42 Revision 1.9
Intel order number: D31979-010
Intel
®
Server Board S5000PAL / S5000XAL TPS Connector / Header Locations and Pin-outs
5. Connector / Header Locations and Pin-outs
5.1 Board Connector Information
The following section provides detailed information regarding all connectors, headers and jumpers on the server board. Table 9 lists all connector types available on the board and the corresponding reference designators printed on the silkscreen.
Connector
Power supply
Main Memory
Full Height Riser
Low Profile Riser
Bridge Board
Connector
Quantity
3 J3K4
J3K3
J1K1
Table 9. Board Connector Matrix
Reference Designators
8 J7B1,J7B2,J8B1,J8B2,J8B3,J9B1,J9B2,
J9B3
1
1
J4F1
J5B1
1 J4G1
RMM NIC
Intel
®
I/O
Expansion Module
SATA RAID Key
IDE (I/O + Power)
Front System Fans
#1 & #2
Rear System Fans
#3 & #4
CPU Fans
1 J1B2
1 J3B1
1
1
J1E4
J3G1
2 J5K1, J9K1
Connector Type
CPU Power
Main Power
P/S Aux
Pin
Count
8
24
5
DIMM Sockets
Card Edge
Card Edge
240
280
98
120
Mezzanine
Mezzanine
Key Holder
Shrouded
Header
Header
Header
Header
30
50
3
44
4
4
4
Rear USB
Serial Port A
Serial Port B
Video connector
LAN connector
10/100/1000
SSI Control Panel
Internal USB
Intrusion detect
Serial ATA
LCP / AUX IPMB
2
1
1
1
2
J5A1, J6A2
J1B1
J9A2
J6A1
JA8A1, JA8A2
1
1
2
6
1
J3H2
J1J1
J1C4
J1H1,J1G2,J1G1,J1F2,J1F1,J1E3
J1C2
External
Header
External, RJ45
External, D-Sub
External LAN connector with built-in magnetic
Header
Header
Header
Header
Header
4
9
10
15
14
24
10
2
7
4
Revision 1.9
Intel order number: D31979-010
43
Connector / Header Locations and Pin-outs
Connector Quantity
Intel
®
Server Board S5000PAL / S5000XAL TPS
Reference Designators Connector Type
4 J1D1, J1D2, J1D3, J3H1 Jumper
Pin
Count
3 System Recovery
Setting Jumpers
The main power supply connection is obtained using an SSI compliant 2x12 pin connector (J3K3). In addition, there are two additional power related connectors; one SSI compliant 2x4 pin power connector
I
(J3K4) providing support for additional 12V, and one SSI compliant 1x5 pin connector (J1K1) providing
2
C monitoring of the power supply. The following tables define the connector pin-outs.
Table 10. Power Connector Pin-out (J3K3)
Signal Color Pin Signal Pin Color
2 +3.3Vdc Orange 14 -12Vdc Blue
3 GND Black 15 GND Black
4 +5Vdc Red 16 PS_ON# Green
5 GND
6 +5Vdc
7 GND
Black 17 GND
Red 18 GND
Black 19 GND
Black
Black
Black
9 5VSB
10 +12Vdc
11 +12Vdc
Purple 21 +5Vdc
Yellow 22 +5Vdc
Yellow 23 +5Vdc
12 +3.3Vdc Orange 24 GND
Table 11. 12V Power Connector Pin-out (J3K4)
Pin Signal
1 GND
2 GND
3 GND
4 GND
Color
Black
Black
Black
Black
5 +12Vdc Yellow/Black
6 +12Vdc Yellow/Black
7 +12Vdc Yellow/Black
8 +12Vdc Yellow/Black
Red
Red
Red
Black
Table 12. Power Supply Signal Connector Pin-out (J1K1)
Pin Signal Color
1 SMB_CLK_ESB_FP_PWR_R Orange
2 SMB_DAT_ESB_FP_PWR_R Black
3 SMB_ALRT_3_ESB_R Red
Yellow
Green
44 Revision 1.9
Intel order number: D31979-010
Intel
®
Server Board S5000PAL / S5000XAL TPS Connector / Header Locations and Pin-outs
5.3.1 Intel
®
Remote Management Module (RMM) Connector
A 120-pin Intel
®
RMM Connector (J1C5) is included on the server board for sole support of the optional
Intel
®
Remote Management Module. There is no support for third party ASMI cards on this server board.
Note: This connector is NOT compatible for use with Intel
®
Edition (Product Code AXXIMMPRO) or the Intel ®
Server Management Module Professional
Server Management Module Advanced Edition
(Product Code AXXIMMADV).
Revision 1.9
Table 13. Intel
®
RMM Connector Pin-out (J1C5)
Pin
1
Signal Name
Reserved - NC
Pin
2
Signal Name
GND
3 ESB_PLT_RST_G1_N 4 NC
7
9
Reserved - NC
Reserved - NC
8
10
11 GND 12
13 GND 14
15 USB_ESB_P7P 16
17 USB_ESB_P7N 18
19 GND 20
21 P3V3 22
23 LPC_LAD<0> 24
25 LPC_LAD<1> 26
27 P3V3 28
29 LPC_LCLK 30
31 P3V3 32
GND
GND
IRQ_SERIAL_R
GND
GND
GND
LPC_FRAME_N
LPC_LAD<2>
LPC_LAD<3>
P3V3
33 SMB_1_3V3SB_MS_DAT 34 SMB_IPMB_3V3SB_DAT
35 SMB_1_3V3SB_SL_DAT 36 SMB_IPMB_3V3SB_CLK
37 SMB_1_3V3SB_MS_CLK 38 SMB_0_3V3SB_MS_CLK
39 SMB_1_3V3SB_INT 40 SMB_0_3V3SB_INT
41 P3V3_AUX 42 SMB_0_3V3SB_MS_DAT
43 SPB_IMM_DSR_N 44 SMB_0_3V3SB_SL_DAT
45 SPB_IMM_RTS_N 46
47 SPB_IMM_CTS_N 48
P3V3_AUX
FM_IMM_PRESENT_N
49 SPB_IMM_DCD_N 50
51 SPB_RI_N 52
53 SPB_IMM_SOUT 54
55 P3V3_AUX 56
57 V_LCDCNTL3 56
SPB_IMM_DTR_N
SPB_IMM_SIN
P3V3_AUX
V_LCDDATA7
V_LCDDATA6
59 P3V3_AUX 60
61 Reserved - NC 62
63 Reserved - NC 64
65 GND 66
67 V_LCDCNTL0 68
69 Reserved - NC 70
71 GND 72
V_LCDDATA5
V_LCDDATA4
V_LCDDATA3
V_LCDCNTL1
GND
V_LCDDATA15
V_LCDDATA714
Intel order number: D31979-010
45
Connector / Header Locations and Pin-outs Intel
®
Server Board S5000PAL / S5000XAL TPS
Pin Signal Name Pin
73 V_LCDDATA23 74
75 V_LCDDATA22 76
77 V_LCDDATA21 78
79 V_LCDDATA20 80
81 V_LCDDATA19 82
83 GND 84
85 FM_MAN_LAN_TYPE1 86
Signal Name
V_LCDDATA13
V_LCDDATA12
V_LCDDATA11
GND
V_LCDCNTL2
V_DVO_DDC_SDA
V_DVO_DDC_SCL
87 FM_MAN_LAN_TYPE1 88
89 Reserved - NC 90
91 Reserved - NC 92
93 MII_MDC_RMII_SPARE 94
RST_PS_PWRGD
Reserved - NC
Reserved - NC
95 MII_COL_RMIIB_RXER 96
97 GND 98
GND
MII_CRS_RMIIB_CRS
99 MII_TXER_RMIIB_TXEN 100 MII_TXCLK_RMIIB_RXCLK
101 MII_MDIO_RMIIB_PRESENT 102 GND
103 GND 104 MII_TXD3_RMIIB_TXD1
105 MII_RXD3_RMIIB_RXD1 106 MII_TXD2_RMIIB_TXD0
107 MII_RXD2_RMIIB_RXD0 108 GND
109 GND 110 MII_TXD1_RMIIA_TXD1
111 MII_RXD1_RMIIA_RXD1 112 MII_TXD0_RMIIA_TXD0
113 MII_RXD0_RMIIA_RXD0 114 GND
115 GND 116 MII_TXEN_RMIIA_TXEN
117 MII_RXCLK 118 MII_RXER_RMIIA_TXER
119 MII_RXDV_RMIIA_CRS 120 GND
5.3.2 Intel
®
RMM NIC Connector
The server board provides an internal 30-pin mezzanine style connector (J1B2) to accommodate a proprietary form factor RMM NIC module. The following table details the pin-out of the RMM NIC module connector.
46
Table 14. 30-pin Intel
®
RMM NIC Module Connector Pin-out (J1B2)
Pin Signal Name Pin Signal Name
1 FM_MAN_LAN_TYPE2 2 MII_MDC_RMII_SPARE
3 FM_MAN_LAN_TYPE1 4 MII_COL_RMIIB_RXER
5 GND 6 GND
9 MII_CRS_RMIIB_CRS 10 MII_MDIO_RMIIB_PRESENT
11 GND 12 GND
13 MII_TXD2_RMIIB_TXD0 14 MII_RXD3_RMIIB_RXD1
15 MII_TXD1_RMIIA_TXD1 16 MII_RXD3_RMIIB_RXD0
17 GND 18 GND
19 MII_TXD3_RMIIB_TXD1 20 MII_RXD1_RMIIA_RXD1
21 MII_TXD0_RMIIA_TXD0 22 MII_RXD0_RMIIA_RXD0
23 GND 24 GND
25 MII_TXEN_RMIIA_TXEN 26 MII_RXCLK
27 P3V3_AUX 28 P3V3_AUX
29 MII_RXER_RMIIA_RXER 30 MII_RXDV_RMIIA_CRS
Revision 1.9
Intel order number: D31979-010
Intel
®
Server Board S5000PAL / S5000XAL TPS Connector / Header Locations and Pin-outs
5.3.3 LCP/AUX IPMB Header
Table 15. LPC/AUX IPMB Header Pin-out (J1C2)
1
Pin Signal Name Description
SMB_IPMB_5VSB_DAT BMC IMB 5V Standby Data Line
2 GND
3 SMB_IPMB_5VSB_CLK
Ground
BMC IMB 5V Standby Clock Line
4 P5V_STBY
Table 16. IPMB Header Pin-out (J1C3)
1
Pin Signal Name Description
SMB_IPMB_5VSB_DAT BMC IMB 5V Standby Data Line
2 GND
3 SMB_IPMB_5VSB_CLK BMC IMB 5V Standby Clock Line
The server board has two riser card slots. The full height riser slot (J4F1) utilizes Intel
®
Adaptive Slot
Technology. It is capable of supporting riser cards that support either the PCI-X* or PCI Express* full height / full length add-in cards. The low profile riser slot (J5B1) supports riser cards that support low profile PCI Express* add-in cards. The following tables show the pin-out for these riser slots.
Table 17. Low-profile Riser Slot Pin-out (J5B1)
Pin Side B PCI Spec Signal Pin Side A PCI Spec Signal
1 P12V 1
2 P12V 2 P12V
3 P12V 3 P12V
4 GND 4 GND
5 SMB_PCI3V3SB_CLK 5 PD_LP_TCK
6 SMB_PCI3V3SB_DAT 6 PU_LP_TDI
Revision 1.9
9 PD_LPTRST_N 9 P3V3
10 P3V3_AUX 10 P3V3
11 PE_WAKE_N 11 PE_RST_LP_N
12 P3V3 12 GND
14
15
PE4_MCH_TXP_C <3..0> 0
PE4_MCH_TXN_C <3..0> 0
14
15
CLK_100M_LP_PCIE_SLOT1_N
GND
16 GND 16 PE4_MCH_RXP <3..0> 0
17 17 PE4_MCH_RXN <3..0> 0
18 GND 18 GND
19 PE4_MCH_TXP_C <3..0> 1 19 P3V3
Intel order number: D31979-010
47
Connector / Header Locations and Pin-outs
Pin Side B
20
PCI Spec Signal
PE4_MCH_TXN_C <3..0> 1
21
22
GND
GND
23
24
25
26
PE4_MCH_TXP_C <3..0> 2
PE4_MCH_TXN_C <3..0> 2
GND
GND
27
28
29
30
PE4_MCH_TXP_C <3..0> 3
PE4_MCH_TXN_C <3..0> 3
GND
P3V3
Intel
®
Server Board S5000PAL / S5000XAL TPS
Pin Side A
20
21
22
23
24
25
26
27
28
29
30
PCI Spec Signal
GND
PE4_MCH_RXP <3..0> 1
PE4_MCH_RXN <3..0> 1
GND
GND
PE4_MCH_RXP <3..0> 2
PE4_MCH_RXN <3..0> 2
GND
GND
PE4_MCH_RXP <3..0> 3
PE4_MCH_RXN <3..0> 3
33
34
35
36
37
38
39
40
41
42
PE5_MCH_TXP_C <3..0> 0
PE5_MCH_TXN_C <3..0> 0
GND
GND
PE5_MCH_TXP_C <3..0> 1
PE5_MCH_TXN_C <3..0> 1
GND
GND
PE5_MCH_TXP_C <3..0> 2
PE5_MCH_TXN_C <3..0> 2
33
34
35
36
37
38
39
40
41
42
CLK_100M_LP_PCIE_SLOT2_N
GND
PE5_MCH_RXP <3..0> 0
PE5_MCH_RXN <3..0> 0
GND
GND
PE5_MCH_RXP <3..0> 1
PE5_MCH_RXN <3..0> 1
GND
GND
43 GND 43 PE5_MCH_RXP <3..0> 2
44
45
46
47
GND
PE5_MCH_TXP_C <3..0> 3
PE5_MCH_TXN_C <3..0> 3
GND
44
45
46
47
PE5_MCH_RXN <3..0> 2
GND
GND
PE5_MCH_RXP <3..0> 3
48 FM_LP_RISER_TYPE1 48 PE5_MCH_RXN <3..0> 3
49 FM_LP_RISER_TYPE0 49 GND
48
Table 18. Full-height Riser Slot Pin-out (J4F1)
Pin-Side B PCI Spec Signal Pin-Side A PCI Spec Signal
140 12V
139 12V
140 12V
139 12V
138 Ground 138 GND
137 -12V 137 3.3VAux
136 12V
135 GND
136 Wake#
135 12V
132 GND
131 GND
132 GND
131 REFCLK1+
130 HSOp(0) 130 REFCLK1+
129 HSOn(0) 129 GND
Revision 1.9
Intel order number: D31979-010
Intel
®
Server Board S5000PAL / S5000XAL TPS Connector / Header Locations and Pin-outs
Pin-Side B PCI Spec Signal Pin-Side A PCI Spec Signal
128 GND
127 GND
128 HSIp(0)
127 HSIn(0)
126 HSOp(1) 126 GND
125 HSOn(1) 125 GND
124 GND
123 GND
124 HSIp(1)
123 HSIn(1)
122 HSOp(2) 122 GND
121 HSOn(2) 121 GND
120 GND
119 GND
120 HSIp(2)
119 HSIn(2)
118 HSOp(3) 118 GND
117 HSOn(3) 117 GND
116 GND
115 GND
116 HSIp(3)
115 HSIn(3)
114 HSOp(4) 114 GND
113 HSOn(4) 113 GND
112 GND
111 GND
112 HSIp(4)
111 HSIn(4)
110 HSOp(5) 110 GND
109 HSOn(6) 109 GND
108 GND
107 GND
108 HSIp(5)
107 HSIn(5)
106 HSOp(6) 106 GND
105 HSOn(6) 105 GND
104 GND
103 GND
104 HSIp(6)
103 HSIn(6)
102 HSOp(7) 102 GND
101 HSOn(7) 101 GND
100 GND 100 HSIp(7)
99 +5V 99 HSIn(7)
98 INTB# 98 GND
97 INTD# 97 ZCR_PRSNT_L
96 +5V 96 +5V
95 Reserved 95 +5V
94 +5V 94 ZCR_MSKID_L
Revision 1.9
91 GND 91 INTC#
90 CLK3 90 GND
89 GND 89 REQ3#
88 CLK2 88 GND
87 GND 87 GNT3#
86 REQ2# 86 GND
85 GND 85 RST#
84 Reserved 84 GND
83 GND 83 Reserved
KEY KEY
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49
Connector / Header Locations and Pin-outs Intel
®
Server Board S5000PAL / S5000XAL TPS
Pin-Side B PCI Spec Signal Pin-Side A PCI Spec Signal
KEY KEY
82 Reserved 82 +5V
81 GND 81 Reserved
80 CLK1 80 GND
79 Ground 79 GNT2#
78 REQ1# 78 +3.3V
77 +3.3V 77 GNT1#
76 PME2# 76 Ground
75 AD[31] 75 PME1#
74 AD[29] 74 PME3#
73 Ground 73 AD[30]
72 AD[27] 72 +3.3V
71 AD[25] 71 AD[28]
70 +3.3V 70 AD[26]
69 C/BE[3]# 69 Ground
68 AD[23] 68 AD[24]
67 Ground 67 RSVRD
66 AD[21] 66 +3.3V
65 AD[19] 65 AD[22]
64 +3.3V 64 AD[20]
63 AD[17] 63 Ground
62 C/BE[2]# 62 AD[18]
61 Ground 61 AD[16]
60 IRDY# 60 +3.3V
59 +3.3V 59 FRAME#
50
56 LOCK# 56 Ground
55 PERR# 55 STOP#
54 +3.3V 54 +3.3V
53 SERR# 53 SMBD
52 +3.3V 52 SMBCLK
51 C/BE[1]# 51 Ground
50 AD[14] 50 PAR
49 Ground 49 AD[15]
48 AD[12] 48 +3.3V
47 AD[10] 47 AD[13]
46 M66EN 46 AD[11]
45 Ground 45 Ground
44 Ground 44 AD[09]
43 AD[08] 43 C/BE[0]#
42 AD[07] 42 +3.3V
41 +3.3V 41 AD[06]
40 AD[05] 40 AD[04]
39 AD[03] 39 Ground
38 Ground 38 AD[02]
37 AD[01] 37 AD[00]
Revision 1.9
Intel order number: D31979-010
Intel
®
Server Board S5000PAL / S5000XAL TPS Connector / Header Locations and Pin-outs
Pin-Side B PCI Spec Signal Pin-Side A PCI Spec Signal
36 +3.3V 36 +3.3V
35 ACK64# 35 REQ64#
34 +5V
33 +5V
34 +5V
33 +5V
32 Reserved 32 +5V
31 Ground 31 C/BE[7]#
30 C/BE[6]# 30 C/BE[5]#
29 C/BE[4]# 29 Ground
28 Ground 28 PAR64
27 AD[63] 27 AD[62]
26 AD[61] 26 3.3V
25 3.3V 25 AD[60]
24 AD[59] 24 AD[58]
23 AD[57] 23 Ground
22 Ground 22 AD[56]
21 AD[55] 21 AD[54]
20 AD[53] 20 3.3V
19 Ground 19 AD[52]
18 AD[51] 18 AD[50]
17 AD[49] 17 Ground
16 3.3V 16 AD[48]
15 AD[47] 15 AD[46]
14 AD[45] 14 Ground
13 Ground 13 AD[44]
12 AD[43] 12 AD[42]
KEY KEY
KEY KEY
11 AD[41] 11 3.3V
10 Ground 10 AD[40]
9 AD[39] 9 AD[38]
8 AD[37] 8 Ground
7 3.3V 7 AD[36]
6 AD[35] 6 AD[34]
5 AD[33] 5 Ground
4 Ground 4 AD[32]
3 Type1 3 PXH_RST_N
2 Type0 2 Ground
1 Size 1 PXH_PWROK
Revision 1.9
Intel order number: D31979-010
51
Connector / Header Locations and Pin-outs Intel
®
Server Board S5000PAL / S5000XAL TPS
5.5 SSI Control Panel Connector
The server board provides a 24-pin SSI control panel connector (J3H2) for use with non-Intel chassis.
The following table provides the pin-out for this connector.
Table 19. Front Panel SSI Standard 24-pin Connector Pin-out (J3H2)
Pin Signal Name
1 P3V3_STBY
Pin Signal Name
2 P3V3_STBY
3 Key 4 P5V_STBY
5 FP_PWR_LED_L 6 FP_ID_LED_L
7 P3V3 8 FP_STATUS_LED1_R
11 FP_PWR_BTN_L 12 LAN_ACT_A_L
13 GND 14 LAN_LINKA_L
17 GND
19 FP_ID_BTN_L
21 TEMP_SENSOR
23 FP_NMI_BTN_L
16 PS_I2C_3VSB_SDA
18 PS_I2C_3VSB_SCL
20 FP_CHASSIS_INTRU
22 LAN_ACT_B_L
24 LAN_LINKB_L
5.6 Bridge Board Connector
For use in supported Intel
®
Server Chassis, the server board provides a 120-pin high-density bridge board connector (J4G1) to route control panel, mid-plane, and backplane signals from the server board to the specified system board. The following table provides the pin-outs for this connector.
52
Table 20. 120-pin Bridgeboard Connector Pin-out (J4G1)
Pin Signal Name Pin Signal Name
A1 SMB_HOST_3V3_CLK B1 GND
A2 SMB_HOST_3V3_DAT B2 PE1_ESB_TXN_C<3>
A4 GND B4 GND
A5 PE1_ESB_RXN_C<3> B5 PE_WAKE_N
A6 PE1_ESB_RXP_C<3> B6 GND
A7 GND B7 PE1_ESB_TXN_C<2>
A8 FM_FAN_D_PRSNT6 B8 PE1_ESB_TXP_C<2>
A9 GND B9 GND
A10 PE1_ESB_RXN_C<2> B10 FM_FAN_D_PRSNT5
A11 PE1_ESB_RXP_C<2> B11 GND
A12 GND
A13 FM_FAN_D_PRSNT4
B12 PE1_ESB_TXN_C<1>
B13 PE1_ESB_TXP_C<1>
A14 GND B14 GND
A15 PE1_ESB_RXN_C<1> B15 RST_MP_PWRGD
A16 PE1_ESB_RXP_C<1> B16 GND
A17 GND B17 PE1_ESB_TXN_C<0>
A18 FM_RAID_PRESENT B18 PE1_ESB_TXP_C<0>
Revision 1.9
Intel order number: D31979-010
Intel
®
Server Board S5000PAL / S5000XAL TPS Connector / Header Locations and Pin-outs
Pin Signal Name
A19 GND
Pin Signal Name
B19 GND
A20 PE1_ESB_RXN_C<0> B20 FM_RAID_MODE
A21 PE1_ESB_RXP_C<0> B21 GND
A22 GND B22 CLK_100M_SRLAKE_N
A23 FM_FAN_D_PRSNT1 B23 CLK_100M_SRLAKE_P
A24 FM_FAN_D_PRSNT3 B24 GND
A25 FM_FAN_D_PRSNT2 B25 SGPIO_DATAOUT1_R
A26 GND
A27 USB_ESB_P4P
A28 USB_ESB_P4N
A29 GND
B26 SGPIO_DATAOUT0_R
B27 SGPIO_LOAD_R
B28 SGPIO_CLOCK_N
B29 GND
A30 USB_ESB_OC_N<4> B30 USB_ESB_P2P
A31 USB_ESB_OC_N<3> B31 USB_ESB_P2N
A32 GND
A33 USB_ESB_P3P
B32 GND
B33 USB_ESB_OC_N<2>
A34 USB_ESB_P3N
A35 GND
B34 NIC1_LINK_LED_N
B35 NIC1_ACT_LED_N
A36 FP_NMI_BTN_N B36 LED_STATUS_GREEN_R1
KEY KEY
A37 BMC_RST_BTN_N
A38 FP_PWR_BTN_N
A39 FP_ID_BTN
A40 GND
B37 NIC2_LINK_LED_N
B38 NIC2_ACT_LED_N
B39 LED_STATUS_AMBER_R1
B40 GND
A43 GND B43 GND
A45 P3V3 B45 V_IO_VSYNC2_BUF_FP
A46 FP_PWR_LED_N_R B46 GND
A47 P3V3_STBY B47 V_IO_BLUE_CONN_FP
A48 FP_ID_LED_R1_N B48 V_IO_GREEN_CONN_FP
A49 FM_SIO_TEMP_SENSOR B49 V_IO_RED_CONN_FP
A50 LED_FAN3_FAULT
A51 LED_FAN2_FAULT
B50 GND
B51 LED_FAN10_FAULT
A52 LED_FAN1_FAULT
A53 FAN_PWM_CPU1
A54 GND
A55 FAN_PWM_CPU2
A56 PCI_FAN_TACH9
A57 FAN_TACH7
A58 FAN_TACH5
A59 FAN_TACH3_H7
A60 FAN_TACH1_H7
B52 LED_FAN5_FAULT
B53 LED_FAN4_FAULT
B54 FAN_IO_PWM
B55 GND
B56 PCI_FAN_TACH10
B57 FAN_TACH8
B58 FAN_TACH6
B59 FAN_TACH4_H7
B60 FAN_TACH2_H7
Revision 1.9
Intel order number: D31979-010
53
Connector / Header Locations and Pin-outs Intel
®
Server Board S5000PAL / S5000XAL TPS
5.7 I/O Connector Pin-out Definition
The following table details the pin-out definition of the VGA connector (J6A1).
Table 21. VGA Connector Pin-out (J6A1)
1
Pin
2
3
Signal Name
V_IO_R_CONN
V_IO_G_CONN
V_IO_B_CONN
4 TP_VID_CONN_B4
5 GND
6 GND
7 GND
8 GND
9 TP_VID_CONN_B9
10 GND
11 TP_VID_CONN_B11
12 V_IO_DDCDAT
13
14
V_IO_HSYNC_CONN
V_IO_VSYNC_CONN
15 V_IO_DDCCLK
Description
Red (analog color signal R)
Green (analog color signal G)
Blue (analog color signal B)
Ground
Ground
Ground
Ground
Ground
DDCDAT
HSYNC (horizontal sync)
VSYNC (vertical sync)
DDCCLK
The server board provides two RJ45 NIC connectors oriented side by side on the back edge of the board
(JA8A1, JA8A2). The pin-out for each connector is identical and is defined in the following table.
54
Table 22. RJ-45 10/100/1000 NIC Connector Pin-out (JA8A1, JA8A2)
Pin Signal Name
1 GND
2 P1V8_NIC
3 NIC_A_MDI3P
4 NIC_A_MDI3N
5 NIC_A_MDI2P
6 NIC_A_MDI2N
7 NIC_A_MDI1P
8 NIC_A_MDI1N
9 NIC_A_MDI0P
10 NIC_A_MDI0N
11 (D1) NIC_LINKA_1000_N (LED
12 (D2) NIC_LINKA_100_N (LED)
13 (D3) NIC_ACT_LED_N
14 NIC_LINK_LED_N
15 GND
16 GND
Revision 1.9
Intel order number: D31979-010
Intel
®
Server Board S5000PAL / S5000XAL TPS Connector / Header Locations and Pin-outs
The server board includes an IDE connector to access the single IDE channel from the ESB-2 IO controller hub. The design intent for this connector is to provide IDE support for a single slim-line optical drive, such as CDROM or DVD. The connector is not a standard 40-pin IDE connector, instead it has 44 pins providing support for both power and IO signals. The pin-out for this connector is defined in the following table.
Table 23. 44-pin IDE Connector Pin-out (J3G1)
Pin Signal Name Pin Signal Name
1 ESB_PLT_RST_IDE_N 2 GND
3 RIDE_DD_7
5 RIDE_DD_6
4 RIDE_DD_8
6 RIDE_DD_9
8 RIDE_DD_10 7 RIDE_DD_5
9 RIDE_DD_4
11 RIDE_DD_3
13 RIDE_DD_2
15 RIDE_DD_1
17 RIDE_DD_0
19 GND
21 RIDE_DDREQ
12 RIDE_DD_12
14 RIDE_DD_13
16 RIDE_DD_14
18 RIDE_DD_15
20 KEY
22 GND
23 RIDE_DIOW_N
25 RIDE_DIOR_N
27 RIDE_PIORDY
29 RIDE_DDACK_N
24 GND
26 GND
28 GND
30 GND
31 IRQ_IDE
33 RIDE_DA1
35 RIDE_DA0
37 RIDE_DCS1_N
39 LED_IDE_N
41 P5V
43 GND
32 TP_PIDE_32
34 IDE_PRI_CBLSNS
36 RIDE_DA2
38 RIDE_DCS3_N
40 GND
42 P5V
44 GND
5.7.4 Intel
®
I/O Expansion Module Connector
The server board provides an internal 50-pin mezzanine style connector (J3B1) to accommodate proprietary form factor Intel ® I/O Expansion Modules, which expand the IO capabilities of the server board without sacrificing an add-in slot from the riser cards. There are three planned IO modules for use on this server board: external 4 port SAS, dual Gb NIC, and Infiniband*. For more detail on the supported IO modules, please refer to the Intel
®
Server Board S5000PAL / S5000XAL IO Module Hardware
Specification . The following table details the pin-out of the Intel
®
I/O Expansion Module connector.
Revision 1.9
Intel order number: D31979-010
55
Connector / Header Locations and Pin-outs Intel
®
Server Board S5000PAL / S5000XAL TPS
Table 24. 50-pin Intel
®
I/O Expansion Module Connector Pin-out (J3B1)
Pin Signal Name
1 P3V3_AUX
3 PE_RST_G2_PM_N
5 GND
Pin Signal Name
2 P3V3_AUX
4 GND
6 PE2_ESB_RXP_C<0>
7 GND 8 PE2_ESB_RXN_C<0>
9 PE2_ESB_TXP_C<0> 10 GND
11 PE2_ESB_TXN_C<0> 12 GND
13 GND
15 GND
14 PE2_ESB_RXP_C<1>
16 PE2_ESB_RXN_C<1>
17 PE2_ESB_TXP_C<2> 18 GND
19 PE2_ESB_TXN_C<2> 20 GND
21 GND
22 GND
22 PE2_ESB_RXP_C<2>
24 PE2_ESB_RXN_C<2>
25 PE2_ESB_TXP_C<1> 26 GND
27 PE2_ESB_TXN_C<1> 28 GND
29 GND
31 GND
30 PE2_ESB_RXP_C<3>
32 PE2_ESB_RXN_C<3>
33 PE2_ESB_TXP_C<0> 34 GND
35 PE2_ESB_TXN_C<0> 36 GND
37 GND
39 GND
38 CLK_100M_LP_PCIE_SLOT3_P
40 CLK_100M_LP_PCIE_SLOT3_N
41 PE_WAKE_N
43 P3V3
45 P3V3
47 P3V3
49 P3V3
42 GND
44 P3V3
46 P3V3
48 P3V3
50 P3V3
The server board provides six SATA (Serial ATA) connectors: SATA-0 (J1H1), SATA-1 (J1G2), SATA-2
(J1G1), SATA-3 (J1F2), SATA-4 (J1F1), and SATA-5 (J1E3), for use with an internal SATA backplane.
The pin configuration for each connector is identical and is defined in the following table.
Table 25. SATA Connector Pin-out (J1H1, J1G2, J1G1, J1F2, J1E3)
Pin Signal Name
1 GND
2 SATA#_TX_P_C
3 SATA#_TX_N_C
4 GND
5
6
SATA#_RX_N_C
SATA#_RX_P_C
7 GND
Description
GND1
Positive side of transmit differential pair
Negative side of transmit differential pair
GND2
Negative side of Receive differential pair
Positive side of Receive differential pair
GND3
56 Revision 1.9
Intel order number: D31979-010
Intel
®
Server Board S5000PAL / S5000XAL TPS Connector / Header Locations and Pin-outs
The server board provides one external RJ45 Serial ‘B’ port (J9A2) and one internal 9-pin Serial ‘A’ port header (J1B1). The following tables define the pin-outs for each.
Table 26. External RJ-45 Serial ‘B’ Port Pin-out (J9A2)
1
2
3
6
Pin Signal Name
SPB_RTS
SPB_DTR
SPB_OUT_N
4 GND
5 SPB_RI
SPB_SIN_N
Description
RTS (request to send)
DTR (Data terminal ready)
TXD (Transmit data)
Ground
RI (Ring Indicate)
RXD (receive data)
Data Set Ready / Data Carrier Detect 1
CTS (clear to send) 8 SPB_CTS
Note:
1
A jumper block on the server board will determine whether DSR or DCD is routed to pin 7. The board will have the jumper block configured with DSR enabled at production.
Table 27. Internal 9-pin Serial ‘A’ Header Pin-out (J1B1)
4
5
6
7
Pin Signal Name
1 SPA_DCD
2
3
SPA_DSR
SPA_SIN_L
SPA_RTS
SPA_SOUT_N
SPA_CTS
SPA_DTR
8 SPA_RI
9 GND
Description
DCD detect)
DSR (data set ready)
RXD (receive data)
RTS (request to send)
TXD (Transmit data)
CTS (clear to send)
DTR (Data terminal ready)
RI (Ring Indicate)
Ground
5.7.7 Keyboard and Mouse Connector
Two stacked PS/2 ports (J9A1) are provided to support both a keyboard and a mouse. Either PS/2 port can support a mouse or keyboard. The following table details the pin-out of the PS/2 connector.
Revision 1.9
Table 28. Stacked PS/2 Keyboard and Mouse Port Pin-out (J9A1)
Description Pin Signal Name
1 KB_DATA_F
2 TP_PS2_2
3 GND
4 P5V_KB_F
5 KB_CLK_F
6 TP_PS2_6
7 MS_DAT_F
8 TP_PS2_8
9 GND
Test point – keyboard
Ground
Keyboard / mouse power
Test point – keyboard / mouse
Test point – keyboard / mouse
Ground
Intel order number: D31979-010
57
Connector / Header Locations and Pin-outs
Pin
10
Signal Name
P5V_KB_F
11 MS_CLK_F
12 TP_PS2_12
13 GND
14 GND
15 GND
16 GND
17 GND
Intel
®
Server Board S5000PAL / S5000XAL TPS
Description
Keyboard / mouse power
Test point – keyboard / mouse
Ground
Ground
Ground
Ground
Ground
5.7.8 USB 2.0 Connectors
The following table details the pin-out of the external USB connectors (J5A1, J6A2) found on the back edge of the server board.
Table 29. External USB Connector Pin-out (J5A1, J6A2)
Pin Signal Name
1 USB_OC#_FB_1 USB_PWR
2 USB_P#N_FB_2
3 USB_P#N_FB_2
4 GND
Description
DATAL0 (Differential data line paired with DATAH0)
DATAH0 (Differential data line paired with DATAL0)
Ground
One 2x5 header on the server board (J1J1) provides an option to support an additional two USB 2.0 ports.
The pin-out of the connector is detailed in the following table.
Table 30. Internal USB Connector Pin-out (J1J1)
1
Pin
2
3
4
5
6
Signal Name
P5V_USB2_VBUS0
P5V_USB2_VBUS1
7 Ground
8 Ground
Description
USBpower port 0
USBpower port 1
USB_ESB_P0N_CONN USB port 0 negative signal
USB_ESB_P1N_CONN USB port 1 negative signal
USB_ESB_P0P_CONN USB port 0 positive signal
USB_ESB_P1P_CONN USB port 1 positive signal
Ground
Ground
58 Revision 1.9
Intel order number: D31979-010
Intel
®
Server Board S5000PAL / S5000XAL TPS Connector / Header Locations and Pin-outs
The server board incorporates three system fan circuits which support a total of six SSI compliant 4-pin fan connectors. Two fan connectors are designated as processor cooling fans, CPU1 Fan (J9K1) and
CPU2 Fan (J5K1). These connectors can support CPU fans that draw a maximum of 1.2 Amps each.
Two system fan connectors can be found towards the front edge of the server board, System Fan 1
(J3K1), System Fan 2 (J3K2). These connectors are capable of supporting a maximum fan load of 3.5
Amps each. Two additional system fan connectors can be found near the back edge of the server board,
System Fan 3(J7A1) and System Fan 4 (J7A2). These two connectors are capable of supporting a maximum fan load of 2.5 Amps per connector. With the proper Sensor Data Record (SDR) installed,
Server Management software can monitor all system fans in use.
The pin configuration for each fan connector is identical and is defined in the following table.
1
Pin
2
3
4
Table 31. SSI Fan Connector Pin-out (J9K1,J5K1,J3K1,J3K2,J7A2,J7A1)
Signal Name
Ground
12V
Fan Tach
Fan PWM
Type
GND
Description
GROUND is the power supply ground
Power Power supply 12V
Out FAN_TACH signal is connected to the BMC to monitor the fan speed
In FAN_PWM signal to control fan speed
Note : Intel Corporation server baseboards support peripheral components and contain a number of highdensity VLSI and power delivery components that need adequate airflow to cool. Intel’s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together. It is the responsibility of the system integrator that chooses not to use
Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental conditions. Intel
Corporation can not be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non-operating limits
Revision 1.9
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59
Jumper Block Settings Intel
®
Server Board S5000PAL / S5000XAL TPS
The server board has several 2-pin and 3-pin jumper blocks that can be used to configure, protect, or recover specific features of the server board. Pin 1 on each jumper block is denoted by an “*” or “ ▼ ”.
6.1 Recovery Jumper Blocks
Table 32. Recovery Jumpers (J1D1, J1D2, J1D3)
Jumper Name Pins
J1D1: BMC Force
Update
What happens at system reset…
1-2
BMC Firmware Force Update Mode – Disabled
(Default)
2-3 BMC Firmware Force Update Mode – Enabled
J1D2: Password
Clear
1-2 These pins should have a jumper in place for normal system operation. (Default)
2-3 If these pins are jumpered, administrator and user passwords will be cleared immediately. These pins should not be jumpered for normal operation.
J1D3: CMOS
Clear
1-2 These pins should have a jumper in place for normal system operation. (Default)
2-3 If these pins are jumpered, the CMOS settings will be cleared immediately. These pins should not
be jumpered for normal operation
BMC Force
Update Mode
2
3
J1D2
Password
Reset
2
3
J1D1
Disable
Enable
2
3
J1D3
Clear
CMOS
Figure 17. Recovery Jumper Blocks (J1D1, J1D2, J1D3)
TP02080
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®
Server Board S5000PAL / S5000XAL TPS Jumper Block Settings
6.1.1 CMOS Clear and Password Reset Usage Procedure
The CMOS Clear (J1D3) and Password Reset (J1D2) recovery features are designed so that the desired operation can be achieved with minimal system down time. The usage procedure for these two features has changed from previous generation Intel
®
Server Boards. The following procedure outlines the new usage model.
CMOS Clear Procedure:
1. Power down the server; do not remove AC power.
2. Open the server and move the jumper from the default operating position (pins1-2) to the “clear” position (pins 2-3).
4. Move the jumper back to the default position (pins 1-2).
5. Close the server system and power up the server.
6. CMOS is now cleared and can be reset by going into the BIOS setup.
Password Reset Procedure:
1. Power down the server; do not remove AC power.
2. Open the server and move the jumper from the default operating position (pins1-2) to the “reset” position (pins 2-3).
3. Power up the server.
4. The password is now cleared.
5. Power down the server; do not remove AC power.
6. Move the jumper back to the default position (pins 1-2) and close the server system.
7. The password can be reset by going into the BIOS setup.
Note: Removing AC power before performing the CMOS clear operation will cause the system to automatically power up and immediately power down, after the procedure is followed and AC power is reapplied. Should this occur, remove the AC power cord again, wait 30 seconds, and re-install the AC power cord. Power up system and proceed to the <F2> BIOS Setup Utility to reset desired settings.
6.1.2 BMC Force Update Procedure
When performing a standard BMC firmware update procedure, the update utility places the BMC into an update mode, allowing the firmware to load safely onto the flash device. In the unlikely event that the
BMC firmware update process fails due to the BMC not being in the proper update state, the server board provides a BMC Force Update jumper (J1D1) which will force the BMC into the proper update state. The following procedure should be following in the event the standard BMC firmware update process fails.
1. Power down the server and remove AC power.
2. Open the server and move the jumper from the default operating position (pins1-2) to the
“enabled” position (pins 2-3).
3. Close the server system and reconnect AC power and power up the server.
4. Perform the standard BMC firmware update procedure as documented in README.TXT file that is included in the given BMC Firmware Update package.
5. After successful completion of the firmware update process, the firmware update utility may generate an error stating that the BMC is still in update mode.
6. Power down and remove AC power.
7. Open the server and move the jumper from the “enabled” position (pins 2-3) to the “disabled” position (pins 1-2).
8. Close the server system and reconnect AC power and power up the server.
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Jumper Block Settings Intel
®
Server Board S5000PAL / S5000XAL TPS
Note: Normal BMC functionality is disabled with the force BMC update jumper set to the “enabled” position. The server should never be run with the BMC force update jumper set in this position and should only be used when the standard firmware update process fails. This jumper should remain in the default – disabled position when the server is running normally.
6.2 BIOS Select Jumper
The jumper block at J3H1, located just to the left of the SSI control panel header, is used to select which
BIOS image the system will boot to. Pin 1 on the jumper is identified with a ‘ ▼ ’. This jumper should only be moved if you wish to force the BIOS to boot to the secondary bank which may hold a different version of BIOS.
3 2
1-2: Force BIOS to bank 0
J3H1
3 2
2-3: System is configured for normal operation
(factory default)
TP02305
Figure 18. BIOS Select Jumper (J3H1)
Pins
1-2
2-3
What happens at system reset…
Force BIOS to a alternative bank
System is configured for normal operation
(Default)
BIOS update is supported when the Recovery Jumper is either set on pins 1-2 (recovery mode), or pins
2-3 (normal mode).
To perform a normal BIOS update, follow the below steps:
1. Boot the system with the jumper covering pins 2 and 3.
2. Update the BIOS using iFlash or the Intel® One Flash Update (OFU) utility.
3. Reset the system.
4. The system will boot from the new BIOS.
If the system can not boot, perform the below steps to recover:
62
1. Boot the system with the jumper covering pins 1 and 2.
2. Update the BIOS using iFlash or the Intel® One Flash Update (OFU) utility.
3. Power down the server and unplug the AC power cord.
4. Move the recovery jumper back to the normal position.
5. Plug in the power cord and power on the system.
6. The system will boot from the new BIOS.
Revision 1.9
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Intel
®
Server Board S5000PAL / S5000XAL TPS Jumper Block Settings
6.3 External RJ45 Serial Port Jumper Block
The jumper block J8A3, located directly behind the external RJ45 serial port, is used to configure either a
DSR or a DCD signal to the connector.
J8A3
2
3 4
1-2: DCD to DTR 3-4: DSR to DTR
(factory default)
TP02303
Figure 19. External RJ45 Serial Port Configuration Jumper
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Light Guided Diagnostics Intel
®
Server Board S5000PAL / S5000XAL TPS
The server board has several on-board diagnostic LEDs to assist in troubleshooting board level issues.
This section shows where each LED is located and provides a high level usage description. For a more detailed description of what drives the diagnostic LED operation, refer to the Intel
®
S5000 Series Chipsets
Server Board Family Datasheet.
7.1 5-Volt Standby LED
Several server management features of this server board require that a 5 volt stand-by voltage be supplied from the power supply. Some of the features and components that require this voltage be present when the system is “Off” include the BMC within the ESB-2, onboard NICs, and optional Intel
®
RMM.
The LED located just below the system recovery jumper block labeled “5V STBY” is illuminated when AC power is applied to the platform and 5 Volt standby voltage is supplied to the server board by the power supply.
TP02307
Figure 20. 5V Standby Status LED Location
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7.2 System ID LED and System Status LED
The server board provides LEDs for both System ID and System Status.
ID LED Status LED
Light Guided Diagnostics
TP02309
Figure 21. System ID LED and System Status LED Locations.
The blue “System ID” LED can be illuminated using either of two mechanisms.
• By pressing the System ID Button on the system control panel the ID LED will display a solid blue color, until the button is pressed again.
• By issuing the appropriate hex IPMI “Chassis Identify” value, the ID LED will either blink blue for
15 seconds and turn off or will blink indefinitely until the appropriate hex IPMI Chassis Identify value is issued to turn it off.
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Light Guided Diagnostics
The bi-color System Status LED will operate as follows:
Intel
®
Server Board S5000PAL / S5000XAL TPS
Color
Off
Green /
Amber
State
N/A
Alternating
Blink
Green Solid on
Green Blink
Amber Blink
Criticality
Not ready
Not ready
System OK
Degraded
Non-critical
Description
AC power off
Pre DC Power On – 15-20 second BMC Initialization when AC is applied to the server. Control Panel buttons are disabled until BMC initialization is complete.
System booted and ready. degraded
• Unable to use all of the installed memory (more than one
DIMM installed).
• Correctable errors over a threshold of 10 and migrating to a spare DIMM (memory sparing). This indicates that the user no longer has spared DIMMs indicating a redundancy lost condition. Corresponding DIMM LED should light up.
• In mirrored configuration, when memory mirroring takes place and system loses memory redundancy. This is not covered by (2).
• Redundancy loss such as power-supply or fan. This does not apply to non-redundant sub-systems.
• PCI-e link errors
• CPU failure / disabled – if there are two processors and one of them fails
• Fan alarm – Fan failure. Number of operational fans should be more than minimum number needed to cool the system
• Non-critical threshold crossed – Temperature and voltage
• Chassis Intrusion events, including lost LAN connection
Non-fatal alarm – system is likely to fail
• Critical voltage threshold crossed
• VRD hot asserted
• Minimum number of fans to cool the system not present or failed
• In non-sparing and non-mirroring mode if the threshold of ten correctable errors is crossed within the window
Amber Solid on Critical, nonrecoverable
Fatal alarm – system has failed or shutdown
• DIMM failure when there is one DIMM present, no good memory present
• Run-time memory uncorrectable error in non-redundant mode
• IERR signal asserted
• Processor 1 missing
• Temperature (CPU ThermTrip, memory TempHi, critical threshold crossed)
• No power good – power fault
• Processor configuration error (for instance, processor stepping mismatch)
7.2.1 System Status LED – BMC Initialization
When the AC power is first applied to the system and 5V-STBY is present, the BMC controller on the server board requires 15-20 seconds to initialize. During this time, the system status LED will blink, alternating between amber and green, and the power button functionality of the control panel is disabled preventing the server from powering up. Once BMC initialization has completed, the status LED will stop blinking and the power button functionality is restored and can be used to turn on the server.
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7.3 DIMM Fault LEDs
Light Guided Diagnostics
The server board provides a memory fault LED for each DIMM slot. The DIMM fault LED is illuminated when the system BIOS disables the specified DIMM after it reaches a specified number of given failures or if specific critical DIMM failures are detected. See the Intel
®
Family Datasheet for more details.
S5000 Series Chipsets Server Board
TP02310
Figure 22. DIMM Fault LED Locations
7.4 Processor Fault LED
The server board provides a Processor Fault LED for each of the two processor sockets. These LEDs will illuminate when a CPU is disabled or a CPU configuration error is detected.
CPU 2 CPU 1
TP02311
Figure 23. Processor Fault LED Location
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Light Guided Diagnostics Intel
®
Server Board S5000PAL / S5000XAL TPS
7.5 Post Code Diagnostic LEDs
During the system boot process, BIOS executes a number of platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, BIOS will display the given POST code to the POST code diagnostic LEDs found on the back edge of the server board. To assist in troubleshooting a system hang during the POST process, the diagnostic LEDs can be used to identify the last POST process to be executed. See Appendix C for a complete description of how these LEDs are read, and for a list of all supported POST codes.
Figure 24. POST Code Diagnostic LED Location
TP02312
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®
Server Board S5000PAL / S5000XAL TPS Power and Environmental Specifications
8. Power and Environmental Specifications
8.1 Intel® Server Board S5000PAL / S5000XAL Design
Specifications
Operation of the server board at conditions beyond those shown in the following table may cause permanent damage to the system. Exposure to absolute maximum rating conditions for extended periods may affect system reliability.
Table 33: Server Board Design Specifications
Operating Temperature
Non-Operating Temperature
DC Voltage
Shock (Unpackaged)
Shock (Packaged)
< 20 lbs
≥ 20 to < 40
≥ 40 to < 80
≥ 80 to < 100
≥ 100 to < 120
≥ 120
0º C to 55º C 1 (32º F to 131º F)
-40º C to 70º C (-40º F to 158º F)
± 5% of all nominal voltages
Trapezoidal, 50 g, 170 inches/sec
36 inches
30 inches
24 inches
18 inches
12 inches
9 inches
Vibration (Unpackaged) 5 Hz to 500 Hz 3.13 g RMS random
Note:
1
Chassis design must provide proper airflow to avoid exceeding the Dual-Core Intel
®
Xeon
® processor 5000 sequence maximum case temperature.
Disclaimer Note : Intel Corporation server boards support add-in peripherals and contain a number of high-density VLSI and power delivery components that need adequate airflow to cool. Intel ensures through its own chassis development and testing that when Intel server building blocks are used together, the fully integrated system will meet the intended thermal requirements of these components. It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental conditions. Intel Corporation cannot be held responsible, if components fail or the server board does not operate correctly when used outside any of their published operating or non-operating limits.
Revision 1.9
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Power and Environmental Specifications Intel
®
Server Board S5000PAL / S5000XAL TPS
8.2 Server Board Power Requirements
This section provides power supply design guidelines for a system using the Intel® Server Board
S5000PAL / S5000XAL, including voltage and current specifications, and power supply on/off sequencing characteristics. The following diagram shows the power distribution implemented on this server board.
Figure 25. Power Distribution Block Diagram
8.2.1 Processor Support
The server board supports the Thermal Design Point (TDP) guideline for Dual-Core Intel ® Xeon ® processors 5000 sequence. The Flexible Motherboard Guidelines (FMB) has also been followed to help determine the suggested thermal and current design values for anticipating future processor needs. The following table provides maximum values for Icc, TDP power and T
CASE processor 5000 sequence family.
for the Dual-Core Intel
®
Xeon
®
Table 34. Dual-Core Intel
®
Xeon
®
Processor 5000 Sequence TDP Guidelines per processor
TDP Power
130 W
Max TCASE
70º C
Icc MAX
150 A
Note:
Datasheet contains the actual specifications for the processor. If the values found in the Dual-Core Intel
Xeon
Xeon
®
®
These values are for reference only. The
processor 5000 sequence Datasheet are different than those published here, the Dual-Core Intel
processor 5000 sequence Datasheet
Dual-Core Intel
®
Xeon
®
processor 5000 sequence
values will supersede these, and should be used.
®
®
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Server Board S5000PAL / S5000XAL TPS Power and Environmental Specifications
8.2.2 Power Supply Output Requirements
This section is for reference purposes only. Its intent is to provide guidance to system designers for determining a proper power supply for use with this server board. The contents of this section specify the power supply requirements Intel used to develop a power supply for its 1U server platform.
The combined power of all outputs shall not exceed the rated output power of the power supply. The power supply must meet both static and dynamic voltage regulation requirements for the minimum loading conditions.
Table 35. 600W Load Ratings
Voltage
+3.3 V
+5 V
+12 V1
+12 V2
+12 V3
+12 V4
-12 V
+5 VSB
Minimum
Continuous
1.5 A
1.0 A
0.5 A
0.5 A
0.5 A
0.5 A
0 A
0.1 A
Maximum
Continuous
10 A
20 A
16 A
16 A
16 A
16 A
0.5 A
3.0 A
1. Maximum continuous total DC output power should not exceed 600W.
2. Peak load on the combined 12 V output shall not exceed 49A.
Peak
3. Maximum continuous load on the combined 12 V output shall not exceed 44A.
4. Peak total DC output power should not exceed 650W.
5. Peak power and current loading shall be supported for a minimum of 12 seconds.
6. Combined 3.3V and 5V power shall not exceed 100W.
18 A
18 A
3.5 A
8.2.3 Turn On No Load Operation
At power on the system shall present a no load condition to the power supply. In this no load state the voltage regulation limits for the 3.3V and 5V are relaxed to +/-10% and the +12V rails relaxed to +10/-8%.
When operating loads are applied the voltages must regulated to there normal limits.
Voltage
+3.3 V
+5 V
+12 V1
+12 V2
+12 V3
+12 V4
-12 V
+5 VSB
Table 36: No load operating range
Minimum Maximum
Continuous
0 A
0 A
0 A
0 A
0 A
0 A
0 A
0.1 A
Continuous
7 A
5 A
5 A
5 A
6 A
5 A
0.5 A
3.0 A
Peak
7 A
7 A
3.5 A
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Power and Environmental Specifications Intel
®
Server Board S5000PAL / S5000XAL TPS
8.2.4 Grounding
The grounds of the pins of the power supply output connector provide the power return path. The output connector ground pins shall be connected to safety ground (power supply enclosure). This grounding should be well designed to ensure passing the maximum allowed Common Mode Noise levels.
The power supply shall be provided with a reliable protective earth ground. All secondary circuits shall be connected to protective earth ground. Resistance of the ground returns to chassis shall not exceed 1.0 m Ω . This path may be used to carry DC current.
The 5VSB output shall be present when an AC input greater than the power supply turn on voltage is applied.
8.2.6 Remote Sense
The power supply has remote sense return (ReturnS) to regulate out ground drops for all output voltages:
+3.3V, +5V, +12V1, +12V2, +12V3, -12V, and 5VSB. The power supply uses remote sense (3.3VS) to regulate out drops in the system for the +3.3V output. The +5V, +12V1, +12V2, +12V3, –12V and 5VSB outputs only use remote sense referenced to the ReturnS signal. The remote sense input impedance to the power supply must be greater than 200 Ω on 3.3VS and 5VS; this is the value of the resistor connecting the remote sense to the output voltage internal to the power supply. Remote sense must be able to regulate out a minimum of a 200 mV drop on the +3.3V output. The remote sense return
(ReturnS) must be able to regulate out a minimum of a 200 mV drop in the power ground return. The current in any remote sense line shall be less than 5 mA to prevent voltage sensing errors. The power supply must operate within specification over the full range of voltage drops from the power supply’s output connector to the remote sense points.
The power supply output voltages must stay within the following voltage limits when operating at steady state and dynamic loading conditions. These limits include the peak-peak ripple/noise.
PARAMETER
+ 3.3V
+ 5V
+ 12V1,2,3,4
- 12V
+ 5VSB
Table 37. Voltage Regulation Limits
TOLERANCE
- 5% / +5%
- 5% / +5%
- 5% / +5%
- 5% / +9%
- 5% / +5%
MIN
+3.14
+4.75
+11.40
-10.80
+4.75
NOM
+3.30
+5.00
+12.00
-12.00
+5.00
MAX
+3.46
+5.25
+12.60
-13.20
+5.25
UNITS
V rms
V rms
V rms
V rms
V rms
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Server Board S5000PAL / S5000XAL TPS Power and Environmental Specifications
The output voltages shall remain within limits for the step loading and capacitive loading specified in the table below. The load transient repetition rate shall be tested between 50 Hz and 5 kHz at duty cycles ranging from 10%-90%. The load transient repetition rate is only a test specification. The Δ step load may occur anywhere within the MIN load to the MAX load conditions.
Table 38. Transient Load Requirements
Output
Δ
Step Load Size
(See note 2)
Load Slew Rate Test capacitive Load
+3.3V 5.0A 0.25 A/ μ sec 250
+5V 6.0A 0.25 A/ μ sec 400
12V1+12V2+12V3+12
V4
28.0A 0.25 A/ μ sec 2200
+5VSB 0.5A 0.25 A/ μ sec 20
Notes:
1) Step loads on each 12V output may happen simultaneously.
2) The +12V should be tested with 2200
μ
F evenly split between the four +12V rails.
The power supply shall be stable and meet all requirements with the following capacitive loading ranges.
Table 39. Capacitive Loading Conditions
Output MIN MAX Units
+3.3V 250 6,800 F
+12V1,2,3,4 500 11,000 μ F
+5VSB 20 350 F
The power supply shall be unconditionally stable under all line/load/transient load conditions including capacitive load ranges. A minimum of: 45 degrees phase margin and -10dB-gain margin is required.
Closed-loop stability must be ensured at the maximum and minimum loads as applicable.
8.2.11 Common Mode Noise
The common mode noise on any output shall not exceed 350 mV pk-pk over the frequency band of 10Hz to 30MHz.
1. The measurement shall be made across a 100 Ω resistor between each of the DC outputs, including ground, at the DC power connector and chassis ground (power subsystem enclosure).
2. The test set-up shall use an FET probe such as Tektronix* model P6046 or equivalent.
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Power and Environmental Specifications
8.2.12 Ripple / Noise
Intel
®
Server Board S5000PAL / S5000XAL TPS
The maximum allowed ripple/noise output of the power supply is defined in the following table. This is measured over a bandwidth of 0Hz to 20MHz at the power supply output connectors. A 10 μ F tantalum capacitor in parallel with a 0.1 μ F ceramic capacitor are placed at the point of measurement.
Table 40. Ripple and Noise
+3.3V +5V +12V1/2/3/4 -12V +5VSB
50mVp-p 50mVp-p 120mVp-p 120mVp-p 50mVp-p
The power supply shall contain a control circuit which provides a monotonic soft start for its outputs without overstress of the AC line or any power supply components at any specified AC line or load conditions. There is no requirement for rise time on the 5 V standby, but the turn on/off shall be monotonic.
8.2.14 Timing Requirements
These are the timing requirements for the power supply operation. The output voltages must rise from
10% to within regulation limits (T vout_rise
(T
) within 5 to 70 ms, except for 5VSB; it is allowed to rise from 1.0 to
25 ms.
All outputs must rise monotonically . Each output voltage shall reach regulation within 50 ms vout_on
) of each other during turn on of the power supply. Each output voltage shall fall out of regulation within 400 msec (T vout_off
) of each other during turn off. The following diagrams show the timing requirements for the power supply being turned on and off via the AC input with PSON held low, and the
PSON signal with the AC input applied.
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Table 41. Output Voltage Timing
Item
T vout_rise
T vout_on
Description
Output voltage rise time from each main output.
All main outputs must be within regulation of each other within this time.
5.0 *
MIN
T vout_off
All main outputs must leave regulation within this time.
1
The 5VSB output voltage rise time shall be from 1.0ms to 25.0ms
V out
MAX UNITS
70
1
msec
V1
10% V out
V2
V3
V4
Tvout_off
Tvout_rise
Tvout_on
Figure 26. Output Voltage Timing
TP02313
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Power and Environmental Specifications Intel
®
Server Board S5000PAL / S5000XAL TPS
Item
T sb_on_delay
T ac_on_delay
T vout_holdup
T pwok_holdup
T pson_on_delay
T pson_pwok
T pwok_on
T pwok_off
T pwok_low
T sb_vout
T
5VSB_holdup
AC Input
Table 42. Turn On/Off Timing
Description
Delay from AC being applied to 5VSB being within regulation.
Delay from AC being applied to all output voltages being within regulation.
Time all output voltages stay within regulation after loss of AC.
Measured at 60% of maximum load.
Delay from loss of AC to de-assertion of PWOK. Measured at
60% of maximum load.
Delay from PSON
# limits.
active to output voltages within regulation
Delay from PSON
#
de-active to PWOK being de-asserted.
Delay from output voltages within regulation limits to PWOK asserted at turn on.
Delay from PWOK de-asserted to output voltages (3.3V, 5V,
12V, -12V) dropping out of regulation limits.
Duration of PWOK being in the de-asserted state during an off/on cycle using AC or the PSON signal.
Delay from 5VSB being in regulation to O/Ps being in regulation at AC turn on.
Time the 5VSB output voltage stays within regulation after loss of AC.
MIN MAX
1500
21
20
50 msec
100 500 msec
1 msec
100 msec
70
UNITS msec msec msec msec
T vout_holdup
V out
Tsb_on_delay
PWOK
T
AC_on_delay
Tpwok_on
Tpwok_holdup
Tpwok_off
Tpwok_low
Tsb_on_delay Tpwok_on Tpwok_off
Tpson_pwok
T5VSB_holdup
5 VSB
Tsb_vout
Tpson_on_delay
PSON
AC turn on/off cycle PSON turn on/off cycle
Figure 27. Turn On/Off Timing (Power Supply Signals)
TP02314
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®
Server Board S5000PAL / S5000XAL TPS Power and Environmental Specifications
8.2.15 Residual Voltage Immunity in Standby Mode
The power supply shall be immune to any residual voltage placed on its outputs (typically a leakage voltage through the system from standby output) up to 500 mV. There shall be no additional heat generated, nor stress of any internal components with this voltage applied to any individual output, and all outputs simultaneously. It also should not trip the power supply protection circuits during turn on.
Residual voltage at the power supply outputs for a no load condition shall not exceed 100 mV when AC voltage is applied and the PSON# signal is de-asserted.
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Regulatory and Certification Information Intel
®
Server Board S5000PAL / S5000XAL TPS
9. Regulatory and Certification Information
9.1 Product Regulatory Compliance
Intended Application – This product was evaluated as Information Technology Equipment (ITE), which may be installed in offices, schools, computer rooms, and similar commercial type locations. The suitability of this product for other product categories and environments (such as: medical, industrial, telecommunications, NEBS, residential, alarm systems, test equipment, etc.), other than an ITE application, may require further evaluation. This is an FCC Class A device. Integration of it into a Class B chassis does not result in a Class B device.
The following table references Server Board Compliance and markings that may appear on the product. Markings below are typical markings however, may vary or be different based on how certification is obtained.
Note: Certifications Emissions requirements are to Class A
9.1.1 Product Safety & Electromagnetic (EMC) Compliance
Compliance Regional Compliance
Description Reference
Australia / New Zealand AS/NZS 3548 (Emissions)
Compliance Reference Marking
Example
N232
Canada / USA CSA 60950 – UL 60950
(Safety)
CANADA ICES-003 CLASS A
CANADA NMB-003 CLASSE A
CENELEC Europe
International
Korea
Industry Canada ICES-003
(Emissions)
Low Voltage Directive
93/68/EEC
;
EMC Directive 89/336/EEC
EN55022 (Emissions)
EN55024 (Immunity)
CE Declaration of Conformity
CB Certification – IEC60950
CISPR 22 / CISPR 24
RRL Certification
MIC Notice No. 1997-41 (EMC)
& 1997-42 (EMI)
None Required
인증번호 : CPU-Model Name (A)
Taiwan BSMI CNS13438
D33025
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Intel
®
Server Board S5000PAL / S5000XAL TPS Regulatory and Certification Information
9.2.1 FCC Verification Statement (USA)
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
(1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
Intel Corporation
5200 N.E. Elam Young Parkway
Hillsboro, OR 97124-6497
Phone: 1-800-628-8686
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
• Reorient or relocate the receiving antenna.
• Increase the separation between the equipment and the receiver.
• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
• Consult the dealer or an experienced radio/TV technician for help.
Any changes or modifications not expressly approved by the grantee of this device could void the user’s authority to operate the equipment. The customer is responsible for ensuring compliance of the modified product.
All cables used to connect to peripherals must be shielded and grounded. Operation with cables, connected to peripherals that are not shielded and grounded may result in interference to radio and TV reception.
Cet appareil numérique respecte les limites bruits radioélectriques applicables aux appareils numériques de Classe B prescrites dans la norme sur le matériel brouilleur:
“Appareils Numériques”, NMB-003 édictée par le Ministre Canadian des Communications.
English translation of the notice above:
This digital apparatus does not exceed the Class B limits for radio noise emissions from digital apparatus set out in the interference-causing equipment standard entitled “Digital Apparatus,” ICES-003 of the
Canadian Department of Communications.
9.2.3 Europe (CE Declaration of Conformity)
This product has been tested in accordance too, and complies with the Low Voltage Directive
(73/23/EEC) and EMC Directive (89/336/EEC). The product has been marked with the CE Mark to illustrate its compliance.
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Regulatory and Certification Information Intel
®
Server Board S5000PAL / S5000XAL TPS
(Taiwan)
The BSMI Certification Marking and EMC warning is located on the outside rear area of the product.
Following is the RRL certification information for Korea.
English translation of the notice above:
1. Type of Equipment (Model Name): On License and Product
2. Certification No.: On RRL certificate. Obtain certificate from local Intel representative
3. Name of Certification Recipient: Intel Corporation
4. Date of Manufacturer: Refer to date code on product
5. Manufacturer/Nation: Intel Corporation/Refer to country of origin marked on product
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®
Server Board S5000PAL / S5000XAL TPS Regulatory and Certification Information
Intel has a system in place to restrict the use of banned substances in accordance with world wide product ecology regulatory requirements. The following is Intel’s product ecology compliance criteria.
Compliance Regional
Description
California
Compliance Reference
California Code of Regulations, Title 22, Division 4.5;
Chapter 33: Best Management Practices for
Perchlorate Materials.
China China RoHS
Administrative Measures on the Control of Pollution
Caused by Electronic Information Products” (EIP) #39.
Referred to as China RoHS.
Mark requires to be applied to retail products only.
Mark used is the Environmental Friendly Use Period
(EFUP). Number represents years.
Compliance Reference
Marking Example
Special handling may apply. See
www.dtsc.ca.gov/hazar douswaste/perchlorate
This notice is required by
California Code of
Regulations, Title 22,
Division 4.5; Chapter 33:
Best Management
Practices for Perchlorate
Materials. This product / part include a battery which contains
Perchlorate material.
Intel Internal
Specification
Europe
China Recycling (GB18455-2001)
Mark requires to be applied to be retail product only.
Marking applied to bulk packaging and single packages. Not applied to internal packaging such as plastics, foams, etc.
All materials, parts and subassemblies must not contain restricted materials as defined in Intel’s
Environmental Product Content Specification of
Suppliers and Outsourced Manufacturers – http://supplier.intel.com/ehs/environmental.htm
European Directive 2002/95/EC -
Restriction of Hazardous Substances (RoHS)
Threshold limits and banned substances are
noted below.
Quantity limit of 0.1% by mass (1000 PPM) for:
Lead, Mercury, Hexavalent Chromium,
Polybrominated Biphenyls Diphenyl Ethers
(PBB/PBDE)
Quantity limit of 0.01% by mass (100 PPM) for:
Cadmium
None Required
None Required
Germany German Green Dot
Applied to Retail Packaging Only for Boxed Boards
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Regulatory and Certification Information Intel
®
Server Board S5000PAL / S5000XAL TPS
Compliance Regional
Description
Intel Internal
Specification
Compliance Reference
All materials, parts and subassemblies must not contain restricted materials as defined in Intel’s
Environmental Product Content Specification of
Suppliers and Outsourced Manufacturers – http://supplier.intel.com/ehs/environmental.htm
Compliance Reference
Marking Example
None Required
International ISO11469 - Plastic parts weighing >25gm are intended to be marked with per ISO11469.
Recycling Markings – Fiberboard (FB) and Cardboard
(CB) are marked with international recycling marks.
Applied to outer bulk packaging and single package.
>PC/ABS<
Japan
Japan Recycling
Applied to Retail Packaging Only for Boxed Boards
Compliance
Description
Compliance Reference
Country of Origin Logistic Requirements
Applied to products to indicate where product was
made.
Compliance Reference
Marking Example
Made in XXXX
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®
Server Board S5000PAL / S5000XAL TPS Appendix A: Integration and Usage Tips
Appendix A: Integration and Usage Tips
When adding or removing components or peripherals from the server board, AC power must be removed. With AC power plugged into the server board, 5-volt standby is still present even though the server board is powered off.
When two processors are installed, both must be of identical revision, core voltage, and bus/core speed. Mixed processor steppings is supported. However, the stepping of one processor can not greater then one stepping back of the other.
Processors must be installed in order. CPU 1 is located near the edge of the server board and must be populated to operate the board.
On the back edge of the server board are four diagnostic LEDs which display a sequence of red, green, or amber POST codes during the boot process. If the server board hangs during POST, the LEDs will display the last POST event run before the hang.
Only Fully Buffered DIMMs (FBD) are supported on this server board. For a list of supported memory for this server board, see the Intel® Server Board S5000PAL / S5000XAL Tested
Memory List .
For a list of Intel supported operating systems, add-in cards, and peripherals for this server board, see the Intel® Server Board S5000PAL / S5000XAL Tested Hardware and OS List.
Only Dual-Core Intel
®
Xeon
®
processors 5000 sequence, with system bus speeds of
667/1066/1333 MHz are supported on this server board. Previous generation Intel processors are not supported.
®
Xeon
®
For best performance, the number of DIMMs installed should be balanced across both memory branches. For example: a four DIMM configuration will perform better than a two DIMM configuration and should be installed in DIMM Slots A1, B1, C1, and D1. An eight DIMM configuration will perform better then a six DIMM configuration.
There are no population rules for installing a single low profile add-in card in the 2U LP riser card; a single add in card can be installed in either PCI Express* slot. While each slot can accommodate a x8 card, each slot will only support x4 bus speeds.
For the 2U PCI-X* (passive) riser card, add-in cards should be installed starting with the top slot first, followed by the middle, and then the bottom. Any add-in card populated in the bottom PCI slot will cause the bus to operate at 66MHz.
Each PCI slot on the 2U PCI-X* (active) riser card operates on an independent PCI bus.
Therefore, using an add-in card that operates below 133MHz will not affect the bus speed of the other PCI slots.
The IDE connector on this server board is NOT a standard 40-pin IDE connector. Instead, this connector has an additional 4 power pins over and above the standard 40 I/O pins. The design intent of this connector is to provide support for a slim-line optical drive only.
Removing AC Power before performing the CMOS clear operation will cause the system to automatically power up and immediately power down after the procedure is followed and AC power is re-applied. Should this occur, remove the AC power cord again, wait 30 seconds, and re-install the AC power cord. Power up system and proceed to the <F2> BIOS setup utility to reset desired settings.
Normal BMC functionality is disabled with the force BMC update jumper set to the “enabled” position (pins 2-3). The server should never be run with the BMC force update jumper set in this position and should only be used when the standard firmware update process fails. This jumper should remain in the default (disabled) position (pins 1-2) when the server is running normally.
When performing a BIOS update procedure, the BIOS select jumper must be set to its default position (pins 2-3).
When AC power is applied to the server, a 25-30 second delay is necessary to initialize the BMC.
During this initialization period, the Power Button functionality is disabled.
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Appendix B: Sensor Tables Intel
®
Server Board S5000PAL / S5000XAL TPS
Appendix B: BMC Sensor Tables
This appendix lists the sensor identification numbers and information regarding the sensor type, name, supported thresholds, assertion and de-assertion information, and a brief description of the sensor purpose. See the Intelligent Platform Management Interface Specification, Version 1.5
, for sensor and event/reading-type table information.
Sensor Type
The Sensor Type references the values enumerated in the Sensor Type Codes table in the IPMI specification. It provides the context in which to interpret the sensor, e.g., the physical entity or characteristic that is represented by this sensor.
Event / Reading Type
The Event/Reading Type references values from the Event/Reading Type Code Ranges and
Generic Event/Reading Type Codes tables in the IPMI specification . Note that digital sensors are a specific type of discrete sensors, which have only two states.
Event Offset/Triggers
Event Thresholds are ‘supported event generating thresholds’ for threshold types of sensors. o
[u,l][nr,c,nc]: upper non-recoverable, upper critical, upper non-critical, lower non-recoverable, lower critical, lower non-critical o
uc, lc: upper critical, lower critical
Event Triggers are ‘supported event generating offsets’ for discrete type sensors. The offsets can be found in the Generic Event/Reading Type Codes or Sensor Type Codes tables in the IPMI specification, depending on whether the sensor event/reading type is generic or a sensor specific response.
Assertion / De-assertion Enables
Assertion and de-assertion indicators reveal the type of events the sensor can generate: o
As: o
De:
Readable Value / Offsets o
Readable Value indicates the type of value returned for threshold and other non-discrete type sensors. o
Readable Offsets indicate the offsets for discrete sensors that are readable via the Get
Sensor Reading command. Unless otherwise indicated, all event triggers are readable, i.e.,
Readable Offsets consists of the reading type offsets that do not generate events.
Event Data
This is the data that is included in an event message generated by the associated sensor. For threshold-based sensors, the following abbreviations are used: o
R: value o
T: Threshold value
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®
Server Board S5000PAL / S5000XAL TPS
Rearm Sensors
Appendix B: Sensor Tables
-
The rearm is a request for the event status for a sensor to be rechecked and updated upon a transition between good and bad states. Rearming the sensors can be done manually or automatically. This column indicates the type supported by the sensor. The following abbreviations are used in the comment column to describe a sensor:
A: Auto-rearm
M: Manual rearm
Default Hysteresis
-
Hysteresis setting applies to all thresholds of the sensor. This column provides the count of hysteresis for the sensor, which can be 1 or 2 (positive or negative Hysteresis).
Criticality
-
Criticality is a classification of the severity and nature of the condition. It also controls the behavior of the Control Panel Status LED.
Standby
-
Some sensors operate on standby power. These sensors may be accessed and / or generate events when the main (system) power is off, but AC power is present.
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Appendix B: Sensor Tables Intel
®
Server Board S5000PAL / S5000XAL TPS
Table 43. BMC Sensors
Sensor
Name
Power Unit
Status
Power Unit
Redundancy
Sensor
Number
System
Applicability
02h Chassisspecific
Sensor Type Event /
Reading
Type
09h
Power Unit
09h
Specific
6Fh
Generic
0Bh
Event Offset
Triggers
Criticality
Power down
Power cycle
A/C lost
Soft power control failure
Power unit failure
Predictive failure
Redundancy regained
Non-red: suff res from redund
Redundancy lost
Redundancy degraded
Non-red: suff from insuff
Non-red: insufficient
Redun degrade from full
Redun degrade from nonredundant
OK
Critical
Non-Critical
OK
Degraded
OK
Critical
OK
Assert /
De-assert
Readable
Value /
Offsets
Event Data Rearm Standby
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®
Server Board S5000PAL / S5000XAL TPS Appendix B: Sensor Tables
Sensor
Name
Platform
Security
Violation
Physical
Security
FP Diag
Interrupt
(NMI)
System
Event Log
Session
Audit
Sensor
Number
Watchdog 03h
System
Applicability
All
Intrusion is chassisspecific
Sensor Type Event /
Reading
23h
Type
Sensor
Specific
6Fh
04h All Platform Sensor
Security
Violation
Attempt
06h
Security
05h
Specific
6Fh
Sensor
Specific
6Fh
07h All Critical
Interrupt
13h
Sensor
Specific
6Fh
09h All Event
Logging
Disabled
10h
Sensor
Specific
6Fh
0Ah All Session Sensor
2Ah
Specific
6Fh
Event Offset
Triggers
Criticality Assert /
De-assert
Readable
Value /
Event Data Rearm
Offsets
OK As –
Standby
Timer expired, status only
Hard reset
Power down
Power cycle
Timer interrupt
Secure mode violation attempt
Out-of-band access password violation
Chassis intrusion
LAN leash lost
1
OK As
OK As and De
–
– Trig Offset A
Front panel NMI
/ diagnostic interrupt
Bus uncorrectable error
Log area reset / cleared
OK As –
OK As –
X
00h – Session activation
01h – Session deactivation
OK As defined by IPMI
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Appendix B: Sensor Tables Intel
®
Server Board S5000PAL / S5000XAL TPS
Sensor
Name
System
Event
('System
Event')
BB +1.2V
Vtt
BB+1.9V
NIC Core
Sensor
Number
System
Applicability
Sensor Type Event /
Reading
12h
Type
Sensor
Specific
6Fh
10h All Voltage Threshold
02h 01h
11h All Voltage Threshold
02h 01h
BB +1.5V
AUX
12h All Voltage Threshold
02h 01h
BB +1.5V 13h All
BB +1.8V 14h All
Voltage
02h
Voltage
02h
Threshold
01h
Threshold
01h
BB +3.3V 15h All Voltage
02h
Threshold
01h
BB +3.3V
STB
BB +1.5V
ESB
BB +5V
BB +1.2V
NIC
16h All Voltage Threshold
02h 01h
17h All Voltage Threshold
18h All
02h
Voltage
01h
Threshold
02h 01h
19h All Voltage Threshold
02h 01h
BB +12V
AUX
BB 0.9V
1Ah All Voltage Threshold
1Bh All
02h
Voltage
01h
Threshold
BB Vbat 1Eh All
02h
Voltage
02h
01h
Digital
Discrete
05h
Event Offset
Triggers
00 – System reconfigured
04 – PEF action
[u,l] [c,nc]
[u,l] [c,nc]
[u,l] [c,nc]
[u,l] [c,nc]
[u,l] [c,nc]
[u,l] [c,nc]
[u,l] [c,nc]
[u,l] [c,nc]
[u,l] [c,nc]
[u,l] [c,nc]
[u,l] [c,nc]
[u,l] [c,nc]
01h – Limit exceeded
Criticality Assert /
De-assert
Readable
Value /
Event Data Rearm
Offsets
OK As Offset
Standby
Threshold defined
Threshold defined
Threshold defined
Threshold defined
Threshold defined
Threshold defined
Threshold defined
Threshold defined
Threshold defined
Threshold defined
Threshold defined
Threshold defined
Critical
As and De
As and De
As and De
As and De
As and De
As and De
As and De
As and De
As and De
As and De
As and De
As and De
As and De
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
–
R, T
R, T
R, T
R, T
R, T
R, T
R, T
R, T
R, T
R, T
R, T
R, T
R, T
A
A
A
A
A
A
A
A
A
A
A
A
A
–
X
–
–
–
–
X
X
–
–
–
–
X
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®
Server Board S5000PAL / S5000XAL TPS Appendix B: Sensor Tables
Sensor
Name
Front
Panel
Temp
Sensor
Number
BB Temp 30h
System
Applica-
All bility
Sensor Type Event /
Reading
Temperature
Type
Threshold
01h
32h All Temperature
01h
01h
Threshold
01h
Fan 1A
Fan 2A
50h
51h
Chassisspecific
Chassisspecific
Fan
04h
Fan
04h
Threshold
01h
Threshold
01h
Fan 3A 52h Chassisspecific
Fan 4A
Fan 5A
Tach Fan
(not used on this server)
Fan 1B
53h
54h
55h Chassis-
56h
Chassisspecific
Chassisspecific specific
Chassisspecific
Fan
04h
Fan
04h
Fan
04h
Fan
04h
Threshold
01h
Threshold
01h
Threshold
01h
Threshold
01h
Fan 2B
Fan 3B
Fan 4B
57h
58h
59h
Chassisspecific
Chassisspecific
Chassisspecific
Fan
04h
Fan
04h
Fan
04h
Fan
04h
Threshold
01h
Threshold
01h
Threshold
01h
Threshold
01h
Fan 5B
Fan 1
Present
5Ah Chassisspecific
60h Chassisspecific
Fan
04h
Fan
04h
Threshold
01h
Generic
08h
Event Offset
Triggers
[u,l] [c,nc]
[u,l] [c,nc]
[l] [c,nc]
[l] [c,nc]
[l] [c,nc]
[l] [c,nc]
[l] [c,nc]
[l] [c,nc]
[l] [c,nc]
[l] [c,nc]
[l] [c,nc]
[l] [c,nc]
Criticality
Threshold defined
Threshold defined
Threshold defined
Threshold defined
Threshold defined
Threshold defined
Threshold defined
Threshold defined
Threshold defined
Threshold defined
Threshold defined
Threshold defined
[l] [c,nc] Threshold defined
Device present OK
Assert /
De-assert
Readable
Value /
Offsets
As and De Analog
Event Data
R, T
Rearm
A
Standby
X
As and De Analog
As and De Analog
As and De Analog
As and De Analog
As and De Analog
As and De Analog
As and De Analog
As and De Analog
As and De Analog
As and De Analog
As and De Analog
As and De Analog
As and De –
R, T
R, T
R, T
R, T
R, T
R, T
R, T
R, T
R, T
R, T
R, T
R, T
T
A
M
M
M
M
M
M
M
M
M
M
M
A
X
–
–
–
–
–
–
–
–
–
–
–
–
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Appendix B: Sensor Tables Intel
®
Server Board S5000PAL / S5000XAL TPS
Sensor
Name
Fan 2
Present
Fan 3
Present
Fan 4
Present
Fan 5
Present
Fan 6
Present
Fan 7
Present
Fan 8
Present
Fan 9
Present
Fan 10
Present
Fan
Redundancy
Sensor
Number
System
Applicability
61h Chassisspecific
62h Chassisspecific
63h Chassisspecific
64h Chassisspecific
65h Chassisspecific
66h Chassisspecific
67h Chassisspecific
68h Chassisspecific
69h Chassisspecific
6Fh Chassisspecific
04h
Fan
04h
Fan
04h
Fan
04h
Fan
Sensor Type Event /
Reading
Fan
Type
Generic
04h
Fan
08h
Generic
04h
Fan
04h
Fan
08h
Generic
08h
Generic
04h
Fan
04h
08h
Generic
08h
Generic
08h
Generic
08h
Generic
08h
Generic
08h
Fan
04h
Generic
0Bh
Event Offset
Triggers
Redundancy regained
Redundancy lost
Redundancy degraded
Non-red: suff res from redund
Non-red: suff from insuff
Non-red: insufficient
Criticality
Device present OK
Device present OK
Device present OK
Device present OK
Device present OK
Device present OK
Device present OK
Device present OK
Device present OK
OK
Degraded
OK
Critical
Assert /
De-assert
As and De
As and De
As and De
As and De
As and De
As and De
As and De
As and De
As and De
Readable
Value /
Offsets
–
Event Data
T
Rearm
A
Standby
–
–
–
–
–
–
–
–
–
T
T
T
T
T
T
T
T
A
A
A
A
A
A
A
A
–
–
–
–
–
–
–
–
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®
Server Board S5000PAL / S5000XAL TPS Appendix B: Sensor Tables
Power
Nozzle
Power
Supply 1
Power
Nozzle
Power
Supply 2
Power
Gauge
V1 rail
(+12v)
Power
Supply 1
Sensor
Name
Power
Supply
Status 1
Power
Supply
Status 2
Sensor
Number
System
Applicability
70h Chassisspecific
71h Chassisspecific
78h Chassisspecific
Sensor Type Event /
Reading
Type
Power Supply
08h
Power Supply
08h
Current
03h
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Threshold
01h
Event Offset
Triggers
Criticality Assert /
De-assert
Readable
Value /
Offsets
Redun degrade from full
Redun degrade from nonredundant
OK
Presence OK As and De
Failure Critical
Predictive fail Non-Critical
A/C lost Critical
Configuration error
Non-Critical
–
Presence OK As and De
Failure Critical
Predictive fail Non-Critical
A/C lost Critical
Non-Critical Configuration error
[u] [c,nc] Threshold defined
As and De
–
Analog
Event Data
Trig Offset A
Trig Offset A
R, T
Rearm
A
Standby
X
X
–
79h Chassisspecific
7Ah Chassisspecific
Current
03h
Current
03h
Threshold
01h
Threshold
01h
[u] [c,nc]
[u] [c,nc]
Threshold defined
Threshold defined
As and De
As and De
Analog
Analog
R, T
R, T
A
A
–
–
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Appendix B: Sensor Tables Intel
®
Server Board S5000PAL / S5000XAL TPS
Sensor
Name
Power
Gauge
V1 rail
(+12v)
Power
Supply 2
Power
Gauge
(aggregate power)
Power
Supply 1
Power
Gauge
(aggregate power)
Power
Supply 2
System
ACPI
Power
State
Sensor
Number
System
Applicability
7Bh Chassisspecific
7Ch Chassisspecific
7Dh Chassisspecific
Button 84h All
SMI
Timeout
Sensor Type Event /
Current
03h
Other Units
0Bh
Other Units
0Bh
Power State
22h
Button
14h
F3h
Reading
Type
Threshold
01h
Threshold
01h
Threshold
01h
Specific
6Fh
Sensor
Specific
6Fh
Digital
Discrete
03h
Event Offset
S1
S3
Triggers
[u] [c,nc]
[u] [c,nc]
[u] [c,nc]
S0 / G0
S4
S5 / G2
G3 mechanical off
Power button
Reset button
01h – State asserted
Criticality
Threshold defined
Threshold defined
Threshold defined
Critical
Assert /
De-assert
As and De
As and De
As and De
Readable
Value /
Offsets
As and De Analog
Analog
Analog
–
Event Data
R, T
R, T
R, T
Trig Offset
Rearm
A
A
A
OK As –
OK As Offset
A
Standby
–
–
–
–
92 Revision 1.9
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Intel
®
Server Board S5000PAL / S5000XAL TPS Appendix B: Sensor Tables
Sensor
Name
Sensor
Failure
NMI Signal
State
SMI Signal
State
Sensor
Number
System
Applica-
Sensor Type Event /
Reading bility
86h All Sensor
Failure
F6h
Type
OEM
Sensor
Specific
73h
87h All OEM
C0h
88h All OEM
C0h
Digital
Discrete
03h
Digital
Discrete
03h
Event Offset
Triggers
I 2 C device not found
I
2
C device error detected
I 2 C bus timeout
01h – State asserted
Criticality Assert /
De-assert
Readable
Value /
Event Data Rearm
Offsets
OK As –
Standby
01h – State asserted
Proc 1
Status
Proc 2
Status
Proc 1
Temp
Proc 2
Temp
PCIe Link0 A0h Critical
Interrupt
13F
07h
07h
98h All Temperature
01h
9Ah All Temperature
01h
Sensor
Specific
6Fh
Specific
6Fh
Specific
6Fh
Threshold
01h
Threshold
01h
PCIe
Link0
–
Thermal trip
Config error
Non-rec
Critical
Presence OK
Disabled Degraded
–
Thermal trip Non-rec
Config error Critical
Presence OK
Disabled Degraded
[u,l] [c,nc] Threshold defined
As and De Analog
As and De Analog [u,l] [c,nc] Threshold defined
Bus correctable error
Bus uncorrectable error
OK
Degraded
Trig Offset M
Trig Offset
R, T
R, T
BIOS EPS
M
A
A
X
X
–
–
Revision 1.9
Intel order number: D31979-010
93
Appendix B: Sensor Tables Intel
®
Server Board S5000PAL / S5000XAL TPS
Sensor
Name
Sensor
Number
PCIe Link1 A1h
System
Applicability
Critical
Interrupt
13F
PCIe Link2 A2h
PCIe Link3 A3h
PCIe Link4 A4h
PCIe Link5 A5h
PCIe Link6 A6h
PCIe Link7 A7h
Critical
Interrupt
13F
Critical
Interrupt
13F
Critical
Interrupt
13F
Critical
Interrupt
13F
Critical
Interrupt
13F
Critical
Interrupt
Sensor Type Event /
Reading
Sensor
Specific
Type
PCIe
Link1
6Fh
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Sensor
Specific
PCIe
Link2
PCIe
Link3
PCIe
Link4
PCIe
Link5
PCIe
Link6
PCIe
Link7
Event Offset
Triggers
Criticality Assert /
De-assert
Readable
Value /
Offsets
Event Data Rearm
Bus correctable error
Bus uncorrectable error
Bus correctable error
Bus uncorrectable error
Bus correctable error
Bus uncorrectable error
Bus correctable error
Bus uncorrectable error
Bus correctable error
Bus uncorrectable error
Bus correctable error
Bus uncorrectable error
Bus correctable error
OK
Degraded
OK
Degraded
OK
Degraded
OK
Degraded
OK
Degraded
OK
Degraded
BIOS EPS
BIOS EPS
BIOS EPS
BIOS EPS
BIOS EPS
BIOS EPS
OK As – the
BIOS EPS
Standby
94 Revision 1.9
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Intel
®
Server Board S5000PAL / S5000XAL TPS Appendix B: Sensor Tables
Sensor
Name
PCIe
Link10
PCIe
Link11
PCIe
Link12
PCIe
Link13
Sensor
Number
PCIe Link8 A8h
PCIe Link9 A9h
System
Applica-
Sensor Type bility
13F 6Fh
Event /
Reading
Type
Critical
Interrupt
13F
Critical
Interrupt
13F
Interrupt
13F
Interrupt
13F
Interrupt
13F
Interrupt
13F
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Specific
6Fh
Specific
6Fh
Specific
6Fh
Specific
6Fh
PCIe
Link8
PCIe
Link9
PCIe
Link10
PCIe
Link11
PCIe
Link12
PCIe
Link13
Event Offset
Triggers
Criticality
Bus uncorrectable error
Bus correctable error
Bus uncorrectable error
Bus correctable error
Bus uncorrectable error
Bus correctable error
Bus uncorrectable error
Bus correctable error
Bus uncorrectable error
Bus correctable error
Bus uncorrectable error
Bus correctable error
Bus uncorrectable error
Degraded
OK
Degraded
OK
Degraded
OK
Degraded
OK
Degraded
OK
Degraded
OK
Degraded
Assert /
De-assert
Readable
Value /
Offsets
Event Data Rearm Standby
BIOS EPS
BIOS EPS
BIOS EPS
BIOS EPS
BIOS EPS
BIOS EPS
Revision 1.9
Intel order number: D31979-010
95
Appendix B: Sensor Tables Intel
®
Server Board S5000PAL / S5000XAL TPS
Sensor
Name
Proc 1
Thermal
Control
Proc 2
Thermal
Control
Proc 1
VRD Over
Temp
Proc 2
VRD Over
Temp
Sensor
Number
System
Applica-
Sensor Type bility
C0h All Temperature
Event /
Reading
Type
Threshold
01h
C1h All Temperature
01h
C8h All Temperature
01h
C9h All Temperature
01h
01h
Threshold
01h
Proc 1 Vcc D0h
Proc 2 Vcc D1h
All
All
Voltage
02h
Voltage
02h
Proc 1 Vcc
Out-of-
Range
Proc 2
Vcc Outof-Range
CPU
Population
Error
DIMM A1 E0h
D2h All Voltage
02h
Digital
Discrete
05h
D3h All Voltage
02h
Digital
Discrete
05h
All
07h 03h
Slot
Connector
21h
Sensor
Specific
6Fh
Digital
Discrete
05h
Digital
Discrete
05h
Threshold
01h
Threshold
01h
DIMM A2 E1h All Slot
Connector
Sensor
Specific
Event Offset
Triggers
[u] [c,nc]
[u] [c,nc]
01h – Limit exceeded
01h – Limit exceeded
[u,l] [c,nc]
[u,l] [c,nc]
01h – Limit exceeded
01h – Limit exceeded
01h –- State asserted
Fault status asserted
Criticality
Threshold defined
Threshold defined
Non-Critical
Non-Critical
Threshold defined
Threshold defined
Non-Critical As and De Discrete
Non-Critical
Critical
Degraded
Device installed OK
Assert /
De-assert
Offsets
As and De Analog
As and De
As and De
As and De
As and De
As and De
As and De
As and De
Disabled Degraded
Sparing OK
Fault status asserted
Degraded As
Readable
Value /
Analog
–
–
Analog
Analog
Discrete
–
Event Data
Trig Offset
Trig Offset
Trig Offset
R, T
R, T
R, T
R, T
R, T
Rearm
Trig Offset M
M
M
M
A
A
A
A
A
Standby
–
–
–
–
–
–
–
–
–
–
96 Revision 1.9
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Intel
®
Server Board S5000PAL / S5000XAL TPS Appendix B: Sensor Tables
Sensor
Name
DIMM B1
DIMM B2
DIMM C1
DIMM C2
DIMM D1
DIMM D2
Sensor
Number
E2h
E3h
E4h
E5h
E6h
E7h
System
Applicability
All
All
All
All
All
All
Sensor Type Event /
Reading
Slot
Connector
21h
Slot
Connector
21h
Slot
Connector
21h
Slot
Connector
21h
Slot
Connector
21h
Slot
Connector
Type
Event Offset
Triggers
Criticality Assert /
De-assert
Readable
Value /
Offsets
Event Data Rearm Standby
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Sensor
Specific
Disabled Degraded
Sparing OK
Fault status asserted
Degraded
Device installed OK
Disabled Degraded
Sparing OK
Fault status asserted
Degraded
Device installed OK
Disabled Degraded
Sparing OK
Fault status asserted
Degraded
Device installed OK
Disabled Degraded
Sparing OK
Fault status asserted
Degraded
Device installed OK
Disabled Degraded
Sparing OK
Fault status asserted
Degraded
Device installed OK
Disabled Degraded
Sparing OK
Fault status asserted
Degraded As –
Revision 1.9
Intel order number: D31979-010
97
Appendix B: Sensor Tables Intel
®
Server Board S5000PAL / S5000XAL TPS
Sensor
Name
Sensor
Number
System
Applicability
Sensor Type Event /
Reading
Type
Event Offset
Triggers
Criticality Assert /
De-assert
Readable
Value /
Offsets
Event Data Rearm Standby
Memory A
Error
Memory B
Error
Memory C
Error
Memory D
Error
ECh All Memory
EDh Systemspecific
EEh Systemspecific
EFh Systemspecific
0Ch
Memory
0Ch
Memory
0Ch
Memory
0Ch
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Sensor
Specific
6Fh
B0 DIMM
Sparing
Enabled
B0 DIMM
Sparing
Redundancy
F0h All Entity
Presence
25h
Sensor
Specific
6Fh
F1h All Memory Discrete
0Ch
0Bh
Disabled Degraded
Sparing OK
Correctable
ECC
OK As –
Uncorrectable
ECC
Correctable
ECC
OK As –
Uncorrectable
ECC
Correctable
ECC
Uncorrectable
ECC
Correctable
ECC
OK As
OK As
Uncorrectable
ECC
Entity present OK As
–
–
– Trig Offset A
Fully redundant OK
Non-red: suff res from redund
Non-red: suff res from insuff res
Degraded
Non-red: Insuff res
Critical
Entity present OK As – Trig Offset A B1 DIMM
Sparing
Enabled
F2h All Entity
Presence
25h
Sensor
Specific
6Fh
–
–
98 Revision 1.9
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Intel
®
Server Board S5000PAL / S5000XAL TPS Appendix B: Sensor Tables
Sensor
Name
B1 DIMM
Sparing
Redundancy
Sensor
Number
System
Applica-
Sensor Type Event /
Reading bility Type
F3h All Memory Discrete
0Ch
0Bh
Event Offset
Triggers
Criticality
Fully redundant OK
Non-red: suff res from redund
Non-red: suff res from insuff res
Degraded
Non-red: insuff res
Critical
Entity present OK B01 DIMM
Mirroring
Enabled
B01 DIMM
Mirroring
Redundancy
F4h All Entity
Presence
25h
Sensor
Specific
6Fh
F5h All Memory Discrete
0Ch
0Bh
Fully redundant OK
Non-red:suff res from redund
Non-red:suff res from insuff res
Non-red: insuff res
Degraded
Critical
Note 1: Not supported except for ESB-2 embedded NICs
Assert /
De-assert
As
Readable
Value /
Offsets
Event Data Rearm Standby
– Trig Offset A –
Revision 1.9
Intel order number: D31979-010
99
Appendix C: POST Code Diagnostic LEDs Intel
®
Server Board S5000PAL / S5000XAL TPS
Appendix C: POST Code Diagnostic LED Decoder
During the system boot process, BIOS executes a number of platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, BIOS will display the given POST code to the POST Code Diagnostic LEDs found on the back edge of the server board. To assist in troubleshooting a system hang during the POST process, the Diagnostic LEDs can be used to identify the last POST process to be executed.
Each POST code will be represented by a combination of colors from the four LEDs. The LEDs are capable of displaying three colors: green, red, and amber. The POST codes are divided into two nibbles, an upper nibble and a lower nibble. Each bit in the upper nibble is represented by a red LED and each bit in the lower nibble is represented by a green LED. If both bits are set in the upper and lower nibbles then both red and green LEDs are lit, resulting in an amber color. If both bits are clear, then the LED is off.
In the below example, BIOS sends a value of ACh to the diagnostic LED decoder. The LEDs are decoded as follows:
• red bits = 1010b = Ah
green bits = 1100b = Ch
Since the red bits correspond to the upper nibble and the green bits correspond to the lower nibble, the two are concatenated to be ACh.
Table 44: POST Progress Code LED Example
LEDs Red
8h
Green Red
4h
Result Amber Green
MSB
Green Red
2h
Green
Red
Red
1h
Green
Off
LSB
USB Port USB Port
Back edge of baseboard
Diagnostic LEDs
MSB LSB
Figure 28. Diagnostic LED Placement Diagram
100 Revision 1.9
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Intel
®
Server Board S5000PAL / S5000XAL TPS Appendix C: POST Code Diagnostic LEDs
Table 45. Diagnostic LED POST Code Decoder
Checkpoint
Diagnostic LED Decoder
G=Green, R=Red, A=Amber
MSB LSB
Host Processor
Description
0x10h OFF OFF OFF R Power-on of the host processor (bootstrap processor)
0x11h
0x12h
OFF
OFF
OFF
OFF
0x13h OFF OFF
OFF
G
A Host processor cache initialization (including AP)
R Starting application processor initialization
Chipset
0x21h
Memory
OFF OFF R G Initializing a chipset component
0x23h
0x25h
0x27h
OFF OFF
OFF
OFF
G
G
A
R
A
G Detecting presence of memory
G Configuring memory parameters in the memory controller
G Initializing memory, such as ECC init
PCI Bus
0x50h
0x51h
OFF
OFF
0x53h
0x54h
0x55h
0x56h
0x57h
USB
0x58h
0x59h
G
G
ATA / ATAPI / SATA
0x5Ah
0x5Bh
G
G
SMBUS
OFF
OFF
OFF
OFF
OFF
A
A
A
R OFF R Enumerating PCI busses
R OFF A Allocating resources to PCI busses
Hot PCI
R
A
G
OFF
A
R
Reserved for PCI bus
Reserved for PCI bus
OFF
G
G
A Reserved for PCI bus
R Reserved for PCI bus
A Reserved for PCI bus
R OFF
R OFF
R
R
G
G
R
A
R
A
Resetting USB bus
Reserved for USB devices
Resetting PATA / SATA bus and all devices
Reserved for ATA
0x5Dh G
Local Console
0x70h OFF
0x71h
0x72h
OFF
OFF
Remote Console
0x78h G
0x79h G
A
R
R
R
R
R
OFF
R
R
A
R
R
A
R
A
Reserved for SMBUS
Resetting the video controller (VGA)
A Disabling the video controller (VGA)
R Enabling the video controller (VGA)
R Resetting the console controller
Disabling the console controller
Keyboard (PS2 or USB)
0x90h R OFF OFF R Resetting the keyboard
0x91h R OFF
Revision 1.9
Intel order number: D31979-010
101
Appendix C: POST Code Diagnostic LEDs
Checkpoint
0x92h
Intel
®
Server Board S5000PAL / S5000XAL TPS
Diagnostic LED Decoder
G=Green, R=Red, A=Amber
MSB
R OFF G
LSB
R
Description
Detecting the presence of the keyboard
0x94h
0x95h
R
R
Mouse (PS2 or USB)
0x98h A
0x99h
0x9Ah
A
A
G
G
OFF
OFF
OFF OFF
OFF OFF
OFF G
R
A
R
A
R
Clearing keyboard input buffer
Instructing keyboard controller to run Self Test (PS2 only)
Resetting the mouse
Detecting the mouse
Detecting the presence of mouse
Fixed Media
0xB0h
0xB1h
0xB2h
R
R
OFF
OFF
R OFF
R
R
R
A
Resetting fixed media device
Disabling fixed media device
0xB3h R OFF
Removable Media
0xB8h
0xB9h
0xBAh
A
A
OFF
OFF
A OFF
A
R
R
A
R
A
Enabling / configuring a fixed media device
Resetting removable media device
Disabling removable media device
0xBCh A
Boot Device Selection
0xD0 R
0xD1
0xD2
R
R
0xD3
0xD4
0xD5
0xD6
R
R
R
R
0xD7
0xD8
0xD9
0XDA
0xDB
0xDC
0xDE
0xDF
A
A
A
A
R
A
A
A
G R
R OFF
R OFF
R G
R
A
A
A
R
A
A
A
G
OFF
OFF
G
A G
R OFF
R OFF
R G
G
OFF
G
G
R Enabling / configuring a removable media device
R Trying boot device selection
A Trying boot device selection
R Trying boot device selection
A Trying boot device selection
R Trying boot device selection
A Trying boot device selection
R Trying boot device selection
A Trying boot device selection
R Trying boot device selection
A Trying boot device selection
R Trying boot device selection
A Trying boot device selection
R Trying boot device selection
R Trying boot device selection
A Trying boot device selection
Pre-EFI Initialization (PEI) Core
0xE0h R R R OFF Started dispatching early initialization modules (PEIM)
0xE2h
0xE1h
0xE3h
R
R
R
R
R
R
A
R
A
OFF Initial memory found, configured, and installed correctly
G
G
Reserved for initialization module use (PEIM)
Reserved for initialization module use (PEIM)
Driver Execution Environment (DXE) Core
0xE4h R A R OFF Entered EFI driver execution phase (DXE)
0xE5h
0xE6h
R
R
A
A
R
A
G Started dispatching drivers
OFF Started connecting drivers
DXE Drivers
102 Revision 1.9
Intel order number: D31979-010
Intel
®
Server Board S5000PAL / S5000XAL TPS
Checkpoint
0xE7h
Appendix C: POST Code Diagnostic LEDs
Diagnostic LED Decoder
G=Green, R=Red, A=Amber
MSB
R A A
LSB
G Waiting for user input
Description
0xE9h A R R G Entering BIOS setup
0xEEh
0xEFh
A
A
A
A
A OFF Calling Int 19. One beep unless silent boot is enabled.
A G Unrecoverable boot failure / S3 resume failure
Runtime Phase / EFI Operating System Boot
0xF4h
0xF5h
0xF8h
R
R
A
A
R
R
R
A
Entering Sleep state
Exiting Sleep state
0xF9h
0xFAh
Pre-EFI Initialization Module (PEIM) / Recovery
0x30h OFF OFF R R Crisis recovery has been initiated because of a user request
0x31h
0x34h
0x35h
0x3Fh
OFF
OFF
OFF
G
OFF
G
G
G
R
R
R
A
A Crisis recovery has been initiated by software (corrupt flash)
R Loading crisis recovery capsule
A Handing off control to the crisis recovery capsule
A Unable to complete crisis recovery.
Revision 1.9
Intel order number: D31979-010
103
8300
8306
8305
84F2
84F3
84F4
8160
8161
8190
8198
0192
0194
0195
Appendix D: POST Error Messages and Handling Intel
®
Server Board S5000PAL / S5000XAL TPS
Appendix D: POST Error Messages and Handling
Whenever possible, the BIOS will output the current boot progress codes on the video screen. Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class, subclass, and operation information. The class and subclass fields point to the type of hardware that is being initialized. The operation field represents the specific initialization activity. Based on the data bit availability to display progress codes, a progress code can be customized to fit the data width. The higher the data bit, the higher the granularity of information that can be sent on the progress port. The progress codes may be reported by the system BIOS or option ROMs.
The Response section in the following table is divided into two types:
Pause: The message is displayed in the Error Manager screen, an error is logged to the
SEL, and user input is required to continue. The user can take immediate corrective action or choose to continue booting.
Halt: The message is displayed in the Error Manager screen, an error is logged to the SEL, and the system cannot boot unless the error is resolved. The user needs to replace the faulty part and restart the system.
0048
0141
0146
8110
8111
8120
8121
Table 46. POST Error Messages and Handling
Error Code
004C
0012
5220
5221
Error Message
Keyboard / interface error
CMOS date / time not set
Configuration cleared by jumper
Passwords cleared by jumper
Password check failed
PCI resource conflict
Insufficient memory to shadow PCI ROM
Processor 01 internal error (IERR) on last boot
Processor 02 internal error (IERR) on last boot
Processor 01 thermal trip error on last boot
Processor 02 thermal trip error on last boot
Processor 01 unable to apply BIOS update
Processor 02 unable to apply BIOS update
Watchdog timer failed on last boot
Operating system boot watchdog timer expired on last boot
L3 cache size mismatch
CPUID, processor family are different
Front side bus mismatch
Baseboard management controller failed self-test
Front panel controller locked
Hot swap controller failed
Baseboard management controller failed to respond
Baseboard management controller in update mode
Sensor data record empty
Response
Pause
Pause
Pause
Pause
Pause
Halt
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Halt
Halt
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
104 Revision 1.9
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Intel
®
Server Board S5000PAL / S5000XAL TPS Appendix D: POST Error Messages and Handling
852D
852E
852F
8540
8580
8581
8582
8583
8584
8585
8586
8587
8588
8589
858A
858B
858C
858D
858E
858F
8600
8525
8526
8527
8528
8529
852A
852B
852C
Error Code
84FF
8500
8520
8521
8522
8523
8524
8601
8602
8603
Error Message
System event log full
Memory Component could not be configured in the selected RAS mode.
DIMM_A1 failed Self Test (BIST).
DIMM_A2 failed Self Test (BIST).
DIMM_A3 failed Self Test (BIST).
DIMM_A4 failed Self Test (BIST).
DIMM_B1 failed Self Test (BIST).
DIMM_B2 failed Self Test (BIST).
DIMM_B3 failed Self Test (BIST).
DIMM_B4 failed Self Test (BIST).
DIMM_C1 failed Self Test (BIST).
DIMM_C2 failed Self Test (BIST).
DIMM_C3 failed Self Test (BIST).
DIMM_C4 failed Self Test (BIST).
DIMM_D1 failed Self Test (BIST).
DIMM_D2 failed Self Test (BIST).
DIMM_D3 failed Self Test (BIST).
DIMM_D4 failed Self Test (BIST).
Memory Component lost redundancy during the last boot.
DIMM_A1 Correctable ECC error encountered.
DIMM_A2 Correctable ECC error encountered.
DIMM_A3 Correctable ECC error encountered.
DIMM_A4 Correctable ECC error encountered.
DIMM_B1 Correctable ECC error encountered.
DIMM_B2 Correctable ECC error encountered.
DIMM_B3 Correctable ECC error encountered.
DIMM_B4 Correctable ECC error encountered.
DIMM_C1 Correctable ECC error encountered.
DIMM_C2 Correctable ECC error encountered.
DIMM_C3 Correctable ECC error encountered.
DIMM_C4 Correctable ECC error encountered.
DIMM_D1 Correctable ECC error encountered.
DIMM_D2 Correctable ECC error encountered.
DIMM_D3 Correctable ECC error encountered.
DIMM_D4 Correctable ECC error encountered.
Primary and secondary BIOS IDs do not match.
Override jumper is set to force boot from lower alternate BIOS bank of flash
ROM
WatchDog timer expired (secondary BIOS may be bad!)
Secondary BIOS checksum fail
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Response
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Pause
Revision 1.9
Intel order number: D31979-010
105
Appendix D: POST Error Messages and Handling Intel
®
Server Board S5000PAL / S5000XAL TPS
POST Error Beep Codes
The following table lists POST error beep codes. Prior to system Video initialization, BIOS uses these beep codes to inform users on error conditions. The beep code is followed by a user visible code on
POST Progress LEDs.
Table 47. POST Error Beep Codes
Beeps
3
Error Message POST Progress Code
Memory error
6 BIOS error
Description
System halted because a fatal error related to the memory was detected.
The system has detected a corrupted BIOS in the flash part, and is rolling back to the last good BIOS.
The BMC may generate beep codes upon detection of failure conditions. Beep codes are sounded each time the problem is discovered, such as on each power-up attempt, but are not sounded continuously.
Codes that are common across all Intel
®
Server Boards and systems that use the Intel
®
S5000 chipset are listed in Table 48. Each digit in the code is represented by a sequence of beeps whose count is equal to the digit.
Table 48. BMC Beep Codes
Code Reason for Beep
1-5-2-1 CPU: Empty slot / population error – Processor slot 1 is not populated.
1-5-2-2 CPU: No processors (terminators only)
Associated Sensors
CPU Population Error
N/A
1-5-2-3 CPU: Configuration error (e.g., VID mismatch) N/A
1-5-2-4 CPU: Configuration error (e.g., BSEL mismatch) N/A
1-5-4-2 Power fault: DC power unexpectedly lost (power good dropout)
Power Unit – power unit failure offset
1-5-4-3 Chipset control failure
1-5-4-4 Power control fault
N/A
Power Unit – soft power control failure offset
Supported?
Yes
No
No
No
Yes
No
Yes
106 Revision 1.9
Intel order number: D31979-010
Intel
®
Server Board S5000PAL / S5000XAL TPS Appendix E: Supported Intel
®
Server Chassis
Appendix E: Supported Intel
®
Server Chassis
The Intel® Server Board S5000PAL / S5000XAL is supported in the following Intel high density rack mount server chassis:
•
•
Intel
Intel
• Intel
®
®
®
Server Chassis SR1500
Server Chassis SR1550
Server Chassis SR2500
This section provides a high level descriptive overview of each chassis. For more detail, please reference the appropriate Technical Product Specification (TPS) available for each.
F
E G
H
D
I
C
B
A
P
O
K
J
L
N
A
M
TP02154
A
B
Rack handles
Backplane – Passive SAS/SATA or Active
SAS/SAS RAID
I
J
PCI card bracket (low profile) – PCIe*
Processor air duct
D
E
F
G
H
Power supply fans
600 Watt Power supply
Intel® Server Board S5000PAL / S5000XAL
PCI card bracket (full height) – PCI-X* or PCIe*
PCI add-in riser assembly
L
M
N
O
P
Bridge board
Control panel (standard control panel shown)
Hard drive bays (drives not included)
Slimline drive bay (drive not included)
Front bezel (optional)
Figure 29. 1U – Intel
®
Server Chassis SR1500 Overview
Revision 1.9
Intel order number: D31979-010
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Appendix E: Supported Intel
®
Server Chassis Intel
®
Server Board S5000PAL / S5000XAL TPS
108
A Rack Handles
B SAS/SATA Backplane
C
SAS RAID Battery Pack
(Optional)
D Power Supply Air Duct
E Power Distribution Board
F
G
1+1 650 Watt Power Supply
Modules
Intel® Server Board S5000PAL /
S5000XAL
I Intel
®
J Intel ®
K
RMM Module (Optional)
RMM NIC(Optional)
IO Module (Optional)
L Riser Card Assembly
M System Memory
N Processor and Heat Sink
O Processor Air Duct
P
Q
R
S
T
U
System Fan Bank
Mid-plane Board
(Active - SAS/SAS RAID shown)
Front Bezel (Optional; Standard Control Panel shown)
Standard Control Panel or Intel
®
Local Control
Panel (Optional)
Mini Control Panel Bay – required option to support eight hard drives
Slimline Optical Drive Bay
V Up to Eight 2.5” Hard Drive Bays
Figure 30. 1U – Intel
®
Server Chassis SR1550 Overview
Revision 1.9
Intel order number: D31979-010
Intel
®
Server Board S5000PAL / S5000XAL TPS Appendix E: Supported Intel
®
Server Chassis
E
F
B
C
D
A
G
N
H
M
I
L
K
J
A
TP02094
A. Rack Handles
B. SAS/SATA Backplane
C. Air Baffles
D. Power Distribution Module
E.
1+1 750 Watt Power Supply
Modules
F. Riser Card Assembly
G. System Memory
Mid-pane – Passive SAS/SATA or Active SAS/SAS RAID
(Not shown)
H. CPU Air Duct
I. System Fan Assembly
J. Standard Control Panel
K. Flex Bay – 6 th
HDD or Tape (Optional)
L. Five SATA/SAS Hard Drive Bays
M. Slim-Line Optical Drive Bay
N. Front Bezel (Optional)
Figure 31. 2U – Intel
®
Server Chassis SR2500 Overview
Revision 1.9
Intel order number: D31979-010
109
APIC
ASIC
ASMI
BIOS
BIST
BMC
Bridge
Glossary Intel
®
Server Board S5000PAL / S5000XAL TPS
Glossary
This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (e.g., “82460GX”) with alpha entries following (e.g., “AGP 4x”). Acronyms are then entered in their respective place, with non-acronyms following.
Term
ACPI Advanced Configuration and Power Interface
Definition
Advanced Programmable Interrupt Control
Application Specific Integrated Circuit
Advanced Server Management Interface
Basic Input/Output System
Built-In Self Test
Baseboard Management Controller
Circuitry connecting one computer bus to another, allowing an agent on one to access the other
CBC
CEK
CHAP
CMOS
Chassis Bridge Controller (A microcontroller connected to one or more other CBCs, together they bridge the IPMB buses of multiple chassis.
Common Enabling Kit
Challenge Handshake Authentication Protocol
In terms of this specification, this describes the PC-AT compatible region of battery-backed 128 bytes of memory, which normally resides on the server board.
EHCI
EMP
EPS
ESB-2
FBD
Enhanced Host Controller Interface
Emergency Management Port
External Product Specification
Enterprise South Bridge 2
Fully Buffered DIMM
FRU
FSB
Field Replaceable Unit
Front Side Bus
GB 1024MB
GPIO General I/O
Hz Hertz (1 cycle/second)
IA Intel
®
Architecture
ICH
ICMB
I/O Controller Hub
Intelligent Chassis Management Bus
IFB I/O and Firmware Bridge
INTR Interrupt
IPMB
110
Intelligent Platform Management Bus
Revision 1.9
Intel order number: D31979-010
Intel
®
Server Board S5000PAL / S5000XAL TPS
Term
IPMI Intelligent Platform Management Interface
IR Infrared
Definition
KCS
LAN
LCD
LED
LPC
LUN
Keyboard Controller Style
Local Area Network
Liquid Crystal Display
Light Emitting Diode
Low Pin Count
Logical Unit Number
MB 1024KB
MCH Memory Controller Hub
MD2
MD5
Message Digest 2 – Hashing Algorithm
Message Digest 5 – Hashing Algorithm – Higher Security ms milliseconds
MTTR Memory Type Range Register
Mux Multiplexor
Glossary
Ohm
PEF
PEP
PIA
PLD
PMI
POST
PSMI
Unit of electrical resistance
Platform Event Filtering
Platform Event Paging
Platform Information Area (This feature configures the firmware for the platform hardware)
Programmable Logic Device
Platform Management Interrupt
Power-On Self Test
Power Supply Management Interface
RAM
RASUM
RISC
ROM
RTC
SDR
SECC
Random Access Memory
Reliability, Availability, Serviceability, Usability, and Manageability
Reduced Instruction Set Computing
Read Only Memory
Real-Time Clock (Component of ICH peripheral chip on the server board)
Sensor Data Record
Single Edge Connector Cartridge
SEEPROM Serial Electrically Erasable Programmable Read-Only Memory
SEL System Event Log
SMI Server Management Interrupt (SMI is the highest priority nonmaskable interrupt)
SMS
SNMP
TBD
TIM
Server Management Software
Simple Network Management Protocol
To Be Determined
Thermal Interface Material
Revision 1.9
Intel order number: D31979-010
111
Glossary Intel
®
Server Board S5000PAL / S5000XAL TPS
Definition Term
UDP
UHCI
User Datagram Protocol
Universal Host Controller Interface
VRD
ZIF
Voltage Regulator Down
Zero Insertion Force
112 Revision 1.9
Intel order number: D31979-010
Intel
®
Server Board S5000PAL / S5000XAL TPS
Reference Documents
Reference Documents
See the following documents for additional information:
Intel
®
S5000 Series Chipsets Server Board Family Datasheet
Intel ® S5000 Server Board Family BIOS Core External Product Specification (Yellow Cover)
Intel ® S5000 Server Board Family BMC Core External Product Specification (Yellow Cover)
Intel
®
5000P Memory Controller Hub External Design Specification (Yellow Cover)
Intel
®
Enterprise South Bridge-2 (ESB-2) External Design Specification (Yellow Cover)
TEB 2.11 – Thin Electronics Bay (1U/2U Rack Optimized)
EPS 1U Rev. 2.93 – Entry Level Power Supply – 1U non-redundant – Intel ® S5000 Server Board
Family
ERP 2U – Rev. 2.31 – Entry Redundant Power Supply 2U form factor – Intel ® S5000 Server
Board Family
Note: Yellow Cover documents can only be obtained under NDA with Intel and ordered through an Intel representative.
Revision 1.9
Intel order number: D31979-010
113
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Klíčové vlastnosti
Intel LGA 771 (Socket J)
Server SSI TEB Intel® 5000P
DDR2-SDRAM Maximum internal memory: 32 GB
IDE/ATA RAID support
Fast Ethernet, Gigabit Ethernet
