6.3 Clock functionality. STMicroelectronics SuperH™(SH) 32-bit RISC series SH-4, ST40 system architecture, volume 1: system, SUPERH SH-4, ST40 SYSTEM ARCHITECTURE VOLUME 1
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Clock functionality
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125
6.3.1 Internal organization
The internal organization of each clock controller is shown in
XTAL in
27 MHz
CPGL
Bank
FRQCR
FRQCR2
STBCR
STBCR2
S
T
B u s pwr_down_ack[7:0]
PLL1
ST40-CLOCKGEN div 1/2
Dividers bank1 x1 x2 x2/3 x3 x4 x6 x8 main_1clk clkstop
RATIO
FILTER
CLOCKGEN A only
PLL1CR1
PLL1CR2
CLK1CR
CLK2CR
CLK3CR ratio
CPG_BYPASS
CLOCKGEN bank
STBREQCR
STBACKCR
CLK4CR
CLK_SELCR
PLL2_MUXCR
PLL2CR
GCK
Clock domain A11
Clock domain A12
Clock domain A13
Clock domain A14 pwr_down_req [7:0] clk_sel [7:0]
PLL2 main_2clk
: 11
: 4
: 8
: 16
: 21
Dividers bank 2
Figure 13: CLOCKGEN architecture
Clock Domain A2M
Clock Domain A21
Clock Domain A22
Clock Domain A23
Clock Domain A24
Clock Domain A25
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Clock functionality
If two or more clock controllers are implemented, the area controlled by the CPG registers is only available on CLOCKGEN A.
organized.
27 MHz
CPGL
SuperHyway
ST40-CLOCKGEN A
PLL1
DIV bank1 sel ratio filt clk domain A11 clk domain A12 clk domain A13 clk domain A14
Control
Low Power
PLL2
DIV bank2
:11
:8
:4
:16
:21 clockgena_clk_sel[7:0] clockgena_stb_req[7:0] clk domain A2M clk domain A21 clk domain A22 clk domain A23 clk domain A24 clk domain A25
ST40-CLOCKGEN B
PLL1
DIV bank1 sel clk domain B11 clk domain B12 clk domain B13 clk domain B14 ratio filt
PPC
Control clockgenb_clk_sel[7:0] clockgenb_stb_req[7:0]
Low Power
PLL2
DIV bank2 clk domain B2M clk domain B21 clk domain B22 clk domain B23 clk domain B24 clk domain B25
Figure 14: ST40 clock architecture
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Clock functionality
The correspondence between clock domains and peripherals is tabulated in the
product datasheet.
6.3.2 PLL1 control
Diagram
127 external-clock x2 _p ll1e na
0
1 cpg _b ypa ss sin ch _sh _p ll1e n sin ch_ stb _p ll1e n sinc h_ sh_ pll1 en x2_istp
0
1
Clockin
PLL1
En
PLL Config
Clock
Lock en clk deglitcher
GBUF en
PLLclock en clk deglitcher en clk deglitcher
0
1
0
1 en clk deglitcher
Mdiv Ndiv Pdiv PllSetup PllPowerOn
PLL1CR1
PllOutEn Lock sin ch_ stb _p ll1e n
STBpllen STBPllensel STBfastsel STBmode
PLL1CR2 note: this symbol means a synchronization stage that can cause a delay of two stage.
0
1
2*main clk
Figure 15: Configuration and control of PLL1 using the PLL1CR1 and PLL1CR2 registers
Introduction
The frequency and behavior of clocks associated with PLL1 may be controlled using three methods:
• by enabling or disabling PLL1 and bypassing the PLL function,
• by changing the frequency division ratio of each clock domain,
• by changing the configuration of PLL1.
To ensure that a stable clock is delivered whilst a change is occurring, the PLL control logic should follow only those state transactions shown
should take care when changing PLL frequencies or relative clock ratios that:
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Clock functionality
• the PLL is stable before re-enabling clocks,
• there is no communications traffic between semi-synchronous domains when changing relative clock ratios.
The PLL frequency is defined by the contents of the MDIV, NDIV and PDIV in the
CLKGEN.PLL1CR1
register. For details of allowable values refer to the datasheet.
Allowable transitions start-up (mode 6 & 7) sh_run_slow ratio encoded cpg_bypass=0
CLOCKGEN PLL1 valid states
(related to PLL1) sh2st_slow st2sh_slow program PLL1CR1
(PLL dividers) and CPGL-WDT st_run_slow ratio encoded cpg_bypass=0 no ratio encoded cpg_bypass=1 program PLL1CR1
(PLL dividers) st_leaving_slow after PLL locked sh_run_fast ratio encoded cpg_bypass=0 start-up (mode 0 to 5) sh2st_fast st2sh_fast
_fast: clock source is PLL1
_slow: clock source is external xosc @ 27 MHz sh_: control by FRQCR st_: control by PLL1CR2
Figure 16: CLOCKGEN A PLL1 valid states st_run_fast ratio encoded cpg_bypass=0 no ratio encoded cpg_bypass=1
States labelled sh_xxx are available for CLOCKGEN A only,
States labeled st_xxx are available for all CLOCKGEN macros.
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Clock functionality 129
State definitions
Register fields sh_run slow sh_run fast st_run slow st_run fast st_leaving slow sh2st slow sh2st fast st2sh slow st2sh fast
1 1 0 1 1 PLL1CR1.
PLLOUTEN
PLL1CR2.
STBPLLEN
PLL1CR2.
STBPLLENSEL
PLL1CR2.
STFASTSEL
PLL1CR2.
STBMODE
(CPGL)FRQCR.
PLL1EN
CPG_BYPASS
-
-
-
A
0
0
0
0
-
-
0
0
1
0 -
-
0
1
0
1
-
-
1
1
1
1
-
1
1
0
1
0
0
1
0
0
0
0
1
1
1
0
1
0
0
1
0
1
0
0
1
1
1
1
1
0
Table 68: Allowed configurations for CLOCKGEN A and CPGL.FRQCR registers
A. - don’t care
Enabling and disabling PLL1
Software may enable or disable the CLOCKGEN A PLL1 by changing the clock source from PLL1 to the external xosc clock directly. The internal clock is then preset to the xosc frequency/2.
This is achieved by placing the CLOCKGEN PLL in either the SH_RUN_SLOW or
ST_RUN_SLOW state.
Changing PLL1 divide ratios (clk1 to 3)
The frequency of a CLOCKGEN output clock may be changed by updating its divide ratio.
For clocks 11 through 13, CLOCKGEN ensures a safe transition between the two frequencies, whilst for clock 14, the user is responsible for stopping the clock before modifying the ratios.
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Clock functionality
Whilst the transition is guaranteed for clocks 11 through 13, the user must ensure the target module functions correctly during this period. Some modules such as
UARTs require stable frequencies during operation. Others are associated with more than one clock and are unable to function correctly if the ratio between those clocks changes whilst the module is active.
Restrictions may apply. As an example, in some ST40 systems, the CPU has direct dependencies on two clock domains, I-Clk and P-Clk. Changes in relative frequency between these clocks whilst the CPU is active may lead to undefined behavior. For the ST40 CPU, I-Clk must be an integer multiple of the P-Clk frequency. The maximum supported frequencies are in the product datasheet.
Two methods are supported for changing PLL1 divide ratios.
• CPGL mode (allowed only for CLOCKGEN A clocks)
If CLKGEN.CPG_BYPASS
is inactive (set to 0), CLOCKGEN A is in CPGL mode.
The frequency of clocks 11 through 13 may be changed by reprogramming
CPG.FRQCR
. CPGL mode is the default for CLOCKGEN A clocks.
• ST mode
If CLKGEN.CPG_BYPASS
is active (set to 1), the CLOCKGEN macro is in ST mode.
The frequency of clocks 11 through 13 may be changed by programming
CLKGEN.CLK1CR
, CLKGEN.CLK2CR
and CLKGEN.CLK3CR
respectively.
Changing the PLL1 divide ratio for clock 14
The frequency of clock 14 may be changed by updating the CLKGEN.CLK4CR
register. The following procedure ensures safe operation.
1 Stop clock 14 by asserting (setting to 1) CLKGEN.CLK4CR.CLKSTOP
.
2 Change the field ratio of CLKGEN.CLK4CR
.
3 Restart clock 14 by de-asserting (setting to 0) CLKGEN.CLK4CR.CLKSTOP
.
Changing PLL1 lock frequency
The ST40 CLOCKGEN macro includes a highly flexible PLL which may be programmed to output a range of frequencies. This is achieved by updating the
MDIV, NDIV and PDIV fields of CLKGEN.PLL1CR1
. However whilst the PLL is locking-on the new frequency, the clock outputted by the macro is unstable.
Software should ensure there is no activity in parts of the system associated with the PLL. There are two methods of handling this. You can either put the system to
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Clock functionality 131 sleep, and use the watchdog to restart the system when the PLL clocks are stable, or bypass the PLL and use an external clock during the period of instability.
Examples of these procedures are described below.
SH procedure: CLOCKGENA only
1 Move CLOCKGEN to state sh_run_slow.
This action disables the PLL1 and sets the CLOCKGEN clock source to the external crystal (27 MHz).
Note: the maximum clock rate is half of the input clock rate (see
2 Update PLL1 using the MDIV, NDIV and PDIV fields of CLKGEN.PLL1CR1
.
Only values defined in the datasheet are valid, other values may lead to undefined behavior.
3 Program the WDT to provide the specified oscillation stabilization time before timing out.
The WDT should have the following settings:
CPG.WTCSR
register: TME bit = 0, WDT stopped,
CPG.WTCSR
register: CKS2 to CKS0 bits, WDT count clock division ratio,
CPG.WTCNT
register: initial counter value,
CPG.WTCNT
register: initial counter value.
4 Move CLOCKGEN to STATE sh_run_fast.
This puts the CPU in a suspend state until the WDT countdown completes, at which point the PLL is re-enabled and clocks 11 through 14 are restarted using the new
PLL frequency.
ST procedure
1 Move CLOCKGEN to state st_run_slow.
This action disables PLL1 and selects the external crystal clock as the input to the system bypassing PLL1. The internal clock frequency is a divisor of half the external clock ratio as determined by the clock 11 through 14 divide ratios.
2 Update PLL1 using the MDIV, NDIV and PDIV fields of CLKGEN.PLL1CR1
.
Only values defined in the datasheet are valid, other values may lead to undefined behavior.
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132 Clock functionality
3 Move CLOCKGEN to state st_leaving_slow.
PLL1 is enabled, but is still bypassed.
for to reach 1.
This indicates the PLL has stabilized.
5 Move CLOCKGEN to state st_run_fast.
The clock source for clocks 11 through 14 to the PLL is changed rather than the external x-tal clock.
Note: no clocks are stopped using the ST procedure.
PLL frequency calculation
Details of the relationship between CLKGEN.PLL1CR1.[MDIV, NDIV, PDIV] and the
PLL frequency are available in the product datasheet.
6.3.3 Configuring PLL2
Introduction pci_host pci_clkin external-clock
Clockin
PLL2
PLL Config
Clock
Lock
En
1
0
GBUF en PLLclock
0
1
PCIclock
Mdiv Ndiv Pdiv PllSetup PllPowerOn PllOutEn LockSelect Lock
Figure 17: Configuration and control of PLL2 using the PLL2CR registers
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Clock functionality 133
There are two ways of changing the frequency of clocks associated with the PLL2 clock:
• enabling or disabling PLL2,
• changing the configuration of PLL2.
The procedures are discussed below, for details on specific PLL settings refer to the datasheet for that device.
Procedure to enable and disable PLL2
CLOCKGEN PLL2 is disabled by writing 0 to CLKGEN.PLL2CR.PLLOUTEN
and
CLKGEN.PLL2CR.LOCKSELECT.
It is enabled by writing 1 to CLKGEN.PLL2CR.PLLOUTEN
and
CLKGEN.PLL2CR.LOCKSELECT.
In some systems it may be possible to bypass PLL2, see datasheet for details.
Changing the frequency of PLL2
The PLL2 derived clocks are generated by CLOCKGEN using PLL2 which is a programmable PLL.
PLL2 takes the input frequency from the external qx_xtalout27 clock, which runs at
27 MHz. It is possible to change the output frequency of this PLL by changing the value of its MDIV, NDIV and PDIV. This can be achieved programming the corresponding fields of the configuration register PLL2CR .
To change the PLL2 output frequency to a value different from at start up, use the following procedure.
1 Write 0 in the PLL2CR register fields PLLOUTEN and LOCKSELECT.
This allows CLOCKGEN to stop the PLL2 clockout (PLL2 clock = 0).
2 Disable PLL2 by setting PLL2CR.PLLPOWERON
to 0.
3 Change the division and multiply ratios of PLL2 by updating the values of the
MDIV, NDIV and PDIV fields of the PLL2CR register, as defined by the datasheet.
4 Restart PLL2 by setting PLL2CR.PLLPOWERON
to 1.
5 Set the LOCKSELECT field of PLL2CR to 1 to enable output of the PLL2 clock when the lock is achieved.
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134 Clock functionality
This is the recommended way to enable the output of the PLL clock. However alternatively you can poll CLKGEN.PLL2CR.LCK
until active and then select the
PLL2 clockout by setting CLKGEN.PLL2CR.PLLOUTEN
to 1.
6.3.4 Register description
Frequency control register 1 (CPG.FRQCR)
The clock frequency division ratios are controlled by the FRQCR register in the CPG bank.
Field
RATIO
CPG.FRQCR
0x00
Bits
Read
Write
Hard reset
Size Volatile
[0:8]
Operation
9 No
Synopsis
Clock frequency division ratios
Type
RW
Specifies the frequency ratios with respect to the Output of
PLL circuit 1 output frequency
Refer to the product datasheet for details
Use of invalid values may lead to undefined behavior
Returns current value
Updates current value
Set by MD0,MD1 and MD2 pins
See product datasheet for details
No Reserved RW 9
Operation
1
Read
Write
Hard reset
Returns current value
Updates current value
1
Table 69: CPG.FRQCR
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Clock functionality 135
-
Field
PLL1EN
CPG.FRQCR
0x00
Bits Size Volatile
10
Operation
Read
Write
1 No PLL Circuit 1 enable
Returns current value
0: PLL 1 is not used
1: PLL1 is used
1
No
Synopsis
Specifies whether PLL 1 is used
Type
RW
Reserved RW
Hard reset
11 1
Operation
Read
Write
Hard reset
[12:15] 4
Operation
Read
Write
Hard reset
-
Returns current value
Updates current value
1
Reserved
Returns 0
Ignored
0
Reserved Res
Table 69: CPG.FRQCR
Valid FRQCR values and the associated ratios are defined for each product and listed in the product datasheet.
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CLKGEN.PLL1CR1
This register defines the behavior of PLL 1.
Field
MDIV
NDIV
CLOCKGEN.PLL1CR1
PLL1 control Register
0x00
Bits
[0:7]
Operation
8
Read
Write
Hard reset
[8:15]
Operation
Read
Write
Hard reset
Size Volatile
8
Pre-divider
Returns current value
Synopsis
Parameter for programming PLL1
Type
Other
Updates current value
Note: this register has a write lock
A
Only certain values, as defined in the product datasheet, may be written. All other values are reserved and give undefined behavior.
-
See datasheet
Feedback divider
Parameter for programming PLL1
Returns current value
Other
Updates current value
Note: this register has a write lock
Only certain values, as defined in the product datasheet, may be written. All other values are reserved and give undefined behavior.
See the product datasheet
Table 70: CLOCKGEN.PLL1CR1
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Clock functionality 137
Field
PDIV
SETUP
CLOCKGEN.PLL1CR1
PLL1 control Register
POWERON
0x00
Bits Size Volatile
[16:18] 3
Operation
Read
Write
Hard reset
[19:27]
Operation
Read
Write
Hard reset
28
Operation
Read
Write
Hard reset
9
1
Post divider
Returns current value
Synopsis
Parameter for programming PLL1
Type
Other
Updates current value
Note: this register has a write lock
Only certain values, as defined in the product datasheet, may be written. All other values are reserved and give undefined behavior.
-
See datasheet
Loop characteristics
Parameter for programming PLL1
Other
Returns current value
Updates current value
Note: this register has a write lock
Only certain values, as defined in the product datasheet, may be written. All other values are reserved and give undefined behavior.
-
See datasheet
PLL1 Power On
Specifies the power setting of PLL1
1: power on
0: power off
Ignored
See the product datasheet
RO
Table 70: CLOCKGEN.PLL1CR1
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Clock functionality
CLOCKGEN.PLL1CR1
PLL1 control Register
0x00
-
Field
OUTENABLE 29
Operation
1
Read
Write
LOCK
Bits
Read
Write
Size Volatile
Hard reset
30 1
Operation
Hard reset
31
Operation
1
Read
Write
Hard reset
Synopsis
Enable output of PLL clock
Allows s/w control of PLL1 output clock
Type
Other
Returns current value
Updates current value
1: PLL1 out Enabled
0: PLL1 out not Enabled
Note: this register has a write lock
1
Yes PLL Circuit 1 Lock achieved RO
Specifies whether PLL 1 output has achieved lock and the output is stable
0: PLL 1 Lock not achieved
1: PLL1 is Locked
Updates current value.
Note: this register has a write lock
1
Res -
Reserved
Reserved
Returns 0
Ignored
0
Table 70: CLOCKGEN.PLL1CR1
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Clock functionality
A. CLOCKGEN.PLL1CR1 is writable if
(PLL1CR2.STBPLLENSEL = 0 and FRQCR.PLL1EN = 0) or
(PLL1CR2.STBPLLENSEL= 1 and
PLL1CR2.STBPLLEN = 0)
139
CLKGEN.PLL1CR2
This register defines the behavior of PLL 1.
Field
STBPLLEN
CLOCKGEN.PLL1CR2
PLL1 control Register
Bits
Read
Write
Hard reset
Size
0
Operation
1 -
Volatile
0x08
Synopsis
PLL1 enable
Table 71: CLOCKGEN.PLL1CR2
Type
RW
Alternative enable to the FRQCR.PLL1EN field See
This field specifies whether PLL1 is enabled when
STBPLLENSEL is 1, otherwise it has no effect
Returns current value
1: enabled
0: not enabled AND selected the external-clock as input clock
0
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Clock functionality
STBFASTSE
L
CLOCKGEN.PLL1CR2
PLL1 control Register
Field
STBPLLENS
EL
Bits Size Volatile
0x08
Synopsis Type
1
Operation
1
Read
Write
Hard reset
2
Operation
1
Read
Write
Hard reset
PLL1 enable selector.
Selects if PLL1 is enabled by FRQCR.PLL1EN or
STBPLLEN.
See
RW
Returns current value
Updates current value
0: FRQCR.PLL1EN specifies enabling
A
1: STBPLLEN specifies enabling
0
Clock selector RW
Select if 2*main clock is set to PLL1_CLOCK (fast) or to external clock from the xtal.
The switch is synchronized
Note: Selection take place only if STBMODE field is set to
1 see
Returns current value
Updates current value
1: 2*main_clock equal to PLL1 clock (fast clock)
0: 2*main_clock equal to external clock
0
Table 71: CLOCKGEN.PLL1CR2
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Clock functionality 141
CLOCKGEN.PLL1CR2
PLL1 control Register
0x08
Field Bits Size Volatile Synopsis Type
-
STBMODE 3
Operation
Read
Write
1
Hard reset
[4:31]
Operation
29
Read
Write
Hard reset
Clock selector
Select if 2*main_clock is controlled by
PLL1CR.STBFASTSEL or FRQCR.PLL1EN see
.
RW
Returns current value
Updates current value
1: control given to PLL1CR.STBFASTSET
0: control given to FRQCR.PLL1EN
0
-
Reserved
Returns 0
Ignored
0
Reserved
Table 71: CLOCKGEN.PLL1CR2
Res
A. Write lock operation
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CLKGEN.PLL2CR
This register defines the behavior of PLL 2.
Field
MDIV
NDIV
CLOCKGEN.PLL2CR
PLL2 control Register
0x10
Bits
Hard reset
[8:15]
Operation
8
Read
Write
Hard reset
Size Volatile
[0:7]
Operation
8
Read
Write
Pre-divider
Returns current value
Synopsis
Parameter for programming PLL2
Type
RW
Updates current value
Note: Only certain values, as defined in the product datasheet, may be written. All other values are reserved and give undefined behavior.
See product datasheet
RW Feedback divider
Parameter for programming PLL2
Returns current value
Updates current value
Note: Only certain values, as defined in the product datasheet, may be written. All other values are reserved and give undefined behavior.
See product datasheet
Table 72: CLOCKGEN.PLL2CR
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CLOCKGEN.PLL2CR
PLL2 control Register
0x10
Field Bits Size Volatile Synopsis Type
PDIV
SETUP
[16:18] 3
Operation
Read
Write
Hard reset
[19:27] 9
Operation
Read
Write
Hard reset
POWERON 28 1
Operation
Read
Write
Hard reset
Post divider
Parameter for programming PLL2
RW
Returns current value
Updates current value
Note: Only certain values, as defined in the product datasheet, may be written. All other values are reserved and give undefined behavior.
-
See product datasheet
Loop characteristics
Parameter for programming PLL2
Other
Returns current value
Updates current value
Note: Only certain values, as defined in the product datasheet, may be written. All other values are reserved and give undefined behavior.
-
See product datasheet
PLL2 Power On
Specifies the power setting of PLL2
RO
1: power on
0: power off
Ignored
See product datasheet
Table 72: CLOCKGEN.PLL2CR
143
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Clock functionality
CLOCKGEN.PLL2CR
PLL2 control Register
0x10
Field Bits Size Volatile Synopsis Type
PLLOUTEN 29
Operation
1
Read
Write
LOCKSELE
CT
LOCK
Hard reset
30
Operation
1
Read
Write
Hard reset
31
Operation
1
Read
Write
Hard reset
Enable output of PLL2 clock
Allows s/w control of PLL2 output clock
Returns current value
Updates current value
1: PLL out Enabled
0: PLL out not Enabled
RW
See product datasheet
Yes Selects how the PLL2 is enabled RW
Specifies whether PLL2 output should be enabled when lock is achieved or as indicated by PLLOUTEN field
Returns current value
0: PLLOUTEN setting governs PLL2 output
1: Lock setting governs PLL PCIoutput
See product datasheet
Yes PLL2 Lock achieved RO
Specifies whether PLL2 output has achieved lock and the output is stable
0: PLL2 Lock not achieved
1: PLL2 is Locked
Updates current value
See product datasheet
Table 72: CLOCKGEN.PLL2CR
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Clock functionality
CLOCKGEN.CLK4CR
CLK4CR allows software to change the division ratio of this clock.
CLOCKGEN.CLK4CR
PLL1 Clock 4 control register
Field
RATIO
CLKSTOP
0x38
Bits
[0:2]
Size Volatile
3 -
Synopsis Type
Division ratio of PLL1CLK4 clock
with respect of output of PLL1 div 2
RW
Operation
Read
Write
Hard reset
3 1
Operation
Read
Write
Hard reset
Returns current value
000: ratio 1:1
001: ratio 1:2
010: ratio 1:3
011: ratio 2:3
100: ratio 1:4
101: ratio 1:6
110: ratio 1:8
111: ratio 1:8.
see datasheet
PLL1 enable selector.
This bit allows stopping of the PLL1CLK4 clock
Returns current value
Updates current value
1: PLL1CLK4 clock stopped
0
Table 73: CLOCKGEN.CLK4CR
RW
145
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Clock functionality
-
CLOCKGEN.CLK4CR
PLL1 Clock 4 control register
Field
0x38
Bits Size Volatile
[4:31]
Operation
Read
28
Write
Hard reset
-
Reserved
Returns 0
Ignored
0
Reserved
Synopsis
Table 73: CLOCKGEN.CLK4CR
Type
Res
To safely change the value of the division ratio of the PLL1CLK4 clock the following sequence should be followed:
1 Stop PLL1CLK4 clock by setting CLK4CR.CLKSTOP = 0
2 Write the new setting in CLK4CR.RATIO
3 Restart PLL1CLK4 clock by setting PLL1CLK4.CLKSTOP
= 1
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Clock functionality
CLOCKGEN.CPGBYPASS
-
CLOCKGEN.CPGBYPASS
Field
BYPASS
Bits
[0]
Operation
Read
Write
Hard reset
[1:31]
Operation
28
Read
Write
Hard reset
Size Volatile
1
Synopsis Type
No master control source for clocks 11 -
13
RW
0: PLL1 clocks 1, 2, 3 controlled by CPG.FRQCR
1= PLL1 clocks controlled as below
CLKGEN.CLK1CR controls clock 11
CLKGEN.CLK2CR controls clock 12
CLKGEN.CLK3CR controls clock 13
Returns current value
Updated
See product datasheet
—
Reserved
Reserved Res
Reserved
0: ignored, other values undefined
0
Table 74: CLOCKGEN.CPGBYPASS
147
ADCS 7153464G
STMicroelectronics
SH-4, ST40 System Architecture, Volume 1: System
148
PRELIMINARY DATA
Clock functionality
CLKGEN.PLL2_MUXCR
-
CLOCKGEN.PLL2_MUXCR
Field
MUXCTRL
Bits
[1:0]
Operation
Read
Write
Hard reset
[2:31] 28
Operation
Read
Write
Hard reset
Size Volatile
2
Synopsis
No Controls division ratio of clock 2M with respect to the output of PLL2
00: Ratio 1:8
01: Ratio 1:16
10: Ratio 1:21
11: Ratio 1:1
Returns current value
Updates current value
See product datasheet
— Reserved
Reserved
Reserved
0: ignored, other values undefined
0
Table 75: CLOCKGEN.PLL2_MUXCR
Type
RW
Res
STMicroelectronics
SH-4, ST40 System Architecture, Volume 1: System ADCS 7153464G
PRELIMINARY DATA
Clock functionality 149
CLKGEN.CLK1CR
-
Field
RATIO
CLKSTOP
CLOCKGEN.CLK1CR
Bits
[2:0]
Operation
Read
Write
Hard reset
[3]
Operation
1
Read
Write
Hard reset
[2:31] 28
Operation
Read
Write
Hard reset
Size Volatile
2
Synopsis Type
No clock ratio control when
CLKGEN.CPG_BYPASS active
RW
Controls the ratio of clock with respect to PLL1 division 2
000: 1:1 100: 1:4
001: 1:2
010: 1:3
011: 2:3
101: 1:6
110: 1:8
111: 1:8
Returns current value
Updated
See product datasheet
No Clock 11 enable override
1: clock 11 disabled
0: clock 11 enabled
Returns current value
Updated
RO
-
See product datasheet
Reserved
Reserved
Reserved
0: ignored, other values undefined
0
Res
Table 76: CLOCKGEN.CLK1CR
ADCS 7153464G
STMicroelectronics
SH-4, ST40 System Architecture, Volume 1: System
150
PRELIMINARY DATA
Clock functionality
CLKGEN.CLK2CR
-
Field
RATIO
CLKSTOP
CLOCKGEN.CLK2CR
Bits
[2:0]
Operation
Read
Write
Hard reset
[3]
Operation
1
Read
Write
Hard reset
[2:31] 28
Operation
Read
Write
Hard reset
Size Volatile
2
Synopsis Type
No clock ratio control when
CLKGEN.CPG_BYPASS active
RW
Controls the ratio of clock with respect to PLL1 division 2
000: 1:1 100: 1:4
001: 1:2
010: 1:3
011: 2:3
101: 1:6
110: 1:8
111: 1:8
Returns current value
Updated
See product datasheet
No Clock 12 enable override
1: clock 11 disabled
0: clock 11 enabled
Returns current value
Updated
RO
-
See product datasheet
Reserved
Reserved
Reserved
0: ignored, other values undefined
0
Res
Table 77: CLOCKGEN.CLK2CR
STMicroelectronics
SH-4, ST40 System Architecture, Volume 1: System ADCS 7153464G
PRELIMINARY DATA
Clock functionality 151
CLKGEN.CLK3CR
-
Field
RATIO
CLKSTOP
CLOCKGEN.CLK3CR
Bits
[2:0]
Operation
Read
Write
Hard reset
[3]
Operation
1
Read
Write
Hard reset
[2:31] 28
Operation
Read
Write
Hard reset
Size Volatile
2
Synopsis Type
No clock ratio control when
CLKGEN.CPG_BYPASS active
RW
Controls the ratio of clock with respect to PLL1 division 2
000: 1:1 100: 1:4
001: 1:2
010: 1:3
011: 2:3
101: 1:6
110: 1:8
111: 1:8
Returns current value
Updated
See product datasheet
No Clock 13 enable override
1: clock 11 disabled
0: clock 11 enabled
Returns current value
Updated
RO
-
See product datasheet
Reserved
Reserved
Reserved
0: ignored, other values undefined
0
Res
Table 78: CLOCKGEN.CLK3CR
ADCS 7153464G
STMicroelectronics
SH-4, ST40 System Architecture, Volume 1: System
152
PRELIMINARY DATA
CLKGEN.CLK_SELCR
CLOCKGEN.CLK_SELCR
Field Bits Size Volatile
-
EXTCLKSEL [7:0]
Operation
Read
8
Write
Hard reset
[2:31] 28
Operation
Read
Write
Hard reset
Synopsis
No Clock mux control
See product datasheet
Returns current value
-
Updates current value see product datasheet
Reserved
Reserved
Reserved
0: ignored, other values undefined
0
Table 79: CLOCKGEN.CLK_SELCR
Clock functionality
Type
RW
Res
STMicroelectronics
SH-4, ST40 System Architecture, Volume 1: System ADCS 7153464G
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