STMicroelectronics SPC58EE84E7 Datasheet

SPC58EEx, SPC58NEx

32-bit Power Architecture microcontroller for automotive ASIL-D applications

Datasheet

-

production data

FPBGA292 (17 x 17 x 1.8 mm)

Known Good Die eLQFP176 (24 x 24 x 1.4 mm)

Features

• AEC-Q100 qualified

• 32-bit Power Architecture VLE compliant CPU cores:

– Three main CPUs, dual issue, 32-bit CPU core complexes (e200z4), two of them having one checker core in lock-step

– Floating Point, End-to-End Error Correction

• 6576 KB (6288 KB code flash + 288 KB data flash) on-chip flash memory:

– supports read during program and erase operations, and multiple blocks allowing

EEPROM emulation

– Supports read while read between the two code Flash partitions.

• 608 KB on-chip general-purpose SRAM (in addition to 160 KB core local data RAM)

• 96-channel direct memory access controller

(eDMA)

• Comprehensive new generation ASIL-D safety concept:

– ASIL-D of ISO 26262

– FCCU for collection and reaction to failure notifications

– Memory Error Management Unit (MEMU) for collection and reporting of error events in memories

– Cyclic redundancy check (CRC) unit

• Dual-channel FlexRay controller

• Hardware Security Module (HSM)

• Junction temperature range -40 °C to 165 °C

• GTM 343 - Generic Timer Module:

– Intelligent complex timer module

– 144 channels (40 input and 104 output)

– 5 programmable fine grain multi-threaded cores

– 24-bit wide channels

• Enhanced analog-to-digital converter system with:

– 1 supervisor 12-bit SAR analog converter

– 4 separate fast 12-bit SAR analog converters

– 3 separate 10-bit SAR analog converters, one with STDBY mode support

– 6 separate 16-bit Sigma-Delta analog converters

• Communication interfaces:

– 18 LINFlexD modules

– 10 deserial serial peripheral interface

(DSPI) modules

– 8 MCAN interfaces with advanced shared memory scheme and ISO CAN-FD support, one supporting time-triggered controller area network (TTCAN)

• Two Ethernet controller 10/100 Mbps, compliant IEEE 802.3-2008

• Flexible Power Supply options:

– External Regulators (1.2 V core, 3.3 V–5 V

IO)

– Single internal SMPS regulator

(eLQFP176)

– Single internal Linear Regulator with external ballast (FPBGA292)

• Nexus development interface (NDI) per IEEE-

ISTO 5001-2003 standard, with some support for 2010 standard

• Boot assist Flash (BAF) supports factory programming using a serial bootload through the asynchronous CAN or LIN/UART

July 2019

This is information on a product in full production.

DS11646 Rev 4 1/154 www.st.com

Package eLQFP176

FPBGA292

KGD

SPC58EEx, SPC58NEx

Dual core

SPC58EE80E7

SPC58EE80C3

—

Table 1. Device summary

Part number

4 MB

Triple core

SPC58NE80E7

SPC58NE80C3

—

Dual core

SPC58EE84E7

SPC58EE84C3

—

6 MB

Triple core

SPC58NE84E7

SPC58NE84C3

SPC58NE84H0

2/154 DS11646 Rev 4

SPC58EEx, SPC58NEx

Table of contents

1

2

3

Table of contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1

Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3

Device feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.4

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.5

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Package pinouts, pad characteristics, and signal descriptions . . . . . 13

2.1

Pad dimensions/ KGD coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.3.1

Power domains and power up/down sequencing . . . . . . . . . . . . . . . . . 20

3.4

Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.5

Electromagnetic compatibility characteristics . . . . . . . . . . . . . . . . . . . . . . 23

3.6

Temperature profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.7

Device consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.8

I/O pad specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.8.1

3.8.2

3.8.3

I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

I/O pad current specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.9

Reset pad (PORST, ESR0) electrical characteristics . . . . . . . . . . . . . . . . 38

3.10

PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.10.1

PLL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.10.2

PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.11

Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.11.1

Crystal oscillator 40 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.11.2

Crystal Oscillator 32 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.11.3

RC oscillator 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.11.4

Low power RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

DS11646 Rev 4 3/154

5

Table of contents

4

5

SPC58EEx, SPC58NEx

3.12

ADC system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.12.1

ADC input description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.12.2

SAR ADC 12 bit electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.12.3

SAR ADC 10 bit electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.12.4

S/D ADC electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.12.5

SD ADC filter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.13

Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.14

LFAST pad electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.14.1

LFAST interface timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.14.2

LFAST and MSC/DSPI LVDS interface electrical characteristics . . . . . 69

3.14.3

LFAST PLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3.15

Aurora LVDS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

3.16

Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.16.1

Power management integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.16.2

Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.16.3

Voltage monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

3.17

Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

3.18

AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

3.18.1

Debug and calibration interface timing . . . . . . . . . . . . . . . . . . . . . . . . . 92

3.18.2

DSPI timing with CMOS and LVDS pads . . . . . . . . . . . . . . . . . . . . . . . . 99

3.18.3

Ethernet timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

3.18.4

FlexRay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

3.18.5

PSI5 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

3.18.6

CAN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

3.18.7

UART timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

3.18.8

I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

4.1

eLQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

4.2

FPBGA292 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

4.3

Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

4.3.1

4.3.2

4.3.3

LQFP176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

FPBGA292 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

General notes for specifications at maximum junction temperature . . 138

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

4/154 DS11646 Rev 4

SPC58EEx, SPC58NEx

6

Table of contents

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

DS11646 Rev 4 5/154

5

Introduction

1 Introduction

SPC58EEx, SPC58NEx

This document provides electrical specifications, pin assignments, and package diagrams for the SPC5x series of microcontroller units (MCUs). For functional characteristics, see the

SPC5x microcontroller reference manual.

1.2 Description

The SPC58xEx microcontroller is the first in a new family of devices superseding the SPC5x family. SPC58xEx builds on the legacy of the SPC5x family, while introducing new features coupled with higher throughput to provide substantial reduction of cost per feature and significant power and performance improvement (MIPS per mW).

6/154

Feature

SPC58 family

Local RAM

Single Precision Floating Point

SIMD (LSP)

VLE

Cache

Table 2. SPC58xEx feature summary

Description

40 nm

Computing Shell 0

Number of Cores

Number of checker cores up to 2 up to

16 KB Instruction

64 KB Data

Yes

No

Yes

8 KB Instruction

4 KB Data

Computing Shell 1

Number of Cores

Number of checker cores

Local RAM

Single Precision Floating Point

SIMD (LSP)

VLE

Cache

1 up to 1

16 KB Instruction

32 KB Data

Yes

Yes

Yes

8 KB Instruction

DS11646 Rev 4

SPC58EEx, SPC58NEx Introduction

Table 2. SPC58xEx feature summary (continued)

Feature Description

MPU

Security (HSM Module)

Semaphores

CRC Channels

Software Watchdog Timer (SWT)

Core Nexus Class

Event Processor

Run control Module

System SRAM

User Flash memory

Flash fetch accelerator

Security Flash memory

Flash Overlay RAM

Calibration Interface

DMA channels

DMA Nexus Class

LINFlexD

M_CAN supporting CAN-FD according to ISO 11898-1 2015

(instances supporting also TTCAN)

DSPI

Microsecond channel downlink

SENT bus

I2C

PSI5 bus

FlexRay

Ethernet

SIPI / LFAST Interprocessor bus

System Timers

GTM Timer

GTM RAM

Other

Yes up to 1

Yes

2 x 4

4

3+

4 x SCU

4 x PMC

Yes

608 KB (including 256 KB of standby RAM

(1)

) up to 6144 KB code / 256 KB data

2 x 2 x4 x 256-bit up to 144 KB code / 32 KB data

2 x 16 KB

64-bit IPS Slave

96

3

18

8 (1)

10

2

15

1

2

1 x Dual channel

2

High Speed

8 PIT channels

4 AUTOSAR® (STM)

RTC/API

40 Input Channels, 104 Output Channels

61 KB

DS11646 Rev 4 7/154

12

Introduction SPC58EEx, SPC58NEx

Table 2. SPC58xEx feature summary (continued)

Feature Description

Interrupt controller

ADC (SAR)

ADC (SD)

Temp. sensor

Self Test Controller

PLL

Integrated linear voltage regulator

Integrated switch mode voltage regulator (SMPS)

External Power Supplies

> 710 sources

8

6

Yes

Yes

Dual PLL with FM

Yes

(1)

Yes

(2)

Low Power Modes

3.3 V - 5 V, 1.2 V

Stop Mode

Halt Mode

Smart Standby with output controller, analog and digital

inputs (1)

Standby Mode

(1)

1. Except eLQFP176.

2. Except LFBGA292.

Figure 1

and Figure 2

show the top-level block diagrams.

8/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Introduction

Figure 1. Block diagram

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DS11646 Rev 4 9/154

12

Introduction

Figure 2. Periphery allocation

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10/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Introduction

1.5 Features

On-chip modules within SPC58xEx include the following features:

• main CPUs, dual issue, 32-bit CPU core complexes (e200z4), paired in lock-step.

– Power Architecture embedded specification compliance

– Instruction set enhancement allowing variable length encoding (VLE), encoding a mix of 16-bit and 32-bit instructions, for code size footprint reduction

– Single-precision floating point operations

– Lightweight signal processing auxiliary processing unit (LSP APU) instruction support for digital signal processing (DSP) on Core_2

– 16 KB Local instruction RAM and 64 KB local data RAM for Core_0 and Core_1,

16 KB Local instruction RAM and 32 KB local data RAM for Core_2

– 8 KB I-Cache and 4 KB D-Cache for Core_0 and Core_1, 8kB I-Cache for Core_2

• 6582 KB on-chip Flash

– Supports read during program and erase operations, and multiple blocks allowing

EEPROM emulation

– Supports read while read between the two code Flash partitions.

• 608 KB on-chip general-purpose SRAM (+ 160 KB data RAM included in the CPUs)

• Multi channel direct memory access controllers (eDMA paired in lock-step)

– One eDMA with 64 channels

– One eDMA with 32 channels

• One interrupt controller (INTC) in lock-step

• Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell

• Dual crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC

• Hardware security module (HSM) to provide robust integrity checking of Flash memory

• System integration unit lite (SIUL)

• Boot assist Flash (BAF) supports factory programming using a serial bootload through the asynchronous CAN or LIN/UART.

• GTM343 - generic timer module

– Intelligent complex timer module

– 144 channels (40 input and 104 output)

– 5 programmable fine grain multi-threaded cores

– 61 KB of dedicated RAM

– 24-bit wide channels

– Hardware support for engine control, motor control and safety related applications

• Enhanced analog-to-digital converter system with

– One supervisor 12-bit SAR analog converter

– Four separate fast 12-bit SAR analog converters

– Three separate 10-bit SAR analog converters, one with STDBY mode support

(except in eLQFP176 package)

– Six separate 16-bit Sigma-Delta analog converters

• Ten deserial serial peripheral interface (DSPI) modules

DS11646 Rev 4 11/154

12

Introduction SPC58EEx, SPC58NEx

• Eighteen LIN and UART communication interface (LINFlexD) modules

– LINFlexD_0 is a Master/Slave

– All others are Masters

• 8 MCAN interfaces with advanced shared memory scheme and ISO CAN-FD support, one supporting time-triggered controller area network (TTCAN)

• Dual-channel FlexRay controller

• Two ethernet controllers 10/100 Mbps, compliant IEEE 802.3-2008

– IEEE 1588-2008 Time stamping (internal 64-bit time stamp)

– IEEE 802.1AS and IEEE 802.1Qav (AVB-Feature)

– IEEE 802.1Q VLAN tag detection

– IPv4 and IPv6 checksum modules

• Flexible Power Supply options:

– External Regulators (1.2V core, 3.3V–5V IO)

– Single internal SMPS regulator (eLQFP176, KGD)

– Single internal Linear Regulator with external ballast (FPBGA292, KGD)

• Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with some support for 2010 standard.

• Device and board test support per Joint Test Action Group (JTAG) (IEEE 1149.1)

• Standby power domain with smart wake-up sequence (LFBGA292, KGD)

12/154 DS11646 Rev 4

SPC58EEx, SPC58NEx

2

Package pinouts, pad characteristics, and signal descriptions

Package pinouts, pad characteristics, and signal descriptions

Refer to the SPC58xEx IO_ Definition document.

It includes the following sections:

1.

Package pinouts a) Power supply and reference voltage pins a) Power supply and reference voltage pads

2.1 Pad dimensions/ KGD coordinates

For KDG information, please contact your local sales organization or distributor.

DS11646 Rev 4 13/154

13

Electrical characteristics SPC58EEx, SPC58NEx

3.1 Introduction

The present document contains the target Electrical Specification for the 40 nm family 32-bit

MCU SPC58xEx products.

In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” (Controller Characteristics) is included in the “Symbol” column.

In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol “SR” (System Requirement) is included in the

“Symbol” column.

The electrical parameters shown in this document are guaranteed by various methods. To

give the customer a better understanding, the classifications listed in Table 3 are used and

the parameters are tagged accordingly in the tables where appropriate.

Classification tag

P

C

T

D

Table 3. Parameter classifications

Tag description

Those parameters are guaranteed during production testing on each individual device.

NOTE: Parameters specified at junction temperature T

J

= 165 °C are tested at T

J

= 150 °C in production. Evaluation at higher temperature is performed during Design and Validation phases.

Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations.

Those parameters are achieved by design validation on a small sample size from typical devices.

Those parameters are derived mainly from simulations.

14/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

3.2 Absolute maximum ratings

Table 4 describes the maximum ratings for the device. Absolute maximum ratings are stress

ratings only, and functional operation at the maxima is not guaranteed. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Stress beyond the listed maxima, even momentarily, may affect device reliability or cause permanent damage to the device.

Table 4. Absolute maximum ratings

Symbol C Parameter Conditions

Min

Value

Typ Max

Unit

V

DD_LV

V

DD_LV_BD

SR D

SR D

Core voltage operating life range

(1)

Buddy device voltage operating life range

(2)

—

—

–0.3

–0.3

—

—

1.4

1.5

V

V

V

DD_HV_IO_MAIN

V

DD_HV_IO_JTAG

V

DD_HV_IO_FLEX

V

DD_HV_IO_BD

V

DD_HV_FLA

V

SS_HV_ADV

SR D

I/O supply voltage

(3)

— –0.3

–0.3

—

—

6.0

0.3

V

V

V

DD_HV_ADV

V

SS_HV_ADR_D

V

DD_HV_ADR_D

V

SS

-V

SS_HV_ADR_D

V

SS_HV_ADR_S

V

DD_HV_ADR_S

V

SS

-V

SS_HV_ADR_S

V

SS

-V

SS_HV_ADV

SR D

SR D

SR D

SR D

SR D

SR D

SR D

SR D

SR D

ADC ground voltage

ADC Supply voltage

(3)

SD ADC ground reference

SD ADC voltage reference

(3)

V

SS_HV_ADR_D differential voltage

SAR ADC ground reference

SAR ADC voltage reference

(3)

V

SS_HV_ADR_S differential voltage

V

SS_HV_ADV differential voltage

Reference to digital ground

Reference to

V

SS_HV_ADV

—

Reference to

V

SS_HV_ADR_D

—

—

Reference to

V

SS_HV_ADR_S

—

—

–0.3

–0.3

–0.3

–0.3

–0.3

–0.3

–0.3

–0.3

—

—

—

—

—

—

—

—

6.0

0.3

6.0

0.3

0.3

6.0

0.3

0.3

V

V

V

V

V

V

V

V

DS11646 Rev 4 15/154

17

Electrical characteristics

Symbol

V

IN

T

TRIN

I

INJ

T

STG

T

PAS

T

STORAGE

T

SDR

MSL

T

XRAY dose

SPC58EEx, SPC58NEx

Table 4. Absolute maximum ratings (continued)

C Parameter Conditions

SR

SR

SR

SR

SR

SR —

SR

SR

SR

D

D

T

T

C

T

T

T

I/O input voltage

range

(3)(4)

(5)

—

Relative to V ss

Relative to

V

DD_HV_IO

and

V

DD_HV_ADV

Digital Input pad transition time

(6)

Maximum DC injection current for each analog/digital

PAD

(7)

Maximum nonoperating

Storage temperature range

—

Maximum nonoperating temperature during passive lifetime

—

Maximum storage time, assembled part programmed in

ECU

No supply; storage temperature in range –40 °C to

60 °C

Maximum solder temperature Pbfree packaged

(9)

Moisture sensitivity level

(10)

—

—

—

—

Maximum cumulated

XRAY dose

Typical range for

X-rays source during inspection:80 ÷

130 KV; 20 ÷

50 μ A

Min

–0.3

–0.3

—

—

–5

–55

–55

—

—

—

—

Value

Typ

—

—

—

—

—

—

—

—

—

—

—

Max

6.0

—

0.3

1

5

125

150 (8)

20

260

3

1

Unit

V ms mA

°C

°C years

°C

— grey

16/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

1. V

DD_LV

: allowed 1.335 V - 1.400 V for 60 seconds cumulative time at the given temperature profile. Remaining time allowed

1.260 V - 1.335 V for 10 hours cumulative time at the given temperature profile. Remaining time as defined in Section 3.3:

Operating conditions . In the range [1.26-1.33] V and if the above-mentioned cumulative times are not exceeded, the device

functionality is granted and is expected to receive a flag by the internal HVD134 monitors to warn that the regulator (internal or external), providing the VDD_LV supply, exited the expected operating conditions. If the internal HVD134 monitors are disabled by the application, then an external voltage monitor with equivalent thresholds measured at the device pad, has to

be implemented. Please refer to Section 3.16.3: Voltage monitors

for the list of available internal monitors and to the

Reference Manual for the configurability of the monitors. In this range, the device may exceed the maximum consumptions reported in

Table 9: Device consumption

.

2. V

DD_LV_BD

: allowed 1.450 V - 1.500 V for 60 seconds cumulative time at the given temperature profile. Remaining time allowed 1.375 V - 1.450 V for 10 hours cumulative time at maximum T

Operating conditions

.

J

= 125 °C. Remaining time as defined in Section 3.3:

3. V

DD_HV

: allowed 5.5 V – 6.0 V for 60 seconds cumulative time at the given temperature profile, for 10 hours cumulative

time with the device in reset at the given temperature profile. Remaining time as defined in Section 3.3: Operating conditions

.

4. The maximum input voltage on an I/O pin tracks with the associated I/O supply maximum. For the injection current condition on a pin, the voltage will be equal to the supply plus the voltage drop across the internal ESD diode from I/O pin to supply. The diode voltage varies greatly across process and temperature, but a value of 0.3 V can be used for nominal calculations.

5. Relative value can be exceeded if design measures are taken to ensure injection current limitation (parameter IINJ).

6. This limitation applies to pads with digital input buffer enabled. If the digital input buffer is disabled, there are no maximum limits to the transition time.

7. The limits for the sum of all normal and injected currents on all pads within the same supply segment can be found in

Section 3.8.3: I/O pad current specifications .

8. 175°C are allowed for limited time. Mission profile with passive lifetime temperature >150°C have to be evaluated by ST to confirm that are granted by product qualification.

9. Solder profile per IPC/JEDEC J-STD-020D.

10. Moisture sensitivity per JDEC test method A112.

DS11646 Rev 4 17/154

17

Electrical characteristics SPC58EEx, SPC58NEx

Table 5 describes the operating conditions for the device, and for which all the specifications

in the data sheet are valid, except where explicitly noted. The device operating conditions must not be exceeded or the functionality of the device is not guaranteed.

Table 5. Operating conditions

Symbol C Parameter Conditions

Min

Value

(1)

Typ Max

Unit

F

SYS

(2)

T

J

T

J

T

A

V

DD_LV

SR P

SR C

SR

SR

SR

SR

P

P

P

P

Operating system clock frequency

(3)

Operating

Junction temperature

Operating

Junction temperature

Operating

Ambient temperature

Core supply voltage

(4)

Buddy core supply voltage

— —

Bare Die

Packaged

Devices

—

—

—

–40

–40

–40

1.14

(5)

1.20

—

—

—

—

1.20

—

180

165

150

125

1.26

(6) (7)

1.32

MHz

°C

°C

°C

V

V V

DD_LV_BD

V

DD_HV_IO_MAIN

V

DD_HV_IO_JTAG

V

DD_HV_IO_FLEX

V

DD_HV_FLA

V

DD_HV_IO_BD

V

DD_HV_ADV

SR P

IO supply voltage

—

—

3.0

3.0

(8)

—

—

5.5

5.5

V

V

V

SS_HV_ADV

-

V

SS

V

DD_HV_ADR_D

V

DD_HV_ADR_D

-

V

DD_HV_ADV

V

SS_HV_ADR_D

SR P

SR D

SR

SR D

SR

P

P

ADC supply voltage

ADC ground differential voltage

SD ADC supply reference voltage

SD ADC reference differential voltage

SD ADC ground reference voltage

—

—

—

—

–25

3.0

(8)

—

—

—

—

V

SS_HV_ADV

25

5.5

25 mV

V mV

V

18/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Symbol

V

SS_HV_ADR_D

-

V

SS_HV_ADV

V

DD_HV_ADR_S

V

DD_HV_ADR_S

-

V

DD_HV_ADV

V

SS_HV_ADR_S

V

SS_HV_ADR_S

V

SS_HV_ADV

-

V

RAMP_LV

V

RAMP_HV

V

IN

I

INJ1

I

INJ2

C

SR D

SR P

SR D

SR P

SR D

SR D

SR D

SR P

SR T

Table 5. Operating conditions (continued)

Value (1)

Parameter Conditions

Min Typ

V

SS_HV_ADR_D differential voltage

SAR ADC reference voltage

SAR ADC reference differential voltage

SAR ADC ground reference voltage

V

SS_HV_ADR_S differential voltage

Slew rate on core power supply pins

Slew rate on

HV power supply

I/O input voltage range

DC Injection current (per pin) without performance degradation

(10) (11)

(9)

V

V

—

—

—

—

—

DD_LV

DD_LV_BD

—

—

Digital pins and analog pins

–25

3.0

V

DD_HV_ADV

-10%

–25

—

—

0

–3.0

—

—

—

V

SS_HV_ADV

—

—

—

—

—

SR D

Dynamic

Injection current (per pin) with performance degradation

(11)

(12)

Digital pins and analog pins

–10 —

Max

25

5.5

25

25

20

100

5.5

3.0

10

1. The ranges in this table are design targets and actual data may vary in the given range.

2. The maximum number of PRAM wait states has to be configured accordingly to the system clock frequency. Refer to

Table 6

.

3. Maximum operating frequency is applicable to the cores and platform of the device. See the Clock Chapter in the

Microcontroller Reference Manual for more information on the clock limitations for the various IP blocks on the device.

4. Core voltage as measured on device pin to guarantee published silicon performance.

Unit mV

V mV

V mV

V/ms

V/ms

V mA mA

DS11646 Rev 4 19/154

21

Electrical characteristics SPC58EEx, SPC58NEx

5. In the range [1.14-1.08]V, the device functionality and specifications are granted and the device is expected to receive a flag by the internal LVD100 monitors to warn that the regulator (internal or external), providing the V

DD_LV

supply, exited the expected operating conditions. If the internal LVD100 monitors are disabled by the application, then an external voltage monitor with minimum threshold of V

DD_LV

(min) = 1.08 V measured at the device pad, has to be implemented. Refer to

Section 3.16.3: Voltage monitors for the list of available internal monitors and to the Reference Manual for the

configurability of the monitors.

6. Core voltage can exceed 1.26 V with the limitations provided in Section 3.2: Absolute maximum ratings

, provided that

HVD134_C monitor reset is disabled.

7. 1.260 V - 1.290 V range allowed periodically for supply with sinusoidal shape and average supply value below or equal to

1.236 V at the given temperature profile.

8. S/D ADC is functional in the range 3.0 V < V conversion is not guaranteed.

DD_HV_ADV

< 4.0 V and 3.0 V < V

DD_HV_ADR_D

< 4.0 V, but precision of

9. Full device lifetime. I/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits. See

Section 3.2: Absolute maximum ratings for maximum input current for reliability requirements.

10. The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pins is above the supply rail, current will be injected through the clamp diode to the supply rails. For external RC network calculation, assume typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature.

11. The limits for the sum of all normal and injected currents on all pads within the same supply segment can be found in

Section 3.8.3: I/O pad current specifications .

12. Positive and negative Dynamic current injection pulses are allowed up to this limit, with different specifications for I/O, ADC accuracy and analog input. See the dedicated chapters for the different specification limits. See the Absolute Maximum

Ratings table for maximum input current for reliability requirements. Refer to the following pulses definitions: Pulse1 (ISO

7637-2:2011), Pulse 2a(ISO 7637-2:2011 5.6.2), Pulse 3a (ISO 7637-2:2011 5.6.3), Pulse 3b (ISO 7637-2:2011 5.6.3).

Table 6. PRAM wait states configuration

PRAMC WS Clock Frequency (MHz)

1

0

< 180

< 120

domains power up/down sequencing

The following table shows the constraints and relationships for the different power domains.

Supply1 (on rows) can exceed Supply2 (on columns), only if the cell at the given row and column is reporting ‘ok’. This limitation is valid during power-up and power-down phases, as well as during normal device operation.

20/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Table 7. Device supply relation during power-up/power-down sequence

Supply2

V

DD_

LV

V

DD_HV_IO

_FLEX

V

DD_HV_IO

_JTAG

V

DD_HV_IO_

MAIN

V

DD_HV_FLA ok

V

DD_HV_

ADV

V

DD_HV

_ADR

V

DD_LV_BD

V

DD_HV_BD

V

DD_LV

(1)

V

DD_HV_IO_F

LEX

V

DD_HV_IO_J

TAG

V

DD_HV_IO_

MAIN

V

DD_HV_FLA

V

DD_HV_ADV ok ok ok ok ok ok ok ok ok ok ok ok not allowed not allowed not allowed ok ok ok ok ok ok ok ok ok ok ok ok ok ok ok ok ok ok ok

V

DD_HV_ADR ok ok ok not allowed not allowed ok ok

V

DD_LV_BD

V

DD_HV_BD ok ok ok ok ok ok ok ok ok ok ok ok ok ok

1. V and if V

can be higher than V

DD_HV

DD_HV

supplies only during power-up/down transient ramps, in case of external LV regulator

supply voltage level is lower than V

DD_LV

allowed max operating condition.

During power-up, all functional terminals are maintained in a known state as described in the device pinout Microsoft Excel file attached to the IO_Definition document.

DS11646 Rev 4 21/154

21

Electrical characteristics SPC58EEx, SPC58NEx

The following table describes the ESD ratings of the device:

• All ESD testing are in conformity with CDF-AEC-Q100 Stress Test Qualification for

Automotive Grade Integrated Circuits,

• Device failure is defined as: “If after exposure to ESD pulses, the device does not meet the device specification requirements, which include the complete DC parametric and functional testing at room temperature and hot temperature, maximum DC parametric variation within 10% of maximum specification”.

Parameter

ESD for Human Body Model (HBM) (1)

Table 8. ESD ratings

ESD for field induced Charged Device Model (CDM)

(2)

C

T

T

T

Conditions

All pins

All pins

Corner Pins

Value

2000

500

750

1. This parameter tested in conformity with ANSI/ESD STM5.1-2007 Electrostatic Discharge Sensitivity Testing.

2. This parameter tested in conformity with ANSI/ESD STM5.3-1990 Charged Device Model - Component Level.

Unit

V

V

V

22/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

EMC measurements at IC-level IEC standards are available from STMicroelectronics on request.

DS11646 Rev 4 23/154

23

Electrical characteristics SPC58EEx, SPC58NEx

The device is qualified in accordance to AEC-Q100 Grade1 requirements, such as HTOL

1,000 h and HTDR 1,000 hrs, T

J

= 150 °C.

Mission profile with junction Temperature higher than 150 °C and up to 165 °C have to be evaluated by ST to confirm to be granted by product qualification. Please contact your

STMicroelectronics Sales representative for validation.

24/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

I

DD_LKG

(2),(3)

I

DD_LV

(3)

I

DDHALT

(8)

I

DDSTOP

(9)

I

DD_LV_BD

I

DD_HV_BD

I

SPIKE dI

Symbol

I

DD_HV

I

DD_MAIN_CORE_AC

I

DD_CHKR_CORE_AC

I

DD_HSM_AC

I

DD_AMU_AC

C

Table 9. Device consumption

Parameter Conditions

CC

CC

CC

CC

CC

CC

CC

CC

CC

CC

CC

C

D

P

D

Leakage current on the

V

DD_LV

supply

P

P

T

T

T

T

T

T

P

D

T

Dynamic current on the V

DD_LV

supply, very high consumption profile

(4)

Total current on the

V

DD_HV

supply

(4)

Main Core dynamic current

(5)

Checker Core dynamic operating current

HSM platform dynamic operating current

(6)

AMU dynamic operating current

(7)

Dynamic current on the V

DD_LV

supply

+Total current on the

V

DD_HV

supply

Dynamic current on the V

DD_LV

supply

+Total current on the

V

DD_HV

supply

Buddy Device

Consumption on

V

DD_LV

supply

(10)

Buddy Device

V

Consumption on

DD_HV

supply

(10)

CC T

Maximum short term current spike

(11)

SR D

Current difference ratio to average current

(dI/avg(I))

(12)

T

T

T

J

T

J

J

J f

= 40 °C

= 120 °C

= 150 °C

= 165 °C f f f f

—

MAX

MAX

MAX

MAX

—

—

—

/2

MAX

T

J

= 150 °C

T

J

= 165 °C

< 20 µs observation window

20 µs observation window

—

—

—

—

—

—

—

—

—

—

—

Min

—

—

—

—

Value

(1)

Typ

—

—

—

—

Max

40

180

320

500

Unit mA

—

—

—

—

—

—

—

—

489 mA

30

20

97

50

20

110 180 mA

21

—

—

—

—

—

40

500

600 mA

130 mA

100 mA

20 mA mA mA mA mA mA

%

DS11646 Rev 4 25/154

26

Electrical characteristics SPC58EEx, SPC58NEx

Table 9. Device consumption (continued)

Value (1)

Symbol C Parameter Conditions Unit

Min Typ Max

I

I

SR

(13)

DDOFF

CC

CC

D

T

Current variation during power up/down

Power-off current on high voltage supply rails (15)

See footnote

V

DD_HV

(14)

= 2.5 V

—

100

—

—

200

— mA

µA

1. The ranges in this table are design targets and actual data may vary in the given range.

2. The leakage considered is the sum of core logic and RAM memories. The contribution of analog modules is not considered, and they are computed in the dynamic I

DD_LV

and I

DD_HV

parameters.

3. I

DD_LKG

(leakage current) and I

DD_LV

(dynamic current) are reported as separate parameters, to give an indication of the consumption (leakage+dynamic) is lower or equal to the sum of the maximum values provided (I

DD_LKG the software profile used.

+I

DD_LV

). The two parameters, measured separately, may exceed the maximum reported for each, depending on the operative conditions and

4. Use case: 3 x e200z4 @ 180 MHz with all locksteps on (main core + core0 + dma + irq), HSM @ 90 MHz, all IPs clock enabled, Flash access with prefetch disabled (Flash consumption includes parallel read and program/erase), all SARADC and SDADC in continuous conversion, DMA continuously triggered by ADC conversions, 7 CAN / 5 DSPI / 12 LINFlex /

FlexRay, GTM (3 TOM channels, 1 ATOM), FIRC, SIRC, FXOSC, PLL0-1 running. The switching activity estimated for dynamic consumption does not include I/O toggling, which is highly dependent on the application. Details of the software configuration are available separately. The total device consumption is I temperature.

DD_LV

+ I

DD_HV

+ I

DD_LKG

for the selected

5. Dynamic consumption of one core, including the dedicated I/D-caches and I/D-MEMS contribution.

6. Dynamic consumption of the HSM module, including the dedicated memories, during the execution of Electronic Code

Book crypto algorithm on 1 block of 16 byte of shared RAM.

7. Dynamic consumption of the AMU module standalone.

8. Flash in Low Power. Sysclk at 160 MHz, PLL0_PHI at 160 MHz, XTAL at 40 MHz, FIRC 16 MHz ON, RCOSC1M off.

FlexCAN: instances: 0, 1, 2, 3, 4, 5, 6, 7 ON (configured but no reception or transmission), Ethernet ON (configured but no reception or transmission), ADC ON (continuously converting). All others IPs clock-gated.

9. Sysclk = RC16 MHz, RC16 MHz ON, RC1 MHz ON, PLL OFF. All possible peripherals off and clock gated. Flash in power down mode.

10. Worst case usage (data trace, data overlay, full Aurora utilization). If Aurora and JTAGM/LFAST not used, VDD_LV_BD current is reduced by ~20mA.

11. Current spike may occur during normal operation that are above average current, valid for an application running and if the following conditions are unchanged: clock configuration, frequency and gating; peripherals activation and configuration; number of cores and checker-cores activation and configuration; no functional/destructive reset occurring; no mbist/lbist execution. An internal auxiliary and clamp regulator can be enabled, in order to support internal current variations. Please refer to the Power Management chapter for the details and the external component requirements.

12. Moving window, measured on application specific pattern, with a maximum of 100 mA for the worst case application.

13. This specification is the maximum value and is a boundary for the dl specification.

14. Condition1: For power on period from 0 V up to normal operation with reset asserted. Condition 2: From reset asserted until

PLL running free. Condition 3: Increasing PLL from free frequency to full frequency. Condition 4: reverse order for power down to 0 V. Internal schemes must be used by the application (example: frequency ramping feature enable) to ensure that incremental demands are made on the external power supply within the maximum value. Mbist/Lbist must be configured to avoid exceeding the maximum value.

15. I

DDOFF

is the minimum guaranteed consumption of the device during power-up. It can be used to correctly size power-off ballast in case of current injection during power-off state.

26/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

3.8 I/O pad specification

The following table describes the different pad type configurations.

Pad type

Table 10. I/O pad specification descriptions

Description

Weak configuration Provides a good compromise between transition time and low electromagnetic emission.

Medium configuration

Provides transition fast enough for the serial communication channels with controlled current to reduce electromagnetic emission.

Strong configuration Provides fast transition speed; used for fast interface.

Very strong configuration

Provides maximum speed and controlled symmetric behavior for rise and fall transition.

Used for fast interface including Ethernet and FlexRay interfaces requiring fine control of rising/falling edge jitter.

Differential configuration

Input only pads

Standby pads

A few pads provide differential capability providing very fast interface together with good

EMC performances.

These low input leakage pads are associated with the ADC channels.

Some pads are active during Standby. Low Power Pads input buffer can only be configured in TTL mode. When the pads are in Standby mode, the Pad-Keeper feature is activated: if the pad status is high, the weak pull-up resistor is automatically enabled; if the pad status is low, the weak pull-down resistor is automatically enabled. Please refer to the tables below in this chapter for the thresholds details and weak-pull currents.

Note: Each I/O pin on the device supports specific drive configurations. See the signal description table in the device reference manual for the available drive configurations for each I/O pin.

PMC_DIG_VSIO register has to be configured to select the voltage level (3.3 V or 5.0 V) for each IO segment.

Logic level is configurable in running mode while it is TTL not-configurable in STANDBY for

LP (low power) pads, so if a LP pad is used to wakeup from STANDBY, it should be configured as TTL also in running mode in order to prevent device wrong behavior in

STANDBY.

The following table provides input DC electrical characteristics, as described in

Figure 3 .

DS11646 Rev 4 27/154

38

Electrical characteristics SPC58EEx, SPC58NEx

Figure 3. I/O input electrical characteristics

V

DD

V

IH

V

IN

V

HYS

V

IL

V

INTERNAL

(SIUL register)

Symbol

In the following table, in case of current injection pulses on one pad under the conditions and limits described in I

INJ2

parameter in Section 3.3: Operating conditions

, other pads of the same supply segment will have a drift of 4 % above the maximum V il minimum V ih

limits. Similarly V hys

parameter will be decreased of 4 %.

and 4 % below the

Table 11. I/O input electrical characteristics

Value

C Parameter Conditions Unit

Min Typ Max

TTL

V ihttl

V ilttl

V hysttl

SR

SR

P

P

CC C

Input high level

TTL

Input low level

TTL

Input hysteresis

TTL

—

—

—

2

–0.3

0.3

—

—

—

V

DD_HV_IO

+ 0.3

0.8

—

V

V

V

V ihaut

(1)

V ilaut

(2)

V hysaut

(3)

SR

SR

P

P

CC C

Input high level

AUTO

Input low level

AUTO

Input hysteresis

AUTO

AUTOMOTIVE

V

DD_HV_IO

= 5.0 V ±

10%

V

DD_HV_IO

= 5.0 V ±

10%

V

DD_HV_IO

= 5.0 V ±

10%

CMOS

3.8

–0.3

0.5

—

—

—

V

DD_HV_IO

+ 0.3

2.2

—

V

V

V

V ihcmos

SR P

Input high level

CMOS

(1)

— 0.65 * V

DD

—

V

DD_HV_IO

+ 0.3

V

28/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Symbol C

Table 11. I/O input electrical characteristics (continued)

Value

Parameter Conditions

Min Typ

V ihcmos

BD SR T

Input high level

CMOS

Buddy Device, hysteresis on

Buddy Device, hysteresis off

0.65 *

V

DD_HV_IO

0.60 *

V

DD_HV_IO

—

—

V ilcmos

V hyscmos

SR P

CC C

Input low level

CMOS

Input hysteresis

CMOS

—

—

–0.3

0.10 * V

DD

—

—

COMMON

I

I

I

I

I

LKG

LKG

LKG

LKG

LKG

I

LKG

CC

CC

CC

CC

CC

CC

P

C

P

C

P

C

Pad input leakage

Pad input leakage

Pad input leakage

Pad input leakage

Pad input leakage

Pad input leakage

INPUT-ONLY pads

T

J

= 150 °C

INPUT-ONLY pads

T

J

= 165 °C

MEDIUM pads

T

J

= 150 °C

MEDIUM pads

T

J

= 165 °C

STRONG pads

T

J

= 150 °C

STRONG pads

T

J

= 165 °C

VERY STRONG pads,

T

J

= 150 °C

VERY STRONG pads,

T

J

= 165 °C

—

—

—

—

—

—

I

I

LKG

LKG

C

P1

CC

CC

CC

P

C

D

Pad input leakage

Pad input leakage

Pad capacitance

—

—

—

—

V

W

W drift

FI

NFI

CC

SR

SR

D

C

C

Input V il

/V ih temperature drift

Wakeup input filtered pulse

(4)

Wakeup input not filtered pulse

(4)

In a 1 ms period, with a temperature variation

<30 °C

—

—

—

—

400

1. Good approximation of the variation of the minimum value with supply is given by formula:

5 V range: V

IHAUT

= 0.69 × V

DD_HV_IO

; 3.3 V range: V

IHAUT

= 0.75 × V

DD_HV_IO

2. Good approximation of the variation of the maximum value with supply is given by formula:

5 V range: V

ILAUT

= 0.49 × V

DD_HV_IO

; 3.3 V range: V

ILAUT

= 0.35 × V

DD_HV_IO

3. Good approximation of the variation of the minimum value with supply is given by formula:

5 V and 3.3 V range: V

HYSAUT

= 0.11 × V

DD_HV_IO

—

—

—

—

—

—

—

—

—

—

—

—

Max

V

DD_HV_IO

+ 0.3

V

DD_HV_IO

+ 0.3

Unit

V

V

0.35 * V

DD

V

— V

100

20

— mV ns ns

1,000

1,500

1,000

2,000

10

200

270

360

500 nA nA nA nA pF nA nA nA nA

DS11646 Rev 4 29/154

38

Electrical characteristics SPC58EEx, SPC58NEx

4. In the range from W

FI

(max) to W

NFI

(min), pulses can be filtered or not filtered, according to operating temperature and voltage. Refer to the device pinout IO definition excel file for the list of pins supporting the wakeup filter feature.

Symbol

I

WPU

R

WPU

I

WPD

CC

CC

C

Table 12. I/O pull-up/pull-down electrical characteristics

Value

Parameter Conditions

Min Typ

T

P

CC D

T

P

Weak pull-up current absolute value

Weak Pull-up resistance

Weak pulldown current absolute value

V

IN

= 1.1 V

(1)

V

V

IN

= 0.69 *

DD_HV_IO

(2)

V

DD_HV_IO

= 5.0 V ±

10%

V

V

IN

= 0.69 *

DD_HV_IO

(1)

V

IN

= 0.9 V

(2)

—

15

33

—

15

—

—

—

—

—

R

WPD

CC D

Weak Pulldown resistance

V

DD_HV_IO

= 5.0 V ±

10%

29

1. Maximum current when forcing a change in the pin level opposite to the pull configuration.

2. Minimum current when keeping the same pin level state than the pull configuration.

—

Note:

3.8.2

Max

130

—

93

130

—

60

Unit

μ A

K Ω

μ A

K Ω

When the device enters into standby mode, the LP pads have the input buffer switched-on.

As a consequence, if the pad input voltage VIN is V

SS

<V

IN

<V

DD_HV

, an additional consumption can be measured in the VDD_HV domain. The highest consumption can be seen around mid-range (VIN ~=VDD_HV/2), 2-3mA depending on process, voltage and temperature.

This situation may occur if the PAD is used as a ADC input channel, and V

SS

<V

IN

<V

DD_HV

.

The applications should ensure that LP pads are always set to VDD_HV or VSS, to avoid the extra consumption. Please refer to the device pinout IO definition excel file to identify the low-power pads which also have an ADC function.

I/O output DC characteristics

Figure 4 provides description of output DC electrical characteristics.

30/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Figure 4. I/O output DC electrical characteristics definition

V

INTERNAL

(SIUL register)

V

HYS t

SKEW20-80

V out

90%

80%

20%

10% t

R20-80 t

R10-90 t

TR

(max) = MAX(t

R10-90

; t

F10-90

) t

TR

(min) = MIN(t

R10-90

; t

F10-90

) t

F20-80 t

F10-90 t

TR20-80

(max) = MAX(t

R20-80

; t

F20-80

) t

TR20-80

(min) = MIN(t

R20-80

; t

F20-80

) t

SKEW20-80 t

SKEW10-90

=

=

| t

| t

R20-80

-t

R10-90

-t

F20-80

|

F10-90

|

The following tables provide DC characteristics for bidirectional pads:

•

Table 13 provides output driver characteristics for I/O pads when in WEAK/SLOW

configuration.

•

Table 14 provides output driver characteristics for I/O pads when in MEDIUM

configuration.

•

Table 15 provides output driver characteristics for I/O pads when in STRONG/FAST

configuration.

•

Table 16 provides output driver characteristics for I/O pads when in VERY

STRONG/VERY FAST configuration.

10%/90% is the default condition for any parameter if not explicitly mentioned differently.

Note:

Symbol

V ol_W

V oh_W

C

CC D

CC D

Table 13. WEAK/SLOW I/O output characteristics

Value

Parameter Conditions

Min Typ

Output low voltage for Weak type PADs

Output high voltage for Weak type PADs

V

DD

I ol

= 0.5 mA

= 5.0 V ± 10%

V

DD

= 3.3 V ± 10%

V

Ioh = 0.5 mA

DD

= 5.0 V ± 10%

V

DD

= 3.3 V ± 10%

—

0.9*V

DD

—

—

Max

0.1*V

DD

—

Unit

V

V

DS11646 Rev 4 31/154

38

Electrical characteristics SPC58EEx, SPC58NEx

Symbol

R

_W

F max_W t

TR_W

I

DCMAX_W

Table 13. WEAK/SLOW I/O output characteristics (continued)

Value

C Parameter Conditions

Min Typ

380 —

CC P

CC T

CC T

| t

SKEW_W

| CC T

CC D

Output impedance for

Weak type PADs

V

DD

= 5.0 V ± 10%

V

DD

= 3.3 V ± 10%

Maximum output frequency for

Weak type PADs

Transition time output pin weak configuration,

10%-90%

CL = 25 pF

V

DD

V

DD

= 5.0 V ± 10%

= 3.3 V ± 10%

CL = 50 pF

V

DD

V

DD

= 5.0 V ± 10%

= 3.3 V ± 10 %

V

DD

V

DD

CL = 25 pF

= 5.0 V + 10%

= 3.3 V + 10%

CL = 50 pF

V

DD

V

DD

= 5.0 V ± 10 %

= 3.3 V ± 10 %

Difference between rise and fall time,

90%-10%

—

Maximum DC current

V

DD

V

DD

= 5.0 V ± 10%

= 3.3 V ± 10%

250

—

—

25

50

—

—

—

—

—

—

—

—

—

Max

1040

700

2

1

120

240

25

0.5

Unit

Ω

MHz

MHz ns ns

% mA

Symbol

V ol_M

V oh_M

R

_M

C

CC D

CC D

CC P

Table 14. MEDIUM I/O output characteristics

Value

Parameter Conditions

Min Typ

Output low voltage for

Medium type

PADs

Output high voltage for

Medium type

PADs

Output impedance for

Medium type

PADs

V

DD

I ol

= 2.0 mA

=5.0 V ± 10 %

V

DD

=3.3 V ± 10 %

V

DD

I oh

=2.0 mA

= 5.0 V ± 10%

V

DD

= 3.3 V ± 10%

V

DD

= 5.0 V ± 10%

V

DD

= 3.3 V ± 10%

—

0.9*V

DD

90

60

—

—

—

—

Max

0.1*V

DD

—

260

170

Unit

V

V

Ω

32/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Symbol

F max_M t

TR_M

I

DCMAX_M

C

Table 14. MEDIUM I/O output characteristics (continued)

Value

Parameter Conditions

Min Typ

CC T

CC T

| t

SKEW_M

| CC T

CC D

Maximum output frequency for

Medium type

PADs

Transition time output pin

MEDIUM configuration,

10%-90%

CL = 25 pF

V

DD

V

DD

= 5.0 V ± 10%

= 3.3 V ± 10%

CL = 50 pF

V

DD

V

DD

= 5.0 V ± 10 %

= 3.3 V ± 10 %

CL = 25 pF

V

DD

V

DD

= 5.0 V ± 10%

= 3.3 V ± 10%

CL = 50 pF

V

DD

V

DD

= 5.0 V ± 10%

= 3.3 V ± 10%

Difference between rise and fall time,

90%-10%

—

Maximum DC current

V

DD

V

DD

= 5.0 V ± 10%

= 3.3 V ± 10%

—

—

8

12

—

—

—

—

—

—

—

—

Max

12

6

30

60

25

2

Unit

MHz

MHz ns ns

% mA

V ol_S

V oh_S

Symbol

R

_S

CC D

CC D

C

CC P

Table 15. STRONG/FAST I/O output characteristics

Value

Parameter Conditions

Min Typ

Output low voltage for

Strong type

PADs

Output high voltage for

Strong type

PADs

Output impedance for

Strong type

PADs

V

DD

I ol

= 8.0 mA

= 5.0 V ± 10%

V

DD

I ol

= 5.5 mA

=3 .3 V ± 10%

V

DD

I oh

= 8.0 mA

= 5.0 V ± 10%

V

DD

I oh

= 5.5 mA

= 3.3 V ± 10%

V

DD

= 5.0 V ± 10%

V

DD

= 3.3 V ± 10%

—

—

0.9*V

DD

0.85*V

DD

20

28

—

—

—

—

—

—

Max

0.1*V

DD

—

V

0.15*V

DD

V

V

Unit

— V

65

90

Ω

DS11646 Rev 4 33/154

38

Electrical characteristics SPC58EEx, SPC58NEx

Symbol

F max_S t

TR_S

I

DCMAX_S

Table 15. STRONG/FAST I/O output characteristics (continued)

Value

C Parameter Conditions

Min Typ

CC T

CC T

CC D

| t

SKEW_S

| CC T

Maximum output frequency for

Strong type

PADs

Transition time output pin

STRONG configuration,

10%-90%

Maximum DC current

CL = 25 pF

V

DD

=5.0 V ± 10%

CL = 50 pF

V

DD

=5.0 V ± 10%

CL = 25 pF

V

DD

= 3.3 V ± 10%

CL = 50 pF

V

DD

= 3.3 V ± 10%

CL = 25 pF

V

DD

= 5.0 V ± 10%

CL = 50 pF

V

DD

= 5.0 V ± 10%

CL = 25 pF

V

DD

= 3.3 V ± 10%

CL = 50 pF

V

DD

= 3.3 V ± 10%

V

DD

= 5 V ± 10%

V

DD

= 3.3 V ± 10%

Difference between rise and fall time,

90%-10%

—

—

—

—

—

3

5

1.5

2.5

—

—

—

—

—

—

—

—

—

—

—

—

—

—

Max

50

25

25

12.5

10

16

15

25

26

8

5.5

Unit mA

%

MHz

MHz

MHz

MHz ns

Symbol

V ol_V

V oh_V

R

_V

Table 16. VERY STRONG/VERY FAST I/O output characteristics

Value

C Parameter Conditions

Min Typ

CC D

CC D

CC P

Output low voltage for Very

Strong type

PADs

Output high voltage for Very

Strong type

PADs

V

DD

I ol

= 9.0 mA

=5.0 V ± 10%

V

DD

I ol

= 9.0 mA

=3.3 V ± 10%

V

DD

I oh

= 9.0 mA

= 5.0 V ± 10%

V

DD

I oh

= 9.0 mA

= 3.3 V ± 10%

V

DD

= 5.0 V ± 10% Output impedance for

Very Strong type

PADs

V

DD

= 3.3 V ± 10%

—

—

0.9*V

DD

0.85*V

DD

20

18

—

—

—

—

—

—

Max

0.1*V

DD

0.15*V

DD

—

—

60

50

Unit

V

V

V

V

Ω

34/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Table 16. VERY STRONG/VERY FAST I/O output characteristics (continued)

Value

Symbol C Parameter Conditions

Min Typ Max

F max_V t

TR_V t

TR20-80_V t

TRTTL_V

Σ t

TR20-80_V

| t

SKEW_V

| CC T

I

DCMAX_V

CC T

CC T

CC T

CC T

CC T

CC D

Maximum output frequency for

Very Strong type

PADs

10–90% threshold transition time output pin VERY

STRONG configuration

CL = 25 pF

V

DD

= 5.0 V ± 10%

CL = 50 pF

V

DD

= 5.0 V ± 10%

CL = 25 pF

V

DD

= 3.3 V ± 10%

CL = 50 pF

V

DD

= 3.3 V ± 10%

CL = 25 pF

V

DD

= 5.0 V ± 10%

CL = 50 pF

V

DD

= 5.0 V ± 10%

CL = 25 pF

V

DD

= 3.3 V ± 10%

CL = 50 pF

V

DD

= 3.3 V ± 10%

CL = 25 pF

V

DD

= 5.0 V ± 10%

20–80% threshold transition time output pin VERY

STRONG configuration

(Flexray

Standard)

TTL threshold transition time for output pin in

VERY STRONG configuration

(Ethernet standard)

V

DD

V

DD

CL = 15 pF

= 3.3 V ± 10%

CL = 25 pF

= 3.3 V ± 10%

Sum of transition time

20–80% output pin VERY

STRONG configuration

Difference between rise and fall delay

CL = 25 pF

V

DD

= 5.0 V ± 10%

V

DD

V

DD

CL = 15 pF

= 3.3 V ± 10%

CL = 25 pF

= 5.0 V ± 10%

Maximum DC current

V

DD

V

DD

= 5.0 V±10%

= 3.3 V ± 10%

—

—

—

—

1

3

1.5

3

0.8

1

0.88

—

—

0

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

50

25

50

25

6

12

6

11

4.5

4.5

5

9

9

1.2

9

Unit ns ns ns ns ns mA

MHz

MHz

MHz

MHz

DS11646 Rev 4 35/154

38

Electrical characteristics SPC58EEx, SPC58NEx

3.8.3

Note:

Symbol

I/O pad current specifications

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a V

DD

/V

SS

supply pair as described in the device pinout Microsoft Excel file attached to the IO_Definition document.

Table 17 provides I/O consumption figures.

In order to ensure device reliability, the average current of the I/O on a single segment should remain below the I

RMSSEG

maximum value.

In order to ensure device functionality, the sum of the dynamic and static current of the I/O on a single segment should remain below the I

DYNSEG

maximum value.

Pad mapping on each segment can be optimized using the pad usage information provided on the I/O Signal Description table.

In order to ensure correct functionality for SENT, the sum of all pad usage ratio within the

SENT segment should remain below 10%.

Table 17. I/O consumption

C Parameter Conditions

Value

(1)

Min Typ Max

Unit

I

RMSSEG

I

RMS_W

I

RMS_M

SR D

CC D

CC D

Average consumption

(2)

Sum of all the DC I/O current within a supply segment

—

RMS I/O current for WEAK configuration

RMS I/O current for MEDIUM configuration

C

L

V

DD

= 25 pF, 2 MHz,

= 5.0 V ± 10 %

C

L

V

DD

= 50 pF, 1 MHz,

= 5.0 V ± 10 %

C

L

V

DD

= 25 pF, 2 MHz,

= 3.3 V ± 10 %

C

L

= 25 pF, 1 MHz,

V

DD

= 3.3 V ± 10%

C

L

= 25 pF, 12 MHz,

V

DD

= 5.0 V ± 10%

C

L

= 50 pF, 6 MHz,

V

DD

= 5.0 V ± 10%

C

L

= 25 pF, 12 MHz,

V

DD

= 3.3 V ± 10%

C

L

= 25 pF, 6 MHz,

V

DD

= 3.3 V ± 10%

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

80 mA

1.1

1.1

1.0

1.0

5.5

5.5

4.2

4.2

mA mA

36/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Table 17. I/O consumption (continued)

Symbol C Parameter Conditions

I

I

RMS_S

RMS_V

I

DYN_SEG

I

I

DYN_W

DYN_M

CC D

CC D

SR D

CC D

CC D

RMS I/O current for STRONG configuration

C

L

= 25 pF, 50 MHz,

V

DD

= 5.0 V ± 10%

C

L

= 50 pF, 25 MHz,

V

DD

= 5.0 V ± 10%

C

L

= 25 pF, 25 MHz,

V

DD

= 3.3 V ± 10%

C

L

= 25 pF, 12.5 MHz,

V

DD

= 3.3 V ± 10%

C

L

= 25 pF, 50 MHz,

V

DD

= 5.0 V ± 10%

C

L

= 50 pF, 25 MHz,

V

DD

= 5.0 V ± 10%

RMS I/O current for VERY

STRONG configuration

C

L

= 25 pF, 50 MHz,

V

DD

= 3.3 V ± 10%

C

L

= 25 pF, 25 MHz,

V

DD

= 3.3 V ± 10%

Dynamic consumption

(3)

Sum of all the dynamic and DC

I/O current within a supply segment

Dynamic I/O current for WEAK configuration

Dynamic I/O current for

MEDIUM configuration

V

DD

= 5.0 V ± 10%

V

DD

= 3.3 V ± 10%

C

L

= 25 pF, V

DD

10%

= 5.0 V ±

C

L

= 50 pF, V

DD

10%

= 5.0 V ±

C

L

= 25 pF, V

DD

10%

= 3.3 V ±

C

L

= 50 pF, V

DD

10%

= 3.3 V ±

C

L

= 25 pF, V

DD

10%

= 5.0 V ±

C

L

= 50 pF, V

DD

10%

= 5.0 V ±

C

L

= 25 pF, V

DD

10%

= 3.3 V ±

C

L

= 50 pF, V

DD

10%

= 3.3 V ±

Value (1)

Min Typ Max

Unit

— — 21

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

21

10

10

23

23

16

16

— 195

— 150

—

—

—

—

—

—

—

—

16.7

16.8

12.9

12.9

18.2

18.4

14.3

16.4

mA mA mA mA mA

DS11646 Rev 4 37/154

38

Electrical characteristics SPC58EEx, SPC58NEx

Table 17. I/O consumption (continued)

Value (1)

Symbol C Parameter Conditions Unit

Min Typ Max

I

DYN_S

CC D

Dynamic I/O current for

STRONG configuration

C

L

= 25 pF, V

DD

10%

= 5.0 V ±

C

L

= 50 pF, V

DD

10%

= 5.0 V ±

C

L

= 25 pF, V

DD

10%

= 3.3 V ±

C

L

= 50 pF, V

DD

10%

= 3.3 V ±

C

L

= 25 pF, V

DD

10%

= 5.0 V ±

C

L

= 50 pF, V

DD

10%

= 5.0 V ±

—

—

—

—

—

—

—

—

—

—

—

—

57

63.5

31

33.5

62

70 mA

I

DYN_V

CC D

Dynamic I/O current for VERY

STRONG configuration

C

L

= 25 pF, V

DD

10%

= 3.3 V ±

C

L

= 50 pF, V

DD

10%

= 3.3 V ±

—

—

—

—

52

55

1. I/O current consumption specifications for the 4.5 V

VSIO[VSIO_xx] = 0 for 3.0 V ≤ V

DD_HV_IO

≤ 3.6 V.

≤ V

DD_HV_IO

≤ 5.5 V range are valid for VSIO_[VSIO_xx] = 1, and

2. Average consumption in one pad toggling cycle.

3. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition. When possible (timed output) it is recommended to delay transition between pads by few cycles to reduce noise and consumption.

mA

38/154 DS11646 Rev 4

SPC58EEx, SPC58NEx

3.9

Electrical characteristics

Reset pad (PORST, ESR0) electrical characteristics

The device implements dedicated bidirectional reset pins as below specified. PORST pin does not require active control. It is possible to implement an external pull-up to ensure correct reset exit sequence. Recommended value is 4.7 K Ω .

Figure 5. Startup Reset requirements

V

DD

V

DD_POR

PORST

V

IH

V

IL

PORST undriven device reset by internal power-on reset

PORST driven low by internal power-on reset device start-up phase device reset forced by external circuitry

Figure 6 describes device behavior depending on supply signal on PORST:

1.

PORST low pulse has too low amplitude: it is filtered by input buffer hysteresis. Device remains in current state.

2. PORST low pulse has too short duration: it is filtered by low pass filter. Device remains in current state.

3. PORST low pulse is generating a reset: a) PORST low but initially filtered during at least WFRST. Device remains initially in current state.

b) PORST potentially filtered until WNFRST. Device state is unknown. It may either be reset or remains in current state depending on extra condition (temperature, voltage, device).

c) PORST asserted for longer than WNFRST. Device is under reset.

DS11646 Rev 4 39/154

41

Electrical characteristics

Figure 6. Noise filtering on reset signal

SPC58EEx, SPC58NEx

V

PORST,

V

ESR0

V

DD

V

IH

V

IL

V

HYS internal reset filtered by

hysteresis

1 filtered by

lowpass filter

W

FRST

2 filtered by

lowpass filter unknown reset state device under hardware reset

W

FRST

W

NFRST

3a 3b 3c

Symbol

V

IHRES

V

ILRES

V

HYSRES

V

DD_POR

C

Table 18. Reset PAD electrical characteristics

Parameter Conditions

SR

SR

P

P

Input high level

TTL

Input low level

TTL

CC C Input hysteresis

TTL

CC D Minimum supply for strong pulldown activation

V

DD_HV

V

DD_HV

= 5.0 V ± 10%

= 3.3 V ± 10%

V

DD_HV

= 5.0 V ± 10%

V

DD_HV

= 3.3 V ± 10%

V

DD_HV

= 5.0 V ± 10%

V

DD_HV

= 3.3 V ± 10%

V

DD_HV

= 5.0 V ± 10%

V

DD_HV

= 3.3 V ± 10%

Min

2

-0.3

-0.3

0.3

0.2

—

—

Value

Typ

—

—

—

—

—

—

—

Max

V

DD_HV_IO

+0.3

0.8

0.6

—

—

1.6

1.05

Unit

V

V

V

V

40/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Symbol C

Table 18. Reset PAD electrical characteristics (continued)

Value

Parameter Conditions

Min Typ

Unit

Max

I

I

I

OL_R

WPU

WPD

CC

CC

P

P

P

P

P

P

P

P

Strong pull-down current

(1)

Weak pull-up current absolute value

CC P Weak pull-down current absolute value

V

DD_HV

= 5.0 V ± 10%

V

DD_HV

= 3.3 V ± 10%

V

IN

V

DD_HV

= 1.1 V

(2)

= 5.0 V ± 10%

V

V

IN

DD_HV

= 1.1 V

= 3.3 V ± 10%

V

V

IN

= 0.69 *

DD_HV_IO

(3)

V

DD_HV

= 5.0 V ± 10%

V

V

IN

= 0.69 * V

DD_HV_IO

DD_HV

= 3.3 V ± 10%

V

V

IN

= 0.69 *

DD_HV_IO

(2)

V

DD_HV

= 5.0 V ± 10%

V

V

IN

= 0.69 *

DD_HV_IO

(2)

V

DD_HV

= 3.3 V ± 10%

V

V

IN

DD_HV

= 0.9 V

= 5.0 V ± 10%

V

IN

= 0.9 V

V

DD_HVDD_HV

± 10%

= 3.3 V

12

8

—

—

15

15

—

—

15

15

—

—

—

—

—

—

—

—

—

—

—

—

130

70

—

—

130

80

—

— mA

μ

μ

A

A

W

W

FRST

NFRST

CC

CC

P

P

P

P

Input filtered pulse

Input not filtered pulse

V

DD_HV

= 5.0 V ± 10%

V

DD_HV

= 3.3 V ± 10%

V

DD_HV

= 5.0 V ± 10%

V

DD_HV

= 3.3 V ± 10%

—

—

2000

3000

—

—

—

—

500

600

—

— ns ns

1. I ol_r

applies to PORST: Strong Pull-down is active on PHASE0 for PORST. Refer to the device pinout IO definition excel file for details regarding pin usage.

2. Maximum current when forcing a change in the pin level opposite to the pull configuration.

3. Minimum current when keeping the same pin level state than the pull configuration.

PAD

Table 19. Reset Pad state during power-up and reset

POWER-UP State RESET state DEFAULT state

(1)

STANDBY state

PORST

ESR0

Strong pull-down

Strong pull-down

Weak pull-down

Strong pull-down

Weak pull-down

Weak pull-up

Weak pull-up

Weak pull-up

1. Before SW Configuration. Please refer to the Device Reference Manual, Reset Generation Module (MC_RGM) Functional

Description chapter for the details of the power-up phases.

DS11646 Rev 4 41/154

41

Electrical characteristics SPC58EEx, SPC58NEx

3.10 PLLs

Two phase-locked loop (PLL) modules are implemented to generate system and auxiliary clocks on the device.

Figure 7 depicts the integration of the two PLLs. Please, refer to device Reference Manual

for more detailed schematic.

Figure 7. PLLs integration

IRCOSC

XOSC

PLL0

PLL0_PHI

PLL0_PHI1

PLL1_PHI

PLL1

3.10.1 PLL0

Table 20. PLL0 electrical characteristics t f f f f

Δ f

Symbol

PLL0IN

PLL0IN

INFIN

PLL0VCO

PLL0PHI0

PLL0PHI1

PLL0LOCK

|Δ

PLL0PHI0SPJ

|

(4)

C Parameter Conditions

SR — PLL0 input clock

(1)

SR —

PLL0 input clock duty

cycle

(1)

SR —

PLL0 PFD (Phase

Frequency Detector) input clock frequency

CC P PLL0 VCO frequency

CC D PLL0 output frequency

CC D PLL0 output clock PHI1

CC P PLL0 lock time

CC T

PLL0_PHI0 single period jitter f

PLL0IN

= 20 MHz

(resonator)

—

—

—

—

—

—

— f

PLL0PHI0

= 400 MHz,

6-sigma pk-pk

Min

8

40

8

600

4.762

20

—

—

Value

Typ

—

Max

44

—

—

—

60

20

1400

— F

SYS

(2)

—

—

—

175

(3)

100

200

Unit

MHz

%

MHz

MHz

MHz

MHz

µs ps

42/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Table 20. PLL0 electrical characteristics (continued)

Value

Symbol C Parameter Conditions Unit

Min Typ Max

|Δ

PLL0PHI1SPJ

|

(4)

CC D

PLL0_PHI1 single period jitter f

PLL0IN

= 20 MHz

(resonator) f

PLL0PHI1

= 40 MHz,

6-sigma pk-pk

— — 300

(5) ps

Δ

PLL0LTJ

(4)

CC D

PLL0 output long term jitter

(5)

f

PLL0IN

= 20 MHz

(resonator), VCO frequency = 800 MHz

10 periods accumulated jitter

(80 MHz equivalent frequency), 6-sigma pk-pk

16 periods accumulated jitter

(50 MHz equivalent frequency), 6-sigma pk-pk

—

—

—

—

±250

±300 ps ps long term jitter

(< 1 MHz equivalent frequency), 6-sigma pk-pk)

— — ±500 ps

I

PLL0

CC D PLL0 consumption FINE LOCK state — — 6 mA

1. PLL0IN clock retrieved directly from either internal RCOSC or external FXOSC clock. Input characteristics are granted when using internal RCOSC or external oscillator is used in functional mode.

2. Please refer to Section 3.3: Operating conditions

for the maximum operating frequency.

3. If the PLL0_PHI1 is used as an input for PLL1, then the PLL0_PHI1 frequency shall obey the maximum input frequency limit set for PLL1 (87.5 MHz, according to

Table 21

).

4. Jitter values reported in this table refer to the internal jitter, and do not include the contribution of the divider and the path to the output CLKOUT pin.

5. V filtered.

noise due to application in the range V

DD_LV

= 1.20 V±5%, with frequency below PLL bandwidth (40 kHz) will be

DS11646 Rev 4 43/154

44

Electrical characteristics SPC58EEx, SPC58NEx

3.10.2 PLL1

PLL1 is a frequency modulated PLL with Spread Spectrum Clock Generation (SSCG) support.

Table 21. PLL1 electrical characteristics

Value

Symbol C Parameter Conditions Unit

Min Typ Max f

Δ f

PLL1IN

PLL1IN

INFIN

SR — PLL1 input clock

(1)

SR —

PLL1 input clock duty

cycle

(1)

SR —

PLL1 PFD (Phase

Frequency Detector) input clock frequency

—

—

—

37.5

35

37.5

—

—

87.5

65

87.5

MHz

%

MHz f

PLL1VCO f

PLL1PHI0 t

PLL1LOCK

CC

CC

P

D

PLL1 VCO frequency

PLL1 output clock PHI0

—

—

600

4.762

—

—

1400

F

SYS

(2)

50

MHz

MHz f

PLL1MOD

CC

CC

P PLL1 lock time

T

PLL1 modulation frequency

—

—

—

—

—

— 250

µs kHz

|Δ

|δ

PLL1MOD

|

|

CC

CC

T

T

PLL1 modulation depth

(when enabled)

PLL1_PHI0 single period peak to peak jitter

Center spread

Down spread f

PLL1PHI0

=

(3)

200 MHz, 6-sigma

0.25

0.5

—

—

—

—

2

4

500

(5)

%

% ps

I

PLL1

CC D PLL1 consumption FINE LOCK state — — 5 mA

1. PLL1IN clock retrieved directly from either internal PLL0 or external FXOSC clock. Input characteristics are granted when using internal PPL0 or external oscillator is used in functional mode.

2. Please refer to Section 3.3: Operating conditions

for the maximum operating frequency.

3. The device maximum operating frequency F

SYS

(max) includes the frequency modulation. If center modulation is selected, the FSYS must be below the maximum by MD (Modulation Depth Percentage), such that FSYS(max)=FSYS(1+MD%).

Please refer to the Reference Manual for the PLL programming details.

4. Jitter values reported in this table refer to the internal jitter, and do not include the contribution of the divider and the path to the output CLKOUT pin.

5. 1.25 V±5%, application noise below 40 kHz at V

DD_LV

pin - no frequency modulation.

44/154 DS11646 Rev 4

SPC58EEx, SPC58NEx

3.11 Oscillators

Electrical characteristics

Symbol f

XTAL t cst t rec

V

IHEXT

V

ILEXT

C

S_EXTAL

C

S_XTAL g m

V

EXTAL

Table 22. External 40 MHz oscillator electrical specifications

Value

C Parameter Conditions

CC D Crystal Frequency

Range

(1)

—

CC T Crystal start-up time

(3),(4)

CC D Crystal recovery time

(5)

CC D EXTAL input high voltage

(6)

(External

Reference)

CC D

CC D

EXTAL input low

voltage

(6)

(External

Reference)

Total on-chip stray capacitance on EXTAL pin

(7)

CC D

CC P

Total on-chip stray capacitance on XTAL pin

(7)

Oscillator

Transconductance

V

REF

V

REF

T

J

= 150 °C

T

J

= 165 °C

—

= 0.29 * V

= 0.29 * V

—

—

DD_HV_IO_JTAG

DD_HV_IO_JTAG

D

D

P

D

D

D

P

CC D Oscillation Amplitude on the EXTAL pin after startup (8) f

XTAL

= 4 − 8 MHz freq_sel[2:0] = 000 f

XTAL

= 5 - 10 MHz freq_sel[2:0] = 001 f

XTAL

= 10 − 15 MHz freq_sel[2:0] = 010 f

XTAL

= 15 - 20 MHz freq_sel[2:0] = 011 f

XTAL

= 20 - 25 MHz freq_sel[2:0] = 100 f

XTAL

= 25 − 30 MHz freq_sel[2:0] = 101 f

XTAL

= 30 - 35 MHz freq_sel[2:0] = 110 f

XTAL

= 35 - 40 MHz freq_sel[2:0] = 111

T

J

= –40 °C to 150 °C

T

J

= 150 °C to 165 °C

Min

4 (2)

>8

>20

—

—

—

V

REF

0.75

+

—

3

3

3.9

5

8.6

14.4

21.2

27

33.5

33.5

0.5

0.5

Max

5

6

0.5

—

8

20

40

V

REF

0.75

-

7

7

13.6

17.5

29.3

48

69

86

115

115

1.8

1.9

Unit

MHz ms ms

V

V pF pF mA/V

V

DS11646 Rev 4 45/154

48

Electrical characteristics SPC58EEx, SPC58NEx

Symbol

Table 22. External 40 MHz oscillator electrical specifications (continued)

Value

C Parameter Conditions

Min Max

Unit

V

I

HYS

XTAL

CC

CC

D

D

Comparator Hysteresis

XTAL current

(8),(9)

T

J

= –40 °C to 150 °C

T

J

= 150 °C to 165 °C

T

J

= –40 °C to 150 °C

T

J

= 150 °C to 165 °C

0.1

0.1

—

—

1.0

1.1

14

15

V mA

1. The range is selectable by UTEST miscellaneous DCF client XOSC_FREQ_SEL.

2. The XTAL frequency, if used to feed the PPL0 (or PLL1), shall obey the minimum input frequency limit set for PLL0 (or

PLL1).

3. This value is determined by the crystal manufacturer and board design, and it can potentially be higher than the maximum provided.

4. Proper PC board layout procedures must be followed to achieve specifications.

5. Crystal recovery time is the time for the oscillator to settle to the correct frequency after adjustment of the integrated load capacitor value.

6. Applies to an external clock input and not to crystal mode.

7. See crystal manufacturer’s specification for recommended load capacitor (C

L

) values.The external oscillator requires external load capacitors when operating from 8 MHz to 16 MHz. Account for on-chip stray capacitance (C /C

S_XTAL

) and PCB capacitance when selecting a load capacitor value. When operating at 20 MHz/40 MHz, the integrated load capacitor value is selected via S/W to match the crystal manufacturer’s specification, while accounting for on-chip and PCB capacitance.

8. Amplitude on the EXTAL pin after startup is determined by the ALC block, that is the Automatic Level Control Circuit. The function of the ALC is to provide high drive current during oscillator startup, but reduce current after oscillation in order to reduce power, distortion, and RFI, and to avoid over driving the crystal. The operating point of the ALC is dependent on the crystal value and loading conditions.

9. I

XTAL

is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. This is the maximum current during startup of the oscillator.

Symbol f sxosc g msxosc

V sxosc

I sxoosc

T sxosc

Table 23. 32 kHz External Slow Oscillator electrical specifications

Value

C Parameter Conditions

Min Typ

SR T — — 32768

CC P

CC T

CC D

CC T

Slow external crystal oscillator frequency

Slow external crystal oscillator transconductance

Oscillation

Amplitude

Oscillator consumption

Start up time

—

—

—

—

9.5

0.5

—

—

—

—

—

—

Max

—

32

1.7

9

2

Unit

Hz

µA/V

V

µA s

46/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Symbol

Table 24. Internal RC oscillator electrical specifications

Value

C Parameter Conditions

Min Typ

Unit

Max

δ f

δ

T f f

δ

Target var_noT f var_T var_SW start_noT

T start_T

CC D

CC P

CC

CC

CC

T

T

T

IRC target frequency

IRC frequency variation without temperature compensation

IRC frequency variation with temperature compensation

IRC software trimming accuracy

T Startup time to reach within f var_noT

T Startup time to reach within f var_T

—

T < 150 °C

T < 165 o

C

T < 150 °C

T < 165 o

C

Trimming temperature

Factory trimming already applied

Factory trimming already applied

—

–5

–7

–3

–4

–0.5

—

—

16

—

—

—

—

+0.3

—

—

—

5

7

3

4

0.5

5

120

MHz

%

%

%

µs

µs

I

FIRC

CC T Current consumption on HV power supply

(1)

After T start_T

— — 1200 µA

1. The consumption reported considers the sum of the RC oscillator 16 MHz IP, and the core logic clocked by the IP during

Standby mode.

DS11646 Rev 4 47/154

48

Electrical characteristics SPC58EEx, SPC58NEx

Symbol

F sirc

δ f var_T

δ f var_V

I sirc

T sirc

Table 25. 1024 kHz internal RC oscillator electrical characteristics

Value

C Parameter Conditions

Min Typ Max

CC T

CC P

CC P

CC T

CC T

Slow Internal

RC oscillator frequency

Frequency variation across temperature

Frequency variation across voltage

Slow Internal

RC oscillator current

Start up time, after switching

ON the internal regulator.

—

–40 °C < T <

150 °C

–40 °C < T <

150 °C

T = 55 °C

—

—

–9

–5

—

—

1024

—

—

—

—

—

+9

+5

6

12

Unit kHz

%

%

µA

µS

48/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

3.12.1 ADC input description

Figure 8 shows the input equivalent circuit for SARn and SARB channels.

Figure 8. Input equivalent circuit (Fast SARn and SARB channels)

INTERNAL CIRCUIT SCHEME

V

DD

Channel

Selection

Sampling

R

SW1

R

AD

C

EXT

C

P1

C

P2

V

SS_HV_ADR

R

SW1

R

AD

: Sampling Switch Impedance

C

P

C

S

: Pin Capacitance (two contributions, C

P1

and C

P2

)

R

CMSW

: Common mode switch

R

CMRL

: Common mode resistive ladder

V

CM

: Common mode voltage (~0.5 V

DD

)

C

EXT

: External capacitance

The above scheme can be used as approximation circuitry for external filtering definition.

C

S

R

CMSW

R

CMRL

V

CM

Common mode switch

Common mode resistive ladder

Specifications in the following table apply to both packaged parts and Known Good Die

(KGD) parts, except where noted.

All specifications in the following table valid for the full input voltage range for the analog inputs.

R

20K Ω

I

LKG

I

INJ1,2

C

HV_ADC

C

P1

Symbol

Table 26. ADC pin specification

Value

C Parameter Conditions Unit

Min Max

CC D

Internal voltage reference source impedance.

CC —

Input leakage current, two ADC channels on input-only pin.

SR —

Injection current on analog input preserving functionality at full or degraded performances.

—

See IO chapter

16

Table 11: I/O input electrical characteristics , parameter I

LKG

.

See Operating Conditions chapter

Operating conditions

, I

INJ1

and I

30

Table 5:

INJ2

K

parameters.

Ω

SR D V

DD_HV_ADV

external capacitance.

CC D Pad capacitance

See Power Management chapter Table 39: External components integration , C

ADC

parameter.

See IO chapter Table 11: I/O input electrical characteristics , parameter C

P1

.

DS11646 Rev 4 49/154

66

Electrical characteristics SPC58EEx, SPC58NEx

Table 26. ADC pin specification (continued)

Value

Symbol C Parameter Conditions Unit

Min Max

C

P2

CC D Internal routing capacitance

SARB channels

SARn 10bit channels

SARn 12bit channels

—

—

—

2

0.5

1 pF

C

S

CC D SAR ADC sampling capacitance

SARn 12bit

SARn 10bit

SARB channels

SARn 10bit channels

0

0

—

—

5

2

1.8

0.8

pF

R

SWn

CC D Analog switches resistance k Ω

R

AD

CC D

ADC input analog switches resistance

SARn 12bit channels

SARn 12bit

SARn 10bit

0

—

—

1.8

0.8

3.2

k Ω

R

R

CMSW

CMRL

CC D Common mode switch resistance

CC D Common mode resistive ladder

CC D

Discharge resistance for ADC input-only pins (strong pull-down for safety)

CC D ADC digital bandgap accuracy

Sum of the two resistances

V

DD_HV_IO

= 5.0 V ± 10%

—

—

9

300 k Ω k Ω

W

R

SAFEPD

(1)

A

BGAP

C

EXT

SR —

External capacitance at the pad input pin

V

DD_HV_IO

= 3.3 V ± 10% — 500 W

-1.5

+1.5

%

To preserve the accuracy of the ADC, it is necessary that analog input pins have low AC impedance.

Placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as possible. This capacitor contributes to attenuating the noise present on the input pin. The impedance relative to the signal source can limit the ADC’s sample rate.

1. It enables discharge of up to 100 nF from 5 V every 300 ms. Refer to the device pinout Microsoft Excel file attached to the

IO_Definition document for the pads supporting it.

3.12.2 SAR ADC 12 bit electrical specification

Note:

The SARn ADCs are 12-bit Successive Approximation Register analog-to-digital converters with full capacitive DAC. The SARn architecture allows input channel multiplexing.

The functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maximum may affect device reliability or cause permanent damage to the device.

50/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics f

ADCK t

ADCINIT t

ADCBIASINIT t

ADCPRECH

Δ V

PRECH

R

20K Ω

Δ V

INTREF

Symbol C

Table 27. SARn ADC electrical specification

Parameter Conditions

P

SR Clock frequency

T

SR — ADC initialization time

SR —

ADC BIAS initialization time

Standard frequency mode

High frequency mode

—

—

SR

SR

T

D

ADC decharge time

Decharge voltage precision

Fast SAR

Slow SAR (SARDAC_B)

T

J

< 150 °C

T

J

< 165 °C

CC D

Internal voltage reference source impedance

—

CC P

Internal reference voltage precision

Applies to all internal reference points

(V

SS_HV_ADR

,

1/3 * V

DD_HV_ADR

2/3 * V

DD_HV_ADR

,

,

V

DD_HV_ADR

)

Min

7.5

>13.33

1.5

Value

Max

13.33

16.0

—

5

1/f

ADCK

2/f

ADCK

0

0

16

− 0.20

30

0.20

—

—

—

0.25

0.3

Unit

MHz

µs

µs

µs

V

K Ω

V

DS11646 Rev 4 51/154

66

Electrical characteristics SPC58EEx, SPC58NEx

Symbol

Table 27. SARn ADC electrical specification (continued)

Value

C Parameter Conditions

Min Max t

ADCSAMPLE t

ADCEVAL

I

ADCREFH

(5),(6)

I

ADCREFL

(6)

I

ADV_S

(6)

SR

SR

CC

CC

P

D

P

D

T

CC D

P

D

ADC sample time

ADC high reference current

ADC low reference current

V

DD_HV_ADV

power supply current

(1)

ADC evaluation time

Fast SAR – 12-bit configuration

Fast SAR – 10-bit configuration mode 1

(2)

(Standard frequency mode only)

Fast SAR – 10-bit configuration mode 2

(3)

(Standard frequency mode only)

Fast SAR – 10-bit configuration mode 3

(4)

(High frequency mode only)

Slow SAR (SARADC_B) –

12-bit configuration

Slow SAR (SARADC_B) –

10-bit configuration mode

1

(2)

(Standard frequency mode only)

Slow SAR (SARADC_B) –

10-bit configuration mode

2 (3)

(Standard frequency mode only)

Slow SAR (SARADC_B) –

10-bit configuration mode

3

(4)

(High frequency mode only)

Conversion of BIAS test channels through 20 k Ω input.

12-bit configuration

10-bit configuration

Run mode

(average across all codes)

Power Down mode

Run mode

V

DD_HV_ADR_S

≤ 5.5 V

Power Down mode

V

DD_HV_ADR_S

≤ 5.5 V

Run mode

Power Down mode

6/f

ADCK

6/f

ADCK

5/f

ADCK

6/f

ADCK

12/f

ADCK

12/f

ADCK

10/f

ADCK

12/f

ADCK

40/f

ADCK

12/f

ADCK

10/f

ADCK

—

—

—

—

—

—

—

—

—

7

1

15

1

4.0

0.04

Unit

µs

µs

µA

µA mA

52/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Symbol

TUE

12

TUE

10

CC

CC

Table 27. SARn ADC electrical specification (continued)

Value

C Parameter Conditions

Min Max

T

P

T

T

T

D

D

D

D

D

C

C

Total unadjusted error in 12-bit configuration

(7)

Total unadjusted error in 10-bit

configuration

(7)

T

J

< 150 °C,

V

DD_HV_ADV

> 3 V,

V

DD_HV_ADR_S

> 3 V

T

J

< 150 °C,

V

DD_HV_ADV

> 3 V,

V

DD_HV_ADR_S

> 3 V

T

J

< 150 °C,

V

DD_HV_ADV

> 3 V,

3 V > V

DD_HV_ADR_S

> 2 V

T

J

< 165 °C,

V

DD_HV_ADV

> 3 V,

V

DD_HV_ADR_S

> 3 V

T

J

< 165 °C,

V

DD_HV_ADV

> 3 V,

3 V > V

DD_HV_ADR_S

> 2 V

High frequency mode,

T

J

< 150 °C,

V

DD_HV_ADV

> 3 V,

V

DD_HV_ADR_S

> 3 V

Mode 1, T

J

< 150 °C,

V

DD_HV_ADV

> 3 V

V

DD_HV_ADR_S

> 3 V

Mode 1, T

J

< 150 °C,

V

DD_HV_ADV

> 3 V,

3 V > V

DD_HV_ADR_S

> 2 V

Mode 1, T

J

< 165 °C,

V

DD_HV_ADV

> 3 V,

V

DD_HV_ADR_S

> 3 V

Mode 1, T

J

< 165 °C,

V

DD_HV_ADV

> 3 V,

3 V > V

DD_HV_ADR_S

> 2 V

Mode 2, T

J

< 150 °C,

V

DD_HV_ADV

> 3 V

V

DD_HV_ADR_S

> 3 V

Mode 3, T

J

< 150 °C,

V

DD_HV_ADV

> 3 V

V

DD_HV_ADR_S

> 3 V

–4

–6

–6

–9

–11

–12

–1.5

–2.0

–2.5

–3.5

–3.0

–4.0

4

6

6

9

11

12

1.5

2.0

2.5

3.5

3.0

4.0

Unit

LSB

(12b)

LSB

(10b)

DS11646 Rev 4 53/154

66

Electrical characteristics SPC58EEx, SPC58NEx

Table 27. SARn ADC electrical specification (continued)

Value

Symbol C Parameter Conditions Unit

Min Max

Δ TUE

12

CC D

TUE degradation due to V with respect to

V

DD_HV_ADR

DD_HV_ADV offset

V

IN

< V

DD_HV_ADV

V

DD_HV_ADR

∈ [0:25 mV]

− V

DD_HV_ADV

V

IN

< V

DD_HV_ADV

V

DD_HV_ADR

∈ [25:50 mV]

− V

DD_HV_ADV

V

IN

< V

DD_HV_ADV

V

DD_HV_ADR

∈ [50:75 mV]

− V

DD_HV_ADV

V

IN

< V

DD_HV_ADV

V

DD_HV_ADR

− V

DD_HV_ADV

∈ [75:100 mV]

V

DD_HV_ADV

< V

IN

<

V

DD_HV_ADR

V

DD_HV_ADR

∈ [0:25 mV]

− V

DD_HV_ADV

V

DD_HV_ADV

< V

IN

<

V

DD_HV_ADR

V

DD_HV_ADR

∈ [25:50 mV]

− V

DD_HV_ADV

V

DD_HV_ADV

< V

IN

<

V

DD_HV_ADR

V

DD_HV_ADR

∈ [50:75 mV]

− V

DD_HV_ADV

V

DD_HV_ADV

< V

IN

<

V

DD_HV_ADR

V

DD_HV_ADR

− V

DD_HV_ADV

∈ [75:100 mV]

–1

–2

–4

–6

–2.5

–4

–7

–12

1

2

4

6

2.5

4

7

12

LSB

(12b)

TUE

INJ2

CC T

TUE degradation addition, due to

I current injection in

INJ2

range.

(8)

See Operating Conditions

chapter Table 5 , I

INJ2 parameter.

+8 LSB

DNL

(9)

CC

P

T

Differential nonlinearity

Standard frequency mode,

V

DD_HV_ADV

> 4 V

V

DD_HV_ADR_S

> 4 V

High frequency mode,

V

DD_HV_ADV

> 4 V

V

DD_HV_ADR_S

> 4 V

–1

–1

2

2

LSB

(12b)

1. Minimum ADC sample times are dependent on adequate charge transfer from the external driving circuit to the internal sample capacitor. The time constant of the entire circuit must allow the sampling capacitor to charge within 1/2 LSB within

the sampling window. Refer to Figure 8

for models of the internal ADC circuit, and the values to use in external RC sizing and calculating the sampling window duration.

2. Mode1: 6 sampling cycles + 10 conversion cycles at 13.33 MHz.

3. Mode2: 5 sampling cycles + 10 conversion cycles at 13.33 MHz.

54/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

4. Mode3: 6 sampling cycles + 10 conversion cycles at 16 MHz.

5. I

ADCREFH and I

ADCREFL are independent from ADC clock frequency. It depends on conversion rate: consumption is driven by the transfer of charge between internal capacitances during the conversion.

6. Current parameter values are for a single ADC.

7. TUE is granted with injection current within the range defined in

Table 26 , for parameters classified as T and D.

8. All channels of all SAR-ADC12bit and SAR-ADC10bit are impacted with same degradation, independently from the ADC and the channel subject to current injection.

9. DNL is granted with injection current within the range defined in

Table 26 , for parameters classified as T and D.

3.12.3 SAR ADC 10 bit electrical specification

Note:

The ADC comparators are 10-bit Successive Approximation Register analog-to-digital converters with full capacitive DAC. The SARn architecture allows input channel multiplexing.

The functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maximum may affect device reliability or cause permanent damage to the device.

Symbol f

ADCK t

ADCINIT t

ADCBIASINIT t

ADCINITSBY t

ADCPRECH

Δ V

PRECH t

ADCSAMPLE t

ADCEVAL

I

ADCREFH

(2),(3)

C

Table 28. ADC-Comparator electrical specification

Parameter Conditions

P

SR Clock frequency

T

SR — ADC initialization time

Standard frequency mode

High frequency mode

—

SR —

ADC BIAS initialization time

SR —

ADC initialization time in standby

Standby Mode

—

SR T ADC precharge time

SR

SR

SR

CC

D

Precharge voltage precision

P ADC sample time

P

D

T

ADC high reference current

(1)

ADC evaluation time

—

T

J

< 150 °C

T

J

< 165 °C

10-bit ADC mode

ADC comparator mode

10-bit ADC mode

ADC comparator mode

Run mode

(average across all codes)

Power Down mode

ADC comparator mode

Value

Min

7.5

>13.33

1.5

Max

13.33

16.0

—

5

8

1/f

ADCK

0

0

5/f

ADCK

2/f

ADCK

10/f

ADCK

2/f

ADCK

—

—

—

—

—

—

0.25

0.3

—

—

—

—

7

1

19.5

Unit

MHz

µs

µs

µs

µs

V

µs

µs

µs

µA

DS11646 Rev 4 55/154

66

Electrical characteristics SPC58EEx, SPC58NEx

Symbol

I

ADCREFL

(4)

I

ADV_S

(4)

TUE

10

Table 28. ADC-Comparator electrical specification (continued)

Value

C Parameter Conditions

Min Max

CC

CC

CC

D

ADC low reference current

Run mode

V

DD_HV_ADR_S

≤ 5.5 V

Power Down mode

V

DD_HV_ADR_S

≤ 5.5 V

ADC comparator mode

P V

DD_HV_ADV

D

power supply current

T

P

T

T

T

D

Run mode

Power Down mode

Total unadjusted error in 10-bit configuration

(5)

T

V

J

< 150 °C,

V

DD_HV_ADV

> 3 V,

DD_HV_ADR_S

> 3 V

T

V

J

< 150 °C,

V

DD_HV_ADV

> 3 V,

DD_HV_ADR_S

> 3 V

T

V

J

< 150 °C,

DD_HV_ADV

3 V > V

> 3 V,

DD_HV_ADR_S

> 2 V

T

V

J

< 165 °C,

V

DD_HV_ADV

> 3 V,

DD_HV_ADR_S

> 3 V

T

V

J

< 165 °C,

DD_HV_ADV

3 V > V

> 3 V,

DD_HV_ADR_S

> 2 V

High frequency mode,

T

V

J

< 150 °C,

V

DD_HV_ADV

> 3 V,

DD_HV_ADR_S

> 3 V

—

—

—

—

—

–2

–3

–3

–3

–4

–3

15

1

20.5

4

0.04

2

3

3

3

4

3

Unit

µA mA

LSB

(10b)

56/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Symbol

Table 28. ADC-Comparator electrical specification (continued)

Value

C Parameter Conditions

Min Max

Unit

V

IN

< V

DD_HV_ADV

V

DD_HV_ADR

[0:25 mV]

− V

DD_HV_ADV

∈

V

IN

< V

DD_HV_ADV

V

DD_HV_ADR

[25:50 mV]

− V

DD_HV_ADV

∈

V

IN

< V

DD_HV_ADV

V

DD_HV_ADR

[50:75 mV]

− V

DD_HV_ADV

∈

–1.0

–2.0

–3.5

1.0

2.0

3.5

Δ TUE

10

CC D

TUE degradation due to V

DD_HV_ADR with respect to

V

DD_HV_ADV offset

V

IN

< V

DD_HV_ADV

V

DD_HV_ADR

[75:100 mV]

− V

DD_HV_ADV

∈

V

DD_HV_ADV

< V

IN

<

V

DD_HV_ADR

V

DD_HV_ADR

[0:25 mV]

− V

DD_HV_ADV

∈

V

DD_HV_ADV

< V

IN

<

V

DD_HV_ADR

V

DD_HV_ADR

[25:50 mV]

− V

DD_HV_ADV

∈

V

DD_HV_ADV

< V

IN

<

V

DD_HV_ADR

V

DD_HV_ADR

[50:75 mV]

− V

DD_HV_ADV

∈

V

DD_HV_ADV

< V

IN

<

V

DD_HV_ADR

V

DD_HV_ADR

[75:100 mV]

− V

DD_HV_ADV

∈

–6.0

–2.5

–4.0

–7.0

–12.0

6.0

2.5

4.0

7.0

12.0

LSB

(10b)

TUE

INJ2

CC T

TUE degradation addition, due to current injection in I

INJ2

range.

(4)

See Operating Conditions

chapter Table 5 , I

INJ2 parameter.

3 LSB

DNL

(6)

CC

P

T

Differential non-linearity std. mode

Standard frequency mode,

V

DD_HV_ADV

> 4 V

V

DD_HV_ADR_S

> 4 V

High frequency mode,

V

DD_HV_ADV

> 4 V

V

DD_HV_ADR_S

> 4 V

–1

–1

2

2

LSB

(10b)

1. Minimum ADC sample times are dependent on adequate charge transfer from the external driving circuit to the internal sample capacitor. The time constant of the entire circuit must allow the sampling capacitor to charge within 1/2 LSB within

the sampling window. Refer to Figure 8

for models of the internal ADC circuit, and the values to use in external RC sizing and calculating the sampling window duration.

2. I

ADCREFH and I

ADCREFL are independent from ADC clock frequency. It depends on conversion rate: consumption is driven by the transfer of charge between internal capacitances during the conversion.

3. Current parameter values are for a single ADC.

DS11646 Rev 4 57/154

66

Electrical characteristics SPC58EEx, SPC58NEx

4. All channels of all SAR-ADC12bit and SAR-ADC10bit are impacted with same degradation, independently from the ADC and the channel subject to current injection.

5. TUE is granted with injection current within the range defined in

Table 26 , for parameters classified as T and D.

6. DNL is granted with injection current within the range defined in

Table 26 , for parameters classified as T and D.

Note:

The SDn ADCs are Sigma Delta 16-bit analog-to-digital converters with 333666 Ksps maximum output rate.

The functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maximum may affect device reliability or cause permanent damage to the device.

S/D ADC is functional in the range 3.0 V < VDD_HV_ADV < 4.0 V and

3.0 V < VDD_HV_ADR_D < 4.0 V, but precision of conversion is not guaranteed.

Table 29. SDn ADC electrical specification

Symbol C Parameter Conditions

Min

Value

Typ Max

Unit

V

IN_PK2PK

(1) f f

ADCD_M f

IN

ADCD_S

—

GAIN

SR

D

D

D

Input range peak to peak

V = V

INP

(2)

– V

INM

Single ended

V

INM

= V

SS_HV_ADR_D

Single ended

V

INM

= 0.5*V

DD_HV_ADR

_D

GAIN = 1

Single ended

V

INM

= 0.5*V

DD_HV_ADR

_D

GAIN = 2,4,8,16

D

Differential,

0 < V

IN

<

V

DD_HV_IO_MAIN

SR P

S/D modulator input

Clock 3

T

J

< 150 °C

SR P

Input signal frequency

SR D

Output conversion rate

T

J

—

< 150 °C

CC D Oversampling ratio

RESOLUTION CC D

S/D register resolution

SR D ADC gain

(5)

Internal modulator

External modulator

2’s complement notation

Defined via

ADC_SD[PGA] register.

Only integer powers of

2 are valid gain values.

4

±V

DD_HV_ADR_D

/GAIN

±V

DD_HV_ADR_D

/GAIN

0.01

—

24

—

1

V

DD_HV_ADR_D

/GAIN

±0.5*V

DD_HV_ADR_D

14.4

—

—

—

—

16

—

16

75

(4)

333

256

256

16

V

MHz kHz

— ksps

—

— bit

58/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Symbol

|δ

GAIN

| (6)

V

OFFSET

C

Table 29. SDn ADC electrical specification (continued)

Value

Parameter Conditions

Min Typ

C

CC

D

Absolute value of the ADC gain

error

(7) (8)

P

CC

D

Conversion offset

(7),(8),(9)

Before calibration

(applies to gain setting = 1)

After calibration,

Δ V

DD_HV_ADR_D

Δ V

DD_HV_ADV_D

Δ T

J

< 50 °C

< 5%

< 10%

After calibration,

Δ V

DD_HV_ADR_D

Δ V

DD_HV_ADV_D

Δ T

J

< 100 °C

< 5%

< 10%

After calibration,

Δ V

DD_HV_ADR_D

Δ V

DD_HV_ADV_D

Δ T

J

< 150 °C

< 5%

< 10%

Before calibration

(applies to all gain settings – 1, 2, 4, 8, 16)

After calibration,

Δ V

DD_HV_ADR_D

Δ T

J

< 50 °C

< 10%

After calibration,

Δ V

DD_HV_ADR_D

Δ T

J

< 100 °C

< 10%

After calibration,

Δ V

DD_HV_ADR_D

Δ T

J

< 150 °C

< 10%

—

—

—

—

—

—

—

0.5

—

—

—

—

10*

(1+1/gain)

—

—

—

Max

1

5

7.5

10

65

5

7.5

19

Unit

% mV mV mV

DS11646 Rev 4 59/154

66

Electrical characteristics SPC58EEx, SPC58NEx

Symbol C

Table 29. SDn ADC electrical specification (continued)

Value

Parameter Conditions

Min Typ

SNR

DIFF150

(10)

CC

P

C

C

Signal to noise ratio in differential mode

150 ksps output rate

(11)

C

D

4.0 < V

DD_HV_ADV

V

DD_HV_ADR_D

= V

< 5.5

DD_H

V_ADV

GAIN = 1

T

J

< 150 °C

4.0 < V

DD_HV_ADV

V

DD_HV_ADR_D

V

DD_HV_ADV

GAIN = 2

=

T

J

< 150 °C

< 5.5

4.0 < V

DD_HV_ADV

V

DD_HV_ADR_D

V

DD_HV_ADV

GAIN = 4

=

T

J

< 150 °C

< 5.5

4.0 < V

DD_HV_ADV

V

DD_HV_ADR_D

V

DD_HV_ADV

GAIN = 8

=

T

J

< 150 °C

< 5.5

4.0 < V

DD_HV_ADV

V

DD_HV_ADR_D

V

DD_HV_ADV

GAIN = 16

=

T

J

< 150 °C

< 5.5

80

77

74

71

68

—

—

—

—

—

Max

—

—

—

—

—

Unit dBFS

60/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Symbol C

Table 29. SDn ADC electrical specification (continued)

Value

Parameter Conditions

Min Typ

SNR

DIFF333

(10)

CC

P

C

C

Signal to noise ratio in differential mode

333 ksps output

rate (11)

C

D

4.0 < V

DD_HV_ADV

V

DD_HV_ADR_D

V

DD_HV_ADV

GAIN = 1

=

T

J

< 150 °C

< 5.5

4.0 < V

DD_HV_ADV

V

DD_HV_ADR_D

V

DD_HV_ADV

GAIN = 2

=

T

J

< 150 °C

< 5.5

4.0 < V

DD_HV_ADV

V

DD_HV_ADR_D

V

DD_HV_ADV

GAIN = 4

=

T

J

< 150 °C

< 5.5

4.0 < V

DD_HV_ADV

V

DD_HV_ADR_D

V

DD_HV_ADV

GAIN = 8

=

T

J

< 150 °C

< 5.5

4.0 < V

DD_HV_ADV

V

DD_HV_ADR_D

V

DD_HV_ADV

GAIN = 16

=

T

J

< 150 °C

< 5.5

71

68

65

62

60

—

—

—

—

—

Max

—

—

—

—

—

Unit dBFS

DS11646 Rev 4 61/154

66

Electrical characteristics SPC58EEx, SPC58NEx

Symbol

SNR

SE150

(10)

Δ

SNR165C

Δ

SNRINJ2

SFDR

Z

DIFF

C

Table 29. SDn ADC electrical specification (continued)

Value

Parameter Conditions

Min Typ

CC

P

T

Signal to noise ratio in single ended mode 150 ksps

output rate (11)

D

CC C

CC T

P

165 °C Signal to noise ratio impact

TUE degradation addition, due to current injection in

I

INJ2

range.

4.0 < V

DD_HV_ADV

V

DD_HV_ADR_D

V

DD_HV_ADV

GAIN = 1

=

T

J

< 150 °C

< 5.5

4.0 < V

DD_HV_ADV

V

DD_HV_ADR_D

V

DD_HV_ADV

GAIN = 2

=

T

J

< 150 °C

< 5.5

4.0 < V

DD_HV_ADV

V

DD_HV_ADR_D

V

DD_HV_ADV

GAIN = 4

=

T

J

< 150 °C

< 5.5

4.0 < V

DD_HV_ADV

V

DD_HV_ADR_D

V

DD_HV_ADV

GAIN = 8

=

T

J

< 150 °C

< 5.5

4.0 <

V

V

DD_HV_ADV

DD_HV_ADR_D

V

DD_HV_ADV

GAIN = 16

=

< 5.5

T

J

< 150 °C

Any GAIN

150 °C < T

J

< 165 °C

See Operating

Conditions chapter

Table 5 , I

parameter

GAIN = 1

CC

C

C

Spurious free dynamic range

C

GAIN = 2

GAIN = 4

GAIN = 8

CC

D

D

GAIN = 16

GAIN = 1

D

D

D

Differential input impedance

(f

ADCD_M

= 16 MHz)

GAIN = 2

GAIN = 4

GAIN = 8

D GAIN = 16

74

71

68

65

62

–9

—

60

900

550

250

180

180

60

60

60

60

—

—

—

—

—

—

—

—

1125

700

350

225

225

—

—

—

—

Max

—

—

—

—

—

—

–9

Unit dBFS dBFS dBFS

—

1350

900

450

270

270

—

—

—

— dBc k Ω

62/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Symbol

Z

CM

R

BIAS

V

BIAS

Δ V

INTCM

δ V

BIAS

V cmrr

R

Caaf f

PASSBAND

δ

RIPPLE

F rolloff

C

Table 29. SDn ADC electrical specification (continued)

Value

Parameter Conditions

Min Typ

CC

D GAIN = 1

D

D

D

Common mode input impedance

(f

ADCD_M

= 16 MHz)

GAIN = 2

GAIN = 4

GAIN = 8

D GAIN = 16

CC D Bias resistance —

1250

900

620

450

450

120

CC D Bias voltage

CC D common mode input reference voltage

—

—

—

–12

1600

1150

850

580

580

160

V

DD_HV_

ADR_D

/2

(V

DD_HV_

ADV

+

V

SS_HV_

ADV

)/2

CC D

Bias voltage accuracy

— –2.5

—

CC T

Common mode rejection ratio

SR D

Anti-aliasing filter

CC D

GAIN = 1

GAIN ≥ 4

External series resistance

Filter capacitances

40

46

—

180

—

—

—

—

CC D Pass band

(13)

— 0.01

—

CC D Pass band ripple

(14)

CC D

Stop band attenuation

0.333 * f

ADCD_Sin

[0.5 * f

ADCD_S

1.0 * f

ADCD_S

]

,

[1.0 * f

ADCD_S

1.5 * f

ADCD_S

]

,

[1.5 * f

ADCD_S

2.0 * f

ADCD_S

]

,

[2.0 * f

ADCD_S

2.5 * f

ADCD_S

]

, f

[2.5 * f

ADCD_S

ADCD_M

/2]

,

–1

40

45

50

55

60

—

—

—

—

—

—

+12

+2.5

—

—

20

—

0.333 * f

ADCD_S

1

—

—

—

—

—

Max

2000

1450

1050

720

720

200

—

Unit k Ω k Ω

V

%

% dB dB k Ω pF kHz

%

DS11646 Rev 4 63/154

66

Electrical characteristics SPC58EEx, SPC58NEx

Symbol

δ

GROUP f

HIGH t

STARTUP t

LATENCY

C

Table 29. SDn ADC electrical specification (continued)

Value

Parameter Conditions

Min Typ

CC D

Group delay

OSR = 96

OSR = 112

OSR = 128

OSR = 144

OSR = 160

OSR = 176

OSR = 192

OSR = 224

OSR = 256

CC D

High pass filter 3dB frequency

Enabled

CC D

Start-up time from power down state

CC D

Latency between input data and converted data

(input mux not changed)

(15)

HPF = ON

HPF = OFF

—

Within pass band – Tclk is f

ADCD_M

/ 2

OSR = 24

OSR = 28

OSR = 32

OSR = 36

OSR = 40

OSR = 44

OSR = 48

OSR = 56

OSR = 64

OSR = 72

OSR = 75

OSR = 80

OSR = 88

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

10e-5* f

ADCD_S

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

Max

100

δ

GROUP

+ f

ADCD_S

δ

GROUP

—

758.5

884.5

1010.5

1136.5

1262.5

1388.5

1514.5

1766.5

2018.5

443.5

506.5

569.5

550

632.5

695.5

191.5

223

254.5

286

317.5

349

380.5

—

Unit

—

Tclk

—

µs

—

—

64/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Symbol C

Table 29. SDn ADC electrical specification (continued)

Value

Parameter Conditions

Min Typ

Unit

Max t t

SETTLING

ODRECOVERY

Σ

I

C

S_D

IBIAS

I

ADV_D

ADR_D

CC D

Settling time after mux change

Analog inputs are muxed

HPF = ON

HPF = OFF

CC D

Overdrive recovery time

After input comes within range from saturation

HPF = ON

CC D

S/D ADC sampling capacitance after sampling switch

(16)

HPF = OFF

GAIN = 1, 2, 4, 8

GAIN = 16

CC D Bias consumption

At least 1 ADCD enabled

CC C

V

DD_HV_ADV power supply current (each ADC)

CC C

Sum of all ADC reference consumption

(17)

ADCD enabled

ADCD enabled

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

2* δ

GROUP

+

3*f

ADCD_S

2* δ

GROUP

+

2*f

ADCD_S

2* δ

GROUP f

2* δ

+

ADCD_S

GROUP

75*GAIN

600

5

3.5

80

—

—

—

— fF fF mA mA

µA

1. For input voltage above the maximum and below the clamp voltage of the input pad, there is no latch-up concern, and the signal will only be ‘clipped’.

2. V

INP

is the input voltage applied to the positive terminal of the SDADC.

3. V

INM

is the input voltage applied to the negative terminal of the SDADC.

4. Maximum input of 166.67 KHz supported with reduced accuracy. See SNR specifications.

5. When using a GAIN setting of 16, the conversion result will always have a value of zero in the least significant bit. This gives an effective resolution of 15 bits.

6. The absolute value of the ADC gain error (| δ GAIN|) after calibration is applicable in differential mode only. In single-ended mode after calibration, this value should be considered as 25mV.

7. Offset and gain error due to temperature drift can occur in either direction (+/-) for each of the SDADCs on the device.

8. Calibration of gain is possible when gain = 1. Offset Calibration should be done with respect to 0.5*VDD_HV_ADR_D for

"differential mode" and "single ended mode with negative input=0.5*VDD_HV_ADR_D". Offset Calibration should be done with respect to 0 for "single ended mode with negative input=0". Both offset and Gain Calibration is guaranteed for ±5% variation of VDD_HV_ADR_D, ±10% variation of VDD_HV_ADV, and ± 50 °C temperature variation.

9. Conversion offset error must be divided by the applied gain factor (1, 2, 4, 8, or 16) to obtain the actual input referred offset error.

10. This parameter is guaranteed by bench validation with a small sample of devices across process variations, and tested in production to a value of 3 dB less.

11. S/D ADC is functional in the range 3.6 V < V value based on simulation and granted by design.

< 4.0 V and, SNR parameter degrades by 12 dB. Degraded SNR

12. All channels of all SD-ADCs are impacted with same degradation, independently from the ADC and the channel subject to current injection.

13. SNR value guaranteed only if external noise on the ADC input pin is attenuated by the required SNR value in the frequency range of fADCD_M - fADCD_S to fADCD_M + fADCD_S, where fADCD_M is the input sampling frequency, and fADCD_S is the output sample frequency. A proper external input filter should be used to remove any interfering signals in this frequency range.

14. The ±1% passband ripple specification is equivalent to 20 * log

10

(0.99) = 0.087 dB.

DS11646 Rev 4 65/154

66

Electrical characteristics SPC58EEx, SPC58NEx

15. Propagation of the information from the pin to the register CDR[CDATA] and flags SFR[DFEF], SFR[DFFF] is given by the different modules that need to be crossed: delta/sigma filters, high pass filter, fifo module, clock domain synchronizers. The time elapsed between data availability at pin and internal S/D module registers is given by the below formula:

REGISTER LATENCY = t of the sampling clock, f

LATENCY

+ 0.5/f

ADCD_M

ADCD_S

+ 2 (~+1)/f

ADCD_M

+ 2(~+1)f

is the frequency of the modulator, and f

PBRIDGEx_CLK

PBRIDGEx_CLK

where f

ADCD_S

is the frequency clock cycle) to be added due to resynchronization of the signal during clock domain crossing. Some further latency may be added by the target module (core, DMA, interrupt) controller to process the data received from the ADC S/D module.

16. This capacitance does not include pin capacitance, that can be considered together with external capacitance, before sampling switch.

17. Consumption is given after power-up, when steady state is reached. Extra consumption up to 2 mA may be required during internal circuitry set-up.

3.12.5 SD ADC filter modes

Table 30. Digital output codes in full scale

OSR MCR[GECEN] = 1

72

75

80

88

96

112

36

40

44

24

28

32

48

56

64

128

144

160

176

192

224

256

512

1024

31075

31128

31026

31040

31081

31078

31081

31077

31079

31075

31026

31040

31081

31077

31079

31079

31076

31026

31040

31081

31078

31079

31079

31079

66/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

The following table describes the temperature sensor electrical characteristics.

Symbol

—

T

SENS

T

ACC

C

Table 31. Temperature sensor electrical characteristics

Value

Parameter Conditions

CC — Temperature monitoring range

CC T Sensitivity

CC P Accuracy

C

—

—

T

J

< 150 ° C

T

J

< 165 o C

Min

–40

—

–3

–7

Typ

—

5.18

—

—

Unit

Max

165

—

3

7

°C mV/°C

°C

DS11646 Rev 4 67/154

67

Electrical characteristics SPC58EEx, SPC58NEx

3.14 LFAST pad electrical characteristics

The LFAST(LVDS Fast Asynchronous Serial Transmission) pad electrical characteristics apply to both the SIPI and high-speed debug serial interfaces on the device. The same

LVDS pad is used for the Microsecond Channel (MSC) and DSPI LVDS interfaces, with different characteristics given in the following tables.

3.14.1 LFAST interface timing diagrams

Figure 9. LFAST and MSC/DSPI LVDS timing definition

Signal excursions above this level NOT allowed

Max. common mode input at RX

1600 mV

|Δ

VOD

|

Max Differential Voltage =

285 mV (LFAST)

400 mV (MSC/DSPI)

PAD_P

Minimum Data Bit Time

Opening =

0.55 * T (LFAST)

0.50 * T (MSC/DSPI)

|Δ

VOD

|

Min Differential

Voltage =

100 mV (LFAST)

150 mV (MSC/DSPI)

“No-Go” V

OS

= 1.2 V +/- 10%

TX common mode

PAD_N

Δ PER

EYE

V

ICOM

Δ PER

EYE

Data Bit Period

T = 1 /F

DATA

Min. common mode input at RX

Signal excursions below this level NOT allowed

150 mV

0 V

68/154 DS11646 Rev 4

SPC58EEx, SPC58NEx lfast_pwr_down

H

L

Differential TX

Data Lines pad_p/pad_n

Figure 10. Power-down exit time

Electrical characteristics t

PD2NM_TX

Data Valid

Figure 11. Rise/fall time

V

IH

Differential TX

Data Lines pad_p/pad_n

| Δ VOD(min)|

V

IL

| Δ VOD(min)| t

TR t

TR

3.14.2 LFAST and MSC/DSPI LVDS interface electrical characteristics

The following table contains the electrical characteristics for the LFAST interface.

Symbol

Table 32. LVDS pad startup and receiver electrical characteristics

(1),(2)

Value

C Parameter Conditions

Min Typ t

STRT_BIAS t

PD2NM_TX

CC T

CC T

STARTUP

(3),(4)

Bias current reference startup time

(5)

Transmitter startup time (power down to normal mode)

(6)

—

—

—

—

0.5

0.4

Max

4

2.75

Unit

μ s

μ s

DS11646 Rev 4 69/154

74

Electrical characteristics SPC58EEx, SPC58NEx

Table 32. LVDS pad startup and receiver electrical characteristics (1),(2) (continued)

Value

Symbol C Parameter Conditions

Min Typ Max

Unit t t t

I

SM2NM_TX

PD2NM_RX

PD2SM_RX

LVDS_BIAS

Z

Z

0

DIFF

CC T

CC T

Transmitter startup time (sleep mode to normal mode)

(7)

Receiver startup time (power down to normal mode)

(8)

CC T

Receiver startup time (power down to sleep mode)

(9)

CC D LVDS bias current consumption

SR D

SR D

Not applicable to the

MSC/DSPI LVDS pad

—

Not applicable to the

MSC/DSPI LVDS pad

Tx or Rx enabled

—

—

—

—

TRANSMISSION LINE CHARACTERISTICS (PCB Track)

Transmission line characteristic impedance

— 47.5

Transmission line differential impedance

— 95

RECEIVER

SR T Common mode voltage —

0.15

(10)

0.4

20

20

—

50

100

0.6

40

50

0.95

52.5

105

µs ns ns mA

Ω

Ω

V

ICOM

— 1.6

(11)

V

| Δ

VI

|

V

HYS

R

IN

SR T

CC T

Differential input voltage

Input hysteresis

(12)

—

—

100

25

—

—

—

—

CC D Terminating resistance V

DD_HV_IO

=

5.0 V ± 10%

-40 ° C < T

J

< 150 ° C

V

DD_HV_IO

=

3.3 V ± 10%

-40 ° C < T

J

< 150 ° C

V

DD_HV_IO

=

5.0 V ± 10%

-40 ° C<Tj<165 ° C

V

DD_HV_IO

=

3.3 V ± 10%

-40 ° C<Tj<165 ° C

80

80

80

80

—

—

—

—

150

175

170

180

I

C

IN

LVDS_RX

CC D Differential input capacitance

(13)

CC C

Receiver DC current consumption

—

Enabled

—

—

3.5

—

6.0

1.6

pF mA

I

PIN_RX

CC D

Maximum consumption on receiver input pin

Δ

VI

R

IN

= 400 mV,

= 80 Ω

— — 5 mA

1. The LVDS pad startup and receiver electrical characteristics in this table apply to both the LFAST & High-speed Debug

(HSD) LVDS pad, and the MSC/DSPI LVDS pad except where noted in the conditions.

2. All LVDS pad electrical characteristics are valid from -40 °C to 150 °C.

3. All startup times are defined after a 2 peripheral bridge clock delay from writing to the corresponding enable bit in the LVDS control registers (LCR) of the LFAST and High-speed Debug modules. The value of the LCR bits for the LFAST/HSD modules don’t take effect until the corresponding SIUL2 MSCR ODC bits are set to LFAST LVDS mode. Startup times for

MSC/DSPI LVDS are defined after 2 peripheral bridge clock delay after selecting MSC/DSPI LVDS in the corresponding

SIUL2 MSCR ODC field.

mV mV

Ω

70/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

4. Startup times are valid for the maximum external loads CL defined in both the LFAST/HSD and MSC/DSPI transmitter electrical characteristic tables.

5. Bias startup time is defined as the time taken by the current reference block to reach the settling bias current after being enabled.

6. Total transmitter startup time from power down to normal mode is t ods.

STRT_BIAS

+ t

PD2NM_TX

+ 2 peripheral bridge clock peri-

7. Total transmitter startup time from sleep mode to normal mode is t remains enabled in sleep mode.

SM2NM_TX

+ 2 peripheral bridge clock periods. Bias block

8. Total receiver startup time from power down to normal mode is t

STRT_BIAS

+ t

PD2NM_RX

+ 2 peripheral bridge clock periods.

9. Total receiver startup time from power down to sleep mode is t mains enabled in sleep mode.

PD2SM_RX

+ 2 peripheral bridge clock periods. Bias block re-

10. Absolute min = 0.15 V – (285 mV/2) = 0 V

11. Absolute max = 1.6 V + (285 mV/2) = 1.743 V

12. Value valid for LFAST mode and SPI mode. In LFAST mode the LXRXOP_BR bit in the LFAST LVDS Control Register

(LCR) must be set to one to ensure proper LFAST receive timing.

13. Total internal capacitance including receiver and termination, co-bonded GPIO pads, and package contributions. For bare die devices, subtract the package value given in

Figure 12 .

Symbol C

Table 33. LFAST transmitter electrical characteristics (1),(2),(3)

Value

Parameter Conditions

Min Typ

Unit

Max

I

I f

DATA

V t

OS

| Δ

VOD

TR

C

L

|

LVDS_TX

PIN_TX

SR D

CC P

CC P

CC T

Data rate

Common mode voltage

Differential output voltage swing

(terminated)

(4),(5)

Rise time from -| Δ VOD(min)| to

+| Δ VOD(min)|. Fall time from

+| Δ VOD(min)| to -| Δ VOD(min)|

—

—

—

—

—

1.08

110

0.26

SR D

External lumped differential load capacitance

(4)

CC C Transmitter DC current consumption

CC D

Transmitter DC current sourced through output pin

V

DD_HV_IO

= 4.5 V —

V

DD_HV_IO

= 3.0 V —

Enabled —

— 1.1

—

—

—

—

—

—

—

320

1.32

285

1.25

6.0

4.0

3.6

2.85

1. This table is applicable to LFAST LVDS pads used in LFAST configuration (SIUL2_MSCR_IO_n.ODC=101).

2. The LFAST and High-Speed Debug LFAST pad electrical characteristics are based on worst case internal capacitance values shown in

Figure 12 .

3. All LFAST and High-Speed Debug LVDS pad electrical characteristics are valid from -40 °C to 165 °C.

4. Valid for maximum data rate f

Figure 12 .

DATA

. Value given is the capacitance on each terminal of the differential pair, as shown in

5. Valid for maximum external load C

L

.

Mbps

V mV ns pF mA mA

DS11646 Rev 4 71/154

74

Electrical characteristics SPC58EEx, SPC58NEx

Symbol

Table 34. MSC/DSPI LVDS transmitter electrical characteristics (1),(2),(3)

Value

C Parameter Conditions

Min Typ Max

Unit

I

I f

DATA

V t

OS

| Δ

VOD

TR

C

L

|

LVDS_TX

PIN_TX

SR D

CC P

CC P

CC T

Data rate

Common mode voltage

Differential output voltage swing

(terminated)

(4),(5)

Rise time from -| Δ VOD(min)| to

+| Δ VOD(min)|. Fall time from

+| Δ VOD(min)| to -| Δ VOD(min)| (6)

—

—

—

—

—

1.08

150

0.8

SR D

External lumped differential load

capacitance

(4)

CC C Transmitter DC current consumption

CC D

Transmitter DC current sourced through output pin

V

DD_HV_IO

= 4.5 V —

V

DD_HV_IO

= 3.0 V —

Enabled —

— 1.5

—

—

—

—

—

—

—

—

80

1.32

400

5.8

50

39

5.0

4.0

Mbps

V mV ns pF mA mA

1. This table is applicable to MSC/DSPI LVDS pads used in MSC configuration (SIUL2_MSCR_IO_n.ODC=100).

2. The MSC and DSPI LVDS pad electrical characteristics are based on the application circuit and typical worst case internal

capacitance values given in Figure 12

.

3. All MSC and DSPI LVDS pad electrical characteristics are valid from -40 °C to 165 °C.

4. Valid for maximum data rate f

Figure 12

.

DATA

. Value given is the capacitance on each terminal of the differential pair, as shown in

5. Valid for maximum external load C

L

.

6. The transition time is measured from 10% to 90% of the voltage transition from -| Δ VOD|(min) to +| Δ VOD|(min).

Table 35. MSC LVDS transmitter electrical characteristics for LFAST pads.

(1),(2),(3)

Value

Symbol C Parameter Conditions

Min Typ Max

Unit

I f

DATA

| Δ

V t

OS

VOD

TR

C

L

|

LVDS_TX

I

PIN_TX

SR D

CC P

CC P

CC T

Data rate

Common mode voltage

Differential output voltage swing

(terminated)

(4),(5)

Rise time from -| Δ VOD(min)| to

+| Δ VOD(min)|. Fall time from

+| Δ VOD(min)| to -| Δ VOD(min)|

(6)

—

—

—

—

SR D

External lumped differential load capacitance

(4)

CC C Transmitter DC current consumption

CC D

Transmitter DC current sourced through output pin

V

DD_HV_IO

= 4.5 V

V

DD_HV_IO

= 3.0 V

Enabled

—

—

1.08

120

0.26

—

—

—

1.5

—

—

—

—

—

—

—

320

1.32

400

1.4

12.0

8.5

5.0

4.0

Mbps

V mV ns pF mA mA

1. This table is applicable to LFAST LVDS pads used in MSC configuration (SIUL2_MSCR_IO_n.ODC=100).

2. The MSC and DSPI LVDS pad electrical characteristics are based on the application circuit and typical worst case internal capacitance values given in

Figure 12

.

72/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

3. All MSC and DSPI LVDS pad electrical characteristics are valid from -40 °C to 165 °C.

4. Valid for maximum data rate f

Figure 12 .

DATA

. Value given is the capacitance on each terminal of the differential pair, as shown in

5. Valid for maximum external load C

L

.

6. The transition time is measured from 10% to 90% of the voltage transition from -| Δ VOD|(min) to +| Δ VOD|(min).

Figure 12. LVDS pad external load diagram

Die Package PCB

GPIO Driver

1pF C

L

2.5pF

LVDS Driver

100 Ω terminator

GPIO Driver

1pF C

L

2.5pF

Symbol f

RF_REF

ERR

REF

The following table contains the electrical characteristics for the LFAST PLL.

Table 36. LFAST PLL electrical characteristics

(1)

Value

C Parameter Conditions

SR D PLL reference clock frequency (CLKIN)

CC D PLL reference clock frequency error

—

—

Min

10

(2)

-1

Typ

—

—

Unit

Max

30 MHz

1 %

DS11646 Rev 4 73/154

74

Electrical characteristics SPC58EEx, SPC58NEx

Symbol C

Table 36. LFAST PLL electrical characteristics (1) (continued)

Value

Parameter Conditions

Min Typ

Unit

Max

DC

REF

CC D PLL reference clock duty cycle (CLKIN) — 30 — 70 %

PN CC D

Integrated phase noise (single side band) f

RF_REF

= 20 MHz — — -58 dBc f

VCO t

LOCK

CC P

CC D

PLL VCO frequency

PLL phase lock

—

—

312

—

—

—

320

150

(3)

(4)

MHz

µs

Δ PER

REF

SR

T

T

Input reference clock jitter (peak to peak) f

Single period,

RF_REF

= 20 MHz f

Long term,

RF_REF

= 20 MHz

—

—

-500

—

—

350

500 ps ps

Δ PER

EYE

CC T Output Eye Jitter (peak to peak)

(5)

— — 400 ps

1. The specifications in this table apply to both the interprocessor bus and debug LFAST interfaces.

2. If the input frequency is lower than 20 MHz, it is required to set a input division factor of 1.

3. The 320 MHz frequency is achieved with a 20 MHz reference clock.

4. The total lock time is the sum of the coarse lock time plus the programmable lock delay time 2 clock cycles of the peripheral bridge clock that is connected to the PLL on the device (to set the PLL enable bit).

5. Measured at the transmitter output across a 100 Ω termination resistor on a device evaluation board. See

Figure 12 .

74/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

3.15 Aurora LVDS electrical characteristics

Note:

The following table describes the Aurora LVDS electrical characteristics.

The Aurora interface is AC coupled, so there is no common-mode voltage specification

.

Table 37. Aurora LVDS electrical characteristics

(1),(2)

Value

Symbol C Parameter Conditions Unit

Min Typ Max

Transmitter

F

TX

CC D Transmit Data Rate

|Δ V

OD_LVDS

| CC T

Differential output voltage swing

(terminated) (3) t

TR_LVDS

R

V_L_Tx

T

Loss

CC T Rise/Fall time (10%–90% of swing)

SR D Differential Terminating resistance

CC D

Transmission Line Loss due to loading effects

—

—

—

—

—

—

±400

60

81

—

— 1.25 Gbps

±600 ±800

—

100

— 6

—

120

(4) mV ps

W dB

C

C

L

Z

AC_CLK

AC_TX

|Δ

F

LINE

LINE

V

RX

I_L

|

Transmission line characteristics (PCB track)

SR D Transmission line length —

SR D

Transmission line characteristic impedance

—

SR D

SR D

Clock Receive Pin External AC

Coupling Capacitance

Transmit Lane External AC Coupling

Capacitance

Values are nominal, valid for +/-50% tolerance

Values are nominal, valid for +/-50% tolerance

Receiver

CC

D

Receive Clock Rate

D

SR T

Differential input voltage (peak to peak)

T

T

J

J

= 150 °C

= 165 °C

—

—

45

100

250

—

—

200

—

50

—

—

—

—

—

20

55

270

2000

1.25

1

1000

R

V_L_Rx

CC D Differential Terminating resistance — 81 100 120

1. All Aurora electrical characteristics are valid from –40 °C to 150 °C, except where noted.

2. All specifications valid for maximum transmit data rate F

TX

.

3. The minimum value of 400 mV is only valid for differential terminating resistance (R differential output voltage swing tracks with the value of R

V_L

.

V_L

) = 99 ohm to 101 ohm. The

4. Transmission line loss maximum value is specified for the maximum drive level of the Aurora transmit pad.

cm

W pF pF

Gbps mV

W

DS11646 Rev 4 75/154

75

Electrical characteristics SPC58EEx, SPC58NEx

The power management module monitors the different power supplies as well as it generates the required internal supplies. The device can operate in the following configurations:

Device

External regulator

(1)

Table 38. Power management regulators

Internal

SMPS regulator

(2)

Internal linear regulator external ballast

Internal linear regulator internal ballast

Auxiliary regulator

(3)

Clamp regulator

(3)

Internal standby regulator

(4)

SPC58NE84E7

SPC58NE84C3

SPC58NE84H0

X

X

X

X

—

X

—

X

X

—

—

—

—

X

X

—

X

X

—

X

X

1. The application can select between the internal or external regulator mode, by controlling the EXTREG_SEL pin of the device. If EXTREG_SEL is connected to VDD_HV_IO_MAIN, the external regulator mode is selected.

2. Parts with SMPS enabled can only be used in this mode and EXTREG_SEL has to be set to V

SS

.

3. In external regulator mode, the auxiliary and clamp regulators can be optionally enabled, to support the compensation of overshoots and undershoots in the supply. In internal regulator mode, the auxiliary and clamp regulators are always active.

In SMPS regulator mode, the auxiliary and clamp regulators cannot be enabled. In parts packaged with LQFP176, the auxiliary and clamp regulators cannot be enabled.

4. Standby regulator is automatically activated when the device enters standby mode. Standby mode is not supported if the device operates in External regulator mode or SMPS regulator mode. Emulation Device calibration and trace features are not supported in standby mode.

Use the integration schemes provided below to ensure the proper device function, according to the selected regulator configuration.

The internal regulators are supplied by V

DD_HV_IO_MAIN

V

DD_LV

supply.

supply and are used to generate

Place capacitances on the board as near as possible to the associated pins and limit the serial inductance of the board to less than 5 nH.

It is recommended to use the internal regulators only to supply the device itself.

76/154 DS11646 Rev 4

SPC58EEx, SPC58NEx

Figure 13. External regulator mode

Electrical characteristics

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DS11646 Rev 4 77/154

87

Electrical characteristics SPC58EEx, SPC58NEx

Figure 14. Internal regulator with external ballast mode

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966

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78/154 DS11646 Rev 4

SPC58EEx, SPC58NEx

Figure 15. SMPS Regulator Mode

Electrical characteristics

Note: Refer to the device pinout IO definition excel file for the list of available PMU control pins for each device and package.

DS11646 Rev 4 79/154

87

Electrical characteristics

9''B+9

SPC58EEx, SPC58NEx

Figure 16. Standby regulator with external ballast mode

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966

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Symbol

C

E

R

E

C

LVn

R

LVn

C

BV

C

Table 39. External components integration

Parameter Conditions

(1)

Min

Value

Typ Max

Unit

Common Components

SR D

Internal voltage regulator stability external capacitance.

(2) (3)

SR D

Stability capacitor equivalent serial resistance

Total resistance including board track

SR D

SR D

Internal voltage regulator decoupling external capacitance

(2)

(4) (5)

Stability capacitor equivalent serial resistance

Each V

DD_LV

/V

—

SS

pair

SR D Bulk capacitance for HV supply

(2)

on one V

DD_HV_IO_MAIN

V

SS

pair

/

— 2 × 2.2

—

—

—

—

—

—

47

—

4.7

50

—

50

—

µF m Ω nF m Ω

µF

80/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Table 39. External components integration (continued)

C

C

C

Symbol

HVn

FLA

ADC

C Parameter Conditions

(1)

Min

SR D

SR D

SR D

Decoupling capacitance for

ballast and IOs

(2)

Decoupling capacitance for Flash supply

(6) on all V

DD_HV_IO

V

DD_HV_ADR

/V

SS

/V

SS

and

pairs

—

ADC supply external capacitance

(2)

V

DD_HV_ADV/ pair.

V

SS_HV_ADV

Internal Linear Regulator with External Ballast Mode

—

—

—

Value

Typ

100

10

2.2

Max

—

—

—

Unit nF nF

µF

Q

EXT

SR D

Recommended external NPN transistors

NJD2873T4, BCP68

V

Q

SR D

External NPN transistor collector voltage

— 2.0

—

V

DD_

HV_IO

_MAIN

V

C

R

B

B

SR D

Internal voltage regulator stability external capacitance on ballast

base (4)

(7)

SR D

Stability capacitor equivalent serial resistance

—

Total resistance including board track

—

—

2.2

—

—

50

µF m Ω

C

S2

SMPS Regulator Mode

Common Configuration (8)

PMOS

NMOS

SR D

SR D

Recommended PMOS transistor for SMPS mode

Recommended NMOS transistor for SMPS mode

SR D

SMPS External capacitance on

HV supply

(2)

PMPB100XPEA

PMPB55XNEA

— -50% 47

(9)

+35% µF

Option A

C

S1_A

SR D

SMPS External capacitance on

LV supply

(2)

SR D SMPS External inductance

— -50% 2 × 10 +35% µF

L

S_A

Option B

— -30% 10 +30% µH

C

S1_B

SR D

SMPS External capacitance on

LV supply

(10)

— -35% 3 × 10 +35% µF

L

S_B

SR D SMPS External inductance — -30% 4.7

+30%

1. V

DD

= 3.3 V ± 10% / 5.0 V ± 10%, T

J

= –40 / 165 °C, unless otherwise specified.

2. Recommended X7R or X5R ceramic –50% / +35% variation across process, temperature, voltage and after aging.

3. CE capacitance is required both in internal and external regulator mode.

4. For noise filtering, add a high frequency bypass capacitance of 10 nF.

5. For BGA and KGD applications it is recommended to implement at least 5 C

LV

capacitances.

6. Recommended X7R capacitors. For noise filtering, add a high frequency bypass capacitance of 100 nF.

µH

DS11646 Rev 4 81/154

87

Electrical characteristics SPC58EEx, SPC58NEx

7. CB capacitance is required if only the external ballast is implemented.

8. The application has to implement one of the two recommended combinations of external components for the SMPS regulator:

PMOS, NMOS and CS2 (common), plus CS1_A and LS_A (option A), or

PMOS, NMOS and CS2 (common), plus CS1_B and LS_B (option B).

9. The value of the capacitance on the HV supply reported in the datasheet is a general recommendation. The application can select a different number, based on the external regulator and emc requirements.

10. Recommended X7R or X5R ceramic –35% / +35% variation across process, temperature, voltage and after aging.

82/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Table 40. Linear regulator specifications

Symbol C Parameter Conditions

Min

Value

Typ Max

Unit

V

MREG

CC P

Main regulator output voltage

CC P

Main regulator current provided to

V

DD_LV

domain

Power-up, before trimming, no load

After trimming, maximum load

1.12

1.08

1.20

1.18

1.28

1.23

V

IDD

IDD

MREG

CLAMP

CC T

CC D

The maximum current required by the device (I

DD_LV

) may exceed the maximum current which can be provided by the internal linear regulator. In this case, the internal regulator mode cannot be used.

Main regulator rush current sinked from V

DD_HV_IO_MAIN domain during V

DD_LV loading

domain

—

Power-up condition

—

—

—

—

700

400 mA mA

Δ IDD

CC T

Main regulator output current variation

20 µs observation window

-200 — 200 mA

I

MREGINT

CC

D Main regulator current

D consumption

I

MREG

= max

I

MREG

= 0 mA

—

—

—

—

22

— mA

1. Internal schemes must be used by the application (for example: frequency ramping feature enabled) to ensure that incremental demands are made on the external power supply within the maximum value. Mbist/Lbist must be configured to avoid exceeding the maximum value.

Symbol

V

AUX

IDD

AUX

Δ IDD

AUX

I

AUXINT

Table 41. Auxiliary regulator specifications

C Parameter Conditions

Min

Value

Typ Max

Unit

CC P

CC P

Aux regulator output voltage

After trimming, internal regulator mode

After trimming, external regulator mode

CC T

Aux regulator current provided to

V

DD_LV

domain

CC T Aux regulator current variation

CC

D Aux regulator current

D consumption

—

20 µs observation window

I

MREG

= max

I

MREG

= 0 mA

1.08

1.03

—

—100

—

—

1.18

1.12

—

—

—

—

1.21

1.16

250

100

1.1

1.1

V mA mA mA

DS11646 Rev 4 83/154

87

Electrical characteristics SPC58EEx, SPC58NEx

Table 42. Clamp regulator specifications

Symbol C Parameter Conditions

Min

Value

Typ Max

Unit

V

CLAMP

CC P

CC P

Clamp regulator output voltage

Δ IDD

CLAMP

CC T Clamp regulator current variation

After trimming, internal regulator mode

After trimming, external regulator mode

20 µs observation window

I

CLAMPINT

CC D

Clamp regulator current consumption

I

MREG

= 0 mA

1.17

1.24

—100

—

1.21

1.28

—

—

1.32

1.39

100

0.7

V mA mA

Symbol C

Table 43. Standby regulator specifications

Parameter Conditions

V

SBY

IDD

SBY

CC P Standby regulator output voltage

After trimming, maximum load

CC T

Standby regulator current provided to V

DD_LV

domain

—

Min

Value

Typ Max

Unit

1.02

1.06

1.26

V

— — 50 mA

Table 44. SMPS Regulator specifications

Value

Symbol C Parameter Conditions Unit

Min Typ Max

V

DD_HV_IO

V

δ V

F

SMPS

SMPS

SMPS

SR P

CC T

SMPS Regulator Supply

Voltage

(1)

CC P SMPS regulator output voltage

CC T

SMPS regulator output voltage tolerance

SMPS regulator switching frequency

—

After trimming, max load after trimming, < 20 µs observation window

—

4.5

1.14

-5%

-5%

—

1.20

—

727

5.5

1.26

+5%

+5%

V

V

— kHz

IDD

IDD

SMPS

CLAMP

CC T

CC D

SMPS regulator current provided to V

DD_LV

domain

SMPS regulator rush current sinked from VDD_HV_IO_MAIN domain during VDD_LV domain loading

—

Power-up condition

—

—

—

—

1000

400 mA mA

Δ IDD

CC T SMPS regulator current variation

20 µs observation window

-200 — 200

1. SMPS regulator is functional in the range 2.85 V < V

DD_HV_IO

< 4.5 V, but at a reduced efficiency.

2. Internal schemes must be used by the application (eg frequency ramping feature enable) to ensure that incremental demands are made on the external power supply within the maximum value. Mbist/Lbist must be configured to avoid exceeding the maximum value.

mA

84/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

The monitors and their associated levels for the device are given in Table 45 . Figure 17

illustrates the workings of voltage monitoring threshold.

Figure 17. Voltage monitor threshold definition

V

DD_xxx

V

HVD

V

LVD

T

VMFILTER

T

VMFILTER

HVD TRIGGER

(INTERNAL)

T

VMFILTER

T

VMFILTER

LVD TRIGGER

(INTERNAL)

Symbol C

Table 45. Voltage monitor electrical characteristics

Supply/Parameter

(1)

Conditions

Min

Value

(2)

Typ Max

Unit

V

V

MVD270_C

V

MVD270_F

V

MVD270_SBY

V

POR200_C

LVD290_C

PowerOn Reset HV

CC P V

DD_HV_IO_MAIN

—

Minimum Voltage Detectors HV

CC P V

DD_HV_IO_MAIN

CC P V

DD_HV_FLA

CC P V

DD_HV_IO_MAIN

(in Standby)

Low Voltage Detectors HV

—

—

—

CC P V

DD_HV_IO_MAIN

—

1.80

2.71

2.71

2.71

2.89

2.18

2.76

2.76

2.76

2.94

2.40

2.80

2.80

2.80

2.99

V

V

V

V

V

DS11646 Rev 4 85/154

87

Electrical characteristics SPC58EEx, SPC58NEx

V

LVD290_F

V

LVD290_AD

V

LVD290_AS

V

LVD290_IJ

V

LVD290_IF

V

LVD400_AD

V

LVD400_AS

V

LVD400_IM

V

LVD400_IJ

V

LVD400_IF

Symbol

V

HVD400_C

V

HVD400_IJ

V

HVD400_IF

V

UVD600_C

V

UVD600_F

V

UVD600_IJ

V

UVD600_IF

V

POR031_C

V

MVD082_C

V

MVD082_B

V

MVD094_C

V

MVD094_FA

V

MVD094_FB

V

LVD100_C

V

LVD100_SB

V

LVD100_F

V

HVD134_C

Table 45. Voltage monitor electrical characteristics (continued)

Value (2)

C Supply/Parameter

(1)

Conditions

Min Typ

CC P V

DD_HV_FLA

CC P V

DD_HV_ADV

(ADCSD pad)

CC P V

DD_HV_ADV

(ADCSAR pad)

CC P V

DD_HV_IO_JTAG

CC P V

DD_HV_IO_FLEX

—

—

—

—

—

CC P V

DD_HV_ADV

(ADCSD pad)

CC P V

DD_HV_ADV

(ADCSAR pad)

CC P V

DD_HV_IO_MAIN

CC P V

DD_HV_IO_JTAG

CC P V

DD_HV_IO_FLEX

High Voltage Detectors HV

—

—

—

—

CC P V

DD_HV_IO_MAIN

CC P V

DD_HV_IO_JTAG

CC P V

DD_HV_IO_FLEX

—

Upper Voltage Detectors HV

CC P V

DD_HV_IO_MAIN

CC P V

DD_HV_FLA

CC P V

DD_HV_IO_JTAG

CC P V

DD_HV_IO_FLEX

—

—

—

PowerOn Reset LV

CC P V

DD_LV

—

CC P V

DD_LV

CC P V

DD_LV_BD

CC P V

DD_LV

CC P V

DD_LV

(Flash)

CC P V

DD_LV

(Flash)

Minimum Voltage Detectors LV

—

—

—

—

—

CC P V

DD_LV

Low Voltage Detectors LV

CC P V

DD_LV

CC P V

DD_LV

(In Standby)

CC P V

DD_LV

(Flash)

High Voltage Detectors LV

—

—

—

—

2.89

2.89

2.89

2.89

2.89

4.15

4.15

4.15

4.15

4.15

3.68

3.68

3.68

5.72

5.72

5.72

5.72

0.29

0.85

0.85

0.98

1.00

1.00

1.06

0.99

1.08

1.28

3.75

3.75

3.75

0.60

0.88

0.88

1.00

1.02

1.02

5.82

5.82

5.82

5.82

1.08

1.01

1.10

1.31

2.94

2.94

2.94

2.94

2.94

4.23

4.23

4.23

4.23

4.23

Max

2.99

2.99

2.99

2.99

2.99

4.31

4.31

4.31

4.31

4.31

3.82

3.82

3.82

5.92

5.92

5.92

5.92

0.97

0.91

0.91

1.02

1.04

1.04

1.11

1.03

1.12

1.33

Unit

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

86/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Symbol

Table 45. Voltage monitor electrical characteristics (continued)

Value (2)

C Supply/Parameter

(1)

Conditions

Min Typ

Unit

Max

Upper Voltage Detectors LV

V

UVD140_C

V

UVD140_F

CC P V

DD_LV

CC P V

DD_LV

(Flash)

—

—

1.34

1.34

1.37

1.37

1.39

1.39

V

V

Common

T

VMFILTER

CC D Voltage monitor filter (3) — 5 — 25

1. Even if LVD/HVD monitor reaction is configurable, the application ensures that the device remains in the operative condition range, and the internal LVDx monitors are disabled by the application. Then an external voltage monitor with minimum threshold of VDD_LV(min) = 1.08 V measured at the device pad, has to be implemented.

For HVDx, if the application disables them, then they need to grant that VDD_LV and VDD_HV voltage levels stay withing the limitations provided in

Section 3.2: Absolute maximum ratings .

2. The values reported are Trimmed values, where applicable.

3. See

Figure 17

. Transitions shorter than minimum are filtered. Transitions longer than maximum are not filtered, and will be delayed by T

VMFILTER time. Transitions between minimum and maximum can be filtered or not filtered, according to temperature, process and voltage variations.

μ s

DS11646 Rev 4 87/154

87

Electrical characteristics SPC58EEx, SPC58NEx

The following table shows the Wait State configuration.

APC

000

(1)

100

(2)

001

(3)

Table 46. Wait State configuration

RWSC Frequency range (MHz)

5

2

3

4

5

5

0

3

4

1

2

3

4

0

1

2 f<30 f<60 f<90 f<120 f<150 f<180 f<30 f<60 f<90 f<120 f<150 f<180

55<f<80

55<f<120

55<f<160

55<f<180

1. STD pipelined, no address anticipation.

2. No pipeline (STD + 1 Tck).

3. Pipeline with 1 Tck address anticipation.

Symbol

The following table shows the Program/Erase Characteristics.

Table 47. Flash memory program and erase specifications

Value

Characteristics

(1)(2)

Typ

(3)

C

Initial max

25 °C

(6)

All temp

(7)

C

Lifetime max

(5)

Typical end of life

(4)

< 1 K cycles

< 250 K cycles

C

Unit t dwprogram t pprogram

Double Word (64 bits) program time EEPROM

(partitions 2, 3, 4) [KGD]

55 C 130

Page (256 bits) program time 76 C 240

— — 140

— — 255

650

1000

C µs

C µs

88/154 DS11644 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Symbol

Table 47. Flash memory program and erase specifications

Value

Characteristics

(1)(2)

Typ

(3)

C

Initial max

25 °C

(6)

All temp

(7)

C

Lifetime max

(5)

Typical end of life

(4)

< 1 K cycles

< 250 K cycles

C

Unit t t t t t t t pprogrameep t qprogram qprogrameep

16kpperase

32kpperase

64kpperase

128kpperase

256kpperase

Page (256 bits) program time

EEPROM (partitions 2, 3, 4)

[KGD]

Quad Page (1024 bits) program time

Quad Page (1024 bits) program time EEPROM

(partitions 2, 3, 4) [KGD]

16 KB block pre-program and erase time

32 KB block pre-program and erase time

64 KB block pre-program and erase time

128 KB block pre-program and erase time

256 KB block pre-program and erase time t t t t

16kprogram t

32kprogram t

64kprogram

128kprogram

256kprogram t

64kprogrameep

64keraseeep

16 KB block program time

32 KB block program time

64 KB block program time

128 KB block program time

256 KB block program time

Program 64 KB EEPROM

(partition 2,3) [KGD]

Erase 64 KB EEPROM

(partition 2,3) [KGD] t

16kprogrameep t

16keraseeep t t t prr err prfm

Program 16 KB EEPROM

(partition 4) [KGD]

Erase 16 KB EEPROM

(partition 4) [KGD]

Program rate (8)

Erase rate

(8)

Program rate Factory

Mode

(8)

90

220

306

190

250

360

600

1050 C 1800 2400 P 1600 4000

25

50

102

205

410

120

530

30

225

1.7

4.8

1.12

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

300

840

1200

450

520

700

1300

45

90

175

350

700

200

910

52

645

2.8

7.2

1.4

—

1200

1800

500

600

750

1600

300

1150

75

715

3.40

9.6

1.6

—

P

P

P

P

P

P

50 P

100 P

P

P

P

P

C

C

C

315

850

1270

250

310

420

800

40

75

200 P 150

430 P 300

850 P 590

330

1040

84

520

2.4

6.4

—

1000

1200

1600

4000

1000

1200

1600

2000

4000

1300

2000

2600

2275

4700

2275

4700

—

—

—

—

—

—

—

—

—

—

—

—

—

C µs

C µs

C µs

C ms

C ms

C ms

C ms

C ms

C ms

C ms

C ms

C ms

C ms

C ms

C ms

C ms

C ms

C s/MB

C s/MB

C s/MB

DS11644 Rev 4 89/154

91

Electrical characteristics SPC58EEx, SPC58NEx

Table 47. Flash memory program and erase specifications

Value

Symbol Characteristics

(1)(2)

Typ

(3)

C

Initial max

25 °C

(6)

All temp

(7)

C

Lifetime max

(5)

Typical end of life

(4)

< 1 K cycles

< 250 K cycles

C

Unit t t t t t t t t t t t t t erfm ffprogram fferase

ESRT

PSRT

AMRT

PSUS

ESUS

AIC0S

AIC256KS

AIC0P

MR0S

MR256KS

Erase rate Factory Mode

(8)

Full flash programming time

(9)

Full flash erasing time

(9)

Erase suspend request rate

(10)

Program suspend request rate

(10)

Array Integrity Check -

Margin Read suspend request rate

Program suspend latency

(11)

Erase suspend latency

(11)

Array Integrity Check (6.0

MB, sequential)

(12)

Array Integrity Check (256

KB, sequential)

(12)

Array Integrity Check (6.0

MB, proprietary)

(12)

Margin Read (6.0 MB,

sequential)

(12)

Margin Read (256 KB,

sequential)

(12)

4.0

12.0

25.0

200

30

15

—

—

40

1.5

4.0

120

4.0

C

C

C

T

T

T

—

—

T

T

T

T

T

5.2

17.8

40.0

—

—

—

—

—

—

—

—

—

—

5.8

22.0

50.0

—

—

—

—

—

—

—

—

—

—

C

P

P

—

—

—

—

—

—

—

—

—

—

—

15.4

40.0

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

12

22

—

—

—

—

—

—

—

C s/MB

C

C

— µs

— µs

— µs

T

T

µs

µs

— ms

— ms

— s s

— ms

— ms

1. Characteristics are valid both for Data Flash and Code Flash, unless specified in the characteristics column.

2. Actual hardware operation times; this does not include software overhead.

3. Typical program and erase times assume nominal supply values and operation at 25 °C.

4. Typical End of Life program and erase times represent the median performance and assume nominal supply values.

Typical End of Life program and erase values may be used for throughput calculations. These values are characteristic, but not tested.

5. Lifetime maximum program & erase times apply across the voltages and temperatures and occur after the specified number of program/erase cycles. These maximum values are characterized but not tested or guaranteed.

6. Initial factory condition: < 100 program/erase cycles, 25 °C typical junction temperature and nominal (± 5%) supply voltages.

7. Initial maximum “All temp” program and erase times provide guidance for time-out limits used in the factory and apply for less than or equal to 100 program or erase cycles, –40 °C < TJ < 150 °C junction temperature and nominal (± 5%) supply voltages.

8. Rate computed based on 256 KB sectors.

9. Only code sectors, not including EEPROM.

10. Time between suspend resume and next suspend. Value stated actually represents Min value specification.

s

90/154 DS11644 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

11. Timings guaranteed by design.

12. AIC is done using system clock, thus all timing is dependent on system frequency and number of wait states. Timing in the table is calculated at max frequency.

All the Flash operations require the presence of the system clock for internal synchronization. About 50 synchronization cycles are needed: this means that the timings of the previous table can be longer if a low frequency system clock is used.

Symbol

Table 48. Flash memory Life Specification

Value

Characteristics

(1) (2)

Min C Typ C

Unit

N

CER16K

N

CER32K

N

CER64K

N

CER128K

16 KB CODE Flash endurance

32 KB CODE Flash endurance

64 KB CODE Flash endurance

N

CER256K

128 KB CODE Flash endurance

256 KB CODE Flash endurance

256 KB CODE Flash endurance

(3)

N

DER64K

N

DER16K

64 KB DATA EEPROM Flash endurance

16 KB HSM DATA EEPROM Flash endurance t

DR1k t

DR10k t

DR100k

Minimum data retention Blocks with 0 - 1,000 P/E cycles

Minimum data retention Blocks with 1,001 - 10,000

P/E cycles

Minimum data retention Blocks with 10,001 - 100,000

P/E cycles t

DR250k

Minimum data retention Blocks with 100,001 -

250,000 P/E cycles

10 — 100 — Kcycles

10 — 100 — Kcycles

10 — 100 — Kcycles

1 — 100 — Kcycles

1 — 100 — Kcycles

10 — 100 — Kcycles

250 — — — Kcycles

100 — — — Kcycles

25 —

20 —

15 —

10 —

—

—

—

—

— Years

— Years

— Years

— Years

1. Program and erase cycles supported across specified temperature specifications.

2. It is recommended that the application enables the core cache memory.

3. 10K cycles on 4-256 KB blocks is not intended for production. Reduced reliability and degraded erase time are possible.

DS11644 Rev 4 91/154

91

Electrical characteristics SPC58EEx, SPC58NEx

All AC timing specifications are valid up to 150 °C, except where explicitly noted.

3.18.1 Debug and calibration interface timing

Table 49. JTAG pin AC electrical characteristics

Value

(1) , (2)

# Symbol C Characteristic Unit

Min Max

1

2 t

JCYC t

JDC

3 t

TCKRISE

4 t

TMSS, t

TDIS

5 t

TMSH, t

TDIH

6 t

TDOV

7

8

9

10 t

TDOI t

TDOHZ t

JCMPPW t

JCMPS

11

12

13

14

15 t

BSDV t

BSDVZ t

BSDHZ t

BSDST t

BSDHT

CC D TCK cycle time

CC T TCK clock pulse width

CC D TCK rise and fall times (40%–70%)

CC D TMS, TDI data setup time

CC D TMS, TDI data hold time

CC D TCK low to TDO data valid

CC D TCK low to TDO data invalid

CC D TCK low to TDO high impedance

CC D JCOMP assertion time

CC D JCOMP setup time to TCK low

CC D TCK falling edge to output valid

CC D TCK falling edge to output valid out of high impedance

CC D TCK falling edge to output high impedance

CC D Boundary scan input valid to TCK rising edge

CC D TCK rising edge to boundary scan input invalid

100

40

—

5

5

—

0

—

100

40

—

—

—

15

15

—

60

3

—

—

15

(3)

—

15

—

—

600

(4)

600

600

—

— ns

% ns ns ns ns ns ns ns ns ns ns ns ns ns

1. These specifications apply to JTAG boundary scan only. See Table 50

for functional specifications.

2. JTAG timing specified at V

DD_HV_IO_JTAG datasheet.

= 4.0 to 5.5 V and max. loading per pad type as specified in the I/O section of the

3. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.

4. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.

92/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Figure 18. JTAG test clock input timing

TCK

3

2

1 3

Figure 19. JTAG test access port timing

2

TCK

4

TMS, TDI

6

7 8

TDO

DS11646 Rev 4 93/154

128

Electrical characteristics

Figure 20. JTAG JCOMP timing

SPC58EEx, SPC58NEx

TCK

JCOMP

10

9

Figure 21. JTAG boundary scan timing

TCK

11 13

Output

Signals

12

Output

Signals

14

15

Input

Signals

94/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

3.18.1.2 Nexus interface timing

Table 50. Nexus debug port timing

#

9

11

14 t

15

16 t t

Symbol

7 t

EVTIPW

8 t

EVTOPW

TCYC

NTDIS

12 t

NTDIH

13 t

NTMSS

NTMSH

—

—

C Characteristic

CC D EVTI pulse width

CC D EVTO pulse width

CC D

TCK cycle time

Absolute minimum TCK cycle time (5) (TDO sampled on posedge of TCK)

Absolute minimum TCK cycle time

(7)

(TDO sampled on negedge of TCK)

CC D TDI data setup time

CC D TDI data hold time

CC D TMS data setup time

CC D TMS data hold time

CC D TDO propagation delay from falling edge of TCK

(8)

CC D

TDO hold time with respect to TCK falling edge (minimum TDO propagation delay)

Value

(1)

Min Max

4

40

2

(3),(4)

60

30

5

5

5

5

(6)

(6)

—

2.25

— t

—

— t

—

—

—

—

—

—

25

—

Unit

CYC

(2) ns

CYC

(2)

ns ns

1. Nexus timing specified at V section of the data sheet.

DD_HV_IO_JTAG

= 3.0 V to 5.5 V, and maximum loading per pad type as specified in the I/O

2. t

CYC

is system clock period.

3. Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual peripheral frequency being used. To ensure proper operation TCK frequency should be set to the peripheral frequency divided by a number greater than or equal to that specified here.

4. This is a functionally allowable feature. However, it may be limited by the maximum frequency specified by the Absolute minimum TCK period specification.

5. This value is TDO propagation time 36 ns + 4 ns setup time to sampling edge.

6. This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system frequency being used.

7. This value is TDO propagation time 16 ns + 4 ns setup time to sampling edge.

8. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.

ns ns ns ns ns

DS11646 Rev 4 95/154

128

Electrical characteristics SPC58EEx, SPC58NEx

Figure 22. Nexus event trigger and test clock timings

TCK

EVTI

EVTO

9

TCK

EVTI

EVTO

9 7

8

Figure 23. Nexus TDI, TMS, TDO timing

7

8

TCK

11

13

12

14

TMS, TDI

16

15

TDO

96/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

3.18.1.3 Aurora LVDS interface timing

Symbol C

Table 51. Aurora LVDS interface timing specifications

Value

Parameter

Min Typ

Unit

Max

Data Rate

— SR T Data rate — — 1250 Mbps

STARTUP t

STRT_BIAS t

STRT_TX t

STRT_RX

CC T Bias startup time

CC T

(1)

CC T Transmitter startup time

Receiver startup time (3)

(2)

—

—

—

—

—

—

5

5

4

µs

µs

µs

1. Startup time is defined as the time taken by LVDS current reference block for settling bias current after its pwr_down (power down) has been deasserted. LVDS functionality is guaranteed only after the startup time.

2. Startup time is defined as the time taken by LVDS transmitter for settling after its pwr_down (power down) has been deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality is guaranteed only after the startup time.

3. Startup time is defined as the time taken by LVDS receiver for settling after its pwr_down (power down) has been deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality is guaranteed only after the startup time.

3.18.1.4 Aurora debug port timing

Table 52. Aurora debug port timing

# Symbol C Characteristic Unit

3

4

5

1

1a

2

6

7

8

9

10 t

REFCLK t

MCYC t

RCDC

J

RC t

STABILITY

BER

J

D

J

T

S

O

S

MO

OUI

1. ± +/-100 PPM

CC T Reference clock frequency

CC T Reference clock rise/fall time

CC D Reference clock duty cycle

CC D Reference clock jitter

CC D Reference clock stability

CC D Bit error rate

SR D Transmit lane deterministic jitter

SR D Transmit lane total jitter

CC T Differential output skew

CC T Lane to lane output skew

D

CC Aurora lane unit interval

(1)

D

625 Mbps

1.25 Gbps

Min

—

50

—

625

—

45

—

—

—

—

1600

800

Value

Max

0.17

0.35

20

1000

1600

800

1250

400

55

40

—

10

–12

MHz ps

% ps

PPM

—

OUI

OUI ps ps ps

DS11646 Rev 4 97/154

128

Electrical characteristics SPC58EEx, SPC58NEx

Figure 24. Aurora timings

CLOCK

REF

-

Zero Crossover

CLOCK

REF

+

1a

Tx Data

-

Ideal Zero Crossover

Tx Data

+

8

2

1a

1

1a

8

1a

2

8

Tx Data [n]

Zero Crossover

Tx Data [n+1]

Zero Crossover

Tx Data [m]

Zero Crossover

9 9

3.18.1.5 External interrupt timing (IRQ pin)

Characteristic

Table 53. External interrupt timing

Symbol Min

IRQ Pulse Width Low

IRQ Pulse Width High

IRQ Edge to Edge Time

(1) t

IPWL t

IPWH t

ICYC

3

3

6

1. Applies when IRQ pins are configured for rising edge or falling edge events, but not both.

Max

—

—

—

Unit t cyc t cyc t cyc

98/154 DS11646 Rev 4

SPC58EEx, SPC58NEx

Figure 25. External interrupt timing

Electrical characteristics

IRQ

1 2

3

Figure 26. External interrupt timing

D_CLKOUT

4

IRQ

1

3

2

Note: DSPI in TSB mode with LVDS pads can be used to implement Micro Second Channel bus protocol.

DSPI channel frequency support is shown in Table 54

.

Timing specifications are shown in the tables below.

DS11646 Rev 4 99/154

128

Electrical characteristics SPC58EEx, SPC58NEx

Table 54. DSPI channel frequency support

DSPI use mode

(1)

Max usable frequency

(MHz) (2),(3)

CMOS (Master mode)

Full duplex – Classic timing (

Table 55

Full duplex – Modified timing (

)

Table 56

)

DSPI_0, DSPI_3,

DSPI_5, DSPI_7

DSPI_8

DSPI_1, DSPI_2,

DSPI_4, DSPI_6,

DSPI_9

DSPI_0, DSPI_3,

DSPI_5, DSPI_7

DSPI_8

DSPI_1, DSPI_2,

DSPI_4, DSPI_6,

DSPI_9

12

5

17

12

5

30

Output only mode (SCK/SOUT/PCS) (

Table 55 and

Table 56

)

Output only mode TSB mode (SCK/SOUT/PCS)

LVDS (Master mode)

Full duplex – Modified timing ( Table 57

)

Output only mode TSB mode (SCK/SOUT/PCS)

(

Table 58 )

CMOS (Slave mode Full duplex) (

Table 60 )

—

—

—

—

30

30

33

40

— 16

1. Each DSPI module can be configured to use different pins for the interface. Refer to the device pinout Microsoft Excel file attached to the IO_Definition document for the available combinations. It is not possible to reach the maximum performance with every possible combination of pins.

2. Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads.

3. Maximum usable frequency does not take into account external device propagation delay.

3.18.2.1 DSPI master mode full duplex timing with CMOS and LVDS pads

3.18.2.1.1 DSPI CMOS master mode – classic timing

Note: In the following table, all output timing is worst case and includes the mismatching of rise and fall times of the output pads.

#

Table 55. DSPI CMOS master classic timing (full duplex and output only)

MTFE = 0, CPHA = 0 or 1

Condition Value

(1)

Symbol C Characteristic

Pad drive (2) Load (C

L

) Min Max

1 t

SCK

CC D SCK cycle time

SCK drive strength

Very strong 25 pF

Strong

Medium

50 pF

50 pF

59.0

80.0

200.0

—

—

—

Unit ns

100/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

#

Table 55. DSPI CMOS master classic timing (full duplex and output only)

MTFE = 0, CPHA = 0 or 1 (continued)

Condition Value (1)

Symbol C Characteristic

Pad drive

(2)

Load (C

L

) Min Max

SCK and PCS drive strength

2 t

CSC

CC D

PCS to SCK delay

Very strong

Strong

Medium

25 pF

50 pF

50 pF

(N

(3)

× t

SYS

(4)

16

) –

(N

(3)

× t

SYS

(4)

16

) –

(N

(3)

× t

SYS

(4)

16

) –

—

—

—

3 t

ASC

4 t

SDC

5 t

PCSC

6 t

PASC

7 t

SUI

CC D After SCK delay

PCS medium and SCK strong

PCS = 50 pF

SCK = 50 pF

SCK and PCS drive strength

Very strong

Strong

Medium

PCS = 0 pF

SCK = 50 pF

PCS = 0 pF

SCK = 50 pF

PCS = 0 pF

SCK = 50 pF

CC D

CC D

SCK duty cycle

(6)

PCSx to PCSS time

(7)

PCS medium and SCK strong

PCS = 0 pF

SCK = 50 pF

SCK drive strength

Very strong

Strong

Medium

0 pF

0 pF

0 pF

PCS strobe timing

PCS and PCSS drive strength

Strong 25 pF

CC D

PCSS to PCSx time

(7)

PCS and PCSS drive strength

Strong 25 pF

SIN setup time

CC D

SIN setup time to

SCK

(8)

SCK drive strength

Very strong

Strong

25 pF

50 pF

Medium 50 pF

(N

(3)

× t

SYS

(4)

29

) –

(M

(5)

× t

SYS

(4)

35

) –

(M

(5)

× t

SYS

(4)

35

) –

(M

(5)

× t

SYS

(4)

35

) –

(M

(5)

× t

SYS

(4)

35

) –

1

/

2 t

SCK

– 2

1 /

2 t

SCK

– 2

1

/

2 t

SCK

– 5

16.0

16.0

25.0

31.0

52.0

—

—

—

—

—

1

/

2 t

SCK

+ 2

1 /

2 t

SCK

+ 2

1

/

2 t

SCK

+ 5

—

—

—

—

—

Unit ns ns ns ns ns ns

DS11646 Rev 4 101/154

128

Electrical characteristics SPC58EEx, SPC58NEx

#

8

Table 55. DSPI CMOS master classic timing (full duplex and output only)

MTFE = 0, CPHA = 0 or 1 (continued)

Condition Value (1)

Symbol C Characteristic

Pad drive

(2)

Load (C

L

) Min Max

SIN hold time t

HI

9 t

SUO

10 t

HO

CC D

SIN hold time from SCK

(8)

SCK drive strength

Very strong 0 pF

Strong

Medium

0 pF

0 pF

SOUT data valid time (after SCK edge)

SOUT and SCK drive strength

CC D

SOUT data valid time from SCK

(9)

Very strong

Strong

25 pF

50 pF

CC D

SOUT data hold time after SCK

(9)

Medium 50 pF

SOUT data hold time (after SCK edge)

SOUT and SCK drive strength

Very strong

Strong

Medium

25 pF

50 pF

50 pF

–1.0

–1.0

–1.0

—

—

—

–7.7

–11.0

–15.0

—

—

—

7.0

8.0

16.0

—

—

—

Unit

1. All timing values for output signals in this table are measured to 50% of the output voltage.

2. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect operation.

3. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous

SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn).

4. t t

SYS

SYS

is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min

= 10 ns).

5. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn).

6. t

SDC

is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

7. PCSx and PCSS using same pad configuration.

8. Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL / Automotive voltage thresholds.

9. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value.

ns ns ns

102/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Figure 27. DSPI CMOS master mode — classic timing, CPHA = 0 t

CSC t

ASC

PCSx t

SDC t

SCK

SCK Output

(CPOL = 0) t

SDC

SCK Output

(CPOL = 1) t

SUI t

HI

SIN First Data

SOUT First Data

Data t

SUO

Data

Last Data t

HO

Last Data

Figure 28. DSPI CMOS master mode — classic timing, CPHA = 1

3&6[

6&.2XWSXW

&32/

6&.2XWSXW

&3 2/

6,1

6287

W

68,

W

+,

)LUVW'DWD

)LUVW'DWD

'DWD

W

682

'DWD

/DVW'DWD

W

+2

/DVW'DWD

DS11646 Rev 4 103/154

128

Electrical characteristics SPC58EEx, SPC58NEx

Figure 29. DSPI PCS strobe (PCSS) timing (master mode) t

PCSC t

PASC

PCSS

PCSx

3.18.2.1.2 DSPI CMOS master mode — modified timing

Note: In the following table, all output timing is worst case and includes the mismatching of rise and fall times of the output pads.

Table 56. DSPI CMOS master modified timing (full duplex and output only)

MTFE = 1, CPHA = 0 or 1

Value

(1)

# Symbol C Characteristic

Condition

Pad drive

(2)

Load (C

L

) Min Max

1 t

SCK

2 t

CSC

3 t

ASC

CC D SCK cycle time

CC D

PCS to SCK delay

CC D After SCK delay

SCK drive strength

Very strong 25 pF

Strong

Medium

50 pF

50 pF

SCK and PCS drive strength

Very strong 25 pF

Strong 50 pF

Medium

PCS medium and

SCK strong

50 pF

PCS = 50 pF

SCK = 50 pF

SCK and PCS drive strength

Very strong

PCS = 0 pF

SCK = 50 pF

Strong

Medium

PCS = 0 pF

SCK = 50 pF

PCS = 0 pF

SCK = 50 pF

PCS medium and

SCK strong

PCS = 0 pF

SCK = 50 pF

33.0

80.0

200.0

(N

(3)

× t

SYS

(4)

) – 16

(N

(3)

× t

SYS

(4)

) – 16

(N

(3)

× t

SYS

(4)

) – 16

(N

(3)

× t

SYS

(4)

) – 29

(M

(5)

× t

SYS

(4)

) – 35

(M

(5)

× t

SYS

(4)

) – 35

(M

(5)

× t

SYS

(4)

) – 35

(M

(5)

× t

SYS

(4)

) – 35

—

—

—

—

—

—

—

—

—

—

—

Unit ns ns ns

104/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Table 56. DSPI CMOS master modified timing (full duplex and output only)

MTFE = 1, CPHA = 0 or 1 (continued)

Condition Value (1)

# Symbol C Characteristic

Pad drive

(2)

Load (C

L

) Min Max

SCK drive strength

4 t

SDC

CC D SCK duty cycle

(6)

Very strong 0 pF

Strong 0 pF

Medium 0 pF

PCS strobe timing

1

/

2 t

SCK

– 2

1

/

2 t

SCK

– 2

1

/

2 t

SCK

– 5

1

/

2 t

SCK

+ 2

1

/

2 t

SCK

+ 2

1

/

2 t

SCK

+ 5

5 t

PCSC

6 t

PASC

7 t

SUI

8 t

HI

CC D

CC D

PCSx to PCSS time

(7)

PCSS to PCSx

time

(7)

PCS and PCSS drive strength

Strong 25 pF

PCS and PCSS drive strength

Strong 25 pF

SIN setup time

CC D

SCK drive strength

SIN setup time to

SCK

CPHA = 0

(8)

Very strong 25 pF

Strong 50 pF

Medium 50 pF

SCK drive strength

SIN setup time to

SCK

CPHA = 1

(8)

Very strong

Strong

25 pF

50 pF

Medium 50 pF

SIN hold time

SIN hold time from SCK

CPHA = 0

(8)

SCK drive strength

Very strong 0 pF

Strong 0 pF

CC D

SIN hold time from SCK

CPHA = 1

(8)

Medium 0 pF

SCK drive strength

Very strong 0 pF

Strong

Medium

0 pF

0 pF

16.0

16.0

25 – (P

(9)

× t

SYS

(4)

)

31 – (P

(9)

× t

SYS

(4)

)

52 – (P

(9)

× t

SYS

(4)

)

25.0

31.0

52.0

–1 + (P

(9)

× t

SYS

(4)

)

–1 + (P

(9)

× t

SYS

(4)

)

–1 + (P

(9)

× t

SYS

(4)

)

–1.0

–1.0

–1.0

—

—

—

—

—

—

—

—

—

—

—

—

—

—

Unit ns ns ns ns ns ns ns

DS11646 Rev 4 105/154

128

Electrical characteristics SPC58EEx, SPC58NEx

Table 56. DSPI CMOS master modified timing (full duplex and output only)

MTFE = 1, CPHA = 0 or 1 (continued)

Condition Value (1)

# Symbol C Characteristic

Pad drive

(2)

Load (C

L

) Min Max

SOUT data valid time (after SCK edge)

9 t

SUO

10 t

HO

CC D

SOUT data valid time from SCK

CPHA = 0

(10)

SOUT and SCK drive strength

Very strong

Strong

25 pF

50 pF

SOUT data valid time from SCK

CPHA = 1

(10)

Medium

Very strong

50 pF

SOUT and SCK drive strength

25 pF

Strong

Medium

50 pF

50 pF

SOUT data hold time (after SCK edge)

—

—

—

—

—

—

SOUT and SCK drive strength

Very strong 25 pF

Strong

Medium

50 pF

50 pF

CC D

SOUT data hold time after SCK

CPHA = 0

(10)

–7.7 + t

SYS

(4)

–11.0 + t

SYS

(4)

–15.0 + t

SYS

(4)

SOUT data hold time after SCK

CPHA = 1

(10)

SOUT and SCK drive strength

Very strong 25 pF

Strong 50 pF

Medium 50 pF

–7.7

–11.0

–15.0

7.0 + t

SYS

(4)

8.0 + t

SYS

(4)

16.0 + t

SYS

(4)

7.0

8.0

16.0

—

—

—

—

—

—

Unit ns ns ns ns

1. All timing values for output signals in this table are measured to 50% of the output voltage.

2. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect operation.

3. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous

SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn).

4. t t

SYS

SYS

is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min

= 10 ns).

5. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn).

6. t

SDC

is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

7. PCSx and PCSS using same pad configuration.

8. Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL / Automotive voltage thresholds.

9. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using DSPI_

MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set to 1.

106/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

10. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value.

Figure 30. DSPI CMOS master mode — modified timing, CPHA = 0 t

CSC t

ASC

PCSx t

SDC t

SCK

SCK Output

(CPOL = 0) t

SDC

SCK Output

(CPOL = 1) t

SUI t

HI

SIN

SOUT

First Data

First Data

Data t

SUO

Data

Last Data t

HO

Last Data

Figure 31. DSPI CMOS master mode — modified timing, CPHA = 1

PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

SIN

SOUT t

SUI t

HI

First Data

First Data t

SUO

Data

Data t

HO

Last Data t

HI

Last Data

DS11646 Rev 4 107/154

128

Electrical characteristics SPC58EEx, SPC58NEx

Figure 32. DSPI PCS strobe (PCSS) timing (master mode) t

PCSC t

PASC

PCSS

PCSx

3.18.2.1.3 DSPI LVDS master mode – modified timing

Table 57. DSPI LVDS master timing — full duplex — modified transfer format

(MTFE = 1), CPHA = 0 or 1

Value

(1)

# Symbol C Characteristic

Condition

Pad drive Load Min Max

1 t

SCK

CC D SCK cycle time LVDS

15 pF to 25 pF differential

(2)

PCS drive strength

30.0

—

2 t

CSC

CC D

PCS to SCK delay

(LVDS SCK)

3 t

ASC

CC D

After SCK delay

(LVDS SCK)

Strong

4 t

SDC

CC D

SCK duty cycle (6)

Very strong

Strong

Medium

Very strong

Medium

LVDS

25 pF

50 pF

50 pF

PCS = 0 pF

SCK = 25 pF

PCS = 0 pF

SCK = 25 pF

PCS = 0 pF

SCK = 25 pF

15 pF to 25 pF differential

(N

(3)

× t

SYS

(4)

10

) –

(N

(3)

× t

SYS

(4)

10

) –

(N

(3)

× t

SYS

(4)

32

) –

(M

(5)

× t

SYS

(4)

8

) –

(M

(5)

× t

SYS

(4)

8

) –

(M

(5)

× t

SYS

(4)

8

) –

1

/

2 t

SCK

– 2

—

—

—

—

—

—

1

/

2 t

SCK

+2

SIN setup time

7 t

SUI

CC D

SIN setup time to SCK

CPHA = 0

(7)

SIN setup time to SCK

CPHA = 1 (7)

SCK drive strength

LVDS

15 pF to 25 pF differential

SCK drive strength

LVDS

15 pF to 25 pF differential

(P

(8)

23 –

× t

SYS

(4)

)

23

—

—

Unit ns ns ns ns ns ns ns ns ns ns

108/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Table 57. DSPI LVDS master timing — full duplex — modified transfer format

(MTFE = 1), CPHA = 0 or 1 (continued)

Condition Value (1)

# Symbol C Characteristic

Pad drive Load Min Max

Unit

SIN Hold Time

8 t

HI

CC D

SIN hold time from SCK

CPHA = 0

(7)

SIN hold time from SCK

CPHA = 1

(7)

SCK drive strength

LVDS

0 pF differential

SCK drive strength

LVDS

0 pF differential

SOUT data valid time (after SCK edge)

9 t

SUO

CC D

SOUT data valid time from SCK

CPHA = 0

(9)

SOUT and SCK drive strength

LVDS

15 pF to 25 pF differential

SOUT data valid time from SCK

CPHA = 1

(9)

SOUT and SCK drive strength

LVDS

15 pF to 25 pF differential

SOUT data hold time (after SCK edge)

1 + (P

(8)

–

× t

SYS

(4)

)

–1

—

—

—

—

7.0 + t

SYS

(4)

7.0

ns ns ns ns

CC D

SOUT data hold time after SCK

CPHA = 0

(9)

SOUT and SCK drive strength

LVDS

15 pF to 25 pF differential

–7.5 + t

SYS

(4)

— ns

10 t

HO

SOUT data hold time after SCK

CPHA = 1

(9)

SOUT and SCK drive strength

LVDS

15 pF to 25 pF differential

–7.5

— ns

1. All timing values for output signals in this table are measured to 50% of the output voltage.

2. LVDS differential load considered is the capacitance on each terminal of the differential pair, as shown in

Figure 12

.

3. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous

SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn).

4. t t

SYS

SYS

is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min

= 10 ns).

5. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn).

6. t

SDC

is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

7. Input timing assumes an input slew rate of 1 ns (10% – 90%) and LVDS differential voltage = ±100 mV.

8. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using

DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set to

1.

DS11646 Rev 4 109/154

128

Electrical characteristics SPC58EEx, SPC58NEx

9. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value.

Figure 33. DSPI LVDS master mode — modified timing, CPHA = 0 t

CSC t

ASC

PCSx t

SDC t

SCK

SCK Output

(CPOL = 0) t

SDC

SCK Output

(CPOL = 1) t

SUI t

HI

SIN

SOUT

First Data

First Data

Data t

SUO

Data

Last Data t

HO

Last Data

Figure 34. DSPI LVDS master mode — modified timing, CPHA = 1

PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

SIN

SOUT t

SUI t

HI

First Data

First Data t

SUO

Data

Data t

HO

Last Data t

HI

Last Data

110/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

3.18.2.1.4 DSPI master mode – output only

Note:

•

In the following table:

• All DSPI timing specifications apply to pins when using LVDS pads for SCK and SOUT and CMOS pad for PCS with pad driver strength as defined. Timing may degrade for weaker output drivers.

TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.

Table 58. DSPI LVDS master timing – output only – timed serial bus mode

TSB = 1 or ITSB = 1, CPOL = 0 or 1, continuous SCK clock

Condition Value

# Symbol C Characteristic

Pad drive Load Min Max

Unit

1 t

2 t

3 t

4 t

SCK

CSV

CSH

SDC

CC D SCK cycle time LVDS

15 pF to 50 pF differential

(1)

25 pF

CC D

PCS valid after

SCK

(2)

(SCK with 50 pF differential load cap.)

Very strong

Strong

CC D

PCS hold after

SCK

(2)

(SCK with 50 pF differential load cap.)

Very strong

Strong

CC D

SCK duty cycle

(SCK with 50 pF differential load cap.)

LVDS

50 pF

0 pF

0 pF

15 pF to 50 pF differential

SOUT data valid time (after SCK edge)

5 t

SUO

6 t

HO

CC D

SOUT data valid time from SCK

(3)

SOUT and SCK drive strength

LVDS

15 pF to 50 pF differential

SOUT data hold time (after SCK edge)

SOUT and SCK drive strength

CC D

SOUT data hold time after SCK (3)

LVDS

15 pF to 50 pF differential

1

/

2 t

25.0

—

—

–4.0

–4.0

SCK

—

–3.5

– 2

1

/

2 t

—

6.0

10.5

—

—

SCK

3.5

—

+ 2 ns ns ns ns ns ns ns ns

1. LVDS differential load considered is the capacitance on each terminal of the differential pair, as shown in

Figure 12

.

2. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This timing value is due to pad delays and signal propagation delays.

3. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value.

Note:

•

In the following table:

• All output timing is worst case and includes the mismatching of rise and fall times of the output pads.

TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.

DS11646 Rev 4 111/154

128

Electrical characteristics SPC58EEx, SPC58NEx

Table 59. DSPI CMOS master timing – output only – timed serial bus mode

TSB = 1 or ITSB = 1, CPOL = 0 or 1, continuous SCK clock

Condition Value

(1)

# Symbol C Characteristic

Pad drive

(2)

Load (C

L

) Min Max

SCK drive strength

1 t

2 t

SCK

CSV

CC D SCK cycle time

CC D PCS valid after SCK

(3)

Very strong

Strong

25 pF

50 pF

Medium 50 pF

SCK and PCS drive strength

Very strong

Strong

Medium

PCS medium and SCK strong

25 pF

50 pF

50 pF

PCS = 50 pF

SCK = 50 pF

SCK and PCS drive strength

Very strong

PCS = 0 pF

SCK = 50 pF

3 t

CSH

CC D PCS hold after SCK

(3)

Strong

Medium

PCS = 0 pF

SCK = 50 pF

PCS = 0 pF

SCK = 50 pF

PCS medium and SCK strong

PCS = 0 pF

SCK = 50 pF

SCK drive strength

Very strong 0 pF

4 t

SDC

CC D SCK duty cycle

(4)

Strong

Medium

0 pF

0 pF

SOUT data valid time (after SCK edge)

9 t

SUO

CC D

SOUT data valid time from

SCK

CPHA = 1

(5)

SOUT and SCK drive strength

Very strong

Strong

25 pF

50 pF

Medium 50 pF

SOUT data hold time (after SCK edge)

SOUT and SCK drive strength

10 t

HO

CC D

SOUT data hold time after

SCK

CPHA = 1

(5)

Very strong

Strong

Medium

25 pF

50 pF

50 pF

33.0

80.0

200.0

7

8

16

29

–14

–14

–33

–35

1

/

2 t

SCK

– 2

1

/

2 t

SCK

– 2

1 /

2 t

SCK

– 5

—

—

—

–7.7

–11.0

–15.0

—

—

—

—

—

1

/

2 t

SCK

+ 2 ns

1

/

2 t

SCK

+ 2 ns

1 /

2 t

SCK

+ 5 ns

7.0

8.0

16.0

—

—

—

—

—

—

—

—

—

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

112/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

1. All timing values for output signals in this table are measured to 50% of the output voltage.

2. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect operation.

3. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This timing value is due to pad delays and signal propagation delays.

4. t

SDC

is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

5. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value.

Figure 35. DSPI LVDS and CMOS master timing–output only— MTFE = 1, CHPA = 1

PCSx t

CSV

SCK Output

(CPOL = 0) t

SDC t

SCK t

CSH

SOUT First Data t

SUO

Data t

HO

Last Data

#

Table 60. DSPI CMOS slave timing — full duplex — normal and modified transfer formats

(MTFE = 0/1)

Condition

Symbol C Characteristic Min Max Unit

Pad Drive Load

1

2

3

4 t

SCK t

CSC t

ASC t

SDC

CC D SCK Cycle Time

(1)

SR

D SS to SCK Delay

(1)

SR

D SCK to SS Delay

(1)

CC

D SCK Duty Cycle

(1)

—

—

—

—

—

—

—

62

16

16

30

—

—

—

— ns ns ns ns

5 t

A

CC D

Slave Access Time

(1)

(2) (3)

(SS active to SOUT driven)

—

Very strong

Strong

25 pF

50 pF

—

—

50

50 ns ns

50 pF — 60 ns

6 t

DIS

CC D

Slave SOUT Disable Time

(1)

(2) (3)

(SS inactive to SOUT High-

Z or invalid)

Medium

Very strong

Strong

Medium

25 pF

50 pF

50 pF

—

—

—

5

5

10 ns ns ns

DS11646 Rev 4 113/154

128

Electrical characteristics SPC58EEx, SPC58NEx

#

Table 60. DSPI CMOS slave timing — full duplex — normal and modified transfer formats

(MTFE = 0/1) (continued)

Condition

Symbol C Characteristic Min Max Unit

Pad Drive Load

9

10

11

12 t t t t

SUI

HI

SUO

HO

CC D

Data Setup Time for

Inputs

(1)

CC

D Data Hold Time for Inputs

(1)

CC

CC

D

D

SOUT Valid Time (1)

(after SCK edge)

SOUT Hold Time

(1)

(after SCK edge)

(2)

(2)

(3)

(3)

—

—

Very strong

Strong

Medium

Very strong

Strong

Medium

—

—

25 pF

50 pF

50 pF

25 pF

50 pF

50 pF

10

10

—

—

—

2.5

2.5

2.5

1. Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL / Automotive voltage thresholds.

2. All timing values for output signals in this table, are measured to 50% of the output voltage.

3. All output timing is worst case and includes the mismatching of rise and fall times of the output pads.

—

—

30

30

50

—

—

— ns ns ns ns ns ns ns ns

Figure 36. DSPI slave mode — modified transfer format timing (MFTE = 0/1) CPHA = 0 t

CSC t

ASC

SS t

SCK

SCK Input

(CPOL = 0) t

SDC t

SDC

SCK Input

(CPOL = 1) t

A t

SUO t

HO t

DIS

SOUT First Data t

SUI

Data Last Data

SIN First Data Data t

HI

Last Data

114/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Figure 37. DSPI slave mode — modified transfer format timing (MFTE = 0/1) CPHA = 1

SS

SCK Input

(CPOL = 0)

SCK Input

(CPOL = 1) t

A t

SUO

SOUT

SIN

First Data t

SUI t

HI

First Data

Data

Data t

HO

Last Data t

DIS

Last Data

The Ethernet provides both MII and RMII interfaces. The MII and RMII signals can be configured for either CMOS or TTL signal levels compatible with devices operating at either

5.0 V or 3.3 V. Please check the device pinout details to review the packages supporting MII and RMII.

3.18.3.1 MII receive signal timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)

Note:

The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%.

There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency.

In the following table, all timing specifications are referenced from RX_CLK = 1.4 V to the valid input levels, 0.8 V and 2.0 V.

M1

M2

M3

M4

Symbol C

Table 61. MII receive signal timing

Characteristic

CC D RXD[3:0], RX_DV, RX_ER to RX_CLK setup

CC D RX_CLK to RXD[3:0], RX_DV, RX_ER hold

CC D RX_CLK pulse width high

CC D RX_CLK pulse width low

Min

5

5

35%

35%

Value

Max

—

—

65%

65%

Unit ns ns

RX_CLK period

RX_CLK period

DS11646 Rev 4 115/154

128

Electrical characteristics SPC58EEx, SPC58NEx

Figure 38. MII receive signal timing diagram

M3

RX_CLK (input)

M4

RXD[3:0] (inputs)

RX_DV

RX_ER

M1 M2

3.18.3.2 MII transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)

Note:

The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%.

There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the TX_CLK frequency.

The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising or falling edge of TX_CLK, and the timing is the same in either case. This option allows the use of non-compliant MII PHYs.

Refer to the SPC58xEx 32-bit Power Architecture microcontroller reference manual’s

Ethernet chapter for details of this option and how to enable it.

In the following table, all timing specifications are referenced from TX_CLK = 1.4 V to the valid output levels, 0.8 V and 2.0 V.

Table 62. MII transmit signal timing

Value

(1)

Symbol C Characteristic Unit

Min Max

M5

M6

M7

M8

CC D TX_CLK to TXD[3:0], TX_EN, TX_ER invalid

CC D TX_CLK to TXD[3:0], TX_EN, TX_ER valid

CC D TX_CLK pulse width high

CC D TX_CLK pulse width low

5

—

35%

35%

—

25

65%

65% ns ns

TX_CLK period

TX_CLK period

1. Output parameters are valid for C

L

= 25 pF, where C

L

is the external load to the device. The internal package capacitance is accounted for, and does not need to be subtracted from the 25 pF value

116/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Figure 39. MII transmit signal timing diagram

M7

TX_CLK (input)

M5

M8

TXD[3:0] (outputs)

TX_EN

TX_ER

M6

3.18.3.3 MII async inputs signal timing (CRS and COL)

M9

Symbol C

Table 63. MII async inputs signal timing

Value

Characteristic

CC D CRS, COL minimum pulse width

Min

1.5

Max

—

Figure 40. MII async inputs timing diagram

CRS, COL

M9

Unit

TX_CLK period

DS11646 Rev 4 117/154

128

Electrical characteristics SPC58EEx, SPC58NEx

3.18.3.4 MII and RMII serial management channel timing (MDIO and MDC)

The Ethernet functions correctly with a maximum MDC frequency of 2.5 MHz.

Figure 41. MII serial management channel timing diagram

M14

M15

MDC (output)

M10

MDIO (output)

M11

MDIO (input)

M12

M13

3.18.3.5 MII and RMII serial management channel timing (MDIO and MDC)

Note:

The Ethernet functions correctly with a maximum MDC frequency of 2.5 MHz.

In the following table, all timing specifications are referenced from MDC = 1.4 V (TTL levels) to the valid input and output levels, 0.8 V and 2.0 V (TTL levels). For 5 V operation, timing is referenced from MDC = 50% to 2.2 V/3.5 V input and output levels.

M12

M13

M14

M15

M10

M11

Symbol C

Table 64. MII serial management channel timing

Value

Characteristic

Min Max

CC D

MDC falling edge to MDIO output invalid

(minimum propagation delay)

CC D

MDC falling edge to MDIO output valid (max prop delay)

CC D MDIO (input) to MDC rising edge setup

CC D MDIO (input) to MDC rising edge hold

CC D MDC pulse width high

CC D MDC pulse width low

0

—

10

0

40%

40%

—

25

—

—

60%

60%

Unit ns ns ns ns

MDC period

MDC period

118/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Note: In the following table, all timing specifications are referenced from MDC = 1.4 V (TTL levels) to the valid input and output levels, 0.8 V and 2.0 V (TTL levels). For 5 V operation, timing is referenced from MDC = 50% to 2.2 V/3.5 V input and output levels.

M12

M13

M14

M15

M10

M11

Symbol C

Table 65. RMII serial management channel timing

Value

Characteristic

Min Max

CC D

MDC falling edge to MDIO output invalid

(minimum propagation delay)

CC D

MDC falling edge to MDIO output valid (max prop delay)

CC D MDIO (input) to MDC rising edge setup

CC D MDIO (input) to MDC rising edge hold

CC D MDC pulse width high

CC D MDC pulse width low

0

—

10

0

40%

40%

—

25

—

—

60%

60%

Unit ns ns ns ns

MDC period

MDC period

Figure 42. MII serial management channel timing diagram

M14

M15

MDC (output)

M10

MDIO (output)

M11

MDIO (input)

M12

M13

3.18.3.6 RMII receive signal timing (RXD[1:0], CRS_DV)

The receiver functions correctly up to a REF_CLK maximum frequency of 50 MHz +1%.

There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency, which is half that of the REF_CLK frequency.

DS11646 Rev 4 119/154

128

Electrical characteristics SPC58EEx, SPC58NEx

Note: In the following table, all timing specifications are referenced from REF_CLK = 1.4 V to the valid input levels, 0.8 V and 2.0 V.

R1

R2

R3

R4

Symbol C

Table 66. RMII receive signal timing

Characteristic

CC D RXD[1:0], CRS_DV to REF_CLK setup

CC D REF_CLK to RXD[1:0], CRS_DV hold

CC D REF_CLK pulse width high

CC D REF_CLK pulse width low

Min

4

2

35%

35%

Value

Max

—

—

65%

65%

Unit ns ns

REF_CLK period

REF_CLK period

Figure 43. RMII receive signal timing diagram

R3

REF_CLK (input)

R4

RXD[1:0] (inputs)

CRS_DV

R1 R2

3.18.3.7 RMII transmit signal timing (TXD[1:0], TX_EN)

Note:

The transmitter functions correctly up to a REF_CLK maximum frequency of 50 MHz + 1%.

There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the TX_CLK frequency, which is half that of the REF_CLK frequency.

The transmit outputs (TXD[1:0], TX_EN) can be programmed to transition from either the rising or falling edge of REF_CLK, and the timing is the same in either case. This option allows the use of non-compliant RMII PHYs.

In the following table, all timing specifications are referenced from REF_CLK = 1.4 V to the valid output levels, 0.8 V and 2.0 V.

RMII transmit signal valid timing specified is considering the rise/fall time of the ref_clk on the pad as 1ns.

120/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

R5

R6

R7

R8

Symbol C

Table 67. RMII transmit signal timing

Characteristic

CC D REF_CLK to TXD[1:0], TX_EN invalid

CC D REF_CLK to TXD[1:0], TX_EN valid

CC D REF_CLK pulse width high

CC D REF_CLK pulse width low

Min

2

—

35%

35%

Value

Max

—

14

65%

65%

Unit ns ns

REF_CLK period

REF_CLK period

Figure 44. RMII transmit signal timing diagram

R7

REF_CLK (input)

R5

R8

TXD[1:0] (outputs)

TX_EN

R6

This section provides the FlexRay Interface timing characteristics for the input and output signals.

These are recommended numbers as per the FlexRay EPL v3.0 specification, and subject to change per the final timing analysis of the device.

DS11646 Rev 4 121/154

128

Electrical characteristics

3.18.4.1 TxEN

80 %

TxEN

20 %

Figure 45. TxEN signal

SPC58EEx, SPC58NEx dCCTxEN

FALL dCCTxEN

RISE

Symbol C

Table 68. TxEN output characteristics

Characteristic

(1) (2) dCCTxEN

RISE25 dCCTxEN

FALL25 dCCTxEN dCCTxEN

01

10

CC D Rise time of TxEN signal at CC

CC D Fall time of TxEN signal at CC

CC D

Sum of delay between Clk to Q of the last FF and the final output buffer, rising edge

CC D

Sum of delay between Clk to Q of the last FF and the final output buffer, falling edge

1. TxEN pin load maximum 25 pF.

2. Pad configured as VERY STRONG.

Min

—

—

Value

Max

9

9

— 25

Unit ns ns ns

— 25 ns

122/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

Figure 46. TxEN signal propagation delays

PE_Clk

TxEN

3.18.4.2 TxD

dCCTxEN

10

80 %

TxD

50 %

20 %

Figure 47. TxD signal dCCTxD

50% dCCTxEN

01

Note: dCCTxD

FALL dCCTxD

RISE

In the following table, specifications valid according to FlexRay EPL 3.0.1 standard with

20%–80% levels and a 10 pF load at the end of a 50 Ohm, 1 ns stripline. Please refer to the

Very Strong I/O pad specifications.

DS11646 Rev 4 123/154

128

Electrical characteristics SPC58EEx, SPC58NEx

Table 69. TxD output characteristics

Value

Symbol C Characteristic

(1) , (2)

Min Max dCCTxAsym dCCTxD

RISE25

+dCCTxD

FALL25 dCCTxD dCCTxD

01

10

CC D

CC

Asymmetry of sending CC at 25 pF load

(= dCCTxD

50%

− 100 ns)

D Sum of Rise and Fall time of TxD signal at the

D output pin (3)

CC D

Sum of delay between Clk to Q of the last FF and the final output buffer, rising edge

CC D

Sum of delay between Clk to Q of the last FF and the final output buffer, falling edge

–2.45

—

—

—

—

2.45

9

9

(4)

(5)

25

25

1. TxD pin load maximum 25 pF.

2. Pad configured as VERY STRONG.

3. Sum of transition time simulation is performed according to Electrical Physical Layer Specification 3.0.1 and the entire temperature range of the device has been taken into account.

4. V

DD_HV_IO

= 5.0 V ± 10%, Transmission line Z = 50 ohms, t delay

= 1 ns, C

L

= 10 pF.

5. V

DD_HV_IO

= 3.3 V ± 10%, Transmission line Z = 50 ohms, t delay

= 0.6 ns, C

L

= 10 pF.

Unit ns ns ns ns

Figure 48. TxD Signal propagation delays

PE_Clk *

TxD dCCTxD

10

* FlexRay Protocol Engine Clock

3.18.4.3 RxD

Symbol

C_CCRxD uCCLogic_1

C

Table 70. RxD input characteristics

Characteristic

CC D Input capacitance on RxD pin

CC D Threshold for detecting logic high

124/154 DS11646 Rev 4 dCCTxD

01

Min

—

35

Value

Max

7

70

Unit pF

%

SPC58EEx, SPC58NEx Electrical characteristics

Table 70. RxD input characteristics (continued)

Symbol C Characteristic uCCLogic_0 dCCRxD

01

CC D Threshold for detecting logic low

CC D

Sum of delay from actual input to the D input of the first FF, rising edge dCCRxD

10

CC D

Sum of delay from actual input to the D input of the first FF, falling edge dCCRxAsymAccept15 CC D

Acceptance of asymmetry at receiving CC with

15 pF load dCCRxAsymAccept25 CC D

Acceptance of asymmetry at receiving CC with

25 pF load

—

–31.5

–30.5

Min

30

—

Value

Max

65

10

10

44

43

Unit ns ns

% ns ns

The following table describes the PSI5 timing.

Table 71. PSI5 timing

Value

Symbol C Parameter Unit

Min Max t t

MSG_DLY

SYNC_DLY

CC D

CC D

Delay from last bit of frame (CRC0) to assertion of new message received interrupt

Delay from internal sync pulse to sync pulse trigger at the SDOUT_PSI5_n pin

—

—

3

2 t t

MSG_JIT

SYNC_JIT

CC D

CC D

Delay jitter from last bit of frame (CRC0) to assertion of new message received interrupt

Delay jitter from internal sync pulse to sync pulse trigger at the SDOUT_PSI5_n pin

—

—

1

+/-±(1 PSI5_1µs_CLK +

1 PBRIDGEn_CLK)

1. Measured in PSI5 clock cycles (PBRIDGEn_CLK on the device). Minimum PSI5 clock period is 20 ns.

µs

µs cycles

(1) cycles

The following table describes the CAN timing.

DS11646 Rev 4 125/154

128

Electrical characteristics SPC58EEx, SPC58NEx

Table 72. CAN timing

Symbol C Parameter Condition t

P(RX:TX) t

PLP(RX:TX)

CC

CC

CC D

CC D

CC

CC

CC

D

D

D

D

D

CC D

CAN controller propagation delay time standard pads

Medium type pads 25pF load

Medium type pads 50pF load

STRONG, VERY STRONG type pads

25pF load

STRONG, VERY STRONG type pads

50pF load

Medium type pads 25pF load

CAN controller propagation delay time low power pads

Medium type pads 50pF load

STRONG, VERY STRONG type pads

25pF load

STRONG, VERY STRONG type pads

50pF load

Min

—

—

—

—

—

—

—

—

—

—

—

—

—

Value

Typ

—

—

—

Max

70

80

60

65

90

100

80

85

Unit ns ns

UART channel frequency support is shown in the following table.

Table 73. UART frequency support

LINFlexD clock frequency LIN_CLK

(MHz)

Oversampling rate Voting scheme

80

100

4

16

8

6

5

4

16

8

6

5

3:1 majority voting

Limited voting on one sample with configurable sampling point

3:1 majority voting

Limited voting on one sample with configurable sampling point

Max usable frequency

(Mbaud)

5

10

13.33

16

20

6.25

12.5

16.67

20

25

Note:

The I

2

C AC timing specifications are provided in the following tables.

In the following table, I2C input timing is valid for Automotive and TTL inputs levels, hysteresis enabled, and an input edge rate no slower than 1 ns (10% – 90%).

126/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Electrical characteristics

No. Symbol C

Table 74. I2C input timing specifications – SCL and SDA

Value

Parameter

Min Max

Unit

1 — CC D Start condition hold time 2

8

4.7

0.0

—

—

—

—

PER_CLK

Cycle

(1)

PER_CLK Cycle 2 — CC D Clock low time

3

4

— CC D Bus free time between Start and Stop condition

— CC D Data hold time

5 — CC D Clock high time

6 — CC D Data setup time

4

0.0

—

—

µs ns

PER_CLK Cycle ns

7 — CC D Start condition setup time (for repeated start condition only)

8 — CC D Stop condition setup time

2

2

—

—

PER_CLK Cycle

PER_CLK Cycle

1. PER_CLK is the SoC peripheral clock, which drives the I 2 device reference manual for more detail.

C BIU and module clock inputs. See the Clocking chapter in the

Note: In the following table:

• All output timing is worst case and includes the mismatching of rise and fall times of the output pads.

• Output parameters are valid for CL = 25 pF, where CL is the external load to the device

(lumped). The internal package capacitance is accounted for, and does not need to be subtracted from the 25 pF value.

• Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect operation.

• Programming the IBFD register (I2C bus Frequency Divider) with the maximum frequency results in the minimum output timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the pre-scale and division values programmed in the IBC field of the IBFD register.

No. Symbol C

Table 75. I2C output timing specifications — SCL and SDA

Value

Parameter

Min Max

1 — CC D Start condition hold time

2 — CC D Clock low time

3 — CC D Bus free time between Start and Stop condition

4 — CC D Data hold time

5 — CC D Clock high time

6 — CC D Data setup time

7 — CC D Start condition setup time (for repeated start condition only)

8 — CC D Stop condition setup time

6

10

4.7

7

10

2

20

10

Unit

—

PER_CLK

Cycle (1)

— PER_CLK Cycle

— µs

— PER_CLK Cycle

— PER_CLK Cycle

— PER_CLK Cycle

— PER_CLK Cycle

— PER_CLK Cycle

DS11646 Rev 4 127/154

128

Electrical characteristics SPC58EEx, SPC58NEx

1. PER_CLK is the SoC peripheral clock, which drives the I 2 device reference manual for more detail.

C BIU and module clock inputs. See the Clocking chapter in the

2

Figure 49. I

2

C input/output timing

5

SCL

8

1

4

6

7

3

SDA

128/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK is an ST trademark.

The following table lists the case numbers for SPC58xEx.

Package Type

Table 76. Package case numbers

Device Type eLQFP176 Production

FPBGA292 Production

Package reference

8153717

8537045

DS11646 Rev 4 129/154

136

Package information

4.1 eLQFP176 package information

Figure 50. eLQFP176 package outline

SPC58EEx, SPC58NEx

130/154 DS11646 Rev 4

OLIH DXJPHQWHG

SPC58EEx, SPC58NEx

Figure 51. eLQFP176 section A-A ș ș

Package information ș

Figure 52. eLQFP176 section B-B ș

DS11646 Rev 4 131/154

136

Package information SPC58EEx, SPC58NEx

Symbol

Ө

Ө 1

Ө 2

Ө 3

A

(15)

A1

(12)

A2

(15) b

(9)(11)

b1

(11) c

(11) c1

(11)

D

(4)

D1

(2)(5)

D2

(13)

D3

(14)

e

E

(4)

E1

(2)(5)

E2

(13)

E3

(14)

L

L1

N

(16)

R1

R2

S aaa

(1)(7)(19)

bbb

(1)(7)(19)

ccc

(1)(7)(19)

ddd

(1)(7)(19)

Table 77. eLQFP176 package mechanical data

Dimensions

(7)

Min.

0°

0°

10°

10°

—

0.05

1.35

0.17

0.17

0.09

0.09

—

7.30

—

—

7.30

0.45

0.08

0.08

0.20

Nom.

24.00 BSC

—

—

0.60

1.00 REF

176

—

—

—

0.20

0.20

0.08

0.08

0.22

0.20

—

—

26.00 BSC

24.00 BSC

—

—

0.50 BSC

26.00 BSC

3.5°

—

12°

12°

—

—

1.40

Max.

7°

—

14°

14°

1.60

0.15

1.45

0.27

0.23

0.20

0.16

8.97

—

—

8.97

—

0.75

—

0.20

132/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Package information

The following notes are relative to above figures and table:

1.

Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.

2. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm.

3. Datums A-B and D to be determined at datum plane H.

4. To be determined at seating datum plane C.

5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size dimensions including mold mismatch.

6. Details of pin 1 identifier are optional but must be located within the zone indicated.

7. All dimensions are in millimeter except where explicitly noted.

8. No intrusion allowed inwards the leads.

9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.

Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.

10. Exact shape of each corner is optional.

11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.

12. A1 is defined as the distance from the seating plane to the lowest point on the package body.

13. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located (if present). It includes all metal protrusions

from exposed pad itself. Type of exposed pad on SPC58xEx is as Figure 53

. End user should verify D2 and E2 dimensions according to the specific device application.

14. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of exposed pad which is guaranteed to be free from resin flashes/bleeds, bordered by internal edge of inner groove.

15. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude beyond that surface.

16. “N” is the max number of terminal positions for the specified body size.

17. For Tolerance of Form and Position see Table.

18. Critical dimensions: a) Stand-Off

19. For Symbols, Recommended Values and Tolerances see Table 78

.

DS11646 Rev 4 133/154

136

Package information SPC58EEx, SPC58NEx

Figure 53. eLQFP176 leadframe pad design

Note: number, dimensions and positions of grooves are for reference only.

Symbol aaa bbb ccc ddd

Table 78. eLQFP176 Symbol definitions

Definition Notes

The tolerance that controls the position of the terminal pattern with respect to Datum A and B. The center of the tolerance zone for each terminal is defined by basic dimension e as related to Datum A and B.

For flange-molded packages, this tolerance also applies for basic dimensions D1 and

E1. For packages tooled with intentional terminal tip protrusions, aaa does not apply to those protrusions.

The bilateral profile tolerance that controls the position of the plastic body sides. The centers of the profile zones are defined by the basic dimensions D and E.

—

The unilateral tolerance located above the seating plane where in the bottom surface of all terminals must be located.

This tolerance is commonly know as the

“coplanarity” of the package terminals.

The tolerance that controls the position of the terminals to each other. The centers of the profile zones are defined by basic dimension e.

This tolerance is normally compounded with tolerance zone defined by “b”.

134/154 DS11646 Rev 4

SPC58EEx, SPC58NEx

Figure 54. FPBGA292 package outline

Package information

DS11646 Rev 4 135/154

136

Package information SPC58EEx, SPC58NEx

Table 79. FPBGA292 package mechanical data

Dimensions

REF.

Millimeters Inches

(1)

Min Typ Max Min Typ

A

(2)

A1

A2

A4

D

D1

E

E1 e b (3)

Z aaa bbb ddd eee

(4) fff (5)

–

0.35

–

–

16.85

–

16.85

–

–

0.50

–

–

–

–

–

–

–

–

0.53

–

17.00

15.20

17.00

15.20

0.80

0.55

0.90

–

–

–

–

–

1.8

–

–

0.80

17.15

–

17.15

–

–

0.60

–

0.15

0.10

0.12

0.15

0.08

–

0.014

–

–

0.663

–

0.663

–

–

0.019

–

–

–

–

–

–

1. Values in inches are converted from millimeters (mm) and rounded to three decimal digits.

2. FPBGA stands for Fine Pitch Plastic Ball Grid Array.

Fine pitch: e < 1.00mm pitch.

Low Profile: The total profile height (Dim A) is measured from the seating plane to the top of the component.

The maximum total package height is calculated by the following methodology (tolerance values):

Amax = A

1

( TYP ) + A

2

( TYP ) + A

4

( TYP ) +

1

2

+

2

2

+ ( )

2

0.031

0.021

0.035

–

–

–

–

–

–

–

0.021

–

0.669

0.598

0.669

0.598

Max

3. The typical ball diameter before mounting is 0.55mm.

4. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.

5. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained entirely in the respective zone eee above. The axis of each ball must lie simultaneously in both tolerance zones.

–

0.023

–

0.006

0.004

0.005

0.006

0.003

0.071

–

–

0.031

0.675

–

0.675

–

136/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Package information

The following tables describe the thermal characteristics of the device. The parameters in this chapter have been evaluated by considering the device consumption configuration reported in the

Section 3.7: Device consumption

.

4.3.1 LQFP176

Symbol

Table 80. Thermal characteristics for 176 exposed pad LQFP package

C Parameter

(1)

Conditions Value Unit

R

θ JA

CC D Junction-to-Ambient, Natural Convection

(2)

Four layer board (2s2p) 20.9

°C/W

R

θ JMA

CC D Junction-to-Moving-Air, Ambient

(2)

at 200 ft./min., four layer board (2s2p)

15.3

°C/W

R

θ JB

R

θ JCtop

R

θ JCbottom

Ψ

JT

CC D

CC D

CC D

CC D

Junction-to-board

(3)

Junction-to-case top (4)

Junction-to-case bottom

(5)

Junction-to-package top

(6)

—

—

—

Natural convection

9

7.3

1

1

°C/W

°C/W

°C/W

°C/W

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.

4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

5. Thermal resistance between the die and the exposed pad ground on the bottom of the package based on simulation without any interface resistance.

6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.

4.3.2 FPBGA292

Symbol C

Table 81. Thermal characteristics for 292-pin FPBGA

Parameter (1) Conditions Value Unit

R

θ JA

R

θ JB

R

θ JC

Ψ

JT

CC D Junction-to-Ambient, Natural Convection

(2)

CC D Junction-to-board (3)

CC

CC

D

D

Junction-to-case

(4)

Junction-to-package top

(5)

Four layer board (2s2p)

—

—

Natural convection

21.3

9.8

6.5

0.6

°C/W

°C/W

°C/W

°C/W

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2. Per JEDEC JESD51-6 with the board (JESD51-9) horizontal.

3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.

4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

5. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.

DS11646 Rev 4 137/154

140

Package information

4.3.3

SPC58EEx, SPC58NEx

General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, T

J

, can be obtained from the equation:

Equation 1

T

J

= T

A

+ (R

θ JA

* P

D

) where:

T

A

= ambient temperature for the package (°C)

R

θ JA

P

D

= junction-to-ambient thermal resistance (°C/W)

= power dissipation in the package (W)

The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The differences between the values determined for the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance depends on the:

• Construction of the application board (number of planes)

• Effective size of the board which cools the component

• Quality of the thermal and electrical connections to the planes

• Power dissipated by adjacent components

Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between the vias leaves the planes virtually disconnected, the thermal performance is also greatly reduced.

As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. The value obtained on a board with the internal planes is usually within the normal range if the application board has:

• One oz. (35 micron nominal thickness) internal planes

• Components are well separated

• Overall power dissipation on the board is less than 0.02 W/cm

2

The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device.

At a known board temperature, the junction temperature is estimated using the following equation:

Equation 2

T

J

= T

B

+ (R

θ JB

* P

D

) where:

T

B

= board temperature for the package perimeter (°C)

R

θ JB

P

D

= junction-to-board thermal resistance (°C/W) per JESD51-8

= power dissipation in the package (W)

138/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Package information

When the heat loss from the package case to the air does not factor into the calculation, the junction temperature is predictable if the application board is similar to the thermal test condition, with the component soldered to a board with internal planes.

The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal resistance:

Equation 3

R

θ JA

= R

θ JC

+ R

θ CA where:

R

θ JA

= junction-to-ambient thermal resistance (°C/W)

R

θ JC

= junction-to-case thermal resistance (°C/W)

R

θ CA

= case to ambient thermal resistance (°C/W)

R

θ JC

is device related and is not affected by other factors. The thermal environment can be controlled to change the case-to-ambient thermal resistance, R

θ CA

. For example, change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where

90% of the heat flow is through the case to heat sink to ambient. For most packages, a better model is required.

A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple estimations and for computational fluid dynamics (CFD) thermal models. More accurate compact Flotherm models can be generated upon request.

To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization parameter ( Ψ

JT

) to determine the junction temperature by measuring the temperature at the top center of the package case using the following equation:

Equation 4

T

J

= T

T

+ ( Ψ

JT

x P

D

) where:

T

T

= thermocouple temperature on top of the package (°C)

Ψ

JT

= thermal characterization parameter (°C/W)

P

D

= power dissipation in the package (W)

The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire.

When board temperature is perfectly defined below the device, it is possible to use the thermal characterization parameter ( Ψ

JPB

) to determine the junction temperature by

DS11646 Rev 4 139/154

140

Package information SPC58EEx, SPC58NEx measuring the temperature at the bottom center of the package case (exposed pad) using the following equation:

Equation 5

T

J

= T

B

+ ( Ψ

JPB

x P

D

) where:

T

T

= thermocouple temperature on bottom of the package (°C)

Ψ

JT

= thermal characterization parameter (°C/W)

P

D

= power dissipation in the package (W)

140/154 DS11646 Rev 4

SPC58EEx, SPC58NEx

Figure 55. Commercial product scheme

Example code:

SPC58

Product identifier

N E

Core Product

84

Memory

E7

Package

Q

Frequency

M

Reserved

H A

Reserved

R

Packing

Ordering information

Y = Tray

R = Tape and Reel

H = Safety + Security HW

S = Safety HW

C = Security HW (HSM)

O = No option

X = 180 MHz at 165 o

C T

Q = 180 MHz at 150 C T

N = 120 MHz at 150 C T

J

J

J

C3 = FPBGA292

E7 = eLQFP176

H0 = Known Good Die

84 = 6 MB

80 = 4 MB

E = SPC58NE84xx family

N = Triple computing e200z4d core

E = Double computing e200z4d core

(CPU_0 + CPU_2)

SPC58 = Power Architecture in 40 nm

Note: Please contact your ST sales office to ask for the availability of a particular commercial product.

Features (For example flash, RAM or peripherals) not included in the commercial product cannot be used. ST cannot be called to take any liability for features used outside the commercial product.

SPC58xE84 (6M)

16

16

16

16

Table 82. Code Flash options

SPC58xE80 (4M) Partition Start address

16

16

16

16

0

0

1

1

0x00FC0000

0x00FC4000

0x00FC8000

0x00FCC000

End address

0x00FC3FFF

0x00FC7FFF

0x00FCBFFF

0x00FCFFFF

DS11646 Rev 4 141/154

143

Ordering information

SPC58xE84 (6M)

256

256

256

256

256

256

256

256

256

256

128

128

256

256

32

32

64

64

256

256

256

256

256

256

256

256

256

256

Table 82. Code Flash options (continued)

SPC58xE80 (4M) Partition Start address

256

256

256

256

256

256

256

256

256

256

128

128

256

256

32

32

64

64

256

256

NA

NA

NA

NA

NA

NA

NA

NA

0

1

1

1

1

1

0

0

0

0

0

0

0

1

0

0

0

1

5

5

5

5

5

5

5

1

1

5

0x00FD0000

0x00FD8000

0x00FE0000

0x00FF0000

0x01000000

0x01020000

0x01040000

0x01080000

0x010C0000

0x01100000

0x01140000

0x01180000

0x011C0000

0x01200000

0x01240000

0x01280000

0x012C0000

0x01300000

0x01340000

0x01380000

0x013C0000

0x01400000

0x01440000

0x01480000

0x014C0000

0x01500000

0x01540000

0x01580000

SPC58EEx, SPC58NEx

End address

0x00FD7FFF

0x00FDFFFF

0x00FEFFFF

0x00FFFFFF

0x0101FFFF

0x0103FFFF

0x0107FFFF

0x010BFFFF

0x010FFFFF

0x0113FFFF

0x0117FFFF

0x011BFFFF

0x011FFFFF

0x0123FFFF

0x0127FFFF

0x012BFFFF

0x012FFFFF

0x0133FFFF

0x0137FFFF

0x013BFFFF

0x013FFFFF

0x0143FFFF

0x0147FFFF

0x014BFFFF

0x014FFFFF

0x0153FFFF

0x0157FFFF

0x015BFFFF

Table 83. RAM options (1)

SPC58NE84 SPC58EE84 SPC58NE80 SPC58EE80

Type

768 768 768 768

128

160

128

160

128

160

128

160

Start address

PRAMC_0 0x40060000

PRAMC_1 0x40080000

End address

0x4007FFFF

0x400A7FFF

142/154 DS11646 Rev 4

SPC58EEx, SPC58NEx Ordering information

Table 83. RAM options (1) (continued)

SPC58NE84 SPC58EE84 SPC58NE80 SPC58EE80

Type Start address

768 768 768 768

256

64

64

64

32

256

64

64

64

32

256

64

64

64

32

256

64

64

64

32

PRAMC_2

(STBY)

PRAMC_3

D_MEM

CPU_0

D_MEM

CPU_1

D_MEM

CPU_2

0x400A8000

0x400E8000

0x50800000

0x51800000

0x52800000

1. RAM size is the sum of TCM and SRAM.

End address

0x400E7FFF

0x400F7FFF

0x5080FFFF

0x5180FFFF

0x52807FFF

DS11646 Rev 4 143/154

143

Revision history SPC58EEx, SPC58NEx

Date

10-Jun-2016

03-April-2017

Revision

1

2

Table 84. Document revision history

Changes

Initial release.

Following are the changes for this release of the document:

Editorial and formatting updates throughout the document.

Updated the cover page.

Section 1.2: Description :

Replaced “SPC58NE84x” with “SPC58xEx”.

Table 2: SPC58xEx feature summary ::

Updated table.

Section 1.5: Features

:

Updated the feature bullet points.

Section 2.1: Pad dimensions/ KGD coordinates

:

Added this section.

Section 3.1: Introduction :

– Removed text “The IPs and...for the details”.

– Removed the two notes.

Section 3.2: Absolute maximum ratings

:

– Added text “Exposure to absolute ... reliability”

– Added text “even momentarily”

Table 4: Absolute maximum ratings

:

– Updated values in conditions column.

– Added parameter T

TRIN.

– For parameter “T

STG

”, maximum value updated from “175” to “125”

– Added new parameter “T

PAS

”

– For parameter “I

INJ

”, description updated from “maximum...PAD” to

“maximum DC...pad”

Table 5: Operating conditions

:

– For parameter “V

DD_LV

”, added footnote “In the range...”

– For parameter “V

DD_LV

”, changed the classification from “D” to “P”

– For parameter “V

DD_HV_ADR_S

”, removed the second row.

– For parameter V

DD_HV_ADR_S

-V

DD_HV_ADV

, updated the min value.

– Added footnote “The maximum number...” to parameter F

SYS

.

– For parameter “V

DD_HV_ADR_S

“Min” columns.

-V

DD_HV_ADV

”, swapped the “conditions” and

Added new table Table 6: PRAM wait states configuration .

Table 7: Device supply relation during power-up/power-down sequence

:

Updated the table.

Section 3.6: Temperature profile :

Added text “Mission profile with junction....representative for validation”

144/154 DS11646 Rev 4

SPC58EEx, SPC58NEx

Date

03-April-2017

Revision history

Table 84. Document revision history (continued)

Revision Changes

2

Table 9: Device consumption :

– Updated parameter “I

DDHALT

”

– Updated parameter “I

DDSTOP

”

– Changed the condition from “C” to “D” for parameter “I

DD_LV_BD

”

– Changed the condition from “C” to “T” for parameter “I

DD_HV_BD

”

– Changed from “Cc” to “SR” for parameters “I

SPIKE and dl”

– Changed the condition from “P” to “T” for parameter “I

DDOFF

”

– Updated the max values for parameter I

DD_LKG.

– Deleted parameters: I

DDSTBY8,

I

DDSTBY128, and I

DDSTBY256.

Table 11: I/O input electrical characteristics :

Added parameter “V ihcmos

BD”.

Updated table footnote 1.

Table 13: WEAK/SLOW I/O output characteristics

:

– For parameter “F max_W

”, updated condition “25 pF load” to “CL=25pF”.

– For parameter “t

TR_S

”, changed min value (25 pF load) from “4” to “3”.

– Changed min value (50 pF load) from “6” to “5”.

Table 17: I/O consumption

:

Updated all the max values of parameters, I

DYN_W

and I

DYN_M

Table 3.8: I/O pad specification :

– Replaced all occurences of “50 pF load” with “CL=50pF”.

– Removed note “The external ballast....”.

Table 3.8.2: I/O output DC characteristics

:

Added note “10%/90% is the....”

Table 15: STRONG/FAST I/O output characteristics

– Parameter “I

DCMAX_S

” updated:

– Condition added “V

DD

=5V+10%

– Condition added “V

DD

=3.3V+10%, Max value updated to 5.5mA

Table 19: Reset Pad state during power-up and reset :

Added this table.

Table 20: PLL0 electrical characteristics

:

– For parameter “I

PLL0

”, classification changed from “C” to “T”.

– Footnote “Jitter values...measurement” added for parameters:

|Δ

PLL0PHI0SPJ

|Δ

PLL0PHI1SPJ

Δ

PLL0LTJ

|

|

Table 21: PLL1 electrical characteristics

:

– For parameter “I

PLL1

”, classification changed from “C” to “T”.

– Footnote “Jitter values...measurement” added for parameter “ |Δ

PLL1PHI0SPJ

|”

Table 22: External 40 MHz oscillator electrical specifications

:

– Classification for parameters “C

S_EXTAL

“D”.

” and “C

S_EXTAL

” changed from “T” to

– Updated classification, conditions, min and max values for parameter “g m

”.

– Updated parameters C

S_EXTAL

, and C

S_XTAL

.

DS11646 Rev 4 145/154

153

Revision history

Date

03-April-2017

SPC58EEx, SPC58NEx

Table 84. Document revision history (continued)

Revision Changes

2

Renamed the section “RC oscillator 1024 kHz” to Section 3.11.4: Low power

RC oscillator

Table 24: Internal RC oscillator electrical specifications :

– For parameter “I

FIRC

”, replaced max value of 300 with 600.

– Added footnote to the description.

– For parameter I

FIRC, changed the max value to 600 and added footnote.

– Min, Typ and Max value of ” δ f var_SW

“+0.3” and “0.5” respectively.

” updated from “-1”, “-”, “1” to “-0.5”,

– For parameter “gmsxosc”, changed the cassification to “P”.

Table 25: 1024 kHz internal RC oscillator electrical characteristics :

For parameter “ δ f var_T

”, and “ δ f var_V

“ changed the cassification to “P”.

Table 27: SARn ADC electrical specification

:

– Classification for parameter “I

ADCREFH

” changed from “C” to “T”.

– For parameter f

ADCK

“> 13.33”.

(High frequency mode), changed min value from “7.5” to

– Deleted footnote “Values are subject to change (possibly improved to ±2

LSB) after characterization”

Table 28: ADC-Comparator electrical specification :

– Classification for parameter “I

ADCREFH

” changed from “C” to “T”

– Removed table footnote “Values are subject to change (possibly improved to

±2 LSB) after characterization”

– For parameter f

ADCK , replaced the min value “7.5” with “>13.33”

Table 26: ADC pin specification

:

For I

LKG

, changed condition “C” to “—”.

Table 29: SDn ADC electrical specification

:

– Added footnote “When using a GAIN ... resolution of 15 bits” to parameter

“RESOLUTION”.

– Added footnote “Conversion offset ... offset error” to parameter V

OFFSET

.

– Removed footnote “SNR value guaranteed ... frequency range” from parameters- SNR

DIFF150

and SNR

DIFF333.

– In V cmrr

, changed “SR” to “CC” and “D” to “T”

– Changed min value from “1.5” to “—” in parameter “I

ADV_D

”

– Changed min value from “3” to “—” in parameter “ Σ I

ADR_D

”.

– Added footnote “Consumption is given ... set-up” to parameter “ Σ I

ADR_D

”

– Removed footnote “Sampling is .... f

ADCD_M

/2”

– Updated footnote “S/D ADC is ...12 dB”

– Added table footnote “This parameter ...3 dB less” to parameters -

SNR

DIFF150

, SNR

DIFF333, and SNR

SE150

– Replaced the max value of Σ I

ADR_D

of “16” with “80”.

Table 8: Input equivalent circuit (Fast SARn and SARB channels) :

Updated the figure.

Table 31: Temperature sensor electrical characteristics :

For “temperature monitoring range”, classification removed (was C)

146/154 DS11646 Rev 4

SPC58EEx, SPC58NEx

Date

03-April-2017

Revision history

Table 84. Document revision history (continued)

Revision Changes

2

Table 36: LFAST PLL electrical characteristics :

– Min and Max value of parameter “ERR

REF

“+1” respectively

” updated from “TBD” to “-1” and

– Max value of parameter “PN” updated from “TBD” to “-58”

– Frequency of parameter “ Δ PER

REF

” updated from “10MHz” to “20MHz”.

– Max value of parameter “ Δ PER

REF from “TBD” to “350”

” for condition “Single period” updated

– Min and Max value of parameter “ Δ PER

REF

” for condition “Long period” updated from “TBD” to “-500” and “+500” respectively.

Table 37: Aurora LVDS electrical characteristics,

:

– For parameter |Δ V

I_L

|, changed classification to “T”

– For parameter |Δ V

OD_LVDS

|, changed the classification to "T".

Table 45: Voltage monitor electrical characteristics :

– For V

POR200_C

, changed the min value from 1.96 to 1.80

– For V

POR031_C

, changed the max value from 0.85 to 0.97.

– For T

VMFILTER

, replaced T with D.

– Min value of “V

POR200_C

” updated from “1.96” to “1.80”

– Max value of “V

POR031_C

” updated from “.85” “0.97”

– Changed the min value of parameter V

POR200_C

from “1.96” to “1.80”

– Changed the max value of parameter V

POR031_C

from “0.85” to “0.97”

– Changed the condition of parameter T

VMFILTER

from “T” to “D”

Table 38: Power management regulators

:

– Removed text “In parts packaged with LQFP176, the auxiliary and clamp regulators cannot be enabled” from note 2.

– Removed column “Internal

– linear regulator internal ballast”

– Removed “Internal standby regulator” from SPC58NE84E7 device.

Table 39: External components integration

:

– For PMOS, replaced “STT4P3LLH6” with “PMPB100XPEA”

– For NMOS, replaced “STT6N3LLH6” with “PMPB55XNEA”

– Added table footnote to typ value of C

S2

.

– Updated the parameters under ”SMPS Regulator Mode”

– Removed table footnote “External components number.......”

Table 44: SMPS Regulator specifications

:

– Removed “Power-up, before trimming, no load”, from V

SMPS

.

– Updated the Min, Typ, and Max values for “After trimming, max load”

– Added parameter δ F

SMPS.

– Updated parameter V

SMPS

.

– Added new parameter δ F

SMPS

Table 40: Linear regulator specifications

:

– Classification of parameter “IDD

MREG

” changed from “P” to “T”.

– Classification of parameter “IDD

MREG

” changed from “T” to “P”.

Table 41: Auxiliary regulator specifications :

– Classification of parameter “IDD

AUX

” changed from “P” to “T”.

– Classification of parameter “IDD

AUX

” changed from “T” to “P”.

DS11646 Rev 4 147/154

153

Revision history

Date

03-April-2017

SPC58EEx, SPC58NEx

Table 84. Document revision history (continued)

Revision Changes

2

Table 43: Standby regulator specifications

:

– Classification of parameter “IDD

SBY

” changed from “P” to “T”.

– Classification of parameter “IDD

SBY

” changed from “T” to “P”.

Table 17: Voltage monitor threshold definition :

Updated the figure.

Section 3.17: Flash memory

:

Updated the section.

Table 50: Nexus debug port timing

:

Classification of parameters “t

EVTIPW

” and “t

EVTOPW

” changed from “P” to “D”.

Table 56: DSPI CMOS master modified timing (full duplex and output only)

MTFE = 1, CPHA = 0 or 1 :

Changed the Min value of t

SCK

(very strong) from 33 to 59.

Table 57: DSPI LVDS master timing — full duplex — modified transfer format

(MTFE = 1), CPHA = 0 or 1 :

Added footnote “LVDS differential load considered is the capacitance on each terminal of the differential pair...”.

Table 58: DSPI LVDS master timing – output only – timed serial bus mode

TSB = 1 or ITSB = 1, CPOL = 0 or 1, continuous SCK clock

:

Added footnote “LVDS differential load considered is the capacitance on each terminal of the differential pair...”.

Table 54: DSPI channel frequency support

:

Added column to show slower and faster frequencies.

Section 5: Ordering information :

Renamed figure “Ordering information scheme” to “Commercial product scheme”

Added tables: Table 82: Code Flash options

, and

Table 83: RAM options

148/154 DS11646 Rev 4

SPC58EEx, SPC58NEx

Date

10-Oct-2017

Revision history

Table 84. Document revision history (continued)

Revision Changes

3

Following are the changes for this release of the document:

Editorial and formatting changes throughout the document.

Replaced all references of “SPC58xEx_IO_Definition_v3.1.xlsx” attached to this document by "device pin out IO definition excel file”

Updated the cover page.

Table 3: Parameter classifications

:

– Updated the description of classification tag “T”.

Table 4: Absolute maximum ratings

:

– Added text “In the range [1.26-1.33] V and if the above-mentioned......” to note 1.

Table 5: Operating conditions

:

– Removed note “Core voltage as ....”

– Changed the max value of parameter V

RAMP_LV to

“20”.

Table 9: Device consumption : Updated table and its values.

– Removed parameters I

DDAR_LV

, and I

DDAR_HV

– Updated parameter “I

DDHALT

”

– Updated parameter “I

DDSTOP

”

– “I

DD_LKG

” parameter: Classification “P” changed to “C” when T

J

Added footnote “I

DD_LKG

and I

DD_LV

are reported as...”

= 40 °C.

– “I

DD_LV

” parameter: added footnote “I

DD_LKG

and I

DD_LV

are reported as...”

Table 13: WEAK/SLOW I/O output characteristics

:

– For parameter “|t

SKEW_W

|”, changed max value from “30” to “25”.

Table 14: MEDIUM I/O output characteristics

:

– For parameter “|t

SKEW_W

|”, changed max value from “30” to “25”.

Table 15: STRONG/FAST I/O output characteristics :

– For parameter “|t

SKEW_W

|”, changed max value from “30” to “25”.

Table 11: I/O input electrical characteristics :

– For parameter “V ihcmos

BD”, swapped the conditions for off and on.

– Replaced all references to the IO_definitions excel file by “the device pin out

IO definition excel file”

Table 20: PLL0 electrical characteristics

:

– Added “f

INFIN

”

– Symbol “f

INFIN

” : changed “C” by “—” in column “C”

Table 21: PLL1 electrical characteristics

:

– Added “f

INFIN

”

– Symbol “f

INFIN

” : changed “C” by “—” in column “C”

Table 23: 32 kHz External Slow Oscillator electrical specifications :

– Added “CC” to T sxosc

.

Table 26: ADC pin specification

:

– For parameter C

P2

, updated the max value to “1”.

– Updated Max value for C

S

Table 27: SARn ADC electrical specification

:

– Added symbols tADCINIT and tADCBIASINIT

Table 28: ADC-Comparator electrical specification :

– Added new parameter “t

ADCINITSBY

”.

DS11646 Rev 4 149/154

153

Revision history

Date

10-Oct-2017

SPC58EEx, SPC58NEx

Table 84. Document revision history (continued)

Revision Changes

3 (cont’)

Table 29: SDn ADC electrical specification

:

– Added note “Propagation of the information...” to parameter t

LATENCY.

– For parameter F rolloff

(Stop band attenuation, Modified bandwidth mode), updated all the conditions.

Table 32: LVDS pad startup and receiver electrical characteristics, :

– For parameter ILVDS_BIAS, changed the characteristics to “C”

Table 36: LFAST PLL electrical characteristics :

– Min and Max value of parameter “ERR

REF

“+1” respectively

” updated from “TBD” to “-1” and

– Max value of parameter “PN” updated from “TBD” to “-58”

– Frequency of parameter “ Δ PER

REF

” updated from “10MHz” to “20MHz”.

– Max value of parameter “ Δ PER

REF from “TBD” to “350”

” for condition “Single period” updated

– Min and Max value of parameter “ Δ PER

REF

” for condition “Long period” updated from “TBD” to “-500” and “+500” respectively.

Figure 17: Voltage monitor threshold definition

:

– Right blue line adjusted on the top figure

Table 39: External components integration

:

– For parameter C

S1_B description column.

, replaced “HV supply” with “LV supply” in parameter

Table 78: FPBGA292 package mechanical data :

– Updated the second table footnote.

Section 3.17: Flash memory

:

– Updated the section.

Section 3.18.6: CAN timing

:

– Added this section.

150/154 DS11646 Rev 4

SPC58EEx, SPC58NEx

Date

01-Jul-2019

Revision history

Table 84. Document revision history (continued)

Revision Changes

4

Hereunder are the changes for this release of the document with respect to revision 3:

Cover Page

Removed Registered symbol in title as per latest procedure.

Rephrased introduction sentence since the pinout excel file will no longer be attached to the datasheet

Section 3.1: Introduction

– Reformatted note from introduction

Table 4: Absolute maximum ratings

: Added cross reference to footnote

(3)

to all

V

DD_HV*

and V

IN

Section 3.3: Operating conditions

Table 5: Operating conditions

:

T

J

: changed value in column C from “P” to “C”.

Table 9: Device consumption :

– For I

SPIKE

updated footnote and “SR” to “CC” and for I footnote.

SR updated the second

– Deleted I

DD_LV_TCU

, I

DD_HV_TCU

, I

DD_LV_ECU

, I

DD_HV_ECU

.

– Updated footnote 4: Use case.

Table 15: STRONG/FAST I/O output characteristics : updated values for t

TR_S for condition CL = 25 pF and CL = 50 pF

Table 16: VERY STRONG/VERY FAST I/O output characteristics :

– “tTR20-80” replaced by “tTR20-8_V”

– “tTRTTL” replaced by “tTRTTL_V”

– “ Σ t

TR20-80

” replaced by “ Σ t

TR20-80_V

”

Section 3.9: Reset pad (PORST, ESR0) electrical characteristics

–

Figure 5: Startup Reset requirements

: deleted V

DDMIN

–

Table 18: Reset PAD electrical characteristics : added values for Conditions =

3.3V.

Table 20: PLL0 electrical characteristics

:

– |Δ

PLL0PHI0SPJ

|: added pk-pk to Conditions value

– |Δ

PLL0PHI1SPJ

|: added pk-pk to Conditions value

– The maximum value of f

PLL0PHI0 footnote.

is changed from “400” to “FSYS” with a

– changed condition from T to D for |Δ

PLL0PHI1SPJ

|, Δ

PLL0LTJ

and I

PLL0.

Table 21: PLL1 electrical characteristics

:

– changed condition from T to D for I

PLL1.

Table 22: External 40 MHz oscillator electrical specifications

:

– Changed table footnote 3 by: This value is determined by the crystal manufacturer and board design, and it can potentially be higher than the maximum provided.

– Table footnote 1 updated: “DCF clients XOSC_LF_EN and

XOSC_EN_40MHZ” changed by “XOSC_FREQ_SEL”

Table 23: 32 kHz External Slow Oscillator electrical specifications : Updated the

parameter symbols.

Added “CC” to T sxosc

.

DS11646 Rev 4 151/154

153

Revision history

Date

01-Jul-2019

SPC58EEx, SPC58NEx

Table 84. Document revision history (continued)

Revision Changes

4(cont’)

Section 3.11.3: RC oscillator 16 MHz

–

Table 24: Internal RC oscillator electrical specifications

: updated Max value for I

FIRC.

Table 26: ADC pin specification

:

– Added electrical specification for R

20K Ω

– Added row for symbol “C

EXT

/ SR”.

symbol.

Table 27: SARn ADC electrical specification

:

– column “C” splited and added “D” for I

ADV_S

– Added electrical specification for R

20K Ω

symbol.

Table 28: ADC-Comparator electrical specification :

– Set min = 5/f

ADCK mode, at symbol t

µs for 10-bit ADC mode, min = 2/f

ADCK

ADCSAMPLE

.

for ADC comparator

– column “C” split and added “D” for I

ADV_S

– Added “ADC comparator mode” condition to the following two parameters:

I

ADCREFH

Min: - and Max: 19.5 µA

I

ADCREFL

Min: - and Max: 20.5 µA

Figure 8: Input equivalent circuit (Fast SARn and SARB channels) : Added

parameter “C

EXT

: external capacitance” and component to scheme.

Section 3.12.4: S/D ADC electrical specification

– Added note.

–

Table 29: SDn ADC electrical specification

:

Table 29: SDn ADC electrical specification

:

– Updated Max value before calibration for V

OFFSET,

IBIAS, I

ADV_D

.

– Updated footnote “S/D ADC is functional...”

– Added footnote “The absolute value...” for |δ

GAIN

| .

– updated V cmrr

.

Section 3.12.5: SD ADC filter modes

: added this section

Updated

Figure 9: LFAST and MSC/DSPI LVDS timing definition

Table 32: LVDS pad startup and receiver electrical characteristics,

Updated footnote #12 starting with “Value valid for LFAST mode...” with new sentence containing DSPI mode related data.

Section 3.16: Power management

: Changed “flash” by “Flash” throughout the chapter

Section 3.16.1: Power management integration

: added sentence “It is recommended...device itself” for all devices

Table 40: Linear regulator specifications

:

– updated values for symbol “ Δ IDD

MREG”:

Min: added -200, Max: added 200

– For Δ IDD

MREG

Added a footnote “Internal schemes must be....”.

Figure 15: SMPS Regulator Mode : Figure updated and footnote added

Table 44: SMPS Regulator specifications

:

– For “ Δ IDD

SMPS” updated the Min and Max values. Added a table footnote.

– Updated Min and Max values for Δ IDD

SMPS from 100 to 200.

– Changed condition for IDD

SMPS.

Section 3.16.1: Power management integration

Table 39: External components integration : added unit to Max value for C

s2

C s1_A

.

and

152/154 DS11646 Rev 4

SPC58EEx, SPC58NEx

Date

01-Jul-2019

Revision history

Table 84. Document revision history (continued)

Revision Changes

4(cont’)

Section 3.16.2: Voltage regulators

Section 3.16.1: Power management integration

–

Table 39: External components integration : updated Conditions for C

BV

.

Section 3.16.3: Voltage monitors

Table 45: Voltage monitor electrical characteristics : added footnote “Even if

LVD/HVD ...”

Table 46: Wait State configuration

: for APC=001 changed the minimum frequency from 40 to 55 MHz.

Section 3.17: Flash memory

Updated

Table 47: Flash memory program and erase specifications

Table 48: Flash memory Life Specification

: updated table with N

CER128K

N

DER16K

.

and

Updated

Table 54: DSPI channel frequency support

Table 68: TxEN output characteristics

: added table footnote “ Pad configured as

VERY STRONG.”

Table 69: TxD output characteristics :

changed note 3 to apply to the whole table

Table 72: CAN timing

: added columns for “CC” and “D”

Section 3.18.3.7: RMII transmit signal timing (TXD[1:0], TX_EN) : added Note

“RMII transmit ... as 1ns”.

Section 3.18.1.2: Nexus interface timing

–

Table 50: Nexus debug port timing :

Updated Min values for t

TCYC

Absolute minimum TCK cycle time.

Updated Max value on line 15.

– Figure 16: Nexus output timing : deleted this figure.

Table 79: FPBGA292 package mechanical data

: updated Amax formula in table footnote 2.

Section 4.1: eLQFP176 package information

: updated section according latest

POA.

Section 4.2: FPBGA292 package information

–

Figure 54: FPBGA292 package outline : minor format changes.

–

Table 79: FPBGA292 package mechanical data

: updated footnote 2.

Table 80: Thermal characteristics for 176 exposed pad LQFP package

and

Table 81: Thermal characteristics for 292-pin FPBGA updated values

DS11646 Rev 4 153/154

153

SPC58EEx, SPC58NEx

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