STMicroelectronics STA309B Datasheet
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STA309B
Multichannel digital audio processor with FFX
®
Preliminary data
Features
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8 channels of 24-bit FFX
®
>100 dB SNR and dynamic range
Selectable 32 kH-192 kHz input sampling rates
6 channels of DSD/SACD and PDM input
Digital gain/attenuation +58 dB to -100 dB in
0.5 dB steps
Advanced “pop-free” operation
Digital “pop-free” operation for single-ended mode
Soft volume update
Individual channel and master gain/attenuation plus channel trim (-10 dB to +10 dB)
Up to 10 independent 32-bit userprogrammable biquads (EQ) per channel
Bass/treble tone control
Pre- and post-EQ full 8-channel input mix on all
8 channels
Dual independent limiters/compressors
Dynamic range compression or anti-clipping modes
AutoModes
– 5-band graphic EQ
– 32 preset EQ curves (rock, jazz, pop, etc.)
– Automatic volume controlled loudness
– 5.1 to 2-channel downmix
– Simultaneous 5.1- and 2-channel downmix outputs
– 3 preset volume curves
– 2 preset anti-clipping modes
– Preset movie nighttime listening mode
– Preset TV channel/commercial AGC mode
– 5.1, 2.1 bass management configurations
– AM frequency automatic output PWM frequency shifting
– 8 preset crossover filters
Individual channel and master soft/hard mute
VFQFPN-56
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Automatic zero-detect and invalid input mute
Automatic amplifier power-down on clock loss
Advanced AM interference frequency switching and noise suppression modes
I
2
S output channel mapping function
Independent channel volume and DSP bypass
Channel mapping of any input to any processing/FFX channel
Selectable per-channel FFX damped ternary or binary PWM output
Max power correction for lower full-power THD
Variable per-channel FFX output delay control
192 kHz internal processing sampling rate,
24-bit to 36-bit precision
Description
The STA309B is a single-chip solution for digital audio processing and control in multichannel applications and provides output capabilities for
FFX (full flexible amplification). In conjunction with an FFX power device, it provides high-quality, high-efficiency, all-digital amplification. The device is extremely versatile, allowing for input of most digital formats including 6.1/7.1-channel and
192 kHz, 24-bit DVD-audio, DSD/SACD and PDM for MEMS microphone inputs. In the 5.1 application, the additional 2 channels can be used for audio line-out or headphone drive. In speaker mode, with 8 channel outputs in parallel, the
STA309B can deliver 1 W (maximum).
Table 1.
Device summary
Order code Package
STA309B VFQFPN56
STA309BTR VFQFPN56
Packaging
Tube
Tape and reel
January 2012 Doc ID 022570 Rev 2 1/66 www.st.com
66
Contents
Contents
STA309B
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
C bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Application reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Configuration register A (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Configuration register B (0x01) - serial input formats . . . . . . . . . . . . . . 24
Configuration register C (0x02) - serial output formats . . . . . . . . . . . . . 26
Configuration register D (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Configuration register E (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Configuration register F (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/66 Doc ID 022570 Rev 2
STA309B Contents
Configuration register G (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Configuration register H (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Configuration register I (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Master mute register (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Master volume register (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Channel 1 volume (0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Channel 2 volume (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Channel 3 volume (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Channel 4 volume (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Channel 5 volume (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Channel 6 volume (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Channel 7 volume (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Channel 8 volume (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Channel 1 volume trim, mute, bypass (0x13) . . . . . . . . . . . . . . . . . . . . 34
Channel 2 volume trim, mute, bypass (0x14) . . . . . . . . . . . . . . . . . . . . 34
Channel 3 volume trim, mute, bypass (0x15) . . . . . . . . . . . . . . . . . . . . 34
Channel 4 volume trim, mute, bypass (0x16) . . . . . . . . . . . . . . . . . . . . 35
Channel 5 volume trim, mute, bypass (0x17) . . . . . . . . . . . . . . . . . . . . 35
Channel 6 volume trim, mute, bypass (0x18) . . . . . . . . . . . . . . . . . . . . 35
Channel 7 volume trim, mute, bypass (0x19) . . . . . . . . . . . . . . . . . . . . 35
Channel 8 volume trim, mute, bypass (0x1A) . . . . . . . . . . . . . . . . . . . . 35
Channel input mapping channels 1 and 2 (0x1B) . . . . . . . . . . . . . . . . . 37
Channel input mapping channels 3 and 4 (0x1C) . . . . . . . . . . . . . . . . . 37
Channel input mapping channels 5 and 6 (0x1D) . . . . . . . . . . . . . . . . . 37
Channel input mapping channels 7 and 8 (0x1E) . . . . . . . . . . . . . . . . . 37
AUTO1 - AutoModes EQ, volume, GC (0x1F) . . . . . . . . . . . . . . . . . . . . 38
AUTO2 - AutoModes bass management2 (0x20) . . . . . . . . . . . . . . . . . 39
AUTO3 - AutoMode AM/pre-scale/bass management scale (0x21) . . . 40
PREEQ - preset EQ settings (0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
AGEQ - graphic EQ 80-Hz band (0x23) . . . . . . . . . . . . . . . . . . . . . . . . . 42
BGEQ - graphic EQ 300-Hz band (0x24) . . . . . . . . . . . . . . . . . . . . . . . . 42
CGEQ - graphic EQ 1-kHz band (0x25) . . . . . . . . . . . . . . . . . . . . . . . . . 42
DGEQ - graphic EQ 3-kHz band (0x26) . . . . . . . . . . . . . . . . . . . . . . . . . 42
EGEQ - graphic EQ 8-kHz band (0x27) . . . . . . . . . . . . . . . . . . . . . . . . . 43
Biquad internal channel loop-through (0x28) . . . . . . . . . . . . . . . . . . . . . 43
Mix internal channel loop-through (0x29) . . . . . . . . . . . . . . . . . . . . . . . 44
Doc ID 022570 Rev 2 3/66
Contents STA309B
Tone control bypass (0x2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Channel limiter select channels 1,2,3,4 (0x2D) . . . . . . . . . . . . . . . . . . . 45
Channel limiter select channels 5,6,7,8 (0x2E) . . . . . . . . . . . . . . . . . . . 45
Limiter 1 attack/release rate (0x2F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Limiter 1 attack/release threshold (0x30) . . . . . . . . . . . . . . . . . . . . . . . . 46
Limiter 2 attack/release rate (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Limiter 2 attack/release threshold (0x32) . . . . . . . . . . . . . . . . . . . . . . . . 46
Channel 1 and 2 output timing (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Channel 3 and 4 output timing (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Channel 5 and 6 output timing (0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Channel 7 and 8 output timing (0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2
S output mapping channels 1 and 2 (0x37) . . . . . . . . . . . . . 51
2
S output mapping channels 3 and 4 (0x38) . . . . . . . . . . . . . 51
2
S output mapping channels 5 and 6 (0x39) . . . . . . . . . . . . . 51
2
S output mapping channels 7 and 8 (0x3A) . . . . . . . . . . . . . 52
Coefficient address register 1 (0x3B) . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Coefficient address register 2 (0x3C) . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Coefficient b1 data register, bits 23:16 (0x3D) . . . . . . . . . . . . . . . . . . . . 52
Coefficient b1 data register, bits 15:8 (0x3E) . . . . . . . . . . . . . . . . . . . . . 53
Coefficient b1 data register, bits 7:0 (0x3F) . . . . . . . . . . . . . . . . . . . . . . 53
Coefficient b2 data register, bits 23:16 (0x40) . . . . . . . . . . . . . . . . . . . . 53
Coefficient b2 data register, bits 15:8 (0x41) . . . . . . . . . . . . . . . . . . . . . 53
Coefficient b2 data register, bits 7:0 (0x42) . . . . . . . . . . . . . . . . . . . . . . 53
Coefficient a1 data register, bits 23:16 (0x43) . . . . . . . . . . . . . . . . . . . . 53
Coefficient a1 data register, bits 15:8 (0x44) . . . . . . . . . . . . . . . . . . . . . 53
Coefficient a1 data register, bits 7:0 (0x45) . . . . . . . . . . . . . . . . . . . . . . 54
Coefficient a2 data register, bits 23:16 (0x46) . . . . . . . . . . . . . . . . . . . . 54
Coefficient a2 data register, bits 15:8 (0x47) . . . . . . . . . . . . . . . . . . . . . 54
Coefficient a2 data register, bits 7:0 (0x48) . . . . . . . . . . . . . . . . . . . . . . 54
Coefficient b0 data register, bits 23:16 (0x49) . . . . . . . . . . . . . . . . . . . . 54
Coefficient b0 data register, bits 15:8 (0x4A) . . . . . . . . . . . . . . . . . . . . . 54
Coefficient b0 data register, bits 7:0 (0x4B) . . . . . . . . . . . . . . . . . . . . . . 54
Coefficient write control register (0x4C) . . . . . . . . . . . . . . . . . . . . . . . . . 55
Reading a coefficient from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Reading a set of coefficients from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4/66 Doc ID 022570 Rev 2
STA309B
Contents
Writing a single coefficient to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Writing a set of coefficients to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Equalization and mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Variable maximum power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
MPCC1-2 (0x4D, 0x4E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Variable distortion compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
DCC1-2 (0x4F, 0x50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
PSC1-2: ripple correction value (RCV) (0x51, 0x52) . . . . . . . . . . . . . . . 60
PSC3: correction normalization value (CNV) (0x53) . . . . . . . . . . . . . . . 60
Digital pop-free operation in single-ended mode . . . . . . . . . . . . . . . . . . . 60
PFCXON: digital pop-free register (0x5F) . . . . . . . . . . . . . . . . . . . . . . . 61
RAMPTIM: ramp duration register (0x66) . . . . . . . . . . . . . . . . . . . . . . . 62
TSPUPT: waiting time after EAPD (0x67 - 0x68) . . . . . . . . . . . . . . . . . . 62
LSPDWT: waiting time before EAPD (0x71 - 0x72) . . . . . . . . . . . . . . . . 62
Doc ID 022570 Rev 2 5/66
List of tables
List of tables
STA309B
6/66 Doc ID 022570 Rev 2
STA309B
List of figures
List of figures
Doc ID 022570 Rev 2 7/66
Block diagram STA309B
Figure 1.
Block diagram
SA SCL SDA MVO
LRCKI
BICKI
SDI12
SDI34
SDI56
SDI78
SERIAL
DATA
IN
I 2 C
SYSTEM
CONTROL
OVERSAMPLING
PLLB
CHANNEL
MAPPING
VARIABLE
OVER-
SAMPLING
PLL
SYSTEM TIMING
POWER
DOWN
TREBLE,
BASS, EQ
(BIQUADS )
VOLUME
LIMITING
VARIABLE
DOWN-
SAMPLING
XTI CKOUT PWDN EAPD
DDX
FFX
SERIAL
DATA
OUT
Figure 2.
Channel signal flow
6 Inputs
From DSD
DSD
Conversion
Interp_Rate
8 Inputs
From I2S
1x,2x,4x
Interp
DSDE
Mapping/
Mix #1
Biquads
B/T
Mix #2
Volume
Limiter
2x
Interp
OUT1A/B
OUT2A/B
OUT3A/B
OUT4A/B
OUT5A/B
OUT6A/B
OUT7A/B
OUT8A/B
LRCKO
BICKO
SDO12
SDO34
SDO56
SDO78
DDX
Output
Distortion
Compensation
NS C_Con PWM
From
Mix#1
Engine
Or
Previous
Channel
Biquad#10
Output
(CxBLP)
PreScale
Hard Set to
-18dB when
AutoMode EQ
(AMEQ)
High-Pass
Filter
User Progammable
Biquad #1 when
High-Pass Bypassed
(HPB)
Biquad
#2
Biquad
#3
Biquad
#4
Biquad
#5
Hard Set Coeffecients when AutoMode EQ
(AMEQ)
Biquad
#6
Biquad
#7
Biquad
#8
Bass Treble
Hard Set
Coeffecients when
AutoMode
Bass Management
Crossover
(AMBMXE)
Hard Set
Coeffecients when
DeEmphasis
Enabled
(DEMP)
User Programmable
Biquads #9 and #10
When Tone Bypassed
(CxTCB)
To
Mix#2
Engine
8/66 Doc ID 022570 Rev 2
STA309B
Figure 3.
Pin connections (top view)
MVO 1
GND 2
VDD 3
GND 4
SDI_78 5
SDI_56 6
SDI_34 7
SDI_12 8
LRCKI 9
BICKI 10
VDD 11
GND 12
RESET 13
BYPASS 14
VFQFPN-56
Pin connections
42 OUT2_A
41 OUT2B
40 GND
39 VDD
38 OUT3_A
37 OUT3_B
36 OUT4_A
35 OUT4_B
34 OUT5_A
33 OUT5_B
32 GND
31 VDD
30 OUT6_A
29 OUT6_B
Doc ID 022570 Rev 2 9/66
Pin connections STA309B
Table 2.
Pin description
STA309B pin
1
5
6
7
8
9
10
13
14
15
16
17
18
19
20
21
22
25
26
27
28
29
Type
5-V tolerant TTL input buffer
5-V tolerant TTL input buffer
5-V tolerant TTL input buffer
5-V tolerant TTL input buffer
5-V tolerant TTL input buffer
5-V tolerant TTL input buffer
5-V tolerant TTL input buffer
5-V tolerant TTL schmitt trigger input buffer
CMOS input buffer with pull-down
CMOS input buffer with pull-down
PLL_BYPASS
SA
Bidirectional buffer: 5-V tolerant TTL schmitt trigger input; 3.3-V capable
2 mA slew-rate controlled output
SDA
5-V tolerant TTL schmitt trigger input buffer
5-V tolerant TTL schmitt trigger input buffer
RESET
SCL
XTI
Analog pad
Analog ground
3.3V analog supply voltage
FILTER_PLL
GNDA
VDDA
3.3-V capable TTL tristate 4mA output buffer
3.3-V capable TTL 2mA output buffer
3.3-V capable TTL 2mA output buffer
3.3-V capable TTL 2mA output buffer
3.3-V capable TTL 2mA output buffer
3.3-V capable TTL 2mA output buffer
CKOUT
OUT8B
OUT8A
OUT7B
OUT7A
OUT6B
Name
MVO/DSD_CLK
SDI_78/DSD_6
SDI_56/DSD_5
SDI_34/DSD_4
SDI_12/DSD_3
LRCKI/DSD_2
BICKI/DSD_1
Description
Master volume override/
DSD input clock
Input serial data channels 7 & 8/
DSD input channel 6
Input serial data channels 5 & 6/
DSD input channel 5
Input serial data channels 3 & 4/
DSD input channel 4
Input serial data channels 1 & 2/
DSD input channel 3
Input left/right clock/
DSD input channel 2
Input serial clock/
DSD input channel 1
Global reset
Bypass phase locked loop
Select address (I
2
Serial data (I
Serial clock (I
PLL filter
PLL ground
PLL supply
2
2
C)
C)
C)
Crystal oscillator input (clock input)
Clock output
PWM channel 8 output B
PWM channel 8 output A
PWM channel 7 output B
PWM channel 7 output A
PWM channel 6 output B
10/66 Doc ID 022570 Rev 2
STA309B
Table 2.
Pin description (continued)
STA309B pin Type
30
33
34
35
36
37
38
41
42
43
44
45
48
49
50
51
54
55
3.3-V capable TTL 2mA output buffer
3.3-V capable TTL 2mA output buffer
3.3-V capable TTL 2mA output buffer
3.3-V capable TTL 2mA output buffer
3.3-V capable TTL 2mA output buffer
3.3-V capable TTL 2mA output buffer
3.3-V capable TTL 2mA output buffer
3.3-V capable TTL 2mA output buffer
3.3-V capable TTL 2mA output buffer
3.3-V capable TTL 2mA output buffer
3.3-V capable TTL 2mA output buffer
3.3-V capable TTL 4mA output buffer
3.3-V capable TTL 2mA output buffer
3.3-V capable TTL 2mA output buffer
3.3-V capable TTL 2mA output buffer
3.3-V capable TTL 2mA output buffer
3.3-V capable TTL 2mA output buffer
3.3-V capable TTL 2mA output buffer
56
5-V tolerant TTL schmitt trigger input buffer
3,11,21,24,31,39,
46,52
3.3-V digital supply voltage
2,4,12,20,23,32,
40,47,53
Digital ground
SDO_34
SDO_56
SDO_78
PWDN
VDD
GND
OUT2B
OUT2A
OUT1B
OUT1A
EAPD
BICKO
LRCKO
SDO_12
Name
OUT6A
OUT5B
OUT5A
OUT4B
OUT4A
OUT3B
OUT3A
Pin connections
Description
PWM channel 6 output A
PWM channel 5 output B
PWM channel 5 output A
PWM channel 4 output B
PWM channel 4 output A
PWM channel 3 output B
PWM channel 3 output A
PWM channel 2 output B
PWM channel 2 output A
PWM channel 1 output B
PWM channel 1 output A
Ext. amp power-down
Output serial clock
Output left/right clock
Output serial data channels 1&2
Output serial data channels 3&4
Output serial data channels 5&6
Output serial data channels 7&8
Device power-down
3.3-V supply
Ground
Doc ID 022570 Rev 2 11/66
Electrical specifications STA309B
3.1 Absolute maximum ratings
Table 3.
Symbol
V
DD
V
DDA
V i
V o
T stg
T amb
Absolute maximum ratings
Parameter
3.3-V I/O power supply
3.3-V logic power supply
Voltage on input pins
Voltage on output pins
Storage temperature
Ambient operating temperature
-0.5
-0.5
-0.5
-0.5
-40
-40
Min Typ Max Unit
4 V
4 V
VDD + 0.5 V
VDD + 0.3 V
150 °C
90 °C
3.3
Table 4.
Symbol
R thj-case
Thermal data
Parameter
Thermal resistance, junction-case (thermal pad)
STA309B
Min Typ Max
1.5
Unit
°C/W
Recommended operating conditions
Table 5.
Symbol
V
DD
V
DDA
T j
Recommended operating conditions
Parameter
I/O power supply
Logic power supply
Operating junction temperature
Min
3.0
3.0
-40
Typ Max
3.6
3.6
125
Unit
V
V
°C
12/66 Doc ID 022570 Rev 2
STA309B Electrical specifications
The following specifications are valid for V
DD
= 3.3 V ± 0.3 V, V
DDA
= 3.3 V ± 0.3 V and
Tamb = 0 to 70 °C, unless otherwise stated.
Table 6.
Symbol
I il
I ih
I
OZ
V esd
General interface electrical specifications
Parameter Conditions
Low-level input no pull-up V i
= 0 V
High-level input no pull-down
V i
= V
DD
Tristate output leakage without pull-up/down
Electrostatic protection
(human body model)
V i
= V
DD
Leakage < 1 μ A
Min Typ Max Unit
1
(1) μ A
2000
2
2
μ A
μ A
V
1.
The leakage currents are generally very small, < 1 nA. The values given here are maximum after an electrostatic stress on the pin.
Table 7.
DC electrical characteristics: 3.3-V buffers
Symbol Parameter Conditions Min Typ Max Unit
V
IL
V
IH
V
ILhyst
V
IHhyst
V hyst
V ol
Low-level input voltage
High-level input voltage
Low-level threshold
High-level threshold
Schmitt trigger hysteresis
Low-level output
Input falling
Input rising
IoI = 100 µA
2.0
0.8
1.3
0.3
0.8
V
V
1.35
V
2.0
V
0.8
V
0.2
V
V oh
High-level output
Ioh = -100 µA
Ioh = -2 mA
VDD-
0.2
2.4
V
V
Doc ID 022570 Rev 2 13/66
Pin description STA309B
Master volume override (MVO)
This pin enables the user to bypass the volume control on all channels. When MVO is pulled high, the master volume register is set to 0x00, which corresponds to its full-scale setting.
The master volume register setting offsets the individual channel volume settings, which default to 0 dB.
Serial data in (SDI_12, SDI_34, SDI_56, SDI_78)
Audio information enters the device here. Six format choices are available including I
2
S, left- or right-justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.
RESET
Driving this pin low turns off the outputs and returns all settings to their defaults.
I
2
C bus
The SA, SDA and SCL pins operate per the Phillips I
2
C specification. See
.
Phase locked loop (PLL)
The phase locked loop section provides the system timing signals and CKOUT.
Clock output (CKOUT)
System synchronization and master clocks are provided by CKOUT.
PWM outputs (OUT1 through OUT8)
The PWM outputs provide the input signal for the power devices.
External amplifier power-down (EAPD)
This signal can be used to control the power-down of FFX power devices.
Serial data out (SDO_12, SDO_34, SDO_56, SDO_78)
These are the outputs for audio information. Six different formats are available including I
2
S, left- or right-justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.
Device power-down (PWDN)
Pulling PWDN low begins the power-down sequence which puts the STA309B into a low-power state. EAPD (pin 51) goes low approximately 30 ms later.
14/66 Doc ID 022570 Rev 2
STA309B
5 I
2
C bus operation
I
2
C bus operation
The STA309B supports the I
2
C protocol via the input ports SCL and SDA_IN (master to slave) and the output port SDA_OUT (slave to master).
This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver.
The device that controls the data transfer is known as the master and the other as the slave.
The master always starts the transfer and provides the serial clock for synchronization. The
STA309B is always a slave device in all of its communications.
5.1.1 Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. An SDA transition while the clock is high is used to identify a START or STOP condition.
START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer.
STOP is identified by low to high transition of the data bus SDA signal while the clock signal
SCL is stable in the high state. A STOP condition terminates communication between the
STA309B and the bus master.
During the data input the STA309B samples the SDA signal on the rising edge of clock SCL.
For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low.
To start communication between the master and the Omega FFX core, the master must initiate with a start condition. Following this, the master sends 8 bits to the SDA line (MSB first) corresponding to the device select address and read or write mode.
The 7 most significant bits are the device address identifiers, corresponding to the I
2
C bus definition. In the STA309B the I
2
C interface has two device addresses depending on the SA port configuration, 0x40 or 0100000x when SA = 0, and 0x42 or 0100001x when SA = 1.
The 8 th
bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and 0 for write mode. After a START condition, the STA309B identifies on the bus the device address and if a match is found, it acknowledges the identification on the SDA bus during
Doc ID 022570 Rev 2 15/66
I
2
C bus operation STA309B the 9 th
-bit time. The byte following the device identification byte is the internal space address.
Following the START condition the master sends a device select code with the RW bit set to 0. The STA309B acknowledges this and then waits for the byte of internal address.
After receiving the internal byte address the STA309B again responds with an acknowledgement.
In the byte write mode the master sends one data byte, this is acknowledged by the FFX core. The master then terminates the transfer by generating a STOP condition.
The multi-byte write modes can start from any internal address. The master generating a
STOP condition terminates the transfer.
Figure 4.
Write mode sequence
ACK ACK ACK
BYTE
WRITE
DEV-ADDR SUB-ADDR DATA IN
START RW
ACK ACK ACK
STOP
ACK
MULTIBYTE
WRITE
DEV-ADDR SUB-ADDR DATA IN DATA IN
START RW STOP
Figure 5.
Read mode sequence
ACK NO ACK
CURRENT
ADDRESS
READ
DEV-ADDR DATA
START RW
ACK ACK
STOP
RANDOM
ADDRESS
READ
DEV-ADDR SUB-ADDR
START RW
RW=
HIGH
ACK ACK
S T A R T
SEQUENTIAL
CURRENT
READ
DEV-ADDR DATA
START
ACK ACK
SEQUENTIAL
RANDOM
READ
DEV-ADDR SUB-ADDR
START RW S T A R T
DATA
DEV-ADDR
DEV-ADDR
R W
ACK
R W
ACK
ACK
DATA
DATA
DATA
NO ACK
NO ACK
STOP
ACK
STOP
DATA
ACK
DATA
NO ACK
STOP
16/66 Doc ID 022570 Rev 2
STA309B
6 Application reference schematic
Application reference schematic
Figure 6.
Reference schematic for STA309B-based application
C4 2.2UF
6.3VDC EIA3216_A
CH1_A CH1_B
54
55
57
56
59
58
52
51
53
50
49
63
62
64
61
60
.3_6
EAPD
GND_6
NC 54
BICKO
OUT1_A
OUT1_B
LRCKO
SDO_12
.3_7
GND_7
NC 61
SDO_34
SDO_56
SDO_78
PWDN
VDD3
VDD3
CH4_A CH4_B CH5_A CH5_B
ER
GNDA_PLL
VDDA_PLL
.3_3
NC 26
CKOUT
OUT8_B
OUT8_A
GND_3
VDD3
OUT7_B
OUT7_A
VDD3.3_PLL
24
23
21
20
22
19
18
17
29
30
31
32
26
25
27
28
SA
SDA
XTI
SCL
PLL_FILT
C22 22UF 6.3VDC EIA3528_B
SDATA1 SDATA0
Doc ID 022570 Rev 2 17/66
Registers
7 Registers
STA309B
Table 8.
Addr
Register summary
Name D7 D6 D5 D4 D3
Configuration
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
Volume control
CONFA
ConfB
ConfC
ConfD
ConfE
ConfF
ConfG
ConfH
ConfI
MMUTE
Mvol
C1Vol
C2Vol
C3Vol
C4Vol
C5Vol
C6Vol
C7Vol
C8Vol
C7V7
C8V7
C1VTMB C1M
C2VTMB C2M
C3VTMB C3M
C4VTMB C4M
C5VTMB C5M
C6VTMB C6M
C7VTMB C7M
C8VTMB C8M
MV7
C1V7
C2V7
C3V7
C4V7
C5V7
C6V7
COS1 COS0 DSPB IR1
SAIFB
IR0
SAI3
SAOFB SAO3
CSZ2 CSZ1 MPC CSZ4 CSZ3
C8BO C7BO C6BO C5BO
PWMS2 PWMS1 PWMS0 BQL
C4BO
PSL
MPCV
ECLE
EAPD
DCCV
LDTE
HPE
BCLE
AM2E
IDE
AME
ZDE
MV6
C1V6
C2V6
C3V6
C4V6
C5V6
C6V6
C7V6
C8V6
C1VBP
C2VBP
C3VBP
C4VBP
C5VBP
C6VBP
C7VBP
C8VBP
MV5
C1V5
C2V5
C3V5
C4V5
C5V5
C6V5
C7V5
C8V5
C7V4
C8V4
C1VT4
C2VT4
C3VT4
C4VT4
C5VT4
C6VT4
C7VT4
C8VT4
MV4
C1V4
C2V4
C3V4
C4V4
C5V4
C6V4
C7V3
C8V3
C1VT3
C2VT3
C3VT3
C4VT3
C5VT3
C6VT3
C7VT3
C8VT3
MV3
C1V3
C2V3
C3V3
C4V3
C5V3
C6V3
D2
MCS2
SAI2
SAO2
CSZ0
C3BO
DEMP
COD
SVE
C7V2
C8V2
C1VT2
C2VT2
C3VT2
C4VT2
C5VT2
C6VT2
C7VT2
C8VT2
MV2
C1V2
C2V2
C3V2
C4V2
C5V2
C6V2
D1
MCS1
SAI1
SAO1
OM1
C2BO
DRC
SID
ZCE
D0
C7V0
C8V0
C1VT0
C2VT0
C3VT0
C4VT0
C5VT0
C6VT0
C7VT0
C8VT0
MMUTE
MV0
C1V0
C2V0
C3V0
C4V0
C5V0
C6V0
C7V1
C8V1
C1VT1
C2VT1
C3VT1
C4VT1
C5VT1
C6VT1
C7VT1
C8VT1
MV1
C1V1
C2V1
C3V1
C4V1
C5V1
C6V1
MCS0
SAI0
SAO0
OM0
C1BO
HPB
PWMD
NSBW
PSCE
18/66 Doc ID 022570 Rev 2
STA309B Registers
Table 8.
Addr
Register summary (continued)
Name D7 D6 D5 D4 D3 D2 D1 D0
Input mapping
0x1B
0x1C
0x1D
0x1E
C12im
C34im
C56im
C78im
C2IM2
C4IM2
C6IM2
C8IM2
C2IM1
C4IM1
C6IM1
C8IM1
C2IM0
C4IM0
C6IM0
C8IM0
C1IM2
C3IM2
C5IM2
C7IM2
C1IM1
C3IM1
C5IM1
C7IM1
C1IM0
C3IM0
C5IM0
C7IM0
AutoMode
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
Auto1
Auto2
Auto3
PreEQ
Ageq
Bgeq
Cgeq
Dgeq
Egeq
AMDM
SUB
AMGC2 AMGC1 AMGC0 AMV1
RSS1 RSS0 CSS1
AMAM2 AMAM1 AMAM0 AMAME
CSS0
XO2 XO1 XO0
AMV0
FSS
AMEQ1 AMEQ0
AMBMXE AMBMME
MSA AMPS
PEQ4 PEQ3 PEQ2 PEQ1 PEQ0
AGEQ4 AGEQ3 AGEQ2 AGEQ1 AGEQ0
BGEQ4 BGEQ3 BGEQ2 BGEQ1 BGEQ0
CGEQ4 CGEQ3 CGEQ2 CGEQ1 CGEQ0
DGEQ4 DGEQ3 DGEQ2 DGEQ1 DGEQ0
EGEQ4 EGEQ3 EGEQ2 EGEQ1 EGEQ0
Processing loop
0x28
0x29
BQlp
MXlp
Processing bypass
C8BLP C7BLP C6BLP C5BLP C4BLP C3BLP C2BLP C1BLP
C8MXLP C7MXLP C6MXLP C5MXLP C4MXLP C3MXLP C2MXLP C1MXLP
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x2A
0x2B
EQbp C8EQBP C7EQBP C6EQBP C5EQBP C4EQBP C3EQBP C2EQBP C1EQBP
ToneBP C8TCB C7TCB C6TCB C5TCB C4TCB C3TCB C2TCB C1TCB
Tone control
0x2C Tone TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0
Dynamics control
C1234ls
C5678ls
L1ar
L1atrt
L2ar
L2atrt
PWM output timing
C4LS1
C8LS1
L1A3
L1AT3
L2A3
L2AT3
C4LS0
C8LS0
L1A2
L1AT2
L2A2
L2AT2
C3LS1
C7LS1
L1A1
L1AT1
L2A1
L2AT1
C3LS0
C7LS0
L1A0
L1AT0
L2A0
L2AT0
C2LS1
C6LS1
L1R3
L1RT3
L2R3
L2RT3
C2LS0
C6LS0
L1R2
L1RT2
L2R2
L2RT2
C1LS1
C5LS1
L1R1
L1RT1
L2R1
L2RT1
C1LS0
C5LS0
L1R0
L1RT0
L2R0
L2RT0
0x33
0x34
C12ot
C34ot
C2OT2
C4OT2
C2OT1
C4OT1
C2OT0
C4OT0
C1OT2
C3OT2
C1OT1
C3OT1
C1OT0
C3OT0
Doc ID 022570 Rev 2 19/66
Registers STA309B
Table 8.
Addr
Register summary (continued)
Name D7 D6 D5
0x35 C56ot
0x36 C78ot
I
2
S output channel mapping
C6OT2
C8OT2
C6OT1
C8OT1
D4
C6OT0
C8OT0
D3 D2
C5OT2
C7OT2
D1
C5OT1
C7OT1
D0
C5OT0
C7OT0
0x37
0x38
0x39
0x3A
C12om
C34om
C56om
C78om
C2OM2 C2OM1 C2OM0
C4OM2 C4OM1 C4OM0
C6OM2 C6OM1 C6OM0
C8OM2 C8OM1 C8OM0
C1OM2 C1OM1 C1OM0
C3OM2 C3OM1 C3OM0
C5OM2 C5OM1 C5OM0
C7OM2 C7OM1 C7OM0
0x44
0x45
0x46
0x47
0x48
0x49
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
User-defined coefficient RAM
Cfaddr1
Cfaddr2 CFA7
B1cf1 C1B23
B1cf2
B1cf3
B2cf1
B2cf2
B2cf3
A1cf1
C1B15
C1B7
C2B23
C2B15
C2B7
C3B23
CFA6
C1B22
C1B14
C1B6
C2B22
C2B14
C2B6
C3B22
CFA5
C1B21
C1B13
C1B5
C2B21
C2B13
C2B5
C3B21
CFA4
C1B20
C1B12
C1B4
C2B20
C2B12
C2B4
C3B20
CFA3
C1B19
C1B11
C1B3
C2B19
C2B11
C2B3
C3B19
CFA2
C1B18
C1B10
C1B2
C2B18
C2B10
C2B2
C3B18
CFA9
CFA1
C1B17
C1B9
C1B1
C2B17
C2B9
C2B1
C3B17
A1cf2
A1cf3
A2cf1
A2cf2
A2cf3
B0cf1
C3B15
C3B7
C4B23
C4B15
C4B7
C5B23
C5B15
C5B7
C3B14
C3B6
C4B22
C4B14
C4B6
C5B22
C5B14
C5B6
C3B13
C3B5
C4B21
C4B13
C4B5
C5B21
C5B13
C5B5
C3B12
C3B4
C4B20
C4B12
C4B4
C5B20
C5B12
C5B4
C3B11
C3B3
C4B19
C4B11
C4B3
C5B19
C5B11
C5B3
C3B10
C3B2
C4B18
C4B10
C4B2
C5B18
C5B10
C5B2
C3B9
C3B1
C4B17
C4B9
C4B1
C5B17
C3B8
C3B0
C4B16
C4B8
C4B0
C5B16
B0cf2
B0cf3
Cfud
C5B9
C5B1
WA
C5B8
C5B0
W1
MPCC1 MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8
MPCC2 MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0
DCC1 DCC15 DCC14 DCC13 DCC12 DCC11 DCC10 DCC9 DCC8
DCC2
PSC1
DCC7
RCV11
DCC6
RCV10
DCC5
RCV9
DCC4
RCV8
DCC3
RCV7
DCC2
RCV6
DCC1
RCV5
DCC0
RCV4
PSC2
PSC3
RCV3
CNV7
RCV2
CNV6
RCV1
CNV5
RCV0
CNV4
CNV11
CNV3
CNV10
CNV2
CNV9
CNV1
CNV8
CNV0
CFA8
CFA0
C1B16
C1B8
C1B0
C2B16
C2B8
C2B0
C3B16
20/66 Doc ID 022570 Rev 2
STA309B Registers
Table 8.
Addr
Register summary (continued)
Name D7 D6 D5
Digital Pop-Free
0x6B
0x6C
0x70
0x71
0x72
0x57
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
PFCXON CH8
Reserved -
Reserved -
Reserved -
Reserved -
Reserved -
Reserved -
RAMPTIM TR7
TSPUPT1 TP15
TSPUPT0 TP7
Reserved -
Reserved -
Reserved -
Reserved -
Reserved -
LSPDWT1 TL15
LSPDWT0 TL7
-
-
-
TL14
TL6
-
-
-
CH7
-
-
-
TR6
TP14
-
-
TP6
-
-
-
TL13
TL5
-
-
-
CH6
-
-
-
TR5
TP13
-
-
TP5
D4
-
-
-
TL12
TL4
-
-
-
CH5
-
-
-
TR4
TP12
-
-
TP4
D3
-
-
-
TL11
TL3
-
-
-
CH4
-
-
-
TR3
TP11
-
-
TP3
D2
-
-
-
TL10
TL2
-
-
-
CH3
-
-
-
TR2
TP10
-
-
TP2
-
-
-
TL9
TL1
-
-
-
TR1
TP9
-
-
-
CH2
-
-
TP1
D1
-
-
-
TL8
TL
-
-
-
TR0
TP8
-
-
-
CH1
-
-
TP0
D0
Doc ID 022570 Rev 2 21/66
Registers STA309B
22/66
0
1
2
D7
COS1
1
Bit RW
RW
RW
RW
D6
COS0
0
1
1
0
RST
D5
DSPB
0
IR1
0
MCS0
MCS1
MCS2
Name
D4
IR0
0
D3 D2
MCS2
0
D1
MCS1
1
Description
D0
MCS0
1
Master clock select: selects the ratio between the input I
2
S sampling frequency and the input clock
●
●
●
The STA309B supports sampling rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,
176.4 kHz, 192 kHz, and 2.8224 MHz DSD. Therefore the internal clocks are:
65.536 MHz for 32 kHz
90.3168 MHz for 44.1 kHz, 88.2 kHz, 176.4 kHz, and DSD
98.304 MHz for 48 kHz, 96 kHz, and 192 kHz
The external clock frequency provided to the XTI pin must be a multiple of the input sampling frequency (fs). The relationship between the input clock and the input sampling rate is determined by both the MCSn and the IRn (input rate) register bits. The MCSn bits determine the PLL factor generating the internal clock and the IRn bits determine the oversampling ratio used internally.
Input sampling rate fs (kHz)
32, 44.1, 48
88.2, 96
176.4, 192
DSD
Interpolation ratio select
00
01
10
11
IR
1XX
128 * fs
64 * fs
64 * fs
2 * fs
011
256 * fs
128 * fs
128 * fs
4 * fs
MCS[2:0]
010 001 000
384 * fs 512 * fs 768 * fs
192 * fs 256 * fs 384 * fs
192 * fs 256 * fs 384 * fs
6 * fs 8 * fs 10 * fs
Bit
3
4
RW
RW
RW
0
RST
IR0
0 IR1
Name Description
Interpolation ratio select: selects internal interpolation ratio based on input I
2
S sampling frequency
The STA309B has variable interpolation (oversampling) settings such that internal processing and FFX output rates remain consistent. The first processing block interpolates by either 4 times, 2 times, or 1 time (pass-through).
The oversampling ratio of this interpolation is determined by the IR bits.
Doc ID 022570 Rev 2
STA309B Registers
I
IR[1,0]
Input sampling rate
Fs (kHz)
1 st
stage interpolation ratio
01
10
10
11
00
00
00
01
32
44.1
48
88.2
96
176.4
192
DSD
4-times oversampling
4-times oversampling
4-times oversampling
2-times oversampling
2-times oversampling
Pass-through
Pass-through
DSD to 176.4 kHz conversion
Bit
0
RW
RW 0
RST
DSPB
Name Description
DSP bypass bit:
0: normal operation
1: bypass of biquad and bass/treble functions
Setting the DSPB bit bypasses the biquad function of the FFX core.
00
01
10
11
COS[1,0]
PLL output
PLL output / 4
PLL output / 8
PLL output / 16
CKOUT frequency
Doc ID 022570 Rev 2 23/66
Registers STA309B
Note:
D7 D6 D5 D4
SAIFB
0
SAI3
0
D3
SAI2
0
D2
SAI1
0
D1
SAI0
0
D0
Bit
0
1
2
3
RW
RW
RW
RW
RW
0
0
0
0
RST
SAI0
SAI1
SAI2
SAI3
Name Description
Serial audio input interface format: determines the interface format of the input serial digital audio interface.
Serial data interface
The STA309B audio serial input interfaces with standard digital audio components and accepts a number of serial data formats. The STA309B always acts a slave when receiving audio input from standard digital audio components. Serial data for eight channels is provided using 6 input pins: left/right clock LRCKI (pin 10), serial clock BICKI (pin 11), serial data 1 and 2 SDI12 (pin 9), serial data 3 and 4 SDI34 (pin 8), serial data 5 and 6 SDI56 (pin
7), and serial data 7 and 8 SDI78 (pin 6). The SAI/SAIFB register (configuration register B, address 0x01) is used to specify the serial data format. The default serial data format is I
2
S,
MSB-first. Available formats are shown in the tables that follow.
Bit RW RST Name
4 RW 0 SAIFB
Description
Determines MSB or LSB first for all SAO formats:
0: MSB first
1: LSB first
Serial input and output formats are specified separately
For example, SAI = 1110 and SAIFB = 1 specifies right-justified 16-bit data, LSB-first.
24/66 Doc ID 022570 Rev 2
STA309B Registers
The table below lists the serial audio input formats supported by the STA309B as related to
BICKI = 32 * fs, 48 * fs, 64 * fs , where sampling rate, fs = 32, 44.1, 48, 88.2, 96, 176.4,
192 kHz.
32 * fs
48 * fs
64 * fs
BICKI
X
X
X
X
X
X
X
X
0
1
X
X
X
X
X
X
X
X
X
X
1
X
X
0
X
X
X
X
SAI [3:0]
1001
1101
0010
0110
1010
1110
0100
1000
0000
1100
0001
0101
0101
1001
1101
0010
0110
1010
1110
0000
1100
1110
0100
0100
1000
0100
1100
0001
SAIFB Interface format
I
2
S 15-bit data
Left/right-justified 16-bit data
I
2
S 23-bit data
I
2
S 20-bit data
I
2
S 18-bit data
MSB-first I
2
S 16-bit data
LSB-first I
2
S 16-bit data
Left-justified 24-bit data
Left-justified 20-bit data
Left-justified 18-bit data
Left-justified 16-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
I
2
S 24-bit data
I
2
S 20-bit data
I
2
S 18-bit data
MSB-first I
2
S 16-bit data
LSB-first I
2
S 16-bit data
Left-justified 24-bit data
Left-justified 20-bit data
Left-justified 18-bit data
Left-justified 16-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
Doc ID 022570 Rev 2 25/66
Registers STA309B
D7 D6 D5 D4
SAOFB
0
D3
SAO3
0
D2
SAO2
0
D1
SAIO
0
D0
SAO0
0
Bit
0
1
2
3
RW
RW
RW
RW
RW
0
0
0
0
RST
SAO0
SAO1
SAO2
SAO3
Name Description
Serial audio output interface format: determines the interface format of the output serial digital audio interface.
The STA309B features a serial audio output interface that consists of 8 channels. The serial audio output always acts as a slave to the serial audio input interface and, therefore, all output clocks are synchronous with the input clocks. The output sampling frequency (fs) is also equivalent to the input sampling frequency. In the case of SACD/DSD and PDM input, the serial audio output acts as a master with an output sampling frequency of 176.4 kHz.
The output serial format can be selected independently from the input format and is done via the SAO and SAOFB bits.
Bit RW RST Name
4 RW 0 SAOFB
Description
Determines MSB or LSB first for all SAO formats:
0: MSB first
1: LSB first
BICKI = BICKO
32 * fs
48 * fs
64 * fs
SAO[3:0]
1100
1101
0000
0001
0010
0011
0100
0101
0111
1111
1110
0001
1010
1011
Interface data format
I
2
S data
Left/right-justified 16-bit data
I
2
S data
Left-justified data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
I
2
S data
Left-justified data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
26/66 Doc ID 022570 Rev 2
STA309B Registers
MPC
1
D7
Bit
0
1
RW
RW
RW
D6
CSZ4
1
CSZ3
0
D5
0
1
RST
OM0
OM1
Name
D4
CSZ2
0
CSZ1
0
D3
0
D2
CSZ0 OM1
1
Description
D1
OM0
0
D0
FFX power output mode: selects configuration of
FFX output
The FFX power output mode selects how the FFX output timing is configured. Different power devices use different output modes. The STA50x recommended use is
OM = 10.
OM[1,0]
00
01
10
11
Output stage - mode
STA50x/STA51xB - drop compensation
Discrete output stage - tapered compensation
STA50x/STA51xB - full power mode
Variable drop compensation (CSZn bits)
Bit
2
3
4
5
6
RW
RW
RW
RW
RW
RW
00000
00001
…
11111
CSZ[4:0]
0
0
0
0
1
RST
CSZ0
CSZ1
CSZ2
CSZ3
CSZ4
Name Description
Contra size register: when OM[1,0] = 11, this register determines the size of the FFX compensating pulse from 0 clock ticks to 31 clock periods.
Compensating pulse size
0 clock period compensating pulse size
1 clock period compensating pulse size
…
31 clock period compensating pulse size
Bit
7
RW
RW 1
RST
MPC
Name Description
Max power correction: setting to 1 enables STA50x correction for THD reduction near maximum power output
Setting the MPC bit turns on special processing that corrects the STA50x power device at high power. This mode should lower the THD+N of a full STA50x FFX system at maximum power output and slightly below. This mode will only be operational at OM[1,0] = 01.
Doc ID 022570 Rev 2 27/66
Registers STA309B
D7
C8BO
0
Bit
5
6
3
4
7
0
1
2
RW
RW
RW
RW
RW
RW
RW
RW
RW
D6
C7BO
0
C6BO
0
D5
0
0
0
0
0
0
0
0
RST
C1BO
C2BO
C3BO
C4BO
C5BO
C6BO
C7BO
C8BO
Name
D4
C5BO
0
C4BO
0
D3
0
D2
C3BO
D1
C2BO
0
Description
C1BO
0
D0
Channels 1, 2, 3, 4, 5, 6, 7, and 8 binary output mode enable bits. A setting of 0 indicates ordinary
FFX tristate output. A setting of 1 indicates binary output mode
Each individual channel output can be set to output a binary PWM stream. In this mode output A of a channel will be considered the positive output and output B is the negative inverse.
7.2.6 Configuration register F (0x05)
D7
PWMS2
0
Bit RW
D6
PWMS1
0
RST
D5
PWMS0
0
Name
BQL
0
D4
0 RW 0 HPB
PSL
0
D3
0
D2
DEMP DRC
0
D1
HPB
0
D0
Description
High-pass filter bypass bit: setting to one bypasses the internal AC coupling digital high-pass filter
The STA309B features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter is to prevent DC signals from passing through an FFX amplifier. DC signals can cause speaker damage.
If HPB = 1, then the filter that the high-pass filter utilizes is made available as userprogrammable biquad #1.
Bit
1
RW
RW 0
RST
DRC
Name Description
Dynamic range compression/anti-clipping
0: limiters act in anti-clipping mode
1: limiters act in dynamic range compression mode
Both limiters can be used in one of two ways, anti-clipping or dynamic range compression.
When used in anti-clipping mode the limiter threshold values are constant and dependent on the limiter settings.
28/66 Doc ID 022570 Rev 2
STA309B Registers
In dynamic range compression mode the limiter threshold values vary with the volume settings allowing a nighttime listening mode that provides a reduction in the dynamic range regardless of the volume level.
Bit RW RST Name Description
2 RW 0 DEMP
De-emphasis:
0: no de-emphasis
1: de-emphasis
By setting this bit to one, de-emphasis will be implemented on all channels. When this is used, it takes the place of biquad #7 in each channel and any coefficients using biquad #1 will be ignored. The DSPB (DSP bypass) bit must be set to 0 for de-emphasis to function.
Bit
3
RW
RW 0
RST
PSL
Name Description
Post-scale link:
0: each channel uses individual post-scale value
1: each channel uses channel 1 post-scale value
Post-Scale functionality can be used for power-supply error correction. For multichannel applications running off the same power supply, the post-scale values can be linked to the value of channel 1 for ease of use and in order to update the values faster.
Bit
4
RW
RW 0
RST
BQL
Name Description
Biquad link:
0: each channel uses coefficient values
1: each channel uses channel 1 coefficient values
For ease of use, all channels can use the biquad coefficients loaded into the channel 1 coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to be performed once.
Bit
7:5
RW
RW
000
001
010
011
100
PWMS[1:0]
RST
00
Name
PWMS[2:0]
Description
PWM speed selection:
PWM output speed
Normal speed (384 kHz) (all channels)
Half-speed (192 kHz) (all channels)
Double-speed (768 kHz) (all channels)
Normal speed (channels 1-6), double-speed (channels 7-8)
Odd speed (341.3 kHz) (all channels)
Doc ID 022570 Rev 2 29/66
Registers STA309B
D7
MPCV
0
Bit
D6
DCCV
0
HPE
0
D5 D4
AM2E
0
AME
0
D3
COD
0
D2
SID
0
D1 D0
PWMD
0
0
1
2
RW
RW
RW
RW
0
0
0
RST Name
PWMD
SID
COD
Description
PWM output disable:
0: PWM output normal
1: no PWM output
Serial interface (I
2
S out) disable:
0: I
2
S output normal
1: no I
2
S output
Clock output disable:
0: clock output normal
1: no clock output
Bit
3
RW
RW 0
RST
AME
Name Description
AM mode enable:
0: normal FFX operation.
1: AM reduction mode FFX operation
The STA309B features an FFX processing mode that minimizes the amount of noise generated in the frequency range of AM radio. This mode is intended for use when FFX is operating in a device with an active AM tuner. The SNR of the FFX processing is reduced to
~83 dB in this mode, which is still greater than the SNR of AM radio.
Bit
4
RW
RW 0
RST
AM2E
Name Description
AM2 mode enable:
0: normal FFX operation
1: AM2 reduction mode FFX operation
The STA309B features 2 FFX processing modes that minimize the amount of noise generated in the frequency range of AM radio. This second mode is intended for use when
FFX is operating in a device with an active AM tuner. This mode eliminates the noiseshaper.
Bit
5
RW
RW 0
RST
HPE
Name Description
FFX headphone enable:
0: channels 7 and 8 normal FFX operation
1: channels 7 and 8 headphone operation
Channels 7 and 8 can be configured to be processed and output in such a manner that headphones can be driven using an appropriate output device. This signal is a differential
3-wire drive called FFX headphone.
30/66 Doc ID 022570 Rev 2
STA309B
Bit RW RST
6 RW 0 DCCV
Name
Bit RW RST
7 RW 0 MPCV
Name
Description
Distortion compensation variable enable
:
0: uses preset DC coefficient
1: uses DCC coefficient
Description
Max power correction variable:
0: uses standard MPC coefficient
1: uses MPCC bits for MPC coefficient
Registers
D7
ECLE
0
Bit RW
D6
LDTE
1
RST
D5
BCLE
1
IDE
1
D4
ZDE
1
D3
SVE
1
D2
ZCE
1
D1 D0
NSBW
0
0 RW 0 NSBW
Name Description
Noise-shaper bandwidth selection:
1: 3 rd
order NS
0: 4 th
order NS
Bit
1
RW
RW 1
RST
ZCE
Name Description
Zero-crossing volume enable:
1: volume adjustments will only occur at digital zerocrossings
0: volume adjustments will occur immediately
The ZCE bit enables zero-crossing volume adjustments. When the volume is adjusted on digital zero-crossings, no clicks will be audible.
Bit
2
RW
RW 1
RST
SVE
Name Description
Soft volume enable:
1: volume adjustments use soft volume
0: volume adjustments occur immediately
Bit
3
RW
RW 1
RST
ZDE
Name Description
Zero-detect mute enable: setting to 1 enables the automatic zero-detect mute
Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at the input data of each processing channel after the channel-mapping block. If any channel receives 2048 consecutive zero-value samples (regardless of fs), then that individual channel is muted if this function is enabled.
Doc ID 022570 Rev 2 31/66
Registers STA309B
Bit RW RST Name Description
4 RW 1 IDE
Invalid input detect mute enable:
1: enables the automatic invalid input detect mute
Setting the IDE bit enables this function, which looks at the input I
2
S data and will automatically mute if the signals are perceived as invalid.
Bit
5
RW
RW 1
RST
BCLE
Name Description
Binary output mode clock loss detection enable
This function detects loss of input MCLK in binary mode and will output 50% duty cycle.
Bit
6
RW
RW 1
RST
LDTE
Name Description
LRCLK double triggering protection enable
This function actively prevents double triggering of LRCLK.
Bit
7
RW
RW 1
RST
ECLE
Name Description
Auto EAPD on clock loss
Device power-down signal (EAPD) on clock loss detection. This function is enabled by default. It is strongly recommended to avoid spurious noise during the on-off sequence. The
STA309B has the ECLE bit set to 0.
D7
EAPD
0
D6 D5 D4 D3 D2 D1 D0
PSCE
0
This feature utilizes an ADC on SDI78 that provides power supply ripple information for correction. Registers PSC1, PSC2, PSC3 are utilized in this mode.
Bit RW RST Name
0 RW 0 PSCE
Description
Power supply ripple correction enable:
0: normal operation
1: PSCorrect operation
Bit RW RST Name
7 RW 0 EAPD
Description
External amplifier power-down:
0: external power-stage power-down active
1: normal operation
32/66 Doc ID 022570 Rev 2
STA309B
7.2.10 Master mute register (0x09)
D7 D6 D5 D4
Registers
D3 D2 D1 D0
MMUTE
0
Note:
MV7
1
D7
MV6
1
D6
MV5
1
D5
MV4
1
D4
MV3
1
D3
MV2
1
D2
MV1
1
D1
MV0
1
D0
The value of the volume derived from MVOL is dependent on the AMV AutoMode volume settings.
7.2.12 Channel 1 volume (0x0B)
D7
C1V7
0
D6
C1V6
1
D5
C1V5
1
D4
C1V4
0
D3
C1V3
0
D2
C1V2
0
D1
C1V1
0
D0
C1V0
0
7.2.13 Channel 2 volume (0x0C)
D7
C2V7
0
D6
C2V6
1
D5
C2V5
1
D4
C2V4
0
D3
C2V3
0
D2
C2V2
0
D1
C2V1
0
D0
C2V0
0
7.2.14 Channel 3 volume (0x0D)
D7
C3V7
0
D6
C3V6
1
D5
C3V5
1
D4
C3V4
0
7.2.15 Channel 4 volume (0x0E)
D7
C4V7
0
D6
C4V6
1
D5
C4V5
1
D4
C4V4
0
D3
C3V3
0
D3
C4V3
0
D2
C3V2
0
D2
C4V2
0
D1
C3V1
0
D1
C4V1
0
D0
C3V0
0
D0
C4V0
0
Doc ID 022570 Rev 2 33/66
Registers STA309B
7.2.16 Channel 5 volume (0x0F)
D7
C5V7
0
D6
C5V6
1
D5
C5V5
1
D4
C5V4
0
7.2.17 Channel 6 volume (0x10)
D7
C6V7
0
D6
C6V6
1
D5
C6V5
1
D4
C6V4
0
D3
C5V3
0
D3
C6V3
0
D2
C5V2
0
D2
C6V2
0
7.2.18 Channel 7 volume (0x11)
D7
C7V7
0
D6
C7V6
1
D5
C7V5
1
D4
C7V4
0
D3
C7V3
0
D2
C7V2
0
7.2.19 Channel 8 volume (0x12)
D7
C8V7
0
D6
C8V6
1
D5
C8V5
1
D4
C8V4
0
D3
C8V3
0
D2
C8V2
0
7.2.20 Channel 1 volume trim, mute, bypass (0x13)
C1M
0
D7 D6
C1VBP
0 0
D5 D4
C1VT4
1
D3
C1VT3
0
D2
C1VT2
0
7.2.21 Channel 2 volume trim, mute, bypass (0x14)
C2M
0
D7 D6
C2VBP
0 0
D5 D4
C2VT4
1
D3
C2VT3
0
D2
C2VT2
0
7.2.22 Channel 3 volume trim, mute, bypass (0x15)
C3M
0
D7 D6
C3VBP
0 0
D5 D4
C3VT4
1
D3
C3VT3
0
D2
C3VT2
0
D1
C5V1
0
D0
C5V0
0
D1
C6V1
0
D0
C6V0
0
D1
C7V1
0
D0
C7V0
0
D1
C8V1
0
D0
C8V0
0
D1
C1VT1
0
D0
C1VT0
0
D1
C2VT1
0
D0
C2VT0
0
D1
C3VT1
0
D0
C3VT0
0
34/66 Doc ID 022570 Rev 2
STA309B Registers
7.2.23 Channel 4 volume trim, mute, bypass (0x16)
C4M
0
D7 D6
C4VBP
0 0
D5 D4
C4VT4
1
D3
C4VT3
0
D2
C4VT2
0
7.2.24 Channel 5 volume trim, mute, bypass (0x17)
C5M
0
D7 D6
C5VBP
0 0
D5 D4
C5VT4
1
D3
C5VT3
0
D2
C5VT2
0
D1
C4VT1
0
D1
C5VT1
0
D0
C4VT0
0
D0
C5VT0
0
7.2.25 Channel 6 volume trim, mute, bypass (0x18)
C6M
0
D7 D6
C6VBP
0 0
D5 D4
C6VT4
1
D3
C6VT3
0
D2
C6VT2
0
7.2.26 Channel 7 volume trim, mute, bypass (0x19)
C7M
0
D7 D6
C7VBP
0 0
D5 D4
C7VT4
1
D3
C7VT3
0
D2
C7VT2
0
D1
C6VT1
0
D0
C6VT0
0
D1
C7VT1
0
D0
C7VT0
0
7.2.27 Channel 8 volume trim, mute, bypass (0x1A)
C8M
0
D7 D6
C8VBP
0
D5 D4
C8VT4
1
D3
C8VT3
0
D2
C8VT2
0
D1
C8VT1
0
D0
C8VT0
0 0
The volume structure of the STA309B consists of individual volume registers for each channel and a master volume register that provides an offset to each channel’s volume setting. There is also an additional offset for each channel called the channel volume trim.
The individual channel volumes are adjustable in 0.5 dB steps from +48 dB to -78 dB. As an example if C5V = 0xXX or +XXX dB and MV = 0xXX or -XX dB, then the total gain for channel 5 = XX dB. The channel volume trim is adjustable independently on each channel from -10 dB to +10 dB in 1 dB steps. The master mute when set to 1 will mute all channels at once, whereas the individual channel mutes (CnM) will mute only that channel. Both the master mute and the channel mutes provide a "soft mute" with the volume ramping down to mute in 8192 samples from the maximum volume setting at the internal processing rate
(~192 kHz). A "hard mute" can be obtained by commanding a value of 0xFF (255) to any channel volume register or the master volume register. When volume offsets are provided via the master volume register, any channel whose total volume is less than -91 dB will be muted. All changes in volume take place at zero-crossings when ZCE = 1 (configuration register H) on a per-channel basis as this creates the smoothest possible volume
Doc ID 022570 Rev 2 35/66
Registers STA309B
0x00
0x01
0x02
…
0x5F
0x60
0x61
…
0xFE
0xFF
0x00
0x01
0x02
…
0x4C
…
0xFE
0xFF transitions. When ZCE = 0, volume updates occur immediately. Each channel also contains an individual channel volume bypass. If a particular channel has volume bypassed via the
CnVBP = 1 register, then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel. Each channel also contains a channel mute. If CnM = 1, a soft mute is performed on that channel.
MV[7:0] Volume offset from channel value
0 dB
-0.5 dB
-1 dB
…
-38 dB
…
-127 dB
Hardware channel mute
CnV[7:0] Volume
+48 dB
+47.5 dB
+47 dB
…
+0.5 dB
0 dB
-0.5 dB
…
-79.5 dB
Hardware channel mute
CnVT[4:0] Volume
0x00 to 0x06
0x07
…
0x0F
0x10
0x11
…
0x19
0x1A to 0x1F
+10 dB
+9 dB
…
+1 dB
0 dB
-1 dB
…
-9 dB
-10 dB
36/66 Doc ID 022570 Rev 2
STA309B Registers
7.2.28 Channel input mapping channels 1 and 2 (0x1B)
D7 D6
C2IM2
0
D5
C2IM1
0
D4
C2IM0
1
D3 D2
C1IM2
0
7.2.29 Channel input mapping channels 3 and 4 (0x1C)
D7 D6
C4IM2
0
D5
C4IM1
1
D4
C4IM0
1
D3 D2
C3IM2
0
D1
C1IM1
0
D1
C3IM1
1
D0
C1IM0
0
D0
C3IM0
0
7.2.30 Channel input mapping channels 5 and 6 (0x1D)
D7 D6
C6IM2
1
D5
C6IM1
0
D4
C6IM0
1
D3 D2
C5IM2
1
D1
C5IM1
0
D0
C5IM0
0
7.2.31 Channel input mapping channels 7 and 8 (0x1E)
000
001
010
011
100
101
110
111
D7 D6 D5 D4 D3 D2 D1 D0
C8IM2
1
C8M1
1
C8IM0
1
C7IM2
1
C7IM1
1
C7IM0
0
Each channel received via I
2
S can be mapped to any internal processing channel via the channel input mapping registers. This allows for flexibility in processing, simplifies output stage designs, and enables the ability to perform crossovers. The default settings of these registers map each I
2
S input channel to its corresponding processing channel.
CnIM[2:0] Serial input from
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
Doc ID 022570 Rev 2 37/66
Registers STA309B
7.2.32 AUTO1 - AutoModes EQ, volume, GC (0x1F)
D7
AMDM
0
Bit RW
D6
AMGC2
0
RST
D5
AMGC1
0
Name
D4
AMGC0
0
1:0 RW 0 AMEQ[1:0]
0
D3
AMV1
D2
AMV0
0
AMEQ1
0
D1
Description
Biquad 2-6 mode is:
00: user-programmable
01: preset EQ - PEQ bits
10: graphic EQ - xGEQ bits
11: auto volume controlled loudness curve
D0
AMEQ0
0
By setting AMEQ to any setting other than 00 enables AutoMode EQ, biquads 1-5 are not user programmable. Any coefficient settings for these biquads will be ignored. Also when
AutoMode EQ is used, the pre-scale value for channels 1-6 becomes hard-set to -18 dB.
Bit
3:2
6:4
RW
RW
RW
0
0
RST Name
AMV[1:0]
AMGC[2:0]
Description
AutoMode volume mode (MVOL) is:
00: MVOL 0.5 dB 256 steps (standard)
01: MVOL auto curve 30 steps
10: MVOL auto curve 40 steps
11: MVOL auto curve 50 steps
AutoMode gain compression/limiters mode is:
000: user programmable GC
001: AC no clipping
010: AC limited clipping (10%)
011: DRC nighttime listening mode
100: DRC TV commercial/channel AGC
101: AC 5.1 no clipping
110: AC 5.1 limited clipping (10%)
Bit
7
RW
RW 0
RST
AMDM
Name Description
AutoMode 5.1 downmix:
0: normal operation
1: channels 7-8 are 2-channel downmix of channels
1-6
The AutoMode downmix setting uses channels 7-8 of Mix#1 engine and therefore these channels of this function are fixed and not allowed to be set by the user when in this mode.
Channels 1-6 must be arranged via channel mapping (registers CnIM), if necessary, in the following manner for this operation:
Channel 1: left
Channel 2: right
Channel 3: left surround
Channel 4: right surround
Channel 5: center
Channel 6: LFE
38/66 Doc ID 022570 Rev 2
STA309B Registers
7.2.33 AUTO2 - AutoModes bass management2 (0x20)
SUB
1
D7
Bit RW
D6
RSS1
0
RST
D5
RSS0
0
Name
D4
CSS1
0
0 RW 0 AMBMME
0
D3
CSS0 FSS
0
D2 D1 D0
AMBMXE AMBMME
0 0
Description
0: AutoMode bass management mix disabled
1: AutoMode bass management mix enabled
Bit
1
RW
RW 0
RST Name
AMBMXE
Description
0: AutoMode bass management crossover disabled
1: AutoMode bass management crossover enabled
Setting the AMBMME bit enables the proper mixing to take place for various preset bass management configurations. Setting the AMBMXE bit enables the proper crossover filtering in biquad #7 to take place. The crossover for bass management is always 2 nd
order
(24 dB/oct) and the crossover frequency is determined by register bits PREEQ.XO[2:0].
All configurations of Dolby Bass Management can be performed in the IC. These different configurations are selected as they would be by the end-user.
The AutoMode bass management settings utilize channels 1-6 in the Mix #1 engine,
Channels 1-6 biquad #6, and channels 1-2 in the mix #2 engine in configuration #2. These functions cannot be user-programmed while the bass management automode is active.
Not all settings are valid as some configurations are unlikely and do not have to be supported by Dolby specifications.
Automatic crossover settings are provided or custom crossovers can be implemented using the available programmable biquads.
Input channels must be mapped using the channel-mapping feature in the following manner for bass management to be performed properly.
1: left front
2: right front
3: left rear
4: right rear
5: center
6: LFE
Bitfield
CSS - center speaker size
RSS - rear speaker size
Off
Off
10
Large
Large
01
Small
Small
00
Doc ID 022570 Rev 2 39/66
Registers STA309B
Bitfield 1 0
FSS - front speaker size
SUB - subwoofer
Large
On
Small
Off
When AMBMXE = 1, biquad #7 on channels 1-6 are utilized for the bass-management crossover filter, this biquad is not user-programmable in this mode. The XO settings determine the crossover frequency used, the crossover is 2 nd
order for both high-pass and low-pass with a -3 dB cross point. Higher order filters can be obtained be programming coefficients in other biquads if desired.
It is recommended to use settings of 120-160 Hz when using small, single driver satellite speakers as the frequency response of these speakers normally is limited to this region.
7.2.34 AUTO3 - AutoMode AM/pre-scale/bass management scale (0x21)
D7
AMAM2
0
Bit RW
D6
AMAM1
0
RST
D5
AMAM0
0
Name
D4
AMAME
0
D3 D2
MSA
0
D1
0 RW 0 AMPS
Description
AutoMode pre-scale
0: -18 dB used for pre-scale when AMEQ = 00
1: user-defined pre-scale when AMEQ = 00
D0
AMPS
0
Bit RW RST Name
1 RW 0 MSA
Description
Bass management mix scale adjustment
0: -12 dB scaling on satellite channels in config #1
1: no scaling on satellite channels in config #1
Bit RW RST Name
4 RW 0 AMAME
Description
AutoMode AM enable
0: switching frequency determined by PWMS settings
1: switching frequency determined by AMAM settings
AMAM[2:0]
000
001
010
011
100
101
110
48 kHz/96 kHz input Fs
0.535 MHz - 0.720 MHz
0.721 MHz - 0.900 MHz
0.901 MHz - 1.100 MHz
1.101 MHz - 1.300 MHz
1.301 MHz - 1.480 MHz
1.481 MHz - 1.600 MHz
1.601 MHz - 1.700 MHz
44.1 / 88.2 kHz input Fs
0.535 MHz - 0.670 MHz
0.671 MHz - 0.800 MHz
0.801 MHz - 1.000 MHz
1.001 MHz - 1.180 MHz
1.181 MHz - 1.340 MHz
1.341 MHz - 1.500 MHz
1.501 MHz - 1.700 MHz
40/66 Doc ID 022570 Rev 2
STA309B Registers
7.2.35 PREEQ - preset EQ settings (0x22)
XO2
1
D7
XO1
0
D6
XO0
1
D5 D4
PEQ4
0
D3
PEQ3
0
XO[2:0]
100
101
110
111
000
001
010
011
70 Hz
80 Hz
90 Hz
100 Hz
110 Hz
120 Hz
140 Hz
160 Hz
PEQ[4:0]
01001
01010
01011
01100
01101
01110
00000
00001
00010
00011
00100
00101
00110
00111
01000
01111
10000
10001
10010
10011
Flat
Rock
Soft Rock
Jazz
Classical
Dance
Pop
Soft
Hard
Party
Vocal
Hip-Hop
Dialog
Bass-boost #1
Bass-boost #2
Bass-boost #3
Loudness 1
Loudness 2
Loudness 3
Loudness 4
D2
PEQ2
0
D1
PEQ1
0
Bass management crossover frequency
Mode / setting
D0
PEQ0
0
Doc ID 022570 Rev 2 41/66
Registers
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
STA309B
Loudness 5
Loudness 6
Loudness 7
Loudness 8
Loudness 9
Loudness 10
Loudness 11
Loudness 12
Loudness 13
Loudness 14
Loudness 15
Loudness 16
D7 D6 D5 D4
AGEQ4
0
D3
AGEQ3
1
D2
AGEQ2
1
D1
AGEQ1
1
D0
AGEQ0
1
D7 D6 D5 D4
BGEQ4
0
D3
BGEQ3
1
D2
BGEQ2
1
D1
BGEQ1
1
D0
BGEQ0
1
D7 D6 D5 D4
CGEQ4
0
D3
CGEQ3
1
D2
CGEQ2
1
D1
CGEQ1
1
D0
CGEQ0
1
D7 D6 D5 D4
DGEQ4
0
D3
DGEQ3
1
D2
DGEQ2
1
D1
DGEQ1
1
D0
DGEQ0
1
42/66 Doc ID 022570 Rev 2
STA309B Registers
11111
11110
11101
…
10000
01111
01110
…
00001
00000
D7 D6 xGEQ[4:0]
D5 D4
EGEQ4
0
D3
EGEQ3
1
D2
EGEQ2
1
D1
EGEQ1
1
Boost / cut
D0
EGEQ0
1
…
+1
0
-1
…
+16
+15
+14
-14
-15
D7
C8BLP
0
D6
C7BLP
0
D5
C6BLP
0
D4
C5BLP
0
D3
C4BLP
0
D2
C3BLP
0
D1
C2BLP
0
D0
C1BLP
0
Each internal processing channel can receive two possible inputs at the input to the biquad block. The input can come either from the output of that channel’s MIX#1 engine or from the output of the bass/treble (biquad #10) of the previous channel. In this scenario, channel 1 receives channel 8. This enables the use of more than 10 biquads on any given channel at the expense of losing the number of separate internal processing channels.
Bit RW RST Name
7:0 RW 0 CnBLP
Description
For n = 1 to 8:
0: input from channel n MIX#1 engine output - normal operation
1: input from channel (n - 1) biquad #10 output - loop operation
Doc ID 022570 Rev 2 43/66
Registers STA309B
D7 D6 D5 D4 D3 D2 D1 D0
C8MXLP C7MXLP C6MXLP C5MXLP C4MXLP C3MXLP C2MXLP C1MXLP
0 0 0 0 0 0 0 0
Each internal processing channel can receive two possible sets of inputs at the inputs to the
Mix#1 block. The inputs can come from the outputs of the interpolation block as normally occurs (CnMXLP = 0) or they can come from the outputs of the Mix#2 block. This enables the use of additional filtering after the second mix block at the expense of losing this processing capability on the channel.
Bit RW RST Name
7:0 RW 0 CnMXLP
Description
For n = 1 to 8:
0: inputs to channel n MIX#1 engine from interpolation outputs - normal operation
1: inputs to channel n MIX#1 engine from MIX#2 engine outputs - loop operation
D7 D6 D5 D4 D3 D2 D1 D0
C8EQBP C7EQBP C6EQBP C5EQBP C4EQCBP C3EQBP C2EQBP C1EQBP
0 0 0 0 0 0 0 0
EQ control can be bypassed on a per-channel basis. If EQ control is bypassed on a given channel, the prescale and all 10 filters (high-pass, biquads, de-emphasis, bass management crossover, bass, treble in any combination) are bypassed for that channel.
Bit RW RST Name
7:0 RW 0 CnEQBP
Description
For n = 1 to 8:
0: perform EQ on channel n - normal operation
1: bypass EQ on channel n
D7
C8TCB
0
D6
C7TCB
0
D5
C6TCB
0
D4
C5TCB
0
D3
C4TCB
0
D2
C3TCB
0
D1
C2TCB
0
D0
C1TCB
0
Tone control (bass/treble) can be bypassed on a per-channel basis. If tone control is bypassed on a given channel, the two filters that tone control utilizes are made available as user-programmable biquads #9 and #10.
44/66 Doc ID 022570 Rev 2
STA309B Registers
7.2.45 Tone control (0x2C)
0000
0001
…
0111
0110
0111
1000
1001
…
1101
1110
1111
D7
TTC3
0
D6
TTC2
1
D5
TTC1
1
D4
TTC0
1
D3
BTC3
0
D2
BTC2
1
D1
BTC1
1
This is the tone control boost / cut as a function of the BTC and TTC bits.
BTC[3:0] / TTC[3:0) Boost / cut
-12 dB
-12 dB
…
-4 dB
-2 dB
0 dB
+2 dB
+4 dB
…
+12 dB
+12 dB
+12dB
D0
BTC0
1
D7
C4LS1
0
D6
C4LS0
0
D5
C3LS1
0
D4
C3LS0
0
D3
C2LS1
0
D2
C2LS0
0
D1
C1LS1
0
D0
C1LS0
0
D7
C8LS1
0
D6
C8LS0
0
D5
C7LS1
0
D4
C7LS0
0
D3
C6LS1
0
7.2.48 Limiter 1 attack/release rate (0x2F)
D7
L1A3
0
D6
L1A2
1
D5
L1A1
1
D4
L1A0
0
D3
L1R3
1
D2
C6LS0
0
D1
C5LS1
0
D0
C5LS0
0
D2
L1R2
0
D1
L1R1
1
D0
L1R0
0
Doc ID 022570 Rev 2 45/66
Registers
7.2.49 Limiter 1 attack/release threshold (0x30)
D7
L1AT3
0
D6
L1AT2
1
D5
L1AT1
1
D4
L1AT0
0
D3
L1RT3
1
7.2.50 Limiter 2 attack/release rate (0x31)
D7
L2A3
0
D6
L2A2
1
D5
L2A1
1
D4
L2A0
0
D3
L2R3
1
7.2.51 Limiter 2 attack/release threshold (0x32)
D7
L2AT3
0
D6
L2AT2
1
D5
L2AT1
1
D4
L2AT0
0
D3
L2RT3
1
STA309B
D2
L1RT2
0
D1
L1RT1
0
D0
L1RT0
1
D2
L2R2
0
D1
L2R1
1
D0
L2R0
0
D2
L2RT2
0
D1
L2RT1
0
D0
L2RT0
1
46/66
The STA309B includes two independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode or to actively reduce the dynamic range for a better listening environment such as a nighttime listening mode which is often needed for DVDs. The two modes are selected via the DRC bit in configuration register B, bit 7 address 0x02. Each channel can be mapped to either limiter or not mapped, meaning that the channel will clip when 0 dBFS is exceeded. Each limiter will look at the present value of each channel that is mapped to it, select the maximum absolute value of all these channels, perform the limiting algorithm on that value, and then, if needed, adjust the gain of the mapped channels in unison.
The limiter attack thresholds are determined by the LnAT registers. It is recommended in anti-clipping mode to set this to 0 dBFS, which corresponds to the maximum unclipped output power of an FFX amplifier. Since gain can be added digitally within the STA309B it is possible to exceed 0 dBFS or any other LnAT setting. When this occurs, the limiter, when active, will automatically start reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. The gain reduction occurs on a peak-detect algorithm.
The release of the limiter, when the gain is again increased, is dependent on an RMS-detect algorithm. The output of the volume/limiter block is passed through a RMS filter. The output of this filter is compared to the release threshold, determined by the release threshold register. When the RMS filter output falls below the release threshold, the gain is again increased at a rate dependent upon the release rate register. The gain can never be increased past it's set value and therefore the release will only occur if the limiter has already reduced the gain. The release threshold value can be used to set what is effectively a minimum dynamic range which is helpful as overlimiting can reduce the dynamic range to virtually zero and cause program material to sound lifeless.
Doc ID 022570 Rev 2
STA309B Registers
In AC mode the attack and release thresholds are set relative to full-scale. In DRC mode the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting, plus the attack threshold.
Figure 7.
Basic limiter and volume flow diagram
Limiter RM S
G a in/Vol u me
I n p u t
G a in Atten ua tion Sa t u r a tion
O u t p u t
00
01
10
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
CnLS[1,0]
LnA[3:0]
Channel limiter mapping
Channel has limiting disabled
Channel is mapped to limiter #1
Channel is mapped to limiter #2
3.1584 (fast)
2.7072
2.2560
1.8048
1.3536
0.9024
0.4512
0.2256
0.1504
0.1123
0.0902
0.0752
0.0645
0.0564
0.0501
0.0451 (slow)
Attack rate (dB/ms)
Doc ID 022570 Rev 2 47/66
Registers
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
48/66
LnR[3:0]
LnAT[3:0]
+3
+4
+5
+6
+7
+8
+9
+10
-2
0
+2
-12
-10
-8
-6
-4
0.5116 (fast)
0.1370
0.0744
0.0499
0.0360
0.0299
0.0264
0.0208
0.0198
0.0172
0.0147
0.0137
0.0134
0.0117
0.0110
0.0104 (slow)
Release rate (dB/ms)
Anti-clipping (AC)
(dB relative to F
S
)
STA309B
Doc ID 022570 Rev 2
STA309B
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
0000
0001
0010
0011
0100
0101
0110
1101
1110
1111
LnRT[3:0]
LnAT[3:0]
Registers
Anti-clipping (AC)
(dB relative to F
S
)
-8 dB
-7 dB
-6 dB
-5 dB
-4 dB
-3 dB
-2 dB
-1 dB
-0 dB
∞
-29 dB
-20 dB
-16 dB
-14 dB
-12 dB
-10 dB
-17
-16
-15
-14
-13
-12
-31
-29
-27
-25
-23
-21
-19
-10
-7
-4
Dynamic range compression (DRC)
(dB relative to volume)
Doc ID 022570 Rev 2 49/66
Registers STA309B
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
LnRT[3:0]
7.2.53 Channel 1 and 2 output timing (0x33)
D7 D6
C2OT2
1
D5
C2OT1
0
D4
C2OT0
0
D3
7.2.54 Channel 3 and 4 output timing (0x34)
D7 D3 D6
C4OT2
1
D5
C4OT1
1
D4
C4OT0
0
7.2.55 Channel 5 and 6 output timing (0x35)
D7 D3 D6
C6OT2
1
D5
C6OT1
0
D4
C6OT0
1
-26 dB
-24 dB
-22 dB
-20 dB
-18 dB
-15 dB
-12 dB
-9 dB
-6 dB
∞
-38 dB
Dynamic range compression (DRC)
(db relative to volume + LnAT)
-36 dB
-33 dB
-31 dB
-30 dB
-28 dB
D2
C1OT2
0
D2
C3OT2
0
D2
C5OT2
0
D1
C1OT1
0
D1
C3OT1
1
D1
C5OT1
0
D0
C1OT0
0
D0
C3OT0
0
D0
C5OT0
1
50/66 Doc ID 022570 Rev 2
STA309B Registers
7.2.56 Channel 7 and 8 output timing (0x36)
000
001
010
011
100
101
110
111
D7 D6
C8OT2
1
D5
C8OT1
1
D4
C8OT0
1
D3 D2
C7OT2
0
D1
C7OT1
1
D0
C7OT0
1
The centering of the individual channel PWM output periods can be adjusted by the output timing registers. The PWM slot settings can be chosen to ensure that pulse transitions do not occur at the same time on different channels using the same power device. There are 8 possible settings, the appropriate setting is based on the application and connections to the
FFX power devices.
CnOT[2:0] PWM slot
4
5
6
7
8
1
2
3
D7 D6
C2OM2
0
D5
C2OM1
0
D4
C2OM0
1
D3 D2
C1OM2
0
D1
C1OM1
0
D0
C1OM0
0
D7 D6
C4OM2
0
D5
C4OM1
1
D4
C4OM0
1
D3 D2
C3OM2
0
D1
C3OM1
1
D0
C3OM0
0
D7 D6
C6OM2
1
D5
C6OM1
0
D4
C6OM0
1
D3 D2
C5OM2
1
D1
C5OM1
0
D0
C5OM0
0
Doc ID 022570 Rev 2 51/66
Registers STA309B
000
001
010
011
100
101
110
111
D7 D6 D5 D4 D3 D2 D1 D0
C8OM2
1
C8M1
1
C8OM0
1
C7OM2
1
C7OM1
1
C7OM0
0
Each I
2
S output channel can receive data from any channel output of the volume block.
Which channel a particular I
2
S output receives is dependent upon that channel’s CnOM register bits.
CnOM[2:0] Serial output from
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
D7 D6 D5 D4 D3 D2 D1
CFA9
0
D0
CFA8
0
D7
CFA7
0
D6
CFA6
0
D5
CFA5
0
D4
CFA4
0
D3
CFA3
0
D2
CFA2
0
7.2.63 Coefficient register, bits 23:16 (0x3D)
D7
C1B23
0
D6
C1B22
0
D5
C1B21
0
D4
C1B20
0
D3
C1B19
0
D2
C1B18
0
D1
CFA1
0
D0
CFA0
0
D1
C1B17
0
D0
C1B16
0
52/66 Doc ID 022570 Rev 2
STA309B Registers
7.2.64 Coefficient register, bits 15:8 (0x3E)
D7
C1B15
0
D6
C1B14
0
D5
C1B13
0
D4
C1B12
0
D3
C1B11
0
D2
C1B10
0
7.2.65 Coefficient register, bits 7:0 (0x3F)
D7
C1B7
0
D6
C1B6
0
D5
C1B5
0
D4
C1B4
0
D3
C1B3
0
D2
C1B2
0
7.2.66 Coefficient register, bits 23:16 (0x40)
D7
C2B23
0
D6
C2B22
0
D5
C2B21
0
D4
C2B20
0
D3
C2B19
0
D2
C2B18
0
7.2.67 Coefficient register, bits 15:8 (0x41)
D7
C2B15
0
D6
C2B14
0
D5
C2B13
0
D4
C2B12
0
D3
C2B11
0
D2
C2B10
0
7.2.68 Coefficient register, bits 7:0 (0x42)
D7
C2B7
0
D6
C2B6
0
D5
C2B5
0
D4
C2B4
0
D3
C2B3
0
D2
C2B2
0
7.2.69 Coefficient register, bits 23:16 (0x43)
D7
C1B23
0
D6
C1B22
0
D5
C1B21
0
D4
C1B20
0
D3
C1B19
0
D2
C1B18
0
7.2.70 Coefficient register, bits 15:8 (0x44)
D7
C3B15
0
D6
C3B14
0
D5
C3B13
0
D4
C3B12
0
D3
C3B11
0
D2
C3B10
0
D1
C1B9
0
D0
C1B8
0
D1
C1B1
0
D0
C1B0
0
D1
C2B17
0
D0
C2B16
0
D1
C2B9
0
D0
C2B8
0
D1
C2B1
0
D0
C2B0
0
D1
C1B17
0
D0
C1B16
0
D1
C3B9
0
D0
C3B8
0
Doc ID 022570 Rev 2 53/66
Registers STA309B
7.2.71 Coefficient register, bits 7:0 (0x45)
D7
C3B7
0
D6
C3B6
0
D5
C3B5
0
D4
C3B4
0
D3
C3B3
0
D2
C3B2
0
7.2.72 Coefficient register, bits 23:16 (0x46)
D7
C4B23
0
D6
C4B22
0
D5
C4B21
0
D4
C4B20
0
D3
C4B19
0
D2
C4B18
0
7.2.73 Coefficient register, bits 15:8 (0x47)
D7
C4B15
0
D6
C4B14
0
D5
C4B13
0
D4
C4B12
0
D3
C4B11
0
D2
C4B10
0
7.2.74 Coefficient register, bits 7:0 (0x48)
D7
C4B7
0
D6
C4B6
0
D5
C4B5
0
D4
C4B4
0
D3
C4B3
0
D2
C4B2
0
7.2.75 Coefficient register, bits 23:16 (0x49)
D7
C5B23
0
D6
C5B22
0
D5
C5B21
0
D4
C5B20
0
D3
C5B19
0
D2
C5B18
0
7.2.76 Coefficient register, bits 15:8 (0x4A)
D7
C5B15
0
D6
C5B14
0
D5
C5B13
0
D4
C5B12
0
D3
C5B11
0
D2
C5B10
0
7.2.77 Coefficient register, bits 7:0 (0x4B)
D7
C5B7
0
D6
C5B6
0
D5
C5B5
0
D4
C5B4
0
D3
C5B3
0
D2
C5B2
0
D1
C3B1
0
D0
C3B0
0
D1
C4B17
0
D0
C4B16
0
D1
C4B9
0
D1
C4B1
0
D0
C4B8
0
D0
C4B0
0
D1
C5B17
0
D0
C5B16
0
D1
C5B9
0
D0
C5B8
0
D1
C5B1
0
D0
C5B0
0
54/66 Doc ID 022570 Rev 2
STA309B Registers
7.3
7.4
D7 D6 D5 D4 D3 D2 D1 D0
WA
0
W1
0
Coefficients for EQ and bass management are handled internally in the STA309B via RAM.
Access to this RAM is available to the user via an I
2
C register interface.
A collection of I
2
C registers are dedicated to this function. One contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write of the coefficient(s) to RAM. The following are instructions for reading and writing coefficients.
Reading a coefficient from RAM
1.
write top 2 bits of address to I
2
C register 0x3B
2. write bottom 8 bits of address to I
2
C register 0x3C
3. read top 8 bits of coefficient in I
2
C address 0x3D
4. read middle 8 bits of coefficient in I
2
C address 0x3E
5. read bottom 8 bits of coefficient in I
2
C address 0x3F
Reading a set of coefficients from RAM
1.
write top 2 bits of address to I
2
C register 0x3B
2. write bottom 8 bits of address to I
2
C register 0x3C
3. read top 8 bits of coefficient in I
2
C address 0x3D
4. read middle 8 bits of coefficient in I
2
C address 0x3E
5. read bottom 8 bits of coefficient in I
2
C address 0x3F
6. read top 8 bits of coefficient b2 in I
2
C address 0x40
7. read middle 8 bits of coefficient b2 in I
2
C address 0x41
8. read bottom 8 bits of coefficient b2 in I
2
C address 0x42
9. read top 8 bits of coefficient a1 in I
2
C address 0x43
10. read middle 8 bits of coefficient a1 in I
2
C address 0x44
11. read bottom 8 bits of coefficient a1 in I
2
C address 0x45
12. read top 8 bits of coefficient a2 in I
2
C address 0x46
13. read middle 8 bits of coefficient a2 in I
2
C address 0x47
14. read bottom 8 bits of coefficient a2 in I
2
C address 0x48
15. read top 8 bits of coefficient b0 in I
2
C address 0x49
16. read middle 8 bits of coefficient b0 in I
2
C address 0x4A
17. read bottom 8 bits of coefficient b0 in I
2
C address 0x4B
Doc ID 022570 Rev 2 55/66
Registers
7.5 Writing a single coefficient to RAM
1.
write top 2 bits of address to I
2
C register 0x3B
2. write bottom 8 bits of address to I
2
C register 0x3C
3. write top 8 bits of coefficient in I
2
C address 0x3D
4. write middle 8 bits of coefficient in I
2
C address 0x3E
5. write bottom 8 bits of coefficient in I
2
C address 0x3F
6. write 1 to W1 bit in I
2
C address 0x4C
7.6
STA309B
Writing a set of coefficients to RAM
1.
write top 2 bits of starting address to I
2
C register 0x3B
2. write bottom 8 bits of starting address to I
2
C register 0x3C
3. write top 8 bits of coefficient b1 in I
2
C address 0x3D
4. write middle 8 bits of coefficient b1 in I
2
C address 0x3E
5. write bottom 8 bits of coefficient b1 in I
2
C address 0x3F
6. write top 8 bits of coefficient b2 in I
2
C address 0x40
7. write middle 8 bits of coefficient b2 in I
2
C address 0x41
8. write bottom 8 bits of coefficient b2 in I
2
C address 0x42
9. write top 8 bits of coefficient a1 in I
2
C address 0x43
10. write middle 8 bits of coefficient a1 in I
2
C address 0x44
11. write bottom 8 bits of coefficient a1 in I
2
C address 0x45
12. write top 8 bits of coefficient a2 in I
2
C address 0x46
13. write middle 8 bits of coefficient a2 in I
2
C address 0x47
14. write bottom 8 bits of coefficient a2 in I
2
C address 0x48
15. write top 8 bits of coefficient b0 in I
2
C address 0x49
16. write middle 8 bits of coefficient b0 in I
2
C address 0x4A
17. write bottom 8 bits of coefficient b0 in I
2
C address 0x4B
18. write 1 to WA bit in I
2
C address 0x4C
The mechanism for writing a set of coefficients to RAM provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side-effects.
When using this technique, the 10-bit address specifies the address of the biquad b1 coefficient (for example, decimals 0, 5, 10, 15, …, 100, … 395), and the STA309B generates the RAM addresses as offsets from this base value to write the complete set of coefficient data.
56/66 Doc ID 022570 Rev 2
STA309B
8 Equalization and mixing
Figure 8.
Channel mixer
Channel 1
CxMIX1
CxMIX2
Channel 2
CxMIX3
Channel 3
CxMIX4
Channel 4
CxMIX5
Channel 5
CxMIX6
Channel 6
CxMIX7
Channel 7
CxMIX8
Channel 8
Equalization and mixing
Channel x
8.1 Post-scale
The STA309B provides one additional multiplication after the last interpolation stage and before the distortion compensation on each channel. This is a 24-bit signed fractional multiplier.
The scale factor for this multiplier is loaded into RAM using the same I
2
C registers as the biquad coefficients and the bass-management.
This post-scale factor can be used in conjunction with an ADC-equipped microcontroller to perform power-supply error correction. All channels can use channel 1 by setting the postscale link bit.
2
3
0
1
4
5
Table 9.
Index
(decimal)
RAM block for biquads, mixing, and bass management
Index
(hex)
Coefficient
Channel 1 - Biquad 1 0x00
0x01
0x02
0x03
0x04
0x05 Channel 1 - Biquad 2
C1H10 (b1/2)
C1H11 (b2)
C1H12 (a1/2)
C1H13 (a2)
C1H14 (b0/2)
C1H20
Default
0x000000
0x000000
0x000000
0x000000
0x400000
0x000000
Doc ID 022570 Rev 2 57/66
Equalization and mixing STA309B
Table 9.
Index
(decimal)
RAM block for biquads, mixing, and bass management (continued)
Index
(hex)
Coefficient Default
425
…
463
464
465
…
415
416
417
…
423
424
471
472
473
…
527
…
399
400
401
402
…
407
408
409
…
…
49
50
51
…
99
100
…
Channel 2 - Biquad 10
Channel 3 - Biquad 1
…
Channel 8 - Biquad 10
Channel 1 - Pre-Scale
Channel 2 - Pre-Scale
Channel 3 - Pre-Scale
…
Channel 8 - Pre-Scale
Channel 1 - Post-Scale
Channel 2 - Post-Scale
…
Channel 8 - Post-Scale
Channel 1 - Mix#1 1
Channel 1 - Mix#1 2
…
Channel 1 - Mix#1 8
Channel 2 - Mix#1 1
Channel 2 - Mix#1 2
…
Channel 8 - Mix#1 8
Channel 1 - Mix#2 1
Channel 1 - Mix#2 2
…
Channel 1 - Mix#2 8
Channel 2 - Mix#2 1
Channel 2 - Mix#2 2
…
Channel 8 - Mix#2 8
0x1A9
…
0x1CF
0x1D0
0x1D1
…
0x19F
0x1A0
0x1A1
…
0x1A7
0x1A8
…
0x18F
0x190
0x191
0x192
…
0x197
0x198
0x199
…
…
0x31
0x32
0x33
…
0x63
0x64
0x1D7
0x1D8
0x1D9
…
0x20F
…
Channel 1 - Biquad 10
Channel 2 - Biquad 1
C8PstS
C1MX11
C1MX12
…
C1MX18
C2MX11
C2MX12
…
C8MX18
C1MX21
C1MX22
…
…
C8HA4
C1PreS
C2PreS
C3PreS
…
C8PreS
C1PstS
C2PstS
…
…
C1HA4
C2H10
C2H11
…
C2HA4
C3H10
C1MX28
C2MX21
C2MX22
…
C8MX28
0x7FFFFF
0x7FFFFF
0x000000
…
0x000000
0x000000
0x7FFFFF
…
0x7FFFFF
0x7FFFFF
0x000000
…
…
0x400000
0x000000
0x000000
…
0x4000000
0x000000
…
0x400000
0x7FFFFF
0x7FFFFF
0x7FFFFF
…
0x7FFFFF
0x7FFFFF
0x7FFFFF
…
0x000000
0x000000
0x7FFFFF
…
0x7FFFFF
58/66 Doc ID 022570 Rev 2
STA309B
8.2 Variable maximum power correction
Equalization and mixing
The MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1.
D7 D6 D5 D4 D3 D2 D1
MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9
0 0 1 0 1 1 0
D7
MPCC7
1 1
D6
MPCC6
D5
MPCC5
0
MPCC4
0
D4
0
D3
MPCC3
D2
MPCC2
0
MPCC1
0
D1
D0
MPCC8
1
D0
MPCC0
0
8.3
8.3.1
Variable distortion compensation
DCC1-2 (0x4F, 0x50)
The DCC bits determine the 16 MSBs of the distortion compensation coefficient. This coefficient is used in place of the default coefficient when DCCV = 1.
D7
DCC15
1
D7
DCC7
0
D6
DCC14
1
D6
DCC6
0
D5
DCC13
1
D5
DCC5
1
D4
DCC12
1
D4
DCC4
1
D3
DCC11
0
D3
DCC3
0
D2
DCC10
0
D2
DCC2
0
D1
DCC9
1
D1
DCC1
1
D0
DCC8
1
D0
DCC0
1
Doc ID 022570 Rev 2 59/66
Equalization and mixing STA309B
8.4.1
ADC is used to input ripple data to SDI78. The left channel (7) is used internally. No audio data can therefore be used on these channels, although all channel mapping and mixing from other inputs to channels 7 and 8 internally are still valid.
PSC1-2: ripple correction value (RCV) (0x51, 0x52)
This function is equivalent to the negative maximum ripple peak as a percentage of Vcc
(MPR), scaled by the inverse of the maximum ripple p-p as a percentage of full-scale analog input to ADC. It is represented as a 1.11 signed fractional number.
D7
RCV11
0
D7
RCV3
0
D6
RCV10
0
D6
RCV2
0
D5
RCV9
0
D5
RCV1
0
D4
RCV8
0
D4
RCV0
0
D3
RCV7
0
D3
CNV11
1
D2
RCV6
0
D2
CNV10
1
D1
RCV5
0
D1
CNV9
1
D0
RCV4
0
D0
CNV8
1
8.5
This function is equivalent to 1 / (1+MPR) expressed as a 0.12 unsigned fractional number.
D7
CNV7
1
D6
CNV6
1
D5
CNV5
1
D4
CNV4
1
D3
CNV3
1
D2
CNV2
1
D1
CNV1
1
D0
CNV0
1
Digital pop-free operation in single-ended mode
The STA309B pop-free feature allows digitally pre-loading the bypass capacitor between the filtered amplifier output and the load in single-ended applications. Normally, a bypass capacitor needs to be preloaded to half of the power supply in order to avoid having popnoise at PWM startup.
By enabling the STA309B pop-free feature, it is possible to preload the capacitor using the amplifier, without needing the resistive partition. By forcing a ramp, it is possible to gradually load the capacitor from zero to half the supply with the PWM signal starting from near 0% duty cycle to 50% duty cycle. This “active load” is also faster than the resistive partition method.
60/66 Doc ID 022570 Rev 2
STA309B Equalization and mixing
Figure 9.
Typical single-ended driver - power stage configuration
O U T x y INxy O U T x y
EAPD
PWRDN
TRI-STATE
The R pull-down resistor (typical value: 3.3 kOhm) is placed to ensure that there is zero voltage across the load and the bypass capacitor is discharged when the amplifier is in tristate mode.
CH8
1
D7
CH7
1
D6
CH6
1
D5
CH5
1
D4
CH4
1
D3
CH3
1
D2
CH2
1
D1
CH1
1
D0
PFCXON[I]: when ‘1’, digital pop free is active on channel i+1 when in binary mode (see
Section 7.2.5: Configuration register E (0x04) on page 28 )
when ‘0’, digital pop free is not active on channel i+1
Figure 10.
Pop-free timing diagram
T S PUPT
Doc ID 022570 Rev 2
L S PDWT
61/66
Equalization and mixing
8.5.3 RAMPTIM: ramp duration register (0x66)
STA309B
8.5.4
TR7
0
D7
TR6
0
D6
TR5
0
D5
TR4
0
D4
TR3
0
D3
TR2
1
D2
TR1
0
D1
TR0
0
D0
This function is the total pop-free ramp duration (same value for ramp-up and ramp-down and for all channels); default is 400 ms (range is 0-25 sec.).
TSPUPT: waiting time after EAPD (0x67 - 0x68)
D7
TP15
0
D6
TP14
0
D5
TP13
0
D4
TP12
1
D3
TP11
0
D2
TP10
0
TP9
0
D1
TP8
0
D0
TP7
0
D7
TP6
0
D6
TP5
0
D5
TP4
0
D4
TP3
0
D3
TP2
0
D2
TP1
0
D1
TP0
0
D0
This function is the waiting time after EAPD=1 to start ramp-up (same value for all channels); default is 680 ms (range is 0-11 sec.). In a typical application the EAPD line is connected to the TRI-STATE input pin of the STA5xx power stage through the RC filter (see
). TSPUPT shall be greater than the RC time constant.
D7
TL15
0
D6
TL14
0
D5
TLP13
1
D4
TL12
0
D3
TL11
0
D2
TL10
0
TL9
0
D1
TL8
0
D0
TL7
0
D7
TL6
0
D6
TL5
0
D5
TL4
0
D4
TL3
0
D3
TL2
0
D2
TL1
0
D1
TL0
0
D0
This function is the waiting time after end of ramp-down to assert EAPD=0 (same value for all channels); default is 1.4 sec. (range is 0-11 sec.). If a resistor is placed in parallel to the output filter capacitor (see
Figure 9 on page 61 ), the LSPDWT value is 0x00.
62/66 Doc ID 022570 Rev 2
STA309B Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
Table 10.
VFQFPN-56 (8 x 8 mm) package dimensions mm
Reference
Min. Typ.
0.80
0
0.90
A
A1
D
D2
E
E2 b b1 e (pad pitch)
(1)
L1 aaa bbb ddd eee fff ccc
1.
0.25
0.20
0.05
8.00
See exposed pad variations
8.00
See exposed pad variations
0.30
0.25
0.15
0.10
0.05
0.08
0.10
0.10
Max.
1.00
0.05
0.35
0.30
0.15
Table 11.
Exposed pad variations
D2
Variation
Min.
Typ.
A
B
5.85
4.25
5.90
4.30
Max
5.95
4.35
Min.
5.85
4.25
E2
Typ. Max.
5.90
4.30
5.95
4.35
Doc ID 022570 Rev 2 63/66
Package information
Figure 11.
VFQFPN-56 (8 x 8 mm) package outline
STA309B
64/66
The axis of each pad must lie simultaneously in both tolerance zones.
(4) - The terminal A1 corner must be identified on the top surface through inked or lasered mark dot.
A distinguishing feature is allowable on the bottom surface of the package, chamfer at die paddle corner to identify the terminal A1. Exact shape of each corner is optional.
(5) – All dimensions are in mm.
8 26 8 20
Doc ID 022570 Rev 2
STA309B
Table 12.
Document revision history
Date Revision
09-Dec-2011
24-Jan-2012
1
2
Changes
Initial release
Updated title and
Revision history
Doc ID 022570 Rev 2 65/66
STA309B
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66/66 Doc ID 022570 Rev 2
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