STMicroelectronics STA381BW Datasheet
விளம்பரம்
விளம்பரம்
STA381BW
Features
Wide-range supply voltage
– 4.5 V to 26 V (operating range)
– 30 V (absolute maximum rating)
I 2 C control with selectable device address
Embedded full IC protection
– Manufacturing short-circuit protection (out vs. gnd, out vs. vcc, out vs. out)
– Thermal protection
– Overcurrent protection
– Undervoltage protection
1 Vrms stereo analog input
I 2 S interface, sampling rate 32 kHz ~ 192 kHz, with internal sampling frequency converter for fixed processing frequency
Three output power stage configurations
– 2.0 mode, L/R full bridges
– 2.1 mode, L/R two half-bridges, subwoofer full bridge
– 2.1 mode, L/R full bridges, PWM output for external subwoofer amplifier
Driving load capabilities
– 2 x 20 W into 8 ternary modulation
– 2 x 9 W into 4 + 1 x 20 W into 8
FFX TM 100 dB dynamic range
Fixed output PWM frequency at any input sampling frequency
Embedded RMS meter for measuring real-time loudness
Two analog outputs
– Selectable headphone / line out driver with adjustable gain via external resistors
– New F3X TM analog output
Sound Terminal
®
2.1-channel high-efficiency digital audio system
Datasheet
-
production data
VQFN48 (7 x 7 mm)
New fully programmable noise-gating function
Headphone
– Embedded negative charge pump
– Full capless output configuration
– Driving load capabilities: 40 mW into 32
Line out
– 2 Vrms line output capability
Up to 12 user-programmable biquads with noise-shaping technology
Direct access to coefficients through I 2 C shadowing mechanism
Fixed (88.2 kHz / 96 kHz) internal processing sampling rate
Two independent DRCs configurable as a dual-band anticlipper or independent limiters/compressors (B 2 DRC)
Digital gain/att +48 dB to -80 dB with
0.125 dB/step resolution
Independent (fade-in, fade-out) soft volume update with programmable rate 48 ~ 1.5 dB/ms
Bass/treble tones control
Audio presets: 15 crossover filters,
5 anticlipping modes, nighttime listening mode
STSpeakerSafe TM protection circuitry
– Pre
-
and post
processing DC blocking filters
– Checksum engine for filter coefficients
– PWM fault self-diagnosis
STCompressor TM dual-band DRC
Table 1. Device summary
Order code Package Packing
STA381BW
STA381BWTR
VQFN48
VQFN48
Tray
Tape and Reel
May 2013
This is information on a product in full production.
DocID018835 Rev 8 1/174 www.st.com
174
Contents
Contents
STA381BW
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Electrical specifications for the digital section . . . . . . . . . . . . . . . . . . . . . 23
Electrical specifications for the power section . . . . . . . . . . . . . . . . . . . . . 24
Power-on/off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Electrical specifications for the analog section . . . . . . . . . . . . . . . . . . . . . 27
STC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Programming of coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2
C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2/174 DocID018835 Rev 8
STA381BW
Contents
Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Register description: New Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
STATUS register (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
RESET register (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Soft volume register (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
MVOL register (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
FINEVOL register (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
CH1VOL register (addr 0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
CH2VOL register (addr 0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
POST scaler register (addr 0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
OPER register (addr 0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
FUNCT register (addr 0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
HPCFG register (addr 0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Configuration register A (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Interpolation ratio selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Fault-detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Configuration register B (addr 0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DocID018835 Rev 8 3/174
Contents STA381BW
Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Configuration register C (addr 0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
FFX compensating pulse size register . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Configuration register D (addr 0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Configuration register E (addr 0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Configuration register F (addr 0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . 68
LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
External amplifier power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Volume control registers (addr 0x17 - 0x1B) . . . . . . . . . . . . . . . . . . . . . . 69
Mute/line output configuration register (addr 0x17) . . . . . . . . . . . . . . . . 69
Channel 3 / line output volume (addr 0x1B) . . . . . . . . . . . . . . . . . . . . . 71
Audio preset registers (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
AM interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Channel configuration registers (addr 0x1F - 0x21) . . . . . . . . . . . . . . . . . 73
Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4/174 DocID018835 Rev 8
STA381BW Contents
Tone control register (addr 0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Dynamic control registers (addr 0x23 - 0x26 / addr 0x43 - 0x46) . . . . . . 76
Limiter 1 attack/release rate (L1AR addr 0x23) . . . . . . . . . . . . . . . . . . . 76
Limiter 1 attack/release threshold (L1ATRT addr 0x24) . . . . . . . . . . . . 76
Limiter 2 attack/release rate ( L2AR addr 0x25) . . . . . . . . . . . . . . . . . . 76
Limiter 2 attack/release threshold ( L2 ATRT addr 0x26) . . . . . . . . . . . . 76
Limiter 1 extended attack threshold (addr 0x43) . . . . . . . . . . . . . . . . . . 80
Limiter 1 extended release threshold (addr 0x44) . . . . . . . . . . . . . . . . . 80
Limiter 2 extended attack threshold (addr 0x45) . . . . . . . . . . . . . . . . . . 81
Limiter 2 extended release threshold (addr 0x46) . . . . . . . . . . . . . . . . . 81
User-defined coefficient control registers (addr 0x27 - 0x37) . . . . . . . . . . 81
Coefficient address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Coefficient b1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Coefficient b1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Coefficient b1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Coefficient b2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Coefficient b2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Coefficient b2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Coefficient a1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Coefficient a1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Fault-detect recovery constant registers (addr 0x3C - 0x3D) . . . . . . . . . . 88
Extended configuration register (addr 0x47) . . . . . . . . . . . . . . . . . . . . . . 88
Extended post-scale range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
DocID018835 Rev 8 5/174
Contents
STA381BW
Extended biquad selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
(address 0x52; 0x53; 0x54; 0x55; 0x56; 0x57) . . . . . . . . . . . . . . . . . . . . 90
Short-circuit protection mode registers SHOK (address 0x58) . . . . . . . . 92
Extended coefficient range up to -4...4 (address 0x5A) . . . . . . . . . . . . . . 93
Miscellaneous registers (address 0x5C, 0x5D) . . . . . . . . . . . . . . . . . . . . 94
Rate power-down enable (RPDNEN) bit . . . . . . . . . . . . . . . . . . . . . . . . 94
Bridge immediately off (BRIDGOFF) bit (address 0x4B, bit D5) . . . . . . 94
Channel PWM enable (CPWMEN) bit . . . . . . . . . . . . . . . . . . . . . . . . . . 95
External amplifier hardware pin enabler (LPDP, LPD LPDE) bits . . . . . 95
Power-down delay selector (PNDLSL[2:0]) bits . . . . . . . . . . . . . . . . . . . 95
Short-circuit check enable bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Bad PWM detection registers (address 0x5E, 0x5F, 0x60) . . . . . . . . . . . 96
Enhanced zero-detect mute and input level measurement
(address 0x61-0x65, 0x3F, 0x40, 0x6F) . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Headphone/Line out configuration register (address 0x66) . . . . . . . . . . . 99
F3XCFG (address 0x69; 0x6A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
STCompressorTM configuration register (address 0x6B; 0x6C) . . . . . . 101
Charge pump synchronization (address 0x70) . . . . . . . . . . . . . . . . . . . . 101
Coefficient RAM CRC protection (address 0x71-0x7D) . . . . . . . . . . . . . 102
MISC4 (address 0x7E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Register description: Sound Terminal compatibility . . . . . . . . . . . . . 106
Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Fault-detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
FFX compensating pulse size register . . . . . . . . . . . . . . . . . . . . . . . . . 115
Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6/174 DocID018835 Rev 8
STA381BW Contents
Zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
AM mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Zero-crossing enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . 124
LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
External amplifier power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Volume control registers (addr 0x06 - 0x0A) . . . . . . . . . . . . . . . . . . . . . 125
Mute/line output configuration register . . . . . . . . . . . . . . . . . . . . . . . . . 125
Master volume register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Channel 1 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Channel 2 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Channel 3 / line output volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Audio preset registers (addr 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Audio preset register (addr 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
AM interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Channel configuration registers (addr 0x0E - 0x10) . . . . . . . . . . . . . . . . 129
Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Tone control register (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
DocID018835 Rev 8 7/174
Contents STA381BW
Dynamic control registers (addr 0x12 - 0x15) . . . . . . . . . . . . . . . . . . . . 132
Limiter 1 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Limiter 1 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Limiter 2 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Limiter 2 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Limiter 1 extended attack threshold (addr 0x32) . . . . . . . . . . . . . . . . . 136
Limiter 1 extended release threshold (addr 0x33) . . . . . . . . . . . . . . . . 136
Limiter 2 extended attack threshold (addr 0x34 . . . . . . . . . . . . . . . . . ) 137
Limiter 2 extended release threshold (addr 0x35) . . . . . . . . . . . . . . . . 137
User-defined coefficient control registers (addr 0x16 - 0x26) . . . . . . . . . 137
Coefficient address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Coefficient b1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . 137
Coefficient b1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Coefficient b1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Coefficient b2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . 138
Coefficient b2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Coefficient b2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Coefficient a1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . 138
Coefficient a1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Fault-detect recovery constant registers (addr 0x2B - 0x2C) . . . . . . . . . 144
Device status register (addr 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
EQ coefficients configuration register (addr 0x31) . . . . . . . . . . . . . . . . . 144
Extended configuration register (addr 0x36) . . . . . . . . . . . . . . . . . . . . . 145
8/174 DocID018835 Rev 8
STA381BW
Contents
Extended post-scale range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Extended attack rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Extended BIQUAD selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
EQ soft volume configuration registers (addr 0x37 - 0x38) . . . . . . . . . . 148
Extra volume resolution configuration registers (address 0x3F; 0x40) . 149
(address 0x41; 0x42; 0x43; 0x44; 0x45; 0X46) . . . . . . . . . . . . . . . . . . . 150
Short-circuit protection mode registers SHOK (address 0x47) . . . . . . . 152
Extended coefficient range up to -4...4 (address 0x49, 0x4A) . . . . . . . . 154
Miscellaneous registers (address 0x4B, 0x4C) . . . . . . . . . . . . . . . . . . . 154
Rate power-down enable (RPDNEN) bit (address 0x4B, bit D7) . . . . . 154
Bridge immediately off (BRIDGOFF) bit (address 0x4B, bit D5) . . . . . 155
Channel PWM enable (CPWMEN) bit (address 0x4B, bit D2) . . . . . . . 155
External amplifier hardware pin enabler (LPDP, LPD LPDE) bits
(address 0x4C, bit D7, D6, D5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Power-down delay selector (PNDLSL[2:0]) bits
(address 0x4C, bit D4, D3, D2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Short-circuit check enable bit (address 0x4C, bit D0) . . . . . . . . . . . . . 156
Bad PWM detection registers (address 0x4D, 0x4E, 0x4F) . . . . . . . . . . 157
Enhanced zero-detect mute and input level measurement
(address 0x50-0x54, 0x2E, 0x2F and 0x5E) . . . . . . . . . . . . . . . . . . . . . 158
Headphone/Line out configuration register (address 0x55) . . . . . . . . . . 160
F3XCFG (address 0x58; 0x59) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
STCompressorTM configuration register (address 0x5A; 0x5B) . . . . . . 162
Charge pump synchronization (address 0x5F) . . . . . . . . . . . . . . . . . . . 163
Coefficient RAM CRC protection (address 0x60-0x6C) . . . . . . . . . . . . . 164
MISC3 (address 0x6E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
MISC4 (address 0x7E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Headphone and 2 Vrms line out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
DocID018835 Rev 8 9/174
Contents
STA381BW
10/174 DocID018835 Rev 8
STA381BW
List of tables
List of tables
Table 6.
Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DocID018835 Rev 8 11/174
List of tables STA381BW
C registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
12/174 DocID018835 Rev 8
STA381BW List of tables
DocID018835 Rev 8 13/174
List of tables STA381BW
14/174 DocID018835 Rev 8
STA381BW
List of figures
List of figures
Processing path, second part: 2.1 output with individually configurable anticlipper/DRCs. 29
Processing path, second part: 2.0 output with B
DRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Processing path, second part: 2.1 output configuration with STCompressor
TM
. . . . . . . . . 30
block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
behavior as a limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DRC scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DRC scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
DocID018835 Rev 8 15/174
List of figures STA381BW
16/174 DocID018835 Rev 8
STA381BW
1 Description
Description
The STA381BW is an integrated solution embedding digital audio processing, digital amplification, FFX TM power output stage, headphone and 2 Vrms line outputs. It is part of the Sound Terminal ® family and provides full digital audio streaming from the source to the speaker, offering cost effectiveness, low power dissipation and sound enrichment.
The STA381BW input section consists of a flexible digital input serial audio interface, feeding the digital processing unit, and an analog 1 Vrms input for a seamless connection with pure analog sources. The serial audio data input interface supports many formats, including the popular IIS format.
The STA381BW is based on an FFX TM (Fully Flexible Amplification) processor, proprietary technology from STMicroelectronics. FFX TM is the evolution of the ST ternary technology: the advanced processor is available for ternary, binary, binary differential and phase shift
PWM modulation. The STA381BW embeds the ternary, binary and binary differential implementations, a subset of the full capability of the FFX TM processor.
The STA381BW power section consists of four independent half-bridges. These can be configured via digital control to operate in different modes. A 2.1-channel setup can be implemented with two half-bridges (L/R) together with a single full-bridge (subwoofer).
Alternatively, the 2.0-channel setup can be done with two full-bridges. When using this configuration, an external amplifier for the SW channel can also be driven through the PWM output. The STA381BW is able to deliver 2 x 20 W (ternary) into an 8 load at 18 V or
2 x 9 W (binary) into a 4 load, plus 1 x 20 W (ternary) into an 8 load at 18 V.
The STA381BW also provides a capless headphone out (with embedded negative charge pump), able to deliver up to 40 mW into a 32 load or, alternatively, can be configured as a
2 Vrms line output.
The STA381BW digital processing unit includes up to 12 programmable biquads (EQs), allowing perfect sound equalization and offering advanced noise-shaping techniques.
Moreover, the coefficient range ensures a great variety of filter shapes (low/high-pass, low/high shelf, peak, notch, band-pass). The equalization engine is fully compatible with the
ST speaker compensation technology embedded into the APWorkbench suite. A state-ofthe-art multi-band DRC, STCompressor TM equalizes the system to provide active speaker protection with full audio quality preservation against sudden sound peaks. Moreover,
STSpeakerSafe TM technology offers reliable speaker protection under any condition. The master clock can be from stable BICKI (64xfs, 50% duty cycle) or external XTI.
DocID018835 Rev 8 17/174
Description
Figure 1. Block diagram
STA381BW
18/174 DocID018835 Rev 8
STA381BW Pin connections
Figure 2. Pin connections VQFN48 (top view)
VCC_REG 1
VSS_REG
2
OUT2B 3
GND2 4
VCC2 5
OUT2A
OUT1B
6
7
VCC1 8
GND1 9
OUT1A 10
VDD_REG 11
GND_REG 12
STA381BW
36 MCLK
35
AGNDPLL
34 VREGFILT
33 TWARN/FFX4A
32 EAPD/FFX4B
31 FFX3B
30 FFX3A
29 GNDDIG1
28 VDDDIG1
27 VDD3V3CHP
26 CPP
25 GNDPSUB
DocID018835 Rev 8 19/174
Pin connections STA381BW
20/174
Name
LINEINR
LINEHPOUT_L
LINEHPOUT_R
GNDA
SOFTMUTE
VDD3V3
CPVSS
CPM
GNDPSUB
CPP
VDD3V3CHP
VDDDIG1
GNDDIG1
FFX3A
FFX3B
VCC_REG
VSS_REG
OUT2B
GND2
VCC2
OUT2A
OUT1B
VCC1
GND1
OUT1A
VDD_REG
GND_REG
F3X_FILT
F3XL
F3XR
LINEINL
VQFN 48-pin
29
30
31
25
26
27
28
21
22
23
24
17
18
19
20
13
14
15
16
9
10
11
12
7
8
5
6
3
4
1
2
Table 2. Pin list
Type
Power
Filter
Power
Power
Power
Output
Output
Input
Output
Output
Power
Input
Power
Power
Filter
Power
Output
Power
Power
Power
Output
Output
Input
Power
Power
Output
Power
Power
Output
Output
Power
Description
VCC reg
Vss reg, VCC_REG-3.3 V
Half-bridge 2B output
Half-bridge 2A and 2B ground
Half-bridge 2A and 2B supply
Half-bridge 2A output
Half-bridge 1B output
Half-bridge 1A and 1B supply
Half-bridge 1A and 1B ground
Half-bridge 1A output
VDD reg 3.3 V
DC reg ground
F3X reference voltage
F3X analog out left channel
F3X analog out right channel
Line in left channel
Line in right channel
Headphone/line driver left channel
Headphone/line driver right channel
Headphone/line driver power ground
Soft mute
+3 V LDO power supply
-3.3 V charge pump pin
CHP Cfly negative
Charge pump ground
CHP Cfly positive
Charge pump power supply
I/O ring power supply
Digital core ground
Digital PWM line out
Digital PWM line out
DocID018835 Rev 8
STA381BW Pin connections
42
43
44
45
VQFN 48-pin
36
37
38
39
40
32
33
34
35
41
46
47
48
Name
Table 2. Pin list (continued)
Type
EAPD/FFX4B
TWARN/FFX4A
VREGFILT
AGNDPLL
MCLK
BICKI
LRCKI
SDI
RESET
Output
Output
Power
Power
Input
Input
Input
Input
Input
PWDN
INTLINE
SDA
SCL
SA
TEST_MODE
GNDDIG2
VDDDIG2
Input
Output
I/O
Input
Input
Input
Power
Power
Description
Digital PWM line out
Digital PWM line out
Digital VDD from core
PLL analog ground
PLL input clock
IIS serial clock
IIS left/right clock
IIS serial data input
Reset
Device power-down
0 = power-down
1 = normal operation
Fault interrupt
IIC serial data
IIC serial clock
IIC select address (pull-down)
This pin must be connected to ground (pull-down)
Digital I/O ground
Digital core LDO supply
DocID018835 Rev 8 21/174
Electrical specifications STA381BW
3.1 Absolute maximum ratings
Symbol
Table 3. Absolute maximum ratings
Parameter
Vcc
VDD_DIG
VDD3V3
VDD3V3CHP
Top
Tstg
R
Line
R
Hp
R
Btl
Power supply voltage (VCCxA, VCCxB)
Digital supply voltage
Charge pump and analog path LDO supply
Operating junction temperature
Storage temperature
Load impedance - line driver mode
Load impedance - headphone driver mode
Load impedance - power output-BTL mode
Min Typ Max Unit
-0.3
-0.3
-0.3
0
-40
1
16
5
30 V
4 V
4 V
150 °C
150 °C k
Warning: Stresses beyond those listed in
permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under
“Recommended operating conditions” are not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. In the real application, power supplies with nominal values rated within the recommended operating conditions may rise beyond the maximum operating conditions for a short time when no or very low current is sunk (amplifier in mute state). In this case the reliability of the device is guaranteed, provided that the absolute maximum ratings are not exceeded.
22/174
Symbol
Rth j-case
Tth-sdj
Tth-w
Tth-sdh
Table 4. Thermal data
Parameter
Thermal resistance junction-case (thermal pad)
Thermal shutdown junction temperature
Thermal warning temperature
Thermal shutdown hysteresis
DocID018835 Rev 8
Min Typ Max Unit
150
130
20
1.5
°C/W
°C
°C
°C
STA381BW
3.3
Electrical specifications
Recommended operating conditions
Symbol
Table 5. Recommended operating conditions
Parameter
Vcc
R
Line
R
Hp
R
Btl
Power supply voltage (VCCxA, VCCxB)
VDD_DIG
VDD3V3
VDD3V3CHP
Tamb
Digital supply voltage
Charge pump and analog path LDO supply
Ambient temperature
Load impedance - line driver mode
Load impedance - headphone driver mode
Load impedance - power output-BTL mode
Min Typ Max Unit
4.5
2.7
2.7
0
5
16
5
3.3
3.3
10
32
8
26
3.6
3.6
70
V
V
V
°C k
3.4 Electrical specifications for the digital section
The specifications given in this section are valid for the operating conditions:
VDD_DIG = 3.3 V, T amb
= 25 °C.
V il
V ih
V ol
V oh
R pu
Table 6. Electrical specifications - digital section
Symbol Parameter Conditions Min Typ
I il
I ih
Low level input current without pull-up/down device
High level input current without pull-up/down device
Low level input voltage
High level input voltage
Low level output voltage
High level output voltage
V i
= 0 V
V i
= VDD_DIG
= 3.3 V
I ol
= 2 mA
I oh
= 2 mA
2.0
VDD_DIG
-0.15
Pull-up/down resistance 50
Max
0.5
0.1
0.8
0.15
Unit
μ A
μ A
V k
V
V
V
DocID018835 Rev 8 23/174
Electrical specifications STA381BW
3.5 Electrical specifications for the power section
The specifications given in this section are valid for the operating conditions: V
CC f = 1 kHz, f sw
= 384 kHz, T amb
= 25° C and R
L
= 8 , unless otherwise specified.
= 24 V,
Table 7. Electrical specifications - power section
Symbol Parameter Conditions
Po
Output power BTL
Output power SE
Digital limited
(1)
Digital limited
(1)
Digital limited
(1)
R dsON gP gN
Output power SE R
L
= 4
Power Pchannel/Nchannel MOSFET l d
= 1.5 A
Power Pchannel R dsON
matching l d
= 1.5 A
Power Nchannel R dsON
matching
Idss Power Pchannel/Nchannel leakage l d
= 1.5 A
I
LDT t t f r
Low current dead time (static)
Rise time
Fall time
Resistive load
(2)
Resistive load
(2)
Resistive load
(2)
Supply current from Vcc in power-down PWRDN = 0
Min
95
95
I vcc
Supply current from Vcc in operation
PCM Input signal = -60 dBfs,
Switching frequency = 384 kHz,
No LC filters
Ilim Overcurrent limit
UVL Undervoltage protection
V
OV t min
DR
Overvoltage protection
Output minimum pulse width
Dynamic range
SNR
Signal-to-noise ratio, ternary mode
Signal-to-noise ratio, binary mode
THD+N Total harmonic distortion + noise
No load
A-weighted
A-weighted
FFX stereo mode, Po = 1 W, f = 1 kHz
4
20
52
5
3.5
28.25
30
100
100
90
0.2
8
10
10
0.1
Typ Max Unit
20
5
9
120
W m
%
%
10 μ A
15 ns
18 ns
18 ns
1 μ A
60 mA
6.5
A
4.3
V
V
60 ns dB dB dB
%
X
TALK
Crosstalk
Peak efficiency, FFX mode
FFX stereo mode,
<5 kHz, one channel driven at
1 W and other channel measured
Po = 2 x 20 W into 8
2. Refer to
80
90 dB
%
24/174 DocID018835 Rev 8
STA381BW
Figure 3. Test circuit
Electrical specifications
DocID018835 Rev 8 25/174
Electrical specifications STA381BW
Figure 4. Power-on sequence
Note: no specific VCC and
VDD_DIG turn
− on sequence is required
VCC
VDD_DIG
XTI or BICKI
HW RESET
I 2 C
Don’t care
TR TC
Don’t care CMD0 CMD1 CMD2
Note:
HW PWDN
TR = minimum time between XTI master clock stable and Reset removal: 1 ms
TC = minimum time between Reset removal and I
2
C program, sequence start: 1ms
The definition of a stable clock is when fmax - fmin < 1 MHz.
Section 6.14.1: Serial data interface
gives information on setting up the I
2
S interface.
Figure 5. Power-off sequence for pop-free turn-off
Note: no specific VCC and
VDD_DIG turn
− off sequence is required
VCC
VDD_DIG
Note:
XTI or BICKI
Soft Mute
Reg. 0x07
Data 0xFE
FE
Soft EAPD
Reg. 0x05
Bit 7 = 0
The register addresses for Soft Mute and Soft EAPD refer to Sound Terminal compatibility
(see Section 7: Register description: Sound Terminal compatibility on page 106
) and are not the default addresses.
26/174 DocID018835 Rev 8
STA381BW Electrical specifications
3.7 Electrical specifications for the analog section
The specifications given in this section are valid for the operating conditions: V
CC
= 24 V f = 1 kHz, T amb
= 25 °C, VDD3V3 = 3.3 V, R
Line
= 5 k , R
Hp
= 32 , unless otherwise specified.
Symbol
Table 8. Electrical specifications for the analog section
Parameter Conditions Min Typ Max Unit
Vout
Pout
DR
Output voltage for line out
Output voltage for HP out
Dynamic range for line out
G v
= 2.5, THD < 1%, Rload = 5 k
THD+N = 10%, G v
= 2.5, Rload = 32
Vout = 2 V
RMS
V in
, F in
= 200 Hz,
= 0.8 mV (-60 dBFs)
X-Talk Channel separation for line out V out
= 2 Vrms, G v
= 2.5
PSRR Power supply rejection ratio
HP mode, P
0
= 15 mW
Line out mode, V
Out
= 2 Vrms
R in
Line input resistance
THD+N Total harmonic distortion + noise
HP mode, V out
= 200 mV
RMS
, G v
= 2.5
Line out mode, V
Out
= 0.2 Vrms, G v
= 2.5
1.9
40
100
75
70
70
0.03
0.03
1. Refer to 8.2: Headphone and 2 Vrms line out
,
Figure 49: Headphone and line out block diagram , R
in
= R1
2.1
Vrms mW
30
(1) dB dB dB k
%
%
DocID018835 Rev 8 27/174
Device overview STA381BW
4.1
The mentioned hyperlink in this section relates to the default New Map
Section 6: Register description: New Map
.
Processing data path
The whole STA381BW processing chain is composed of two consecutive sections. In the first one dual-channel processing is implemented (
Figure 6 ) and then each channel is fed
into the post-mixing block allowing to generate either a third channel (typically used in 2.1 output configurations together with crossover filters) or to have the channels processed by the dual-band DRC block (2.0 output configuration with crossover filters used to define the cutoff frequency of the two bands).
The first section begins with a 2x oversampling FIR filter allowing 2*Fs audio processing.
Then a selectable high-pass filter removes the DC level (enabled if HFB = 0). The channel 1 and 2 processing chain can include up to 8 filters, depending on the selected configuration
(bits BQL, BQ5, BQ6, BQ7 and XO[3:0]). By default, 4 independent filters per channel are enabled, plus the pre-configured Bass and Treble controls (BQL=0, BQ5=0, BQ6=0,
BQ7=0).
The STA381BW offers the possibility to share the filter coefficients between the two processing channels. When this option is set (BQL=1), filters from the 1st to the 4th have the same coeffcients set. Under these conditions, filters from the 5th to 7th can be used as custom filters as well (provided the relevant BQx bits are set). Once again filter coefficients are shared between the two processing channels.
Moreover the common 8th filter, from the subsequent processing section, can be available on both channels (provided the pre-defined crossover frequencies are not used, XO[3:0]=0, and the dual-band DRC is not used).
Figure 6. Processing path, first part
I2S Input
Interface
Sampling Frequency = 2xFs
X2Over-
-sampling
FIR
Pre-
-scale
Hi-Pass
Filter
Biquad
#1
Biquad
#2
Biquad
#3
Biquad
#4
De-emph
Or
Biquad #5
Bass
Or
Biquad #6
Treble
Or
Biquad #7
Userd Defined Filters Tone Control
Sampling Frequency = Fs
L
X2Over-
-sampling
FIR
Pre-
-scale
Sampling Frequency = 2xFs
Hi-Pass
Filter
Biquad
#1
Biquad
#2
Biquad
#3
Biquad
#4
De-emph
Or
Biquad #5
Bass
Or
Biquad #6
Treble
Or
Biquad #7
Userd Defined Filters Tone Control
R
28/174 DocID018835 Rev 8
STA381BW Device overview
The second processing stage embeds a mixing block, a biquadratic/crossover filter, a DRC stage, the volume control, a DC cut filter and a post scaler. Depending on the device settings, the following configuration and features are available:
2.1 output with individually configurable anticlipper/DRCs (
configurable DRC/anticlippers are available while the eighth biquadratic filter, jointly with the mixer block, can be used to perform LFE. This configuration and features ensure the backward compatibility with previous Sound Terminal
®
products.
Figure 7. Processing path, second part: 2.1 output with individually configurable anticlipper/DRCs
L
R
C1Mx1
+
C1Mx2
Ch an n el ½
Biq uad #8
--------------
Hi-p ass XO
Filter
Ch an n el 1
Vo lume
An ti-clipper
/
DRC
DC Cut
Filter
Po st Scale
C2Mx1
+
C2Mx2
Ch an n el ½
Biq uad #8
--------------
Hi-p ass XO
Filter
Ch an n el 2
Vo lume
An ti-clipper
/
DRC
DC Cut
Filter
Po st Scale
C3Mx1
+
C3Mx2
Ch an n el 3
Biq uad #8
--------------
Lo w-p ass XO filter
U s er-D efined
M ix C oeffic ients
C ros sov er F requenc y
D eterm ined by XO Setting
(User Defin ed If
XO =0000)
Ch an n el 3
Vo lume
An ti-clipper
/
DRC
DC Cut
Filter
Po st Scale
DocID018835 Rev 8 29/174
Device overview STA381BW
2.0 output with B 2
DRC ( Figure 8 ): the mixer and the eighth biquadratic filter are used to
divide the channel into two sub-bands, then each sub-band is independently processed by a DRC block. The two bands are then re-composed and fed to the following processing blocks. The crossover frequency is user-selectable. This configuration and features ensure the backward compatibility with the previous Sound Terminal ® products. For further information please refer to
Chapter 6.11.1: Dual-band DRC .
Figure 8. Processing path, second part: 2.0 output with B 2 DRC
Channel 3
Volume
DRC 2
L
R
C1Mx1
+
C1Mx2
B 2 DRC
Hi-pass XO filter
-
+
Channel 1
Volume
DRC 1
+
DC Cut
Filter
Post Scale
C2Mx1
+
C2Mx2
B 2 DRC
Hi-pass XO filter
- +
Channel 2
Volume
DRC 1
C3Mx1
+
C3Mx2
C2Mx1
+
C2Mx2
Channel 3
Volume
Channel ½
Biquad #8
--------------
Hi-pass XO
Filter
STCompressor
Volume
And
Limiter
DRC 2
+
DC Cut
Filter
DC Cut
Filter
Post Scale
User-Defined
Mix Coefficients
Crossover Frequency
Determined by XO Setting
(User Defined If
XO=0000)
2.1 output with STCompressor TM (
Figure 9 ): the STA381BW embeds the latest, state-
of-the-art multi-band dynamic, range compressor, called STCompressor TM . When using this configuration, up to 10 biquad filters are available for dedicated processing.
Please refer to
for further information about this feature.
Figure 9. Processing path, second part: 2.1 output configuration with
STCompressor TM
L
R
C1Mx1
+
C1Mx2
Channel ½
Biquad #8
--------------
Hi-pass XO
Filter
STCompressor
Volume
And
Limiter
DC Cut
Filter
Post Scale
Post Scale
C3Mx1
+
C3Mx2
Channel 3
Biquad #8
--------------
Low-pass XO filter
User-Defined
Mix Coefficients
Crossover Frequency
Determined by XO Setting
(User Defined If
XO=0000)
Volume
And
Limiter
DC Cut
Filter
Post Scale
30/174 DocID018835 Rev 8
STA381BW Device overview
Figure 6 shows the input oversampling block in front of the main processing. When 32 kHz
Fs is used, the default x2 oversampling ratio can be increased to a x3.
Activating this feature, it is possible to have a 384 kHz PWM switching frequency (instead of the default 256 kHz) when 32 kHz Fs is used.
When bit 0 of register PLLCFG1 is set to one, the feature is activated so that the PLL ratio is modified to generate 49.152 MHz internal clock and the audio data path (after the input oversampling block) is running at 96 kHz.
It is not recommended to use the x3 oversampling feature when Fs > 32 kHz because of the
PLL maximum frequency constraint.
4.3 STCompressor TM
The STCompressor TM (STC from now on) is a stereo, dual-band Dynamic Range Control
(DRC) and its main purpose is to provide optimum output power level control for speaker protection, preserving as much as possible the original audio quality of the signal.
Two main I 2 C registers control the STC behavior: STCCFG0 and STCCFG1. On top of the data flow control bits, these registers also allow enabling the checksum engine to protect the
STC filters from erroneous coefficients downloads, thus improving the final application circuitry and safety of the speakers.
DocID018835 Rev 8 31/174
Device overview
4.3.1 STC block diagram
In p ut
Ch 0
Figure 10. STCompressor TM block diagram
Ban d 0
(Lo w freq s)
Ban d
Sp litter
Ban d 1
(Hig h freq s)
Level
Meter
Level
Meter
DRC 0
Map p er
DRC 1
Map p er
O ffs et
Atten uato r
Atten uato r
O ffs et
X
X
STA381BW
+
O utp ut
Ch 0
Ban d 0
(Lo w freq s )
In p ut
Ch 1
Ban d
Sp litter
Ban d 1
(Hig h freq s)
Lev el
Meter
Lev el
Meter
DRC 2
O ffset
Atten uato r Map p er
DRC 3
Map p er Atten uato r
O ffset
X
+
O utp ut
Ch 1
X
The STC takes as input 2 channels and every channel is processed independently (i.e. an independent DRC for each band of each channel) following the steps listed below
1.
Splits the input signal into 2 bands (band splitter)
2. Measures the level of the signal (level meter)
3. Computes the attenuation (mapper)
4. Applies the attenuation and offset (attenuator)
The band splitter settings are common to both the processing channels while the settings of the remaining blocks can be independently set for each band of each processing channel.
Caution: All the settings explained hereafter apply only to the behavior of the STCompressor
TM
. For
32/174
The band splitter block is used to divide the signal into 2 sub-bands (typically low- and high- frequency bands). This is done through two 2 nd order biquads (IIR filters) for each band, thus allowing to have up to a 4 th order filter per band. This feature guarantees a totally flat band recombination (see
). Using different filtering orders, indeed, causes a nonnegligible gain around the filter’s cutoff frequency, endangering the overall audio fidelity and, eventually, also the safety of the speaker. The sub-band recombination can be enabled or disabled.
DocID018835 Rev 8
STA381BW Device overview
The band splitter filter coefficients have a user-selectable range [-1, 1), [-2, 2) and [-4, 4).
The RAM coefficient 0x7 is responsible for these settings according to Table 9 . The range
default value is [-4, 4).
Table 9. Coefficients extended-range configuration 0x74h
CEXT_Bx[1] CEXT_Bx[0] Range
0
0
0
1
[-1;1)
[-2;2)
1
1
0
1
[-4;4)
Reserved
Please refer to
Section 6.24: User-defined coefficient control registers (addr 0x27 - 0x37)
and to
Figure 11. Band splitter with 4 th order filtering
BQ 0
Band Splitter
BQ 1
Input
Ch x
Band 0
…
Output
Ch x
+ =
BQ 0 BQ 1
Band 1
…
The level meter block measures the input signal level (in dB). Two kinds of measures are performed: peak and RMS. The mapper configuration and the input signal automatically determine which measurement to take into account.
4.3.4 Mapper
The mapper block computes the appropriate attenuation value (expressed in dB) to be applied to the signal, basing its calculations on the level meter output value, on the compressor threshold and on the limiter threshold.The attenuation value is then passed to the attenuator block.
DocID018835 Rev 8 33/174
Device overview STA381BW
The STC reacts differently depending on these three parameters ( Figure 12 ):
level meter output value < compressor threshold < limiter threshold: under these circumstances the signal level is small enough to not require any type of limiting/compressing action. The signal remains unchanged.
compressor threshold < level meter output value < limiter threshold: under these circumstances the signal level is compressed to a ratio determined by the compressor rate.
compressor threshold < limiter threshold < level meter output value: under these circumstances the signal level exceeds the limiter threshold which represents the maximum output power allowed. The signal is limited to avoid unpredictable effects and damages.
The compressor threshold, the limiter threshold and the compressor rate are all userselectable parameters. The compressor threshold range of value is [-48, 0] dB with a
0.25 dB step. The limiter threshold range of values is [-24, +12] dB with a 0.25 dB step. The compressor ratio range of value is [0, 15], the meaning of these values is specified in
. For further details please refer to Table 12
. Either setting the compressor rate to
1:1 or setting the compressor threshold greater than the limiter threshold makes the STC behave as a pure limiter (
Figure 12. STCompressor
TM
behavior
Linear Zone
Compression Zone
Limiting Zone
L.T.
C.R.
C.T.
C.T.
L.T.
INPUT
L.T. comp
[dB]
34/174 DocID018835 Rev 8
STA381BW
L.T.
Figure 13. STCompressor TM behavior as a limiter
Linear Zone
Limiting Zone
Device overview
L.T.
INPUT
[dB]
Compressor ratio
Table 10. Compressor ratio
12
13
14
15
10
11
8
9
6
7
4
5
2
3
0
1
Ratio value
1:4
1:4.5
1:5
1:5.5
1.6
1:7
1:8
1:16
1:1
1:1.25
1:1.5
1:1.75
1:2
1:2.5
1:3
1:3.5
DocID018835 Rev 8 35/174
Device overview STA381BW
4.3.5 Attenuator
The attenuation is characterized by two different phases: attack and release.
Given an input signal above the limiter threshold, during the attack phase the STC decreases the gain in order to reach the output level determined by the mapper. In this process the key parameter is the attack rate (dB/ms) which determines how fast the STC reacts according to the following equation:
AttackTime =
AttackRate where:
Output Signal Level is the attenuated signal coming from the attenuator block itself and used as feedback
Mapper Level is the target signal level to be reached
The attack rate is user-selectable and its range is [0, +16] dB/ms with a 0.25 dB/ms step.
Given an input signal moving below the limiter threshold, during the release phase the STC increases the gain in order to return the original input signal dynamic. In this process the key parameter is the release rate (dB/ms) which determines how fast the STC releases the attenuation on the input signal according to the following equation:
ReleaseTime
=
ReleaseRate
The release rate is user-selectable and its range is [0.0078, 1) dB/ms with a 0.0039 dB/ms step.
Due to its dynamic, the input signal may exceed the limiter threshold by a variable amount of decibels. In such different situations it might be useful to be able to tune the attack rate to make the STC react slower or faster depending on the context. The attack rate value, set by the user, can be dynamically varied through the dynamic attack rate (DAR). It is a parameter
(expressed in ms/dB) acting as a weighted coefficient, multiplying the difference between the attenuator output signal and the mapper target level. The dynamic attack rate affects the user-programmed attack rate according to the following equations:
DynamicAttackTime
=
OutputSignalLevel MapperLevel DAR
AttackTime =
OutputSignalLevel MapperLevel
AttackRate
+ DynamicAttackTime
AttackRate
=
The DAR is user-definable and its range of values is [0, +1) ms/dB, (
0.0039 ms/dB step. The DAR is the same for all 4 sub-bands.
36/174 DocID018835 Rev 8
STA381BW Device overview
4.3.7 Offset
The offset is a user-selectable gain or volume control. When using the STC it is advised to use the offset to tune the output volume instead of the regular volume controls. The offset is located before the attenuator block, ensuring that the output power limit (limiter threshold) is never exceeded (
Figure 14 ). On the other side, the traditional volume control is located after
the STC attenuator, thus a wrong setting of this control could nullify the STC effect.
Each sub-band has its own and independent offset. Its range is [0, +48] dB with a 0.25 dB step (
Figure 14. Offset effect
The stereo link feature allows applying the same attenuation to the corresponding band of each channel (i.e. band 0 left channel and band 0 right or band 1 left channel and band 1 right channel). This should help to prevent image shifting that could occur when individually compressing each channel and causing a volume mismatch between left and right.
When the stereo link is active, the proper attenuation for each band is independently computed, then the highest one for each band is applied (
).
DocID018835 Rev 8 37/174
Device overview
4.3.9
STA381BW
Figure 15. Stereo link block diagram
Ch 0 – Band 0
From mapper
Ch 0 – Band 0
From mapper
Ch 0 – Band 1
Ch 0 – Band 1
Ch 1 – Band 0
From mapper
Ch 1 – Band 0
From mapper
Ch 1 – Band 1
Ch 1 – Band 1
Attenuator
Attenuator
Attenuator
Attenuator
Attenuator
Max
Attenuation
Band 0
Attenuator
Attenuator
Max
Attenuation
Band 1
Attenuator
X
X
X
X
+
+
Output
Ch 0
Output
Ch 1
Programming of coefficients
The coefficients are expressed in different value ranges and in decimal notation (refer to the previous paragraphs). In order to be programmed they must be converted into a
[-1, +1) range and in hexadecimal notation (
Table 11 ). This can be achieved with the
following procedure:
if CoeffDecValue>0
CoeffI2CValue =
6
2
23
if CoeffDecValue<0
CoeffI2CValue
=
2
24
–
6
2
23
where CoeffI2CValue is the final decimal value to be converted into hexadecimal notation while CoeffDecValue is the coefficient value (in decimal notation) to start from.
38/174 DocID018835 Rev 8
STA381BW Device overview
Table 11. Conversion example
Original value (dec) I
2
C value (hex)
+48.00
+24.00
+16.00
+12.00
+06.00
+02.00
+01.00
-01.00
-02.00
-06.00
-12.00
-24.00
-48.00
0x600000
0x300000
0x200000
0x180000
0x0C0000
0x040000
0x020000
0xFE0000
0xFC0000
0xF40000
0xE80000
0xD00000
0xA00000
DocID018835 Rev 8 39/174
Device overview STA381BW
All the control parameters listed in the previous paragraphs are stored in the internal device memory. Please refer to
Table 13 for a complete list of their addresses.
For the programming procedure please refer to
the STC coefficients memory.
Function
Table 12. STC coefficients memory map
Address Parameter Range Precision Unit
0x54 RR: release rate
0x55 AR: attack rate
0x56 LT: limiter threshold
0x57 CR: compressor ratio
0x58 CT: compressor threshold
[0.0078,1)
[0,16]
[-24, +12]
[0,15]
[-48, 0]
0.0039
0.25
0.25
1
0.25
dB/ms dB/ms dB index dB
Default
0x200000
0x200000
0x000000
0x000000
0x000000
OFFSET
Dynamic attack rate
CRC expected
CRC computed
Biquads CTRL
0x59 RR: release rate
05A AR: attack rate
0x5B LT: limiter threshold
0x5C CR: compressor ratio
0x5D CT: compressor threshold
[0.0078,1)
[0,16]
[-24, +12]
[0,15]
[-48, 0]
0x5E RR: release rate
0x5F AR: attack rate
0x60 LT: limiter threshold
0x61 CR: compressor ratio
0x62 CT: compressor threshold
[0.0078,1)
[0,16]
[-24, +12]
[0,15]
[-48, 0]
0x63 RR: release rate
0x64 AR: attack rate
0x65 LT: limiter threshold
0x66 CR: compressor ratio
0x67 CT: compressor threshold
0X68 OFS0: offset DRC 0
0X69 OFS1: offset DRC 1
0X6A OFS2: offset DRC 2
0X6B OFS3: offset DRC 3
[0.0078,1)
[0,16]
[-24, +12]
[0,15]
[-48, 0]
[0, +48]
[0, +48]
[0, +48]
[0, +48]
0x71 DAR: dynamic attack rate
0x72
0x73
0x74
Band splitter filter coefficients range
[0, 1)
0.0039
0.25
0.25
1
0.25
0.25
0.25
0.25
0.25
0.0039
0.25
0.25
1
0.25
0.0039
0.25
0.25
1
0.25
0.0039
dB/ms dB/ms dB index dB dB dB dB dB dB/ms dB/ms dB index dB dB/ms dB/ms dB index dB ms/dB
0x200000
0x200000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x200000
0x200000
0x000000
0x000000
0x000000
0x200000
0x200000
0x000000
0x000000
0x000000
0x000000
0x0000AA
40/174 DocID018835 Rev 8
STA381BW
Function
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
Table 13. STC band splitter filters memory map
Address Coefficient Range
0x40
0x41
0x42
0x43
0x44
B1/2
B2
-A1/2
-A2
B0/2
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
B1/2
B2
-A1/2
-A2
B0/2
B1/2
B2
-A1/2
-A2
B0/2
B1/2
B2
-A1/2
-A2
B0/2
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
Device overview
Default
0x000000
0x000000
0x000000
0x000000
0x100000
0x000000
0x000000
0x000000
0x000000
0x100000
0x000000
0x000000
0x000000
0x000000
0x100000
0x000000
0x000000
0x000000
0x000000
0x100000
DocID018835 Rev 8 41/174
I 2 C bus specification
5 I
2
C bus specification
STA381BW
The STA381BW supports the I 2 C protocol via the input ports SCL and SDA_IN (master to slave) and the output port SDA_OUT (slave to master). This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. The STA381BW is always a slave device in all of its communications. It supports up to 400 kb/sec rate (fast-mode bit rate). The STA381BW I 2 C is a slave-only interface. The I 2 C interface works properly only in the case that the master clock generated by the PLL has a frequency 10 times higher compared to the frequency of the applied SCL signal.
5.1.1 Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. An SDA transition while the clock is high is used to identify a START or STOP condition.
START is identified by a high-to-low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer.
STOP is identified by a low-to-high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communication between the STA381BW and the bus master.
During the data input the STA381BW samples the SDA signal on the rising edge of clock
SCL. For correct device operation, the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low.
42/174
To start communication between the master and the STA381BW, the master must initiate with a start condition. Following this, the master sends to the SDA line 8 bits (MSB first) corresponding to the device select address and read or write mode.
The seven most significant bits are the device address identifiers, corresponding to the I
2
C bus definition. In the STA381BW the I
2
C interface has two device addresses depending on the SA port configuration, 0x38 when SA = 0, and 0x3A when SA = 1.
The eighth bit (LSB) identifies read or write operation RW, this bit is set to 1 for read mode and to 0 for write mode. After a START condition the STA381BW identifies on the bus the
DocID018835 Rev 8
STA381BW I 2 C bus specification device address and if a match is found, it acknowledges the identification on SDA bus during the 9th bit time. The byte following the device identification byte is the internal space address.
Following the START condition, the master sends a device select code with the RW bit set to 0. The STA381BW acknowledges this and then waits for the byte of the internal address.
After receiving the internal byte address the STA381BW again responds with an acknowledgement.
In the byte write mode the master sends one data byte which is acknowledged by the
STA381BW. The master then terminates the transfer by generating a STOP condition.
The multi-byte write mode can start from any internal address. The master generating a
STOP condition terminates the transfer.
5.4.1
5.4.2
5.4.3
5.4.4
Current address byte read
Following the START condition, the master sends a device select code with the RW bit set to 1. The STA381BW acknowledges this and then responds by sending one byte of data.
The master then terminates the transfer by generating a STOP condition.
Current address multi-byte read
The multi-byte read modes can start from any internal address. Sequential data bytes are read from sequential addresses within the STA381BW. The master acknowledges each data byte read and then generates a STOP condition, terminating the transfer.
Random address byte read
Following the START condition, the master sends a device select code with the RW bit set to 0. The STA381BW acknowledges this and then the master writes the internal address byte. After receiving the internal byte address, the STA381BW again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA381BW acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.
Random address multi-byte read
The multi-byte read mode can start from any internal address. Sequential data bytes are read from sequential addresses within the STA381BW. The master acknowledges each data byte read and then generates a STOP condition, terminating the transfer.
DocID018835 Rev 8 43/174
I 2 C bus specification
5.4.5 Write mode sequence
Figure 16. Write mode sequence
STA381BW
5.4.6 Read mode sequence
Figure 17. Read mode sequence
RANDOM
READ
S T A R T R W
S T A R T R W
44/174 DocID018835 Rev 8
STA381BW
6 Register description: New Map
Register description: New Map
Addr Name
0x08
0x09
0x0A
0x10
0x11
0x12
0x13
0x14
0x00 CLK
0x01 STATUS
0x02
0x03
RESET
SVOL
0x04 MVOL
0x05 FINEVOL
0x06 CH1VOL
0x07 CH2VOL
POST
OPER
FUNCT
HPCFG
CONFA
CONFB
CONFC
CONFD
0x15
0x16
CONFE
CONFF
0x17 MUTELOC
0x1B CH3VOL
0x1D
0x1F
0x20
0x21
AUTO
C1CFG
C2CFG
C3CFG
0x22
0x23
0x24
TONE
L1AR
L1ATRT
Mapping of two registers is available on the STA381BW, the selection is done by setting register 0x7E bit D7. By default, 0x7E is set to 1 and refers to a map that is not compatible with previous Sound Terminal devices. This register’s mapping is also called “New Map”.
To keep compatibility with previous Sound Terminal devices, 0x7E bit D7 must be set to 0 after device turn-on and after any reset (via SW or via external pin). Please refer to
Section 7: Register description: Sound Terminal compatibility for all the information about
device compatibility.
Missing addresses are to be considered as reserved.
D7
FAULT
Table 14. Default register map table: NEW MAP
D6 D5 D4 D3 D2
CLK_CFG[3:0]
DRCCRC EQCRC BADPWM
D1 D0
I2SERR
I2S
PLLUL
SRESET
SVOL[1:0]
FDRB
C2IM
SME
EAPD
LOC1
XO3
C3OM1
TTC3
L1A3
L1AT3
CRC
C1IM
ZDE
ZCE
PWDN
LOC0
XO2
C3OM0
TTC2
L1A2
L1AT2
APEQ
DSCKE
CSZ3
XO1
C3LS1
TTC1
L1A1
L1AT1
MVOL[7:0]
CH1VOL[7:0]
CH2VOL[7:0]
POST[7:0]
PEQ
IR1
SAIFB
CSZ2
BQL
IR0
SAI3
CSZ1
PSL
PWMS
LDTE
AME
BCLE
C3M
CH3VOL[7:0]
XO0 AMAM2
C1BO
C3LS0
TTC0
L1A0
L1AT0
C2BO
C3BO
BTC3
L1R3
L1RT3
AMDRC
AMAM1
C1VBP
C2VBP
C3VBP
BTC2
L1R2
L1RT2
MCS2
SAI2
CSZ0
DSPB
NSBW
IDE
C2M
FINE[1:0]
OPER[1:0]
MDRCE DRC
MCS1
SAI1
MUTE
MCS0
SAI0
C1M
AMAM0
C1EQBP
C2EQBP
BTC1
L1R1
L1RT1
MMUTE
AMAME
C1TCB
C2TCB
BTC0
L1R0
L1RT0
DocID018835 Rev 8 45/174
Register description: New Map STA381BW
Addr Name
Table 14. Default register map table: NEW MAP (continued)
D7 D6 D5 D4 D3 D2 D1 D0
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x3C
0x3D
0x25
0x26
L2AR
L2ATRT
0x27 CFADDR
0x28 B1CF1
0x29
0x2A
0x2B
0x2C
B1CF2
B1CF3
B2CF1
B2CF2
B0CF2
B0CF3
CFUD
FDRC1
FDRC2
B2CF3
A1CF1
A1CF2
A1CF3
A2CF1
A2CF2
A2CF3
B0CF1
0x3F
0x40
0x43
0x44
MTH2
MTH1
EATH1
ERTH1
0x45
0x46
EATH2
ERTH2
0x47 CONFX
0x52 PLLFRAC1
0x53 PLLFRAC2
0x54 PLLDIV
L2A3
L2AT3
C3B7
C4B23
C4B15
C4B7
C5B23
C5B15
C5B7
C1B23
C1B15
C1B7
C2B23
C2B15
C2B7
C3B23
C3B15
FDRC15
FDRC7
EATHEN1
ERTHEN1
EATHEN2
ERTHEN2
L2A2
L2AT2
C3B6
C4B22
C4B14
C4B6
C5B22
C5B14
C5B6
C1B22
C1B14
C1B6
C2B22
C2B14
C2B6
C3B22
C3B14
FDRC14
FDRC6
PLL_DITH[1:0]
C2B5
C3B21
C3B13
C3B5
C4B21
C4B13
C4B5
C5B21
C5B13
C5B5
L2A1
L2AT1
CFA5
C1B21
C1B13
C1B5
C2B21
C2B13
FDRC13
FDRC5
PS48DB
C2B4
C3B20
C3B12
C3B4
C4B20
C4B12
C4B4
C5B20
C5B12
C5B4
L2A0
L2AT0
CFA4
C1B20
C1B12
C1B4
C2B20
C2B12
FDRC12
FDRC4
C2B3
C3B19
C3B11
C3B3
C4B19
C4B11
C4B3
C5B19
L2R3
L2RT3
CFA3
C1B19
C1B11
C1B3
C2B19
C2B11
C5B11
C5B3
RA
FDRC11
FDRC3
MTH[21:16]
MTH[15:8]
EATH1[6:0]
ERTH1[6:0]
EATH2[6:0]
XAR1
ERTH2[6:0]
XAR2
PLL_FRAC[15:8]
PLL_FRAC[7:0]
FDRC2
BQ5
PLL_NDIV[5:0]
C2B1
C3B17
C3B9
C3B1
C4B17
C4B9
C4B1
C5B17
L2R1
L2RT1
CFA1
C1B17
C1B9
C1B1
C2B17
C2B9
C5B9
C5B1
WA
FDRC9
FDRC1
C2B2
C3B18
C3B10
C3B2
C4B18
C4B10
C4B2
C5B18
L2R2
L2RT2
CFA2
C1B18
C1B10
C1B2
C2B18
C2B10
C5B10
C5B2
R1
FDRC10
BQ6
C2B0
C3B16
C3B8
C3B0
C4B16
C4B8
C4B0
C5B16
L2R0
L2RT0
CFA0
C1B16
C1B8
C1B0
C2B16
C2B8
C5B8
C5B0
W1
FDRC8
FDRC0
BQ7
0x55
0x56
0x57
0x58
0x5A
PLLCFG0
PLLCFG1
PLLSTATE
SHOK
CXT41
PLL_DPD PLL_FCT
CEXT_B4[1:0]
PLL_STB
PLL_
STBBYP
CEXT_B3[1:0]
PLL_IDIV[3:0]
PLL_DIRP PLL_PWD PLL_BYP OSC_PD
BYPSTATE PDSTATE
GNDSH
CEXT_B2[1:0]
OSCOK
BOOST32K
LOWCK
VCCSH OUTSH
CEXT_B1[1:0]
46/174 DocID018835 Rev 8
STA381BW Register description: New Map
0x61
0x62
0x63
0x64
0x65
0x66
0x69
0x6A
0x5B
0x5C
0x5D
0x5E
0x60
Addr Name
0x6B STCCFG0
Table 14. Default register map table: NEW MAP (continued)
D7
CXT75
MISC1
MISC2
BPTH
BPTIM
ZCCFG0
ZCCFG1
ZCCFG2
RPDNEN
LPDP
WTHH
ZCCFG3
ZCCFG4
HPCFG HPLN
F3XCFG1 F3XLNK
F3XCFG2 F3X_FAULT
D6
LPD
WTHL
D5 D4 D3 D2
CEXT_B7[1:0]
BRIDGOFF
LPDE
BPTH[5:0]
FINETH
BPTIM[7:0]
HSEL[1:0]
RMS_CH0[7:0]
CEXT_B6[1:0]
CPWMEN
PNDLSL[2:0]
RMS_CH0[15:8]
RMS_CH1[7:0]
RMS_CH1[15:8]
CPFEN CPOK
F3X_SM_SLOPE[2:0]
NP_
CRCRES
D1 D0
CEXT_B5[1:0]
ZMTH[2:0]
ABFAULT
SHEN
DCROK
F3X_MUTE F3X_ENA
0x6C
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
STCCFG1
MTH0
CHPSINC
BQCHKE0
BQCHKE1
BQCHKE2
XCCHKE0
XCCHKE1
XCCHKE2
BQCHKR0
BQCHKR1
BQCHKR2
XCCHKR0
XCCHKR1
XCCHKR2
CHKCTRL XCAUTO
MISC4 SMAP
CHPI
MTH[7:0]
INITCNT[3:0]
BQ_CKE[7:0]
BQ_CKE[15:8]
BQ_CKE[23:16]
XC_CKE[7:0]
XC_CKE[15:8]
XC_CKE[23:16]
BQ_CKR[7:0]
BQ_CKR[15:8]
BQ_CKR[23:16]
XC_CKR[7:0]
XC_CKR[15:8]
XC_CKR[23:16]
BCAUTO
STC_LNK
WRA
CHPRD
CH12
DocID018835 Rev 8 47/174
Register description: New Map
6.1 CLK register (addr 0x00)
D7
Bit
5
4
7
6
0
0
STA381BW
R/W
R/W
R/W
R/W
R/W
R/W
D6 D5
0
CLK_CFG[3:0]
0
RST
0
0
0
0
0
D4
0
D3
Reserved
0
D2
Reserved
0
D1
Reserved
0
D0
I2S
0
Table 15. CLK register
Name Description
CLK_CFG[3:0]
I2S
0000: 44.1/48 kHz BITCLK = 64 Fs
0001: 32 kHz BITCLK = 64 Fs
0010: 96 kHz BITCLK = 64 Fs
0011: 48/44.1/32 kHz MCK = 256 Fs others: clock configuration depends on IR/MCS bits
0 = SAI configured in I
2
S mode
1 = SAI configuration depends on CONFB register status
6.2 STATUS register (addr 0x01)
D7
FAULT
NA
D6
DRCCRC
NA
D5
EQCRC
NA
D4
BADPWM
NA
D3
Reserved
NA
D2
Reserved
NA
D1
I2SERR
NA
D0
PLLUL
NA
Bit R/W RST
Table 16. STATUS register
Name Description
7
6
5
4
1
0
R
R
R
R
R
R
FAULT
(1)
DRCCRC
EQCRC
BADPWM
I2SERR
PLLUL
0 = the power bridge is in fault condition
1 = the power bridge is in normal condition
0 = normal operation
1 = CRC error on DRC BIQUADS
0 = normal operation
1 = CRC error on BIQUADS
0 = normal operation
1 = PWM outputs are invalid
0 = normal operation
1 = SAI interface error detected (see
Configuration register B (addr 0x12)
)
0 = PLL is locked
1 = PLL is not locked
1. Fault status is set to 1 once the power bridge goes to tri-state mode.
48/174 DocID018835 Rev 8
STA381BW
6.3 RESET register (addr 0x02)
D7
Reserved
0
D6
Reserved
0
D5
Reserved
0
D4
Reserved
0
D3
Reserved
0
Register description: New Map
D2
Reserved
0
D1
Reserved
0
D0
SRESET
0
Bit
0
R/W
R/W
RST
0
Table 17. RESET register
Name
SRESET
0: normal operation
1: reset the device
Description
6.4
After SRESET is written, the last IC acknowledge is skipped and the EAPD bit (reg 0x16 bit
D7) is set to 1 instead of the 0 default value obtained after hardware reset.
Soft volume register (addr 0x03)
D1
SVOL[1:0]
D0
0 1
D7
Reserved
0
D6
Reserved
0
D5
Reserved
0
D4
Reserved
0
D3
Reserved
0
D2
Reserved
0
Bit
1
0
R/W
R/W
R/W
RST
Table 18. Soft volume register
Name Description
SVOL[1:0]
00: 30 ms
01: 100 ms (default)
10: 100 ms
11: Soft-mute disabled
Values are specified for fs = 48 kHz, 96 kHz or 192 kHz.
DocID018835 Rev 8 49/174
Register description: New Map
6.5 MVOL register (addr 0x04)
6.6
STA381BW
D7
0
D6
0
D5
0
D4
MVOL[7:0]
D3
0 0
D2
0
D1
0
Bit R/W RST
Table 19. Master volume register
Name Description
1
0
3
2
5
4
7
6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
MVOL[7:0]
0x00: Hard mute (immediate switchoff)
0x01: Mute
0x02: Mute (PWM on)
0x03: Mute (PWM on) others: volume = [(MVOL-255)/2] dB
(1)
1. If the volume is below -60 dB, the level will be approximated to 1 dB step.
D0
0
FINEVOL register (addr 0x05)
D1
FINE[1:0]
D0
0 0
D7
Reserved
0
D6
Reserved
0
D5
Reserved
0
D4
Reserved
0
D3
Reserved
0
D2
Reserved
0
Bit
1
0
R/W
R/W
R/W
RST
Table 20. Fine volume register
Name Description
FINE[1:0]
00 = 0 dB
01 = -0.125 dB
10 = -0.25 dB
11 = -0.375 dB
50/174 DocID018835 Rev 8
STA381BW
6.7 CH1VOL register (addr 0x06)
6.8
Register description: New Map
D7
1
D6
0
D5
0
D4
CH1VOL[7:0]
D3
1 1
D2
1
D1
1
Bit R/W RST
Table 21. Channel 1 volume register
Name Description
2
1
4
3
0
7
6
5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
0
1
1
1
1
1
CH1VOL[7:0]
0x00: mute others: volume = [(CH1VOL-159)/2] dB
1. If the volume is below -60 dB, the level will be approximated to 1 dB step.
(1)
D0
1
CH2VOL register (addr 0x07)
D7
1
D6
0
D5
0
D4
CH2VOL[7:0]
D3
1 1
D2
1
D1
1
Bit R/W RST
Table 22. Channel 2 volume register
Name Description
1
0
3
2
5
4
7
6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
0
1
1
1
1
1
CH2VOL[7:0]
0x00: mute others: volume = [(CH2VOL-159)/2] dB
1. If the volume is below -60 dB, the level will be approximated to 1 dB step.
(1)
D0
1
DocID018835 Rev 8 51/174
Register description: New Map
6.9 POST scaler register (addr 0x08)
D7 D6 D5 D4 D3
POST[7:0]
1 0 0 0 0
Post scaler is set to POST/128 for both CH1 and CH2.
D2
0
D1
0
STA381BW
6.10 OPER register (addr 0x09)
D7
Reserved
0
Bit
1
0
R/W
R/W
R/W
D6
Reserved
0
RST
0
0
D5
Reserved
0
D4
Reserved
0
D3
Reserved
0
Table 23. OPER register
Name Description
D2
Reserved
0
OPER[1:0] output configuration modes
D1
OPER[1:0]
D0
0 0
OPER[1:0]
00
11
10
01
Table 24. OPER configuration selection
Output configuration
2-channel (full-bridge) power, 2-channel data-out:
1A/1B 1A/1B
2A/2B 2A/2B
LineOut1 3A/3B
LineOut2 4A/4B
Line out configuration determined by LOC register
2-channel (full-bridge) power, 1-channel FFX:
1A/1B 1A/1B
2A/2B 2A/2B
3A/3B 3A/3B
EAPDEXT and TWARNEXT Active
2(half-bridge).1(full-bridge) on-board power:
1A 1A Binary 0°
2A 1B Binary 90°
3A/3B 2A/2B Binary 45°
1A/B 3A/B Binary 0°
2A/B 4A/B Binary 90°
1 channel mono-parallel:
3A 1A/1B w/ C3BO 45°
3B 2A/2B w/ C3BO 45°
1A/1B 3A/3B
2A/2B 4A/4B
CH3 downmixed on all the PWM channels.
PBTL enable
No
Yes
No
No
D0
0
52/174 DocID018835 Rev 8
STA381BW Register description: New Map
Figure 18. OPER = 00 (default value)
Figure 19. OPER = 11
Figure 20. OPER = 10
DocID018835 Rev 8 53/174
Register description: New Map
Figure 21. OPER = 01
STA381BW
The STA381BW can be configured to support different output configurations. For each
PWM output channel, a PWM slot is defined. A PWM slot is always 1 / (8 * fs) seconds length. The PWM slot defines the maximum extension for the PWM rising and falling edge, that is, the rising edge as well as the falling edge cannot range outside the PWM slot boundaries.
Figure 22. Output mapping scheme
54/174 DocID018835 Rev 8
STA381BW Register description: New Map
For each configuration the PWM signals from the digital driver are mapped in different ways to the power stage.
2.0 channels, two full-bridges (
OPER
= 00)
FFX1A -> OUT1A
FFX1B -> OUT1B
FFX2A -> OUT2A
FFX2B -> OUT2B
FFX3A -> OUT3A
FFX3B -> OUT3B
FFX4A -> OUT4A
FFX4B -> OUT4B
FFX1A/1B configured as ternary
FFX2A/2B configured as ternary
FFX3A/3B configured as line out ternary
FFX4A/4B configured as line out ternary
On channel 3 line out (LOC bits = 00, reg 0x17 bit D7,D6) the same data as channel 1 processing is sent. On channel 4 line out (LOC bits = 00) the same data as channel 2 processing is sent. In this configuration, neither volume control nor EQ has any effect on channels 3 and 4.
In this configuration the PWM slot phase is the following as shown in
Figure 23. 2.0 channels (OPER = 00) PWM slots
DocID018835 Rev 8 55/174
Register description: New Map STA381BW
2.1 channels, two half-bridges + one full-bridge (
OPER
= 11)
FFX1A -> OUT1A
FFX2A -> OUT1B
FFX3A -> OUT2A
FFX3B -> OUT2B
FFX1A -> OUT3A
FFX1B -> OUT3B
FFX2A -> OUT4A
FFX2B -> OUT4B
FFX1A/1B configured as binary
FFX2A/2B configured as binary
FFX3A/3B configured as binary
FFX4A/4B is not used
In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT3/OUT4 channels, channel 1 and channel 2 PWM are replicated.
In this configuration the PWM slot phase is the following as shown in
Figure 24. 2.1 channels (OPER = 11) PWM slots
56/174 DocID018835 Rev 8
STA381BW Register description: New Map
2.1 channels, two full-bridges + one external full-bridge (
OPER
= 10)
FFX1A -> OUT1A
FFX1B -> OUT1B
FFX2A -> OUT2A
FFX2B -> OUT2B
FFX3A -> OUT3A
FFX3B -> OUT3B
EAPD -> OUT4A
TWARN -> OUT4B
FFX1A/1B configured as ternary
FFX2A/2B configured as ternary
FFX3A/3B configured as ternary
FFX4A/4B is not used
In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT4 channel the external bridge control signals are muxed.
In this configuration the PWM slot phase is the following as shown in
Figure 25. 2.1 channels (OPER = 10) PWM slots
DocID018835 Rev 8 57/174
Register description: New Map STA381BW
6.11 FUNCT register (addr 0x0A)
D7
Reserved
0
Bit
6
5
4
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
D6
CRC
0
RST
0
1
0
0
0
0
D5
APEQ
1
D4
PEQ
0
D3
Reserved
0
D2
AMDRC
0
D1
MDRCE
0
D0
DRC
0
Table 25. FUNCT register
Name Description
CRC
APEQ
PEQ
AMDRC
MDRCE
DRC
0: disable CRC computation and comparison
1: enable CRC computation and comparison
0: extended BQ disabled, 8th biquadratic filter disabled
1: extended BQ enabled, 8th biquadratic filter enabled
0: Normal operation
1: PEQ disabled, disables all biquadratic filters
0: STCompressor bypassed
1: STCompressor enabled
0: MDRCE bypassed
1: MDRCE enabled
0: DRC disabled
1: DRC enabled
The STA381BW device provides a dual-band DRC (B 2 DRC) on the left and right channels data path, as depicted in
. Dual-band DRC is activated by setting MDRCE = 1.
Figure 26. B 2 DRC scheme
Channel 3
Volume
DRC 2
L
B 2 DRC
Hi-pass XO filter
-
+
Channel 1
Volume
DRC 1 +
R
B 2 DRC
Hi-pass XO filter
- +
Channel 2
Volume
DRC 1
58/174
Channel 3
Volume
DRC 2 +
The low-frequency information (LFE) is extracted from the left and right channels, removing the high frequencies using a programmable biquad filter, and then computing the difference
DocID018835 Rev 8
STA381BW Register description: New Map with the original signal. Limiter 1 (DRC1) is then used to control the amplitude of the left/right high-frequency components, while limiter 2 (DRC2) is used to control the low-frequency
components (see Section 6.23: Dynamic control registers (addr 0x23 - 0x26 / addr 0x43 -
The cutoff frequency of the high-pass filters can be user-defined, XO[3:0] = 0, or selected from the pre-defined values.
DRC1 and DRC2 are then used to independently limit L/R high frequencies and LFE
channel amplitude (see Section 6.23: Dynamic control registers (addr 0x23 - 0x26 / addr
0x43 - 0x46) ) as well as their volume control. To be noted that, in this configuration, the
dedicated channel 3 volume control can actually act as a bass boost enhancer as well (0.5 dB/step resolution).
The processed LFE channel is then recombined with the L and R channels in order to reconstruct the 2.0 output signal.
Sub-band decomposition
The sub-band decomposition for B 2 DRC can be configured specifying the cutoff frequency.
The cutoff frequency can be programmed in two ways, using the XO bits in register 0x0C, or using the “user programmable” mode (coefficients stored in RAM addresses 0x28 to 0x31).
For the user-programmable mode, use the formulas below to compute the high-pass filters: b0 = (1 + alpha) / 2 b1 = -(1 + alpha) / 2 a0 = 1 a1 = -alpha b2 = 0 a2 = 0 where alpha = (1-sin(
0
))/cos(
0
), and
0
is the cutoff frequency.
A first-order filter is recommended to guarantee that for every
0
the corresponding low-pass filter obtained as difference (as shown in
Figure 26 ) will have a symmetric (relative
to the HP filter) frequency response, and the corresponding recombination after the DRC has low ripple. Second-order filters can be used as well, but in this case the filter shape must be carefully chosen to provide good low-pass response and minimum ripple recombination. For second-order filters, it is not possible to give a closed formula to get the best coefficients, but empirical adjustment should be done.
DRC settings
The DRC blocks used by B 2 DRC are the same as those described in
Section 6.23: Dynamic control registers (addr 0x23 - 0x26 / addr 0x43 - 0x46) . B
2 DRC configure automatically the
DRC blocks in anticlipping mode. Attack and release thresholds can be selected using registers 0x32, 0x33, 0x34, 0x35, while attack and release rates are configured by registers
0x12 and 0x14.
Band downmixing
The low-frequency band is down-mixed to the left and right channels at the B 2 DRC output.
Channel volume can be used to weight the bands recombination to fine-tune the overall frequency response.
DocID018835 Rev 8 59/174
Register description: New Map
6.12 HPCFG register (addr 0x10)
STA381BW
D7
Reserved
0
D6
Reserved
0
D5
Reserved
0
D4
Reserved
0
D3
Reserved
0
D2
Reserved
0
D1
Reserved
0
Bit
0
R/W
R/W
RST
1
Table 26. HPCFG register
Name Description
MUTE
0: HP/Line out is ON
1: HP/LIne out is muted
D0
MUTE
1
6.13 Configuration register A (addr 0x11)
D7
FDRB
0
D6
Reserved
1
D5
Reserved
1
D4
IR1
0
D3
IR0
0
6.13.1 Master clock select
Bit
0
1
2
R/W
R/W
R/W
R/W
RST
1
1
1
D2
MCS2
1
D1
MCS1
1
D0
MCS0
1
Table 27. Master clock select
Name Description
MCS0
MCS1
MCS2
Selects the ratio between the input I
2
S sampling frequency and the input clock.
The STA381BW supports sampling rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,
176.4 kHz, and 192 kHz. Therefore the internal clock is:
32.768 MHz for 32 kHz
45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz
49.152 MHz for 48 kHz, 96 kHz, and 192 kHz
The external clock frequency provided to the XTI pin or BICKI pin (depending on the MCS settings) must be a multiple of the input sampling frequency (f s
).
The relationship between the input clock (either XTI or BICKI) and the input sampling rate is determined by both the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio
MCS 111 and 110 indicate that BICKI has to be used as the clock source, while XTI is used in all the other cases.
60/174 DocID018835 Rev 8
STA381BW Register description: New Map
Table 28. Input sampling rates
Input sampling rate fs (kHz)
IR
32, 44.1, 48
88.2, 96
176.4, 192
MCS[2:0]
111 110 101 100 011 010 001 000
00 64*fs(*) NA
01 64*fs(*) 32*fs(*)
1X 64*fs(*) 32*fs(*)
576 * fs 128 * fs 256 * fs 384 * fs 512 * fs 768 * fs
NA 64 * fs 128 * fs 192 * fs 256 * fs 384 * fs
NA 32 * fs 64 * fs 96 * fs 128 * fs 192 * fs
Note: (*): Clock is BICKI
6.13.2 Interpolation ratio selection
Bit
4:3
R/W
R/W
RST
00
Table 29. Internal interpolation ratio
Name
IR [1:0]
Description
Selects internal interpolation ratio based on input I
2
S sampling frequency
The STA381BW has variable interpolation (oversampling) settings such that internal processing and FFX output rates remain consistent. The first processing block interpolates
by either 3 times ( Table 83: PLL register 0x56 bits D0), 2 times or 1 time (pass-through) or
provides a 2-times downsample. The oversampling ratio of this interpolation is determined by the IR bits.
Table 30. IR bit settings as a function of the input sampling rate
Input sampling rate fs (kHz) IR 1st stage interpolation ratio
32
44.1
48
88.2
96
176.4
192
01
01
10
10
00
00
00
2-times oversampling
2-times oversampling
2-times oversampling
Pass-through
Pass-through
2-times downsampling
2-times downsampling
6.13.3 Fault-detect recovery bypass
Bit
7
R/W
R/W
RST
0
Table 31. Fault-detect recovery bypass
Name Description
FDRB
0: fault-detect recovery enabled
1: fault-detect recovery disabled
DocID018835 Rev 8 61/174
Register description: New Map STA381BW
The on-chip STA381BW power output block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition
(either overcurrent or thermal). When FAULT is asserted (set to 0), the power control block attempts a recovery from the fault by asserting the tri-state output (setting it to 0 which directs the power output block to begin recovery), holds it at 0 for period of time in the range of 0.1 ms to 1 second as defined by the fault-detect recovery constant register (FDRC registers 0x3C-0x3D), then toggles it back to 1. This sequence is repeated as long as the fault indication exists. This feature is enabled by default but can be bypassed by setting the
FDRB control bit to 1.
6.14 Configuration register B (addr 0x12)
D7
C2IM
1
D6
C1IM
0
D5
DSCKE
0
D4
SAIFB
0
D3
SAI3
0
D2
SAI2
0
D1
SAI1
0
D0
SAI0
0
6.14.1 Serial data interface
The STA381BW audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. The STA381BW always acts as the slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and serial data 1 and 2 SDI12.
The SAI bits (D3 to D0) and the SAIFB bit (D4) are used to specify the serial data format.
The default serial data format is I 2 S, MSB-first. Available formats are shown in the tables that follow.
62/174 DocID018835 Rev 8
STA381BW
6.14.2 Serial data first bit
SAIFB
0
1
Register description: New Map
Table 32. Serial data first bit
Format
MSB-first
LSB-first
Table 33. Support serial audio input formats for MSB-first (SAIFB = 0)
BICKI SAI [3:0] SAIFB Interface format
32 * fs
48 * fs
64 * fs
0000
0001
0010
0110
1010
1110
0000
0001
0000
0001
0010
0110
1010
1110
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I
2
S 15-bit data
Left/right-justified 16-bit data
I
2
S 16- to 23-bit data
Left-justified 16- to 24-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
I
2
S 16- to 24-bit data
Left-justified 16- to 24-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
DocID018835 Rev 8 63/174
Register description: New Map STA381BW
Table 34. Supported serial audio input formats for LSB-first (SAIFB = 1)
BICKI SAI [3:0] SAIFB Interface format
I
2
S 15-bit data
32 * fs
1100 1
1110
0100
0100
1000
1100
0001
1
1
1
1
1
1
Left/right-justified 16-bit data
I
2
S 23-bit data
I
2
S 20-bit data
I
2
S 18-bit data
LSB first I
2
S 16-bit data
Left-justified 24-bit data
48 * fs
64 * fs
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0100
1000
1100
0001
0101
1001
1101
0010
0101
1001
1101
0010
0110
1010
1110
0000
0110
1010
1110
Left-justified 20-bit data
Left-justified 18-bit data
Left-justified 16-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
I
2
S 24-bit data
I
2
S 20-bit data
I
2
S 18-bit data
LSB first I
2
S 16-bit data
Left-justified 24-bit data
Left-justified 20-bit data
Left-justified 18-bit data
Left-justified 16-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
To make the STA381BW work properly, the serial audio interface LRCKI clock must be synchronous to the PLL output clock. It means that:
the frequency of PLL clock / frequency of LRCKI = N ±4 cycles, where N depends on the settings in
the PLL must be locked.
If these two conditions are not met, and the IDE bit (reg 0x05 bit 2) is set to 1, the
STA381BW will immediately mute the I
2
S PCM data out (provided to the processing block) and it will freeze any active processing task.
64/174 DocID018835 Rev 8
STA381BW Register description: New Map
Note:
To avoid any audio side effects (like pop noise), it is strongly recommended to soft mute any audio streams flowing into the STA381BW data path before the desynchronization event happens. At the same time any processing related to the I 2 C configuration should be issued only after the serial audio interface and the internal PLL are synchronous again.
Any mute or volume change causes some delay in the completion of the I 2 C operation due to the soft volume feature. The soft volume phase change must be finished before any clock desynchronization.
6.14.3 Delay serial clock enable
Bit
5
R/W
R/W
RST
0
Table 35. Delay serial clock enable
Name Description
DSCKE
0: No serial clock delay
1: Serial clock delay by 1 core clock cycle to tolerate anomalies in some I
2
S master devices
6.14.4 Channel input mapping
Bit
6
7
R/W
R/W
R/W
RST
0
1
Table 36. Channel input mapping
Name
C1IM
C2IM
Description
0: Processing channel 1 receives left I
2
1: Processing channel 1 receives right I
S input
2
S input
0: Processing channel 2 receives left I
2
1: Processing channel 2 receives right I
S input
2
S input
Each channel received via I
2
S can be mapped to any internal processing channel via the channel input mapping registers. This allows for flexibility in processing. The default settings of these registers map each I
2
S input channel to its corresponding processing channel.
6.15 Configuration register C (addr 0x13)
D7
Reserved
1
D6
Reserved
0
D5
CSZ3
0
D4
CSZ2
1
D3
CSZ1
0
D2
CSZ0
1
D1
Reserved
1
D0
Reserved
1
6.15.1 FFX compensating pulse size register
Bit
4
5
2
3
R/W
R/W
R/W
R/W
R/W
RST
Table 37. FFX compensating pulse size bits
Name Description
1
0
1
1
CSZ0
CSZ1
CSZ2
CSZ3
When OM[1,0] = 11, this register determines the size of the FFX compensating pulse from 0 clock ticks to
15 clock periods.
DocID018835 Rev 8 65/174
Register description: New Map
CSZ[3:0]
0000
0001
…
1111
Table 38. Compensating pulse size
Compensating pulse size
0 ns (0 ticks) compensating pulse size
20 ns (1 tick) clock period compensating pulse size
…
300 ns (15 ticks) clock period compensating pulse size
6.16 Configuration register D (addr 0x14)
D7
SME
0
D6
ZDE
0
D5
Reserved
0
D4
BQL
1
D3
PSL
1
STA381BW
D2
DSPB
0
D1
Reserved
0
D0
Reserved
0
Bit
2
R/W
R/W
RST
0
Table 39. DSP bypass
Name
DSPB
Description
0: Normal operation
1: Bypass of biquad and bass/treble functions
Setting the DSPB bit bypasses the EQ function of the STA381BW.
Bit
3
R/W
R/W
RST
1
Table 40. Post-scale link
Name
PSL
Description
0: Each channel uses individual post-scale values
1: Each channel uses channel 1 post-scale values
Post-scale functionality can be used for power-supply error correction. For multi-channel applications running off the same power supply, the post-scale values can be linked to the value of channel 1 for ease of use and in order to update the values faster.
6.16.3 Biquad coefficient link
Bit
4
R/W
R/W
RST
1
Table 41. Biquad coefficient link
Name Description
BQL
0: Each channel uses coefficient values
1: Each channel uses channel 1 coefficient values
For ease of use, all channels can use the biquad coefficients loaded into the channel 1 coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to be performed once.
66/174 DocID018835 Rev 8
STA381BW Register description: New Map
6.16.4 Zero-detect mute enable
Bit
6
R/W
R/W
RST
0
Table 42. Zero-detect mute enable
Name Description
ZDE
Setting of 1 enables the automatic zero-detect mute
Setting of 0 disables the automatic zero-detect mute
Refer to 6.32: Enhanced zero-detect mute and input level measurement (address 0x61-
6.16.5 Submix mode enable
Bit
7
R/W
R/W
RST
0
Table 43. Submix mode enable
Name Description
SME
0: Submix into left/right disabled
1: Submix into left/right enabled
6.17 Configuration register E (addr 0x15)
D7
Reserved
1
D6
ZCE
0
D5
Reserved
0
D4
PWMS
0
D3
AME
0
D2
NSBW
0
6.17.1 Noise-shaper bandwidth selection
Bit
2
R/W
R/W
RST
0
Table 44. Noise-shaper bandwidth selection
Name Description
NSBW
1: Third order NS
0: Fourth order NS
D1
Reserved
1
D0
Reserved
0
6.17.2 AM mode enable
Bit
3
R/W
R/W
RST
0
Table 45. AM mode enable
Name Description
AME
0: Normal FFX operation
1: AM reduction mode FFX operation
The STA381BW features an FFX processing mode that minimizes the amount of noise generated in the frequency range of AM radio. This mode is intended for use when FFX is operating in a device with an active AM tuner. The SNR of the FFX processing is reduced to approximately 83 dB in this mode, which is still greater than the SNR of AM radio.
DocID018835 Rev 8 67/174
Register description: New Map STA381BW
6.17.3 PWM speed mode
Bit R/W RST
4 R/W 0
Table 46. PWM speed mode
Name Description
PWMS
0: Normal speed (384 kHz) all channels
1: Odd speed (341.3 kHz) all channels. Not suitable for binary BTL mode.
Bit
6
R/W
R/W
RST
0
Table 47. Zero-crossing enable
Name Description
ZCE
1: Volume adjustment only occurs at digital zero-crossing
0: Volume adjustment occur immediately
The ZCE bit enables zero-crossing adjustment. When volume is adjusted on digital zerocrossing, no clicks are audible
6.18 Configuration register F (addr 0x16)
D7
EAPD
0
D6
PWDN
1
D5
Reserved
0
D4
LDTE
1
D3
BCLE
1
D2
IDE
1
D1
Reserved
D0
Reserved
6.18.1 Invalid input detect mute enable
Bit
2
R/W
R/W
RST
Table 48. Invalid input detect mute enable
Name Description
1 IDE
Setting of 1 enables the automatic invalid input detect mute
Setting the IDE bit enables this function, which looks at the input I 2 S data and automatically mutes if the signals are perceived as invalid.
6.18.2 Binary output mode clock loss detection
Bit
3
R/W
R/W
Table 49. Binary output mode clock loss detection
RST Name Description
1 BCLE Binary output mode clock loss detection enable
This bit detects loss of input MCLK in binary mode and will output 50% duty cycle.
68/174 DocID018835 Rev 8
STA381BW Register description: New Map
6.18.3 LRCK double trigger protection
Bit
4
R/W
R/W
RST
Table 50. LRCK double trigger protection
Name Description
1 LDTE LRCLK double trigger protection enable
This bit actively prevents double triggering of LRCLK.
6.18.4 Power-down
Bit
7
R/W
R/W
RST
1
Table 51. IC power-down
Name
PWDN
Description
0: IC power-down low-power condition
1: IC normal operation
The PWDN register is used to place the IC in a low-power state. When PWDN is written as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted
I to power down the power stage, then the master clock to all internal hardware except the
2
C block is gated. This places the IC in a very low power consumption state.The register state is preserved once the device recovers from power-down.
6.18.5 External amplifier power-down
Bit
7
R/W
R/W
RST
0
Table 52. External amplifier power-down
Name Description
EAPD
0: External power stage power-down active
1: Normal operation
The EAPD register directly disables/enables the internal power circuitry.
When EAPD = 0, the internal power section is placed in a low-power state (disabled). This register also controls the EAPD/FFX4B output pin when OCFG = 11.
6.19 Volume control registers (addr 0x17 - 0x1B)
6.19.1 Mute/line output configuration register (addr 0x17)
D7
LOC1
0
D6
LOC0
0
D5
Reserved
0
D4
Reserved
0
D3
C3M
0
D2
C2M
0
D1
C1M
0
D0
MMUTE
0
DocID018835 Rev 8 69/174
Register description: New Map STA381BW
LOC[1:0]
00
01
10
11
Table 53. Line output configuration
Line output configuration
Line output fixed - no volume, no EQ
Line output variable - CH3 volume effects line output, no EQ
Line output variable with EQ - CH3 volume effects line output
Reserved
Line output is only active when OCFG = 00. In this case LOC determines the line output configuration. The source of the line output is always the channel 1 and 2 inputs.
Bit
3
2
1
0
R/W
R/W
R/W
R/W
R/W
RST
0
0
0
0
Table 54. Mute configuration
Name Description
C3M
C2M
C1M
MMUTE
Channel 3 mute
0 - No mute condition. It is possible to set the channel volume
1 - Channel 3 in hardware mute
Channel 2 mute
0 - No mute condition. It is possible to set the channel volume
1 - Channel 2 in hardware mute
Channel 1 mute
0 - No mute condition. It is possible to set the channel volume
1 - Channel 1 in hardware mute
Master mute
0 - Normal operation
1 - All channels are in mute condition
70/174 DocID018835 Rev 8
STA381BW Register description: New Map
6.19.2 Channel 3 / line output volume (addr 0x1B)
D7 D6 D5 D4 D3 D2 D1 D0
CH3VOL
0 1 1 0 0 0 0 0
The volume structure of the STA381BW consists of individual volume registers for each channel and a master volume register that provides an offset to each channel’s volume setting. The individual channel volumes are adjustable in 0.5 dB steps from +48 dB to
-80 dB.
As an example, if CH3VOL = 0x00 or +48 dB and MVOL= -12 dB, then the total gain for channel 3 = +36 dB.
The master mute, when set to 1, mutes all channels at once, whereas the individual channel mute (CxM) mutes only that channel. Both the master mute and the channel mutes provide a “soft mute” with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (approximately 96 kHz).
A “hard (instantaneous) mute” can be obtained by programming a value of 0xFF (255) to any channel volume register or the master volume register. When volume offsets are provided via the master volume register, any channel whose total volume is less than -80 dB is muted.
All changes in volume take place at zero-crossings when ZCE = 1 (
Configuration register E (addr 0x15) ) on a per-channel basis as this creates the smoothest
possible volume transitions. When ZCE = 0, volume updates occur immediately.
Table 55. Channel 3 volume as a function of CH3VOL[7:0]
CH3VOL[7:0] Volume
00000000 (0x00)
00000001 (0x01)
00000010 (0x02)
…
01011111 (0x5F)
01100000 (0x60)
01100001 (0x61)
…
11010111 (0xD7)
11011000 (0xD8)
11011001 (0xD9)
11011010 (0xDA)
…
11101100 (0xEC)
11101101 (0xED)
…
11111111 (0xFF)
+48 dB
+47.5 dB
+47 dB
…
+0.5 dB
0 dB
-0.5 dB
…
-59.5 dB
-60 dB
-61 dB
-62 dB
…
-80 dB
Hard channel mute
…
Hard channel mute
DocID018835 Rev 8 71/174
Register description: New Map STA381BW
6.20 Audio preset registers (0x1D)
D7
XO3
0
D6
XO2
0
D5
XO1
0
D4
XO0
0
D3
AMAM2
0
D2
AMAM1
0
D1
AMAM0
0
D0
AMAME
0
6.20.1 AM interference frequency switching
Bit
0
R/W
R/W
Table 56. AM interference frequency switching bits
RST Name Description
0 AMAME
Audio preset AM enable
0: switching frequency determined by PWMS setting
1: switching frequency determined by AMAM settings
Table 57. Audio preset AM switching frequency selection
AMAM[2:0] 48 kHz/96 kHz input fs 44.1 kHz/88.2 kHz input fs
000
001
010
011
100
101
110
0.535 MHz - 0.720 MHz
0.721 MHz - 0.900 MHz
0.901 MHz - 1.100 MHz
1.101 MHz - 1.300 MHz
1.301 MHz - 1.480 MHz
1.481 MHz - 1.600 MHz
1.601 MHz - 1.700 MHz
0.535 MHz - 0.670 MHz
0.671 MHz - 0.800 MHz
0.801 MHz - 1.000 MHz
1.001 MHz - 1.180 MHz
1.181 MHz - 1.340 MHz
1.341 MHz - 1.500 MHz
1.501 MHz - 1.700 MHz
6.20.2 Bass management crossover
Bit
4
5
6
7
R/W
R/W
R/W
R/W
R/W
RST
0
0
0
0
Table 58. Bass management crossover
Name Description
XO0
XO1
XO2
XO3
Selects the bass management crossover frequency.
A 1 st
-order high-pass filter (channels 1 and 2) or a
2 nd
-order low-pass filter (channel 3) at the selected frequency is performed.
72/174 DocID018835 Rev 8
STA381BW Register description: New Map
0000
1001
1010
1011
1100
1101
1110
1111
0001
0010
0011
0100
0101
0110
0111
1000
XO[3:0]
Table 59. Bass management crossover frequency
Crossover frequency
200 Hz
220 Hz
240 Hz
260 Hz
280 Hz
300 Hz
320 Hz
340 Hz
360 Hz
Table 73.: RAM block for biquads, mixing, scaling and bass management
80 Hz
100 Hz
120 Hz
140 Hz
160 Hz
180 Hz
6.21 Channel configuration registers (addr 0x1F - 0x21)
D7
Reserved
0
D7
Reserved
0
D7
C3OM1
1
D6
Reserved
0
D6
Reserved
1
D6
C3OM0
0
D5
Reserved
0
D5
Reserved
0
D5
C3LS1
0
D4
Reserved
0
D4
Reserved
0
D4
C3LS0
0
D3
C1BO
0
D3
C2BO
0
D3
C3BO
0
D2
C1VPB
0
D2
C2VPB
0
D2
C3VPB
0
D1
C1EQBP
0
D1
C2EQBP
0
D1
Reserved
0
D0
C1TCB
0
D0
C2TCB
0
D0
Reserved
0
6.21.1 Tone control bypass
Tone control (bass/treble) can be bypassed on a per-channel basis for channels 1 and 2.
CxTCB
0
1
Table 60. Tone control bypass
Mode
Perform tone control on channel x - normal operation
Bypass tone control on channel x
DocID018835 Rev 8 73/174
Register description: New Map STA381BW
EQ control can be bypassed on a per-channel basis for channels 1 and 2. If EQ control is bypassed on a given channel, the prescale and all filters (biquads, bass, treble in any combination) are bypassed for that channel.
CxEQBP
0
1
Table 61. EQ bypass
Mode
Perform EQ on channel x - normal operation
Bypass EQ on channel x
Each channel contains an individual channel volume bypass. If a particular channel has volume bypassed via the CxVBP = 1 register, then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel.
CxVBP
0
1
Table 62. Volume bypass register
Mode
Normal volume operations
Volume is bypassed
6.21.4 Binary output enable registers
Each individual channel output can be set to output a binary PWM stream. In this mode output A of a channel is considered the positive output and output B is the negative inverse.
CxBO
0
1
Table 63. Binary output enable registers
Mode
FFX 3-state output - normal operation
Binary output
74/174
Limiter selection can be made on a per-channel basis according to the channel limiter select bits. CxLS bits are not considered in case of dual-band DRC (
Section 6.26.1: Extended post-scale range
) usage.
Table 64. Channel limiter mapping as a function of C3LS bits
C3LS[1:0] Channel limiter mapping
00
01
10
Channel has limiting disabled
Channel is mapped to limiter #1
Channel is mapped to limiter #2
DocID018835 Rev 8
STA381BW Register description: New Map
Output mapping can be performed on a per-channel basis according to the CxOM channel output mapping bits. Each input into the output configuration engine can receive data from any of the three processing channel outputs.
.
Table 65. Channel output mapping as a function of C3OM bits
C3OM[1:0] Channel x output source from
00
01
10
Channel1
Channel 2
Channel 3
6.22 Tone control register (addr 0x22)
D7
TTC3
0
D6
TTC2
1
D5
TTC1
1
D4
TTC0
1
D3
BTC3
0
D2
BTC2
1
D1
BTC1
1
D0
BTC0
1
Table 66. Tone control boost/cut as a function of BTC and TTC bits
BTC[3:0]/TTC[3:0] Boost/cut
0000
0001
…
0111
0110
0111
1000
1001
…
1101
1110
1111
-12 dB
-12 dB
…
-4 dB
-2 dB
0 dB
+2 dB
+4 dB
…
+12 dB
+12 dB
+12 dB
DocID018835 Rev 8 75/174
Register description: New Map STA381BW
6.23 Dynamic control registers (addr 0x23 - 0x26 / addr 0x43 -
0x46)
6.23.1 Limiter 1 attack/release rate (L1AR addr 0x23)
D7
L1A3
0
D6
L1A2
1
D5
L1A1
1
D4
L1A0
0
D3
L1R3
1
D2
L1R2
0
D1
L1R1
1
D0
L1R0
0
6.23.2 Limiter 1 attack/release threshold (L1ATRT addr 0x24)
D7
L1AT3
0
D6
L1AT2
1
D5
L1AT1
1
D4
L1AT0
0
D3
L1RT3
1
D2
L1RT2
0
D1
L1RT1
0
6.23.3 Limiter 2 attack/release rate ( L2AR addr 0x25)
D7
L2A3
0
D6
L2A2
1
D5
L2A1
1
D4
L2A0
0
D3
L2R3
1
D2
L2R2
0
D1
L2R1
1
D0
L1RT0
1
D0
L2R0
0
6.23.4 Limiter 2 attack/release threshold ( L2 ATRT addr 0x26)
D7
L2AT3
0
D6
L2AT2
1
D5
L2AT1
1
D4
L2AT0
0
D3
L2RT3
1
D2
L2RT2
0
D1
L2RT1
0
D0
L2RT0
1
The STA381BW includes two independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anticlipping mode or to actively reduce the dynamic range for a better listening environment such as a nighttime listening mode which is often needed for DVDs. The two modes are selected via the DRC bit in
Section 6.11: FUNCT register (addr 0x0A)
. Each channel can be mapped to either limiter or not mapped, meaning that the channel will clip when 0 dBfs is exceeded. Each limiter looks at the present value of each channel that is mapped to it, selects the maximum absolute value of all these channels, performs the limiting algorithm on that value, and then, if needed, adjusts the gain of the mapped channels in unison.
The limiter attack thresholds are determined by the LxAT registers if the EATHx[7] (bit D7 of register 0x43 or 0x45) bits are set to 0, else the thresholds are determined by EATHx[6:0]. It is recommended in anticlipping mode to set this to 0 dBfs, which corresponds to the maximum unclipped output power of an FFX amplifier. Since gain can be added digitally within the STA381BW it is possible to exceed 0 dBfs or any other LxAT setting. When this occurs, the limiter, when active, automatically starts reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. Gain reduction occurs on a peak-detect algorithm. Setting the
EATHx[7] bits to 1 selects the anticlipping mode.
The limiter release thresholds are determined by the LxRT registers if the ERTHx[7] (bit D7 of register 0x44 or 0x46) bits are set to 0, else the thresholds are determined by
76/174 DocID018835 Rev 8
STA381BW Register description: New Map
ERTHx[6:0]. Setting the ERTHx[7] bits to 1 automatically selects the anticlipping mode. The release of the limiter, when the gain is again increased, is dependent on an RMS-detect algorithm. The output of the volume/limiter block is passed through an RMS filter. The output of this filter is compared to the release threshold, determined by the release threshold register. When the RMS filter output falls below the release threshold, the gain is again increased at a rate dependent upon the release rate register. The gain can never be increased past its set value and, therefore, the release only occurs if the limiter has already reduced the gain. The release threshold value can be used to set what is effectively a minimum dynamic range, this is helpful as overlimiting can reduce the dynamic range to virtually zero and cause program material to sound “lifeless”.
In anticlipping mode, the attack and release thresholds are set relative to full-scale. In DRC mode (bit D0 reg 0x0A set to 1), the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold.
DocID018835 Rev 8 77/174
Register description: New Map
Figure 27. Basic limiter and volume flow diagram
RMS
Limiter
STA381BW
Gain / Vo lume
+
In p ut
Gain
Table 67. Limiter attack rate as a function of LxA bits
LxA[3:0] Attack rate dB/ms
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
0.1504
0.1123
0.0902
0.0752
0.0645
0.0564
0.0501
0.0451
3.1584
2.7072
2.2560
1.8048
1.3536
0.9024
0.4512
0.2256
Fast
Slow
Atten uatio n Saturatio n
Outp ut
Table 68. Limiter release rate as a function of LxR bits
LxR[3:0] Release rate dB/ms
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
0.0198
0.0172
0.0147
0.0137
0.0134
0.0117
0.0110
0.0104
0.5116
0.1370
0.0744
0.0499
0.0360
0.0299
0.0264
0.0208
Fast
Slow
78/174 DocID018835 Rev 8
STA381BW Register description: New Map
Anticlipping mode
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
Table 69. Limiter attack threshold as a function of LxAT bits (AC mode)
LxAT[3:0] AC (dB relative to fs)
-12
-10
-8
-6
0000
0001
0010
0011
-4
-2
0100
0101
0 0110
+2 0111
+3
+4
+5
+6
1000
1001
1010
1011
+7
+8
1100
1101
+9 1110
+10 1111
Table 70. Limiter release threshold as a function of LxRT bits (AC mode)
LxRT[3:0] AC (dB relative to fs)
-29 dB
-20 dB
-16 dB
-14 dB
-12 dB
-8 dB
-7 dB
-6 dB
-5 dB
-4 dB
-3 dB
-2 dB
-0 dB
DocID018835 Rev 8 79/174
Register description: New Map
Dynamic range compression mode
Table 71. Limiter attack threshold as a function of LxAT bits (DRC mode)
LxAT[3:0] DRC (dB relative to volume)
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
-12
-10
-7
-4
-16
-15
-14
-13
-23
-21
-19
-17
-31
-29
-27
-25
STA381BW
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
Table 72. Limiter release threshold as a function of LxRT bits (DRC mode)
LxRT[3:0]
DRC (dB relative to volume +
LxAT)
-24 dB
-22 dB
-20 dB
-18 dB
-15 dB
-12 dB
-9 dB
-6 dB
-38 dB
-36 dB
-33 dB
-31 dB
-30 dB
-28 dB
-26 dB
6.23.5 Limiter 1 extended attack threshold (addr 0x43)
D7
EATHEN1
0
D6
EATH1[6]
0
D5
EATH1[5]
1
D4
EATH1[4]
1
D3
EATH1[3]
0
D2
EATH1[2]
0
The extended attack threshold value is determined as follows: attack threshold = -12 + EATH1 / 4
To enable this feature, the EATHEN1 bit must be set to 1.
6.23.6 Limiter 1 extended release threshold (addr 0x44)
D7
ERTHEN1
0
D6
ERTH1[6]
0
D5
ERTH1[5]
1
D4
ERTH1[4]
1
D3
ERTH1[3]
0
D2
ERTH1[2]
0
The extended release threshold value is determined as follows: release threshold = -12 + ERTH1 / 4
To enable this feature, the ERTHEN1 bit must be set to 1.
D1
EATH1[1]
0
D1
ERTH1[1]
0
D0
EATH1[0]
0
D0
ERTH1[0]
0
80/174 DocID018835 Rev 8
STA381BW Register description: New Map
6.23.7 Limiter 2 extended attack threshold (addr 0x45)
D7
EATHEN2
0
D6
EATH2[6]
0
D5
EATH2[5]
1
D4
EATH2[4]
1
D3
EATH2[3]
0
D2
EATH2[2]
0
The extended attack threshold value is determined as follows: attack threshold = -12 + EATH2 / 4
To enable this feature, the EATHEN2 bit must be set to 1.
D1
EATH2[1]
0
6.23.8 Limiter 2 extended release threshold (addr 0x46)
Note:
D7
ERTHEN2
0
D6
ERTH2[6]
0
D5
ERTH2[5]
1
D4
ERTH2[4]
1
D3
ERTH2[3]
0
D2
ERTH2[2]
0
The extended release threshold value is determined as follows: release threshold = -12 + ERTH2 / 4
To enable this feature, the ERTHEN2 bit must be set to 1.
Attack/release threshold step is 0.125 dB in the range -12 dB to 0 dB.
D1
ERTH2[1]
0
D0
EATH2[0]
0
D0
ERTH2[0]
0
6.24 User-defined coefficient control registers (addr 0x27 - 0x37)
6.24.1 Coefficient address register
D7
Reserved
0
D6
Reserved
0
D5
CFA5
0
D4
CFA4
0
D3
CFA3
0
D2
CFA2
0
D1
CFA1
0
D0
CFA0
0
6.24.2 Coefficient b1 data register bits 23:16
D7
C1B23
0
D6
C1B22
0
D5
C1B21
0
D4
C1B20
0
D3
C1B19
0
6.24.3 Coefficient b1 data register bits 15:8
D7
C1B15
0
D6
C1B14
0
D5
C1B13
0
D4
C1B12
0
D3
C1B11
0
6.24.4 Coefficient b1 data register bits 7:0
D7
C1B7
0
D6
C1B6
0
D5
C1B5
0
D4
C1B4
0
D3
C1B3
0
D2
C1B18
0
D2
C1B10
0
D2
C1B2
0
D1
C1B17
0
D1
C1B9
0
D1
C1B1
0
D0
C1B16
0
D0
C1B8
0
D0
C1B0
0
DocID018835 Rev 8 81/174
Register description: New Map
6.24.5 Coefficient b2 data register bits 23:16
D7
C2B23
0
D6
C2B22
0
D5
C2B21
0
D4
C2B20
0
D3
C2B19
0
6.24.6 Coefficient b2 data register bits 15:8
D7
C2B15
0
D6
C2B14
0
D5
C2B13
0
D4
C2B12
0
D3
C2B11
0
6.24.7 Coefficient b2 data register bits 7:0
D7
C2B7
0
D6
C2B6
0
D5
C2B5
0
D4
C2B4
0
D3
C2B3
0
6.24.8 Coefficient a1 data register bits 23:16
D7
C1B23
0
D6
C1B22
0
D5
C1B21
0
D4
C1B20
0
D3
C1B19
0
6.24.9 Coefficient a1 data register bits 15:8
D7
C3B15
0
D6
C3B14
0
D5
C3B13
0
D4
C3B12
0
D3
C3B11
0
6.24.10 Coefficient a1 data register bits 7:0
D7
C3B7
0
D6
C3B6
0
D5
C3B5
0
D4
C3B4
0
D3
C3B3
0
6.24.11 Coefficient a2 data register bits 23:16
D7
C4B23
0
D6
C4B22
0
D5
C4B21
0
D4
C4B20
0
D3
C4B19
0
D2
C2B18
0
D1
C2B17
0
D0
C2B16
0
D2
C2B10
0
D2
C2B2
0
D2
C3B10
0
D2
C3B2
0
D1
C2B9
0
D1
C2B1
0
D1
C3B9
0
D1
C3B1
0
STA381BW
D0
C2B8
0
D0
C2B0
0
D2
C1B18
0
D1
C1B17
0
D0
C1B16
0
D0
C3B8
0
D0
C3B0
0
D2
C4B18
0
D1
C4B17
0
D0
C4B16
0
82/174 DocID018835 Rev 8
STA381BW Register description: New Map
6.24.12 Coefficient a2 data register bits 15:8
D7
C4B15
0
D6
C4B14
0
D5
C4B13
0
D4
C4B12
0
D3
C4B11
0
6.24.13 Coefficient a2 data register bits 7:0
D7
C4B7
0
D6
C4B6
0
D5
C4B5
0
D4
C4B4
0
D3
C4B3
0
6.24.14 Coefficient b0 data register bits 23:16
D7
C5B23
0
D6
C5B22
0
D5
C5B21
0
D4
C5B20
0
D3
C5B19
0
D2
C4B10
0
D2
C4B2
0
D1
C4B9
0
D1
C4B1
0
D0
C4B8
0
D0
C4B0
0
D2
C5B18
0
D1
C5B17
0
D0
C5B16
0
6.24.15 Coefficient b0 data register bits 15:8
D7
C5B15
0
D6
C5B14
0
D5
C5B13
0
D4
C5B12
0
D3
C5B11
0
6.24.16 Coefficient b0 data register bits 7:0
D7
C5B7
0
D6
C5B6
0
D5
C5B5
0
D4
C5B4
0
D3
C5B3
0
D2
C5B10
0
D1
C5B9
0
D0
C5B8
0
D2
C5B2
0
D1
C5B1
0
D0
C5B0
0
6.24.17 Coefficient write/read control register
Note:
D7 D6
Reserved
0
D5 D4 D3
RA
0
D2
R1
0
D1
WA
0
D0
W1
0
Coefficients for user-defined EQ, mixing, scaling, and bass management are handled internally in the STA381BW via RAM. Access to this RAM is available to the user via an I 2 C register interface. A collection of I 2 C registers is dedicated to this function. One contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write/read of the coefficient(s) to/from RAM.
The read and write operation on RAM coefficients works only if the LRCKI pin is switching.
DocID018835 Rev 8 83/174
Register description: New Map
Reading a coefficient from RAM
1.
Write 6 bits of the address to I 2 C register 0x27.
2. Write 1 to the R1 bit in I
2
C address 0x37.
3. Read the top 8 bits of the coefficient in I 2 C address 0x28.
4. Read the middle 8 bits of the coefficient in I
2
C address 0x29.
5. Read the bottom 8 bits of the coefficient in I 2 C address 0x2A.
Reading a set of coefficients from RAM
1.
Write 6 bits of the address to I 2 C register 0x27.
2. Write 1 to the RA bit in I
2
C address 0x37.
3. Read the top 8 bits of the coefficient in I 2 C address 0x28.
4. Read the middle 8 bits of the coefficient in I
2
C address 0x29.
5. Read the bottom 8 bits of the coefficient in I 2 C address 0x2A.
6. Read the top 8 bits of coefficient b2 in I
2
C address 0x2B.
7. Read the middle 8 bits of coefficient b2 in I 2 C address 0x2C.
8. Read the bottom 8 bits of coefficient b2 in I
2
C address 0x2D.
9. Read the top 8 bits of coefficient a1 in I 2 C address 0x2E.
10. Read the middle 8 bits of coefficient a1 in I
2
C address 0x2F.
11. Read the bottom 8 bits of coefficient a1 in I 2 C address 0x30.
12. Read the top 8 bits of coefficient a2 in I
2
C address 0x31.
13. Read the middle 8 bits of coefficient a2 in I 2 C address 0x32.
14. Read the bottom 8 bits of coefficient a2 in I
2
C address 0x33.
15. Read the top 8 bits of coefficient b0 in I 2 C address 0x34.
16. Read the middle 8 bits of coefficient b0 in I
2
C address 0x35.
17. Read the bottom 8 bits of coefficient b0 in I 2 C address 0x36.
Writing a single coefficient to RAM
1.
Write 6 bits of the address to I 2 C register 0x27.
2. Write the top 8 bits of the coefficient in I
2
C address 0x28.
3. Write the middle 8 bits of the coefficient in I 2 C address 0x29.
4. Write the bottom 8 bits of the coefficient in I
2
C address 0x2A.
5. Write 1 to the W1 bit in I 2 C address 0x37.
STA381BW
84/174 DocID018835 Rev 8
STA381BW Register description: New Map
Writing a set of coefficients to RAM
1.
Write 6 bits of the starting address to I 2 C register 0x27.
2. Write the top 8 bits of coefficient b1 in I
2
C address 0x28.
3. Write the middle 8 bits of coefficient b1 in I 2 C address 0x29.
4. Write the bottom 8 bits of coefficient b1 in I
2
C address 0x2A.
5. Write the top 8 bits of coefficient b2 in I 2 C address 0x2B.
6. Write the middle 8 bits of coefficient b2 in I
2
C address 0x2C.
7. Write the bottom 8 bits of coefficient b2 in I 2 C address 0x2D.
8. Write the top 8 bits of coefficient a1 in I
2
C address 0x2E.
9. Write the middle 8 bits of coefficient a1 in I 2 C address 0x2F.
10. Write the bottom 8 bits of coefficient a1 in I
2
C address 0x30.
11. Write the top 8 bits of coefficient a2 in I 2 C address 0x31.
12. Write the middle 8 bits of coefficient a2 in I
2
C address 0x32.
13. Write the bottom 8 bits of coefficient a2 in I 2 C address 0x33.
14. Write the top 8 bits of coefficient b0 in I
2
C address 0x34.
15. Write the middle 8 bits of coefficient b0 in I 2 C address 0x35.
16. Write the bottom 8 bits of coefficient b0 in I
2
C address 0x36.
17. Write 1 to the WA bit in I 2 C address 0x37.
The mechanism for writing a set of coefficients to RAM provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side effects. When using this technique, the 6-bit address specifies the address of the biquad b1 coefficient (for example, 0, 5, 10, 20, 35 decimal), and the
STA381BW generates the RAM addresses as offsets from this base value to write the complete set of coefficient data.
DocID018835 Rev 8 85/174
Register description: New Map STA381BW
The STA381BW can be programmed for four EQ filters (biquads) per each of the two input channels. The biquads use the following equation:
Y[n] = 2 * (b
0
/ 2) * X[n] + 2 * (b
1
/ 2) * X[n-1] + b
2
* X[n-2] - 2 * (a
1
/ 2) * Y[n-1] - a
2
* Y[n-2]
= b
0
* X[n] + b
1
* X[n-1] + b
2
* X[n-2] - a
1
* Y[n-1] - a
2
* Y[n-2] where Y[n] represents the output and X[n] represents the input. Multipliers are 24-bit signed fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF
(0.9999998808).
Coefficients stored in the user-defined coefficient RAM are referenced in the following manner:
CxHy0 = b
1
/ 2
CxHy1 = b
2
CxHy2 = -a
1
/ 2
CxHy3 = -a
2
CxHy4 = b
0
/ 2 where x represents the channel and the y the biquad number. For example, C2H41 is the b coefficient in the fourth biquad for channel 2.
2
Additionally, the STA381BW can be programmed for a high-pass filter (processing channels 1 and 2) and a low-pass filter (processing channel 3) to be used for bassmanagement crossover when the XO setting is 000 (user-defined). Both of these filters when defined by the user (rather than using the preset crossover filters) are second order filters that use the biquad equation given above. They are loaded into the C12H0-4 and
C3Hy0-4 areas of RAM noted in
.
Channel 1 and channel 2 biquads use by default the extended coefficient range (-4, +4);
Xover filters use only the standard coefficients range (-1, +1).
By default, all user-defined filters are pass-through where all coefficients are set to 0, except the channel 1 and 2 b
0 b
0
/2 coefficient which is set to 0x100000 (representing 0.5) and Xover
/2 coefficient which is set to 0x400000 (representing 0.5).
6.24.19 Pre-scale
The STA381BW provides a multiplication for each input channel for the purpose of scaling the input prior to EQ. This pre-EQ scaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiplication is loaded into RAM using the same I 2 C registers as the biquad coefficients and the bass management. All channels can use the channel-1 pre-scale factor by setting the biquad link bit. By default, all pre-scale factors are set to 0x7FFFFF.
6.24.20 Post-scale
The STA381BW provides one additional multiplication after the last interpolation stage and the distortion compensation on each channel. This post-scaling is accomplished by using a
24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiplication is loaded into RAM using the same I
2
C registers as the biquad coefficients and the bass management. This post-scale factor can be used in conjunction with an ADC-equipped microcontroller to perform power-supply error correction.
All channels can use the channel-1 post-scale factor by setting the post-scale link bit. By
86/174 DocID018835 Rev 8
STA381BW Register description: New Map default, all post-scale factors are set to 0x7FFFFF. When line output is being used, channel-3 post-scale will affect both channels 3 and 4.
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x3C
0x3D
0x3E
0x3F
0x14
0x15
…
0x27
0x28
0x29
0x2A
0x2B
0x00
0x01
0x02
0x03
0x04
0x05
…
0x13
Table 73. RAM block for biquads, mixing, scaling and bass management
Index (decimal) Index (hex) Description Coefficient Default
56
57
58
59
52
53
54
55
60
61
62
63
48
49
50
51
44
45
46
47
40
41
42
43
20
21
…
39
…
19
4
5
2
3
0
1
Channel 1 - Biquad 1
Channel 1 - Biquad 2
…
Channel 1 - Biquad 4
Channel 2 - Biquad 1
…
Channel 2 - Biquad 4
Channel 1/2 - Biquad 5 for XO = 000
High-pass 2 nd
order filter for XO 000
Channel 3 - Biquad for XO = 000
Low-pass 2 nd
order filter for XO 000
Channel 1 - Pre-Scale
Channel 2 - Pre-Scale
Channel 1 - Post-Scale
Channel 2 - Post-Scale
Channel 3 - Post-Scale
Reserved
Channel 1 - Mix 1
Channel 1 - Mix 2
Channel 2 - Mix 1
Channel 2 - Mix 2
Channel 3 - Mix 1
Channel 3 - Mix 2
UNUSED
UNUSED
C12H4(b0/2)
C3H0(b1/2)
C3H1(b2)
C3H2(a1/2)
C3H3(a2)
C3H4(b0/2)
C1PreS
C2PreS
C1PstS
C2PstS
C3PstS reserved
C1MX1
C1MX2
C2MX1
C2MX2
C3MX1
C3MX2
C1H10(b1/2)
C1H11(b2)
C1H12(a1/2)
C1H13(a2)
C1H14(b0/2)
C1H20
…
C1H44
C2H10
C2H11
…
C2H44
C12H0(b1/2)
C12H1(b2)
C12H2(a1/2)
C12H3(a2)
0x400000
0x000000
0x000000
0x000000
0x000000
0x400000
0x7FFFFF
0x7FFFFF
0x7FFFFF
0x7FFFFF
0x7FFFFF
0x5A9DF7
0x7FFFFF
0x000000
0x000000
0x7FFFFF
0x400000
0x400000
0x000000
0x000000
0x000000
0x000000
0x100000
0x000000
…
0x100000
0x000000
0x000000
…
0x100000
0x000000
0x000000
0x000000
0x000000
DocID018835 Rev 8 87/174
Register description: New Map STA381BW
6.25 Fault-detect recovery constant registers (addr 0x3C - 0x3D)
D7
FDRC15
0
D6
FDRC14
0
D5
FDRC13
1
D4
FDRC12
1
D3
FDRC11
0
D2
FDRC10
0
D1
FDRC9
0
D0
FDRC8
0
D7
FDRC7
0
D6
FDRC6
0
D5
FDRC5
0
D4
FDRC4
0
D3
FDRC3
1
D2
FDRC2
1
D1
FDRC1
0
D0
FDRC0
0
The FDRC bits specify the 16-bit fault-detect recovery time delay. When FAULT is asserted, the TRISTATE output is immediately asserted low and held low for the time period specified by this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The default value of 0x300C gives approximately 1 sec.
0x0000 is a reserved value.
6.26 Extended configuration register (addr 0x47)
D7
Reserved
0
D6
Reserved
D5
PS48DB
0
D4
XAR1
0
D3
XAR2
0
D2
BQ5
1
D1
BQ6
1
The extended configuration register provides access to biquad 5, 6 and 7.
D0
BQ7
1
6.26.1 Extended post-scale range
PS48DB
0
1
Table 74. Extended post-scale range
Mode
Post-scale value is applied as defined in the coefficient RAM
Post-scale value is applied with a +48 dB offset with respect to the coefficient RAM value
Post-scale is an attenuation by default. When PS48DB is set to 1, a 48-dB offset is applied to the coefficient RAM value, so post-scale can act as a gain too.
6.26.2 Extended attack rate
The attack rate shown in
Table 67 can be extended to provide up to an 8 dB/ms attack rate
on both limiters.
XAR1
0
1
Table 75. Extended attack rate, limiter 1
Mode
Limiter1 attack rate is configured using
Limiter1 attack rate is 8 dB/ms
88/174 DocID018835 Rev 8
STA381BW
XAR2
0
1
Register description: New Map
Table 76. Extended attack rate, limiter 2
Mode
Limiter2 attack rate is configured using
Limiter2 attack rate is 8 dB/ms
6.26.3 Extended biquad selector
Bass and treble controls can be configured as user-defined filters when the equalization coefficients link is activated (BQL = 1) and the corresponding BQx bit is set to 1.
BQ5
0
1
Table 77. Extended biquad selector, biquad 5
Mode
Reserved
User-defined biquad 5 coefficients are selected
Note:
BQ6
0
1
Table 78. Extended biquad selector, biquad 6
Mode
Pre-set bass filter selected as per
User-defined biquad 6 coefficients are selected
BQ7
0
1
Table 79. Extended biquad selector, biquad 7
Mode
Pre-set treble filter selected as per Table 66
User-defined biquad 7 coefficients are selected
When filters from the 5th to 7th are configured as user-programmable, the corresponding coefficients are stored respectively in addresses 0x20-0x24 (BQ5), 0x25-0x29 (BQ6), 0x2A-
0x2E (BQ7) as given in
The BQx bits are ignored if BQL = 0 or if DEMP = 1 (relevant for BQ5) or CxTCB = 1
(relevant for BQ6 and BQ7).
DocID018835 Rev 8 89/174
Register description: New Map STA381BW
6.27 PLL configuration registers (address 0x52; 0x53; 0x54; 0x55;
0x56; 0x57)
D7
0
D7
D6
0
D6
0 0
D7
PLL_DITH[1:0]
D6
0 0
D7
PLL_DPD
0
D6
PLL_FCT
0
D7
Reserved
0
D6
Reserved
0
D5
0
D5
0
D5
0
D5
PLL_STB
0
D5
PLL_DIRP
0
D4 D3
PLL_FRAC[15:8]
0 0
D4 D3
0
PLL_FRAC[7:0]
0
D4
0
D4
PLL_STBBYP
0
D4
PLL_PWD
0
D2
0
D2
D1
0
D1
D0
0
D0
0 0 0
D0 D3 D2
PLL_NDIV[5:0]
0 0
D3
0
D1
0
D2
PLL_IDIV[3:0]
D1
0 0
D3
PLL_BYP
0
D2
OSC_PD
0
0
D0
D1
Reserved
0
0
D0
BOOST32K
0
D7
Reserved
NA
D6
Reserved
NA
D5
Reserved
NA
D4
Reserved
NA
D3
BYPSTATE
NA
By default, the STA381BW is able to configure the embedded PLL automatically depending on the MCS bits (reg 0x00). For certain applications and to provide flexibility to the user, a manual PLL configuration can be used (setting PLL_DIRP to ‘1’)
The output PLL frequency formula is:
Fin
+
65536
where Fin is the input clock frequency from the pad.
D2
PDSTATE
NA
D1
OSCOK
NA
D0
LOWCK
NA
PLL parameter
FRAC
IDIV
NDIV
Table 80. PLL factors
Min
0
0
5
Max
65535
3
55
90/174 DocID018835 Rev 8
STA381BW Register description: New Map
Bit
7
6
3
2
5
4
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
RST
0
0
Table 81. PLL register 0x54 bits
Name Description
PLL_DITH[1:0]
00: PLL clock dithering disabled
01: PLL clock dithering enabled (triangular)
10: PLL clock dithering enabled (rectangular)
11: reserved
PLL_NDIV PLL loop divider
6
5
4
1
0
3
2
Bit
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
RST
0
0
0
0
Table 82. PLL register 0x55 bits
Name Description
PLL_DPD
PLL_FCT
0: any PLL dividers change is implemented via PLL powerdown
1: PLL divider change will happen without PLL powerdown
0: PLL use integer ratio
1: PLL use fractional ratio
PLL_STB PLL synchronous divider changes strobe
PLL_STBBYP
0: PLL_STB is active
1: PLL_STB control is bypassed
PLL_IDIV[3:0] Input PLL divider
3
2
0
Bit
5
4
R/W
R/W
R/W
R/W
R/W
R/W
RST
0
0
0
0
0
Table 83. PLL register 0x56 bits
Name Description
PLL_DIRP
PLL_PWD
PLL_BYP
OSC_PD
BOOST32K
0: PLL configuration is determined by the MCS bits
1: PLL configuration is determined by FRAC, IDIV and NDIV
0: PLL normal behavior
1: PLL is in power-down mode
0: sys clock is from PLL
1: sys clock is from external pin (PLL is bypassed)
0: Normal behavior
1: Internal oscillator is in power-down
0: Input oversampling selected by the IR bits
1: Input oversampling is selected x3
DocID018835 Rev 8 91/174
Register description: New Map STA381BW
Bit
1
0
3
2
R/W
R/W
R/W
R/W
R/W
RST
Table 84. PLL register 0x57 bits
Name Description
BYPSTATE
PDSTATE
OSCOK
LOWCK
PLL bypass state
PLL PD state
OSCI locked
Clock input low-frequency check
6.28 Short-circuit protection mode registers SHOK (address 0x58)
D7 reserved
NA
D6 reserved
NA
D5 reserved
NA
D4 reserved
NA
D3 reserved
NA
D2
GNDSH
NA
D1
VCCSH
NA
D0
OUTSH
NA
The following power bridge pins short-circuit protections are implemented in the
STA381BW:
OUTxx vs. GNDx
OUTxx vs. VCCx
OUT1B vs. OUT2A
The protection is enabled when reg. 0x50 bit 0 (SHEN) is set to ‘1’. The protection will check the short-circuit when the EAPD bit is toggled from ‘0’ to ‘1’ (i.e. the power bridge is switched on), and only if the test passes (no short), does the power bridge leave the tristate condition.
Register 0x58 (read-only registers) will give more information about the detected short type.
GNDSH equal to ‘0’ means that OUTxx is shorted to ground, while the same value on
VCCSH means that OUTxx is shorted to Vcc, finally OUTSH=’0’ means that OUT1B is shorted to OUT2A.
To be noted that once the check is performed, and the tristate released, the short protection is not active anymore until the next EAPD 0->1 toggling which means that shorts that happened during normal operation cannot be detected.
To be noted that register SHOK is meaningful only after the EAPD bit is set to ‘1’ at least once.
The short-circuit protections implemented are effective only in BTL configuration, and they must not be activated if a single-ended application scheme is needed.
92/174 DocID018835 Rev 8
STA381BW Register description: New Map
Figure 28. Short-circuit detection timing diagram (no short detected)
S t a r t g n d t e s t S t a r t v c c t e s t
Start out test
E n d o f S h o r t t e s t
EAPD
OUT1A
OUT1B
OUT2A
OUT2B
GNDSH]
VCCSH
OUTSH]
50005 cycles
TBD cycles
44 cycles
50005 cycles
1cycle
In
Figure 28 the short protection timing diagram is shown. The time information is expressed
carrying the status of the previous EAPD 0->1 toggling (to be noted that after reset this state is meaningless since no EAPD transition occurs). The GND-related SHOK bits are updated as soon as the gnd test is completed, the VCC bits are updated after vcc test is completed, and the SOUT bit is updated after the shorted output test is completed. The gnd test, vcc test and output test, are always run (if the SHEN bit is active and EAPD toggled to ‘1’), and only if both tests are successful (no short) do the bridge outputs leave the tristate (indicated by dotted lines in the figure). If one of the three tests (or all) fail, the power bridge outputs are kept in the tristate until the procedure is restarted with a new EAPD toggling.
In this figure EAPD is intended to be bit 7 of register 0x05.
6.29 Extended coefficient range up to -4...4 (address 0x5A)
D7 D6
CEXT_B4[1] CEXT_B4[0]
1 0
D5
CEXT_B3[1]
1
D4
CEXT_B3[0]
0
D3 D2
CEXT_B2[1] CEXT_B2[0]
1 0
D1
CEXT_B1[1]
1
D0
CEXT_B1[0]
0
D7 reserved
0
D6 reserved
0
D5
CEXT_B7[1]
1
D4
CEXT_B7[0]
0
D3 D2
CEXT_B6[1] CEXT_B6[0]
1 0
D1
CEXT_B51]
1
D0
CEXT_B5[0]
0
Biquads from 1 to 7 have in the STA381BW the possibility to extend the coefficient range from [-1,1) to [-4..4) which allows the use of high-shelf filters that may require a coefficient dynamic greater in absolute value than 1.
Three ranges are available, [-1;1) [-2;2) [-4;4). By default, the extended range is activated.
Each biquad has its independent setting according to the following table.
DocID018835 Rev 8 93/174
Register description: New Map STA381BW
Table 85. Coefficients extended range configuration
CEXT_Bx[1] CEXT_Bx[0] Range
0
0
0
1
[-1;1)
[-2;2)
1
1
0
1
[-4;4)
Reserved
In this case the user can decide, for each filter stage, the right coefficient range. Note that for a given biquad the same range will be applied to the left and right (channel 1 and channel 2).
The crossover biquad does not have the availability of this feature, maintaining the [-1;1) range unchanged.
6.30 Miscellaneous registers (address 0x5C, 0x5D)
D7
RPDNEN
0
D7
LPDP
0
D6
Reserved
1
D6
LPD
1
D5
BRIDGOFF
1
D5
LPDE
0
D4
Reserved
0
D3
Reserved
0
D2
CPWMEN
1
D4
PNDLSL[2]
0
D3
PNDLSL[1]
1
D2
PNDLSL[0]
1
D1
Reserved
0
D1
Reserved
0
D0
Reserved
0
D0
SHEN
0
6.30.1 Rate power-down enable (RPDNEN) bit
In the STA381BW, by default, the power-down pin and I 2 C power-down act on mute commands to perform the fade-out. This default can be changed so that the fade-out can be started using the master volume. The RPDNEN bit, when set, activates this feature.
6.30.2 Bridge immediately off (BRIDGOFF) bit (address 0x4B, bit D5)
A fade-out procedure is started in the STA381BW once the PWDN function is enabled, and after 13 million clock cycles (PLL internal frequency) the bridge is put in power-down
(tristate mode). There is also the possibility to change this behavior so that the power bridge will be switched off immediately after the PWDN pin is tied to ground, without waiting for the
13 million clock cycles. The BRIDGOFF bit, when set, activates this function. Obviously the immediate power-down will generate a pop noise at the output, therefore this procedure must be used only in cases where pop noise is not relevant in the application. Note that this feature works only for hardware PWDN assertion and not for a power-down applied through the IIC interface. Refer to
if programming a different number of clock cycles is needed.
94/174 DocID018835 Rev 8
STA381BW Register description: New Map
6.30.3 Channel PWM enable (CPWMEN) bit
This bit, when set, activates a mute output in case the volume reaches a value lower than -76 dBFS.
6.30.4 External amplifier hardware pin enabler (LPDP, LPD LPDE) bits
Pin 42 (INTLINE), normally indicating a fault condition, using the following 3 register settings can be reconfigured as a hardware pin enabler for an external headphone or line amplifier.
In particular the LPDE bit, when set, activates this function. Accordingly, the LPD value (0 or
1) is exported on pin 42 and in case of power-down assertion, pin 42 is tied to LPDP.
The LPDP bit, when set, negates the value programmed as the LPD value, refer to the following table.
0
1
1
LPDP
Table 86. External amplifier enabler configuration bits
LPD LPDE Pin 42 output x
0 x
0
0
1
INT_LINE
0
1
0
1
1
1
1
1
1
0
Figure 29. Alternate function for INTLINE pin
P o w er B rid ge Fau lt
0
‘0 ’
Y
L P D
N
0
1
1
IN T L IN E
L P D E
“is th e d evice in p ow erd o w n ?” LP D P
6.30.5 Power-down delay selector (PNDLSL[2:0]) bits
The assertion of PWDN activates a counter that, by default, after 13 million clock cycles puts the power bridge in tristate mode, independently from the fade-out time. Using these registers it is possible to program this counter according to the following table.
DocID018835 Rev 8 95/174
Register description: New Map STA381BW
PNDLSL[2]
0
0
0
1
1
0
1
1
PNDLSL[1]
Table 87. PNDLSL bits configuration
PNDLSL[2] Fade-out time
0
0
0
1
Default time (13M PLL clock cycles)
Default time divided by 2
1
1
0
0
1
1
0
1
0
1
0
1
Default time divided by 4
Default time divided by 8
Default time divided by 16
Default time divided by 32
Default time divided by 64
Default time divided by 128
6.30.6 Short-circuit check enable bit
This bit, when enabled, will activate the short-circuit checks before any power bridge activation (EAPD bit 0->1). See section
Section 6.28: Short-circuit protection mode registers
SHOK (address 0x58) for more details.
6.31 Bad PWM detection registers (address 0x5E, 0x5F, 0x60)
D7
BPTH[5]
0
D6
BPTH[4]
0
D5
BPTH[3]
1
D4
BPTH[2]
1
D3
BPTH[1]
0
D2
BPTH[0]
0
D1 reserved
1
D0 reserved
0
D7
BPTIM[7]
0
D6
BPTIM[6]
1
D5
BPTIM[5]
0
D4
BPTIM[4]
1
D3
BPTIM[3]
1
D2
BPTIM[2]
1
D1
BPTIM[1]
1
D0
BPTIM[0]
0
The STA381BW implements a detection on PWM outputs able to verify if the output signal has no zero-crossing in a configurable time window. This check can be useful to detect the
DC level in the PWM outputs. To be noted that the checks are performed on logic level
PWM (i.e. not the power bridge ones, nor the PWM on DDX3 and DDX4 IOs).
In case of ternary modulation, the detection threshold is computed as:
TH=[(BPTH*2+1)/128]*100%
If the measured PWM duty cycle is detected greater than or equal to TH for more than
BPTIM PWM periods, the corresponding PWM bit will be set in register 0x01.
In case of binary modulation, there are two thresholds:
TH1=[(64+BPTH)/128]*100%
TH2=[(64-BPTH)/128]*100%
In this case if the measured PWM duty cycle is outside the TH1-TH2 range for more than
BPTIM PWM periods, the corresponding bit will be set in register 0x4E.
96/174 DocID018835 Rev 8
STA381BW Register description: New Map
6.32 Enhanced zero-detect mute and input level measurement
(address 0x61-0x65, 0x3F, 0x40, 0x6F)
D7
WTHH
0
D6
WTHL
0
D5
FINETH
0
D4
HSEL[1:0]
D3
0 0
D2
1
D1
ZMTH[2:0]
1
D0
1
D7
N/A
D7
N/A
D6
N/A
D6
N/A
D5
N/A
D5
N/A
D4 D3
RMS_CH0[7:0]
N/A N/A
D4 D3
RMS_CH0[15:8]
N/A N/A
D2
N/A
D2
N/A
D1
N/A
D1
N/A
D0
N/A
D0
N/A
D7
N/A
D6
N/A
D5
N/A
D4 D3
RMS_CH1[7:0]
N/A N/A
D2
N/A
D1
N/A
D0
N/A
D7
N/A
D6
N/A
D5
N/A
D4 D3
RMS_CH1[15:8]
N/A N/A
D2
N/A
D1
N/A
D0
N/A
The STA381BW implements an RMS-based zero-detect function (on serial input interface data) able to detect in a very reliable way the presence of an input signal, so that the power bridge outputs can be automatically connected to ground.
When active, the function will mute the output PWM when the input level becomes less than
“threshold - hysteresis”. Once muted, the PWM will be unmuted when the input level is detected greater than “threshold + hysteresis”.
The measured level is then reported (for each input channel) on registers ZCCCFG1 -
ZCCCFG2, ZCCCFG3 - ZCCCFG4 according to the following equation:
Value_in_dB = 20*Log
10
(Reg_value/(2
16
*0.635))
ZMTH[2:0]
000
001
010
011
100
101
110
111
Table 88. Zero-detect threshold
Equivalent input level (dB)
-78
-84
-90
-96
-102
-108
-114
-114
DocID018835 Rev 8 97/174
Register description: New Map STA381BW
HSEL[1:0]
00
01
10
11
Table 89. Zero-detect hysteresis
Equivalent input level hysteresis(dB)
5
6
3
4
The thresholds and hysteresis table above can be overridden and the low-level threshold and high-level threshold can be set by the MTH[21:0] bits.
To activate the manual thresholds the FINETH bit has to be set to ‘1’.
To configure the low threshold, the WTHL bit must be set to ‘1’ so that any write operation to the MTH bits will set the low threshold.
To configure the low threshold, the WTHH bit must be set to ‘1’ so that any write operation to the MTH bits will set the low threshold.
If the zero-mute block does not detect mute, it will mute the output when the current RMS value falls below the low threshold.
If the zero-mute block does not detect mute, it will unmute the output when the current RMS value rises above the high threshold.
Table 90. Manual threshold register 0x3F, 0x40 and 0x6F
D7
ReservedT
0
D6
Reserved
0
D5
0
D4
0
D3
MTH[21:16]
D2
0 0
D1
0
D0
0
D7
0
D6
0
D5
0
D4
MTH[15:8]
D3
0 0
D2
0
D1
0
D0
0
D7
0
D6
0
D5
0
D4
MTH[7:0]
D3
0 0
D2
0
D1
0
D0
0
98/174 DocID018835 Rev 8
STA381BW Register description: New Map
6.33 Headphone/Line out configuration register (address 0x66)
D7
HPLN
0
D6
Reserved
0
D5
Reserved
1
D4
Reserved
0
D3
CPFEN
0
D2
CPOK
NA
D1
ABFAULT
NA
D0
DCROK
NA
3
2
1
0
Bit
7
R/W
R
R
R
R/W
R/W
Table 91. Headphone/Line out configuration bits
RST Name Description
0
0
NA
NA
NA
HPLN
CPFEN
CPOK
ABFAULT
DCROK
When F3X is connected to the internal HP/Line driver this bit selects the gain of the F3X->analog out path.
0: HP out. When the MVOL+Channel Vol is
0 dBFs, a 0 dBFs input will generate a 40 mW output on a 32 ohm load (+/- 3.3V supply).
1: Line out. When the MVOL+Channel Vol is
0 dBFs, a 0 dBFs input will generate a 2 Vrms output (+/- 3.3 V supply)
0: Charge pump auto-enable when unmute
1: Charge pump is always enabled
0: Charge pump is not working
1: Charge pump is working and it is OK
0: No fault on class-AB
1: Overcurrent fault detected on class-AB
1: Core supply OK
DocID018835 Rev 8 99/174
Register description: New Map
6.34 F3XCFG (address 0x69; 0x6A)
STA381BW
D7
F3XLNK
0
D7
F3X_FAULT
1
D6 reserved
0
D6 reserved
1
D5 reserved
0
D5 reserved
1
D4 reserved
0
D3 reserved
0
D2 reserved
0
D4
0
D3
F3X_SM_SLOPE[2:0]
1
D2
1
D1 reserved
0
D1
F3X_MUTE
1
D0 reserved
0
D0
F3X_ENA
0
Bit
7
R/W
R/W
RST
0
Table 92. F3X configuration register 1
Name Description
F3XLNK
0: F3X normal control mode
1: F3X mute/unmute linked to HP/Line mute
Bit
7
4
3
2
1
0
R/W
R
R/W
R/W
R/W
R/W
R/W
RST
1
0
1
1
1
0
Table 93. F3X configuration register 2
Name Description
F3X_FAULT
F3X_SM_SLOPE
F3X_MUTE
F3X_ENA
0: Normal operation
000: 0 ms
001: 25 ms
010: 50 ms
011: 100 ms
100: 200 ms
101: 250 ms
110: 500 ms
111: 1000 ms
1: Mute
1: F3X enable
100/174 DocID018835 Rev 8
STA381BW Register description: New Map
6.35 STCompressor
TM
configuration register (address 0x6B;
0x6C)
D7
Reserved
0
D6
Reserved
0
D5
Table 94. Register STCCFG0
D4 D3 D2
Reserved
0
Reserved
1
Reserved
0
CRC_RES
0
D1
Reserved
0
D0
Reserved
0
Bit
2
R/W
R/W
RST
0
Table 95. STCCFG0 register
Name Description
CRC_RES
0 = CRC comparison successful
1 = CRC comparison error
D7
Reserved
0
Bit
1
D6
Reserved
0
R/W
R/W
RST
0
D5
Table 96. Register STCCFG1
D4 D3 D2
Reserved Reserved Reserved Reserved
0 0 0 0
D1
STC_LNK
0
D0
Reserved
0
Table 97. STCCFG1 register
Name Description
STC_LNK
0 = normal operations
1 = stereo link enabled. See
6.36 Charge pump synchronization (address 0x70)
4
3
2
1
D7
Reserved
0
Bit
5
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
D6
Reserved
0
D5
CHPI
0
D4
1
D3
INITCNT[3:0]
D2
1 0
D1
0
D0
CHPRD
1
1
1
0
0
Table 98. Charge pump sync configuration bits
RST Name Description
0 CHPI
0: Charge pump phase: 0 deg
1: Charge pump phase: 180 deg
INITCNT[3:0] Change charge pump phase at one clock step
1 CHPRD
0: Charge pump synchronized with PWM frame
1: Charge pump not synchronized with PWM frame
DocID018835 Rev 8 101/174
Register description: New Map STA381BW
The charge pump can be synchronized with the PWM frame in order to minimize the crosstalk between the charge pump and the PWM waveform.
This functionality cannot be activated when the PWMS bit (address 0x15 bit D4) is set to 1.
6.37 Coefficient RAM CRC protection (address 0x71-0x7D)
D7
BQCKE[7]
0
D6
BQCKE[6]
0
D5
BQCKE[5]
0
D4
BQCKE[4]
0
D3
BQCKE[3]
0
D2
BQCKE[2]
0
D1
BQCKE[1]
0
D0
BQCKE[0]
0
D7
BQCKE[15]
0
D6
BQCKE[14]
0
D5
BQCKE[13]
0
D4
BQCKE[12]
0
D3
BQCKE[11]
0
D2
BQCKE[10]
0
D7
BQCKE[23]
0
D6
BQCKE[22]
0
D5
BQCKE[21]
0
D4
BQCKE[20]
0
D3
BQCKE[19]
0
D2
BQCKE[18]
0
D1
BQCKE[17]
0
D0
BQCKE[16]
0
D7
XCCKE[7]
0
D7
XCCKE[15]
0
D6
XCCKE[6]
0
D6
XCCKE[14]
0
D5
XCCKE[5]
0
D5
XCCKE[13]
0
D4
XCCKE[4]
0
D4
XCCKE[12]
0
D3
XCCKE[3]
0
D3
XCCKE[11]
0
D2
XCCKE[2]
0
D2
XCCKE[10]
0
D1
BQCKE[9]
0
D1
XCCKE[1]
0
D1
XCCKE[9]
0
D0
BQCKE[8]
0
D0
XCCKE[0]
0
D0
XCCKE[8]
0
D7
XCCKE[23]
0
D6
XCCKE[22]
0
D5
XCCKE[21]
0
D4
XCCKE[20]
0
D3
XCCKE[19]
0
D2
XCCKE[18]
0
D1
XCCKE[17]
0
D0
XCCKE[16]
0
D7
BQCKR[7]
0
D7
BQCKR[15]
0
D6
BQCKR[6]
0
D6
BQCKR[14]
0
D5
BQCKR[5]
0
D5
BQCKR[13]
0
D4
BQCKR[4]
0
D3
BQCKR[3]
0
D4
BQCKR[12]
0
D3
BQCKR[11]
0
D2
BQCKR[2]
0
D2
BQCKR[10]
0
D1
BQCKR[1]
0
D1
BQCKR[9]
0
D0
BQCKR[0]
0
D0
BQCKR[8]
0
D7
BQCKR[23]
0
D6
BQCKR[22]
0
D5
BQCKR[21]
0
D4
BQCKR[20]
0
D3
BQCKR[19]
0
D2
BQCKR[18]
0
D1
BQCKR[17]
0
D0
BQCKR[16]
0
D7
XCCKR[23]
0
D6
XCCKR[22]
0
D5
XCCKR[21]
0
D4
XCCKR[20]
0
D3
XCCKR[19]
0
D2
XCCKR[18]
0
D1
XCCKR[17]
0
D0
XCCKR[16]
0
D7
XCCKR[23]
0
D6
XCCKR[22]
0
D5
XCCKR[21]
0
D4
XCCKR[20]
0
D3
XCCKR[19]
0
D2
XCCKR[18]
0
D1
XCCKR[17]
0
D0
XCCKR[16]
0
D7
XCCKR[23]
D6
XCCKR[22]
D5
XCCKR[21]
D4
XCCKR[20]
D3
XCCKR[19]
D2
XCCKR[18]
D1
XCCKR[17]
D0
XCCKR[16]
102/174 DocID018835 Rev 8
STA381BW Register description: New Map
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
D7
XCAUTO
0
D6
XCRES
0
D5
XCCMP
0
D4
XCGO
0
D3
BCAUTO
0
D2
BCCRES
0
D1
BCCMP
0
D0
BCCGO
0
The STA381BW implements an automatic CRC computation for the biquad and
MDRC/XOver coefficient memory (
Table 73 ). Memory cell contents from address 0x00 to
0x27 will be bit XORed to obtain the BQCHKE checksum, while cells from 0x28 to 0x31 will
I be XORed to obtain the XCCHKE checksum. Both checksums (24-bit wide) are exported on
2 C registers from 0x60 to 0x65. The checksum computation will start as soon as the BCGO
(for biquad RAM bank) or the XCGO bit (for MDRC/XOver coefficients) is set to 1. The checksum is computed at the processing sample rate if the IR bits equal “01” or “10”, otherwise the checksum is computed to half of the processing sample rate.
When BCCMP or XCCMP is set to ‘1’, the relative checksum (BQCHKE and XCCHKE) is continuously compared with BQCHKR and XCCHKR respectively. If the checksum matches its own reference value, the respective result bits (BCRES and XCRES) will be set to ‘0’.
The compare bits have no effect if the respective GO bit is not set.
In case of checksum errors (i.e. the internally computed didn’t match the reference), an automatic device reset action can be activated. This function is enabled when the BCAUTO or XCAUTO bit is set to ‘1’. The automatic reset bits have no effect if the respective compare bits are not set.
The recommended procedure for automatic reset activation is the following:
Download the set of coefficients (RAM locations 0x00…0x27)
Download the externally computed biquad checksum into registers BQCHKR
Enable the checksum of the biquad coefficients by setting the BCGO bit. The checksum will start to be automatically computed by the STA381BW and its value exposed on registers BQCHECKE.
The checksum value is computed and updated.
Enable the checksum comparison by setting the BCCMP bit. The internally computed checksum will start to be compared with the reference one and the result will be exposed on the BCRES bit. The following operation will be executed on each audio frame:
{ if (( BQCHKE == BQCHKR ))
BC_RES = 0;// Checksum is ok, reset the error bit
}
DocID018835 Rev 8 103/174
Register description: New Map STA381BW
{ else
BC_RES = 1;// Checksum error detected, set the error bit
}
Wait until the BCRES bit goes to 0, meaning that the checksum result bit has started to be updated and everything is ok. Time-out of this operation (e.g. >1 ms) will indicate checksum failure, and the MCU will handle this event
Enable automatic reset of the device in case of checksum error by setting the BCAUTO bit. The BCRES bit will then be automatically checked by the STA381BW, on each audio frame, and a reset event will be triggered in case of checksum mismatch.
Periodically check the BC_RES status. A value of 1 indicates a checksum mismatch has occurred and, therefore, that the device went through a reset cycle.
The previous example is intended for biquad CRC bank calculation, but it can be easily extended to MDRC/XOver CRC computation.
6.38 MISC4 (address 0x7E)
Bit
7
1
0
D7
SMAP
1
R/W
R/W
R/W
R/W
D6 reserved
0
RST
1
0
0
D5 reserved
0
D4 reserved
0
D3 reserved
0
D2 reserved
0
D1
WRA
0
D0
CH12
0
Table 99. Misc register 4
Name
SMAP
WRA
CH12
Description
1 = NEW MAP
0 = STMAP
0 = normal operations
1 = enables the write-all procedure when using the
RAM coefficients direct access
0 = normal operations
1 = enables the RAM coefficients direct access
The STA381BW allows direct access to the RAM coefficients bypassing the indirect access mechanism described in
Section 6.24: User-defined coefficient control registers (addr 0x27
- 0x37) . Direct access is implemented as follows.
104/174 DocID018835 Rev 8
STA381BW Register description: New Map
Direct single-write procedure
1.
Set reg 0x7E bit 0 to 1 and bit 1 to 0 to enable the direct RAM access in single-write mode.
2. Write the coefficient value to the device using an I discribed in
2 C bus single-write operation as
Figure 30. Coefficients direct access single-write operation
Direct multi-write procedure
1.
Set the reg 0x7E bit 0 to 1 and bit 1 to 1 to enable direct RAM access in multi-write mode.
2. Write the coefficients value to the device using an I 2 C bus multi-write operation as discribed in
Figure 31 . Please note that by using the multi-write procedure, it is possible
to write the entire RAM contents at once.
Figure 31. Coefficients direct access multiple-write operation
S Slave address w A Mem Addr A
Coeff_0(3) A Coeff_0(2) A Coeff_0(1) A Coeff_0(0) A
Coeff_1(3) A Coeff_1(2) A Coeff_1(1) A Coeff_1(0) A
Coeff_n(3) A Coeff_n(2) A Coeff_n(1) A Coeff_n(0) A
Direct single-read procedure
1.
Set reg 0x7E bit 0 to 1 and bit 1 to 0 to enable the direct RAM access in single-read mode.
2. Read the coefficient value from the device using an I
2
C bus single-read operation as discribed in
Figure 32. Coefficients direct access single-read operation
Please be aware that the STA381BW supports 24-bit coefficients, for this reason in the above figures Coeff_x(0) is always equal to 0x00 when either reading or writing. The multiwrite procedure embeds a wrap-around mechanism: when trying to write into a location exceeding the maximum coefficient address, the multi-write procedure will start from location 0x00.
DocID018835 Rev 8 105/174
Register description: Sound Terminal compatibility
7
STA381BW
Register description: Sound Terminal compatibility
To keep compatibility with previous Sound Terminal devices, the 0x7E bit D7 must be set to
0 after device turn-on and after any reset (via SW or via external pin).
Missing addresses are to be considered as reserved.
Addr Name D7
Table 100. I 2 C registers summary
D6 D5
1A
1B
1C
1D
1E
16
17
18
19
12
13
14
15
0E
0F
10
11
08
09
0A
0C
00
01
02
03
CONFA
CONFB
CONFC
CONFD
FDRB
C2IM
04
05
CONFE
CONFF
SME
SVE
EAPD
06 MUTE LOC LOC1
07 MVOL
CH1VOL
CH2VOL
CH3VOL
AUTO
C1CFG
C2CFG
C3CFG
TONE
L1AR
L1ATRT
L2AR
L2ATRT
CFADDR
B1CF1
B1CF2
B1CF3
B2CF1
B2CF2
B2CF3
A1CF1
A1CF2
C3OM1
TTC3
L1A3
L1AT3
L2A3
L2AT3
C1B23
C1B15
C1B7
C2B23
C2B15
C2B7
C3B23
C3B15
C1IM
ZDE
ZCE
PWDN
LOC0
DSCKE
CSZ3
XO3 XO2 XO1
C1OM1 C1OM0 C1LS1
C2OM1 C2OM0 C2LS1
C3OM0
TTC2
L1A2
L1AT2
L2A2
L2AT2
C1B22
C1B14
C1B6
C2B22
C2B14
C2B6
C3B22
C3B14
C3LS1
TTC1
L1A1
L1AT1
L2A1
L2AT1
CFA5
C1B21
C1B13
C1B5
C2B21
C2B13
C2B5
C3B21
C3B13
D4 D3 D2 D1 D0
L1A0
L1AT0
L2A0
L2AT0
CFA4
C1B20
C1B12
C1B4
C2B20
C2B12
C2B4
C3B20
C3B12
IR1
SAIFB
CSZ2
BQL
IR0
SAI3
CSZ1
PSL
PWMS
LDTE
AME
BCLE
BQB_ALL C3M
MVOL[7:0]
MCS2
SAI2
CSZ0
DSPB
NSBW
IDE
C2M
MCS1
SAI1
OCFG1
C1M
MCS0
SAI0
OCFG0
MMUTE
CH1VOL[7:0]
CH2VOL[7:0]
CH3VOL[7:0]
XO0 AMAM2 AMAM1 AMAM0 AMAME
C1LS0
C2LS0
C3LS0
TTC0
C1BO
C2BO
C3BO
BTC3
C1VBP C1EQBP C1TCB
C2VBP C2EQBP C2TCB
C3VBP
BTC2 BTC1 BTC0
L1R3
L1RT3
L2R3
L2RT3
CFA3
C1B19
C1B11
C1B3
C2B19
C2B11
C2B3
C3B19
C3B11
L1R2
L1RT2
L2R2
L2RT2
CFA2
C1B18
C1B10
C1B2
C2B18
C2B10
C2B2
C3B18
C3B10
L1R1
L1RT1
L2R1
L2RT1
CFA1
C1B17
C1B9
C1B1
C2B17
C2B9
C2B1
C3B17
C3B9
L1R0
L1RT0
L2R0
L2RT0
CFA0
C1B16
C1B8
C1B0
C2B16
C2B8
C2B0
C3B16
C3B8
106/174 DocID018835 Rev 8
STA381BW Register description: Sound Terminal compatibility
46 PLLSTATE
47
49
4A
2E
2F
31
32
26
2B
2C
2D
33
34
35
36
22
23
24
25
1F
20
21
37
38
A1CF3
A2CF1
A2CF2
A2CF3
B0CF1
B0CF2
B0CF3
CFUD
FDRC1
FDRC2
STATUS
C4B7
C5B23
C5B15
C5B7
C4B6
C5B22
C5B14
C5B6
C4B5
C5B21
C5B13
C5B5
C4B4
C5B20
C5B12
C5B4
C4B3
C5B19
C5B11
C5B3
C4B2
C5B18
C5B10
C5B2
RA R1 WA
FDRC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9
FDRC7
PLLUL
FDRC6
FAULT
FDRC5 FDRC4 FDRC3 FDRC2 FDRC1
MTH[21:16] MTH2
MTH1
EQCFG XOB
EATH1 EATHEN1
MTH[15:8]
C3B1
C4B17
C4B9
C4B1
C5B17
C5B9
C5B1
ERTH1
EATH2
ERTH2 ERTHEN2
CONFX MDRCE
SVUP
SVDN
C3B7
C4B23
C4B15
ERTHEN1
EATHEN2
Table 100. I 2 C registers summary (continued)
C3B6 C3B5 C3B4 C3B3 C3B2
C4B22
C4B14
C4B21
C4B13
PS48DB
SVUP_
EN
SVDN_
EN
C4B20
C4B12
XAR1
C4B19
C4B11
EATH1[6:0]
ERTH1[6:0]
EATH2[6:0]
ERTH2[6:0]
XAR2
C4B18
C4B10
BQ5
SVUP_RATE[4:0]
SVDN_RATE[4:0]
BQ6
3F EVOLRES VRES_EN
VRESTG
_EN
40
EVOLRES
2
41 PLLFRAC1
42 PLLFRAC0
43 PLLDIV
44 PLLCFG0
PLL_DITH[1:0]
PLL_
DPD
PLL_
FCT
EXVRES_CH3[1:0]
PLL_STB
EXVRES_CH2[1:0]
PLL_FRAC[15:8]
PLL_FRAC[7:0]
PLL_NDIV[5:0]
PLL_
STBBYP
PLL_IDIV[3:0]
BQ7
EXVRES_CH1[1:0]
EXVRES_MVOL[1:0]
C3B0
C4B16
C4B8
C4B0
C5B16
C5B8
C5B0
W1
FDRC8
FDRC0
45 PLLCFG1
PLL_
DIRP
PLL_PWD PLL_BYP OSC_PD BOOST32K
SHOK
CXT41
CXT75
CEXT_B4[1:0] CEXT_B3[1:0]
CEXT_B7[1:0]
BYPSTAT
E
PDSTATE OSCOK LOWCK
GNDSH VCCSH
CEXT_B2[1:0]
CEXT_B6[1:0]
OUTSH
CEXT_B1[1:0]
CEXT_B5[1:0]
DocID018835 Rev 8 107/174
Register description: Sound Terminal compatibility STA381BW
4B
4C
4D
MISC1
MISC2
BPTH
4E BADPWM
4F BPTIM
50
51
ZCCFG0
ZCCFG1
5A STCCFG0
5B STCCFG1
5E MTH0
RPDNEN
LPDP
BP4B
WTHH
52
53
54
55
ZCCFG2
ZCCFG3
ZCCFG4
HPCFG HPLN
58 F3XCFG1 F3XLNK
59 F3XCFG2
F3X_
FAULT
Table 100. I 2 C registers summary (continued)
LPD
BP4A
WTHL
LIM_
BYP
BRIDGOFF
LPDE
BPTH(5:0)
BP3B
FINETH
MUTE
PNDLSL[2:0]
BP3A BP2B
BPTIM[7:0]
HSEL[1:0]
RMS_CH0[7:0]
RMS_CH0[15:8]
RMS_CH1[7:0]
RMS_CH1[15:8]
CPFEN
F3X_SM_SLOPE[2:0]
STC_BYP STC_ENA
MTH[7:0]
CPWMEN
BP2A
CPOK ABFAULT DCROK
NP_
CRCRES
BP1B
ZMTH[2:0]
SHEN
BP1A
F3X_
MUTE
F3X_ENA
NP_CRC_
GO
STC_LNK BRC_EN
CHPRD 5F CHPSINC CHPI
60 BQCHKE0
61 BQCHKE1
62 BQCHKE2
63 XCCHKE0
64 XCCHKE1
65 XCCHKE2
66 BQCHKR0
67 BQCHKR1
68 BQCHKR2
69 XCCHKR0
6A XCCHKR1
6B XCCHKR2
6C CHKCTRL XCAUTO XCRES XCCMP
6E
7E
MISC3
MISC4 SMAP
INITCNT[3:0]
BQ_CKE[7:0]
BQ_CKE[15:8]
BQ_CKE[23:16]
XC_CKE[7:0]
XC_CKE[15:8]
XC_CKE[23:16]
BQ_CKR[7:0]
BQ_CKR[15:8]
BQ_CKR[23:16]
XC_CKR[7:0]
XC_CKR[15:8]
XC_CKR[23:16]
XCGO BCAUTO BCRES BCCMP
SRESET
BCGO
108/174 DocID018835 Rev 8
STA381BW
7.1
7.1.1
Register description: Sound Terminal compatibility
Configuration register A (addr 0x00)
D7
FDRB
0
D6
Reserved
1
D5
Reserved
1
D4
IR1
0
D3
IR0
0
Master clock select
Bit
0
1
2
R/W
R/W
R/W
R/W
RST
1
1
1
D2
MCS2
1
D1
MCS1
1
D0
MCS0
1
Table 101. Master clock select
Name Description
MCS0
MCS1
MCS2
Selects the ratio between the input I
2
S sampling frequency and the input clock.
The STA381BW supports sampling rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,
176.4 kHz, and 192 kHz. Therefore the internal clock is:
32.768 MHz for 32 kHz
45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz
49.152 MHz for 48 kHz, 96 kHz, and 192 kHz
The external clock frequency provided to the XTI pin or BICKI pin (depending on MCS settings) must be a multiple of the input sampling frequency (f s
).
The relationship between the input clock (either XTI or BICKI) and the input sampling rate is determined by both the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio
used internally. In Table 102 MCS 111 and 110 indicate that BICKI has to be used as the
clock source, while XTI is used in all the other cases.
Table 102. Input sampling rates
Input sampling rate fs (kHz)
IR
32, 44.1, 48
88.2, 96
176.4, 192
MCS[2:0]
111 110
00 64*fs(*) NA
01 64*fs(*) 32*fs(*)
1X 64*fs(*) 32*fs(*)
101 100 011 010 001 000
576 * fs 128 * fs 256 * fs 384 * fs 512 * fs 768 * fs
NA
NA
64 * fs
32 * fs
128 * fs 192 * fs 256 * fs 384 * fs
64 * fs 96 * fs 128 * fs 192 * fs
Note: (*) Clock is BICKI
DocID018835 Rev 8 109/174
Register description: Sound Terminal compatibility
7.1.2 Interpolation ratio select
Bit
4:3
R/W
R/W
RST
00
STA381BW
Table 103. Internal interpolation ratio
Name Description
IR [1:0]
Selects internal interpolation ratio based on input I
2
S sampling frequency
The STA381BW has variable interpolation (oversampling) settings such that internal processing and FFX output rates remain consistent. The first processing block interpolates
by either 3 times (see Section 4.2
), 2 times or 1 time (pass-through) or provides a 2 times downsample. The oversampling ratio of this interpolation is determined by the IR bits.
Table 104. IR bit settings as a function of the input sampling rate
Input sampling rate fs (kHz) IR 1st stage interpolation ratio
32
44.1
48
88.2
96
176.4
192
01
10
10
00
00
00
01
2-times oversampling
2-times oversampling
2-times oversampling
Pass-through
Pass-through
2-times downsampling
2-times downsampling
7.1.3 Fault-detect recovery bypass
Bit
7
R/W
R/W
RST
0
Table 105. Fault-detect recovery bypass
Name Description
FDRB
0: fault-detect recovery enabled
1: fault-detect recovery disabled
The on-chip STA381BW power output block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition
(either overcurrent or thermal). When FAULT is asserted (set to 0), the power control block attempts a recovery from the fault by asserting the tri-state output (setting it to 0 which directs the power output block to begin recovery), holds it at 0 for period of time in the range of 0.1 ms to 1 second as defined by the fault-detect recovery constant register (FDRC registers 0x2B-0x2C), then toggles it back to 1. This sequence is repeated as long as the fault indication exists. This feature is enabled by default, but can be bypassed by setting the
FDRB control bit to 1.
110/174 DocID018835 Rev 8
STA381BW
7.2
7.2.1
7.2.2
Register description: Sound Terminal compatibility
Configuration register B (addr 0x01)
D7
C2IM
1
D6
C1IM
0
D5
DSCKE
0
D4
SAIFB
0
D3
SAI3
0
D2
SAI2
0
D1
SAI1
0
D0
SAI0
0
Serial data interface
The STA381BW audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. The STA381BW always acts as the slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and serial data 1 and 2 SDI12.
The SAI bits (D3 to D0) and the SAIFB bit (D4) are used to specify the serial data format.
The default serial data format is I 2 S, MSB-first. Available formats are shown in the tables that follow.
Serial audio input interface format
Bit
2
3
0
1
R/W
R/W
R/W
R/W
R/W
RST
0
0
0
0
Table 106. Serial audio input interface
Name Description
SAI0
SAI1
SAI2
SAI3
Determines the interface format of the input serial digital audio interface
7.2.3 Serial data first bit
SAIFB
0
1
Table 107. Serial data first bit
Format
MSB-first
LSB-first
DocID018835 Rev 8 111/174
Register description: Sound Terminal compatibility STA381BW
Table 108. Support serial audio input formats for MSB-first (SAIFB = 0)
BICKI SAI [3:0] SAIFB Interface format
32 * fs
48 * fs
64 * fs
0000
0001
0010
0110
1010
1110
0000
0001
0000
0001
0010
0110
1010
1110
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I
2
S 15-bit data
Left/right-justified 16-bit data
I
2
S 16- to 23-bit data
Left-justified 16- to 24-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
I
2
S 16- to 24-bit data
Left-justified 16- to 24-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
112/174 DocID018835 Rev 8
STA381BW Register description: Sound Terminal compatibility
Table 109. Supported serial audio input formats for LSB-first (SAIFB = 1)
BICKI SAI [3:0] SAIFB Interface format
32 * fs
48 * fs
64 * fs
1001
1101
0010
0110
1010
1110
0000
0100
1100
1110
0100
0100
1000
1100
0001
0101
1000
1100
0001
0101
1001
1101
0010
0110
1010
1110
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
2
S 15-bit data
Left/right-justified 16-bit data
I
2
S 23-bit data
I
2
S 20-bit data
I
2
S 18-bit data
LSB first I
2
S 16-bit data
Left-justified 24-bit data
Left-justified 20-bit data
Left-justified 18-bit data
Left-justified 16-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
I
2
S 24-bit data
I
2
S 20-bit data
I
2
S 18-bit data
LSB first I
2
S 16-bit data
Left-justified 24-bit data
Left-justified 20-bit data
Left-justified 18-bit data
Left-justified 16-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
To make the STA381BW work properly, the serial audio interface LRCKI clock must be synchronous to the PLL output clock which means that:
the frequency of PLL clock / frequency of LRCKI = N ±4 cycles, where N depends on the settings in
the PLL must be locked.
If these two conditions are not met, and the IDE bit (reg 0x05 bit 2) is set to 1, the
STA381BW will immediately mute the I 2 S PCM data out (provided to the processing block) and it will freeze any active processing task.
To avoid any audio side effects (like pop noise), it is strongly recommended to soft-mute any audio streams flowing into the STA381BW data path before the desynchronization event
DocID018835 Rev 8 113/174
Register description: Sound Terminal compatibility
Note:
7.2.4
STA381BW happens. At the same time any processing related to the I 2 C configuration should be issued only after the serial audio interface and the internal PLL are synchronous again.
Any mute or volume change causes some delay in the completion of the I 2 C operation due to the soft volume feature. The soft volume phase change must be finished before any clock desynchronization.
Delay serial clock enable
Bit
5
R/W
R/W
RST
0
Table 110. Delay serial clock enable
Name Description
DSCKE
0: No serial clock delay
1: Serial clock delay by 1 core clock cycle to tolerate anomalies in some I
2
S master devices
7.2.5 Channel input mapping
Bit
6
7
R/W
R/W
R/W
RST
0
1
Table 111. Channel input mapping
Name
C1IM
C2IM
Description
0: Processing channel 1 receives left I
2
1: Processing channel 1 receives right I
S input
2
S input
0: Processing channel 2 receives left I
2
1: Processing channel 2 receives right I
S input
2
S input
Each channel received via I
2
S can be mapped to any internal processing channel via the channel input mapping registers. This allows for flexibility in processing. The default settings of these registers map each I
2
S input channel to its corresponding processing channel.
114/174 DocID018835 Rev 8
STA381BW
7.3
7.3.1
Register description: Sound Terminal compatibility
Configuration register C (addr 0x02)
D7
Reserved
1
D6
Reserved
0
D5
CSZ3
0
D4
CSZ2
1
D3
CSZ1
0
D2
CSZ0
1
D1
Reserved
1
D0
Reserved
1
FFX compensating pulse size register
Bit
2
3
4
5
R/W
R/W
R/W
R/W
R/W
RST
Table 112. FFX compensating pulse size bits
Name Description
1
1
1
0
CSZ0
CSZ1
CSZ2
CSZ3
When OM[1,0] = 11, this register determines the size of the FFX compensating pulse from 0 clock ticks to
15 clock periods.
Table 6:
CSZ[3:0]
0000
0001
…
1111
Table 113. Compensating pulse size
Compensating pulse size
0 ns (0 ticks) compensating pulse size
20 ns (1 tick) clock period compensating pulse size
…
300 ns (15 ticks) clock period compensating pulse size
7.4 Configuration register D (addr 0x03)
D7
SME
0
D6
ZDE
0
D5
Reserved
0
D4
BQL
1
D3
PSL
1
D2
DSPB
0
D1
Reserved
0
D0
Reserved
0
Bit
2
R/W
R/W
RST
0
Table 114. DSP bypass
Name
DSPB
Description
0: Normal operation
1: Bypass of biquad and bass/treble functions
Setting the DSPB bit bypasses the EQ function of the STA381BW.
DocID018835 Rev 8 115/174
Register description: Sound Terminal compatibility STA381BW
7.4.3
7.4.4
7.4.5
Bit
3
R/W
R/W
RST
1
Table 115. Post-scale link
Name
PSL
Description
0: Each channel uses individual post-scale value
1: Each channel uses channel 1 post-scale value
Post-scale functionality can be used for power supply error correction. For multi-channel applications running off the same power supply, the post-scale values can be linked to the value of channel 1 for ease of use and in order to update the values faster.
Biquad coefficient link
Bit
4
R/W
R/W
RST
1
Table 116. Biquad coefficient link
Name Description
BQL
0: Each channel uses coefficient values
1: Each channel uses channel 1 coefficient values
For ease of use, all channels can use the biquad coefficients loaded into the channel-1 coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to be performed once.
Zero-detect mute enable
Bit
6
R/W
R/W
RST
0
Table 117. Zero-detect mute enable
Name Description
ZDE
Setting of 1 enables the automatic zero-detect mute
Setting of 0 disables the automatic zero-detect mute
Refer to 7.24: Enhanced zero-detect mute and input level measurement (address 0x50-
.
Submix mode enable
Bit
7
R/W
R/W
RST
0
Table 118. Submix mode enable
Name Description
SME
0: Submix into left/right disabled
1: Submix into left/right enabled
7.5
116/174
Configuration register E (addr 0x04)
D7
SVE
1
D6
ZCE
0
D5
Reserved
0
D4
PWMS
0
D3
AME
0
DocID018835 Rev 8
D2
NSBW
0
D1
Reserved
1
D0
Reserved
0
STA381BW
7.5.1
Register description: Sound Terminal compatibility
Noise-shaper bandwidth selection
Bit
2
R/W
R/W
RST
Table 119. Noise-shaper bandwidth selection
Name Description
0 NSBW
1: Third order NS
0: Fourth order NS
7.5.2
7.5.3
AM mode enable
Bit
3
R/W
R/W
RST
0
Table 120. AM mode enable
Name Description
AME
0: Normal FFX operation
1: AM reduction mode FFX operation
The STA381BW features an FFX processing mode that minimizes the amount of noise generated in the frequency range of AM radio. This mode is intended for use when FFX is operating in a device with an active AM tuner. The SNR of the FFX processing is reduced to approximately 83 dB in this mode, which is still greater than the SNR of AM radio.
PWM speed mode
Bit
4
R/W
R/W
RST
0
Table 121. PWM speed mode
Name Description
PWMS
0: Normal speed (384 kHz) all channels
1: Odd speed (341.3 kHz) all channels. Not suitable for binary BTL mode.
7.5.5
Bit
6
R/W
R/W
RST
0
Table 122. Zero-crossing enable
Name Description
ZCE
1: Volume adjustments only occur at digital zero-crossing
0: Volume adjustments occur immediately
The ZCE bit enables zero-crossing adjustment. When volume is adjusted on digital zerocrossing, no clicks are audible.
Soft volume update enable
Bit
7
R/W
R/W
RST
1
Table 123. Soft volume update enable
Name Description
SVE
1: Volume adjustments ramp according to SVR settings
0: Volume adjustments occur immediately
DocID018835 Rev 8 117/174
Register description: Sound Terminal compatibility
7.6 Configuration register F (addr 0x05)
D7
EAPD
0
D6
PWDN
1
D5
Reserved
0
D4
LDTE
1
D3
BCLE
1
STA381BW
D2
IDE
1
D1
OCFG1
0
D0
OCFG0
0
Note:
Bit
0
1
R/W
R/W
R/W
RST
0
0
Table 124. Output configuration
Name Description
OCFG0
OCFG1
Selects the output configuration
OCFG[1:0]
00
01
10
11
Table 125. Output configuration engine selection
Output configuration
2-channel (full-bridge) power, 2-channel data-out:
1A/1B 1A/1B
2A/2B 2A/2B
LineOut1 3A/3B
LineOut2 4A/4B
Line Out configuration determined by LOC register
2(half-bridge).1(full-bridge) on-board power:
1A 1A Binary 0 °
2A 1B Binary 90°
3A/3B 2A/2B Binary 45°
1A/B 3A/B Binary 0°
2A/B 4A/B Binary 90°
2-channel (full-bridge) power, 1-channel FFX:
1A/1B 1A/1B
2A/2B 2A/2B
3A/3B 3A/3B
EAPDEXT and TWARNEXT active
1-channel mono-parallel:
3A 1A/1B w/ C3BO 45°
3B 2A/2B w/ C3BO 45°
1A/1B 3A/3B
2A/2B 4A/4B
PBTL enable
No
No
No
Yes
To the left of the arrow is the processing channel. When using channel output mapping, any of the three processing channel outputs can be used for any of the three inputs.
118/174 DocID018835 Rev 8
STA381BW Register description: Sound Terminal compatibility
Figure 33. OCFG = 00 (default value)
Figure 34. OCFG = 01
Figure 35. OCFG = 10
DocID018835 Rev 8 119/174
Register description: Sound Terminal compatibility
Figure 36. OCFG = 11
STA381BW
The STA381BW can be configured to support different output configurations. For each
PWM output channel a PWM slot is defined. A PWM slot is always 1 / (8 * fs) seconds length. The PWM slot defines the maximum extension for the PWM rising and falling edge, that is, the rising edge as well as the falling edge cannot range outside the PWM slot boundaries.
Figure 37. Output mapping scheme
120/174 DocID018835 Rev 8
STA381BW Register description: Sound Terminal compatibility
For each configuration the PWM signals from the digital driver are mapped in different ways to the power stage:
2.0 channels, two full-bridges (OCFG = 00)
FFX1A -> OUT1A
FFX1B -> OUT1B
FFX2A -> OUT2A
FFX2B -> OUT2B
FFX3A -> OUT3A
FFX3B -> OUT3B
FFX4A -> OUT4A
FFX4B -> OUT4B
FFX1A/1B configured as C1B0 (default: ternary)
FFX2A/2B configured as C2B0 (default: ternary)
FFX3A/3B configured as C3B0 (default: ternary) line out
FFX4A/4B configured as C4B0 (default: ternary) line out
On channel 3 line out (LOC bits = 00) the same data as channel 1 processing is sent. On channel 4 line out (LOC bits = 00) the same data as channel 2 processing is sent. In this configuration, neither volume control nor EQ has any effect on channels 3 and 4.
In this configuration the PWM slot phase is the following as shown in
Figure 38. 2.0 channels (OCFG = 00) PWM slots
DocID018835 Rev 8 121/174
Register description: Sound Terminal compatibility STA381BW
2.1 channels, two half-bridges + one full-bridge (OCFG = 01)
FFX1A -> OUT1A
FFX2A -> OUT1B
FFX3A -> OUT2A
FFX3B -> OUT2B
FFX1A -> OUT3A
FFX1B -> OUT3B
FFX2A -> OUT4A
FFX2B -> OUT4B
FFX1A/1B configured as binary
FFX2A/2B configured as binary
FFX3A/3B configured as binary
FFX4A/4B is not used
In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT3/OUT4 channels channel 1 and channel 2 PWM are replicated.
In this configuration the PWM slot phase is the following as shown in
Figure 39. 2.1 channels (OCFG = 01) PWM slots
122/174 DocID018835 Rev 8
STA381BW Register description: Sound Terminal compatibility
2.1 channels, two full-bridges + one external full-bridge (OCFG = 10)
FFX1A -> OUT1A
FFX1B -> OUT1B
FFX2A -> OUT2A
FFX2B -> OUT2B
FFX3A -> OUT3A
FFX3B -> OUT3B
EAPD -> OUT4A
TWARN -> OUT4B
FFX1A/1B configured as C1B0 (default: ternary)
FFX2A/2B configured as C2B0 (default: ternary)
FFX3A/3B configured as C3B0 (default: ternary)
FFX4A/4B is not used
In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT4 channel the external bridge control signals are muxed.
In this configuration the PWM slot phase is the following as shown in
Figure 40. 2.1 channels (OCFG = 10) PWM slots
DocID018835 Rev 8 123/174
Register description: Sound Terminal compatibility
7.6.2
7.6.3
Invalid input detect mute enable
Bit
2
R/W RST
R/W 1
STA381BW
Table 126. Invalid input detect mute enable
Name Description
IDE Setting of 1 enables the automatic invalid input detect mute
Setting the IDE bit enables this function, which looks at the input I
2
S data and automatically mutes if the signals are perceived as invalid.
Binary output mode clock loss detection
Bit
3
Table 127. Binary output mode clock loss detection
R/W RST Name Description
R/W 1 BCLE Binary output mode clock loss detection enable
7.6.4
This bit detects loss of input MCLK in binary mode and will output 50% duty cycle.
LRCK double trigger protection
Bit R/W RST
4 R/W 1
Table 128. LRCK double trigger protection
Name Description
LDTE LRCLK double trigger protection enable
This bit actively prevents double triggering of LRCLK.
7.6.6
Bit
7
R/W
R/W
RST
1
Name
Table 129. IC power-down
Description
PWDN
0: IC power-down low-power condition
1: IC normal operation
The PWDN register is used to place the IC in a low-power state. When PWDN is written as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted
I to power down the power stage, then the master clock to all internal hardware except the
2
C block is gated. This places the IC in a very low power consumption state.
External amplifier power-down
Bit
7
R/W
R/W
RST
Table 130. External amplifier power-down
Name Description
0 EAPD
0: External power stage power-down active
1: Normal operation
124/174 DocID018835 Rev 8
STA381BW Register description: Sound Terminal compatibility
The EAPD register directly disables/enables the internal power circuitry.
When EAPD = 0, the internal power section is placed in a low-power state (disabled). This register also controls the EAPD/FFX4B output pin when OCFG = 10.
7.7
7.7.1
Volume control registers (addr 0x06 - 0x0A)
Mute/line output configuration register
D7
LOC1
0
LOC[1:0]
00
01
10
11
D6
LOC0
0
D5
Reserved
0
D4
BQBALL
0
D3
C3M
0
D2
C2M
0
Table 131. Line output configuration
Line output configuration
Line output fixed - no volume, no EQ
Line output variable - CH3 volume effects line output, no EQ
Line output variable with EQ - CH3 volume effects line output
Reserved
D1
C1M
0
D0
MMUTE
0
Line output is only active when OCFG = 00. In this case LOC determines the line output configuration. The source of the line output is always channel 1 and 2 inputs.
Bit R/W RST
4 R/W 0
Bit R/W RST
3 R/W 0
2 R/W 0
Name
BQBALL
Description
Global biquad bypass
0: Biquad filters active
1: All the biquad filters are bypassed (pass-through)
Table 132. Mute configuration
Name Description
C3M
C2M
Channel 3 mute
0 - No mute condition. It is possible to set the channel volume
1 - Channel 3 in hardware mute
Channel 2 mute
0 - No mute condition. It is possible to set the channel volume
1 - Channel 2 in hardware mute
DocID018835 Rev 8 125/174
Register description: Sound Terminal compatibility STA381BW
7.7.2
7.7.3
7.7.4
7.7.5
Bit R/W RST
1
0
R/W
R/W
0
0
Name
C1M
MMUTE
Description
Channel 1 mute
0 - No mute condition. It is possible to set the channel volume
1 - Channel 1 in hardware mute
Master mute
0 - Normal operation
1 - All channels are in mute condition
Master volume register
D7 D6 D5 D4
MVOL[7:0]
D3
1 1
D2 D1 D0
1 1
Channel 1 volume
D7 D6
1 1 1 1
D5 D4
CH1VOL[7:0]
D3
0 0
D2 D1 D0
0 1
Channel 2 volume
D7 D6
1 0 0 0
0 1
D5
1
D4
CH2VOL[7:0]
D3
0 0
D2
0
D1
0
D0
0
Channel 3 / line output volume
D7
0
D6
1
D5
1
D4
CH3VOL[7:0]
D3
0 0
D2
0
D1
0
D0
0
The volume structure of the STA381BW consists of individual volume registers for each channel and a master volume register that provides an offset to each channel’s volume setting. The individual channel volumes are adjustable in 0.5 dB steps from +48 dB to
-80 dB.
As an example if CH3VOL = 0x00 or +48 dB and MVOL = 0x18 or -12 dB, then the total gain for channel 3 = +36 dB.
The master mute, when set to 1, mutes all channels at once, whereas the individual channel mute (CxM) mutes only that channel. Both the master mute and the channel mutes provide a “soft mute” with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (approximately 96 kHz).
A “hard (instantaneous) mute” can be obtained by programming a value of 0xFF (255) to any channel volume register or the master volume register. When volume offsets are
126/174 DocID018835 Rev 8
STA381BW Register description: Sound Terminal compatibility provided via the master volume register, any channel whose total volume is less than -80 dB is muted.
All changes in volume take place at zero-crossings when ZCE = 1 (
(addr 0x04) ) on a per-channel basis as this creates the smoothest possible volume
transitions. When ZCE = 0, volume updates occur immediately.
Table 133. Master volume offset as a function of MVOL[7:0]
MVOL[7:0] Volume offset from channel value
00000000 (0x00)
00000001 (0x01)
00000010 (0x02)
…
01001100 (0x4C)
…
11111110 (0xFE)
11111111 (0xFF)
0 dB
-0.5 dB
-1 dB
…
-38 dB
…
-127.5 dB
Hard master mute
Table 134. Channel volume as a function of CxVOL[7:0]
CxVOL[7:0] Volume
00000000 (0x00)
00000001 (0x01)
00000010 (0x02)
…
01011111 (0x5F)
01100000 (0x60)
01100001 (0x61)
…
11010111 (0xD7)
11011000 (0xD8)
11011001 (0xD9)
11011010 (0xDA)
…
11101100 (0xEC)
11101101 (0xED)
…
11111111 (0xFF)
+48 dB
+47.5 dB
+47 dB
…
+0.5 dB
0 dB
-0.5 dB
…
-59.5 dB
-60 dB
-61 dB
-62 dB
…
-80 dB
Hard channel mute
…
Hard channel mute
7.8
7.8.1
Audio preset registers (addr 0x0C)
Audio preset register (addr 0x0C)
D7
XO3
D6
XO2
D5
XO1
D4
XO0
D3
AMAM2
D2
AMAM1
D1
AMAM0
D0
AMAME
DocID018835 Rev 8 127/174
Register description: Sound Terminal compatibility
7.8.2
7.8.3
STA381BW
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
AM interference frequency switching
Bit
0
R/W
R/W
Table 135. AM interference frequency switching bits
RST Name Description
0 AMAME
Audio preset AM enable
0: switching frequency determined by PWMS setting
1: switching frequency determined by AMAM settings
Table 136. Audio preset AM switching frequency selection
AMAM[2:0] 48 kHz/96 kHz input fs 44.1 kHz/88.2 kHz input fs
000
001
010
011
100
101
110
0.535 MHz - 0.720 MHz
0.721 MHz - 0.900 MHz
0.901 MHz - 1.100 MHz
1.101 MHz - 1.300 MHz
1.301 MHz - 1.480 MHz
1.481 MHz - 1.600 MHz
1.601 MHz - 1.700 MHz
0.535 MHz - 0.670 MHz
0.671 MHz - 0.800 MHz
0.801 MHz - 1.000 MHz
1.001 MHz - 1.180 MHz
1.181 MHz - 1.340 MHz
1.341 MHz - 1.500 MHz
1.501 MHz - 1.700 MHz
Bass management crossover
Bit
6
7
4
5
R/W
R/W
R/W
R/W
R/W
RST
0
0
0
0
Table 137. Bass management crossover
Name Description
XO0
XO1
XO2
XO3
Selects the bass management crossover frequency.
A 1 st
-order high-pass filter (channels 1 and 2) or a
2 nd
-order low-pass filter (channel 3) at the selected frequency is performed.
128/174 DocID018835 Rev 8
STA381BW Register description: Sound Terminal compatibility
XO[3:0]
Table 138. Bass management crossover frequency
Crossover frequency
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
220 Hz
240 Hz
260 Hz
280 Hz
300 Hz
320 Hz
340 Hz
360 Hz
User-defined
80 Hz
100 Hz
120 Hz
140 Hz
160 Hz
180 Hz
200 Hz
7.9
7.9.1
Channel configuration registers (addr 0x0E - 0x10)
D7
C1OM1
0
D7
C2OM1
0
D7
C3OM1
1
D6
C1OM0
0
D6
C2OM0
1
D6
C3OM0
0
D5
C1LS1
0
D5
C2LS1
0
D5
C3LS1
0
D4
C1LS0
0
D4
C2LS0
0
D4
C3LS0
0
D3
C1BO
0
D3
C2BO
0
D3
C3BO
0
D2
C1VPB
0
D2
C2VPB
0
D2
C3VPB
0
D1
C1EQBP
0
D1
C2EQBP
0
D1
Reserved
0
D0
C1TCB
0
D0
C2TCB
0
D0
Reserved
0
Tone control bypass
Tone control (bass/treble) can be bypassed on a per-channel basis for channels 1 and 2.
CxTCB
0
1
Table 139. Tone control bypass
Mode
Perform tone control on channel x - normal operation
Bypass tone control on channel x
DocID018835 Rev 8 129/174
Register description: Sound Terminal compatibility STA381BW
EQ control can be bypassed on a per-channel basis for channels 1 and 2. If EQ control is bypassed on a given channel, the prescale and all filters (biquads, bass, treble in any combination) are bypassed for that channel.
CxEQBP
0
1
Table 140. EQ bypass
Mode
Perform EQ on channel x - normal operation
Bypass EQ on channel x
7.9.4
Each channel contains an individual channel volume bypass. If a particular channel has volume bypassed via the CxVBP = 1 register, then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel.
CxVBP
0
1
Table 141. Volume bypass register
Mode
Normal volume operations
Volume is bypassed
Binary output enable registers
Each individual channel output can be set to output a binary PWM stream. In this mode output A of a channel is considered the positive output and output B is the negative inverse.
CxBO
0
1
Table 142. Binary output enable registers
Mode
FFX 3-state output - normal operation
Binary output
Limiter selection can be made on a per-channel basis according to the channel limiter select bits. CxLS bits are considered in case of dual-band DRC and EQDRC usage (
).
Table 143. Channel limiter mapping as a function of CxLS bits
CxLS[1:0] Channel limiter mapping
00
01
10
Channel has limiting disabled
Channel is mapped to limiter #1
Channel is mapped to limiter #2
130/174 DocID018835 Rev 8
STA381BW Register description: Sound Terminal compatibility
Output mapping can be performed on a per-channel basis according to the CxOM channel output mapping bits. Each input into the output configuration engine can receive data from any of the three processing channel outputs.
.
Table 144. Channel output mapping as a function of CxOM bits
CxOM[1:0] Channel x output source from
00
01
10
Channel1
Channel 2
Channel 3
7.10 Tone control register (addr 0x11)
D7
TTC3
0
D6
TTC2
1
D5
TTC1
1
D4
TTC0
1
D3
BTC3
0
D2
BTC2
1
D1
BTC1
1
D0
BTC0
1
Table 145. Tone control boost/cut as a function of BTC and TTC bits
BTC[3:0]/TTC[3:0] Boost/cut
0000
0001
…
0111
0110
0111
1000
1001
…
1101
1110
1111
-12 dB
-12 dB
…
-4 dB
-2 dB
0 dB
+2 dB
+4 dB
…
+12 dB
+12 dB
+12 dB
DocID018835 Rev 8 131/174
Register description: Sound Terminal compatibility STA381BW
7.11 Dynamic control registers (addr 0x12 - 0x15)
7.11.1 Limiter 1 attack/release rate
D7
L1A3
0
D6
L1A2
1
D5
L1A1
1
D4
L1A0
0
D3
L1R3
1
D2
L1R2
0
D1
L1R1
1
D0
L1R0
0
7.11.2 Limiter 1 attack/release threshold
D7
L1AT3
0
D6
L1AT2
1
D5
L1AT1
1
D4
L1AT0
0
7.11.3 Limiter 2 attack/release rate
D7
L2A3
0
D6
L2A2
1
D5
L2A1
1
D4
L2A0
0
D3
L1RT3
1
D2
L1RT2
0
D1
L1RT1
0
D0
L1RT0
1
D3
L2R3
1
D2
L2R2
0
D1
L2R1
1
D0
L2R0
0
7.11.4 Limiter 2 attack/release threshold
D7
L2AT3
0
D6
L2AT2
1
D5
L2AT1
1
D4
L2AT0
0
D3
L2RT3
1
D2
L2RT2
0
D1
L2RT1
0
D0
L2RT0
1
The STA381BW includes two independent limiter blocks (not to be mistaken with the
STCompressor TM , for further details about this feature please refer to
purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anticlipping mode or to actively reduce the dynamic range for a better listening environment such as a nighttime listening mode which is often needed for DVDs. The two modes are selected via the DRC bit in
(addr 0x04) on page 116 . Each channel can be mapped to either limiter or not mapped,
meaning that the channel will clip when 0 dBfs is exceeded. Each limiter looks at the present value of each channel that is mapped to it, selects the maximum absolute value of all these channels, performs the limiting algorithm on that value, and then, if needed, adjusts the gain of the mapped channels in unison.
The limiter attack thresholds are determined by the LxAT registers if the EATHx[7] bits are set to 0, else the thresholds are determined by EATHx[6:0]. It is recommended in anticlipping mode to set this to 0 dBfs, which corresponds to the maximum unclipped output power of an FFX amplifier. Since gain can be added digitally within the STA381BW, it is possible to exceed 0 dBfs or any other LxAT setting. When this occurs, the limiter, when active, automatically starts reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. Gain reduction occurs on a peak-detect algorithm. Setting the EATHx[7] bits to 1 selects the anticlipping mode.
The limiter release thresholds are determined by the LxRT registers if the ERTHx[7] bits are set to 0, else the thresholds are determined by ERTHx[6:0]. Settings the ERTHx[7] bits to 1
132/174 DocID018835 Rev 8
STA381BW Register description: Sound Terminal compatibility automatically selects the anticlipping mode. The release of the limiter, when the gain is again increased, is dependent on an RMS-detect algorithm. The output of the volume/limiter block is passed through an RMS filter. The output of this filter is compared to the release threshold, determined by the release threshold register. When the RMS filter output falls below the release threshold, the gain is again increased at a rate dependent upon the release rate register. The gain can never be increased past its set value and, therefore, the release only occurs if the limiter has already reduced the gain. The release threshold value can be used to set what is effectively a minimum dynamic range, this is helpful as overlimiting can reduce the dynamic range to virtually zero and cause program material to sound “lifeless”.
In AC mode, the attack and release thresholds are set relative to full-scale. In DRC mode, the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter, and the release threshold is set relative to the maximum volume setting plus the attack threshold.
DocID018835 Rev 8 133/174
Register description: Sound Terminal compatibility
Figure 41. Basic limiter and volume flow diagram
RMS
Limiter
STA381BW
Gain / Vo lume
+
In p ut
Gain
Table 146. Limiter attack rate as a function of LxA bits
LxA[3:0]
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
Attack rate dB/ms
0.2256
0.1504
0.1123
0.0902
0.0752
0.0645
0.0564
0.0501
0.0451
3.1584
2.7072
2.2560
1.8048
1.3536
0.9024
0.4512
Fast
Slow
Atten uatio n Saturatio n
Outp ut
Table 147. Limiter release rate as a function of LxR bits
LxR[3:0] Release rate dB/ms
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0.0208
0.0198
0.0172
0.0147
0.0137
0.0134
0.0117
0.0110
0.0104
0.5116
0.1370
0.0744
0.0499
0.0360
0.0299
0.0264
Fast
Slow
134/174 DocID018835 Rev 8
STA381BW Register description: Sound Terminal compatibility
Anticlipping mode
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
Table 148. Limiter attack threshold as a function of LxAT bits (AC mode)
LxAT[3:0] AC (dB relative to fs)
-12
-10
-8
-6
0000
0001
0010
0011
-4
-2
0100
0101
0 0110
+2 0111
+3
+4
+5
+6
1000
1001
1010
1011
+7
+8
1100
1101
+9 1110
+10 1111
Table 149. Limiter release threshold as a function of LxRT bits (AC mode)
LxRT[3:0] AC (dB relative to fs)
-29 dB
-20 dB
-16 dB
-14 dB
-12 dB
-8 dB
-7 dB
-6 dB
-5 dB
-4 dB
-3 dB
-2 dB
-0 dB
DocID018835 Rev 8 135/174
Register description: Sound Terminal compatibility
Dynamic range compression mode
Table 150. Limiter attack threshold as a function of LxAT bits (DRC mode)
LxAT[3:0] DRC (dB relative to volume)
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
-12
-10
-7
-4
-16
-15
-14
-13
-23
-21
-19
-17
-31
-29
-27
-25
STA381BW
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
Table 151. Limiter release threshold as a function of LxRT bits (DRC mode)
LxRT[3:0]
DRC (db relative to volume +
LxAT)
-24 dB
-22 dB
-20 dB
-18 dB
-15 dB
-12 dB
-9 dB
-6 dB
-38 dB
-36 dB
-33 dB
-31 dB
-30 dB
-28 dB
-26 dB
7.11.5 Limiter 1 extended attack threshold (addr 0x32)
D7
EATHEN1
0
D6
EATH1[6]
0
D5
EATH1[5]
1
D4
EATH1[4]
1
D3
EATH1[3]
0
D2
EATH1[2]
0
The extended attack threshold value is determined as follows: attack threshold = -12 + EATH1 / 4
To enable this feature, the EATHEN1 bit must be set to 1.
7.11.6 Limiter 1 extended release threshold (addr 0x33)
D7
ERTHEN1
0
D6
ERTH1[6]
0
D5
ERTH1[5]
1
D4
ERTH1[4]
1
D3
ERTH1[3]
0
D2
ERTH1[2]
0
The extended release threshold value is determined as follows: release threshold = -12 + ERTH1 / 4
To enable this feature, the ERTHEN2 bit must be set to 1.
D1
EATH1[1]
0
D1
ERTH1[1]
0
D0
EATH1[0]
0
D0
ERTH1[0]
0
136/174 DocID018835 Rev 8
STA381BW Register description: Sound Terminal compatibility
7.11.7 Limiter 2 extended attack threshold (addr 0x34)
D7
EATHEN2
0
D6
EATH2[6]
0
D5
EATH2[5]
1
D4
EATH2[4]
1
D3
EATH2[3]
0
D2
EATH2[2]
0
The extended attack threshold value is determined as follows: attack threshold = -12 + EATH2 / 4
To enable this feature, the EATHEN2 bit must be set to 1.
D1
EATH2[1]
0
7.11.8 Limiter 2 extended release threshold (addr 0x35)
Note:
D7
ERTHEN2
0
D6
ERTH2[6]
0
D5
ERTH2[5]
1
D4
ERTH2[4]
1
D3
ERTH2[3]
0
D2
ERTH2[2]
0
The extended release threshold value is determined as follows: release threshold = -12 + ERTH2 / 4
To enable this feature, the ERTHEN2 bit must be set to 1.
Attack/release threshold step is 0.125 dB in the range -12 dB to 0 dB.
D1
ERTH2[1]
0
D0
EATH2[0]
0
D0
ERTH2[0]
0
7.12 User-defined coefficient control registers (addr 0x16 - 0x26)
7.12.1 Coefficient address register
D7
Reserved
0
D6
Reserved
0
D5
CFA5
0
D4
CFA4
0
D3
CFA3
0
D2
CFA2
0
D1
CFA1
0
D0
CFA0
0
7.12.2 Coefficient b1 data register bits 23:16
D7
C1B23
0
D6
C1B22
0
D5
C1B21
0
D4
C1B20
0
D3
C1B19
0
7.12.3 Coefficient b1 data register bits 15:8
D7
C1B15
0
D6
C1B14
0
D5
C1B13
0
D4
C1B12
0
D3
C1B11
0
7.12.4 Coefficient b1 data register bits 7:0
D7
C1B7
0
D6
C1B6
0
D5
C1B5
0
D4
C1B4
0
D3
C1B3
0
D2
C1B18
0
D2
C1B10
0
D2
C1B2
0
D1
C1B17
0
D1
C1B9
0
D1
C1B1
0
D0
C1B16
0
D0
C1B8
0
D0
C1B0
0
DocID018835 Rev 8 137/174
Register description: Sound Terminal compatibility
7.12.5 Coefficient b2 data register bits 23:16
D7
C2B23
0
D6
C2B22
0
D5
C2B21
0
D4
C2B20
0
D3
C2B19
0
7.12.6 Coefficient b2 data register bits 15:8
D7
C2B15
0
D6
C2B14
0
D5
C2B13
0
D4
C2B12
0
D3
C2B11
0
7.12.7 Coefficient b2 data register bits 7:0
D7
C2B7
0
D6
C2B6
0
D5
C2B5
0
D4
C2B4
0
D3
C2B3
0
7.12.8 Coefficient a1 data register bits 23:16
D7
C1B23
0
D6
C1B22
0
D5
C1B21
0
D4
C1B20
0
D3
C1B19
0
7.12.9 Coefficient a1 data register bits 15:8
D7
C3B15
0
D6
C3B14
0
D5
C3B13
0
D4
C3B12
0
D3
C3B11
0
7.12.10 Coefficient a1 data register bits 7:0
D7
C3B7
0
D6
C3B6
0
D5
C3B5
0
D4
C3B4
0
D3
C3B3
0
7.12.11 Coefficient a2 data register bits 23:16
D7
C4B23
0
D6
C4B22
0
D5
C4B21
0
D4
C4B20
0
D3
C4B19
0
D2
C2B18
0
D1
C2B17
0
D0
C2B16
0
D2
C2B10
0
D2
C2B2
0
D2
C3B10
0
D2
C3B2
0
D1
C2B9
0
D1
C2B1
0
D1
C3B9
0
D1
C3B1
0
STA381BW
D0
C2B8
0
D0
C2B0
0
D2
C1B18
0
D1
C1B17
0
D0
C1B16
0
D0
C3B8
0
D0
C3B0
0
D2
C4B18
0
D1
C4B17
0
D0
C4B16
0
138/174 DocID018835 Rev 8
STA381BW Register description: Sound Terminal compatibility
7.12.12 Coefficient a2 data register bits 15:8
D7
C4B15
0
D6
C4B14
0
D5
C4B13
0
D4
C4B12
0
D3
C4B11
0
7.12.13 Coefficient a2 data register bits 7:0
D7
C4B7
0
D6
C4B6
0
D5
C4B5
0
D4
C4B4
0
D3
C4B3
0
7.12.14 Coefficient b0 data register bits 23:16
D7
C5B23
0
D6
C5B22
0
D5
C5B21
0
D4
C5B20
0
D3
C5B19
0
D2
C4B10
0
D2
C4B2
0
D1
C4B9
0
D1
C4B1
0
D0
C4B8
0
D0
C4B0
0
D2
C5B18
0
D1
C5B17
0
D0
C5B16
0
7.12.15 Coefficient b0 data register bits 15:8
D7
C5B15
0
D6
C5B14
0
D5
C5B13
0
D4
C5B12
0
D3
C5B11
0
7.12.16 Coefficient b0 data register bits 7:0
D7
C5B7
0
D6
C5B6
0
D5
C5B5
0
D4
C5B4
0
D3
C5B3
0
D2
C5B10
0
D1
C5B9
0
D0
C5B8
0
D2
C5B2
0
D1
C5B1
0
D0
C5B0
0
7.12.17 Coefficient write/read control register
Note:
D7 D6
Reserved
D5 D4 D3
RA
D2
R1
D1
WA
D0
W1
0 0 0 0 0
Coefficients for user-defined EQ, mixing, scaling, bass management and STCompressor TM
) are handled internally in the STA381BW via RAM. Access to this RAM is available to the user via an I 2 C register interface. A collection of I 2 C registers are dedicated to this function. One contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write/read of the coefficient(s) to/from RAM.
The read and write operation on RAM coefficients works only if LRCKI (pin 29) is switching.
DocID018835 Rev 8 139/174
Register description: Sound Terminal compatibility
Reading a coefficient from RAM
1.
Write 6 bits of the address to I 2 C register 0x16.
2. Write 1 to the R1 bit in I
2
C address 0x26.
3. Read the top 8 bits of the coefficient in I 2 C address 0x17.
4. Read the middle 8 bits of the coefficient in I
2
C address 0x18.
5. Read the bottom 8 bits of the coefficient in I 2 C address 0x19.
Reading a set of coefficients from RAM
1.
Write 6 bits of the address to I 2 C register 0x16.
2. Write 1 to the RA bit in I
2
C address 0x26.
3. Read the top 8 bits of the coefficient in I 2 C address 0x17.
4. Read the middle 8 bits of the coefficient in I
2
C address 0x18.
5. Read the bottom 8 bits of the coefficient in I 2 C address 0x19.
6. Read the top 8 bits of coefficient b2 in I
2
C address 0x1A.
7. Read the middle 8 bits of coefficient b2 in I 2 C address 0x1B.
8. Read the bottom 8 bits of coefficient b2 in I
2
C address 0x1C.
9. Read the top 8 bits of coefficient a1 in I 2 C address 0x1D.
10. Read the middle 8 bits of coefficient a1 in I
2
C address 0x1E.
11. Read the bottom 8 bits of coefficient a1 in I 2 C address 0x1F.
12. Read the top 8 bits of coefficient a2 in I
2
C address 0x20.
13. Read the middle 8 bits of coefficient a2 in I 2 C address 0x21.
14. Read the bottom 8 bits of coefficient a2 in I
2
C address 0x22.
15. Read the top 8 bits of coefficient b0 in I 2 C address 0x23.
16. Read the middle 8 bits of coefficient b0 in I
2
C address 0x24.
17. Read the bottom 8 bits of coefficient b0 in I 2 C address 0x25.
Writing a single coefficient to RAM
1.
Write 6 bits of the address to I 2 C register 0x16.
2. Write the top 8 bits of the coefficient in I
2
C address 0x17.
3. Write the middle 8 bits of the coefficient in I 2 C address 0x18.
4. Write the bottom 8 bits of the coefficient in I
2
C address 0x19.
5. Write 1 to the W1 bit in I 2 C address 0x26.
STA381BW
140/174 DocID018835 Rev 8
STA381BW Register description: Sound Terminal compatibility
Writing a set of coefficients to RAM
1.
Write 6 bits of the starting address to I 2 C register 0x16.
2. Write the top 8 bits of coefficient b1 in I
2
C address 0x17.
3. Write the middle 8 bits of coefficient b1 in I 2 C address 0x18.
4. Write the bottom 8 bits of coefficient b1 in I
2
C address 0x19.
5. Write the top 8 bits of coefficient b2 in I 2 C address 0x1A.
6. Write the middle 8 bits of coefficient b2 in I
2
C address 0x1B.
7. Write the bottom 8 bits of coefficient b2 in I 2 C address 0x1C.
8. Write the top 8 bits of coefficient a1 in I
2
C address 0x1D.
9. Write the middle 8 bits of coefficient a1 in I 2 C address 0x1E.
10. Write the bottom 8 bits of coefficient a1 in I
2
C address 0x1F.
11. Write the top 8 bits of coefficient a2 in I 2 C address 0x20.
12. Write the middle 8 bits of coefficient a2 in I
2
C address 0x21.
13. Write the bottom 8 bits of coefficient a2 in I 2 C address 0x22.
14. Write the top 8 bits of coefficient b0 in I
2
C address 0x23.
15. Write the middle 8 bits of coefficient b0 in I 2 C address 0x24.
16. Write the bottom 8 bits of coefficient b0 in I
2
C address 0x25.
17. Write 1 to the WA bit in I 2 C address 0x26.
The mechanism for writing a set of coefficients to RAM provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side effects. When using this technique, the 6-bit address specifies the address of the biquad b1 coefficient (for example, 0, 5, 10, 20, 35 decimal), and the
STA381BW generates the RAM addresses as offsets from this base value to write the complete set of coefficient data.
DocID018835 Rev 8 141/174
Register description: Sound Terminal compatibility STA381BW
The STA381BW can be programmed for four EQ filters (biquads) per each of the two input channels. The biquads use the following equation:
Y[n] = 2 * (b
0
/ 2) * X[n] + 2 * (b
1
/ 2) * X[n-1] + b
2
* X[n-2] - 2 * (a
1
/ 2) * Y[n-1] - a
2
* Y[n-2]
= b
0
* X[n] + b
1
* X[n-1] + b
2
* X[n-2] - a
1
* Y[n-1] - a
2
* Y[n-2] where Y[n] represents the output and X[n] represents the input. Multipliers are 24-bit signed fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF
(0.9999998808).
Coefficients stored in the user-defined coefficient RAM are referenced in the following manner:
CxHy0 = b
1
/ 2
CxHy1 = b
2
CxHy2 = -a
1
/ 2
CxHy3 = -a
2
CxHy4 = b
0
/ 2 where x represents the channel and y the biquad number. For example, C2H41 is the b
2 coefficient in the fourth biquad for channel 2.
Additionally, the STA381BW can be programmed for a high-pass filter (processing channels 1 and 2) and a low-pass filter (processing channel 3) to be used for bass management crossover when the XO setting is 000 (user-defined). Both of these filters, when defined by the user (rather than using the preset crossover filters), are second order filters that use the biquad equation given above. They are loaded into the C12H0-4 and
C3Hy0-4 areas of RAM noted in
.
Channel 1 and channel 2 biquads use by default the extended coefficient range (-4, +4);
Xover filters use only the standard coefficients range (-1, +1).
By default, all user-defined filters are pass-through where all coefficients are set to 0, except the channel 1 and 2 b
0 b
0
/2 coefficient which is set to 0x100000 (representing 0.5) and xover
/2 coefficient which is set to 0x400000 (representing 0.5).
7.12.19 Pre-scale
The STA381BW provides a multiplication for each input channel for the purpose of scaling the input prior to EQ. This pre-EQ scaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiplication is loaded into RAM using the same I 2 C registers as the biquad coefficients and the bass management. All channels can use the channel-1 pre-scale factor by setting the biquad link bit. By default, all pre-scale factors are set to 0x7FFFFF.
7.12.20 Post-scale
The STA381BW provides one additional multiplication after the last interpolation stage and the distortion compensation on each channel. This post-scaling is accomplished by using a
24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiplication is loaded into RAM using the same I
2
C registers as the biquad coefficients and the bass management. This post-scale factor can be used in conjunction with an ADC-equipped microcontroller to perform power-supply error correction.
All channels can use the channel-1 post-scale factor by setting the post-scale link bit. By
142/174 DocID018835 Rev 8
STA381BW Register description: Sound Terminal compatibility default, all post-scale factors are set to 0x7FFFFF. When line output is being used, channel-3 post-scale will affect both channels 3 and 4.
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x3C
0x3D
0x3E
0x3F
0x14
0x15
…
0x27
0x28
0x29
0x2A
0x2B
0x00
0x01
0x02
0x03
0x04
0x05
…
0x13
Table 152. RAM block for biquads, mixing, scaling and bass management
Index (decimal) Index (hex) Description Coefficient Default
56
57
58
59
52
53
54
55
60
61
62
63
48
49
50
51
44
45
46
47
40
41
42
43
20
21
…
39
4
5
…
19
2
3
0
1
Channel 1 - Biquad 1
Channel 1 - Biquad 2
…
Channel 1 - Biquad 4
Channel 2 - Biquad 1
…
Channel 2 - Biquad 4
Channel 1/2 - Biquad 5 for XO = 000
High-pass 1 st
order filter for XO 000
Channel 3 - Biquad for XO = 000
Low-pass 2 nd
order filter for XO 000
Channel 1 - Pre-Scale
Channel 2 - Pre-Scale
Channel 1 - Post-Scale
Channel 2 - Post-Scale
Channel 3 - Post-Scale
Reserved
Channel 1 - Mix 1
Channel 1 - Mix 2
Channel 2 - Mix 1
Channel 2 - Mix 2
Channel 3 - Mix 1
Channel 3 - Mix 2
UNUSED
UNUSED
C12H4(b0/2)
C3H0(b1/2)
C3H1(b2)
C3H2(a1/2)
C3H3(a2)
C3H4(b0/2)
C1PreS
C2PreS
C1PstS
C2PstS
C3PstS
Reserved
C1MX1
C1MX2
C2MX1
C2MX2
C3MX1
C3MX2
C1H10(b1/2)
C1H11(b2)
C1H12(a1/2)
C1H13(a2)
C1H14(b0/2)
C1H20
…
C1H44
C2H10
C2H11
…
C2H44
C12H0(b1/2)
C12H1(b2)
C12H2(a1/2)
C12H3(a2)
0x400000
0x000000
0x000000
0x000000
0x000000
0x400000
0x7FFFFF
0x7FFFFF
0x7FFFFF
0x7FFFFF
0x7FFFFF
0x5A9DF7
0x7FFFFF
0x000000
0x000000
0x7FFFFF
0x400000
0x400000
0x000000
0x000000
0x000000
0x000000
0x400000
0x000000
…
0x400000
0x000000
0x000000
…
0x400000
0x000000
0x000000
0x000000
0x000000
DocID018835 Rev 8 143/174
Register description: Sound Terminal compatibility STA381BW
7.13 Fault-detect recovery constant registers (addr 0x2B - 0x2C)
D7
FDRC15
0
D6
FDRC14
0
D5
FDRC13
1
D4
FDRC12
1
D3
FDRC11
0
D2
FDRC10
0
D1
FDRC9
0
D0
FDRC8
0
D7
FDRC7
0
D6
FDRC6
0
D5
FDRC5
0
D4
FDRC4
0
D3
FDRC3
1
D2
FDRC2
1
D1
FDRC1
0
D0
FDRC0
0
The FDRC bits specify the 16-bit fault-detect recovery time delay. When FAULT is asserted, the TRISTATE output is immediately asserted low and held low for the time period specified by this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The default value of 0x300C gives approximately 1 sec.
0x0000 is a reserved value.
7.14 Device status register (addr 0x2D)
D7
PLLUL
D6
FAULT
D5
Reserved
D4
Reserved
D3
Reserved
D2
Reserved
D1
Reserved
D0
Reserved
This read-only register provides fault and thermal-warning status information from the power control block. Logic value 1 for faults or warning means normal state. Logic 0 means a fault or warning detected on power bridge. The PLLUL = 1 means that the PLL is not locked.
Bit
7
6
R/W
R
R
RST
-
-
Table 153. Status register bits
Name Description
PLLUL
FAULT
0: PLL locked
1: PLL not locked
0: fault detected on power bridge
1: normal operation
7.15 EQ coefficients configuration register (addr 0x31)
D7
XOB
0
D6
Reserved
0
D5
Reserved
0
D4
Reserved
0
D3
Reserved
0
D2
Reserved
0
D1
Reserved
0
D0
Reserved
0
The XOB bit can be used to bypass the crossover filters. Logic 1 means that the function is not active. In this case, the high-pass crossover filter works as a pass-through on the data path (b=0, all the other coefficients at logic 0 ) while the low-pass filter is configured to have zero signal on channel 3 data processing (all the coefficients are at logic 0) .
144/174 DocID018835 Rev 8
STA381BW Register description: Sound Terminal compatibility
7.16 Extended configuration register (addr 0x36)
D7 D6 D5 D4 D3 D2 D1 D0
MDRCE
0
Reserved
0
PS48DB
0
XAR1
0
XAR2
0
BQ5
0
BQ6
0
BQ7
0
The extended configuration register provides access to B
2
DRC and biquad 5, 6 and 7.
The STA381BW device provides a dual-band DRC (B 2 DRC) on the left and right channel data path, as depicted in
. The dual-band DRC is activated by setting MDRCE = 1.
Figure 42. B 2 DRC scheme
Channel 3
Volume
DRC 2
L
B 2 DRC
Hi-pass XO filter
-
+
Channel 1
Volume
DRC 1 +
R
B 2 DRC
Hi-pass XO filter
- +
Channel 2
Volume
DRC 1
Channel 3
Volume
DRC 2 +
The low-frequency information (LFE) is extracted from the left and right channels, removing the high frequencies using a programmable biquad filter, and then computing the difference with the original signal. Limiter 1 (DRC1) is then used to control the amplitude of the left/right high-frequency components, while limiter 2 (DRC2) is used to control the low-frequency
The cutoff frequency of the high-pass filters can be user-defined, XO[3:0] = 0, or selected from the pre-defined values.
DRC1 and DRC2 are then used to independently limit L/R high frequencies and LFE
channel amplitude (see Chapter 7.11
) as well as their volume control. To be noted that, in
this configuration, the dedicated channel 3 volume control can actually act as a bass-boost enhancer as well (0.5 dB/step resolution).
The processed LFE channel is then recombined with the L and R channels in order to reconstruct the 2.0 output signal.
DocID018835 Rev 8 145/174
Register description: Sound Terminal compatibility STA381BW
Sub-band decomposition
The sub-band decomposition for B 2 DRC can be configured specifying the cutoff frequency.
The cutoff frequency can be programmed in two ways, using the XO bits in register 0x0C, or using the “user programmable” mode (coefficients stored in RAM addresses 0x28 to 0x31).
For the user-programmable mode, use the formulas below to compute the high-pass filters: b0 = (1 + alpha) / 2 b1 = -(1 + alpha) / 2 a0 = 1 a1 = -alpha b2 = 0 a2 = 0 where alpha = (1-sin(
0
))/cos(
0
), and
0
is the cutoff frequency.
A first-order filter is suggested to guarantee that for every
0
the corresponding low-pass filter obtained as difference (as shown in
Figure 26 ) will have a symmetric (relative to the HP
filter) frequency response, and the corresponding recombination after the DRC has low ripple. Second-order filters can be used as well, but in this case the filter shape must be carefully chosen to provide good low-pass response and minimum ripple recombination. For second-order filters, it is not possible to give a closed formula to get the best coefficients, but empirical adjustment should be done.
DRC settings
The DRC blocks used by B 2 DRC are the same as those described in
2 DRC configure automatically the DRC blocks in anticlipping mode. Attack and release thresholds can be selected using registers 0x32, 0x33, 0x34, 0x35, while attack and release rates are configured by registers 0x12 and 0x14.
Band downmixing
The low-frequency band is down-mixed to the left and right channels at the B 2 DRC output.
Channel volume can be used to weight the bands recombination to fine-tune the overall frequency response.
7.16.2 Extended post-scale range
PS48DB
0
1
Table 154. Extended post-scale range
Mode
Post-scale value is applied as defined in coefficient RAM
Post-scale value is applied with +48 dB offset with respect to the coefficient RAM value
Post-scale is an attenuation by default. When PS48DB is set to 1, a 48-dB offset is applied to the coefficient RAM value, so post-scale can act as a gain too.
146/174 DocID018835 Rev 8
STA381BW Register description: Sound Terminal compatibility
7.16.3 Extended attack rate
The attack rate shown in Table 146 can be extended to provide up to an 8 dB/ms attack rate
on both limiters.
XAR1
0
1
Table 155. Extended attack rate, limiter 1
Mode
Limiter1 attack rate is configured using
Limiter1 attack rate is 8 dB/ms
XAR2
0
1
Table 156. Extended attack rate, limiter 2
Mode
Limiter2 attack rate is configured using
Limiter2 attack rate is 8 dB/ms
7.16.4 Extended BIQUAD selector
Bass and treble controls can be configured as user-defined filters when the equalization coefficients link is activated (BQL = 1) and the corresponding BQx bit is set to 1.
BQ5
0
1
Table 157. Extended biquad selector, biquad 5
Mode
Reserved
User-defined biquad 5 coefficients are selected
Note:
BQ6
0
1
Table 158. Extended biquad selector, biquad 6
Mode
Pre-set bass filter selected as per
User-defined biquad 6 coefficients are selected
BQ7
0
1
Table 159. Extended biquad selector, biquad 7
Mode
Pre-set treble filter selected as per Table 145
User-defined biquad 7 coefficients are selected
When filters from the 5th to 7th are configured as user-programmable, the corresponding coefficients are stored respectively in addresses 0x20-0x24 (BQ5), 0x25-0x29 (BQ6), 0x2A-
0x2E (BQ7) as given in
BQx bits are ignored if BQL = 0 or if DEMP = 1 (relevant for BQ5) or CxTCB = 1 (relevant for
BQ6 and BQ7).
DocID018835 Rev 8 147/174
Register description: Sound Terminal compatibility STA381BW
7.17 EQ soft volume configuration registers (addr 0x37 - 0x38)
D7
Reserved
0
D6
Reserved
0
D5
SVUPE
0
D4
SVUP[4]
0
D3
SVUP[3]
0
D2
SVUP[2]
0
D1
SVUP[1]
0
D0
SVUP[0]
0
D7
Reserved
0
D6
Reserved
0
D5
SVDWE
0
D4
SVDW4]
0
D3
SVDW[3]
0
D2
SVDW[2]
0
D1
SVDW[1]
0
D0
SVDW[0]
0
The soft volume update has a fixed rate by default. Using register 0x37 and 0x38 it is possible to override the default behavior, allowing different volume change rates.
It is also possible to independently define the fade-in (volume is increased) and fade-out
(volume is decreased) rates according to the desired behavior.
SVUPE
0
1
Table 160. Soft volume update enable, increase
Mode
When volume is increased, use the default rate
When volume is increased, use the rates defined by SVUP[4:0].
Note:
When SVUPE = 1 the volume-up rate is defined by the SVUP[4:0] bits according to the following formula: volume-up rate = 48 / (N + 1) dB/ms where N is the SVUP[4:0] value.
SVDWE
0
1
Table 161. Soft volume update enable, decrease
Mode
When volume is decreased, use the default rate
When volume is decreased, use the rates defined by SVDW[4:0].
When SVDWE = 1 the volume-down rate is defined by the SVDW[4:0] bits according to the following formula: volume-down rate = 48 / (N + 1) dB/ms where N is the SVDW[4:0] value.
For volume-down rates greater than 6 dB/msec it is recommended to disable the CPWMEN bit and ZCE bit in order to avoid any audible pop noise.
148/174 DocID018835 Rev 8
STA381BW Register description: Sound Terminal compatibility
7.18 Extra volume resolution configuration registers (address
0x3F; 0x40)
D7
VRESEN
1
D6
VRESTG
0
D5
C3VR[1]
0
D4
C3VR[0]
0
D3
C2VR[1]
0
D2
C2VR[0]
0
D1
C1VR[1]
0
D0
C1VR[0]
0
D7 reserved
0
D6 reserved
0
D5 reserved
0
D4 reserved
0
D3 reserved
0
D2 reserved
0
Extra volume resolution allows fine volume tuning by steps of 0.125 dB.
The feature is enabled when VRESEN=1, as depicted in Figure 43 . The overall channel
volume in this case will be CxVol+CxVR (in dB), while the master volume will be
MVOL+MVR (in dB).
Figure 43. Extra resolution volume scheme
D1
MVR[1]
0
D0
MVR[0]
0
If VRESEN = 0 the channel volume will be defined only by the CxVol registers.
Fine tuning steps can be set according to the following table for channels 1, 2,3, and master volume.
CxVR/MVR
00
01
10
11
Table 162. Volume fine-tuning steps
Mode
0 dB
-0.125 dB
-0.25 dB
-0.375 dB
DocID018835 Rev 8 149/174
Register description: Sound Terminal compatibility STA381BW
Two different behaviors can be configured by the VRESTG bit.
I
If VRESTG=’0’ the CxVR contribution will be applied immediately after the corresponding
2 C bits are written.
If VRESTG=’1’ the CxVR bits will be effective on channel volume only after the corresponding CxVol register or master volume register is written (even to the previous values).
VRESEN
0
0
1
1
Table 163. Extra volume resolution enable
VRESTG Mode
0
1
0
1
Extra volume resolution disabled
Extra volume resolution disabled
Fine volume tuning enabled and applied immediately
Fine volume tuning enabled and applied when master or channel volume is updated
7.19 PLL configuration registers (address 0x41; 0x42; 0x43; 0x44;
0x45; 0X46)
D7
0
D7
D6
0
D6
0 0
D7
PLL_DITH[1:0]
D6
0 0
D7
PLL_DPD
0
D6
PLL_FCT
0
D7
Reserved
0
D6
Reserved
0
D5
0
D5
0
D5
0
D5
PLL_STB
0
D5
PLL_DIRP
0
D4 D3
PLL_FRAC[15:8]
0 0
D4 D3
0
PLL_FRAC[7:0]
0
D4
0
D4
PLL_STBBYP
0
D4
PLL_PWD
0
D2
0
D2
D1
0
D1
D0
0
D0
0 0 0
D0 D3 D2
PLL_NDIV[5:0]
0 0
D3
0
D1
0
D2
PLL_IDIV(3:0)
D1
0 0
D3
PLL_BYP
0
D2
OSC_PD
1
0
D0
D1
Reserved
0
0
D0
BOOST32K
0
150/174
D7
Reserved
NA
D6
Reserved
NA
D5
Reserved
NA
D4
Reserved
NA
D3
BYPSTATE
NA
D2
PDSTATE
NA
D1
OSCOK
NA
D0
LOWCK
NA
By default the STA381BW is able to configure the embedded PLL automatically depending on the MCS bits (reg 0x00). For certain applications and to provide flexibility to the user, a manual PLL configuration can be used (setting PLL_DIRP to ‘1’).
DocID018835 Rev 8
STA381BW Register description: Sound Terminal compatibility
The output PLL frequency formula is:
Fin
+
65536
where Fin is the input clock frequency from the pad.
PLL parameter
FRAC
IDIV
NDIV
Table 164. PLL factors
Min
0
0
5
Max
65535
3
55
6
5
4
1
0
3
2
Bit
7
6
2
1
0
5
4
3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RST
0
0
0
0
0
0
0
0
Table 165. PLL register 0x43 bits
Name Description
PLL_DITH(1:0)
00: PLL clock dithering disabled
01: PLL clock dithering enabled (triangular))
10: PLL clock dithering enabled (rectangular)
11: Reserved
NDIV PLL loop divider
Bit R/W RST
7 R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Table 166. PLL register 0x44 bits
Name Description
PLL_DPD
PLL_FCT
PLL_STB
PLL_STBBYP
0: any PLL dividers change is implemented via PLL power-down
1: PLL divider change will happen without PLL power-down
0: PLL use integer ratio
1: PLL use fractional ratio
PLL synchronous divider changes strobe
0: PLL_STB is active
1: PLL_STB control is bypassed
PLL_IDIV (3:0) Input PLL divider
DocID018835 Rev 8 151/174
Register description: Sound Terminal compatibility STA381BW
2
0
4
3
Bit R/W RST
5 R/W 0
R/W
R/W
R/W
R/W
0
0
0
0
Bit
3
2
1
0
R/W
R
R
R
R
RST
Table 167. PLL register 0x45 bits
Name Description
PLL_DIRP
PLL_PWD
PLL_BYP
OSC_PD
BOOST32K
0: PLL configuration is determined by MCS bits
1: PLL configuration is determined by FRAC, IDIV and NDIV
0: PLL normal behavior
1: PLL is in power-down mode
0: sys clock is from PLL
1: sys clock is from external pin (PLL is bypassed)
0: Normal behavior
1: Internal oscillator is in power-down
0: Input oversampling selected by IR bits
1: Input oversampling is selected x3
Table 168. PLL register 0x46 bits
Name Description
BYPSTATE
PDSTATE
OSCOK
LOWCK
PLL bypass state
PLL PD state
OSCI locked
Clock input frequency check
7.20 Short-circuit protection mode registers SHOK (address 0x47)
D7 reserved
NA
D6 reserved
NA
D5 reserved
NA
D4 reserved
NA
D3 reserved
NA
D2
GNDSH
NA
D1
VCCSH
NA
D0
OUTSH
NA
The following power bridge pins short-circuit protections are implemented in the
STA381BW:
OUTxx vs GNDx
OUTxx vs VCCx
OUT1B vs OUT2A
The protection is enabled when reg. 0x4C bit 0 (SHEN) is set to ‘1’. The protection will check the short-circuit when the EAPD bit is toggled from ‘0’ to ‘1’ (i.e. the power bridge is switched on), and only if the test passes (no short) does the power bridge leave the tristate condition.
Register 0x47 (read-only registers) will give more information about the detected short type.
GNDSH equal to ‘0’ means that OUTxx is shorted to ground, while the same value on
VCCSH means that OUTxx is shorted to Vcc, finally OUTSH=’0’ means that OUT1B is shorted to OUT2A.
152/174 DocID018835 Rev 8
STA381BW Register description: Sound Terminal compatibility
To be noted that once the check is performed, and the tristate released, the short protection is not active anymore until the next EAPD 0->1 toggling which means that shorts that happened during normal operation cannot be detected.
To be noted that register 0x47 is meaningful only after the EAPD bit is set to ‘1’ at least once.
The short-circuit protections implemented are effective only in BTL configuration, and they must not be activated if a single ended-application scheme is needed.
Figure 44. Short-circuit detection timing diagram (no short detected)
S t a r t g n d t e s t S t a r t v c c t e s t E n d o f S h o r t t e s t
Start o ut test
EAPD
OUT1A
OUT1B
OUT2A
OUT2B
SHOK1[7:4]
SHOK1[3:0]
SHOK2[0]
50005 cy cles
44 cy c les
50005 cy c les
TBD c yc les
1c yc le
In
Figure 44 the short protection timing diagram is shown. The time information is expressed
in clock cycles, where the clock frequency is defined as in section 7.1.1
used for the SHOKx bits to indicate that the bits are carrying the status of the previous
EAPD 0->1 toggling (to be noted that after reset this state is meaningless since no EAPD transition occurs). GND-related SHOK bits are updated as soon as the gnd test is completed, VCC bits are updated after the vcc test is completed, and the SOUT bit is updated after the shorted output test is completed. The gnd test, vcc test and output test are always run (if the SHEN bit active and EAPD is toggled to ‘1’), and only if both tests are successful (no short) do the bridge outputs leave the tristate (indicated by dotted lines in the figure). If one of the three tests (or all) fail, the power bridge outputs are kept in tristate until the procedure is restarted with a new EAPD toggling.
In this figure EAPD is intended to be bit 7 of register 0x05.
DocID018835 Rev 8 153/174
Register description: Sound Terminal compatibility STA381BW
7.21 Extended coefficient range up to -4...4 (address 0x49, 0x4A)
D7 D6
CEXT_B4[1] CEXT_B4[0]
1 0
D5
CEXT_B3[1]
1
D4
CEXT_B3[0]
0
D3 D2
CEXT_B2[1] CEXT_B2[0]
1 0
D1
CEXT_B1[1]
1
D0
CEXT_B1[0]
0
D7 reserved
0
D6 reserved
0
D5
CEXT_B7[1]
1
D4
CEXT_B7[0]
0
D3 D2
CEXT_B6[1] CEXT_B6[0]
1 0
D1
CEXT_B51]
1
D0
CEXT_B5[0]
0
Biquads from 1 to 7 have in the STA381BW the possibility to extend the coefficient range from [-1,1) to [-4..4) which allows the implementation of high-shelf filters that may require a coefficient dynamic greater in absolute value than 1.
Three ranges are available, [-1;1) [-2;2) [-4;4). By default, the extended range is activated
Each biquad has its independent setting according to the following table.
Table 169. Coefficients extended range configuration
CEXT_Bx[1] CEXT_Bx[0] Range
0
0
0
1
[-1;1)
[-2;2)
1
1
0
1
[-4;4)
Reserved
In this case the user can decide, for each filter stage, the right coefficients range. Note that for a given biquad, the same range will be applied to the left and right (channel 1 and channel 2).
Crossover biquad does not have the availability of this feature, maintaining the [-1;1) range unchanged.
7.22 Miscellaneous registers (address 0x4B, 0x4C)
D7 D6 D5 D4 D3 D2
RPDNEN
0 1
BRIDGOFF
1 0 0
CPWMEN
1
D1 reserved
0
D0
0
D7
LPDP
0
D6
LPD
1
D5
LPDE
0
D4
PNDLSL[2]
0
D3
PNDLSL[1]
1
D2
PNDLSL[0]
1
D1 reserved
0
D0
SHEN
0
7.22.1 Rate power-down enable (RPDNEN) bit (address 0x4B, bit D7)
In the STA381BW, by default, the power-down pin and I
2
C power-down act on mute commands to perform the fade-out. This default can be changed so that the fade-out can be started using master volume. The RPDNEN bit, when set, activates this feature.
154/174 DocID018835 Rev 8
STA381BW Register description: Sound Terminal compatibility
7.22.2 Bridge immediately off (BRIDGOFF) bit (address 0x4B, bit D5)
A fade-out procedure is started in the STA381BW once the PWDN function is enabled, and after 13 million clock cycles (PLL internal frequency) the bridge is put in power-down
(tristate mode). There is also the possibility to change this behavior so that the power bridge will be switched off immediately after the PWDN pin is tied to ground, without waiting for the
13 million clock cycles. The BRIDGOFF bit, when set, activates this function. Obviously the immediate power-down will generate a pop noise at the output, therefore this procedure must be used only in case pop noise is not relevant in the application. Note that this feature works only for hardware PWDN assertion and not for a power-down applied through the IIC
interface. Refer to Section 7.22.5
if programming a different number of clock cycles is needed.
7.22.3 Channel PWM enable (CPWMEN) bit (address 0x4B, bit D2)
This bit, when set, activates a mute output in case the volume reaches a value lower than -76 dBFS.
7.22.4 External amplifier hardware pin enabler (LPDP, LPD LPDE) bits
(address 0x4C, bit D7, D6, D5)
Pin 42 (INTLINE), normally indicating a fault condition, using the following 3 register settings, can be reconfigured as hardware pin enabler for an external headphone or line amplifier.
In particular the LPDE bit, when set, activates this function. Accordingly, the LPD value (0 or
1) is exported on pin 42 and in case of power-down assertion, pin 42 is tied to LPDP.
The LPDP bit, when set, negates the value programmed as the LPD value, refer to the following table.
0
1
1
LPDP
Table 170. External amplifier enabler configuration bits
LPD LPDE Pin 42 output x
0 x
0
0
1
INT_LINE
0
1
0
1
1
1
1
1
1
0
DocID018835 Rev 8 155/174
Register description: Sound Terminal compatibility
Figure 45. Alternate function for INTLINE pin
P o w er B rid ge Fau lt
0
‘0 ’
Y
L P D
N
0
1
1
STA381BW
IN T L IN E
L P D E
“is th e d evice in p ow erd o w n ?” LP D P
7.22.5 Power-down delay selector (PNDLSL[2:0]) bits (address 0x4C, bit D4,
D3, D2)
As per
, the assertion of PWDN activates a counter that, by default, after 13
million clock cycles puts the power bridge in tristate mode, independently from the fade-out time. Using these registers it is possible to program this counter according to the following table.
PNDLSL[2] PNDLSL[1]
Table 171. PNDLSL bits configuration
PNDLSL[2] Fade-out time
0
0
0
0
0
1
Default time (13M PLL clock cycles)
Default time divided by 2
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
Default time divided by 4
Default time divided by 8
Default time divided by 16
Default time divided by 32
Default time divided by 64
Default time divided by 128
7.22.6 Short-circuit check enable bit (address 0x4C, bit D0)
This bit, when enabled, will activate the short-circuit checks before any power bridge activation (EAPD bit 0->1). See section
for more details.
156/174 DocID018835 Rev 8
STA381BW Register description: Sound Terminal compatibility
7.23 Bad PWM detection registers (address 0x4D, 0x4E, 0x4F)
D7
BPTH[5]
0
D7
BP4B
0
D6
BPTH[4]
0
D6
BP4A
0
D5
BPTH[3]
1
D5
BP3B
0
D4
BPTH[2]
1
D4
BP3A
0
D3
BPTH[1]
0
D3
BP2B
0
D2
BPTH[0]
0
D2
BP2A
0
D1 reserved
1
D1
BP1B
0
D0 reserved
0
D0
BP1A
0
D7
BPTIM[7]
0
D6
BPTIM[6]
1
D5
BPTIM[5]
0
D4
BPTIM[4]
1
D3
BPTIM[3]
1
D2
BPTIM[2]
1
D1
BPTIM[1]
1
D0
BPTIM[0]
0
The STA381BW implements a detection on the PWM outputs able to verify if the output signal has no zero-crossing in a configurable time window. This check can be useful to detect DC levels in the PWM outputs. To be noted that the checks are performed on logic level PWM (i.e. not the power bridge ones, nor the PWM on DDX3 and DDX4 I/Os).
In case of ternary modulation, the detection threshold is computed as:
TH=[(BPTH*2+1)/128]*100%
If the measured PWM duty cycle is detected greater than or equal to TH for more than
BPTIM PWM periods, the corresponding PWM bit will be set in register 0x4E.
In case of binary modulation, there are two thresholds:
TH1=[(64+BPTH)/128]*100%
TH2=[(64-BPTH)/128]*100%
In this case if the measured PWM duty cycle is outside the TH1-TH2 range for more than
BPTIM PWM periods, the corresponding bit will be set in register 0x4E.
DocID018835 Rev 8 157/174
Register description: Sound Terminal compatibility STA381BW
7.24 Enhanced zero-detect mute and input level measurement
(address 0x50-0x54, 0x2E, 0x2F and 0x5E)
D7
WTHH
0
D6
WTHL
0
D5
FINETH
0
D4
HSEL[1:0]
D3
0 0
D2
1
D1
ZMTH[2:0]
1
D0
1
D7
N/A
D7
N/A
D6
N/A
D6
N/A
D5
N/A
D5
N/A
D4 D3
RMS_CH0[7:0]
N/A N/A
D4 D3
RMS_CH0[15:8]
N/A N/A
D2
N/A
D2
N/A
D1
N/A
D1
N/A
D0
N/A
D0
N/A
D7
N/A
D6
N/A
D5
N/A
D4 D3
RMS_CH1[7:0]
N/A N/A
D2
N/A
D1
N/A
D0
N/A
D7
N/A
D6
N/A
D5
N/A
D4 D3
RMS_CH1[15:8]
N/A N/A
D2
N/A
D1
N/A
D0
N/A
The STA381BW implements an RMS-based zero-detect function (on serial input interface data) able to detect in a very reliable way the presence of an input signal, so that the power bridge outputs can be automatically connected to ground.
When active, the function will mute the output PWM when the input level become less than
“threshold - hysteresis”. Once muted, the PWM will be unmuted when the input level is detected greater than “threshold + hysteresis”.
The measured level is then reported (for each input channel) on registers 0x51 - 0x52, 0x53
- 0x54 according to the following equation:
Value_in_dB = 20*Log
10
(Reg_value/(2
16
*0.635))
158/174 DocID018835 Rev 8
STA381BW
ZMTH[2:0]
100
101
110
111
000
001
010
011
Register description: Sound Terminal compatibility
Table 172. Zero-detect threshold
Equivalent input level (dB)
-102
-108
-114
-114
-78
-84
-90
-96
HSEL[1:0]
00
01
10
11
Table 173. Zero-detect hysteresis
Equivalent input level hysteresis (dB)
5
6
3
4
The above thresholds and hysteresis table can be overridden and the low-level threshold and high-level threshold can be set by the MTH[21:0] bits.
To activate the manual thresholds the FINETH bit has to be set to ‘1’.
To configure the low threshold, the WTHL bit must be set to ‘1’ so that any write operation to the MTH bits will set the low threshold.
To configure the low threshold, the WTHH bit must be set to ‘1’ so that any write operation to the MTH bits will set the low threshold.
If the zero-mute block does not detect mute, it will mute the output when the current RMS value falls below the low threshold.
If the zero-mute block does not detect mute, it will unmute the output when the current RMS value rises above the high threshold.
DocID018835 Rev 8 159/174
Register description: Sound Terminal compatibility
D7
ReservedT
0
Table 174. Manual threshold register 0x2E, 0x2F and 0x5E
D6 D5 D4 D3 D2 D1
Reserved
0 0 0 0
MTH[21:16]
0 0
STA381BW
D0
0
D7
0
D6
0
D5
0
D4
MTH[15:8]
D3
0 0
D2
0
D1
0
D0
0
D7
0
D6
0
D5
0
D4
MTH[7:0]
D3
0 0
D2
0
D1
0
D0
0
7.25 Headphone/Line out configuration register (address 0x55)
1
0
7
5
3
2
D7
HPLN
0
Bit R/W
R/W
R/W
R/W
R
R
R
D6
Reserved
0
D5
MUTE
1
D4
Reserved
0
D3
CPFEN
0
D2
CPOK
NA
D1
ABFAULT
NA
D0
DCROK
NA
Table 175. Headphone/Line out configuration bits
RST Name Description
0
1
0
NA
NA
NA
HPLN
MUTE
CPFEN
CPOK
ABFAULT
DCROK
When F3X is connected to the internal HP/Line driver this bit selects the gain of the F3X->analog out path.
0: HP out. When the MVOL+Channel Vol is 0 dBFs, a 0 dBFs input will generate a 40 mW output on a
32 ohm load (+/- 3.3 V supply).
1:Line out. When the MVOL+Channel Vol is
0 dBFs, a 0 dBFs input will generate a 2 Vrms output
(+/- 3.3 V supply)
1: HP/Line out muted
0: HP/Line out playing
0: Charge pump auto enable when unmute
1: Charge pump is always enabled
0: Charge pump is not working
1: Charge pump is working and it is OK
0: No fault on class-AB
1: Overcurrent fault detected on class-AB
1: core supply OK
160/174 DocID018835 Rev 8
STA381BW Register description: Sound Terminal compatibility
7.26 F3XCFG (address 0x58; 0x59)
D7
F3XLNK
0
D6
Reserved
0
D5
Reserved
0
D4
Reserved
0
D3
Reserved
0
D2
Reserved
0
D1
Reserved
0
D0
Reserved
0
D7
F3X_FAULT
NA
D6
Reserved
1
D5
Reserved
1
D4
0
D3
F3X_SM_SLOPE
1
D2
1
D1
F3X_MUTE
1
D0
F3X_ENA
0
Bit
7
R/W
R/W
RST
0
Table 176. F3X configuration register 1
Name Description
F3XLNK
0: F3X normal control mode
1: F3X mute/unmute linked to HP/Line mute
Bit
7
4
3
2
1
0
R/W
R
R/W
R/W
R/W
R/W
R/W
RST
NA
0
1
1
1
0
Table 177. F3X configuration register 2
Name Description
F3X_FAULT
F3X_SM_SLOPE
F3X_MUTE
F3X_ENA
0: Normal operation
000: 0 ms
001: 25 ms
010: 50 ms
011: 100 ms
100: 200 ms
101: 250 ms
110: 500 ms
111: 1000 ms
1: Mute
1: F3X enable
DocID018835 Rev 8 161/174
Register description: Sound Terminal compatibility STA381BW
7.27 STCompressor
TM
configuration register (address 0x5A;
0x5B)
D7 reserved
0
D6
LIM_BYP
0
D5
STC_BYP
1
D4
STC_ENA
1
D3 reserved
0
D2
NP_CRES
0
D1 reserved
0
D7 reserved
0
Bit R/W
D6 reserved
0
D5 reserved
0
D4 reserved
0
D3 reserved
0
D2 reserved
0
Table 178. STCompressor TM configuration bits1
RST Name Description
D1
STC_LNK
0
6
5
4
2
0
R/W
R/W
R/W
R
R/W
0
1
1
0
0
LIM_BYP
STC_BYP
STC_EN
NP_CRCRES
NP_CRC_GO
D0
NP_CRC-GO
0
D0
BRC_EN
0
0: STCompressor
TM
DRC active
1: STCompressor TM DRC is bypassed
0: STCompressor
TM
processing activated
1: STCompressor
TM
is in pass-through
0: STCompressor
TM
is switched off (no configuration is possible in this state)
1: STCompressor
TM
is enabled
1: CRC STCompressor ok
0: CRC STCompressor error
1: Start CRC STCompressor compute ON
0: Idle
1
0
Bit R/W
R/W
R/W
0
0
Table 179. STCompressor
TM
configuration bits 2
RST Name Description
STC_LNK
BRC_EN
0: Channel 0 and channel 1 attenuation are applied independently
1: Channel 0 and channel 1 attenuation are linked so that the higher one is applied to both channel 0 and channel 1
1: STCompressor band recombination enabled
0: Disabled
162/174 DocID018835 Rev 8
STA381BW Register description: Sound Terminal compatibility
7.28 Charge pump synchronization (address 0x5F)
2
1
4
3
D7
Reserved
0
Bit
5
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
D6
Reserved
0
D5
CHPI
0
D4
1
D3
INITCNT[3:0]
D2
1 0
D1
0
D0
CHPRD
1
0
0
1
1
Table 180. Charge pump sync configuration bits
RST Name Description
0 CHPI
0: Charge pump phase: 0 deg
1: Charge pump phase: 180 deg
INITCNT[3:0] Change charge pump phase at one clock step
1 CHPRD
0: Charge pump synchronized with PWM frame
1: Charge pump not synchronized with PWM frame
The charge pump can be synchronized with the PWM frame in order to minimize the crosstalk between the charge pump and the PWM waveform.
This functionality cannot be activated when the PWMS bit (address 0x15 bit D4) is set to 1.
DocID018835 Rev 8 163/174
Register description: Sound Terminal compatibility STA381BW
7.29 Coefficient RAM CRC protection (address 0x60-0x6C)
D7
BQCKE[7]
0
D6
BQCKE[6]
0
D5
BQCKE[5]
0
D4
BQCKE[4]
0
D3
BQCKE[3]
0
D2
BQCKE[2]
0
D1
BQCKE[1]
0
D0
BQCKE[0]
0
D7
BQCKE[15]
0
D6
BQCKE[14]
0
D5
BQCKE[13]
0
D4
BQCKE[12]
0
D3
BQCKE[11]
0
D2
BQCKE[10]
0
D7
BQCKE[23]
0
D6
BQCKE[22]
0
D5
BQCKE[21]
0
D4
BQCKE[20]
0
D3
BQCKE[19]
0
D2
BQCKE[18]
0
D1
BQCKE[17]
0
D0
BQCKE[16]
0
D7
XCCKE[7]
0
D7
XCCKE[15]
0
D6
XCCKE[6]
0
D6
XCCKE[14]
0
D5
XCCKE[5]
0
D5
XCCKE[13]
0
D4
XCCKE[4]
0
D4
XCCKE[12]
0
D3
XCCKE[3]
0
D3
XCCKE[11]
0
D2
XCCKE[2]
0
D2
XCCKE[10]
0
D1
BQCKE[9]
0
D1
XCCKE[1]
0
D1
XCCKE[9]
0
D0
BQCKE[8]
0
D0
XCCKE[0]
0
D0
XCCKE[8]
0
D7
XCCKE[23]
0
D6
XCCKE[22]
0
D5
XCCKE[21]
0
D4
XCCKE[20]
0
D3
XCCKE[19]
0
D2
XCCKE[18]
0
D1
XCCKE[17]
0
D0
XCCKE[16]
0
D7
BQCKR[7]
0
D7
BQCKR[15]
0
D6
BQCKR[6]
0
D6
BQCKR[14]
0
D5
BQCKR[5]
0
D5
BQCKR[13]
0
D4
BQCKR[4]
0
D3
BQCKR[3]
0
D4
BQCKR[12]
0
D3
BQCKR[11]
0
D2
BQCKR[2]
0
D2
BQCKR[10]
0
D1
BQCKR[1]
0
D1
BQCKR[9]
0
D0
BQCKR[0]
0
D0
BQCKR[8]
0
D7
BQCKR[23]
0
D6
BQCKR[22]
0
D5
BQCKR[21]
0
D4
BQCKR[20]
0
D3
BQCKR[19]
0
D2
BQCKR[18]
0
D1
BQCKR[17]
0
D0
BQCKR[16]
0
D7
XCCKR[23]
0
D6
XCCKR[22]
0
D5
XCCKR[21]
0
D4
XCCKR[20]
0
D3
XCCKR[19]
0
D2
XCCKR[18]
0
D1
XCCKR[17]
0
D0
XCCKR[16]
0
D7
XCCKR[23]
0
D6
XCCKR[22]
0
D5
XCCKR[21]
0
D4
XCCKR[20]
0
D3
XCCKR[19]
0
D2
XCCKR[18]
0
D1
XCCKR[17]
0
D0
XCCKR[16]
0
D7
XCCKR[23]
0
D6
XCCKR[22]
0
D5
XCCKR[21]
0
D4
XCCKR[20]
0
D3
XCCKR[19]
0
D2
XCCKR[18]
0
D1
XCCKR[17]
0
D0
XCCKR[16]
0
D7
XCAUTO
0
D6
XCRES
0
D5
XCCMP
0
D4
XCGO
0
D3
BCAUTO
0
D2
BCCRES
0
D1
BCCMP
0
D0
BCCGO
0
164/174 DocID018835 Rev 8
STA381BW Register description: Sound Terminal compatibility
The STA381BW implements an automatic CRC computation for the biquad and
MDRC/XOver coefficient memory. Memory cell contents from address 0x00 to 0x27 will be bit XORed to obtain the BQCHKE checksum, while cells from 0x28 to 0x31 will be XORed to obtain the XCCHKE checksum. Both checksums (24-bit wide) are exported on I 2 C registers from 0x60 to 0x65. The checksum computation will start as soon as the BCGO (for biquad
RAM bank) or the XCGO bit (for MDRC/XOver coefficients) is set to 1. The checksum is computed at the processing sample rate if the IR bits equal “01” or “10”, otherwise the checksum is computed to half the processing sample rate.
When BCCMP or XCCMP are set to ‘1’, the relative checksum (BQCHKE and XCCHKE) is continuously compared with BQCHKR and XCCHKR respectively. If the checksum matches its own reference value, the respective result bits (BCRES and XCRES) will be set to ‘0’.
The compare bits have no effect if the respective GO bit is not set.
In case of checksum errors (i.e. the internally computed didn’t match the reference), an automatic device reset action can be activated. This function is enabled when the BCAUTO or XCAUTO bit is set to ‘1’. The automatic reset bits have no effect if the respective compare bits are not set.
The recommended procedure for the automatic reset activation is the following:
Download the set of coefficients (RAM locations 0x00…0x27)
Download the externally computed biquad checksum into registers BQCHKR
Enable the checksum of the biquad coefficients by setting the BCGO bit. The checksum will start to be automatically computed by the STA381BW and its value exposed on registers BQCHECKE.
The checksum value is computed and updated.
Enable the checksum comparison by setting the BCCMP bit. The internally computed checksum will start to be compared with the reference one and the result will be exposed on the BCRES bit. The following operation will be executed on each audio frame:
{ if (( BQCHKE == BQCHKR ))
BC_RES = 0;// Checksum is ok, reset the error bit
{
} else
BC_RES = 1;// Checksum error detected, set the error bit
}
Wait until the BCRES bit goes to 0, meaning that the checksum result bit has started to be updated and everything is ok. Time-out of this operation (e.g. > 1 ms) will indicate checksum failure, and the MCU will handle this event.
Enable automatic reset of the device in case of checksum error by setting the BCAUTO bit. The BCRES bit will then be automatically checked by the STA381BW, on each audio frame, and the reset event will be triggered in case of checksum mismatch.
Periodically check the BC_RES status. A value of 1 indicates that a checksum mismatch has occurred and, therefore, the device went through a reset cycle.
The previous example is intended for biquad CRC bank calculation, but it can be easily extended to MDRC/XOver CRC computation.
DocID018835 Rev 8 165/174
Register description: Sound Terminal compatibility
7.30 MISC3 (address 0x6E)
STA381BW
D7 reserved
0
D6 reserved
0
D5 reserved
0
D4 reserved
0
D3 reserved
0
D2
SRESET
0
D1 reserved
0
D0 reserved
0
Bit
2
R/W
R/W
RST
0
Table 181. Misc register 3
Name
SRESET
0: normal operation
1: reset the device
Description
After SRESET is written, the last IC acknowledge is skipped and the EAPD bit (reg 0x16 bit
D7) is set to1 instead of the 0 default value obtained after the hardware reset.
7.31 MISC4 (address 0x7E)
D7
SMAP
1
D6 reserved
0
D5 reserved
0
D4 reserved
0
D3 reserved
0
D2 reserved
0
D1 reserved
0
D0 reserved
0
Bit
7
R/W RST
1
Name
Table 182. MISC4
SMAP
1: NEWMAP
0: STMAP
Description
166/174 DocID018835 Rev 8
STA381BW
8 Applications
Applications
The following figures illustrate typical application schemes for the STA381BW. The line/headphone out can be fed either with an external analog source (
F3X output, allowing to have the audio content coming from the digital interface on both the power output and on the line/headphone out (
). Regardless of the LINEINx pins input, the F3Xx outputs can be connected to an external amplifier as an auxiliary analog output (
). The F3X audio content is provided by the device digital audio interface.
Figure 46. External audio source to line/headphone out application scheme
Note: For further information, please refer to application note AN3959, 2.0-channel demonstration board based on the STA381BW and STA381BWS.
DocID018835 Rev 8 167/174
Applications STA381BW
Figure 47. F3X (from SAI) source to line/headphone out application scheme
Note: For further information, please refer to application note AN3959, 2.0-channel demonstration board based on the STA381BW and STA381BWS.
168/174 DocID018835 Rev 8
STA381BW
Figure 48. F3X auxiliary analog output
Applications
Note:
8.2
For further information, please refer to application note AN3959, 2.0-channel demonstration board based on the STA381BW and STA381BWS.
Headphone and 2 Vrms line out
Figure 49. Headphone and line out block diagram
Note: For further information, please refer to application note AN3959, 2.0-channel demonstration board based on the STA381BW and STA381BWS.
DocID018835 Rev 8 169/174
Applications
Note:
STA381BW
Besides the digital input to the power output path, a line in to the headphone / 2Vrms line out path is provided. The headphone and line out block diagram is shown in
overall gain is determined by the external resistors R1 and R2 as:
Gain=R2/R1*2
The LINEINR/LINEINL pins can be either connected to an external line in or to the
F3XL/F3XR pins as depicted in
. Thanks to this latter option it is possible to route the digital input (SAI) content on both the power and the line out/headphone output.
The charge pump of the headphone and line out cannot drive a purely capacitive load.
Please refer to AN3959 (2.0-channel demonstration board based on the STA381BW and
STA381BWS) for detailed information about headphone and line out filtering.
8.3 Typical output configuration
illustrates the typical output configuration used for BTL stereo mode. Please refer to the application note for all the other schematics for the recommended output configuration.
Figure 50. Output configuration for stereo BTL mode in filterlight configuration
Note: For further information, please refer to application note AN3959, 2.0-channel demonstration board based on the STA381BW and STA381BWS.
170/174 DocID018835 Rev 8
STA381BW Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
Figure 51. VQFN48 (7 x 7 x 0.9 mm) package outline
DocID018835 Rev 8
8320060_wk
171/174
Package information STA381BW
Table 183. VQFN48 (7 x 7 x 0.9 mm) package dimensions mm
Reference
Min.
Typ.
0.90
b1 e (pad pitch)
L1 aaa bbb ddd eee fff ccc
D2
E
E2 b
A
A1
D
0.80
0
6.90
5.65
6.90
5.65
0.25
0.20
0.05
0.15
0.10
0.05
0.08
0.10
0.10
7.00
5.70
7.00
5.70
0.30
0.25
0.50
Max
1.00
0.05
7.10
5.75
7.10
5.75
0.35
0.30
0.15
172/174 DocID018835 Rev 8
STA381BW Revision history
Date
08-Jun-2011
28-Jun-2011
Revision
1
2
02-Sep-2011 3
Table 184. Document revision history
Changes
Initial release
Removed TQFP64 package option
Added note to
,
,
Section 8.2: Headphone and 2 Vrms line out , referencing AN3959
20-Dec-2011
17-Jan-2012
20-Jun-2012
03-Aug-2012
17-May-2013
4
5
6
7
8
Updated names of pin 32 and 33 in
Document promoted from preliminary to full datasheet
Added “VDD3V3CHP” to
Updated footnotes in
Updated register names to “SVUP” and “SVDN” for addresses 37 and 38 in
and
Updated 2.0 channels, two full-bridges (OCFG = 00) on page 121
Updated 2.1 channels, two full-bridges + one external full-bridge (OCFG = 10) on page 123
Updated high-pass filter in Table 152
Textual changes to formulas in
Section 7.17: EQ soft volume configuration registers (addr
Added overvoltage protection threshold (V
OV
) to Table 7: Electrical specifications - power
Removed ECLE bit and sections concerning “Auto EAPD on clock loss” from datasheet
Updated
Table 14: Default register map table: NEW MAP on page 45
Updated
C registers summary on page 106
Updated
Section 6.32: Enhanced zero-detect mute and input level measurement
(address 0x61-0x65, 0x3F, 0x40, 0x6F) on page 97
Added
Table 90: Manual threshold register 0x3F, 0x40 and 0x6F on page 98
Added
Section 6.36: Charge pump synchronization (address 0x70) on page 101
Added
Table 98: Charge pump sync configuration bits on page 101
Updated
Section 7.24: Enhanced zero-detect mute and input level measurement
(address 0x50-0x54, 0x2E, 0x2F and 0x5E) on page 158
Added
Table 174: Manual threshold register 0x2E, 0x2F and 0x5E on page 160
Added
Section 7.28: Charge pump synchronization (address 0x5F) on page 163
Added
Table 180: Charge pump sync configuration bits on page 163
Added
Section 3.6: Power-on/off sequence
(added
Updated description of CHPRD bit in
DocID018835 Rev 8 173/174
STA381BW
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
ST PRODUCTS ARE NOT AUTHORIZED FOR USE IN WEAPONS. NOR ARE ST PRODUCTS DESIGNED OR AUTHORIZED FOR USE
IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH
PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B) AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR
ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED
FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN
WRITING OF SUCH USAGE, UNLESS A PRODUCT IS EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE,
AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS.
PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE DEEMED SUITABLE FOR USE IN AEROSPACE BY THE
CORRESPONDING GOVERNMENTAL AGENCY.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2013 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
174/174 DocID018835 Rev 8
பதிவிறக்கு
பொது இணைப்பு புதுப்பிக்கப்பட்டது
உங்கள் அரட்டைக்கான பொது இணைப்பு புதுப்பிக்கப்பட்டுள்ளது. You may view and manage your chat links after registration here.
ஆவண பொது இணைப்பு
விளம்பரம்