STMicroelectronics STA382BWS Datasheet
বিজ্ঞাপন
বিজ্ঞাপন
STA382BWS
Sound Terminal
®
2.1-channel high-efficiency digital audio system
Datasheet
−
preliminary data
Features
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Wide-range supply voltage
– 4.5 V to 25.5 V (operating range)
– 27 V (absolute maximum rating)
I
2
C control with selectable device address
Embedded full IC protection
– Manufacturing short-circuit protection (out vs. gnd, out vs. vcc, out vs. out)
– Thermal protection
– Overcurrent protection
– Undervoltage protection
1 Vrms stereo analog input
I
2
S interface, sampling rate 32 kHz ~ 192 kHz, with internal sampling frequency converter for fixed processing frequency
Three output power stage configurations
– 2.0 mode, L/R full bridges
– 2.1 mode, L/R two half-bridges, subwoofer full bridge
– 2.1 mode, L/R full bridges, PWM output for external subwoofer amplifier
Driving load capabilities
– 2 x 20 W into 8 Ω ternary modulation
– 2 x 9 W into 4 Ω + 1 x 20 W into 8 Ω
FFX
TM
100 dB dynamic range
Fixed output PWM frequency at any input sampling frequency
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Two analog outputs
– Selectable headphone / line out driver with adjustable gain via external resistors
– New F3X
TM
analog output
New fully programmable noise-gating function
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VQFN48 (7 x 7 mm)
Headphone
– Embedded negative charge pump
– Full capless output configuration
– Driving load capabilities: 40 mW into 32
Ω
Line out
– 2 Vrms line output capability
Up to 12 user-programmable biquads with noise-shaping technology
Direct access to coefficients through I
2
C shadowing mechanism
Fixed (88.2 kHz / 96 kHz) internal processing sampling rate
Two independent DRCs configurable as a dual-band anticlipper or independent limiters/compressors (B
2
DRC)
Digital gain/att +48 dB to -80 dB with
0.125 dB/step resolution
Independent (fade-in, fade-out) soft volume update with programmable rate 48 ~ 1.5 dB/ms
Bass/treble tones control
Audio presets: 15 crossover filters,
5 anticlipping modes, nighttime listening mode
STSpeakerSafe
TM
protection circuitry
– Pre
-
and post
processing DC blocking filters
– Checksum engine for filter coefficients
– PWM fault self-diagnosis
STCompressor
TM
dual-band DRC
Table 1.
Device summary
Order code Package
STA382BWS
STA382BWSTR
VQFN48
VQFN48
Packing
Tray
Tape and Reel
April 2012 Doc ID 022784 Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/172 www.st.com
1
STA382BWS Contents
Contents
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Electrical specifications for the digital section . . . . . . . . . . . . . . . . . . . . . 23
Electrical specifications for the power section . . . . . . . . . . . . . . . . . . . . . 24
Electrical specifications for the analog section . . . . . . . . . . . . . . . . . . . . . 25
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
STC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Programming of coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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STA382BWS Contents
Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6 Register description: New Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
STATUS register (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
RESET register (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Soft volume register (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
MVOL register (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
FINEVOL register (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
CH1VOL register (addr 0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
CH2VOL register (addr 0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
POST scaler register (addr 0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
OPER register (addr 0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
FUNCT register (addr 0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Obsolete Product(s) - Obsolete Product(s)
Configuration register A (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Interpolation ratio selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Fault-detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Configuration register B (addr 0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
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Contents STA382BWS
Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Configuration register C (addr 0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
FFX compensating pulse size register . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Configuration register D (addr 0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Configuration register E (addr 0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Configuration register F (addr 0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . 66
LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
External amplifier power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Volume control registers (addr 0x17 - 0x1B) . . . . . . . . . . . . . . . . . . . . . . 68
Mute/line output configuration register (addr 0x17) . . . . . . . . . . . . . . . . 68
Channel 3 / line output volume (addr 0x1B) . . . . . . . . . . . . . . . . . . . . . . 69
Audio preset registers (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
AM interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Obsolete Product(s) - Obsolete Product(s)
Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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STA382BWS Contents
Tone control register (addr 0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Dynamic control registers (addr 0x23 - 0x26 / addr 0x43 - 0x46) . . . . . . 74
Limiter 1 attack/release rate (L1AR addr 0x23) . . . . . . . . . . . . . . . . . . . 74
Limiter 1 attack/release threshold (L1ATRT addr 0x24) . . . . . . . . . . . . . 74
Limiter 2 attack/release rate ( L2AR addr 0x25) . . . . . . . . . . . . . . . . . . 74
Limiter 2 attack/release threshold ( L2 ATRT addr 0x26) . . . . . . . . . . . . 74
Limiter 1 extended attack threshold (addr 0x43) . . . . . . . . . . . . . . . . . . 78
Limiter 1 extended release threshold (addr 0x44) . . . . . . . . . . . . . . . . . 78
Limiter 2 extended attack threshold (addr 0x45) . . . . . . . . . . . . . . . . . . 79
Limiter 2 extended release threshold (addr 0x46) . . . . . . . . . . . . . . . . . 79
User-defined coefficient control registers (addr 0x27 - 0x37) . . . . . . . . . . 79
Coefficient address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Coefficient b1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Coefficient b1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Coefficient b1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Coefficient b2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Coefficient b2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Coefficient b2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Coefficient a1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Coefficient a1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Fault-detect recovery constant registers (addr 0x3C - 0x3D) . . . . . . . . . . 86
Extended configuration register (addr 0x47) . . . . . . . . . . . . . . . . . . . . . . 86
Extended post-scale range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Doc ID 022784 Rev 1 5/172
Contents
STA382BWS
Extended biquad selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
(address 0x52; 0x53; 0x54; 0x55; 0x56; 0x57) . . . . . . . . . . . . . . . . . . . . 88
Short-circuit protection mode registers SHOK (address 0x58) . . . . . . . . 90
Extended coefficient range up to -4...4 (address 0x5A) . . . . . . . . . . . . . . 91
Miscellaneous registers (address 0x5C, 0x5D) . . . . . . . . . . . . . . . . . . . . 92
Rate power-down enable (RPDNEN) bit . . . . . . . . . . . . . . . . . . . . . . . . 92
Bridge immediately off (BRIDGOFF) bit (address 0x4B, bit D5) . . . . . . 92
Channel PWM enable (CPWMEN) bit . . . . . . . . . . . . . . . . . . . . . . . . . . 93
External amplifier hardware pin enabler (LPDP, LPD LPDE) bits . . . . . 93
Power-down delay selector (PNDLSL[2:0]) bits . . . . . . . . . . . . . . . . . . . 93
Short-circuit check enable bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Bad PWM detection registers (address 0x5E, 0x5F, 0x60) . . . . . . . . . . . 94
Enhanced zero-detect mute and input level measurement
(address 0x61-0x65, 0x3F, 0x40, 0x6F) . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Headphone/Line out configuration register (address 0x66) . . . . . . . . . . . 97
F3XCFG (address 0x69; 0x6A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
configuration register (address 0x6B; 0x6C) . . . . . . . . 99
Charge pump synchronization (address 0x70) . . . . . . . . . . . . . . . . . . . . . 99
Coefficient RAM CRC protection (address 0x71-0x7D) . . . . . . . . . . . . . 100
MISC4 (address 0x7E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Register description: Sound Terminal compatibility . . . . . . . . . . . . . 104
Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Fault-detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
FFX compensating pulse size register . . . . . . . . . . . . . . . . . . . . . . . . . 113
Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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STA382BWS Contents
Zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
AM mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Zero-crossing enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . 122
LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
External amplifier power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Volume control registers (addr 0x06 - 0x0A) . . . . . . . . . . . . . . . . . . . . . 123
Mute/line output configuration register . . . . . . . . . . . . . . . . . . . . . . . . . 123
Master volume register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Channel 1 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Channel 2 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Channel 3 / line output volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Audio preset registers (addr 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Audio preset register (addr 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
AM interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Obsolete Product(s) - Obsolete Product(s)
Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Doc ID 022784 Rev 1 7/172
Contents STA382BWS
Tone control register (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Dynamic control registers (addr 0x12 - 0x15) . . . . . . . . . . . . . . . . . . . . 130
Limiter 1 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Limiter 1 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Limiter 2 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Limiter 2 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Limiter 1 extended attack threshold (addr 0x32) . . . . . . . . . . . . . . . . . 134
Limiter 1 extended release threshold (addr 0x33) . . . . . . . . . . . . . . . . 134
Limiter 2 extended attack threshold (addr 0x34 . . . . . . . . . . . . . . . . . ) 135
Limiter 2 extended release threshold (addr 0x35) . . . . . . . . . . . . . . . . 135
User-defined coefficient control registers (addr 0x16 - 0x26) . . . . . . . . . 135
Coefficient address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Coefficient b1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . 135
Coefficient b1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Coefficient b1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Coefficient b2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . 136
Coefficient b2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Coefficient b2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Coefficient a1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . 136
Coefficient a1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Fault-detect recovery constant registers (addr 0x2B - 0x2C) . . . . . . . . . 142
Device status register (addr 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
EQ coefficients configuration register (addr 0x31) . . . . . . . . . . . . . . . . . 142
Extended configuration register (addr 0x36) . . . . . . . . . . . . . . . . . . . . . 143
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STA382BWS Contents
Extended post-scale range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Extended attack rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Extended BIQUAD selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
EQ soft volume configuration registers (addr 0x37 - 0x38) . . . . . . . . . . 146
Extra volume resolution configuration registers (address 0x3F; 0x40) . . 147
(address 0x41; 0x42; 0x43; 0x44; 0x45; 0X46) . . . . . . . . . . . . . . . . . . . 148
Short-circuit protection mode registers SHOK (address 0x47) . . . . . . . 150
Extended coefficient range up to -4...4 (address 0x49, 0x4A) . . . . . . . . 152
Miscellaneous registers (address 0x4B, 0x4C) . . . . . . . . . . . . . . . . . . . 152
Rate power-down enable (RPDNEN) bit (address 0x4B, bit D7) . . . . . 152
Bridge immediately off (BRIDGOFF) bit (address 0x4B, bit D5) . . . . . 153
Channel PWM enable (CPWMEN) bit (address 0x4B, bit D2) . . . . . . . 153
External amplifier hardware pin enabler (LPDP, LPD LPDE) bits
(address 0x4C, bit D7, D6, D5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Power-down delay selector (PNDLSL[2:0]) bits
(address 0x4C, bit D4, D3, D2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Short-circuit check enable bit (address 0x4C, bit D0) . . . . . . . . . . . . . 154
Bad PWM detection registers (address 0x4D, 0x4E, 0x4F) . . . . . . . . . . 155
Enhanced zero-detect mute and input level measurement
(address 0x50-0x54, 0x2E, 0x2F and 0x5E) . . . . . . . . . . . . . . . . . . . . . 156
Headphone/Line out configuration register (address 0x55) . . . . . . . . . . 158
F3XCFG (address 0x58; 0x59) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
configuration register (address 0x5A; 0x5B) . . . . . . . 160
Charge pump synchronization (address 0x5F) . . . . . . . . . . . . . . . . . . . 161
Coefficient RAM CRC protection (address 0x60-0x6C) . . . . . . . . . . . . . 162
MISC3 (address 0x6E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
MISC4 (address 0x7E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Obsolete Product(s) - Obsolete Product(s)
Headphone and 2 Vrms line out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
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Contents
STA382BWS
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10/172 Doc ID 022784 Rev 1
List of tables STA382BWS
List of tables
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List of tables STA382BWS
12/172 Doc ID 022784 Rev 1
STA382BWS List of tables
2
C registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
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List of tables STA382BWS
configuration bits1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
configuration bits 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
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List of figures STA382BWS
List of figures
Processing path, second part: 2.1 output with individually configurable anticlipper/DRCs. 27
Processing path, second part: 2.0 output with B
2
DRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Processing path, second part: 2.1 output configuration with STCompressor
. . . . . . . . . 28
block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
behavior as a limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DRC scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
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DRC scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
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List of figures STA382BWS
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STA382BWS
1 Description
Description
The STA382BWS is an integrated solution embedding digital audio processing, digital amplification, FFX
TM the Sound Terminal
®
power output stage, headphone and 2 Vrms line outputs. It is part of family and provides full digital audio streaming from the source to the speaker, offering cost effectiveness, low power dissipation and sound enrichment.
The STA382BWS input section consists of a flexible digital input serial audio interface, feeding the digital processing unit, and an analog 1 Vrms input for a seamless connection with pure analog sources. The serial audio data input interface supports many formats, including the popular IIS format.
The STA382BWS is based on an FFX
TM
(Fully Flexible Amplification) processor, proprietary technology from STMicroelectronics. FFX
TM
is the evolution of the ST ternary technology: the advanced processor is available for ternary, binary, binary differential and phase shift
PWM modulation. STA382BWS embeds the ternary, binary and binary differential implementations, a subset of the full capability of the FFX
TM
processor.
The STA382BWS power section consists of four independent half-bridges. These can be configured via digital control to operate in different modes. A 2.1-channel setup can be implemented with two half-bridges (L/R) together with a single full-bridge (subwoofer).
Alternatively, the 2.0-channel setup can be done with two full-bridges. When using this configuration, an external amplifier for the SW channel can also be driven through the PWM output. The STA382BWS is able to deliver 2 x 20 W (ternary) into an 8 Ω load at 18 V or
2 x 9 W (binary) into a 4 Ω load, plus 1 x 20 W (ternary) into an 8 Ω load at 18 V.
The STA382BWS also provides a capless headphone out (with embedded negative charge pump), able to deliver up to 40 mW into a 32 Ω load or, alternatively, can be configured as a
2 Vrms line output.
The STA382BWS digital processing unit includes up to 12 programmable biquads (EQs), allowing perfect sound equalization and offering advanced noise-shaping techniques.
Moreover, the coefficient range ensures a great variety of filter shapes (low/high-pass, low/high shelf, peak, notch, band-pass). The equalization engine is fully compatible with the
ST speaker compensation technology embedded into the APWorkbench suite. A state-ofthe-art multi-band DRC, STCompressor
TM
, equalizes the system to provide active speaker protection with full audio quality preservation against sudden sound peaks. Moreover,
STSpeakerSafe
TM
technology offers reliable speaker protection under any condition. The master clock can be from stable BICKI (64xfs, 50% duty cycle) or external XTI.
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Description STA382BWS
Figure 1.
Block diagram
MCLK
LRCKI
BICKI
SDI
STA382BWS
2.1 Channel
Audio Processor
STAudioFx TM
STSpeakerSafe TM
Parametric EQ
Volume
Bass and Treble
Speaker Compensation
Stereo Widening
FFX TM
Modulator
Binary
Ternary
4
Half
Bridges
OUT 1A
OUT 1B
OUT 2A
OUT 2B
FFX3A
FFX3B
EAPD/FFX4B
TWARN/FFX4A
F3XL
F3XR
LINEINL
LINEINR
TESTMODE
PWDN
INTLINE
RESET
SA
SDA
SCL
IIC
Control logic
&
Protections
PLL
Headphone
(2Vrms)
-3.3V
Negative
Charge
Pump
LINEHPOUT_L
LINEHPOUT_R
SOFT_MUTE
CPVSS
CPP
CPM
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STA382BWS Pin connections
Figure 2.
Pin connections VQFN48 (top view)
VCC_REG 1
V SS _REG
2
OUT2B 3
GND2 4
VCC2 5
OUT2A
OUT1B
6
7
VCC1 8
GND1 9
OUT1A 10
VDD_REG 11
GND_REG 12
S TA 38 2BW S
3 6 MCLK
3 5
AGNDPLL
3 4 VREGFILT
33 TWARN/FFX4A
3 2 EAPD/FFX4B
3 1 FFX 3 B
3 0 FFX 3 A
29 GNDDIG1
2 8 VDDDIG1
27 VDD 3 V 3 CHP
26 CPP
25 GNDP S UB
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Pin connections STA382BWS
20/172
26
27
28
29
30
31
Table 2.
Pin list
VQFN 48-pin
13
14
15
16
9
10
11
12
7
8
5
6
3
4
1
2
21
22
23
24
17
18
19
20
Name
LINEINR
LINEHPOUT_L
LINEHPOUT_R
GNDA
SOFTMUTE
VDD3V3
CPVSS
CPM
GNDPSUB
CPP
VDD3V3CHP
VDDDIG1
GNDDIG1
FFX3A
FFX3B
VCC_REG
VSS_REG
OUT2B
GND2
VCC2
OUT2A
OUT1B
VCC1
GND1
OUT1A
VDD_REG
GND_REG
F3X_FILT
F3XL
F3XR
LINEINL
Type
INPUT
OUTPUT
OUTPUT
POWER
INPUT
POWER
POWER
FILTER
POWER
FILTER
POWER
POWER
POWER
OUTPUT
OUTPUT
POWER
POWER
OUTPUT
POWER
POWER
OUTPUT
OUTPUT
POWER
POWER
OUTPUT
POWER
POWER
POWER
OUTPUT
OUTPUT
INPUT
Description
VCC reg
Vss reg, VCC_REG-3.3 V
Half-bridge 2B output
Half-bridge 2A and 2B ground
Half-bridge 2A and 2B supply
Half-bridge 2A output
Half-bridge 1B output
Half-bridge 1A and 1B supply
Half-bridge 1A and 1B ground
Half-bridge 1A output
VDD reg 3.3 V
DC reg ground
F3X reference voltage
F3X analog out left channel
F3X analog out right channel
Line in left channel
Line in right channel
Headphone/line driver left channel
Headphone/line driver right channel
Headphone/line driver power ground
Soft mute
+3 V LDO power supply
-3.3 V charge pump pin
CHP Cfly negative
Charge pump ground
CHP Cfly positive
Charge pump power supply
I/O ring power supply
Digital core ground
Digital PWM line out
Digital PWM line out
Doc ID 022784 Rev 1
STA382BWS
Table 2.
Pin list (continued)
VQFN 48-pin Name
36
37
38
39
40
32
33
34
35
EAPD/FFX4B
TWARN/FFX4A
VREGFILT
AGNDPLL
MCLK
BICKI
LRCKI
SDI
RESET
41
46
47
48
42
43
44
45
PWDN
INTLINE
SDA
SCL
SA
TEST_MODE
GNDDIG2
VDDDIG2
Pin connections
Type
OUTPUT
OUTPUT
POWER
POWER
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
I/O
INPUT
INPUT
INPUT
POWER
POWER
Description
Digital PWM line out
Digital PWM line out
Digital VDD from core
PLL analog ground
PLL input clock
IIS serial clock
IIS left/right clock
IIS serial data input
Reset
Device power-down
0 = power-down
1 = normal operation
Fault interrupt
IIC serial data
IIC serial clock
IIC select address (pull-down)
This pin must be connected to ground (pull-down)
Digital I/O ground
Digital core LDO supply
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Electrical specifications STA382BWS
3.1 Absolute maximum ratings
Table 3.
Symbol
Absolute maximum ratings
Parameter
Vcc
VDD_DIG
Power supply voltage (VCCxA, VCCxB)
Digital supply voltage
VDD3V3
VDD3V3CHP
Charge pump and analog path LDO supply
Top
Tstg
R
Line
R
Hp
R
Btl
Operating junction temperature
Storage temperature
Load impedance - line driver mode
Load impedance - headphone driver mode
Load impedance - power output-BTL mode
-0.3
0
-40
1
16
5
Min Typ Max Unit
-0.3
-0.3
27
4
V
V
4 V
150 °C
150 °C k Ω
Ω
Ω
Warning:
Stresses beyond those listed in Table 3
above may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under
“Recommended operating conditions” are not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. In the real application, power supplies with nominal values rated within the recommended operating conditions may rise beyond the maximum operating conditions for a short time when no or very low current is sunk (amplifier in mute state). In this case the reliability of the device is guaranteed, provided that the absolute maximum ratings are not exceeded.
Obsolete Product(s) - Obsolete Product(s)
Table 4.
Thermal data
Symbol Parameter Min Typ Max Unit
Rth j-case
Tth-sdj
Tth-w
Tth-sdh
Thermal resistance junction-case (thermal pad)
Thermal shutdown junction temperature
Thermal warning temperature
Thermal shutdown hysteresis
150
130
20
1.5
°C/W
°C
°C
°C
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STA382BWS
3.3 Recommended operating conditions
Table 5.
Symbol
Recommended operating conditions
Parameter
Vcc
VDD_DIG
Power supply voltage (VCCxA, VCCxB)
Digital supply voltage
VDD3V3
VDD3V3CHP
Charge pump and analog path LDO supply
Tamb
R
Line
R
Hp
R
Btl
Ambient temperature
Load impedance - line driver mode
Load impedance - headphone driver mode
Load impedance - power output-BTL mode
3.4
Electrical specifications
2.7
16
5
0
5
Min Typ Max Unit
4.5
2.7
3.3
25.5
3.6
V
V
3.3
10
32
8
3.6
70
V
°C k Ω
Ω
Ω
Electrical specifications for the digital section
The specifications given in this section are valid for the operating conditions:
VDD_DIG = 3.3 V, T amb
= 25 °C.
(shou
Table 6.
Electrical specifications - digital section
Symbol Parameter Conditions
I il
I ih
V il
V ih
V ol
V oh
R pu
Low level input current without pull-up/down device
High level input current without pull-up/down device
Low level input voltage
High level input voltage
Low level output voltage
High level output voltage
Pull-up/down resistance
Vi = 0 V
Vi = VDD_DIG
= 3.3 V
Iol = 2 mA
Ioh = 2 mA
Min
2.0
VDD_DIG
-0.15
Typ
50
Max
0.5
0.1
0.8
0.15
Unit
µA
µA
V k Ω
V
V
V
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Electrical specifications STA382BWS
The specifications given in this section are valid for the operating conditions: V
CC f = 1 kHz, f sw
= 384 kHz, T amb
= 25° C and R
L
= 8 Ω , unless otherwise specified.
= 18 V,
Table 7.
Symbol
Electrical specifications - power section
Parameter Conditions
Po
Output power BTL
Output power SE
Low current dead time (static)
Digital limited
(1)
Digital limited
(1)
R dsON gP gN
Output power SE R
L
= 4 Ω
Power Pchannel/Nchannel MOSFET
Power Pchannel R dsON
matching
Power Nchannel R dsON
matching
Idss Power Pchannel/Nchannel leakage l l l
Digital limited d d d
= 1.5 A
= 1.5 A
= 1.5 A
(1)
Resistive load
(2)
I
LDT t r t f
Rise time
Fall time
Resistive load
Resistive load
(2)
(2)
Supply current from Vcc in power-down PWRDN = 0
I vcc
Supply current from Vcc in operation
PCM Input signal = -60 dBfs,
Switching frequency = 384 kHz,
No LC filters
Ilim Overcurrent limit
UVL Undervoltage protection t min
DR
Output minimum pulse width
Dynamic range
SNR
THD+N
Signal-to-noise ratio, ternary mode
Signal-to-noise ratio binary mode
Total harmonic distortion + noise
No load
A-weighted
A-weighted
FFX stereo mode, Po = 1 W, f = 1 kHz,
Min
95
95
4
20
8
10
10
0.1
Typ Max Unit
20
5
9
120
W m Ω
%
%
10 µA
15 ns
18 ns
18 ns
1 µA
52
5
3.5
30
100
100
90
0.2
60 mA
6.5
A
4.3
V
60 ns dB dB dB
%
FFX stereo mode,
X
TALK
Crosstalk
<5 kHz, one channel driven at
Obsolete Product(s) - Obsolete Product(s) measured
80 dB
η
Peak efficiency, FFX mode
Po = 2 x 20 W into 8 Ω
1.
The related THD can be defined through appropriate DRC settings (see section: 4.3: STCompressorTM )
2.
Refer to Figure 3: Test circuit .
90 %
24/172 Doc ID 022784 Rev 1
STA382BWS
Figure 3.
Test circuit
Electrical specifications
The specifications given in this section are valid for the operating conditions: f = 1 kHz, T amb
= 25 °C, VDD3V3 = 3.3 V, R
Line
= 5 k
Ω
, R
Hp
= 32
Ω
, unless otherwise specified.
Table 8.
Symbol
Electrical specifications for the analog section
Parameter Conditions
Vout
Pout
Output voltage for line out
Output voltage for HP out
G v
= 2.5, THD < 1%, Rload = 5 k
Ω
THD+N = 10%, G v
= 2.5, Rload = 32 Ω
DR Dynamic range for line out
Vout = 2 V
RMS
, F in
= 200 Hz,
V in
= 0.8 mV (-60 dBFs)
X-Talk Channel separation for line out V out
= 2 Vrms, G v
= 2.5
HP mode, P
0
= 15 mW
PSRR Power supply rejection ratio
Line out mode, V
Out
= 2 Vrms
Min Typ Max Unit
1.9
40
2.1
Vrms mW
100
75
70
70 dB dB dB
THD+N Total harmonic distortion + noise
HP mode, V out
= 200 mV
RMS
, G v
= 2.5
Line out mode, V
Out
= 0.2 Vrms, G v
= 2.5
0.03
0.03
1.
Refer to 8.2: Headphone and 2 Vrms line out
,
Figure 47: Headphone and line out block diagram , R
in
= R1 k Ω
%
%
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Device overview STA382BWS
The mentioned hyperlink in this section relates to the default New Map
Section 6: Register description: New Map
.
4.1 Processing data path
The whole STA382BWS processing chain is composed of two consecutive sections. In the first one dual-channel processing is implemented (
) and then each channel is fed into the post-mixing block allowing to generate either a third channel (typically used in 2.1 output configurations together with crossover filters) or to have the channels processed by the dual-band DRC block (2.0 output configuration with crossover filters used to define the cutoff frequency of the two bands).
The first section begins with a 2x oversampling FIR filter allowing 2*Fs audio processing.
Then a selectable high-pass filter removes the DC level (enabled if HFB = 0). The channel 1 and 2 processing chain can include up to 8 filters, depending on the selected configuration
(bits BQL, BQ5, BQ6, BQ7 and XO[3:0]). By default, 4 independent filters per channel are enabled, plus the pre-configured Bass and Treble controls (BQL=0, BQ5=0, BQ6=0,
BQ7=0).
The STA382BWS offers the possibility to share the filter coefficients between the two processing channels. When this option is set (BQL=1), filters from the 1st to the 4th have the same coeffcients set. Under these conditions, filters from the 5th to 7th can be used as custom filters as well (provided the relevant BQx bits are set). Once again filter coefficients are shared between the two processing channels.
Moreover the common 8th filter, from the subsequent processing section, can be available on both channels (provided the pre-defined crossover frequencies are not used, XO[3:0]=0, and the dual-band DRC is not used).
Figure 4.
Processing path, first part
Sa mpling Fre qu ency = 2xF s
X2Over-
sa mpling
FIR
-
Pres c a le
Hi-P ass
Filter
Bi qua d
#1
Bi qua d
#2
Bi qua d
# 3
Bi qua d
#4
De-emph
Or
Bi qua d #5
B ass
Or
Bi qua d #6
Tre b le
Or
Bi qua d #7
U s erd Defined Filter s Tone Control
Sa mpling Fre qu ency = F s
I2 S Inp u t
Interf a ce
Obsolete Product(s) - Obsolete Product(s)
X2OverDe-emph B ass Tre b le
PreHi-P ass Bi qua d Bi qua d Bi qua d Bi qua d R
sa mpling
FIR
s c a le Filter #1 #2 # 3 #4
Or
Bi qua d #5
Or
Bi qua d #6
Or
Bi qua d #7
Sa mpling Fre qu ency = 2xF s
U s erd Defined Filter s Tone Control
L
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STA382BWS Device overview
The second processing stage embeds a mixing block, a biquadratic/crossover filter, a DRC stage, the volume control, a DC cut filter and a post scaler. Depending on the device settings, the following configuration and features are available:
●
2.1 output with individually configurable anticlipper/DRCs ( Figure 5 ): two individually
configurable DRC/anticlippers are available while the eighth biquadratic filter, jointly with the mixer block, can be used to perform LFE. This configuration and features ensure the backward compatibility with previous Sound Terminal
®
products.
Figure 5.
Processing path, second part: 2.1 output with individually configurable anticlipper/DRCs
L
R
C1Mx1
+
C1Mx2
Ch a n n el ½
Bi q ua d # 8
--------------
Hi-p ass XO
Filter
Ch a n n el 1
Vo l u me
An ti-clipper
/
DRC
DC C u t
Filter
Po s t S c a le
C2Mx1
+
C2Mx2
Ch a n n el ½
Bi q ua d # 8
--------------
Hi-p ass XO
Filter
Ch a n n el 2
Vo l u me
An ti-clipper
/
DRC
DC C u t
Filter
Po s t S c a le
C 3 Mx1
+
C 3 Mx2
Ch a n n el 3
Bi q ua d # 8
--------------
Lo w-p ass XO filter
U s er-D efined
M ix C oeffic ient s
C ro s s ov er F re qu enc y
D eterm ined b y XO S etting
(U s er Defin ed If
XO =0000)
Ch a n n el 3
Vo l u me
An ti-clipper
/
DRC
DC C u t
Filter
Po s t S c a le
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Device overview STA382BWS
● 2.0 output with B
2
DRC (
Figure 6 ): the mixer and the eighth biquadratic filter are used to
divide the channel into two sub-bands, then each sub-band is independently processed by a DRC block. The two bands are then re-composed and fed to the following processing blocks. The crossover frequency is user-selectable. This configuration and features ensure the backward compatibility with the previous Sound Terminal
® products. For further information please refer to
Chapter 6.11.1: Dual-band DRC .
Figure 6.
Processing path, second part: 2.0 output with B
2
DRC
Ch a nnel 3
Vol u me
DRC 2
L
R
C1Mx1
+
C1Mx2
C2Mx1
+
C2Mx2
B 2 DRC
Hi-p ass XO filter
-
+
B 2 DRC
Hi-p ass XO filter
- +
Ch a nnel 1
Vol u me
Ch a nnel 2
Vol u me
DRC 1
+
DC C u t
Filter
DRC 1
Po s t S c a le
C 3 Mx1
+
C 3 Mx2
Ch a nnel 3
Vol u me
DRC 2
+
DC C u t
Filter
Po s t S c a le
●
U s er-Defined
Mix Coefficient s
Cro ss over Fre qu ency
Determined b y XO S etting
(U s er Defined If
XO=0000)
2.1 output with STCompressor
TM
(
Figure 7 ): the STA382BWS embeds the latest, state-
of-the-art multi-band dynamic, range compressor, called STCompressor
TM
. When using this configuration, up to 10 biquad filters are available for dedicated processing.
Please refer to Section 4.3: STCompressorTM
for further information about this feature.
Figure 7.
Processing path, second part: 2.1 output configuration with
STCompressor
TM
L
R
C1Mx1
+
C1Mx2
Ch a nnel ½
Bi qua d # 8
--------------
Hi-p ass XO
Filter
S TCompre ss or
Vol u me
And
Limiter
DC C u t
Filter
Po s t S c a le
C2Mx1
Ch a nnel ½
Bi qua d # 8 Vol u me
+ S TCompre ss or And
Limiter
DC C u t
Filter
Po s t S c a le --------------
Hi-p ass XO
C2Mx2
Filter Obsolete Product(s) - Obsolete Product(s)
C 3 Mx1
Ch a nnel 3
+
Bi qua d # 8
--------------
Low-p ass XO filter
Vol u me
And
Limiter
DC C u t
Filter
Po s t S c a le
C 3 Mx2
U s er-Defined
Mix Coefficient s
Cro ss over Fre qu ency
Determined b y XO S etting
(U s er Defined If
XO=0000)
28/172 Doc ID 022784 Rev 1
STA382BWS Device overview
Figure 4 shows the input oversampling block in front of the main processing. When 32 kHz
Fs is used, the default x2 oversampling ratio can be increased to a x3.
Activating this feature, it is possible to have a 384 kHz PWM switching frequency (instead of the default 256 kHz) when 32 kHz Fs is used.
When bit 0 of register PLLCFG1 is set to one, the feature is activated so that the PLL ratio is modified to generate 49.152 MHz internal clock and the audio data path (after the input oversampling block) is running at 96 kHz.
It is not recommended to use the x3 oversampling feature when Fs > 32 kHz because of the
PLL maximum frequency constraint.
4.3 STCompressor
TM
The STCompressor
TM
(STC from now on) is a stereo, dual-band Dynamic Range Control
(DRC) and its main purpose is to provide optimum output power level control for speaker protection, preserving as much as possible the original audio quality of the signal.
Two main I
2
C registers control the STC behavior: STCCFG0 and STCCFG1. On top of the data flow control bits, these registers also allow enabling the checksum engine to protect the
STC filters from erroneous coefficients downloads, thus improving the final application circuitry and safety of the speakers.
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Device overview STA382BWS
Figure 8.
STCompressor
TM
block diagram
DRC 0
B a n d 0
(Lo w fre q s )
In p u t
Ch 0
B a n d
S p litter
B a n d 1
(Hig h fre q s )
Level
Meter
Level
Meter
M a p p er
DRC 1
M a p p er
O ff s et
Atten ua to r
Atten ua to r
O ff s et
B a n d 0
(Lo w fre q s )
In p u t
Ch 1
B a n d
S p litter
B a n d 1
(Hig h fre q s )
Lev el
Meter
Lev el
Meter
DRC 2
O ff s et
Atten ua to r M a p p er
DRC 3
M a p p er Atten ua to r
O ff s et
X
X
+
O u tp u t
Ch 0
X
+
O u tp u t
Ch 1
X
The STC takes as input 2 channels and every channel is processed independently (i.e. an independent DRC for each band of each channel) following the steps listed below
(
1.
Splits the input signal into 2 bands (band splitter)
2. Measures the level of the signal (level meter)
3. Computes the attenuation (mapper)
4. Applies the attenuation and offset (attenuator)
The band splitter settings are common to both the processing channels while the settings of the remaining blocks can be independently set for each band of each processing channel.
Caution: All the settings explained hereafter apply only to the behavior of the STCompressor
TM
. For
the settings concerning other device operating configurations (see Chapter 4.1: Processing
Obsolete Product(s) - Obsolete Product(s)
The band splitter block is used to divide the signal into 2 sub-bands (typically low- and high- frequency bands). This is done through two 2 nd
order biquads (IIR filters) for each band, thus allowing to have up to a 4 th
order filter per band. This feature guarantees a totally flat
band recombination (see Figure 9
). Using different filtering orders, indeed, causes a nonnegligible gain around the filter’s cutoff frequency, endangering the overall audio fidelity and, eventually, also the safety of the speaker. The sub-band recombination can be enabled or disabled.
30/172 Doc ID 022784 Rev 1
STA382BWS Device overview
The band splitter filter coefficients have a user-selectable range [-1, 1), [-2, 2) and [-4, 4).
The RAM coefficient 0x7 is responsible for these settings according to
default value is [-4, 4).
Table 9.
Coefficients extended-range configuration 0x74h
CEXT_Bx[1] CEXT_Bx[0]
0
0
1
1
0
1
0
1
Range
[-1;1)
[-2;2)
[-4;4)
Reserved
Please refer to Section 6.24: User-defined coefficient control registers (addr 0x27 - 0x37)
and to
Figure 9.
Band splitter with 4 th
order filtering
BQ 0
B a nd S plitter
BQ 1
Inp u t
Ch x
B a nd 0
…
O u tp u t
Ch x
+ =
BQ 0 BQ 1
B a nd 1
…
The level meter block measures the input signal level (in dB). Two kinds of measures are performed: peak and RMS. The mapper configuration and the input signal automatically determine which measurement to take into account.
Obsolete Product(s) - Obsolete Product(s)
4.3.4 Mapper
The mapper block computes the appropriate attenuation value (expressed in dB) to be applied to the signal, basing its calculations on the level meter output value, on the compressor threshold and on the limiter threshold.The attenuation value is then passed to the attenuator block.
Doc ID 022784 Rev 1 31/172
Device overview STA382BWS
The STC reacts differently depending on these three parameters (
):
● level meter output value < compressor threshold < limiter threshold: under these circumstances the signal level is small enough to not require any type of limiting/compressing action. The signal remains unchanged.
●
● compressor threshold < level meter output value < limiter threshold: under these circumstances the signal level is compressed to a ratio determined by the compressor rate.
compressor threshold < limiter threshold < level meter output value: under these circumstances the signal level exceeds the limiter threshold which represents the maximum output power allowed. The signal is limited to avoid unpredictable effects and damages.
The compressor threshold, the limiter threshold and the compressor rate are all userselectable parameters. The compressor threshold range of value is [-48, 0] dB with a
0.25 dB step. The limiter threshold range of values is [-24, +12] dB with a 0.25 dB step. The compressor ratio range of value is [0, 15], the meaning of these values is specified in
. For further details please refer to
. Either setting the compressor rate to
1:1 or setting the compressor threshold greater than the limiter threshold makes the STC
behave as a pure limiter ( Figure 11 ).
Figure 10.
STCompressor
TM
behavior
Linear Zone
Compression Zone
Limiting Zone
L.T.
C.R.
C.T.
C.T.
L.T.
INPUT
L.T. comp
[dB]
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32/172 Doc ID 022784 Rev 1
STA382BWS
Figure 11.
STCompressor
TM
behavior as a limiter
Linear Zone
Limiting Zone
Device overview
L.T.
L.T.
INPUT
[dB]
Table 10.
Compressor ratio
Compressor ratio Ratio value
5
6
3
4
0
1
2
9
10
7
8
1:1
1:1.25
1:1.5
1:1.75
1:2
1:2.5
1:3
1:3.5
1:4
1:4.5
1:5
11 1:5.5
12
13
1.6
Obsolete Product(s) - Obsolete Product(s)
14 1:8
15 1:16
Doc ID 022784 Rev 1 33/172
Device overview STA382BWS
4.3.5 Attenuator
The attenuation is characterized by two different phases: attack and release.
Given an input signal above the limiter threshold, during the attack phase the STC decreases the gain in order to reach the output level determined by the mapper. In this process the key parameter is the attack rate (dB/ms) which determines how fast the STC reacts according to the following equation:
AttackTime =
OutputSignalLevel – MapperLevel
AttackRate where:
● Output Signal Level used as feedback is the attenuated signal coming from the attenuator block itself and
● Mapper Level is the target signal level to be reached
The attack rate is user-selectable and its range is [0, +16] dB/ms with a 0.25 dB/ms step.
Given an input signal moving below the limiter threshold, during the release phase the STC increases the gain in order to return the original input signal dynamic. In this process the key parameter is the release rate (dB/ms) which determines how fast the STC releases the attenuation on the input signal according to the following equation:
ReleaseTime =
OutputSignalLevel – MapperLevel
ReleaseRate
The release rate is user-selectable and its range is [0.0078, 1) dB/ms with a 0.0039 dB/ms step.
Due to its dynamic, the input signal may exceed the limiter threshold by a variable amount of decibels. In such different situations it might be useful to be able to tune the attack rate to make the STC react slower or faster depending on the context. The attack rate value, set by the user, can be dynamically varied through the dynamic attack rate (DAR). It is a parameter
(expressed in ms/dB) acting as a weighted coefficient, multiplying the difference between the attenuator output signal and the mapper target level. The dynamic attack rate affects the user-programmed attack rate according to the following equations:
DynamicAttackTime =
(
OutputSignalLevel – MapperLevel
) ×
DAR
Obsolete Product(s) - Obsolete Product(s)
AttackTime =
OutputSignalLevel – MapperLevel
AttackRate
+ DynamicAttackTime
⇒
AttackRate = ---------------------------------------------------------------------------------------------------
AttackTime – DynamicAttackTime
The DAR is user-definable and its range of values is [0, +1) ms/dB, ( Table 12
) with a
0.0039 ms/dB step. The DAR is the same for all 4 sub-bands.
34/172 Doc ID 022784 Rev 1
STA382BWS Device overview
4.3.7 Offset
The offset is a user-selectable gain or volume control. When using the STC it is advised to use the offset to tune the output volume instead of the regular volume controls. The offset is located before the attenuator block, ensuring that the output power limit (limiter threshold) is never exceeded (
). On the other side, the traditional volume control is located after the STC attenuator, thus a wrong setting of this control could nullify the STC effect.
Each sub-band has its own and independent offset. Its range is [0, +48] dB with a 0.25 dB
Figure 12.
Offset effect
The stereo link feature allows applying the same attenuation to the corresponding band of each channel (i.e. band 0 left channel and band 0 right or band 1 left channel and band 1 right channel). This should help to prevent image shifting that could occur when individually compressing each channel and causing a volume mismatch between left and right.
When the stereo link is active, the proper attenuation for each band is independently
computed, then the highest one for each band is applied ( Figure 13
).
Obsolete Product(s) - Obsolete Product(s)
Doc ID 022784 Rev 1 35/172
Device overview
Figure 13.
Stereo link block diagram
Ch 0 – B a nd 0
From m a pper
Ch 0 – B a nd 0
Atten ua tor
Atten ua tor
Atten ua tor
M a x
Atten ua tion
B a nd 0
Atten ua tor
From m a pper
Ch 0 – B a nd 1
Ch 0 – B a nd 1
Ch 1 – B a nd 0
From m a pper
Ch 1 – B a nd 0
Atten ua tor
Atten ua tor
Atten ua tor
M a x
Atten ua tion
B a nd 1
Atten ua tor
From m a pper
Ch 1 – B a nd 1
Ch 1 – B a nd 1
STA382BWS
X
X
+
O u tp u t
Ch 0
X
X
+
O u tp u t
Ch 1
The coefficients are expressed in different value ranges and in decimal notation (refer to the previous paragraphs). In order to be programmed they must be converted into a
[-1, +1) range and in hexadecimal notation (
Table 11 ). This can be achieved with the
following procedure:
● if CoeffDecValue>0
CoeffI2CValue = ( ( 6 ) × 2
23 )
● if CoeffDecValue<0
CoeffI2CValue = 2
24
–
( ( ⁄ 6 ) × 2
23 ) where CoeffI2CValue is the final decimal value to be converted into hexadecimal notation while CoeffDecValue is the coefficient value (in decimal notation) to start from.
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36/172 Doc ID 022784 Rev 1
STA382BWS
Table 11.
Conversion example
Original value (dec)
-01.00
-02.00
-06.00
-12.00
-24.00
-48.00
+48.00
+24.00
+16.00
+12.00
+06.00
+02.00
+01.00
Device overview
I
2
C value (hex)
0x600000
0x300000
0x200000
0x180000
0x0C0000
0x040000
0x020000
0xFE0000
0xFC0000
0xF40000
0xE80000
0xD00000
0xA00000
Obsolete Product(s) - Obsolete Product(s)
Doc ID 022784 Rev 1 37/172
Device overview STA382BWS
All the control parameters listed in the previous paragraphs are stored in the internal device memory. Please refer to
for a complete list of their addresses.
For the programming procedure please refer to
the STC coefficients memory.
Table 12.
STC coefficients memory map
Function Address Parameter
0x54 RR: release rate
0x55 AR: attack rate
0x56 LT: limiter threshold
0x57 CR: compressor ratio
0x58 CT: compressor threshold
Range
[0.0078,1)
[0,16]
[-24, +12]
[0,15]
[-48, 0]
Precision Unit
0.0039
0.25
0.25
1
0.25
dB/ms dB/ms dB index dB
Default
0x200000
0x200000
0x000000
0x000000
0x000000
0x59 RR: release rate
05A AR: attack rate
0x5B LT: limiter threshold
0x5C CR: compressor ratio
0x5D CT: compressor threshold
[0.0078,1)
[0,16]
[-24, +12]
[0,15]
[-48, 0]
0x5E RR: release rate
0x5F AR: attack rate
0x60 LT: limiter threshold
0x61 CR: compressor ratio
0x62 CT: compressor threshold
[0.0078,1)
[0,16]
[-24, +12]
[0,15]
[-48, 0]
0.0039
0.25
0.25
1
0.25
0.0039
0.25
0.25
1
0.25
dB/ms dB/ms dB index dB dB/ms dB/ms dB index dB
0x200000
0x200000
0x000000
0x000000
0x000000
0x200000
0x200000
0x000000
0x000000
0x000000
Dynamic attack rate
CRC expected
CRC computed
Biquads CTRL
0x63 RR: release rate
0x64 AR: attack rate
0x65 LT: limiter threshold
0x66 CR: compressor ratio
0x67 CT: compressor threshold
[0.0078,1)
[0,16]
[-24, +12]
[0,15]
[-48, 0]
0X68 OFS0: offset DRC 0 [0, +48] 0.25
dB 0x000000
OFFSET
0X69 OFS1: offset DRC 1
0X6A OFS2: offset DRC 2
[0, +48]
[0, +48]
0.25
0.25
dB dB
0x000000
0x000000
0X6B OFS3: offset DRC 3 [0, +48] 0.25
dB 0x000000
0x71 DAR: dynamic attack rate
0x72
0x73
0x74
Band splitter filter coefficients range
[0, 1)
0.0039
0.25
0.25
1
0.25
0.0039
dB/ms dB/ms dB index dB ms/dB
0x200000
0x200000
0x000000
0x000000
0x000000
0x000000
0x0000AA
38/172 Doc ID 022784 Rev 1
STA382BWS
Table 13.
STC band splitter filters memory map
Function Address Coefficient
0x40
0x41
0x42
0x43
0x44
B1/2
B2
-A1/2
-A2
B0/2
Range
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
B1/2
B2
-A1/2
-A2
B0/2
B1/2
B2
-A1/2
-A2
B0/2
B1/2
B2
-A1/2
-A2
B0/2
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
[-1, 1), [-2, 2), [-4, 4)
Device overview
Default
0x000000
0x000000
0x000000
0x000000
0x100000
0x000000
0x000000
0x000000
0x000000
0x100000
0x000000
0x000000
0x000000
0x000000
0x100000
0x000000
0x000000
0x000000
0x000000
0x100000
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Doc ID 022784 Rev 1 39/172
I
2
C bus specification
5 I
2
C bus specification
STA382BWS
The STA382BWS supports the I
2
C protocol via the input ports SCL and SDA_IN (master to slave) and the output port SDA_OUT (slave to master). This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver.
The device that controls the data transfer is known as the master and the other as the slave.
The master always starts the transfer and provides the serial clock for synchronization. The
STA382BWS is always a slave device in all of its communications. It supports up to
400 kb/sec rate (fast-mode bit rate). The STA382BWS I
2
C is a slave-only interface. The I
2
C interface works properly only in the case that the master clock generated by the PLL has a frequency 10 times higher compared to the frequency of the applied SCL signal.
5.1.1 Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. An SDA transition while the clock is high is used to identify a START or STOP condition.
START is identified by a high-to-low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer.
STOP is identified by a low-to-high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communication between the STA382BWS and the bus master.
During the data input the STA382BWS samples the SDA signal on the rising edge of clock
SCL. For correct device operation, the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low.
40/172 with a start condition. Following this, the master sends to the SDA line 8 bits (MSB first) corresponding to the device select address and read or write mode.
The seven most significant bits are the device address identifiers, corresponding to the I
2
C bus definition. In the STA382BWS the I
2
C interface has two device addresses depending on the SA port configuration, 0x38 when SA = 0, and 0x3A when SA = 1.
The eighth bit (LSB) identifies read or write operation RW, this bit is set to 1 for read mode and to 0 for write mode. After a START condition the STA382BWS identifies on the bus the device address and if a match is found, it acknowledges the identification on SDA bus during
Doc ID 022784 Rev 1
STA382BWS I
2
C bus specification the 9th bit time. The byte following the device identification byte is the internal space address.
Following the START condition, the master sends a device select code with the RW bit set to 0. The STA382BWS acknowledges this and then waits for the byte of the internal address. After receiving the internal byte address the STA382BWS again responds with an acknowledgement.
In the byte write mode the master sends one data byte which is acknowledged by the
STA382BWS. The master then terminates the transfer by generating a STOP condition.
The multi-byte write mode can start from any internal address. The master generating a
STOP condition terminates the transfer.
5.4.1
5.4.2
Current address byte read
Following the START condition, the master sends a device select code with the RW bit set to 1. The STA382BWS acknowledges this and then responds by sending one byte of data.
The master then terminates the transfer by generating a STOP condition.
Current address multi-byte read
The multi-byte read modes can start from any internal address. Sequential data bytes are read from sequential addresses within the STA382BWS. The master acknowledges each data byte read and then generates a STOP condition, terminating the transfer.
Following the START condition, the master sends a device select code with the RW bit set to 0. The STA382BWS acknowledges this and then the master writes the internal address byte. After receiving the internal byte address, the STA382BWS again responds with an acknowledgement. The master then initiates another START condition and sends the device Obsolete Product(s) - Obsolete Product(s) responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.
5.4.4 Random address multi-byte read
The multi-byte read mode can start from any internal address. Sequential data bytes are read from sequential addresses within the STA382BWS. The master acknowledges each data byte read and then generates a STOP condition, terminating the transfer.
Doc ID 022784 Rev 1 41/172
I
2
C bus specification
Figure 14.
Write mode sequence
S UB-ADDR
S TART
S UB-ADDR
S TART
Figure 15.
Read mode sequence
ADDRE SS
S TART
ADDRE SS
S EQUENTIAL
S TART
S TART
S EQUENTIAL
S TART
S UB-ADDR
S TOP
S T A R T
S UB-ADDR
S T A R T
R W
R W
S TOP
S TOP
S TOP
STA382BWS
S TOP
S TOP
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42/172 Doc ID 022784 Rev 1
STA382BWS
6 Register description: New Map
Register description: New Map
Mapping of two registers is available on the STA382BWS, the selection is done by setting register 0x7E bit D7. By default, 0x7E is set to 1 and refers to a map that is not compatible with previous Sound Terminal devices. This register’s mapping is also called “New Map”.
To keep compatibility with previous Sound Terminal devices, 0x7E bit D7 must be set to 0 after device turn-on and after any reset (via SW or via external pin). Please refer to
Section 7: Register description: Sound Terminal compatibility for all the information about
device compatibility.
Missing addresses are to be considered as reserved.
Table 14.
Default register map table: NEW MAP
Addr Name D7 D6 D5 D4 D3 D2 D1 D0
0x08
0x09
0x0A
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x00
0x01
0x02
0x03
CLK
STATUS
RESET
SVOL
0x04 MVOL
0x05 FINEVOL
0x06
0x07
CH1VOL
CH2VOL
POST
OPER
FUNCT
HPCFG
CONFA
CONFB
CONFC
CONFD
CONFE
CONFF
FAULT
FDRB
C2IM
SME
CLK_CFG[3:0]
DRCCRC EQCRC
CRC
C1IM
ZDE
ZCE
PWDN
APEQ
DSCKE
CSZ3
BADPWM
MVOL[7:0]
CH1VOL[7:0]
CH2VOL[7:0]
POST[7:0]
PEQ
IR1
SAIFB
CSZ2
BQL
PWMS
LDTE
IR0
SAI3
CSZ1
PSL
AME
BCLE
AMDRC
MCS2
SAI2
CSZ0
DSPB
NSBW
IDE
I2SERR
I2S
PLLUL
SRESET
SVOL[1:0]
FINE[1:0]
OPER[1:0]
MDRCE DRC
MCS1
SAI1
MUTE
MCS0
SAI0
EAPD ECLE
0x17 MUTELOC
0x1B CH3VOL
LOC1 LOC0 C3M
CH3VOL[7:0]
C2M C1M MMUTE
Obsolete Product(s) - Obsolete Product(s)
0x1D AUTO XO3 XO2 XO1 XO0 AMAM2 AMAM1 AMAM0 AMAME
0x1F
0x20
0x21
0x22
0x23
0x24
C1CFG
C2CFG
C3CFG
TONE
L1AR
L1ATRT
C3OM1
TTC3
L1A3
L1AT3
C3OM0
TTC2
L1A2
L1AT2
C3LS1
TTC1
L1A1
L1AT1
C3LS0
TTC0
L1A0
L1AT0
C1BO
C2BO
C3BO
BTC3
L1R3
L1RT3
C1VBP
C2VBP
C3VBP
BTC2
L1R2
L1RT2
C1EQBP
C2EQBP
BTC1
L1R1
L1RT1
C1TCB
C2TCB
BTC0
L1R0
L1RT0
Doc ID 022784 Rev 1 43/172
Register description: New Map STA382BWS
Table 14.
Default register map table: NEW MAP (continued)
Addr Name D7 D6 D5 D4 D3 D2 D1 D0
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x3C
0x3D
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x3F
B2CF3
A1CF1
A1CF2
A1CF3
A2CF1
A2CF2
A2CF3
B0CF1
L2AR
L2ATRT
CFADDR
B1CF1
B1CF2
B1CF3
B2CF1
B2CF2
B0CF2
B0CF3
CFUD
FDRC1
FDRC2
MTH2
C2B1
C3B17
C3B9
C3B1
C4B17
C4B9
C4B1
C5B17
L2R1
L2RT1
CFA1
C1B17
C1B9
C1B1
C2B17
C2B9
C5B9
C5B1
WA
FDRC9
FDRC1
0x40
0x43
0x44
0x45
0x46
0x47
MTH1
EATH1
ERTH1
EATH2
ERTH2
CONFX
EATHEN1
ERTHEN1
EATHEN2
ERTHEN2
MTH[15:8]
EATH1[6:0]
ERTH1[6:0]
EATH2[6:0]
XAR1
ERTH2[6:0]
XAR2 PS48DB BQ5 BQ6 BQ7
0x52 PLLFRAC1
0x53 PLLFRAC2
PLL_FRAC[15:8]
Obsolete Product(s) - Obsolete Product(s)
0x54 PLLDIV PLL_DITH[1:0] PLL_NDIV[5:0]
0x55 PLLCFG0 PLL_DPD PLL_FCT PLL_STB
PLL_
STBBYP
PLL_IDIV[3:0]
PLLCFG1 0x56 PLL_DIRP PLL_PWD PLL_BYP OSC_PD BOOST32K
0x57 PLLSTATE
0x58
0x5A
SHOK
CXT41
L2A3
L2AT3
C3B7
C4B23
C4B15
C4B7
C5B23
C5B15
C5B7
C1B23
C1B15
C1B7
C2B23
C2B15
C2B7
C3B23
C3B15
FDRC15
FDRC7
L2A2
L2AT2
C3B6
C4B22
C4B14
C4B6
C5B22
C5B14
C5B6
C1B22
C1B14
C1B6
C2B22
C2B14
C2B6
C3B22
C3B14
FDRC14
FDRC6
CEXT_B4[1:0]
C2B5
C3B21
C3B13
C3B5
C4B21
C4B13
C4B5
C5B21
C5B13
C5B5
L2A1
L2AT1
CFA5
C1B21
C1B13
C1B5
C2B21
C2B13
FDRC13
FDRC5
C2B4
C3B20
C3B12
C3B4
C4B20
C4B12
C4B4
C5B20
C5B12
C5B4
L2A0
L2AT0
CFA4
C1B20
C1B12
C1B4
C2B20
C2B12
FDRC12
FDRC4
CEXT_B3[1:0]
C2B3
C3B19
C3B11
C3B3
C4B19
C4B11
C4B3
C5B19
L2R3
L2RT3
CFA3
C1B19
C1B11
C1B3
C2B19
C2B11
C5B11
C5B3
RA
FDRC11
FDRC3
MTH[21:16]
C2B2
C3B18
C3B10
C3B2
C4B18
C4B10
C4B2
C5B18
L2R2
L2RT2
CFA2
C1B18
C1B10
C1B2
C2B18
C2B10
C5B10
C5B2
R1
FDRC10
FDRC2
BYPSTATE PDSTATE
GNDSH
CEXT_B2[1:0]
OSCOK
C2B0
C3B16
C3B8
C3B0
C4B16
C4B8
C4B0
C5B16
L2R0
L2RT0
CFA0
C1B16
C1B8
C1B0
C2B16
C2B8
C5B8
C5B0
W1
FDRC8
FDRC0
LOWCK
VCCSH OUTSH
CEXT_B1[1:0]
44/172 Doc ID 022784 Rev 1
STA382BWS Register description: New Map
Table 14.
Default register map table: NEW MAP (continued)
Addr Name D7 D6 D5 D4 D3 D2 D1 D0
0x5B
0x5C
0x5D
0x5E
0x60
CXT75
MISC1
MISC2
BPTH
BPTIM
RPDNEN
LPDP
0x61
0x62
0x63
0x64
0x65
0x66
0x69
0x6A
ZCCFG0
ZCCFG1
ZCCFG2
ZCCFG3
WTHH
ZCCFG4
HPCFG HPLN
F3XCFG1 F3XLNK
F3XCFG2 F3X_FAULT
0x6B STCCFG0
LPD
WTHL
CEXT_B7[1:0]
BRIDGOFF
LPDE
BPTH[5:0]
FINETH
PNDLSL[2:0]
BPTIM[7:0]
HSEL[1:0]
RMS_CH0[7:0]
RMS_CH0[15:8]
RMS_CH1[7:0]
CEXT_B6[1:0]
CPWMEN
RMS_CH1[15:8]
CPFEN CPOK
CEXT_B5[1:0]
ZMTH[2:0]
ABFAULT
SHEN
DCROK
F3X_MUTE F3X_ENA F3X_SM_SLOPE[2:0]
NP_
CRCRES
0x6C STCCFG1
0x6F MTH0
0x70
0x71
CHPSINC
BQCHKE0
0x72 BQCHKE1
0x73 BQCHKE2
0x74
0x75
XCCHKE0
XCCHKE1
0x76
0x77
XCCHKE2
BQCHKR0
0x78 BQCHKR1
CHPI
MTH[7:0]
BQ_CKE[7:0]
INITCNT[3:0]
BQ_CKE[15:8]
BQ_CKE[23:16]
XC_CKE[7:0]
XC_CKE[15:8]
XC_CKE[23:16]
BQ_CKR[7:0]
BQ_CKR[15:8]
STC_LNK
CHPRD
0x79 BQCHKR2 BQ_CKR[23:16]
0x7A
0x7B
XCCHKR0
XCCHKR1
XC_CKR[7:0]
XC_CKR[15:8]
XCCHKR2 XC_CKR[23:16] 0x7C
BCAUTO 0x7D CHKCTRL XCAUTO
MISC4 0x7E SMAP WRA CH12
Doc ID 022784 Rev 1 45/172
Register description: New Map
6.1
STA382BWS
CLK register (addr 0x00)
D7
0
D6 D5
0
CLK_CFG[3:0]
0
D4
0
D3
Reserved
0
D2
Reserved
0
D1
Reserved
0
D0
I2S
0
Table 15.
CLK register
Bit R/W RST
7
6
5
4
R/W
R/W
R/W
R/W
0
0
0
0
Name
CLK_CFG[3:0]
0 R/W 0 I2S
Description
0000: 44.1/48 kHz BITCLK = 64 Fs
0001: 32 kHz BITCLK = 64 Fs
0010: 96 kHz BITCLK = 64 Fs
0011: 48/44.1/32 kHz MCK = 256 Fs others: clock configuration depends on IR/MCS bits
‘0’ = SAI configured in I
2
S mode
‘1’ = SAI configuration depends on CONFB register status
6.2 STATUS register (addr 0x01)
D7
FAULT
NA
D6
DRCCRC
NA
D5
EQCRC
NA
Table 16.
STATUS register
Bit R/W RST Name
D4
BADPWM
NA
D3
Reserved
NA
Description
D2
Reserved
NA
D1
I2SERR
NA
D0
PLLUL
NA
7
6
5
4
R
R
R
R
FAULT
(1)
DRCCRC
EQCRC
BADPWM
‘0’ = the power bridge is in fault condition
‘1’ = the power bridge is in normal condition
‘0’ = normal operation
‘1’ = CRC error on DRC BIQUADS
‘0’ = normal operation
‘1’ = CRC error on BIQUADS
‘0’ = normal operation
‘1’ = PWM outputs are invalid
‘0’ = normal operation
1 R I2SERR ‘1’ = SAI interface error detected (see
Section 6.14: Obsolete Product(s) - Obsolete Product(s)
‘0’ = PLL is locked
0 R PLLUL
‘1’ = PLL is not locked
1.
Fault status is set to 1 once the power bridge goes to tri-state mode.
46/172 Doc ID 022784 Rev 1
STA382BWS
6.3
Register description: New Map
RESET register (addr 0x02)
D7
Reserved
0
D6
Reserved
0
D5
Reserved
0
D4
Reserved
0
D3
Reserved
0
D2
Reserved
0
D1
Reserved
0
D0
SRESET
0
Table 17.
RESET register
Bit R/W RST Name
0 R/W 0 SRESET
‘0’: normal operation
‘1’: reset the device
Description
After SRESET is written, the last IC acknowledge is skipped and the EAPD bit (reg 0x16 bit
D7) is set to 1 instead of the 0 default value obtained after hardware reset.
6.4 Soft volume register (addr 0x03)
D7
Reserved
0
D6
Reserved
0
D5
Reserved
0
D4
Reserved
0
D3
Reserved
0
D2
Reserved
0
Table 18.
Soft volume register
Bit R/W RST Name
1 R/W
SVOL[1:0]
0 R/W
Description
00: 30 ms
01: 100 ms (default)
10: 100 ms
11: Soft-mute disabled
Values are specified for fs = 48 kHz, 96 kHz or 192 kHz.
D1
SVOL[1:0]
D0
0 1
Obsolete Product(s) - Obsolete Product(s)
Doc ID 022784 Rev 1 47/172
Register description: New Map
6.5 MVOL register (addr 0x04)
6.6
STA382BWS
D7
0
D6
0
D5
0
D4
MVOL[7:0]
D3
0 0
D2
0
D1
0
Table 19.
Master volume register
Bit R/W RST Name Description
2
1
4
3
0
7
6
5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
MVOL[7:0]
0x00: Hard mute (immediate switchoff)
0x01: Mute
0x02: Mute (PWM on)
0x03: Mute (PWM on) others: volume = [(MVOL-255)/2] dB
(1)
1.
If the volume is below -60 dB, the level will be approximated to 1 dB step.
D0
0
FINEVOL register (addr 0x05)
D7
Reserved
0
D6
Reserved
0
D5
Reserved
0
D4
Reserved
0
D3
Reserved
0
D2
Reserved
0
D1
FINE[1:0]
D0
0 0
Table 20.
Fine volume register
Bit R/W RST Name Description
1 R/W 00 = 0 dB
01 = -0.125 dB
FINE[1:0]
10 = -0.25 dB
0 R/W
11 = -0.375 dB
Obsolete Product(s) - Obsolete Product(s)
48/172 Doc ID 022784 Rev 1
STA382BWS
6.7 CH1VOL register (addr 0x06)
6.8
Register description: New Map
D7
1
D6
0
D5
0
D4
CH1VOL[7:0]
D3
1 1
D2
1
D1
1
Table 21.
Channel 1 volume register
Bit R/W RST Name Description
1
0
3
2
5
4
7
6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
0
1
1
1
1
1
CH1VOL[7:0]
0x00: mute others: volume = [(CH1VOL-159)/2] dB
1.
If the volume is below -60 dB, the level will be approximated to 1 dB step.
(1)
D0
1
CH2VOL register (addr 0x07)
D7
1
D6
0
D5
0
D4
CH2VOL[7:0]
D3
1 1
D2
1
D1
1
D0
1
Table 22.
Channel 2 volume register
Bit R/W RST Name Description
7
6
R/W
R/W
1
0
5 R/W 0
4 R/W 1
Obsolete Product(s) - Obsolete Product(s)
2
R/W
R/W
1
1
CH2VOL[7:0]
0x00: mute others: volume = [(CH2VOL-159)/2] dB
(1)
1 R/W 1
0 R/W 1
1.
If the volume is below -60 dB, the level will be approximated to 1 dB step.
Doc ID 022784 Rev 1 49/172
Register description: New Map
6.9 POST scaler register (addr 0x08)
D7 D6 D5 D4 D3
POST[7:0]
1 0 0 0 0
Post scaler is set to POST/128 for both CH1 and CH2.
D2
0
D1
0
STA382BWS
D0
0
6.10 OPER register (addr 0x09)
D7
Reserved
0
D6
Reserved
0
D5
Reserved
0
Table 23.
OPER register
Bit R/W RST
1
0
R/W
R/W
0
0
D4
Reserved
0
Name
OPER[1:0]
D3
Reserved
0
Description
D2
Reserved
0 output configuration modes
D1
OPER[1:0]
D0
0 0
Table 24.
OPER configuration selection
OPER[1:0] Output configuration PBTL enable
00
11
2-channel (full-bridge) power, 2-channel data-out:
1A/1B → 1A/1B
2A/2B
→
2A/2B
LineOut1 → 3A/3B
LineOut2 → 4A/4B
Line out configuration determined by LOC register
2-channel (full-bridge) power, 1-channel FFX:
1A/1B → 1A/1B
2A/2B → 2A/2B
3A/3B → 3A/3B
EAPDEXT and TWARNEXT Active
No
Yes
2(half-bridge).1(full-bridge) on-board power:
1A
→
1A Binary 0°
10
2A → 1B Binary 90° Obsolete Product(s) - Obsolete Product(s)
1A/B → 3A/B Binary 0°
No
2A/B → 4A/B Binary 90°
01
1 channel mono-parallel:
3A → 1A/1B w/ C3BO 45°
3B → 2A/2B w/ C3BO 45°
1A/1B
→
3A/3B
2A/2B → 4A/4B
CH3 downmixed on all the PWM channels.
No
50/172 Doc ID 022784 Rev 1
STA382BWS
Figure 16.
OPER = 00 (default value)
H a lf
H a lf
H a lf
H a lf
Register description: New Map
Ch a nnel 1
OUT 3 A
OUT 3 B
Ch a nnel 2
LineO u t1
LineO u t2
Figure 17.
OPER = 11
H a lf
H a lf
H a lf
H a lf
Ch a nnel 1
Ch a nnel 2
Ch a nnel 3
Figure 18.
OPER = 10
H a lf
H a lf
H a lf
H a lf
OUT 3 A
Ch a nnel 1
Ch a nnel 2
Doc ID 022784 Rev 1 51/172
Register description: New Map
Figure 19.
OPER = 01
STA382BWS
H a lf
H a lf
H a lf
H a lf
Ch a nnel 3
OUT 3 A
OUT 3 B
Ch a nnel 1
Ch a nnel 2
The STA382BWS can be configured to support different output configurations. For each
PWM output channel, a PWM slot is defined. A PWM slot is always 1 / (8 * fs) seconds length. The PWM slot defines the maximum extension for the PWM rising and falling edge, that is, the rising edge as well as the falling edge cannot range outside the PWM slot boundaries.
Figure 20.
Output mapping scheme
52/172
TM mod u l a tor
FFX 3 A
FFX 3 B
FFX 4B
OUT 3 A
OUT4A
OUT4B
Doc ID 022784 Rev 1
STA382BWS Register description: New Map
For each configuration the PWM signals from the digital driver are mapped in different ways to the power stage.
2.0 channels, two full-bridges (
OPER
= 00)
●
●
●
●
●
●
●
●
●
●
●
●
FFX1A -> OUT1A
FFX1B -> OUT1B
FFX2A -> OUT2A
FFX2B -> OUT2B
FFX3A -> OUT3A
FFX3B -> OUT3B
FFX4A -> OUT4A
FFX4B -> OUT4B
FFX1A/1B configured as ternary
FFX2A/2B configured as ternary
FFX3A/3B configured as line out ternary
FFX4A/4B configured as line out ternary
On channel 3 line out (LOC bits = 00, reg 0x17 bit D7,D6) the same data as channel 1 processing is sent. On channel 4 line out (LOC bits = 00) the same data as channel 2 processing is sent. In this configuration, neither volume control nor EQ has any effect on channels 3 and 4.
In this configuration the PWM slot phase is the following as shown in Figure 21 .
Figure 21.
2.0 channels (OPER = 00) PWM slots
OUT 3 A
OUT 3 B
Obsolete Product(s) - Obsolete Product(s)
Doc ID 022784 Rev 1 53/172
Register description: New Map STA382BWS
2.1 channels, two half-bridges + one full-bridge (
OPER
= 11)
●
●
●
●
●
●
●
●
●
●
●
●
FFX1A -> OUT1A
FFX2A -> OUT1B
FFX3A -> OUT2A
FFX3B -> OUT2B
FFX1A -> OUT3A
FFX1B -> OUT3B
FFX2A -> OUT4A
FFX2B -> OUT4B
FFX1A/1B configured as binary
FFX2A/2B configured as binary
FFX3A/3B configured as binary
FFX4A/4B is not used
In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT3/OUT4 channels, channel 1 and channel 2 PWM are replicated.
In this configuration the PWM slot phase is the following as shown in Figure 22 .
Figure 22.
2.1 channels (OPER = 11) PWM slots
OUT 3 A
OUT 3 B
OUT4A
OUT4B
Obsolete Product(s) - Obsolete Product(s)
54/172 Doc ID 022784 Rev 1
STA382BWS Register description: New Map
2.1 channels, two full-bridges + one external full-bridge (
OPER
= 10)
●
●
●
●
●
●
●
●
●
●
●
●
FFX1A -> OUT1A
FFX1B -> OUT1B
FFX2A -> OUT2A
FFX2B -> OUT2B
FFX3A -> OUT3A
FFX3B -> OUT3B
EAPD -> OUT4A
TWARN -> OUT4B
FFX1A/1B configured as ternary
FFX2A/2B configured as ternary
FFX3A/3B configured as ternary
FFX4A/4B is not used
In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT4 channel the external bridge control signals are muxed.
In this configuration the PWM slot phase is the following as shown in Figure 23 .
Figure 23.
2.1 channels (OPER = 10) PWM slots
OUT 3 A
OUT 3 B
Obsolete Product(s) - Obsolete Product(s)
Doc ID 022784 Rev 1 55/172
Register description: New Map STA382BWS
6.11 FUNCT register (addr 0x0A)
D7
Reserved
0
D6
CRC
0
D5
APEQ
1
Table 25.
FUNCT register
Bit R/W RST Name
D4
PEQ
0
6
5
4
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
0
1
0
0
0
0
CRC
APEQ
PEQ
AMDRC
MDRCE
DRC
D3
Reserved
0
D2
AMDRC
0
D1
MDRCE
0
D0
DRC
0
Description
‘0’: disable CRC computation and comparison
‘1’: enable CRC computation and comparison
‘0’: extended BQ disabled, 8th biquadratic filter disabled
‘1’: extended BQ enabled, 8th biquadratic filter enabled
‘0’: Normal operation
‘1’: PEQ disabled, disables all biquadratic filters
‘0’: STCompressor bypassed
‘1’: STCompressor enabled
‘0’: MDRCE bypassed
‘1’: MDRCE enabled
‘0’: DRC disabled
‘1’: DRC enabled
The STA382BWS device provides a dual-band DRC (B
2
DRC) on the left and right channels data path, as depicted in
Figure 24 . Dual-band DRC is activated by setting MDRCE = 1.
Figure 24.
B
2
DRC scheme
Ch a nnel 3
Vol u me
DRC 2
L
B 2 DRC
Hi-p ass XO filter
-
+
Ch a nnel 1
Vol u me
DRC 1 +
Obsolete Product(s) - Obsolete Product(s)
R
B 2 DRC
Hi-p ass XO filter
- +
Ch a nnel 2
Vol u me
DRC 1
56/172
Ch a nnel 3
Vol u me
DRC 2 +
The low-frequency information (LFE) is extracted from the left and right channels, removing the high frequencies using a programmable biquad filter, and then computing the difference
Doc ID 022784 Rev 1
STA382BWS Register description: New Map with the original signal. Limiter 1 (DRC1) is then used to control the amplitude of the left/right high-frequency components, while limiter 2 (DRC2) is used to control the low-
).
The cutoff frequency of the high-pass filters can be user-defined, XO[3:0] = 0, or selected from the pre-defined values.
DRC1 and DRC2 are then used to independently limit L/R high frequencies and LFE
channel amplitude (see Section 6.23: Dynamic control registers (addr 0x23 - 0x26 / addr
) as well as their volume control. To be noted that, in this configuration, the dedicated channel 3 volume control can actually act as a bass boost enhancer as well (0.5 dB/step resolution).
The processed LFE channel is then recombined with the L and R channels in order to reconstruct the 2.0 output signal.
Sub-band decomposition
The sub-band decomposition for B
2
DRC can be configured specifying the cutoff frequency.
The cutoff frequency can be programmed in two ways, using the XO bits in register 0x0C, or using the “user programmable” mode (coefficients stored in RAM addresses 0x28 to 0x31).
For the user-programmable mode, use the formulas below to compute the high-pass filters: b0 = (1 + alpha) / 2 b1 = -(1 + alpha) / 2 a0 = 1 a1 = -alpha b2 = 0 a2 = 0 where alpha = (1-sin( ω
0
))/cos( ω
0
), and ω
0
is the cutoff frequency.
A first-order filter is recommended to guarantee that for every ω
0
the corresponding
low-pass filter obtained as difference (as shown in Figure 24
) will have a symmetric (relative to the HP filter) frequency response, and the corresponding recombination after the DRC has low ripple. Second-order filters can be used as well, but in this case the filter shape must be carefully chosen to provide good low-pass response and minimum ripple recombination. For second-order filters, it is not possible to give a closed formula to get the best coefficients, but empirical adjustment should be done.
DRC settings
The DRC blocks used by B
2
DRC are the same as those described in
Section 6.23: Dynamic control registers (addr 0x23 - 0x26 / addr 0x43 - 0x46)
. B
2
DRC configure automatically the
DRC blocks in anticlipping mode. Attack and release thresholds can be selected using
Obsolete Product(s) - Obsolete Product(s)
0x12 and 0x14.
Band downmixing
The low-frequency band is down-mixed to the left and right channels at the B
2
DRC output.
Channel volume can be used to weight the bands recombination to fine-tune the overall frequency response.
Doc ID 022784 Rev 1 57/172
Register description: New Map
6.12 HPCFG register (addr 0x10)
STA382BWS
D7
Reserved
0
D6
Reserved
0
D5
Reserved
0
D4
Reserved
0
D3
Reserved
0
D2
Reserved
0
D1
Reserved
0
D0
MUTE
1
Table 26.
HPCFG register
Bit R/W RST
0 R/W 1
Name
MUTE
Description
‘0’: HP/Line out is ON
‘1’: HP/LIne out is muted
6.13 Configuration register A (addr 0x11)
D7
FDRB
0
D6
Reserved
1
D5
Reserved
1
D4
IR1
0
D3
IR0
0
D2
MCS2
1
D1
MCS1
1
D0
MCS0
1
Table 27.
Master clock select
Bit R/W RST Name
0
1
2
R/W
R/W
R/W
1
1
1
MCS0
MCS1
MCS2
Description
Selects the ratio between the input I
2
S sampling frequency and the input clock.
●
●
●
The STA382BWS supports sampling rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,
176.4 kHz, and 192 kHz. Therefore the internal clock is:
32.768 MHz for 32 kHz
45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz
49.152 MHz for 48 kHz, 96 kHz, and 192 kHz
The external clock frequency provided to the XTI pin or BICKI pin (depending on the MCS settings) must be a multiple of the input sampling frequency (f s
). determined by both the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internally. In
Table 28 MCS 111 and 110 indicate that BICKI has to be used as the
clock source, while XTI is used in all the other cases.
58/172 Doc ID 022784 Rev 1
STA382BWS Register description: New Map
Table 28.
Input sampling rates
Input sampling rate fs (kHz)
IR
32, 44.1, 48
88.2, 96
176.4, 192
MCS[2:0]
111 110 101 100 011 010 001 000
00 64*fs(*) NA
01 64*fs(*) 32*fs(*)
1X 64*fs(*) 32*fs(*)
576 * fs 128 * fs 256 * fs 384 * fs 512 * fs 768 * fs
NA
NA
64 * fs
32 * fs
128 * fs 192 * fs 256 * fs 384 * fs
64 * fs 96 * fs 128 * fs 192 * fs
Note: (*): Clock is BICKI
6.13.2 Interpolation ratio selection
Table 29.
Internal interpolation ratio
Bit R/W RST Name
4:3 R/W 00 IR [1:0]
Description
Selects internal interpolation ratio based on input I
2
S sampling frequency
The STA382BWS has variable interpolation (oversampling) settings such that internal processing and FFX output rates remain consistent. The first processing block interpolates by either 3 times (
Table 84.: PLL register 0x56 bits
D0), 2 times or 1 time (pass-through) or provides a 2-times downsample. The oversampling ratio of this interpolation is determined by the IR bits.
Table 30.
IR bit settings as a function of the input sampling rate
Input sampling rate fs (kHz) IR 1st stage interpolation ratio
32
44.1
48
88.2
96
00
00
00
01
01
2-times oversampling
2-times oversampling
2-times oversampling
Pass-through
Pass-through
176.4
10 2-times downsampling
192 10 2-times downsampling Obsolete Product(s) - Obsolete Product(s)
6.13.3 Fault-detect recovery bypass
Table 31.
Fault-detect recovery bypass
Bit R/W RST Name
7 R/W 0 FDRB
Description
0: fault-detect recovery enabled
1: fault-detect recovery disabled
Doc ID 022784 Rev 1 59/172
Register description: New Map STA382BWS
The on-chip STA382BWS power output block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition
(either overcurrent or thermal). When FAULT is asserted (set to 0), the power control block attempts a recovery from the fault by asserting the tri-state output (setting it to 0 which directs the power output block to begin recovery), holds it at 0 for period of time in the range of 0.1 ms to 1 second as defined by the fault-detect recovery constant register (FDRC registers 0x3C-0x3D), then toggles it back to 1. This sequence is repeated as long as the fault indication exists. This feature is enabled by default but can be bypassed by setting the
FDRB control bit to 1.
6.14 Configuration register B (addr 0x12)
D7
C2IM
1
D6
C1IM
0
D5
DSCKE
0
D4
SAIFB
0
D3
SAI3
0
D2
SAI2
0
D1
SAI1
0
D0
SAI0
0
The STA382BWS audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. The STA382BWS always acts as the slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and serial data 1 and 2 SDI12.
The SAI bits (D3 to D0) and the SAIFB bit (D4) are used to specify the serial data format.
The default serial data format is I
2
S, MSB-first. Available formats are shown in the tables that follow.
Obsolete Product(s) - Obsolete Product(s)
60/172 Doc ID 022784 Rev 1
STA382BWS
6.14.2 Serial data first bit
Table 32.
Serial data first bit
SAIFB
0
1
MSB-first
LSB-first
Register description: New Map
Format
Table 33.
Support serial audio input formats for MSB-first (SAIFB = 0)
BICKI SAI [3:0] SAIFB Interface format
0000 0 I
2
S 15-bit data
32 * fs
0001
0000
0
0
Left/right-justified 16-bit data
I
2
S 16- to 23-bit data
48 * fs
64 * fs
0001
0010
0110
1010
1110
0000
0001
0010
0110
1010
1110
0
0
0
0
0
0
0
0
0
0
0
Left-justified 16- to 24-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
I
2
S 16- to 24-bit data
Left-justified 16- to 24-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
Obsolete Product(s) - Obsolete Product(s)
Doc ID 022784 Rev 1 61/172
Register description: New Map STA382BWS
Table 34.
Supported serial audio input formats for LSB-first (SAIFB = 1)
BICKI SAI [3:0] SAIFB Interface format
32 * fs
48 * fs
64 * fs
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1001
1101
0010
0110
1010
1110
0000
0100
1000
1100
0001
0101
1001
1101
0010
0110
1010
1110
1100
1110
0100
0100
1000
1100
0001
0101
I
2
S 15-bit data
Left/right-justified 16-bit data
I
2
S 23-bit data
I
2
S 20-bit data
I
2
S 18-bit data
LSB first I
2
S 16-bit data
Left-justified 24-bit data
Left-justified 20-bit data
Left-justified 18-bit data
Left-justified 16-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
I
2
S 24-bit data
I
2
S 20-bit data
I
2
S 18-bit data
LSB first I
2
S 16-bit data
Left-justified 24-bit data
Left-justified 20-bit data
Left-justified 18-bit data
Left-justified 16-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data synchronous to the PLL output clock. It means that:
● the frequency of PLL clock / frequency of LRCKI = N ±4 cycles, where N depends on the settings in
● the PLL must be locked.
If these two conditions are not met, and the IDE bit (reg 0x05 bit 2) is set to 1, the
STA382BWS will immediately mute the I
2
S PCM data out (provided to the processing block) and it will freeze any active processing task.
62/172 Doc ID 022784 Rev 1
STA382BWS Register description: New Map
Note:
To avoid any audio side effects (like pop noise), it is strongly recommended to soft mute any audio streams flowing into the STA382BWS data path before the desynchronization event happens. At the same time any processing related to the I
2
C configuration should be issued only after the serial audio interface and the internal PLL are synchronous again.
Any mute or volume change causes some delay in the completion of the I
2
C operation due to the soft volume feature. The soft volume phase change must be finished before any clock desynchronization.
6.14.3 Delay serial clock enable
Table 35.
Delay serial clock enable
Bit R/W RST Name
5 R/W 0 DSCKE
Description
0: No serial clock delay
1: Serial clock delay by 1 core clock cycle to tolerate anomalies in some I
2
S master devices
6.14.4 Channel input mapping
Table 36.
Channel input mapping
Bit R/W RST Name
6
7
R/W
R/W
0
1
C1IM
C2IM
Description
0: Processing channel 1 receives left I
2
S input
1: Processing channel 1 receives right I
2
S input
0: Processing channel 2 receives left I
2
S input
1: Processing channel 2 receives right I
2
S input
Each channel received via I
2
S can be mapped to any internal processing channel via the channel input mapping registers. This allows for flexibility in processing. The default settings of these registers map each I
2
S input channel to its corresponding processing channel.
6.15 Configuration register C (addr 0x13)
D7
Reserved
1
D6
Reserved
0
D5
CSZ3
0
D4
CSZ2
1
D3
CSZ1
0
D2
CSZ0
1
D1
Reserved
1
D0
Reserved
1
Table 37.
FFX compensating pulse size bits
Bit R/W RST Name
2
3
4
5
R/W
R/W
R/W
R/W
1
1
1
0
CSZ0
CSZ1
CSZ2
CSZ3
Description
When OM[1,0] = 11, this register determines the size of the FFX compensating pulse from 0 clock ticks to 15 clock periods.
Doc ID 022784 Rev 1 63/172
Register description: New Map
Table 6:
Table 38.
Compensating pulse size
CSZ[3:0]
0000
0001
…
1111
Compensating pulse size
0 ns (0 ticks) compensating pulse size
20 ns (1 tick) clock period compensating pulse size
…
300 ns (15 ticks) clock period compensating pulse size
STA382BWS
6.16 Configuration register D (addr 0x14)
D7
SME
0
D6
ZDE
0
D5
Reserved
0
D4
BQL
1
D3
PSL
1
D2
DSPB
0
D1
Reserved
0
D0
Reserved
0
Table 39.
DSP bypass
Bit R/W RST
2 R/W 0
Name
DSPB
Description
0: Normal operation
1: Bypass of biquad and bass/treble functions
Setting the DSPB bit bypasses the EQ function of the STA382BWS.
Table 40.
Post-scale link
Bit R/W RST Name
3 R/W 1 PSL
Description
0: Each channel uses individual post-scale values
1: Each channel uses channel 1 post-scale values
Post-scale functionality can be used for power-supply error correction. For multi-channel applications running off the same power supply, the post-scale values can be linked to the value of channel 1 for ease of use and in order to update the values faster.
6.16.3 Biquad coefficient link Obsolete Product(s) - Obsolete Product(s)
Table 41.
Biquad coefficient link
Bit R/W RST Name Description
4 R/W 1 BQL
0: Each channel uses coefficient values
1: Each channel uses channel 1 coefficient values
For ease of use, all channels can use the biquad coefficients loaded into the channel 1 coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to be performed once.
64/172 Doc ID 022784 Rev 1
STA382BWS Register description: New Map
6.16.4 Zero-detect mute enable
Table 42.
Zero-detect mute enable
Bit R/W RST Name
6 R/W 0 ZDE
Description
Setting of 1 enables the automatic zero-detect mute
Setting of 0 disables the automatic zero-detect mute
Refer to
6.32: Enhanced zero-detect mute and input level measurement (address 0x61-
.
Table 43.
Submix mode enable
Bit R/W RST Name
7 R/W 0 SME
Description
0: Submix into left/right disabled
1: Submix into left/right enabled
6.17 Configuration register E (addr 0x15)
D7
Reserved
1
D6
ZCE
0
D5
Reserved
0
D4
PWMS
0
D3
AME
0
D2
NSBW
0
6.17.1 Noise-shaper bandwidth selection
Table 44.
Noise-shaper bandwidth selection
Bit R/W RST Name
2 R/W 0 NSBW
1: Third order NS
0: Fourth order NS
Description
D1
Reserved
1
D0
Reserved
0
Table 45.
AM mode enable
Bit R/W RST Name Description Obsolete Product(s) - Obsolete Product(s)
3 R/W 0 AME
0: Normal FFX operation
1: AM reduction mode FFX operation
The STA382BWS features an FFX processing mode that minimizes the amount of noise generated in the frequency range of AM radio. This mode is intended for use when FFX is operating in a device with an active AM tuner. The SNR of the FFX processing is reduced to approximately 83 dB in this mode, which is still greater than the SNR of AM radio.
Doc ID 022784 Rev 1 65/172
Register description: New Map STA382BWS
Table 46.
PWM speed mode
Bit R/W RST Name
4 R/W 0 PWMS
Description
0: Normal speed (384 kHz) all channels
1: Odd speed (341.3 kHz) all channels. Not suitable for binary BTL mode.
Table 47.
Zero-crossing enable
Bit R/W RST Name
6 R/W 0 ZCE
Description
‘1’: Volume adjustment only occurs at digital zero-crossing
‘0’: Volume adjustment occur immediately
The ZCE bit enables zero-crossing adjustment. When volume is adjusted on digital zerocrossing, no clicks are audible
6.18 Configuration register F (addr 0x16)
D7
EAPD
0
D6
PWDN
1
D5
ECLE
0
D4
LDTE
1
D3
BCLE
1
D2
IDE
1
D1
Reserved
D0
Reserved
Table 48.
Invalid input detect mute enable
Bit R/W RST Name
2 R/W 1 IDE
Description
Setting of 1 enables the automatic invalid input detect mute
Setting the IDE bit enables this function, which looks at the input I
2
S data and automatically mutes if the signals are perceived as invalid.
Table 49.
Binary output mode clock loss detection
Bit R/W RST Name
3 R/W 1 BCLE
Description
Binary output mode clock loss detection enable
This bit detects loss of input MCLK in binary mode and will output 50% duty cycle.
66/172 Doc ID 022784 Rev 1
STA382BWS Register description: New Map
6.18.3 LRCK double trigger protection
Table 50.
LRCK double trigger protection
Bit R/W RST Name
4 R/W 1 LDTE
Description
LRCLK double trigger protection enable
This bit actively prevents double triggering of LRCLK.
6.18.4 Auto EAPD on clock loss
Table 51.
Auto EAPD on clock loss
Bit R/W RST Name
5 R/W 0 ECLE
Description
Auto EAPD on clock loss
When active, this bit issues a power device power-down signal (EAPD) on clock loss detection.
6.18.5 Power-down
Table 52.
IC power-down
Bit R/W RST Name
7 R/W 1 PWDN
Description
0: IC power-down low-power condition
1: IC normal operation
The PWDN register is used to place the IC in a low-power state. When PWDN is written as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted to power down the power stage, then the master clock to all internal hardware except the I
2
C block is gated. This places the IC in a very low power consumption state.The register state is preserved once the device recovers from power-down.
Table 53.
External amplifier power-down
Bit R/W RST Name
R/W 0 EAPD
Description
0: External power stage power-down active
1: Normal operation
The EAPD register directly disables/enables the internal power circuitry.
When EAPD = 0, the internal power section is placed in a low-power state (disabled). This register also controls the EAPD/FFX4B output pin when OCFG = 11.
Doc ID 022784 Rev 1 67/172
Register description: New Map
6.19 Volume control registers (addr 0x17 - 0x1B)
6.19.1 Mute/line output configuration register (addr 0x17)
D7
LOC1
0
D6
LOC0
0
D5
Reserved
0
D4
Reserved
0
D3
C3M
0
D2
C2M
0
Table 54.
Line output configuration
LOC[1:0] Line output configuration
00
01
10
11
Line output fixed - no volume, no EQ
Line output variable - CH3 volume effects line output, no EQ
Line output variable with EQ - CH3 volume effects line output
Reserved
D1
C1M
0
STA382BWS
D0
MMUTE
0
Line output is only active when OCFG = 00. In this case LOC determines the line output configuration. The source of the line output is always the channel 1 and 2 inputs.
Table 55.
Mute configuration
Bit R/W RST Name Description
3
2
1
R/W
R/W
R/W
0
0
0
C3M
C2M
C1M
Channel 3 mute
0 - No mute condition. It is possible to set the channel volume
1 - Channel 3 in hardware mute
Channel 2 mute
0 - No mute condition. It is possible to set the channel volume
1 - Channel 2 in hardware mute
Channel 1 mute
0 - No mute condition. It is possible to set the channel volume
1 - Channel 1 in hardware mute
Master mute
0 - Normal operation 0 R/W 0 MMUTE
1 - All channels are in mute condition
Obsolete Product(s) - Obsolete Product(s)
68/172 Doc ID 022784 Rev 1
STA382BWS Register description: New Map
6.19.2 Channel 3 / line output volume (addr 0x1B)
D7 D6 D5 D4 D3 D2 D1 D0
CH3VOL
0 1 1 0 0 0 0 0
The volume structure of the STA382BWS consists of individual volume registers for each channel and a master volume register that provides an offset to each channel’s volume setting. The individual channel volumes are adjustable in 0.5 dB steps from +48 dB to
-80 dB.
As an example, if CH3VOL = 0x00 or +48 dB and MVOL= -12 dB, then the total gain for channel 3 = +36 dB.
The master mute, when set to 1, mutes all channels at once, whereas the individual channel mute (CxM) mutes only that channel. Both the master mute and the channel mutes provide a “soft mute” with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (approximately 96 kHz).
A “hard (instantaneous) mute” can be obtained by programming a value of 0xFF (255) to any channel volume register or the master volume register. When volume offsets are provided via the master volume register, any channel whose total volume is less than -80 dB is muted.
All changes in volume take place at zero-crossings when ZCE = 1 ( Section 6.17:
Configuration register E (addr 0x15)
) on a per-channel basis as this creates the smoothest possible volume transitions. When ZCE = 0, volume updates occur immediately.
Table 56.
Channel 3 volume as a function of CH3VOL[7:0]
CH3VOL[7:0] Volume
00000000 (0x00)
00000001 (0x01)
00000010 (0x02)
…
01011111 (0x5F)
01100000 (0x60)
01100001 (0x61)
…
+48 dB
+47.5 dB
+47 dB
…
+0.5 dB
0 dB
-0.5 dB
…
11010111 (0xD7) -59.5 dB
11011000 (0xD8) -60 dB Obsolete Product(s) - Obsolete Product(s)
11011001 (0xD9) -61 dB
11011010 (0xDA) -62 dB
…
11101100 (0xEC)
11101101 (0xED)
…
11111111 (0xFF)
…
-80 dB
Hard channel mute
…
Hard channel mute
Doc ID 022784 Rev 1 69/172
Register description: New Map
6.20 Audio preset registers (0x1D)
D7
XO3
0
D6
XO2
0
D5
XO1
0
D4
XO0
0
D3
AMAM2
0
STA382BWS
D2
AMAM1
0
D1
AMAM0
0
D0
AMAME
0
Table 57.
AM interference frequency switching bits
Bit R/W RST Name
0 R/W 0 AMAME
Description
Audio preset AM enable
0: switching frequency determined by PWMS setting
1: switching frequency determined by AMAM settings
Table 58.
Audio preset AM switching frequency selection
AMAM[2:0] 48 kHz/96 kHz input fs 44.1 kHz/88.2 kHz input fs
000
001
010
011
100
101
110
0.535 MHz - 0.720 MHz
0.721 MHz - 0.900 MHz
0.901 MHz - 1.100 MHz
1.101 MHz - 1.300 MHz
1.301 MHz - 1.480 MHz
1.481 MHz - 1.600 MHz
1.601 MHz - 1.700 MHz
0.535 MHz - 0.670 MHz
0.671 MHz - 0.800 MHz
0.801 MHz - 1.000 MHz
1.001 MHz - 1.180 MHz
1.181 MHz - 1.340 MHz
1.341 MHz - 1.500 MHz
1.501 MHz - 1.700 MHz
Table 59.
Bass management crossover
Bit R/W RST Name Description
4 R/W 0 XO0
Selects the bass management crossover frequency.
5 R/W 0 XO1
A 1 st
-order high-pass filter (channels 1 and 2) or a
2 nd
-order low-pass filter (channel 3) at the selected
6 R/W 0 XO2 frequency is performed.
7 R/W 0 XO3 Obsolete Product(s) - Obsolete Product(s)
70/172 Doc ID 022784 Rev 1
STA382BWS Register description: New Map
1001
1010
1011
1100
1101
1110
1111
0001
0010
0011
0100
0101
0110
0111
1000
Table 60.
Bass management crossover frequency
XO[3:0] Crossover frequency
0000
200 Hz
220 Hz
240 Hz
260 Hz
280 Hz
300 Hz
320 Hz
340 Hz
360 Hz
Table 74.: RAM block for biquads, mixing, scaling and bass management
80 Hz
100 Hz
120 Hz
140 Hz
160 Hz
180 Hz
D7
Reserved
0
D7
Reserved
0
D7
C3OM1
1
D6
Reserved
0
D6
Reserved
1
D6
C3OM0
0
D5
Reserved
0
D5
Reserved
0
D5
C3LS1
0
D4
Reserved
0
D4
Reserved
0
D4
C3LS0
0
D3
C1BO
0
D3
C2BO
0
D3
C3BO
0
D2
C1VPB
0
D2
C2VPB
0
D2
C3VPB
0
D1
C1EQBP
0
D1
C2EQBP
0
D1
Reserved
0
D0
C1TCB
0
D0
C2TCB
0
D0
Reserved
0
Tone control (bass/treble) can be bypassed on a per-channel basis for channels 1 and 2.
Table 61.
Tone control bypass
CxTCB
0
1
Mode
Perform tone control on channel x - normal operation
Bypass tone control on channel x
Doc ID 022784 Rev 1 71/172
Register description: New Map STA382BWS
EQ control can be bypassed on a per-channel basis for channels 1 and 2. If EQ control is bypassed on a given channel, the prescale and all filters (biquads, bass, treble in any combination) are bypassed for that channel.
Table 62.
EQ bypass
CxEQBP
0
1
Mode
Perform EQ on channel x - normal operation
Bypass EQ on channel x
Each channel contains an individual channel volume bypass. If a particular channel has volume bypassed via the CxVBP = 1 register, then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel.
Table 63.
Volume bypass register
CxVBP
0
1
Normal volume operations
Volume is bypassed
Mode
6.21.4 Binary output enable registers
Each individual channel output can be set to output a binary PWM stream. In this mode output A of a channel is considered the positive output and output B is the negative inverse.
Table 64.
Binary output enable registers
CxBO
0
1
Mode
FFX 3-state output - normal operation
Binary output
Limiter selection can be made on a per-channel basis according to the channel limiter select
Obsolete Product(s) - Obsolete Product(s)
), EQ DRC ( Section 6.26.1: Extended post-scale range ) usage.
Table 65.
Channel limiter mapping as a function of C3LS bits
C3LS[1:0] Channel limiter mapping
00
01
10
Channel has limiting disabled
Channel is mapped to limiter #1
Channel is mapped to limiter #2
72/172 Doc ID 022784 Rev 1
STA382BWS Register description: New Map
Output mapping can be performed on a per-channel basis according to the CxOM channel output mapping bits. Each input into the output configuration engine can receive data from any of the three processing channel outputs.
.
Table 66.
Channel output mapping as a function of C3OM bits
C3OM[1:0] Channel x output source from
00
01
10
Channel1
Channel 2
Channel 3
6.22 Tone control register (addr 0x22)
D7
TTC3
0
D6
TTC2
1
D5
TTC1
1
D4
TTC0
1
D3
BTC3
0
D2
BTC2
1
D1
BTC1
1
D0
BTC0
1
Table 67.
Tone control boost/cut as a function of BTC and TTC bits
BTC[3:0]/TTC[3:0] Boost/cut
0000
0001
…
0111
0110
0111
1000
1001
-12 dB
-12 dB
…
-4 dB
-2 dB
0 dB
+2 dB
+4 dB
… …
1101 +12 dB
1110 +12 dB Obsolete Product(s) - Obsolete Product(s)
1111 +12 dB
Doc ID 022784 Rev 1 73/172
Register description: New Map STA382BWS
6.23 Dynamic control registers (addr 0x23 - 0x26 / addr 0x43 -
0x46)
6.23.1 Limiter 1 attack/release rate (L1AR addr 0x23)
D7
L1A3
0
D6
L1A2
1
D5
L1A1
1
D4
L1A0
0
D3
L1R3
1
D2
L1R2
0
D1
L1R1
1
D0
L1R0
0
6.23.2 Limiter 1 attack/release threshold (L1ATRT addr 0x24)
D7
L1AT3
0
D6
L1AT2
1
D5
L1AT1
1
D4
L1AT0
0
D3
L1RT3
1
D2
L1RT2
0
D1
L1RT1
0
6.23.3 Limiter 2 attack/release rate ( L2AR addr 0x25)
D7
L2A3
0
D6
L2A2
1
D5
L2A1
1
D4
L2A0
0
D3
L2R3
1
D2
L2R2
0
D1
L2R1
1
D0
L1RT0
1
D0
L2R0
0
6.23.4 Limiter 2 attack/release threshold ( L2 ATRT addr 0x26)
D7
L2AT3
0
D6
L2AT2
1
D5
L2AT1
1
D4
L2AT0
0
D3
L2RT3
1
D2
L2RT2
0
D1
L2RT1
0
D0
L2RT0
1
The STA382BWS includes two independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anticlipping mode or to actively reduce the dynamic range for a better listening environment such as a nighttime listening mode which is often needed for DVDs. The two modes are selected via the DRC bit in
Section 6.11: FUNCT register (addr 0x0A) . Each
channel can be mapped to either limiter or not mapped, meaning that the channel will clip when 0 dBfs is exceeded. Each limiter looks at the present value of each channel that is mapped to it, selects the maximum absolute value of all these channels, performs the limiting algorithm on that value, and then, if needed, adjusts the gain of the mapped channels in unison.
The limiter attack thresholds are determined by the LxAT registers if the EATHx[7] (bit D7 of Obsolete Product(s) - Obsolete Product(s) is recommended in anticlipping mode to set this to 0 dBfs, which corresponds to the maximum unclipped output power of an FFX amplifier. Since gain can be added digitally within the STA382BWS it is possible to exceed 0 dBfs or any other LxAT setting. When this occurs, the limiter, when active, automatically starts reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. Gain reduction occurs on a peak-detect algorithm. Setting the
EATHx[7] bits to 1 selects the anticlipping mode.
The limiter release thresholds are determined by the LxRT registers if the ERTHx[7] (bit D7 of register 0x44 or 0x46) bits are set to 0, else the thresholds are determined by
74/172 Doc ID 022784 Rev 1
STA382BWS Register description: New Map
ERTHx[6:0]. Setting the ERTHx[7] bits to 1 automatically selects the anticlipping mode. The release of the limiter, when the gain is again increased, is dependent on an RMS-detect algorithm. The output of the volume/limiter block is passed through an RMS filter. The output of this filter is compared to the release threshold, determined by the release threshold register. When the RMS filter output falls below the release threshold, the gain is again increased at a rate dependent upon the release rate register. The gain can never be increased past its set value and, therefore, the release only occurs if the limiter has already reduced the gain. The release threshold value can be used to set what is effectively a minimum dynamic range, this is helpful as overlimiting can reduce the dynamic range to virtually zero and cause program material to sound “lifeless”.
In anticlipping mode, the attack and release thresholds are set relative to full-scale. In DRC mode (bit D0 reg 0x0A set to 1), the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold.
Obsolete Product(s) - Obsolete Product(s)
Doc ID 022784 Rev 1 75/172
Register description: New Map
Figure 25.
Basic limiter and volume flow diagram
Limiter
RM S
STA382BWS
G a in / Vo l u me
+
In p u t
G a in
Table 68.
Limiter attack rate as a function of LxA bits
LxA[3:0] Attack rate dB/ms
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
0.1123
0.0902
0.0752
0.0645
0.0564
0.0501
0.0451
3.1584
2.7072
2.2560
1.8048
1.3536
0.9024
0.4512
0.2256
0.1504
Fast
Atten ua tio n Sa t u r a tio n
O u tp u t
Table 69.
Limiter release rate as a function of LxR bits
LxR[3:0] Release rate dB/ms
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
0.0172
0.0147
0.0137
0.0134
0.0117
0.0110
0.0104
0.5116
0.1370
0.0744
0.0499
0.0360
0.0299
0.0264
0.0208
0.0198
Fast
Slow
76/172 Doc ID 022784 Rev 1
STA382BWS Register description: New Map
Anticlipping mode
LxAT[3:0]
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
Table 70.
Limiter attack threshold as a function of LxAT bits
(AC mode)
AC (dB relative to fs) LxRT[3:0]
+3
+4
+5
-12
-10
-8
0000
0001
0010
-6
-4
0011
0100
-2 0101
0 0110
+2 0111
1000
1001
1010
+6
+7
+8
1011
1100
1101
+9 1110
+10 1111
Table 71.
Limiter release threshold as a function of LxRT bits
(AC mode)
AC (dB relative to fs)
∞
-29 dB
-20 dB
-16 dB
-14 dB
-12 dB
-10 dB
-8 dB
-7 dB
-6 dB
-5 dB
-4 dB
-3 dB
-2 dB
-1 dB
-0 dB
Obsolete Product(s) - Obsolete Product(s)
Doc ID 022784 Rev 1 77/172
Register description: New Map
Dynamic range compression mode
Table 72.
Limiter attack threshold as a function of LxAT bits (DRC mode)
LxAT[3:0] DRC (dB relative to volume)
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
-16
-15
-14
-13
-12
-10
-7
-4
-23
-21
-19
-17
-31
-29
-27
-25
STA382BWS
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
Table 73.
Limiter release threshold as a function of LxRT bits
(DRC mode)
LxRT[3:0]
DRC (dB relative to volume +
LxAT)
∞
-38 dB
-36 dB
-33 dB
-31 dB
-30 dB
-28 dB
-26 dB
-24 dB
-22 dB
-20 dB
-18 dB
-15 dB
-12 dB
-9 dB
-6 dB
6.23.5 Limiter 1 extended attack threshold (addr 0x43)
D7
EATHEN1
0
D6
EATH1[6]
0
D5
EATH1[5]
1
D4
EATH1[4]
1
D3
EATH1[3]
0
D2
EATH1[2]
0
The extended attack threshold value is determined as follows: attack threshold = -12 + EATH1 / 4
To enable this feature, the EATHEN1 bit must be set to 1.
D1
EATH1[1]
0
D0
EATH1[0]
0
78/172
D7
ERTHEN1
0
D6
ERTH1[6]
0
D5
ERTH1[5]
1
D4
ERTH1[4]
1
D3
ERTH1[3]
0
D2
ERTH1[2]
0
The extended release threshold value is determined as follows: release threshold = -12 + ERTH1 / 4
To enable this feature, the ERTHEN1 bit must be set to 1.
D1
ERTH1[1]
0
D0
ERTH1[0]
0
Doc ID 022784 Rev 1
STA382BWS Register description: New Map
6.23.7 Limiter 2 extended attack threshold (addr 0x45)
D7
EATHEN2
0
D6
EATH2[6]
0
D5
EATH2[5]
1
D4
EATH2[4]
1
D3
EATH2[3]
0
D2
EATH2[2]
0
The extended attack threshold value is determined as follows: attack threshold = -12 + EATH2 / 4
To enable this feature, the EATHEN2 bit must be set to 1.
D1
EATH2[1]
0
6.23.8 Limiter 2 extended release threshold (addr 0x46)
Note:
D7
ERTHEN2
0
D6
ERTH2[6]
0
D5
ERTH2[5]
1
D4
ERTH2[4]
1
D3
ERTH2[3]
0
D2
ERTH2[2]
0
The extended release threshold value is determined as follows: release threshold = -12 + ERTH2 / 4
To enable this feature, the ERTHEN2 bit must be set to 1.
Attack/release threshold step is 0.125 dB in the range -12 dB to 0 dB.
D1
ERTH2[1]
0
D0
EATH2[0]
0
D0
ERTH2[0]
0
6.24 User-defined coefficient control registers (addr 0x27 - 0x37)
6.24.1 Coefficient address register
D7
Reserved
0
D6
Reserved
0
D5
CFA5
0
D4
CFA4
0
D3
CFA3
0
D2
CFA2
0
D1
CFA1
0
D0
CFA0
0
6.24.2 Coefficient register bits 23:16
D7
C1B23
0
D6
C1B22
0
D5
C1B21
0
D4
C1B20
0
D3
C1B19
0
D2
C1B18
0
D1
C1B17
0
D0
C1B16
0
6.24.3 Coefficient data register bits 15:8
Obsolete Product(s) - Obsolete Product(s)
D7 D6 D5 D4 D3 D2 D1 D0
C1B15
0
C1B14
0
C1B13
0
C1B12
0
C1B11
0
C1B10
0
C1B9
0
C1B8
0
6.24.4 Coefficient data register bits 7:0
D7
C1B7
0
D6
C1B6
0
D5
C1B5
0
D4
C1B4
0
D3
C1B3
0
D2
C1B2
0
D1
C1B1
0
D0
C1B0
0
Doc ID 022784 Rev 1 79/172
Register description: New Map
6.24.5 Coefficient register bits 23:16
D7
C2B23
0
D6
C2B22
0
D5
C2B21
0
D4
C2B20
0
D3
C2B19
0
6.24.6 Coefficient data register bits 15:8
D7
C2B15
0
D6
C2B14
0
D5
C2B13
0
D4
C2B12
0
D3
C2B11
0
6.24.7 Coefficient data register bits 7:0
D7
C2B7
0
D6
C2B6
0
D5
C2B5
0
D4
C2B4
0
D3
C2B3
0
6.24.8 Coefficient register bits 23:16
D7
C1B23
0
D6
C1B22
0
D5
C1B21
0
D4
C1B20
0
D3
C1B19
0
6.24.9 Coefficient data register bits 15:8
D7
C3B15
0
D6
C3B14
0
D5
C3B13
0
D4
C3B12
0
D3
C3B11
0
D2
C2B18
0
D1
C2B17
0
D0
C2B16
0
D2
C2B10
0
D2
C2B2
0
D2
C1B18
0
D1
C1B17
0
D0
C1B16
0
D2
C3B10
0
D1
C2B9
0
D1
C2B1
0
D1
C3B9
0
STA382BWS
D0
C2B8
0
D0
C2B0
0
D0
C3B8
0
D7
C3B7
0
D6
C3B6
0
D5
C3B5
0
D4
C3B4
0
D3
C3B3
0
D2
C3B2
0
D1
C3B1
0
D0
C3B0
0
Obsolete Product(s) - Obsolete Product(s)
D7 D6 D5 D4 D3 D2 D1 D0
C4B23
0
C4B22
0
C4B21
0
C4B20
0
C4B19
0
C4B18
0
C4B17
0
C4B16
0
80/172 Doc ID 022784 Rev 1
STA382BWS Register description: New Map
D7
C4B15
0
D6
C4B14
0
D5
C4B13
0
D4
C4B12
0
D3
C4B11
0
D2
C4B10
0
D1
C4B9
0
D0
C4B8
0
D7
C4B7
0
D6
C4B6
0
D5
C4B5
0
D4
C4B4
0
D3
C4B3
0
D2
C4B2
0
D1
C4B1
0
D0
C4B0
0
D7
C5B23
0
D6
C5B22
0
D5
C5B21
0
D4
C5B20
0
D3
C5B19
0
D2
C5B18
0
D1
C5B17
0
D0
C5B16
0
D7
C5B15
0
D6
C5B14
0
D5
C5B13
0
D4
C5B12
0
D3
C5B11
0
D2
C5B10
0
D1
C5B9
0
D0
C5B8
0
D7
C5B7
0
D6
C5B6
0
D5
C5B5
0
D4
C5B4
0
D3
C5B3
0
D2
C5B2
0
D1
C5B1
0
D0
C5B0
0
D7 D6 D5 D4
Reserved
0
D3
RA
0
D2
R1
0
D1
WA
0
D0
W1
0
Coefficients for user-defined EQ, mixing, scaling, and bass management are handled
I internally in the STA382BWS via RAM. Access to this RAM is available to the user via an Obsolete Product(s) - Obsolete Product(s) a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write/read of the coefficient(s) to/from RAM.
Note: The read and write operation on RAM coefficients works only if the LRCKI pin is switching.
Doc ID 022784 Rev 1 81/172
Register description: New Map STA382BWS
Reading a coefficient from RAM
1.
Write 6 bits of the address to I
2
C register 0x27.
2. Write 1 to the R1 bit in I
2
C address 0x37.
3. Read the top 8 bits of the coefficient in I
2
C address 0x28.
4. Read the middle 8 bits of the coefficient in I
2
C address 0x29.
5. Read the bottom 8 bits of the coefficient in I
2
C address 0x2A.
Reading a set of coefficients from RAM
1.
Write 6 bits of the address to I
2
C register 0x27.
2. Write 1 to the RA bit in I
2
C address 0x37.
3. Read the top 8 bits of the coefficient in I
2
C address 0x28.
4. Read the middle 8 bits of the coefficient in I
2
C address 0x29.
5. Read the bottom 8 bits of the coefficient in I
2
C address 0x2A.
6. Read the top 8 bits of coefficient b2 in I
2
C address 0x2B.
7. Read the middle 8 bits of coefficient b2 in I
2
C address 0x2C.
8. Read the bottom 8 bits of coefficient b2 in I
2
C address 0x2D.
9. Read the top 8 bits of coefficient a1 in I
2
C address 0x2E.
10. Read the middle 8 bits of coefficient a1 in I
2
C address 0x2F.
11. Read the bottom 8 bits of coefficient a1 in I
2
C address 0x30.
12. Read the top 8 bits of coefficient a2 in I
2
C address 0x31.
13. Read the middle 8 bits of coefficient a2 in I
2
C address 0x32.
14. Read the bottom 8 bits of coefficient a2 in I
2
C address 0x33.
15. Read the top 8 bits of coefficient b0 in I
2
C address 0x34.
16. Read the middle 8 bits of coefficient b0 in I
2
C address 0x35.
17. Read the bottom 8 bits of coefficient b0 in I
2
C address 0x36.
Writing a single coefficient to RAM
1.
Write 6 bits of the address to I
2
C register 0x27.
2. Write the top 8 bits of the coefficient in I
2
C address 0x28.
3. Write the middle 8 bits of the coefficient in I
2
C address 0x29.
4. Write the bottom 8 bits of the coefficient in I
2
C address 0x2A.
5. Write 1 to the W1 bit in I
2
C address 0x37.
Obsolete Product(s) - Obsolete Product(s)
82/172 Doc ID 022784 Rev 1
STA382BWS Register description: New Map
Writing a set of coefficients to RAM
1.
Write 6 bits of the starting address to I
2
C register 0x27.
2. Write the top 8 bits of coefficient b1 in I
2
C address 0x28.
3. Write the middle 8 bits of coefficient b1 in I
2
C address 0x29.
4. Write the bottom 8 bits of coefficient b1 in I
2
C address 0x2A.
5. Write the top 8 bits of coefficient b2 in I
2
C address 0x2B.
6. Write the middle 8 bits of coefficient b2 in I
2
C address 0x2C.
7. Write the bottom 8 bits of coefficient b2 in I
2
C address 0x2D.
8. Write the top 8 bits of coefficient a1 in I
2
C address 0x2E.
9. Write the middle 8 bits of coefficient a1 in I
2
C address 0x2F.
10. Write the bottom 8 bits of coefficient a1 in I
2
C address 0x30.
11. Write the top 8 bits of coefficient a2 in I
2
C address 0x31.
12. Write the middle 8 bits of coefficient a2 in I
2
C address 0x32.
13. Write the bottom 8 bits of coefficient a2 in I
2
C address 0x33.
14. Write the top 8 bits of coefficient b0 in I
2
C address 0x34.
15. Write the middle 8 bits of coefficient b0 in I
2
C address 0x35.
16. Write the bottom 8 bits of coefficient b0 in I
2
C address 0x36.
17. Write 1 to the WA bit in I
2
C address 0x37.
The mechanism for writing a set of coefficients to RAM provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side effects. When using this technique, the 6-bit address specifies the address of the biquad b1 coefficient (for example, 0, 5, 10, 20, 35 decimal), and the
STA382BWS generates the RAM addresses as offsets from this base value to write the complete set of coefficient data.
Obsolete Product(s) - Obsolete Product(s)
Doc ID 022784 Rev 1 83/172
Register description: New Map STA382BWS
The STA382BWS can be programmed for four EQ filters (biquads) per each of the two input channels. The biquads use the following equation:
Y[n] = 2 * (b
0
/ 2) * X[n] + 2 * (b
1
/ 2) * X[n-1] + b
2
* X[n-2] - 2 * (a
1
/ 2) * Y[n-1] - a
2
* Y[n-2]
= b
0
* X[n] + b
1
* X[n-1] + b
2
* X[n-2] - a
1
* Y[n-1] - a
2
* Y[n-2] where Y[n] represents the output and X[n] represents the input. Multipliers are 24-bit signed fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF
(0.9999998808).
Coefficients stored in the user-defined coefficient RAM are referenced in the following manner:
CxHy0 = b
1
/ 2
CxHy1 = b
2
CxHy2 = -a
1
/ 2
CxHy3 = -a
2
CxHy4 = b
0
/ 2 where x represents the channel and the y the biquad number. For example, C2H41 is the b
2 coefficient in the fourth biquad for channel 2.
Additionally, the STA382BWS can be programmed for a high-pass filter (processing channels 1 and 2) and a low-pass filter (processing channel 3) to be used for bassmanagement crossover when the XO setting is 000 (user-defined). Both of these filters when defined by the user (rather than using the preset crossover filters) are second order filters that use the biquad equation given above. They are loaded into the C12H0-4 and
C3Hy0-4 areas of RAM noted in
Channel 1 and channel 2 biquads use by default the extended coefficient range (-4, +4);
Xover filters use only the standard coefficients range (-1, +1).
By default, all user-defined filters are pass-through where all coefficients are set to 0, except the channel 1 and 2 b
0
/2 coefficient which is set to 0x100000 (representing 0.5) and Xover b
0
/2 coefficient which is set to 0x400000 (representing 0.5).
6.24.19 Pre-scale
The STA382BWS provides a multiplication for each input channel for the purpose of scaling the input prior to EQ. This pre-EQ scaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiplication is loaded into RAM using the same I
2
C registers as the biquad coefficients and the bass management. All channels can use the channel-1 pre-scale factor Obsolete Product(s) - Obsolete Product(s)
6.24.20 Post-scale
The STA382BWS provides one additional multiplication after the last interpolation stage and the distortion compensation on each channel. This post-scaling is accomplished by using a
24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiplication is loaded into RAM using the same I
2
C registers as the biquad coefficients and the bass management. This post-scale factor can be used in conjunction with an ADC-equipped microcontroller to perform power-supply error correction.
All channels can use the channel-1 post-scale factor by setting the post-scale link bit. By
84/172 Doc ID 022784 Rev 1
STA382BWS Register description: New Map default, all post-scale factors are set to 0x7FFFFF. When line output is being used, channel-3 post-scale will affect both channels 3 and 4.
Table 74.
RAM block for biquads, mixing, scaling and bass management
Index (decimal) Index (hex) Description Coefficient Default
46
47
48
49
42
43
44
45
50
51
52
53
…
39
40
41
19
20
21
3
4
5
…
0
1
2
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x13
0x14
0x15
…
0x27
0x28
0x29
0x00
0x01
0x02
0x03
0x04
0x05
…
Channel 1 - Biquad 1
Channel 1 - Biquad 2
…
Channel 1 - Biquad 4
Channel 2 - Biquad 1
…
Channel 2 - Biquad 4
Channel 1/2 - Biquad 5 for XO = 000
High-pass 2 nd
order filter for XO ≠ 000
Channel 3 - Biquad for XO = 000
Low-pass 2 nd
order filter for XO ≠ 000
Channel 1 - Pre-Scale
Channel 2 - Pre-Scale
Channel 1 - Post-Scale
Channel 2 - Post-Scale
C12H2(a1/2)
C12H3(a2)
C12H4(b0/2)
C3H0(b1/2)
C3H1(b2)
C3H2(a1/2)
C3H3(a2)
C3H4(b0/2)
C1PreS
C2PreS
C1PstS
C2PstS
C1H10(b1/2)
C1H11(b2)
C1H12(a1/2)
C1H13(a2)
C1H14(b0/2)
C1H20
…
C1H44
C2H10
C2H11
…
C2H44
C12H0(b1/2)
C12H1(b2)
54 0x36 Channel 3 - Post-Scale C3PstS 0x7FFFFF
55 0x37 Reserved reserved 0x5A9DF7
56 0x38 Channel 1 - Mix 1 C1MX1 0x7FFFFF Obsolete Product(s) - Obsolete Product(s)
57 0x39 Channel 1 - Mix 2 C1MX2 0x000000
58 0x3A Channel 2 - Mix 1 C2MX1 0x000000
59 0x3B Channel 2 - Mix 2 C2MX2 0x7FFFFF
60
61
62
63
0x3C
0x3D
0x3E
0x3F
Channel 3 - Mix 1
Channel 3 - Mix 2
UNUSED
UNUSED
C3MX1
C3MX2
0x400000
0x400000
0x000000
0x000000
0x400000
0x000000
0x000000
0x000000
0x000000
0x400000
0x7FFFFF
0x7FFFFF
0x7FFFFF
0x7FFFFF
0x000000
0x000000
0x000000
0x000000
0x100000
0x000000
…
0x100000
0x000000
0x000000
…
0x100000
0x000000
0x000000
Doc ID 022784 Rev 1 85/172
Register description: New Map STA382BWS
6.25 Fault-detect recovery constant registers (addr 0x3C - 0x3D)
D7
FDRC15
0
D6
FDRC14
0
D5
FDRC13
1
D4
FDRC12
1
D3
FDRC11
0
D2
FDRC10
0
D1
FDRC9
0
D0
FDRC8
0
D7
FDRC7
0
D6
FDRC6
0
D5
FDRC5
0
D4
FDRC4
0
D3
FDRC3
1
D2
FDRC2
1
D1
FDRC1
0
D0
FDRC0
0
The FDRC bits specify the 16-bit fault-detect recovery time delay. When FAULT is asserted, the TRISTATE output is immediately asserted low and held low for the time period specified by this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The default value of 0x300C gives approximately 1 sec.
0x0000 is a reserved value.
D7
Reserved
0
D6
Reserved
D5
PS48DB
0
D4
XAR1
0
D3
XAR2
0
D2
BQ5
1
D1
BQ6
1
The extended configuration register provides access to biquad 5, 6 and 7.
D0
BQ7
1
6.26.1 Extended post-scale range
Table 75.
Extended post-scale range
PS48DB
0
1
Mode
Post-scale value is applied as defined in the coefficient RAM
Post-scale value is applied with a +48 dB offset with respect to the coefficient RAM value
Post-scale is an attenuation by default. When PS48DB is set to 1, a 48-dB offset is applied to the coefficient RAM value, so post-scale can act as a gain too.
6.26.2 Extended attack rate on both limiters.
Table 76.
Extended attack rate, limiter 1
XAR1
0
1
Mode
Limiter1 attack rate is configured using
Limiter1 attack rate is 8 dB/ms
86/172 Doc ID 022784 Rev 1
STA382BWS Register description: New Map
Table 77.
Extended attack rate, limiter 2
XAR2
0
1
Mode
Limiter2 attack rate is configured using
Limiter2 attack rate is 8 dB/ms
Bass and treble controls can be configured as user-defined filters when the equalization coefficients link is activated (BQL = 1) and the corresponding BQx bit is set to 1.
Table 78.
Extended biquad selector, biquad 5
BQ5
0
1
Mode
Reserved
User-defined biquad 5 coefficients are selected
Table 79.
Extended biquad selector, biquad 6
BQ6
0
1
Mode
Pre-set bass filter selected as per Table 67
User-defined biquad 6 coefficients are selected
Table 80.
Extended biquad selector, biquad 7
BQ7
0
1
Mode
Pre-set treble filter selected as per Table 67
User-defined biquad 7 coefficients are selected
Note:
When filters from the 5th to 7th are configured as user-programmable, the corresponding coefficients are stored respectively in addresses 0x20-0x24 (BQ5), 0x25-0x29 (BQ6), 0x2A-
0x2E (BQ7) as given in
.
The BQx bits are ignored if BQL = 0 or if DEMP = 1 (relevant for BQ5) or CxTCB = 1
(relevant for BQ6 and BQ7).
Obsolete Product(s) - Obsolete Product(s)
Doc ID 022784 Rev 1 87/172
Register description: New Map STA382BWS
6.27 PLL configuration registers (address 0x52; 0x53; 0x54; 0x55;
0x56; 0x57)
D7
0
D7
D6
0
D6
0 0
D7
PLL_DITH[1:0]
D6
0 0
D7
PLL_DPD
0
D6
PLL_FCT
0
D7
Reserved
0
D6
Reserved
0
D5
0
D5
0
D5
0
D5
PLL_STB
0
D5
PLL_DIRP
0
D4 D3
PLL_FRAC[15:8]
0 0
D4 D3
0
PLL_FRAC[7:0]
0
D4
0
D4
PLL_STBBYP
0
D4
PLL_PWD
0
D2
0
D2
D1
0
D1
D0
0
D0
0 0 0
D0 D3 D2
PLL_NDIV[5:0]
0 0
D3
0
D1
0
D2
PLL_IDIV[3:0]
D1
0 0
D3
PLL_BYP
0
D2
OSC_PD
0
0
D0
D1
Reserved
0
0
D0
BOOST32K
0
D7
Reserved
NA
D6
Reserved
NA
D5
Reserved
NA
D4
Reserved
NA
D3
BYPSTATE
NA
D2
PDSTATE
NA
D1
OSCOK
NA
D0
LOWCK
NA
By default, the STA382BWS is able to configure the embedded PLL automatically depending on the MCS bits (reg 0x00). For certain applications and to provide flexibility to the user, a manual PLL configuration can be used (setting PLL_DIRP to ‘1’)
The output PLL frequency formula is:
Fin
×
( )
(
IDIV
+
1
)
+ -----------------
65536
⎞ where Fin is the input clock frequency from the pad.
Table 81.
PLL factors Obsolete Product(s) - Obsolete Product(s)
PLL parameter Min Max
FRAC
IDIV
0
0
65535
3
NDIV 5 55
88/172 Doc ID 022784 Rev 1
STA382BWS Register description: New Map
2
1
0
5
4
3
Table 82.
PLL register 0x54 bits
Bit
7
6
R/W
R/W
R/W
RST
0
0
Name Description
PLL_DITH[1:0]
“00”: PLL clock dithering disabled
“01”: PLL clock dithering enabled (triangular)
“10”: PLL clock dithering enabled (rectangular)
“11”: reserved
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
PLL_NDIV PLL loop divider
Table 83.
PLL register 0x55 bits
Bit
7
6
5
4
R/W
R/W
R/W
R/W
R/W
RST
0
0
0
0
Name Description
PLL_DPD
‘0’: any PLL dividers change is implemented via PLL power-down
‘1’: PLL divider change will happen without PLL powerdown
PLL_FCT
‘0’: PLL use integer ratio
‘1’: PLL use fractional ratio
PLL_STB PLL synchronous divider changes strobe
PLL_STBBYP
‘0’: PLL_STB is active
‘1’: PLL_STB control is bypassed
1
0
3
2
R/W
R/W
R/W
R/W
0
0
0
0
PLL_IDIV[3:0] Input PLL divider
Table 84.
PLL register 0x56 bits
Bit R/W RST Name Description
‘0’: PLL configuration is determined by the MCS bits
5 R/W 0 PLL_DIRP
4 R/W 0 PLL_PWD
‘1’: PLL configuration is determined by FRAC, IDIV and NDIV
‘0’: PLL normal behavior
‘1’: PLL is in power-down mode
3
2
0
R/W
R/W
R/W
0
0
0
PLL_BYP
OSC_PD
BOOST32K
‘0’: sys clock is from PLL
‘1’: sys clock is from external pin (PLL is bypassed)
‘0’: Normal behavior
‘1’: Internal oscillator is in power-down
‘0’: Input oversampling selected by the IR bits
‘1’: Input oversampling is selected x3
Doc ID 022784 Rev 1 89/172
Register description: New Map STA382BWS
Table 85.
PLL register 0x57 bits
Bit R/W RST Name
3
2
1
0
R/W
R/W
R/W
R/W
BYPSTATE
PDSTATE
OSCOK
LOWCK
Description
PLL bypass state
PLL PD state
OSCI locked
Clock input low-frequency check
6.28 Short-circuit protection mode registers SHOK (address 0x58)
D7 reserved
NA
D6 reserved
NA
D5 reserved
NA
D4 reserved
NA
D3 reserved
NA
D2
GNDSH
NA
D1
VCCSH
NA
D0
OUTSH
NA
●
●
●
The following power bridge pins short-circuit protections are implemented in the
STA382BWS:
OUTxx vs. GNDx
OUTxx vs. VCCx
OUT1B vs. OUT2A
The protection is enabled when reg. 0x50 bit 0 (SHEN) is set to ‘1’. The protection will check the short-circuit when the EAPD bit is toggled from ‘0’ to ‘1’ (i.e. the power bridge is switched on), and only if the test passes (no short), does the power bridge leave the tristate condition.
Register 0x58 (read-only registers) will give more information about the detected short type.
GNDSH equal to ‘0’ means that OUTxx is shorted to ground, while the same value on
VCCSH means that OUTxx is shorted to Vcc, finally OUTSH=’0’ means that OUT1B is shorted to OUT2A.
To be noted that once the check is performed, and the tristate released, the short protection is not active anymore until the next EAPD 0->1 toggling which means that shorts that happened during normal operation cannot be detected.
To be noted that register SHOK is meaningful only after the EAPD bit is set to ‘1’ at least once.
The short-circuit protections implemented are effective only in BTL configuration, and they must not be activated if a single-ended application scheme is needed.
Obsolete Product(s) - Obsolete Product(s)
90/172 Doc ID 022784 Rev 1
STA382BWS Register description: New Map
Figure 26.
Short-circuit detection timing diagram (no short detected)
S t a r t g n d t e s t S t a r t v c c t e s t
S t a rt o u t te s t
E n d o f S h o r t t e s t
EAPD
OUT1A
OUT1B
OUT2A
OUT2B
GND S H]
VCC S H
OUT S H]
50005 cycle s
44 cycle s
50005 cycle s
TBD cycle s
1cycle
the short protection timing diagram is shown. The time information is expressed
. The gray color is used for the short status bits to indicate that the bits are carrying the status of the previous EAPD 0->1 toggling (to be noted that after reset this state is meaningless since no EAPD transition occurs). The GND-related SHOK bits are updated as soon as the gnd test is completed, the VCC bits are updated after vcc test is completed, and the SOUT bit is updated after the shorted output test is completed. The gnd test, vcc test and output test, are always run (if the SHEN bit is active and EAPD toggled to ‘1’), and only if both tests are successful (no short) do the bridge outputs leave the tristate (indicated by dotted lines in the figure). If one of the three tests (or all) fail, the power bridge outputs are kept in the tristate until the procedure is restarted with a new EAPD toggling.
In this figure EAPD is intended to be bit 7 of register 0x05.
D7 D6
CEXT_B4[1] CEXT_B4[0]
1 0
D5
CEXT_B3[1]
1
D4
CEXT_B3[0]
0
D3 D2
CEXT_B2[1] CEXT_B2[0]
1 0
D1
CEXT_B1[1]
1
D0
CEXT_B1[0]
0 reserved
0
D6 reserved
0
D5
CEXT_B7[1]
1
D4
CEXT_B7[0]
0
D3 D2
CEXT_B6[1] CEXT_B6[0]
1 0
D1
CEXT_B51]
1
D0
CEXT_B5[0]
0
Biquads from 1 to 7 have in the STA382BWS the possibility to extend the coefficient range from [-1,1) to [-4..4) which allows the use of high-shelf filters that may require a coefficient dynamic greater in absolute value than 1.
Three ranges are available, [-1;1) [-2;2) [-4;4). By default, the extended range is activated.
Each biquad has its independent setting according to the following table.
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Register description: New Map
Table 86.
Coefficients extended range configuration
CEXT_Bx[1]
0
0
1
1
CEXT_Bx[0]
0
1
0
1
STA382BWS
Range
[-1;1)
[-2;2)
[-4;4)
Reserved
In this case the user can decide, for each filter stage, the right coefficient range. Note that for a given biquad the same range will be applied to the left and right (channel 1 and channel
2).
The crossover biquad does not have the availability of this feature, maintaining the [-1;1) range unchanged.
D7
RPDNEN
0
D7
LPDP
0
D6
Reserved
1
D6
LPD
1
D5
BRIDGOFF
1
D5
LPDE
0
D4
Reserved
0
D4
PNDLSL[2]
0
D3
Reserved
0
D2
CPWMEN
1
D3
PNDLSL[1]
1
D2
PNDLSL[0]
1
D1
Reserved
0
D1
Reserved
0
D0
Reserved
0
D0
SHEN
0
In the STA382BWS, by default, the power-down pin and I
2
C power-down act on mute commands to perform the fade-out. This default can be changed so that the fade-out can be started using the master volume. The RPDNEN bit, when set, activates this feature.
6.30.2 Bridge immediately off (BRIDGOFF) bit (address 0x4B, bit D5)
A fade-out procedure is started in the STA382BWS once the PWDN function is enabled, and after 13 million clock cycles (PLL internal frequency) the bridge is put in power-down
(tristate mode). There is also the possibility to change this behavior so that the power bridge
Obsolete Product(s) - Obsolete Product(s) immediate power-down will generate a pop noise at the output, therefore this procedure must be used only in cases where pop noise is not relevant in the application. Note that this feature works only for hardware PWDN assertion and not for a power-down applied through
the IIC interface. Refer to Section 6.30.5
if programming a different number of clock cycles is needed.
92/172 Doc ID 022784 Rev 1
STA382BWS Register description: New Map
6.30.3 Channel PWM enable (CPWMEN) bit
This bit, when set, activates a mute output in case the volume reaches a value lower than -76 dBFS.
Pin 42 (INTLINE), normally indicating a fault condition, using the following 3 register settings can be reconfigured as a hardware pin enabler for an external headphone or line amplifier.
In particular the LPDE bit, when set, activates this function. Accordingly, the LPD value (0 or
1) is exported on pin 42 and in case of power-down assertion, pin 42 is tied to LPDP.
The LPDP bit, when set, negates the value programmed as the LPD value, refer to the following table.
Table 87.
External amplifier enabler configuration bits
LPDP LPD LPDE Pin 42 output
0
1 x
0
1 x
0
1
0
1
0
1
1
1
1
INT_LINE
0
1
1
0
Figure 27.
Alternate function for INTLINE pin
P o w er B rid ge Fau lt
0
‘0 ’
Y
L P D
N
0
1
1
IN T L IN E
L P D E
L P D P
6.30.5 Power-down delay selector (PNDLSL[2:0]) bits
The assertion of PWDN activates a counter that, by default, after 13 million clock cycles puts the power bridge in tristate mode, independently from the fade-out time. Using these registers it is possible to program this counter according to the following table.
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Register description: New Map
Table 88.
PNDLSL bits configuration
PNDLSL[2] PNDLSL[1] PNDLSL[2]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
0
1
0
1
1
STA382BWS
Fade-out time
Default time (13M PLL clock cycles)
Default time divided by 2
Default time divided by 4
Default time divided by 8
Default time divided by 16
Default time divided by 32
Default time divided by 64
Default time divided by 128
6.30.6 Short-circuit check enable bit
This bit, when enabled, will activate the short-circuit checks before any power bridge
activation (EAPD bit 0->1). See section Section 6.28: Short-circuit protection mode registers
SHOK (address 0x58) for more details.
6.31 Bad PWM detection registers (address 0x5E, 0x5F, 0x60)
D7
BPTH[5]
0
D6
BPTH[4]
0
D5
BPTH[3]
1
D4
BPTH[2]
1
D3
BPTH[1]
0
D2
BPTH[0]
0
D1 reserved
1
D0 reserved
0
D7
BPTIM[7]
0
D6
BPTIM[6]
1
D5
BPTIM[5]
0
D4
BPTIM[4]
1
D3
BPTIM[3]
1
D2
BPTIM[2]
1
D1
BPTIM[1]
1
D0
BPTIM[0]
0
The STA382BWS implements a detection on PWM outputs able to verify if the output signal has no zero-crossing in a configurable time window. This check can be useful to detect the
DC level in the PWM outputs. To be noted that the checks are performed on logic level PWM
(i.e. not the power bridge ones, nor the PWM on DDX3 and DDX4 IOs).
In case of ternary modulation, the detection threshold is computed as:
Obsolete Product(s) - Obsolete Product(s)
If the measured PWM duty cycle is detected greater than or equal to TH for more than
BPTIM PWM periods, the corresponding PWM bit will be set in register 0x01.
In case of binary modulation, there are two thresholds:
TH1=[(64+BPTH)/128]*100%
TH2=[(64-BPTH)/128]*100%
In this case if the measured PWM duty cycle is outside the TH1-TH2 range for more than
BPTIM PWM periods, the corresponding bit will be set in register 0x4E.
94/172 Doc ID 022784 Rev 1
STA382BWS Register description: New Map
6.32 Enhanced zero-detect mute and input level measurement
(address 0x61-0x65, 0x3F, 0x40, 0x6F)
D7
WTHH
0
D6
WTHL
0
D5
FINETH
0
D4
HSEL[1:0]
D3
0 0
D2
1
D1
ZMTH[2:0]
1
D0
1
D7
N/A
D7
N/A
D6
N/A
D6
N/A
D5
N/A
D5
N/A
D4 D3
RMS_CH0[7:0]
N/A N/A
D4 D3
RMS_CH0[15:8]
N/A N/A
D2
N/A
D2
N/A
D1
N/A
D1
N/A
D0
N/A
D0
N/A
D7
N/A
D6
N/A
D5
N/A
D4 D3
RMS_CH1[7:0]
N/A N/A
D2
N/A
D1
N/A
D0
N/A
D7
N/A
D6
N/A
D5
N/A
D4 D3
RMS_CH1[15:8]
N/A N/A
D2
N/A
D1
N/A
D0
N/A
The STA382BWS implements an RMS-based zero-detect function (on serial input interface data) able to detect in a very reliable way the presence of an input signal, so that the power bridge outputs can be automatically connected to ground.
When active, the function will mute the output PWM when the input level becomes less than
“threshold - hysteresis”. Once muted, the PWM will be unmuted when the input level is detected greater than “threshold + hysteresis”.
The measured level is then reported (for each input channel) on registers ZCCCFG1 -
ZCCCFG2, ZCCCFG3 - ZCCCFG4 according to the following equation:
Value_in_dB = 20*Log
10
(Reg_value/(2
16
*0.635))
Table 89.
Zero-detect threshold
ZMTH[2:0]
000
001
011
100
101
110
111
Equivalent input level (dB)
-78
-84
-90
-96
-102
-108
-114
-114
Doc ID 022784 Rev 1 95/172
Register description: New Map
Table 90.
Zero-detect hysteresis
HSEL[1:0]
00
01
10
11
Equivalent input level hysteresis(dB)
3
4
5
6
STA382BWS
The thresholds and hysteresis table above can be overridden and the low-level threshold and high-level threshold can be set by the MTH[21:0] bits.
To activate the manual thresholds the FINETH bit has to be set to ‘1’.
To configure the low threshold, the WTHL bit must be set to ‘1’ so that any write operation to the MTH bits will set the low threshold.
To configure the low threshold, the WTHH bit must be set to ‘1’ so that any write operation to the MTH bits will set the low threshold.
If the zero-mute block does not detect mute, it will mute the output when the current RMS value falls below the low threshold.
If the zero-mute block does not detect mute, it will unmute the output when the current RMS value rises above the high threshold.
Table 91.
Manual threshold register 0x3F, 0x40 and 0x6F
D7
ReservedT
0
D6
Reserved
0
D5
0
D4
0
D3
MTH[21:16]
D2
0 0
D1
0
D0
0
D7
0
D6
0
D5
0
D4
MTH[15:8]
D3
0 0
D2
0
D1
0
D0
0
D7 D6 D5 D4 D3 D2 D1 D0
MTH[7:0]
0 0 0 0 0 0 0 0
Obsolete Product(s) - Obsolete Product(s)
96/172 Doc ID 022784 Rev 1
STA382BWS Register description: New Map
6.33 Headphone/Line out configuration register (address 0x66)
D7
HPLN
0
D6
Reserved
0
D5
Reserved
1
D4
Reserved
0
D3
CPFEN
0
D2
CPOK
NA
D1
ABFAULT
NA
D0
DCROK
NA
Table 92.
Headphone/Line out configuration bits
Bit R/W RST Name
7
3
2
1
0
R/W
R/W
R
R
R
0
0
NA
NA
NA
HPLN
CPFEN
CPOK
ABFAULT
DCROK
Description
When F3X is connected to the internal HP/Line driver this bit selects the gain of the F3X->analog out path.
‘0’: HP out. When the MVOL+Channel Vol is
0 dBFs, a 0 dBFs input will generate a 40 mW output on a 32 ohm load (+/- 3.3V supply).
‘1’: Line out. When the MVOL+Channel Vol is
0 dBFs, a 0 dBFs input will generate a 2 Vrms output (+/- 3.3 V supply)
‘0’: Charge pump auto-enable when unmute
‘1’: Charge pump is always enabled
‘0’: Charge pump is not working
‘1’: Charge pump is working and it is OK
‘0’: No fault on class-AB
‘1’: Overcurrent fault detected on class-AB
‘1’: Core supply OK
Obsolete Product(s) - Obsolete Product(s)
Doc ID 022784 Rev 1 97/172
Register description: New Map
6.34 F3XCFG (address 0x69; 0x6A)
STA382BWS
D7
F3XLNK
0
D7
F3X_FAULT
1
D6 reserved
0
D6 reserved
1
D5 reserved
0
D5 reserved
1
D4 reserved
0
D3 reserved
0
D2 reserved
0
D4
0
D3
F3X_SM_SLOPE[2:0]
1
D2
1
D1 reserved
0
D1
F3X_MUTE
1
D0 reserved
0
D0
F3X_ENA
0
Table 93.
F3X configuration register 1
Bit R/W RST Name
7 R/W 0 F3XLNK
Description
‘0’: F3X normal control mode
‘1’: F3X mute/unmute linked to HP/Line mute
Table 94.
F3X configuration register 2
Bit
7
4
3
2
1
0
R/W
R
R/W
R/W
R/W
R/W
R/W
RST
1
0
1
1
1
0
Name Description
F3X_FAULT
F3X_SM_SLOPE
F3X_MUTE
F3X_ENA
‘0’: Normal operation
‘000’: 0 ms
‘001’: 25 ms
‘010’: 50 ms
‘011’: 100 ms
‘100’: 200 ms
‘101’: 250 ms
‘110’: 500 ms
‘111’: 1000 ms
‘1’: Mute
‘1’: F3X enable
Obsolete Product(s) - Obsolete Product(s)
98/172 Doc ID 022784 Rev 1
STA382BWS Register description: New Map
6.35 STCompressor
TM
configuration register (address 0x6B;
0x6C)
Table 95.
Register STCCFG0
D7 D6 D5
Reserved
0
Reserved
0
Reserved
0
D4
Reserved
1
Table 96.
STCCFG0 register
Bit R/W RST Name
D3
Reserved
0
D2
CRC_RES
0
D1
Reserved
0
2 R/W 0 CRC_RES
Description
‘0’ = CRC comparison successful
‘1’ = CRC comparison error
D0
Reserved
0
Table 97.
Register STCCFG1
D7 D6 D5
Reserved Reserved Reserved
0 0 0
D4
Reserved
0
Table 98.
STCCFG1 register
Bit R/W RST Name
D3
Reserved
0
1 R/W 0 STC_LNK
D2
Reserved
0
D1
STC_LNK
0
D0
Reserved
0
Description
‘0’ = normal operations
‘1’ = stereo link enabled. See
6.36 Charge pump synchronization (address 0x70)
D7
Reserved
0
D6
Reserved
0
D5
CHPI
0
D4
1
D3
INITCNT[3:0]
D2
1 0
D1
0
D0
CHPRD
1
Table 99.
Charge pump sync configuration bits
Bit R/W RST Name Description
5 R/W 0 CHPI
‘0’: Charge pump phase: 0 deg
‘1’: Charge pump phase: 180 deg
4
3
R/W
R/W
1 Obsolete Product(s) - Obsolete Product(s)
1
INITCNT[3:0] Change charge pump phase at one clock step
2 R/W 0
1 R/W 0
0 R/W 1 CHPRD
‘0’: Charge pump synchronized with PWM frame
‘0’: Charge pump not synchronized with PWM frame
Doc ID 022784 Rev 1 99/172
Register description: New Map STA382BWS
The charge pump can be synchronized with the PWM frame in order to minimize the crosstalk between the charge pump and the PWM waveform.
This functionality cannot be activated when the PWMS bit (address 0x15 bit D4) is set to 1.
6.37 Coefficient RAM CRC protection (address 0x71-0x7D)
D7
BQCKE[7]
0
D6
BQCKE[6]
0
D5
BQCKE[5]
0
D4
BQCKE[4]
0
D3
BQCKE[3]
0
D2
BQCKE[2]
0
D1
BQCKE[1]
0
D0
BQCKE[0]
0
D7
BQCKE[15]
0
D6
BQCKE[14]
0
D5
BQCKE[13]
0
D4
BQCKE[12]
0
D3
BQCKE[11]
0
D2
BQCKE[10]
0
D7
BQCKE[23]
0
D6
BQCKE[22]
0
D5
BQCKE[21]
0
D4
BQCKE[20]
0
D3
BQCKE[19]
0
D2
BQCKE[18]
0
D1
BQCKE[17]
0
D0
BQCKE[16]
0
D7
XCCKE[7]
0
D7
XCCKE[15]
0
D6
XCCKE[6]
0
D6
XCCKE[14]
0
D5
XCCKE[5]
0
D5
XCCKE[13]
0
D4
XCCKE[4]
0
D4
XCCKE[12]
0
D3
XCCKE[3]
0
D3
XCCKE[11]
0
D2
XCCKE[2]
0
D2
XCCKE[10]
0
D1
BQCKE[9]
0
D1
XCCKE[1]
0
D1
XCCKE[9]
0
D0
BQCKE[8]
0
D0
XCCKE[0]
0
D0
XCCKE[8]
0
D7
XCCKE[23]
0
D6
XCCKE[22]
0
D5
XCCKE[21]
0
D4
XCCKE[20]
0
D3
XCCKE[19]
0
D2
XCCKE[18]
0
D1
XCCKE[17]
0
D0
XCCKE[16]
0
D7
BQCKR[7]
0
D7
BQCKR[15]
0
D6
BQCKR[6]
0
D6
BQCKR[14]
0
D5
BQCKR[5]
0
D5
BQCKR[13]
0
D4
BQCKR[4]
0
D3
BQCKR[3]
0
D4
BQCKR[12]
0
D3
BQCKR[11]
0
D2
BQCKR[2]
0
D2
BQCKR[10]
0
D1
BQCKR[1]
0
D1
BQCKR[9]
0
D0
BQCKR[0]
0
D0
BQCKR[8]
0
D7
BQCKR[23]
D6
BQCKR[22]
D5
BQCKR[21]
D4
BQCKR[20]
D3
BQCKR[19]
D2
BQCKR[18]
D1
BQCKR[17]
D0
BQCKR[16]
0 0 0 0 0 0 0 0 Obsolete Product(s) - Obsolete Product(s)
D7 D6 D5 D4 D3 D2 D1 D0
XCCKR[23] XCCKR[22] XCCKR[21] XCCKR[20] XCCKR[19] XCCKR[18] XCCKR[17] XCCKR[16]
0 0 0 0 0 0 0 0
D7
XCCKR[23]
0
D6
XCCKR[22]
0
D5
XCCKR[21]
0
D4
XCCKR[20]
0
D3
XCCKR[19]
0
D2
XCCKR[18]
0
D1
XCCKR[17]
0
D0
XCCKR[16]
0
D7
XCCKR[23]
D6
XCCKR[22]
D5
XCCKR[21]
D4
XCCKR[20]
D3
XCCKR[19]
D2
XCCKR[18]
D1
XCCKR[17]
D0
XCCKR[16]
100/172 Doc ID 022784 Rev 1
STA382BWS Register description: New Map
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
D7
XCAUTO
0
D6
XCRES
0
D5
XCCMP
0
D4
XCGO
0
D3
BCAUTO
0
D2
BCCRES
0
D1
BCCMP
0
D0
BCCGO
0
The STA382BWS implements an automatic CRC computation for the biquad and
MDRC/XOver coefficient memory (
). Memory cell contents from address 0x00 to
0x27 will be bit XORed to obtain the BQCHKE checksum, while cells from 0x28 to 0x31 will
I be XORed to obtain the XCCHKE checksum. Both checksums (24-bit wide) are exported on
2
C registers from 0x60 to 0x65. The checksum computation will start as soon as the BCGO
(for biquad RAM bank) or the XCGO bit (for MDRC/XOver coefficients) is set to 1. The checksum is computed at the processing sample rate if the IR bits equal “01” or “10”, otherwise the checksum is computed to half of the processing sample rate.
When BCCMP or XCCMP is set to ‘1’, the relative checksum (BQCHKE and XCCHKE) is continuously compared with BQCHKR and XCCHKR respectively. If the checksum matches its own reference value, the respective result bits (BCRES and XCRES) will be set to ‘0’.
The compare bits have no effect if the respective GO bit is not set.
In case of checksum errors (i.e. the internally computed didn’t match the reference), an automatic device reset action can be activated. This function is enabled when the BCAUTO or XCAUTO bit is set to ‘1’. The automatic reset bits have no effect if the respective compare bits are not set.
●
●
●
The recommended procedure for automatic reset activation is the following:
Download the set of coefficients (RAM locations 0x00…0x27)
Download the externally computed biquad checksum into registers
Enable the checksum of the biquad coefficients by setting the
BQCHKR
BCGO bit. The checksum will start to be automatically computed by the STA382BWS and its value exposed on registers BQCHECKE.
The checksum value is computed and updated.
● Enable the checksum comparison by setting the BCCMP bit. The internally computed checksum will start to be compared with the reference one and the result will be exposed on the BCRES bit. The following operation will be executed on each audio frame: if (( BQCHKE == BQCHKR ))
{
BC_RES = 0;// Checksum is ok, reset the error bit
}
Obsolete Product(s) - Obsolete Product(s)
Doc ID 022784 Rev 1 101/172
Register description: New Map STA382BWS
●
●
● else
{
BC_RES = 1;// Checksum error detected, set the error bit
}
Wait until the BCRES bit goes to 0, meaning that the checksum result bit has started to be updated and everything is ok. Time-out of this operation (e.g. >1 ms) will indicate checksum failure, and the MCU will handle this event
Enable automatic reset of the device in case of checksum error by setting the BCAUTO bit. The BCRES bit will then be automatically checked by the STA382BWS, on each audio frame, and a reset event will be triggered in case of checksum mismatch.
Periodically check the BC_RES status. A value of 1 indicates a checksum mismatch has occurred and, therefore, that the device went through a reset cycle.
The previous example is intended for biquad CRC bank calculation, but it can be easily extended to MDRC/XOver CRC computation.
6.38 MISC4 (address 0x7E)
D7
SMAP
1
D6 reserved
0
D5 reserved
0
Table 100.
Misc register 4
Bit R/W RST Name
D4 reserved
0
7
1
0
R/W
R/W
R/W
1
0
0
SMAP
WRA
CH12
D3 reserved
0
D2 reserved
0
D1
WRA
0
D0
CH12
0
Description
‘1’ = NEW MAP
‘0’ = STMAP
‘0’ = normal operations
‘1’ = enables the write-all procedure when using the
RAM coefficients direct access
‘0’ = normal operations
‘1’ = enables the RAM coefficients direct access
The STA382BWS allows direct access to the RAM coefficients bypassing the indirect access mechanism described in
Section 6.24: User-defined coefficient control registers
. Direct access is implemented as follows.
Obsolete Product(s) - Obsolete Product(s)
102/172 Doc ID 022784 Rev 1
STA382BWS Register description: New Map
Direct single-write procedure
1.
Set reg 0x7E bit 0 to 1 and bit 1 to 0 to enable the direct RAM access in single-write mode.
2. Write the coefficient value to the device using an I
2
C bus single-write operation as
.
Figure 28.
Coefficients direct access single-write operation
Direct multi-write procedure
1.
Set the reg 0x7E bit 0 to 1 and bit 1 to 1 to enable direct RAM access in multi-write mode.
2. Write the coefficients value to the device using an I
2
C bus multi-write operation as discribed in
. Please note that by using the multi-write procedure, it is possible to write the entire RAM contents at once.
Figure 29.
Coefficients direct access multiple-write operation
S Slave address w A Mem Addr A
Coeff_0(3) A Coeff_0(2) A Coeff_0(1) A Coeff_0(0) A
Coeff_1(3) A Coeff_1(2) A Coeff_1(1) A Coeff_1(0) A
Coeff_n(3) A Coeff_n(2) A Coeff_n(1) A Coeff_n(0) A
Direct single-read procedure
1.
Set reg 0x7E bit 0 to 1 and bit 1 to 0 to enable the direct RAM access in single-read mode.
2. Read the coefficient value from the device using an I
2
C bus single-read operation as
.
Figure 30.
Coefficients direct access single-read operation
Obsolete Product(s) - Obsolete Product(s)
Please be aware that the STA382BWS supports 24-bit coefficients, for this reason in the above figures Coeff_x(0) is always equal to 0x00 when either reading or writing. The multiwrite procedure embeds a wrap-around mechanism: when trying to write into a location exceeding the maximum coefficient address, the multi-write procedure will start from location 0x00.
Doc ID 022784 Rev 1 103/172
Register description: Sound Terminal compatibility
7
STA382BWS
Register description: Sound Terminal compatibility
To keep compatibility with previous Sound Terminal devices, the 0x7E bit D7 must be set to
0 after device turn-on and after any reset (via SW or via external pin).
Missing addresses are to be considered as reserved.
Table 101.
I
2
C registers summary
Addr Name D7 D6 D5 D4 D3 D2 D1 D0
0F
10
11
12
13
14
07
08
09
0A
0C
0E
00
01
02
CONFA
CONFB
CONFC
FDRB
C2IM
03
04
CONFD
CONFE
SME
SVE
05 CONFF EAPD
06 MUTE LOC LOC1
MVOL
CH1VOL
CH2VOL
CH3VOL
AUTO
C1CFG
C2CFG
C3CFG
TONE
L1AR
L1ATRT
L2AR
C1IM
ZDE
ZCE
PWDN
LOC0
XO3 XO2
C1OM1 C1OM0
C2OM1 C2OM0
C3OM1 C3OM0
TTC3 TTC2
L1A3
L1AT3
L2A3
L1A2
L1AT2
L2A2
DSCKE
CSZ3
ECLE
XO1
C1LS1
C2LS1
C3LS1
TTC1
L1A1
L1AT1
L2A1
IR1
SAIFB
CSZ2
BQL
PWMS
LDTE
BQB_ALL
IR0
SAI3
CSZ1
PSL
AME
BCLE
C3M
MCS2
SAI2
CSZ0
DSPB
NSBW
IDE
C2M
MCS1
SAI1
OCFG1
C1M
MCS0
SAI0
OCFG0
MMUTE
MVOL[7:0]
CH1VOL[7:0]
CH2VOL[7:0]
CH3VOL[7:0]
XO0 AMAM2 AMAM1 AMAM0 AMAME
C1LS0 C1BO C1VBP C1EQBP C1TCB
C2LS0
C3LS0
TTC0
L1A0
L1AT0
L2A0
C2BO
C3BO
BTC3
L1R3
L1RT3
L2R3
C2VBP C2EQBP C2TCB
C3VBP
BTC2 BTC1 BTC0
L1R2
L1RT2
L2R2
L1R1
L1RT1
L2R1
L1R0
L1RT0
L2R0
15 L2ATRT L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 L2RT1 L2RT0
16 CFADDR CFA5 CFA4 CFA3 CFA2 CFA1 CFA0
17 B1CF1 C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16 Obsolete Product(s) - Obsolete Product(s)
18 B1CF2 C1B15 C1B14 C1B13 C1B12 C1B11 C1B10 C1B9 C1B8
19
1A
B1CF3
B2CF1
C1B7
C2B23
C1B6
C2B22
C1B5
C2B21
C1B4
C2B20
C1B3
C2B19
C1B2
C2B18
C1B1
C2B17
C1B0
C2B16
1B
1C
1D
1E
B2CF2
B2CF3
A1CF1
A1CF2
C2B15
C2B7
C3B23
C3B15
C2B14
C2B6
C3B22
C3B14
C2B13
C2B5
C3B21
C3B13
C2B12
C2B4
C3B20
C3B12
C2B11
C2B3
C3B19
C3B11
C2B10
C2B2
C3B18
C3B10
C2B9
C2B1
C3B17
C3B9
C2B8
C2B0
C3B16
C3B8
104/172 Doc ID 022784 Rev 1
STA382BWS Register description: Sound Terminal compatibility
25
26
2B
2C
21
22
23
24
Table 101.
I
2
C registers summary (continued)
1F
20
2D
2E
2F
31
32
33
34
35
36
37
38
A1CF3
A2CF1
A2CF2
A2CF3
B0CF1
B0CF2
B0CF3
CFUD
FDRC1
FDRC2
C3B7
C4B23
C4B15
C4B7
C5B23
C5B15
C5B7
C3B6
C4B22
C4B14
C4B6
C5B22
C5B14
C5B6
C3B5
C4B21
C4B13
C4B5
C5B21
C5B13
C5B5
C3B4
C4B20
C4B12
C4B4
C5B20
C5B12
C5B4
C3B3
C4B19
C4B11
C4B3
C5B19
C5B11
C5B3
RA
C3B2
C4B18
C4B10
C4B2
C5B18
C5B10
C5B2
R1
STATUS
MTH2
MTH1
EQCFG
EATH1
FDRC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9
FDRC7 FDRC6 FDRC5 FDRC4 FDRC3 FDRC2 FDRC1
PLLUL FAULT
MTH[21:16]
MTH[15:8]
XOB
EATHEN1
ERTH1 ERTHEN1
EATH2 EATHEN2
ERTH2 ERTHEN2
CONFX
SVUP
SVDN
MDRCE PS48DB
SVUP_
EN
SVDN_
EN
XAR1
EATH1[6:0]
ERTH1[6:0]
EATH2[6:0]
ERTH2[6:0]
XAR2 BQ5
SVUP_RATE[4:0]
SVDN_RATE[4:0]
BQ6
C3B1
C4B17
C4B9
C4B1
C5B17
C5B9
C5B1
WA
3F EVOLRES VRES_EN
VRESTG
_EN
40 EVOLRES2
41 PLLFRAC1
EXVRES_CH3[1:0] EXVRES_CH2[1:0]
BQ7
EXVRES_CH1[1:0]
42 PLLFRAC0
43 PLLDIV PLL_DITH[1:0]
PLL_
DPD
PLL_
FCT
PLL_STB
C3B0
C4B16
C4B8
C4B0
C5B16
C5B8
C5B0
W1
FDRC8
FDRC0
EXVRES_MVOL[1:0]
PLL_FRAC[15:8]
PLL_FRAC[7:0]
PLL_NDIV[5:0]
PLL_
STBBYP
PLL_IDIV[3:0]
45 PLLCFG1
PLL_
DIRP
PLL_PWD PLL_BYP OSC_PD BOOST32K
46 PLLSTATE
47 SHOK
49 CXT41
4A
4B
CXT75
MISC1
CEXT_B4[1:0]
RPDNEN
CEXT_B3[1:0]
CEXT_B7[1:0]
BRIDGOFF
BYPSTATE PDSTATE OSCOK LOWCK
GNDSH VCCSH
CEXT_B2[1:0]
OUTSH
CEXT_B1[1:0]
CEXT_B6[1:0]
CPWMEN
CEXT_B5[1:0]
Doc ID 022784 Rev 1 105/172
Register description: Sound Terminal compatibility STA382BWS
Table 101.
I
2
C registers summary (continued)
4C MISC2 LPDP LPD LPDE
4D BPTH BPTH(5:0)
BP4A BP3B 4E BADPWM
4F BPTIM
50
51
ZCCFG0
ZCCFG1
BP4B
WTHH
52
53
54
55
ZCCFG2
ZCCFG3
ZCCFG4
HPCFG HPLN
58 F3XCFG1 F3XLNK
59 F3XCFG2
F3X_
FAULT
WTHL FINETH
MUTE
5A STCCFG0
5B STCCFG1
5E MTH0
LIM_
BYP
PNDLSL[2:0]
BP3A BP2B
BPTIM[7:0]
HSEL[1:0]
RMS_CH0[7:0]
RMS_CH0[15:8]
RMS_CH1[7:0]
RMS_CH1[15:8]
CPFEN
BP2A BP1B
ZMTH[2:0]
SHEN
BP1A
CPOK ABFAULT DCROK
F3X_SM_SLOPE[2:0]
STC_BYP STC_ENA
F3X_
MUTE
F3X_ENA
NP_
CRCRES
NP_CRC_
GO
STC_LNK BRC_EN
MTH[7:0]
5F CHPSINC CHPI INITCNT[3:0] CHPRD
60 BQCHKE0
61 BQCHKE1
62 BQCHKE2
63 XCCHKE0
64 XCCHKE1
65 XCCHKE2
66 BQCHKR0
67 BQCHKR1
68 BQCHKR2
69 XCCHKR0
BQ_CKE[7:0]
BQ_CKE[15:8]
BQ_CKE[23:16]
XC_CKE[7:0]
XC_CKE[15:8]
XC_CKE[23:16]
BQ_CKR[7:0]
BQ_CKR[15:8]
BQ_CKR[23:16]
XC_CKR[7:0]
6A XCCHKR1
6B XCCHKR2
XC_CKR[15:8]
Obsolete Product(s) - Obsolete Product(s)
6C CHKCTRL XCAUTO XCRES XCCMP XCGO BCAUTO BCRES BCCMP BCGO
SRESET 6E
7E
MISC3
MISC4 SMAP
106/172 Doc ID 022784 Rev 1
STA382BWS
7.1
Register description: Sound Terminal compatibility
Configuration register A (addr 0x00)
D7
FDRB
0
D6
Reserved
1
D5
Reserved
1
D4
IR1
0
D3
IR0
0
D2
MCS2
1
D1
MCS1
1
D0
MCS0
1
Table 102.
Master clock select
Bit R/W RST Name
0
1
2
R/W
R/W
R/W
1
1
1
MCS0
MCS1
MCS2
Description
Selects the ratio between the input I
2
S sampling frequency and the input clock.
●
●
●
The STA382BWS supports sampling rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,
176.4 kHz, and 192 kHz. Therefore the internal clock is:
32.768 MHz for 32 kHz
45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz
49.152 MHz for 48 kHz, 96 kHz, and 192 kHz
The external clock frequency provided to the XTI pin or BICKI pin (depending on MCS settings) must be a multiple of the input sampling frequency (f s
).
The relationship between the input clock (either XTI or BICKI) and the input sampling rate is determined by both the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internally. In
MCS 111 and 110 indicate that BICKI has to be used as the clock source, while XTI is used in all the other cases.
Table 103.
Input sampling rates
Input sampling rate fs (kHz)
IR MCS[2:0]
111 110 101 100 011 010 001 000
32, 44.1, 48 00 64*fs(*) NA 576 * fs 128 * fs 256 * fs 384 * fs 512 * fs 768 * fs
88.2, 96
176.4, 192
01 64*fs(*) 32*fs(*)
1X 64*fs(*) 32*fs(*)
NA
NA
64 * fs 128 * fs 192 * fs 256 * fs 384 * fs
32 * fs 64 * fs 96 * fs 128 * fs 192 * fs
Note: (*) Clock is BICKI
Doc ID 022784 Rev 1 107/172
Register description: Sound Terminal compatibility
7.1.2
STA382BWS
Interpolation ratio select
Table 104.
Internal interpolation ratio
Bit R/W RST Name
4:3 R/W 00 IR [1:0]
Description
Selects internal interpolation ratio based on input I
2
S sampling frequency
The STA382BWS has variable interpolation (oversampling) settings such that internal processing and FFX output rates remain consistent. The first processing block interpolates
by either 3 times (see Section 4.2
), 2 times or 1 time (pass-through) or provides a 2 times downsample. The oversampling ratio of this interpolation is determined by the IR bits.
Table 105.
IR bit settings as a function of the input sampling rate
Input sampling rate fs (kHz) IR 1st stage interpolation ratio
32
44.1
48
88.2
96
176.4
192
00
00
00
01
01
10
10
2-times oversampling
2-times oversampling
2-times oversampling
Pass-through
Pass-through
2-times downsampling
2-times downsampling
Table 106.
Fault-detect recovery bypass
Bit R/W RST Name
7 R/W 0 FDRB
Description
0: fault-detect recovery enabled
1: fault-detect recovery disabled
The on-chip STA382BWS power output block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition
(either overcurrent or thermal). When FAULT is asserted (set to 0), the power control block attempts a recovery from the fault by asserting the tri-state output (setting it to 0 which directs the power output block to begin recovery), holds it at 0 for period of time in the range Obsolete Product(s) - Obsolete Product(s) registers 0x2B-0x2C), then toggles it back to 1. This sequence is repeated as long as the fault indication exists. This feature is enabled by default, but can be bypassed by setting the
FDRB control bit to 1.
108/172 Doc ID 022784 Rev 1
STA382BWS
7.2
Register description: Sound Terminal compatibility
Configuration register B (addr 0x01)
D7
C2IM
1
D6
C1IM
0
D5
DSCKE
0
D4
SAIFB
0
D3
SAI3
0
D2
SAI2
0
D1
SAI1
0
D0
SAI0
0
7.2.2
7.2.3
The STA382BWS audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. The STA382BWS always acts as the slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and serial data 1 and 2 SDI12.
The SAI bits (D3 to D0) and the SAIFB bit (D4) are used to specify the serial data format.
The default serial data format is I
2
S, MSB-first. Available formats are shown in the tables that follow.
Serial audio input interface format
Table 107.
Serial audio input interface
Bit R/W RST Name
0
1
2
3
R/W
R/W
R/W
R/W
0
0
0
0
SAI0
SAI1
SAI2
SAI3
Description
Determines the interface format of the input serial digital audio interface
Serial data first bit
Table 108.
Serial data first bit
SAIFB
0
1
MSB-first
LSB-first
Format
Obsolete Product(s) - Obsolete Product(s)
Doc ID 022784 Rev 1 109/172
Register description: Sound Terminal compatibility
Table 109.
Support serial audio input formats for MSB-first (SAIFB = 0)
BICKI SAI [3:0] SAIFB Interface format
0000 0 I
2
S 15-bit data
32 * fs
0001
0000
0
0
Left/right-justified 16-bit data
I
2
S 16- to 23-bit data
48 * fs
64 * fs
0001
0010
0110
1010
1110
0000
0001
0010
0110
1010
1110
0
0
0
0
0
0
0
0
0
0
0
Left-justified 16- to 24-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
I
2
S 16- to 24-bit data
Left-justified 16- to 24-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
STA382BWS
Obsolete Product(s) - Obsolete Product(s)
110/172 Doc ID 022784 Rev 1
STA382BWS Register description: Sound Terminal compatibility
Table 110.
Supported serial audio input formats for LSB-first (SAIFB = 1)
BICKI SAI [3:0] SAIFB Interface format
1100 1 I
2
S 15-bit data
32 * fs
1110
0100
0100
1000
1100
0001
1
1
1
1
1
1
Left/right-justified 16-bit data
I
2
S 23-bit data
I
2
S 20-bit data
I
2
S 18-bit data
LSB first I
2
S 16-bit data
Left-justified 24-bit data
48 * fs
64 * fs
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1100
0001
0101
1001
1101
0010
0101
1001
1101
0010
0110
1010
1110
0000
0100
1000
0110
1010
1110
Left-justified 20-bit data
Left-justified 18-bit data
Left-justified 16-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
I
2
S 24-bit data
I
2
S 20-bit data
I
2
S 18-bit data
LSB first I
2
S 16-bit data
Left-justified 24-bit data
Left-justified 20-bit data
Left-justified 18-bit data
Left-justified 16-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data synchronous to the PLL output clock which means that:
● the frequency of PLL clock / frequency of LRCKI = N ±4 cycles, where N depends on the settings in
● the PLL must be locked.
If these two conditions are not met, and the IDE bit (reg 0x05 bit 2) is set to 1, the
STA382BWS will immediately mute the I
2
S PCM data out (provided to the processing block) and it will freeze any active processing task.
To avoid any audio side effects (like pop noise), it is strongly recommended to soft-mute any audio streams flowing into the STA382BWS data path before the desynchronization event
Doc ID 022784 Rev 1 111/172
Register description: Sound Terminal compatibility
Note:
7.2.4
STA382BWS happens. At the same time any processing related to the I
2
C configuration should be issued only after the serial audio interface and the internal PLL are synchronous again.
Any mute or volume change causes some delay in the completion of the I
2
C operation due to the soft volume feature. The soft volume phase change must be finished before any clock desynchronization.
Delay serial clock enable
Table 111.
Delay serial clock enable
Bit R/W RST Name
5 R/W 0 DSCKE
Description
0: No serial clock delay
1: Serial clock delay by 1 core clock cycle to tolerate anomalies in some I
2
S master devices
7.2.5 Channel input mapping
Table 112.
Channel input mapping
Bit R/W RST Name
6
7
R/W
R/W
0
1
C1IM
C2IM
Description
0: Processing channel 1 receives left I
2
S input
1: Processing channel 1 receives right I
2
S input
0: Processing channel 2 receives left I
2
S input
1: Processing channel 2 receives right I
2
S input
Each channel received via I
2
S can be mapped to any internal processing channel via the channel input mapping registers. This allows for flexibility in processing. The default settings of these registers map each I
2
S input channel to its corresponding processing channel.
Obsolete Product(s) - Obsolete Product(s)
112/172 Doc ID 022784 Rev 1
STA382BWS
7.3
7.3.1
Register description: Sound Terminal compatibility
Configuration register C (addr 0x02)
D7
Reserved
1
D6
Reserved
0
D5
CSZ3
0
D4
CSZ2
1
D3
CSZ1
0
D2
CSZ0
1
D1
Reserved
1
D0
Reserved
1
FFX compensating pulse size register
Table 113.
FFX compensating pulse size bits
Bit R/W RST Name
4
5
2
3
R/W
R/W
R/W
R/W
1
0
1
1
CSZ0
CSZ1
CSZ2
CSZ3
Description
When OM[1,0] = 11, this register determines the size of the FFX compensating pulse from 0 clock ticks to 15 clock periods.
Table 6:
Table 114.
Compensating pulse size
CSZ[3:0]
0000
0001
…
1111
Compensating pulse size
0 ns (0 ticks) compensating pulse size
20 ns (1 tick) clock period compensating pulse size
…
300 ns (15 ticks) clock period compensating pulse size
7.4 Configuration register D (addr 0x03)
D7
SME
0
D6
ZDE
0
D5
Reserved
0
D4
BQL
1
D3
PSL
1
D2
DSPB
0
D1
Reserved
0
D0
Reserved
0
Table 115.
DSP bypass
Bit R/W RST
R/W 0
Name
DSPB
Description
0: Normal operation
1: Bypass of biquad and bass/treble functions
Setting the DSPB bit bypasses the EQ function of the STA382BWS.
Doc ID 022784 Rev 1 113/172
Register description: Sound Terminal compatibility STA382BWS
7.4.3
7.4.4
Table 116.
Post-scale link
Bit R/W RST Name
3 R/W 1 PSL
Description
0: Each channel uses individual post-scale value
1: Each channel uses channel 1 post-scale value
Post-scale functionality can be used for power supply error correction. For multi-channel applications running off the same power supply, the post-scale values can be linked to the value of channel 1 for ease of use and in order to update the values faster.
Biquad coefficient link
Table 117.
Biquad coefficient link
Bit R/W RST Name
4 R/W 1 BQL
Description
0: Each channel uses coefficient values
1: Each channel uses channel 1 coefficient values
For ease of use, all channels can use the biquad coefficients loaded into the channel-1 coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to be performed once.
Zero-detect mute enable
Table 118.
Zero-detect mute enable
Bit R/W RST Name
6 R/W 0 ZDE
Description
Setting of 1 enables the automatic zero-detect mute
Setting of 0 disables the automatic zero-detect mute
Refer to
7.24: Enhanced zero-detect mute and input level measurement (address 0x50-
.
Table 119.
Submix mode enable
Bit R/W RST Name Description Obsolete Product(s) - Obsolete Product(s)
7 R/W 0 SME
0: Submix into left/right disabled
1: Submix into left/right enabled
7.5
114/172
Configuration register E (addr 0x04)
D7
SVE
1
D6
ZCE
0
D5
Reserved
0
D4
PWMS
0
D3
AME
0
Doc ID 022784 Rev 1
D2
NSBW
0
D1
Reserved
1
D0
Reserved
0
STA382BWS
7.5.1
Register description: Sound Terminal compatibility
Noise-shaper bandwidth selection
Table 120.
Noise-shaper bandwidth selection
Bit R/W RST Name
2 R/W 0 NSBW
1: Third order NS
0: Fourth order NS
Description
Table 121.
AM mode enable
Bit R/W RST Name
3 R/W 0 AME
Description
0: Normal FFX operation
1: AM reduction mode FFX operation
The STA382BWS features an FFX processing mode that minimizes the amount of noise generated in the frequency range of AM radio. This mode is intended for use when FFX is operating in a device with an active AM tuner. The SNR of the FFX processing is reduced to approximately 83 dB in this mode, which is still greater than the SNR of AM radio.
Table 122.
PWM speed mode
Bit R/W RST Name
4 R/W 0 PWMS
Description
0: Normal speed (384 kHz) all channels
1: Odd speed (341.3 kHz) all channels. Not suitable for binary BTL mode.
Table 123.
Zero-crossing enable
Bit R/W RST Name
6 R/W 0 ZCE
Description
‘1’: Volume adjustments only occur at digital zero-crossing
‘0’: Volume adjustments occur immediately
7.5.5 crossing, no clicks are audible.
Soft volume update enable
Table 124.
Soft volume update enable
Bit R/W RST Name
7 R/W 1 SVE
Description
1: Volume adjustments ramp according to SVR settings
0: Volume adjustments occur immediately
Doc ID 022784 Rev 1 115/172
Register description: Sound Terminal compatibility
7.6 Configuration register F (addr 0x05)
D7
EAPD
0
D6
PWDN
1
D5
ECLE
0
D4
LDTE
1
D3
BCLE
1
STA382BWS
D2
IDE
1
D1
OCFG1
0
D0
OCFG0
0
Table 125.
Output configuration
Bit R/W RST Name
0
1
R/W
R/W
0
0
OCFG0
OCFG1
Description
Selects the output configuration
Table 126.
Output configuration engine selection
OCFG[1:0] Output configuration PBTL enable
00
01
10
2-channel (full-bridge) power, 2-channel data-out:
1A/1B → 1A/1B
2A/2B → 2A/2B
LineOut1 → 3A/3B
LineOut2 → 4A/4B
Line Out configuration determined by LOC register
2(half-bridge).1(full-bridge) on-board power:
1A → 1A Binary 0 °
2A → 1B Binary 90°
3A/3B → 2A/2B Binary 45°
1A/B
→
3A/B Binary 0°
2A/B → 4A/B Binary 90°
2-channel (full-bridge) power, 1-channel FFX:
1A/1B → 1A/1B
2A/2B → 2A/2B
3A/3B
→
3A/3B
EAPDEXT and TWARNEXT active
No
No
No
1-channel mono-parallel:
3A → 1A/1B w/ C3BO 45°
11 Yes 3B → 2A/2B w/ C3BO 45°
1A/1B
→
3A/3B
Obsolete Product(s) - Obsolete Product(s)
Note: To the left of the arrow is the processing channel. When using channel output mapping, any of the three processing channel outputs can be used for any of the three inputs.
116/172 Doc ID 022784 Rev 1
STA382BWS Register description: Sound Terminal compatibility
Figure 31.
OCFG = 00 (default value)
H a lf
Ch a nnel 1
H a lf
H a lf
H a lf
Ch a nnel 2
OUT 3 A
OUT 3 B
LineO u t1
LineO u t2
Figure 32.
OCFG = 01
H a lf
H a lf
H a lf
H a lf
Ch a nnel 1
Ch a nnel 2
Ch a nnel 3
Figure 33.
OCFG = 10
H a lf
H a lf
H a lf
H a lf
OUT 3 A
Ch a nnel 1
Ch a nnel 2
Doc ID 022784 Rev 1 117/172
Register description: Sound Terminal compatibility
Figure 34.
OCFG = 11
H a lf
H a lf
H a lf
H a lf
Ch a nnel 3
STA382BWS
OUT 3 A
OUT 3 B
Ch a nnel 1
Ch a nnel 2
The STA382BWS can be configured to support different output configurations. For each
PWM output channel a PWM slot is defined. A PWM slot is always 1 / (8 * fs) seconds length. The PWM slot defines the maximum extension for the PWM rising and falling edge, that is, the rising edge as well as the falling edge cannot range outside the PWM slot boundaries.
Figure 35.
Output mapping scheme
TM mod u l a tor
FFX 3 A
FFX 3 B
FFX 4B
OUT 3 A
OUT 3 B Obsolete Product(s) - Obsolete Product(s)
OUT4A
OUT4B
118/172 Doc ID 022784 Rev 1
STA382BWS Register description: Sound Terminal compatibility
For each configuration the PWM signals from the digital driver are mapped in different ways to the power stage:
2.0 channels, two full-bridges (OCFG = 00)
●
●
●
●
●
●
●
●
●
●
●
●
FFX1A -> OUT1A
FFX1B -> OUT1B
FFX2A -> OUT2A
FFX2B -> OUT2B
FFX3A -> OUT3A
FFX3B -> OUT3B
FFX4A -> OUT4A
FFX4B -> OUT4B
FFX1A/1B configured as C1B0 (default: ternary)
FFX2A/2B configured as C2B0 (default: ternary)
FFX3A/3B configured as C3B0 (default: ternary) line out
FFX4A/4B configured as C4B0 (default: ternary) line out
On channel 3 line out (LOC bits = 00) the same data as channel 1 processing is sent. On channel 4 line out (LOC bits = 00) the same data as channel 2 processing is sent. In this configuration, neither volume control nor EQ has any effect on channels 3 and 4.
In this configuration the PWM slot phase is the following as shown in Figure 36 .
Figure 36.
2.0 channels (OCFG = 00) PWM slots
OUT 3 A
OUT 3 B
Obsolete Product(s) - Obsolete Product(s)
Doc ID 022784 Rev 1 119/172
Register description: Sound Terminal compatibility STA382BWS
2.1 channels, two half-bridges + one full-bridge (OCFG = 01)
●
●
●
●
●
●
●
●
●
●
●
●
FFX1A -> OUT1A
FFX2A -> OUT1B
FFX3A -> OUT2A
FFX3B -> OUT2B
FFX1A -> OUT3A
FFX1B -> OUT3B
FFX2A -> OUT4A
FFX2B -> OUT4B
FFX1A/1B configured as binary
FFX2A/2B configured as binary
FFX3A/3B configured as binary
FFX4A/4B is not used
In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT3/OUT4 channels channel 1 and channel 2 PWM are replicated.
In this configuration the PWM slot phase is the following as shown in Figure 37 .
Figure 37.
2.1 channels (OCFG = 01) PWM slots
OUT 3 A
OUT 3 B
OUT4A
OUT4B
Obsolete Product(s) - Obsolete Product(s)
120/172 Doc ID 022784 Rev 1
STA382BWS Register description: Sound Terminal compatibility
2.1 channels, two full-bridges + one external full-bridge (OCFG = 10)
●
●
●
●
●
●
●
●
●
●
●
●
FFX1A -> OUT1A
FFX1B -> OUT1B
FFX2A -> OUT2A
FFX2B -> OUT2B
FFX3A -> OUT3A
FFX3B -> OUT3B
EAPD -> OUT4A
TWARN -> OUT4B
FFX1A/1B configured as C1B0 (default: ternary)
FFX2A/2B configured as C2B0 (default: ternary)
FFX3A/3B configured as C3B0 (default: ternary)
FFX4A/4B is not used
In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT4 channel the external bridge control signals are muxed.
In this configuration the PWM slot phase is the following as shown in Figure 38 .
Figure 38.
2.1 channels (OCFG = 10) PWM slots
OUT 3 A
OUT 3 B
Obsolete Product(s) - Obsolete Product(s)
Doc ID 022784 Rev 1 121/172
Register description: Sound Terminal compatibility STA382BWS
7.6.3
7.6.4
7.6.5
Table 127.
Invalid input detect mute enable
Bit
2
R/W RST
R/W 1
Name
IDE
Description
Setting of 1 enables the automatic invalid input detect mute
Setting the IDE bit enables this function, which looks at the input I
2
S data and automatically mutes if the signals are perceived as invalid.
Binary output mode clock loss detection
Table 128.
Binary output mode clock loss detection
Bit R/W RST Name Description
3 R/W 1 BCLE Binary output mode clock loss detection enable
This bit detects loss of input MCLK in binary mode and will output 50% duty cycle.
LRCK double trigger protection
Table 129.
LRCK double trigger protection
Bit R/W RST
4 R/W 1
Name
LDTE
Description
LRCLK double trigger protection enable
This bit actively prevents double triggering of LRCLK.
Auto EAPD on clock loss
Table 130.
Auto EAPD on clock loss
Bit R/W RST Name
5 R/W 0 ECLE Auto EAPD on clock loss
Description
When active, this bit issues a device power-down signal (EAPD) on clock loss detection.
122/172
Bit
7
R/W
R/W
RST
1
Name
PWDN
Description
0: IC power-down low-power condition
1: IC normal operation
The PWDN register is used to place the IC in a low-power state. When PWDN is written as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted to power down the power stage, then the master clock to all internal hardware except the I
2
C block is gated. This places the IC in a very low power consumption state.
Doc ID 022784 Rev 1
STA382BWS Register description: Sound Terminal compatibility
7.7
Table 132.
External amplifier power-down
Bit R/W RST Name
7 R/W 0 EAPD
Description
0: External power stage power-down active
1: Normal operation
The EAPD register directly disables/enables the internal power circuitry.
When EAPD = 0, the internal power section is placed in a low-power state (disabled). This register also controls the EAPD/FFX4B output pin when OCFG = 10.
Volume control registers (addr 0x06 - 0x0A)
D7
LOC1
0
D6
LOC0
0
D5
Reserved
0
D4
BQBALL
0
D3
C3M
0
D2
C2M
0
Table 133.
Line output configuration
LOC[1:0] Line output configuration
00
01
10
11
Line output fixed - no volume, no EQ
Line output variable - CH3 volume effects line output, no EQ
Line output variable with EQ - CH3 volume effects line output
Reserved
D1
C1M
0
D0
MMUTE
0
Line output is only active when OCFG = 00. In this case LOC determines the line output configuration. The source of the line output is always channel 1 and 2 inputs.
Bit R/W RST Name Description
Global biquad bypass
4 R/W 0 BQBALL 0: Biquad filters active
1: All the biquad filters are bypassed (pass-through) Obsolete Product(s) - Obsolete Product(s)
Doc ID 022784 Rev 1 123/172
Register description: Sound Terminal compatibility
Table 134.
Mute configuration
Bit R/W RST Name
3
2
1
0
R/W
R/W
R/W
R/W
0
0
0
0
C3M
C2M
C1M
MMUTE
STA382BWS
Description
Channel 3 mute
0 - No mute condition. It is possible to set the channel volume
1 - Channel 3 in hardware mute
Channel 2 mute
0 - No mute condition. It is possible to set the channel volume
1 - Channel 2 in hardware mute
Channel 1 mute
0 - No mute condition. It is possible to set the channel volume
1 - Channel 1 in hardware mute
Master mute
0 - Normal operation
1 - All channels are in mute condition
7.7.2
7.7.3
7.7.4
Master volume register
D7 D6 D5 D4
MVOL[7:0]
D3
1 1
D2 D1 D0
1 1
Channel 1 volume
D7 D6
1 1 1 1
D5 D4
CH1VOL[7:0]
D3
0 0
D2 D1 D0
0 1
Channel 2 volume
D7 D6
1 0 0 0
0 1
D5
1
D4
CH2VOL[7:0]
D3
0 0
D2
0
D1
0
D0
0
Channel 3 / line output volume
D7 D6 D5 D4
CH3VOL[7:0]
D3
0 0
D2 D1 D0
0 1 1 0 0 0
The volume structure of the STA382BWS consists of individual volume registers for each channel and a master volume register that provides an offset to each channel’s volume setting. The individual channel volumes are adjustable in 0.5 dB steps from +48 dB to
-80 dB.
124/172 Doc ID 022784 Rev 1
STA382BWS Register description: Sound Terminal compatibility
As an example if CH3VOL = 0x00 or +48 dB and MVOL = 0x18 or -12 dB, then the total gain for channel 3 = +36 dB.
The master mute, when set to 1, mutes all channels at once, whereas the individual channel mute (CxM) mutes only that channel. Both the master mute and the channel mutes provide a “soft mute” with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (approximately 96 kHz).
A “hard (instantaneous) mute” can be obtained by programming a value of 0xFF (255) to any channel volume register or the master volume register. When volume offsets are provided via the master volume register, any channel whose total volume is less than -80 dB is muted.
All changes in volume take place at zero-crossings when ZCE = 1 ( Configuration register E
(addr 0x04) ) on a per-channel basis as this creates the smoothest possible volume
transitions. When ZCE = 0, volume updates occur immediately.
Table 135.
Master volume offset as a function of MVOL[7:0]
MVOL[7:0] Volume offset from channel value
00000000 (0x00)
00000001 (0x01)
00000010 (0x02)
…
01001100 (0x4C)
…
11111110 (0xFE)
11111111 (0xFF)
0 dB
-0.5 dB
-1 dB
…
-38 dB
…
-127.5 dB
Hard master mute
Table 136.
Channel volume as a function of CxVOL[7:0]
CxVOL[7:0] Volume
00000000 (0x00)
00000001 (0x01)
00000010 (0x02)
…
01011111 (0x5F)
01100000 (0x60)
+48 dB
+47.5 dB
+47 dB
…
+0.5 dB
0 dB
01100001 (0x61)
…
-0.5 dB
…
11010111 (0xD7)
11011000 (0xD8)
-59.5 dB Obsolete Product(s) - Obsolete Product(s)
11011001 (0xD9) -61 dB
11011010 (0xDA) -62 dB
…
11101100 (0xEC)
11101101 (0xED)
…
11111111 (0xFF)
…
-80 dB
Hard channel mute
…
Hard channel mute
Doc ID 022784 Rev 1 125/172
Register description: Sound Terminal compatibility
7.8 Audio preset registers (addr 0x0C)
D7
XO3
0
D6
XO2
0
D5
XO1
0
STA382BWS
D4
XO0
0
D3
AMAM2
0
D2
AMAM1
0
D1
AMAM0
0
D0
AMAME
0
Table 137.
AM interference frequency switching bits
Bit R/W RST Name
0 R/W 0 AMAME
Description
Audio preset AM enable
0: switching frequency determined by PWMS setting
1: switching frequency determined by AMAM settings
Table 138.
Audio preset AM switching frequency selection
AMAM[2:0] 48 kHz/96 kHz input fs 44.1 kHz/88.2 kHz input fs
000
001
010
011
100
101
110
0.535 MHz - 0.720 MHz
0.721 MHz - 0.900 MHz
0.901 MHz - 1.100 MHz
1.101 MHz - 1.300 MHz
1.301 MHz - 1.480 MHz
1.481 MHz - 1.600 MHz
1.601 MHz - 1.700 MHz
0.535 MHz - 0.670 MHz
0.671 MHz - 0.800 MHz
0.801 MHz - 1.000 MHz
1.001 MHz - 1.180 MHz
1.181 MHz - 1.340 MHz
1.341 MHz - 1.500 MHz
1.501 MHz - 1.700 MHz
Table 139.
Bass management crossover
Bit R/W RST Name Description
4 R/W 0 XO0
5 Obsolete Product(s) - Obsolete Product(s)
6
R/W
R/W
0
0
XO1
XO2
Selects the bass management crossover frequency.
A 1 st
-order high-pass filter (channels 1 and 2) or a
2 nd
-order low-pass filter (channel 3) at the selected frequency is performed.
7 R/W 0 XO3
126/172 Doc ID 022784 Rev 1
STA382BWS Register description: Sound Terminal compatibility
Table 140.
Bass management crossover frequency
XO[3:0] Crossover frequency
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
200 Hz
220 Hz
240 Hz
260 Hz
280 Hz
300 Hz
320 Hz
340 Hz
360 Hz
User-defined
80 Hz
100 Hz
120 Hz
140 Hz
160 Hz
180 Hz
D7
C1OM1
0
D6
C1OM0
0
D5
C1LS1
0
D4
C1LS0
0
D3
C1BO
0
D2
C1VPB
0
D1
C1EQBP
0
D0
C1TCB
0
D7
C2OM1
0
D6
C2OM0
1
D5
C2LS1
0
D4
C2LS0
0
D3
C2BO
0
D2
C2VPB
0
D1
C2EQBP
0
D0
C2TCB
0
D7 D6 D5 D4 D3 D2 D1 D0
C3OM1 C3OM0 C3LS1 C3LS0 C3BO C3VPB Reserved Reserved
1 0 Obsolete Product(s) - Obsolete Product(s)
7.9.1 Tone control bypass
0 0 0 0 0 0
Tone control (bass/treble) can be bypassed on a per-channel basis for channels 1 and 2.
Table 141.
Tone control bypass
CxTCB
0
1
Mode
Perform tone control on channel x - normal operation
Bypass tone control on channel x
Doc ID 022784 Rev 1 127/172
Register description: Sound Terminal compatibility STA382BWS
EQ control can be bypassed on a per-channel basis for channels 1 and 2. If EQ control is bypassed on a given channel, the prescale and all filters (biquads, bass, treble in any combination) are bypassed for that channel.
Table 142.
EQ bypass
CxEQBP
0
1
Mode
Perform EQ on channel x - normal operation
Bypass EQ on channel x
7.9.4
Each channel contains an individual channel volume bypass. If a particular channel has volume bypassed via the CxVBP = 1 register, then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel.
Table 143.
Volume bypass register
CxVBP
0
1
Normal volume operations
Volume is bypassed
Mode
Binary output enable registers
Each individual channel output can be set to output a binary PWM stream. In this mode output A of a channel is considered the positive output and output B is the negative inverse.
Table 144.
Binary output enable registers
CxBO
0
1
Mode
FFX 3-state output - normal operation
Binary output
Limiter selection can be made on a per-channel basis according to the channel limiter select
Obsolete Product(s) - Obsolete Product(s)
Table 145.
Channel limiter mapping as a function of CxLS bits
CxLS[1:0] Channel limiter mapping
00
01
10
Channel has limiting disabled
Channel is mapped to limiter #1
Channel is mapped to limiter #2
128/172 Doc ID 022784 Rev 1
STA382BWS Register description: Sound Terminal compatibility
Output mapping can be performed on a per-channel basis according to the CxOM channel output mapping bits. Each input into the output configuration engine can receive data from any of the three processing channel outputs.
.
Table 146.
Channel output mapping as a function of CxOM bits
CxOM[1:0] Channel x output source from
00
01
10
Channel1
Channel 2
Channel 3
7.10 Tone control register (addr 0x11)
D7
TTC3
0
D6
TTC2
1
D5
TTC1
1
D4
TTC0
1
D3
BTC3
0
D2
BTC2
1
D1
BTC1
1
D0
BTC0
1
Table 147.
Tone control boost/cut as a function of BTC and TTC bits
BTC[3:0]/TTC[3:0] Boost/cut
0000
0001
…
0111
0110
0111
1000
1001
-12 dB
-12 dB
…
-4 dB
-2 dB
0 dB
+2 dB
+4 dB
… …
1101 +12 dB
1110 +12 dB Obsolete Product(s) - Obsolete Product(s)
1111 +12 dB
Doc ID 022784 Rev 1 129/172
Register description: Sound Terminal compatibility STA382BWS
7.11 Dynamic control registers (addr 0x12 - 0x15)
7.11.1 Limiter 1 attack/release rate
D7
L1A3
0
D6
L1A2
1
D5
L1A1
1
D4
L1A0
0
D3
L1R3
1
D2
L1R2
0
7.11.2 Limiter 1 attack/release threshold
D7
L1AT3
0
D6
L1AT2
1
D5
L1AT1
1
D4
L1AT0
0
7.11.3 Limiter 2 attack/release rate
D7
L2A3
0
D6
L2A2
1
D5
L2A1
1
D4
L2A0
0
D3
L1RT3
1
D3
L2R3
1
D2
L1RT2
0
D2
L2R2
0
D1
L1R1
1
D1
L1RT1
0
D0
L1R0
0
D0
L1RT0
1
D1
L2R1
1
D0
L2R0
0
7.11.4 Limiter 2 attack/release threshold
D7
L2AT3
0
D6
L2AT2
1
D5
L2AT1
1
D4
L2AT0
0
D3
L2RT3
1
D2
L2RT2
0
D1
L2RT1
0
D0
L2RT0
1
The STA382BWS includes two independent limiter blocks (not to be mistaken with the
STCompressor
TM
, for further details about this feature please refer to Section 4.2
). The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anticlipping mode or to actively reduce the dynamic range for a better listening environment such as a nighttime listening mode which is often needed for DVDs. The two modes are selected via the DRC bit in
. Each channel can be mapped to either limiter or not mapped, meaning that the channel will clip when 0 dBfs is exceeded. Each limiter looks at the present value of each channel that is mapped to it, selects the maximum absolute value of all these channels, performs the limiting algorithm on that value, and then, if needed, adjusts the gain of the mapped channels in unison.
The limiter attack thresholds are determined by the LxAT registers if the EATHx[7] bits are
Obsolete Product(s) - Obsolete Product(s) anticlipping mode to set this to 0 dBfs, which corresponds to the maximum unclipped output power of an FFX amplifier. Since gain can be added digitally within the STA382BWS, it is possible to exceed 0 dBfs or any other LxAT setting. When this occurs, the limiter, when active, automatically starts reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. Gain reduction occurs on a peak-detect algorithm. Setting the EATHx[7] bits to 1 selects the anticlipping mode.
The limiter release thresholds are determined by the LxRT registers if the ERTHx[7] bits are set to 0, else the thresholds are determined by ERTHx[6:0]. Settings the ERTHx[7] bits to 1
130/172 Doc ID 022784 Rev 1
STA382BWS Register description: Sound Terminal compatibility automatically selects the anticlipping mode. The release of the limiter, when the gain is again increased, is dependent on an RMS-detect algorithm. The output of the volume/limiter block is passed through an RMS filter. The output of this filter is compared to the release threshold, determined by the release threshold register. When the RMS filter output falls below the release threshold, the gain is again increased at a rate dependent upon the release rate register. The gain can never be increased past its set value and, therefore, the release only occurs if the limiter has already reduced the gain. The release threshold value can be used to set what is effectively a minimum dynamic range, this is helpful as overlimiting can reduce the dynamic range to virtually zero and cause program material to sound “lifeless”.
In AC mode, the attack and release thresholds are set relative to full-scale. In DRC mode, the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter, and the release threshold is set relative to the maximum volume setting plus the attack threshold.
Obsolete Product(s) - Obsolete Product(s)
Doc ID 022784 Rev 1 131/172
STA382BWS Register description: Sound Terminal compatibility
Figure 39.
Basic limiter and volume flow diagram
Limiter
RM S
G a in / Vo l u me
+
In p u t
Sa t u r a tio n
O u tp u t
G a in Atten ua tio n
Table 148.
Limiter attack rate as a function of LxA bits
LxA[3:0] Attack rate dB/ms
Table 149.
Limiter release rate as a function of LxR bits
LxR[3:0] Release rate dB/ms
1000
1001
1010
1011
1100
1101
0000
0001
0010
0011
0100
0101
0110
0111
0.1504
0.1123
0.0902
0.0752
0.0645
0.0564
3.1584
2.7072
2.2560
1.8048
1.3536
0.9024
0.4512
0.2256
Fast
1000
1001
1010
1011
1100
1101
0000
0001
0010
0011
0100
0101
0110
0111
0.0198
0.0172
0.0147
0.0137
0.0134
0.0117
0.5116
0.1370
0.0744
0.0499
0.0360
0.0299
0.0264
0.0208
Fast
1110
1111
0.0501
0.0451
Slow
1110
1111
0.0110
0.0104
132/172 Doc ID 022784 Rev 1
STA382BWS Register description: Sound Terminal compatibility
Anticlipping mode
LxAT[3:0]
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
Table 150.
Limiter attack threshold as a function of LxAT bits
(AC mode)
AC (dB relative to fs) LxRT[3:0]
+3
+4
+5
-12
-10
-8
0000
0001
0010
-6
-4
0011
0100
-2 0101
0 0110
+2 0111
1000
1001
1010
+6
+7
+8
1011
1100
1101
+9 1110
+10 1111
Table 151.
Limiter release threshold as a function of LxRT bits
(AC mode)
AC (dB relative to fs)
∞
-29 dB
-20 dB
-16 dB
-14 dB
-12 dB
-10 dB
-8 dB
-7 dB
-6 dB
-5 dB
-4 dB
-3 dB
-2 dB
-1 dB
-0 dB
Obsolete Product(s) - Obsolete Product(s)
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Register description: Sound Terminal compatibility
Dynamic range compression mode
Table 152.
Limiter attack threshold as a function of LxAT bits (DRC mode)
LxAT[3:0] DRC (dB relative to volume)
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
-16
-15
-14
-13
-12
-10
-7
-4
-23
-21
-19
-17
-31
-29
-27
-25
STA382BWS
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
Table 153.
Limiter release threshold as a function of LxRT bits
(DRC mode)
LxRT[3:0]
DRC (db relative to volume +
LxAT)
∞
-38 dB
-36 dB
-33 dB
-31 dB
-30 dB
-28 dB
-26 dB
-24 dB
-22 dB
-20 dB
-18 dB
-15 dB
-12 dB
-9 dB
-6 dB
7.11.5 Limiter 1 extended attack threshold (addr 0x32)
D7
EATHEN1
0
D6
EATH1[6]
0
D5
EATH1[5]
1
D4
EATH1[4]
1
D3
EATH1[3]
0
D2
EATH1[2]
0
The extended attack threshold value is determined as follows: attack threshold = -12 + EATH1 / 4
To enable this feature, the EATHEN1 bit must be set to 1.
D1
EATH1[1]
0
D0
EATH1[0]
0
134/172
D7
ERTHEN1
0
D6
ERTH1[6]
0
D5
ERTH1[5]
1
D4
ERTH1[4]
1
D3
ERTH1[3]
0
D2
ERTH1[2]
0
The extended release threshold value is determined as follows: release threshold = -12 + ERTH1 / 4
To enable this feature, the ERTHEN2 bit must be set to 1.
D1
ERTH1[1]
0
D0
ERTH1[0]
0
Doc ID 022784 Rev 1
STA382BWS Register description: Sound Terminal compatibility
7.11.7 Limiter 2 extended attack threshold (addr 0x34)
D7
EATHEN2
0
D6
EATH2[6]
0
D5
EATH2[5]
1
D4
EATH2[4]
1
D3
EATH2[3]
0
D2
EATH2[2]
0
The extended attack threshold value is determined as follows: attack threshold = -12 + EATH2 / 4
To enable this feature, the EATHEN2 bit must be set to 1.
D1
EATH2[1]
0
7.11.8 Limiter 2 extended release threshold (addr 0x35)
Note:
D7
ERTHEN2
0
D6
ERTH2[6]
0
D5
ERTH2[5]
1
D4
ERTH2[4]
1
D3
ERTH2[3]
0
D2
ERTH2[2]
0
The extended release threshold value is determined as follows: release threshold = -12 + ERTH2 / 4
To enable this feature, the ERTHEN2 bit must be set to 1.
Attack/release threshold step is 0.125 dB in the range -12 dB to 0 dB.
D1
ERTH2[1]
0
D0
EATH2[0]
0
D0
ERTH2[0]
0
7.12 User-defined coefficient control registers (addr 0x16 - 0x26)
7.12.1 Coefficient address register
D7
Reserved
0
D6
Reserved
0
D5
CFA5
0
D4
CFA4
0
D3
CFA3
0
D2
CFA2
0
D1
CFA1
0
D0
CFA0
0
7.12.2 Coefficient register bits 23:16
D7
C1B23
0
D6
C1B22
0
D5
C1B21
0
D4
C1B20
0
D3
C1B19
0
D2
C1B18
0
D1
C1B17
0
D0
C1B16
0
7.12.3 Coefficient data register bits 15:8
Obsolete Product(s) - Obsolete Product(s)
D7 D6 D5 D4 D3 D2 D1 D0
C1B15
0
C1B14
0
C1B13
0
C1B12
0
C1B11
0
C1B10
0
C1B9
0
C1B8
0
7.12.4 Coefficient data register bits 7:0
D7
C1B7
0
D6
C1B6
0
D5
C1B5
0
D4
C1B4
0
D3
C1B3
0
D2
C1B2
0
D1
C1B1
0
D0
C1B0
0
Doc ID 022784 Rev 1 135/172
Register description: Sound Terminal compatibility
7.12.5 Coefficient register bits 23:16
D7
C2B23
0
D6
C2B22
0
D5
C2B21
0
D4
C2B20
0
D3
C2B19
0
7.12.6 Coefficient data register bits 15:8
D7
C2B15
0
D6
C2B14
0
D5
C2B13
0
D4
C2B12
0
D3
C2B11
0
7.12.7 Coefficient data register bits 7:0
D7
C2B7
0
D6
C2B6
0
D5
C2B5
0
D4
C2B4
0
D3
C2B3
0
7.12.8 Coefficient register bits 23:16
D7
C1B23
0
D6
C1B22
0
D5
C1B21
0
D4
C1B20
0
D3
C1B19
0
7.12.9 Coefficient data register bits 15:8
D7
C3B15
0
D6
C3B14
0
D5
C3B13
0
D4
C3B12
0
D3
C3B11
0
D2
C2B18
0
D1
C2B17
0
D0
C2B16
0
D2
C2B10
0
D2
C2B2
0
D2
C1B18
0
D1
C1B17
0
D0
C1B16
0
D2
C3B10
0
D1
C2B9
0
D1
C2B1
0
D1
C3B9
0
STA382BWS
D0
C2B8
0
D0
C2B0
0
D0
C3B8
0
D7
C3B7
0
D6
C3B6
0
D5
C3B5
0
D4
C3B4
0
D3
C3B3
0
D2
C3B2
0
D1
C3B1
0
D0
C3B0
0
Obsolete Product(s) - Obsolete Product(s)
D7 D6 D5 D4 D3 D2 D1 D0
C4B23
0
C4B22
0
C4B21
0
C4B20
0
C4B19
0
C4B18
0
C4B17
0
C4B16
0
136/172 Doc ID 022784 Rev 1
STA382BWS Register description: Sound Terminal compatibility
D7
C4B15
0
D6
C4B14
0
D5
C4B13
0
D4
C4B12
0
D3
C4B11
0
D2
C4B10
0
D1
C4B9
0
D0
C4B8
0
D7
C4B7
0
D6
C4B6
0
D5
C4B5
0
D4
C4B4
0
D3
C4B3
0
D2
C4B2
0
D1
C4B1
0
D0
C4B0
0
D7
C5B23
0
D6
C5B22
0
D5
C5B21
0
D4
C5B20
0
D3
C5B19
0
D2
C5B18
0
D1
C5B17
0
D0
C5B16
0
D7
C5B15
0
D6
C5B14
0
D5
C5B13
0
D4
C5B12
0
D3
C5B11
0
D2
C5B10
0
D1
C5B9
0
D0
C5B8
0
D7
C5B7
0
D6
C5B6
0
D5
C5B5
0
D4
C5B4
0
D3
C5B3
0
D2
C5B2
0
D1
C5B1
0
D0
C5B0
0
D7 D6
Reserved
0
D5 D4 D3
RA
0
D2
R1
0
D1
WA
0
D0
W1
0
Coefficients for user-defined EQ, mixing, scaling, bass management and STCompressor
TM
) are handled internally in the STA382BWS via RAM. Access to this RAM is
Obsolete Product(s) - Obsolete Product(s) to this function. One contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write/read of the coefficient(s) to/from RAM.
Note: The read and write operation on RAM coefficients works only if LRCKI (pin 29) is switching.
Doc ID 022784 Rev 1 137/172
Register description: Sound Terminal compatibility STA382BWS
Reading a coefficient from RAM
1.
Write 6 bits of the address to I
2
C register 0x16.
2. Write 1 to the R1 bit in I
2
C address 0x26.
3. Read the top 8 bits of the coefficient in I
2
C address 0x17.
4. Read the middle 8 bits of the coefficient in I
2
C address 0x18.
5. Read the bottom 8 bits of the coefficient in I
2
C address 0x19.
Reading a set of coefficients from RAM
1.
Write 6 bits of the address to I
2
C register 0x16.
2. Write 1 to the RA bit in I
2
C address 0x26.
3. Read the top 8 bits of the coefficient in I
2
C address 0x17.
4. Read the middle 8 bits of the coefficient in I
2
C address 0x18.
5. Read the bottom 8 bits of the coefficient in I
2
C address 0x19.
6. Read the top 8 bits of coefficient b2 in I
2
C address 0x1A.
7. Read the middle 8 bits of coefficient b2 in I
2
C address 0x1B.
8. Read the bottom 8 bits of coefficient b2 in I
2
C address 0x1C.
9. Read the top 8 bits of coefficient a1 in I
2
C address 0x1D.
10. Read the middle 8 bits of coefficient a1 in I
2
C address 0x1E.
11. Read the bottom 8 bits of coefficient a1 in I
2
C address 0x1F.
12. Read the top 8 bits of coefficient a2 in I
2
C address 0x20.
13. Read the middle 8 bits of coefficient a2 in I
2
C address 0x21.
14. Read the bottom 8 bits of coefficient a2 in I
2
C address 0x22.
15. Read the top 8 bits of coefficient b0 in I
2
C address 0x23.
16. Read the middle 8 bits of coefficient b0 in I
2
C address 0x24.
17. Read the bottom 8 bits of coefficient b0 in I
2
C address 0x25.
Writing a single coefficient to RAM
1.
Write 6 bits of the address to I
2
C register 0x16.
2. Write the top 8 bits of the coefficient in I
2
C address 0x17.
3. Write the middle 8 bits of the coefficient in I
2
C address 0x18.
4. Write the bottom 8 bits of the coefficient in I
2
C address 0x19.
5. Write 1 to the W1 bit in I
2
C address 0x26.
Obsolete Product(s) - Obsolete Product(s)
138/172 Doc ID 022784 Rev 1
STA382BWS Register description: Sound Terminal compatibility
Writing a set of coefficients to RAM
1.
Write 6 bits of the starting address to I
2
C register 0x16.
2. Write the top 8 bits of coefficient b1 in I
2
C address 0x17.
3. Write the middle 8 bits of coefficient b1 in I
2
C address 0x18.
4. Write the bottom 8 bits of coefficient b1 in I
2
C address 0x19.
5. Write the top 8 bits of coefficient b2 in I
2
C address 0x1A.
6. Write the middle 8 bits of coefficient b2 in I
2
C address 0x1B.
7. Write the bottom 8 bits of coefficient b2 in I
2
C address 0x1C.
8. Write the top 8 bits of coefficient a1 in I
2
C address 0x1D.
9. Write the middle 8 bits of coefficient a1 in I
2
C address 0x1E.
10. Write the bottom 8 bits of coefficient a1 in I
2
C address 0x1F.
11. Write the top 8 bits of coefficient a2 in I
2
C address 0x20.
12. Write the middle 8 bits of coefficient a2 in I
2
C address 0x21.
13. Write the bottom 8 bits of coefficient a2 in I
2
C address 0x22.
14. Write the top 8 bits of coefficient b0 in I
2
C address 0x23.
15. Write the middle 8 bits of coefficient b0 in I
2
C address 0x24.
16. Write the bottom 8 bits of coefficient b0 in I
2
C address 0x25.
17. Write 1 to the WA bit in I
2
C address 0x26.
The mechanism for writing a set of coefficients to RAM provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side effects. When using this technique, the 6-bit address specifies the address of the biquad b1 coefficient (for example, 0, 5, 10, 20, 35 decimal), and the
STA382BWS generates the RAM addresses as offsets from this base value to write the complete set of coefficient data.
Obsolete Product(s) - Obsolete Product(s)
Doc ID 022784 Rev 1 139/172
Register description: Sound Terminal compatibility STA382BWS
The STA382BWS can be programmed for four EQ filters (biquads) per each of the two input channels. The biquads use the following equation:
Y[n] = 2 * (b
0
/ 2) * X[n] + 2 * (b
1
/ 2) * X[n-1] + b
2
* X[n-2] - 2 * (a
1
/ 2) * Y[n-1] - a
2
* Y[n-2]
= b
0
* X[n] + b
1
* X[n-1] + b
2
* X[n-2] - a
1
* Y[n-1] - a
2
* Y[n-2] where Y[n] represents the output and X[n] represents the input. Multipliers are 24-bit signed fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF
(0.9999998808).
Coefficients stored in the user-defined coefficient RAM are referenced in the following manner:
CxHy0 = b
1
/ 2
CxHy1 = b
2
CxHy2 = -a
1
/ 2
CxHy3 = -a
2
CxHy4 = b
0
/ 2 where x represents the channel and y the biquad number. For example, C2H41 is the b
2 coefficient in the fourth biquad for channel 2.
Additionally, the STA382BWS can be programmed for a high-pass filter (processing channels 1 and 2) and a low-pass filter (processing channel 3) to be used for bass management crossover when the XO setting is 000 (user-defined). Both of these filters, when defined by the user (rather than using the preset crossover filters), are second order filters that use the biquad equation given above. They are loaded into the C12H0-4 and
C3Hy0-4 areas of RAM noted in
.
Channel 1 and channel 2 biquads use by default the extended coefficient range (-4, +4);
Xover filters use only the standard coefficients range (-1, +1).
By default, all user-defined filters are pass-through where all coefficients are set to 0, except the channel 1 and 2 b
0
/2 coefficient which is set to 0x100000 (representing 0.5) and xover b
0
/2 coefficient which is set to 0x400000 (representing 0.5).
7.12.19 Pre-scale
The STA382BWS provides a multiplication for each input channel for the purpose of scaling the input prior to EQ. This pre-EQ scaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiplication is loaded into RAM using the same I
2
C registers as the biquad coefficients and the bass management. All channels can use the channel-1 pre-scale factor Obsolete Product(s) - Obsolete Product(s)
7.12.20 Post-scale
The STA382BWS provides one additional multiplication after the last interpolation stage and the distortion compensation on each channel. This post-scaling is accomplished by using a
24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiplication is loaded into RAM using the same I
2
C registers as the biquad coefficients and the bass management. This post-scale factor can be used in conjunction with an ADC-equipped microcontroller to perform power-supply error correction.
All channels can use the channel-1 post-scale factor by setting the post-scale link bit. By
140/172 Doc ID 022784 Rev 1
STA382BWS Register description: Sound Terminal compatibility default, all post-scale factors are set to 0x7FFFFF. When line output is being used, channel-3 post-scale will affect both channels 3 and 4.
Table 154.
RAM block for biquads, mixing, scaling and bass management
Index (decimal) Index (hex) Description Coefficient Default
…
39
40
41
42
19
20
21
3
4
5
…
0
1
2
47
48
49
50
51
43
44
45
46
52
53
54
55
0x13
0x14
0x15
…
0x27
0x28
0x29
0x2A
0x00
0x01
0x02
0x03
0x04
0x05
…
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
Channel 1 - Biquad 1
Channel 1 - Biquad 2
…
Channel 1 - Biquad 4
Channel 2 - Biquad 1
…
Channel 2 - Biquad 4
Channel 1/2 - Biquad 5 for XO = 000
High-pass 1 st
order filter for XO ≠ 000
Channel 3 - Biquad for XO = 000
Low-pass 2 nd
order filter for XO ≠ 000
Channel 1 - Pre-Scale
Channel 2 - Pre-Scale
Channel 1 - Post-Scale
Channel 2 - Post-Scale
Channel 3 - Post-Scale
Reserved
C12H1(b2)
C12H2(a1/2)
C12H3(a2)
C12H4(b0/2)
C3H0(b1/2)
C3H1(b2)
C3H2(a1/2)
C3H3(a2)
C3H4(b0/2)
C1PreS
C2PreS
C1PstS
C2PstS
C3PstS
Reserved
C1H10(b1/2)
C1H11(b2)
C1H12(a1/2)
C1H13(a2)
C1H14(b0/2)
C1H20
…
C1H44
C2H10
C2H11
…
C2H44
C12H0(b1/2)
0x000000
0x000000
0x000000
0x400000
0x000000
0x000000
0x000000
0x000000
0x400000
0x7FFFFF
0x7FFFFF
0x7FFFFF
0x7FFFFF
0x7FFFFF
0x5A9DF7
0x000000
0x000000
0x000000
0x000000
0x400000
0x000000
…
0x400000
0x000000
0x000000
…
0x400000
0x000000
56
57
0x38
0x39
Channel 1 - Mix 1
Channel 1 - Mix 2
C1MX1
C1MX2
0x7FFFFF
0x000000
58 0x3A Channel 2 - Mix 1 C2MX1 0x000000
59 0x3B Channel 2 - Mix 2 C2MX2 0x7FFFFF
60
61
62
63
0x3C
0x3D
0x3E
0x3F
Channel 3 - Mix 1
Channel 3 - Mix 2
UNUSED
UNUSED
C3MX1
C3MX2
0x400000
0x400000
Doc ID 022784 Rev 1 141/172
Register description: Sound Terminal compatibility STA382BWS
7.13 Fault-detect recovery constant registers (addr 0x2B - 0x2C)
D7
FDRC15
0
D6
FDRC14
0
D5
FDRC13
1
D4
FDRC12
1
D3
FDRC11
0
D2
FDRC10
0
D1
FDRC9
0
D0
FDRC8
0
D7
FDRC7
0
D6
FDRC6
0
D5
FDRC5
0
D4
FDRC4
0
D3
FDRC3
1
D2
FDRC2
1
D1
FDRC1
0
D0
FDRC0
0
The FDRC bits specify the 16-bit fault-detect recovery time delay. When FAULT is asserted, the TRISTATE output is immediately asserted low and held low for the time period specified by this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The default value of 0x300C gives approximately 1 sec.
0x0000 is a reserved value.
7.14 Device status register (addr 0x2D)
D7
PLLUL
D6
FAULT
D5
Reserved
D4
Reserved
D3
Reserved
D2
Reserved
D1
Reserved
D0
Reserved
This read-only register provides fault and thermal-warning status information from the power control block. Logic value 1 for faults or warning means normal state. Logic 0 means a fault or warning detected on power bridge. The PLLUL = 1 means that the PLL is not locked.
Table 155.
Status register bits
Bit R/W RST Name
7
6
R
R -
PLLUL
FAULT
Description
0: PLL locked
1: PLL not locked
0: fault detected on power bridge
1: normal operation
D7 D6 D5 D4 D3 D2 D1 D0
XOB Reserved Reserved Reserved Reserved Reserved Reserved Reserved
0 0 0 0 0 0 0 0
Obsolete Product(s) - Obsolete Product(s)
The XOB bit can be used to bypass the crossover filters. Logic 1 means that the function is not active. In this case, the high-pass crossover filter works as a pass-through on the data path (b=0, all the other coefficients at logic 0 ) while the low-pass filter is configured to have zero signal on channel 3 data processing (all the coefficients are at logic 0) .
142/172 Doc ID 022784 Rev 1
STA382BWS Register description: Sound Terminal compatibility
D7
MDRCE
0
D6
Reserved
0
D5
PS48DB
0
D4
XAR1
0
D3
XAR2
0
D2
BQ5
0
D1
BQ6
0
The extended configuration register provides access to B
2
DRC and biquad 5, 6 and 7.
D0
BQ7
0
The STA382BWS device provides a dual-band DRC (B
2
DRC) on the left and right channel data path, as depicted in
. The dual-band DRC is activated by setting MDRCE = 1.
Figure 40.
B
2
DRC scheme
Ch a nnel 3
Vol u me
DRC 2
L
B 2 DRC
Hi-p ass XO filter
-
+
Ch a nnel 1
Vol u me
DRC 1 +
R
B 2 DRC
Hi-p ass XO filter
- +
Ch a nnel 2
Vol u me
DRC 1
Ch a nnel 3
Vol u me
DRC 2 +
The low-frequency information (LFE) is extracted from the left and right channels, removing the high frequencies using a programmable biquad filter, and then computing the difference with the original signal. Limiter 1 (DRC1) is then used to control the amplitude of the left/right high-frequency components, while limiter 2 (DRC2) is used to control the low-
frequency components (see Chapter 7.11
The cutoff frequency of the high-pass filters can be user-defined, XO[3:0] = 0, or selected from the pre-defined values.
Obsolete Product(s) - Obsolete Product(s)
channel amplitude (see Chapter 7.11
) as well as their volume control. To be noted that, in
this configuration, the dedicated channel 3 volume control can actually act as a bass-boost enhancer as well (0.5 dB/step resolution).
The processed LFE channel is then recombined with the L and R channels in order to reconstruct the 2.0 output signal.
Doc ID 022784 Rev 1 143/172
Register description: Sound Terminal compatibility STA382BWS
Sub-band decomposition
The sub-band decomposition for B
2
DRC can be configured specifying the cutoff frequency.
The cutoff frequency can be programmed in two ways, using the XO bits in register 0x0C, or using the “user programmable” mode (coefficients stored in RAM addresses 0x28 to 0x31).
For the user-programmable mode, use the formulas below to compute the high-pass filters: b0 = (1 + alpha) / 2 b1 = -(1 + alpha) / 2 a0 = 1 a1 = -alpha b2 = 0 a2 = 0 where alpha = (1-sin(
ω
0
))/cos(
ω
0
), and
ω
0
is the cutoff frequency.
A first-order filter is suggested to guarantee that for every
ω
0
the corresponding low-pass
filter obtained as difference (as shown in Figure 24 ) will have a symmetric (relative to the HP
filter) frequency response, and the corresponding recombination after the DRC has low ripple. Second-order filters can be used as well, but in this case the filter shape must be carefully chosen to provide good low-pass response and minimum ripple recombination. For second-order filters, it is not possible to give a closed formula to get the best coefficients, but empirical adjustment should be done.
DRC settings
The DRC blocks used by B
2
DRC are the same as those described in Chapter 7.11
2
DRC configure automatically the DRC blocks in anticlipping mode. Attack and release thresholds can be selected using registers 0x32, 0x33, 0x34, 0x35, while attack and release rates are configured by registers 0x12 and 0x14.
Band downmixing
The low-frequency band is down-mixed to the left and right channels at the B
2
DRC output.
Channel volume can be used to weight the bands recombination to fine-tune the overall frequency response.
7.16.2 Extended post-scale range
Table 156.
Extended post-scale range
PS48DB Mode
0 Post-scale value is applied as defined in coefficient RAM
Post-scale value is applied with +48 dB offset with respect to the
1 coefficient RAM value Obsolete Product(s) - Obsolete Product(s)
Post-scale is an attenuation by default. When PS48DB is set to 1, a 48-dB offset is applied to the coefficient RAM value, so post-scale can act as a gain too.
144/172 Doc ID 022784 Rev 1
STA382BWS Register description: Sound Terminal compatibility
7.16.3 Extended attack rate
The attack rate shown in Table 148 can be extended to provide up to an 8 dB/ms attack rate
on both limiters.
Table 157.
Extended attack rate, limiter 1
XAR1
0
1
Mode
Limiter1 attack rate is configured using
Limiter1 attack rate is 8 dB/ms
Table 158.
Extended attack rate, limiter 2
XAR2
0
1
Mode
Limiter2 attack rate is configured using
Limiter2 attack rate is 8 dB/ms
Note:
Bass and treble controls can be configured as user-defined filters when the equalization coefficients link is activated (BQL = 1) and the corresponding BQx bit is set to 1.
Table 159.
Extended biquad selector, biquad 5
BQ5
0
1
Mode
Reserved
User-defined biquad 5 coefficients are selected
Table 160.
Extended biquad selector, biquad 6
BQ6
0
1
Mode
Pre-set bass filter selected as per Table 147
User-defined biquad 6 coefficients are selected
Table 161.
Extended biquad selector, biquad 7
BQ7
1
Mode
Pre-set treble filter selected as per Table 147
User-defined biquad 7 coefficients are selected
When filters from the 5th to 7th are configured as user-programmable, the corresponding coefficients are stored respectively in addresses 0x20-0x24 (BQ5), 0x25-0x29 (BQ6), 0x2A-
0x2E (BQ7) as given in
BQx bits are ignored if BQL = 0 or if DEMP = 1 (relevant for BQ5) or CxTCB = 1 (relevant for
BQ6 and BQ7).
Doc ID 022784 Rev 1 145/172
Register description: Sound Terminal compatibility STA382BWS
7.17 EQ soft volume configuration registers (addr 0x37 - 0x38)
D7
Reserved
0
D6
Reserved
0
D5
SVUPE
0
D4
SVUP[4]
0
D3
SVUP[3]
0
D2
SVUP[2]
0
D1
SVUP[1]
0
D0
SVUP[0]
0
D7
Reserved
0
D6
Reserved
0
D5
SVDWE
0
D4
SVDW4]
0
D3
SVDW[3]
0
D2
SVDW[2]
0
D1
SVDW[1]
0
D0
SVDW[0]
0
The soft volume update has a fixed rate by default. Using register 0x37 and 0x38 it is possible to override the default behavior, allowing different volume change rates.
It is also possible to independently define the fade-in (volume is increased) and fade-out
(volume is decreased) rates according to the desired behavior.
Table 162.
Soft volume update enable, increase
SVUPE
0
1
Mode
When volume is increased, use the default rate
When volume is increased, use the rates defined by SVUP[4:0].
When SVUPE = 1 the volume-up rate is defined by the SVUP[4:0] bits according to the following formula: volume-up rate = 48 / (N + 1) dB/ms where N is the SVUP[4:0] value.
Table 163.
Soft volume update enable, decrease
SVDWE
0
1
Mode
When volume is decreased, use the default rate
When volume is decreased, use the rates defined by SVDW[4:0].
When SVDWE = 1 the volume-down rate is defined by the SVDW[4:0] bits according to the following formula: volume-down rate = 48 / (N + 1) dB/ms where N is the SVDW[4:0] value.
For volume-down rates greater than 6 dB/msec it is recommended to disable the CPWMEN bit and ZCE bit in order to avoid any audible pop noise.
146/172 Doc ID 022784 Rev 1
STA382BWS Register description: Sound Terminal compatibility
7.18 Extra volume resolution configuration registers (address
0x3F; 0x40)
D7
VRESEN
1
D6
VRESTG
0
D5
C3VR[1]
0
D4
C3VR[0]
0
D3
C2VR[1]
0
D2
C2VR[0]
0
D1
C1VR[1]
0
D0
C1VR[0]
0
D7 reserved
0
D6 reserved
0
D5 reserved
0
D4 reserved
0
D3 reserved
0
D2 reserved
0
D1
MVR[1]
0
D0
MVR[0]
0
Extra volume resolution allows fine volume tuning by steps of 0.125 dB.
The feature is enabled when VRESEN=1, as depicted in Figure 41 . The overall channel
volume in this case will be CxVol+CxVR (in dB), while the master volume will be
MVOL+MVR (in dB).
Figure 41.
Extra resolution volume scheme
A u dio D a t a In
S oft
Vol u me
A u dio D a t a O u t
VRE S TG
VRE S EN
If VRESEN = 0 the channel volume will be defined only by the CxVol registers.
Fine tuning steps can be set according to the following table for channels 1, 2,3, and master volume.
Table 164.
Volume fine-tuning steps Obsolete Product(s) - Obsolete Product(s)
00 0 dB
01
10
11
-0.125 dB
-0.25 dB
-0.375 dB
Doc ID 022784 Rev 1 147/172
Register description: Sound Terminal compatibility STA382BWS
Two different behaviors can be configured by the VRESTG bit.
I
If VRESTG=’0’ the CxVR contribution will be applied immediately after the corresponding
2
C bits are written.
If VRESTG=’1’ the CxVR bits will be effective on channel volume only after the corresponding CxVol register or master volume register is written (even to the previous values).
Table 165.
Extra volume resolution enable
VRESEN
0
0
1
1
VRESTG
0
1
0
1
Mode
Extra volume resolution disabled
Extra volume resolution disabled
Fine volume tuning enabled and applied immediately
Fine volume tuning enabled and applied when master or channel volume is updated
7.19 PLL configuration registers (address 0x41; 0x42; 0x43; 0x44;
0x45; 0X46)
D7
0
D7
D6
0
D6
0 0
D7
PLL_DITH[1:0]
D6
0 0
D7
PLL_DPD
0
D6
PLL_FCT
0
D5
0
D5
0
D5
0
D5
PLL_STB
0
D4 D3
PLL_FRAC[15:8]
0 0
D4 D3
0
PLL_FRAC[7:0]
0
D4
0
D4
PLL_STBBYP
0
D2
0
D2
D1
0 0
D3 D2
PLL_NDIV[5:0]
0 0
D3
0
D1
0
D2
PLL_IDIV(3:0)
D1
0 0
0
D1
D0
0
D0
0
D0
0
D0
0
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
0
Reserved
0
PLL_DIRP
0
PLL_PWD
0
PLL_BYP
0
OSC_PD
1
Reserved
0
BOOST32K
0
D7
Reserved
NA
D6
Reserved
NA
D5
Reserved
NA
D4
Reserved
NA
D3
BYPSTATE
NA
D2
PDSTATE
NA
D1
OSCOK
NA
D0
LOWCK
NA
By default the STA382BWS is able to configure the embedded PLL automatically depending on the MCS bits (reg 0x00). For certain applications and to provide flexibility to the user, a manual PLL configuration can be used (setting PLL_DIRP to ‘1’).
148/172 Doc ID 022784 Rev 1
STA382BWS Register description: Sound Terminal compatibility
The output PLL frequency formula is:
Fin
×
⎛
⎝
( )
(
IDIV
+
1
)
+
⎛
⎝
-----------------
65536
⎞
⎠
⎞
⎠ where Fin is the input clock frequency from the pad.
Table 166.
PLL factors
PLL parameter
FRAC
IDIV
NDIV
Min
0
0
5
Max
65535
3
55
3
2
5
4
1
0
Table 167.
PLL register 0x43 bits
Bit R/W RST Name
7 R/W 0
PLL_DITH(1:0)
6 R/W 0
Description
‘00’: PLL clock dithering disabled
‘01’: PLL clock dithering enabled (triangular))
‘10’: PLL clock dithering enabled (rectangular)
‘11’: Reserved
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
NDIV PLL loop divider
Table 168.
PLL register 0x44 bits
Bit R/W RST Name Description
7 R/W 0 PLL_DPD
‘0’: any PLL dividers change is implemented via PLL power-down
‘1’: PLL divider change will happen without PLL power-down
6 R/W 0 PLL_FCT
‘0’: PLL use integer ratio Obsolete Product(s) - Obsolete Product(s)
5 R/W 0 PLL_STB PLL synchronous divider changes strobe
4 R/W 0 PLL_STBBYP
‘0’: PLL_STB is active
‘1’: PLL_STB control is bypassed
3 R/W 0
2
1
0
R/W
R/W
R/W
0
0
0
PLL_IDIV (3:0) Input PLL divider
Doc ID 022784 Rev 1 149/172
Register description: Sound Terminal compatibility STA382BWS
Table 169.
PLL register 0x45 bits
Bit
5
2
0
4
3
R/W
R/W
R/W
R/W
R/W
R/W
RST
0
0
0
0
0
Name
PLL_DIRP
PLL_PWD
PLL_BYP
OSC_PD
BOOST32K
Description
‘0’: PLL configuration is determined by MCS bits
‘1’: PLL configuration is determined by FRAC, IDIV and NDIV
‘0’: PLL normal behavior
‘1’: PLL is in power-down mode
‘0’: sys clock is from PLL
‘1’: sys clock is from external pin (PLL is bypassed)
‘0’: Normal behavior
‘1’: Internal oscillator is in power-down
‘0’: Input oversampling selected by IR bits
‘1’: Input oversampling is selected x3
Table 170.
PLL register 0x46 bits
Bit R/W RST Name
1
0
3
2
R
R
R
R
BYPSTATE
PDSTATE
OSCOK
LOWCK
Description
PLL bypass state
PLL PD state
OSCI locked
Clock input frequency check
7.20 Short-circuit protection mode registers SHOK (address 0x47)
D7 reserved
NA
D6 reserved
NA
D5 reserved
NA
D4 reserved
NA
D3 reserved
NA
D2
GNDSH
NA
D1
VCCSH
NA
D0
OUTSH
NA
The following power bridge pins short-circuit protections are implemented in the
STA382BWS:
●
●
OUTxx vs GNDx
OUTxx vs VCCx
● OUT1B vs OUT2A
Obsolete Product(s) - Obsolete Product(s) the short-circuit when the EAPD bit is toggled from ‘0’ to ‘1’ (i.e. the power bridge is switched on), and only if the test passes (no short) does the power bridge leave the tristate condition.
Register 0x47 (read-only registers) will give more information about the detected short type.
GNDSH equal to ‘0’ means that OUTxx is shorted to ground, while the same value on
VCCSH means that OUTxx is shorted to Vcc, finally OUTSH=’0’ means that OUT1B is shorted to OUT2A.
150/172 Doc ID 022784 Rev 1
STA382BWS Register description: Sound Terminal compatibility
To be noted that once the check is performed, and the tristate released, the short protection is not active anymore until the next EAPD 0->1 toggling which means that shorts that happened during normal operation cannot be detected.
To be noted that register 0x47 is meaningful only after the EAPD bit is set to ‘1’ at least once.
The short-circuit protections implemented are effective only in BTL configuration, and they must not be activated if a single ended-application scheme is needed.
Figure 42.
Short-circuit detection timing diagram (no short detected)
S t a r t g n d t e s t S t a r t v c c t e s t E n d o f S h o r t t e s t
S t a rt o u t te s t
EAPD
OUT1A
OUT1B
OUT2A
OUT2B
S HOK1[7:4]
S HOK1[ 3 :0]
S HOK2[0]
50005 cy cle s
44 cy c le s
50005 cy c le s
TBD c yc le s
1c yc le
the short protection timing diagram is shown. The time information is expressed
in clock cycles, where the clock frequency is defined as in section 7.1.1
used for the SHOKx bits to indicate that the bits are carrying the status of the previous
EAPD 0->1 toggling (to be noted that after reset this state is meaningless since no EAPD transition occurs). GND-related SHOK bits are updated as soon as the gnd test is completed, VCC bits are updated after the vcc test is completed, and the SOUT bit is updated after the shorted output test is completed. The gnd test, vcc test and output test are always run (if the SHEN bit active and EAPD is toggled to ‘1’), and only if both tests are successful (no short) do the bridge outputs leave the tristate (indicated by dotted lines in the figure). If one of the three tests (or all) fail, the power bridge outputs are kept in tristate until the procedure is restarted with a new EAPD toggling.
In this figure EAPD is intended to be bit 7 of register 0x05.
Obsolete Product(s) - Obsolete Product(s)
Doc ID 022784 Rev 1 151/172
Register description: Sound Terminal compatibility STA382BWS
7.21 Extended coefficient range up to -4...4 (address 0x49, 0x4A)
D7 D6
CEXT_B4[1] CEXT_B4[0]
1 0
D5
CEXT_B3[1]
1
D4
CEXT_B3[0]
0
D3 D2
CEXT_B2[1] CEXT_B2[0]
1 0
D1
CEXT_B1[1]
1
D0
CEXT_B1[0]
0
D7 reserved
0
D6 reserved
0
D5
CEXT_B7[1]
1
D4
CEXT_B7[0]
0
D3 D2
CEXT_B6[1] CEXT_B6[0]
1 0
D1
CEXT_B51]
1
D0
CEXT_B5[0]
0
Biquads from 1 to 7 have in the STA382BWS the possibility to extend the coefficient range from [-1,1) to [-4..4) which allows the implementation of high-shelf filters that may require a coefficient dynamic greater in absolute value than 1.
Three ranges are available, [-1;1) [-2;2) [-4;4). By default, the extended range is activated
Each biquad has its independent setting according to the following table.
Table 171.
Coefficients extended range configuration
CEXT_Bx[1] CEXT_Bx[0]
0
0
1
1
0
1
0
1
Range
[-1;1)
[-2;2)
[-4;4)
Reserved
In this case the user can decide, for each filter stage, the right coefficients range. Note that for a given biquad, the same range will be applied to the left and right (channel 1 and channel 2).
Crossover biquad does not have the availability of this feature, maintaining the [-1;1) range unchanged.
D7 D6 D5 D4 D3 D2 D1 D0
RPDNEN BRIDGOFF CPWMEN reserved
0 1 1 0 0 1 0 0 Obsolete Product(s) - Obsolete Product(s)
D7 D6 D5 D4 D3 D2 D1 D0
LPDP LPD LPDE PNDLSL[2] PNDLSL[1] PNDLSL[0] reserved SHEN
0 1 0 0 1 1 0 0
7.22.1 Rate power-down enable (RPDNEN) bit (address 0x4B, bit D7)
In the STA382BWS, by default, the power-down pin and I
2
C power-down act on mute commands to perform the fade-out. This default can be changed so that the fade-out can be started using master volume. The RPDNEN bit, when set, activates this feature.
152/172 Doc ID 022784 Rev 1
STA382BWS Register description: Sound Terminal compatibility
7.22.2 Bridge immediately off (BRIDGOFF) bit (address 0x4B, bit D5)
A fade-out procedure is started in the STA382BWS once the PWDN function is enabled, and after 13 million clock cycles (PLL internal frequency) the bridge is put in power-down
(tristate mode). There is also the possibility to change this behavior so that the power bridge will be switched off immediately after the PWDN pin is tied to ground, without waiting for the
13 million clock cycles. The BRIDGOFF bit, when set, activates this function. Obviously the immediate power-down will generate a pop noise at the output, therefore this procedure must be used only in case pop noise is not relevant in the application. Note that this feature works only for hardware PWDN assertion and not for a power-down applied through the IIC
interface. Refer to Section 7.22.5
if programming a different number of clock cycles is needed.
7.22.3 Channel PWM enable (CPWMEN) bit (address 0x4B, bit D2)
This bit, when set, activates a mute output in case the volume reaches a value lower than -76 dBFS.
(address 0x4C, bit D7, D6, D5)
Pin 42 (INTLINE), normally indicating a fault condition, using the following 3 register settings, can be reconfigured as hardware pin enabler for an external headphone or line amplifier.
In particular the LPDE bit, when set, activates this function. Accordingly, the LPD value (0 or
1) is exported on pin 42 and in case of power-down assertion, pin 42 is tied to LPDP.
The LPDP bit, when set, negates the value programmed as the LPD value, refer to the following table.
Table 172.
External amplifier enabler configuration bits
LPDP LPD LPDE Pin 42 output x
0 x
0
0
1
INT_LINE
0
0
1
1
0
1
1
1
1
1 1 1 0
Obsolete Product(s) - Obsolete Product(s)
Doc ID 022784 Rev 1 153/172
Register description: Sound Terminal compatibility
Figure 43.
Alternate function for INTLINE pin
P o w er B rid ge Fau lt
STA382BWS
‘0 ’
Y
L P D
N
0
1
0
1
IN T L IN E
L P D E
“is th e d evice in p ow erd o w n ?” L P D P
7.22.5 Power-down delay selector (PNDLSL[2:0]) bits (address 0x4C, bit D4,
D3, D2)
, the assertion of PWDN activates a counter that, by default, after 13 million clock cycles puts the power bridge in tristate mode, independently from the fade-out time. Using these registers it is possible to program this counter according to the following table.
Table 173.
PNDLSL bits configuration
PNDLSL[2] PNDLSL[1] PNDLSL[2]
0
0
0
0
0
1
0
0
1
1
1
1
1
0
0
1
0
1
0
1
0
1 1 1
Fade-out time
Default time (13M PLL clock cycles)
Default time divided by 2
Default time divided by 4
Default time divided by 8
Default time divided by 16
Default time divided by 32
Default time divided by 64
Default time divided by 128
This bit, when enabled, will activate the short-circuit checks before any power bridge
activation (EAPD bit 0->1). See section 7.20
154/172 Doc ID 022784 Rev 1
STA382BWS Register description: Sound Terminal compatibility
7.23 Bad PWM detection registers (address 0x4D, 0x4E, 0x4F)
D7
BPTH[5]
0
D7
BP4B
0
D6
BPTH[4]
0
D6
BP4A
0
D5
BPTH[3]
1
D5
BP3B
0
D4
BPTH[2]
1
D4
BP3A
0
D3
BPTH[1]
0
D3
BP2B
0
D2
BPTH[0]
0
D2
BP2A
0
D1 reserved
1
D1
BP1B
0
D0 reserved
0
D0
BP1A
0
D7
BPTIM[7]
0
D6
BPTIM[6]
1
D5
BPTIM[5]
0
D4
BPTIM[4]
1
D3
BPTIM[3]
1
D2
BPTIM[2]
1
D1
BPTIM[1]
1
D0
BPTIM[0]
0
The STA382BWS implements a detection on the PWM outputs able to verify if the output signal has no zero-crossing in a configurable time window. This check can be useful to detect DC levels in the PWM outputs. To be noted that the checks are performed on logic level PWM (i.e. not the power bridge ones, nor the PWM on DDX3 and DDX4 I/Os).
In case of ternary modulation, the detection threshold is computed as:
TH=[(BPTH*2+1)/128]*100%
If the measured PWM duty cycle is detected greater than or equal to TH for more than
BPTIM PWM periods, the corresponding PWM bit will be set in register 0x4E.
In case of binary modulation, there are two thresholds:
TH1=[(64+BPTH)/128]*100%
TH2=[(64-BPTH)/128]*100%
In this case if the measured PWM duty cycle is outside the TH1-TH2 range for more than
BPTIM PWM periods, the corresponding bit will be set in register 0x4E.
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Register description: Sound Terminal compatibility STA382BWS
7.24 Enhanced zero-detect mute and input level measurement
(address 0x50-0x54, 0x2E, 0x2F and 0x5E)
D7
WTHH
0
D6
WTHL
0
D5
FINETH
0
D4
HSEL[1:0]
D3
0 0
D2
1
D1
ZMTH[2:0]
1
D0
1
D7
N/A
D7
N/A
D6
N/A
D6
N/A
D5
N/A
D5
N/A
D4 D3
RMS_CH0[7:0]
N/A N/A
D4 D3
RMS_CH0[15:8]
N/A N/A
D2
N/A
D2
N/A
D1
N/A
D1
N/A
D0
N/A
D0
N/A
D7
N/A
D6
N/A
D5
N/A
D4 D3
RMS_CH1[7:0]
N/A N/A
D2
N/A
D1
N/A
D0
N/A
D7
N/A
D6
N/A
D5
N/A
D4 D3
RMS_CH1[15:8]
N/A N/A
D2
N/A
D1
N/A
D0
N/A
The STA382BWS implements an RMS-based zero-detect function (on serial input interface data) able to detect in a very reliable way the presence of an input signal, so that the power bridge outputs can be automatically connected to ground.
When active, the function will mute the output PWM when the input level become less than
“threshold - hysteresis”. Once muted, the PWM will be unmuted when the input level is detected greater than “threshold + hysteresis”.
The measured level is then reported (for each input channel) on registers 0x51 - 0x52, 0x53
- 0x54 according to the following equation:
Value_in_dB = 20*Log
10
(Reg_value/(2
16
*0.635))
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STA382BWS
Table 174.
Zero-detect threshold
ZMTH[2:0]
000
001
010
011
100
101
110
111
Register description: Sound Terminal compatibility
Equivalent input level (dB)
-78
-84
-90
-96
-102
-108
-114
-114
Table 175.
Zero-detect hysteresis
HSEL[1:0]
00
01
10
11
Equivalent input level hysteresis (dB)
3
4
5
6
The above thresholds and hysteresis table can be overridden and the low-level threshold and high-level threshold can be set by the MTH[21:0] bits.
To activate the manual thresholds the FINETH bit has to be set to ‘1’.
To configure the low threshold, the WTHL bit must be set to ‘1’ so that any write operation to the MTH bits will set the low threshold.
To configure the low threshold, the WTHH bit must be set to ‘1’ so that any write operation to the MTH bits will set the low threshold.
If the zero-mute block does not detect mute, it will mute the output when the current RMS value falls below the low threshold.
If the zero-mute block does not detect mute, it will unmute the output when the current RMS value rises above the high threshold.
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Register description: Sound Terminal compatibility
Table 176.
Manual threshold register 0x2E, 0x2F and 0x5E
D7 D6 D5 D4 D3 D2
ReservedT
0
Reserved
0 0 0 0
MTH[21:16]
0
D1
0
STA382BWS
D0
0
D7
0
D6
0
D5
0
D4
MTH[15:8]
D3
0 0
D2
0
D1
0
D0
0
D7
0
D6
0
D5
0
D4
MTH[7:0]
D3
0 0
D2
0
D1
0
D0
0
7.25 Headphone/Line out configuration register (address 0x55)
D7
HPLN
0
D6
Reserved
0
D5
MUTE
1
D4
Reserved
0
D3
CPFEN
0
D2
CPOK
NA
D1
ABFAULT
NA
D0
DCROK
NA
Table 177.
Headphone/Line out configuration bits
Bit R/W RST Name
7
5
3
1
0
R/W
R/W
R/W
R
R
R
0
1
0
NA
NA
NA
HPLN
MUTE
CPFEN
CPOK
ABFAULT
DCROK
Description
When F3X is connected to the internal HP/Line driver this bit selects the gain of the F3X->analog out path.
‘0’: HP out. When the MVOL+Channel Vol is 0 dBFs, a 0 dBFs input will generate a 40 mW output on a
32 ohm load (+/- 3.3 V supply).
‘1’:Line out. When the MVOL+Channel Vol is
0 dBFs, a 0 dBFs input will generate a 2 Vrms output
(+/- 3.3 V supply)
‘1’: HP/Line out muted
‘0’: HP/Line out playing
‘0’: Charge pump auto enable when unmute
‘1’: Charge pump is always enabled
‘0’: Charge pump is not working
‘1’: Charge pump is working and it is OK
‘0’: No fault on class-AB
‘1’: Overcurrent fault detected on class-AB
‘1’: core supply OK
158/172 Doc ID 022784 Rev 1
STA382BWS Register description: Sound Terminal compatibility
7.26 F3XCFG (address 0x58; 0x59)
D7
F3XLNK
0
D6
Reserved
0
D5
Reserved
0
D4
Reserved
0
D3
Reserved
0
D2
Reserved
0
D1
Reserved
0
D0
Reserved
0
D7
F3X_FAULT
NA
D6
Reserved
1
D5
Reserved
1
D4
0
D3
F3X_SM_SLOPE
1
D2
1
D1
F3X_MUTE
1
D0
F3X_ENA
0
Table 178.
F3X configuration register 1
Bit R/W RST Name
7 R/W 0 F3XLNK
Description
‘0’: F3X normal control mode
‘1’: F3X mute/unmute linked to HP/Line mute
Table 179.
F3X configuration register 2
Bit
7
4
3
2
1
0
R/W
R
R/W
R/W
R/W
R/W
R/W
RST
NA
0
1
1
1
0
Name Description
F3X_FAULT
F3X_SM_SLOPE
F3X_MUTE
F3X_ENA
‘0‘: Normal operation
‘000’: 0 ms
‘001’: 25 ms
‘010’: 50 ms
‘011’: 100 ms
‘100’: 200 ms
‘101’: 250 ms
‘110’: 500 ms
‘111’: 1000 ms
‘1’: Mute
‘1’: F3X enable
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Register description: Sound Terminal compatibility STA382BWS
7.27 STCompressor
TM
configuration register (address 0x5A;
0x5B)
D7 reserved
0
D6
LIM_BYP
0
D5
STC_BYP
1
D4
STC_ENA
1
D3 reserved
0
D7 reserved
0
D6 reserved
0
D5 reserved
0
D4 reserved
0
D3 reserved
0
Table 180.
STCompressor
TM
configuration bits1
Bit R/W RST Name
6
5
4
2
0
R/W
R/W
R/W
R
R/W
0
1
1
0
0
LIM_BYP
STC_BYP
STC_EN
NP_CRCRES
NP_CRC_GO
D2
NP_CRES
0
D2 reserved
0
D1 reserved
0
D1
STC_LNK
0
Description
‘
0’: STCompressor
TM
DRC active
‘1’: STCompressor
TM
DRC is bypassed
‘0’: STCompressor
TM
processing activated
‘1’: STCompressor
TM
is in pass-through
‘0’: STCompressor
TM
is switched off (no configuration is possible in this state)
‘1’: STCompressor
TM
is enabled
‘1’: CRC STCompressor ok
‘0’: CRC STCompressor error
‘1’: Start CRC STCompressor compute ON
‘0’: Idle
D0
NP_CRC-GO
0
D0
BRC_EN
0
Table 181.
STCompressor
TM
configuration bits 2
Bit R/W RST Name
1
0
R/W
R/W
0
0
STC_LNK
BRC_EN
Description
‘0’: Channel 0 and channel 1 attenuation are applied indepenently
‘1’: Channel 0 and channel 1 attenuation are linked so that the higher one is applied to both channel 0 and channel 1
‘1’: STCompressor band recombination enabled
‘0’: Disabled
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STA382BWS Register description: Sound Terminal compatibility
7.28 Charge pump synchronization (address 0x5F)
D7
Reserved
0
D6
Reserved
0
D5
CHPI
0
D4
1
D3
INITCNT[3:0]
D2
1 0
D1
0
D0
CHPRD
1
Table 182.
Charge pump sync configuration bits
Bit
5
R/W
R/W
RST
0
Name
CHPI
Description
0: Charge pump phase: 0 deg
1: Charge pump phase: 180 deg
4
3
2
1
R/W
R/W
R/W
R/W
1
1
0
0
INITCNT[3:0] Change charge pump phase at one clock step
0 R/W 1 CHPRD
0: Charge pump synchronized with PWM frame
0: Charge pump not synchronized with PWM frame
The charge pump can be synchronized with the PWM frame in order to minimize the crosstalk between the charge pump and the PWM waveform.
This functionality cannot be activated when the PWMS bit (address 0x15 bit D4) is set to 1.
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Register description: Sound Terminal compatibility STA382BWS
7.29 Coefficient RAM CRC protection (address 0x60-0x6C)
D7
BQCKE[7]
0
D6
BQCKE[6]
0
D5
BQCKE[5]
0
D4
BQCKE[4]
0
D3
BQCKE[3]
0
D2
BQCKE[2]
0
D1
BQCKE[1]
0
D0
BQCKE[0]
0
D7
BQCKE[15]
0
D6
BQCKE[14]
0
D5
BQCKE[13]
0
D4
BQCKE[12]
0
D3
BQCKE[11]
0
D2
BQCKE[10]
0
D7
BQCKE[23]
0
D6
BQCKE[22]
0
D5
BQCKE[21]
0
D4
BQCKE[20]
0
D3
BQCKE[19]
0
D2
BQCKE[18]
0
D1
BQCKE[17]
0
D0
BQCKE[16]
0
D7
XCCKE[7]
0
D7
XCCKE[15]
0
D6
XCCKE[6]
0
D6
XCCKE[14]
0
D5
XCCKE[5]
0
D5
XCCKE[13]
0
D4
XCCKE[4]
0
D4
XCCKE[12]
0
D3
XCCKE[3]
0
D3
XCCKE[11]
0
D2
XCCKE[2]
0
D2
XCCKE[10]
0
D1
BQCKE[9]
0
D1
XCCKE[1]
0
D1
XCCKE[9]
0
D0
BQCKE[8]
0
D0
XCCKE[0]
0
D0
XCCKE[8]
0
D7
XCCKE[23]
0
D6
XCCKE[22]
0
D5
XCCKE[21]
0
D4
XCCKE[20]
0
D3
XCCKE[19]
0
D2
XCCKE[18]
0
D1
XCCKE[17]
0
D0
XCCKE[16]
0
D7
BQCKR[7]
0
D7
BQCKR[15]
0
D6
BQCKR[6]
0
D6
BQCKR[14]
0
D5
BQCKR[5]
0
D5
BQCKR[13]
0
D4
BQCKR[4]
0
D3
BQCKR[3]
0
D4
BQCKR[12]
0
D3
BQCKR[11]
0
D2
BQCKR[2]
0
D2
BQCKR[10]
0
D1
BQCKR[1]
0
D1
BQCKR[9]
0
D0
BQCKR[0]
0
D0
BQCKR[8]
0
D7
BQCKR[23]
0
D6
BQCKR[22]
0
D5
BQCKR[21]
0
D4
BQCKR[20]
0
D3
BQCKR[19]
0
D2
BQCKR[18]
0
D1
BQCKR[17]
0
D0
BQCKR[16]
0
D7
XCCKR[23]
0
D6
XCCKR[22]
0
D5
XCCKR[21]
0
D4
XCCKR[20]
0
D3
XCCKR[19]
0
D2
XCCKR[18]
0
D1
XCCKR[17]
0
D0
XCCKR[16]
0
D7
XCCKR[23]
D6
XCCKR[22]
D5
XCCKR[21]
D4
XCCKR[20]
D3
XCCKR[19]
D2
XCCKR[18]
D1
XCCKR[17]
D0
XCCKR[16]
0 0 0 0 0 0 0 0
D7
XCCKR[23]
0
D6
XCCKR[22]
0
D5
XCCKR[21]
0
D4
XCCKR[20]
0
D3
XCCKR[19]
0
D2
XCCKR[18]
0
D1
XCCKR[17]
0
D0
XCCKR[16]
0
D7
XCAUTO
0
D6
XCRES
0
D5
XCCMP
0
D4
XCGO
0
D3
BCAUTO
0
D2
BCCRES
0
D1
BCCMP
0
D0
BCCGO
0
162/172 Doc ID 022784 Rev 1
STA382BWS Register description: Sound Terminal compatibility
The STA382BWS implements an automatic CRC computation for the biquad and
MDRC/XOver coefficient memory. Memory cell contents from address 0x00 to 0x27 will be bit XORed to obtain the BQCHKE checksum, while cells from 0x28 to 0x31 will be XORed to obtain the XCCHKE checksum. Both checksums (24-bit wide) are exported on I
2
C registers from 0x60 to 0x65. The checksum computation will start as soon as the BCGO (for biquad
RAM bank) or the XCGO bit (for MDRC/XOver coefficients) is set to 1. The checksum is computed at the processing sample rate if the IR bits equal “01” or “10”, otherwise the checksum is computed to half the processing sample rate.
When BCCMP or XCCMP are set to ‘1’, the relative checksum (BQCHKE and XCCHKE) is continuously compared with BQCHKR and XCCHKR respectively. If the checksum matches its own reference value, the respective result bits (BCRES and XCRES) will be set to ‘0’.
The compare bits have no effect if the respective GO bit is not set.
In case of checksum errors (i.e. the internally computed didn’t match the reference), an automatic device reset action can be activated. This function is enabled when the BCAUTO or XCAUTO bit is set to ‘1’. The automatic reset bits have no effect if the respective compare bits are not set.
●
●
●
The recommended procedure for the automatic reset activation is the following:
Download the set of coefficients (RAM locations 0x00…0x27)
Download the externally computed biquad checksum into registers
Enable the checksum of the biquad coefficients by setting the
BQCHKR
BCGO bit. The checksum will start to be automatically computed by the STA382BWS and its value exposed on registers BQCHECKE.
The checksum value is computed and updated.
● Enable the checksum comparison by setting the BCCMP bit. The internally computed checksum will start to be compared with the reference one and the result will be exposed on the BCRES bit. The following operation will be executed on each audio frame: if (( BQCHKE == BQCHKR ))
{
BC_RES = 0;// Checksum is ok, reset the error bit
} else
{
BC_RES = 1;// Checksum error detected, set the error bit
}
● Wait until the BCRES bit goes to 0, meaning that the checksum result bit has started to be updated and everything is ok. Time-out of this operation (e.g. > 1 ms) will indicate
● checksum failure, and the MCU will handle this event.
Obsolete Product(s) - Obsolete Product(s) bit. The BCRES bit will then be automatically checked by the STA382BWS, on each audio frame, and the reset event will be triggered in case of checksum mismatch.
● Periodically check the BC_RES status. A value of 1 indicates that a checksum mismatch has occurred and, therefore, the device went through a reset cycle.
The previous example is intended for biquad CRC bank calculation, but it can be easily extended to MDRC/XOver CRC computation.
Doc ID 022784 Rev 1 163/172
Register description: Sound Terminal compatibility
7.30 MISC3 (address 0x6E)
STA382BWS
D7 reserved
0
D6 reserved
0
D5 reserved
0
D4 reserved
0
D3 reserved
0
D2
SRESET
0
D1 reserved
0
D0 reserved
0
Table 183.
Misc register 3
Bit R/W RST
2 R/W 0
Name
SRESET
‘0’: normal operation
‘1’: reset the device
Description
After SRESET is written, the last IC acknowledge is skipped and the EAPD bit (reg 0x16 bit
D7) is set to1 instead of the 0 default value obtained after the hardware reset.
7.31 MISC4 (address 0x7E)
D7
SMAP
1
D6 reserved
0
D5 reserved
0
D4 reserved
0
D3 reserved
0
D2 reserved
0
D1 reserved
0
D0 reserved
0
Table 184.
MISC4
Bit R/W RST
7 1
Name
SMAP
‘1’: NEWMAP
‘0’: STMAP
Description
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STA382BWS
8 Applications
Applications
The following figures illustrate typical application schemes for the STA382BWS. The line/headphone out can be fed either with an external analog source (
), or with the
F3X output, allowing to have the audio content coming from the digital interface on both the
power output and on the line/headphone out ( Figure 45
). Regardless of the LINEINx pins input, the F3Xx outputs can be connected to an external amplifier as an auxiliary analog output (
). The F3X audio content is provided by the device digital audio interface.
Figure 44.
External audio source to line/headphone out application scheme
STA382BWS
Obsolete Product(s) - Obsolete Product(s)
Note: For further information, please refer to application note AN3959, 2.0-channel demonstration board based on the STA382BWS and STA381BWS.
Doc ID 022784 Rev 1 165/172
Applications STA382BWS
Figure 45.
F3X (from SAI) source to line/headphone out application scheme
STA382BWS
Note: For further information, please refer to application note AN3959, 2.0-channel demonstration board based on the STA382BWS and STA381BWS.
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STA382BWS
Figure 46.
F3X auxiliary analog output
STA382BWS
Applications
Note:
8.2
For further information, please refer to application note AN3959, 2.0-channel demonstration board based on the STA382BWS and STA381BWS.
Headphone and 2 Vrms line out
Figure 47.
Headphone and line out block diagram
Obsolete Product(s) - Obsolete Product(s)
Note: For further information, please refer to application note AN3959, 2.0-channel demonstration board based on the STA382BWS and STA381BWS.
Doc ID 022784 Rev 1 167/172
Applications
Note:
STA382BWS
Besides the digital input to the power output path, a line in to the headphone / 2Vrms line out
path is provided. The headphone and line out block diagram is shown in Figure 47 . The
overall gain is determined by the external resistors R1 and R2 as:
Gain=R2/R1*2
The LINEINR/LINEINL pins can be either connected to an external line in or to the
F3XL/F3XR pins as depicted in
and Figure 45 . Thanks to this latter option it is
possible to route the digital input (SAI) content on both the power and the line out/headphone output.
The charge pump of the headphone and line out cannot drive a purely capacitive load.
Please refer to AN3959 (2.0-channel demonstration board based on the STA382BWS and
STA381BWS) for detailed information about headphone and line out filtering.
illustrates the typical output configuration used for BTL stereo mode. Please refer to the application note for all the other schematics for the recommended output configuration.
Figure 48.
Output configuration for stereo BTL mode in filterlight configuration
168/172
For further information, please refer to application note AN3959, 2.0-channel demonstration board based on the STA382BWS and STA381BWS.
Doc ID 022784 Rev 1
STA382BWS Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
Figure 49.
VQFN48 (7 x 7 x 0.9 mm) package outline
Obsolete Product(s) - Obsolete Product(s)
83 20060_wk
Doc ID 022784 Rev 1 169/172
Package information
Table 185.
VQFN48 (7 x 7 x 0.9 mm) package dimensions mm
Reference
Min.
Typ.
0.90
e (pad pitch)
L1 aaa bbb ddd eee fff ccc
E
E2 b b1
A
A1
D
D2
6.90
5.65
0.25
0.20
0.80
0
6.90
5.65
0.05
7.00
5.70
7.00
5.70
0.30
0.25
0.50
0.15
0.10
0.05
0.08
0.10
0.10
STA382BWS
Max
7.10
5.75
0.35
0.30
1.00
0.05
7.10
5.75
0.15
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STA382BWS
Table 186.
Document revision history
Date Revision
04-Apr-2012 1 Initial release.
Changes
Revision history
Obsolete Product(s) - Obsolete Product(s)
Doc ID 022784 Rev 1 171/172
STA382BWS
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