STMicroelectronics ST72521R9 Datasheet

– Select the edge of the active transition on the

ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as floating input or input with pull-up without interrupt if this configuration is available).

And select the following in the CR1 register:

– Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1pin must be configured as floating input or input with pullup without interrupt if this configuration is available).

When an input capture occurs:

– ICFi bit is set.

– The ICiR register contains the value of the free running counter on the active transition on the

ICAPi pin (see Figure 47

– A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true.

Clearing the Input Capture interrupt request (i.e.

clearing the ICFi bit) is done in two steps:

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

Notes:

1. After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read.

2. The ICiR register contains the free running counter value which corresponds to the most recent input capture.

3. The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions.

4. In One pulse Mode and PWM mode only Input

Capture 2 can be used.

5. The alternate inputs (ICAP1 & ICAP2) are always directly connected to the timer. So any transitions on these pins activates the input capture function.

Moreover if one of the ICAPi pins is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set.

This can be avoided if the input capture function i is disabled by reading the ICiHR (see note

1).

6. The TOF bit can be used with interrupt generation in order to measure events that go beyond the timer range (FFFFh).

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Figure 46. Input Capture Block Diagram

ICAP1 pin

ICAP2 pin

EDGE DETECT

CIRCUIT2

EDGE DETECT

CIRCUIT1

IC2R Register IC1R Register

16-BIT

16-BIT FREE RUNNING

COUNTER

ICIE

ICF1

(Control Register 1) CR1

IEDG1

ICF2

(Status Register) SR

0 0 0

(Control Register 2) CR2

CC1 CC0 IEDG2

Figure 47. Input Capture Timing Diagram

TIMER CLOCK

COUNTER REGISTER

ICAPi PIN

ICAPi FLAG

FF01 FF02

ICAPi REGISTER

Note: The rising edge is the a ctive edge.

FF03

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10.4.3.4 Output Compare

In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer.

This function can be used to control an output waveform or indicate when a period of time has elapsed.

When a match is found between the Output Compare register and the free running counter, the output compare function:

– Assigns pins with a programmable value if the

OCiE bit is set

– Sets a flag in the status register

– Generates an interrupt if enabled

Two 16-bit registers Output Compare Register 1

(OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle.

OCiR

MS Byte

OCiHR

LS Byte

OCiLR

These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OC i R value to 8000h.

Timing resolution is one count of the free running counter: ( f

CPU/ CC[1:0]

Procedure:

To use the output compare function, select the following in the CR2 register:

– Set the OCiE bit if an output is needed then the

OCMPi pin is dedicated to the output compare i signal.

– Select the timer clock (CC[1:0]) (see

And select the following in the CR1 register:

– Select the OLVLi bit to applied to the OCMPi pins after the match occurs.

– Set the OCIE bit to generate an interrupt if it is needed.

When a match is found between OCRi register and CR register:

– OCFi bit is set.

– The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset).

– A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is cleared in the CC register (CC).

The OC i R register value required for a specific timing application can be calculated using the following formula:

∆

OCiR =

∆ t

CPU

PRESC

Where:

∆ t = Output compare period (in seconds) f

CPU

= CPU clock frequency (in hertz)

PRESC

= Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see

the OCiR register value (see Figure 49 on page

Clock Control Bits )

If the timer clock is an external clock, the formula is:

∆

OCiR =

∆ t

EXT

Where:

∆ t = Output compare period (in seconds) f

EXT

= External timer clock frequency (in hertz)

Clearing the output compare interrupt request (i.e.

clearing the OCFi bit) is done by:

1. Reading the SR register while the OCFi bit is set.

2. An access (read or write) to the OCiLR register.

The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OC i R register:

– Write to the OCiHR register (further compares are inhibited).

– Read the SR register (first step of the clearance of the OCFi bit, which may be already set).

– Write to the OCiLR register (enables the output compare function and clears the OCFi bit).

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Notes:

1. After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written.

2. If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set.

3. When the timer clock is f

CPU

/2, OCFi and

OCMPi are set while the counter value equals

). This behaviour is the same in OPM or

PWM mode.

When the timer clock is f

CPU

/4, f

CPU

/8 or in external clock mode, OCFi and OCMPi are set while the counter value equals the OCiR register value plus 1 (see

Figure 50 on page 78

4. The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used.

5. The value in the 16-bit OC i R register and the

OLVi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout.

Figure 48. Output Compare Block Diagram

Forced Compare Output capability

When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit=1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated.

The FOLVLi bits have no effect in both one pulse mode and PWM mode.

16 BIT FREE RUNNING

COUNTER

16-bit

OUTPUT COMPARE

CIRCUIT

16-bit 16-bit

OC1R Register

OC2R Register

OC1E OC2E

OCIE

CC1 CC0

(Control Register 2) CR2

(Control Register 1) CR1

FOLV2 FOLV1 OLVL2 OLVL1

Latch

OCF1 OCF2 0 0 0

(Status Register) SR

OCMP1

OCMP2

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Figure 49. Output Compare Timing Diagram, f

TIMER

CPU

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER

OUTPUT COMPARE REGISTER i (OCRi)

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

2ECF 2ED0 2ED1 2ED2 2ED3 2ED4

2ED3

Figure 50. Output Compare Timing Diagram, f

TIMER

CPU

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER

OUTPUT COMPARE REGISTER i (OCRi)

COMPARE REGISTER i LATCH

2ECF 2ED0 2ED1 2ED2 2ED3 2ED4

2ED3

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

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10.4.3.5 One Pulse Mode

One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register.

The one pulse mode uses the Input Capture1 function and the Output Compare1 function.

Procedure:

To use one pulse mode:

1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column).

2. Select the following in the CR1 register:

– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse.

– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse.

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input).

3. Select the following in the CR2 register:

– Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function.

– Set the OPM bit.

– Select the timer clock CC[1:0] (see Table 16

Clearing the Input Capture interrupt request (i.e.

clearing the ICFi bit) is done in two steps:

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

The OC1R register value required for a specific timing application can be calculated using the following formula: t

* f

CPU

OCiR Value =

- 5

PRESC

Where: t = Pulse period (in seconds) f

CPU

= CPU clock frequency (in hertz)

PRESC

= Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see

bit is output on the OCMP1 pin, (See Figure 51 ).

Clock Control Bits )

If the timer clock is an external clock the formula is:

OCiR = t

EXT

-5

Where: t = Pulse period (in seconds) f

EXT

= External timer clock frequency (in hertz)

When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1

When event occurs on ICAP1

When

Counter

= OC1R

One pulse mode cycle

ICR1 = Counter

OCMP1 = OLVL2

Counter is reset to FFFCh

ICF1 bit is set

OCMP1 = OLVL1

Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register.

Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set.

Notes:

1. The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an

Output Compare interrupt.

2. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.

4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set.

5. When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and

OCF2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the one pulse mode.

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Figure 51. One Pulse Mode Timing Example

IC1R

COUNTER

01F8 FFFC FFFD FFFE

ICAP1

OCMP1

OLVL2

01F8

2ED0 2ED1 2ED2

2ED3

FFFC FFFD

OLVL2 compare1

OLVL1

Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1

Figure 52. Pulse Width Modulation Mode Timing Example with 2 Output Compare Functions

COUNTER 34E2

FFFC FFFD FFFE

OLVL2

OCMP1 compare2

2ED0 2ED1 2ED2 34E2 FFFC compare1

OLVL1 OLVL2 compare2

Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1

Note: On timers with only 1 Output Compare register, a fixed frequency PWM signal can be generated using the output compare and the counter overflow to define the pulse length.

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10.4.3.6 Pulse Width Modulation Mode

Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and

OC2R registers.

Pulse Width Modulation mode uses the complete

Output Compare 1 function plus the OC2R register, and so this functionality can not be used when

PWM mode is activated.

In PWM mode, double buffering is implemented on the output compare registers. Any new values written in the OC1R and OC2R registers are taken into account only at the end of the PWM period

(OC2) to avoid spikes on the PWM output pin

(OCMP1).

Procedure

To use pulse width modulation mode:

1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column.

2. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1=0 and OLVL2=1) using the formula in the opposite column.

3. Select the following in the CR1 register:

– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful comparison with the OC1R register.

– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful comparison with the OC2R register.

4. Select the following in the CR2 register:

– Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.

– Set the PWM bit.

– Select the timer clock (CC[1:0]) (see

ing on CC[1:0] bits, see Table 16 Clock

Pulse Width Modulation cycle

When

Counter

= OC1R

OCMP1 = OLVL1

When

Counter

= OC2R

OCMP1 = OLVL2

Counter is reset to FFFCh

ICF1 bit is set

If OLVL1=1 and OLVL2=0 the length of the positive pulse is the difference between the OC2R and

OC1R registers.

If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.

The OC i R register value required for a specific timing application can be calculated using the following formula: t

* f

CPU

OCiR Value =

- 5

PRESC

Where: t = Signal or pulse period (in seconds) f

CPU

= CPU clock frequency (in hertz)

PRESC

= Timer prescaler factor (2, 4 or 8 depend-

Control Bits

)

If the timer clock is an external clock the formula is:

OCiR = t

EXT

-5

Where: t = Signal or pulse period (in seconds) f

EXT

= External timer clock frequency (in hertz)

The Output Compare 2 event causes the counter to be initialized to FFFCh (See

Figure 52 )

Notes:

1. After a write instruction to the OCiHR register, the output compare function is inhibited until the

OCiLR register is also written.

2. The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output

Compare interrupt is inhibited.

3. The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared.

4. In PWM mode the ICAP1 pin can not be used to perform input capture because it is disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and

IC2R can be loaded) but the user must take care that the counter is reset each period and

ICF1 can also generates interrupt if ICIE is set.

5. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

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10.4.4 Low Power Modes

Mode Description

WAIT

No effect on 16-bit Timer.

Timer interrupts cause the device to exit from WAIT mode.

16-bit Timer registers are frozen.

HALT

In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the MCU is woken up by a RESET.

If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and the counter value present when exiting from HALT mode is captured into the ICiR register.

10.4.5 Interrupts

Interrupt Event

Input Capture 1 event/Counter reset in PWM mode

Input Capture 2 event

Output Compare 1 event (not available in PWM mode)

Output Compare 2 event (not available in PWM mode)

Timer Overflow event

Event

Flag

Enable

Control

Bit

ICF1

ICF2

OCF1

OCF2

TOF

ICIE

OCIE

TOIE

Exit from

Wait

Yes

Exit from

Halt

Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).

10.4.6 Summary of Timer modes

MODES

Input Capture (1 and/or 2)

Output Compare (1 and/or 2)

One Pulse Mode

PWM Mode

Input Capture 1

Yes

TIMER RESOURCES

Input Capture 2 Output Compare 1 Output Compare 2

Yes Yes Yes

Yes

Not Recommended

Yes

Partially

1) See note 4 in

Section 10.4.3.5 One Pulse Mode

2) See note 5 in

Section 10.4.3.5 One Pulse Mode

3) See note 4 in

Section 10.4.3.6 Pulse Width Modulation Mode

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10.4.7 Register Description

Each Timer is associated with three control and status registers, and with six pairs of data registers

(16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter.

Bit 4 = FOLV2 Forced Output Compare 2.

This bit is set and cleared by software.

0: No effect on the OCMP2 pin.

1: Forces the OLVL2 bit to be copied to the

OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison.

CONTROL REGISTER 1 (CR1)

Read/Write

Reset Value: 0000 0000 (00h)

7 0

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

Bit 7 = ICIE Input Capture Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the

ICF1 or ICF2 bit of the SR register is set.

Bit 3 = FOLV1 Forced Output Compare 1.

This bit is set and cleared by software.

0: No effect on the OCMP1 pin.

1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no successful comparison.

Bit 2 = OLVL2 Output Level 2.

This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse Mode and Pulse Width Modulation mode.

Bit 6 = OCIE Output Compare Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the

OCF1 or OCF2 bit of the SR register is set.

Bit 5 = TOIE Timer Overflow Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.

Bit 1 = IEDG1 Input Edge 1.

This bit determines which type of level transition on the ICAP1 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 0 = OLVL1 Output Level 1.

The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the

OC1R register and the OC1E bit is set in the CR2 register.

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CONTROL REGISTER 2 (CR2)

Read/Write

Reset Value: 0000 0000 (00h)

7 0

OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

Bit 4 = PWM Pulse Width Modulation.

0: PWM mode is not active.

1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register.

Bit 7 = OC1E Output Compare 1 Pin Enable.

This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever the value of the OC1E bit, the Output Compare 1 function of the timer remains active.

0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O).

1: OCMP1 pin alternate function enabled.

Bit 6 = OC2E Output Compare 2 Pin Enable.

This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the Output Compare 2 function of the timer remains active.

0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O).

1: OCMP2 pin alternate function enabled.

Bit 5 = OPM One Pulse Mode.

0: One Pulse Mode is not active.

1: One Pulse Mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register.

Bit 3, 2 = CC[1:0] Clock Control.

The timer clock mode depends on these bits:

Table 16. Clock Control Bits

Timer Clock f

CPU

/ 4 f

CPU

/ 2 f

CPU

/ 8

External Clock (where available)

Note: If the external clock pin is not available, programming the external clock configuration stops the counter.

CC1

CC0

Bit 1 = IEDG2 Input Edge 2.

This bit determines which type of level transition on the ICAP2 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 0 = EXEDG External Clock Edge.

This bit determines which type of level transition on the external clock pin EXTCLK will trigger the counter register.

0: A falling edge triggers the counter register.

1: A rising edge triggers the counter register.

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CONTROL/STATUS REGISTER (CSR)

Read/Write (bits 7:3 read only)

Reset Value: xxxx x0xx (xxh)

ICF1 OCF1 TOF ICF2 OCF2 TIMD 0

Bit 7 = ICF1 Input Capture Flag 1.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in

PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the

IC1R (IC1LR) register.

Bit 6 = OCF1 Output Compare Flag 1.

0: No match (reset value).

1: The content of the free running counter has matched the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register.

Bit 5 = TOF Timer Overflow Flag.

0: No timer overflow (reset value).

1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR

(CLR) register.

Note: Reading or writing the ACLR register does not clear TOF.

Bit 4 = ICF2 Input Capture Flag 2.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R

(IC2LR) register.

Bit 3 = OCF2 Output Compare Flag 2.

0: No match (reset value).

1: The content of the free running counter has matched the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register.

Bit 2 = TIMD Timer disable.

This bit is set and cleared by software. When set, it freezes the timer prescaler and counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce power consumption. Access to the timer registers is still available, allowing the timer configuration to be changed, or the counter reset, while it is disabled.

0: Timer enabled

1: Timer prescaler, counter and outputs disabled

Bits 1:0 = Reserved, must be kept cleared.

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INPUT CAPTURE 1 HIGH REGISTER (IC1HR)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event).

7 0

MSB LSB

OUTPUT COMPARE 1 HIGH REGISTER

(OC1HR)

Read/Write

Reset Value: 1000 0000 (80h)

This is an 8-bit register that contains the high part of the value to be compared to the CHR register.

7 0

MSB LSB

INPUT CAPTURE 1 LOW REGISTER (IC1LR)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event).

7 0

MSB LSB

OUTPUT COMPARE 1 LOW REGISTER

(OC1LR)

Read/Write

Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of the value to be compared to the CLR register.

7 0

MSB LSB

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OUTPUT COMPARE 2 HIGH REGISTER

(OC2HR)

Read/Write

Reset Value: 1000 0000 (80h)

This is an 8-bit register that contains the high part of the value to be compared to the CHR register.

7 0

MSB LSB

ALTERNATE COUNTER HIGH REGISTER

(ACHR)

Read Only

Reset Value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part of the counter value.

7 0

MSB LSB

OUTPUT COMPARE 2 LOW REGISTER

(OC2LR)

Read/Write

Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of the value to be compared to the CLR register.

7 0

MSB LSB

ALTERNATE COUNTER LOW REGISTER

(ACLR)

Read Only

Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR register does not clear the TOF bit in the

CSR register.

7 0

MSB LSB

COUNTER HIGH REGISTER (CHR)

Read Only

Reset Value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part of the counter value.

7 0

MSB LSB

INPUT CAPTURE 2 HIGH REGISTER (IC2HR)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the high part of the counter value (transferred by the

Input Capture 2 event).

MSB

LSB COUNTER LOW REGISTER (CLR)

Read Only

Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the CSR register clears the TOF bit.

7 0

MSB LSB

INPUT CAPTURE 2 LOW REGISTER (IC2LR)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the low part of the counter value (transferred by the Input Capture 2 event).

MSB

LSB

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Table 17. 16-Bit Timer Register Map and Reset Values

Address

(Hex.)

Register

Label

CR1

Reset Value

CR2

Reset Value

CSR

Reset Value

IC1HR

Reset Value

IC1LR

Reset Value

OC1HR

Reset Value

OC1LR

Reset Value

OC2HR

Reset Value

OC2LR

Reset Value

CHR

Reset Value

CLR

Reset Value

ACHR

Reset Value

ACLR

Reset Value

IC2HR

Reset Value

IC2LR

Reset Value

Timer A: 32

Timer B: 42

Timer A: 31

Timer B: 41

Timer A: 33

Timer B: 43

Timer A: 34

Timer B: 44

Timer A: 35

Timer B: 45

Timer A: 36

Timer B: 46

Timer A: 37

Timer B: 47

Timer A: 3E

Timer B: 4E

Timer A: 3F

Timer B: 4F

Timer A: 38

Timer B: 48

Timer A: 39

Timer B: 49

Timer A: 3A

Timer B: 4A

Timer A: 3B

Timer B: 4B

Timer A: 3C

Timer B: 4C

Timer A: 3D

Timer B: 4D

MSB

MSB x

MSB

ICIE

OC1E

ICF1 x

MSB x

MSB

OCIE

OC2E

OCF1 x x x

1 x x

TOIE

OPM

TOF x x x

1 x x

FOLV2

PWM

ICF2 x x x

1 x x

Related Documentation

AN 973: SCI software communications using 16bit timer

AN 974: Real Time Clock with ST7 Timer Output

Compare

AN 976: Driving a buzzer through the ST7 Timer

PWM function

FOLV1

CC1

OCF2 x x x

1 x

OLVL2

CC0

TIMD

0 x x

1 x

IEDG1

IEDG2

x x x

0 x

LSB

LSB x

LSB

OLVL1

EXEDG

LSB x

LSB

1 x x x

AN1041: Using ST7 PWM signal to generate analog input (sinusoid)

AN1046: UART emulation software

AN1078: PWM duty cycle switch implementing true 0 or 100 per cent duty cycle

AN1504: Starting a PWM signal directly at high level using the ST7 16-Bit timer

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10.5 SERIAL PERIPHERAL INTERFACE (SPI)

10.5.1 Introduction

The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves however the SPI interface can not be a master in a multi-master system.

10.5.2 Main Features

■

Full duplex synchronous transfers (on 3 lines)

Simplex synchronous transfers (on 2 lines)

Master or slave operation

Six master mode frequencies (f

CPU

/4 max.) f

CPU

/2 max. slave mode frequency (see note)

SS Management by software or hardware

Programmable clock polarity and phase

End of transfer interrupt flag

Write collision, Master Mode Fault and Overrun flags

Figure 53. Serial Peripheral Interface Block Diagram

Note: In slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence.

10.5.3 General Description

Figure 53

shows the serial peripheral interface

(SPI) block diagram. There are 3 registers:

– SPI Control Register (SPICR)

– SPI Control/Status Register (SPICSR)

– SPI Data Register (SPIDR)

The SPI is connected to external devices through

4 pins:

– MISO: Master In / Slave Out data

– MOSI: Master Out / Slave In data

– SCK: Serial Clock out by SPI masters and input by SPI slaves

Data/Address Bus

Read

SPIDR

Read Buffer

Interrupt request

MOSI

MISO

8-Bit Shift Register

SPIF WCOL OVR MODF 0

SPICSR 0

SOD SSM SSI

Write

SOD bit

SCK

SPI

STATE

CONTROL

7 SPICR 0

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

MASTER

CONTROL

SERIAL CLOCK

GENERATOR

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SERIAL PERIPHERAL INTERFACE (Cont’d)

– SS: Slave select:

This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves individually and to avoid contention on the data lines. Slave SS inputs can be driven by standard I/O ports on the master MCU.

10.5.3.1 Functional Description

A basic example of interconnections between a single master and a single slave is illustrated in

Figure 54

The MOSI pins are connected together and the

MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first).

Figure 54. Single Master/ Single Slave Application

The communication is always initiated by the master. When the master device transmits data to a slave device via MOSI pin, the slave device responds by sending data to the master device via the MISO pin. This implies full duplex communication with both data out and data in synchronized with the same clock signal (which is provided by the master device via the SCK pin).

To use a single data line, the MISO and MOSI pins must be connected at each node ( in this case only simplex communication is possible).

Four possible data/clock timing relationships may

be chosen (see Figure 57

) but master and slave must be programmed with the same timing mode.

MASTER

MSBit LSBit

8-BIT SHIFT REGISTER

MISO

MOSI

MISO

MOSI

SLAVE

MSBit LSBit

8-BIT SHIFT REGISTER

SPI

CLOCK

GENERATOR

SCK

+5V

SCK

Not used if SS is managed

by software

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.3.2 Slave Select Management

As an alternative to using the SS pin to control the

Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM bit in the SPICSR register (see

Figure 56

)

In software management, the external SS pin is free for other application uses and the internal SS signal level is driven by writing to the SSI bit in the

SPICSR register.

In Master mode:

– SS internal must be held high continuously

In Slave Mode:

There are two cases depending on the data/clock

timing relationship (see Figure 55 ):

If CPHA=1 (data latched on 2nd clock edge):

– SS internal must be held low during the entire transmission. This implies that in single slave applications the SS pin either can be tied to

, or made free for standard I/O by managing the SS function by software (SSM= 1 and

SSI=0 in the in the SPICSR register)

If CPHA=0 (data latched on 1st clock edge):

– SS internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. If SS is not pulled high, a Write Collision error will occur when the slave writes to the

shift register (see Section 10.5.5.3

Figure 55. Generic SS Timing Diagram

MOSI/MISO

Master SS

Slave SS

(if CPHA=0)

Slave SS

(if CPHA=1)

Byte 1 Byte 2 Byte 3

Figure 56. Hardware/Software Slave Select Management

SSM bit

SSI bit

SS external pin

SS internal

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10.5.3.3 Master Mode Operation

In master mode, the serial clock is output on the

SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register).

Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if

CPOL=0).

To operate the SPI in master mode, perform the following steps in order (if the SPICSR register is not written first, the SPICR register setting (MSTR bit) may be not taken into account):

1. Write to the SPICR register:

– Select the clock frequency by configuring the

SPR[2:0] bits.

– Select the clock polarity and clock phase by

configuring the CPOL and CPHA bits. Figure

57 shows the four possible configurations.

Note: The slave must have the same CPOL and CPHA settings as the master.

2. Write to the SPICSR register:

– Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin high for the complete byte transmit sequence.

3. Write to the SPICR register:

– Set the MSTR and SPE bits

Note: MSTR and SPE bits remain set only if

SS is high).

The transmit sequence begins when software writes a byte in the SPIDR register.

10.5.3.4 Master Mode Transmit Sequence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most significant bit first.

When data transfer is complete:

– The SPIF bit is set by hardware

– An interrupt request is generated if the SPIE bit is set and the interrupt mask in the CCR register is cleared.

Clearing the SPIF bit is performed by the following software sequence:

1. An access to the SPICSR register while the

SPIF bit is set

2. A read to the SPIDR register.

Note: While the SPIF bit is set, all writes to the

SPIDR register are inhibited until the SPICSR register is read.

10.5.3.5 Slave Mode Operation

In slave mode, the serial clock is received on the

SCK pin from the master device.

To operate the SPI in slave mode:

1. Write to the SPICSR register to perform the following actions:

– Select the clock polarity and clock phase by configuring the CPOL and CPHA bits (see

Figure 57 ).

Note: The slave must have the same CPOL and CPHA settings as the master.

– Manage the SS pin as described in

condition (see Section 10.5.5.2

10.5.3.2

and

Figure 55

. If CPHA=1 SS must be held low continuously. If CPHA=0 SS must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register.

2. Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI I/O functions.

10.5.3.6 Slave Mode Transmit Sequence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MISO pin most significant bit first.

The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin.

When data transfer is complete:

– The SPIF bit is set by hardware

– An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR register is cleared.

Clearing the SPIF bit is performed by the following software sequence:

1. An access to the SPICSR register while the

SPIF bit is set.

2. A write or a read to the SPIDR register.

Notes: While the SPIF bit is set, all writes to the

SPIDR register are inhibited until the SPICSR register is read.

The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.4 Clock Phase and Clock Polarity

Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See

Figure 57

Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if

CPOL=0).

The combination of the CPOL clock polarity and

CPHA (clock phase) bits selects the data capture clock edge

Figure 57. Data Clock Timing Diagram

CPHA =1

Figure 57 , shows an SPI transfer with the four

combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly connected between the master and the slave device.

Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit.

SCK

(CPOL = 1)

SCK

(CPOL = 0)

MISO

(from master)

MSBit Bit 6

MOSI

(from slave)

(to slave)

CAPTURE STROBE

MSBit Bit 6

Bit 5 Bit 4

Bit3 Bit 2 Bit 1 LSBit

CPHA =0

SCK

(CPOL = 1)

SCK

(CPOL = 0)

MISO

(from master)

MOSI

(from slave)

MSBit

Bit 6

Bit 5

Bit 4

Bit3

Bit 2

Bit 1

(to slave)

CAPTURE STROBE

Note: This figure should not be used as a replacement for parametric information.

Refer to the Electrical Characteristics chapter.

LSBit

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10.5.5 Error Flags

10.5.5.1 Master Mode Fault (MODF)

Master mode fault occurs when the master device has its SS pin pulled low.

When a Master mode fault occurs:

– The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set.

– The SPE bit is reset. This blocks all output from the device and disables the SPI peripheral.

– The MSTR bit is reset, thus forcing the device into slave mode.

Clearing the MODF bit is done through a software sequence:

1. A read access to the SPICSR register while the

MODF bit is set.

2. A write to the SPICR register.

Notes: To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high during the MODF bit clearing sequence. The

SPE and MSTR bits may be restored to their original state during or after this clearing sequence.

Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence.

10.5.5.2 Overrun Condition (OVR)

An overrun condition occurs, when the master device has sent a data byte and the slave device has not cleared the SPIF bit issued from the previously transmitted byte.

When an Overrun occurs:

– The OVR bit is set and an interrupt request is generated if the SPIE bit is set.

In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the SPIDR register returns this byte. All other bytes are lost.

The OVR bit is cleared by reading the SPICSR register.

10.5.5.3 Write Collision Error (WCOL)

A write collision occurs when the software tries to write to the SPIDR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and the software write will be unsuccessful.

Write collisions can occur both in master and slave mode. See also

Section 10.5.3.2 Slave Select

Management

Note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the MCU operation.

The WCOL bit in the SPICSR register is set if a write collision occurs.

No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only).

Clearing the WCOL bit is done through a software

sequence (see Figure 58 ).

Figure 58. Clearing the WCOL bit (Write Collision Flag) Software Sequence

Clearing sequence after SPIF = 1 (end of a data byte transfer)

Read SPICSR

1st Step

2nd Step

Read SPIDR

RESULT

SPIF =0

WCOL=0

Clearing sequence before SPIF = 1 (during a data byte transfer)

Read SPICSR

1st Step

2nd Step Read SPIDR

RESULT

WCOL=0

Note: Writing to the SPIDR register instead of reading it does not reset the WCOL bit

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.5.4 Single Master Systems

A typical single master system may be configured, using an MCU as the master and four MCUs as slaves (see

Figure 59

The master device selects the individual slave devices by using four pins of a parallel port to control the four SS pins of the slave devices.

The SS pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices.

Note: To prevent a bus conflict on the MISO line the master allows only one active slave device during a transmission.

For more security, the slave device may respond to the master with the received data byte. Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are connected and the slave has not written to its SPIDR register.

Other transmission security methods can use ports for handshake lines or data bytes with command fields.

Figure 59. Single Master / Multiple Slave Configuration

SCK

Slave

MCU

MOSI MISO

SCK

Slave

MCU

MOSI MISO

SCK

Slave

MCU

MOSI MISO

SCK

Slave

MCU

MOSI MISO

SCK

Master

MCU

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.6 Low Power Modes

Mode Description

WAIT

HALT

No effect on SPI.

SPI interrupt events cause the device to exit from WAIT mode.

SPI registers are frozen.

In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with “exit from HALT mode” capability. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetching). If several data are received before the wakeup event, then an overrun error is generated.

This error can be detected after the fetch of the interrupt routine that woke up the device.

Note: When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to perform an extra communications cycle to bring the

SPI from Halt mode state to normal state. If the

SPI exits from Slave mode, it returns to normal state immediately.

Caution: The SPI can wake up the ST7 from Halt mode only if the Slave Select signal (external SS pin or the SSI bit in the SPICSR register) is low when the ST7 enters Halt mode. So if Slave selection is configured as external (see

Section 10.5.5.1 Master Mode Fault

10.5.3.2

), make sure the master drives a low level on the SS pin when the slave enters Halt mode.

10.5.7 Interrupts

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit from

Wait

Exit from

Halt

10.5.6.1 Using the SPI to wakeup the MCU from

Halt mode

In slave configuration, the SPI is able to wakeup the ST7 device from HALT mode through a SPIF interrupt. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetch). If multiple data transfers have been performed before software clears the SPIF bit, then the OVR bit is set by hardware.

SPI End of Transfer

Event

Master Mode Fault

Event

Overrun Error

SPIF

MODF

OVR

SPIE

Yes

Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter).

They generate an interrupt if the corresponding

Enable Control Bit is set and the interrupt mask in

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.8 Register Description

CONTROL REGISTER (SPICR)

Read/Write

Reset Value: 0000 xxxx (0xh)

7 0

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

Bit 7 = SPIE Serial Peripheral Interrupt Enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SPI interrupt is generated whenever

SPIF=1, MODF=1 or OVR=1 in the SPICSR register

Bit 3 = CPOL Clock Polarity.

This bit is set and cleared by software. This bit determines the idle state of the serial Clock. The

CPOL bit affects both the master and slave modes.

0: SCK pin has a low level idle state

1: SCK pin has a high level idle state

Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit.

Bit 2 = CPHA Clock Phase.

This bit is set and cleared by software.

0: The first clock transition is the first data capture edge.

1: The second clock transition is the first capture edge.

Note: The slave must have the same CPOL and

CPHA settings as the master.

Bit 6 = SPE Serial Peripheral Output Enable.

This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0

(see

(MODF) ). The SPE bit is cleared by reset, so the

SPI peripheral is not initially connected to the external pins.

0: I/O pins free for general purpose I/O

1: SPI I/O pin alternate functions enabled

Bit 5 = SPR2 Divider Enable.

This bit is set and cleared by software and is cleared by reset. It is used with the SPR[1:0] bits to set the baud rate. Refer to

Table 18 SPI Master mode SCK Frequency

0: Divider by 2 enabled

1: Divider by 2 disabled

Note: This bit has no effect in slave mode.

Bit 4 = MSTR Master Mode.

This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0

(see

Section 10.5.5.1 Master Mode Fault

(MODF) ).

0: Slave mode

1: Master mode. The function of the SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are reversed.

Bits 1:0 = SPR[1:0] Serial Clock Frequency.

These bits are set and cleared by software. Used with the SPR2 bit, they select the baud rate of the

SPI serial clock SCK output by the SPI in master mode.

Note: These 2 bits have no effect in slave mode.

Table 18. SPI Master mode SCK Frequency

Serial Clock f

CPU

/4 f

CPU

/8 f

CPU

/16 f

CPU

/32 f

CPU

/64 f

CPU

/128

SPR2 SPR1 SPR0

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SERIAL PERIPHERAL INTERFACE (Cont’d)

CONTROL/STATUS REGISTER (SPICSR)

Read/Write (some bits Read Only)

Reset Value: 0000 0000 (00h)

7 0

SPIF WCOL OVR MODF SOD SSM SSI

Bit 7 = SPIF Serial Peripheral Data Transfer Flag

(Read only).

This bit is set by hardware when a transfer has been completed. An interrupt is generated if

SPIE=1 in the SPICR register. It is cleared by a software sequence (an access to the SPICSR register followed by a write or a read to the

SPIDR register).

0: Data transfer is in progress or the flag has been cleared.

1: Data transfer between the device and an external device has been completed.

Note: While the SPIF bit is set, all writes to the

SPIDR register are inhibited until the SPICSR register is read.

Bit 6 = WCOL Write Collision status (Read only).

This bit is set by hardware when a write to the

SPIDR register is done during a transmit sequence. It is cleared by a software sequence (see

Figure 58

0: No write collision occurred

1: A write collision has been detected

Bit 5 = OVR SPI Overrun error (Read only).

This bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the SPIDR register while SPIF = 1

(See Section 10.5.5.2

). An interrupt is generated if

SPIE = 1 in SPICR register. The OVR bit is cleared by software reading the SPICSR register.

0: No overrun error

1: Overrun error detected

Bit 4 = MODF Mode Fault flag (Read only).

This bit is set by hardware when the SS pin is pulled low in master mode (see

Master Mode Fault (MODF)

0: No master mode fault detected

Section 10.5.5.1

). An SPI interrupt can be generated if SPIE=1 in the SPICSR register.

This bit is cleared by a software sequence (An access to the SPICR register while MODF=1 followed by a write to the SPICR register).

1: A fault in master mode has been detected

Bit 3 = Reserved, must be kept cleared.

Bit 2 = SOD SPI Output Disable.

This bit is set and cleared by software. When set, it disables the alternate function of the SPI output

(MOSI in master mode / MISO in slave mode)

0: SPI output enabled (if SPE=1)

1: SPI output disabled

Bit 1 = SSM SS Management.

This bit is set and cleared by software. When set, it disables the alternate function of the SPI SS pin and uses the SSI bit value instead. See

10.5.3.2 Slave Select Management

0: Hardware management (SS managed by external pin)

1: Software management (internal SS signal controlled by SSI bit. External SS pin free for general-purpose I/O)

Bit 0 = SSI SS Internal Mode.

This bit is set and cleared by software. It acts as a

‘chip select’ by controlling the level of the SS slave select signal when the SSM bit is set.

0 : Slave selected

1 : Slave deselected

DATA I/O REGISTER (SPIDR)

Read/Write

Reset Value: Undefined

D7 D6 D5 D4 D3 D2 D1

The SPIDR register is used to transmit and receive data on the serial bus. In a master device, a write to this register will initiate transmission/reception of another byte.

Notes: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read.

While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read.

Warning: A write to the SPIDR register places data directly into the shift register for transmission.

A read to the SPIDR register returns the value located in the buffer and not the content of the shift

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SERIAL PERIPHERAL INTERFACE (Cont’d)

Table 19. SPI Register Map and Reset Values

Address

(Hex.)

0021h

0022h

0023h

Register

Label

SPIDR

Reset Value

SPICR

Reset Value

SPICSR

Reset Value

MSB x

SPIE

SPIF

6 x

SPE

WCOL

5 x

SPR2

4 x

MSTR

MODF

3 2 x

CPOL x

0 x

CPHA x

SOD

1 x

SPR1 x

SSM

LSB x

SPR0 x

SSI

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10.6 SERIAL COMMUNICATIONS INTERFACE (SCI)

■

10.6.1 Introduction

The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard

NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems.

10.6.2 Main Features

■

Full duplex, asynchronous communications

NRZ standard format (Mark/Space)

Dual baud rate generator systems

Independently programmable transmit and receive baud rates up to 500K baud.

Programmable data word length (8 or 9 bits)

Receive buffer full, Transmit buffer empty and

End of Transmission flags

Two receiver wake-up modes:

■

– Address bit (MSB)

– Idle line

Muting function for multiprocessor configurations

Separate enable bits for Transmitter and

Receiver

Four error detection flags:

– Overrun error

■

– Noise error

– Frame error

– Parity error

Five interrupt sources with flags:

– Transmit data register empty

– Transmission complete

– Receive data register full

– Idle line received

– Overrun error detected

Parity control:

– Transmits parity bit

– Checks parity of received data byte

Reduced power consumption mode

10.6.3 General Description

The interface is externally connected to another device by two pins (see

Figure 61

– TDO: Transmit Data Output. When the transmitter and the receiver are disabled, the output pin returns to its I/O port configuration. When the transmitter and/or the receiver are enabled and nothing is to be transmitted, the TDO pin is at high level.

– RDI: Receive Data Input is the serial data input.

Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise.

Through these pins, serial data is transmitted and received as frames comprising:

– An Idle Line prior to transmission or reception

– A start bit

– A data word (8 or 9 bits) least significant bit first

– A Stop bit indicating that the frame is complete.

This interface uses two types of baud rate generator:

– A conventional type for commonly-used baud rates,

– An extended type with a prescaler offering a very wide range of baud rates even with non-standard oscillator frequencies.

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

Figure 60. SCI Block Diagram

Write

Transmit Data Register (TDR)

Read

(DATA REGISTER) DR

Received Data Register (RDR)

TDO

RDI

Transmit Shift Register Received Shift Register

CR1

R8 T8 SCID M WAKE PCE PS PIE

TRANSMIT

CONTROL

WAKE

UNIT

CR2

TIE TCIE RIE ILIE TE RE RWU SBK

SCI

INTERRUPT

CONTROL

TRANSMITTER

CLOCK f

CPU

/16 /PR

RECEIVER

CONTROL

RECEIVER

CLOCK

TDRE TC RDRF IDLE OR NF FE PE

TRANSMITTER RATE

CONTROL

BRR

SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0

RECEIVER RATE

CONTROL

CONVENTIONAL BAUD RATE GENERATOR

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.4 Functional Description

The block diagram of the Serial Control Interface,

is shown in Figure 60

. It contains 6 dedicated registers:

– Two control registers (SCICR1 & SCICR2)

– A status register (SCISR)

– A baud rate register (SCIBRR)

– An extended prescaler receiver register (SCIER-

PR)

– An extended prescaler transmitter register (SCI-

ETPR)

Refer to the register descriptions in

10.6.7

for the definitions of each bit.

10.6.4.1 Serial Data Format

Word length may be selected as being either 8 or 9 bits by programming the M bit in the SCICR1 register (see

Figure 60

The TDO pin is in low state during the start bit.

The TDO pin is in high state during the stop bit.

An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next frame which contains data.

A Break character is interpreted on receiving “0”s for some multiple of the frame period. At the end of the last break frame the transmitter inserts an extra “1” bit to acknowledge the start bit.

Transmission and reception are driven by their own baud rate generator.

Figure 61. Word Length Programming

9-bit Word length (M bit is set)

Start

Bit Bit0 Bit1

Data Frame

Bit2 Bit3 Bit4 Bit5 Bit6 Bit7

Possible

Parity

Bit

Bit8

Next Data Frame

Stop

Bit

Start

Bit

Idle Frame

Start

Bit

Break Frame Extra

’1’

Start

Bit

8-bit Word length (M bit is reset)

Start

Bit Bit0

Data Frame

Bit1 Bit2 Bit3 Bit4 Bit5 Bit6

Possible

Parity

Bit

Bit7

Stop

Bit

Next Data Frame

Start

Bit

Idle Frame

Break Frame

Start

Bit

Extra

’1’

Start

Bit

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.4.2 Transmitter

The transmitter can send data words of either 8 or

9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the

MSB) has to be stored in the T8 bit in the SCICR1 register.

Character Transmission

During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see

Figure 60

Procedure

– Select the M bit to define the word length.

– Select the desired baud rate using the SCIBRR and the SCIETPR registers.

– Set the TE bit to assign the TDO pin to the alternate function and to send a idle frame as first transmission.

– Access the SCISR register and write the data to send in the SCIDR register (this sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted.

Clearing the TDRE bit is always performed by the following software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register

The TDRE bit is set by hardware and it indicates:

– The TDR register is empty.

– The data transfer is beginning.

– The next data can be written in the SCIDR register without overwriting the previous data.

This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR register.

When a transmission is taking place, a write instruction to the SCIDR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission.

When no transmission is taking place, a write instruction to the SCIDR register places the data directly in the shift register, the data transmission starts, and the TDRE bit is immediately set.

When a frame transmission is complete (after the stop bit or after the break frame) the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CCR register.

Clearing the TC bit is performed by the following software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register

Note: The TDRE and TC bits are cleared by the same software sequence.

Break Characters

Setting the SBK bit loads the shift register with a break character. The break frame length depends on the M bit (see

Figure 61

As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame.

Idle Characters

Setting the TE bit drives the SCI to send an idle frame before the first data frame.

Clearing and then setting the TE bit during a transmission sends an idle frame after the current word.

Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set i.e. before writing the next byte in the SCIDR.

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10.6.4.3 Receiver

The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the SCICR1 register.

Character reception

During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, the

SCIDR register consists or a buffer (RDR) between the internal bus and the received shift register (see

Figure 60

Procedure

– Select the M bit to define the word length.

– Select the desired baud rate using the SCIBRR and the SCIERPR registers.

– Set the RE bit, this enables the receiver which begins searching for a start bit.

When a character is received:

– The RDRF bit is set. It indicates that the content of the shift register is transferred to the RDR.

– An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register.

– The error flags can be set if a frame error, noise or an overrun error has been detected during reception.

Clearing the RDRF bit is performed by the following software sequence done by:

1. An access to the SCISR register

2. A read to the SCIDR register.

The RDRF bit must be cleared before the end of the reception of the next character to avoid an overrun error.

Break Character

When a break character is received, the SPI handles it as a framing error.

Idle Character

When a idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register.

Overrun Error

An overrun error occurs when a character is received when RDRF has not been reset. Data can not be transferred from the shift register to the

RDR register as long as the RDRF bit is not cleared.

When a overrun error occurs:

– The OR bit is set.

– The RDR content will not be lost.

– The shift register will be overwritten.

– An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register.

The OR bit is reset by an access to the SCISR register followed by a SCIDR register read operation.

Noise Error

Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Normal data bits are considered valid if three consecutive samples (8th, 9th, 10th) have the same bit value, otherwise the NF flag is set. In the case of start bit detection, the NF flag is set on the basis of an algorithm combining both valid edge detection and three samples (8th, 9th, 10th).

Therefore, to prevent the NF flag getting set during start bit reception, there should be a valid edge detection as well as three valid samples.

When noise is detected in a frame:

– The NF flag is set at the rising edge of the RDRF bit.

– Data is transferred from the Shift register to the

SCIDR register.

– No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt.

The NF flag is reset by a SCISR register read operation followed by a SCIDR register read operation.

During reception, if a false start bit is detected (e.g.

8th, 9th, 10th samples are 011,101,110), the frame is discarded and the receiving sequence is not started for this frame. There is no RDRF bit set for this frame and the NF flag is set internally (not accessible to the user). This NF flag is accessible along with the RDRF bit when a next valid frame is received.

Note: If the application Start Bit is not long enough to match the above requirements, then the NF

Flag may get set due to the short Start Bit. In this case, the NF flag may be ignored by the application software when the first valid byte is received.

See also description of Noise error in

from the 16 divider (see Figure 62

10.6.4.3

Start bit

The noise flag (NF) is set during start bit reception if one of the following conditions occurs:

1. A valid falling edge is not detected. A falling edge is considered to be valid if the 3 consecutive samples before the falling edge occurs are detected as '1' and, after the falling edge occurs, during the sampling of the 16 samples, if one of the samples numbered 3, 5 or 7 is detected as a “1”.

2. During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is detected as a

“1”.

Therefore, a valid Start Bit must satisfy both the above conditions to prevent the Noise Flag getting set.

Data Bits

The noise flag (NF) is set during normal data bit reception if the following condition occurs:

– During the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not the same.

The majority of the 8th, 9th and 10th samples is considered as the bit value.

Therefore, a valid Data Bit must have samples 8, 9 and 10 at the same value to prevent the Noise

Flag getting set.

Figure 63. Bit Sampling in Reception Mode

RDI LINE

Sample

clock sampled values

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

7/16

6/16

7/16

One bit time

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.5 Low Power Modes

Mode Description

No effect on SCI.

WAIT SCI interrupts cause the device to exit from Wait mode.

SCI registers are frozen.

HALT

In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.

10.6.6 Interrupts

The SCI interrupt events are connected to the same interrupt vector.

These events generate an interrupt if the corresponding Enable Control Bit is set and the inter-

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit from

Wait

Transmit Data Register

Empty

Transmission Complete

TDRE

TIE

TCIE

Received Data Ready to be Read

RDRF

RIE

Overrun Error Detected OR

Idle Line Detected IDLE ILIE

Parity Error PE PIE

Yes

Exit from

Halt

No rupt mask in the CC register is reset (RIM instruction).

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10.6.7 Register Description

STATUS REGISTER (SCISR)

Read Only

Reset Value: 1100 0000 (C0h)

Note: The IDLE bit will not be set again until the

RDRF bit has been set itself (i.e. a new idle line occurs).

TDRE TC RDRF IDLE OR NF FE

Bit 7 = TDRE Transmit data register empty.

This bit is set by hardware when the content of the

TDR register has been transferred into the shift register. An interrupt is generated if the TIE bit=1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a write to the SCIDR register).

0: Data is not transferred to the shift register

1: Data is transferred to the shift register

Note: Data will not be transferred to the shift register unless the TDRE bit is cleared.

Bit 3 = OR Overrun error.

This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RDRF=1.

An interrupt is generated if RIE=1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register).

0: No Overrun error

1: Overrun error is detected

Note: When this bit is set RDR register content will not be lost but the shift register will be overwritten.

Bit 6 = TC Transmission complete.

This bit is set by hardware when transmission of a frame containing Data is complete. An interrupt is generated if TCIE=1 in the SCICR2 register. It is cleared by a software sequence (an access to the

SCISR register followed by a write to the SCIDR register).

0: Transmission is not complete

1: Transmission is complete

Note: TC is not set after the transmission of a Preamble or a Break.

Bit 2 = NF Noise flag.

This bit is set by hardware when noise is detected on a received frame. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register).

0: No noise is detected

1: Noise is detected

Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt.

Bit 5 = RDRF Received data ready flag.

This bit is set by hardware when the content of the

RDR register has been transferred to the SCIDR register. An interrupt is generated if RIE=1 in the

SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register).

0: Data is not received

1: Received data is ready to be read

Bit 1 = FE Framing error.

This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register).

0: No Framing error is detected

1: Framing error or break character is detected

Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. If the word currently being transferred causes both frame error and overrun error, it will be transferred and only the OR bit will be set.

Bit 4 = IDLE Idle line detect.

This bit is set by hardware when a Idle Line is detected. An interrupt is generated if the ILIE=1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register).

0: No Idle Line is detected

1: Idle Line is detected

Bit 0 = PE Parity error.

This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by a software sequence (a read to the status register followed by an access to the SCIDR data register). An interrupt is generated if PIE=1 in the SCICR1 register.

0: No parity error

1: Parity error

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CONTROL REGISTER 1 (SCICR1)

Read/Write

Reset Value: x000 0000 (x0h)

7 0

Bit 3 = WAKE Wake-Up method.

This bit determines the SCI Wake-Up method, it is set or cleared by software.

0: Idle Line

1: Address Mark

R8 T8 SCID M WAKE PCE PS PIE

Bit 7 = R8 Receive data bit 8.

This bit is used to store the 9th bit of the received word when M=1.

Bit 6 = T8 Transmit data bit 8.

This bit is used to store the 9th bit of the transmitted word when M=1.

Bit 2 = PCE Parity control enable.

This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission).

0: Parity control disabled

1: Parity control enabled

Bit 5 = SCID Disabled for low power consumption

When this bit is set the SCI prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.This bit is set and cleared by software.

0: SCI enabled

1: SCI prescaler and outputs disabled

Bit 1 = PS Parity selection.

This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity will be selected after the current byte.

0: Even parity

1: Odd parity

Bit 4 = M Word length.

This bit determines the word length. It is set or cleared by software.

0: 1 Start bit, 8 Data bits, 1 Stop bit

1: 1 Start bit, 9 Data bits, 1 Stop bit

Note: The M bit must not be modified during a data transfer (both transmission and reception).

Bit 0 = PIE Parity interrupt enable.

This bit enables the interrupt capability of the hardware parity control when a parity error is detected

(PE bit set). It is set and cleared by software.

0: Parity error interrupt disabled

1: Parity error interrupt enabled.

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CONTROL REGISTER 2 (SCICR2)

Read/Write

Reset Value: 0000 0000 (00h)

TIE TCIE RIE ILIE TE RE RWU

SBK

Notes:

– During transmission, a “0” pulse on the TE bit

(“0” followed by “1”) sends a preamble (idle line) after the current word.

– When TE is set there is a 1 bit-time delay before the transmission starts.

Caution: The TDO pin is free for general purpose

I/O only when the TE and RE bits are both cleared

(or if TE is never set).

Bit 7 = TIE Transmitter interrupt enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever

TDRE=1 in the SCISR register

Bit 6 = TCIE Transmission complete interrupt ena- ble

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever TC=1 in the SCISR register

Bit 2 = RE Receiver enable.

This bit enables the receiver. It is set and cleared by software.

0: Receiver is disabled

1: Receiver is enabled and begins searching for a start bit

Bit 5 = RIE Receiver interrupt enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever OR=1 or RDRF=1 in the SCISR register

Bit 1 = RWU Receiver wake-up.

This bit determines if the SCI is in mute mode or not. It is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized.

0: Receiver in Active mode

1: Receiver in Mute mode

Note: Before selecting Mute mode (setting the

RWU bit), the SCI must receive some data first, otherwise it cannot function in Mute mode with wakeup by idle line detection.

Bit 4 = ILIE Idle line interrupt enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever IDLE=1 in the SCISR register.

Bit 3 = TE Transmitter enable.

This bit enables the transmitter. It is set and cleared by software.

0: Transmitter is disabled

1: Transmitter is enabled

Bit 0 = SBK Send break.

This bit set is used to send break characters. It is set and cleared by software.

0: No break character is transmitted

1: Break characters are transmitted

Note: If the SBK bit is set to “1” and then to “0”, the transmitter will send a BREAK word at the end of the current word.

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DATA REGISTER (SCIDR)

Read/Write

Reset Value: Undefined

Contains the Received or Transmitted data character, depending on whether it is read from or written to.

Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor

These 3 bits, in conjunction with the SCP1 & SCP0 bits define the total division applied to the bus clock to yield the transmit rate clock in conventional Baud Rate Generator mode.

(RDR).

DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0

The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception

The TDR register provides the parallel interface between the internal bus and the output shift register (see

Figure 60 ).

The RDR register provides the parallel interface between the input shift register and the internal

bus (see Figure 60 ).

TR dividing factor

128

Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.

These 3 bits, in conjunction with the SCP[1:0] bits define the total division applied to the bus clock to yield the receive rate clock in conventional Baud

Rate Generator mode.

SCT2

SCT1

SCT0

BAUD RATE REGISTER (SCIBRR)

Read/Write

Reset Value: 0000 0000 (00h)

7 clock division ranges:

SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0

Bits 7:6= SCP[1:0] First SCI Prescaler

These 2 prescaling bits allow several standard

RR Dividing factor

128

SCR2

SCR1

SCR0

PR Prescaling factor

SCP1

SCP0

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EXTENDED RECEIVE PRESCALER DIVISION

REGISTER (SCIERPR)

Read/Write

Reset Value: 0000 0000 (00h)

Allows setting of the Extended Prescaler rate division factor for the receive circuit.

EXTENDED TRANSMIT PRESCALER DIVISION

REGISTER (SCIETPR)

Read/Write

Reset Value:0000 0000 (00h)

Allows setting of the External Prescaler rate division factor for the transmit circuit.

7 0

ERPR

7 0

ETPR

Bits 7:0 = ERPR[7:0] 8-bit Extended Receive

Prescaler Register.

The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued

) is divided by the binary factor set in the SCIERPR register (in the range 1 to 255).

The extended baud rate generator is not used after a reset.

Table 21. Baudrate Selection

Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit

Prescaler Register.

The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued

from the 16 divider (see Figure 62

) is divided by the binary factor set in the SCIETPR register (in the range 1 to 255).

The extended baud rate generator is not used after a reset.

Symbol f f

Parameter f

CPU

Communication frequency 8MHz

Conditions

Accuracy vs. Standard

Prescaler

~0.16%

~0.79%

Conventional Mode

TR (or RR)=128, PR=13

TR (or RR)= 32, PR=13

TR (or RR)= 16, PR=13

TR (or RR)= 8, PR=13

TR (or RR)= 4, PR=13

TR (or RR)= 16, PR= 3

TR (or RR)= 2, PR=13

TR (or RR)= 1, PR=13

Extended Mode

ETPR (or ERPR) = 35,

TR (or RR)= 1, PR=1

Standard

Baud

Rate

300

1200

2400

4800

9600

10400

19200

38400

~300.48

~1201.92

~2403.84

~4807.69

~9615.38

~10416.67

~19230.77

~38461.54

14400 ~14285.71

Unit

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Table 22. SCI Register Map and Reset Values

Address

(Hex.)

0050h

0051h

0052h

0053h

0054h

0055h

0057h

Register

Label

SCISR

Reset Value

SCIDR

Reset Value

SCIBRR

Reset Value

SCICR1

Reset Value

SCICR2

Reset Value

SCIERPR

Reset Value

SCIPETPR

Reset Value

TDRE

MSB x

SCP1

R8 x

TIE

MSB

1 x

SCP0

TCIE

RDRF

0 x

SCT2

SCID

RIE

IDLE

0 x

SCT1

ILIE

0 x

SCT0

WAKE

0 x

SCR2

PCE

0 x

SCR1

RWU

LSB x

SCR0

PIE

SBK

LSB

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10.7 I

C BUS INTERFACE (I2C)

10.7.1 Introduction

The I

C Bus Interface serves as an interface between the microcontroller and the serial I

C bus. It provides both multimaster and slave functions, and controls all I

C bus-specific sequencing, protocol, arbitration and timing. It supports fast I

C mode (400kHz).

10.7.2 Main Features

■ Parallel-bus/I

C protocol converter

■

Multi-master capability

7-bit/10-bit Addressing

■

SMBus V1.1 Compliant

Transmitter/Receiver flag

■ End-of-byte transmission flag

■ Transfer problem detection

C Master Features:

■

Clock generation

C bus busy flag

Arbitration Lost Flag

■

End of byte transmission flag

Transmitter/Receiver Flag

■

Start bit detection flag

■ Start and Stop generation

C Slave Features:

Stop bit detection

C bus busy flag

■

Detection of misplaced start or stop condition

Programmable I

C Address detection

Transfer problem detection

End-of-byte transmission flag

Transmitter/Receiver flag

10.7.3 General Description

In addition to receiving and transmitting data, this interface converts it from serial to parallel format

Figure 64. I

C BUS Protocol

SDA

MSB and vice versa, using either an interrupt or polled handshake. The interrupts are enabled or disabled by software. The interface is connected to the I

C bus by a data pin (SDAI) and by a clock pin (SCLI).

It can be connected both with a standard I

C bus and a Fast I

C bus. This selection is made by software.

Mode Selection

The interface can operate in the four following modes:

– Slave transmitter/receiver

– Master transmitter/receiver

By default, it operates in slave mode.

The interface automatically switches from slave to master after it generates a START condition and from master to slave in case of arbitration loss or a

STOP generation, allowing then Multi-Master capability.

Communication Flow

In Master mode, it initiates a data transfer and generates the clock signal. A serial data transfer always begins with a start condition and ends with a stop condition. Both start and stop conditions are generated in master mode by software.

In Slave mode, the interface is capable of recognising its own address (7 or 10-bit), and the General Call address. The General Call address detection may be enabled or disabled by software.

Data and addresses are transferred as 8-bit bytes,

MSB first. The first byte(s) following the start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is always transmitted in Master mode.

A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer to

Figure 64

ACK

SCL

1 2 8 9

START

CONDITION

STOP

CONDITION

VR02119B

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Acknowledge may be enabled and disabled by software.

The I

C interface address and/or general call address can be selected by software.

The speed of the I

C interface may be selected between Standard (up to 100KHz) and Fast I

(up to 400KHz).

The SCL frequency (F scl

) is controlled by a pro-

I grammable clock divider which depends on the

C bus mode.

When the I

C cell is enabled, the SDA and SCL ports must be configured as floating inputs. In this case, the value of the external pull-up resistor used depends on the application.

When the I

C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins.

SDA/SCL Line Control

Transmitter mode: the interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the Data Register.

Receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the Data Register.

Figure 65. I

C Interface Block Diagram

DATA REGISTER (DR)

SDA or SDAI

DATA CONTROL

DATA SHIFT REGISTER

COMPARATOR

OWN ADDRESS REGISTER 1 (OAR1)

OWN ADDRESS REGISTER 2 (OAR2)

SCL or SCLI

CLOCK CONTROL

CLOCK CONTROL REGISTER (CCR)

CONTROL REGISTER (CR)

STATUS REGISTER 1 (SR1)

STATUS REGISTER 2 (SR2)

CONTROL LOGIC

INTERRUPT

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10.7.4 Functional Description

Refer to the CR, SR1 and SR2 registers in

10.7.7

. for the bit definitions.

By default the I

C interface operates in Slave mode (M/SL bit is cleared) except when it initiates a transmit or receive sequence.

First the interface frequency must be configured using the FRi bits in the OAR2 register.

10.7.4.1 Slave Mode

As soon as a start condition is detected, the address is received from the SDA line and sent to the shift register; then it is compared with the address of the interface or the General Call address (if selected by software).

Note: In 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and the two most significant bits of the address.

Header matched (10-bit mode only): the interface generates an acknowledge pulse if the ACK bit is set.

Address not matched: the interface ignores it and waits for another Start condition.

Address matched: the interface generates in sequence:

– Acknowledge pulse if the ACK bit is set.

– EVF and ADSL bits are set with an interrupt if the

ITE bit is set.

Then the interface waits for a read of the SR1 register, holding the SCL line low (see

Transfer sequencing EV1).

Next, in 7-bit mode read the DR register to determine from the least significant bit (Data Direction

Bit) if the slave must enter Receiver or Transmitter mode.

In 10-bit mode, after receiving the address sequence the slave is always in receive mode. It will enter transmit mode on receiving a repeated Start condition followed by the header sequence with matching address bits and the least significant bit set (11110xx1).

Slave Receiver

Following the address reception and after SR1 register has been read, the slave receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence:

– Acknowledge pulse if the ACK bit is set

– EVF and BTF bits are set with an interrupt if the

ITE bit is set.

Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding

the SCL line low (see

Figure 66 Transfer sequencing

Transfer sequencing EV2).

Slave Transmitter

Following the address reception and after SR1 register has been read, the slave sends bytes from the DR register to the SDA line via the internal shift register.

The slave waits for a read of the SR1 register followed by a write in the DR register, holding the

SCL line low (see

EV3).

When the acknowledge pulse is received:

– The EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.

Closing slave communication

After the last data byte is transferred a Stop Condition is generated by the master. The interface detects this condition and sets:

– EVF and STOPF bits with an interrupt if the ITE bit is set.

Then the interface waits for a read of the SR2 register (see

ple set PE bit), holding the SCL line low (see Figure 66

Transfer sequencing EV4).

Error Cases

– BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and the BERR bits are set with an interrupt if the ITE bit is set.

If it is a Stop then the interface discards the data, released the lines and waits for another Start condition.

If it is a Start then the interface discards the data and waits for the next slave address on the bus.

– AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with an interrupt if the ITE bit is set.

The AF bit is cleared by reading the I2CSR2 register. However, if read before the completion of the transmission, the AF flag will be set again, thus possibly generating a new interrupt. Software must ensure either that the SCL line is back at 0 before reading the SR2 register, or be able to correctly handle a second interrupt during the

9th pulse of a transmitted byte.

Note: In case of errors, SCL line is not held low; however, the SDA line can remain low if the last bits transmitted are all 0. While AF=1, the SCL line may be held low due to SB or BTF flags that are set at the same time. It is then necessary to release both lines by software.

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C INTERFACE (Cont’d)

How to release the SDA / SCL lines

Set and subsequently clear the STOP bit while

BTF is set. The SDA/SCL lines are released after the transfer of the current byte.

Then the second address byte is sent by the interface.

SMBus Compatibility

ST7 I

C is compatible with SMBus V1.1 protocol. It supports all SMBus adressing modes, SMBus bus protocols and CRC-8 packet error checking. Refer to AN1713: SMBus Slave Driver For ST7 I

C Peripheral.

After completion of this transfer (and acknowledge from the slave if the ACK bit is set):

– The EVF bit is set by hardware with interrupt generation if the ITE bit is set.

Then the master waits for a read of the SR1 register followed by a write in the CR register (for exam-

Transfer sequencing EV6).

10.7.4.2 Master Mode

To switch from default Slave mode to Master mode a Start condition generation is needed.

Start condition

Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master mode (M/SL bit set) and generates a Start condition.

Once the Start condition is sent:

– The EVF and SB bits are set by hardware with an interrupt if the ITE bit is set.

Then the master waits for a read of the SR1 register followed by a write in the DR register with the

Slave address, holding the SCL line low (see

Transfer sequencing EV5).

Slave address transmission

Then the slave address is sent to the SDA line via the internal shift register.

In 7-bit addressing mode, one address byte is sent.

In 10-bit addressing mode, sending the first byte including the header sequence causes the following event:

– The EVF bit is set by hardware with interrupt generation if the ITE bit is set.

Then the master waits for a read of the SR1 register followed by a write in the DR register, holding

the SCL line low (see

Transfer sequencing EV9).

Next the master must enter Receiver or Transmitter mode.

Note: In 10-bit addressing mode, to switch the master to Receiver mode, software must generate a repeated Start condition and resend the header sequence with the least significant bit set

(11110xx1).

Master Receiver

Following the address transmission and after SR1 and CR registers have been accessed, the master receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence:

– Acknowledge pulse if the ACK bit is set

– EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.

Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding

the SCL line low (see

SCL line low (see Figure 66 Transfer sequencing

Transfer sequencing EV7).

To close the communication: before reading the last byte from the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared).

Note: In order to generate the non-acknowledge pulse after the last received data byte, the ACK bit must be cleared just before reading the second last data byte.

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C BUS INTERFACE (Cont’d)

Master Transmitter

Following the address transmission and after SR1 register has been read, the master sends bytes from the DR register to the SDA line via the internal shift register.

The master waits for a read of the SR1 register followed by a write in the DR register, holding the

EV8).

When the acknowledge bit is received, the interface sets:

– EVF and BTF bits with an interrupt if the ITE bit is set.

To close the communication: after writing the last byte to the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared).

Error Cases

– BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and

BERR bits are set by hardware with an interrupt if ITE is set.

Note that BERR will not be set if an error is detected during the first or second pulse of each 9bit transaction:

Single Master Mode

If a Start or Stop is issued during the first or second pulse of a 9-bit transaction, the BERR flag will not be set and transfer will continue however the BUSY flag will be reset. To work around this, slave devices should issue a NACK when they receive a misplaced Start or Stop. The reception of a NACK or BUSY by the master in the middle of communication gives the possibility to reinitiate transmission.

Multimaster Mode

Normally the BERR bit would be set whenever unauthorized transmission takes place while transfer is already in progress. However, an issue will arise if an external master generates an unauthorized Start or Stop while the I

C master is on the first or second pulse of a 9-bit transaction. It is possible to work around this by polling the BUSY bit during I

C master mode transmission. The resetting of the BUSY bit can then be handled in a similar manner as the BERR flag being set.

– AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by hardware with an interrupt if the ITE bit is set. To resume, set the Start or Stop bit.

9th pulse of a transmitted byte.

– ARLO: Detection of an arbitration lost condition.

In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and the interface goes automatically back to slave mode (the M/SL bit is cleared).

Note: In all these cases, the SCL line is not held low; however, the SDA line can remain low due to possible «0» bits transmitted last. It is then necessary to release both lines by software.

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C BUS INTERFACE (Cont’d)

Figure 66. Transfer Sequencing

7-bit Slave receiver:

S Address A Data1 A

EV1 EV2

Data2 A

EV2

.....

DataN

7-bit Slave transmitter:

S Address A

EV1 EV3

Data1

7-bit Master receiver:

S Address A

EV5 EV6

Data1 A

EV3

EV7

Data2 A

EV3

EV7

.....

DataN

EV2

DataN NA

EV7

EV4

EV3-1

EV4

7-bit Master transmitter:

S Address A

EV5 EV6 EV8

10-bit Slave receiver:

S Header A Address A

EV1

Data1 A

EV8

EV2

Data2 A

EV8

.....

DataN A

EV2

DataN A

EV4

EV8

10-bit Slave transmitter:

S r

Header A

10-bit Master transmitter

S Header A

EV5 EV9

Address A

EV6 EV8

10-bit Master receiver:

EV1 EV3

Data1 A

EV3

....

DataN A

Data1 A

EV8

.....

EV3-1

DataN A

EV8

EV4

S r

EV5

Header A

EV6

Data1 A

EV7

.....

DataN A

EV7

Legend: S=Start, Sr = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,

EVx=Event (with interrupt if ITE=1)

EV1: EVF=1, ADSL=1, cleared by reading SR1 register.

EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.

EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.

EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the lines (STOP=1, STOP=0) or by writing DR register (DR=FFh). Note: If lines are released by

STOP=1, STOP=0, the subsequent EV4 is not seen.

EV4: EVF=1, STOPF=1, cleared by reading SR2 register.

EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.

EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).

EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.

EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.

EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.

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C BUS INTERFACE (Cont’d)

10.7.5 Low Power Modes

Mode Description

WAIT

No effect on I

C interface.

C interrupts cause the device to exit from WAIT mode.

HALT

C registers are frozen.

In HALT mode, the I

C interface is inactive and does not acknowledge data on the bus. The I

C interface resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability.

10.7.6 Interrupts

Figure 67. Event Flags and Interrupt Generation

ADD10

BTF

ADSL

STOPF

ARLO

BERR

ITE

EVF can also be set by EV6 or an error from the SR2 register.

INTERRUPT

EVF

Interrupt Event

10-bit Address Sent Event (Master mode)

End of Byte Transfer Event

Address Matched Event (Slave mode)

Start Bit Generation Event (Master mode)

Acknowledge Failure Event

Stop Detection Event (Slave mode)

Arbitration Lost Event (Multimaster configuration)

Bus Error Event

Note: The I

C interrupt events are connected to the same interrupt vector (see Interrupts chapter).

They generate an interrupt if the corresponding

Enable Control Bit is set and the I-bit in the CC register is reset (RIM instruction).

Event

Flag

Enable

Control

Bit

ADD10

BTF

ADSEL

STOPF

ARLO

BERR

ITE

Exit from

Wait

Yes

Exit from

Halt

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C BUS INTERFACE (Cont’d)

10.7.7 Register Description

C CONTROL REGISTER (CR)

Read / Write

Reset Value: 0000 0000 (00h)

0 0

PE ENGC START ACK STOP ITE

– In slave mode:

0: No start generation

1: Start generation when the bus is free

Bit 2 = ACK Acknowledge enable.

This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0).

0: No acknowledge returned

1: Acknowledge returned after an address byte or a data byte is received

Bit 7:6 = Reserved. Forced to 0 by hardware.

Bit 5 = PE Peripheral enable.

This bit is set and cleared by software.

0: Peripheral disabled

1: Master/Slave capability

Notes:

– When PE=0, all the bits of the CR register and the SR register except the Stop bit are reset. All outputs are released while PE=0

– When PE=1, the corresponding I/O pins are selected by hardware as alternate functions.

– To enable the I

C interface, write the CR register

TWICE with PE=1 as the first write only activates the interface (only PE is set).

Bit 4 = ENGC Enable General Call.

This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0). The 00h General Call address is acknowledged (01h ignored).

0: General Call disabled

1: General Call enabled

Note: In accordance with the I2C standard, when

GCAL addressing is enabled, an I2C slave can only receive data. It will not transmit data to the master.

Bit 3 = START Generation of a Start condition.

This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0) or when the Start condition is sent

(with interrupt generation if ITE=1).

– In master mode:

0: No start generation

1: Repeated start generation

Bit 1 = STOP Generation of a Stop condition.

This bit is set and cleared by software. It is also cleared by hardware in master mode. Note: This bit is not cleared when the interface is disabled

(PE=0).

– In master mode:

0: No stop generation

1: Stop generation after the current byte transfer or after the current Start condition is sent. The

STOP bit is cleared by hardware when the Stop condition is sent.

– In slave mode:

0: No stop generation

1: Release the SCL and SDA lines after the current byte transfer (BTF=1). In this mode the

STOP bit has to be cleared by software.

Bit 0 = ITE Interrupt enable.

This bit is set and cleared by software and cleared by hardware when the interface is disabled

(PE=0).

0: Interrupts disabled

1: Interrupts enabled

Refer to

Figure 67

for the relationship between the events and the interrupt.

SCL is held low when the ADD10, SB, BTF or

ADSL flags or an EV6 event (See Figure 66 ) is de-

tected.

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C BUS INTERFACE (Cont’d)

C STATUS REGISTER 1 (SR1)

Read Only

Reset Value: 0000 0000 (00h)

7 0

EVF ADD10 TRA BUSY BTF ADSL M/SL SB

Bit 7 = EVF Event flag.

This bit is set by hardware as soon as an event occurs. It is cleared by software reading SR2 register in case of error event or as described in

Figure 66 .

It is also cleared by hardware when the interface is disabled (PE=0).

0: No event

1: One of the following events has occurred:

– BTF=1 (Byte received or transmitted)

– ADSL=1 (Address matched in Slave mode while ACK=1)

– SB=1 (Start condition generated in Master mode)

– AF=1 (No acknowledge received after byte transmission)

– STOPF=1 (Stop condition detected in Slave mode)

– ARLO=1 (Arbitration lost in Master mode)

– BERR=1 (Bus error, misplaced Start or Stop condition detected)

– ADD10=1 (Master has sent header byte)

– Address byte successfully transmitted in Master mode.

Bit 6 = ADD10 10-bit addressing in Master mode.

This bit is set by hardware when the master has sent the first byte in 10-bit address mode. It is cleared by software reading SR2 register followed by a write in the DR register of the second address byte. It is also cleared by hardware when the peripheral is disabled (PE=0).

0: No ADD10 event occurred.

1: Master has sent first address byte (header)

Bit 5 = TRA Transmitter/Receiver.

When BTF is set, TRA=1 if a data byte has been transmitted. It is cleared automatically when BTF is cleared. It is also cleared by hardware after detection of Stop condition (STOPF=1), loss of bus arbitration (ARLO=1) or when the interface is disabled (PE=0).

0: Data byte received (if BTF=1)

1: Data byte transmitted

Bit 4 = BUSY Bus busy.

This bit is set by hardware on detection of a Start condition and cleared by hardware on detection of a Stop condition. It indicates a communication in progress on the bus. The BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs.

0: No communication on the bus

1: Communication ongoing on the bus

Note:

– The BUSY flag is NOT updated when the interface is disabled (PE=0). This can have consequences when operating in Multimaster mode; i.e. a second active I

C master commencing a transfer with an unset BUSY bit can cause a conflict resulting in lost data. A software workaround consists of checking that the I

C is not busy before enabling the I

C Multimaster cell.

Bit 3 = BTF Byte transfer finished.

This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ITE=1. It is cleared by software reading

SR1 register followed by a read or write of DR register. It is also cleared by hardware when the interface is disabled (PE=0).

– Following a byte transmission, this bit is set after reception of the acknowledge clock pulse. In case an address byte is sent, this bit is set only

after the EV6 event (See Figure 66 ). BTF is

cleared by reading SR1 register followed by writing the next byte in DR register.

– Following a byte reception, this bit is set after transmission of the acknowledge clock pulse if

ACK=1. BTF is cleared by reading SR1 register followed by reading the byte from DR register.

The SCL line is held low while BTF=1.

0: Byte transfer not done

1: Byte transfer succeeded

Bit 2 = ADSL Address matched (Slave mode).

This bit is set by hardware as soon as the received slave address matched with the OAR register content or a general call is recognized. An interrupt is generated if ITE=1. It is cleared by software reading SR1 register or by hardware when the interface is disabled (PE=0).

The SCL line is held low while ADSL=1.

0: Address mismatched or not received

1: Received address matched

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C BUS INTERFACE (Cont’d)

Bit 1 = M/SL Master/Slave.

This bit is set by hardware as soon as the interface is in Master mode (writing START=1). It is cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration (ARLO=1). It is also cleared when the interface is disabled (PE=0).

0: Slave mode

1: Master mode

Bit 0 = SB Start bit (Master mode).

This bit is set by hardware as soon as the Start condition is generated (following a write

START=1). An interrupt is generated if ITE=1. It is cleared by software reading SR1 register followed by writing the address byte in DR register.

It is also cleared by hardware when the interface is disabled (PE=0).

0: No Start condition

1: Start condition generated

C STATUS REGISTER 2 (SR2)

Read Only

Reset Value: 0000 0000 (00h)

7 0

0 0 0 AF STOPF ARLO BERR GCAL

The SCL line is not held low while STOPF=1.

0: No Stop condition detected

1: Stop condition detected

Bit 2 = ARLO Arbitration lost.

This bit is set by hardware when the interface loses the arbitration of the bus to another master. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0).

After an ARLO event the interface switches back automatically to Slave mode (M/SL=0).

The SCL line is not held low while ARLO=1.

0: No arbitration lost detected

1: Arbitration lost detected

Note:

– In a Multimaster environment, when the interface is configured in Master Receive mode it does not perform arbitration during the reception of the

Acknowledge Bit. Mishandling of the ARLO bit from the I2CSR2 register may occur when a second master simultaneously requests the same data from the same slave and the I

C master does not acknowledge the data. The ARLO bit is then left at 0 instead of being set.

Bit 7:5 = Reserved. Forced to 0 by hardware.

Bit 4 = AF Acknowledge failure.

This bit is set by hardware when no acknowledge is returned. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0).

The SCL line is not held low while AF=1 but by other flags (SB or BTF) that are set at the same time.

0: No acknowledge failure

1: Acknowledge failure

Note:

– When an AF event occurs, the SCL line is not held low; however, the SDA line can remain low if the last bits transmitted are all 0. It is then necessary to release both lines by software.

Bit 1 = BERR Bus error.

This bit is set by hardware when the interface detects a misplaced Start or Stop condition. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0).

The SCL line is not held low while BERR=1.

0: No misplaced Start or Stop condition

1: Misplaced Start or Stop condition

Note:

– If a Bus Error occurs, a Stop or a repeated Start condition should be generated by the Master to re-synchronize communication, get the transmission acknowledged and the bus released for further communication

Bit 3 = STOPF Stop detection (Slave mode).

This bit is set by hardware when a Stop condition is detected on the bus after an acknowledge (if

ACK=1). An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0).

Bit 0 = GCAL General Call (Slave mode).

This bit is set by hardware when a general call address is detected on the bus while ENGC=1. It is cleared by hardware detecting a Stop condition

(STOPF=1) or when the interface is disabled

(PE=0).

0: No general call address detected on bus

1: general call address detected on bus

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C BUS INTERFACE (Cont’d)

C CLOCK CONTROL REGISTER (CCR)

Read / Write

Reset Value: 0000 0000 (00h)

7 0

FM/SM CC6 CC5 CC4 CC3 CC2 CC1 CC0

Bit 7 = FM/SM Fast/Standard I

C mode.

This bit is set and cleared by software.

It is not cleared when the interface is disabled (PE=0).

0: Standard I

C mode

1: Fast I

C mode

C DATA REGISTER (DR)

Read / Write

Reset Value: 0000 0000 (00h)

D7 D6 D5 D4 D3 D2 D1

Bit 6:0 = CC[6:0] 7-bit clock divider.

These bits select the speed of the bus (F

SCL pending on the I

) de-

C mode. They are not cleared when the interface is disabled (PE=0).

Refer to the Electrical Characteristics section for the table of values.

Note: The programmed F

SCL

SCL and SDA lines.

assumes no load on

Bit 7:0 = D[7:0] 8-bit Data Register.

These bits contain the byte to be received or transmitted on the bus.

– Transmitter mode: Byte transmission start automatically when the software writes in the DR register.

– Receiver mode: the first data byte is received automatically in the DR register using the least significant bit of the address.

Then, the following data bytes are received one by one after reading the DR register.

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C BUS INTERFACE (Cont’d)

C OWN ADDRESS REGISTER (OAR1)

Read / Write

Reset Value: 0000 0000 (00h)

ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0

7-bit Addressing Mode

Bit 7:1 = ADD[7:1] Interface address.

These bits define the I

C bus address of the interface. They are not cleared when the interface is disabled (PE=0).

Bit 0 = ADD0 Address direction bit.

This bit is don’t care, the interface acknowledges either 0 or 1. It is not cleared when the interface is disabled (PE=0).

Note: Address 01h is always ignored.

C OWN ADDRESS REGISTER (OAR2)

Read / Write

Reset Value: 0100 0000 (40h)

FR1 FR0 0 0

0 ADD9 ADD8 0

Bit 7:6 = FR[1:0] Frequency bits.

These bits are set by software only when the interface is disabled (PE=0). To configure the interface to I

C specified delays select the value corresponding to the microcontroller frequency F

CPU

. f

CPU

< 6 MHz

6 to 8 MHz

Bit 5:3 = Reserved

FR1

FR0

10-bit Addressing Mode

Bit 7:0 = ADD[7:0] Interface address.

These are the least significant bits of the I

C bus address of the interface. They are not cleared when the interface is disabled (PE=0).

Bit 2:1 = ADD[9:8] Interface address.

These are the most significant bits of the I

C bus address of the interface (10-bit mode only). They are not cleared when the interface is disabled

(PE=0).

Bit 0 = Reserved.

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I²C BUS INTERFACE (Cont’d)

Table 23. I

C Register Map and Reset Values

Address

(Hex.)

0018h

0019h

001Ah

001Bh

001Ch

001Dh

001Eh

Register

Label

I2CCR

Reset Value

I2CSR1

Reset Value

I2CSR2

Reset Value

I2CCCR

Reset Value

I2COAR1

Reset Value

I2COAR2

Reset Value

I2CDR

Reset Value

EVF

FM/SM

ADD7

FR1

MSB

ADD10

CC6

ADD6

FR0

TRA

CC5

ADD5

ENGC

BUSY

CC4

ADD4

3 2

START

BTF

STOPF

CC3

ADD3

ACK

ADSL

ARLO

CC2

ADD2

ADD9

0 0 0

STOP

M/SL

BERR

CC1

ADD1

ADD8

ITE

GCAL

CC0

ADD0

LSB

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10.8 CONTROLLER AREA NETWORK (CAN)

10.8.1 Introduction

This peripheral is designed to support serial data exchanges using a multi-master contention based priority scheme as described in CAN specification

Rev. 2.0 part A. It can also be connected to a 2.0 B network without problems, since extended frames

Figure 68. CAN Block Diagram are checked for correctness and acknowledged accordingly although such frames cannot be transmitted nor received. The same applies to overload frames which are recognized but never initiated.

ST7 Internal Bus

ST7 Interface

TX/RX

Buffer 1

10 Bytes

TX/RX

Buffer 2

10 Bytes

TX/RX

Buffer 3

10 Bytes

Filter 0

4 Bytes

Filter 1

4 Bytes

BTL BCDL

EML

SHREG

CAN 2.0B passive Core

CRC

ICR

ISR

CSR

TECR

RECR

PSR

BRPR

BTR

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CONTROLLER AREA NETWORK (Cont’d)

10.8.2 Main Features

– Support of CAN specification 2.0A and 2.0B passive

– Three prioritized 10-byte Transmit/Receive message buffers

– Two programmable global 12-bit message acceptance filters

– Programmable baud rates up to 1 MBit/s

– Buffer flip-flopping capability in transmission

– Maskable interrupts for transmit, receive (one per buffer), error and wake-up

– Automatic low-power mode after 20 recessive bits or on demand (standby mode)

– Interrupt-driven wake-up from standby mode upon reception of dominant pulse

– Optional dominant pulse transmission on leaving standby mode

– Automatic message queuing for transmission upon writing of data byte 7

– Programmable loop-back mode for self-test operation

– Advanced error detection and diagnosis functions

– Software-efficient buffer mapping at a unique address space

– Scalable architecture.

10.8.3 Functional Description

10.8.3.1 Frame Formats

A summary of all the CAN frame formats is given

in Figure 69 for reference. It covers only the stand-

ard frame format since the extended one is only acknowledged.

A message begins with a start bit called Start Of

Frame (SOF). This bit is followed by the arbitration field which contains the 11-bit identifier (ID) and the Remote Transmission Request bit (RTR). The

RTR bit indicates whether it is a data frame or a remote request frame. A remote request frame does not have any data byte.

The control field contains the Identifier Extension bit (IDE), which indicates standard or extended format, a reserved bit (ro) and, in the last four bits, a count of the data bytes (DLC). The data field ranges from zero to eight bytes and is followed by the Cyclic Redundancy Check (CRC) used as a frame integrity check for detecting bit errors.

The acknowledgement (ACK) field comprises the

ACK slot and the ACK delimiter. The bit in the ACK slot is placed on the bus by the transmitter as a recessive bit (logical 1). It is overwritten as a dominant bit (logical 0) by those receivers which have at this time received the data correctly. In this way, the transmitting node can be assured that at least one receiver has correctly received its message.

Note that messages are acknowledged by the receivers regardless of the outcome of the acceptance test.

The end of the message is indicated by the End Of

Frame (EOF). The intermission field defines the minimum number of bit periods separating consecutive messages. If there is no subsequent bus access by any station, the bus remains idle.

10.8.3.2 Hardware Blocks

The CAN controller contains the following func-

tional blocks (refer to Figure 68 ):

– ST7 Interface: buffering of the ST7 internal bus and address decoding of the CAN registers.

– TX/RX Buffers: three 10-byte buffers for transmission and reception of maximum length messages.

– ID Filters: two 12-bit compare and don’t care masks for message acceptance filtering.

– PSR: page selection register (see memory map).

– BRPR: clock divider for different data rates.

– BTR: bit timing register.

– ICR: interrupt control register.

– ISR: interrupt status register.

– CSR: general purpose control/status register.

– TECR: transmit error counter register.

– RECR: receive error counter register.

– BTL: bit timing logic providing programmable bit sampling and bit clock generation for synchronization of the controller.

– BCDL: bit coding logic generating a NRZ-coded datastream with stuff bits.

– SHREG: 8-bit shift register for serialization of data to be transmitted and parallelisation of received data.

– CRC: 15-bit CRC calculator and checker.

– EML: error detection and management logic.

– CAN Core: CAN 2.0B passive protocol controller.

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CONTROLLER AREA NETWORK (Cont’d)

Figure 69. CAN Frames

Inter-Frame Space Data Frame

44 + 8 * N

Arbitration Field Control Field Data Field

12 6 8 * N

ID DLC

CRC Field

CRC

Inter-Frame Space or Overload Frame

Ack Field

EOF

Inter-Frame Space Remote Frame

Arbitration Field Control Field

12 6

ID DLC

CRC Field

CRC

Inter-Frame Space or Overload Frame

Ack Field End Of Frame

Data Frame or

Remote Frame Error Frame

Inter-Frame Space or Overload Frame

Error Flag Flag Echo

≤

Error Delimiter

Any Frame Inter-Frame Space

Intermission

Suspend

Transmission

Bus Idle

Data Frame or

Remote Frame

End Of Frame or

Error Delimiter or

Overload Delimiter Overload Frame

Inter-Frame Space or Error Frame

Overload Flag Overload Delimiter

6 8

Notes:

• 0

• SOF = Start Of Frame

• ID = Identifier

• RTR = Remote Transmission Request

• IDE = Identifier Extension Bit

• r0 = Reserved Bit

• DLC = Data Length Code

• CRC = Cyclic Redundancy Code

• Error flag: 6 dominant bits if node is error active else 6 recessive bits.

• Suspend transmission: applies to error passive nodes only.

• EOF = End of Frame

• ACK = Acknowledge bit

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10.8.3.3 Modes of Operation

The CAN Core unit assumes one of the seven states described below:

– STANDBY. Standby mode is entered either on a chip reset or on resetting the RUN bit in the Control/Status Register (CSR). Any on-going transmission or reception operation is not interrupted and completes normally before the Bit Time Logic and the clock prescaler are turned off for minimum power consumption. This state is signalled by the RUN bit being read-back as 0.

Once in standby, the only event monitored is the reception of a dominant bit which causes a wakeup interrupt if the SCIE bit of the Interrupt Control

The STANDBY mode is left by setting the RUN

Figure 70. CAN Controller State Diagram

ARESET bit. If the WKPS bit is set in the CSR register, then the controller passes through WAKE-UP otherwise it enters RESYNC directly.

It is important to note that the wake-up mechanism is software-driven and therefore carries a significant time overhead. All messages received after the wake-up bit and before the controller is set to run and has completed synchronization are ignored.

Note: Standby mode is not entered on resetting the RUN bit in the Control/Status register (CSR) if the CANRX pin is shorted to GND.

– WAKE-UP. The CAN bus line is forced to dominant for one bit time signalling the wake-up condition to all other bus members.

RUN & WKPS

STANDBY

RUN RUN & WKPS WAKE-UP

RESYNC

FSYN & BOFF & 11 Recessive bits |

( FSYN | BOFF) & 128 * 11 Recessive bits

RUN

IDLE

Write to DATA7 |

TX Error & NRTX

TRANSMISSION

TX OK RX OK

Arbitration lost

Start Of Frame

RECEPTION

TX Error

ERROR

RX Error

BOFF

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– RESYNC. The resynchronization mode is used to find the correct entry point for starting transmission or reception after the node has gone asynchronous either by going into the STANDBY or bus-off states.

Resynchronization is achieved when 128 sequences of 11 recessive bits have been monitored unless the node is not bus-off and the

FSYN bit in the CSR register is set in which case a single sequence of 11 recessive bits needs to be monitored.

– IDLE. The CAN controller looks for one of the following events: the RUN bit is reset, a Start Of

Frame appears on the CAN bus or the DATA7 register of the currently active page is written to.

– TRANSMISSION. Once the LOCK bit of a Buffer

Control/Status Register (BCSRx) has been set and read back as such, a transmit job can be submitted by writing to the DATA7 register. The message with the highest priority will be transmitted as soon as the CAN bus becomes idle.

Among those messages with a pending transmission request, the highest priority is given to

Buffer 3 then 2 and 1. If the transmission fails due to a lost arbitration or to an error while the NRTX bit of the CSR register is reset, then a new transmission attempt is performed. This goes on until the transmission ends successfully or until the job is cancelled by unlocking the buffer, by setting the NRTX bit or if the node ever enters busoff or if a higher priority message becomes pending. The RDY bit in the BCSRx register, which was set since the job was submitted, gets reset.

When a transmission is in progress, the BUSY bit in the BCSRx register is set. If it ends successfully then the TXIF bit in the Interrupt Status Register (ISR) is set, else the TEIF bit is set. An interrupt is generated in either case provided the

TXIE and TEIE bits of the ICR register are set.

Note 1: Setting the SRTE bit of the CSR register allows transmitted messages to be simultaneously received when they pass the acceptance filtering. This is particularly useful for checking the integrity of the communication path.

RECEPTION. Once the CAN controller has synchronized itself onto the bus activity, it is ready for reception of new messages. Every incoming message gets its identifier compared to the acceptance filters. If the bitwise comparison of the selected bits ends up with a match for at least one of the filters then that message is elected for reception and a target buffer is searched for. This buffer will be the first one - order is 1 to 3 - that has the LOCK and RDY bits of its BCSRx register reset.

– When no such buffer exists then an overrun interrupt is generated if the ORIE bit of the ICR register has been set. In this case the identifier of the last message is made available in the

Last Identifier Register (LIDHR and LIDLR) at least until it gets overwritten by a new identifier picked-up from the bus.

– When a buffer does exist, the accepted message gets written into it, the ACC bit in the

BCSRx register gets the number of the matching filter, the RDY and RXIF bits get set and an interrupt is generated if the RXIE bit in the ISR register is set.

Up to three messages can be automatically received without intervention from the CPU because each buffer has its own set of status bits, greatly reducing the reactiveness requirements in the processing of the receive interrupts.

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– ERROR. The error management as described in the CAN protocol is completely handled by hardware using 2 error counters which get incremented or decremented according to the error condition. Both of them may be read by the appli-

Figure 71. CAN Error State Diagram cation to determine the stability of the network.

Moreover, as one of the node status bits (EPSV or BOFF of the CSR register) changes, an interrupt is generated if the SCIE bit is set in the ICR

When TECR or RECR > 127, the EPSV bit gets set

Figure 71 .

ERROR ACTIVE

ERROR PASSIVE

When 128 * 11 recessive bits occur:

- the BOFF bit gets cleared

- the TECR register gets cleared

- the RECR register gets cleared

When TECR and RECR < 128, the EPSV bit gets cleared

When TECR > 255 the BOFF bit gets set and the EPSV bit gets cleared

BUS OFF

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10.8.3.4 Bit Timing Logic

The bit timing logic monitors the serial bus-line and performs sampling and adjustment of the sample point by synchronizing on the start-bit edge and resynchronizing on following edges.

Its operation may be explained simply when the nominal bit time is divided into three segments as follows:

– Synchronisation segment (SYNC_SEG): a bit change is expected to lie within this time segment. It has a fixed length of one time quanta (1 x t

CAN

– Bit segment 1 (BS1): defines the location of the sample point. It includes the PROP_SEG and

PHASE_SEG1 of the CAN standard. Its duration is programmable between 1 and 16 time quanta but may be automatically lengthened to compensate for positive phase drifts due to differences in the frequency of the various nodes of the network.

– Bit segment 2 (BS2): defines the location of the transmit point. It represents the PHASE_SEG2 of the CAN standard. Its duration is programmable between 1 and 8 time quanta but may also be automatically shortened to compensate for negative phase drifts.

Figure 72. Bit Timing

– Resynchronization Jump Width (RJW): defines an upper bound to the amount of lengthening or shortening of the bit segments. It is programmable between 1 and 4 time quanta.

To guarantee the correct behaviour of the CAN controller, SYNC_SEG + BS1 + BS2 must be greater than or equal to 5 time quanta.

The CAN controller resynchronizes on recessive to dominant edges only.

For a detailed description of the CAN resynchronization mechanism and other bit timing configuration constraints, please refer to the Bosch CAN standard 2.0.

As a safeguard against programming errors, the configuration of the Bit Timing Register (BTR) is only possible while the device is in STANDBY mode.

SYNC_SEG

1 x t

CAN

NOMINAL BIT TIME

BIT SEGMENT 1 (BS1) t

BS1

SAMPLE POINT

BIT SEGMENT 2 (BS2) t

BS2

TRANSMIT POINT

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10.8.4 Register Description

The CAN registers are organized as 6 general purpose registers plus 5 pages of 16 registers spanning the same address space and primarily used for message and filter storage. The page actually selected is defined by the content of the Page Selection Register.

10.8.4.1 General Purpose Registers

INTERRUPT STATUS REGISTER (ISR)

Read/Write

Reset Value: 00h

7 0

RXIF3 RXIF2 RXIF1 TXIF SCIF ORIF TEIF EPND

Bit 7 = RXIF3 Receive Interrupt Flag for Buffer 3

Read/Clear

Set by hardware to signal that a new error-free message is available in buffer 3.

Cleared by software to release buffer 3.

Also cleared by resetting bit RDY of BCSR3.

Bit 6 = RXIF2 Receive Interrupt Flag for Buffer 2

Read/Clear

Set by hardware to signal that a new error-free message is available in buffer 2.

Cleared by software to release buffer 2.

Also cleared by resetting bit RDY of BCSR2.

−

Read/Clear

Set by hardware to signal that a new error-free message is available in buffer 1.

Cleared by software to release buffer 1.

Also cleared by resetting bit RDY of BCSR1.

−

Read/Clear

Set by hardware to signal that the highest priority message queued for transmission has been successfully transmitted.

Cleared by software.

−

Read/Clear

Set by hardware to signal the reception of a dominant bit while in standby mode. In Run mode this bit

is set when EPVS is set or reset (refer to Figure 71.

CAN Error State Diagram ). This bit also signals any

receive error when ESCI=1.

Cleared by software.

−

Read/Clear

Set by hardware to signal that a message could not be stored because no receive buffer was available.

Cleared by software.

−

Read/Clear

Set by hardware to signal that an error occurred during the transmission of the highest priority message queued for transmission.

Cleared by software.

−

Read Only

Set by hardware when at least one of the three error interrupt flags SCIF, ORIF or TEIF is set.

Reset by hardware when all error interrupt flags have been cleared.

Caution:

Interrupt flags are reset by writing a “0” to the corresponding bit position. The appropriate way consists in writing an immediate mask or the one’s complement of the register content initially read by the interrupt handler. Bit manipulation instruction

BRES should never be used due to its read-modifywrite nature.

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INTERRUPT CONTROL REGISTER (ICR)

Read/Write

Reset Value: 00h

7 0

0 ESCI RXIE TXIE SCIE ORIE TEIE 0

Bit 7 = Reserved.

−

Read/Set/Clear

Set by software to specify that SCIF is to be set on receive errors also.

Cleared by software to set SCIF only on status changes and wake-up but not on all receive errors.

Bit 5 = RXIE Receive Interrupt Enable

Read/Set/Clear

Set by software to enable an interrupt request whenever a message has been received free of errors.

Cleared by software to disable receive interrupt requests.

Bit 4 = TXIE Transmit Interrupt Enable

Read/Set/Clear

Set by software to enable an interrupt request whenever a message has been successfully transmitted.

Cleared by software to disable transmit interrupt requests.

−

Read/Set/Clear

Set by software to enable an interrupt request whenever the node’s status changes in run mode or whenever a dominant pulse is received in standby mode.

Cleared by software to disable status change interrupt requests.

Bit 2 = ORIE Overrun Interrupt Enable

−

Read/Set/Clear

Set by software to enable an interrupt request whenever a message should be stored and no receive buffer is avalaible.

Cleared by software to disable overrun interrupt requests.

−

Read/Set/Clear

Set by software to enable an interrupt whenever an error has been detected during transmission of a message.

Cleared by software to disable transmit error interrupts.

Bit 0 = Reserved.

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CONTROL/STATUS REGISTER (CSR)

Read/Write

Reset Value: 00h

7 0

0 BOFF EPSV SRTE NRTX FSYN WKPS RUN

−

Read Only

Set by hardware to indicate that the node is in busoff state, i.e. the Transmit Error Counter exceeds

255.

Reset by hardware to indicate that the node is involved in bus activities.

−

Read Only

Set by hardware to indicate that the node is error passive.

Reset by hardware to indicate that the node is either error active (BOFF = 0) or bus-off.

able

−

Read/Set/Clear

Set by software to enable simultaneous transmission and reception of a message passing the acceptance filtering. Allows to check the integrity of the communication path.

Reset by software to discard all messages transmitted by the node. Allows remote and data frames to share the same identifier.

−

Read/Set/Clear

Set by software to disable the retransmission of unsuccessful messages. It does not stop transmission in case of Arbitration Lost.

Cleared by software to enable retransmission of messages until success is met.

Bit 2 = FSYN Fast Synchronization

Read/Set/Clear

Set by software to enable a fast resynchronization when leaving standby mode, i.e. wait for only 11 recessive bits in a row.

Cleared by software to enable the standard resynchronization when leaving standby mode, i.e. wait for 128 sequences of 11 recessive bits.

−

Read/Set/Clear

Set by software to generate a dominant pulse when leaving standby mode.

Cleared by software for no dominant wake-up pulse.

Bit 0 = RUN CAN Enable

−

Read/Set/Clear

Set by software to leave standby mode after 128 sequences of 11 recessive bits or just 11 recessive bits if FSYN is set.

Cleared by software to request a switch to the standby or low-power mode as soon as any on-going transfer is complete. Read-back as 1 in the meantime to enable proper signalling of the standby state. The CPU clock may therefore be safely switched OFF whenever RUN is read as 0.

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BAUD RATE PRESCALER REGISTER (BRPR)

Read/Write in Standby mode

Reset Value: 00h

7 0

RJW1 RJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0

RJW[1:0] determine the maximum number of time quanta by which a bit period may be shortened or lengthened to achieve resynchronization.

RJW

= t

CAN

* (RJW + 1)

BRP[5:0] determine the CAN system clock cycle time or time quanta which is used to build up the individual bit timing.

CAN

= t

CPU

* (BRP + 1)

Where t

CPU

= time period of the CPU clock.

The resulting baud rate can be computed by the formula:

BR = t

CPU

× ( BRP + 1 ) × ( BS1 + BS2 + 3 )

BIT TIMING REGISTER (BTR)

Read/Write in Standby mode

Reset Value: 23h

BS22 BS21 BS20 BS13 BS12 BS11 BS10

BS2[2:0] determine the length of Bit Segment 2.

BS2

= t

CAN

* (BS2 + 1)

BS1[3:0] determine the length of Bit Segment 1.

BS1

= t

CAN

* (BS1 + 1)

Note: Writing to this register is allowed only in

Standby mode to prevent any accidental CAN protocol violation through programming errors.

PAGE SELECTION REGISTER (PSR)

Read/Write

Reset Value: 00h

0 0 0 0 0

PAGE

PAGE[2:0] determine which buffer or filter page is mapped at addresses 0010h to 001Fh.

Note: Writing to this register is allowed only in

Standby mode to prevent any accidental CAN protocol violation through programming errors.

PAGE2

PAGE1

PAGE0

Page Title

Diagnosis

Buffer 1

Buffer 2

Buffer 3

Filters

Reserved

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10.8.4.2 Paged Registers

LAST IDENTIFIER HIGH REGISTER (LIDHR)

Read/Write

Reset Value: Undefined

7 0

LID10 LID9 LID8 LID7 LID6 LID5 LID4 LID3

TRANSMIT ERROR COUNTER REG. (TECR)

Read Only

Reset Value: 00h

7 0

TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0

LID[10:3] are the most significant 8 bits of the last

Identifier read on the CAN bus.

LAST IDENTIFIER LOW REGISTER (LIDLR)

Read/Write

Reset Value: Undefined

7 0

LID2 LID1 LID0 LRTR

LDLC

TEC[7:0] is the least significant byte of the 9-bit

Transmit Error Counter implementing part of the fault confinement mechanism of the CAN protocol.

In case of an error during transmission, this counter is incremented by 8. It is decremented by 1 after every successful transmission. When the counter value exceeds 127, the CAN controller enters the error passive state. When a value of 256 is reached, the CAN controller is disconnected from the bus.

RECEIVE ERROR COUNTER REG. (RECR)

Page: 00h — Read Only

Reset Value: 00h

7 0

REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0

LID[2:0] are the least significant 3 bits of the last

Identifier read on the CAN bus.

LRTR is the last Remote Transmission Request bit read on the CAN bus.

LDLC[3:0] is the last Data Length Code read on the

CAN bus.

REC[7:0] is the Receive Error Counter implementing part of the fault confinement mechanism of the

CAN protocol. In case of an error during reception, this counter is incremented by 1 or by 8 depending on the error condition as defined by the CAN standard. After every successful reception the counter is decremented by 1 or reset to 120 if its value was higher than 128. When the counter value exceeds

127, the CAN controller enters the error passive state.

IDENTIFIER HIGH REGISTERS (IDHRx)

Read/Write

Reset Value: Undefined

ID10 ID9 ID8 ID7 ID6 ID5 ID4

ID3

ID[10:3] are the most significant 8 bits of the 11-bit message identifier.The identifier acts as the message’s name, used for bus access arbitration and acceptance filtering.

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IDENTIFIER LOW REGISTERS (IDLRx)

Read/Write

Reset Value: Undefined

7 0

ID2 ID1 ID0 RTR DLC3 DLC2 DLC1 DLC0

BUFFER CONTROL/STATUS REGs. (BCSRx)

Read/Write

Reset Value: 00h

7 0

0 0 0 0 ACC RDY BUSY LOCK

ID[2:0] are the least significant 3 bits of the 11-bit message identifier.

RTR is the Remote Transmission Request bit. It is set to indicate a remote frame and reset to indicate a data frame.

DLC[3:0] is the Data Length Code. It gives the number of bytes in the data field of the message.The valid range is 0 to 8.

DATA REGISTERS (DATA0-7x)

Read/Write

Reset Value: Undefined

7 0

DATA

DATA[7:0] is a message data byte. Up to eight such bytes may be part of a message. Writing to byte

DATA7 initiates a transmit request and should always be done even when DATA7 is not part of the message.

−

Read Only

Set by hardware with the id of the highest priority filter which accepted the message stored in the buffer.

ACC = 0: Match for Filter/Mask0. Possible match for Filter/Mask1.

ACC = 1: No match for Filter/Mask0 and match for

Filter/Mask1.

Reset by hardware when either RDY or RXIF gets reset.

−

Read/Clear

Set by hardware to signal that a new error-free message is available (LOCK = 0) or that a transmission request is pending (LOCK = 1).

Cleared by software when LOCK = 0 to release the buffer and to clear the corresponding RXIF bit in the Interrupt Status Register.

Cleared by hardware when LOCK = 1 to indicate that the transmission request has been serviced or cancelled.

−

Read Only

Set by hardware when the buffer is being filled

(LOCK = 0) or emptied (LOCK = 1) and reset after the 2nd intermission bit.

Reset by hardware when the buffer is not accessed by the CAN core for transmission nor reception purposes.

−

Read/Set/Clear

Set by software to lock a buffer. No more message can be received into the buffer thus preserving its content and making it available for transmission.

Cleared by software to make the buffer available for reception. Cancels any pending transmission request.

Cleared by hardware once a message has been successfully transmitted provided the early transmit interrupt mode is on. Left untouched otherwise.

Note that in order to prevent any message corruption or loss of context, LOCK cannot be set nor reset while BUSY is set. Trying to do so will result in

LOCK not changing state.

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FILTER HIGH REGISTERS (FHRx)

Read/Write

Reset Value: Undefined

7 0

FIL11 FIL10 FIL9 FIL8 FIL7 FIL6 FIL5 FlL4

MASK HIGH REGISTERS (MHRx)

Read/Write

Reset Value: Undefined

7 0

MSK1

MSK9 MSK8 MSK7 MSK6 MSK5 MSK4

FIL[11:3] are the most significant 8 bits of a 12-bit message filter. The acceptance filter is compared bit by bit with the identifier and the RTR bit of the incoming message. If there is a match for the set of bits specified by the acceptance mask then the message is stored in a receive buffer.

FILTER LOW REGISTERS (FLRx)

Read/Write

Reset Value: Undefined

FIL3 FIL2 FIL1 FIL0 0 0 0

MSK[11:3] are the most significant 8 bits of a 12bit message mask. The acceptance mask defines which bits of the acceptance filter should match the identifier and the RTR bit of the incoming message.

MSK i

= 0: don’t care.

= 1: match required.

MASK LOW REGISTERS (MLRx)

Read/Write

Reset Value: Undefined

MSK3 MSK2 MSK1 MSK0 0 0 0

FIL[3:0] are the least significant 4 bits of a 12-bit message filter.

MSK[3:0] are the least significant 4 bits of a 12-bit message mask.

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CONTROLLER AREA NETWORK (Cont’d)

Figure 73. CAN Register Map

5Ah

5Bh

5Ch

5Dh

5Eh

5Fh

60h

6Fh

Interrupt Status

Interrupt Control

Control/Status

Baud Rate Prescaler

Bit Timing

Page Selection

Paged Reg1

Paged Reg0

Paged Reg2

Paged Reg1

Paged Reg2

Paged Reg3

Paged Reg4

Paged Reg5

Paged Reg6

Paged Reg7

Paged Reg8

Paged Reg9

Paged Reg10

Paged Reg11

Paged Reg12

Paged Reg13

Paged Reg15

ST72F521, ST72521B

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Figure 74. Page Maps

6Ah

6Bh

6Ch

6Dh

6Eh

6Fh

64h

65h

66h

67h

68h

69h

60h

61h

62h

63h

PAGE 0

LIDHR

LIDLR

Reserved

TECR

RECR

Diagnosis

BCSR1

Buffer 1

PAGE 1

IDHR1

IDLR1

DATA01

DATA11

DATA21

DATA31

DATA41

DATA51

DATA61

DATA71

Reserved

PAGE 2

IDHR2

IDLR2

DATA02

DATA12

DATA22

DATA32

DATA42

DATA52

DATA62

DATA72

Reserved

BCSR2

Buffer 2

PAGE 3

IDHR3

IDLR3

DATA03

DATA13

DATA23

DATA33

DATA43

DATA53

DATA63

DATA73

Reserved

PAGE 4

FHR0

FLR0

MHR0

MLR0

FHR1

FLR1

MHR1

MLR1

Reserved

BCSR3

Buffer 3 Acceptance Filters

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Table 24. CAN Register Map and Reset Values

Address

(Hex.)

60, 64

61, 65

62 to 69 1 to 3

62, 66

63, 67

Page

1 to 3

Register

Label

CANIDLRx

Reset Value

CANFLRx

Reset Value

CANDRx

Reset Value

CANMHRx

Reset Value

CANMLRx

Reset Value

CANTECR

Reset Value

CANRECR

Reset Value

CANBCSRx

Reset Value

CANISR

Reset Value

CANICR

Reset Value

CANCSR

Reset Value

CANBRPR

Reset Value

CANBTR

Reset Value

CANPSR

Reset Value

CANLIDHR

Reset Value

CANIDHRx

Reset Value

CANFHRx

Reset Value

CANLIDLR

Reset Value

RXIF3

RJW1

6 x

MSK10 x

MSK2 x

ID2 x

FIL3 x

MSB x

MSK11 x

MSK3 x

MSB

LID10 x

ID10 x

FIL11 x

LID2 x

RXIF2

ESCI

BOFF

RJW0

BS22

LID9 x

ID9 x

FIL10 x

LID1 x

ID1 x

FIL2 x

RXIF1

RXIE

EPSV

BRP5

BS21

1 x

MSK9 x

MSK1 x

LID8 x

ID8 x

FIL9 x

LID0 x

ID0 x

FIL1 x

4 3 2 1 0

LID7 x

ID7 x

FIL8 x

LRTR x

RTR x

FIL0 x

TXIF

TXIE

SRTE

BRP4

BS20

SCIF

SCIE

NRTX

BRP3

BS13

LID6 x

ID6 x

FIL7 x

LDLC3 x

DLC3 x

BS12

PAGE2

LID5 x

ID5 x

ORIF

ORIE

FSYN

BRP2

FIL6 x

LDLC2 x

DLC2 x

EPND

ETX

RUN

BRP0

BS10

PAGE0

LID3 x

ID3 x

FIL4 x

LDLC0 x

DLC0 x

TEIF

TEIE

WKPS

BRP1

BS11

PAGE1

LID4 x

ID4 x

FIL5 x

LDLC1 x

DLC1 x

0 0 0 x

MSK8 x

MSK0 x x

MSK7 x

0 x

MSK6 x

0 x

MSK5 x

LSB x

MSK4 x

ACC

RDY

BUSY

LSB

LOCK

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10.8.5 List of CAN Cell Limitations

10.8.5.1 Omitted SOF bit

Symptom:

Start of Frame (SOF) bit is omitted if transmission is requested in the last Intermission bit.

Test Case:

5.3.1 10-Kbit Stress Test

Details:

The IUT is requested to start transmission immediately after the completion of the previous transmission. The LT also starts its transmission and asserts the SOF bit just after the 3 rd

Intermission bit.

The IUT also starts transmission but omits the

SOF bit. The IUT wins the arbitration and continues the transmission. The frame is sent correctly.

Impact On The Application:

As this effect only occurs when the IUT detects a

SOF bit on the CAN bus, the fact that it omits its own SOF bit has no impact on the communication.

10.8.5.2 CAN: CPU Write Access (More Than

One Cycle) Corrupts CAN Frame

Symptoms:

For CAN received messages the identifier high byte or last data byte can be corrupted.

For CAN transmitted messages the 2nd data byte can be corrupted.

Details:

The CAN transmit and receive buffers are implemented as dual ported RAM. During the reception of a CAN frame the CAN core writes the received identifier and the data byte-by-byte in the corresponding buffer.

IF the CAN bit timing configuration is t

BS2 quanta

< 5 time

AND

IF concurrently with the pCAN, the CPU executes a write access to the dual ported RAM using an instruction with more than one cycle access, e.g.

CLR, BSET, BRES

THEN the access conflict can lead to the corruption described in the symptoms paragraph above.

Impact On The Application:

Several CAN frames with erroneous data or identifier will be received/transmitted.

Software Workaround:

Program t

BS2

> 4 time quanta or, when accessing the receive or transmit buffers, do not use the critical instructions which are:

BSET, BRES, CLR, CPL, DEC, INC, NEG, RLC,

SLL, SRL, RRC, SRA, SWAP.

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10.8.5.3 Unexpected message transmission

Symptom:

The previous message received by pCAN, even if this message did not pass the receive filter, will be retransmitted by pCAN with a correct identifier and

DLC but with corrupted data. The data bytes will be a copy of the identifier bytes IDHR and IDLR in the following repetitive pattern:

DATA_0 = IDHR

DATA_1 = IDLR

DATA_2 = IDHR

DATA_3 = IDLR etc.

DATA_7 = IDLR

If no message has been received before the problem occurs then identifier byte values are random but the data bytes are in the same repetitive pattern.

Details:

The buffers of the pCAN cell are configurable as receive or transmit buffers. By default, all buffers are configured in reception. To use a buffer to transmit a CAN message the application has to reserve this buffer for transmission by setting the

LOCK bit in the BCSR register. So the buffer is then locked for any further reception and reserved for transmission.

Once a transmission has been requested by a write access to data byte 7 of the buffer the application might need to abort this transmission request. To do so, the application can reset the

LOCK bit in the BCSR register.

If the message is pending (RDY bit set) but not currently being transmitted, then clearing the

LOCK bit will abort it immediately.

If the message is pending (RDY bit set) and currently being transmitted then the message will not be interrupted but the CAN core will wait until the end of this transmission attempt. Then software must clear the LOCK bit again to abort the transmission.

An unexpected transmission can occur:

IF the application resets the LOCK bit

WHILE the CAN core is preparing the transmission

AND there is no other transmission pending in another buffer

THEN the LOCK bit is reset but the transmission is not stopped. Instead the content of the page 0 buffer will be transmitted.

Impact On The Application: pCAN will echo some messages sent by other nodes. Identifier and DLC will be correct but data are corrupted as described previously.

Note 1: The preparation lasts two bit times just before SOF, this is the critical window during which the LOCK bit must not be reset by the application.

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CONTROLLER AREA NETWORK (Cont’d)

Software Work-around - Devices with Hardware Fix (ST72F521 rev “R”):

To implement a transmission abort under safe conditions, the LOCK bit must not be reset during the critical window (2 bit times). A new function has been implemented in the MCU allowing the application to synchronize the reset of the LOCK bit (abort request) with the reset of the TXRQST bit

(internal signal) in the pCAN core.

The synchronization is done using the WKPS bit in the CANCSR register, the function of this bit has been modified and no more Wake-up Pulse (dominant bit) is sent on the CAN_TX signal when the

WKPS bit is set. This means the functionality described in the datasheet is no longer applicable

(see Section 10.8.5.4

To abort the transmission, first the application sets the WKPS bit and polls it until it is set. The maximum time needed to set this bit is two CAN bit times. Once the application has read the WKPS bit as one, it can reset the LOCK bit to stop the current transmission.

The abort is completed when the LOCK bit is read back as zero by the application. Once the abort has been completed, the application must reset the WKPS bit to be able to transmit again. Of course the transmit buffer must be in LOCK state as usual before any transmission attempt.

The “C” code sequence below shows the software work-around using the WKPS bit.

CANCSR |= WKPS; // Set WKPS bit while(!(CANCSR & WKPS) );// Wait until WKPS bit is set while( CANBCSR & LOCK )// Wait until abort has been confirmed

{

CANBCSR &= ~LOCK;

}

CANCSR &= ~WKPS; // Allow transmission again

CANBCSR |= LOCK; //Alloc buffer for next transmission

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CONTROLLER AREA NETWORK (Cont’d)

Software Work-around - Devices without Hardware Fix:

To implement a transmission abort under safe conditions, any reset of the LOCK bit during the critical window (2 bit times) must be avoided. Two different cases have to be considered, either the pCAN enters standby mode after the abort, or the abort is performed and pCAN keeps running.

Abort followed by STANDBY mode (RUN=0)

In this case, aborting the pending transmissions can safely be done by first entering STANDBY mode and then releasing the transmit buffers.

STANDBY mode is entered by resetting the RUN bit in the CSR register and once the current transmission attempt, even if it fails due to error or lost arbitration, has been performed, pCAN enters

STANDBY mode (RUN=0). Once in STANDBY mode the application can abort all pending transmissions by resetting the corresponding LOCK bit.

Abort while staying in RUN mode (RUN=1)

Contrary to the STANDBY case described previously, in the RUN case the application has to handle the error or arbitration lost conditions. In case of transmission errors, causing the frame to be transmitted again and again, the application must set the NRTX bit in the CSR register. This will cause pCAN to abort the transmission at the end of the current attempt.

In case of arbitration lost, setting the NRTX bit does not abort the transmission, therefore the application must reset the LOCK bit to abort the transmission. To avoid resetting the LOCK bit during the critical time window, leading to the problem described at the start of this section, the application must monitor the BUSY bit in the BCSR register and reset the LOCK bit just after the falling edge of the BUSY bit. The time between the falling edge of the BUSY bit and the SOF of the next transmission attempt is in any case long enough to guarantee that the LOCK bit is reset before the critical time window.

The “C” code sequence below shows the software work-around for both the error and arbitration lost cases.

_asm("SIM\n"); // Mask interrupts

CANCSR |= NRTX; // Set non automatic retransmission bit while(!(CANBCSR & BUSY) &&// Wait till BUSY bit is set

(CANBCSR & RDY) ); // or transmission done while( CANBCSR & BUSY ); // Wait till BUSY bit is reset (falling edge) if( CANBCSR & RDY )

{ // transmission still pending -> must be aborted

CANBCSR &= ~LOCK; //Arbitration lost => cancel transmission safel while( CANBCSR & RDY );// Wait for unlock confirmed

CANCSR &= ~NRTX;// Reset NRTX bit once abort sequence done

_asm("RIM\n");

} else

{ // No more abort required as RDY bit already reset

CANCSR &= ~NRTX;// Reset NRTX bit once abort sequence done

_asm("RIM\n"); // Enable interrupts

}

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Figure 75. Work-around Flowchart

Application Requests an Abort

YES

READY == 1

MASK INT

SET NRTX

YES

BUSY == 0

AND

READY == 1

YES

BUSY == 0

READY == 1

RESET LOCK

READY == 1

SET LOCK

YES

RESET NRTX

ENABLE INT

Abort Done

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CONTROLLER AREA NETWORK (Cont’d)

The figures below show the abort behaviour in the four possible cases.

Figure 76. Abort and successful transmission

TX RQST

ABORT RQST

CAN TX

CAN RX

LOCK

READY

BUSY

NRTX

In this case the abort request performed during the transmission has no effect, as the first transmission is successful.

Figure 77. Abort and transmission delayed by busy CAN bus

TX RQST

ABORT RQST

CAN TX

CAN RX

LOCK

READY

BUSY

NRTX

In this case the NRTX bit is set to abort the transmission after the first attempt. As the first attempt is successful the READY and BUSY bits are reset by pCAN and the transmit buffer becomes empty.

An abort is no longer required.

Figure 78. Abort and error during transmission

Error

TX RQST

ABORT RQST

CAN TX

CAN RX

LOCK

READY

BUSY

NRTX the error (the first attempt). The abort has been successful and the transmit buffer is empty.

Figure 79. Abort and arbitration lost

TX RQST

ABORT RQST

CAN TX

CAN RX

LOCK

READY

BUSY

NRTX

In this case the NRTX bit is set but has no effect, as the previous transmission attempt failed due to an arbitration lost. The application waits for the falling edge of BUSY bit and checks that READY is still set. This is the case, this means pCAN has lost the arbitration and LOCK bit can be safely reset.

Abort is immediate and pCAN resets the READY and BUSY bits.

Timing Considerations

As no interrupt signals that an abort has been successful, the application has to wait until the transmit buffer is empty (transmission has been aborted or transmitted successfully). This time can vary depending on the case in which the abort is performed (arbitration lost, error or successful transmission). To show the impact of the software work-

around on this timing behaviour Figure 80 and

Figure 81

compare the reference behaviour (worst case when abort is done by LOCK only) with the behaviour when NRTX, BUSY and LOCK bits are used.

Figure 80. Abort by LOCK only - Reference behaviour

TX RQST

ABORT RQST

CAN TX

CAN RX

LOCK

READY

BUSY

NRTX

In this case NRTX (abort request) is set before the error, thus pCAN resets READY and BUSY after

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CONTROLLER AREA NETWORK (Cont’d)

The worst case is when the abort request is done when the transmission has just started. In this case the LOCK bit cannot be reset as long as the

BUSY bit is set, this means until the end of the frame. So the application will wait for READY to be reset during the whole frame and in this case the worst case will be the longest frame the application is expected to transmit.

Figure 81. Abort with the software work-around

- by NRTX, BUSY and LOCK

TX RQST

ABORT RQST

CAN TX

CAN RX

LOCK

READY

BUSY

NRTX

Using the software work-around the worst case occurs in the arbitration lost case. If the abort is requested just after pCAN has lost the arbitration then the application has to wait for the next falling edge of the BUSY bit before the LOCK bit can be reset. If the next arbitration is won by pCAN then the BUSY bit will be reset by the end of the successful transmission. The longest time the application has to wait in this case is the time of the longest message expected on the bus (minus identifier) plus the longest message expected to be transmitted by the application. This roughly double the time the application may have to wait before the abort sequence is performed.

10.8.5.4 WKPS Functionality

Due to a fix implemented to solve the “Unexpected

Message Transmission” issue (see

set of the LOCK bit (see “Software

10.8.5.3

) the WKPS functionality has been modified as follows in Flash ST72F521 devices:

Device

Flash

ST72F521

Rev R

Modification

WKPS bit does not generate a wakeup pulse. It is used to synchronize the re-

Work-around - Devices with Hardware

Fix (ST72F521 rev “R”):” on page 148 )

ROM

ST72521 All revisions

WKPS bit functions according to the datasheet description.

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CONTROLLER AREA NETWORK (Cont’d)

10.8.5.5 Bus-off state not entered

Symptom: pCAN does not enter bus-off state under certain conditions. This is fixed in FLASH version of

ST72F521 starting from silicon Rev R and in ROM version ST72521B starting from silicon Rev Y.

Details:

According to the CAN standard, pCAN is expected to enter bus-off state when TEC (Transmit Error

Counter) is greater than 255.

But if REC (Receive Error Counter) is greater than

127 (Error Passive State) pCAN does not enter bus-off and the BOFF bit of the CSR register is not set. To enter bus-off, REC must decrease to a value lower than 128, this is the case with any correct reception even if the message is filtered out.

As bus-off state is not entered and pCAN still attempts to transmit its message, after the overflow the TEC register continues to increment as long as transmission errors occur.

Impact on the application:

The application will not stop attempting to transmit

CAN messages, even when the bus-off conditions have been reached, until the transmission has been successful or the value of REC becomes lower than 128. However the application will not disturb the communication of the other nodes on the CAN network as pCAN is in Error Passive

State.

Figure 82. CAN Error State Diagram showing “BUSOFF not entered” limitation

When TECR or RECR > 127, the EPSV bit gets set

ERROR ACTIVE

ERROR PASSIVE

When 128 * 11 recessive bits occur:

- the BOFF bit gets cleared

- the TECR register gets cleared

- the RECR register gets cleared

When TECR and RECR < 128, the EPSV bit gets cleared

When TECR > 255 and RECR < 128 the BOFF bit

gets set and the EPSV bit gets cleared

BUS OFF

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Workaround Description

The bus-off entry works correctly in almost all cases, only when REC is greater than 127 a bus-off will not be recognized by pCAN. Therefore the pCAN bus-off signalling (BOFF) is still used but it needs to be complemented by monitoring TEC by software.

To detect the bus-off condition by software the application has to monitor the value of the TEC register periodically. An overflow signals a bus-off condition. When a bus-off condition has been detected the application must execute the following sequence to recover from bus-off properly: the application stops pCAN by clearing the RUN bit in the

CANCSR register resets all pending transmission by clearing the LOCK bit in the BCSR register and starts it again by setting the RUN bit.

To detect the bus-off condition properly, the TEC monitoring period must be lower than the time between two overflows. As the problem only occurs when pCAN is in Error Passive State (REC > 127) pCAN will continuously try to send a SOF followed by an Error Passive Flag and a Suspend Transmission. This leads to 26 (1 + 6 + 8 + 3 + 8) bit times. Each time TEC is incremented by 8, hence

* ***********************************************/

/* INITIALISATION

/************************************************/ unsigned char TECReg=0; //Previous value of TEC unsigned char BusOffFlag=0; //Set to one if bus-off to reach 256 the sequence must be executed 32 times. Under these conditions the shortest sequence leading to a TEC overflow lasts 832 bit times.

Depending on the baudrate the application will have to adapt the monitoring period, for example at 500kbps the period must be less than 1600us.

The ‘C’ code below shows an implementation example of the monitoring sequence. This code is called periodically as described above.

To detect the overflow, the test condition must take into account that TEC might also have been decremented due to a successful transmission. So an overflow condition is detected:

IF the current TEC value is lower than the previous

TEC value

AND the difference is greater than the number of possible successful transmissions during the monitoring period.

In the example above, one message can be sent, therefore one is added to CANTECR.

/************************************************/

/* BUS-OFF MONITORING SEQUENCE

/************************************************/ if( (CANCSR & BOFF) || ( CANTECR+1 < TECReg) )

{

BusOffFlag = 1;

} else

{

TECReg = CANTECR;

}

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10.9 10-BIT A/D CONVERTER (ADC)

10.9.1 Introduction

The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources.

The result of the conversion is stored in a 10-bit

Data Register. The A/D converter is controlled through a Control/Status Register.

Figure 83. ADC Block Diagram f

CPU DIV 4

0 f

ADC

DIV 2 1

10.9.2 Main Features

■ 10-bit conversion

■

Up to 16 channels with multiplexed input

Linear successive approximation

■

Data register (DR) which contains the results

Conversion complete status flag

On/off bit (to reduce consumption)

The block diagram is shown in

Figure 83 .

EOC SPEED ADON 0 CH3 CH2 CH1 CH0 ADCCSR

AIN0

AIN1

AINx

ANALOG

MUX

ANALOG TO DIGITAL

CONVERTER

ADCDRH D9 D8 D7 D6 D5 D4 D3 D2

ADCDRL 0 0 0 0 0 0 D1 D0

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10.9.3 Functional Description

The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not.

If the input voltage (V

AIN

) is greater than V

AREF

(high-level voltage reference) then the conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without overflow indication).

If the input voltage (V

AIN

) is lower than V

SSA

(lowlevel voltage reference) then the conversion result in the ADCDRH and ADCDRL registers is 00 00h.

The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH and AD-

CDRL registers. The accuracy of the conversion is described in the Electrical Characteristics Section.

AIN

is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time.

10.9.3.1 A/D Converter Configuration

The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the «I/O ports» chapter. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input.

In the ADCCSR register:

– Select the CS[3:0] bits to assign the analog channel to convert.

10.9.3.2 Starting the Conversion

In the ADCCSR register:

– Set the ADON bit to enable the A/D converter and to start the conversion. From this time on, the ADC performs a continuous conversion of the selected channel.

To read the 10 bits, perform the following steps:

1. Poll the EOC bit

2. Read the ADCDRL register

3. Read the ADCDRH register. This clears EOC automatically.

Note: The data is not latched, so both the low and the high data register must be read before the next conversion is complete, so it is recommended to disable interrupts while reading the conversion result.

To read only 8 bits, perform the following steps:

1. Poll the EOC bit

2. Read the ADCDRH register. This clears EOC automatically.

10.9.3.3 Changing the conversion channel

The application can change channels during conversion. When software modifies the CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is cleared, and the A/D converter starts converting the newly selected channel.

10.9.4 Low Power Modes

Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed and between single shot conversions.

Mode Description

WAIT No effect on A/D Converter

A/D Converter disabled.

HALT

After wakeup from Halt mode, the A/D

Converter requires a stabilization time t

STAB

(see Electrical Characteristics) before accurate conversions can be performed.

When a conversion is complete:

– The EOC bit is set by hardware.

– The result is in the ADCDR registers.

A read to the ADCDRH resets the EOC bit.

10.9.5 Interrupts

None.

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10-BIT A/D CONVERTER (ADC) (Cont’d)

10.9.6 Register Description

CONTROL/STATUS REGISTER (ADCCSR)

Read/Write (Except bit 7 read only)

Reset Value: 0000 0000 (00h)

7 0

EOC SPEED ADON 0 CH3 CH2 CH1 CH0

Bit 7 = EOC End of Conversion

This bit is set by hardware. It is cleared by hardware when software reads the ADCDRH register or writes to any bit of the ADCCSR register.

0: Conversion is not complete

1: Conversion complete

Bit 6 = SPEED ADC clock selection

This bit is set and cleared by software.

0: f

ADC

= f

CPU

1: f

ADC

= f

CPU

Bit 5 = ADON A/D Converter on

This bit is set and cleared by software.

0: Disable ADC and stop conversion

1: Enable ADC and start conversion

Bit 4 = Reserved. Must be kept cleared.

Bit 3:0 = CH[3:0] Channel Selection

These bits are set and cleared by software. They select the analog input to convert.

Channel Pin*

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

AIN10

AIN11

AIN12

AIN13

AIN14

AIN15

CH3

CH2

CH1

CH0

*The number of channels is device dependent. Refer to the device pinout description.

DATA REGISTER (ADCDRH)

Read Only

Reset Value: 0000 0000 (00h)

D9 D8 D7 D6 D5 D4 D3

Bit 7:0 = D[9:2] MSB of Converted Analog Value

DATA REGISTER (ADCDRL)

Read Only

Reset Value: 0000 0000 (00h)

7 0

0 0 0 0 0 0 D1

Bit 7:2 = Reserved. Forced by hardware to 0.

Bit 1:0 = D[1:0] LSB of Converted Analog Value

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10-BIT A/D CONVERTER (Cont’d)

Table 25. ADC Register Map and Reset Values

Address

(Hex.)

0070h

0071h

0072h

Register

Label

ADCCSR

Reset Value

ADCDRH

Reset Value

ADCDRL

Reset Value

EOC

SPEED

ADON

CH3

CH2

CH1

CH0

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11 INSTRUCTION SET

11.1 CPU ADDRESSING MODES

The CPU features 17 different addressing modes which can be classified in 7 main groups:

Addressing Mode

Inherent

Immediate

Direct

Indexed

Indirect

Relative

Bit operation

Bit

Inherent

Immediate

Short

Long

No Offset

Short

Long

Short

Long

Short

Long

Relative

Example nop ld A,#$55 ld A,$55 ld A,($55,X) ld A,([$55],X) jrne loop bset byte,#5 so, most of the addressing modes may be subdivided in two sub-modes called long and short:

– Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles.

– Short addressing mode is less powerful because it can generally only access page zero (0000h -

00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only

(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,

INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)

The ST7 Assembler optimizes the use of long and short addressing modes.

The CPU Instruction set is designed to minimize the number of bytes required per instruction: To do

Table 26. CPU Addressing Mode Overview

Mode Syntax Destination

Pointer

Address

(Hex.)

Direct

Indirect

Indexed nop ld A,#$55 ld A,$10 ld A,$1000 ld A,(X)

Indexed ld A,($10,X)

Indexed ld A,($1000,X) ld A,[$10] ld A,[$10.w]

Indirect Indexed ld A,([$10],X)

Indirect Indexed ld A,([$10.w],X)

Direct

Indirect jrne loop jrne [$10]

00..FF

0000..FFFF

00..FF

00..1FE

0000..FFFF

00..FF

0000..FFFF

00..FF

00..1FE

00..FF

0000..FFFF

00..FF

PC+/-127

PC+/-127 00..FF

Direct

Indirect bset $10,#7 bset [$10],#7

00..FF

Direct Relative btjt $10,#7,skip 00..FF

Indirect Relative btjt [$10],#7,skip 00..FF

00..FF

Pointer Size

(Hex.) byte word byte word byte byte byte

Length

(Bytes)

+ 2

+ 1

+ 2

+ 1

+ 2

+ 1

+ 2

+ 3

+ 0

+ 1

+ 2

+ 0

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INSTRUCTION SET OVERVIEW (Cont’d)

11.1.1 Inherent

All Inherent instructions consist of a single byte.

The opcode fully specifies all the required information for the CPU to process the operation.

Inherent Instruction

NOP

TRAP

WFI

HALT

RET

IRET

SIM

RIM

SCF

RCF

RSP

CLR

PUSH/POP

INC/DEC

TNZ

CPL, NEG

MUL

SLL, SRL, SRA, RLC,

RRC

SWAP

Function

No operation

S/W Interrupt

Wait For Interrupt (Low Power Mode)

Halt Oscillator (Lowest Power

Mode)

Sub-routine Return

Interrupt Sub-routine Return

Set Interrupt Mask (level 3)

Reset Interrupt Mask (level 0)

Set Carry Flag

Reset Carry Flag

Reset Stack Pointer

Load

Clear

Push/Pop to/from the stack

Increment/Decrement

Test Negative or Zero

1 or 2 Complement

Byte Multiplication

Shift and Rotate Operations

Swap Nibbles

11.1.2 Immediate

Immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value.

Immediate Instruction

Function

Load

Compare

BCP

AND, OR, XOR

Bit Compare

Logical Operations

ADC, ADD, SUB, SBC Arithmetic Operations

11.1.3 Direct

In Direct instructions, the operands are referenced by their memory address.

The direct addressing mode consists of two submodes:

Direct (short)

The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF addressing space.

Direct (long)

The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode.

11.1.4 Indexed (No Offset, Short, Long)

In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset.

The indirect addressing mode consists of three sub-modes:

Indexed (No Offset)

There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space.

Indexed (Short)

The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing space.

Indexed (long)

The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode.

11.1.5 Indirect (Short, Long)

The required data byte to do the operation is found by its memory address, located in memory (pointer).

The pointer address follows the opcode. The indirect addressing mode consists of two sub-modes:

Indirect (short)

The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode.

Indirect (long)

The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.

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INSTRUCTION SET OVERVIEW (Cont’d)

11.1.6 Indirect Indexed (Short, Long)

This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode.

The indirect indexed addressing mode consists of two sub-modes:

Indirect Indexed (Short)

The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode.

Indirect Indexed (Long)

The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.

Table 27. Instructions Supporting Direct,

Indexed, Indirect and Indirect Indexed

Addressing Modes

Long and Short

Instructions

AND, OR, XOR

ADC, ADD, SUB, SBC

BCP

Function

Load

Compare

Logical Operations

Arithmetic Additions/Substractions operations

Bit Compare

11.1.7 Relative mode (Direct, Indirect)

This addressing mode is used to modify the PC register value, by adding an 8-bit signed offset to it.

Available Relative

Direct/Indirect

Instructions

JRxx

CALLR

Function

Conditional Jump

Call Relative

The relative addressing mode consists of two submodes:

Relative (Direct)

The offset is following the opcode.

Relative (Indirect)

The offset is defined in memory, which address follows the opcode.

Short Instructions

Only

CLR

INC, DEC

TNZ

CPL, NEG

BSET, BRES

BTJT, BTJF

SLL, SRL, SRA, RLC,

RRC

SWAP

CALL, JP

Function

Clear

Increment/Decrement

Test Negative or Zero

1 or 2 Complement

Bit Operations

Bit Test and Jump Operations

Shift and Rotate Operations

Swap Nibbles

Call or Jump subroutine

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INSTRUCTION SET OVERVIEW (Cont’d)

11.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may

Load and Transfer

Stack operation

Increment/Decrement

Compare and Tests

Logical operations

Bit Operation

Conditional Bit Test and Branch

Arithmetic operations

Shift and Rotates

Unconditional Jump or Call

Conditional Branch

Interruption management

Condition Code Flag modification

LD CLR

PUSH POP

INC DEC

AND

BSET

TNZ

BRES

BTJT

ADC

SLL

JRA

JRxx

TRAP WFI

SIM RIM

BTJF

ADD

SRL

JRT be subdivided into 13 main groups as illustrated in the following table:

RSP

BCP

XOR

SUB

SRA

JRF

CPL

SBC MUL

RLC

RRC SWAP

CALL CALLR

HALT IRET

SCF RCF

NEG

SLA

NOP RET

Using a pre-byte

The instructions are described with one to four opcodes.

In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede.

The whole instruction becomes:

PC-2 End of previous instruction

PC-1

Prebyte opcode

PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address

These prebytes enable instruction in Y as well as indirect addressing modes to be implemented.

They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are:

PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one.

PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode.

It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode.

PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.

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INSTRUCTION SET OVERVIEW (Cont’d)

Mnemo

ADC

ADD

AND

BCP

BRES

BSET

BTJF

BTJT

CALL

Description

Add with Carry

Addition

Jump if bit is false (0)

Jump if bit is true (1)

Call subroutine

Function/Example

A = A + M + C

A = A + M

Logical And A = A . M

Bit compare A, Memory tst (A . M)

Bit Reset

Bit Set bres Byte, #3 bset Byte, #3 btjf Byte, #3, Jmp1 btjt Byte, #3, Jmp1

CALLR Call subroutine relative

CLR Clear

CPL

DEC

HALT

IRET

INC

JRA

JRT

JRF

JRIH

Arithmetic Compare

One Complement tst(Reg - M)

A = FFH-A dec Y Decrement

Halt

Interrupt routine return

Increment

Absolute Jump

Pop CC, A, X, PC inc X jp [TBL.w]

Jump relative always

Jump relative

Never jump jrf *

Jump if ext. INT pin = 1 (ext. INT pin high)

JRIL

JRH

JRNH

JRM

JRNM

JRMI

JRPL

JREQ

JRNE

Jump if ext. INT pin = 0

Jump if H = 1

Jump if H = 0

Jump if I1:0 = 11

Jump if I1:0 <> 11

Jump if N = 1 (minus)

Jump if N = 0 (plus)

JRC

JRNC

Jump if C = 1

Jump if C = 0

JRULT Jump if C = 1

JRUGE Jump if C = 0

JRUGT Jump if (C + Z = 0)

(ext. INT pin low)

H = 1 ?

H = 0 ?

I1:0 = 11 ?

I1:0 <> 11 ?

N = 1 ?

N = 0 ?

Jump if Z = 1 (equal) Z = 1 ?

Jump if Z = 0 (not equal) Z = 0 ?

C = 1 ?

C = 0 ?

Unsigned <

Jmp if unsigned >=

Unsigned >

Dst reg, M reg reg, M reg, M reg, M

Src

I1 H I0 N Z C

H N Z C

N Z

0 1

N Z C

N Z 1

N Z

1 0

I1 H I0 N Z C

N Z

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ST72F521, ST72521B

INSTRUCTION SET OVERVIEW (Cont’d)

Mnemo Description

JRULE Jump if (C + Z = 1)

LD Load

MUL

NEG

NOP

Multiply

Negate (2's compl)

No Operation

OR operation

Function/Example

Unsigned <= dst <= src

X,A = X * A neg $10

POP Pop from the Stack

A = A + M pop reg pop CC push Y

C = 0

PUSH

RCF

RET

RIM

RLC

RRC

RSP

SBC

SCF

SIM

Push onto the Stack

Reset carry flag

Subroutine Return

Enable Interrupts

Rotate left true C

Rotate right true C

Reset Stack Pointer

Substract with Carry

Set carry flag

Disable Interrupts

SLA

SLL

SRL

SRA

Shift left Arithmetic

Shift left Logic

Shift right Logic

Shift right Arithmetic

SUB Substraction

SWAP SWAP nibbles

TNZ

TRAP

WFI

XOR

Test for Neg & Zero

S/W trap

Wait for Interrupt

Exclusive OR

I1:0 = 10 (level 0)

C <= A <= C

C => A => C

S = Max allowed

A = A - M - C

C = 1

I1:0 = 11 (level 3)

C <= A <= 0

0 => A => C

A7 => A => C

A = A - M

A7-A4 <=> A3-A0 tnz lbl1

S/W interrupt

A = A XOR M

Dst

M reg, CC

Src reg, M M, reg

A, X, Y X, Y, A reg, M

A reg

M reg, M reg, M

A reg, M reg, M reg, M reg, M

A reg, M

I1 H I0 N Z C

N Z

N Z C

N Z

I1 H I0 N Z C

N Z C

0 Z C

N Z C

N Z

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12 ELECTRICAL CHARACTERISTICS

12.1 PARAMETER CONDITIONS

Unless otherwise specified, all voltages are referred to V

12.1.1 Minimum and Maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T

A and T

A range).

=25°C max (given by the selected temperature

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3 Σ ).

12.1.2 Typical values

Unless otherwise specified, typical data are based on T

=25°C, V

=5V.They are given only as design guidelines and are not tested.

12.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

12.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in

Figure 84

Figure 84. Pin loading conditions

Figure 85. Pin input voltage

ST7 PIN

12.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in

Figure 85 .

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ST72F521, ST72521B

12.2 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these condi-

12.2.1 Voltage Characteristics tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol Ratings

- V

Supply voltage

Programming Voltage

1) & 2)

Input Voltage on true open drain pin

ESD(MM)

Input voltage on any other pin

∆

DDx

| and |

∆

SSx

| Variations between different digital power pins

SSA

- V

SSx

| Variations between digital and analog ground pins

ESD(HBM)

Electro-static discharge voltage (Human Body Model)

Electro-static discharge voltage (Machine Model)

12.2.2 Current Characteristics

Maximum value

6.5

-0.3 to 6.5

-0.3 to V

+0.3

Unit

V mV see

section 12.7.3 on page 181

Symbol

VDD

VSS

Ratings

Total current into V

power lines (source)

Total current out of V

ground lines (sink)

Output current sunk by any standard I/O and control pin

Output current sunk by any high sink I/O pin

Maximum value

150

Unit mA

Output current source by any I/Os and control pin - 25

Injected current on V

Injected current on RESET pin

± 5

± 5 mA

INJ(PIN)

2) & 4)

Injected current on OSC1 and OSC2 pins ± 5

Injected current on PC6 (Flash devices only)

Injected current on any other pin

5) & 6)

Total injected current (sum of all I/O and control pins)

+ 5

± 5

INJ(PIN)

± 25

Notes:

1. Directly connecting the RESET and I/O pins to V

or V

SS could damage the device if an unintentional internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).

To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k

Ω

for

RESET, 10k

Ω

for I/Os). For the same reason, unused I/O pins must not be directly tied to V

2. I

INJ(PIN)

must never be exceeded. This is implicitly insured if V

or V

maximum cannot be respected, the injection current must be limited externally to the I while a negative injection is induced by V

maximum must always be respected

maximum is respected. If V

INJ(PIN)

value. A positive injection is induced by V

. For true open-drain pads, there is no positive injection current, and the corresponding V

3. All power (V

) and ground (V

) lines must always be connected to the external supply.

4. Negative injection disturbs the analog performance of the device. See note in “ADC Accuracy” on page 196 .

For best reliability, it is recommended to avoid negative injection of more than 1.6mA.

5. When several inputs are submitted to a current injection, the maximum

I and negative injected currents (instantaneous values). These results are based on characterisation with

I mum current injection on four I/O port pins of the device.

INJ(PIN)

is the absolute sum of the positive

INJ(PIN)

maxi-

6. True open drain I/O port pins do not accept positive injection.

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ST72F521, ST72521B

12.2.3 Thermal Characteristics

Symbol

STG

Ratings Value

Storage temperature range -65 to +150

Maximum junction temperature (see Section 13.2 THERMAL CHARACTERISTICS )

Unit

°C

12.3 OPERATING CONDITIONS

12.3.1 General Operating Conditions

Symbol f

CPU

Parameter

Internal clock frequency

Conditions

Standard voltage range (except Flash

Write/Erase)

Operating Voltage for Flash Write/Erase V

= 11.4 to 12.6V

1 Suffix Version

5 Suffix Version

Ambient temperature range 6 or A Suffix Versions

7 or B Suffix Versions

C Suffix Version

Figure 86. f

CPU

Max Versus V

Min

3.8

4.5

-10

-40

Max

5.5

105

125

Unit

MHz

°C f

CPU

[MHz]

FUNCTIONALITY

NOT GUARANTEED

IN THIS AREA

3.5

3.8

4.0

4.5

SUPPLY VOLTAGE [V]

5.5

FUNCTIONALITY

GUARANTEED

IN THIS AREA

(UNLESS

OTHERWISE

SPECIFIED

IN THE TABLES

OF PARAMETRIC

DATA)

Note: Some temperature ranges are only available with a specific package and memory size. Refer to Ordering Information.

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ST72F521, ST72521B

OPERATING CONDITIONS (Cont’d)

12.3.2 Operating Conditions with Low Voltage Detector (LVD)

Subject to general operating conditions for V

, f

CPU

, and T

Symbol

IT+(LVD)

IT-(LVD)

V hys(LVD)

POR t g(VDD)

Reset release threshold

rise)

Reset generation threshold

fall)

Parameter Conditions Min

VD level = High in option byte 4.0

VD level = Med. in option byte

VD level = Low in option byte

3.55

2.95

VD level = High in option byte

VD level = Med. in option byte

VD level = Low in option byte

3.8

3.35

2.8

LVD voltage threshold hysteresis

IT+(LVD)

-V

IT-(LVD)

150

rise time

1)2)

Flash device, LVD enabled

ROM device, LVD enabled

µ s/V

glitches filtered (not detected) by LVD

Typ

4.2

3.75

3.15

4.0

3.55

3.0

200

Max

4.5

4.0

3.35

4.25

3.75

3.15

250

20ms/V

100ms/V

Unit

V mV ns

Notes:

1. Data based on characterization results, tested in production for ROM devices only.

2. When Vt

POR

IT+(LVD)

is faster than 100

threshold.

µ s/V, the Reset signal is released after a delay of max. 42µs after V

crosses the

3. If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range.

Below 3.8V, device operation is not guaranteed.

12.3.3 Auxiliary Voltage Detector (AVD) Thresholds

Subject to general operating conditions for V

, f

CPU

, and T

Symbol

IT+(AVD)

IT-(AVD) hys(AVD)

∆

IT-

⇒

0 AVDF flag toggle threshold rise)

1 AVDF flag toggle threshold

fall)

Parameter

AVD voltage threshold hysteresis

Voltage drop between AVD flag set and LVD reset activated

IT+(AVD)

Conditions

VD level = High in option byte

VD level = Med. in option byte

VD level = Low in option byte

VD level = High in option byte

VD level = Med. in option byte

VD level = Low in option byte

-V

IT-(AVD)

-V

IT-(LVD)

1. Data based on characterization results, tested in production for ROM devices only.

Min

4.4

3.95

3.4

4.2

3.75

3.2

Typ

4.6

4.15

3.6

4.4

4.0

3.4

200

450

Max

4.9

4.4

3.8

4.65

4.2

3.6

Unit

V mV mV

12.3.4 External Voltage Detector (EVD) Thresholds

Subject to general operating conditions for V

, f

CPU

, and T

Symbol

IT+(EVD)

IT-(EVD)

V hys(EVD)

Parameter

⇒

0 AVDF flag toggle threshold

DD rise)

⇒

1 AVDF flag toggle threshold

fall)

EVD voltage threshold hysteresis V

IT+(EVD)

Conditions

-V

IT-(EVD)

1. Data based on characterization results, not tested in production.

Min

1.15

1.1

Typ

1.26

1.2

200

Max

1.35

1.3

Unit

V mV

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12.4 SUPPLY CURRENT CHARACTERISTICS

The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consumption, the two current values must be added (except for HALT mode for which the clock is stopped).

12.4.1 CURRENT CONSUMPTION

Symbol Parameter Conditions

Flash Devices ROM Devices

Unit

Supply current in RUN mode

Supply current in SLOW mode

Supply current in WAIT mode

Supply current in SLOW WAIT mode

Supply current in HALT mode

Supply current in ACTIVE-HALT mode

4) f f f

OSC f

OSC

=2MHz, f

CPU

=4MHz, f

CPU

=8MHz, f

CPU

=16MHz, f

=1MHz

=2MHz

=4MHz

CPU

=8MHz f f f

OSC f

OSC

=2MHz, f

CPU

=4MHz, f

CPU

=8MHz, f

CPU

=16MHz, f

=62.5kHz

=125kHz

=250kHz

CPU

=500kHz f f f

OSC f

OSC

=2MHz, f

CPU

=4MHz, f

CPU

=8MHz, f

CPU

=16MHz, f

=1MHz

=2MHz

=4MHz

CPU

=8MHz f f f

OSC f

OSC

=2MHz, f

CPU

=4MHz, f

CPU

=8MHz, f

CPU

=16MHz, f

=62.5kHz

=125kHz

=250kHz

CPU

=500kHz

-40°C

≤

+85°C

-40°C

≤

+125°C f f

OSC

=2MHz

=4MHz f

OSC

=8MHz f

OSC

=16MHz

1.3

2.0

3.6

7.1

600

700

800

1100

1.0

1.5

2.5

4.5

580

650

770

1050

160

325

650

100

200

1.3

2.0

3.3

6.0

200

300

600

1200

2.0

3.0

5.0

10.0

1800

2100

2400

3000

120

1.0

1.5

2.5

4.5

100

200

350

1.3

2.0

3.6

7.1

600

700

800

1100

3.0

4.0

5.0

7.0

1200

1300

1800

2000

3.0

5.0

8.0

15.0

2700

3000

3600

4000

No max. guaranteed mA

µ mA

Notes:

1. Data based on characterization results, tested in production at V

max. and f

CPU

max.

2. Measurements are done in the following conditions:

- Program executed from RAM, CPU running with RAM access. The increase in consumption when executing from Flash is 50%.

- All I/O pins in input mode with a static value at V

or V

(no load)

- All peripherals in reset state.

- LVD disabled.

- Clock input (OSC1) driven by external square wave.

- In SLOW and SLOW WAIT mode, f

CPU

is based on f

OSC

divided by 32.

To obtain the total current consumption of the device, add the clock source (

Section 12.4.2

) and the peripheral power

consumption ( Section 12.4.3

3. All I/O pins in push-pull 0 mode (when applicable) with a static value at V

DD based on characterization results, tested in production at V

max. and f

CPU

or VSS (no load), LVD disabled. Data

max.

4. Data based on characterisation results, not tested in production. All I/O pins in push-pull 0 mode (when applicable) with a static value at V

or V

(no load); clock input (OSC1) driven by external square wave, LVD disabled. To obtain the

total current consumption of the device, add the clock source consumption ( Section 12.4.2

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ST72F521, ST72521B

SUPPLY CURRENT CHARACTERISTICS (Cont’d)

12.4.1.1 Power Consumption vs f

CPU

: Flash Devices

Figure 87. Typical I

in RUN mode Figure 89. Typical I

in WAIT mode

8MHz

4MHz

2MHz

1MHz

8MHz

4MHz

2MHz

1MHz

3.2

3.6

4 4.4

Vdd (V)

4.8

5.2

5.5

3.2

3.6

4 4.4

Vdd (V)

4.8

5.2

Figure 88. Typical I

1.20

1.00

0.80

0.60

0.40

0.20

0.00

3.2

500kHz

250kHz

125kHz

62.5kHz

3.6

in SLOW mode

4 4.4

Vdd (V)

4.8

5.2

5.5

0.60

0.40

0.20

0.00

Figure 90. Typ. I

in SLOW-WAIT mode

1.20

1.00

500kHz

250kHz

125kHz

62.5kHz

0.80

3.2

3.6

4 4.4

Vdd (V)

4.8

5.2

5.5

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ST72F521, ST72521B

SUPPLY CURRENT CHARACTERISTICS (Cont’d)

12.4.2 Supply and Clock Managers

The previous current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consumption, the two current values must be added (except for HALT mode).

Symbol

DD(RCINT)

Parameter

Supply current of internal RC oscillator

DD(RES)

DD(PLL)

DD(LVD)

Supply current of resonator oscillator

1) & 2)

PLL supply current

LVD supply current

= 5V

Conditions Typ Max

625

see section

12.5.3 on page

174

360

150 300

Unit

Notes:

1.. Data based on characterization results done with the external components specified in

Section 12.5.3

, not tested in

production.

2. As the oscillator is based on a current source, the consumption does not depend on the voltage.

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ST72F521, ST72521B

SUPPLY CURRENT CHARACTERISTICS (Cont’d)

12.4.3 On-Chip Peripherals

Measured on S72F521R9T3 on TQFP64 generic board T

= 25°C f

CPU

=4MHz.

Symbol

DD(TIM)

DD(ART)

DD(SPI)

DD(SCI)

DD(I2C)

DD(ADC)

DD(CAN)

Parameter

16-bit Timer supply current

ART PWM supply current

SPI supply current

SCI supply current

I2C supply current

ADC supply current when converting

CAN supply current

Conditions

5.0V

Typ

400

175

400

Notes:

1. Data based on a differential I

measurement between reset configuration (timer counter running at f

CPU

/4) and timer counter stopped (only TIMD bit set). Data valid for one timer.

2. Data based on a differential I

(only TCE bit set).

measurement between reset configuration (timer stopped) and timer counter enabled

3. Data based on a differential I

measurement between reset configuration (SPI disabled) and a permanent SPI master communication at maximum speed (data sent equal to 55h).This measurement includes the pad toggling consumption.

4. Data based on a differential I

DD mit sequence.

measurement between SCI low power state (SCID=1) and a permanent SCI data trans-

5. Data based on a differential I

measurement between reset configuration (I2C disabled) and a permanent I2C master communication at 100kHz (data sent equal to 55h). This measurement include the pad toggling consumption (27kOhm external pull-up on clock and data lines).

6. Data based on a differential I

measurement between reset configuration and continuous A/D conversions.

7. Data based on a differential IDD measurement between reset configuration (CAN disabled) and a permanent CAN data transmit sequence with RX and TX connected together. This measurement include the pad toggling consumption.

Unit

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ST72F521, ST72521B

12.5 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating conditions for V

, f

CPU

, and T

12.5.1 General Timings

Symbol Parameter Conditions t c(INST)

Instruction cycle time f

CPU

=8MHz t v(IT)

Interrupt reaction time

2) t v(IT)

∆ t c(INST)

+ 10 f

CPU

=8MHz

12.5.2 External Clock Source

Symbol

OSC1H

OSC1L t w(OSC1H) t w(OSC1L) t r(OSC1) t f(OSC1)

Parameter

OSC1 input pin high level voltage

OSC1 input pin low level voltage

OSC1 high or low time

OSC1 rise or fall time

OSC1 Input leakage current

Conditions

see Figure 91

≤

Figure 91. Typical Application with an External Clock Source

OSC1H

90%

10%

OSC1L t r(OSC1) t f(OSC1) t w(OSC1H)

Min

250

1.25

Typ

375

Max

1500

2.75

Min

-1

Typ t w(OSC1L)

Max

Unit

±1 ns

Unit t

CPU ns t

CPU

µ s

EXTERNAL

CLOCK SOURCE

OSC2

OSC1

Not connected internally f

OSC

ST72XXX

Notes:

1. Data based on typical application software.

2. Time measured between interrupt event and interrupt vector fetch.

∆ t c(INST) the current instruction execution.

is the number of t

CPU

cycles needed to finish

3. Data based on design simulation and/or technology characteristics, not tested in production.

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ST72F521, ST72521B

CLOCK AND TIMING CHARACTERISTICS (Cont’d)

12.5.3 Crystal and Ceramic Resonator Oscillators

The ST7 internal clock can be supplied with four different Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...).

Symbol f

OSC

Parameter

Oscillator Frequency

Conditions

LP: Low power oscillator

MP: Medium power oscillator

MS: Medium speed oscillator

HS: High speed oscillator

Feedback resistor

Recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (R

)

=200

Ω

=200

Ω

=200

Ω

=100

Ω

LP oscillator

MP oscillator

MS oscillator

HS oscillator

Min

Max

Unit

MHz k

Ω pF

Unit i

Symbol Parameter

OSC2 driving current

=5V

Conditions

LP oscillator

MP oscillator

MS oscillator

HS oscillator

Figure 92. Typical Application with a Crystal or Ceramic Resonator

WHEN RESONATOR WITH

INTEGRATED CAPACITORS i

Typ

160

310

610 f

OSC

L1 OSC1

Max

150

250

460

910

RESONATOR R

OSC2

ST72XXX

Notes:

1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R

Refer to crystal/ceramic resonator manufacturer for more details.

value.

2. Data based on characterisation results, not tested in production.

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ST72F521, ST72521B

CLOCK AND TIMING CHARACTERISTICS (Cont’d)

Supplier f

OSC

(MHz)

Typical Ceramic Resonators

Reference

CSTCC2M00G56A-R0

CSTCR4M00G55B-R0

CSTCE8M00G55A-R0

CSTCE16M0G53A-R0

Recommended OSCRANGE

Option bit configuration

MP Mode

MS Mode

HS Mode

Notes:

1. Resonator characteristics given by the ceramic resonator manufacturer.

2. SMD = [-R0: Plastic tape package ( ∅ =180mm), -B0: Bulk]

LEAD = [-A0: Flat pack package (Radial taping Ho= 18mm), -B0: Bulk]

3. LP mode is not recommended for 2 MHz resonator because the peak to peak amplitude is too small (>0.8V)

For more information on these resonators, please consult www.murata.com

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ST72F521, ST72521B

CLOCK CHARACTERISTICS (Cont’d)

12.5.4 RC Oscillators

Symbol f

OSC (RCINT)

Parameter

Internal RC oscillator frequency

See Figure 93

Figure 93. Typical f

OSC(RCINT)

vs T

Conditions

=25°C, V

=5V

Min

Typ

3.5

Max

5.6

Unit

MHz

Note: To reduce disturbance to the RC oscillator, it is recommended to place decoupling capacitors between V

and V

as shown in

Figure 113

3.8

3.6

3.4

3.2

-45 0 25

(°C)

Vdd = 5V

Vdd = 5.5V

70 130

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ST72F521, ST72521B

CLOCK CHARACTERISTICS (Cont’d)

12.5.5 PLL Characteristics

Symbol f

OSC

Parameter

PLL input frequency range

∆ f

CPU

/ f

CPU

Instantaneous PLL jitter

Conditions

ROM device, f

OSC

= 4 MHz.

Flash device, f

OSC

= 4 MHz.

Flash device, f

OSC

= 2 MHz.

Min

Typ

0.7

1.0

2.5

Max

2.5

4.0

Unit

MHz

Note:

1. Data characterized but not tested.

The user must take the PLL jitter into account in the application (for example in serial communication or sampling of high frequency signals). The PLL jitter is a periodic effect, which is integrated over several

CPU cycles. Therefore the longer the period of the application signal, the less it will be impacted by the

PLL jitter.

Figure 94 shows the PLL jitter integrated on application signals in the range 125kHz to 4MHz. At frequen-

cies of less than 125KHz, the jitter is negligible.

Figure 94. Integrated PLL Jitter vs signal frequency

+/-Jitter (%)

1.2

0.8

0.6

0.4

0.2

FLASH typ

ROM max

ROM typ

4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz

Application Frequency

Note 1: Measurement conditions: f

CPU

= 8MHz.

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ST72F521, ST72521B

12.6 MEMORY CHARACTERISTICS

12.6.1 RAM and Hardware Registers

Symbol

Parameter

Data retention mode

Conditions

HALT mode (or RESET)

Min

1.6

Typ Max Unit

12.6.2 FLASH Memory

DUAL VOLTAGE HDFLASH MEMORY

Symbol f

CPU

Parameter

Operating frequency

Programming voltage

Conditions

Read mode

Write / Erase mode

4.5V

≤

5.5V

RUN mode (f

CPU

= 4MHz)

Write / Erase

Power down mode / HALT

Read (V

=12V)

Write / Erase

Min

11.4

Typ Max

12.6

Unit

MHz

Supply current

4) mA

current

4) t

VPP

Internal stabilization time t

RET

Data retention

PROG

ERASE

Write erase cycles

Programming or erasing temperature range

=55°C

=25°C

100

-40

200

µA mA

µs years cycles

°C

Notes:

1. Minimum V

supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware registers (only in HALT mode). Not tested in production.

2. Data based on characterization results, not tested in production.

3. V

must be applied only during the programming or erasing operation and not permanently for reliability reasons.

4. Data based on simulation results, not tested in production.

Warning: Do not connect 12V to V

before V

is powered on, as this may damage the device.

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ST72F521, ST72521B

12.7 EMC CHARACTERISTICS

Susceptibility tests are performed on a sample basis during product characterization.

12.7.1 Functional EMS (Electro Magnetic

Susceptibility)

Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs).

■ ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard.

■ FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V

and V

through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-

4 standard.

A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709.

12.7.1.1 Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It

Symbol

FESD

FFTB

should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies

EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations:

The software flowchart must include the management of runaway conditions such as:

– Corrupted program counter

– Unexpected reset

– Critical Data corruption (control registers...)

Prequalification trials:

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RE-

SET pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behaviour is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015)

Parameter Conditions

Voltage limits to be applied on any I/O pin to induce a functional disturbance f

Flash device: V

OSC

5V, T

+25°C,

8MHz, conforms to IEC 1000-4-2

ROM device: V

5V, T

+25°C, f

O-

8MHz,conforms to IEC 1000-4-2

Fast transient voltage burst limits to be applied through 100pF on V

and V

DD pins to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100pF on V

and V

DD pins to induce a functional disturbance

Flash device: V

5V, T

+25°C, f

OSC

MHz, conforms to IEC 1000-4-4

Flash device: V

5V, T

+25°C, f

OSC

MHz, conforms to IEC 1000-4-4

Level/

Class

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ST72F521, ST72521B

EMC CHARACTERISTICS (Cont’d)

12.7.2 Electro Magnetic Interference (EMI)

Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/

3 which specifies the board and the loading of each pin.

Symbol

EMI

Parameter

Peak level

Conditions

Monitored

Frequency Band

5V, T

+25°C,

TQFP64 14x14 package conforming to SAE J 1752/3

0.1MHz to 30MHz

30MHz to 130MHz

130MHz to 1GHz

SAE EMI Level

Notes:

1. Data based on characterization results, not tested in production.

2. Refer to Application Note AN1709 for data on other package types.

Max vs. [f

OSC

CPU

] Unit

8/4MHz 16/8MHz

2.5

3.0

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ST72F521, ST72521B

EMC CHARACTERISTICS (Cont’d)

12.7.3 Absolute Maximum Ratings (Electrical

Sensitivity)

Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181.

12.7.3.1 Electro-Static Discharge (ESD)

Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models can be simulated: Human

Body Model and Machine Model. This test conforms to the JESD22-A114A/A115A standard.

Absolute Maximum Ratings

Symbol

ESD(HBM)

ESD(MM)

Ratings

Electro-static discharge voltage

(Human Body Model)

Electro-static discharge voltage

(Machine Model)

+25°C

Conditions Maximum value

Unit

2000

200

Notes:

1. Data based on characterization results, not tested in production.

12.7.3.2 Static and Dynamic Latch-Up

■ LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance.

A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note

AN1181.

■ DLU: Electro-Static Discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details, refer to the application note AN1181.

Electrical Sensitivities

Symbol

DLU

Parameter

Static latch-up class

Dynamic latch-up class

Conditions

+25°C

+85°C

+125°C

5.5V, f

OSC

4MHz, T

+25°C

Class

Notes:

1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the

JEDEC criteria (international standard).

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ST72F521, ST72521B

12.8 I/O PORT PIN CHARACTERISTICS

12.8.1 General Characteristics

Subject to general operating conditions for V

, f

OSC

, and T

unless otherwise specified.

Symbol

V hys

IH hys

Parameter

Input low level voltage

Input high level voltage

Schmitt trigger voltage hysteresis

Input low level voltage

Input high level voltage

Schmitt trigger voltage hysteresis

Injected Current on PC6 (Flash devices only)

INJ(PIN)

Total injected current (sum of all I/O and control pins)

IO t f(IO)out t r(IO)out t w(IT)in

Injected Current on an I/O pin

Input leakage current

Weak pull-up equivalent resistor

I/O pin capacitance

Output high to low level fall time

Output low to high level rise time

External interrupt pulse time

Conditions

CMOS ports

TTL ports

=5V

≤

=5V

=50pF

Between 10% and 90%

Min

0.7xV

Typ

0.7

400

120

Max

0.3xV

0.8

± 4

± 25

±1

250

Figure 95. Unused I/O Pins configured as input

Unit mA

A k

Ω pF ns t

CPU

Figure 96. Typical I

vs. V

with V

DD ST7XXX

10k

Ω

UNUSED I/O PORT

Ta=1 40°C

Ta=9 5°C

Ta=2 5°C

Ta=-45 °C

10k Ω

UNUSED I/O PORT 40

ST7XXX

Note: I/O can be left unconnected if it is configured as output

(0 or 1) by the software. This has the advantage of

greater EMC robustness and lower cost.

2 2.5

3 3.5

V dd(V)

4.5

5 5.5

Notes:

1. Data based on characterization results, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

3. When the current limitation is not possible, the V

IN tion. A positive injection is induced by V

on page 166 for more details.

maximum must be respected, otherwise refer to I

while a negative injection is induced by V

INJ(PIN)

specifica-

. Refer to section 12.2.2

4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for example and leaving the I/O unconnected on the board or an external pull-up or pull-down resistor (see

Figure 95 ). Data

based on design simulation and/or technology characteristics, not tested in production.

5. The R

pull-up equivalent resistor is based on a resistive transistor (corresponding I

scribed in Figure 96 ).

PU current characteristics de-

6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source.

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ST72F521, ST72521B

I/O PORT PIN CHARACTERISTICS (Cont’d)

12.8.2 Output Driving Current

Subject to general operating conditions for V

, f

CPU

, and T

unless otherwise specified.

Symbol Min

Parameter

Output low level voltage for a standard I/O pin when 8 pins are sunk at same time

(see

Figure 97 )

Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time

(see

Figure 98 and

Figure 100 )

Output high level voltage for an I/O pin when 4 pins are sourced at same time

(see

Figure 99 and

Figure 102 )

Conditions

=+5mA

=+2mA

=+20mA, T

≤

85°C

≥

85°C

=+8mA

=-5mA, T

≤

85°C

≥

85°C

=-2mA

-1.4

-1.6

-0.7

Max

1.2

0.5

1.3

1.5

0.6

Unit

Figure 97. Typical V

at V

=5V (standard)

1.4

Figure 99. Typical V

at V

=5V

5.5

1.2

4.5

0.8

0.6

3.5

0.4

0.2

Ta =14 0°C "

Ta =95 °C

Ta =25 °C

Ta =-45 °C

2.5

V dd= 5V 1 40°C m in

V dd= 5v 95°C m in

V dd= 5v 25°C m in

V dd= 5v -4 5°C m in

0 0.005

0.01

0.015

Iio(A )

Figure 98. Typical V

at V

=5V (high-sink)

0.9

0.8

-0.01

-0.008

-0.006

-0.004

-0.002

0.7

0.6

0.5

0.4

0.3

0.2

0.1

Ta= 140 °C

Ta= 95 °C

Ta= 25 °C

Ta= -45°C

0 0.01

0.02

0.03

Iio(A)

Notes:

1. The I

current sunk must always respect the absolute maximum rating specified in Section 12.2.2

and the sum of I

(I/O ports and control pins) must not exceed I

VSS

2. The I

current sourced must always respect the absolute maximum rating specified in

Section 12.2.2

and the sum of

(I/O ports and control pins) must not exceed I

VDD

. True open drain I/O pins do not have V

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ST72F521, ST72521B

I/O PORT PIN CHARACTERISTICS (Cont’d)

Figure 100. Typical V

vs. V

(standard)

Ta= -4 5°C

0.9

Ta= 25°C

0.8

Ta= 95°C

Ta= 140 °C

0.7

0.6

0.5

0.4

0.3

0.2

0.1

2 2.5

3 3.5

Vdd(V )

4.5

5 5.5

Figure 101. Typical V

vs. V

(high-sink)

0 .6

0 .5

0 .4

0 .3

0 .2

0 .1

Ta= 14 0°C

Ta=9 5°C

Ta=2 5°C

Ta=-45 °C

2 2.5

3 3.5

V dd (V )

4.5

Figure 102. Typical V

-V

vs. V

5.5

5 5.5

4.5

3.5

2.5

Ta= -4 5°C

Ta= 25°C

Ta= 95°C

Ta= 140°C

2 2.5

3 3.5

Vdd(V)

4.5

5 5.5

0.45

0.4

0.35

0.3

0.25

0.2

0.15

0.1

0.05

2 2 .5

3 3.5

Vdd(V )

4.5

Ta=-4 5°C

Ta=2 5°C

Ta=9 5°C

Ta=1 40°C

5 5.5

0 .8

0 .6

0 .4

0 .2

1 .6

1 .4

1 .2

Ta = 140 °C

Ta = 95 °C

Ta = 25 °C

Ta = -45°C

2.5

3 3.5

V dd(V )

4.5

5 5.5

Ta= -4 5°C

Ta= 25°C

Ta= 95°C

Ta= 140°C 4

2 2.5

3 3.5

Vdd(V)

4.5

5 5.5

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ST72F521, ST72521B

12.9 CONTROL PIN CHARACTERISTICS

12.9.1 Asynchronous RESET Pin

Subject to general operating conditions for V

, f

CPU

, and T

unless otherwise specified.

Symbol

V hys

Parameter

Input low level voltage

Input high level voltage

Schmitt trigger voltage hysteresis

Output low level voltage

Input current on RESET pin

Weak pull-up equivalent resistor

Conditions

=5V I

=+2mA

Min

0.85xV

Typ

2.5

0.2

Max

0.16xV

0.5

120 t w(RSTL)out

Generated reset pulse duration

Stretch applied on external pulse

0 42

Internal reset sources 20 30 42

6) t h(RSTL)in t g(RSTL)in

External reset pulse hold time

Filtered glitch duration

2.5

200

Unit

V mA k

Ω

µ s

µ s ns

Notes:

1. Data based on characterization results, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels.

3. The I

current sunk must always respect the absolute maximum rating specified in Section 12.2.2

and the sum of I

(I/O ports and control pins) must not exceed I

VSS

4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on the RESET pin with a duration below t h(RSTL)in

can be ignored.

5. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy environments.

6. Data guaranteed by design, not tested in production.

185/215

ST72F521, ST72521B

CONTROL PIN CHARACTERISTICS (Cont’d)

Figure 103. RESET pin protection when LVD is enabled.

1)2)3)4)

ST72XXX

EXTERNAL

RESET

Required Optional

(note 3)

0.01

µ F

1M Ω

Filter

INTERNAL

RESET

PULSE

GENERATOR

WATCHDOG

LVD RESET

Figure 104. RESET pin protection when LVD is disabled.

Recommended for EMC

USER

EXTERNAL

RESET

CIRCUIT

0.01

4.7k

Ω

Filter

0.01

µ F

PULSE

GENERATOR

Required

ST72XXX

INTERNAL

RESET

WATCHDOG

Note 1:

– The reset network protects the device against parasitic resets.

– The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).

– Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the V

IL internally.

max. level specified in section 12.9.1 on page 185 . Otherwise the reset will not be taken into account

– Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for I

INJ(RESET)

section 12.2.2 on page 166

Note 2: When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-down capacitor is required to filter noise on the reset line.

Note 3: In case a capacitive power supply is used, it is recommended to connect a 1M

Ω

pull-down resistor to the RESET pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5µA to the power consumption of the MCU).

Note 4: Tips when using the LVD:

– 1. Check that all recommendations related to reset circuit have been applied (see notes above).

– 2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709 and

AN2017. If this cannot be done, it is recommended to put a 100nF + 1M

Ω

pull-down on the RESET pin.

– 3. The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up marginality.

In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on the

RESET pin with a 5µF to 20µF capacitor.

186/215

ST72F521, ST72521B

CONTROL PIN CHARACTERISTICS (Cont’d)

12.9.2 ICCSEL/V

Pin

Subject to general operating conditions for V

, f

CPU

, and T

unless otherwise specified.

Symbol Parameter

Input low level voltage

Input high level voltage

Input leakage current

Conditions

FLASH versions

ROM versions

FLASH versions

ROM versions

Min Max

0.2

0.3xV

-0.1

12.6

0.7xV

±1

Figure 105. Two typical Applications with ICCSEL/V

Pin

Unit

ICCSEL/V

ST72XXX

PROGRAMMING

TOOL

10k

Ω

ST72XXX

Notes:

1. Data based on design simulation and/or technology characteristics, not tested in production.

2. When ICC mode is not required by the application ICCSEL/V

pin must be tied to V

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ST72F521, ST72521B

12.10 TIMER PERIPHERAL CHARACTERISTICS

Subject to general operating conditions for V

, f

OSC

, and T

unless otherwise specified.

Refer to I/O port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output...).

12.10.1 8-Bit PWM-ART Auto-Reload Timer

Symbol Parameter t res(PWM)

PWM resolution time f

EXT f

PWM

Res

PWM

ART external clock frequency

PWM repetition rate

PWM resolution

PWM/DAC output step voltage

Conditions f

CPU

=8MHz

=5V, Res=8-bits

Min

125

Typ

Max f

CPU

/2 f

CPU

Unit t

CPU ns

MHz bit mV

12.10.2 16-Bit Timer

Symbol t w(ICAP)in

Parameter

Input capture pulse time t res(PWM)

PWM resolution time f

EXT f

PWM

Res

PWM

Timer external clock frequency

PWM repetition rate

PWM resolution

Conditions f

CPU

=8MHz

Min

250

Typ Max f

CPU

/4 f

CPU

Unit t

CPU t

CPU ns

MHz

MHz bit

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ST72F521, ST72521B

12.11 COMMUNICATION INTERFACE CHARACTERISTICS

12.11.1 SPI - Serial Peripheral Interface

Subject to general operating conditions for V

DD f

CPU

, and T

unless otherwise specified.

Symbol Parameter

Master f

SCK

1/t c(SCK)

SPI clock frequency

Slave

Refer to I/O port characteristics for more details on the input/output alternate function characteristics

(SS, SCK, MOSI, MISO).

Conditions f

CPU

=8MHz

Min f

CPU

/128

0.0625

Unit

MHz f

CPU

=8MHz

Max f

CPU

/4 f

CPU

4 t r(SCK) t f(SCK) t su(SS) t h(SS) t w(SCKH) t w(SCKL) t su(MI) t su(SI) t h(MI) t h(SI) t a(SO) t dis(SO) t v(SO) t h(SO) t v(MO) t h(MO)

SPI clock rise and fall time

SS setup time

SS hold time

SCK high and low time

Data input setup time

Data input hold time

Data output access time

Data output disable time

Data output valid time

Data output hold time

Data output valid time

Data output hold time

Slave

Master

Slave

Master

Slave

Master

Slave

Slave (after enable edge)

Master (before capture edge) see I/O port pin description

120

100

0.25

120

240

90 ns t

CPU

Figure 106. SPI Slave Timing Diagram with CPHA=0 3)

INPUT t su(SS) t c(SCK) t h(SS)

CPHA=0

CPOL=0

CPHA=0

CPOL=1 t a(SO) t w(SCKH) t w(SCKL) t v(SO) t h(SO) t r(SCK) t f(SCK) t dis(SO)

MISO

OUTPUT see note 2 t su(SI)

MSB OUT t h(SI)

BIT6 OUT LSB OUT see note 2

MOSI

INPUT

MSB IN BIT1 IN LSB IN

Notes:

1. Data based on design simulation and/or characterisation results, not tested in production.

2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration.

3. Measurement points are done at CMOS levels: 0.3xV

and 0.7xV

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ST72F521, ST72521B

COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)

Figure 107. SPI Slave Timing Diagram with CPHA=1 1)

INPUT t su(SS) t c(SCK)

CPHA=1

CPOL=0

CPHA=1

CPOL=1 t a(SO) t w(SCKH) t w(SCKL) t v(SO)

MISO

OUTPUT see note 2

HZ t su(SI)

MSB OUT t h(SI)

BIT6 OUT

MOSI

INPUT

MSB IN BIT1 IN t h(SS) t h(SO) t t r(SCK) f(SCK)

LSB OUT

LSB IN

Figure 108. SPI Master Timing Diagram 1)

INPUT t c(SCK)

CPHA=0

CPOL=0

CPHA=0

CPOL=1

CPHA=1

CPOL=0

CPHA=1

CPOL=1 t w(SCKH) t w(SCKL) t su(MI) t h(MI)

MISO

INPUT t v(MO)

MSB IN t h(MO)

BIT6 IN

MOSI

OUTPUT see note 2 MSB OUT BIT6 OUT t r(SCK) t f(SCK)

LSB IN

LSB OUT t dis(SO) see note 2 see note 2

Notes:

1. Measurement points are done at CMOS levels: 0.3xV

and 0.7xV

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ST72F521, ST72521B

COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)

12.11.2 I

C - Inter IC Control Interface

Subject to general operating conditions for V

DD f

CPU

, and T

unless otherwise specified.

Refer to I/O port characteristics for more details on the input/output alternate function characteristics

(SDAI and SCLI). The ST7 I

C interface meets the requirements of the Standard I

C communication protocol described in the following table.

Symbol Parameter t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL) t f(SDA) t f(SCL) t h(STA) t su(STA) t su(STO) t w(STO:STA)

C b

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

SDA and SCL rise time

SDA and SCL fall time

START condition hold time

Repeated START condition setup time

STOP condition setup time

STOP to START condition time (bus free)

Capacitive load for each bus line

Standard mode I

Min

Max

4.7

4.0

250

4.0

4.7

4.0

4.7

1000

300

400

Figure 109. Typical Application with I

C Bus and Timing Diagram 4)

Fast mode I

Min

Max

1.3

0.6

100

900

20+0.1C

0.6

1.3

300

400

Unit

µ s ns

µ s

µ s pF

4.7k

Ω

4.7k

Ω

SDAI

C BUS

100 Ω

SCLI

ST72XXX

REPEATED START

START t su(STA) t w(STO:STA)

START

SDA t f(SDA) t r(SDA) t su(SDA) t h(SDA)

STOP

SCK t h(STA) t w(SCKH) t w(SCKL) t r(SCK) t f(SCK) t su(STO)

Notes:

1. Data based on standard I

C protocol requirement, not tested in production.

2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.

3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of

SCL signal.

4. Measurement points are done at CMOS levels: 0.3xV

and 0.7xV

5. At 4MHz f

CPU

, max.I

C speed (400kHz) is not achievable. In this case, max. I

C speed will be approximately 260KHz.

191/215

ST72F521, ST72521B

COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)

The following table gives the values to be written in the I2CCCR register to obtain the required I

SCL line frequency.

Table 28. SCL Frequency Table f

SCL

(kHz)

400

300

200

100

I2CCCR Value f

CPU

=4 MHz.

CPU

=8 MHz.

= 4.1 V V

= 5 V

=3.3k

Ω

=4.7k

Ω

=3.3k

Ω

=4.7k

Ω

= 4.1 V

=3.3k

Ω

=4.7k

Ω

= 5 V

=3.3k

Ω

=4.7k

Ω

NA NA NA NA 83h 83 83h 83h

83h

10h

24h

5Fh

83h

10h

24h

5Fh

83h

10h

24h

5Fh

83h

10h

24h

5Fh

85h

8Ah

24h

4Ch

FFh

85h

89h

23h

4Ch

FFh

85h

8Ah

24h

4Ch

FFh

85h

8Ah

23h

4Ch

FFh

Legend:

= External pull-up resistance f

SCL

= I

C speed

NA = Not achievable

Note:

– For speeds around 200 kHz, achieved speed can have ± 5% tolerance

– For other speed ranges, achieved speed can have ± 2% tolerance

The above variations depend on the accuracy of the external components used.

12.11.3 CAN - Controller Area Network Interface

Subject to general operating condition for V

, f

OSC

, and T

unless otherwise specified.

Refer to I/O port characteristics for more details on the input/output alternate function characteristics

(CANTX and CANRX).

Symbol t p(RX:TX)

Parameter

CAN controller propagation time

Conditions Min Typ Max

Unit ns

Notes:

1. Data based on simulation results, not tested in production

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ST72F521, ST72521B

12.12 10-BIT ADC CHARACTERISTICS

Subject to general operating conditions for V

, f

CPU

, and T

unless otherwise specified.

Typ Symbol f

ADC

AREF

AIN

I lkg

AIN

AIN f

AIN

Parameter Conditions

ADC clock frequency

Analog reference voltage

Conversion voltage range

0.7*V

≤

AREF

≤

Positive input leakage current for analog input

Negative input leakage current on robust analog pins (ROM devices only)

Positive input leakage current for analog input

Negative input leakage current on robust analog pins (ROM devices only)

-40°C

≤

85°C range

Other T

A ranges

SS,

| I

|< 400µA on adjacent robust analog pin

-40°C

≤

85°C range

Other T

A ranges

SS,

| I

|< 400µA on adjacent robust analog pin

External input impedance

External capacitor on analog input

Variation freq. of analog input signal

Min

0.4

3.8

SSA

Max

AREF

±250

±1

±250

±1

6 see

and

2)3)4)

ADC t

ADC

Internal sample and hold capacitor

Conversion time (Sample+Hold) f

CPU

=8MHz, SPEED=0 f

ADC

=2MHz

- No of sample capacitor loading cycles

- No. of Hold conversion cycles

7.5

Unit

MHz

V nA

A nA

A k

Ω pF

Hz pF

µ s

1/f

ADC

Notes:

1. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k

Ω

). Data based on characterization results, not tested in production.

2. For Flash devices: injecting negative current on any of the analog input pins significantly reduces the accuracy of any conversion being performed on any analog input. Analog pins of flash devices can be protected against negative injection by adding a Schottky diode (pin to ground). Injecting negative current on digital input pins degrades ADC accuracy espe-

I cially if performed on a pin close to the analog input pins. Any positive injection current within the limits specified for

INJ(PIN)

and

INJ(PIN)

Section 12.8

does not affect the ADC accuracy.

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ST72F521, ST72521B

ADC CHARACTERISTICS (Cont’d)

Figure 110. R

AIN

max. vs f

ADC

with C

AIN

=0pF

2 MHz

1 MHz

0 10 30 70

PARASITIC

(pF)

Figure 112. Typical A/D Converter Application

AIN

AINx

Figure 111. Recommended C

AIN

& R

AIN values.

1000

100

0.6V

0.1

0.01

0.1

AIN

(KHz)

Ω( max

)

10-Bit A/D

Conversion

±1

Cain 10 nF

Cain 22 nF

Cain 47 nF

ST72XXX

ADC

12pF

Notes:

1. C

PARASITIC

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (3pF). A high C

PARASITIC

value will downgrade conversion accuracy. To remedy this, f

ADC

should be reduced.

2. This graph shows that depending on the input signal variation (f

AIN decreased to allow the use of a larger serial resistor (R

AIN)

), C

AIN

can be increased for stabilization time and

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ST72F521, ST72521B

ADC CHARACTERISTICS (Cont’d)

12.12.1 Analog Power Supply and Reference

Pins

Depending on the MCU pin count, the package may feature separate V

AREF

and V

SSA analog power supply pins. These pins supply power to the

A/D converter cell and function as the high and low reference voltages for the conversion.

Separation of the digital and analog power pins allow board designers to improve A/D performance.

Conversion accuracy can be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines (see