STMicroelectronics ST7LITEU09 Datasheet

ST7LITEU05 ST7LITEU09

8-bit MCU with single voltage Flash memory, ADC, timers

Datasheet

-

production data

Features

• Memories

– 2K Bytes single voltage Flash program memory with readout protection, in-circuit and in-application programming (ICP and

IAP). 10K write/erase cycles guaranteed, data retention: 20 years at 55 °C

– 128 bytes RAM

– 128 bytes data EEPROM. 300K write/erase cycles guaranteed, data retention: 20 years at 55 °C

• Clock, reset and supply management

– 3-level low voltage supervisor (LVD) and auxiliary voltage detector (AVD) for safe power- on/off procedures

– Clock sources: internal trimmable 8-MHz

RC oscillator, internal low power, low frequency RC oscillator or external clock

– Five Power Saving Modes: Halt, Auto-

Wakeup from Halt, Active-halt, Wait and

Slow

• Interrupt management

– 11 interrupt vectors plus TRAP and RESET

– 5 external interrupt lines (on 5 vectors)

DIP8

DFN8

SO8

150”

• A/D converter

– 10-bit resolution for 0 to VDD

– 5 input channels

• Instruction set

– 8-bit data manipulation

– 63 basic instructions with illegal opcode detection

– 17 main addressing modes

– 8 x 8 unsigned multiply instruction

• Development tools

– Full hardware/software development package

– Debug module

• I/O Ports

– 5 multifunctional bidirectional I/O lines

– 1 additional output line

– 6 alternate function lines

•

– 5 high sink outputs Obsolete Product(s) - Obsolete Product(s)

– One 8-bit lite timer (LT) with prescaler including: watchdog, 1 realtime base and 1 input capture

– One 12-bit auto-reload timer (AT) with output compare function and PWM

October 2016

This is information on a product in full production.

DocID13474 Rev 3 1/146 www.st.com

ST7LITEU05 ST7LITEU09 Contents

Contents

1

2

3

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.3

Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.3.1

4.3.2

In-circuit programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

In Application Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.4

ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.5

Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.5.1

4.5.2

Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.6

Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.7

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.7.1

Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5 Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.3

Memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.3.1

Read operation (E2LAT=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.3.2

Write operation (E2LAT=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Obsolete Product(s) - Obsolete Product(s)

5.4

Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.4.1

5.4.2

5.4.3

Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.5

Access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.6

Data EEPROM readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.7

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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7

8

Contents

5.7.1

EEPROM control/status register (EECSR) . . . . . . . . . . . . . . . . . . . . . . 28

Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.2

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.3

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.1

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.2

Internal RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.3

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.3.1

7.3.2

7.3.3

7.3.4

7.3.5

Main clock control/status register (MCCSR) . . . . . . . . . . . . . . . . . . . . . 37

RC control register (RCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

System integrity (SI) control/status register (SICSR) . . . . . . . . . . . . . . . 38

AVD threshold selection register (AVDTHCR) . . . . . . . . . . . . . . . . . . . . 38

Clock controller control/status register (CKCNTCSR) . . . . . . . . . . . . . . 39

7.4

Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.4.1

7.4.2

7.4.3

7.4.4

7.4.5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Internal low voltage detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . . 41

Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.5

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.5.2

Multiplexed IO reset control register 1 (MUXCR1) . . . . . . . . . . . . . . . . 43

Multiplexed IO reset control register 0 (MUXCR0) . . . . . . . . . . . . . . . . 43

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Priority management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Interrupts and low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.1

Non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.2

External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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8.3

Peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.3.1

8.3.2

External interrupt control register 1 (EICR1) . . . . . . . . . . . . . . . . . . . . . 47

External interrupt control register 2 (EICR2) . . . . . . . . . . . . . . . . . . . . . 47

8.4

System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8.4.1

8.4.2

8.4.3

8.4.4

Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

9.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

9.2

Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

9.3

Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

9.4

Active-halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

9.4.1

9.4.2

Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

9.5

Auto-wakeup from Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

9.5.1

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

10 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

10.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

10.2

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

10.2.1

Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

10.2.2

Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.2.3

Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

10.2.4

Analog alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10.3

Unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

10.4

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Obsolete Product(s) - Obsolete Product(s)

10.6

I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

11 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

11.1

Lite timer (LT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

11.1.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

11.1.2

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

11.1.3

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

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11.1.4

Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

11.1.5

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

11.1.6

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

11.1.7

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

11.2

12-bit autoreload timer (AT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

11.2.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

11.2.2

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

11.2.3

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

11.2.4

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

11.2.5

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

11.2.6

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

11.3

10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

11.3.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

11.3.2

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

11.3.3

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

11.3.4

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

11.3.5

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

11.3.6

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

12 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

12.1

ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

12.1.1

Inherent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

12.1.2

Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

12.1.3

Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

12.1.4

Indexed mode (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . 92

12.1.5

Indirect modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

12.1.6

Indirect indexed modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

12.1.7

Relative modes (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

12.2

Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Obsolete Product(s) - Obsolete Product(s)

13 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

13.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

13.1.1

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

13.1.2

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

13.1.3

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

13.1.4

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

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13.1.5

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

13.2

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

13.3

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

13.3.1

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

13.3.2

Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . 102

13.3.3

Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . 103

13.3.4

Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

13.4

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

13.4.1

Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

13.4.2

Internal RC oscillator supply characteristics . . . . . . . . . . . . . . . . . . . . 107

13.4.3

On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

13.5

Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

13.6

Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

13.7

EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

13.7.1

Functional EMS (electro magnetic susceptibility) . . . . . . . . . . . . . . . . 112

13.7.2

EMI (electromagnetic interference) . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

13.7.3

Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 113

13.8

I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

13.8.1

General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

13.8.2

Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

13.9

Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

13.9.1

Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

13.10 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

14.1

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

15 Device configuration and ordering information . . . . . . . . . . . . . . . . . 133

Obsolete Product(s) - Obsolete Product(s)

15.1.1

Option byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

15.1.2

Option byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

15.2

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

15.3

Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

15.3.1

Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

15.3.2

Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

15.3.3

Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

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16

Contents

15.3.4

Order codes for development and programming tools . . . . . . . . . . . . 138

15.4

ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

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7

ST7LITEU05 ST7LITEU09 List of tables

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Data EEPROM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Predefined RC oscillator calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Internal RC prescaler selection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Clock register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

CPU clock cycle delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Multiplexed IO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 9.

Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 10.

Interrupt sensitivity bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 11.

Description of low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 12.

Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 13.

AVD threshold selection bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 14.

System integrity register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 15.

Enabling/disabling Active-halt and Halt modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 16.

Configuring the dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 17.

AWU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 18.

DR value and output pin status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 19.

I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 20.

I/O port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 21.

Effect of low-power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 22.

Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 23.

Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 24.

I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 25.

Description of low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 26.

Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 27.

Lite timer register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 28.

Description of low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 29.

Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 30.

Counter clock selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 31.

Register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 32.

Effect of low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 33.

Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 34.

Configuring the ADC clock speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 35.

ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 36.

Description of addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 37.

ST7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Obsolete Product(s) - Obsolete Product(s)

Table 39.

Instructions supporting inherent immediate addressing mode . . . . . . . . . . . . . . . . . . . . . . 92

Table 40.

Instructions supporting direct, indexed, indirect and indirect indexed addressing modes . 93

Table 41.

Instructions supporting relative modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 42.

ST7 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 43.

Illegal opcode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 44.

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 45.

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 46.

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 47.

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 48.

Operating characteristics with LVD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

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Table 49.

Operating characteristics with AVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 50.

Voltage drop between AVD flag set and LVD reset generation . . . . . . . . . . . . . . . . . . . . 103

Table 51.

Internal RC oscillator characteristics (5.0 V calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 52.

Internal RC oscillator characteristics (3.3 V calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 53.

Supply current characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 54.

Internal RC oscillator supply characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 55.

On-chip peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 56.

General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 57.

Auto-wakeup RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 58.

RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 59.

Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 60.

EEPROM data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 61.

EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 62.

EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 63.

ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 64.

Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 65.

General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 66.

Output driving current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 67.

Asynchronous RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 68.

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 69.

ADC accuracy with VDD = 3.3 V to 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 70.

ADC accuracy with VDD = 2.7 V to 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 71.

ADC accuracy with VDD = 2.4 V to 2.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 72.

8-lead very thin fine pitch dual flat no-lead package, mechanical data . . . . . . . . . . . . . . 128

Table 73.

8-pin plastic small outline package - 150-mil width, mechanical data. . . . . . . . . . . . . . . . 129

Table 74.

8-pin plastic dual in-line outline package, 300-mil width, mechanical data. . . . . . . . . . . . 130

Table 75.

16-pin plastic dual in-line package, 300-mil width, mechanical data . . . . . . . . . . . . . . . . 131

Table 76.

Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 77.

Startup clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 78.

LVD threshold configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 79.

Sector 0 size selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 80.

ST7LITEU0 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Table 81.

Development tool order codes for the ST7LITEU0x family. . . . . . . . . . . . . . . . . . . . . . . . 139

Table 82.

ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 83.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

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9

ST7LITEU05 ST7LITEU09 List of figures

List of figures

Figure 1.

General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2.

8-pin SO and DIP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 3.

8-pin DFN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 4.

16-pin package pinout 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 5.

Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 6.

Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 7.

EEPROM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 8.

Data EEPROM programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 9.

Data EEPROM write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 10.

Data EEPROM programming cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 11.

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 12.

Stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 13.

Clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 14.

Clock management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 15.

Reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 16.

Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 17.

Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 18.

Interrupt processing flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 19.

Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 20.

Reset and supply management block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 21.

Using the AVD to monitor VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 22.

Power saving mode transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 23.

Slow mode clock transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 24.

Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 25.

Active-halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 26.

Active-halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 27.

Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 28.

Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 29.

AWUFH mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 30.

AWUF Halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 31.

AWUFH mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 32.

I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 33.

Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 34.

Lite timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 35.

Watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 36.

Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 37.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Obsolete Product(s) - Obsolete Product(s)

Figure 39.

PWM signal example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 40.

ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 41.

Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 42.

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 43.

fCPU maximum operating frequency versus V

DD supply voltage . . . . . . . . . . . . . . . . . . 102

Figure 44.

Typical accuracy with RCCR=RCCR0 vs VDD= 2.4-6.0 V and temperature . . . . . . . . . . 105

Figure 45.

Typical accuracy with RCCR=RCCR1 vs VDD= 2.4-6.0V and temperature. . . . . . . . . . . 105

Figure 46.

Typical IDD in run mode vs. internal clock frequency and VDD . . . . . . . . . . . . . . . . . . . 108

Figure 47.

Typical IDD in WFI mode vs. internal clock frequency and VDD . . . . . . . . . . . . . . . . . . . 108

Figure 48.

Typical IDD in Slow, Slow-wait and Active-halt mode vs VDD & int

10/146 DocID13474 Rev 3

ST7LITEU05 ST7LITEU09 List of figures

RC = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 49.

Idd vs temp @VDD 5 V & int RC = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 50.

Idd vs temp @VDD 5 V & int RC = 4 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 51.

Idd vs temp @VDD 5V & int RC = 2 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 52.

Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 53.

Typical IPU vs. VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 54.

Typical RPU vs. VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 55.

Typical VOL at vDD = 2.4 V (standard pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 56.

Typical vOL at vDD = 3 V (standard pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 57.

Typical VOL at VDD = 5 V (standard pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 58.

Typical VOL at VDD = 2.4 V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 59.

Typical VOL at VDD = 3 V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 60.

Typical VOL at VDD = 5 V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 61.

Typical VDD-VOH at VDD = 2.4 V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 62.

Typical VDD-VOH at VDD = 3 V (HS pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 63.

Typical VDD-VOH at VDD = 5 V (HS pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 64.

Typical VOL vs. VDD (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 65.

Typical VDD-VOH vs. VDD (HS pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 66.

RESET pin protection when LVD is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 67.

RESET pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 68.

Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 69.

ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 70.

8-lead very thin fine pitch dual flat no-lead package, package outline . . . . . . . . . . . . . . . 127

Figure 71.

8-pin plastic small outline package - 150-mil width, package outline . . . . . . . . . . . . . . . . 128

Figure 72.

8-pin plastic dual in-line outline package - 300-mil width, package outline. . . . . . . . . . . . 129

Figure 73.

16-pin plastic dual in-line package, 300-mil width, package outline . . . . . . . . . . . . . . . . . 130

Figure 74.

ST7LITEU0 FASTROM microcontroller option list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

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11

Description

1 Description

ST7LITEU05 ST7LITEU09

The ST7ULTRALITE is a member of the ST7 microcontroller family. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set.

The ST7ULTRALITE features Flash memory with byte-by-byte in-circuit programming (ICP) and in-application programming (IAP) capability.

Under software control, the ST7ULTRALITE device can be placed in Wait, Slow, or Halt mode, reducing power consumption when the application is in idle or standby state.

The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all the ST7 microcontrollers feature a true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

For easy reference, all parametric data are located in Section 13: Electrical characteristics

.

The devices feature an on-chip debug module (DM) to support in-circuit debugging (ICD).

For a description of the DM registers, refer to the ST7 ICC protocol reference manual.

Figure 1. General block diagram

AWU RC osc.

Internal

Clock

8-MHz RC osc.

External clock

Lite timer with watchdog

V

DD

V

SS

LVD

Power supply

Port A

PA3 / RESET Control

12-bit autoreload timer

PA5:0

(6 bits)

8-bit core

ALU

10-bit ADC

2 Kbyte

Flash memory

Data EEPROM

(128 Bytes)

RAM

(128 Bytes) Obsolete Product(s) - Obsolete Product(s)

12/146 DocID13474 Rev 3

ST7LITEU05 ST7LITEU09 Pin description

Figure 2. 8-pin SO and DIP package pinout

V

DD

1

PA5 (HS) / AIN4 / CLKIN 2 ei4

PA4 (HS) / AIN3 / MCO 3 ei3

PA3 / RESET 4 ei0

8

7

V

SS

PA0 (HS) / AIN0 / ATPWM / ICCDATA ei1 6 PA1 (HS) / AIN1 / ICCCLK ei2 5 PA2 (HS) / LTIC / AIN2

1.

HS : High sink capability

2.

eix : associated external interrupt vector

Figure 3. 8-pin DFN package pinout

V

DD

PA5 (HS) / AIN4 / CLKIN

1

2 ei4

8 ei0 7

PA4 (HS) / AIN3 / MCO 3 ei3

PA3 / RESET 4 ei1 ei2

6

5

V

SS

PA0 (HS) / AIN0 / ATPWM / ICCDATA

PA1 (HS) / AIN1 / ICCCLK

PA2 (HS) / LTIC / AIN2

1.

HS : High sink capability

2.

eix : associated external interrupt vector

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Pin description ST7LITEU05 ST7LITEU09

Figure 4. 16-pin package pinout 1

Reserved

2)

1

V

DD

2

RESET 3

ICCCLK 4

PA5 (HS) / AIN4 / CLKIN

PA4 (HS) / AIN3 / MCO

5 ei4

6 ei3

1 NC ei0

1

1

V

SS

PA0 (HS) / AIN0 / ATPWM ei1 1

12

PA1 (HS) / AIN1

NC

11 ICCDATA

PA3 7

NC 8 ei2 10 PA2 (HS) / LTIC / AIN2

9 NC

Note:

1. For development or tool prototyping purposes only.

Package not orderable in production quantities.

2. Must be tied to ground.

The differences versus the 8-pin packages are listed below:

The ICC signals (ICCCLK and ICCDATA) are mapped on dedicated pins.

The RESET signal is mapped on a dedicated pin. It is not multiplexed with PA3.

The PA3 pin is always configured as output. Any change on multiplexed IO reset control

registers (MUXCR1 and MUXCR2) have no effect on PA3 functionality. Refer to Section 7.5:

Register description

.

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14/146 DocID13474 Rev 3

ST7LITEU05 ST7LITEU09 Pin description

Legend / abbreviations for

Table 1

:

Type: I = input, O = output, S = supply

In/Output level: C

T

= CMOS 0.3 V

DD

/0.7 V

DD

with input trigger

Output level: HS = High sink (on N-buffer only)

Port and control configuration:

• Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog

• Output: OD = open drain, PP = push-pull

The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.

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Pin description

Pin Name

ST7LITEU05 ST7LITEU09

Level

Table 1. Device pin description

Port / Control

Input Output main function

(after reset)

Alternate function

1 V

DD

(1)

2 PA5/AIN4/CLKIN

3 PA4/AIN3/MCO

S -

I/O C

T

I/O C

T

-

HS

HS

-

X

X

-

X ei4 ei3

-

X X X Port A5

Analog input 4 or external clock input

X X X Port A4

Analog input 3 or main clock output

X X Port A3 RESET

(2)

4 PA3/RESET

(2)

O

5 PA2/AIN2/LTIC I/O C

T

6 PA1/AIN1/ICCCLK I/O C

T

HS X

HS X ei2 ei1

X X X Port A2

X X X Port A1

Analog input 2 or lite timer input capture

Analog input 1 or In Circuit

Communication Clock

Caution: During normal operation this pin must be pulledup, internally or externally

(external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset puts it back in pull-up

7

PA0/AIN0/ATPWM/

ICCDATA

I/O C

T

HS X ei0 X X X Port A0

Analog input 0 or Auto-Reload

Timer PWM or In Circuit

Communication Data

S Ground 8 V

SS

(1)

1. It is mandatory to connect all available V

DD

and V

DDA

pins to the supply voltage and all V

SS

and V

SSA

pins to ground.

2. After a reset, the multiplexed PA3/RESET pin acts as RESET. To configure this pin as output (Port A3), write 55h to

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ST7LITEU05 ST7LITEU09

3 Register & memory map

Register & memory map

As shown in

Figure 5 below, the MCU is capable of addressing 64 Kbytes of memories and

I/O registers.

The available memory locations consist of 128 bytes of register locations, 128 bytes of RAM and 1 Kbyte of user program memory. The RAM space includes up to 64 bytes for the stack from 00C0h to 00FFh.

The highest address bytes contain the user reset and interrupt vectors.

The Flash memory contains two sectors (see

Figure 5 ) mapped in the upper part of the ST7

addressing space so the reset and interrupt vectors are located in Sector 0 (FC00-FFFFh).

The size of Flash Sector 0 and other device options are configurable by Option byte.

Important: The memory locations marked as “Reserved” must never be accessed.

Accessing a reserved area can have unpredictable effects on the device.

Figure 5. Memory map

0000h

0080h HW registers

(see Table 2

)

Short addressing

RAM (zero page) 007Fh

0080h

00C0h

64-Byte Stack RAM

(128 Bytes) 00FFh

DEE0h

1)

RCCRH0 00FFh

0100h DEE1h

Reserved

DEE2h

RCCRL0

RCCRH1 0FFFh

1000h

DEE3h

RCCRL1

Data

EEPROM

(128 Bytes)

107Fh

1080h

2K FLASH

PROGRAM MEMORY Reserved

F7FFh

F800h

Flash memory

(2K)

F800h

FBFFh

FC00h

FFFFh

1 Kbyte

SECTOR 1

1 Kbyte

SECTOR 0

FFDFh

FFE0h

Interrupt & reset vectors

(see

Table 9 )

FFFFh

Obsolete Product(s) - Obsolete Product(s)

1. See

Section 7.2: Internal RC oscillator adjustment .

Note: The DEE0h, DEE1h, DEE2h and DEE3h addresses are located in a reserved area but are special bytes containing also the RC calibration values which are read-accessible only in user mode. If all the EEPROM data or Flash space (including the RC calibration values locations) has been erased (after the readout protection removal), then the RC calibration values can still be obtained through these addresses.

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Register & memory map ST7LITEU05 ST7LITEU09

Table 2. Hardware register map

Address

0000h

0001h

0002h

0003h to

000Ah

000Bh

000Ch

000Dh

000Eh

000Fh

0010h

0011h

0012h

0013h

0014h to

0016h

0017h

0018h

0019h to

002Eh

0002Fh

00030h

0031h to

0033h

0034h

0035h

0036h

0037h

0038h

0039h

003Ah

0040h to

0046h

0047h

0048h

Block

Port A

Lite timer

Auto-reload timer

Auto-reload timer

Flash

EEPROM

ADC

ITC

MCC

Clock and reset

Register label

LTCSR

LTICR

ATCSR

CNTRH

CNTRL

ATRH

ATRL

PWMCR

PWM0CSR

DCR0H

DCR0L

FCSR

EECSR

ADCCSR

ADCDRH

ADCDRL

EICR1

MCCSR

RCCR

SICSR

Register name

Reserved area (8 bytes)

Lite timer control/status register

Lite timer input capture register

Timer control/status register

Counter register high

Counter register low

Auto-reload register high

Auto-reload register low

PWM output control register

PWM 0 control/status register

Reserved area (3 bytes)

PWM 0 duty cycle register high

PWM 0 duty cycle register low

Reserved area (22 bytes)

Flash control/status register

Data EEPROM control/status register

Reserved area (3 bytes)

A/D control status register

A/D data register high

A/D data register low

External interrupt control register 1

Main clock control/status register

RC oscillator control register

System integrity control/status register

Reset status

(1)

00h

(2)

08h

02h (3)

0xh

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h xxh

00h

00h

00h

FFh

0000 0x00b

Remarks

(1)

R/W

R/W

R/W

R/W

Read only

R/W

Read only

Read only

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read only

R/W

R/W

R/W

R/W

R/W

003Bh to

003Ch

Reserved area (2 bytes)

Obsolete Product(s) - Obsolete Product(s)

003Dh ITC EICR2 External interrupt control register 2 00h R/W

003Eh AVDTHCR AVD threshold selection register 03h R/W

003Fh

AVD

Clock controller

CKCNTCSR Clock controller control/status register 09h R/W

MuxIOreset

PADR

PADDR

PAOR

MUXCR0

MUXCR1

Port A data register

Port A data direction register

Port A option register

Reserved area (7 bytes)

Mux IO-reset control register 0

Mux IO-reset control register 1

00h

00h

00h

00h

R/W

R/W

R/W

R/W

18/146 DocID13474 Rev 3

ST7LITEU05 ST7LITEU09 Register & memory map

Table 2. Hardware register map (continued)

Address Block Register label Register name

Reset status

(1)

Remarks

(1)

0049h

004Ah

004Bh

004Ch

004Dh

004Eh

004Fh

0050h

0051h to

007Fh

AWU

DM

(4)

AWUPR

AWUCSR

DMCR

DMSR

DMBK1H

DMBK1L

DMBK2H

DMBK2L

AWU prescaler register

DM control register

DM status register

AWU control/status register

DM breakpoint register 1 high

DM breakpoint register 1 low

DM breakpoint register 2 high

DM breakpoint register 2 low

Reserved area (47 bytes)

FFh

00h

00h

00h

00h

00h

00h

00h

1. Legend: x=undefined, R/W=read/write.

2. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the

I/O pins are returned instead of the DR register contents.

3. The bits associated with unavailable pins must always keep their reset value.

4. For a description of the DM registers, see the ST7 ICC Protocol Reference Manual.

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

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Flash program memory

4 Flash program memory

ST7LITEU05 ST7LITEU09

4.1 Introduction

The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel.

The XFlash devices can be programmed off-board (plugged in a programming tool) or onboard using in-circuit programming or in-application programming.

The array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors.

• ICP (In-circuit programming)

• IAP (In-application programming)

• ICT (In-circuit testing) for downloading and executing user application test patterns in

RAM

• Sector 0 size configurable by option byte

• Readout and write protection.

The ST7 can be programmed in three different ways:

• Insertion in a programming tool. In this mode, Flash sectors 0 and 1 and option byte row can be programmed or erased.

• In-Circuit Programming. In this mode, Flash sectors 0 and 1 and option byte row can be programmed or erased without removing the device from the application board.

• In-application programming. In this mode, sector 1 can be programmed or erased without removing the device from the application board and while the application is running.

ICP uses a protocol called ICC (in-circuit communication) which allows an ST7 plugged on a

Obsolete Product(s) - Obsolete Product(s) via cable. ICP is performed in three steps:

• Switch the ST7 to ICC mode (in-circuit communications). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low.

When the ST7 enters ICC mode, it fetches a specific RESET vector which points to the

ST7 system memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface.

• Download ICP driver code in RAM from the ICCDATA pin

• Execute ICP driver code in RAM to program the Flash memory

20/146 DocID13474 Rev 3

ST7LITEU05 ST7LITEU09

4.3.2

Flash program memory

Depending on the ICP Driver code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading).

In Application Programming (IAP)

This mode uses an IAP driver program previously programmed in sector 0 by the user (in

ICP mode).

This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.)

IAP mode can be used to program any memory areas except sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.

ICP needs a minimum of 4 and up to 6 pins to be connected to the programming tool. These pins are:

• RESET: device reset

• V

SS

: device power supply ground

• ICCCLK: ICC output serial clock pin (see note 1)

• ICCDATA: ICC input serial data pin

• CLKIN: main clock input for external source

• V

DD

: application board power supply (see note 3)

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Flash program memory

APPLICATION

POWER SUPPLY

(See Note 3)

ST7LITEU05 ST7LITEU09

Figure 6. Typical ICC interface

PROGRAMMING TOOL

ICC CONNECTOR

ICC Cable

ICC CONNECTOR

HE10 CONNECTOR TYPE

OPTIONAL

(See Note 4) 9 7 5

10 8 6 4

3 1

2

APPLICATION BOARD

3.3k

Ω

(See Note 5)

APPLICATION

RESET SOURCE

See Note 2

See Note 1 and Caution

See Note 1

APPLICATION

I/O

ST7

1. If the ICCCLK or ICCDATA pins are only usedas outputs in the application, no signal isolation is necessary.

As soon as the programming tool isplugged to the board, even if an ICC session is not in progress, the

ICCCLK and ICCDATA pins arenot available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the programmingtool documentation for recommended resistor values.

2. During the ICP session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5 mA at high level

(push pull output or pull-up resistor < 1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset management IC with open drain output and pull-up resistor >1 K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

3. The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be connected when using most ST programming tools (it is used to monitor the application power supply).

Please refer to the programming tool manual.

4. Pin 9 has to be connected to the CLKIN pin of the ST7 when ICC mode is selected with option bytes disabled (35-pulse ICC entry mode). When option bytes are enabled (38-pulse ICC entry mode), the internal RC clock is forced, regardless of the selection in the option byte.

5. A serial resistor must be connected to ICC connector pin 6 in order to prevent contention on PA3/RESET pin. Contention may occur if a tool forces a state on RESET pin while PA3 pin forces the opposite state in output mode. The resistor value is defined to limit the current below 2 mA at 5 V. If PA3 is used as output push-pull, then the application must be switched off to allow the tool to take control of the RESET pin

(PA3). To allow the programming tool to drive the RESET pin below V when a pull-up is placed on PA3 for application reasons.

IL

, special care must also be taken

Caution: During normal operation, ICCCLK pin must be pulled- up, internally or externally (external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset puts it back in input pull-up.

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22/146 DocID13474 Rev 3

ST7LITEU05 ST7LITEU09 Flash program memory

There are two different types of memory protection: readout protection and write/erase protection which can be applied individually.

Readout protection, when selected provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. Program memory is protected.

In Flash devices, this protection is removed by reprogramming the option. In this case, program memory is automatically erased, and the device can be reprogrammed.

Readout protection selection depends on the device type:

• In Flash devices it is enabled and removed through the FMP_R bit in the option byte.

• In ROM devices it is enabled by mask option specified in the option list.

Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. Its purpose is to provide advanced security to applications and prevent any change being made to the memory content.

Warning: Once set, Write/erase protection can never be removed. A write-protected flash device is no longer reprogrammable.

Write/erase protection is enabled through the FMP_W bit in the option byte.

For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming

Reference Manual and to the ST7 ICC Protocol Reference Manual .

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Flash program memory ST7LITEU05 ST7LITEU09

This register controls the XFlash erasing and programming using ICP, IAP or other programming methods.

1st RASS Key: 0101 0110 (56h)

2nd RASS Key: 1010 1110 (AEh)

When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically.

Reset value: 000 0000 (00h)

7

0 0 0 0

Read/write

0 OPT LAT

0

PGM

Address

(Hex.)

002Fh

Register label

FCSR

Reset Value

7

-

0

6

-

0

5

-

0

4

-

0

3

-

0

2

OPT

0

1

LAT

0

0

PGM

0

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24/146 DocID13474 Rev 3

ST7LITEU05 ST7LITEU09 Data EEPROM

5.1 Introduction

The electrically erasable programmable read only memory can be used as a non volatile back-up for storing data. Using the EEPROM requires a basic access protocol described in this chapter.

• Up to 32 bytes programmed in the same cycle

• EEPROM mono-voltage (charge pump)

• Chained erase and programming cycles

• Internal control of the global programming cycle duration

• Wait mode management

• Readout protection

Figure 7. EEPROM block diagram

HIGH VOLTAGE

PUMP

EECSR

0 0 0 0 0 0 E2LAT E2PGM

ADDRESS

DECODER

4

ROW

DECODER

EEPROM

MEMORY MATRIX

(1 ROW = 32 x 8 BITS)

128

DATA

MULTIPLEXER

128

32 x 8 BITS

DATA LATCHES

4

4

ADDRESS BUS DATA BUS

Obsolete Product(s) - Obsolete Product(s)

The data EEPROM memory read/write access modes are controlled by the E2LAT bit of the

EEPROM Control/Status register (EECSR). The flowchart in Figure 8

describes these different memory access modes.

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Data EEPROM

5.3.1

ST7LITEU05 ST7LITEU09

Read operation (E2LAT=0)

The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR register is cleared.

On this device, data EEPROM can also be used to execute machine code. Take care not to write to the data EEPROM while executing from it. This would result in an unexpected code being executed.

Note:

To access the write mode, the E2LAT bit has to be set by software (the E2PGM bit remains cleared). When a write access to the EEPROM area occurs, the value is latched inside the

32 data latches according to its address.

When PGM bit is set by the software, all the previous bytes written in the data latches (up to

32) are programmed in the EEPROM cells. The effective high address (row) is determined by the last EEPROM write sequence. To avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same high address: only the five Least Significant Bits of the address can change.

At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously.

Care should be taken during the programming cycle. Writing to the same memory location over-programs the memory (logical AND between the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of the E2LAT bit. It is not possible to read the latched data.

This note is ilustrated by the

Figure 10

.

Figure 8. Data EEPROM programming flowchart

READ MODE

E2LAT=0

E2PGM=0

WRITE MODE

E2LAT=1

E2PGM=0

READ BYTES

IN EEPROM AREA

WRITE UP TO 32 BYTES

IN EEPROM AREA

(with the same 11 MSB of the address)

START PROGRAMMING CYCLE

E2LAT=1

E2PGM=1 (set by software)

Obsolete Product(s) - Obsolete Product(s)

0

E2LAT

1

CLEARED BY HARDWARE

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ST7LITEU05 ST7LITEU09

ROW

DEFINITION

Data EEPROM

Figure 9. Data EEPROM write operation

 Row / byte 

0

1

...

N

0 1 2 3 ...

30 31 Physical address

00h...1Fh

-

-

-

-

-

-

-

-

-

-

-

-

20h...3Fh

-

Nx20h...Nx20h+1Fh

Read operation impossible Read operation possible

E2LAT bit

Byte 1 Byte 2 Byte 32

PHASE 1

Writing data latches

Programming cycle

PHASE 2

Waiting E2PGM and E2LAT to fall

Set by USER application

Cleared by hardware

E2PGM bit

1. If a programming cycle is interrupted (by a reset action), the integrity of the data in memory is not guaranteed.

The data EEPROM can enter Wait mode on execution of the WFI instruction of the microcontroller or when the microcontroller enters Active-Halt mode.The DATA EEPROM immediately enters this mode if there is no programming in progress, otherwise the data

EEPROM finishes the cycle and then enter Wait mode.

Refer to Wait mode.

instruction. Therefore the EEPROM stops the function in progress, and data may be corrupted.

If a read access occurs while E2LAT=1, then the data bus is not driven.

If a write access occurs while E2LAT=0, then the data on the bus is not latched.

If a programming cycle is interrupted (by a Reset action), the integrity of the data in memory is not guaranteed.

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Data EEPROM ST7LITEU05 ST7LITEU09

Note:

The readout protection is enabled through an option bit (see option byte section).

When this option is selected, the programs and data stored in the EEPROM memory are protected against readout (including a re-write protection). In Flash devices, when this protection is removed by reprogramming the option byte, the entire Program memory and

EEPROM is first automatically erased.

Both program memory and data EEPROM are protected using the same option bit.

Figure 10. Data EEPROM programming cycle

Read operation not possible Read operation possible

Internal programming voltage

WRITE OF

DATA LATCHES

ERASE CYCLE t

PROG

WRITE CYCLE

LAT

PGM

Address: 0030h

Reset value: 0000 0000 (00h)

7

0 0 0 0 E2LAT

0

E2PGM 0

Read/write

0

Bits 7:2 = Reserved , forced by hardware to 0

Bit 1 = E2LAT Latch access transfer bit:

This bit is set by software. It is cleared by hardware at the end of the programming cycle. It can only be cleared by software if the E2PGM bit is cleared Obsolete Product(s) - Obsolete Product(s)

1: Write mode

Note:

Bit 0 = E2PGM Programming control and status bit

This bit is set by software to begin the programming cycle. At the end of the programming cycle, this bit is cleared by hardware.

0: Programming finished or not yet started

1: Programming cycle is in progress

If the E2PGM bit is cleared during the programming cycle, the memory data is not guaranteed.

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ST7LITEU05 ST7LITEU09 Data EEPROM

Address

(Hex.)

0030h

Register

Label

Table 3. Data EEPROM register map and reset values

7 6 5 4 3 2

EECSR

Reset Value 0 0 0 0 0 0

1 0

E2LAT

0

E2PGM

0

Obsolete Product(s) - Obsolete Product(s)

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Central processing unit

6 Central processing unit

ST7LITEU05 ST7LITEU09

6.1 Introduction

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation.

• 63 basic instructions

• Fast 8-bit by 8-bit multiply

• 17 main addressing modes

• Two 8-bit index registers

• 16-bit stack pointer

• Low-power modes

• Maskable hardware interrupts

• Non-maskable software interrupt

The six CPU registers shown in Figure 11

are not present in the memory mapping and are accessed by specific instructions.

The accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.

6.3.2 Index registers (X and Y)

In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The cross-assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the

Y register.)

The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). Obsolete Product(s) - Obsolete Product(s)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (program counter low which is the LSB) and PCH (Program Counter High which is the MSB).

30/146 DocID13474 Rev 3

ST7LITEU05 ST7LITEU09 Central processing unit

15 PCH

7

Figure 11. CPU registers

0

ACCUMULATOR

RESET VALUE = XXh

7 0

X INDEX REGISTER

RESET VALUE = XXh

7 0

Y INDEX REGISTER

8

RESET VALUE = XXh

7 PCL 0

PROGRAM COUNTER

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

7

1

RESET VALUE = 1

1 1 H I N Z

1 1 X 1 X X

0

C

X

15 8 7 0

CONDITION CODE REGISTER

STACK POINTER

RESET VALUE = STACK HIGHER ADDRESS

1.

X = undefined value

The 8-bit condition code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

Reset value: 111x 1xxx

7

1 1 1 N Z

0

C H

Read/write

I

These bits can be individually tested and/or controlled by specific instructions.

Bit 4 = H Half carry bit

This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions.

0: No half carry has occurred.

Obsolete Product(s) - Obsolete Product(s)

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

Bit 3 = I Interrupt mask bit

This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software.

0: Interrupts are enabled.

1: Interrupts are disabled.

This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions.

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Central processing unit ST7LITEU05 ST7LITEU09

Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine.

Bit 2 = N Negative bit

This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7 th

bit of the result.

0: The result of the last operation is positive or null.

1: The result of the last operation is negative (that is, the most significant bit is a logic

1).

This bit is accessed by the JRMI and JRPL instructions.

Bit 1 = Z Zero bit

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero.

0: The result of the last operation is different from zero.

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test instructions.

Bit 0 = C Carry/borrow bit

This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation.

0: No overflow or underflow has occurred.

1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

6.3.5 Stack pointer (SP)

Reset Value: 00 FFh

15

0 0 0 0 0 0 0

8

0

Read/write

7 0

1 1 SP5 SP4 SP3

Read/write

SP2 SP1 SP0

Obsolete Product(s) - Obsolete Product(s)

The stack pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented

before data is popped from the stack (see Figure 12 ).

Since the stack is 64 bytes deep, the 10 most significant bits are forced by hardware.

Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP5 to SP0 bits are set) which is the stack higher address.

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Note:

Central processing unit

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.

When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.

The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in

Figure 12

.

• When an interrupt is received, the SP is decremented and the context is pushed on the stack.

• On return from interrupt, the SP is incremented and the context is popped from the stack.

A subroutine call occupies two locations and an interrupt five locations in the stack area.

CALL

Subroutine

@ 00C0h

Figure 12. Stack manipulation example

Interrupt event

PUSH Y POP Y IRET RET or RSP

SP

@ 00FFh

PCH

PCL

SP

CC

A

X

PCH

PCL

PCH

PCL

SP

Y

CC

A

X

PCH

PCL

PCH

PCL

SP

CC

A

X

PCH

PCL

PCH

PCL

SP

PCH

PCL

SP

1.

Stack higher address = 00FFh

Stack lower address = 00C0h

Obsolete Product(s) - Obsolete Product(s)

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Supply, reset and clock management

7 Supply, reset and clock management

ST7LITEU05 ST7LITEU09

The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components.

• Clock management

– 8 MHz internal RC oscillator (enabled by option byte)

– External clock input (enabled by option byte)

• Reset sequence manager (RSM)

• System integrity management (SI)

– Main supply low voltage detection (LVD) with reset generation (enabled by option byte)

– Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main supply

7.2 Internal RC oscillator adjustment

The ST7 contains an internal RC oscillator with a specific accuracy for a given device, temperature and voltage. It can be selected as the start up clock through the CKSEL[1:0] option bits (see

Section 15.1: Option bytes

). It must be calibrated to obtain the frequency required in the application. This is done by software writing a 10-bit calibration value in the

RCCR (RC Control Register) and in the bits [6:5] in the SICSR (SI control status register).

Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), i.e. each time the device is reset, the calibration value must be loaded in the RCCR. Predefined calibration values are stored in Flash memory for 3.3 and 5 V V

DD as shown in the following table.

supply voltages at 25 °C,

Table 4. Predefined RC oscillator calibration values

Conditions ST7LITEU05/ST7LITEU09 address RCCR

RCCRH0

RCCRL0 f

V

DD

T

A

RC

= 5 V

= 25 °C

= 8 MHz Obsolete Product(s) - Obsolete Product(s)

RCCRH1

DEE1h

(1)

(CR[1:0] bits)

DEE2h

(1)

(CR[9:2] bits)

RCCRL1

V

DD

T

A f

RC

= 3.3 V

= 25 °C

= 8 MHz

DEE0h

(1)

(CR[9:2] bits)

DEE3h

(1)

(CR[1:0] bits)

1. DEE0h, DEE1h, DEE2h and DEE3h are located in a reserved area but are special bytes containing also the RC calibration values which are read-accessible only in user mode. If all the Flash space (including the

RC calibration value locations) has been erased (after the readout protection removal), then the RC calibration values can still be obtained through these two addresses.

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ST7LITEU05 ST7LITEU09 Supply, reset and clock management

Note: In ICC mode, the internal RC oscillator is forced as a clock source, regardless of the selection in the option byte. Refer to note 5 in

Section 4.4: ICC interface for further details.

Section 13: Electrical characteristics for more information on the frequency and accuracy of

the RC oscillator.

To improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the V

DD device.

and V

SS

pins as close as possible to the ST7

Caution: If the voltage or temperature conditions change in the application, the frequency may need to be recalibrated.

Refer to application note AN2326 for information on how to calibrate the RC frequency using an external reference signal.

The ST7ULTRALITE also contains an Auto Wake Up RC oscillator. This RC oscillator should be enabled to enter Auto Wake-up from Halt mode.

The Auto-wakeup RC oscillator can also be configured as the startup clock through the

CKSEL[1:0] option bits (see Section 15.1: Option bytes ).

This is recommended for applications where very low power-consumption is required.

Switching from one startup clock to another can be done in run mode as follows (see

Figure 13

):

Case 1: Switching from internal RC to AWU :

1.

Set the RC/AWU bit in the CKCNTCSR register to enable the AWU RC oscillator

2. The RC_FLAG is cleared and the clock output is at 1.

3. Wait 3 AWU RC cycles till the AWU_FLAG is set

4. The switch to the AWU clock is made at the positive edge of the AWU clock signal

5. Once the switch is made, the internal RC is stopped

Case 2: Switching from AWU RC to internal RC:

1.

Reset the RC/AWU bit to enable the internal RC oscillator

2. Using a 4-bit counter, wait until 8 internal RC cycles have elapsed. The counter is running on internal RC clock.

3. Wait till the AWU_FLAG is cleared (1AWU RC cycle) and the RC_FLAG is set (2 RC cycles)

4. The switch to the internal RC clock is made at the positive edge of the internal RC clock signal

5. Once the switch is made, the AWU RC is stopped

2 When the internal RC is selected, the AWU RC is turned on by hardware when entering

Auto Wake-Up from Halt mode.

3 When the external clock is selected, the AWU RC oscillator is always on.

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Supply, reset and clock management

Figure 13. Clock switching

Internal RC

Set RC/AWU

Poll AWU_FLAG until set

AWU RC

ST7LITEU05 ST7LITEU09

AWU RC

Reset RC/AWU

Poll RC_FLAG until set

Internal RC

Figure 14. Clock management block diagram

CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 RCCR

CR1 CR0 SICSR

Tunable internal RC Oscillator

8 MHz(f

RC

)

Prescaler

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

RC OSC

CLKIN

CK2 CK1 CK0 f

CLKIN

AWU

RC

/2

DIVIDER

33kHz

RC/AWU CKCNTCSR

AVDTHCR

Clock

Controller

AWU CK

Ext Clock

CKSEL[1:0]

Option bits f

OSC f

OSC

/32 DIVIDER

13-BIT

LITE TIMER COUNTER f

OSC

0 f

OSC

/32

1 f

LTIMER

(1ms timebase @ 8 MHz f

OSC

) f

CPU

TO CPU AND

PERIPHERALS

MCO SMS

MCO

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ST7LITEU05 ST7LITEU09 Supply, reset and clock management

7.3.2

Reset value: 0000 0000 (00h)

7

0 0 0 0

Read/write

0 0 MCO

0

SMS

Bits 7:2 = Reserved, must be kept cleared.

Bit 1 = MCO Main Clock Out enable bit

This bit is read/write by software and cleared by hardware after a reset. This bit allows to enable the MCO output clock.

0: MCO clock disabled, I/O port free for general purpose I/O.

1: MCO clock enabled.

Bit 0 = SMS Slow mode selection bit

This bit is read/write by software and cleared by hardware after a reset. This bit selects the input clock f

OSC

or f

OSC

/32.

0: Normal mode (f

CPU = f

OSC

)

1: Slow mode (f

CPU = f

OSC

/32)

RC control register (RCCR)

Reset value: 1111 1111 (FFh)

7

CR9 CR8 CR7 CR6 CR5

Read/write

CR4 CR3

0

CR2

Bits 7:0 = CR[9:2] RC oscillator frequency adjustment bits

These bits, as well as CR[1:0] bits in the SICSR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain the required accuracy.

The application can store the correct value for each voltage range in Flash memory and write it to this register at start-up.

Note: To tune the oscillator, write a series of different values in the register until the correct frequency is reached. The fastest method is to use a dichotomy starting with 80h.

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Supply, reset and clock management

7.3.3

7.3.4

ST7LITEU05 ST7LITEU09

System integrity (SI) control/status register (SICSR)

Reset Value: 0000 0x00 (0xh)

7

0 CR1 CR0

CK2

0

0

0

1

0 0

Read/write

LVDRF AVDF

Table 5. Internal RC prescaler selection bits

CK1 CK0

0

1

1

0

1

0

1

0 f

OSC f

RC/2 f

RC/4 f

RC/8 f

RC/16

0

AVDIE

Bit 7 = Reserved, must be kept cleared.

Bits 6:5 = CR[1:0] RC oscillator frequency adjustment bits

These bits, as well as CR[9:2] bits in the RCCR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain the required accuracy.

Refer to Section 7.2: Internal RC oscillator adjustment

.

Bits 4:3 = Reserved, must be kept cleared.

Bits 2:0 = System Integrity bits. Refer to Section 8.4: System integrity management (SI)

.

AVD threshold selection register (AVDTHCR)

Reset Value: 0000 0011 (03h)

7

CK2 CK1 CK0 0 0

Read/write

0 AVD1

0

AVD0

Bits 7:5 = CK[2:0] internal RC prescaler selection

These bits are set by software and cleared by hardware after a reset. These bits select the prescaler of the internal RC oscillator. See

Figure 14

and the following table and note:

Note: If the internal RC is used with a supply operating range below 3.3V, a division ratio of at least 2 must be enabled in the RC prescaler.

Bits 4:2 = Reserved, must be kept cleared.

Bits 1:0 = AVD threshold selection bits. Refer to

Section 8.4: System integrity management

(SI)

.

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ST7LITEU05 ST7LITEU09 Supply, reset and clock management

Reset Value: 0000 1001 (09h)

7

0 0 0 0 AWU_FLAG

Read/write

RC_FLAG

Bits 7:4 = Reserved, must be kept cleared.

Bit 3 = AWU_FLAG AWU selection bit

This bit is set and cleared by hardware.

0: No switch from AWU to RC requested

1: AWU clock activated and temporization completed

Bit 2 = RC_FLAG RC selection bit

This bit is set and cleared by hardware.

0: No switch from RC to AWU requested

1: RC clock activated and temporization completed

Bit 1 = Reserved, must be kept cleared.

Bit 0 = RC/AWU RC/AWU selection bit

0: RC enabled

1: AWU enabled (default value)

0

0

RC/AWU

Table 6. Clock register map and reset values

Address

(Hex.)

Register label

7 6 5 4 3 2 1 0

0038h

0039h

003Ah

MCCSR

Reset Value

RCCR

Reset Value

SICSR

Reset Value

-

0

CR9

1

-

0

-

0

CR8

1

CR1

0

-

0

CR7

1

CR0

0

-

0

CR6

1

-

0

-

0

CR5

1

-

0

-

0

CR4

1

LVDRF x

MCO

0

CR3

1

AVDF

0

SMS

0

CR2

1

AVDIE

0

AVDTHCR CK2 CK1 CK0 AVD1 AVD2

003Eh

Obsolete Product(s) - Obsolete Product(s)

003Fh

Reset Value

CKCNTCSR

Reset Value

0

-

0

0

-

0

0

-

0

0

-

0

0

AWU_FLAG

1

0

RC_FLAG

0

1

-

1

0

RC/AWU

1

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Supply, reset and clock management ST7LITEU05 ST7LITEU09

7.4 Reset sequence manager (RSM)

7.4.1 Introduction

Note:

The reset sequence manager includes three Reset sources as shown in

Figure 16

:

• External RESET source pulse

• Internal LVD Reset (low voltage detection)

• Internal WATCHDOG Reset

A reset can also be triggered following the detection of an illegal opcode or prebyte code.

Refer to Figure 16 .

These sources act on the RESET pin and it is always kept low during the delay phase.

The Reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.

The basic Reset sequence consists of 3 phases as shown in

Figure 15

:

• Active phase depending on the Reset source

• 256 or 512 CPU clock cycle delay (see table below)

• Reset vector fetch

Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the Reset vector is not programmed. For this reason, it is recommended to keep the RESET pin in low state until programming mode is entered, in order to avoid unwanted behavior.

The 256 or 512 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay is automatically selected depending on the clock source chosen by option byte after a reset or depending on the clock source selected before entering Halt mode or AWU from Halt mode.

Refer to Table 7

.

The Reset vector fetch phase duration is 2 clock cycles.

Table 7. CPU clock cycle delay

Clock source

Internal RC oscillator

External clock (connected to CLKIN pin)

AWURC

CPU clock cycle delay

512

256

Active Phase

RESET

INTERNAL RESET

256 OR 512 CLOCK CYCLES

FETCH

VECTOR

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ST7LITEU05 ST7LITEU09

RESET

V

DD

Supply, reset and clock management

Figure 16. Reset block diagram

R

ON

FILTER

PULSE

GENERATOR

INTERNAL

RESET

WATCHDOG RESET

ILLEGAL OPCODE RESET 1)

LVD RESET

7.4.2

7.4.3

1. See

Section 12.2.1: Illegal opcode reset

for more details on illegal opcode reset conditions.

Asynchronous external RESET pin

The RESET pin is both an input and an open-drain output with integrated R

ON

weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details.

A Reset signal originating from an external source must have a duration of at least t h(RSTL)in

in order to be recognized (see Figure 17 ). This detection is asynchronous and therefore the

MCU can enter reset state even in Halt mode.

The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section.

External power-on reset

If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until V

DD the minimum level specified for the selected f

CLKIN

frequency.

is over

A proper reset signal for a slow rising V

DD

RC network connected to the RESET pin.

supply can generally be provided by an external

Internal low voltage detector (LVD) reset

Two different Reset sequences caused by the internal LVD circuitry can be distinguished:

• Power-on reset

• Voltage drop reset

The device RESET pin acts as an output that is pulled low when V

DD

V

DD

<V

IT-

(falling edge) as shown in Figure 17 .

<V

IT+

(rising edge) or

The LVD filters spikes on V

DD larger than t g(VDD) to avoid parasitic resets.

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Supply, reset and clock management ST7LITEU05 ST7LITEU09

The Reset sequence generated by a internal Watchdog counter overflow is shown in

Figure 17

.

Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least t w(RSTL)out

.

Figure 17. Reset sequences

V

DD

V

IT+(LVD)

V

IT-(LVD)

RUN

LVD

RESET

ACTIVE PHASE

RUN

EXTERNAL

RESET

ACTIVE

PHASE

WATCHDOG

RESET

RUN

ACTIVE

PHASE

RUN t h(RSTL)in t w(RSTL)out

EXTERNAL

RESET

SOURCE

RESET PIN

WATCHDOG

RESET

WATCHDOG UNDERFLOW

INTERNAL RESET (256 or 512 T

CPU

VECTOR FETCH

)

Obsolete Product(s) - Obsolete Product(s)

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ST7LITEU05 ST7LITEU09 Supply, reset and clock management

7.5.1 Multiplexed IO reset control register 1 (MUXCR1)

Reset value: 0000 0000 (00h)

7

MIR15 MIR14 MIR13 MIR12 MIR11

Read/write once only

MIR10 MIR9

0

MIR8

7.5.2 Multiplexed IO reset control register 0 (MUXCR0)

Reset value: 0000 0000 (00h)

7

MIR7 MIR6 MIR5 MIR4 MIR3

Read/write once only

MIR2 MIR1

0

MIR0

Bits 15:0 = MIR[15:0]

This 16-bit register is read/write by software but can be written only once between two reset events. It is cleared by hardware after a reset; When both MUXCR0 and

MUXCR1 registers are at 00h, the multiplexed PA3/RESET pin acts as RESET. To configure this pin as output (Port A3), write 55h to MUXCR0 and AAh to MUXCR1.

These registers are one-time writable only.

To configure PA3 as general purpose output:

After power-on / reset, the application program has to configure the I/O port by writing to these registers as described above. Once the pin is configured as an I/O output, it cannot be changed back to a reset pin by the application code.

To configure PA3 as RESET:

An internally generated reset (such as POR, WDG, illegal opcode) clears the two registers and the pin acts again as a reset function. Otherwise, a power-down is required to put the pin back in reset configuration.

Table 8. Multiplexed IO register map and reset values

Address Register

7 6 5 4 3 2 1 Obsolete Product(s) - Obsolete Product(s)

MUXCR0 MIR7 MIR6 MIR5 MIR4 MIR3 MIR2 MIR1

0

MIR0

0047h

Reset Value 0 0 0 0 0 0 0 0

0048h

MUXCR1

Reset Value

MIR15

0

MIR14

0

MIR13

0

MIR12

0

MIR11

0

MIR10

0

MIR9

0

MIR8

0

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Interrupts

8 Interrupts

Note:

Note:

ST7LITEU05 ST7LITEU09

The ST7 core may be interrupted by one of two different methods: Maskable hardware interrupts as listed in the “interrupt mapping” table and a non-maskable software interrupt

(TRAP). The Interrupt processing flowchart is shown in Figure 18 .

The maskable interrupts must be enabled by clearing the I bit in order to be serviced.

However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection).

After reset, all interrupts are disabled.

When an interrupt has to be serviced:

• Normal processing is suspended at the end of the current instruction execution.

• The PC, X, A and CC registers are saved onto the stack.

• The I bit of the CC register is set to prevent additional interrupts.

• The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping table for vector addresses).

The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack.

As a consequence of the IRET instruction, the I bit is cleared and the main program resumes.

Priority management

By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine.

In the case when several interrupts are simultaneously pending, a hardware priority defines

which one is serviced first (see Table 9: Interrupt mapping ).

Interrupts and low-power mode

All interrupts allow the processor to leave the Wait low-power mode. Only external and specifically mentioned interrupts allow the processor to leave the Halt low-power mode

(refer to the “Exit from Halt” column in the Interrupt Mapping table).

Obsolete Product(s) - Obsolete Product(s)

8.1 Non maskable software interrupt

This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. It is serviced according to the flowchart in

Figure 18

.

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ST7LITEU05 ST7LITEU09 Interrupts

External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the

Halt low-power mode.

The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available).

An external interrupt triggered on edge is latched and the interrupt request automatically cleared upon entering the interrupt service routine.

Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of a NANDed source (as described in the I/O ports section), a low level on an I/O pin, configured as input with interrupt, masks the interrupt request even in case of rising-edge sensitivity.

Note:

Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both:

• The I bit of the CC register is cleared.

• The corresponding enable bit is set in the control register.

If any of these two conditions is false, the interrupt is latched and thus remains pending.

Clearing an interrupt request is done by:

• Writing “0” to the corresponding bit in the status register or

• Access to the status register while the flag is set followed by a read or write of an associated register.

The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for being enabled) is therefore lost if the clear sequence is executed.

Figure 18. Interrupt processing flowchart

FROM RESET

N

I BIT SET?

Y N INTERRUPT

PENDING?

FETCH NEXT INSTRUCTION

Obsolete Product(s) - Obsolete Product(s)

N

IRET?

Y

STACK PC, X, A, CC

SET I BIT

Y

LOAD PC FROM INTERRUPT VECTOR

EXECUTE INSTRUCTION

RESTORE PC, X, A, CC FROM STACK

THIS CLEARS I BIT BY DEFAULT

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Interrupts ST7LITEU05 ST7LITEU09

Table 9. Interrupt mapping

N°

Source block

Description

Register label

Priority order

Exit from

Halt

Address vector

4

5

6

3)

7

0

1

-

-

2

3

2)

8

9

10

11

12

13

RESET

TRAP

AWU ei0 ei1 ei2

-

-

-

(2) ei3 ei4

(3)

SI

AT TIMER

LITE TIMER

Reset

Software interrupt

Auto Wakeup interrupt

External interrupt 0

External interrupt 1

External interrupt 2

(2)

Not used

External interrupt 3

External interrupt 4

(3)

AVD interrupt

AT TIMER output compare interrupt

AT TIMER overflow Interrupt

LITE TIMER input capture interrupt

LITE TIMER RTC1 interrupt

Not used

Not used

N/A

AWUCSR

N/A

SICSR

PWMxCSR or ATCSR

ATCSR

LTCSR

LTCSR

-

-

Highest priority

Lowest priority yes no FFFCh-FFFDh yes

(1) yes no no yes no yes no no

(4)

(4)

FFFEh-FFFFh

FFFAh-FFFBh

FFF8h-FFF9h

FFF6h-FFF7h

FFF4h-FFF5h

FFF2h-FFF3h yes FFF0h-FFF1h no

(3)

FFEEh-FFEFh no FFECh-FFEDh

FFEAh-FFEBh

FFE8h-FFE9h

FFE6h-FFE7h

FFE4h-FFE5h

FFE2h-FFE3h

FFE0h-FFE1h

1. This interrupt exits the MCU from “Auto Wake-up from Halt” mode only.

2. Whatever the sensitivity configuration, this interrupt cannot exit the MCU from Halt, Active-Halt and

AWUFH modes when a falling edge occurs.

3. This interrupt exits the MCU from “Wait” and “Active-Halt” modes only. Moreover IS4[1:0] =01 is the only safe configuration to avoid spurious interrupt in Halt and AWUFH modes.

4. These interrupts exit the MCU from “Active-Halt” mode only.

Obsolete Product(s) - Obsolete Product(s)

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ST7LITEU05 ST7LITEU09 Interrupts

8.3.1 External interrupt control register 1 (EICR1)

Reset value: 0000 0000 (00h)

7

0 0 IS21 IS20 IS11

Read/write

IS10 IS01

0

IS00

Bits 7:6 = Reserved, must be kept cleared.

Bits 5:4 = IS2[1:0] ei2 sensitivity bits

These bits define the interrupt sensitivity for ei2 (Port C) according to

Table 10 .

Bits 3:2 = IS1[1:0] ei1 sensitivity bits

These bits define the interrupt sensitivity for ei1 (Port B) according to

Table 10 .

Bits 1:0 = IS0[1:0] ei0 sensitivity bits

These bits define the interrupt sensitivity for ei0 (Port A) according to

Table 10 .

Note: 1 These 8 bits can be written only when the I bit in the CC register is set.

2 Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts. Refer to Section : External interrupt function .

3 Whatever the sensitivity configuration, ei2 cannot exit the MCU from Halt, Active-Halt and

AWUFH modes when a falling edge occurs.

ISx1

0

0

1

1

ISx0

0

1

0

1

Table 10. Interrupt sensitivity bits

External interrupt sensitivity

Falling edge & low level

Rising edge only

Falling edge only

Rising and falling edge

8.3.2 External interrupt control register 2 (EICR2)

Reset Value: 0000 0000 (00h)

7

0 0 0 0 IS41 IS40 IS31

0

IS30

Read/write

Bits 7:4 = Reserved

Bits 3:2 = IS4[1:0] ei4 sensitivity

These bits define the interrupt sensitivity for ei1 according to

Table 10

.

Bits 1:0 = IS3[1:0] ei3 sensitivity

These bits define the interrupt sensitivity for ei0 according to

Table 10

.

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Interrupts ST7LITEU05 ST7LITEU09

Note: 1 These 8 bits can be written only when the I bit in the CC register is set.

2 Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts. Refer to section Section : External interrupt function .

3 IS4[1:0] = 01 is the only safe configuration to avoid spurious interrupt in Halt and AWUFH modes.

Note:

8.4.1

The system integrity management block contains the low voltage detector (LVD) and

Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register.

A reset can also be triggered following the detection of an illegal opcode or prebyte code.

Refer to Section 12.2.1: Illegal opcode reset for further details.

Low voltage detector (LVD)

The Low Voltage Detector function (LVD) generates a static reset when the V

DD voltage is below a V

IT-(LVD) as the power-down keeping the ST7 in reset.

supply

reference value. This means that it secures the power-up as well

The V

IT-(LVD)

reference value for a voltage drop is lower than the V

IT+(LVD)

reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when V

DD

is below:

• V

IT+(LVD)

when V

DD

is rising

• V

IT-(LVD)

when V

DD

is falling

The LVD function is illustrated in

Figure 19

.

The voltage threshold can be configured by option byte to be low, medium or high. See

Section 15.1: Option bytes .

Provided the minimum V

DD

value (guaranteed for the oscillator frequency) is above V

IT-

(LVD)

, the MCU can only be in two modes:

• under full software control

• in static safe reset

In these conditions, secure operation is always ensured for the application without the need for external reset hardware.

reset other devices.

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ST7LITEU05 ST7LITEU09 Interrupts

Note: Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is recommended to pull V

DD

down to 0V to ensure optimum restart

conditions. Refer to circuit example in Figure 67: RESET pin protection when LVD is disabled and note 4.

The LVD is an optional function which can be selected by option byte. See

Section 15.1:

Option bytes

. It allows the device to be used without any external Reset circuitry. If the LVD is disabled, an external circuitry must be used to ensure a proper power-on reset.

It is recommended to make sure that the V

DD supply voltage rises monotonously when the device is exiting from Reset, to ensure the application functions properly.

Make sure the right combination of LVD and AVD thresholds is used as LVD and AVD levels

are not correlated. Refer to Section 13.3.2: Operating conditions with low voltage detector

(LVD)

and

Section 13.3.3: Auxiliary voltage detector (AVD) thresholds for more details.

Caution: If an LVD reset occurs after a watchdog reset has occurred, the LVD takes the priority and clears the watchdog flag.

Figure 19. Low voltage detector vs reset

V

DD

V hys

V

V

IT+ (LVD)

IT(LVD)

RESET

RESET

Figure 20. Reset and supply management block diagram

RESET SEQUENCE

MANAGER

(RSM)

WATCHDOG

TIMER (WDG)

STATUS FLAG

SYSTEM INTEGRITY MANAGEMENT

AVD Interrupt Request

SICSR

7

0 1 1 0 0

LVD

RF

AVD

F

AVD

IE

0

V

SS

V

DD

LOW VOLTAGE

DETECTOR

(LVD)

DETECTOR

(AVD)

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Interrupts ST7LITEU05 ST7LITEU09

8.4.2 Auxiliary voltage detector (AVD)

The voltage detector function (AVD) is based on an analog comparison between a V

IT-(AVD) and V

IT+(AVD)

reference value and the V

DD

main supply voltage (V reference value for falling voltage is lower than the V

IT+(AVD) voltage in order to avoid parasitic detection (hysteresis).

AVD

). The V

IT-(AVD)

reference value for rising

The output of the AVD comparator is directly readable by the application software through a real time status bit (AVDF) in the SICSR register. This bit is read only.

Note:

Monitoring the V

DD

main supply.

The AVD threshold is selected by the AVD[1:0] bits in the AVDTHCR register.

If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the

V

IT+(AVD)

or V

IT-(AVD)

threshold (AVDF bit is set).

In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing

software to shut down safely before the LVD resets the microcontroller. See Figure 21 .

The interrupt on the rising edge is used to inform the application that the V

DD is over

warning state

Make sure the right combination of LVD and AVD thresholds is used as LVD and AVD levels

are not correlated. Refer to Section 13.3.2: Operating conditions with low voltage detector

(LVD)

and

Section 13.3.3: Auxiliary voltage detector (AVD) thresholds for more details.

V

DD

Figure 21. Using the AVD to monitor V

DD

Early warning interrupt

(Power has dropped, MCU not not yet in reset)

V hyst

V

IT+(AVD)

V

IT-(AVD)

V

IT+(LVD)

V

IT-(LVD)

AVDF bit 0 1 RESET 1 0

AVD INTERRUPT

REQUEST

IF AVDIE bit = 1

INTERRUPT Cleared by reset

INTERRUPT Cleared by hardware Obsolete Product(s) - Obsolete Product(s)

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ST7LITEU05 ST7LITEU09 Interrupts

Wait

Halt

Table 11. Description of low-power modes

Mode Description

No effect on SI. AVD interrupts cause the device to exit from Wait mode.

The SICSR register is frozen.

The AVD remains active but the AVD interrupt cannot be used to exit from Halt mode.

Interrupts

The AVD interrupt event generates an interrupt if the corresponding enable control bit

(AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).

AVD event

Interrupt event

Table 12. Description of interrupt events

Event fl ag

Enable control bit

Exit from

Wait

AVDF AVDIE Yes

Exit from

Halt

No

Note:

System integrity (SI) control/status register (SICSR)

Reset value: 0000 0x00 (0xh)

7

0 CR1 CR0 0

Read/write

0 LVDRF AVDF

0

AVDIE

Bit 7 = Reserved, must be kept cleared.

Bits 6:5 = CR[1:0] RC oscillator frequency adjustment bits

These bits, as well as CR[9:2] bits in the RCCR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain the required accuracy.

Refer to Section 7.2: Internal RC oscillator adjustment

.

Bits 4:3 = Reserved, must be kept cleared.

This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared when read. See WDGRF flag description in

Section 11.1: Lite timer (LT)

for more details. When the LVD is disabled by option byte, the LVDRF bit value is undefined.

If the selected clock source is one of the two internal ones, and if V

DD selected LVD threshold during less than T

AWU_RC

remains below the

(33 µs typ.), the LVDRF flag cannot be set even if the device is reset by the LVD. If the selected clock source is the external clock

(CLKIN), the flag is never set if the reset occurs during Halt mode. In run mode the flag is set only if f

CLKIN

is greater than 10 MHz.

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Interrupts ST7LITEU05 ST7LITEU09

Bit 1 = AVDF Voltage Detector flag

This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt

request is generated when the AVDF bit is set. Refer to Figure 21 for additional details;

0: V

DD

1: V

DD

over AVD threshold

under AVD threshold

Bit 0 = AVDIE Voltage Detector interrupt enable

This bit is set and cleared by software. It enables an interrupt to be generated when the

AVDF flag is set. The pending interrupt information is automatically cleared when software enters the AVD interrupt routine.

0: AVD interrupt disabled

1: AVD interrupt enabled

AVD threshold selection register (AVDTHCR)

Reset value: 0000 0011 (03h)

7

CK2 CK1 CK0 0 0

Read/write

0 AVD1

0

AVD0

Bits 7:5 = CK[2:0] internal RC Prescaler Selection

Refer to Section 7.2: Internal RC oscillator adjustment

.

Bits 4:2 = Reserved, must be kept cleared.

Bits 1:0 = AVD[1:0] AVD Threshold Selection

These bits are set and cleared by software and set by hardware after a reset. They select the AVD threshold.

AVD1

0

0

1

1

AVD0

0

1

0

1

Table 13. AVD threshold selection bits

Functionality

Low

Medium

High

AVD off

Note: Application notes Obsolete Product(s) - Obsolete Product(s)

LVDRF flag remains set to keep trace of the original failure.

In this case, a watchdog reset can be detected by software while an external reset can not.

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ST7LITEU05 ST7LITEU09 Interrupts

Address

(Hex.)

003Ah

003Eh

Table 14. System integrity register map and reset values

Register label

7 6 5 4 3 2 1

SICSR

Reset value

AVDTHCR

Reset value

0

CK2

0

1

CK1

0

1

CK0

0

0

0

0

0

LVDRF x

0

AVDF

0

AVD1

1

0

AVDIE

0

AVD2

1

Obsolete Product(s) - Obsolete Product(s)

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Power saving modes

9 Power saving modes

ST7LITEU05 ST7LITEU09

9.1 Introduction

To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see

Figure 22

):

• Slow

• Wait (and Slow-Wait)

• Active-halt

• Auto-wakeup from Halt (AWUFH)

• Halt

After a Reset the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency (f

OSC

).

From RUN mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status.

Figure 22. Power saving mode transitions

High

RUN

SLOW

Wait

SLOW Wait

ACTIVE HALT

HALT

Low

POWER CONSUMPTION

Note:

54/146

• To reduce power consumption by decreasing the internal clock in the device,

• To adapt the internal clock frequency (f

CPU

) to the available supply voltage.

Slow mode is controlled by the SMS bit in the MCCSR register which enables or disables

Slow mode.

In this mode, the oscillator frequency is divided by 32. The CPU and peripherals are clocked at this lower frequency.

Slow-Wait mode is activated when entering Wait mode while the device is already in Slow mode.

DocID13474 Rev 3

ST7LITEU05 ST7LITEU09

Figure 23. Slow mode clock transition f

OSC

/32 f

OSC f

CPU f

OSC

SMS

NORMAL RUN MODE

REQUEST

Power saving modes

Wait mode places the MCU in a low power-consumption mode by stopping the CPU.

This power saving mode is selected by calling the ‘WFI’ instruction.

All peripherals remain active. During Wait mode, the I bit of the CC register is cleared, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in Wait mode until an interrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine.

The MCU remains in Wait mode until a Reset or an Interrupt occurs, causing it to wake up.

Refer to Figure 24 below.

Figure 24. Wait mode flowchart

WFI INSTRUCTION

OSCILLATOR

PERIPHERALS

CPU

I BIT

ON

ON

OFF

0

N

RESET

Y

N

INTERRUPT

Y

OSCILLATOR

PERIPHERALS

CPU

I BIT

ON

OFF

ON

0

256 OR 512 CPU CLOCK

CYCLE DELAY

Obsolete Product(s) - Obsolete Product(s)

PERIPHERALS

CPU

I BIT

ON

ON

X 1)

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note: 1 Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.

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Power saving modes

9.4 Active-halt and Halt modes

ST7LITEU05 ST7LITEU09

Active-Halt and Halt modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘Halt’ instruction. The decision to enter either in Active-

Halt or Halt mode is given by the LTCSR/ATCSR register status as shown in the following table:

LTCSR TBIE bit

Table 15. Enabling/disabling Active-halt and Halt modes

ATCSR OVFIE bit

ATCSRCK1 bit ATCSRCK0 bit Meaning

0

1

0

0 x

1 x x

0

1

1 x x x

0

1 x

0 x

1

Active-Halt mode disabled

Active-Halt mode enabled

Active-halt mode is the lowest power consumption mode of the MCU with a real time clock available. It is entered by executing the ‘Halt’ instruction when active halt mode is enabled.

The MCU can exit Active-halt mode on reception of a Lite Timer / AT Timer interrupt or a

Reset.

• When exiting Active-halt mode by means of a Reset, a 256 or 512 CPU cycle delay occurs. After the start up delay, the CPU resumes operation by fetching the reset vector

which woke it up (see Figure 26 ).

• When exiting Active-Halt mode by means of an interrupt, the CPU immediately

resumes operation by servicing the interrupt vector which woke it up (see Figure 26

).

When entering Active-Halt mode, the I bit in the CC register is cleared to enable interrupts.

Therefore, if an interrupt is pending, the MCU wakes up immediately.

In Active-halt mode, only the main oscillator and the selected timer counter (LT/AT) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator).

Caution: As soon as Active-halt is enabled, executing a HALT instruction while the Watchdog is active does not generate a Reset if the WDGHalt bit is reset.

Obsolete Product(s) - Obsolete Product(s) mode.

Figure 25. Active-halt timing overview

RUN

ACTIVE

HALT

256 OR 512 CPU

CYCLE DELAY

1)

HALT

INSTRUCTION

[Active Halt Enabled]

RESET

OR

INTERRUPT

RUN

FETCH

VECTOR

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ST7LITEU05 ST7LITEU09 Power saving modes

Figure 26. Active-halt mode flowchart

HALT INSTRUCTION

(Active Halt enabled)

OSCILLATOR

PERIPHERALS

CPU

I BIT

2)

ON

OFF

OFF

0

N

RESET

Y

N

INTERRUPT 3)

Y OSCILLATOR

PERIPHERALS

CPU

I BIT

2)

ON

OFF

ON

X 4)

256 OR 512 CPU CLOCK

CYCLE DELAY

OSCILLATOR

PERIPHERALS

CPU

I BITS

ON

ON

ON

X 4)

FETCH RESET VECTOR

OR SERVICE INTERRUPT

1. This delay occurs only if the MCU exits Active-Halt mode by means of a Reset.

2. Peripherals clocked with an external clock source can still be active.

3. Only the Lite Timer RTC and AT Timer interrupts can exit the MCU from Active-halt mode.

4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.

The Halt mode is the lowest power consumption mode of the MCU. It is entered by executing the ‘Halt’ instruction when active halt mode is disabled.

The MCU can exit Halt mode on reception of either a specific interrupt (see

Table 9:

Interrupt mapping

) or a Reset. When exiting Halt mode by means of a Reset or an interrupt, the main oscillator is immediately turned on and the 256 or 512 CPU cycle delay is used to stabilize it. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see

Figure 28 ).

When entering Halt mode, the I bit in the CC register is forced to 0 to enable interrupts.

Therefore, if an interrupt is pending, the MCU wakes immediately.

including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator).

The compatibility of Watchdog operation with Halt mode is configured by the “WDGHALT” option bit of the option byte. The HALT instruction when executed while the Watchdog

system is enabled, can generate a watchdog Reset (see Section 15.1: Option bytes

for more details).

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Power saving modes ST7LITEU05 ST7LITEU09

Figure 27. Halt timing overview

RUN HALT

256 OR 512

CPU CYCLE DELAY

HALT

INSTRUCTION

[Active Halt disabled]

RESET

OR

INTERRUPT

RUN

FETCH

VECTOR

Figure 28. Halt mode flowchart

HALT INSTRUCTION

(Active Halt disabled)

ENABLE

0

WATCHDOG

DISABLE

WDGHALT 1)

1

WATCHDOG

RESET

OSCILLATOR

PERIPHERALS

CPU

I BIT

2)

OFF

OFF

OFF

0

N

N

RESET

Y

INTERRUPT 3)

Y OSCILLATOR

PERIPHERALS

CPU

I BIT

ON

OFF

ON

X 4)

256 OR 512 CPU CLOCK

CYCLE DELAY 5)

OSCILLATOR

PERIPHERALS

CPU

I BITS

ON

ON

ON

X 4)

FETCH RESET VECTOR

OR SERVICE INTERRUPT

1. WDGHALT is an option bit. See option byte section for more details.

2. Peripheral clocked with an external clock source can still be active.

3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to

Table 9: Interrupt mapping for more details.

Obsolete Product(s) - Obsolete Product(s)

5. The CPU clock must be switched to 1 MHz (RC/8) or AWU RC before entering Halt mode.

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ST7LITEU05 ST7LITEU09 Power saving modes

Halt mode recommendations

• Make sure that an external event is available to wake up the microcontroller from Halt mode.

• When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition.

• For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure.

• The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value

0x8E from memory. For example, avoid defining a constant in ROM with the value

0x8E.

• As the HALT instruction clears the I bit in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction.

This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wakeup event (reset or external interrupt).

9.5 Auto-wakeup from Halt mode

Auto-wake up from Halt (AWUFH) mode is similar to Halt mode with the addition of a specific internal RC oscillator for wakeup (Auto-wakeup from Halt oscillator) which replaces the main clock which was active before entering Halt mode. Compared to Active-halt mode,

AWUFH has lower power consumption (the main clock is not kept running), but there is no accurate realtime clock available.

It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR register has been set.

Figure 29. AWUFH mode block diagram

AWU RC oscillator f

AWU_RC to 8-bit Timer input capture

/64 divider

AWUFH prescaler/1 .. 255

AWUFH interrupt

(ei0 source)

Obsolete Product(s) - Obsolete Product(s) register, the AWU RC oscillator provides a clock signal (f

AWU_RC

). Its frequency is divided by a fixed divider and a programmable prescaler controlled by the AWUPR register. The output of this prescaler provides the delay time. When the delay has elapsed, the following actions are performed:

• the AWUF flag is set by hardware,

• an interrupt wakes-up the MCU from Halt mode,

• the main oscillator is immediately turned on and the 256 or 512 CPU cycle delay is used to stabilize it.

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After this start-up delay, the CPU resumes operation by servicing the AWUFH interrupt. The

AWU flag and its associated interrupt are cleared by software reading the AWUCSR register.

To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated by measuring the clock frequency f

AWU_RC and then calculating the right prescaler value.

Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in Run f mode. This connects f

AWU_RC

AWU_RC

to be measured

to the input capture of the 8-bit lite timer, allowing the using the main oscillator clock as a reference timebase.

Similarities with Halt mode

The following AWUFH mode behaviour is the same as normal Halt mode:

• The MCU can exit AWUFH mode by means of any interrupt with exit from Halt

capability or a reset (see Section 9.4: Active-halt and Halt modes ).

• When entering AWUFH mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.

• In AWUFH mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. None of the peripherals are clocked except those which get their clock supply from another clock generator (such as an external or auxiliary oscillator like the AWU oscillator).

• The compatibility of watchdog operation with AWUFH mode is configured by the

WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction when executed while the watchdog system is enabled, can generate a watchdog Reset.

RUN MODE

Figure 30. AWUF Halt timing diagram t

AWU

HALT MODE 256 or 512 t

CPU

RUN MODE f

CPU f

AWU_RC

Clear by software

AWUFH interrupt

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Figure 31. AWUFH mode flowchart

HALT INSTRUCTION

(Active-Halt disabled)

(AWUCSR.AWUEN=1)

ENABLE

0

WDGHALT 1)

1

WATCHDOG

RESET

WATCHDOG

DISABLE

AWU RC OSC ON

MAIN OSC

PERIPHERALS

CPU

I[1:0] BITS

2)

OFF

OFF

OFF

10

N

INTERRUPT 3)

Y

N

RESET

Y

AWU RC OSC OFF

MAIN OSC

PERIPHERALS

CPU

I[1:0] BITS

ON

OFF

ON

XX 4)

256 OR 512 CPU CLOCK

CYCLE DELAY

AWU RC OSC OFF

MAIN OSC

PERIPHERALS

ON

CPU

I[1:0] BITS

ON

ON

XX 4)

FETCH RESET VECTOR

OR SERVICE INTERRUPT

1. WDGHALT is an option bit. See option byte section for more details.

2. Peripheral clocked with an external clock source can still be active.

3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to

Table 9: Interrupt mapping for more details.

4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.

Reset value: 0000 0000 (00h)

7

0 0 0 0

Read / Write

0 AWUF AWUM

0

AWUEN

Bits 7:3 = Reserved

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Note:

Bit 2 = AWUF Auto Wake Up flag

This bit is set by hardware when the AWU module generates an interrupt and cleared by software on reading AWUCSR. Writing to this bit does not change its value.

0: No AWU interrupt occurred

1: AWU interrupt occurred

Bit 1 = AWUM Auto Wake Up Measurement bit

This bit enables the AWU RC oscillator and connects its output to the input capture of the 8-bit Lite timer. This allows the timer to be used to measure the AWU RC oscillator dispersion and then compensate this dispersion by providing the right value in the

AWUPRE register.

0: Measurement disabled

1: Measurement enabled

Bit 0 = AWUEN Auto Wake Up From Halt Enabled bit

This bit enables the Auto Wake Up From Halt feature: once Halt mode is entered, the

AWUFH wakes up the microcontroller after a time delay dependent on the AWU prescaler value. It is set and cleared by software.

0: AWUFH (Auto Wake Up From Halt) mode disabled

1: AWUFH (Auto Wake Up From Halt) mode enabled

Whatever the clock source, this bit should be set to enable the AWUFH mode once the

HALT instruction has been executed.

AWUFH prescaler register (AWUPR)

Reset value: 1111 1111 (FFh)

7 0

AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0

Read / Write

Bits 7:0= AWUPR[7:0] Auto wakeup prescaler

These 8 bits define the AWUPR Dividing factor (see Table 16

).

Table 16. Configuring the dividing factor

AWUPR[7:0 ] Dividing

00h

01h

Forbidden

Obsolete Product(s) - Obsolete Product(s)

...

...

FEh 254

FFh 255

In AWU mode, the time during which the MCU stays in Halt mode, t

AWU equation below. See also

Figure 30 on page 60

.

, is given by the

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Note: t

AWU

= × f

AWURC

+ t

RCSTRT

The AWUPR prescaler register can be programmed to modify the time during which the

MCU stays in Halt mode before waking up automatically.

If 00h is written to AWUPR, depending on the product, an interrupt is generated immediately after a HALT instruction, or the AWUPR remains unchanged.

Table 17. AWU register map and reset values

Address

(Hex.)

0049h

004Ah

Register label

AWUPR

Reset value

AWUCSR

Reset value

7

AWUPR7

1

AWUPR6

1

AWUPR5

1

AWUPR4

1

AWUPR3

1

AWUPR2

1

AWUPR1

1

AWUPR0

1

0

6

0

5

0

4

0

3

0

2

AWUF

1

AWUM

0

AWUEN

Obsolete Product(s) - Obsolete Product(s)

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10.1 Introduction

The I/O port offers different functional modes:

• transfer of data through digital inputs and outputs and for specific pins:

• external interrupt generation

• alternate signal input/output for the on-chip peripherals.

An I/O port contains up to 6 pins. Each pin (except PA3/RESET) can be programmed independently as digital input (with or without interrupt generation) or digital output.

Each port has 2 main registers:

• Data register (DR)

• Data direction register (DDR) and one optional register:

• Option register (OR)

Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the

DR register.

The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is shown in

Figure 32 .

The input configuration is selected by clearing the corresponding DDR register bit.

In this case, reading the DR register returns the digital value applied to the external I/O pin.

Different input modes can be selected by software through the OR register.

Note: 1 Writing the DR register modifies the latch value but does not affect the pin status.

2 PA3 cannot be configured as input.

Obsolete Product(s) - Obsolete Product(s)

When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU.

Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the EICR register.

Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several I/O interrupt pins on the same interrupt vector are selected simultaneously, they are logically combined. For this reason if one of the interrupt pins is tied low, it may mask the others.

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External interrupts are hardware interrupts. Fetching the corresponding interrupt vector automatically clears the request latch. Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts.

Spurious interrupts

When enabling/disabling an external interrupt by setting/resetting the related OR register bit, a spurious interrupt is generated if the pin level is low and its edge sensitivity includes falling/rising edge. This is due to the edge detector input which is switched to '1' when the external interrupt is disabled by the OR register.

To avoid this unwanted interrupt, a "safe" edge sensitivity (rising edge for enabling and falling edge for disabling) has to be selected before changing the OR register bit and configuring the appropriate sensitivity again.

Caution: In case a pin level change occurs during these operations (asynchronous signal input), as interrupts are generated according to the current sensitivity, it is advised to disable all interrupts before and to reenable them after the complete previous sequence in order to avoid an external interrupt occurring on the unwanted edge.

This corresponds to the following steps:

1.

To enable an external interrupt: a) set the interrupt mask with the SIM instruction (in cases where a pin level change could occur) b) select rising edge c) enable the external interrupt through the OR register d) select the desired sensitivity if different from rising edge e) reset the interrupt mask with the RIM instruction (in cases where a pin level change could occur)

2. To disable an external interrupt: a) set the interrupt mask with the SIM instruction SIM (in cases where a pin level change could occur) b) select falling edge c) disable the external interrupt through the OR register d) select rising edge

The output configuration is selected by setting the corresponding DDR register bit. In this

Obsolete Product(s) - Obsolete Product(s)

Two different output modes can be selected by software through the OR register: Output push-pull and open-drain.

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Note:

ST7LITEU05 ST7LITEU09

DR

0

1

Table 18. DR value and output pin status

Push-pull Open-drain

V

SS

V

DD

Vss

Floating

When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output.

Note:

When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming under the following conditions:

• When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral).

• When the signal is going to an on-chip peripheral, the I/O pin must be configured in floating input mode. In this case, the pin state is also digitally readable by addressing the DR register.

Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input.

When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.

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REGISTER

ACCESS

DR

Figure 32. I/O port general block diagram

ALTERNATE

OUTPUT

1

V

DD

0

ALTERNATE

ENABLE

P-BUFFER

(see table below)

PULL-UP

(see table below)

V

DD

DDR

PULL-UP

CONDITION

PAD

OR

If implemented

OR SEL

N-BUFFER

DDR SEL

DIODES

(see table below)

ANALOG

INPUT

DR SEL

CMOS

SCHMITT

TRIGGER 1

0

ALTERNATE

INPUT

EXTERNAL

INTERRUPT

SOURCE (ei x

)

POLARITY

SELECTION

FROM

OTHER

BITS

Table 19. I/O port mode options

(1)

Configuration mode Pull-up P-buffer to V

DD

Diodes to V

SS

Input

Floating with/without interrupt Off

On

Off

Pull-up with/without interrupt

Push-pull On

Output

Open drain (logic level)

Off

Off

1. Off means implemented not activated, On means implemented and activated.

On On

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PAD

Table 20. I/O port configurations

Hardware configuration

V

DD

DR REGISTER ACCESS

R

PU

PULL-UP

CONDITION

DR

REGISTER

W

DATA BUS

R

ALTERNATE INPUT

EXTERNAL INTERRUPT

SOURCE (ei x

)

POLARITY

SELECTION

ANALOG INPUT

DR REGISTER ACCESS

V

DD

R

PU

INTERRUPT

CONDITION

FROM

OTHER

PINS

PAD

DR

REGISTER

R/W

DATA BUS

PAD

V

DD

R

PU

ALTERNATE

ENABLE

ALTERNATE

OUTPUT

DR REGISTER ACCESS

DR

REGISTER

R/W

DATA BUS

ALTERNATE

ENABLE

ALTERNATE

OUTPUT

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register reads the alternate function output status.

2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.

Caution: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts.

When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input.

It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin.

Caution: The analog input voltage level must be within the limits stated in the absolute maximum ratings.

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10.3 Unused I/O pins

Unused I/O pins must be connected to fixed voltage levels. Refer to Section 13.8: I/O port pin characteristics .

Wait

Halt

Table 21. Effect of low-power modes on I/O ports

Mode Description

No effect on I/O ports. External interrupts cause the device to exit from Wait mode.

No effect on I/O ports. External interrupts cause the device to exit from Halt mode.

10.5 Interrupts

The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the interrupt mask in the CC register is not active

(RIM instruction).

Interrupt event

Table 22. Description of interrupt events

Event flag

Enable control bit

Exit from

Wait

External interrupt on selected external event

-

DDRx

ORx

Yes

Exit from

Halt

Yes

10.6 I/O port implementation

The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain.

Switching these I/O ports from one state to another should be done in a sequence that

prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 33 .

Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation.

Figure 33. Interrupt I/O port state transitions Obsolete Product(s) - Obsolete Product(s)

01 00 10 11

INPUT floating/pull-up interrupt

INPUT floating

(reset state)

OUTPUT open-drain

OUTPUT push-pull

XX = DDR, OR

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The I/O port register configurations are summarised in the following table:

Table 23. Port configuration

Input (DDR=0) Output (DDR=1)

Port Pin name

OR = 0 OR = 1 OR = 0 OR = 1

Port A

PA0:2,

PA4:5

(1)

PA3 (2) floating pull-up interrupt

(1) open drain push-pull

open drain push-pull

1. IS4[1:0] = 01 is the only safe configuration to avoid spurious interrupt in Halt and AWUFH modes. Refer to

EICR2 description on

Section 8.3.2: External interrupt control register 2 (EICR2)

.

2. After reset, to configure PA3 as a general purpose output, the application has to program the MUXCR0 and MUXCR1 registers. See

Section 7.5: Register description .

Address

(Hex.)

0000h

0001h

0002h

Register

Label

Table 24. I/O port register map and reset values

7 6 5 4 3 2

PADR

Reset value

PADDR

Reset value

PAOR

Reset value

MSB

0

MSB

0

MSB

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

1

0

0

1

0

LSB

0

LSB

0

LSB

0

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11.1 Lite timer (LT)

11.1.1 Introduction

The Lite Timer can be used for general-purpose timing functions. It is based on a freerunning 13-bit upcounter with two software-selectable timebase periods, an 8-bit input capture register and watchdog function.

• Real-time clock

– 13-bit upcounter

– 1 ms or 2 ms timebase period (@ 8 MHz f

OSC

)

– Maskable timebase interrupt

• Input capture

– 8-bit input capture register (LTICR)

– Maskable interrupt with wakeup from Halt mode capability

• Watchdog

– Enabled by hardware or software (configurable by option byte)

– Optional reset on HALT instruction (configurable by option byte)

– Automatically resets the device unless disable bit is refreshed

– Software reset (forced watchdog reset)

– Watchdog reset status flag

Obsolete Product(s) - Obsolete Product(s)

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OSC

Figure 34. Lite timer block diagram f

LTIMER

To 12-bit AT TImer f

WDG

WATCHDOG

13-bit UPCOUNTER

/2 f

LTIMER

1

Timebase f

(@ 8 MHz

OSC

)

WATCHDOG RESET

LTICR

8 MSB

LTIC

8-bit

INPUT CAPTURE

REGISTER

LTCSR

7

ICIE ICF TB TBIE TBF

WDG

RF

WDGE WDGD

0

LTTB INTERRUPT REQUEST

LTIC INTERRUPT REQUEST

The value of the 13-bit counter cannot be read or written by software. After an MCU reset, it starts incrementing from 0 at a frequency of f

OSC counter rolls over from 1F39h to 00h. If f

OSC

. A counter overflow event occurs when the

= 8 MHz, then the time period between two counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the

LTCSR register.

When the timer overflows, the TBF bit is set by hardware and an interrupt request is generated if the TBIE is set. The TBF bit is cleared by software reading the LTCSR register.

Watchdog

The watchdog is enabled using the WDGE bit. The normal Watchdog timeout is 2ms (@ fosc = 8 MHz ), after which it then generates a reset.

To prevent this watchdog reset occuring, software must set the WDGD bit. The WDGD bit

Obsolete Product(s) - Obsolete Product(s)

If the watchdog is not enabled immediately after reset, the first watchdog timeout is shorter than 2ms, because this period is counted starting from reset. Moreover, if a 2ms period has already elapsed after the last MCU reset, the watchdog reset takes place as soon as the

WDGE bit is set. For these reasons, it is recommended to enable the Watchdog immediately after reset or else to set the WDGD bit before the WGDE bit so a watchdog reset does not occur for at least 2 ms.

Note: Software can use the timebase feature to set the WDGD bit at 1 or 2 ms intervals.

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A Watchdog reset can be forced at any time by setting the WDGRF bit. To generate a forced watchdog reset, first watchdog has to be activated by setting the WDGE bit and then the

WDGRF bit has to be set.

The WDGRF bit also acts as a flag, indicating that the Watchdog was the source of the reset. It is automatically cleared after it has been read.

Caution: When the WDGRF bit is set, software must clear it, otherwise the next time the watchdog is enabled (by hardware or software), the microcontroller is immediately reset.

If Hardware Watchdog is selected by option byte, the watchdog is always active and the

WDGE bit in the LTCSR is not used.

Refer to the option byte description in the "device configuration and ordering information" section.

Using Halt mode with the watchdog (option)

If the Watchdog reset on Halt option is not selected by option byte, the Halt mode can be used when the watchdog is enabled.

In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the Lite

Timer stops counting and is no longer able to generate a Watchdog reset until the microcontroller receives an external interrupt or a reset.

If an external interrupt is received, the WDG restarts counting after 256 or 512 CPU clocks.

If a reset is generated, the Watchdog is disabled (reset state).

If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT instruction), it is recommended before executing the HALT instruction to refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.

Figure 35. Watchdog timing diagram

HARDWARE CLEARS

WDGD BIT t

WDG

(2ms @ 8 MHz f

OSC

) f

WDG

WDGD BIT

INTERNAL

WATCHDOG

RESET

SOFTWARE SETS

Input capture

The 8-bit input capture register is used to latch the free-running upcounter after a rising or falling edge is detected on the LTIC pin. When an input capture occurs, the ICF bit is set and the LTICR register contains the MSB of the free-running upcounter. An interrupt is generated if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register.

The LTICR is a read only register and always contains the data from the last input capture.

Input capture is inhibited if the ICF bit is set.

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Table 25. Description of low-power modes

Mode Description

Wait

Active-Halt

Halt

No effect on Lite timer

No effect on Lite timer

Lite timer stops counting

11.1.6 Interrupts

Interrupt event

Timebase Event

IC Event

Event flag

TBF

ICF

Table 26. Interrupt events

Enable control bit

Exit from

Wait

TBIE

ICIE

Yes

Yes

Exit from

Halt

No

No

Exit from

Active-Halt

Yes

No

Note: The TBF and ICF interrupt events are connected to separate interrupt vectors (see

Interrupts chapter).

They generate an interrupt if the enable bit is set in the LTCSR register and the interrupt mask in the CC register is reset (RIM instruction).

Figure 36. Input capture timing diagram

125 ns

(@ 8 MHz f

OSC

) f

CPU f

OSC

13-bit COUNTER 0001h 0002h 0003h 0004h 0005h 0006h 0007h

CLEARED

BY S/W

READING

LTIC REGISTER

LTIC PIN

ICF FLAG

LTICR REGISTER xxh 04h 07h Obsolete Product(s) - Obsolete Product(s) t

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Lite timer control/status register (LTCSR)

Reset Value: 0000 0x00 (0xh)

7

ICIE ICF TB TBIE TBF

Read / Write

WDGR WDGE

0

WDGD

Note:

Bit 7 = ICIE Interrupt Enable.

This bit is set and cleared by software.

0: Input Capture (IC) interrupt disabled

1: Input Capture (IC) interrupt enabled

Bit 6 = ICF Input Capture Flag.

This bit is set by hardware and cleared by software by reading the LTICR register.

Writing to this bit does not change the bit value.

0: No input capture

1: An input capture has occurred

After an MCU reset, software must initialise the ICF bit by reading the LTICR register

Bit 5 = TB Timebase period selection.

This bit is set and cleared by software.

0: Timebase period = t

OSC

* 8000 (1 ms @ 8 MHz)

1: Timebase period = t

OSC

* 16000 (2 ms @ 8 MHz)

Bit 4 = TBIE Timebase Interrupt enable .

This bit is set and cleared by software.

0: Timebase (TB) interrupt disabled

1: Timebase (TB) interrupt enabled

Bit 3 = TBF Timebase Interrupt Flag .

This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect.

0: No counter overflow

1: A counter overflow has occurred

Bit 2 = WDGRF Force Reset/ Reset Status Flag

Obsolete Product(s) - Obsolete Product(s) hardware when a watchdog reset occurs and cleared by hardware or by software. It is cleared by hardware only when an LVD reset occurs. It can be cleared by software after a read access to the LTCSR register.

0: No watchdog reset occurred.

1: Force a watchdog reset (write), or, a watchdog reset occurred (read).

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Bit 1 = WDGE Watchdog Enable

This bit is set and cleared by software.

0: Watchdog disabled

1: Watchdog enabled

Bit 0 = WDGD Watchdog Reset Delay

This bit is set by software. It is cleared by hardware at the end of each t

WDG

period.

0: Watchdog reset not delayed

1: Watchdog reset delayed

Lite Timer Input Capture register (LTICR)

Reset value: 0000 0000 (00h)

7

ICR7 ICR6 ICR5 ICR4 ICR3

Read only

ICR2 ICR1

0

ICR0

Bits 7:0 = ICR[7:0] Input capture value

These bits are read by software and cleared by hardware after a reset. If the ICF bit in the

LTCSR is cleared, the value of the 8-bit up-counter is captured when a rising or falling edge occurs on the LTIC pin.

Address

(Hex.)

0B

0C

Table 27. Lite timer register map and reset values

Register label 7 6 5 4 3 2

LTCSR

Reset value

LTICR

Reset value

ICIE

0

ICR7

0

ICF

0

ICR6

0

TB

0

ICR5

0

TBIE

0

ICR4

0

1 0

TBF

0

ICR3

0

WDGRF x

ICR2

0

WDGE

0

ICR1

0

WDGD

0

ICR0

0

Obsolete Product(s) - Obsolete Product(s)

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11.2 12-bit autoreload timer (AT)

11.2.1 Introduction

The 12-bit Autoreload Timer can be used for general-purpose timing functions. It is based on a free-running 12-bit upcounter with a PWM output channel.

• 12-bit upcounter with 12-bit autoreload register (ATR)

• Maskable overflow interrupt

• PWM signal generator

• Frequency range 2 kHz - 4 MHz (@ 8 MHz f

CPU

)

– Programmable duty-cycle

– Polarity control

– Maskable compare interrupt

• Output compare function

0

7 ATCSR

0

Figure 37. Block diagram

0 CK1 CK0

0

OVF OVFIE CMPIE

OVF INTERRUPT

REQUEST f

LTIMER

(1 ms timebase

@ 8 MHz) f

CPU

DCR0H

Preload

DCR0L

Preload on OVF Event

IF OE0=1

12-BIT DUTY CYCLE VALUE (shadow)

CMP INTERRUPT

REQUEST

CMPF0 f

COUNTER

CNTR

12-BIT UPCOUNTER

Update on OVF Event

ATR

12-BIT AUTORELOAD VALUE

OE0 bit

OE0 bit

CMPF0 bit

0

1

COMP-

PARE

OP0 bit f

PWM

POL-

ARITY

PWM0

Obsolete Product(s) - Obsolete Product(s)

Note:

PWM mode

This mode allows a pulse width modulated signals to be generated on the PWM0 output pin with minimum core processing overhead. The PWM0 output signal can be enabled or disabled using the OE0 bit in the PWMCR register. When this bit is set the PWM I/O pin is configured as output push-pull alternate function.

CMPF0 is available in PWM mode (see Section : PWM0 control/status register

(PWM0CSR) ).

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PWM frequency and duty cycle

Note:

The PWM signal frequency (f

PWM value.

) is controlled by the counter period and the ATR register f

PWM

= f

COUNTER

/ (4096 - ATR)

Following the above formula, if f

CPU

is 8 MHz, the maximum value of f

PWM

is 4 MHz (ATR register value = 4094), and the minimum value is 2 kHz (ATR register value = 0).

The maximum value of ATR is 4094 because it must be lower than the DCR value which must be 4095 in this case.

At reset, the counter starts counting from 0.

Software must write the duty cycle value in the DCR0H and DCR0L preload registers. The

DCR0H register must be written first. See caution below.

When a upcounter overflow occurs (OVF event), the ATR value is loaded in the upcounter, the preloaded Duty cycle value is transferred to the Duty Cycle register and the PWM0 signal is set to a high level. When the upcounter matches the DCRx value the PWM0 signals is set to a low level. To obtain a signal on the PWM0 pin, the contents of the DCR0 register must be greater than the contents of the ATR register.

The polarity bit can be used to invert the output signal.

The maximum available resolution for the PWM0 duty cycle is:

Note:

Resolution = 1 / (4096 - ATR)

To get the maximum resolution (1/4096), the ATR register must be 0. With this maximum resolution and assuming that DCR=ATR, a 0% or 100% duty cycle can be obtained by changing the polarity .

Caution: As soon as the DCR0H is written, the compare function is disabled and starts only when the

DCR0L value is written. If the DCR0H write occurs just before the compare event, the signal on the PWM output may not be set to a low level. In this case, the DCRx register should be updated just after an OVF event. If the DCR and ATR values are close, then the DCRx register shouldbe updated just before an OVF event, in order not to miss a compare event and to have the right signal applied on the PWM output.

Figure 38. PWM function

4095

DUTY CYCLE

REGISTER

(DCR0)

000

WITH OE0=1

AND OP0=0

WITH OE0=1

AND OP0=1 t

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Figure 39. PWM signal example f

COUNTER

COUNTER

DCR0=FFEh

FFDh FFEh

ATR= FFDh

FFFh FFDh FFEh FFFh FFDh FFEh t

Note:

Output compare mode

To use this function, the OE bit must be 0, otherwise the compare is done with the shadow register instead of the DCRx register. Software must then write a 12-bit value in the DCR0H and DCR0L registers. This value is loaded immediately (without waiting for an OVF event).

The DCR0H must be written first, the output compare function starts only when the DCR0L value is written.

When the 12-bit upcounter (CNTR) reaches the value stored in the DCR0H and DCR0L registers, the CMPF0 bit in the PWM0CSR register is set and an interrupt request is generated if the CMPIE bit is set.

The output compare function is only available for DCRx values other than 0 (reset value).

Caution: At each OVF event, the DCRx value is written in a shadow register, even if the DCR0L value has not yet been written (in this case, the shadow register contains the new DCR0H value and the old DCR0L value), then:

- If OE=1 (PWM mode): the compare is done between the timer counter and the shadow register (and not DCRx)

- if OE=0 (OCMP mode): the compare is done between the timer counter and DCRx. There is no PWM signal.

The compare between DCRx or the shadow register and the timer counter is locked until

DCR0L is written.

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Table 28. Description of low-power modes

Mode Description

Slow

Wait

Active-halt

Halt

The input frequency is divided by 32

No effect on AT timer

AT timer halted except if CK0=1, CK1=0 and OVFIE=1

AT timer halted

11.2.5 Interrupts

Interrupt event

Overflow Event

CMP Event

(1)

Event flag

OVF

CMPFx

Table 29. Interrupt events

Enable control bit

Exit from

Wait

OVFIE

CMPIE

Yes

Yes

Exit from

Halt

No

No

Exit from

Active-halt

Yes

No

(2)

1. The interrupt events are connected to separate interrupt vectors (see Interrupts chapter).

They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt mask in the CC register is reset

(RIM instruction).

2. Only if CK0=1 and CK1=0

Timer control status register (ATCSR)

Reset value: 0000 0000 (00h)

7

0 0 0 CK1 CK0

Read/write

OVF OVFIE

0

CMPIE

Bits 7:5 = Reserved, must be kept cleared.

Bits 4:3 = CK[1:0] Counter Clock Selection.

These bits are set and cleared by software and cleared by hardware after a reset. They select the clock frequency of the counter.

Obsolete Product(s) - Obsolete Product(s)

Table 30. Counter clock selection

Counter clock selection CK1 CK0

OFF f

LTIMER

(1 ms timebase @ 8 MHz) f

CPU

Reserved

1

1

0

0

0

1

0

1

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Bit 2 = OVF Overflow flag.

This bit is set by hardware and cleared by software by reading the ATCSR register. It indicates the transition of the counter from FFFh to ATR value.

0: No counter overflow occurred

1: Counter overflow occurred

Caution: When set, the OVF bit stays high for 1 f

COUNTER selection) after it has been cleared by software.

cycle (up to 1ms depending on the clock

Bit 1 = OVFIE Overflow interrupt enable.

This bit is read/write by software and cleared by hardware after a reset.

0: OVF interrupt disabled

1: OVF interrupt enabled

Bit 0 = CMPIE Compare interrupt enable .

This bit is read/write by software and clear by hardware after a reset. It allows to mask the interrupt generation when CMPF bit is set.

0: CMPF interrupt disabled

1: CMPF interrupt enabled

Counter register high (CNTRH)

Reset Value: 0000 0000 (00h)

15

0 0 0 0 CN11

Read only

CN10 CN9

8

CN8

Counter register low (CNTRL)

Reset Value: 0000 0000 (00h)

7

CN7 CN6 CN5 CN4 CN3

Read only

Bits 15:12 = Reserved, must be kept cleared.

CN2 CN1

0

CN0

This 12-bit register is read by software and cleared by hardware after a reset. The counter is incremented continuously as soon as a counter clock is selected. To obtain the 12-bit value, software should read the counter value in two consecutive read operations. As there is no latch, it is recommended to read LSB first. In this case,

CNTRH can be incremented between the two read operations and to have an accurate result when f timer

= f

CPU

, special care must be taken when CNTRL values close to FFh are read.

When a counter overflow occurs, the counter restarts from the value specified in the

ATR register.

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Auto reload register (ATRH)

Reset value: 0000 0000 (00h)

15

0 0 0 0 ATR11

Read/Write

ATR10 ATR9

8

ATR8

Auto reload register (ATRL)

Reset value: 0000 0000 (00h)

7

ATR7 ATR6 ATR5 ATR4 ATR3

Read/Write

ATR2 ATR1

0

ATR0

Bits 15:12 = Reserved, must be kept cleared.

Bits 11:0 = ATR[11:0] Autoreload Register.

This is a 12-bit register which is written by software. The ATR register value is automatically loaded into the upcounter when an overflow occurs. The register value is used to set the PWM frequency.

PWM0 duty cycle register high (DCR0H)

Reset value: 0000 0000 (00h)

15

0 0 0 0 DCR11

Read/Write

DCR10 DCR9

8

DCR8

PWM0 duty cycle register low (DCR0L)

Reset Value: 0000 0000 (00h)

7

DCR7 DCR6 DCR5 DCR4 DCR3

Read/Write

DCR2 DCR1

0

DCR0

Bits 11:0 = DCR[11:0] PWMx duty cycle value

This 12-bit value is written by software. The high register must be written first.

In PWM mode (OE0=1 in the PWMCR register) the DCR[11:0] bits define the duty cycle of the PWM0 output signal (see

Figure 38

). In Output Compare mode, (OE0=0 in the

PWMCR register) they define the value to be compared with the 12-bit upcounter value.

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PWM0 control/status register (PWM0CSR)

Reset Value: 0000 0000 (00h)

7

0 0 0 0 0

Read/Write

0 OP0

0

CMPF0

Bit 7:2 = Reserved, must be kept cleared.

Bit 1 = OP0 PWM0 output polarity.

This bit is read/write by software and cleared by hardware after a reset. This bit selects the polarity of the PWM0 signal.

0: The PWM0 signal is not inverted.

1: The PWM0 signal is inverted.

Bit 0 = CMPF0 PWM0 Compare Flag.

This bit is set by hardware and cleared by software by reading the PWM0CSR register.

It indicates that the upcounter value matches the DCR0 register value.

0: Upcounter value does not match DCR value.

1: Upcounter value matches DCR value.

PWM output control register (PWMCR)

Reset Value: 0000 0000 (00h)

7

0 0 0 0

Read/Write

0 0 0

0

OE0

Bits 7:1 = Reserved, must be kept cleared.

Bit 0 = OE0 PWM0 Output enable .

This bit is set and cleared by software.

0: PWM0 output Alternate Function disabled (I/O pin free for general purpose I/O)

1: PWM0 output enabled

Table 31. Register map and reset values

Address Register label

7 6 5 4 3 2 1 0

(Hex.)

Obsolete Product(s) - Obsolete Product(s)

Reset value

0 0 0

CK1

0

CK0

0

OVF

0

OVFIE

0

CMPIE

0

0E

CNTRH

Reset

Value

0 0 0 0

CN11

0

CN10

0

CN9

0

CN8

0

0F

10

CNTRL

Reset value

ATRH

Reset

Value

CN7

0

0

CN6

0

0

CN5

0

0

CN4

0

0

CN3

0

ATR11

0

CN2

0

ATR10

0

CN1

0

ATR9

0

CN0

0

ATR8

0

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Address

(Hex.)

11

12

13

17

18

Table 31. Register map and reset values (continued)

Register label

7 6 5 4 3 2

ATRL

Reset

Value

PWMCR

Reset

Value

PWM0CSR

Reset

Value

DCR0H

Reset

Value

DCR0L

Reset

Value

ATR7

0

0

0

0

DCR7

0

ATR6

0

0

0

0

DCR6

0

ATR5

0

0

0

0

DCR5

0

ATR4

0

0

0

0

DCR4

0

ATR3

0

0

0

DCR11

0

DCR10

0

DCR3

0

ATR2

0

0

0

DCR2

0

1

ATR1

0

0

OP

0

DCR9

0

DCR1

0

0

ATR0

0

OE0

0

CMPF0

0

DCR8

0

DCR0

0

11.3 10-bit A/D converter (ADC)

11.3.1 Introduction

The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 5 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 5 different sources.

The result of the conversion is stored in a 10-bit Data Register. The A/D converter is controlled through a Control/Status Register.

• 10-bit conversion

• Up to 5 channels with multiplexed input

Obsolete Product(s) - Obsolete Product(s)

• Data register (DR) which contains the results

• Conversion complete status flag

• On/off bit (to reduce consumption)

The block diagram is shown in

Figure 40

.

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Analog power supply

V

DD

and V

SS

are the high and low level reference voltage pins.

Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines.

f

CPU

DIV 2

0

1

Figure 40. ADC block diagram

DIV 4

1

0

SLOW bit f

ADC

AIN0

AIN1

AINx

EOC SPEED ADON 0 0 CH2 CH1 CH0 ADCCSR

3

HOLD CONTROL

R

ADC

ANALOG

MUX

ANALOG TO DIGITAL

CONVERTER

C

ADC

ADCDRH D9 D8 D7 D6 D5 D4 D3 D2

ADCDRL 0 0 0 0 SLOW 0 D1 D0

Digital A/D conversion result

The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not.

If the input voltage (V

AIN

) is greater than V

DD

(high-level voltage reference) then the conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without overflow indication).

If the input voltage (V

AIN

) is lower than V

SS

(low-level voltage reference) then the conversion

Obsolete Product(s) - Obsolete Product(s)

The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH and ADCDRL registers. The accuracy of the conversion is described in the Electrical

Characteristics Section.

R

AIN

is the maximum recommended impedance for an analog input signal. If the impedance is too high, there is a loss of accuracy due to leakage and sampling not being completed in the alloted time.

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A/D conversion phases

The A/D conversion is based on two conversion phases:

1.

Sample capacitor loading [duration: t

During this phase, the V

AIN sample capacitor.

SAMPLE

]

input voltage to be measured is loaded into the C

ADC

2. A/D conversion [duration: t

HOLD

]

During this phase, the A/D conversion is computed (8 successive approximations cycles) and the C

ADC

sample capacitor is disconnected from the analog input pin to get the optimum analog to digital conversion accuracy.

t

The total conversion time:

CONV = t

SAMPLE

+ t

HOLD

While the ADC is on, these two phases are continuously repeated.

At the end of each conversion, the sample capacitor is kept loaded with the previous measurement load. The advantage of this behaviour is that it minimizes the current consumption on the analog pin in case of single input channel measurement.

A/D conversion

The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the “I/O ports” chapter. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input.

In the ADCCSR register:

• Select the CS[2:0] bits to assign the analog channel to convert.

ADC conversion mode

In the ADCCSR register:

Set the ADON bit to enable the A/D converter and to start the conversion. From this time on, the ADC performs a continuous conversion of the selected channel.

When a conversion is complete:

• The EOC bit is set by hardware.

• The result is in the ADCDR registers.

A read to the ADCDRH or a write to any bit of the ADCCSR register resets the EOC bit.

To read the 10 bits, perform the following steps:

1.

Poll EOC bit

To read only 8 bits, perform the following steps:

1.

Poll EOC bit

2. Read ADCDRH. This clears EOC automatically.

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Changing the conversion channel

The application can change channels during conversion.

When software modifies the CH[2:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is cleared, and the A/D converter starts converting the newly selected channel.

Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed and between single shot conversions.

Table 32. Effect of low-power modes

Mode Description

Wait

Halt

No effect on A/D Converter

A/D Converter disabled.

After wakeup from Halt mode, the A/D Converter requires a stabilization time t

STAB

(see Electrical Characteristics) before accurate conversions can be performed.

11.3.5 Interrupts

None.

ADC Control/status register (ADCCSR)

Reset Value: 0000 0000 (00h)

7

EOC SPEED CH1

0

CH0 ADON 0 0

Read / Write (Except bit 7 read only)

CH2

Bit 7 = EOC End of conversion

This bit is set by hardware. It is cleared by hardware when software reads the

ADCDRH register or writes to any bit of the ADCCSR register.

Obsolete Product(s) - Obsolete Product(s)

1: Conversion complete

Bit 6 = SPEED ADC clock selection

This bit is set and cleared by software. It is used together with the SLOW bit to configure the ADC clock speed. Refer to the table in the SLOW bit description.

Bit 5 = ADON A/D converter on

This bit is set and cleared by software.

0: A/D converter is switched off

1: A/D converter is switched on

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Bits 4:3 = Reserved. Must be kept cleared.

Bits 2:0 = CH[2:0] Channel Selection

These bits are set and cleared by software. They select the analog input to convert.

Table 33. Channel selection

Channel pin CH2

AIN0

AIN1

AIN2

AIN3

AIN4

0

0

0

0

1

CH1

0

0

1

1

0

CH0

0

1

0

1

0

Note: A write to the ADCCSR register (with ADON set) aborts the current conversion, resets the

EOC bit and starts a new conversion.

ADC data register high (ADCDRH)

Reset value: 0000 0000 (00h)

7

D9 D8 D7 D6

Read only

D5 D4 D3

0

D2

ADC Control/data register Low (ADCDRL)

Reset Value: 0000 0000 (00h)

7

0 0 0 0 SLOW

Read/write

0 D1

0

D0

Bit 4 = Reserved . Forced by hardware to 0.

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Bit 3 = SLOW Slow mode

This bit is set and cleared by software. It is used together with the SPEED bit to configure the ADC clock speed as shown on the table below.

Table 34. Configuring the ADC clock speed f

ADC

SLOW

f

CPU

/2

f

CPU

f

CPU

/4

0

0

1

SPEED

0

1 x

Bit 2 = Reserved. Forced by hardware to 0.

Bits 1:0 = D[1:0] LSB of analog converted value

Address

(Hex.)

0034h

0035h

0036h

Register label

ADCCSR

Reset value

ADCDRH

Reset value

ADCDRL

Reset value

Table 35. ADC register map and reset values

7

EOC

0

D9

0

0

0

6 5

SPEED

0

D8

0

0

0

ADON

0

D7

0

0

0

4

0

0

D6

0

0

0

3

0

0

D5

0

SLOW

0

2

CH2

0

D4

0

0

0

1

CH1

0

D3

0

D1

0

0

CH0

0

D2

0

D0

0

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Instruction set ST7LITEU05 ST7LITEU09

The ST7 Core features 17 different addressing modes which can be classified in seven main groups:

Table 36. Description of addressing modes

Addressing mode Example

Inherent

Immediate

Direct

Indexed

Indirect

Relative

Bit operation nop ld A,#$55 ld A,$55 ld A,($55,X) ld A,([$55],X) jrne loop bset byte,#5

The ST7 instruction set is designed to minimize the number of bytes required per instruction: To do so, most of the addressing modes may be subdivided in two submodes called long and short:

• Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles.

• Short addressing mode is less powerful because it can generally only access page zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG,

BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)

The ST7 Assembler optimizes the use of long and short addressing modes.

Mode

Table 37. ST7 addressing mode overview nop

Syntax

Destination/ source

-

Pointer address

-

Pointe r

-

Length

(Bytes)

Inherent + 0

Immediate

Short

-

Direct

-

ld A,#$55 ld A,$10 00..FF

-

-

-

-

+ 1

+ 1

Long Direct ld A,$1000 0000..FFFF

+ 2

No Offset Direct Indexed ld A,(X) 00..FF

-

+ 0 (with X register)

+ 1 (with Y register)

+ 1 Short Direct Indexed ld A,($10,X) 00..1FE

-

Long

Short

Long

Direct

Indirect

Indirect

Indexed ld A,($1000,X) 0000..FFFF

ld A,[$10] 00..FF

ld A,[$10.w] 0000..FFFF

-

00..FF

00..FF

byte

word

+ 2

+ 2

+ 2

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Short

Long

Relative

Relative

Bit

Bit

Bit

Bit

ST7LITEU05 ST7LITEU09 Instruction set

Table 37. ST7 addressing mode overview (continued)

Mode Syntax

Indirect Indexed ld A,([$10],X)

Destination/ source

00..1FE

Indirect Indexed ld A,([$10.w],X) 0000..FFFF

Direct jrne loop PC-128/PC+127

1)

Indirect jrne [$10] PC-128/PC+127 1)

Pointer address

00..FF

00..FF

Pointe r byte word

-

00..FF

byte

-

Direct bset $10,#7 00..FF

Indirect

Direct

Indirect

bset [$10],#7 00..FF

Relative btjt $10,#7,skip 00..FF

Relative btjt

[$10],#7,skip

00..FF

-

00..FF

-

00..FF

byte

-

byte

+ 2

+ 2

+ 1

+ 2

+ 1

+ 2

+ 2

+ 3

Length

(Bytes)

Note: 1 At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.

All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation.

Table 38. Instructions supporting inherent addressing mode

Inherent instruction Function

NOP

TRAP

WFI

HALT

RET

IRET

No operation

S/W Interrupt

Wait For Interrupt (Low-power mode)

Halt Oscillator (Lowest power mode)

Subroutine return

Interrupt subroutine return

SIM

RIM

Set interrupt mask

Reset interrupt mask

SCF

RCF

Set carry flag Obsolete Product(s) - Obsolete Product(s)

RSP Reset stack pointer

LD

CLR

PUSH/POP

INC/DEC

TNZ

CPL, NEG

Load

Clear

Push/Pop to/from the stack

Increment/Decrement

Test Negative or Zero

1 or 2 complement

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Table 38. Instructions supporting inherent addressing mode (continued)

Inherent instruction Function

MUL

SLL, SRL, SRA, RLC, RRC

SWAP

Byte multiplication

Shift and rotate operations

Swap nibbles

12.1.2 Immediate

Immediate instructions have 2 bytes, the first byte contains the opcode, the second byte contains the operand value.

Table 39. Instructions supporting inherent immediate addressing mode

Immediate instruction Function

LD

CP

BCP

AND, OR, XOR

ADC, ADD, SUB, SBC

Load

Compare

Bit compare

Logical operations

Arithmetic operations

12.1.3 Direct

In Direct instructions, the operands are referenced by their memory address.

The direct addressing mode consists of two submodes:

Direct (short) addressing mode

the address is a byte, thus requires only 1 byte after the opcode, but only allows 00 - ff addressing space.

Direct (long) addressing mode

The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode.

12.1.4 Indexed mode (no offset, short, long)

Obsolete Product(s) - Obsolete Product(s) unsigned addition of an index register (X or Y) with an offset.

The indirect addressing mode consists of three submodes:

Indexed mode (no offset)

There is no offset (no extra byte after the opcode), and allows 00 - FF addressing space.

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Indexed mode (short)

The offset is a byte, thus requires only 1 byte after the opcode and allows 00 - 1FE addressing space.

Indexed mode (long)

The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode.

12.1.5 Indirect modes (short, long)

The required data byte to do the operation is found by its memory address, located in memory (pointer).

The pointer address follows the opcode. The indirect addressing mode consists of two submodes:

Indirect mode (short)

The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode.

Indirect mode (long)

The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.

This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode.

The indirect indexed addressing mode consists of two submodes:

Indirect indexed mode (short)

The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode.

Indirect indexed mode (long)

The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing

Obsolete Product(s) - Obsolete Product(s)

Table 40. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes

Instructions Function

Long and short instructions

LD

CP

AND, OR, XOR

Load

Compare

Logical operations

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Instruction set ST7LITEU05 ST7LITEU09

Table 40. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes (continued)

Instructions Function

ADC, ADD, SUB, SBC

BCP

CLR

INC, DEC

TNZ

CPL, NEG

BSET, BRES

BTJT, BTJF

SLL, SRL, SRA, RLC, RRC

SWAP

CALL, JP

Arithmetic addition/subtraction operations

Bit compare

Short instructions only

Clear

Increment/decrement

Test negative or zero

1 or 2 complement

Bit operations

Bit test and jump operations

Shift and rotate operations

Swap nibbles

Call or jump subroutine

12.1.7 Relative modes (direct, indirect)

This addressing mode is used to modify the PC register value by adding an 8-bit signed offset to it.

Table 41. Instructions supporting relative modes

Available relative direct/indirect instructions Function

JRxx

CALLR

Conditional jump

Call relative

The relative addressing mode consists of two submodes:

Relative mode (Direct)

The offset follows the opcode.

Relative mode (Indirect)

Obsolete Product(s) - Obsolete Product(s)

94/146 DocID13474 Rev 3

ST7LITEU05 ST7LITEU09 Instruction set

The ST 7 family devices use an Instruction Set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table:

Group

Load and Transfer

Stack operation

Increment/Decrement

Compare and tests

Logical operations

Bit operation

Conditional bit test and branch

Arithmetic operations

Shift and rotates

Unconditional jump or call

Conditional branch

Interruption management

Condition code flag modification

Table 42. ST7 instruction set

Instructions

LD CLR -

PUSH POP RSP

INC DEC -

-

-

CP

AND

TNZ BCP

OR XOR

-

CPL

-

NEG

BSET BRES

BTJT BTJF

ADC

-

-

-

-

-

-

ADD SUB SBC MUL

-

-

-

-

-

-

-

-

-

-

-

SLL

JRA

JRxx

SRL

JRT

-

SRA

JRF

-

RLC

JP

-

TRAP WFI HALT IRET

SIM RIM SCF RCF

RRC

-

-

-

SWAP

-

-

-

SLA

-

-

-

-

-

-

-

CALL CALLR NOP RET

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Using a prebyte

The instructions are described with 1 to 4 bytes.

In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede.

The whole instruction becomes:

PC-2 End of previous instruction

PC-1 Prebyte

PC Opcode

PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address Obsolete Product(s) - Obsolete Product(s) implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are:

PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one.

PIX 92 Replace an instruction using direct, direct bit or direct relative addressing mode to an instruction using the corresponding indirect addressing mode.

It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode.

PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.

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Instruction set ST7LITEU05 ST7LITEU09

Note:

In order to provide enhanced robustness to the device against unexpected behavior, a system of illegal opcode detection is implemented. If a code to be executed does not correspond to any opcode or prebyte value, a reset is generated. This, combined with the

Watchdog, allows the detection and recovery from an unexpected fault or interference.

A valid prebyte associated with a valid opcode forming an unauthorized combination does not generate a reset.

Mnemo Description

Table 43. Illegal opcode detection

Function/example Dst Src H I N Z

CPL

DEC

HALT

IRET

INC

JP

ADC

ADD

AND

BCP

BRES

BSET

BTJF

BTJT

CALL

Add with carry

Addition

Logical and

Bit compare A, Memory

Bit Reset

Bit Set

Jump if bit is false (0)

Jump if bit is true (1)

Call subroutine

CALLR Call subroutine relative

CLR Clear

CP Arithmetic compare

One Complement

Decrement

Halt

Interrupt routine return

Increment

Absolute jump

A = A + M + C

A = A + M

A = A . M tst (A . M) bres Byte, #3 bset Byte, #3 btjf Byte, #3, Jmp1 btjt Byte, #3, Jmp1

-

-

tst(Reg - M)

A = FFH-A dec Y

-

Pop CC, A, X, PC inc X jp [TBL.w]

M

M

M

M

-

A

A

A

A

reg, M reg reg, M reg, M

-

-

-

-

-

-

-

-

-

-

-

-

-

-

M

M

M

M

M

-

-

-

H

-

-

-

-

-

-

-

-

-

-

-

-

H

H

-

-

0

-

-

I

-

-

-

-

-

-

-

-

-

-

-

-

N

N

-

N

N

-

-

-

-

-

-

-

0

N

N

N

N

N reg, M

-

JRA Jump relative always -

JRT

JRF

Jump relative

Never jump

jrf *

-

-

-

-

-

-

-

-

-

-

-

-

-

-

JRIH Jump if ext. interrupt = 1 -

-

JRIL

JRH

Jump if ext. interrupt = 0

Jump if H = 1

-

H = 1 ?

-

-

-

-

-

-

-

-

-

-

-

Z

Z

-

Z

Z

-

-

-

-

-

-

-

1

Z

Z

Z

Z

Z

1

-

-

C

-

-

C

C

-

-

-

-

-

C

-

-

C

C

JRNH

JRM

JRNM

JRMI

Jump if H = 0

Jump if I = 1

Jump if I = 0

Jump if N = 1 (minus)

H = 0 ?

I = 1 ?

I = 0 ?

N = 1 ?

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

C

96/146 DocID13474 Rev 3

ST7LITEU05 ST7LITEU09 Instruction set

Mnemo Description

Table 43. Illegal opcode detection (continued)

Function/example Dst Src H I N Z

JRULE

LD

MUL

NEG

NOP

OR

POP

-

PUSH

RCF

JRPL

JREQ

JRNE

JRC

JRNC

JRULT

JRUGE

JRUGT

RET

RIM

RLC

RRC

RSP

SBC

SCF

SIM

Jump if N = 0 (plus)

Jump if Z = 1 (equal)

Jump if Z = 0 (not equal)

Jump if C = 1

Jump if C = 0

Jump if C = 1

Jump if C = 0

Jump if (C + Z = 0)

Jump if (C + Z = 1)

Load

Multiply

Negate (2's compl)

No operation

OR operation

Pop from the stack

-

Push onto the stack

Reset carry flag

Subroutine return

Enable Interrupts

Rotate left true C

Rotate right true C

Reset Stack Pointer

Subtract with carry

Set carry flag

Disable interrupts

N = 0 ?

Z = 1 ?

Z = 0 ?

C = 1 ?

C = 0 ?

Unsigned <

Jmp if unsigned >=

Unsigned >

Unsigned <= dst <= src

X,A = X * A neg $10

-

A = A + M pop reg pop CC push Y

C = 0

-

I = 0

C <= Dst <= C

C => Dst => C

S = Max allowed

A = A - M - C

C = 1

I = 1

-

reg, M reg, M

-

A

-

-

-

-

-

-

-

-

-

-

reg, M

-

M, reg

A, X, Y X, Y, A reg, M -

-

A reg

CC

M

-

-

M

M

M reg, CC

-

-

-

-

-

-

-

-

-

-

-

M

-

-

-

-

-

-

N

-

N

-

-

-

N

-

N

-

-

-

-

-

-

-

-

N

-

N

-

-

-

-

N

-

Z

-

Z

-

-

-

Z

-

Z

-

-

-

-

-

-

-

-

Z

-

Z

-

-

-

-

Z

-

-

1

SLA

SLL

Shift left arithmetic

Shift left logic

C <= Dst <= 0

C <= Dst <= 0 reg, M reg, M

-

-

-

-

-

-

N

N

Z

Z

C

C

SRL Shift right logic 0 => Dst => C reg, M 0 Z C

SRA Shift right arithmetic Dst7 => Dst => C reg, M N Z C

-

-

-

C

-

0

0

C

-

-

-

-

-

-

-

-

-

-

C

-

C

1

-

-

-

C

-

-

-

H

-

-

0

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

I

-

-

-

-

-

-

-

-

-

-

-

-

-

0

-

-

-

SUB

SWAP

TNZ

TRAP

Subtraction

SWAP nibbles

Test for Neg & Zero

S/W trap

A = A - M A

Dst[7..4]<=>Dst[3..0] reg, M tnz lbl1

S/W interrupt

-

-

-

M

-

-

-

-

-

-

1

-

-

N

-

N

N

Z

-

Z

Z

-

-

C

-

C

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145

Instruction set

Mnemo

WFI

XOR

ST7LITEU05 ST7LITEU09

Description

Table 43. Illegal opcode detection (continued)

Function/example Dst Src H

Wait for interrupt

Exclusive OR

-

A = A XOR M

-

A

-

M -

-

I

0

-

N

-

N

Z

-

Z

C

-

-

Obsolete Product(s) - Obsolete Product(s)

98/146 DocID13474 Rev 3

ST7LITEU05 ST7LITEU09 Electrical characteristics

Unless otherwise specified, all voltages are referred to V

SS

.

13.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100 % of the devices with an ambient temperature at T

A selected temperature range).

=25 °C and T

A

=T

A max (given by the

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3 Σ ).

Unless otherwise specified, typical data are based on T

4.5 V ≤ V

DD

V

DD

≤ 5.5 V voltage range), V

DD

=2.7 V (for the 2.4 V ≤ V

DD guidelines and are not tested.

A

=25 °C, V

= 3.75 V (for the 3 V ≤ V

DD

DD

≤

= 5 V (for the

4.5 V voltage range) and

≤ 3 V voltage range). They are given only as design

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

The loading conditions used for pin parameter measurement are shown in

Figure 41

.

Figure 41. Pin loading conditions

ST7 PIN

C

L

Obsolete Product(s) - Obsolete Product(s)

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Electrical characteristics ST7LITEU05 ST7LITEU09

13.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 42 .

Figure 42. Pin input voltage

ST7 PIN

V

IN

13.2 Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol

Table 44. Voltage characteristics

Ratings Maximum value Unit

V

DD

- V

SS

V

V

V

IN

ESD(HBM)

ESD(MM)

Supply voltage

Input voltage on any pin

(1)(2)

Electrostatic discharge voltage (human body model)

Electrostatic discharge voltage (machine model)

7.0

V

SS

-0.3 to V

DD

+0.3

V see

Section 13.7.3: Absolute maximum ratings (electrical sensitivity)

1. Directly connecting the I/O pins to V

DD

or V

SS could damage the device if an unexpected change of the I/O configuration through a pull-up or pull-down resistor (typical: 10 k according to their reset configuration.

Ω for I/Os). Unused I/O pins must be tied in the same way to V

DD

or V

SS

2. I

INJ(PIN)

must never be exceeded. This is implicitly insured if VIN maximum is respected. If V

IN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by V

IN while a negative injection is induced by V

IN

<V

SS

.

>V

DD

Obsolete Product(s) - Obsolete Product(s)

100/146 DocID13474 Rev 3

ST7LITEU05 ST7LITEU09 Electrical characteristics

Symbol

I

VDD

I

VSS

I

IO

I

INJ(PIN)

(2) & (3)

Σ I

INJ(PIN)

(2)

Table 45. Current characteristics

Ratings

Total current into V

DD

power lines (source)

(1)

Total current out of V

SS

ground lines (sink) (1)

Output current sunk by any standard I/O and control pin

Output current sunk by any high sink I/O pin

Output current source by any I/Os and control pin

Injected current on RESET pin

Injected current on any other pin (4)

Total injected current (sum of all I/O and control pins)

(4)

1. All power (V

DD

) and ground (V

SS

) lines must always be connected to the external supply.

Maximum value

75

150

20

40

-25

± 5

± 5

± 20

Unit mA

2.

I

INJ(PIN)

must never be exceeded. This is implicitly insured if V current must be limited externally to the I

V

IN

<V

SS

.

INJ(PIN)

IN

maximum is respected. If V

value. A positive injection is induced by V

IN

IN

maximum cannot be respected, the injection

>V

DD

while a negative injection is induced by

3.

Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:

- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage is lower than the specified limits)

- Pure digital pins must have a negative injection less than 1.6 mA. In addition, it is recommended to inject the current as far as possible from the analog input pins.

4.

When several inputs are submitted to a current injection, the maximum currents (instantaneous values). These results are based on characterisation with Σ I the device.

Σ I

INJ(PIN)

is the absolute sum of the positive and negative injected

INJ(PIN)

maximum current injection on four I/O port pins of

Symbol

T

STG

T

J

Table 46. Thermal characteristics

Ratings Value Unit

Storage temperature range -65 to +150

Maximum junction temperature (see Table 76: Package characteristics on page 132 )

°C

13.3.1 General operating conditions

Obsolete Product(s) - Obsolete Product(s)

Symbol

V

DD f

CPU

Table 47. General operating conditions

Parameter Conditions

Supply voltage

CPU clock frequency f

CPU

= 4 MHz. max.

f

CPU

= 8 MHz. max.

3.3 V ≤ V

DD

≤ 5.5 V

2.4 V ≤ V

DD

< 3.3 V

Min Max

2.4

5.5

3.3

up to 8

5.5

up to 4

Unit

V

MHz

DocID13474 Rev 3 101/146

145

Electrical characteristics ST7LITEU05 ST7LITEU09

Figure 43. f

CPU

maximum operating frequency versus V

DD supply voltage f

CPU

[MHz]

8

FUNCTIONALITY

GUARANTEED

IN THIS AREA

(UNLESS OTHERWISE

STATED IN THE

TABLES OF

PARAMETRIC DATA)

FUNCTIONALITY

NOT GUARANTEED

IN THIS AREA

4

2

0

2.0

2.4

2.7

3.3

3.5

4.0

4.5

5.0

5.5

SUPPLY VOLTAGE [V]

T

A

= -40 to 125 °C, unless otherwise specified

Symbol

V

IT+ (LVD)

V

IT(LVD)

V hys

I

Vt

POR

Table 48. Operating characteristics with LVD

Parameter Conditions Min Typ Max Unit

Reset release threshold

(V

DD

rise)

Reset generation threshold

(V

DD

fall)

High Threshold

Med. Threshold

Low Threshold

High Threshold

Med. Threshold

Low Threshold

3.9

3.2

2.5

3.7

3.0

2.4

4.2

3.5

2.7

4.0

3.3

2.6

4.5

3.8

3.0

4.3

3.6

2.9

V

LVD voltage threshold hysteresis

V

DD

rise time rate

(1)(2)

V

IT+ (LVD)

-V

IT(LVD)

-

-

20

150

-

mV

μ s/V

LVD/AVD current consumption V

DD

= 5V 220 μ A

1.

Not tested in production. The V

DD release. When the V

DD

rise time rate condition is needed to ensure a correct device power-on and LVD reset

slope is outside these values, the LVD may not release properly the reset of the MCU

2.

Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is recommended to pull V

page 122 .

DD

down to 0V to ensure optimum restart conditions. Refer to circuit example in

Figure 66 on

3.

Not tested in production.

Obsolete Product(s) - Obsolete Product(s)

102/146 DocID13474 Rev 3

ST7LITEU05 ST7LITEU09 Electrical characteristics

13.3.3 Auxiliary voltage detector (AVD) thresholds

T

A

= -40 to 125°C, unless otherwise specified

Symbol

Table 49. Operating characteristics with AVD

Parameter Conditions

Min

(1)

Typ

(1)

Max

(1)

V

IT+ (AVD)

1 => 0 AVDF flag toggle threshold

(V

DD

rise)

High threshold

Med. threshold

Low threshold

V

IT(AVD)

0 => 1 AVDF flag toggle threshold

(V

DD

fall)

High threshold

Med. threshold

Low threshold

V hys

AVD voltage threshold hysteresis V

IT+ (AVD)

1. Not tested in production, guaranteed by characterization.

-V

IT(AVD)

4.0

3.4

2.6

3.9

3.3

2.5

-

4.4

3.7

2.9

4.3

3.6

2.8

150

4.8

4.1

3.2

4.7

4.0

3.1

-

Unit

V mV

Note: Refer to Section : Monitoring the VDD main supply.

.

Table 50. Voltage drop between AVD flag set and LVD reset generation

Parameter Min

(1)

Typ

(1)

Max

(1)

Unit

AVD med. threshold - AVD low. threshold

AVD high. threshold - AVD low threshold

AVD high. threshold - AVD med. threshold

AVD low threshold - LVD low threshold

AVD med. threshold - LVD low threshold

AVD med. threshold - LVD med. threshold

AVD high. threshold - LVD low threshold

AVD high. threshold - LVD med. threshold

1. Not tested in production, guaranteed by characterization.

800

1400

600

100

950

250

1600

900

850

1450

650

200

1050

300

1700

1000

950

1550

750

250

1150

400

1800

1050 mV

Obsolete Product(s) - Obsolete Product(s) capacitor, typically 100 nF, between the V

DD device

and V

SS

pins as close as possible to the ST7

Internal RC oscillator calibrated at 5.0

V

The ST7 internal clock can be supplied by an internal RC oscillator (selectable by option byte).

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145

Electrical characteristics ST7LITEU05 ST7LITEU09

Symbol

Table 51. Internal RC oscillator characteristics (5.0

V calibration)

Parameter Conditions f

RC

ACC

RC

Internal RC oscillator frequency

Accuracy of Internal RC oscillator with

RCCR=RCCR0

(1)

RCCR = FF (reset value),

T

A

= 25 °C, V

DD

= 5 V

RCCR = RCCR0

(1)

, T

A

= 5 V

= 25 °C, V

DD

T

A

= 25 °C, V

DD

= 4.5 to 5.5 V

(2)

T

A

V

= 0 to +85 °C,

DD

= 4.5 to 5.5 V

(2)

T

A

V

= 0 to +125 °C,

DD

= 4.5 to 5.5 V

(2)

T

A

V

= -40 °C to 0 °C,

DD

= 4.5 to 5.5 V

(2)

T

A

= 25°C, V

DD

= 5 V t su(RC)

RC oscillator setup time

1. See Section 7.2: Internal RC oscillator adjustment

2. Tested in production at 5.0 V only

Min

-2.0

-2.5

-3.0

-4.0

-

-

-

Typ

4.4

8

-

-

-

-

4

(2)

Internal RC oscillator calibrated at 3.3

V

The ST7 internal clock can be supplied by an internal RC oscillator (selectable by option byte).

Symbol

Table 52. Internal RC oscillator characteristics (3.3

V calibration)

Parameter Conditions f

RC

ACC

RC

Internal RC oscillator frequency

Accuracy of internal RC oscillator with

RCCR=RCCR1

(1)

1.

See

Section 7.2: Internal RC oscillator adjustment

2.

Tested in production at 3.3 V only

RCCR = FF (reset value),

T

A

=25 °C,V

DD

= 3.3 V

RCCR = RCCR1

T

A

=25 °C,V

DD

(1)

,

= 3.3 V

T

A

=25°C, V

DD

= 3.0 to 3.6 V

(2)

T

A

=0 to +85 °C, V

DD

= 3.0 to 3.6 V

(2)

T

A

=0 to +125 °C, V

DD

= 3.0 to 3.6 V

(2)

T

A

V

= -40 °C to 0 °C,

DD

= 3.0 to 3.6 V

(2)

T

A

= 25 °C, V

DD

= 3.3 V

Min

-1.0

-2.5

-3.0

-

-

-

-4.0

Typ

4.3

8

-

-

-

-

Max Unit

-

MHz

-

+1.0

%

+4.0

%

+5.0

%

+2.5

%

μ s

Max Unit

-

MHz

-

+2.0

%

+4.0

%

+5.0

%

+2.5

%

μ s

104/146 DocID13474 Rev 3

ST7LITEU05 ST7LITEU09 Electrical characteristics

Figure 44. Typical accuracy with RCCR=RCCR0 vs V

DD

= 2.4-6.0 V and temperature

0.8

0.6

0.4

0.2

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

-1.2

-1.4

-1.6

-1.8

-2.0

-2.2

2.2

2.0

1.8

1.6

1.4

1.2

1.0

RC5V@-45C

RC5V@25C

RC5V@90C

RC5V@130C

RC5V@0C

Figure 45. Typical accuracy with RCCR=RCCR1 vs V

DD

= 2.4-6.0V and temperature

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

-1.2

-1.4

3.0

2.8

2.6

2.4

2.2

2.0

1.8

RC3.3V@-45C

RC3.3V@25C

RC3.3V@90C

RC3.3V@130C

RC3.3V@0C

The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consumption, the two current values must be added (except for Halt mode for which the clock is stopped). Refer to

Section 13.4.2: Internal RC oscillator supply characteristics .

Obsolete Product(s) - Obsolete Product(s)

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Electrical characteristics ST7LITEU05 ST7LITEU09

T

A

= -40 to +125°C unless otherwise specified.

s

Symbol

Table 53. Supply current characteristics

Parameter Conditions Typ Max Unit

4.5

(2)

Supply current in RUN mode

(1)

Supply current in Wait mode

(3)

Supply current in Slow mode (4)

Supply current in Slow-Wait mode

(5)

Supply current in AWUFH mode

(6)(7) f

CPU

= 4 MHz f

CPU

= 8 MHz f

CPU

= 4 MHz f

CPU

= 8 MHz f

CPU

/32 = 250 kHz f

CPU

/32 = 250 kHz

-

2.5

5.0

7.5

0.85

2.0

(2)

1.2

600

450

45

3.5

950

750

100

(2) mA

μ A

Supply current in ACTIVE Halt mode 100 250

T

A

= 85 °C

T

A

= 125 °C f

CPU

= 4 MHz f

CPU

= 4 MHz f

CPU

/32 = 250 kHz f

CPU

/32 = 250 kHz

-

0.5

3.0

I

DD

Supply current in Halt mode

(8)

Supply current in RUN mode (1)

Supply current in Wait mode

(3)

Supply current in Slow mode

(4)

Supply current in Slow-wait mode

(5)

Supply current in AWUFH mode

(6)(7)

Supply current in ACTIVE Halt mode -

0.5

5.0

1.30

2.0 (2)

0.36

0.5

(2)

300 400

(2)

250 350

(2)

20 50

(2)

90 150

(2)

0.25

2.5 (2)

0.25

4.5

(2)

Supply current in Halt mode

(8)

T

A

= 85 °C

T

A

= 125 °C

1. CPU running with memory access, all I/O pins in input mode with a static value at V reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

DD

or V

SS

(no load), all peripherals in

2. Data based on characterization, not tested in production.

3. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

4. Slow mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at V

(no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

DD

or V

SS

5. Slow-Wait mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at V

V

SS

(no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

DD

or

Obsolete Product(s) - Obsolete Product(s)

7. This consumption refers to the Halt period only and not the associated run period which is software dependent.

CPU

8. All I/O pins in output mode with a static value at VSS (no load), LVD disabled. Data based on characterization results, tested in production at V

DD

max and f

CPU

max.

mA

μ A

106/146 DocID13474 Rev 3

ST7LITEU05 ST7LITEU09 Electrical characteristics

Symbol

Table 54. Internal RC oscillator supply characteristics

Parameter Conditions Min Typ Max

(1)

Unit

I

DD

Supply current in Run mode

Supply current in Wait mode

(2)

(3)

T

A

=25 °C, int RC = 4 MHz

T

A

=25 °C, int RC = 8 MHz

T

A

=25 °C, AWU RC

T

A

=25 °C, int RC = 4 MHz

T

A

=25 °C, int RC = 8 MHz

T

A

=25 °C, int RC/32 = 250 kHz

-

-

-

-

-

3.2

5.7

0.13

1.5

1.9

1.3

3.0

4.5

2.0

5.5

8.5

0.2

mA

Supply current in Slow mode

(4)

Supply current in Slow-Wait mode

(5)

Supply current in Active-Halt mode

T

A

=25 °C, int RC/32 = 250 kHz

-

1.1

0.8

1.8

1.25

I

DD

Supply current in Run mode

Supply current in Wait mode

(2)

(3)

T

A

=25 °C, int RC = 4 MHz

T

A

=25 °C, int RC = 2 MHz

T

A

=25 °C, AWU RC

T

A

=25 °C, int RC = 4 MHz

T

A

=25 °C, int RC = 2 MHz

T

A

=25 °C, int RC/32 = 250 kHz

-

-

-

-

-

-

2.0

1.3

0.1

1.0

0.9

0.95

3.0

2.0

0.18

1.6

1.5

1.5

mA

Supply current in Slow mode

(4)

Supply current in Slow-Wait mode

(5)

Supply current in Active-Halt mode

T

A

=25 °C, int RC/32 = 250 kHz

-

0.85

0.8

1.4

1.3

1. Data based on characterization results, not tested in production.

2. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; CPU clock provided by the internal RC, LVD disabled.

3. All I/O pins in input mode with a static value at V the internal RC, LVD disabled.

DD

or V

SS

(no load), all peripherals in reset state; CPU clock provided by

4.

Slow mode selected with f based on f

OSC

divided by 32. All I/O pins in input mode with a static value at V load), all peripherals in reset state; CPU clock provided by the internal RC, LVD disabled.

DD

or V

SS

(no

5. Slow-Wait mode selected with f

V

SS

CPU

based on f

OSC

divided by 32. All I/O pins in input mode with a static value at V

(no load), all peripherals in reset state; CPU clock provided by the internal RC, LVD disabled.

DD

or

Obsolete Product(s) - Obsolete Product(s)

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Figure 46. Typical I

DD

in run mode vs. internal clock frequency and V

DD

6.00

5.00

4.00

3.00

2.00

1.00

0.00

Idd RUN mode @amb vs int clock freq

RC 8 M Hz

RC 4 M Hz

RC 2 M Hz

AWU

VDD [V]

Figure 47. Typical I

DD

in WFI mode vs. internal clock frequency and V

DD

Idd WFI mode @amb vs int RC freq

2.300

2.100

1.900

1.700

1.500

1.300

1.100

0.900

0.700

8 MHz

4 MHz

2 MHz

VDD [V]

Figure 48. Typical I

DD

in Slow, Slow-wait and Active-halt mode vs V

RC = 8 MHz

DD

& int

1.400

1.300

1.200

1.100

1.000

0.900

0.800

0.700

Idd slow , slow w ait & acthalt m ode, int Rc 8Mhz@amb

Slow slow w ait acthlt

VDD [V]

Obsolete Product(s) - Obsolete Product(s)

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ST7LITEU05 ST7LITEU09 Electrical characteristics

Figure 49. Idd vs temp @V

DD

5 V & int RC = 8 MHz

6.0

5.0

4.0

3.0

2.0

1.0

0.0

run wfi slow slowwait acthlt

Temp [°C]

Figure 50. Idd vs temp @V

DD

5 V & int RC = 4 MHz

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

run wfi

Temp [°C]

Figure 51. Idd vs temp @V

DD

5V & int RC = 2 MHz

3.0

2.5

2.0

run wfi 1.5

1.0

0.5

0.0

Temp [°C]

Obsolete Product(s) - Obsolete Product(s)

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Electrical characteristics ST7LITEU05 ST7LITEU09

Symbol

Table 55. On-chip peripheral characteristics

Parameter Conditions Typ

(1)

Unit

I

I

DD(AT)

DD(ADC)

12-bit auto-reload timer supply current

ADC supply current when converting

(2)

(3) f

CPU

= 4 MHz V

DD

= 3.0 V f

CPU

= 8 MHz V

DD

= 5.0 V f

ADC

= 2 MHz V

DD

= 3.0 V f

ADC

= 4 MHz V

DD

= 5.0 V

15

30

450

750

μ

1. Not tested in production, guaranteed by characterization.

2. Data based on a differential I mode at f cpu

= 8 MHz.

DD

measurement between reset configuration (timer stopped) and the timer running in PWM

3. Data based on a differential I off.

DD

measurement between reset configuration and continuous A/D conversions with amplifier

A

13.5 Clock and timing characteristics

Subject to general operating conditions for V

DD

, f

OSC

, and T

A

.

Table 56. General timings

Symbol Parameter

(1)

Conditions Min Typ

(2)

Max Unit t c(INST) t v(IT)

Instruction cycle time

Interrupt reaction time t v(IT)

= Δ t c(INST)

+ 10

(3) f f

CPU

= 8 MHz

CPU

= 8 MHz

2

250

10

1.25

3

375

-

-

12

1500

22

2.75

t

1. Data based on characterization. Not tested in production.

2. Data based on typical application software.

3. Time measured between interrupt event and interrupt vector fetch. Δ t needed to finish the current instruction execution.

c(INST) is the number of t

CPU

cycles

CPU ns t

CPU

μ s

Table 57. Auto-wakeup RC oscillator

Parameter Typ Max Unit

Supply voltage range 2.4

5.0

5.5

Obsolete Product(s) - Obsolete Product(s)

Current consumption

(1)

-40 25 125

Without prescaler 2.0

8.0

14.0

°C

µA

V

Consumption (1)

Output frequency (f

AWU_RC

)

(1)

AWU RC switched off

-

-

20

0

33

-

60

µA kHz

1. Data guaranteed by Design.

110/146 DocID13474 Rev 3

ST7LITEU05 ST7LITEU09 Electrical characteristics

T

A

= -40 °C to 125 °C, unless otherwise specified

Table 58. RAM and hardware registers

Symbol Parameter Conditions Min Typ Max

V

RM

Data retention mode

(1)

Halt mode (or Reset) 1.6

-

1. Minimum V

DD

supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware registers (only in Halt mode). Guaranteed by construction, not tested in production.

Unit

V

Symbol

Table 59. Flash program memory

Parameter Conditions

V

DD

Operating voltage for Flash write/erase

Programming time for 1~32 bytes

(1)

-

T

A

= − 40 to +125 °C t prog t

N

I

RET

RW

DD

Programming time for 2 KBytes

Data retention

Supply current

(2)

Write erase cycles

(4)

T

A

= +25 °C

T

A

= +55 °C

(3)

T

A

= +25 °C

Read / Write / Erase f modes

CPU

V

= 8 MHz,

DD

= 5.5 V

No Read/No Write mode

Power down mode /

HALT

1. Up to 32 bytes can be programmed at a time.

2. Data based on reliability test results and monitored in production.

3. The data retention time increases when T

A

decreases.

4. Guaranteed by Design. Not tested in production.

Min Typ Max Unit

2.4

-

-

20

-

-

-

-

-

5

0.32

0.64

-

s years

10k cycles

-

-

0

5.5

10

2.6

100

0.1

V ms mA

μ A

μ A

Obsolete Product(s) - Obsolete Product(s)

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Symbol Parameter

Table 60. EEPROM data memory

Conditions

V

DD

Operating voltage for

EEPROM write/erase

Refer to operating range of V

DD with T

A,

Section 13.3.1: General operating conditions

t t prog

N ret

RW

Programming time for

1~32 bytes

Data retention (1)

Write erase cycles

T

A

= − 40 to +125 °C

T

A

= +55 °C (2)

T

A

= +25 °C

1. Data based on reliability test results and monitored in production.

2. The data retention time increases when T

A

decreases.

Min Typ Max Unit

2.4

-

20

-

5

-

-

5.5

10

V ms

years

300k cycles

Susceptibility tests are performed on a sample basis during product characterization.

13.7.1 Functional EMS (electro magnetic susceptibility)

Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs).

• ESD : Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard.

• FTB : A burst of fast transient voltage (positive and negative) is applied to V

DD

and V

SS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard.

A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and

Obsolete Product(s) - Obsolete Product(s)

Software recommendations:

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical data corruption (control registers...)

112/146 DocID13474 Rev 3

ST7LITEU05 ST7LITEU09 Electrical characteristics

Symbol

V

FESD

V

FFTB

Prequalification trials:

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behaviour is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Table 61. EMS test results

Parameter Conditions

Level/ class

Voltage limits to be applied on any I/O pin to induce a functional disturbance

V

DD

= 5 V, T

A

= +25 °C, f

OSC

SO8 package, conforms to IEC 1000-4-2

= 8 MHz,

Fast transient voltage burst limits to be applied through 100 pF on V

SS functional disturbance and V

DD pins to induce a

V

DD

= 5 V, T

A

= +25 °C, f

OSC

SO8 package, conforms to IEC 1000-4-4

= 8 MHz,

3B

4A

13.7.2 EMI (electromagnetic interference)

Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin.

Symbol

S

EMI

Parameter

Peak level

Table 62. EMI emissions

Conditions

V

DD

= 5 V, T

A

= +25 °C,

SO8 package, conforming to SAE J

1752/3

Monitored frequency band

0.1 MHz to 30 MHz

30 MHz to 130 MHz

130 MHz to 1 GHz

SAE EMI Level

Max vs. [f

OSC

/f

CPU

]

-/8 MHz

20

20

13

2.5

Unit dB μ V

-

13.7.3 Absolute maximum ratings (electrical sensitivity)

Obsolete Product(s) - Obsolete Product(s)

Based on three different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity.

For more details, refer to the application note AN1181.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). One model can be simulated: human body model. This test conforms to the JESD22-A114A/A115A standard.

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Table 63. ESD absolute maximum ratings

Ratings Conditions Symbol

V

V

ESD(HBM)

ESD(CDM)

Electro-static discharge voltage

(human body model)

Electro-static discharge voltage

(charge device model)

T

A

1. Data based on characterization results, not tested in production.

-

= +25 °C

Maximum value

(1)

4000

Unit

V

500 V

Static latch-up (LU)

Two complementary static tests are required on six parts to assess the latch-up performance.

• A supply overvoltage is applied to each power supply pin

• A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with the EIA/JESD 78 IC latch-up standard.

Symbol

Table 64. Electrical sensitivities

Parameter Conditions Class

(1)

LU Static latch-up class T

A

= +125 °C A

1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the

JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B

Class strictly covers all the JEDEC criteria (international standard).

13.8 I/O port pin characteristics

Symbol

V

IL

V

IH

V

HYS

I

L

I

S

R

PU

Subject to general operating conditions for V

DD

, f

OSC

, and T

A

unless otherwise specified.

Parameter

Table 65. General characteristics

Conditions Min Typ Max Unit

Input low level voltage

Input high level voltage

-40 °C to 125 °C

-

0.7 x V

DD

-

-

0.3xV

-

DD

V

Schmitt trigger voltage hysteresis

(1)

400 mV

V

SS

≤ V

IN

≤ V

DD

±1 Input leakage current

Static current consumption induced by each floating input pin

(2)

Floating input mode 400

μ A

Weak pull-up equivalent resistor

(3) (4)

V

=

IN

V

SS

V

DD

= 5 V

V

DD

= 3 V

70 110

200

(1)

200 k Ω

114/146 DocID13474 Rev 3

ST7LITEU05 ST7LITEU09 Electrical characteristics

Symbol

C

IO t f(IO)out t r(IO)out

Table 65. General characteristics (continued)

Parameter Conditions Min

I/O pin capacitance

Output high to low level fall time

(1)

Output low to high level rise time

(1)

External interrupt pulse time

(5)

-

-

C

L

= 50 pF

Between 10% and 90%

-

-

1

Typ

5

25

25

Max

-

-

-

Unit pF ns t w(IT)in

t

CPU

1.

Data based on characterization results, not tested in production.

2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor (see

Figure 57

). Static peak current value taken at a fixed V based on design simulation and technology characteristics, not tested in production. This value depends on V temperature values.

IN

DD

value, and

3. The R pull-up equivalent resistor is based on a resistive transistor (corresponding I

Figure 54 ).

PU current characteristics described in

4. R

PU

not applicable on PA3 because it is multiplexed on RESET pin

5. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source.

V

DD

Figure 52. Two typical applications with unused I/O pin

ST7XXX

10k Ω

UNUSED I/O PORT

10k Ω

UNUSED I/O PORT

ST7XXX

Caution: During normal operation the ICCCLK pin must be pulled- up, internally or externally

(external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset

Note: I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of greater EMC robustness and lower cost.

Figure 53. Typical I

PU

vs. V

DD

with V

IN

=V

SS

60

50

40

30

-45°C

25°C

90°C

130°C

10

0

Vdd [V]

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Figure 54. Typical R

PU

vs. V

DD

with V

IN

=V

SS

500

450

400

350

300

250

200

150

100

50

0

-45°C

25°C

90°C

130°C

Vdd [V]

Obsolete Product(s) - Obsolete Product(s)

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ST7LITEU05 ST7LITEU09 Electrical characteristics

13.8.2 Output driving current

Subject to general operating conditions for V

DD

, f

CPU

, and T

A

unless otherwise specified.

Symbol

Table 66. Output driving current characteristics

Parameter Conditions Min Max Unit

V

OL

(1)

Output low level voltage for PA3/RESET standard I/O pin (see

Figure 57 )

Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time

(see Figure 60

)

I

IO

= +5 mA,T

A

≤ 125 °C

I

IO

= +2 mA,T

A

≤ 125 °C

I

IO

T

A

= +20 mA,

≤ 125 °C

I

IO

= +8 mA,T

A

≤ 125 °C -

-

-

-

I

IO

= -5 mA,T

A

≤ 125 °C V

DD

-1500

I

IO

= -2 mA,T

A

≤ 125 °C V

DD

-800

1200

400

1300

750

V

V

OH

(2)

OL

(1)(3)

V

OH

(2)(3)

Output high level voltage for an I/O pin when 4 pins are sourced at same time

(see Figure 63

)

Output low level voltage for PA3/RESET standard I/O pin

(see Figure 56

)

Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time

(see Figure 59

)

Output high level voltage for an I/O pin when 4 pins are sourced at same time

(see Figure 62

)

I

I

I

I

IO

IO

IO

IO

= +2 mA,T

= +2 mA,T

= +8 mA,T

= -2 mA,T

A

A

A

A

≤

≤

≤

125 °C

125 °C

125 °C

≤ 125 °C V

DD

-

-

-

-800

500

180

600

mV

V

OL

(1)(3)

V

OH

(2)(3)

Output low level voltage for PA3/RESET standard I/O pin (see

Figure 55 )

Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time

(see Figure 58

)

Output high level voltage for an I/O pin when 4 pins are sourced at same time

(see Figure 61

)

I

I

I

I

IO

IO

IO

IO

= +2 mA,T

= +2 mA,T

=+8 mA,T

A

=-2 mA,T

A

A

A

≤

≤

125 °C

125 °C

≤ 125 °C

≤ 125 °C V

DD

-

-

-

-900

700

200

800

-

1.

The I

IO

current sunk must always respect the absolute maximum rating specified in

Table 45: Current characteristics

and the sum of I ports and control pins) must not exceed I

VSS

.

IO

(I/O

2.

The I

IO

current sourced must always respect the absolute maximum rating specified in Table 45: Current characteristics and the sum of I

(I/O ports and control pins) must not exceed I

VDD

. True open drain I/O pins do not have V

OH

.

IO

3.

Not tested in production, based on characterization results.

Obsolete Product(s) - Obsolete Product(s)

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Electrical characteristics ST7LITEU05 ST7LITEU09

Figure 55. Typical V

OL

at v

DD

= 2.4 V (standard pins)

1400

1200

1000

800

-45°C

25°C

90°C

130°C

600

400

200

0

0 2

Iol [mA]

4

Figure 56. Typical v

OL

at v

DD

= 3 V (standard pins)

1400

1200

1000

800

600

400

200

0

-45°C

25°C

90°C

130°C

0 2 4

Iol [mA]

6 8

Figure 57. Typical V

OL

at V

DD

= 5 V (standard pins)

1200

1000

800

600

400

-45°C

25°C

90°C

130°C

200

0

0 2 4

Iol [mA]

6 8 Obsolete Product(s) - Obsolete Product(s)

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ST7LITEU05 ST7LITEU09 Electrical characteristics

Figure 58. Typical V

OL

at V

DD

= 2.4 V (HS pins)

1200

1000

800

600

400

200

0

0 2

-45°C

25°C

90°C

130°C

4 6 8

Iol [mA]

10 12 14 16

Figure 59. Typical V

OL

at V

DD

= 3 V (HS pins)

1400

1200

1000

800

600

400

200

0

0

-45°C

25°C

90°C

130°C

2 4 6 8 10

Iol [mA]

12 14 16 18 20

700

600

500

400

300

200

100

Figure 60. Typical V

OL

at V

DD

= 5 V (HS pins)

800

-45°C

25°C

90°C

130°C

0

0 2 4 6 8 12 14 16 18 20 10

Iol [mA]

Obsolete Product(s) - Obsolete Product(s)

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Electrical characteristics ST7LITEU05 ST7LITEU09

Figure 61. Typical V

DD

-V

OH

at V

DD

= 2.4 V (HS pins)

1000

800

600

400

200

0

1800

1600

1400

1200

-45°C

25°C

90°C

130°C

0 2 4 6

Iol [mA]

8 10 12

Figure 62. Typical V

DD

-V

OH

at V

DD

= 3 V (HS pins)

1800

1600

1400

1200

1000

800

600

400

200

0

0 2 4

-45°C

25°C

90°C

130°C

6 8

Iol [mA]

10 12 14 16 18

Figure 63. Typical V

DD

-V

OH

at V

DD

= 5 V (HS pins)

1000

900

800

700

600

500

400

300

200

-45°C

25°C

90°C

130°C

100

0

0 2 4 6 8 10

Iol [mA]

12 14 16 18 20

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ST7LITEU05 ST7LITEU09 Electrical characteristics

Figure 64. Typical V

OL

vs. V

DD

(HS pins)

100

90

80

70

60

-45°C

25°C

90°C

130°C

50

40

2.4 2.6 2.8

3 3.2 3.4 3.6 3.8

4 4.2 4.4 4.6 4.8

Vdd [V]

5 5.2 5.4 5.6 5.8

6

500

450

400

-45°C

25°C

90°C

130°C

200

150

100

350

300

250

2.4 2.6 2.8

3 3.2 3.4 3.6 3.8

4 4.2 4.4 4.6 4.8

5

Vdd [V]

5.2 5.4 5.6 5.8

6

900

800

700

600

500

-45°C

25°C

90°C

130°C

400

300

200

2.4 2.6 2.8

3 3.2 3.4 3.6 3.8

4 4.2 4.4 4.6 4.8

Vdd [V]

5 5.2 5.4 5.6 5.8

6

Figure 65. Typical V

DD

-V

OH

vs. V

DD

(HS pins)

700

200

180

160

140

120

-45°C

25°C

90°C

130°C

100

80

60

40

2.4 2.6 2.8

3 3.2 3.4 3.6 3.8

4 4.2 4.4 4.6 4.8

Vdd [V]

5 5.2 5.4 5.6 5.8

6

600

500

400

300

200

-45°C

25°C

90°C

130°C

100

2.4 2.6 2.8

3 3.2 3.4 3.6 3.8

4 4.2 4.4 4.6 4.8

Vdd [V]

5 5.2 5.4 5.6 5.8

6

Obsolete Product(s) - Obsolete Product(s)

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ST7LITEU05 ST7LITEU09 Electrical characteristics

13.9 Control pin characteristics

T

A

= -40 °C to 125 °C, unless otherwise specified

Symbol

Table 67. Asynchronous RESET pin characteristics

Parameter Conditions Min Typ Max Unit

V

IL

V

IH

V hys

V

OL

Input low level voltage

Input high level voltage

Schmitt trigger voltage hysteresis

(1)

Output low level voltage

(2)

-

-

V

SS - 0.3

0.7xV

DD

-

-

-

2

0.3xV

V

DD + 0.3

-

DD

V

V

R

ON

Pull-up equivalent resistor

(3)

V

DD

= 5 V I

IO

= +2 mA

V

DD

= 5 V

V

IN

= V

SS

V

DD

= 3 V

Internal reset sources

30

-

-

50

90

(1)

90

(1)

400

70

mV k t w(RSTL)out t h(RSTL)in t g(RSTL)in

Generated reset pulse duration

External reset pulse hold time

Filtered glitch duration

(4)

-

-

-

20

-

-

200 -

-

-

1. Data based on characterization results, not tested in production.

2. The I

IO

current sunk must always respect the absolute maximum rating specified in

Table 45: Current characteristics

and the sum of I

IO

(I/O ports and control pins) must not exceed I

VSS

.

3. The R and V

ON

DD

pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between V

ILmax

4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on

RESET pin with a duration below t h(RSTL)in

can be ignored.

Ω

μ s

μ s ns

Figure 66. RESET pin protection when LVD is enabled

V

DD

ST7xxx

Required Optional R

ON

INTERNAL

RESET

EXTERNAL

RESET Filter

0.01

μ F

1M Ω

PULSE

WATCHDOG

ILLEGAL OPCODE 1)

GENERATOR

LVD RESET Obsolete Product(s) - Obsolete Product(s)

1. Please refer to

Section 12.2.1: Illegal opcode reset for more details on illegal opcode reset conditions

The reset network protects the device against parasitic resets. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).

Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the V

IL

max. level specified in

Section 13.9.1: Asynchronous

RESET pin

. Otherwise the reset is not taken into account internally.

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ST7LITEU05 ST7LITEU09 Electrical characteristics

Because the reset circuit is designed to allow the internal Reset to be output in the RESET pin, the user must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for I

INJ(RESET)

in Table 45: Current characteristics

.

When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor.

A 10 nF pull-down capacitor is required to filter noise on the reset line.

In case a capacitive power supply is used, it is recommended to connect a 1 M Ω pull-down resistor to the RESET pin to discharge any residual voltage induced by the capacitive effect of the power supply (this adds 5µA to the power consumption of the MCU).

Tips when using the LVD

• Check that all recommendations related to ICCCLK and reset circuit have been applied

(see caution in

Table 1: Device pin description

and notes above).

• Check that the power supply is properly decoupled (100 nF + 10 µF close to the MCU).

Refer to AN1709 and AN2017. If this cannot be done, it is recommended to put a

100 nF + 1 M Ω pull-down on the RESET pin.

• The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up marginality. In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10 nF pull-down on the RESET pin with a 5 µF to

20 µF capacitor.”

Figure 67. RESET pin protection when LVD is disabled

V

DD ST72XXX

USER

EXTERNAL

RESET

CIRCUIT

0.01

μ F

R

ON

Filter

PULSE

GENERATOR

INTERNAL

RESET

WATCHDOG

ILLEGAL OPCODE

1)

Required

1. Please refer to

Section 12.2.1: Illegal opcode reset for more details on illegal opcode reset conditions.

2. The reset network protects the device against parasitic resets.

The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad.

Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).

Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the V

IL

max. level specified in Section 13.9.1: Asynchronous RESET pin

. Otherwise the reset is not taken into account internally.

Obsolete Product(s) - Obsolete Product(s)

I

Because the reset circuit is designed to allow the internal Reset to be output in the RESET pin, the user must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for

INJ(RESET)

in Table 45: Current characteristics .

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Electrical characteristics ST7LITEU05 ST7LITEU09

13.10 10-bit ADC characteristics

Subject to general operating condition for V

DD

, f

OSC

, and T

A

unless otherwise specified.

Symbol f

ADC

V

R

AIN

AIN

Parameter

ADC clock frequency (2)

Conversion voltage range

External input resistor

Table 68. ADC characteristics

Conditions

-

-

V

DD

= 5 V, f

ADC

= 4 MHz

V

DD

= 3.3 V, f

ADC

= 4 MHz

2.7 V ≤ V

DD f

ADC

≤ 5.5 V,

= 2 MHz

2.4 V ≤ V

DD f

ADC

≤ 2.7 V,

= 1 MHz

Min

-

V

SS

-

-

-

-

Typ

-

-

-

-

-

-

(1)

Max

4

V

DD

8k

(3)

7k

(3)

10k

20k

(3)

(3)

Unit

MHz

V

Ω t

C t

ADC

STAB

ADC

Internal sample and hold capacitor

Stabilization time after ADC enable

Conversion time (sample+hold)

- Sample capacitor loading time

- Hold conversion time f f

CPU

ADC

= 8 MHz,

= 4 MHz

3

0

(4)

3.5

4

10

-

1/f pF

μ

ADC

1. Unless otherwise specified, typical data are based on T guidelines and are not tested.

A

=25 °C and V

DD

-V

SS

= 5 V. They are given only as design

2. The maximum ADC clock frequency allowed within V

DD

= 2.4 V to 2.7 V operating range is 1 MHz.

3. Any added external serial resistor downgrades the ADC accuracy (especially for resistance greater than the maximum value). Data guaranteed by Design, not tested in production.

4. The stabilization time of the A/D converter is masked by the first t valid.

LOAD

. The first conversion after the enable is then always s

V

AIN

R

AIN

Figure 68. Typical application with ADC

V

DD

V

T

0.6 V

AINx 10-bit A/D conversion

V

T

0.6 V

ST7LITEU0x

124/146 DocID13474 Rev 3

ST7LITEU05 ST7LITEU09 Electrical characteristics

Table 69. ADC accuracy with V

DD

= 3.3 V to 5.5 V

Symbol

(1)

Parameter Conditions

|E

T

|

|E

O

|

|E

G

|

|E

D

|

|E

L

|

Total unadjusted error

Offset error

Gain error

Integral linearity error

Differential linearity error f f

CPU

ADC

= 8 MHz,

=4 MHz

(1)

1. Data based on characterization results over the whole temperature range.

Typ

2.0

0.9

1.0

1.2

1.1

Max

5.0

2.5

1.5

3.5

4.5

Unit

LSB

Symbol

(1)

Table 70. ADC accuracy with V

DD

= 2.7 V to 3.3 V

Parameter Conditions

|E

T

| Total unadjusted error

|E

O

| Offset error

|E

G

| Gain error

|E

D

| Differential linearity error

|E

L

| Integral linearity error f f

CPU

ADC

= 4 MHz,

= 2 MHz

(1)

1. Data based on characterization results over the whole temperature range.

Typ

1.9

0.9

0.8

1.4

1.1

Max

3.0

1.5

1.4

2.5

2.5

Unit

LSB

Table 71. ADC accuracy with V

DD

= 2.4 V to 2.7 V

Symbol

(1)

Parameter Conditions Typ Max Unit

|E

T

| Total unadjusted error

|E

O

| Offset error

|E

G

| Gain Error

|E

D

| Differential linearity error

|E

L

| Integral linearity error f f

CPU

ADC

= 2 MHz,

=1 MHz

(1)

1. Data based on characterization results at ambient temperature and above.

2.5

1.1

0.5

1.1

1.2

3.5

1.5

1.5

2.5

2.5

LSB

Obsolete Product(s) - Obsolete Product(s)

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Electrical characteristics ST7LITEU05 ST7LITEU09

1023

1022

1021

Figure 69. ADC accuracy characteristics

Digital Result ADCDR

E

G

1LSBIDEAL =

1024

(2)

E

T

(3)

7

6

5

4

3

2

1

0

V

SS

1

E

O

2 3 4 5

1 LSB

IDEAL

6

E

L

7

E

D

(1)

1021 1022 1023 1024

V

DD

V in

(LSB

IDEAL

)

1. Example of an actual transfer curve.

2. The ideal transfer curve.

3. End point correlation line.

4.

E

T

E

O

E

G

=Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.

=Offset error: deviation between the first actual transition and the first ideal one.

=Gain error: deviation between the last ideal transition and the last actual.

Obsolete Product(s) - Obsolete Product(s)

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ST7LITEU05 ST7LITEU09 Package characteristics

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.

ECOPACK is an ST trademark. ECOPACK® specifications are available at: www.st.com.

14.1 Package mechanical data

Figure 70. 8-lead very thin fine pitch dual flat no-lead package, package outline

D

INDEX AREA

(D/2 x E/2)

E

TOP VIEW

A

SIDE VIEW e b

INDEX AREA

(D/2 x E/2) L

E2

D2

BOTTOM VIEW

Obsolete Product(s) - Obsolete Product(s)

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145

Package characteristics ST7LITEU05 ST7LITEU09

Table 72. 8-lead very thin fine pitch dual flat no-lead package, mechanical data mm inches

(1)

Dim.

Min Typ Max Min Typ Max

D

D2

E

E2

A

A1

A3 b

0.80

0.00

-

0.25

-

3.50

-

1.96

0.90

0.02

0.20

0.30

4.50

3.65

3.50

2.11

1.00

0.05

-

0.35

-

3.75

-

2.21

0.0315

0.0098

-

-

-

0.1378

-

0.0772

e 0.80

-

L 0.30

0.40

0.50

0.0118

-

N

Number of pins

8

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0354

0.0008

0.0079

0.0118

0.1772

0.1437

0.1378

0.0831

0.0315

0.0157

0.0394

0.0020

-

0.0138

-

0.1476

-

0.0870

-

0.0197

Figure 71. 8-pin plastic small outline package - 150-mil width, package outline

D h x 45°

A1

A2 A

α

B L

C

E H

Obsolete Product(s) - Obsolete Product(s) e

128/146 DocID13474 Rev 3

ST7LITEU05 ST7LITEU09 Package characteristics

Table 73. 8-pin plastic small outline package - 150-mil width, mechanical data mm inches

(1)

Dim.

Min Typ Max Min Typ Max

E e

C

D

H h

α

L

-

N

A

A1

A2

B

1.35

0.10

1.10

0.33

0.19

4.80

3.80

-

5.80

0.25

0°

0.40

1.27

-

-

-

-

-

-

-

-

-

-

-

1.75

0.25

1.65

0.51

0.25

5.00

4.00

-

6.20

0.50

8°

0.0531

0.0039

0.0433

0.0130

0.0075

0.1890

0.1496

-

0.2283

0.0098

0°

1.27

0.0157

Number of pins

8

1. Values in inches are converted from mm and rounded to 4 decimal digits.

-

-

-

0.0500

-

-

-

-

-

-

-

-

0.0689

0.0098

0.0650

0.0201

0.0098

0.1969

0.1575

-

0.2441

0.0197

8°

0.0500

Figure 72. 8-pin plastic dual in-line outline package - 300-mil width, package outline ďϮ ď

Ϯ ϭ

Ğ

>

Ğ

Ğ

Đ

Obsolete Product(s) - Obsolete Product(s) ϭ ϭ

3',3%B9

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145

Package characteristics ST7LITEU05 ST7LITEU09

Table 74. 8-pin plastic dual in-line outline package, 300-mil width, mechanical data millimeters inches

(1)

Symbol

Typ Min Max Typ Min Max

E1 e eA eB

L

D

E b2 c

A

A1

A2 b

-

-

3.3

0.46

1.52

0.25

9.27

7.87

6.35

2.54

7.62

-

3.3

-

0.38

2.92

0.36

1.14

0.2

9.02

7.62

6.1

-

-

-

2.92

5.33

-

4.95

0.56

1.78

0.36

10.16

8.26

7.11

-

-

10.92

3.81

1. Values in inches are converted from mm and rounded to 4 decimal digits.

-

-

0.1299

0.0181

0.0598

0.0098

0.3650

0.3098

0.2500

0.1000

0.3000

-

0.1299

-

0.0150

0.1150

0.0142

0.0449

0.0079

0.3551

0.3000

0.2402

-

-

-

0.1150

0.2098

-

0.1949

0.0220

0.0701

0.0142

0.4000

0.3252

0.2799

-

-

0.4299

0.1500

Figure 73. 16-pin plastic dual in-line package, 300-mil width, package outline

E

A1

A2

A

L c b2 b e

E1 eB b3

D

Obsolete Product(s) - Obsolete Product(s)

130/146 DocID13474 Rev 3

ST7LITEU05 ST7LITEU09 Package characteristics

Table 75. 16-pin plastic dual in-line package, 300-mil width, mechanical data mm inches

(1)

Dim.

Min Typ Max Min Typ Max c

D b2 b3

A

A1

A2 b

1.14

0.76

0.20

18.67

-

0.38

2.92

0.36

1.52

0.99

0.25

19.18

-

-

3.30

0.46

1.78

1.14

0.36

19.69

5.33

-

4.95

0.56

D1 e

E

E1

0.13

-

7.62

6.10

-

2.54

7.87

6.35

-

-

8.26

7.11

0.0051

-

0.3000

0.2402

L 2.92

3.30

3.81

0.1150

eB 10.92

-

-

N

Number of pins

16

1. Values in inches are converted from mm and rounded to 4 decimal digits.

-

0.0150

0.1150

0.0142

0.0449

0.0299

0.0079

0.7350

-

0.1000

0.3098

0.2500

0.1299

-

-

-

0.1299

0.0181

0.0598

0.0390

0.0098

0.7551

-

-

0.3252

0.2799

0.1500

0.4299

0.2098

-

0.1949

0.0220

0.0701

0.0449

0.0142

0.7752

Obsolete Product(s) - Obsolete Product(s)

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145

Package characteristics ST7LITEU05 ST7LITEU09

Symbol

Table 76. Package characteristics

Ratings Value Unit

R

P

T thJA

Jmax

Dmax

Package thermal resistance

(junction to ambient)

Maximum junction temperature

Power dissipation

(2)

(1)

DIP8

SO8

DFN8 (on 4-layer PCB)

DFN8 (on 2-layer PCB)

-

DIP8

SO8

DFN8 (on 4-layer PCB)

DFN8 (on 2-layer PCB)

82

130

50

106

150

300

180

500

250

°C/W

°C mW

1. The maximum chip-junction temperature is based on technology characteristics.

2. The maximum power dissipation is obtained from the formula P

D

= (T

J of an application can be defined by the user with the formula: P

D

=P

INT

-T

A

) / R

+P

PORT thJA

. The power dissipation

where P is the chip internal power (I application.

DD x V

DD

) and P

PORT

Obsolete Product(s) - Obsolete Product(s)

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ST7LITEU05 ST7LITEU09

15

Device configuration and ordering information

Device configuration and ordering information

Each device is available for production in user programmable versions (Flash) as well as in factory coded versions (FASTROM).

ST7PLITEU05 and ST7PLITEU09 devices are Factory Advanced Service Technique ROM

(FASTROM) versions of ST7LITEU05 and ST7LITEU09 devices : they are factoryprogrammed XFlash devices.

ST7FLITEU05 and ST7FLITEU09 XFlash devices are XFlash versions of ST7LITEU05 and

ST7LITEU09 devices. They are shipped to customers with a default program memory content (FFh).

The FASTROM factory coded parts contain the code supplied by the customer. This implies that Flash devices have to be configured by the customer using the Option Bytes while the

FASTROM devices are factory-configured.

The two option bytes allow the hardware configuration of the microcontroller to be selected.

The option bytes can be accessed only in programming mode (for example using a standard

ST7 programming tool).

Bits 7:6 = CKSEL[1:0] Startup clock selection.

This bit is used to select the startup frequency. By default, the Internal RC is selected.

Table 77. Startup clock selection

Configuration CKSEL1

Internal RC as startup clock

AWU RC as a startup clock

Reserved

External clock on pin PA5

0

0

1

1

CKSEL0

0

1

0

1

Bit 5 = Reserved, must always be 1.

Obsolete Product(s) - Obsolete Product(s)

Bits 3:2 = LVD[1:0] Low voltage detection selection

These option bits enable the LVD block with a selected threshold as shown in

Table 78 .

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145

Device configuration and ordering information ST7LITEU05 ST7LITEU09

Table 78. LVD threshold configuration

Configuration

LVD Off

Highest voltage threshold

Medium voltage threshold

Lowest voltage threshold

LVD1

1

1

0

0

LVD0

1

0

1

0

Bit 1 = WDG SW Hardware or software watchdog

This option bit selects the watchdog type.

0: Hardware (watchdog always enabled)

1: Software (watchdog to be enabled by software)

Bit 0 = WDG HALT Watchdog reset on Halt

This option bit determines if a Reset is generated when entering Halt mode while the

Watchdog is active.

0: No Reset generation when entering Halt mode

1: Reset generation when entering Halt mode

Bits 7:4 = Reserved, must always be set.

Bits 3:2 = SEC[1:0] Sector 0 size definition

This option bit indicates the size of sector 0 according to the following table.

Sector 0 size

0.5K

1K

2K

Table 79. Sector 0 size selection

SEC0

0

0

1

SEC1

0

1

-

Bit 1 = FMP_R Readout protection

Readout protection, when selected provides a protection against program memory content extraction and against write access to Flash memory. Erasing the option bytes when the FMP_R option is selected causes the whole memory to be erased first, and the device can be reprogrammed. Refer to

Section 4.5: Memory protection

and the

Obsolete Product(s) - Obsolete Product(s)

0: Readout protection off

1: Readout protection on

Bit 0 = FMP_W FLASH write protection

This option indicates if the FLASH program memory is write protected.

0: Write protection off

1: Write protection on

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Warning: When this option is selected, the program memory (and the option bit itself) can never be erased or programmed again.

Default value

OPTION BYTE 0

7 0

Reserved

SEC

1

SEC

0

FMPR FMPW

OPTION BYTE 1

7 0

CKSEL

1

CKSEL

0

Reserved LVD1 LVD0

WDG

SW

WDG

HALT

1 1 1 1 0 0 0 0 0 0 1 0 1 1 1 1

Customer code is made up of the FASTROM contents and the list of the selected options (if any). The FASTROM contents are to be sent on diskette, or by electronic means, with the

S19 hexadecimal file generated by the development tool. All unused bytes must be set to

FFh. The selected options are communicated to STMicroelectronics using the correctly completed option list appended.

Refer to application note AN1635 for information on the counter listing returned by ST after code has been transferred.

The ST Microelectronics sales organization is pleased to provide detailed information on contractual points at request.

Obsolete Product(s) - Obsolete Product(s)

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Device configuration and ordering information ST7LITEU05 ST7LITEU09

Table 80. ST7LITEU0 ordering information scheme

Example

Family

ST7 microcontroller family

ST7 F LITEU09 M 6 TR

Version

F= Flash

P = FASTROM

Subfamily

LITE05

LITE09

Package

B= DIP (1)

M = SO

U = DFN

Temperature range

6 = -40 °C to 85 °C

3 = -40 °C to 125 °C

Shipping option

TR = Tape & Reel (SO8 or

DFN8)

Blank = Tube (DIP8 or SO8) or tray (DFN8)

1. DIP16 for development or tool prototyping purposes only, not orderable in production quantities.

further information on any aspect of this device, please contact the ST Sales Office nearest to you.

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ST7LITEU05 ST7LITEU09 Device configuration and ordering information

Figure 74. ST7LITEU0 FASTROM microcontroller option list

ST7LITEU0 FASTROM microcontroller option list

(Last update: October 2008)

Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference FASTROM Code*: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

*FASTROM code name is assigned by STMicroelectronics.

FASTROM code must be sent in .S19 format. .Hex extension cannot be processed.

Package (check only one option) :

PDIP8:

SO8:

DFN8:

Conditioning (check only one option) :

DIP package: [ ] Tube

SO package:

DFN package:

[ ] Tape & Reel

[ ] Tape & Reel

[ ] Tube

[ ] Tray (ST7LITEU09 only)

Special Marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _ "

Authorized characters are letters, digits, '.', '-', '/' and spaces only.

Maximum character count: PDIP8 / SO8 / DFN8 (8 char. max) : _ _ _ _ _ _ _ _

Temperature range: [ ] -40°C to +85°C [ ] -40°C to +125°C

Clock source selection:

Sector 0 size:

Readout protection:

FLASH write protection

LVD Reset

Watchdog selection:

Watchdog reset on Halt:

[ ] External clock

[ ] AWU RC oscillator

[ ] Internal RC oscillator

[ ] 0.5K

[ ] Disabled

[ ] Disabled

[ ] Disabled

[ ] 1K [ ] 2K

[ ] Enabled

[ ] Enabled

[ ] Highest threshold

[ ] Medium threshold

[ ] Lowest threshold

[ ] software activation

[ ] Disabled

[ ] hardware activation

[ ] Enabled

Comments : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply operating range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Obsolete Product(s) - Obsolete Product(s)

Signature: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Note: Not all configurations are available; see

Section 15.1: Option bytes on page 133 for

authorized option byte combinations.

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Development tools for the ST7 microcontrollers include a complete range of hardware systems and software tools from STMicroelectronics and third-party tool suppliers. The range of tools includes solutions to help you evaluate microcontroller peripherals, develop and debug your application, and program your microcontrollers.

ST offers complete, affordable starter kits . Starter kits are complete hardware/software tool packages that include features and samples to help you quickly start developing your application.

15.3.2 Development and debugging tools

Application development for ST7 is supported by fully optimizing C Compilers and the ST7

Assembler-Linker toolchain, which are all seamlessly integrated in the ST7 integrated development environments in order to facilitate the debugging and fine-tuning of your application. The Cosmic C Compiler is available in a free version that outputs up to

16 KBytes of code.

The range of hardware tools includes full-featured ST7-EMU3 series emulators and the low-cost RLink in-circuit debugger/programmer. These tools are supported by the ST7

Toolset from STMicroelectronics, which includes the STVD7 integrated development environment (IDE) with high-level language debugger, editor, project manager and integrated programming interface.

During the development cycle, the ST7-EMU3 series emulators and the RLink provide incircuit programming capability for programming the Flash microcontroller on your application board.

ST also provides a low-cost dedicated in-circuit programmer, the ST7-STICK , as well as

ST7 Socket Boards which provide all the sockets required for programming any of the devices in a specific ST7 sub-family on a platform that can be used with any tool with incircuit programming capability for ST7.

For production programming of ST7 devices, ST’s third-party tool partners also provide a complete range of gang and automated programming solutions, which are ready to integrate into your production environment.

Table 81 below lists the ordering codes for the ST7LITEU0x development and programming

tools. For additional ordering codes for spare parts and accessories, refer to the online product selector at www.st.com/mcu.

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ST7LITEU05 ST7LITEU09 Device configuration and ordering information

Supported products

Table 81. Development tool order codes for the ST7LITEU0x family

In-circuit debugger, RLink series

(1)

Programming tool

Emulator

Starter kit without demo board

Starter kit with demo board

In-circuit programmer

ST socket boards and

EPBs

STX-RLINK

(2)

ST7FLITE-SK/RAIS

(2)

ST7MDT10-EMU3

(3)

STX-RLINK

ST7-STICK

(4)(5)

ST7SB10-SU0

(4)

ST7FLITEU05

ST7FLITEU09

1. Available from ST or from Raisonance, www.raisonance.com

2. USB connection to PC

3. Includes connection kit for DIP16/SO16 only. See “How to order an EMU or DVP” in ST product and tool selection guide for connection kit ordering information

4. Add suffix /EU, /UK or /US for the power supply for your region

5. Parallel port connection to PC

Obsolete Product(s) - Obsolete Product(s)

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Identification

Table 82. ST7 application notes

Description

AN 980

AN1017

AN1041

AN1042

AN1044

AN1045

AN1046

AN1047

AN1048

AN 969

AN 970

AN 971

AN 972

AN 973

AN 974

AN 976

AN 979

Application Examples

AN1658

AN1720

Serial Numbering Implementation

Managing the Read-out Protection in Flash Microcontrollers

AN1755

AN1756

AN1812

Example Drivers

A High Resolution/precision Thermometer Using ST7 and NE555

Choosing a DALI Implementation Strategy with ST7DALI

A High Precision, Low Cost, Single Supply ADC for Positive and Negative Input Voltages

SCI Communication Between ST7 and PC

SPI Communication Between ST7 and EEPROM

I²C Communication Between ST7 and M24Cxx EEPROM

ST7 Software SPI Master Communication

SCI Software Communication with a PC Using ST72251 16-Bit Timer

Real Time Clock with ST7 Timer Output Compare

Driving a Buzzer Through ST7 Timer PWM Function

Driving an Analog Keyboard with the ST7 ADC

ST7 Keypad Decoding Techniques, Implementing Wake-Up on Keystroke

Using the ST7 Universal Serial Bus Microcontroller

Using ST7 PWM Signal to Generate Analog Output (Sinusoïd)

ST7 Routine for I²C Slave Mode Management

Multiple Interrupt Sources Management for ST7 MCUs

ST7 S/W Implementation of I²C Bus Master

UART Emulation Software

Managing Reception Errors with the ST7 SCI Peripherals

ST7 Software LCD Driver

AN1078 PWM Duty Cycle Switch Implementing True 0% & 100% Duty Cycle

AN1082

AN1083

Description of the ST72141 Motor Control Peripherals Registers Obsolete Product(s) - Obsolete Product(s)

AN1105 ST7 pCAN Peripheral Driver

AN1129 PWM Management for BLDC Motor Drives Using the ST72141

AN1130

AN1148

AN1149

AN1180

An Introduction to Sensorless Brushless DC Motor Drive Applications with the ST72141

Using the ST7263 for Designing a USB Mouse

Handling Suspend Mode on a USB Mouse

Using the ST7263 Kit to Implement a USB Game Pad

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ST7LITEU05 ST7LITEU09 Device configuration and ordering information

Identification

Table 82. ST7 application notes (continued)

Description

AN1276

AN1321

AN1325

AN1445

AN1475

AN1504

AN1602

AN1633

AN 910

AN 990

AN1077

AN1086

AN1103

AN1150

AN1151

AN1278

BLDC Motor Start Routine for the ST72141 Microcontroller

Using the ST72141 Motor Control MCU in Sensor Mode

Using the ST7 USB LOW-SPEED Firmware V4.x

Emulated 16-bit Slave SPI

Developing an ST7265X Mass Storage Application

Starting a PWM Signal Directly at High Level Using the ST7 16-bit Timer

16-bit Timing Operations Using ST7262 or ST7263B ST7 USB MCUs

Device Firmware Upgrade (DFU) Implementation in ST7 Non-USB Applications

AN1712

AN1713

AN1753

AN1947

Generating a High Resolution Sinewave Using ST7 PWMART

SMBus Slave Driver for ST7 I2C Peripherals

Software UART Using 12-bit ART

ST7MC PMAC Sine Wave Motor Control Software Library

General Purpose

AN1476

AN1526

Low Cost Power Supply for Home Appliances

ST7FLITE0 Quick Reference Note

AN1709

AN1752

Product Evaluation

EMC Design for ST Microcontrollers

ST72324 Quick Reference Note

Performance Benchmarking

ST7 Benefits vs Industry Standard

Overview of Enhanced CAN Controllers for ST7 and ST9 MCUs

U435 Can-Do Solutions for Car Multiplexing

Improved B-EMF detection for Low Speed, Low Voltage with ST72141

Benchmark ST72 vs PC16

Performance Comparison Between ST72254 & PC16F876

LIN (Local Interconnect Network) Solutions

Product Migration

Obsolete Product(s) - Obsolete Product(s)

AN1322 Migrating an Application from ST7263 Rev.B to ST7263B

AN1365 Guidelines for Migrating ST72C254 Applications to ST72F264

AN1604

AN2200

Product Optimization

How to Use ST7MDT1-TRAIN with ST72F264

Guidelines for Migrating ST7LITE1x Applications to ST7FLITE1xB

AN 982

AN1014

Using ST7 with Ceramic Resonator

How to Minimize the ST7 Power Consumption

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Identification

Table 82. ST7 application notes (continued)

Description

AN 986

AN 987

AN 988

AN1039

AN1071

AN1106

AN1179

AN1446

AN1015

AN1040

AN1070

AN1181

AN1324

AN1502

AN1529

AN1530

Software Techniques for Improving Microcontroller EMC Performance

Monitoring the Vbus Signal for USB Self-Powered Devices

ST7 Checksum Self-Checking Capability

Electrostatic Discharge Sensitive Measurement

Calibrating the RC Oscillator of the ST7FLITE0 MCU Using the Mains

Emulated Data EEPROM with ST7 HDFLASH Memory

Extending the Current & Voltage Capability on the ST7265 VDDF Supply

Accurate Timebase for Low-cost ST7 Applications with Internal RC Oscillator

AN1605

AN1636

AN1828

AN1946

Using an Active RC to Wakeup the ST7LITE0 from Power Saving Mode

Understanding and Minimizing ADC Conversion Errors

PIR (Passive Infrared) Detector Using the ST7FLITE05/09/SUPERLITE

Sensorless BLDC Motor Control and BEMF Sampling Methods with ST7MC

AN1953

AN1971

PFC for ST7MC Starter Kit

ST7LITE0 Microcontrolled Ballast

Programming and Tools

AN 978

AN 983

AN 985

ST7 Visual DeVELOP Software Key Debugging Features

Key Features of the Cosmic ST7 C-Compiler Package

Executing Code In ST7 RAM

Using the Indirect Addressing Mode with ST7

ST7 Serial Test Controller Programming

Starting with ST7 Assembly Tool Chain

ST7 Math Utility Routines

Half Duplex USB-to-Serial Bridge Using the ST72611 USB Microcontroller

Translating Assembly Code from HC05 to ST7

Programming ST7 Flash Microcontrollers in Remote ISP Mode (In-situ Programming)

Using the ST72521 Emulator to Debug an ST72324 Target Application

AN1477

AN1527

Emulated Data EEPROM with Xflash Memory

Obsolete Product(s) - Obsolete Product(s)

AN1575 On-Board Programming Methods for XFLASH and HDFLASH ST7 MCUs

AN1576 In-application Programming (IAP) Drivers for ST7 HDFLASH or XFLASH MCUs

AN1577

AN1601

AN1603

AN1635

AN1754

Device Firmware Upgrade (DFU) Implementation for ST7 USB Applications

Software Implementation for ST7DALI-EVAL

Using the ST7 USB Device Firmware Upgrade Development Kit (DFU-DK)

ST7 Customer ROM Code Release Information

Data Logging Program for Testing ST7 Applications via ICC

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Identification

Table 82. ST7 application notes (continued)

Description

AN1796

AN1900

AN1904

AN1905

Field Updates for FLASH Based ST7 Applications Using a PC Comm Port

Hardware Implementation for ST7DALI-EVAL

ST7MC Three-phase AC Induction Motor Control Software Library

ST7MC Three-phase BLDC Motor Control Software Library

System Optimization

AN1711 Software Techniques for Compensating ST7 ADC Errors

AN1827

AN2009

AN2030

Implementation of SIGMA-DELTA ADC with ST7FLITE05/09

PWM Management for 3-Phase BLDC Motor Drives Using the ST7FMC

Back EMF Detection During PWM On Time by ST7MC

Obsolete Product(s) - Obsolete Product(s)

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Revision history ST7LITEU05 ST7LITEU09

Date

Table 83. Document revision history

Revision Changes

19-Jan-07 0.1

Initial release

Added note 1 to Table 1 on page 16

Modified “A/D conversion” on page 86 and added

“Changing the conversion channel” on page 87

Updated Section 13.3.2 on page 102 ,

Section 13.3.3 on page 103

,

Section 13.8.1 on page 114 , and

Section 13.3.2 on page 102

Modified EOC bit description in Section 11.3.6 on page

87

Updated “Internal RC oscillator calibrated at 5.0 V” on page 103 and “Internal RC oscillator calibrated at 3.3 V” on page 104

03-May-07 1

Supply current curved updated in

Section 13.4 on page

105

Updated Section 13.4.1 on page 106

Added one R

AIN

value and modified note 3 in

Section 13.10 on page 124

Removed references to ST7LITEU02 part numbers

Modified reset configuration for pin n°6 in Table 1 on page 16

Modified Figure 14 on page 36 (added AVDTHCR)

Added Table 60 on page 112

Modified Table 81 on page 139 : added note 4 for

ST7MDT10-EMU3, removed references to DVP3 and modified starter kit part number.

Modified Table 59 on page 111 (N

RW

)

Modified “Electrostatic discharge (ESD)” on page 113

Modified temperature conditions for LU in Section on page 114

ADC accuracy maximum values inserted into tables in

“10-bit ADC characteristics” on page 124

IPU and RPU graphs updated, Figure 53

and Figure 54 on page 116

Supply characteristics graphs updated, Section 13.4 on page 105

RC oscillator consumption data table inserted,

Section 13.4.2 on page 107

Obsolete Product(s) - Obsolete Product(s) oscillator calibrated at 5.0 V” on page 103, “Internal RC oscillator calibrated at 5.0 V” on page 103

Consumption values for HALT mode inserted,

Section 13.4 on page 105

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ST7LITEU05 ST7LITEU09 Revision history

Date

Table 83. Document revision history

Revision Changes

31-Oct-08 2

Format of the document changed

Status of the document modified (datasheet instead of preliminary data)

One paragraph added below

Figure 66 on page 122

Section 13.7.3: Absolute maximum ratings (electrical sensitivity) on page 113 modified

Section 14.1: Package mechanical data on page 127

modified

Soldering information section removed

Section 15: Device configuration and ordering information on page 133

updated

07-Oct-16 3

– Deleted Table 1: Device summary

– Updated

Figure 9: Data EEPROM write operation

,

Figure 72: 8-pin plastic dual in-line outline package -

300-mil width, package outline and

Figure 74:

ST7LITEU0 FASTROM microcontroller option list

– Replaced Figure 74:ST7LITEU0 ordering information scheme by

Figure 80: ST7LITEU0 ordering information scheme

– Added dashes to empty cells on:

Table 9: Interrupt mapping

Table 37: ST7 addressing mode overview

Table 42: ST7 instruction set

Table 43: Illegal opcode detection

Table 48: Operating characteristics with LVD

Table 49: Operating characteristics with AVD

Table 51: Internal RC oscillator characteristics (5.0 V calibration)

Table 53: Supply current characteristics

Table 54: Internal RC oscillator supply characteristics

Table 56: General timings

Table 57: Auto-wakeup RC oscillator

Table 59: Flash program memory

Table 60: EEPROM data memory

Table 65: General characteristics

Table 66: Output driving current characteristics

Table 67: Asynchronous RESET pin characteristics

Obsolete Product(s) - Obsolete Product(s)

Table 72: 8-lead very thin fine pitch dual flat no-lead package, mechanical data

Table 74: 8-pin plastic dual in-line outline package, 300mil width, mechanical data

Table 75: 16-pin plastic dual in-line package, 300-mil width, mechanical data

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IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Obsolete Product(s) - Obsolete Product(s)

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2016 STMicroelectronics – All rights reserved

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