STMicroelectronics LIS2DTW12 Datasheet
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LIS2DTW12
Datasheet
MEMS digital output dual motion and temperature sensor
Product status link
LIS2DTW12
Product summary
Order code
Temperature range [°C]
Package
Packing
LIS2DTW12TR
-40 to +85
LGA-12
Tape and reel
Product label
Features
• Ultra-low power consumption: 50 nA in power-down mode, below 1 µA in active low-power mode
• Very low noise: down to 1.3 m g RMS in low-power mode
• 0.8 °C (typ. accuracy) embedded temperature sensor
• Multiple operating modes with multiple bandwidths
• Android stationary detection, motion detection
• Supply voltage, 1.62 V to 3.6 V
• Independent IO supply
• ±2 g /±4 g /±8 g /±16 g full scale
• High-speed I²C/SPI digital output interface
• Single data conversion on demand
• 16-bit accelerometer data output
• 12-bit temperature data output
• Self-test
• 32-level FIFO
• 10000 g high shock survivability
• ECOPACK , RoHS and “Green” compliant
Applications
• Fragile shipment tracking
• Motion and temperature monitoring in battery-powered devices
• Gesture recognition and gaming
• Motion-activated functions and user interfaces
• Display orientation
• Tap/double-tap recognition
• Free-fall detection
• Smart power saving for handheld devices
• Hearing aids
• Portable healthcare devices
• Wireless sensor nodes
• Motion-enabled metering devices
Description
The LIS2DTW12 is an ultra-low-power high-performance three-axis linear accelerometer and temperature sensor belonging to the “femto” family which leverages on the robust and mature manufacturing processes already used for the production of micromachined accelerometers.
The device has user-selectable full scales of ±2 g /±4 g /±8 g /±16 g and is capable of measuring accelerations with output data rates from 1.6 Hz to 1600 Hz.
The LIS2DTW12 has an embedded 0.8 °C (typ. accuracy) temperature sensor with
ODRs ranging from 50 to 1.6 Hz and resolution from 8 to 12 bits.
DS12825 - Rev 3 - July 2019
For further information contact your local STMicroelectronics sales office.
www.st.com
LIS2DTW12
The LIS2DTW12 has an integrated 32-level first-in, first-out (FIFO) buffer allowing the user to store data in order to limit intervention by the host processor.
The embedded self-test capability allows the user to check the functioning of the sensor in the final application.
The device has a dedicated internal engine to process motion and acceleration detection including free-fall, wakeup, highly configurable single/double-tap recognition, activity/inactivity, stationary/motion detection, portrait/landscape detection and 6D/4D orientation.
The LIS2DTW12 is available in a small thin plastic land grid array package (LGA) and it is guaranteed to operate over an extended temperature range from -40 °C to
+85 °C.
DS12825 - Rev 3 page 2/65
1
1.1
LIS2DTW12
Block diagram and pin description
Block diagram and pin description
Block diagram a
Figure 1. Block diagram
X+
Y+
Z+
MUX
Z-
Y-
X-
TEMPERATURE SENSOR
CHARG E
AMPLIFIE R
A/D
CONVERTER
CONTROL
LOGIC
SPI
CS
SCL/SPC
SDA/SDO/SDI
SDO/SA0
SELF TEST REFERENCE
TRIMMING
CIRCUITS
CLOCK
32 Level
FIFO
CONTROL LOGIC
&
INTERRUPT GEN.
INT1
INT2
DS12825 - Rev 3 page 3/65
1.2
LIS2DTW12
Pin description
Pin description
Figure 2. Pin connections
Z
1
VDDIO 10
VDD 9
GND 8
RES 7
11 12
6 5
1 SCL/SPC
2 CS
3 SDO/SA0
4 SDA/SDI/SDO
X Y
(TOPVIEW)
DIRECTION OF THE
DETECTABLE
ACCELERATIONS
(BOTTOM VIEW)
Table 1. Pin description
Pin#
2
3
1
4
9
10
11
12
5
6
7
8
Name
SCL
SPC
CS
SDO
SA0
SDA
SDI
SDO
NC
GND
RES
GND
VDD
VDD_IO Power supply for I/O pins
INT2
INT1
Function
I²C serial clock (SCL)
SPI serial port clock (SPC)
SPI enable
I²C/SPI mode selection
(1: SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled)
SPI serial data output (SDO)
I²C less significant bit of the device address (SA0)
I²C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
Internally not connected. Can be tied to VDD, VDDIO, or GND.
0 V supply
Connect to GND
0 V supply
Power supply
Interrupt pin 2. Clock input when selected in single data conversion on demand.
Interrupt pin 1
1. SDO/SA0 and CS pins are internally pulled up. Refer to
Table 2. Internal pull-up values (typ.) for SDO/SA0 and CS pins for
the internal pull-up values (typ).
DS12825 - Rev 3 page 4/65
Vdd_IO
1.7 V
1.8 V
2.5 V
3.6 V
Table 2. Internal pull-up values (typ.) for SDO/SA0 and CS pins
Resistor value for SDO/SA0 and CS pins
Typ. (kΩ)
54.4
49.2
30.4
20.4
LIS2DTW12
Pin description
DS12825 - Rev 3 page 5/65
LIS2DTW12
Mechanical and electrical specifications
2
Mechanical and electrical specifications
2.1
Mechanical characteristics
@ Vdd = 1.8 V, T = 25 °C unless otherwise noted. The product is factory calibrated at 1.8 V. The operational power supply range is from 1.62 V to 3.6 V.
Symbol
FS
Parameter
Measurement range
Table 3. Mechanical characteristics
Test conditions
So Sensitivity
@ FS ±2 g in High-Performance Mode and all low-power modes except Low-Power Mode 1
@ FS ±4 g in High-Performance Mode and all low-power modes except Low-Power Mode 1
@ FS ±8 g in High-Performance Mode and all low-power modes except Low-Power Mode 1
@ FS ±16 g in High-Performance Mode and all lowpower modes except Low-Power Mode 1
@ FS ±2 g in Low-Power Mode 1
@ FS ±4 g in Low-Power Mode 1
@ FS ±8 g in Low-Power Mode 1
@ FS ±16 g in Low-Power Mode 1
An
Noise density - High-performance
@ FS ±2 g
RMS
RMS noise - Low-Power Modes
@ FS ±2 g
Low-Power Mode 4
Low-Power Mode 3
Low-Power Mode 2
Low-Power Mode 1
TyOff Zerog
TCO Zero-g offset change vs. temperature
TCS Sensitivity change vs. temperature
ST Self-test positive difference
1. Typical specifications are not guaranteed.
2. Noise density is the same for all ODRs. Low-noise setting enabled.
3. RMS noise is the same for all ODRs. Low-noise setting enabled.
4. Values after factory calibration test and trimming.
70
Max.
±2
±4
±8
±16
0.244
0.488
0.976
1.952
0.976
1.952
3.904
7.808
90
1.3
1.8
2.4
4.5
±20
±0.2
0.01
1500
Unit g m g /digit
µ g /√Hz m g (RMS) m g m g /°C
%/°C m g
DS12825 - Rev 3 page 6/65
LIS2DTW12
Electrical characteristics
2.2
Electrical characteristics
@ Vdd = 1.8 V, T = 25 °C unless otherwise noted. The product is factory calibrated at 1.8 V. The operational power supply range is from 1.62 V to 3.6 V.
Table 4. Electrical characteristics
Symbol Parameter
Vdd Supply voltage
Vdd_IO I/O pins supply voltage (2)
Test conditions Min.
1.62
1.62
IddHR
IddLP
Current consumption in High-Performance Mode
Current consumption in Low-Power Mode
@ ODR range
12.5 Hz - 1600 Hz, 14-bit
ODR 100 Hz
ODR 50 Hz
ODR 12.5 Hz
ODR 1.6 Hz
Idd_PD Current consumption in power-down
V
IH
V
IL
Digital high-level input voltage
Digital low-level input voltage
V
OH
V
OL
Digital high-level output voltage
Digital low-level output voltage
I
OH
I
OL
0.8*Vdd_IO
VDD_IO - 0.2 V
1. Typical specifications are not guaranteed.
2. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses. In this condition the measurement chain is powered off.
3. Low-noise setting disabled.
4. Low-Power Mode 1. Low-noise setting disabled.
5. 4 mA is the maximum driving capability, ie. the maximum DC current that can be sourced/sunk by the digital pad in order to guarantee the correct digital output voltage levels V
OH
and V
OL
.
1.8
90
5
3
1
0.38
50
Max.
3.6
Vdd+0.1
Unit
V
V
µA
µA nA
V
0.2*Vdd_IO V
V
0.2 V V
DS12825 - Rev 3 page 7/65
LIS2DTW12
Temperature sensor characteristics
2.3
Temperature sensor characteristics
@ Vdd = 1.8 V, T = 25 °C unless otherwise noted.
Table 5. Temperature sensor characteristics
Symbol
Top
Tacc
TODR
Parameter
Operating temperature range
Temperature accuracy (0 °C to 70 °C)
Temperature accuracy (-40 °C to +85 °C)
Temperature refresh rate in High-Performance Mode for all ODRs or in low-power modes for ODRs equal to 200/100/50 Hz
Temperature refresh rate in low-power modes for ODR equal to 25 Hz
Temperature refresh rate in low-power modes for ODR equal to 12.5 Hz
Temperature refresh rate in low-power modes for ODR equal to 1.6 Hz
1. Typical specifications are not guaranteed.
Min.
-40
±0.8
±1.3
Max.
Unit
+85 °C
°C
50
25
12.5
1.6
Hz
DS12825 - Rev 3 page 8/65
LIS2DTW12
Communication interface characteristics
2.4
2.4.1
Communication interface characteristics
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 6. SPI slave timing values
Value
Symbol Parameter Unit
Min Max t c(SPC) f c(SPC) t su(CS) t h(CS) t su(SI) t h(SI) t v(SO) t h(SO) t dis(SO)
SPI clock cycle
SPI clock frequency
CS setup time
CS hold time
SDI input setup time
SDI input hold time
SDO valid output time
SDO output hold time
SDO output disable time
100
6
8
12
15
9
10
50
50
1. 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production.
ns
MHz ns
Figure 3. SPI slave timing diagram
CS t su(CS) t c(SPC) t h(CS)
SPC
SDI
SDO t su(SI)
MSB IN t h(SI) t v(SO)
MSB OUT t h(SO)
LSB IN t dis(SO)
LSB OUT
Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.
DS12825 - Rev 3 page 9/65
LIS2DTW12
Communication interface characteristics
2.4.2
I²C - inter-IC control interface
Subject to general operating conditions for Vdd and Top.
Table 7. I²C slave timing values
Symbol Parameter
Min Max f
(SCL) t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t h(ST) t su(SR) t su(SP) t w(SP:SR)
SCL clock frequency
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
START condition hold time
Repeated START condition setup time
STOP condition setup time
Bus free time between STOP and START condition
0.01
1. Data based on standard I²C protocol requirement, not tested in production.
0
4.7
4.0
250
4
4.7
4
4.7
100
3.45
Figure 4. I²C slave timing diagram
SDA
START t su(SR) t w(SP:SR)
REPEATED
START
START
0.6
0.6
0.6
1.3
I²C fast mode
Min Max
0 400
1.3
0.6
100
0.01
0.9
Unit kHz
µs ns
µs
µs t su(SDA) t h(SDA) t su(SP)
STOP
SCL t h(ST) t w(SCLL) t w(SCLH)
Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
DS12825 - Rev 3 page 10/65
LIS2DTW12
Communication interface characteristics
Table 8. I²C high-speed mode specifications at 1 MHz and 3.4 MHz
Mode
Fast mode plus
t
SU;STO
C b t
VD;DAT t
VD;ACK
V nL
V nH t
SP f
SCLH t
SU;STA t
HD;STA t
LOW t
HIGH t
SU;DAT t
HD;DAT t rCL
Symbol f
SCL t
HD;STA t
LOW t
HIGH t
SU;STA t
HD;DAT t
SU;DAT t rDA t fDA t rCL t fCL
SCL clock frequency
Parameter
Hold time (repeated) START condition
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Data hold time
Data setup time
Rise time of SDA signal
Fall time of SDA signal
Rise time of SCL signal
Fall time of SCL signal
Setup time for STOP condition
Capacitive load for each bus line
Data valid time
Data valid acknowledge time
Noise margin at low level
Noise margin at high level
Pulse width of spikes that must be suppressed by the input filter
SCLH clock frequency
Setup time for a repeated START condition
Hold time (repeated) START condition
Low period of the SCLH clock
High period of the SCLH clock
Data setup time
Data hold time
Rise time of SCLH signal t rCL1
Rise time of SCLH signal after a repeated START condition and after an acknowledge bit t fCL t rDA t fDA t
SU;STO
C b
V nH t
SP
Fall time of SCLH signal
Rise time of SDAH signal
Fall time of SDAH signal
Setup time for STOP condition
Capacitive load for each bus line
Noise margin at high level
Pulse width of spikes that must be suppressed by the input filter
1. Data based on characterization, not tested in production.
10
10
10
10
160
-
0.2Vdd
0
0
0
160
160
160
60
10
0
10
260
-
-
-
0.1Vdd
0.2Vdd
Min
0
260
500
260
260
0
50
-
120
120
20*Vdd/5.5 120
20*Vdd/5.5 120
-
-
-
Max Unit
1 MHz
-
-
ns
-
550 pF
450 ns
450
-
-
V
-
-
-
-
70
40
50 ns
3.4 MHz
ns
80
40
80
80
-
100 pF
V
10 ns
DS12825 - Rev 3 page 11/65
LIS2DTW12
Absolute maximum ratings
2.5
Note:
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Symbol
Vdd
Vdd_IO
Vin
A
POW
Table 9. Absolute maximum ratings
Ratings
Supply voltage
I/O pins supply voltage
Input voltage on any control pin
(CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0)
Acceleration (any axis, powered, Vdd = 1.8 V)
A
UNP
T
OP
T
STG
ESD
Acceleration (any axis, unpowered)
Operating temperature range
Storage temperature range
Electrostatic discharge protection
Maximum value
-0.3 to 4.8
-0.3 to 4.8
-0.3 to Vdd_IO +0.3
3000 g for 0.5 ms
10000 g for 0.2 ms
3000 g for 0.5 ms
10000 g for 0.2 ms
-40 to +85
-40 to +125
2 (HBM)
Unit
V
V
V
°C
°C g g g g kV
Supply voltage on any pin should never exceed 4.8 V.
This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part.
This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part.
DS12825 - Rev 3 page 12/65
LIS2DTW12
Terminology and functionality
3
Terminology and functionality
3.1
3.1.1
3.1.2
Terminology
Sensitivity
Sensitivity describes the gain of the sensor and can be determined by applying 1 g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the Earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and time. The sensitivity tolerance describes the range of sensitivities of a large population of sensors.
Zero-g level offset
Zerog level offset describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g on the X-axis and 0 g on the Y-axis whereas the Z-axis will measure 1 g . The output is ideally in the middle of the dynamic range of the sensor
(content of OUT registers 00h, data expressed as two’s complement number). A deviation from ideal value in this case is called Zerog level offset. Offset is to some extent a result of stress to the MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Zerog level offset change vs. temperature”.
DS12825 - Rev 3 page 13/65
LIS2DTW12
Functionality
3.2
3.2.1
Functionality
Operating modes
•
•
Two sets of operating modes have been designed to offer the customer a broad choice of noise/power consumption combinations:
Low-noise enabled (see
Table 10. Operating modes - low-noise setting disabled
Table 11. Operating modes - low-noise setting enabled
)
Writing the LOW_NOISE bit in CTRL6 (25h)
selects the operating mode (low-noise).
From each of these two sets, five operating modes have been designed:
• 1 High-Performance Mode: focus on low noise
• 4 Low-Power Modes: trade-off between noise and power consumption
These operating modes are selected by writing the MODE[1:0] and LP_MODE[1:0] bits in CTRL1 (20h)
.
Resolution [bit]
ODR [Hz]
BW [Hz]
Parameter
Table 10. Operating modes - low-noise setting disabled
High-Performance
Mode
14-bit
12.5 - 1600
ODR/2 (N/A for
1600 Hz),
ODR/4, ODR/10,
ODR/20
Low-Power
Mode 4
14-bit
1.6 - 200
180
ODR/4,
ODR/10,
ODR/20
Low-Power
Mode 3
14-bit
1.6 - 200
360
ODR/4,
ODR/10,
ODR/20
Low-Power
Mode 2
14-bit
1.6 - 200
720
ODR/4,
ODR/10,
ODR/20
Low-Power
Mode 1
12-bit
1.6 - 200
3200
ODR/4,
ODR/10,
ODR/20
Noise density [µ g /√Hz]
@ FS = ±2 g , ODR=200 Hz
ODR=1.6 Hz
ODR=12.5 Hz
ODR=25 Hz
Current consumption [µA]
@ Vdd=1.8 V
ODR=50 Hz
ODR=100 Hz
ODR=200 Hz
ODR=400, 800,
1600 Hz
110
90
90
90
-
90
90
90
160
16
32
63
0.65
4
8.5
-
210
0.55
2.5
4.5
9
17.5
34.5
-
300
0.45
1.6
3
5.5
10.5
20.5
-
550
3
5
10
0.38
1
1.5
-
DS12825 - Rev 3 page 14/65
LIS2DTW12
Functionality
Resolution [bit]
ODR [Hz]
BW [Hz]
Parameter
Table 11. Operating modes - low-noise setting enabled
High-Performance
Mode
14-bit
12.5 - 1600
ODR/2 (N/A for
1600 Hz),
ODR/4, ODR/10,
ODR/20
Low-Power
Mode 4
14-bit
1.6 - 200
180
ODR/4,
ODR/10,
ODR/20
Low-Power
Mode 3
Low-Power
Mode 2
14-bit
1.6 - 200
360
ODR/4,
ODR/10,
ODR/20
14-bit
1.6 - 200
720
ODR/4,
ODR/10,
ODR/20
Low-Power
Mode 1
12-bit
1.6 - 200
3200
ODR/4,
ODR/10,
ODR/20
Noise density [µ g /√Hz]
@ FS = ±2 g , ODR=200 Hz
ODR=1.6 Hz
ODR=12.5 Hz
ODR=25 Hz
Current consumption [µA]
@ Vdd=1.8 V
ODR=50 Hz
ODR=100 Hz
ODR=200 Hz
ODR=400, 800,
1600 Hz
90
-
120
120
120
120
120
120
130
0.7
5
10
20
39
77
-
180
0.6
3
6
11
21.5
42
-
240
0.5
2
3.5
7
13
25
-
450
0.4
1.1
2
3.5
6
12
-
DS12825 - Rev 3 page 15/65
LIS2DTW12
Functionality
3.2.2
Single data conversion on-demand mode
The device features a single data conversion on-demand mode which is valid for both sets of operating modes
(low-noise disabled or enabled) in the 4 low-power modes. This mode is enabled by writing the MODE[1:0] bits to
'10' in
. Low power modes are selected by writing the LP_MODE[1:0] bits in
The trigger for output data generation can be managed through the I²C/SPI or by applying a clock signal on the
INT2 pin acting here as an input by writing the SLP_MODE_ SEL bit in
• When SLP_MODE_SEL = '0', output data generation is triggered by the clock signal on the INT2 pin (see
Figure 5. Single data conversion on-demand functionality
).
• When SLP_MODE_SEL = '1', output data generation starts when the SLP_MODE_1 bit is set to '1' logic through the I²C/SPI. When XL data are available in the registers, this bit is automatically set to '0' and the device is ready for another triggered session.
Output data are generated according to the selected low-power mode.
When output data is saved in an output register or FIFO, the device goes to power-down mode and waits for a new trigger.
All ODRs in the range from 0 to up to 200 Hz are supported due to the INT2 clock input.
A DRDY signal or FIFO flags are available on the INT1 pin.
Power consumption is the same as that of standard low-power modes for the same ODR.
Figure 5. Single data conversion on-demand functionality
Trigger Signal (INT2 pin)
DRDY (INT1 pin)
T_on PD T_on
3.2.3
•
•
•
At the end of turn-on time T_on, the DRDY interrupt is activated, output data are available to be read and the device goes into power-down. T_on values depend on the low-power mode as follows:
T_on (typ.) =
• 1.20 ms for Low-Power Mode 1
1.70 ms for Low-Power Mode 2
2.30 ms for Low-Power Mode 3
3.55 ms for Low-Power Mode 4
Self-test
The self-test allows checking the sensor functionality without moving it. The self-test function is off when the selftest bits (ST) are programmed to ‘00’. When the self-test bits are changed, an actuation force is applied to the sensor, simulating a definite input acceleration. In this case the sensor outputs will exhibit a change in their DC levels which are related to the selected full scale through the device sensitivity. When the self-test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. If the output signals change within the amplitude specified in
Table 3. Mechanical characteristics
, then the sensor is working properly and the parameters of the interface chip are within the defined specifications.
DS12825 - Rev 3 page 16/65
LIS2DTW12
Functionality
3.2.4
3.2.5
3.2.6
Activity/Inactivity, Android stationary/motion-detection functions
The activity/inactivity function recognizes the device’s sleep state and allows reducing system power consumption.
and the
SLEEP_ON bit in WAKE_UP_THS (34h)
, the LIS2DTW12 automatically goes to 12.5 Hz ODR in the low-power mode previously selected by the LP_MODE[1:0] bits in
if the sleep state condition is detected and wakes up as soon as the interrupt event has been detected, increasing the output data rate and bandwidth.
With this feature the system may be efficiently switched from low-power mode to full performance depending on user-selectable positioning and acceleration events, thus ensuring power saving and flexibility.
The Android stationary/motion detection function only recognizes the device’s sleep state.
When the Android stationary/motion-detection function is activated by setting the STATIONARY bit in
, the LIS2DTW12 detects acceleration below a fixed threshold but does not change either
ODR or operating mode (High-Performance mode or Low-Power mode) after sleep state detection.
The Activity/Inactivity recognition function can use the high-pass filter or the offset outputs, this choice can be
made through the USR_OFF_ON_OUT bit in CTRL7 (3Fh) .
If the device is in sleep (inactivity/stationary) mode, when at least one of the axes exceeds the threshold in
, the device goes into a sleep-to-wake state (as wake-up).
For the activity/inactivity function, the device, in a wake-up state, will return to the operating mode (HP or LP) and
ODR before sleep state detection.
Activity/Inactivity, Android stationary/motion-detection threshold and duration can be configured in the following control registers:
•
•
High tap/double-tap user configurability
The device embeds the possibility to select the following parameters:
•
single axis or multiple axes in TAP_THS_Z (32h)
• axis priority in
threshold value of each axis in TAP_THS_X (30h) ,
TAP_THS_Y (31h) , and TAP_THS_Z (32h)
max time threshold between 2 consecutive taps for double-tap recognition, min time threshold between 2 consecutive taps to detect a new tap event in
Offset management
The user can manage offset in the output or for wakeup detection using dedicated embedded hardware (see
Section 5.1 Block diagram of filters
).
DS12825 - Rev 3 page 17/65
3.3
3.4
3.5
3.6
LIS2DTW12
Sensing element
Sensing element
A proprietary process is used to create a surface micromachined accelerometer. The technology allows processing suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. In order to be compatible with the traditional packaging techniques, a cap is placed on top of the sensing element to avoid blocking the moving parts during the molding phase of the plastic encapsulation. When an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor.
At steady-state the nominal value of the capacitors are a few pF and when an acceleration is applied, the maximum variation of the capacitive load is in the fF range.
IC interface
The complete measurement chain is composed of a low-noise capacitive amplifier which converts the capacitive unbalancing of the MEMS sensor into an analog voltage using an analog-to-digital converter.
The acceleration data may be accessed through an I²C/SPI interface thus making the device particularly suitable for direct interfacing with a microcontroller.
The LIS2DTW12 features a data-ready signal which indicates when a new set of measured acceleration data is available, thus simplifying data synchronization in the digital system that uses the device.
Factory calibration
The IC interface is factory-calibrated for sensitivity (So) and Zero-g level offset.
The trim values are stored inside the device in nonvolatile memory. Any time the device is turned on, the trimming parameters are downloaded into the registers to be used during active operation. This allows using the device without further calibration. If an accidental write occurs in the registers where trimming parameters are stored, the
can help to retrieve the correct trimming parameters from nonvolatile memory without the need to switch on/off the device. This bit is automatically reset at the end of the download operation. Setting this bit has no impact on the control registers.
Temperature sensor
in 12-bit mode.
Refer to
Table 5. Temperature sensor characteristics for the conversion factor.
DS12825 - Rev 3 page 18/65
4
LIS2DTW12
Application hints
Application hints
Figure 6. LIS2DTW12 electrical connections (top view)
SCL/SPC
CS
SDO/SA0
SDA/SDI/SDO
1
2
3
4
12 11
5 6
Vdd_IO
10
9
VDD
8
GND
7
RES
Vdd_IO
100nF
GND
Vdd
10µF
100nF
GND
HOST
I 2 C / SPI (3/4-w)
LIS2DTW12
I 2 C configuration
Vdd_IO
R pu
SCL
SDA
Pull-up to be added
R pu
=10kOhm
R pu
The device core is supplied through the Vdd line while the I/O pads are supplied through the Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF aluminum) should be placed as near as possible to pin 9 of the device (common design practice).
All the voltage and ground supplies must be present at the same time to have proper behavior of the IC (refer to
Figure 6. LIS2DTW12 electrical connections (top view)
). It is possible to remove Vdd while maintaining Vdd_IO without blocking the communication bus, in this condition the measurement chain is powered off.
The functionality of the device and the measured acceleration data are selectable and accessible through the I²C or SPI interfaces. When using the I²C, CS must be tied high (i.e. connected to Vdd_IO).
The functions, the threshold and the timing of the two interrupt pins (INT1 and INT2) can be completely programmed by the user through the I²C/SPI interface.
DS12825 - Rev 3 page 19/65
LIS2DTW12
Application hints
Table 12. Internal pin status
Pin # Name
1
2
SCL
SPC
CS
Function
I²C serial clock (SCL)
SPI serial port clock (SPC)
SPI enable
I²C/SPI mode selection
1: SPI idle mode / I²C communication enabled
0: SPI communication mode / I²C disabled
Serial data output (SDO)
I²C less significant bit of the device address (SA0)
3
SDO
SA0
4
SDA
SDI
SDO
NC
I²C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
Internally not connected. Can be tied to VDD, VDDIO, or GND.
5
6
7
8
GND 0 V supply
RES Connect to GND
GND 0 V supply
9 VDD Power supply
10 VDD_IO Power supply for I/O pins
11
12
INT2 Interrupt pin 2. Clock input when selected in single data conversion on demand.
INT1 Interrupt pin 1
Pin status
Default: push-pull output forced to Gnd
Default: push-pull output forced to Gnd
1. In order to disable the internal pull-up on the CS pin, write '1' to the CS_PU_DISC bit in
.
Default: open drain
Default: input with internal pull-up
Default: input with internal pull-up
Default: (SDA) input open drain
DS12825 - Rev 3 page 20/65
5
5.1
Digital main blocks
Block diagram of filters
Figure 7. Accelerometer chain
LIS2DTW12
Digital main blocks
DS12825 - Rev 3
Referring to Figure 7. Accelerometer chain
, the first block is the Low-Pass Filter 1 (LPF1) whose behavior is a function of the actual ODR and mode selected in
. The signal is then downsampled and can be either directly sent to the output registers or to the Low-Pass Filter 2 (LPF2) or High-Pass-Filter (HP) using the
BW_FILT[1:0] bits and FDS bit in
register values and the USR_OFF_W bit in
and send the result to the
output using the USR_OFF_ON_OUT bit in CTRL7 (3Fh)
.
In the high-pass path, it is possible to use the high-pass filter reference mode (HP) using the HP_REF_MODE bit
page 21/65
5.2
LIS2DTW12
Data stabilization time vs. ODR/device setting
Data stabilization time vs. ODR/device setting
Some data samples need to be discarded when changing the ODR in HP mode with ODR/2 bandwidth selection.
The table below provides the number of samples to be discarded in order to obtain valid usable data.
MODE[1:0] in
00
01
Table 13. Number of samples to be discarded
ODR [Hz]
BW_FILT[1:0] in
Samples to be discarded
-
12.5
25
50
100
200
400
800
1600
00
0
0
0
0
1
1
1
1
2
DS12825 - Rev 3 page 22/65
5.3
LIS2DTW12
FIFO
FIFO
•
•
•
•
•
The LIS2DTW12 embeds 32 slots of 14-bit data FIFO for each of the three output channels, X, Y and Z of the acceleration data. This allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO.
The internal FIFO allows collecting 32 samples (14-bit size data) for each axis.
When the FIFO mode is other than Bypass, reading the output registers (28h to 2Dh) returns the oldest FIFO sample set. In order to minimize communication between the master and slave, the address read may be
automatically incremented by the device by setting the IF_ADD_INC bit of CTRL2 (21h)
to '1'; the device rolls back to 0x28 when register 0x2D is reached.
This buffer can work according to the following 5 different modes:
Bypass mode
FIFO mode
Continuous-to-FIFO
Bypass-to-Continuous
Continuous
Each mode is selected by the FMode[2:0] bits in the FIFO_CTRL (2Eh) register.
Programmable FIFO threshold is selected in
FIFO_CTRL (2Eh) . Status and FIFO overrun events are available in
register and can be used to generate dedicated interrupts on the INT1 and INT2 pins
using the CTRL4_INT1_PAD_CTRL (23h)
registers.
FIFO_SAMPLES (2Fh) (FIFO_FTH) goes to '1' when the number of unread samples FIFO_SAMPLES (2Fh)
(Diff[5:0]) is greater than or equal to FTH[4:0] in
.
If FTH[4:0] is equal to '0',
FIFO_SAMPLES (2Fh) (FIFO_FTH) goes to '0'.
FIFO_SAMPLES (2Fh) (FIFO_OVR) is equal to '1' if a FIFO slot is overwritten.
‘000000’, FIFO is empty. When Diff[5:0] is equal to ‘100000’, FIFO is full and the unread samples are 32.
To guarantee the correct acquisition of data during the switching into and out of FIFO, the first sample acquired must be discarded.
When the FIFO threshold status flag is '0'-logic, FIFO filling is lower than the threshold level and when '1'-logic,
FIFO filling is equal to or higher than the threshold level.
DS12825 - Rev 3 page 23/65
LIS2DTW12
FIFO
5.3.1
5.3.2
5.3.3
Bypass mode
In Bypass mode (
(FMode [2:0])= 000), the FIFO is not operational, no data is collected in FIFO memory, and it remains empty with the only actual sample available in the output registers.
Bypass mode is also used to reset the FIFO when in FIFO mode.
For each channel only the first address is used. When new data is available, the old data is overwritten.
FIFO mode
until it is full, when 32 unread samples are stored in memory, data collecting is stopped.
To reset the FIFO content, Bypass mode should be written in the
FIFO_CTRL (2Eh) register, setting the FMODE
[2:0] bits to '000'. After this reset command, it is possible to restart FIFO mode, writing the value '001' in
(FMODE [2:0]).
The FIFO buffer can memorize 32 slots of X, Y and Z data.
Continuous mode
Continuous mode (
(FMode[2:0] = 110) provides a continuous FIFO update: when 32 unread samples are stored in memory, as new data arrives the oldest data is discarded and overwritten by the newer.
A FIFO threshold flag
FIFO_SAMPLES (2Fh) (FIFO_FTH) is asserted when the number of unread samples in
FIFO is greater than or equal to ( FIFO_CTRL (2Eh) FTH[4:0]).
It is possible to route FIFO_SAMPLES (2Fh)
(FTH) to the INT1 pin by writing the INT1_FTH bit to '1' in register
CTRL4_INT1_PAD_CTRL (23h) or to the INT2 pin by writing the INT2_FTH bit to '1' in register
is asserted.
In order to empty the FIFO before it is full, it is also possible to pull from FIFO the number of unread samples
available in FIFO_SAMPLES (2Fh)
(Diff[5:0]).
DS12825 - Rev 3 page 24/65
LIS2DTW12
FIFO
5.3.4
Continuous-to-FIFO mode
mode starts upon an internal trigger event. When the FIFO is full, data collecting is stopped. The trigger could be a single or double tap, wake-up, free-fall, 6D interrupt or any combination of these events, but every interrupt has to be routed on the corresponding pad to be used as a trigger.
Figure 8. Continuous-to-FIFO mode x i
,y i
,z i x i
,y i
,z i x
0 x
1 x
2 x
30 x
31 y
0 y
1 y
2 y
30 y
31 z
0 z
1 z
2 z
30 z
31 x
0 x
1 x
2 y
0 y
1 y
2 z
0 z
1 z
2 x
31 y
31 z
31
Continuous Mode
Trigger event
FIFO Mode
Figure 9. Trigger event to FIFO for Continuous-to-FIFO mode
DS12825 - Rev 3 page 25/65
LIS2DTW12
FIFO
5.3.5
Bypass-to-Continuous mode
starts in Continuous mode upon an internal trigger event, then the sample that follows the trigger is available in
FIFO. The trigger could be a single or double tap, wake-up, free-fall, 6D interrupt or any combination of these events, but every interrupt has to be routed on the corresponding pad to be used as a trigger.
Figure 10. Bypass-to-Continuous mode x i
,y i
,z i x i
,y i
,z i empty x
0 x
1 x
2 y
0 y
1 y
2 z
0 z
1 z
2 x
0 x
1 x
2 x
30 x
31 y
0 y
1 y
2 y
30 y
31 z
0 z
1 z
2 z
30 z
31 x
31 y
31 z
31
Bypass Mode
Trigger event
Continuous Mode
Figure 11. Trigger event to FIFO for Bypass-to-Continuous mode
DS12825 - Rev 3 page 26/65
6
6.1
LIS2DTW12
Digital interfaces
Digital interfaces
The registers embedded inside the LIS2DTW12 may be accessed through both the I²C and SPI serial interfaces.
The latter may be SW configured to operate either in 3-wire or 4-wire interface mode.
The serial interfaces are mapped to the same pins. To select/exploit the I²C interface, the CS line must be tied high (i.e. connected to Vdd_IO).
Pin name
CS
SCL
SPC
SDA
SDI
SDO
SA0
SDO
I²C serial interface
Table 14. Serial interface pin description
Pin description
SPI enable
I²C/SPI mode selection
(1: SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled)
I²C serial clock (SCL)
SPI serial port clock (SPC)
I²C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
I²C address selection (SA0)
SPI serial data output (SDO)
The LIS2DTW12 I²C is a bus slave. The I²C is employed to write data into registers whose content can also be read back.
The relevant I²C terminology is given in the table below.
Table 15. I²C terminology
Term
Transmitter The device which sends data to the bus
Receiver
Master
Slave
The device which receives data from the bus
Description
The device which initiates a transfer, generates clock signals and terminates a transfer
The device addressed by the master
There are two signals associated with the I²C bus: the serial clock line (SCL) and the Serial DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines must be connected to Vdd_IO through an external pull-up resistor. When the bus is free, both the lines are high.
The I²C interface is compliant with fast mode (400 kHz) I²C standards as well as with normal mode.
In order to disable the I²C block,
CTRL2 (21h) (I2C_DISABLE) = 1 must be set.
DS12825 - Rev 3 page 27/65
LIS2DTW12
I²C serial interface
6.1.1
I²C operation
The transaction on the bus is started through a START (ST) signal. A START condition is defined as a high-to-low transition on the data line while the SCL line is held high. After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master.
The Slave Address (SAD) associated to the LIS2DTW12 is 001100xb where the x bit is modified by the SA0/SDO pin in order to modify the device address. If the SA0/SDO pin is connected to the supply voltage, the address is
0011001b, otherwise if the SA0/SDO pin is connected to ground, the address is 0011000b. This solution permits to connect and address two different accelerometers to the same I²C lines.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received.
The I²C embedded inside the LIS2DTW12 behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent. Once a slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the 7 LSb represents the actual register address while the
CTRL2 (21h) (IF_ADD_INC) bit defines the address increment.
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated START (SR) condition must be issued after the two sub-address bytes. If the bit is ‘0’ (Write) the master will transmit to the slave with direction unchanged.
Table 16 explains how the SAD+Read/Write bit pattern is composed, listing all the possible
configurations.
Command
Read
Write
Read
Write
SAD[6:1]
001100
001100
001100
001100
Table 16. SAD+Read/Write patterns
SAD[0] = SA0
0
0
1
1
R/W
1
0
1
0
SAD+R/W
00110001 (31h)
00110000 (30h)
00110011 (33h)
00110010 (32h)
Master
Slave
ST
Table 17. Transfer when master is writing one byte to slave
SAD + W SUB DATA
SAK SAK SAK
SP
Master
Slave
Master
Slave
ST
Table 18. Transfer when master is writing multiple bytes to slave
SAD + W SUB DATA DATA
SAK SAK SAK SAK
ST
Table 19. Transfer when master is receiving (reading) one byte of data from slave
SAD + W SUB SR SAD + R NMAK
SAK SAK SAK DATA
SP
SP
Master ST
Table 20. Transfer when master is receiving (reading) multiple bytes of data from slave
SAD
+W
SUB SR SAD+R MAK MAK NMAK SP
DS12825 - Rev 3 page 28/65
LIS2DTW12
SPI bus interface
Slave
6.2
SAK SAK SAK DATA DATA DATA
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit (MSb) first. If a receiver can’t receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL low to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left high by the slave. The master can then abort the transfer. A low-to-high transition on the SDA line while the SCL line is high is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.
In the presented communication format MAK is Master acknowledge and NMAK is No Master Acknowledge.
SPI bus interface
The LIS2DTW12 SPI is a bus slave. The SPI allows writing to and reading from the registers of the device.
The serial interface interacts with the application using 4 wires: CS , SPC , SDI and SDO .
Figure 12. Read and write protocol
CS
SPC
SDI
SDO
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are respectively the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC .
Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling edges of SPC . The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS .
bit 0 : RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SDO at the start of bit 8.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
(IF_ADD_INC) bit is ‘1’, the address used to read/write data is increased at every block.
The function and the behavior of SDI and SDO remain unchanged.
DS12825 - Rev 3 page 29/65
LIS2DTW12
SPI bus interface
6.2.1
SPI read
Figure 13. SPI read protocol
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI read command is performed with 16 clock pulses. A multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one.
bit 0 : READ bit. The value is 1.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DO(7:0) (read mode). This is the data that will be read from the device (MSb first).
bit 16-...
: data DO(...-8). Additional data in multiple byte reads.
Figure 14. Multiple byte SPI read protocol (2-byte example)
CS
SPC
SDI
SDO
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14 DO13 DO12 DO11DO10 DO9 DO8
DS12825 - Rev 3 page 30/65
LIS2DTW12
SPI bus interface
6.2.2
SPI write
Figure 15. SPI write protocol
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
The SPI write command is performed with 16 clock pulses. A multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one.
bit 0 : WRITE bit. The value is 0.
bit 1 -7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DI(7:0) (write mode). This is the data that is written inside the device (MSb first).
bit 16-... : data DI(...-8). Additional data in multiple byte writes.
Figure 16. Multiple byte SPI write protocol (2-byte example)
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
DS12825 - Rev 3 page 31/65
LIS2DTW12
SPI bus interface
6.2.3
SPI read in 3-wire mode
3-wire mode is entered by setting the
CTRL2 (21h) (SIM) bit equal to ‘1’ (SPI serial interface mode selection).
Figure 17. SPI read protocol in 3-wire mode
CS
SPC
SDI/O
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI read command is performed with 16 clock pulses: bit 0 : READ bit. The value is 1.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
A multiple read command is also available in 3-wire mode.
DS12825 - Rev 3 page 32/65
7
LIS2DTW12
Register mapping
Register mapping
Name
OUT_T_L
OUT_T_H
WHO_AM_I
RESERVED
CTRL1
CTRL2
CTRL3
CTRL4_INT1_PAD_CTRL
CTRL5_INT2_PAD_CTRL
CTRL6
RESERVED
STATUS
OUT_X_L
OUT_X_H
OUT_Y_L
OUT_Y_H
OUT_Z_L
OUT_Z_H
FIFO_CTRL
FIFO_SAMPLES
TAP_THS_X
TAP_THS_Y
TAP_THS_Z
INT_DUR
WAKE_UP_THS
WAKE_UP_DUR
FREE_FALL
STATUS_DUP
WAKE_UP_SRC
TAP_SRC
SIXD_SRC
The table given below provides a list of the 8-bit registers embedded in the device and the corresponding addresses.
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R/W
R/W
-
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
-
R
R
Table 21. Register map
2A
2B
2C
2D
2E
25
26
27
28
29
2F
30
31
32
33
20
21
22
23
24
0D
0E
0F
10-1F
Register address
Hex Binary
00001101
00001110
00001111
00100000
00100001
00100010
00100011
00100100
00100101
00100111
00101000
00101001
00101010
00101011
00101100
00101101
00101110
00101111
00110000
00110001
00110010
00110011
Default
00000000
-
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
01000100
-
00000000
00000100
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
34
35
36
37
38
39
3A
00110100 00000000
00110101
00110110
00110111
00111000
00111001
00111010
00000000
00000000
00000000
00000000
00000000
00000000
Comment
Temp sensor output
Who am I ID
RESERVED
Control registers
RESERVED
Status data register
Output registers
FIFO control register
Unread samples stored in FIFO
Tap thresholds
Interrupt duration
Tap/double-tap selection, inactivity enable, wakeup threshold
Wakeup duration
Free-fall configuration
Status register
Wakeup source
Tap source
6D source
DS12825 - Rev 3 page 33/65
LIS2DTW12
Register mapping
Name
ALL_INT_SRC
X_OFS_USR
Y_OFS_USR
Z_OFS_USR
CTRL7
R
R/W
R/W
R/W
R/W
Register address
Hex Binary
3B
3C
3D
3E
3F
1. R = read-only register, R/W = readable/writable register
00111011
00111100
00111110
00000100
00000100
Default
00000000
00000000
00000000
00000000
00000000
Comment
Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.
DS12825 - Rev 3 page 34/65
8
8.1
8.2
8.3
LIS2DTW12
Register description
Register description
OUT_T_L (0Dh)
Temperature output register in 12-bit resolution (r).
TEMP3 TEMP2 TEMP1
Table 22. OUT_T_L register
TEMP0 0 0 0 0
TEMP[3:0]
Table 23. OUT_T_L register description
The 8 least significant bits of the temperature sensor output. 0 LSB = 25 °C. Sensitivity = 16 LSB/°C.
OUT_T_H (0Eh)
Temperature output register in 12-bit resolution (r).
TEMP11 TEMP10 TEMP9
Table 24. OUT_T_H register
TEMP8 TEMP7 TEMP6 TEMP5 TEMP4
TEMP[11:4]
Table 25. OUT_T_H register description
The 8 most significant bits of the temperature sensor output. 0 LSB = 25 °C. Sensitivity = 16 LSB/°C.
Together with
OUT_T_L (0Dh) , it forms the output value expressed as a 16-bit word in 2's complement
WHO_AM_I (0Fh)
Who_AM_I register (r). This register is a read-only register. Its value is fixed at 44h.
0 1
Table 26. WHO_AM_I register default values
0 0 0 1 0 0
DS12825 - Rev 3 page 35/65
8.4
LIS2DTW12
CTRL1 (20h)
CTRL1 (20h)
Control register 1 (r/w)
ODR3
ODR[3:0]
MODE[1:0]
LP_MODE[1:0]
ODR1
Table 27. Control register 1
ODR0 MODE1 MODE0 LP_MODE1 LP_MODE0 ODR2
Table 28. Control register 1 description
Output data rate and mode selection (see Table 29. Data rate configuration )
Mode selection (see Table 30. Mode selection )
Low-power mode selection (see Table 31. Low-power mode selection )
ODR[3:0] is used to set the power mode and ODR selection. The following table lists the bit settings for powerdown mode and each available frequency.
ODR[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Table 29. Data rate configuration
Power mode / data rate configuration
Power-down
High-Performance / Low-Power mode 12.5/1.6 Hz
High-Performance / Low-Power mode 12.5 Hz
High-Performance / Low-Power mode 25 Hz
High-Performance / Low-Power mode 50 Hz
High-Performance / Low-Power mode 100 Hz
High-Performance / Low-Power mode 200 Hz
High-Performance / Low-Power mode 400/200 Hz
High-Performance / Low-Power mode 800/200 Hz
High-Performance / Low-Power mode 1600/200 Hz
MODE[1:0]
00
01
10
11
Table 30. Mode selection
Mode and resolution
Low-Power Mode (12/14-bit resolution)
High-Performance Mode (14-bit resolution)
Single data conversion on demand mode (12/14-bit resolution)
-
LP_MODE[1:0]
00
01
10
Table 31. Low-power mode selection
Power mode and resolution
Low-Power Mode 1 (12-bit resolution)
Low-Power Mode 2 (14-bit resolution)
Low-Power Mode 3 (14-bit resolution)
DS12825 - Rev 3 page 36/65
8.5
LIS2DTW12
CTRL2 (21h)
LP_MODE[1:0]
11
CTRL2 (21h)
Control register 2 (r/w)
Power mode and resolution
Low-Power Mode 4 (14-bit resolution)
Table 32. Control register 2
BOOT
SOFT_
RESET
0
CS_PU_
DISC
1. This bit must be set to ‘0’ for the correct operation of the device.
BDU IF_ADD_ INC
I2C_
DISABLE
SIM
BOOT
Boot enables retrieving the correct trimming parameters from nonvolatile memory into registers where trimming parameters are stored.
Once the operation is over, this bit automatically returns to 0.
Default value: 0 (0: disabled; 1: enabled)
SOFT_RESET
Soft reset acts as reset for all control registers, then goes to 0.
Default value: 0 (0: disabled; 1: enabled)
CS_PU_DISC
BDU
IF_ADD_INC
I2C_DISABLE
SIM
Disconnect CS pull-up. Default value: 0
(0: pull-up connected to CS pin;
1: pull-up disconnected to CS pin)
Block data update. Default value: 0
(0: continuous update; 1: output registers not updated until MSB and LSB read)
Register address automatically incremented during multiple byte access with a serial interface (I²C or SPI).
Default value: 1 (0: disabled; 1: enabled)
Disable I²C communication protocol. Default value: 0
(0: SPI and I²C interfaces enabled; 1: I²C mode disabled)
SPI serial interface mode selection. Default value: 0
0: 4-wire interface; 1: 3-wire interface
The BDU bit is used to inhibit the update of the output registers until both upper and lower register parts are read.
In default mode (BDU = ‘0’) the output register values are updated continuously. When the BDU is activated
(BDU = ‘1’), the content of the output registers is not updated until both MSB and LSB are read which avoids reading values related to different sample times.
DS12825 - Rev 3 page 37/65
8.6
LIS2DTW12
CTRL3 (22h)
CTRL3 (22h)
Control register 3 (r/w)
ST2 ST1 PP_OD
Table 33. Control register 3
LIR H_LACTIVE 0
SLP_
MODE_SEL
SLP_
MODE_1
Table 34. Control register 3 description
ST[2:1]
PP_OD
Self-test enable. Default value: 00
(00: Self-test disabled; Other: see Table 35. Self-test mode selection
)
Push-pull/open-drain selection on interrupt pad. Default value: 0
(0: push-pull; 1: open-drain)
LIR
Latched Interrupt. Switches between latched ('1'-logic) and pulsed ('0'-logic) mode for function source signals and interrupts routed to pins (wakeup, single/double-tap). Default value: 0
(0: interrupt request not latched; 1: interrupt request latched)
H_LACTIVE
Interrupt active high, low. Default value: 0
(0: active high; 1: active low)
SLP_
MODE_SEL
Single data conversion on demand mode selection:
0: enabled with external trigger on INT2;
1: enabled by I²C/SPI writing SLP_MODE_1 to 1.
SLP_
MODE_1
Single data conversion on demand mode enable. When SLP_MODE_SEL = '1' and this bit is set to '1' logic, single data conversion on demand mode starts. When XL data are available in the registers, this bit is set to '0' automatically and the device is ready for another triggered session.
ST2
0
0
1
1
ST1
0
1
0
1
Table 35. Self-test mode selection
Self-test mode
-
Normal mode
Positive sign self-test
Negative sign self-test
DS12825 - Rev 3 page 38/65
8.7
LIS2DTW12
CTRL4_INT1_PAD_CTRL (23h)
CTRL4_INT1_PAD_CTRL (23h)
Control register 4 (r/w)
INT1_6D
INT1_
SINGLE_TAP
INT1_WU
Table 36. Control register 4
INT1_FF INT1_TAP
INT1_
DIFF5
INT1_6D
INT1_SINGLE_TAP
INT1_WU
INT1_FF
INT1_TAP
INT1_DIFF5
INT1_FTH
INT1_DRDY
Table 37. Control register 4 description
6D recognition is routed to INT1 pad. Default: 0
(0: disabled; 1: enabled)
Single-tap recognition is routed to INT1 pad. Default value: 0
(0: disabled; 1: enabled)
Wakeup recognition is routed to INT1 pad. Default value: 0
(0: disabled; 1: enabled)
Free-fall recognition is routed to INT1 pad. Default value: 0
(0: disabled; 1: enabled)
Double-tap recognition is routed to INT1 pad. Default value: 0
(0: disabled; 1: enabled)
FIFO full recognition is routed to INT1 pad. Default value: 0
(0: disabled; 1: enabled)
FIFO threshold interrupt is routed to INT1 pad. Default value: 0
(0: disabled; 1: enabled)
Data-Ready is routed to INT1 pad. Default value: 0
(0: disabled; 1: enabled)
INT1_
FTH
INT1_
DRDY
DS12825 - Rev 3 page 39/65
8.8
LIS2DTW12
CTRL5_INT2_PAD_CTRL (24h)
CTRL5_INT2_PAD_CTRL (24h)
Control register 5 (r/w)
INT2_
SLEEP_STATE
INT2_
SLEEP_CHG
INT2_
BOOT
Table 38. Control register 5
INT2_
DRDY_T
INT2_
OVR
INT2_
DIFF5
INT2_SLEEP_STATE
INT2_SLEEP_CHG
INT2 _BOOT
INT2_DRDY_T
INT2 _OVR
INT2_DIFF5
INT2 _FTH
INT2 _DRDY
Table 39. Control register 5 description
Enable routing of SLEEP_STATE on INT2 pad. Default value: 0
(0: disabled; 1: enabled)
Sleep change status routed to INT2 pad. Default value: 0
(0: disabled; 1: enabled)
Boot state routed to INT2 pad. Default value: 0
(0: disabled; 1: enabled)
Temperature data-ready is routed to INT2. Default value: 0
(0: disabled; 1: enabled)
FIFO overrun interrupt is routed to INT2 pad. Default value: 0
(0: disabled; 1: enabled)
FIFO full recognition is routed to INT2 pad. Default value: 0
(0: disabled; 1: enabled)
FIFO threshold interrupt is routed to INT2 pad. Default value: 0
(0: disabled; 1: enabled)
Data-ready is routed to INT2 pad. Default value: 0
(0: disabled; 1: enabled)
INT2_
FTH
INT2_
DRDY
DS12825 - Rev 3 page 40/65
LIS2DTW12
CTRL6 (25h)
8.9
CTRL6 (25h)
Control register 6 (r/w)
BW_FILT1 BW_FILT0 FS1
Table 40. Control register 6
FS0 FDS
LOW_
NOISE
BW_FILT[1:0]
FS[1:0]
FDS
LOW_NOISE
Bandwidth selection (see
Table 41. Digital filtering cutoff selection )
Full-scale selection (see Table 42. Full-scale selection
)
Filtered data type selection. Default value: 0
(0: low-pass filter path selected;
1: high-pass filter path selected)
Low-noise configuration.
(0: disabled; 1: enabled)
BW_FILT[1:0]
00
01
10
11
Table 41. Digital filtering cutoff selection
Bandwidth selection
ODR/2 (up to ODR = 800 Hz, 400 Hz when ODR = 1600 Hz)
ODR/4 (HP/LP)
ODR/10 (HP/LP)
ODR/20 (HP/LP)
FS[1:0]
00
01
10
11
Table 42. Full-scale selection
Full-scale selection
±2 g
±4 g
±8 g
±16 g
0 0
DS12825 - Rev 3 page 41/65
LIS2DTW12
STATUS (27h)
8.10
STATUS (27h)
Status register (r).
FIFO_THS WU_IA
SLEEP_
STATE
Table 43. STATUS register
DOUBLE_
TAP
SINGLE_
TAP
6D_IA FF_IA
Table 44. STATUS register description
FIFO_THS
WU_IA
SLEEP_
STATE
DOUBLE_
TAP
SINGLE_
TAP
6D_IA
FF_IA
DRDY
FIFO threshold status flag.
(0: FIFO filling is lower than threshold level; 1: FIFO filling is equal to or higher than the threshold level.)
Wakeup event detection status.
(0: Wakeup event not detected; 1: Wakeup event detected)
Sleep event status.
(0: Sleep event not detected; 1: Sleep event detected)
Double-tap event status
(0: Double-tap event not detected; 1: Double-tap event detected)
Single-tap event status
(0: Single-tap event not detected; 1: Single-tap event detected)
Source of change in position portrait/landscape/face-up/face-down.
(0: no event detected; 1: a change in position detected)
Free-fall event detection status.
(0: free-fall event not detected; 1: free-fall event detected)
Data-ready status.
(0: not ready; 1: X-, Y- and Z-axis new data available)
DRDY
DS12825 - Rev 3 page 42/65
LIS2DTW12
OUT_X_L (28h)
8.11
8.12
8.13
8.14
OUT_X_L (28h)
X-axis LSB output register (r).
Table 45. OUT_X_L register
X_L7 X_L6 X_L5 X_L4
1. If Low-Power Mode 1 is enabled, this bit is set to 0.
X_L2
0 0
it forms the output value expressed as a 16-bit word in 2's complement.
OUT_X_H (29h)
X-axis MSB output register (r).
X_H7 X_H6 X_H5
Table 46. OUT_X_H register
X_H4 X_H3 X_H2 X_H1 X_H0
register, it forms the output value expressed as a 16-bit word in 2's complement.
OUT_Y_L (2Ah)
Y-axis LSB output register (r).
Table 47. OUT_Y_L register
Y_L7 Y_L6 Y_L5 Y_L4
1. If Low-Power Mode 1 is enabled, this bit is set to 0.
0 0
register, it forms the output value expressed as a 16-bit word in 2's complement.
OUT_Y_H (2Bh)
Y-axis MSB output register (r).
Y_H7 Y_H6 Y_H5
Table 48. OUT_Y_H register
Y_H4 Y_H3 Y_H2 Y_H1 Y_H0
The 8 most significant bits of linear acceleration sensor Y-axis output. Together with the
it forms the output value expressed as a 16-bit word in 2's complement.
DS12825 - Rev 3 page 43/65
LIS2DTW12
OUT_Z_L (2Ch)
8.15
8.16
8.17
OUT_Z_L (2Ch)
Z-axis LSB output register (r).
Table 49. OUT_Z_L register
Z_L7 Z_L6 Z_L5 Z_L4
1. If Low-power Mode 1 is enabled, this bit is set to 0.
0 0
The 8 least significant bits of linear acceleration sensor Z-axis output. Together with the
it forms the output value expressed as a 16-bit word in 2's complement.
OUT_Z_H (2Dh)
Z-axis MSB output register (r).
Z_H7 Z_H6 Z_H5
Table 50. OUT_Z_H register
Z_H4 Z_H3 Z_H2 Z_H1 Z_H0
register, it forms the output value expressed as a 16-bit word in 2's complement.
FIFO_CTRL (2Eh)
FIFO control register (r/w).
FMode2 FMode1 FMode0
Table 51. FIFO_CTRL register
FTH4 FTH3 FTH2 FTH1 FTH0
Table 52. FIFO_CTRL register description
FMode[2:0]
FIFO mode selection bits. Default: 000. For further details refer to Table 53. FIFO mode selection
FTH[4:0] FIFO threshold level setting.
FMode[2:0]
000
001
010
011
100
101
110
111
Table 53. FIFO mode selection
Mode description
Bypass mode: FIFO turned off
FIFO mode: Stops collecting data when FIFO is full.
Reserved
Continuous-to-FIFO: Stream mode until trigger is deasserted, then FIFO mode
Bypass-to-Continuous: Bypass mode until trigger is deasserted, then FIFO mode
Reserved
Continuous mode: If the FIFO is full, the new sample overwrites the older sample.
Reserved
DS12825 - Rev 3 page 44/65
LIS2DTW12
FIFO_SAMPLES (2Fh)
8.18
8.19
FIFO_SAMPLES (2Fh)
FIFO_SAMPLES control register (r).
FIFO_
FTH
FIFO_
OVR
Diff5
Table 54. FIFO_SAMPLES register
Diff4 Diff3 Diff2 Diff1 Diff0
FIFO_FTH
FIFO_OVR
Diff[5:0]
Table 55. FIFO_SAMPLES register desription
FIFO threshold status flag.
(0: FIFO filling is lower than threshold level;
1: FIFO filling is equal to or higher than the threshold level.)
FIFO overrun status.
(0: FIFO is not completely filled;
1: FIFO is completely filled and at least one sample has been overwritten)
Represents the number of unread samples stored in FIFO.
(000000 = FIFO empty; 100000 = FIFO full, 32 unread samples).
TAP_THS_X (30h)
4D configuration enable and TAP threshold configuration (r/w).
4D_EN 6D_THS1 6D_THS0
Table 56. TAP_THS_X register
TAP_
THSX_4
TAP_
THSX_3
TAP_
THSX_2
TAP_
THSX_1
TAP_
THSX_0
Table 57. TAP_THS_X register description
4D_EN
4D detection portrait/landscape position enable.
(0: no position detected;
1: portrait/landscape detection and face-up/face-down position enabled).
6D_THS[1:0] Thresholds for 4D/6D function @ FS = ±2 g
(refer to Table 58. 4D/6D threshold setting FS @ ±2 g
)
TAP_THSX_[4:0] Threshold for TAP recognition @ FS = ±2 g on X direction
6D_THS[1:0]
00
01
10
11
Table 58. 4D/6D threshold setting FS @ ±2 g
Threshold decoding (degrees)
6 (80 degrees)
11 (70 degrees)
16 (60 degrees)
21 (50 degrees)
DS12825 - Rev 3 page 45/65
LIS2DTW12
TAP_THS_Y (31h)
8.20
8.21
TAP_THS_Y (31h)
TAP_
PRIOR_2
TAP_
PRIOR_1
Table 59. TAP_THS_Y register
TAP_
PRIOR_0
TAP_
THSY_4
TAP_
THSY_3
TAP_
THSY_2
TAP_
THSY_1
TAP_
THSY_0
Table 60. TAP_THS_Y register description
TAP_PRIOR_[2:0]
).
TAP_THSY_[4:0] Threshold for tap recognition @ FS = ±2 g on Y direction.
TAP_PRIOR_[2:0]
100
101
110
111
000
001
010
011
Table 61. Selection of axis priority for tap detection
Max priority
X
Y
Z
Z
X
Z
X
Y
Mid priority
Y
Z
X
Y
Z
Y
Y
X
TAP_THS_Z (32h)
TAP_X_
EN
TAP_Y_
EN
TAP_Z_
EN
Table 62. TAP_THS_Z register
TAP_
THSZ_4
TAP_
THSZ_3
TAP_
THSZ_2
TAP_
THSZ_1
Min priority
Z
X
Y
X
Y
X
Z
Z
TAP_
THSZ_0
TAP_X_EN
TAP_Y_EN
TAP_Z_EN
TAP_THSZ_[4:0]
Table 63. TAP_THS_Z register description
Enables X direction in tap recognition.
(0: disabled; 1: enabled)
Enables Y direction in tap recognition.
(0: disabled; 1: enabled)
Enables Z direction in tap recognition.
(0: disabled; 1: enabled)
Threshold for tap recognition @ FS = ±2 g on Z direction.
DS12825 - Rev 3 page 46/65
LIS2DTW12
INT_DUR (33h)
8.22
8.23
INT_DUR (33h)
Interrupt duration register (r/w).
LATENCY3 LATENCY2 LATENCY1
Table 64. INT_DUR register
LATENCY0 QUIET1 QUIET0 SHOCK1 SHOCK0
Table 65. INT_DUR register description
LATENCY[3:0]
Duration of maximum time gap for double-tap recognition. When double-tap recognition is enabled, this register expresses the maximum time between two successive detected taps to determine a double-tap event.
Default value is LATENCY[3:0] = 0000 (which is 16 * 1/ODR)
1 LSB = 32 * 1/ODR
QUIET[1:0]
Expected quiet time after a tap detection: this register represents the time after the first detected tap in which there must not be any overthreshold event.
Default value is QUIET[1:0] = 00 (which is 2 * 1/ODR)
1 LSB = 4 * 1/ODR
SHOCK[1:0]
Maximum duration of over-threshold event: this register represents the maximum time of an over-threshold signal detection to be recognized as a tap event.
Default value is SHOCK[1:0] = 00 (which is 4 * 1/ODR)
1 LSB = 8 *1/ODR
WAKE_UP_THS (34h)
Wakeup threshold register (r/w).
Table 66. WAKE_UP_THS register
SINGLE_
DOUBLE_
TAP
SLEEP_ ON WK_THS5 WK_THS4 WK_THS3 WK_THS 2 WK_THS 1 WK_THS 0
SINGLE_DOUBLE_ TAP
SLEEP_ON
WK_THS[5:0]
Table 67. WAKE_UP_THS register description
Enable single/double-tap event. Default value: 0
(0: only single-tap event is enabled; 1: single and double-tap events are enabled)
Sleep (inactivity) enable. Default value: 0
(0: sleep disabled; 1: sleep enabled)
Wakeup threshold, 6-bit unsigned 1 LSB = 1/64 of FS. Default value: 000000
DS12825 - Rev 3 page 47/65
LIS2DTW12
WAKE_UP_DUR (35h)
8.24
8.25
WAKE_UP_DUR (35h)
Wakeup and sleep duration configuration register (r/w).
FF_DUR5
WAKE_
DUR1
WAKE_
DUR0
Table 68. WAKE_UP_DUR register
STATIONARY SLEEP_ DUR3 SLEEP_ DUR2 SLEEP_ DUR1 SLEEP_ DUR0
FF_DUR5
WAKE_DUR[1:0]
STATIONARY
SLEEP_ DUR[3:0]
Table 69. WAKE_UP_DUR register description
Free-fall duration. In conjunction with FF_DUR [4:0] bit in FREE_FALL (36h) register.
1 LSB = 1 * 1/ODR
Wakeup duration. 1 LSB = 1 *1/ODR
Enable stationary detection / motion detection with no automatic ODR change when detecting stationary state.
Default value: 0
(0: disabled; 1: enabled)
Duration to go in sleep mode.
Default value is SLEEP_ DUR[3:0] = 0000 (which is 16 * 1/ODR).
1 LSB = 512 * 1/ODR
FREE_FALL (36h)
Free-fall duration and threshold configuration register (r/w).
FF_DUR4 FF_DUR3 FF_DUR2
Table 70. FREE_FALL register
FF_DUR1 FF_DUR0 FF_THS2 FF_THS1 FF_THS0
FF_DUR [4:0]
FF_THS [2:0]
Table 71. FREE_FALL register description
Free-fall duration. In conjunction with FF_DUR5 bit in
1 LSB = 1 * 1/ODR
Free-fall threshold @ FS = ±2 g (refer to
Table 72. FREE_FALL threshold decoding @ ± 2 g FS )
FF_THS[2:0]
000
001
010
011
100
101
110
111
Table 72. FREE_FALL threshold decoding @ ± 2 g FS
Threshold decoding (LSB)
5
7
8
10
11
13
15
16
DS12825 - Rev 3 page 48/65
LIS2DTW12
STATUS_DUP (37h)
8.26
STATUS_DUP (37h)
Event detection status register (r).
OVR DRDY_T
SLEEP_
STATE_IA
Table 73. STATUS_DUP register
DOUBLE_
TAP
SINGLE_
TAP
6D_IA FF_IA
OVR
DRDY_T
SLEEP_ STATE_IA
DOUBLE_ TAP
SINGLE_ TAP
6D_IA
FF_IA
DRDY
Table 74. STATUS_DUP register description
FIFO overrun status flag.
(0: FIFO is not completely filled;
1: FIFO is completely filled and at least one sample has been overwritten)
Temperature status.
(0: data not available; 1: a new set of data is available)
Sleep event status.
(0: Sleep event not detected; 1: Sleep event detected)
Double-tap event status:
(0: Double-tap event not detected; 1: Double-tap event detected)
Single-tap event status:
(0: Single-tap event not detected; 1: Single-tap event detected)
Source of change in position portrait/landscape/face-up/face-down.
(0: no event detected; 1: a change in position is detected)
Free-fall event detection status.
(0: free-fall event not detected; 1: free-fall event detected)
Data-ready status.
(0: not ready; 1: X-, Y- and Z-axis new data available)
DRDY
DS12825 - Rev 3 page 49/65
LIS2DTW12
WAKE_UP_SRC (38h)
8.27
WAKE_UP_SRC (38h)
Wakeup source register (r).
0 0 FF_IA
Table 75. WAKE_UP_SRC register
SLEEP_
STATE IA
WU_IA X_WU Y_WU
FF_IA
SLEEP_ STATE IA
WU_IA
X_WU
Y_WU
Z_WU
Table 76. WAKE_UP_SRC register description
Free-fall event detection status.
(0: FF event not detected; 1: FF event detected)
Sleep event status.
(0: Sleep event not detected; 1: Sleep event detected)
Wakeup event detection status.
(0: Wakeup event not detected; 1: Wakeup event is detected)
Wakeup event detection status on X-axis.
(0: Wakeup event on X not detected; 1: Wakeup event on X-axis is detected)
Wakeup event detection status on Y-axis.
(0: Wakeup event on Y not detected; 1: Wakeup event on Y-axis is detected)
Wakeup event detection status on Z-axis.
(0: Wakeup event on Z not detected; 1: Wakeup event on Z-axis is detected)
Z_WU
DS12825 - Rev 3 page 50/65
LIS2DTW12
TAP_SRC (39h)
8.28
TAP_SRC (39h)
Tap source register (r).
0 TAP_IA
SINGLE_
TAP
Table 77. TAP_SRC register
DOUBLE_
TAP
TAP_SIGN X_TAP Y_TAP Z_TAP
TAP_IA
SINGLE_TAP
DOUBLE_TAP
TAP_SIGN
X_TAP
Y_TAP
Z_TAP
Table 78. TAP_SRC register description
Tap event status.
(0: tap event not detected; 1: tap event detected)
Single-tap event status.
(0: single-tap event not detected; 1: single-tap event detected)
Double-tap event status.
(0: double-tap event not detected; 1: double-tap event detected)
Sign of acceleration detected by tap event.
(0: positive sign of acceleration detected; 1: negative sign of acceleration detected)
Tap event detection status on X-axis.
(0: Tap event on X not detected; 1: Tap event on X-axis is detected)
Tap event detection status on Y-axis.
(0: Tap event on Y not detected; 1: Tap event on Y-axis is detected)
Tap event detection status on Z-axis.
(0: Tap event on Z not detected; 1: Tap event on Z-axis is detected)
DS12825 - Rev 3 page 51/65
LIS2DTW12
SIXD_SRC (3Ah)
8.29
SIXD_SRC (3Ah)
6D source register (r).
0 6D_IA ZH
Table 79. SIXD_SRC register
ZL YH YL
ZL
YH
YL
XH
XL
6D_IA
ZH
Table 80. SIXD_SRC register description
Source of change in position portrait/landscape/face-up/face-down.
(0: no event detected; 1: a change in position is detected)
ZH over threshold.
(0: ZH does not exceed the threshold; 1: ZH is over the threshold)
ZL over threshold.
(0: ZL does not exceed the threshold; 1: ZL is over the threshold)
YH over threshold.
(0: YH does not exceed the threshold; 1: YH is over the threshold)
YL over threshold.
(0: YL does not exceed the threshold; 1: YL is over the threshold)
XH over threshold.
(0: XH does not exceed the threshold; 1: XH is over the threshold)
XL over threshold.
(0: XL does not exceed the threshold; 1: XL is over the threshold)
XH XL
DS12825 - Rev 3 page 52/65
LIS2DTW12
ALL_INT_SRC (3Bh)
8.30
ALL_INT_SRC (3Bh)
Reading this register, all related interrupt function flags routed to the INT pads are reset simultaneously.
0 0
Table 81. ALL_INT_SRC register
SLEEP_
CHANGE_IA
6D_IA
DOUBLE_
TAP
SINGLE_
TAP
WU_IA FF_IA
SLEEP_CHANGE_IA
6D_IA
DOUBLE_TAP
SINGLE_TAP
WU_IA
FF_IA
Table 82. ALL_INT_SRC register description
Sleep change status.
(0: Sleep change not detected; 1: Sleep change detected)
Source of change in position portrait/landscape/face-up/face-down.
(0: no event detected; 1: a change in position detected)
Double-tap event status.
(0: double-tap event not detected; 1: double-tap event detected)
Single-tap event status.
(0: single-tap event not detected; 1: single-tap event detected)
Wakeup event detection status.
(0: wakeup event not detected; 1: wakeup event detected)
Free-fall event detection status.
(0: free-fall event not detected; 1: free-fall event detected)
DS12825 - Rev 3 page 53/65
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X_OFS_USR (3Ch)
8.31
8.32
8.33
X_OFS_USR (3Ch)
X_OFS_
USR_7
X_OFS_
USR_6
X_OFS_
USR_5
Table 83. X_OFS_USR register
X_OFS_
USR_4
X_OFS_
USR_3
X_OFS_
USR_2
X_OFS_
USR_1
X_OFS_
USR_0
X_OFS_USR_[7:0]
Y_OFS_USR (3Dh)
Table 84. X_OFS_USR register description
Two's complement user offset value on X-axis data, used for wakeup function.
Y_OFS_
USR_7
Y_OFS_
USR_6
Y_OFS_
USR_5
Table 85. Y_OFS_USR register
Y_OFS_
USR_4
Y_OFS_
USR_3
Y_OFS_
USR_2
Y_OFS_
USR_1
Y_OFS_
USR_0
Y_OFS_USR_[7:0]
Z_OFS_USR (3Eh)
Table 86. Y_OFS_USR register description
Two's complement user offset value on Y-axis data, used for wakeup function.
Z_OFS_
USR_7
Z_OFS_
USR_6
Z_OFS_
USR_5
Table 87. Z_OFS_USR register
Z_OFS_
USR_4
Z_OFS_
USR_3
Z_OFS_
USR_2
Z_OFS_
USR_1
Z_OFS_
USR_0
Z_OFS_USR_[7:0]
Table 88. Z_OFS_USR register description
Two's complement user offset value on Z-axis data, used for wakeup function.
DS12825 - Rev 3 page 54/65
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CTRL7 (3Fh)
8.34
CTRL7 (3Fh)
DRDY_
PULSED
INT2_ON_
INT1
INTERRUPTS
_ENABLE
Table 89. CTRL7 register
USR_OFF
_ON_OUT
USR_OFF
_ON_WU
USR_
OFF _W
HP_REF
_MODE
LPASS_
ON6D
Table 90. CTRL7 register description
DRDY_PULSED
INT2_ON_INT1
Switches between latched and pulsed mode for data ready interrupt.
(0: latched mode is used; 1: pulsed mode enabled for data-ready)
Signal routing.
(1: all signals available only on INT2 are routed on INT1)
INTERRUPTS_ENABLE Enable interrupts.
USR_OFF_ON_OUT
USR_OFF_ON_WU
Enable application of user offset value on XL output data registers.
FDS bit in
CTRL6 (25h) must be set to '0'-logic (low-pass path selected).
Enable application of user offset value on XL data for wakeup function only.
USR_OFF_W
HP_REF_MODE
LPASS_ON6D
Selects the weight of the user offset words specified by X_OFS_USR_[7:0], Y_OFS_USR_[7:0] and
Z_OFS_USR_[7:0] bits.
(0: 977 µg/LSB; 1: 15.6 mg/LSB)
High-pass filter reference mode enable.
(0: high-pass filter reference mode disabled (default);
1: high-pass filter reference mode enabled)
(0: ODR/2 low pass filtered data sent to 6D interrupt function (default);
1: LPF2 output data sent to 6D interrupt function)
DS12825 - Rev 3 page 55/65
9
9.1
9.2
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Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com
. ECOPACK is an ST trademark.
Soldering information
The LGA package is compliant with the ECOPACK ® , RoHS and “Green” standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020.
Land pattern and soldering recommendations are available at www.st.com.
LGA-12 package information
Figure 18. LGA-12 2.0 x 2.0 x 0.7 mm package outline and mechanical data
DS12825 - Rev 3
ITEM
Length [L]
Width [W]
Height [H]
Dimensions are in millimeter unless otherwise specified
General Tolerance is +/-0.15mm unless otherwise specified
OUTER DIMENSIONS
DIMENSION [mm]
2
2
0.7 MAX
TOLERANCE [mm]
±0.1
±0.1
/
DM00170568_2 page 56/65
9.3
LGA-12 packing information
Figure 19. Carrier tape information for LGA-12 package
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LGA-12 packing information
Figure 20. LGA-12 package orientation in carrier tape
DS12825 - Rev 3 page 57/65
Revision history
Date
07-Jan-2019
03-May-2019
02-Jul-2019
Revision
1
2
3
Table 91. Document revision history
Changes
Initial release
Updated Figure 19. Carrier tape information for LGA-12 package
Updated OUT_T_L (0Dh) and OUT_T_H (0Eh)
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Contents
Contents
DS12825 - Rev 3 page 59/65
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Contents
DS12825 - Rev 3 page 60/65
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Contents
DS12825 - Rev 3 page 61/65
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List of tables
List of tables
DS12825 - Rev 3 page 62/65
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List of tables
DS12825 - Rev 3 page 63/65
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List of figures
List of figures
DS12825 - Rev 3 page 64/65
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IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2019 STMicroelectronics – All rights reserved
DS12825 - Rev 3 page 65/65
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