STMicroelectronics ASM330LHH Datasheet

ASM330LHH

LGA-14L

Typ: 2.5 x 3.0 x 0.83 mm

3

Features

 AEC-Q100 qualified

 Extended temperature range from -40 to +105 ° C

 Embedded compensation for high stability over temperature

 Accelerometer user-selectable full scale up to

±16 g

 Extended gyroscope range from ±125 to

±4000 dps

 SPI & I²C host serial interface

 Six-channel synchronized output to enhance accuracy of dead-reckoning algorithms

 Smart programmable interrupts

 Embedded 3 kbytes FIFO available to underload host processor

 ECOPACK, RoHS and “Green” compliant

Automotive 6-axis inertial module:

3D accelerometer and 3D gyroscope

Datasheet

-

production data

Description

The ASM330LHH is a system-in-package featuring a

3D digital accelerometer and a 3D digital gyroscope with an extended temperature range up to +105 ° C and designed to address automotive non-safety applications.

ST’s family of MEMS sensor modules leverages the robust and mature manufacturing processes already used for the production of micromachined accelerometers and gyroscopes to serve both the automotive and consumer market. The ASM330LHH is

AEC-Q100 compliant and industrialized through a dedicated MEMS production flow to meet automotive reliability standards. All the parts are fully tested with respect to temperature to ensure the highest quality level.

The sensing elements are manufactured using ST’s proprietary micromachining processes, while the IC interfaces are developed using CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the characteristics of the sensing element.

The ASM330LHH has a full-scale acceleration range of

±2/±4/±8/±16 g and a wide angular rate range of

±125/±250/±500/±1000/±2000/±4000 dps that enables its usage in a broad range of automotive applications.

All the design aspects of the ASM330LHH have been optimized to reach superior output stability, extremely low noise and full data synchronization to the benefit of sensor-assisted applications like dead reckoning and sensor fusion.

The ASM330LHH is available in a 14-lead plastic land grid array (LGA) package.

Applications

 Dead reckoning (DR)

 Vehicle-to-everything (V2X)

 Telematics, eTolling

 Anti-theft systems

 Impact detection and crash reconstruction

 Motion-activated functions

 Driving comfort

 Vibration monitoring and compensation

Part number

Table 1. Device summary

Temp. range [°C]

Package Packing

ASM330LHH -40 to +105

ASM330LHHTR -40 to +105

LGA-14L

(2.5 x 3.0 x 0.83 mm 3 )

Tray

Tape &

Reel

May 2020

This is information on a product in full production.

DocID031239 Rev 4 1/84 www.st.com

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Contents

Contents

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6

ASM330LHH

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Embedded low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1

Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.2

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3

Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.4

Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.4.1

4.4.2

SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

I²C - inter-IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.5

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.6

Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.6.1

4.6.2

Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Zero-g and zero-rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1

I²C/SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1.1

5.1.2

I²C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.1

Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.2

Gyroscope power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.3

Accelerometer power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.4

Block diagram of filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.4.1

6.4.2

Block diagram of the gyroscope filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Block diagrams of the accelerometer filters . . . . . . . . . . . . . . . . . . . . . . 32

6.5

FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.5.1

6.5.2

Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

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6.5.3

6.5.4

6.5.5

6.5.6

6.5.7

Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Continuous-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Bypass-to-Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Bypass-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

FIFO reading procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.1

ASM330LHH electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.1

PIN_CTRL (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.2

FIFO_CTRL1 (07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.3

FIFO_CTRL2 (08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.4

FIFO_CTRL3 (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9.5

FIFO_CTRL4 (0Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.6

COUNTER_BDR_REG1 (0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.7

COUNTER_BDR_REG2 (0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.8

INT1_CTRL (0Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

9.9

INT2_CTRL (0Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

9.10

WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

9.11

CTRL1_XL (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

9.12

CTRL2_G (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

9.13

CTRL3_C (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9.14

CTRL4_C (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

9.15

CTRL5_C (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9.16

CTRL6_C (15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

9.17

CTRL7_G (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

9.18

CTRL8_XL (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

9.19

CTRL9_XL (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

9.20

CTRL10_C (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

9.21

ALL_INT_SRC (1Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9.22

WAKE_UP_SRC (1Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9.23

D6D_SRC (1Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

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9.24

STATUS_REG (1Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

9.25

OUT_TEMP_L (20h), OUT_TEMP_H (21h) . . . . . . . . . . . . . . . . . . . . . . . 60

9.26

OUTX_H_G (23h), OUTX_L_G (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

9.27

OUTY_H_G (25h), OUTY_L_G (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

9.28

OUTZ_H_G (27h), OUTZ_L_G (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

9.29

OUTX_H_A (29h), OUTX_L_A (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

9.30

OUTY_H_A (2Bh), OUTY_L_A (2Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

9.31

OUTZ_H_A (2Dh), OUTZ_L_A (2Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

9.32

FIFO_STATUS1 (3Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

9.33

FIFO_STATUS2 (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

9.34

TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

9.35

INT_CFG0 (56h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

9.36

INT_CFG1 (58h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

9.37

THS_6D (59h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

9.38

WAKE_UP_THS (5Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

9.39

WAKE_UP_DUR (5Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

9.40

FREE_FALL (5Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

9.41

MD1_CFG (5Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

9.42

MD2_CFG (5Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

9.43

INTERNAL_FREQ_FINE (63h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

9.44

X_OFS_USR (73h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

9.45

Y_OFS_USR (74h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

9.46

Z_OFS_USR (75h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

9.47

FIFO_DATA_OUT_TAG (78h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

9.48

FIFO_DATA_OUT_X_H (7Ah) and FIFO_DATA_OUT_X_L (79h) . . . . . . 72

9.49

FIFO_DATA_OUT_Y_H (7Ch) and FIFO_DATA_OUT_Y_L (7Bh) . . . . . 72

9.50

FIFO_DATA_OUT_Z_H (7Eh) and FIFO_DATA_OUT_Z_L (7Dh) . . . . . . 72

Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

10.1

Gyroscope Angular Random Walk (ARW) . . . . . . . . . . . . . . . . . . . . . . . . 73

10.2

Gyroscope Bias Instability (BI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

10.3

Gyroscope nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

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Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

12.1

LGA-14L package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

12.2

LGA-14 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

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List of tables

List of tables

ASM330LHH

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

SPI slave timing values (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

I²C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 9.

Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 10.

I²C terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 11.

SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 12.

Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 13.

Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 14.

Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 25

Table 15.

Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 25

Table 16.

Gyroscope LPF2 bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 17.

Internal pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 18.

Registers address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 19.

PIN_CTRL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 20.

PIN_CTRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 21.

FIFO_CTRL1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 22.

FIFO_CTRL1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 23.

FIFO_CTRL2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 24.

FIFO_CTRL2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 25.

FIFO_CTRL3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 26.

FIFO_CTRL3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 27.

FIFO_CTRL4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 28.

FIFO_CTRL4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 29.

COUNTER_BDR_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 30.

COUNTER_BDR_REG1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 31.

COUNTER_BDR_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 32.

COUNTER_BDR_REG2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 33.

INT1_CTRL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 34.

INT1_CTRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 35.

INT2_CTRL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 36.

INT2_CTRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 37.

WhoAmI register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 38.

CTRL1_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 39.

CTRL1_XL register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 40.

CTRL2_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 41.

CTRL2_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 42.

CTRL3_C register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 43.

CTRL3_C register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 44.

CTRL4_C register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 45.

CTRL4_C register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 46.

CTRL5_C register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 47.

CTRL5_C register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 48.

Angular rate sensor self-test mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6/84 DocID031239 Rev 4

ASM330LHH List of tables

Table 49.

Linear acceleration sensor self-test mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 50.

CTRL6_C register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 51.

CTRL6_C register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 52.

Trigger mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 53.

Gyroscope LPF1 bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 54.

CTRL7_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 55.

CTRL7_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 56.

CTRL8_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 57.

CTRL8_XL register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 58.

Accelerometer bandwidth configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 59.

CTRL9_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 60.

CTRL9_XL register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 61.

CTRL10_C register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 62.

CTRL10_C register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 63.

ALL_INT_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 64.

ALL_INT_SRC register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 65.

WAKE_UP_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 66.

WAKE_UP_SRC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 67.

D6D_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 68.

D6D_SRC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 69.

STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 70.

STATUS_REG register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 71.

OUT_TEMP_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 72.

OUT_TEMP_H register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 73.

OUT_TEMP register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 74.

OUTX_H_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 75.

OUTX_L_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 76.

OUTX_H_G, OUTX_L_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 77.

OUTY_H_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 78.

OUTY_L_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 79.

OUTY_H_G, OUTY_L_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 80.

OUTZ_H_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 81.

OUTZ_L_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 82.

OUTZ_H_G, OUTZ_L_G register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 83.

OUTX_H_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 84.

OUTX_L_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 85.

OUTX_H_A, OUTX_L_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 86.

OUTY_H_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 87.

OUTY_L_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 88.

OUTY_H_A, OUTY_L_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 89.

OUTZ_H_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 90.

OUTZ_L_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 91.

OUTZ_H_A, OUTZ_L_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 92.

FIFO_STATUS1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 93.

FIFO_STATUS1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 94.

FIFO_STATUS2 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 95.

FIFO_STATUS2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 96.

TIMESTAMP3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 97.

TIMESTAMP2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 98.

TIMESTAMP1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 99.

TIMESTAMP0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 100. TIMESTAMPx register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

DocID031239 Rev 4 7/84

84

List of tables ASM330LHH

Table 101. INT_CFG0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 102. INT_CFG0 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 103. INT_CFG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 104. INT_CFG1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 105. THS_6D register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 106. THS_6D register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 107. WAKE_UP_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 108. WAKE_UP_THS register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 109. WAKE_UP_DUR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 110. WAKE_UP_DUR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 111. FREE_FALL register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 112. FREE_FALL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 113. MD1_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 114. MD1_CFG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 115. MD2_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 116. MD2_CFG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 117. INTERNAL_FREQ_FINE register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 118. INTERNAL_FREQ_FINE register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 119. X_OFS_USR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 120. X_OFS_USR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 121. Y_OFS_USR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 122. Y_OFS_USR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 123. Z_OFS_USR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 124. Z_OFS_USR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 125. FIFO_DATA_OUT_TAG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 126. FIFO_DATA_OUT_TAG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 127. FIFO tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 128. FIFO_DATA_OUT_X_H register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 129. FIFO_DATA_OUT_X_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 130. FIFO_DATA_OUT_X_H, FIFO_DATA_OUT_X_L register description . . . . . . . . . . . . . . . 72

Table 131. FIFO_DATA_OUT_Y_H register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 132. FIFO_DATA_OUT_Y_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 133. FIFO_DATA_OUT_Y_H, FIFO_DATA_OUT_Y_L register description . . . . . . . . . . . . . . . 72

Table 134. FIFO_DATA_OUT_Z_H register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 135. FIFO_DATA_OUT_Z_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 136. FIFO_DATA_OUT_Z_H, FIFO_DATA_OUT_Z_L register description. . . . . . . . . . . . . . . . 72

Table 137. Reel dimensions for carrier tape of LGA-14 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 138. Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

8/84 DocID031239 Rev 4

ASM330LHH

List of figures

List of figures

Figure 1.

Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2.

SPI slave timing diagram (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 3.

I²C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 4.

Read and write protocol (in mode 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 5.

SPI read protocol (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 6.

Multiple byte SPI read protocol (2-byte example) (in mode 3) . . . . . . . . . . . . . . . . . . . . . . 27

Figure 7.

SPI write protocol (in mode 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 8.

Multiple byte SPI write protocol (2-byte example) (in mode 3) . . . . . . . . . . . . . . . . . . . . . . 28

Figure 9.

SPI read protocol in 3-wire mode (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 10.

Block diagram of filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 11.

Gyroscope filtering chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 12.

Accelerometer chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 13.

Accelerometer composite filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 14.

ASM330LHH electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 15.

Accelerometer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 16.

ARW gyro / pitch axis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 17.

ARW gyro / roll axis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 18.

ARW gyro / yaw axis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 19.

BI gyro / pitch axis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 20.

BI gyro / roll axis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 21.

BI gyro / yaw axis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 22.

Gyro NL / pitch axis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 23.

Gyro NL / roll axis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 24.

Gyro NL / yaw axis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 25.

LGA-14L 2.5 x 3.0 x 0.83 mm³ (typ.) package outline and mechanical data . . . . . . . . . . . 80

Figure 26.

Carrier tape information for LGA-14 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 27.

LGA-14 package orientation in carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 28.

Reel information for carrier tape of LGA-14 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

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84

Overview

1 Overview

ASM330LHH

The ASM330LHH is a system-in-package featuring a high-performance 3-axis digital accelerometer and 3-axis digital gyroscope.

This device is suitable for telematics and dead-reckoning applications as well as vehicle-tovehicle (V2X) and impact detection as a result of its high stability over temperature and time, combined with superior sensing precision.

The event-detection interrupts enable efficient and reliable motion-activated functions, implementing hardware recognition of free-fall events, 6D orientation, activity or inactivity, and wakeup events.

Up to 3 kbytes of FIFO allows overall power saving of the system.

Like the entire portfolio of MEMS sensor modules, the ASM330LHH leverages the robust and mature in-house manufacturing processes already used for the production of micromachined accelerometers and gyroscopes. The various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are developed using CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the characteristics of the sensing element.

The ASM330LHH is available in a small plastic land grid array (LGA) package of

2.5 x 3.0 x 0.83 mm to address ultra-compact solutions.

10/84 DocID031239 Rev 4

ASM330LHH

2 Embedded low-power features

Embedded low-power features

The ASM330LHH has been designed to feature the following on-chip functions:

 3 kbytes data buffering:

– 100% efficiency with flexible configurations and partitioning

 Event-detection interrupts (fully configurable):

– free-fall

– wakeup

– 6D orientation

– activity / inactivity recognition

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84

Pin description

3 Pin description

Figure 1. Pin connections

ASM330LHH

12/84

Pin#

1

7

8

5

6

2

3

4

9

10

11

12

Name

SDO

SA0

RES

RES

INT1

(1)

Vdd_IO

(2)

GNSD

GND

Vdd

(3)

INT2

NC

NC

CS

Table 2. Pin description

Function

SPI 4-wire serial data output (SDO)

I²C least significant bit of the device address (SA0)

Connect to VDDIO or GND

Connect to VDDIO or GND

Programmable interrupt #1

Power supply for I/O pin

Connect to GND

Connect to GND

Power supply

Programmable interrupt #2 (INT2) / Data enabled (DEN)

Leave unconnected

Leave unconnected

I²C/SPI mode selection

(1: SPI idle mode / I²C communication enabled;

0: SPI communication mode / I²C disabled and reset)

DocID031239 Rev 4

ASM330LHH

Pin# Name

Table 2. Pin description (continued)

Function

13

14

SCL

SDA

I²C serial clock (SCL)

SPI serial port clock (SPC)

I²C serial data (SDA)

SPI serial data input (SDI)

3-wire interface serial data output (SDO)

1. INT1 must be set to '0' or left unconnected during power-on.

2. Recommended 100 nF filter capacitor.

3. Recommended 100 nF plus 10 μF capacitors.

Pin description

DocID031239 Rev 4 13/84

84

Module specifications

4 Module specifications

ASM330LHH

4.1

Symbol

Mechanical characteristics

@Vdd = 3.0 V, T = -40 ° C to +105 ° C, up to gyroscope FS = ±2000 dps unless otherwise noted

(a)

Parameter

Table 3. Mechanical characteristics

Test conditions Min.

Max.

Unit

LA_FS

Linear acceleration measurement range

G_FS

Angular rate measurement range

LA_So

G_So

Linear acceleration sensitivity

Angular rate sensitivity

LA_So% Sensitivity tolerance

(3)

(2)

(2)

G_So% Sensitivity tolerance

(3)

LA_SoDr

G_SoDr

Linear acceleration sensitivity change vs. temperature

(4)

Angular rate sensitivity change vs.

temperature

(4)

@LA_FS = ±2 g

@LA_FS = ±4 g

@LA_FS = ±8 g

@LA_FS = ±16 g

@G_FS = ±125 dps

@G_FS = ±250 dps

@G_FS = ±500 dps

@G_FS = ±1000 dps

@G_FS = ±2000 dps

@G_FS = ±4000 dps at component level

@25°C at component level

@25°C

-5

-5

Typ.

(1)

±1000

±2000

±4000

0.061

0.122

0.244

0.488

4.37

8.75

17.5

35.0

70.0

140.0

±2

±4

±8

±16

±125

±250

±500

±100

±70

+5

+5 g dps m g /LSB mdps/LSB

%

% ppm/°C ppm/°C

14/84 a. The product is factory calibrated at 3.0 V. The operational power supply range is from 2.0 V to 3.6 V.

DocID031239 Rev 4

ASM330LHH Module specifications

Symbol

Table 3. Mechanical characteristics (continued)

Parameter Test conditions

LA_TyOff

Linear acceleration zerog level offset accuracy

(5)

G_TyOff Angular rate zero-rate level

(5)

LA_TCOff

Linear acceleration zerog level change vs. temperature

(4)

G_TCOff

LA_Cx

Angular rate typical zero-rate level change vs. temperature

(4)

Linear acceleration cross-axis sensitivity

T = 25 °C

G_Cx Angular rate cross-axis sensitivity T = 25 °C

Rn

NL

Rate noise density

(6)

Nonlinearity

(7)

ARW Angular random walk

(7)

BI Bias instability

(7)

An Acceleration noise density

(8)

Best-fit straight line

T = 25 °C

T = 25 °C

@LA_FS = ±2 g

Min.

-80

-10

Typ.

(1)

±0.10

±0.005

±1

LA_ODR

Linear acceleration output data rate

G_ODR Angular rate output data rate

±1

5

0.01

0.21

3

60

12.5

26

52

104

208

416

833

1667

3333

6667

12.5

26

52

104

208

416

833

1667

3333

6667

Vst

Linear acceleration self-test output change

(9)(10)(11)(12)

Angular rate self-test output change

(13)(14)

FS = ±250 dps

FS = ±2000 dps

Top Operating temperature range

1. Typical specifications are not guaranteed.

40

20

150

-40

1700

80

700

+105

Max.

+80

+10

Unit m g dps m g/ °C dps/°C

12

200

%

% mdps/√Hz

% FS deg/√h deg/h

μ g /√Hz

Hz m g dps dps

°C

DocID031239 Rev 4 15/84

84

Module specifications ASM330LHH

2. Sensitivity values after factory calibration test and trimming.

3. Subject to change.

4. Measurements are performed in a uniform temperature setup and they are based on characterization data in a limited number of samples. Not measured during final test for production.

5. Across temperature and life. Assuming post-solder effect compensated at the end of production line.

6. Gyroscope rate noise density is independent of the ODR for FS up to ±2000 dps, max value specified at ambient temperature.

7. Based on characterization data on a limited number of samples. Not measured during final test for production. See

Section 10: Typical performance characteristics for typical distributions.

8. Accelerometer noise density is independent of the ODR, max value specified at ambient temperature.

9. The sign of the linear acceleration self-test output change is defined by the STx_XL bits in a dedicated register for all axes.

10. The linear acceleration self-test output change is defined with the device in stationary condition as the absolute value of:

OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 0.061 m g at ±2 g full scale.

11. Accelerometer self-test limits are full-scale independent.

12. The self-test output change limits include full Vdd range and impact of soldering.

13. The sign of the angular rate self-test output change is defined by the STx_G bits in a dedicated register for all axes.

14. The angular rate self-test output change is defined with the device in stationary condition as the absolute value of:

OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 70 mdps at ±2000 dps full scale.

16/84 DocID031239 Rev 4

ASM330LHH Module specifications

4.2 Electrical characteristics

@ Vdd = 3.0 V, T = -40 ° C to +105 ° C, up to gyroscope FS = ±2000 dps unless otherwise noted

Symbol Parameter

Table 4. Electrical characteristics

Test conditions Min.

Typ.

(1)

Max.

Unit

Vdd Supply voltage

Vdd_IO Power supply for I/O

GA_Idd

A_Idd

IddPD

Ton

Gyroscope and Accelerometer current consumption

Accelerometer current consumption

Gyroscope and accelerometer current consumption during power-down

Turn-on time

(2)

ODR = 1.6 kHz

ODR < 1.6 kHz

@25°C

2.0

1.62

1.3

360

3

35

3.6

3.6

1.6

530

13

V

V mA

μA

μA ms

V

IH

(3)

Digital high-level input voltage

0.7 *

VDD_IO

V

V

IL

(3)

Digital low-level input voltage

0.3 *

VDD_IO

V

V

OH

(3)

High-level output voltage I

OH

= 4 mA

(4)

VDD_IO -

0.2

V

V

OL

(3)

Top

Low-level output voltage

Operating temperature range

I

OL

= 4 mA

(4)

-40

0.2

+105

1. T ypical specifications are not guaranteed.

2. Time to obtain stable sensitivity (within ±5% of final value) switching from power-down to normal operation

3. Guaranteed by design characterization and not tested in production

4. 4 mA is the minimum driving capability, i.e. the minimum DC current that can be sourced/sunk by the digital pad in order to guarantee the correct digital output voltage levels V

OH

and V

OL

.

V

°C

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84

Module specifications

4.3 Temperature sensor characteristics

@ Vdd = 3.0 V, T = 25 °C unless otherwise noted

(b)

.

ASM330LHH

Symbol

Table 5. Temperature sensor characteristics

Parameter Test condition Min.

Typ.

(1)

TODR

Toff

Temperature refresh rate

Temperature offset

(2)

TSen

TST

Temperature sensitivity

Temperature stabilization time

(3)

T_ADC_res Temperature ADC resolution

Top Operating temperature range

1. Typical specifications are not guaranteed.

2. The output of the temperature sensor is 0 LSB (typ.) at 25 °C.

3. Time from power ON bit to valid output data. Based on characterization.

-15

-40

52

256

16

Max.

+15

500

+105

Unit

Hz

°C

LSB/°C

μs bit

°C

18/84 b. The product is factory calibrated at 3.0 V.

DocID031239 Rev 4

ASM330LHH Module specifications

4.4

4.4.1

Communication interface characteristics

SPI - serial peripheral interface

Subject to general operating conditions for Vdd and Top.

Symbol

Table 6. SPI slave timing values (in mode 3)

Value

(1)

Parameter

Min Max

Unit t c(SPC) f c(SPC) t su(CS) t h(CS) t su(SI) t h(SI) t v(SO) t h(SO) t dis(SO)

SPI clock cycle

SPI clock frequency

CS setup time

CS hold time

SDI input setup time

SDI input hold time

SDO valid output time

SDO output hold time

SDO output disable time

100

5

20

5

15

5

10

50

50 ns

MHz ns

1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production

Figure 2. SPI slave timing diagram (in mode 3)

Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.

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Module specifications ASM330LHH

4.4.2 I ² C - inter-IC control interface

Subject to general operating conditions for Vdd and Top.

Symbol Parameter

Table 7. I ² C slave timing values

I²C standard mode

(1)

Min Max f

(SCL) t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t h(ST)

SCL clock frequency

SCL clock low time

SCL clock high time

SDA setup time

SDA data hold time

START condition hold time

0

4.7

4.0

250

0

4

100

3.45

t su(SR)

Repeated START condition setup time

STOP condition setup time

4.7

t su(SP)

4 t w(SP:SR)

Bus free time between STOP and START condition

4.7

1. Data based on standard I²C protocol requirement, not tested in production.

Figure 3. I²C slave timing diagram

I²C fast mode

(1)

Min

0

1.3

0.6

Max

400

100

0

0.6

0.9

0.6

0.6

1.3

5(3($7('

67$57

67$57

W

VX65

67$57

6'$

W

Z6365

Unit

μs kHz

μs ns

μs

W

VX6'$

W

K6'$

W

VX63

6723

6&/

W

K67

W

Z6&//

W

Z6&/+

Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.

20/84 DocID031239 Rev 4

ASM330LHH

4.5

Note:

Module specifications

Absolute maximum ratings

Stresses above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol

Table 8. Absolute maximum ratings

Ratings

Vdd

T

STG

Sg

Supply voltage

Storage temperature range

Acceleration g for 0.3 ms

ESD Electrostatic discharge protection (HBM)

Vin

Input voltage on any control pin

(including CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0)

Maximum value

-0.3 to 4.8

-40 to +125

3000

2

0.3 to Vdd_IO +0.3

Supply voltage on any pin should never exceed 4.8 V.

This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part.

This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part.

Unit

V

°C g kV

V

DocID031239 Rev 4 21/84

84

Module specifications

4.6

4.6.1

4.6.2

Terminology

ASM330LHH

Sensitivity

Linear acceleration sensitivity can be determined, for example, by applying 1 g acceleration to the device. Because the sensor can measure DC accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and over time. The sensitivity tolerance describes

the range of sensitivities of a large number of sensors (see Table 3 ).

An angular rate gyroscope is a device that produces a positive-going digital output for counterclockwise rotation around the axis considered. Sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. This value changes very little over temperature and time (see

Table 3 ).

Zerog and zero-rate level

Linear acceleration zerog level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g on both the X-axis and Y-axis, whereas the Z-axis will measure 1 g . Ideally, the output is in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2’s complement number). A deviation from the ideal value in this case is called zerog offset.

Offset is to some extent a result of stress to MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Linear acceleration zerog level change vs. temperature” in

Table 3 . The zero-

g level tolerance

(TyOff) describes the standard deviation of the range of zerog levels of a group of sensors.

Zero-rate level describes the actual output signal if there is no angular rate present. The zero-rate level of precise MEMS sensors is, to some extent, a result of stress to the sensor and therefore the zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. This value changes very little over temperature and time (see

Table 3 ).

22/84 DocID031239 Rev 4

ASM330LHH

5 Digital interfaces

5.1

5.1.1

Digital interfaces

I ² C/SPI interface

The registers embedded inside the ASM330LHH may be accessed through both the I²C and

SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The device is compatible with SPI modes 0 and 3.

The serial interfaces are mapped onto the same pins. To select/exploit the I²C interface, the

CS line must be tied high (i.e connected to Vdd_IO).

Pin name

CS

SCL/SPC

SDA/SDI/SDO

SDO/SA0

Table 9. Serial interface pin description

Pin description

SPI enable

I²C/SPI mode selection (1: SPI idle mode / I²C communication enabled;

0: SPI communication mode / I²C disabled)

I²C Serial Clock (SCL)

SPI Serial Port Clock (SPC)

I²C Serial Data (SDA)

SPI Serial Data Input (SDI)

3-wire Interface Serial Data Output (SDO)

SPI Serial Data Output (SDO)

I²C less significant bit of the device address

I ² C serial interface

The ASM330LHH I²C is a bus slave. The I²C is employed to write the data to the registers, whose content can also be read back.

The relevant I²C terminology is provided in the table below.

Term

Transmitter

Receiver

Master

Slave

Table 10. I ² C terminology

Description

The device which sends data to the bus

The device which receives data from the bus

The device which initiates a transfer, generates clock signals and terminates a transfer

The device addressed by the master

There are two signals associated with the I²C bus: the serial clock line (SCL) and the Serial

DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines must be connected to Vdd_IO through external pull-up resistors. When the bus is free, both the lines are high.

The I²C interface is implemeted with fast mode (400 kHz) I²C standards as well as with the standard mode.

In order to disable the I²C block, (I2C_disable) = 1 must be written in

CTRL4_C (13h)

.

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Digital interfaces ASM330LHH

Command

Read

Write

Read

Write

I

²

C operation

The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master.

The Slave ADdress (SAD) associated to the ASM330LHH is 110101xb. The SDO/SA0 pin can be used to modify the less significant bit of the device address. If the SDO/SA0 pin is connected to the supply voltage, LSb is ‘1’ (address 1101011b); else if the SDO/SA0 pin is connected to ground, the LSb value is ‘0’ (address 1101010b). This solution permits to connect and address two different inertial modules to the same I²C bus.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received.

The I²C embedded inside the ASM330LHH behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted.

The increment of the address is configured by the CTRL3_C (12h) (IF_INC).

The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated

START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the master will transmit to the slave with direction unchanged.

Table 11

explains how the

SAD+Read/Write bit pattern is composed, listing all the possible configurations.

SAD[6:1]

110101

110101

110101

110101

Table 11. SAD+Read/Write patterns

SAD[0] = SA0 R/W

1

1

0

0

1

0

1

0

SAD+R/W

11010101 (D5h)

11010100 (D4h)

11010111 (D7h)

11010110 (D6h)

Master

Slave

ST

Table 12. Transfer when master is writing one byte to slave

SAD + W SUB DATA

SAK SAK SAK

SP

Master

Slave

ST

Table 13. Transfer when master is writing multiple bytes to slave

SAD + W SUB DATA DATA

SAK SAK SAK SAK

SP

24/84 DocID031239 Rev 4

ASM330LHH Digital interfaces

Master

Table 14. Transfer when master is receiving (reading) one byte of data from slave

ST SAD + W SUB SR SAD + R NMAK

Slave SAK SAK SAK DATA

SP

Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave

Master ST SAD+W SUB SR SAD+R MAK MAK NMAK SP

Slave SAK SAK SAK DATA

DAT

A

DATA

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit

(MSb) first. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left HIGH by the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.

In the presented communication format MAK is Master acknowledge and NMAK is No

Master Acknowledge.

DocID031239 Rev 4 25/84

84

Digital interfaces

5.1.2 SPI bus interface

ASM330LHH

The ASM330LHH SPI is a bus slave. The SPI allows writing and reading the registers of the device.

The serial interface communicates to the application using 4 wires: CS , SPC , SDI and SDO .

Figure 4. Read and write protocol (in mode 3)

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6'2

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CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and

SDO are, respectively, the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC .

Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling edges of SPC . The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS .

bit 0 : RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SDO at the start of bit 8.

bit 1-7 : address AD(6:0). This is the address field of the indexed register.

bit 8-15 : data DI(7:0) (write mode). This is the data that is written into the device (MSb first).

bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

In multiple read/write commands further blocks of 8 clock periods will be added. When the

CTRL3_C (12h)

(IF_INC) bit is ‘0’, the address used to read/write data remains the same for every block. When the

CTRL3_C (12h)

(IF_INC) bit is ‘1’, the address used to read/write data is increased at every block.

The function and the behavior of SDI and SDO remain unchanged.

26/84 DocID031239 Rev 4

ASM330LHH Digital interfaces

SPI read

Figure 5. SPI read protocol (in mode 3)

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The SPI Read command is performed with 16 clock pulses. A multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one.

bit 0 : READ bit. The value is 1.

bit 1-7 : address AD(6:0). This is the address field of the indexed register. bit 8-15 : data DO(7:0) (read mode). This is the data that will be read from the device (MSb first).

bit 16-...

: data DO(...-8). Further data in multiple byte reads.

Figure 6. Multiple byte SPI read protocol (2-byte example) (in mode 3)

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DocID031239 Rev 4 27/84

84

Digital interfaces

SPI write

ASM330LHH

Figure 7. SPI write protocol (in mode 3)

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The SPI Write command is performed with 16 clock pulses. A multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one.

bit 0 : WRITE bit. The value is 0.

bit 1 -7 : address AD(6:0). This is the address field of the indexed register.

bit 8-15 : data DI(7:0) (write mode). This is the data that is written inside the device (MSb first).

bit 16-... : data DI(...-8). Further data in multiple byte writes.

Figure 8. Multiple byte SPI write protocol (2-byte example) (in mode 3)

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28/84 DocID031239 Rev 4

ASM330LHH Digital interfaces

SPI read in 3-wire mode

A 3-wire mode is entered by setting the

CTRL3_C (12h)

(SIM) bit equal to ‘1’ (SPI serial interface mode selection).

Figure 9. SPI read protocol in 3-wire mode (in mode 3)

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The SPI read command is performed with 16 clock pulses: bit 0 : READ bit. The value is 1.

bit 1-7 : address AD(6:0). This is the address field of the indexed register. bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

A multiple read command is also available in 3-wire mode.

DocID031239 Rev 4 29/84

84

Functionality

6 Functionality

6.1

ASM330LHH

Operating modes

In the ASM330LHH, the accelerometer and the gyroscope can be turned on/off independently of each other and are allowed to have different ODRs and power modes.

The ASM330LHH has three operating modes available:

 only accelerometer active and gyroscope in power-down or sleep mode

 only gyroscope active and accelerometer in power-down

 both accelerometer and gyroscope sensors active with independent ODR

The accelerometer is activated from power-down by writing ODR_XL[3:0] in

CTRL1_XL

(10h)

while the gyroscope is activated from power-down by writing ODR_G[3:0] in

CTRL2_G (11h)

. For combo-mode the ODRs are totally independent.

6.2 Gyroscope power modes

In the ASM330LHH, the gyroscope can be configured in two different operating modes: power-down and high-performance mode. High-performance mode is valid for all ODRs

(from 12.5 Hz up to 6.66 kHz).

6.3 Accelerometer power modes

In the ASM330LHH, the accelerometer can be configured in two different operating modes: power-down and high-performance mode. High-performance mode is valid for all ODRs

(from 12.5 Hz up to 6.66 kHz).

30/84 DocID031239 Rev 4

ASM330LHH

6.4 Block diagram of filters

Figure 10. Block diagram of filters

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The gyroscope filtering chain appears below.

Figure 11. Gyroscope filtering chain

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The gyroscope ODR is selectable from 12.5 Hz up to 6.66 kHz. A low-pass filter (LPF1) is

available, for more details about the filter characteristics see Table 53: Gyroscope LPF1 bandwidth selection . The digital LPF2 filter cannot be configured by the user and its cutoff

frequency depends on the selected gyroscope ODR, as indicated in the following table.

Data can be acquired from the output registers and FIFO.

Table 16. Gyroscope LPF2 bandwidth selection

Gyroscope ODR [Hz] LPF2 cut-off [Hz]

12.5

26

52

104

208

417

833

1667

3333

6667

4.3

8.3

16.7

33

67

133

267

539

1137

3333

DocID031239 Rev 4 31/84

84

Functionality

6.4.2

ASM330LHH

Block diagrams of the accelerometer filters

In the ASM330LHH, the filtering chain for the accelerometer part is composed of the following:

 Digital filter (LPF1)

 Composite filter

Details of the block diagram appear in the following figure.

Figure 12. Accelerometer chain

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1. The cutoff value of the LPF1 output is ODR/2.

32/84 DocID031239 Rev 4

ASM330LHH

6.5

Functionality

FIFO

The presence of a FIFO allows consistent power saving for the system since the host processor does not need continuously poll data from the sensor, but It can wake up only when needed and burst the significant data out from the FIFO.

The ASM330LHH embeds 3 kbytes of data in FIFO to store the following data:

 Gyroscope

 Accelerometer

 Timestamp

 Temperature

Writing data in the FIFO is triggered by the accelerometer / gyroscope data-ready signal.

The applications have maximum flexibility in choosing the rate of batching for physical sensors with FIFO-dedicated configurations: accelerometer, gyroscope and temperature sensor batching rates can be selected by the user. It is possible to select decimation for timestamp batching in FIFO with a factor of 1, 8, or 32.

The reconstruction of a FIFO stream is a simple task thanks to the FIFO_DATA_OUT_TAG byte that allows recognizing the meaning of a word in FIFO.

FIFO allows correct reconstruction of the timestamp information for each sensor stored in

FIFO. If a change in the ODR or BDR (Batching Data Rate) configuration is performed, the application can correctly reconstruct the timestamp and know exactly when the change was applied without disabling FIFO batching. FIFO stores information of the new configuration and timestamp in which the change was applied in the device.

The programmable FIFO watermark threshold can be set in FIFO_CTRL1 (07h) and

FIFO_CTRL2 (08h)

using the WTM[8:0] bits. To monitor the FIFO status, dedicated

registers ( FIFO_STATUS1 (3Ah) ,

FIFO_STATUS2 (3Bh)

) can be read to detect FIFO overrun events, FIFO full status, FIFO empty status, FIFO watermark status and the number of unread samples stored in the FIFO. To generate dedicated interrupts on the INT1 and

INT2 pins of these status events, the configuration can be set in

INT1_CTRL (0Dh) and

INT2_CTRL (0Eh) .

The FIFO buffer can be configured according to six different modes:

 Bypass mode

 FIFO mode

 Continuous mode

 Continuous-to-FIFO mode

 Bypass-to-continuous mode

 Bypass-to-FIFO mode

Each mode is selected by the FIFO_MODE_[2:0] bits in the

FIFO_CTRL4 (0Ah)

register.

DocID031239 Rev 4 33/84

84

Functionality

6.5.1

6.5.2

6.5.3

ASM330LHH

Bypass mode

In Bypass mode ( FIFO_CTRL4 (0Ah) (FIFO_MODE_[2:0] = 000), the FIFO is not operational

and it remains empty. Bypass mode is also used to reset the FIFO when in FIFO mode.

FIFO mode

In FIFO mode (

FIFO_CTRL4 (0Ah) (FIFO_MODE_[2:0] = 001) data from the output

channels are stored in the FIFO until it is full.

To reset FIFO content, Bypass mode should be selected by writing

FIFO_CTRL4

(0Ah)

(FIFO_MODE_[2:0]) to '000'. After this reset command, it is possible to restart FIFO mode by writing

FIFO_CTRL4 (0Ah)

(FIFO_MODE_[2:0]) to '001'.

The FIFO buffer memorizes up to 3 kbytes of data but the depth of the FIFO can be resized

by setting the WTM [8:0] bits in FIFO_CTRL1 (07h)

and FIFO_CTRL2 (08h) . If the

STOP_ON_WTM bit in

FIFO_CTRL2 (08h)

is set to '1', FIFO depth is limited up to the WTM

[8:0] bits in

FIFO_CTRL1 (07h)

and

FIFO_CTRL2 (08h) .

Continuous mode

Continuous mode ( FIFO_CTRL4 (0Ah) (FIFO_MODE_[2:0] = 110) provides a continuous

FIFO update: as new data arrives, the older data is discarded.

A FIFO threshold flag

FIFO_STATUS2 (3Bh) (FIFO_WTM_IA) is asserted when the number

of unread samples in FIFO is greater than or equal to FIFO_CTRL1 (07h)

and

FIFO_CTRL2

(08h)

(WTM [8:0]).

It is possible to route the FIFO_WTM_IA flag to

FIFO_CTRL2 (08h)

to the INT1 pin by

writing in register INT1_CTRL (0Dh)

(INT1_FIFO_TH) = '1' or to the INT2 pin by writing in

register INT2_CTRL (0Eh) (INT2_FIFO_TH) = '1'.

A full-flag interrupt can be enabled,

INT1_CTRL (0Dh)

(INT1_FIFO_FULL) = '1' or

INT2_CTRL (0Eh) (INT2_FIFO_FULL) = '1', in order to indicate FIFO saturation and

eventually read its content all at once.

If an overrun occurs, at least one of the oldest samples in FIFO has been overwritten and the FIFO_OVR_IA flag in

FIFO_STATUS2 (3Bh)

is asserted.

In order to empty the FIFO before it is full, it is also possible to pull from FIFO the number of unread samples available in

FIFO_STATUS1 (3Ah) and

FIFO_STATUS2

(3Bh)

(DIFF_FIFO_[9:0]).

34/84 DocID031239 Rev 4

ASM330LHH

6.5.4

6.5.5

6.5.6

Functionality

Continuous-to-FIFO mode

In Continuous-to-FIFO mode ( FIFO_CTRL4 (0Ah) (FIFO_MODE_[2:0] = 011), FIFO

behavior changes according to the trigger event detected in one of the following interrupt events:

 Wake-up

 Free-fall

 D6D

When the selected trigger bit is equal to '1', FIFO operates in FIFO mode.

When the selected trigger bit is equal to '0', FIFO operates in Continuous mode.

Bypass-to-Continuous mode

In Bypass-to-Continuous mode ( FIFO_CTRL4 (0Ah) (FIFO_MODE_[2:0] = '100'), data

measurement storage inside FIFO operates in Continuous mode when selected triggers are equal to '1', otherwise FIFO content is reset (Bypass mode).

FIFO behavior changes according to the trigger event detected in one of the following interrupt events:

 Wake-up

 Free-fall

 D6D

Bypass-to-FIFO mode

In Bypass-to-FIFO mode (

FIFO_CTRL4 (0Ah) (FIFO_MODE_[2:0] = '111'), data

measurement storage inside FIFO operates in FIFO mode when selected triggers are equal to '1', otherwise FIFO content is reset (Bypass mode).

FIFO behavior changes according to the trigger event detected in one of the following interrupt events:

 Wake-up

 Free-fall

 D6D

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84

Functionality

6.5.7

ASM330LHH

FIFO reading procedure

The data stored in FIFO are accessible from dedicated registers and each FIFO word is composed of 7 bytes: one tag byte (

FIFO_DATA_OUT_TAG (78h) , in order to identify the

sensor, and 6 bytes of fixed data (FIFO_DATA_OUT registers from (79h) to (7Eh)).

The DIFF_FIFO_[9:0] field in the

FIFO_STATUS1 (3Ah) and

FIFO_STATUS2 (3Bh)

registers contains the number of words (1 byte TAG + 6 bytes DATA) collected in FIFO.

In addition, it is possible to configure a counter of the batch events of accelerometer or gyroscope sensors. The flag COUNTER_BDR_IA in

FIFO_STATUS2 (3Bh)

alerts that the counter has reached a selectable threshold (CNT_BDR_TH_[9:0] field in

COUNTER_BDR_REG1 (0Bh) and COUNTER_BDR_REG2 (0Ch) ). This allows triggering

the reading of FIFO with the desired latency of one single sensor. The sensor is selectable

using the TRIG_COUNTER_BDR bit in COUNTER_BDR_REG1 (0Bh) . As for the other

FIFO status events, the flag COUNTER_BDR_IA can be routed on the INT1 or INT2 pins by

asserting the corresponding bits (INT1_CNT_BDR of INT1_CTRL (0Dh) and

INT2_CNT_BDR of INT2_CTRL (0Eh) ).

Meta information about accelerometer and gyroscope sensor configuration changes can be managed by enabling the ODR_CHG_EN bit in

FIFO_CTRL2 (08h)

.

36/84 DocID031239 Rev 4

ASM330LHH

7 Application hints

7.1 ASM330LHH electrical connections

Figure 14. ASM330LHH electrical connections

Application hints

The device core is supplied through the Vdd line while the I/O pads are supplied through the

Vdd_IO line. As a common design practice, the power supply decoupling capacitors

C1 = 100 nF ceramic and C2 =10 μF aluminum should be placed as near as possible to pin 8, while C3 = 100 nF ceramic should be positioned as close as possible to pin 5.

All the voltage and ground supplies must be present at the same time to have proper IC behavior.

The functionality of the device and the measured acceleration/angular rate data are selectable and accessible through the I²C or SPI interfaces. When using the I²C protocol,

CS must be tied high. Every time the CS line is set to low level, the I²C bus is internally reset.

All the functions, the threshold and the timing of the two interrupt pins can be completely programmed by the user through the I²C/SPI interface.

DocID031239 Rev 4 37/84

84

Application hints ASM330LHH

The procedure to correctly initialize the device is as follows:

1.

INT1: Leave unconnected or connect with external pull-down during power-on. Pull-up must be avoided on this pin.

2. INT2: Recommended to not connect with external pull-up.

3. Properly configure the device: a) SPI case: I2C_disable = 1 in

CTRL4_C (13h) and DEVICE_CONF = 1 in

CTRL9_XL (18h)

. b) I²C case: I2C_disable = 0 (default) in

CTRL4_C (13h)

and DEVICE_CONF = 1 in

CTRL9_XL (18h)

. pin# Name

Table 17. Internal pin status

Function Pin status

1

7

8

5

6

2

3

4

9

10

11

12

13

14

SDO

SA0

RES

RES

INT1

VDDIO

GND

GND

VDD

INT2

NC

NC

CS

SCL

SDA

SPI 4-wire interface serial data output

(SDO)

I²C least significant bit of the device address (SA0)

Connect to VDDIO or GND

Connect to VDDIO or GND

Programmable interrupt 1

Power supply for I/O pins

0 V supply

0 V supply

Power supply

Programmable interrupt 2 (INT2) / Data enabled (DEN)

Leave unconnected

Leave unconnected

I²C/SPI mode selection

(1:SPI idle mode /

I²C communication enabled;

0: SPI communication mode /

I²C disabled)

I²C serial clock (SCL) /

SPI serial port clock (SPC)

I²C serial data (SDA) /

SPI serial data input (SDI) /

3-wire interface serial data output (SDO)

Default: input without pull-up.

Pull-up is enabled if bit SDO_PU_EN = 1 in reg. 02h.

Default: input without pull-up.

Default: input without pull-up.

Default: input with pull-down

(1)

Default: output forced to ground

Default: input with pull-up.

Default: input with pull-up.

Default: input with pull-up.

Pull-up is disabled if bit I2C_disable = 1 in reg 13h and DEVICE_CONF = 1 in reg 18h.

Default: input without pull-up

Default: input without pull-up

1. INT1 must be set to '0' or left unconnected during power-on.

38/84 DocID031239 Rev 4

ASM330LHH

8 Register mapping

Register mapping

PIN_CTRL

RESERVED

FIFO_CTRL1

FIFO_CTRL2

FIFO_CTRL3

FIFO_CTRL4

COUNTER_BDR_REG1

COUNTER_BDR_REG2

INT1_CTRL

INT2_CTRL

WHO_AM_I

CTRL1_XL

CTRL2_G

CTRL3_C

CTRL4_C

CTRL5_C

CTRL6_C

CTRL7_G

CTRL8_XL

CTRL9_XL

CTRL10_C

ALL_INT_SRC

WAKE_UP_SRC

RESERVED

D6D_SRC

STATUS_REG

RESERVED

OUT_TEMP_L

OUT_TEMP_H

The table given below provides a list of the 8/16-bit registers embedded in the device and the corresponding addresses.

Name

R

R

-

R

R

Table 18. Registers address map

Register address

Type

Hex Binary

00000010

R/W

R/W

R/W

R/W

RW

R/W

R/W

R

R/W

-

R/W

R/W

R/W

R/W

RW

R/W

R/W

R

R

R/W

R/W

R/W

R/W

1C

1D

1E

1F

20

21

18

19

1A

1B

14

15

16

17

10

11

12

13

0C

0D

0E

0F

02

04-06

07

08

09

0A

0B

00010110

0001 0111

00011000

00011001

00011010

00011011

00011100

00011101

00011110

00011111

00100000

00100001

00000111

00001000

00001001

00001010

00001011

00001100

00001101

00001110

00001111

00010000

00010001

00010010

00010011

00010100

00010101

Default output output

Comment

00111111

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

01101011

00000000

00000000

00000100

00000000

00000000

00000000

00000000

00000000

11100000

00000000 output output output output output

Reserved

DocID031239 Rev 4 39/84

84

Register mapping

Name

OUTX_L_G

OUTX_H_G

OUTY_L_G

OUTY_H_G

OUTZ_L_G

OUTZ_H_G

OUTX_L_A

OUTX_H_A

OUTY_L_A

OUTY_H_A

OUTZ_L_A

OUTZ_H_A

RESERVED

FIFO_STATUS1

FIFO_STATUS2

RESERVED

TIMESTAMP0_REG

TIMESTAMP1_REG

TIMESTAMP2_REG

TIMESTAMP3_REG

RESERVED

INT_CFG0

RESERVED

INT_CFG1

THS_6D

RESERVED

WAKE_UP_THS

WAKE_UP_DUR

FREE_FALL

MD1_CFG

MD2_CFG

RESERVED

INTERNAL_FREQ_FINE

ASM330LHH

Table 18. Registers address map (continued)

Register address

Type

Hex Binary

Default

RW

RW

RW

RW

RW

RW

-

RW

-

R

R

-

RW

-

R

R

-

R

R

R

R

-

R

R

R

R

R

R

R

R

R

R

R

5C

5D

5E

5F

58

59

5A

5B

60-62

63

3C-3F

40

41

42

43

44-55

56

57

2D

2E-39

3A

3B

29

2A

2B

2C

25

26

27

28

22

23

24

01010110

01010111

01011000

01011001

01011010

01011011

01011100

01011101

01011110

01011111

00100010

00100011

00100100

00100101

00100110

00100111

00101000

00101001

00101010

00101011

00101100

00101101

00111010

00111011

01000000

01000001

01000010

01000011

01100011 output output output output output output output output output output output output output output output output output output

Comment

Reserved

00000000

Reserved

00000000

00000000

Reserved

00000000

00000000

00000000

00000000

00000000

00000000 Reserved output

40/84 DocID031239 Rev 4

ASM330LHH

Name

RESERVED

X_OFS_USR

Y_OFS_USR

Z_OFS_USR

RESERVED

FIFO_DATA_OUT_TAG

FIFO_DATA_OUT_X_L

FIFO_DATA_OUT_X_H

FIFO_DATA_OUT_Y_L

FIFO_DATA_OUT_Y_H

FIFO_DATA_OUT_Z_L

FIFO_DATA_OUT_Z_H

RESERVED

Register mapping

Table 18. Registers address map (continued)

Register address

Type

Hex Binary

Default

R

R

R

R

R

-

-

RW

RW

RW

-

R

R

7A

7B

7C

7D

7E

7F

64-72

73

74

75

76-77

78

79

01110011

01110100

01110101

01111000

01111001

01111010

01111011

01111100

01111101

01111110

Comment

00000000 Reserved

00000000

00000000

00000000

Reserved output output output output output output output

Reserved

DocID031239 Rev 4 41/84

84

Register description

9 Register description

ASM330LHH

The device contains a set of registers which are used to control its behavior and to retrieve linear acceleration, angular rate and temperature data. The register addresses, made up of

7 bits, are used to identify them and to write the data through the serial interface.

9.1 PIN_CTRL (02h)

SDO pin pull-up enable/disable register (r/w)

Table 19. PIN_CTRL register

0

SDO_

PU_EN

1

(1)

1

(1)

1

(1)

1. This bit must be set to '1' for the correct operation of the device.

1

(1)

SDO_PU_EN

Table 20. PIN_CTRL register description

Enable pull-up on SDO pin. Default value: 0

(0: SDO pin pull-up disconnected; 1: SDO pin with pull-up)

1

(1)

1

(1)

9.2 FIFO_CTRL1 (07h)

FIFO control register 1 (r/w)

WTM7

WTM[7:0]

WTM6

Table 21. FIFO_CTRL1 register

WTM5 WTM4 WTM3 WTM2 WTM1 WTM0

Table 22. FIFO_CTRL1 register description

FIFO watermark threshold, in conjunction with WTM8 in FIFO_CTRL2 (08h)

1 LSB = 1 sensor (6 bytes) + TAG (1 byte) written in FIFO

Watermark flag rises when the number of bytes written in the FIFO is greater than or equal to the threshold level.

42/84 DocID031239 Rev 4

ASM330LHH

9.3

Register description

FIFO_CTRL2 (08h)

FIFO control register 2 (r/w)

STOP_ON

_WTM

0

(1)

0

Table 23. FIFO_CTRL2 register

(1)

ODRCHG

_EN

0

(1)

1. This bit must be set to '0' for the correct operation of the device.

0

(1)

0

(1)

WTM8

STOP_ON_

WTM

Table 24. FIFO_CTRL2 register description

Sensing chain FIFO stop values memorization at threshold level

(0: FIFO depth is not limited (default);

1: FIFO depth is limited to threshold level, defined in FIFO_CTRL1 (07h) and

FIFO_CTRL2 (08h) )

ODRCHG_EN Enables ODR CHANGE virtual sensor to be batched in FIFO

WTM8

FIFO watermark threshold, in conjunction with WTM[7:0] in

FIFO_CTRL1 (07h)

1 LSB = 1 sensor (6 bytes) + TAG (1 byte) written in FIFO

Watermark flag rises when the number of bytes written in the FIFO is greater than or equal to the threshold level.

DocID031239 Rev 4 43/84

84

Register description

9.4 FIFO_CTRL3 (09h)

FIFO control register 3 (r/w)

ASM330LHH

BDR_GY_

3

BDR_GY_

2

Table 25. FIFO_CTRL3 register

BDR_GY_

1

BDR_GY_

0

BDR_XL_

3

BDR_XL_

2

BDR_XL_

1

BDR_XL_

0

BDR_GY_[3:0]

BDR_XL_[3:0]

Table 26. FIFO_CTRL3 register description

Selects Batch Data Rate (writing frequency in FIFO) for gyroscope data. (0000:

Gyro not batched in FIFO (default);

0001: 12.5 Hz;

0010: 26 Hz;

0011: 52 Hz;

0100: 104 Hz;

0101: 208 Hz;

0110: 417 Hz;

0111: 833 Hz;

1000: 1667 Hz;

1001: 3333 Hz;

1010: 6667 Hz;

1011: 6.5 Hz;

1100-1111: not allowed)

Selects Batch Data Rate (writing frequency in FIFO) for accelerometer data.

(0000: Accelerometer not batched in FIFO (default);

0001: 12.5 Hz;

0010: 26 Hz;

0011: 52 Hz;

0100: 104 Hz;

0101: 208 Hz;

0110: 417 Hz;

0111: 833 Hz;

1000: 1667 Hz;

1001: 3333 Hz;

1010: 6667 Hz;

1011-1111: not allowed)

44/84 DocID031239 Rev 4

ASM330LHH

9.5

Register description

FIFO_CTRL4 (0Ah)

FIFO control register 4 (r/w)

DEC_TS_

BATCH_1

DEC_TS_

BATCH_0

Table 27. FIFO_CTRL4 register

ODR_T_

BATCH_1

ODR_T_

BATCH_0

0

(1)

1. This bit must be set to '0' for the correct operation of the device.

FIFO_

MODE2

FIFO_

MODE1

FIFO_

MODE0

DEC_TS_

BATCH_[1:0]

ODR_T_

BATCH_[1:0]

FIFO_

MODE[2:0]

Table 28. FIFO_CTRL4 register description

Selects decimation for timestamp batching in FIFO. Writing rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.

(00: Timestamp not batched in FIFO (default);

01: Decimation 1: max(BDR_XL[Hz],BDR_GY[Hz]) [Hz];

10: Decimation 8: max(BDR_XL[Hz],BDR_GY[Hz])/8 [Hz];

11: Decimation 32: max(BDR_XL[Hz],BDR_GY[Hz])/32 [Hz])

Selects batching data rate (writing frequency in FIFO) for temperature data

(00: Temperature not batched in FIFO (default);

01: 1.6 Hz;

10: 12.5 Hz;

11: 52 Hz)

FIFO mode selection

(000: Bypass mode: FIFO disabled;

001: FIFO mode: stops collecting data when FIFO is full;

010: Reserved;

011: Continuous-to-FIFO mode:

Continuous mode until trigger is deasserted, then FIFO mode;

100: Bypass-to-Continuous mode:

Bypass mode until trigger is deasserted, then Continuous mode;

101: Reserved;

110: Continuous mode:

If the FIFO is full, the new sample overwrites the older one;

111: Bypass-to-FIFO mode:

Bypass mode until trigger is deasserted, then FIFO mode.)

DocID031239 Rev 4 45/84

84

Register description

9.6 COUNTER_BDR_REG1 (0Bh)

Counter batch data rate register 1 (r/w)

ASM330LHH dataready

_pulsed

RST_

COUNTER

_BDR

Table 29. COUNTER_BDR_REG1 register

TRIG_

COUNTER

_BDR

0

(1)

0

(1)

0

(1)

1. This bit must be set to '0' for the correct operation of the device.

CNT_BDR

_TH_9

CNT_BDR

_TH_8

dataready_ pulsed

Table 30. COUNTER_BDR_REG1 register description

Enables pulsed data-ready mode

(0: Data-ready latched mode (returns to 0 only after an interface reading) (default);

1: Data-ready pulsed mode (the data ready pulses are 75 μs long)

RST_

COUNTER_

BDR

Resets the internal counter of batching events for a single sensor.

This bit is automatically reset to zero if it was set to ‘1’.

TRIG_

COUNTER_

BDR

CNT_BDR_

TH_[9:8]

Selects the trigger for the internal counter of batching events between XL and gyro.

(0: XL batching event;

1: GYRO batching event)

In conjunction with CNT_BDR_TH_[7:0] in

COUNTER_BDR_REG2 (0Ch)

, sets the threshold for the internal counter of batching events. When this counter reaches the threshold, the counter is reset and the COUNTER_BDR_IA flag in

FIFO_STATUS2

(3Bh) is set to ‘1’.

9.7 COUNTER_BDR_REG2 (0Ch)

Counter batch data rate register 2 (r/w)

CNT_BDR

_TH_7

CNT_BDR

_TH_6

Table 31. COUNTER_BDR_REG2 register

CNT_BDR

_TH_5

CNT_BDR

_TH_4

CNT_BDR

_TH_3

CNT_BDR

_TH_2

CNT_BDR

_TH_1

CNT_BDR

_TH_0

CNT_BDR_TH_

[7:0]

Table 32. COUNTER_BDR_REG2 register description

In conjunction with CNT_BDR_TH_[9:8] in

COUNTER_BDR_REG1 (0Bh) , sets

the threshold for the internal counter of batching events. When this counter reaches the threshold, the counter is reset and the COUNTER_BDR_IA flag in

FIFO_STATUS2 (3Bh) is set to ‘1’.

46/84 DocID031239 Rev 4

ASM330LHH

9.8

Register description

INT1_CTRL (0Dh)

INT1 pin control register (r/w)

Each bit in this register enables a signal to be carried over INT1. The output of the pad will be the OR combination of the signals selected here and in register

MD1_CFG (5Eh) .

DEN_

DRDY_ flag

DEN_DRDY_flag

INT1_CNT_BDR

INT1_FIFO_FULL

INT1_FIFO_OVR

INT1_FIFO_TH

INT1_BOOT

INT1_DRDY_G

INT1_DRDY_XL

INT1_

CNT_BDR

Table 33. INT1_CTRL register

INT1_

FIFO

_FULL

INT1_

FIFO_

OVR

INT1_

FIFO_TH

INT1_

BOOT

INT1_

DRDY_G

INT1_

DRDY_XL

Table 34. INT1_CTRL register description

Sends DEN_DRDY (DEN stamped on sensor data flag) to INT1 pin.

Enables COUNTER_BDR_IA interrupt on INT1 pin.

Enables FIFO full flag interrupt on INT1 pin.

Enables FIFO overrun interrupt on INT1 pin.

Enables FIFO threshold interrupt on INT1 pin.

Enables boot status on INT1 pin.

Gyroscope data-ready interrupt on INT1 pin.

Accelerometer data-ready interrupt on INT1 pin.

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84

Register description

9.9 INT2_CTRL (0Eh)

ASM330LHH

INT2 pin control register (r/w).

Each bit in this register enables a signal to be carried over INT2. The output of the pad will be the OR combination of the signals selected here and in register

MD2_CFG (5Fh)

.

0

(1)

INT2_

CNT_BDR

INT2_

FIFO_

FULL

Table 35. INT2_CTRL register

INT2_

FIFO_

OVR

INT2_

FTH

INT2_

DRDY_TEMP

1. This bit must be set to '0' for the correct operation of the device.

INT2_CNT_BDR

INT2_FIFO_FULL

INT2_FIFO_OVR

INT_FIFO_TH

Table 36. INT2_CTRL register description

Enables COUNTER_BDR_IA interrupt on INT2 pin.

Enables FIFO full flag interrupt on INT2 pin.

Enables FIFO overrun interrupt on INT2 pin.

Enables FIFO threshold interrupt on INT2 pin.

INT2_DRDY_TEMP Temperature sensor data-ready interrupt on INT2 pin.

INT2_DRDY_G Gyroscope data-ready interrupt on INT2 pin.

INT2_DRDY_XL Accelerometer data-ready interrupt on INT2 pin.

INT2_

DRDY_G

INT2_

DRDY_XL

9.10 WHO_AM_I (0Fh)

WHO_AM_I register (r). This is a read-only register. Its value is fixed at 6Bh.

0 1 1

Table 37. WhoAmI register

0 1 0 1 1

48/84 DocID031239 Rev 4

ASM330LHH Register description

9.11 CTRL1_XL (10h)

Accelerometer control register 1 (r/w)

Table 38. CTRL1_XL register

ODR_XL3 ODR_XL2 ODR_XL1 ODR_XL0 FS1_XL FS0_XL

LPF2_XL_

EN

1. This bit must be set to '0' for the correct operation of the device.

ODR_XL[3:0]

FS[1:0]_XL

Table 39. CTRL1_XL register description

Accelerometer ODR selection

(0000: Power-down (default);

0001: 12.5 Hz;

0010: 26 Hz;

0011: 52 Hz;

0100: 104 Hz;

0101: 208 Hz;

0110: 417 Hz;

0111: 833 Hz;

1000: 1667 Hz;

1001: 3333 Hz;

1010: 6667 Hz;

1011: not allowed;

11xx: not allowed)

Accelerometer full-scale selection

(00: ±2 g (default);

01: ±16 g ;

10: ±4 g ;

11: ±8 g )

LPF2_XL_EN

Accelerometer high-resolution selection:

(0: Output from first stage digital stage filtering selected (default);

1: Output from LPF2 second filtering stage selected)

0

(1)

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84

Register description ASM330LHH

9.12 CTRL2_G (11h)

Gyroscope control register 2 (r/w)

Table 40. CTRL2_G register

ODR_G3 ODR_G2 ODR_G1 ODR_G0 FS1_G FS0_G

ODR_G[3:0]

FS[1:0]_G

FS_125

FS_4000

Table 41. CTRL2_G register description

Gyroscope ODR selection .

(0000: Power-down;

0001: 12.5 Hz;

0010: 26 Hz;

0011: 52 Hz;

0100: 104 Hz;

0101: 208 Hz;

0110: 417 Hz;

0111: 833 Hz;

1000: 1667 Hz;

1001: 3333 Hz;

1010: 6667 Hz;

1011: not allowed;

11xx: not allowed)

Gyroscope chain full-scale selection

(00: ±250 dps;

01: ±500 dps;

10: ±1000 dps;

11: ±2000 dps)

Selects gyro chain full-scale ±125 dps

(0: FS selected through bits FS[1:0]_G;

1: FS set to ±125 dps)

Selects gyro chain full-scale ±4000 dps

(0: FS selected through bits FS[1:0]_G or FS_125;

1: FS set to ±4000 dps)

FS_125 FS_4000

50/84 DocID031239 Rev 4

ASM330LHH Register description

9.13 CTRL3_C (12h)

Control register 3 (r/w)

BOOT BDU

Table 42. CTRL3_C register

H_LACTIVE PP_OD SIM

1. This bit must be set to '0' for the correct operation of the device.

IF_INC

BOOT

BDU

H_LACTIVE

PP_OD

SIM

IF_INC

SW_RESET

0

(1)

SW_RESET

Table 43. CTRL3_C register description

Reboots memory content. Default value: 0

(0: normal mode; 1: reboot memory content)

Note: the accelerometer must be ON. This bit is automatically cleared.

Block Data Update. Default value: 0

(0: continuous update;

1: output registers are not updated until MSB and LSB have been read)

Interrupt activation level. Default value: 0

(0: interrupt output pins active high; 1: interrupt output pins active low

Push-pull/open-drain selection on INT1 and INT2 pins. This bit must be set to '0' when H_LACTIVE is set to '1'. Default value: 0

(0: push-pull mode; 1: open-drain mode)

SPI Serial Interface Mode selection. Default value: 0

(0: 4-wire interface; 1: 3-wire interface)

Register address automatically incremented during a multiple byte access with a serial interface (I²C or SPI). Default value: 1

(0: disabled; 1: enabled)

Software reset. Default value: 0

(0: normal mode; 1: reset device)

This bit is automatically cleared.

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84

Register description ASM330LHH

9.14 CTRL4_C (13h)

Control register 4 (r/w)

0

(1)

SLEEP_G

Table 44. CTRL4_C register

INT2_on_

INT1

0

(1)

DRDY_

MASK

I2C_disable

1. This bit must be set to '0' for the correct operation of the device.

LPF1_

SEL_G

0

(1)

SLEEP_G

INT2_on_INT1

DRDY_MASK

I2C_disable

LPF1_SEL_G

Table 45. CTRL4_C register description

Enables gyroscope Sleep mode. Default value:0

(0: disabled; 1: enabled)

All interrupt signals available on INT1 pin enable. Default value: 0

(0: interrupt signals divided between INT1 and INT2 pins;

1: all interrupt signals in logic or on INT1 pin)

Enables data available

(0: disabled;

1: mask DRDY on pin (both XL & Gyro) until filter settling ends (XL and Gyro independently masked).

Disables I²C interface. Default value: 0

(0: SPI and I²C interfaces enabled (default); 1: I²C interface disabled)

Enables gyroscope digital LPF1; the bandwidth can be selected through

FTYPE[2:0] in CTRL6_C (15h) .

(0: disabled; 1: enabled)

52/84 DocID031239 Rev 4

ASM330LHH Register description

9.15 CTRL5_C (14h)

Control register 5 (r/w)

0

(1)

Table 46. CTRL5_C register

ROUNDING1 ROUNDING0

0

(1)

ST1_G

1. This bit must be set to '0' for the correct operation of the device.

ST0_G ST1_XL ST0_XL

ROUNDING[1:0]

ST[1:0]_G

ST[1:0]_XL

Table 47. CTRL5_C register description

Circular burst-mode (rounding) read of the output registers. Default value: 00

(00: no rounding;

01: accelerometer only;

10: gyroscope only;

11: gyroscope + accelerometer)

Angular rate sensor self-test enable. Default value: 00

(00: Self-test disabled; Other: refer to Table

)

Linear acceleration sensor self-test enable. Default value: 00

(00: Self-test disabled; Other: refer to Table

)

0

0

1

1

ST1_G

Table 48. Angular rate sensor self-test mode selection

ST0_G Self-test mode

0

1

0

1

Normal mode

Positive sign self-test

Not allowed

Negative sign self-test

0

0

1

1

Table 49. Linear acceleration sensor self-test mode selection

ST1_XL ST0_XL Self-test mode

0

1

0

1

Normal mode

Positive sign self-test

Negative sign self-test

Not allowed

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84

Register description ASM330LHH

9.16 CTRL6_C (15h)

Control register 6 (r/w)

Table 50. CTRL6_C register

TRIG_EN LVL1_EN LVL2_EN 0

(1)

USR_

OFF_W

FTYPE_2 FTYPE_1 FTYPE_0

1. This bit must be set to '0' for the correct operation of the device.

TRIG_EN

LVL1_EN

LVL2_EN

USR_OFF_W

FTYPE[2:0]

Table 51. CTRL6_C register description

DEN data edge-sensitive trigger enable. Refer to Table

.

DEN data level-sensitive trigger enable. Refer to

Table .

DEN level-sensitive latched enable. Refer to

Table .

Weight of XL user offset bits of registers

X_OFS_USR (73h) , Y_OFS_USR (74h)

,

Z_OFS_USR (75h)

(0 = 2

-10 g /LSB;

1 = 2

-6 g /LSB)

Gyroscope low-pass filter (LPF1) bandwidth selection.

Table 52. Trigger mode selection

TRIG_EN, LVL1_EN, LVL2_EN Trigger mode

100

010

011

110

Edge-sensitive trigger mode is selected

Level-sensitive trigger mode is selected

Level-sensitive latched mode is selected

Level-sensitive FIFO enable mode is selected

FTYPE

[2:0]

100

101

110

111

000

001

010

011

12.5 Hz 26 Hz

4.3

4.3

4.3

4.3

4.3

4.3

4.3

4.3

8.3

8.3

8.3

8.3

8.3

8.3

8.3

8.3

Table 53. Gyroscope LPF1 bandwidth selection

52 Hz 104 Hz 208 Hz 416 Hz 833 Hz 1.67 kHz 3.33 kHz 6.67 kHz

16.7

16.9

13.4

9.8

16.7

16.7

16.7

16.7

34

31

19

11.6

33

33

33

33

62

43

23

12.2

67

67

67

67

86

48

24.6

12.4

133

128

112

134

96

49

25

12.6

222

186

140

260

99

50

25

12.6

274

212

150

390

292

220

153

451

NA

NA

NA

NA

297

223

154

470

54/84 DocID031239 Rev 4

ASM330LHH Register description

9.17 CTRL7_G (16h)

Control register 7 (r/w)

0

(1)

Table 54. CTRL7_G register

HP_EN_G HPM1_G HPM0_G 0

(1)

0

(1)

USR_OFF

_ON_OUT

0

(1)

1. This bit must be set to '0' for the correct operation of the device.

HP_EN_G

HPM_G[1:0]

USR_OFF_ON_

OUT

Table 55. CTRL7_G register description

Enables gyroscope digital high-pass filter. The filter is enabled only if the gyro is in HP mode. Default value: 0

(0: HPF disabled; 1: HPF enabled)

Gyroscope digital HP filter cutoff selection. Default: 00

(00 = 16 mHz;

01 = 65 mHz;

10 = 260 mHz;

11 = 1.04 Hz)

Enables accelerometer user offset correction block; it's valid for the low-pass path - see

Figure . Default value: 0

(0: accelerometer user offset correction block bypassed;

1: accelerometer user offset correction block enabled)

9.18 CTRL8_XL (17h)

Control register 8 (r/w)

HPCF_XL

_2

HPCF_XL

_1

Table 56. CTRL8_XL register

HPCF_XL

_0

HP_REF_

MODE_XL

FASTSETTL

_MODE_XL

HP_SLOPE

_XL_EN

1. This bit must be set to '0' for the correct operation of the device.

0

(1)

LOW_PASS

_ON_6D

HPCF_XL_[2:0]

HP_REF_

MODE_XL

FASTSETTL

_MODE_XL

Table 57. CTRL8_XL register description

Accelerometer LPF2 and HP filter configuration and cutoff setting. Refer to

Table .

Enables accelerometer high-pass filter reference mode (valid for high-pass path -

HP_SLOPE_XL_EN bit must be ‘1’). Default value: 0

(0: disabled, 1: enabled

(1)

)

Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the second samples after writing this bit. Active only during device exit from power- down mode. Default value: 0

(0: disabled, 1: enabled)

HP_SLOPE_

XL_EN

Accelerometer slope filter / high-pass filter selection. Refer to Figure

LOW_PASS

_ON_6D

LPF2 on 6D function selection. Refer to

Figure . Default value: 0

(0: ODR/2 low-pass filtered data sent to 6D interrupt function;

1: LPF2 output data sent to 6D interrupt function)

1. When enabled, the first output data have to be discarded.

.

DocID031239 Rev 4 55/84

84

Register description

Filter type

Low pass

High pass

ASM330LHH

Table 58. Accelerometer bandwidth configurations

HP_SLOPE_

XL_EN

LPF2_XL_EN HPCF_XL_[2:0]

0

0

1

1

-

010

011

100

101

110

111

000

001

110

111

-

000

001

010

011

100

101

Bandwidth

ODR/2

ODR/4

ODR/10

ODR/20

ODR/45

ODR/100

ODR/200

ODR/400

ODR/800

SLOPE (ODR/4)

ODR/10

ODR/20

ODR/45

ODR/100

ODR/200

ODR/400

ODR/800

Figure 15. Accelerometer block diagram

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1. The cutoff value of the LPF1 output is ODR/2.

56/84 DocID031239 Rev 4

ASM330LHH Register description

9.19 CTRL9_XL (18h)

Control register 9 (r/w)

Table 59. CTRL9_XL register

DEN_X DEN_Y DEN_Z DEN_XL_G DEN_XL_EN DEN_LH

DEVICE

_CONF

1. This bit must be set to '0' for the correct operation of the device.

DEN_X

DEN_Y

DEN_Z

DEN_XL_G

DEN_XL_EN

DEN_LH

DEVICE_CONF

Table 60. CTRL9_XL register description

DEN value stored in LSB of X-axis. Default value: 1

(0: DEN not stored in X-axis LSB; 1: DEN stored in X-axis LSB)

DEN value stored in LSB of Y-axis. Default value: 1

(0: DEN not stored in Y-axis LSB; 1: DEN stored in Y-axis LSB)

DEN value stored in LSB of Z-axis. Default value: 1

(0: DEN not stored in Z-axis LSB; 1: DEN stored in Z-axis LSB)

DEN stamping sensor selection. Default value: 0

(0: DEN pin info stamped in the gyroscope axis selected by bits [7:5];

1: DEN pin info stamped in the accelerometer axis selected by bits [7:5])

Extends DEN functionality to accelerometer sensor. Default value: 0

(0: disabled; 1: enabled)

DEN active level configuration. Default value: 0

(0: active low; 1: active high)

Enables the proper device configuration. Default value: 0

It is recommended to always set this bit to 1 during device configuration.

(0: default;

1: enabled)

0

(1)

9.20 CTRL10_C (19h)

Control register 10 (r/w)

0

(1)

0

(1)

Table 61. CTRL10_C register

TIMESTAMP

_EN

0

(1)

0

(1)

1. This bit must be set to '0' for the correct operation of the device.

0

(1)

0

(1)

TIMESTAMP_EN

Table 62. CTRL10_C register description

Enables timestamp counter. Default value: 0

(0: disabled; 1: enabled)

The counter is readable in

TIMESTAMP0 (40h), TIMESTAMP1 (41h),

TIMESTAMP2 (42h), and TIMESTAMP3 (43h) .

0

(1)

DocID031239 Rev 4 57/84

84

Register description ASM330LHH

9.21 ALL_INT_SRC (1Ah)

Source register for all interrupts (r)

TIMESTAMP_

ENDCOUNT

0

Table 63. ALL_INT_SRC register

SLEEP_

CHANGE_IA

D6D_IA 0 0 WU_IA FF_IA

Table 64. ALL_INT_SRC register description

TIMESTAMP_ENDCOUNT Alerts timestamp overflow within 6.4 ms

SLEEP_CHANGE_IA

D6D_IA

Detects change event in activity/inactivity status. Default value: 0

(0: change status not detected; 1: change status detected)

Interrupt active for change in position of portrait, landscape, face-up, face-down. Default value: 0

(0: change in position not detected; 1: change in position detected)

WU_IA

FF_IA

Wake-up event status. Default value: 0

(0: event not detected, 1: event detected)

Free-fall event status. Default value: 0

(0: event not detected, 1: event detected)

9.22 WAKE_UP_SRC (1Bh)

Wake-up interrupt source register (r)

0

SLEEP_

CHANGE_IA

Table 65. WAKE_UP_SRC register

FF_IA

SLEEP_

STATE

WU_IA X_WU Y_WU Z_WU

SLEEP_

CHANGE_IA

FF_IA

SLEEP_STATE

WU_IA

X_WU

Y_WU

Z_WU

Table 66. WAKE_UP_SRC register description

Detects change event in activity/inactivity status. Default value: 0

(0: change status not detected; 1: change status detected)

Free-fall event detection status. Default: 0

(0: free-fall event not detected; 1: free-fall event detected)

Sleep status bit. Default value: 0

(0: activity status; 1: inactivity status)

Wakeup event detection status. Default value: 0

(0: wakeup event not detected; 1: wakeup event detected.)

Wakeup event detection status on X-axis. Default value: 0

(0: wakeup event on X-axis not detected; 1: wakeup event on X-axis detected)

Wakeup event detection status on Y-axis. Default value: 0

(0: wakeup event on Y-axis not detected; 1: wakeup event on Y-axis detected)

Wakeup event detection status on Z-axis. Default value: 0

(0: wakeup event on Z-axis not detected; 1: wakeup event on Z-axis detected)

58/84 DocID031239 Rev 4

ASM330LHH Register description

9.23 D6D_SRC (1Dh)

Portrait, landscape, face-up and face-down source register (r)

DEN_DRDY D6D_IA

Table 67. D6D_SRC register

ZH ZL YH YL XH XL

DEN_

DRDY

D6D_

IA

ZH

ZL

YH

YL

XH

XL

Table 68. D6D_SRC register description

DEN data-ready signal. It is set high when data output is related to the data coming from a

DEN active condition.

(1)

Interrupt active for change position portrait, landscape, face-up, face-down. Default value: 0

(0: change position not detected; 1: change position detected)

Z-axis high event (over threshold). Default value: 0

(0: event not detected; 1: event (over threshold) detected)

Z-axis low event (under threshold). Default value: 0

(0: event not detected; 1: event (under threshold) detected)

Y-axis high event (over threshold). Default value: 0

(0: event not detected; 1: event (over-threshold) detected)

Y-axis low event (under threshold). Default value: 0

(0: event not detected; 1: event (under threshold) detected)

X-axis high event (over threshold). Default value: 0

(0: event not detected; 1: event (over threshold) detected)

X-axis low event (under threshold). Default value: 0

(0: event not detected; 1: event (under threshold) detected)

1. The DEN data-ready signal can be latched or pulsed depending on the value of the dataready pulsed bit of the

COUNTER_BDR_REG1 (0Bh)

register.

9.24 STATUS_REG (1Eh)

Status register (r)

TDA

GDA

0

XLDA

0 0

Table 69. STATUS_REG register

0 0 TDA

Table 70. STATUS_REG register description

Temperature new data available. Default: 0

(0: no set of data is available at temperature sensor output;

1: a new set of data is available at temperature sensor output)

Gyroscope new data available. Default value: 0

(0: no set of data available at gyroscope output;

1: a new set of data is available at gyroscope output)

Accelerometer new data available. Default value: 0

(0: no set of data available at accelerometer output;

1: a new set of data is available at accelerometer output)

GDA XLDA

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84

Register description ASM330LHH

9.25 OUT_TEMP_L (20h), OUT_TEMP_H (21h)

Temperature data output register (r). L and H registers together express a 16-bit word in two’s complement.

Temp7 Temp6

Table 71. OUT_TEMP_L register

Temp5 Temp4 Temp3 Temp2 Temp1

Temp15 Temp14

Table 72. OUT_TEMP_H register

Temp13 Temp12 Temp11 Temp10 Temp9

Temp[15:0]

Table 73. OUT_TEMP register description

Temperature sensor output data

The value is expressed as two’s complement sign extended on the MSB.

Temp0

Temp8

9.26 OUTX_H_G (23h), OUTX_L_G (22h)

Angular rate sensor pitch axis (X) angular rate output register (r). The value is expressed as a 16-bit word in two’s complement.

D15

D7

D[15:0]

D14 D13

Table 74. OUTX_H_G register

D12 D11 D10

D5

Table 75. OUTX_L_G register

D4 D3 D2

D9

D6 D1

Table 76. OUTX_H_G, OUTX_L_G register description

Gyroscope pitch axis output expressed in 2’s complement

D8

D0

9.27 OUTY_H_G (25h), OUTY_L_G (24h)

Angular rate sensor roll axis (Y) angular rate output register (r). The value is expressed as a

16-bit word in two’s complement.

D15

D7

D[15:0]

D14 D13

Table 77. OUTY_H_G register

D12 D11 D10

D5

Table 78. OUTY_L_G register

D4 D3 D2

D9

D6 D1

Table 79. OUTY_H_G, OUTY_L_G register description

Gyroscope roll axis output expressed in 2’s complement

D8

D0

60/84 DocID031239 Rev 4

ASM330LHH Register description

9.28 OUTZ_H_G (27h), OUTZ_L_G (26h)

Angular rate sensor pitch yaw (Z) angular rate output register (r). The value is expressed as a 16-bit word in two’s complement.

D15

D7

D[15:0]

D14 D13

Table 80. OUTZ_H_G register

D12 D11 D10

D5

Table 81. OUTZ_L_G register

D4 D3 D2

D9

D6 D1

Table 82. OUTZ_H_G, OUTZ_L_G register description

Gyroscope yaw axis output expressed in 2’s complement

D8

D0

9.29 OUTX_H_A (29h), OUTX_L_A (28h)

Linear acceleration sensor X-axis output register (r). The value is expressed as a 16-bit word in two’s complement.

D15

D7

D[15:0]

D14 D13

Table 83. OUTX_H_A register

D12 D11 D10

D5

Table 84. OUTX_L_A register

D4 D3 D2

D9

D6 D1

Table 85. OUTX_H_A, OUTX_L_A register description

Accelerometer X-axis output expressed as 2’s complement

D8

D0

9.30 OUTY_H_A (2Bh), OUTY_L_A (2Ah)

Linear acceleration sensor Y-axis output register (r). The value is expressed as a 16-bit word in two’s complement.

D15

D7

D[15:0]

D14 D13

Table 86. OUTY_H_A register

D12 D11 D10

D5

Table 87. OUTY_L_A register

D4 D3 D2

D9

D6 D1

Table 88. OUTY_H_A, OUTY_L_A register description

Accelerometer Y-axis output expressed as 2’s complement

D8

D0

DocID031239 Rev 4 61/84

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Register description ASM330LHH

9.31 OUTZ_H_A (2Dh), OUTZ_L_A (2Ch)

Linear acceleration sensor Z-axis output register (r). The value is expressed as a 16-bit word in two’s complement.

D15

D7

D[15:0]

D14 D13

Table 89. OUTZ_H_A register

D12 D11 D10

D5

Table 90. OUTZ_L_A register

D4 D3 D2

D9

D6 D1

Table 91. OUTZ_H_A, OUTZ_L_A register description

Accelerometer Z-axis output expressed as 2’s complement

D8

D0

9.32 FIFO_STATUS1 (3Ah)

FIFO status register 1 (r)

DIFF_

FIFO_7

DIFF_

FIFO_[7:0]

DIFF_

FIFO_6

Table 92. FIFO_STATUS1 register

DIFF_

FIFO_5

DIFF_

FIFO_4

DIFF_

FIFO_3

DIFF_

FIFO_2

Table 93. FIFO_STATUS1 register description

Number of unread sensor data (TAG + 6 bytes) stored in FIFO

In conjunction with DIFF_FIFO[9:8] in FIFO_STATUS2 (3Bh).

DIFF_

FIFO_1

DIFF_

FIFO_0

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ASM330LHH Register description

9.33 FIFO_STATUS2 (3Bh)

FIFO status register 2 (r)

FIFO_

WTM_IA

FIFO_

WTM_IA

FIFO_

OVR_IA

FIFO_

FULL_IA

COUNTER_

BDR_IA

FIFO_OVR_

LATCHED

DIFF_

FIFO_[9:8]

FIFO_

OVR_IA

Table 94. FIFO_STATUS2 register

FIFO_

FULL_IA

COUNTER

_BDR_IA

FIFO_OVR_

LATCHED

0

DIFF_

FIFO_9

DIFF_

FIFO_8

Table 95. FIFO_STATUS2 register description

FIFO watermark status. Default value: 0

(0: FIFO filling is lower than WTM;

1: FIFO filling is equal to or greater than WTM)

Watermark is set through bits WTM[8:0] in FIFO_CTRL2 (08h)

and FIFO_CTRL1

(07h) .

FIFO overrun status. Default value: 0

(0: FIFO is not completely filled; 1: FIFO is completely filled)

Smart FIFO full status. Default value: 0

(0: FIFO is not full; 1: FIFO will be full at the next ODR)

Counter BDR reaches the CNT_BDR_TH_[9:0] threshold set in

COUNTER_BDR_REG1 (0Bh) and COUNTER_BDR_REG2 (0Ch)

. Default value: 0

This bit is reset when these registers are read.

Latched FIFO overrun status. Default value: 0

This bit is reset when this register is read.

Number of unread sensor data (TAG + 6 bytes) stored in FIFO. Default value: 00

In conjunction with DIFF_FIFO[7:0] in

FIFO_STATUS1 (3Ah)

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Register description ASM330LHH

9.34 TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h)

Timestamp first data output register (r). The value is expressed as a 32-bit word and the bit resolution is 25 μs.

D31

D23

D30

D22

Table 96. TIMESTAMP3 register

D29 D28 D27 D26

Table 97. TIMESTAMP2 register

D21 D20 D19 D18

D25

D17

D24

D16

D15 D14

Table 98. TIMESTAMP1 register

D13 D12 D11 D10 D9 D8

D7 D6

Table 99. TIMESTAMP0 register

D5 D4 D3 D2 D1 D0

D[31:0]

Table 100. TIMESTAMPx register description

Timestamp output registers: 1LSB = 25 μs

The formula below can be used to calculate a better estimation of the actual timestamp resolution:

TS_Res = 1 / (40000 + (0.0015 * INTERNAL_FREQ_FINE * 40000)) where INTERNAL_FREQ_FINE is the content of

INTERNAL_FREQ_FINE (63h) .

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ASM330LHH Register description

9.35 INT_CFG0 (56h)

Activity/inactivity functions, configuration of filtering, and interrupt latch mode configuration

(r/w).

0

(1)

INT_CLR

_ON_

READ

Table 101. INT_CFG0 register

SLEEP_

STATUS_

ON_INT

SLOPE_

FDS

0

(1)

1. This bit must be set to '0' for the correct operation of the device.

0

(1)

0

(1)

LIR

INT_CLR_ON_

READ

SLOPE_FDS

Table 102. INT_CFG0 register description

This bit allows immediately clearing the latched interrupts of an event detection upon the read of the corresponding status register. It must be set to 1 together with LIR. Default value: 0

(0: latched interrupt signal cleared at the end of the ODR period;

1: latched interrupt signal immediately cleared)

SLEEP_STATUS

_ON_INT

Activity/inactivity interrupt mode configuration.

If INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits are enabled, drives the sleep status or sleep change on INT pins. Default value: 0

(0: sleep change notification on INT pins; 1: sleep status reported on INT pins)

HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.

Default value: 0

(0: SLOPE filter applied; 1: HPF applied)

LIR

Latched Interrupt. Default value: 0

(0: interrupt request not latched; 1: interrupt request latched)

9.36 INT_CFG1 (58h)

Enables interrupt function register (r/w)

INTERRUPTS_

ENABLE

INACT_

EN1

Table 103. INT_CFG1 register

INACT_

EN0

0

(1)

0

(1)

1. This bit must be set to '0' for the correct operation of the device.

0

(1)

0

(1)

Table 104. INT_CFG1 register description

INTERRUPTS

_ENABLE

Enables hardcoded functions

INACT_EN[1:0]

Enables activity/inactivity (sleep) function. Default value: 00

(00: stationary/motion-only interrupts generated, XL and gyro do not change;

01: sets accelerometer ODR to 12.5 Hz, gyro does not change;

10: sets accelerometer ODR to 12.5 Hz, gyro to sleep mode;

11: sets accelerometer ODR to 12.5 Hz, gyro to power-down mode)

0

(1)

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Register description ASM330LHH

9.37 THS_6D (59h)

Portrait/landscape position register (r/w)

Table 105. THS_6D register

D4D_

EN

SIXD_THS1 SIXD_THS0 0

(1)

0

(1)

1. This bit must be set to '0' for the correct operation of the device.

0

(1)

D4D_EN

SIXD_THS[1:0]

0

(1)

0

(1)

Table 106. THS_6D register description

Enables detection of 4D orientation. Z-axis position detection is disabled.

Default value: 0 (0: disabled; 1: enabled)

Threshold for 4D/6D function

(00: 80 degrees (default);

01: 70 degrees;

10: 60 degrees;

11: 50 degrees)

9.38 WAKE_UP_THS (5Bh)

Wake-up configuration register (r/w)

Table 107. WAKE_UP_THS register

0

(1)

USR_OFF

_ON_WU

WK_THS5 WK_THS4 WK_THS3 WK_THS2 WK_THS1 WK_THS0

1. This bit must be set to '0' for the correct operation of the device.

USR_OFF_

ON_WU

WK_THS[5:0]

Table 108. WAKE_UP_THS register description

Sends the low-pass filtered data with user offset correction (instead of high-pass filtered data) to the wakeup function.

Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in

WAKE_UP_DUR (5Ch)

. Default value: 000000

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ASM330LHH Register description

9.39 WAKE_UP_DUR (5Ch)

Free-fall, wakeup and sleep mode functions duration setting register (r/w)

FF_DUR5

WAKE_

DUR1

Table 109. WAKE_UP_DUR register

WAKE_

DUR0

WAKE_

THS_W

SLEEP_

DUR3

SLEEP_

DUR2

SLEEP_

DUR1

SLEEP_

DUR0

FF_DUR5

WAKE_DUR[1:0]

WAKE_THS_W

SLEEP_DUR[3:0]

Table 110. WAKE_UP_DUR register description

Free fall duration event. Default: 0

For the complete configuration of the free-fall duration, refer to FF_DUR[4:0] in

FREE_FALL (5Dh)

configuration.

1 LSB = 1 ODR_time

Wake up duration event. Default: 00

1LSB = 1 ODR_time

Weight of 1 LSB of wakeup threshold. Default:0

(0: 1 LSB =FS_XL / (2

1: 1 LSB = FS_XL / (2

8

6

);

))

Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR)

1 LSB = 512 ODR

9.40 FREE_FALL (5Dh)

Free-fall function duration setting register (r/w)

Table 111. FREE_FALL register

FF_DUR4 FF_DUR3 FF_DUR2 FF_DUR1 FF_DUR0 FF_THS2 FF_THS1 FF_THS0

FF_DUR[4:0]

FF_THS[2:0]

Table 112. FREE_FALL register description

Free-fall duration event. Default: 0

For the complete configuration of the free fall duration, refer to FF_DUR5 in

WAKE_UP_DUR (5Ch) configuration

Free fall threshold setting

(000: 156 m g (default);

001: 219 m g;

010: 250 m g;

011: 312 m g;

100: 344 m g;

101: 406 m g;

110: 469 m g;

111: 500 m g)

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Register description ASM330LHH

9.41 MD1_CFG (5Eh)

Functions routing on INT1 register (r/w)

Table 113. MD1_CFG register

INT1_

SLEEP_

CHANGE

0

(1)

INT1_WU INT1_FF 0

(1)

1. This bit must be set to '0' for the correct operation of the device.

INT1_6D 0

(1)

0

(1)

INT1_SLEEP_

CHANGE

(1)

INT1_WU

INT1_FF

INT1_6D

Table 114. MD1_CFG register description

Routing of activity/inactivity recognition event on INT1. Default: 0

(0: routing of activity/inactivity event on INT1 disabled;

1: routing of activity/inactivity event on INT1 enabled)

Routing of wakeup event on INT1. Default value: 0

(0: routing of wakeup event on INT1 disabled;

1: routing of wakeup event on INT1 enabled)

Routing of free-fall event on INT1. Default value: 0

(0: routing of free-fall event on INT1 disabled;

1: routing of free-fall event on INT1 enabled)

Routing of 6D event on INT1. Default value: 0

(0: routing of 6D event on INT1 disabled;

1: routing of 6D event on INT1 enabled)

1. Activity/Inactivity interrupt mode (sleep change or sleep status) depends on SLEEP_STATUS_ON_INT bit in

INT_CFG0 (56h) register.

9.42 MD2_CFG (5Fh)

Functions routing on INT2 register (r/w)

Table 115. MD2_CFG register

INT2_

SLEEP_

CHANGE

0

(1)

INT2_WU INT2_FF 0

(1)

1. This bit must be set to '0' for the correct operation of the device.

INT2_6D 0

(1)

INT2_

TIMESTAMP

INT2_SLEEP_

CHANGE

(1)

Table 116. MD2_CFG register description

Routing of activity/inactivity recognition event on INT2. Default: 0

(0: routing of activity/inactivity event on INT2 disabled;

1: routing of activity/inactivity event on INT2 enabled)

INT2_WU

INT2_FF

Routing of wakeup event on INT2. Default value: 0

(0: routing of wakeup event on INT2 disabled;

1: routing of wake-up event on INT2 enabled)

Routing of free-fall event on INT2. Default value: 0

(0: routing of free-fall event on INT2 disabled;

1: routing of free-fall event on INT2 enabled)

INT2_6D

Routing of 6D event on INT2. Default value: 0

(0: routing of 6D event on INT2 disabled;

1: routing of 6D event on INT2 enabled)

INT2_TIMESTAMP Enables routing on INT2 pin of the alert for timestamp overflow within 6.4 ms

1. Activity/Inactivity interrupt mode (sleep change or sleep status) depends on SLEEP_STATUS_ON_INT bit in

INT_CFG0 (56h)

register.

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ASM330LHH Register description

9.43 INTERNAL_FREQ_FINE (63h)

Internal frequency register (r)

FREQ_

FINE7

FREQ_

FINE6

Table 117. INTERNAL_FREQ_FINE register

FREQ_

FINE5

FREQ_

FINE4

FREQ_

FINE3

FREQ_

FINE2

FREQ_

FINE1

FREQ_

FINE0

FREQ_FINE[7:0]

Table 118. INTERNAL_FREQ_FINE register description

Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.15%. 8-bit format, 2's complement.

The formula below can be used to calculate a better estimation of the actual ODR:

ODR_Actual = (6667 + ((0.0015 * INTERNAL_FREQ_FINE) * 6667)) / ODR_Coeff

Selected_ODR

12.5

26

833

1667

3333

6667

52

104

208

416

ODR_Coeff

512

256

2

1

8

4

128

64

32

16

The Selected_ODR parameter has to be derived from the ODR_XL selection (

Table 39:

CTRL1_XL register description ) in order to estimate the accelerometer ODR and from the

ODR_G selection (

Table 41: CTRL2_G register description ) in order to estimate the

gyroscope ODR.

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Register description ASM330LHH

9.44 X_OFS_USR (73h)

Accelerometer X-axis user offset correction (r/w). The offset value set in the X_OFS_USR offset register is internally subtracted from the acceleration value measured on the X-axis.

X_OFS_

USR_7

X_OFS_

USR_6

Table 119. X_OFS_USR register

X_OFS_

USR_5

X_OFS_

USR_4

X_OFS_

USR_3

X_OFS_

USR_2

X_OFS_

USR_1

X_OFS_

USR_0

X_OFS_USR_

[7:0]

Table 120. X_OFS_USR register description

Accelerometer X-axis user offset correction expressed in two’s complement,

weight depends on USR_OFF_W in CTRL6_C (15h) . The value must be in the

range [-127 127].

9.45 Y_OFS_USR (74h)

Accelerometer Y-axis user offset correction (r/w). The offset value set in the Y_OFS_USR offset register is internally subtracted from the acceleration value measured on the Y-axis.

Y_OFS_

USR_7

Y_OFS_

USR_[7:0]

Y_OFS_

USR_6

Table 121. Y_OFS_USR register

Y_OFS_

USR_5

Y_OFS_

USR_4

Y_OFS_

USR_3

Y_OFS_

USR_2

Y_OFS_

USR_1

Y_OFS_

USR_0

Table 122. Y_OFS_USR register description

Accelerometer Y-axis user offset calibration expressed in 2’s complement, weight depends on USR_OFF_W in

CTRL6_C (15h)

. The value must be in the range

[-127, +127].

9.46 Z_OFS_USR (75h)

Accelerometer Z-axis user offset correction (r/w). The offset value set in the Z_OFS_USR offset register is internally subtracted from the acceleration value measured on the Z-axis.

Z_OFS_

USR_7

Z_OFS_

USR_[7:0]

Z_OFS_

USR_6

Table 123. Z_OFS_USR register

Z_OFS_

USR_5

Z_OFS_

USR_4

Z_OFS_

USR_3

Z_OFS_

USR_2

Z_OFS_

USR_1

Z_OFS_

USR_0

Table 124. Z_OFS_USR register description

Accelerometer Z-axis user offset calibration expressed in 2’s complement, weight depends on USR_OFF_W in

CTRL6_C (15h)

. The value must be in the range

[-127, +127].

70/84 DocID031239 Rev 4

ASM330LHH Register description

9.47 FIFO_DATA_OUT_TAG (78h)

FIFO tag register (r)

TAG_

SENSOR_

4

TAG_

SENSOR_

3

Table 125. FIFO_DATA_OUT_TAG register

TAG_

SENSOR_

2

TAG_

SENSOR_

1

TAG_

SENSOR_

0

TAG_CNT

_1

TAG_CNT

_0

TAG_

PARITY

Table 126. FIFO_DATA_OUT_TAG register description

TAG_SENSOR_[4:0]

Identifies the sensor in:

FIFO_DATA_OUT_X_H (7Ah) and FIFO_DATA_OUT_X_L (79h) ,

FIFO_DATA_OUT_Y_H (7Ch) and FIFO_DATA_OUT_Y_L (7Bh) , and

FIFO_DATA_OUT_Z_H (7Eh) and FIFO_DATA_OUT_Z_L (7Dh)

TAG_CNT_[1:0] 2-bit counter which identifies sensor time slot

TAG_PARITY Parity check of TAG content

TAG_SENSOR_[4:0]

0x01

0x02

0x03

0x04

0x05

Table 127. FIFO tag

Gyroscope

Accelerometer

Temperature

Timestamp

CFG_Change

Sensor name

DocID031239 Rev 4 71/84

84

Register description ASM330LHH

9.48 FIFO_DATA_OUT_X_H (7Ah) and FIFO_DATA_OUT_X_L

(79h)

FIFO data output X (r)

D15

D7

D14

D6

Table 128. FIFO_DATA_OUT_X_H register

D13 D12 D11 D10

Table 129. FIFO_DATA_OUT_X_L register

D5 D4 D3 D2

D9

D1

D8

D0

Table 130. FIFO_DATA_OUT_X_H, FIFO_DATA_OUT_X_L register description

D[15:0] FIFO X-axis output

9.49 FIFO_DATA_OUT_Y_H (7Ch) and FIFO_DATA_OUT_Y_L

(7Bh)

FIFO data output Y (r)

D15

D7

D14

D6

Table 131. FIFO_DATA_OUT_Y_H register

D13 D12 D11 D10

Table 132. FIFO_DATA_OUT_Y_L register

D5 D4 D3 D2

D9

D1

D8

D0

Table 133. FIFO_DATA_OUT_Y_H, FIFO_DATA_OUT_Y_L register description

D[15:0] FIFO Y-axis output

9.50 FIFO_DATA_OUT_Z_H (7Eh) and FIFO_DATA_OUT_Z_L

(7Dh)

FIFO data output Z (r)

D15

D7

D14

D6

Table 134. FIFO_DATA_OUT_Z_H register

D13 D12 D11 D10

Table 135. FIFO_DATA_OUT_Z_L register

D5 D4 D3 D2

D9

D1

D8

D0

Table 136. FIFO_DATA_OUT_Z_H, FIFO_DATA_OUT_Z_L register description

D[15:0] FIFO Z-axis output

72/84 DocID031239 Rev 4

ASM330LHH

10

Typical performance characteristics

Typical performance characteristics

The following distributions were calculated by measuring 100 samples at room temperature in the characterization lab.

10.1 Gyroscope Angular Random Walk (ARW)

Figure 16. ARW gyro / pitch axis

DocID031239 Rev 4 73/84

84

Typical performance characteristics

Figure 17. ARW gyro / roll axis

ASM330LHH

Figure 18. ARW gyro / yaw axis

74/84 DocID031239 Rev 4

ASM330LHH Typical performance characteristics

10.2 Gyroscope Bias Instability (BI)

Figure 19. BI gyro / pitch axis

Figure 20. BI gyro / roll axis

DocID031239 Rev 4 75/84

84

Typical performance characteristics

Figure 21. BI gyro / yaw axis

ASM330LHH

76/84 DocID031239 Rev 4

ASM330LHH Typical performance characteristics

10.3 Gyroscope nonlinearity

Figure 22. Gyro NL / pitch axis

Figure 23. Gyro NL / roll axis

DocID031239 Rev 4 77/84

84

Typical performance characteristics

Figure 24. Gyro NL / yaw axis

ASM330LHH

78/84 DocID031239 Rev 4

ASM330LHH

11 Soldering information

Soldering information

The LGA package is compliant with the ECOPACK, RoHS and "Green" standard.

It is qualified for soldering heat resistance according to JEDEC J-STD-020.

Land pattern and soldering recommendations are available at www.st.com/mems .

DocID031239 Rev 4 79/84

84

Package information

12 Package information

ASM330LHH

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com.

ECOPACK is an ST trademark.

12.1 LGA-14L package information

Figure 25. LGA-14L 2.5 x 3.0 x 0.83 mm ³ (typ.) package outline and mechanical data

3LQLQGLFDWRU

: +

3LQLQGLFDWRU

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7239,(:

[

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/ H

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J

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W K

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+ H L J K W > + @

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0 $ ;

'0B

80/84 DocID031239 Rev 4

ASM330LHH

12.2 LGA-14 packing information

Figure 26. Carrier tape information for LGA-14 package

Package information

Figure 27. LGA-14 package orientation in carrier tape

DocID031239 Rev 4 81/84

84

Package information ASM330LHH

Figure 28. Reel information for carrier tape of LGA-14 package

7

PPPLQ

$FFHVVKROHDW

VORWORFDWLRQ

%

&

1

$

'

)XOOUDGLXV

*PHDVXUHGDWKXE

7DSHVORW

LQFRUHIRU

WDSHVWDUW

PPPLQZLGWK

Table 137. Reel dimensions for carrier tape of LGA-14 package

Reel dimensions (mm)

A (max)

B (min)

C

D (min)

N (min)

G

T (max)

330

1.5

13 ±0.25

20.2

60

12.4 +2/-0

18.4

82/84 DocID031239 Rev 4

ASM330LHH

13 Revision history

Revision history

Date

18-Feb-2019

06-May-2020

Revision

Table 138. Document revision history

Changes

3

4

First public release

Updated Sg in

Table 8: Absolute maximum ratings

Updated linear acceleration self-test output change in Table

Mechanical characteristics

Updated text in

I²C operation

Updated batch data rate for BDR_XL_[3:0] in

FIFO_CTRL3 (09h)

Updated bit 2 in

COUNTER_BDR_REG1 (0Bh)

Updated bit 6 in

ALL_INT_SRC (1Ah)

Updated bits 4 and 6 in

WAKE_UP_SRC (1Bh)

Updated description of bit D4D_EN in THS_6D (59h)

DocID031239 Rev 4 83/84

84

ASM330LHH

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84/84 DocID031239 Rev 4