STMicroelectronics ISM330DLC Datasheet
STMicroelectronics ISM330DLC is an all-in-one motion sensing solution integrating 3D digital accelerometer and gyroscope. The device provides accurate and reliable measurements at ultra-low power consumption which makes it suitable not only for mobile applications but also for power-constrained industrial solutions. The device embeds hardware event-detection and smart features that can be used to optimize motion tracking. These features together with high robustness to mechanical shock make ISM330DLC a preferred choice for a wide range of applications in industrial IoT, robotics, and other industrial automation applications.
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ISM330DLC
Datasheet iNEMO inertial module: 3D accelerometer and 3D gyroscope with digital output for industrial applications
LGA-14L
(2.5 x 3.0 x 0.83 mm) typ.
Product status link
ISM330DLC
Product summary
Order code ISM330DLCTR
Temperature range
[°C]
-40 to +85
Package
Packing
LGA-14L
(2.5 x 3.0 x 0.83 mm)
Tape and reel
Product label
Features
• 3D accelerometer with selectable full scale: ±2/±4/±8/±16 g
• 3D gyroscope with selectable full scale: ±125/±250/±500/±1000/±2000 dps
• Analog supply voltage: 1.71 V to 3.6 V
• SPI & I²C serial interface with main processor data synchronization
• Dedicated gyroscope output chain with low latency, low noise and dedicated low-pass filters for control loop stability (OIS and other stabilization applications)
• Auxiliary SPI serial interface for independent, low-noise low-latency data output for gyroscope and accelerometer
• Ultra-low power consumption for both accelerometer and gyroscope enabling long-lasting battery-operated applications: 0.5 mA in combo normal mode and
0.75 mA in combo high-performance mode
• Smart FIFO up to 4 kbyte
• Smart embedded functions and interrupts: tilt detection, free-fall, wakeup, 6D/4D orientation, click and double-click
• Sensor hub feature to efficiently collect data from additional external sensors
• Embedded hard, soft ironing for external magnetic sensor corrections
• Embedded temperature sensor
• Embedded self-test both for gyroscope and accelerometer
• High shock survivability
• Extended operating temperature range (-40 °C to +85 °C)
• ECOPACK ® , RoHS and “Green” compliant
Applications
• Industrial IoT and connected devices
• Antennas, platforms, and optical image and lens stabilization
• Robotics, drones and industrial automation
• Navigation systems and telematics
• Vibration monitoring and compensation
Description
The ISM330DLC is a system-in-package featuring a high-performance 3D digital accelerometer and 3D digital gyroscope tailored for Industry 4.0 applications.
ST’s family of MEMS sensor modules leverages the robust and mature manufacturing processes already used for the production of micromachined accelerometers and gyroscopes.
The various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are developed using CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the characteristics of the sensing element.
In the ISM330DLC the sensing element of the accelerometer and of the gyro are implemented on the same silicon die, thus guaranteeing superior stability and robustness.
DS12171 - Rev 3 - November 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
ISM330DLC
The ISM330DLC has a full-scale acceleration range of ±2/±4/±8/±16 g and an angular rate range of ±125/±250/±500/±1000/±2000 dps.
Delivering high accuracy and stability with ultra-low power consumption (0.75 mA in high-performance, combo mode) enables, also in the industrial domain, long-lasting battery-operated applications.
The ISM330DLC includes a dedicated configurable signal processing path with low latency, low noise and dedicated filtering specifically intended for control loop stability. Data from this dedicated signal path can be made available through an auxiliary SPI interface, configurable for both the gyroscope and accelerometer. Highperformance, high-quality, small size and low power consumption together with high robustness to mechanical shock makes the ISM330DLC the preferred choice of system designers for the creation and manufacturing of versatile and reliable products.
The ISM330DLC is available in a plastic, land grid array (LGA) package.
DS12171 - Rev 3 page 2/116
1
ISM330DLC
Overview
Overview
The ISM330DLC is a system-in-package featuring a high-performance 3D digital accelerometer and 3D digital gyroscope tailored for Industry 4.0 applications.
The ISM330DLC has a full-scale acceleration range of ±2/±4/±8/±16 g, an angular rate range of
±125/±250/±500/±1000/±2000 dps and is capable of delivering highly accurate and reliable measurements at an ultra-low power consumption (0.75 mA in high-performance, combo mode).
The ISM330DLC embeds smart features which simplify and optimize the application design and allows the usage of complex motion-sensing information also in power-constrained applications
The event-detection interrupts enable efficient and reliable motion tracking and contextual awareness, implementing hardware recognition of free-fall events, 6D orientation, click and double-click sensing, activity or inactivity, and wakeup events.
Up to 4 kbyte of FIFO with dynamic allocation of significant data (i.e. external sensors, timestamp, etc.) allows overall power saving of the system and protects against any loss of data.
With the sensor hub feature, data from up to 4 external sensors can be collected and stored in the internal FIFO without intervention of the application microcontroller.
Moreover, the ISM330DLC offers specific support, both for the gyroscope and the accelerometer, to applications requiring closed control loop. The device, through a dedicated auxiliary SPI interface and a configurable signal processing path having low latency and low noise, can provide data for the control loop while, at the same time, a second fully independent path can output data for other application intents.
Like the entire portfolio of MEMS sensor modules, the ISM330DLC leverages the robust and mature in-house manufacturing processes already used for the production of micromachined accelerometers and gyroscopes. The various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are developed using CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the characteristics of the sensing element.
In the ISM330DLC, the sensing element of the accelerometer and of the gyroscope are implemented on the same silicon die, thus guaranteeing superior stability and robustness.
The ISM330DLC is available in a small plastic land grid array (LGA) package of 2.5 x 3.0 x 0.83 mm.
DS12171 - Rev 3 page 3/116
2
2.1
ISM330DLC
Embedded smart features
Embedded smart features
The ISM330DLC features the following on-chip smart functions:
• 4 kbyte data buffering
– 100% efficiency with flexible configurations and partitioning
– Possibility to store timestamp
•
•
•
Event-detection interrupts (fully configurable)
– Free-fall
– Wakeup
– 6D orientation
– Click and double-click sensing
– Activity / inactivity recognition
– Tilt (refer to
for additional information)
Sensor hub
– Up to 6 total sensors: 2 internal (accelerometer and gyroscope) and 4 external sensors
Data rate synchronization with external trigger
Tilt detection
The tilt function helps to detect activity change and has been implemented in hardware using only the accelerometer to achieve both the targets of ultra-low power consumption and robustness during the short duration of dynamic accelerations.
The tilt function is based on a trigger of an event each time the device's tilt changes. It is configurable through:
• a programmable average window
• a programmable average threshold
DS12171 - Rev 3 page 4/116
3
Pin description
Figure 1. Pin connections
ISM330DLC
Pin description
DS12171 - Rev 3 page 5/116
ISM330DLC
Pin connections
3.1
Pin connections
•
•
The ISM330DLC offers flexibility to connect the pins in order to have four different mode connections and functionalities. In detail:
Mode 1 : I²C slave interface or SPI (3- and 4-wire) serial interface is available;
Mode 2 : I²C slave interface or SPI (3- and 4-wire) serial interface and I²C interface master for external sensor connections are available;
•
•
Mode 3: I²C slave interface or SPI (3- and 4-wire) serial interface is available for the application processor interface while an auxiliary SPI (3- and 4-wire) serial interface is available for an auxiliary host to access the gyroscope ONLY;
Mode 4: I²C slave interface or SPI (3- and 4-wire) serial interface is available for the application processor interface while an auxiliary SPI (3- and 4-wire) serial interface is available for an auxiliary host to access the accelerometer and gyroscope.
Figure 2. ISM330DLC connection modes
Mode 1
HOST
I 2 C/SPI (3/4-w)
ISM330DLC
Mode 2
HOST
I 2 C/SPI (3/4-w)
Mode 3
HOST
I 2 C/SPI (3/4-w)
Mode 4
HOST
I 2 C/SPI (3/4-w)
ISM330DLC
Master I 2 C
LSM6DSM sensors
ISM330DLC ISM330DLC
Aux SPI (3/4-w) For gyro data only
AUX HOST
Aux SPI (3/4-w) For XL and gyro data
AUX HOST
In the following table each mode is described for the pin connections and function.
Pin # Name Mode 1 function
1 SDO/SA0
SPI 4-wire interface serial data output (SDO)
I²C least significant bit of the device address (SA0)
2
3
4
5
SDx
SCx
INT1
Connect to VDDIO or GND
Connect to VDDIO or GND
Table 1. Pin desription
Mode 2 function
SPI 4-wire interface serial data output
(SDO)
I²C least significant bit of the device address (SA0)
I²C serial data master (MSDA)
I²C serial clock master (MSCL)
Mode 3 / Mode 4 function
SPI 4-wire interface serial data output
(SDO)
I²C least significant bit of the device address (SA0)
Auxiliary SPI 3/4-wire interface serial data input (SDI) and SPI 3-wire serial data output (SDO)
Auxiliary SPI (3/4-wire) interface serial port clock (SPC_Aux)
Programmable interrupt 1
Power supply for I/O pins
DS12171 - Rev 3 page 6/116
ISM330DLC
Pin connections
Pin # Name
6
7
8
9
10
11
12
13
14
GND
GND
VDD
INT2
SDO_Aux
CS
SCL
SDA
I²C/SPI mode selection
(1: SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled)
I²C serial clock (SCL)
SPI serial port clock (SPC)
I²C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output
(SDO)
Mode 1 function
Programmable interrupt 2 (INT2) /
Data enable (DEN)
Connect to VDD_IO or leave
Mode 2 function
0 V supply
0 V supply
Power supply
Programmable interrupt 2 (INT2) /
Data enable (DEN)/
I²C master external synchronization signal (MDRDY)
Mode 3 / Mode 4 function
Programmable interrupt 2 (INT2) / Data enable (DEN)
Connect to VDD_IO or leave
Auxiliary SPI 3/4-wire interface enable
Auxiliary SPI 3-wire interface: leave
Auxiliary SPI 4-wire interface: serial data output (SDO_Aux)
I²C/SPI mode selection
(1: SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled)
I²C serial clock (SCL)
SPI serial port clock (SPC)
I²C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output
(SDO)
I²C/SPI mode selection
(1: SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled)
I²C serial clock (SCL)
SPI serial port clock (SPC)
I²C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
1. Recommended 100 nF filter capacitor.
2. Leave pin electrically unconnected and soldered to PCB.
DS12171 - Rev 3 page 7/116
ISM330DLC
Module specifications
4
Module specifications
4.1
Mechanical characteristics
@ Vdd = 1.8 V, T = 25 °C unless otherwise noted.
Symbol Parameter
Table 2. Mechanical characteristics
LA_FS Linear acceleration measurement range
G_FS Angular rate measurement range
LA_So
Linear acceleration sensitivity (3)
G_So
LA_SoDr Linear acceleration sensitivity change vs. temperature
G_SoDr Angular rate sensitivity change vs. temperature
Test conditions
FS = ±2
FS = ±4
FS = ±8
FS = ±16
FS = ±125
FS = ±250
FS = ±500
FS = ±1000
FS = ±2000 from -40° to +85° delta from T = +25° from -40° to +85° delta from T = +25°
-3%
-3% 4.375
8.75
17.50
35
70
±500
±1000
±2000
0.061
0.122
0.244
0.488
Typ.
±2
±4
±8
±16
±125
±250
+3%
+3% m
Unit dps g g
/LSB mdps/LSB
-0.024
-0.048
±0.01
±0.007
+0.024
+0.048
%/°C
%/°C
LA_TyOff Linear acceleration zero-g level offset accuracy (5)
G_TyOff
Angular rate zero-rate level (5)
LA_OffDr Linear acceleration zero-g level change vs. temperature
G_OffDr Angular rate typical zero-rate level change vs. temperature
-85 ±40
±2
±0.1
±0.015
+85 m g dps mg/ °C dps/°C
LA_NL Linear acceleration nonlinearity
G_NL Angular rate nonlinearity
@FS = ±8 g
Best-fit straight line
@FS = ±2000 dps
Best-fit straight line
±2
±0.07
%FS
%FS
Rn Rate noise density in high-performance mode
RnRMS Gyroscope RMS noise in normal/low-power mode
3.8
75
11 mdps/√Hz mdps
DS12171 - Rev 3 page 8/116
ISM330DLC
Mechanical characteristics
Symbol
An
RMS
Parameter
Acceleration noise density in high-performance mode
Acceleration RMS noise in normal/low-power mode
LA_ODR Linear acceleration output data rate
G_ODR Angular rate output data rate
Test conditions
FS = ±2 g
FS = ±4 g
FS = ±8 g
FS = ±16 g
FS = ±2 g
FS = ±4 g
FS = ±8 g
FS = ±16 g
LA_F0 Sensor resonant frequency
X,Y-axis
Z-axis
G_F0 Sensor resonant frequency
Vst
Linear acceleration self-test output change
Angular rate self-test output change
FS = ±250 dps
FS = ±2000 dps
Top Operating temperature range
1. Min/Max values are based on characterization results, not tested in production and not guaranteed.
2. Typical specifications are not guaranteed.
3. Sensitivity values after factory calibration test and trimming.
4. Measurements are performed in a uniform temperature setup and they are based on characterization data in a limited number of samples. Not measured during final test for production.
5. Values after factory calibration test and trimming.
6. Gyroscope rate noise density in high-performance mode is independent of the ODR and FS setting.
7. Gyroscope RMS noise in normal/low-power mode is independent of the ODR and FS setting.
90
20
150
-40
1.8
2.0
2.4
3.0
104
208
416
833
1.6
12.5
26
52
1666
3332
6664
12.5
26
52
104
208
416
833
1666
3332
6664
3.0
2.2
20
Typ.
75
80
90
130
170
170
180
230
1700
80
700
+85
µ
Unit g /√Hz m g (RMS)
Hz
Hz kHz kHz m g dps dps
°C
DS12171 - Rev 3 page 9/116
8. Accelerometer noise density in high-performance mode is independent of the ODR.
9. Accelerometer RMS noise in normal/low-power mode is independent of the ODR.
10. Noise RMS related to BW = ODR/2 (for ODR/9, typ value can be calculated by Typ *0.6).
11. This ODR is available when accelerometer is in low-power mode.
12. The sign of the linear acceleration self-test output change is defined by the STx_XL bits in
,
13. The linear acceleration self-test output change is defined with the device in stationary condition as the absolute value of: OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 0.061 mg at ±2 g full scale.
14. Accelerometer self-test limits are full-scale independent.
15. The sign of the angular rate self-test output change is defined by the STx_G bits in
16. The angular rate self-test output change is defined with the device in stationary condition as the absolute value of: OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 70 mdps at
±2000 dps full scale.
ISM330DLC
Mechanical characteristics
DS12171 - Rev 3 page 10/116
ISM330DLC
Electrical characteristics
4.2
Electrical characteristics
@ Vdd = 1.8 V, T = 25 °C unless otherwise noted.
Table 3. Electrical characteristics
IddPD
Ton
V
IH
V
IL
V
OH
V
OL
Top
Symbol
Vdd Supply voltage
Vdd_IO Power supply for I/O
IddHP
IddNM
IddLP
Parameter Test conditions
Gyroscope and accelerometer current consumption in high-performance mode ODR = 1.6 kHz
Gyroscope and accelerometer current consumption in normal mode ODR = 208 Hz
Gyroscope and accelerometer current consumption in low-power mode ODR = 52 Hz
LA_IddHP Accelerometer current consumption in high-performance mode
LA_IddNM Accelerometer current consumption in normal mode
LA_IddLM Accelerometer current consumption in low-power mode
ODR < 1.6 kHz
ODR ≥ 1.6 kHz
ODR = 208 Hz
ODR = 52 Hz
ODR = 12.5 Hz
ODR = 1.6 Hz
Gyroscope and accelerometer current consumption during power-down
Turn-on time
Digital high-level input voltage
Digital low-level input voltage
High-level output voltage
Low-level output voltage
Operating temperature range
I
I
OH
OL
Min.
1.71
1.62
0.7 *VDD_IO
VDD_IO - 0.2
-40
Typ.
1.8
0.75
0.5
0.35
180
190
85
25
9
4.5
10
35
Max.
3.6
3.6
0.3 *VDD_IO
0.2
+85
Unit
V
V mA mA mA
µA
µA
µA
µA ms
V
V
V
V
°C
1. Typical specifications are not guaranteed.
2. 4 mA is the maximum driving capability, i.e. the maximum DC current that can be sourced/sunk by the digital pad in order to guarantee the correct digital output voltage levels V
OH
and V
OL
.
4.3
Temperature sensor characteristics
@ Vdd = 1.8 V, T = 25 °C unless otherwise noted.
Table 4. Temperature sensor characteristics
Symbol
Toff
TSen
TST
T_ADC_res
Top
Parameter
Temperature refresh rate
Temperature offset
Temperature sensitivity
Temperature stabilization time
Temperature ADC resolution
Operating temperature range
Test condition Min.
-15
-40
1. Typical specifications are not guaranteed.
2. When the accelerometer is in Low-Power mode and the gyroscope part is turned off, the TODR value is equal to the accelerometer ODR.
3. The output of the temperature sensor is 0 LSB (typ.) at 25 °C.
4. Time from power ON bit to valid data based on characterization data.
52
256
16
Max.
+15
500
+85
Unit
Hz
°C
LSB/°C
µs bit
°C
DS12171 - Rev 3 page 11/116
ISM330DLC
Communication interface characteristics
4.4
4.4.1
Communication interface characteristics
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 5. SPI slave timing values
Symbol Parameter Unit
Min Max t c(SPC) f c(SPC) t su(CS) t h(CS) t su(SI) t h(SI) t v(SO) t h(SO) t dis(SO)
SPI clock cycle
SPI clock frequency
CS setup time
CS hold time
SDI input setup time
SDI input hold time
SDO valid output time
SDO output hold time
SDO output disable time
100
5
20
5
15
5
10
50
50 ns
MHz ns
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production
Figure 3. SPI slave timing diagram
Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO for both input and output ports.
DS12171 - Rev 3 page 12/116
ISM330DLC
Communication interface characteristics
4.4.2
4.4.2.1
Note:
I²C- inter-IC control interface
Subject to general operating conditions for Vdd and Top.
Figure 4. I²C timing diagram
START t su(SR) t w(SP:SR)
REPEATED
START
START
SDA t su(SDA) t h(SDA) t su(SP)
STOP
SCL t h(ST) t w(SCLL) t w(SCLH)
I²C slave
Table 6. I²C slave timing values
Symbol Parameter
Min f
(SCL) t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t h(ST) t su(SR) t su(SP) t w(SP:SR)
SCL clock frequency
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
START condition hold time
Repeated START condition setup time
STOP condition setup time
Bus free time between STOP and START condition
0
4.7
4.0
250
0
4
4.7
4.7
1. Data based on standard I²C protocol requirement, not tested in production.
4
Max
100
3.45
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO for both ports.
0.6
0.6
1.3
100
0
0.6
I²C fast mode
Min Max
0 400
1.3
0.6
0.9
Unit kHz
µs ns
µs
µs
DS12171 - Rev 3 page 13/116
ISM330DLC
Communication interface characteristics
4.4.2.2
I²C master
When in I²C Master Mode, an external sensor can be connected to the ISM330DLC. The ISM330DLC supports
I²C Master - Fast Mode only.
Symbol
Table 7. I²C slave timing values
Parameter f
(SCL)
SCL clock frequency t t w(SCLL) w(SCLH) t su(SR) t su(HD) t su(SP) t w(SP:SR)
SCL clock low time
SCL clock high time
Data valid time
SDA hold time
SDA setup time
Repeated START condition setup time
Repeated START condition hold time
STOP condition setup time
Bus free time between STOP and START condition
I²C Master
116.3
5.86
2.74
3.9
≥0
≥100
1.56
1.56
2.73
21
I²C Fast Mode (min)
0
(400 kHz max)
1.3
0.6
-
0
100
0.6
0.6
0.6
1.3
Unit kHz
µs
µs
µs
µs ns
µs ns ns
µs
DS12171 - Rev 3 page 14/116
4.5
Note:
ISM330DLC
Absolute maximum ratings
Absolute maximum ratings
Stresses above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Symbol
Vdd
T
STG
Sg
ESD
Vin
Table 8. Absolute maximum ratings
Ratings
Supply voltage
Storage temperature range
Acceleration g for 0.2 ms
Electrostatic discharge protection (HBM)
Input voltage on any control pin
(including CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0)
Maximum value
-0.3 to 4.8
-40 to +125
10,000
2
0.3 to Vdd_IO +0.3
Unit
V
°C g kV
V
Supply voltage on any pin should never exceed 4.8 V.
This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part.
This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part.
DS12171 - Rev 3 page 15/116
ISM330DLC
Terminology
4.6
4.6.1
4.6.2
Terminology
Sensitivity
Linear acceleration sensitivity can be determined, for example, by applying 1 g acceleration to the device.
Because the sensor can measure DC accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and over time. The sensitivity tolerance describes the range of sensitivities of a large number of sensors (see mechanical characteristics).
An angular rate gyroscope is a device that produces a positive-going digital output for counterclockwise rotation around the axis considered. Sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. This value changes very little over temperature and time (see mechanical characteristics).
Zero-g and zero-rate level
Linear acceleration zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g on both the X-axis and Y-axis, whereas the Z-axis will measure 1 g. Ideally, the output is in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2’s complement number). A deviation from the ideal value in this case is called zero-g offset.
Offset is to some extent a result of stress to MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Linear acceleration zero-g level change vs. temperature” in the mechanical characteristics. The zero-g level tolerance (TyOff) describes the standard deviation of the range of zero-g levels of a group of sensors.
Zero-rate level describes the actual output signal if there is no angular rate present. The zero-rate level of precise
MEMS sensors is, to some extent, a result of stress to the sensor and therefore the zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress.
This value changes very little over temperature and time (see mechanical characteristics).
DS12171 - Rev 3 page 16/116
ISM330DLC
Functionality
5
Functionality
5.1
5.2
5.3
5.4
Operating modes
•
•
In the ISM330DLC, the accelerometer and the gyroscope can be turned on/off independently of each other and are allowed to have different ODRs and power modes.
The ISM330DLC has three operating modes available:
• only accelerometer active and gyroscope in power-down only gyroscope active and accelerometer in power-down both accelerometer and gyroscope sensors active with independent ODR
The accelerometer is activated from power-down by writing ODR_XL[3:0] in
CTRL1_XL (10h) while the gyroscope
is activated from power-down by writing ODR_G[3:0] in CTRL2_G (11h)
. For combo-mode the ODRs are totally independent.
Gyroscope power modes
In the ISM330DLC, the gyroscope can be configured in four different operating modes: power-down, low-power, normal mode and high-performance mode. The operating mode selected depends on the value of the
G_HM_MODE bit in
CTRL7_G (16h) . If G_HM_MODE is set to '0', high-performance mode is valid for all ODRs
(from 12.5 Hz up to 6.66 kHz).
To enable the low-power and normal mode, the G_HM_MODE bit has to be set to '1'. Low-power mode is available for lower ODRs (12.5, 26, 52 Hz) while normal mode is available for ODRs equal to 104 and 208 Hz.
Accelerometer power modes
In the ISM330DLC, the accelerometer can be configured in four different operating modes: power-down, lowpower, normal mode and high-performance mode. The operating mode selected depends on the value of the
XL_HM_MODE bit in
. If XL_HM_MODE is set to '0', high-performance mode is valid for all ODRs
(from 12.5 Hz up to 6.66 kHz).
To enable the low-power and normal mode, the XL_HM_MODE bit has to be set to '1'. Low-power mode is available for lower ODRs (1.6, 12.5, 26, 52 Hz) while normal mode is available for ODRs equal to 104 and 208
Hz.
Block diagram of filters
Figure 5. Block diagram of filters
DS12171 - Rev 3 page 17/116
ISM330DLC
Block diagram of filters
5.4.1
Block diagrams of the gyroscope filters
In the ISM330DLC, the gyroscope filtering chain depends on the mode configuration:
1. Mode 1 (for General Purpose (GP) functionality through primary interface) and Mode 2
Figure 6. Gyroscope digital chain - Mode 1 (GP) and Mode 2
ADC
HPF
0
1
0
1
LPF1
HP_EN_G FTYPE [1:0] LPF1_SEL_G
LPF2
ODR_G
SPI/I
2
C
FIFO
In this configuration, the gyroscope ODR is selectable from 12.5 Hz up to 6.66 kHz. A low-pass filter (LPF1) is available if the auxiliary SPI is disabled, for more details about the filter characteristics see
.
Data can be acquired from the output registers and FIFO over the primary I²C/SPI interface.
2. Mode 3 / Mode 4 (for control loop functionality (OIS))
Figure 7. Gyroscope digital chain - Mode 3 / Mode 4 (OIS)
Note:
ADC
SPI/I
2
C
HPF
0
1
LPF2
ODR_G
HP_EN_G
0
1
LPF1
FTYPE_ [1:0] _OIS
HP_EN_OIS
FIFO
SPI_Aux
HP_EN_OIS is active to select HPF on the auxiliary SPI chain only if HPF is not already used in the primary interface.
In this configuration, there are two paths:
• the chain for general purpose (GP) where the ODR is selectable from 12.5 Hz up to 6.66 kHz
• the chain for OIS where the ODR is at 6.66 kHz and the LPF1 is available. For more details about the filter
characteristics see Table 215. Gyroscope OIS chain LPF1 bandwidth selection .
DS12171 - Rev 3 page 18/116
ISM330DLC
Block diagram of filters
5.4.2
•
Block diagrams of the accelerometer filters
In the ISM330DLC, the filtering chain for the accelerometer part is composed of the following:
• Analog filter (anti-aliasing)
• Digital filter (LPF1)
Composite filter
Details of the block diagram appear in the following figure.
Figure 8. Accelerometer chain
Analog
Anti-aliasing
LP Filter
Digital
LP Filter
LPF1
ADC
Composite
Filter
LPF1_BW_SEL
INPUT_COMPOSITE
The configuration of the digital filter can be set using the LPF1_BW_SEL bit in
INPUT_COMPOSITE bit in
DS12171 - Rev 3 page 19/116
ISM330DLC
Block diagram of filters
Figure 9. Accelerometer composite filter (for Modes 1/2 and Mode 3*)
Note: * Mode 3 is available only if Mode4_EN = 0 and OIS_EN_SPI2 = 1 in
DS12171 - Rev 3 page 20/116
Figure 10. Accelerometer composite filter (Mode 4 only*)
ISM330DLC
Block diagram of filters
Note: *Mode 4 is enabled when Mode4_EN = 1 and OIS_EN_SPI2 = 1 in
DS12171 - Rev 3 page 21/116
ISM330DLC
FIFO
5.5
5.5.1
5.5.2
FIFO
•
•
•
•
The presence of a FIFO allows consistent power saving for the system since the host processor does not need continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO.
The ISM330DLC embeds 4 kbytes data FIFO to store the following data:
• gyroscope accelerometer external sensors timestamp temperature
Writing data in the FIFO can be configured to be triggered by the:
• accelerometer/gyroscope data-ready signal; in which case the ODR must be lower than or equal to both the accelerometer and gyroscope ODRs;
• sensor hub data-ready signal;
•
•
In addition, each data can be stored at a decimated data rate compared to FIFO ODR and it is configurable by the user, setting the
registers. The available decimation factors are 2, 3,
4, 8, 16, 32.
The programmable FIFO threshold can be set in
FIFO_CTRL1 (06h) and FIFO_CTRL2 (07h)
using the FTH
[10:0] bits.
To monitor the FIFO status, dedicated registers ( FIFO_STATUS1 (3Ah)
,
,
FIFO_STATUS4 (3Dh) ) can be read to detect FIFO overrun events, FIFO full status, FIFO empty status,
FIFO threshold status and the number of unread samples stored in the FIFO. To generate dedicated interrupts on
the INT1 and INT2 pads of these status events, the configuration can be set in INT1_CTRL (0Dh) and
•
•
The FIFO buffer can be configured according to five different modes:
• Bypass mode
FIFO mode
Continuous mode
Continuous-to-FIFO mode
Bypass-to-continuous mode
Each mode is selected by the FIFO_MODE_[2:0] bits in the
FIFO_CTRL5 (0Ah) register. To guarantee the correct
acquisition of data during the switching into and out of FIFO mode, the first sample acquired must be discarded.
Bypass mode
In Bypass mode (
FIFO_CTRL5 (0Ah) (FIFO_MODE_[2:0] = 000), the FIFO is not operational and it remains
empty.
Bypass mode is also used to reset the FIFO when in FIFO mode.
FIFO mode
In FIFO mode ( FIFO_CTRL5 (0Ah)
(FIFO_MODE_[2:0] = 001) data from the output channels are stored in the
FIFO until it is full.
To reset FIFO content, Bypass mode should be selected by writing
(FIFO_MODE_[2:0]) to
'000' After this reset command, it is possible to restart FIFO mode by writing
(FIFO_MODE_[2:0]) to '001'.
FIFO buffer memorizes up to 4096 samples of 16 bits each but the depth of the FIFO can be resized by setting the FTH [10:0] bits in
FIFO_CTRL1 (06h) and FIFO_CTRL2 (07h)
. If the STOP_ON_FTH bit in
DS12171 - Rev 3 page 22/116
ISM330DLC
FIFO
5.5.3
5.5.4
5.5.5
5.5.6
Continuous mode
Continuous mode (
FIFO_CTRL5 (0Ah) (FIFO_MODE_[2:0] = 110) provides a continuous FIFO update: as new
data arrives, the older data is discarded.
A FIFO threshold flag
FIFO_STATUS2 (3Bh) (FTH) is asserted when the number of unread samples in FIFO is
greater than or equal to
FIFO_CTRL1 (06h) and FIFO_CTRL2 (07h)
(FTH [10:0]).
It is possible to route FIFO_STATUS2 (3Bh)
(FTH) to the INT1 pin by writing in register
(INT1_FTH) = ‘1’ or to the INT2 pin by writing in register INT2_CTRL (0Eh)
(INT2_FTH) = ‘1’.
A full-flag interrupt can be enabled,
(INT_ FULL_FLAG) = '1', in order to indicate FIFO saturation and eventually read its content all at once.
If an overrun occurs, at least one of the oldest samples in FIFO has been overwritten and the OVER_RUN flag in
FIFO_STATUS2 (3Bh) is asserted.
In order to empty the FIFO before it is full, it is also possible to pull from FIFO the number of unread samples
available in FIFO_STATUS1 (3Ah) and FIFO_STATUS2 (3Bh)
(DIFF_FIFO [10:0]).
Continuous-to-FIFO mode
In Continuous-to-FIFO mode (
FIFO_CTRL5 (0Ah) (FIFO_MODE_[2:0] = 011), FIFO behavior changes according
to the trigger event detected in one of the following interrupt registers
,
,
When the selected trigger bit is equal to '1', FIFO operates in FIFO mode.
When the selected trigger bit is equal to '0', FIFO operates in Continuous mode.
Bypass-to-Continuous mode
In Bypass-to-Continuous mode ( FIFO_CTRL5 (0Ah)
(FIFO_MODE_[2:0] = '100'), data measurement storage inside FIFO operates in Continuous mode when selected triggers in one of the following interrupt registers
,
,
and D6D_SRC (1Dh) are equal to '1', otherwise
FIFO content is reset (Bypass mode).
FIFO reading procedure
The data stored in FIFO are accessible from dedicated registers (
and
) and each FIFO sample is composed of 16 bits.
All FIFO status registers (
FIFO_STATUS1 (3Ah) , FIFO_STATUS2 (3Bh) , FIFO_STATUS3 (3Ch) ,
Saving data in the FIFO buffer is organized in four FIFO data sets consisting of 6 bytes each:
The 1 st FIFO data set is reserved for gyroscope data;
The 2 nd FIFO data set is reserved for accelerometer data;
The 3 rd
FIFO data set is reserved for the external sensor data stored in the registers from SENSORHUB1_REG
The 4 th FIFO data set can be alternately associated to the external sensor data stored in the registers from
, and timestamp info, or to the temperature sensor data.
DS12171 - Rev 3 page 23/116
ISM330DLC
Digital interfaces
6
Digital interfaces
6.1
6.2
6.3
I²C/SPI interface
The registers embedded inside the ISM330DLC may be accessed through both the I²C and SPI serial interfaces.
The latter may be SW configured to operate either in 3-wire or 4-wire interface mode.
The serial interfaces are mapped onto the same pins. To select/exploit the I²C interface, the CS line must be tied high (i.e connected to Vdd_IO).
Pin name
CS
SCL/SPC
SDA/SDI/SDO
SDO/SA0
Table 9. Serial interface pin description
Pin description
SPI enable
I²C/SPI mode selection
(1: SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled)
I²C Serial Clock (SCL)
SPI Serial Port Clock (SPC)
I²C Serial Data (SDA)
SPI Serial Data Input (SDI)
3-wire Interface Serial Data Output (SDO)
SPI Serial Data Output (SDO)
I²C less significant bit of the device address
Master I²C
If the ISM330DLC is configured in Mode 2, a master I²C line is available. The master serial interface is mapped in the following dedicated pins.
Pin name
MSCL
MSDA
MDRDY
Table 10. Master I²C pin details
I²C serial clock master
I²C serial data master
I²C master external synchronization signal
Pin description
Auxiliary SPI
If ISM330DLC is configured in Mode 3, the auxiliary SPI is available. The auxiliary SPI interface is mapped in the following dedicated pins.
Table 11. Auxiliary SPI pin details
Pin name Pin description
OCS_Aux Auxiliary SPI 3/4-wire enable
SDx Auxiliary SPI 3/4-wire data input (SDI_Aux) and SPI 3-wire data output (SDO_Aux)
SCx Auxiliary SPI 3/4-wire interface serial port clock
SDO_Aux SPI serial data
DS12171 - Rev 3 page 24/116
ISM330DLC
I²C serial interface
6.4
I²C serial interface
The ISM330DLC I²C is a bus slave. The I²C is employed to write the data to the registers, whose content can also be read back.
The relevant I²C terminology is provided in the table below.
Table 12. I²C terminology
Term
Transmitter The device which sends data to the bus
Receiver
Master
Slave
The device which receives data from the bus
Description
The device which initiates a transfer, generates clock signals and terminates a transfer
The device addressed by the master
6.4.1
Command
Read
Write
Read
Write
There are two signals associated with the I²C bus: the serial clock line (SCL) and the Serial DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines must be connected to Vdd_IO through external pull-up resistors. When the bus is free, both the lines are high.
The I²C interface is implemeted with fast mode (400 kHz) I²C standards as well as with the standard mode.
In order to disable the I²C block, (I2C_disable) = 1 must be written in CTRL4_C (13h) .
I²C operation
The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to
LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master.
The Slave ADdress (SAD) associated to the ISM330DLC is 110101xb. The SDO/SA0 pin can be used to modify the less significant bit of the device address. If the SDO/SA0 pin is connected to the supply voltage, LSb is ‘1’
(address 1101011b); else if the SDO/SA0 pin is connected to ground, the LSb value is ‘0’ (address 1101010b).
This solution permits to connect and address two different inertial modules to the same I²C bus.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received.
The I²C embedded inside the ISM330DLC behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted. The increment of the address is configured by the
(IF_INC).
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the master will transmit to the slave with direction unchanged. The following table explains how the SAD+Read/Write bit pattern is composed, listing all the possible configurations.
SAD[6:1]
110101
110101
110101
110101
Table 13. SAD_Read/Write patterns
SAD[0] = SA0
0
0
1
1
R/W
1
0
1
0
SAD+R/W
11010101 (D5h)
11010100 (D4h)
11010111 (D7h)
11010110 (D6h)
DS12171 - Rev 3 page 25/116
ISM330DLC
I²C serial interface
Master
Slave
Master
Slave
ST
ST
Table 14. Transfer when master is writing one byte to slave
SAD + W SUB DATA
SAK SAK
Table 15. Transfer when master is writing multiple bytes to slave
SAD + W SUB DATA DATA
SAK SAK SAK
SAK
SAK
SP
SP
Master
Slave
ST
Table 16. Transfer when master is receiving (reading) one byte of data from slave
SAD + W SUB SR SAD + R NMAK
SAK SAK SAK DATA
SP
Table 17. Transfer when master is receiving (reading) multiple bytes of data from slave
Master ST SAD+W
Slave SAK
SUB
SAK
SR SAD+R
SAK DATA
MAK
DATA
MAK
DATA
NMAK SP
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit (MSb) first. If a receiver can’t receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left HIGH by the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a
STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.
In the presented communication format MAK is Master acknowledge and NMAK is No Master Acknowledge.
DS12171 - Rev 3 page 26/116
6.5
ISM330DLC
SPI bus interface
SPI bus interface
The ISM330DLC SPI is a bus slave. The SPI allows writing and reading the registers of the device.
The serial interface communicates to the application using 4 wires: CS , SPC , SDI and SDO .
Figure 11. Read and write protocol
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are, respectively, the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC .
Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling edges of SPC . The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS .
bit 0 : RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SDO at the start of bit 8.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
(IF_INC) bit is ‘1’, the address used to read/write data is increased at every block.
The function and the behavior of SDI and SDO remain unchanged.
DS12171 - Rev 3 page 27/116
ISM330DLC
SPI bus interface
6.5.1
SPI read
Figure 12. SPI read protocol
CS
SPC
SDI
SDO
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI Read command is performed with 16 clock pulses. A multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one.
bit 0 : READ bit. The value is 1.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DO(7:0) (read mode). This is the data that will be read from the device (MSb first).
bit 16-...
: data DO(...-8). Further data in multiple byte reads.
Figure 13. Multiple byte SPI read protocol (2-byte example)
CS
SPC
SDI
SDO
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14 DO13 DO12 DO11DO10 DO9 DO8
DS12171 - Rev 3 page 28/116
ISM330DLC
SPI bus interface
6.5.2
SPI write
Figure 14. SPI write protocol
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
6.5.3
The SPI Write command is performed with 16 clock pulses. A multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one.
bit 0 : WRITE bit. The value is 0.
bit 1 -7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DI(7:0) (write mode). This is the data that is written inside the device (MSb first).
bit 16-... : data DI(...-8). Further data in multiple byte writes.
Figure 15. Multiple byte SPI write protocol (2-byte example)
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
SPI read in 3-wire mode
A 3-wire mode is entered by setting the
CTRL3_C (12h) (SIM) bit equal to ‘1’ (SPI serial interface mode
selection).
Figure 16. SPI read protocol in 3-wire mode
CS
SPC
SDI/O
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI read command is performed with 16 clock pulses: bit 0 : READ bit. The value is 1.
bit 1-7 : address AD(6:0). This is the address field of the indexed register.
bit 8-15 : data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
A multiple read command is also available in 3-wire mode.
DS12171 - Rev 3 page 29/116
7
Application hints
7.1
ISM330DLC electrical connections in Mode 1
Figure 17. ISM330DLC electrical connections in Mode 1
ISM330DLC
Application hints
DS12171 - Rev 3
1.
Leave pin electrically unconnected and soldered to PCB.
The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1, C2 = 100 nF ceramic) should be placed as near as possible to the supply pin of the device (common design practice).
The functionality of the device and the measured acceleration/angular rate data is selectable and accessible through the SPI/I²C interface.
The functions, the threshold and the timing of the two interrupt pins for each sensor can be completely programmed by the user through the SPI/I²C interface.
page 30/116
7.2
ISM330DLC
ISM330DLC electrical connections in Mode 2
ISM330DLC electrical connections in Mode 2
Figure 18. ISM330DLC electrical connections in Mode 2
DS12171 - Rev 3
1.
Leave pin electrically unconnected and soldered to PCB.
The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1, C2 = 100 nF ceramic) should be placed as near as possible to the supply pin of the device (common design practice).
The functionality of the device and the measured acceleration/angular rate data is selectable and accessible through the SPI/I²C interface.
The functions, the threshold and the timing of the two interrupt pins for each sensor can be completely programmed by the user through the SPI/I²C interface.
page 31/116
7.3
ISM330DLC
ISM330DLC electrical connections in Mode 3 and Mode 4
ISM330DLC electrical connections in Mode 3 and Mode 4
Figure 19. ISM330DLC electrical connections in Mode 3 and Mode 4 (auxiliary 3-wire SPI)
SDO
SDI_Aux
SPC_Aux
INT1
1
4
14 12
5
TOP
VIEW
7
11
8
NC
(1)
OCS_Aux
INT2
VDD
Vdd
C1
100 nF
GND
C2
100 nF
Vdd_IO
GND
NOTE:
To avoid leakage current, it is recommended to add pull-up resistors on the SPI lines unless the SPI master can be left on also while the OIS system is off.
Mode 3
HOST
I 2 C/SPI (3/4-w)
ISM330DLC
Aux SPI (3-w) For gyro data only
AUX HOST
I 2 C configuration
Vdd_IO
R pu
SCL
SDA
Pull-up to be added
R pu
=10kOhm
R pu
Mode 4
HOST
I 2 C/SPI (3/4-w)
ISM330DLC
Aux SPI (3-w) For XL and gyro data
AUX HOST
1.
Leave pin electrically unconnected and soldered to PCB.
The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1, C2 = 100 nF ceramic) should be placed as near as possible to the supply pin of the device (common design practice).
The functionality of the device and the measured acceleration/angular rate data is selectable and accessible through the SPI/I²C interface.
The functions, the threshold and the timing of the two interrupt pins for each sensor can be completely programmed by the user through the SPI/I²C interface.
DS12171 - Rev 3 page 32/116
DS12171 - Rev 3
ISM330DLC
ISM330DLC electrical connections in Mode 3 and Mode 4
Figure 20. ISM330DLC electrical connections in Mode 3 and Mode 4 (auxiliary 4-wire SPI)
SDO
SDI_Aux
SPC_Aux
INT1
1
4
14 12
5
TOP
VIEW
7
11
8
SDO_Aux
OCS_Aux
INT2
VDD
Vdd
GND
C1
100 nF
Mode 3
HOST
I 2 C/SPI (3/4-w)
ISM330DLC
Aux SPI (4-w) For gyro data only
AUX HOST
C2
100 nF
Vdd_IO
GND
NOTE:
To avoid leakage current, it is recommended to add pull-up resistors on the SPI lines unless the SPI master can be left on also while the OIS system is off.
I 2 C configuration
Vdd_IO
R pu
SCL
SDA
Pull-up to be added
R pu
=10kOhm
R pu
Mode 4
HOST
I 2 C/SPI (3/4-w)
ISM330DLC
Aux SPI (4-w) For XL and gyro data
AUX HOST
The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1, C2 = 100 nF ceramic) should be placed as near as possible to the supply pin of the device (common design practice).
The functionality of the device and the measured acceleration/angular rate data is selectable and accessible through the SPI/I²C interface.
The functions, the threshold and the timing of the two interrupt pins for each sensor can be completely programmed by the user through the SPI/I²C interface.
Internal pull-up value is from 30 kΩ to 50 kΩ, depending on VDDIO.
page 33/116
4
5
6
7
8 pin#
1
2
3
9
10
11
Name
SDO
SA0
SDx
SCx
INT1
Vdd_IO
GND
GND
Vdd
INT2
OCS
SDO
_Aux
Table 18. Internal pin status
Mode 1 function Mode 2 function
Mode 3 / Mode 4 function
Pin status Mode 1 Pin status Mode 2 Pin status Mode 3/4
SPI 4-wire interface serial data output (SDO)
I²C least significant bit of the device address (SA0)
Connect to VDDIO or
GND
Connect to VDDIO or
GND
SPI 4-wire interface serial data output (SDO)
I²C least significant bit of the device address (SA0)
I²C serial data master
(MSDA)
I²C serial clock master
(MSCL)
SPI 4-wire interface serial data output (SDO)
I²C least significant bit of the device address (SA0)
Auxiliary SPI 3/4-wire interface serial data input
(SDI) and SPI 3-wire serial data output (SDO)
Auxiliary SPI 3/4-wire interface serial port clock
(SPC_Aux)
Programmable interrupt 1 Programmable interrupt 1 Programmable interrupt 1
Default: Input without pullup.
Default: Input without pullup.
Pull-up is enabled if bit
SIM = 1 (SPI 3-wire) in reg 12h.
Pull-up is enabled if bit
SIM = 1 (SPI 3-wire) in reg 12h.
Default: Input without pullup.
Pull-up is enabled if bit
SIM = 1 (SPI 3-wire) in reg 12h.
Default: input without pullup.
Pull-up is enabled if bit
PULL_UP_EN = 1 in reg
1Ah.
Default: input without pullup.
Pull-up is enabled if bit
PULL_UP_EN = 1 in reg
1Ah.
Default: Output forced to ground
Default: input without pullup.
Pull-up is enabled if bit
PULL_UP_EN = 1 in reg
1Ah.
Default: input without pullup.
Pull-up is enabled if bit
PULL_UP_EN = 1 in reg
1Ah.
Default: Output forced to ground
Default: input without pullup.
Pull-up is enabled if bit
PULL_UP_EN = 1 in reg
1Ah.
Default: input without pullup.
Pull-up is enabled if bit
PULL_UP_EN = 1 in reg
1Ah.
Default: Output forced to ground
Power supply for I/O pins
0 V supply
0 V supply
Power supply
Programmable interrupt 2
(INT2) / Data enabled
(DEN)
Power supply for I/O pins
0 V supply
0 V supply
Power supply
Programmable interrupt 2
(INT2) / Data enabled
(DEN) / I²C master external synchronization signal (MDRDY)
Power supply for I/O pins
0 V supply
0 V supply
Power supply
Programmable interrupt 2
(INT2) / Data enabled
(DEN)
Default: Output forced to ground
Default: Output forced to ground
Default: Output forced to ground
Leave unconnected Leave unconnected
Auxiliary SPI 3/4-wire interface enabled
Default: Input with pull-up.
Default: Input with pull-up.
(See note below to disable pull-up)
(See note below to disable pull-up)
Input without pull-up
Connect to VDDIO or leave unconnected
Connect to VDDIO or leave unconnected
Auxiliary SPI 3-wire interface: leave unconnected / Auxiliary
SPI 4-wire interface: serial data output
(SDO_Aux)
Default: Input with pull-up.
(See note below to disable pull-up)
Default: Input with pull-up.
(See note below to disable pull-up)
Default: Input without pullup.
Pull-up is enabled if bit
SIM_OIS = 1 (Aux_SPI 3wire) in reg 70h.
pin#
12
13
14
Note:
Name
CS
SCL
SDA
Mode 1 function
I²C/SPI mode selection
(1:SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled)
I²C serial clock (SCL) /
SPI serial port clock
(SPC)
I²C serial data (SDA) /
SPI serial data input
(SDI) / 3-wire interface serial data output (SDO)
Mode 2 function
I²C/SPI mode selection
(1:SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled)
I²C serial clock (SCL) /
SPI serial port clock
(SPC)
I²C serial data (SDA) /
SPI serial data input
(SDI) / 3-wire interface serial data output (SDO)
Mode 3 / Mode 4 function
I²C/SPI mode selection
(1:SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled)
I²C serial clock (SCL) /
SPI serial port clock
(SPC)
I²C serial data (SDA) /
SPI serial data input
(SDI) / 3-wire interface serial data output (SDO)
Pin status Mode 1
Input without pull-up
Input without pull-up
Pin status Mode 2 Pin status Mode 3/4
Default: Input with pull-up.
Pull-up is disabled if bit
I2C_disable = 1 in reg
13h.
Default: Input with pull-up.
Pull-up is disabled if bit
I2C_disable = 1 in reg
13h.
Default: Input with pull-up.
Pull-up is disabled if bit
I2C_disable = 1 in reg
13h.
Input without pull-up
Input without pull-up
Input without pull-up
Input without pull-up
Internal pull-up value is from 30 kΩ to 50 kΩ, depending on VDDIO.
The procedure to disable the pull-up on pins 10-11 is as follows:
1. AP side: write 80h in register at address 00h
2. AP side: write 01h in register at address 05h (disable the pull-up on pins 10 and 11 of ISM330DLC)
3. AP side: write 00h in register at address 00h
8
8.1
ISM330DLC
Auxiliary SPI configurations
Auxiliary SPI configurations
When the ISM330DLC is configured in Mode 3 and Mode 4, the auxiliary SPI can be connected to an auxiliary host (OIS). In this interface, the SPI can write only to the dedicated registers
,
,
CTRL2_OIS (71h) , CTRL3_OIS (72h) .
Gyroscope filtering
The gyroscope filtering chain is illustrated in the following figure.
Figure 21. Gyroscope chain
SPI/I
2
C
ADC
HPF
0
1
HP_EN_G
0
1
HP_EN_OIS
LPF2
ODR_G
FIFO
LPF1
_OIS
SPI_Aux
Note: HP_EN_OIS is active to select HPF on the auxiliary SPI chain only if HPF is not already used in the primary interface.
The auxiliary interface needs to be enabled in
) and ODR at 6.66 kHz.
LPF1 configuration depends on the setting of the FTYPE_[1;0] _OIS bit in register CTRL2_OIS (71h)
.
DS12171 - Rev 3 page 36/116
ISM330DLC
Accelerometer filtering
8.2
8.2.1
8.2.2
Accelerometer filtering
Accelerometer filtering is available only when Mode 4 is enabled.
Figure 22. Accelerometer chain (available only in Mode 4)
Free-fall
6D/4D
Smart functions
ADC LPF1
ODR/2
ODR/4
0
1
LPF1_BW_SEL
SLOPE
FILTER
0
1
HP_SLOPE_XL_EN
FIFO
Wake-up
Activity /
Inactivity
S/D Tap
LPF_OIS
FILTER_XL_CONF_OIS[1:0]
SPI_Aux
Accelerometer output values are in registers
through
and ODR at
6.66 kHz.
Accelerometer full scale set from primary interface
If the SPI/I²C primary interface is used, the full-scale setting has been configured by the primary interface and
CTRL3_OIS (72h) must be set to the same full-scale setting of the primary interface.
Accelerometer full scale set from auxiliary SPI
If the configuration uses only the auxiliary SPI, the full scale can be set using the FS[1:0]_XL_OIS bits in
CTRL3_OIS (72h) . The configuration of the low-pass filter depends on the setting of the
FILTER_XL_CONF_OIS[1:0] bits in register
.
DS12171 - Rev 3 page 37/116
9
ISM330DLC
Register mapping
Register mapping
The table given below provides a list of the 8/16-bit registers embedded in the device and the corresponding addresses.
Name
RESERVED
FUNC_CFG_ACCESS
RESERVED
RESERVED
SENSOR_SYNC_TIME_
FRAME
SENSOR_SYNC_RES_
RATIO
FIFO_CTRL1
FIFO_CTRL2
FIFO_CTRL3
FIFO_CTRL4
FIFO_CTRL5
DRDY_PULSE_CFG
RESERVED
INT1_CTRL
INT2_CTRL
WHO_AM_I
CTRL1_XL
CTRL2_G
CTRL3_C
CTRL4_C
CTRL5_C
CTRL6_C
CTRL7_G
CTRL8_XL
CTRL9_XL
CTRL10_C
MASTER_CONFIG
WAKE_UP_SRC
TAP_SRC
D6D_SRC
00000110 00000000
00000111 00000000
00001000 00000000
00001001 00000000
00001010 00000000
00001011 00000000
00001100 -
00001101 00000000
00001110 00000000
00001111 01101010
00010000 00000000
00010001 00000000
00010010 00000100
00010011 00000000
00010100 00000000
00010101 00000000
00010110 00000000
0001 0111 00000000
00011000 11100000
00011001 00000000
00011010 00000000
00011011 output
00011100
00011101 output output
1A
1B
1C
1D
17
18
19
12
13
14
15
16
0D
0E
0F
10
11
06
07
08
09
0A
0B
0C r r r/w r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w
-
-
-
r/w
Type
Table 19. Registers address map
Register address
Hex Binary
00
01
02
03
00000000
Default
-
-
-
00000001 00000000
00000010
00000011
Comment
Reserved
Embedded functions configuration register
Reserved
Reserved r/w r/w
04
05
00000100 00000000
00000101 00000000
Sensor sync configuration register
FIFO configuration registers
Reserved
INT1 pin control
INT2 pin control
Who I am ID
Accelerometer and gyroscope control registers
I²C master configuration register
Interrupt registers
DS12171 - Rev 3 page 38/116
DS12171 - Rev 3
ISM330DLC
Register mapping
Name
SENSORHUB3_REG
SENSORHUB4_REG
SENSORHUB5_REG
SENSORHUB6_REG
SENSORHUB7_REG
SENSORHUB8_REG
SENSORHUB9_REG
SENSORHUB10_REG
SENSORHUB11_REG
SENSORHUB12_REG
FIFO_STATUS1
FIFO_STATUS2
FIFO_STATUS3
FIFO_STATUS4
FIFO_DATA_OUT_L
FIFO_DATA_OUT_H
TIMESTAMP0_REG
TIMESTAMP1_REG
TIMESTAMP2_REG
RESERVED
STATUS_SPIAux
RESERVED
OUT_TEMP_L
OUT_TEMP_H
OUTX_L_G
OUTX_H_G
OUTY_L_G
OUTY_H_G
OUTZ_L_G
OUTZ_H_G
OUTX_L_XL
OUTX_H_XL
OUTY_L_XL
OUTY_H_XL
OUTZ_L_XL
OUTZ_H_XL
SENSORHUB1_REG
SENSORHUB2_REG
Type
Register address
Hex Binary r 1E 00011110
3A
3B
3C
3D
3E
35
36
37
38
39
3F
40
41
42
43-4C
30
31
32
33
34
2B
2C
2D
2E
2F
26
27
28
29
2A
1F
20
21
22
23
24
25
00101011
00101100
00101101
00101110
00101111
00110000
00110001
00110010
00110011
00110100
00011111
00100000
00100001
00100010
00100011
00100100
00100101
00100110
00100111
00101000
00101001
00101010
00110101
00110110
00110111
00111000
00111001
00111010
00111011
00111100
00111101
00111110
00111111
01000000
01000001
01000010 r r r r r r r r r r r r r r/w
r r r r r r r r r r r r r r r r r r r
r r
Default output output output output output output output output output output output output output output output
output output output output output output output output output output
output output output output output output output output output output output
Comment
Status data register for GP and OIS data
Reserved
Temperature output data registers
Gyroscope output registers for GP and OIS data
Accelerometer output registers
Sensor hub output registers
FIFO status registers
FIFO data output registers
Timestamp output registers
Reserved page 39/116
DS12171 - Rev 3
ISM330DLC
Register mapping
Name
SENSORHUB13_REG
SENSORHUB14_REG
SENSORHUB15_REG
SENSORHUB16_REG
SENSORHUB17_REG
SENSORHUB18_REG
FUNC_SRC1
FUNC_SRC2
RESERVED
TAP_CFG
TAP_THS_6D
INT_DUR2
WAKE_UP_THS
WAKE_UP_DUR
FREE_FALL
MD1_CFG
MD2_CFG
MASTER_CMD_CODE
SENS_SYNC_SPI_
ERROR_CODE
RESERVED
OUT_MAG_RAW_X_L
OUT_MAG_RAW_X_H
OUT_MAG_RAW_Y_L
OUT_MAG_RAW_Y_H
OUT_MAG_RAW_Z_L
OUT_MAG_RAW_Z_H
RESERVED
INT_OIS
CTRL1_OIS
CTRL2_OIS
CTRL3_OIS
X_OFS_USR
Y_OFS_USR
Z_OFS_USR
RESERVED
Type r r r
r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w
r r r/w r/w r r
r r r/w r/w
r/w r/w r/w
Register address
Hex Binary
51
52
53
54
55-57
4D
4E
4F
50
5B
5C
5D
5E
5F
60
58
59
5A
61
62-65
66
67
68
69
6A
6B
6C-6E
6F
70
71
72
73
74
75
76-7F
01001101
01001110
01001111
01010000
01010001
01010010
01010011
01010100
01011000
0110 0001
01100110
01100111
01101000
01101001
01101010
01101011
Default output output output output output output output output
-
00000000
01011001 00000000
01011010 00000000
01011011 00000000
01011100 00000000
01011101 00000000
01011110 00000000
01011111 00000000
01100000 00000000
00000000
output output output output output output
-
01101111 00000000
01110000 00000000
01110001 00000000
01110010 00000000
01110011 00000000
01110100 00000000
01110101 00000000
-
Comment
Sensor hub output registers
Interrupt registers
Reserved
Interrupt registers
Reserved
External magnetometer raw data output registers
Reserved
Control registers for OIS connection
Accelerometer user offset correction
1. This register status is read using the auxiliary SPI for OIS data.
2. This register status is read using the primary interface for general-purpose interface data.
Reserved page 40/116
ISM330DLC
Register description
10
10.1
10.2
10.3
Register description
The device contains a set of registers which are used to control its behavior and to retrieve linear acceleration, angular rate and temperature data. The register addresses, made up of 7 bits, are used to identify them and to write the data through the serial interface.
FUNC_CFG_ACCESS (01h)
Enable embedded functions register (r/w).
Table 20. FUNC_CFG_ACCESS register
FUNC_CFG_EN 0
0
1. This bit must be set to ‘0’ for the correct operation of the device.
Table 21. FUNC_CFG_ACCESS register description
FUNC_CFG_EN
Enable access to the embedded functions configuration registers. Default value: 0
0: register access disabled
1: register access enabled
1. The embedded functions configuration registers details are available in
Section 11 Embedded functions register mapping
,
and Section 12 Embedded functions registers description .
SENSOR_SYNC_TIME_FRAME (04h)
Sensor synchronization time frame register (r/w).
Table 22. SENSOR_SYNC_TIME_FRAME register
0
0
0
0
1. This bit must be set to ‘0’ for the correct operation of the device.
TPH_3 TPH_2 TPH_1 TPH_0
TPH_ [3:0]
Table 23. SENSOR_SYNC_TIME_FRAME register description
Sensor synchronization time frame with the step of 500 ms and full range of 5 s. Unsigned 8-bit.
Default value: 0000 0000 (sensor sync disabled)
SENSOR_SYNC_RES_RATIO (05h)
Sensor synchronization resolution ratio (r/w)
Table 24. SENSOR_SYNC_RES_RATIO register
0
0
0
0
1. This bit must be set to ‘0’ for the correct operation of the device.
0
0
RR_1 RR_0
DS12171 - Rev 3 page 41/116
ISM330DLC
FIFO_CTRL1 (06h)
10.4
10.5
RR_[1:0]
Table 25. SENSOR_SYNC_RES_RATIO register description
Resolution ratio of error code for sensor synchronization.
(00: SensorSync, Res_Ratio = 2 11
01: SensorSync, Res_Ratio = 2 12
10: SensorSync, Res_Ratio = 2 13
11: SensorSync, Res_Ratio = 2 14 )
FIFO_CTRL1 (06h)
FIFO control register (r/w).
FTH_7 FTH_6 FTH_5
Table 26. FIFO_CTRL1 register
FTH_4 FTH_3 FTH_2 FTH_1 FTH_0
Table 27. FIFO_CTRL1 register description
FTH_[7:0]
FIFO threshold level setting. Default value: 0000 0000 (1)
Watermark flag rises when the number of bytes written to FIFO after the next write is greater than or equal to the threshold level.
Minimum resolution for the FIFO is 1 LSB = 2 bytes (1 word) in FIFO
1. For a complete watermark threshold configuration, consider FTH_[10:8] in
FIFO_CTRL2 (07h)
FIFO control register (r/w).
Table 28. FIFO_CTRL2 register
FIFO_
TIMER_EN
0
0
0
1. This bit must be set to ‘0’ for the correct operation of the device.
FIFO_
TEMP_EN
FTH10 FTH_9 FTH_8
Table 29. FIFO_CTRL2 register description
Enables timestamp data to be stored as the 4 th FIFO data set.
FIFO_TIMER_EN
(0: timestamp not included in FIFO; 1: timestamp included in FIFO)
FIFO_TEMP_EN
Enables the temperature data storage in FIFO. Default: 0
(0: temperature not included in FIFO; 1: temperature included in FIFO)
FTH_[10:8]
FIFO threshold level setting. Default value: 0000 (1)
Watermark flag rises when the number of bytes written to FIFO after the next write is greater than or equal to the threshold level.
Minimum resolution for the FIFO is 1LSB = 2 bytes (1 word) in FIFO
1. For a complete watermark threshold configuration, consider FTH_[7:0] in
DS12171 - Rev 3 page 42/116
ISM330DLC
FIFO_CTRL3 (08h)
10.6
FIFO_CTRL3 (08h)
FIFO control register (r/w).
Table 30. FIFO_CTRL3 register
0
0
DEC_FIFO_
GYRO2
DEC_FIFO_
GYRO1
1. This bit must be set to ‘0’ for the correct operation of the device.
DEC_FIFO_
GYRO0
DEC_FIFO_
XL2
DEC_FIFO_
XL1
DEC_FIFO_
XL0
DEC_FIFO_GYRO [2:0]
DEC_FIFO_XL [2:0]
Table 31. FIFO_CTRL3 register description
Gyro FIFO (first data set) decimation setting. Default: 000
For the configuration setting, refer to Table 32 .
Accelerometer FIFO (second data set) decimation setting. Default: 000
For the configuration setting, refer to Table 33 .
Table 32. Gyro FIFO decimation setting
DEC_FIFO_GYRO [2:0]
000
001
010
011
100
101
110
111
Gyro sensor not in FIFO
Configuration
No decimation
Decimation with factor 2
Decimation with factor 3
Decimation with factor 4
Decimation with factor 8
Decimation with factor 16
Decimation with factor 32
DEC_FIFO_XL [2:0]
000
001
010
011
100
101
110
111
Table 33. Accelerometer FIFO decimation setting
Configuration
Accelerometer sensor not in FIFO
No decimation
Decimation with factor 2
Decimation with factor 3
Decimation with factor 4
Decimation with factor 8
Decimation with factor 16
Decimation with factor 32
DS12171 - Rev 3 page 43/116
ISM330DLC
FIFO_CTRL4 (09h)
10.7
FIFO_CTRL4 (09h)
FIFO control register (r/w).
STOP_ON_
FTH
ONLY_HIGH_
DATA
DEC_DS4_
FIFO2
Table 34. FIFO_CTRL4 register
DEC_DS4_
FIFO1
DEC_DS4_
FIFO0
DEC_DS3_
FIFO2
DEC_DS3_
FIFO1
DEC_DS3_
FIFO0
Table 35. FIFO_CTRL4 register description
STOP_ON_FTH
ONLY_HIGH_DATA
Enable FIFO threshold level use. Default value: 0.
(0: FIFO depth is not limited; 1: FIFO depth is limited to threshold level)
8-bit data storage in FIFO. Default: 0
(0: disable MSByte only memorization in FIFO for XL and Gyro;
1: enable MSByte only memorization in FIFO for XL and Gyro in FIFO)
.
Table 36. Fourth FIFO data set decimation setting
DEC_DS4_FIFO[2:0]
000
001
010
011
100
101
110
111
Configuration
Fourth FIFO data set not in FIFO
No decimation
Decimation with factor 2
Decimation with factor 3
Decimation with factor 4
Decimation with factor 8
Decimation with factor 16
Decimation with factor 32
Table 37. Third FIFO data set decimation setting
DEC_DS3_FIFO[2:0]
000
001
010
011
100
101
110
111
Configuration
Third FIFO data set not in FIFO
No decimation
Decimation with factor 2
Decimation with factor 3
Decimation with factor 4
Decimation with factor 8
Decimation with factor 16
Decimation with factor 32
DS12171 - Rev 3 page 44/116
ISM330DLC
FIFO_CTRL5 (0Ah)
10.8
FIFO_CTRL5 (0Ah)
FIFO control register (r/w).
Table 38. FIFO_CTRL5 register
0
ODR_FIFO_3 ODR_FIFO_2 ODR_FIFO_1 ODR_FIFO_0 FIFO_MODE_2 FIFO_MODE_1 FIFO_MODE_0
1. This bit must be set to ‘0’ for the correct operation of the device.
ODR_FIFO_[3:0]
FIFO_MODE_[2:0]
Table 39. FIFO_CTRL5 register description
FIFO ODR selection, setting FIFO_MODE also. Default: 0000
For the configuration setting, refer to Table 40 .
FIFO mode selection bits, setting ODR_FIFO also. Default value: 000
For the configuration setting, refer to Table 41 .
Table 40. FIFO ODR selection
ODR_FIFO_[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
FIFO disabled
FIFO ODR is set to 12.5 Hz
FIFO ODR is set to 26 Hz
FIFO ODR is set to 52 Hz
FIFO ODR is set to 104 Hz
FIFO ODR is set to 208 Hz
FIFO ODR is set to 416 Hz
FIFO ODR is set to 833 Hz
FIFO ODR is set to 1.66 kHz
FIFO ODR is set to 3.33 kHz
FIFO ODR is set to 6.66 kHz
Configuration
1. If the device is working at an ODR slower than the one selected, FIFO ODR is limited to that ODR value. Moreover, these bits are effective if the DATA_VALID_SEL FIFO bit of
MASTER_CONFIG (1Ah) is set to 0.
FIFO_MODE_[2:0]
000
001
010
011
100
101
110
111
Table 41. FIFO mode selection
Configuration mode
Bypass mode. FIFO disabled.
FIFO mode. Stops collecting data when FIFO is full.
Reserved
Continuous mode until trigger is deasserted, then FIFO mode.
Bypass mode until trigger is deasserted, then Continuous mode.
Reserved
Continuous mode. If the FIFO is full, the new sample overwrites the older one.
Reserved
DS12171 - Rev 3 page 45/116
ISM330DLC
DRDY_PULSE_CFG (0Bh)
10.9
10.10
DRDY_PULSE_CFG (0Bh)
Data-Ready configuration register (r/w).
Table 42. DRDY_PULSE_CFG register
DRDY_
PULSED
0
0
0
1. This bit must be set to ‘0’ for the correct operation of the device.
0
0
0
0
DRDY_PULSED
Table 43. DRDY_PULSE_CFG register description
Enable pulsed data-ready mode. Default value: 0
(0: data-ready latched mode. Returns to 0 only after output data has been read;
1: data-ready pulsed mode. The data-ready pulses are 75 µs long.)
INT1_CTRL (0Dh)
INT1 pad control register (r/w).
Each bit in this register enables a signal to be carried through INT1. The pad’s output will supply the OR combination of the selected signals.
0 0
INT1_
FULL_FLAG
Table 44. INT1_CTRL register
INT1_FIFO_OVR INT1_FTH INT1_ BOOT INT1_ DRDY_G INT1_DRDY_XL
INT1_FULL_FLAG
INT1_FIFO_OVR
INT1_FTH
INT1_ BOOT
INT1_DRDY_G
INT1_DRDY_XL
Table 45. INT1_CTRL register description
FIFO full flag interrupt enable on INT1 pad. Default value: 0
(0: disabled; 1: enabled)
FIFO overrun interrupt on INT1 pad. Default value: 0
(0: disabled; 1: enabled)
FIFO threshold interrupt on INT1 pad. Default value: 0
(0: disabled; 1: enabled)
Boot status available on INT1 pad. Default value: 0
(0: disabled; 1: enabled)
Gyroscope data-ready on INT1 pad. Default value: 0
(0: disabled; 1: enabled)
Accelerometer data-ready on INT1 pad. Default value: 0
(0: disabled; 1: enabled)
DS12171 - Rev 3 page 46/116
ISM330DLC
INT2_CTRL (0Eh)
10.11
INT2_CTRL (0Eh)
INT2 pad control register (r/w).
Each bit in this register enables a signal to be carried through INT2. The pad’s output will supply the OR combination of the selected signals.
0 0
INT2_
FULL_FLAG
Table 46. INT2_CTRL register
INT2_FIFO_OVR INT2_ FTH
INT2_
DRDY_TEMP
INT2_ DRDY_G INT2_DRDY_XL
10.12
INT2_ FULL_FLAG
INT2_FIFO_OVR
INT2_FTH
INT2_DRDY_TEMP
INT2_DRDY_G
INT2_DRDY_XL
Table 47. INT2_CTRL register description
FIFO full flag interrupt enable on INT2 pad. Default value: 0
(0: disabled; 1: enabled)
FIFO overrun interrupt on INT2 pad. Default value: 0
(0: disabled; 1: enabled)
FIFO threshold interrupt on INT2 pad. Default value: 0
(0: disabled; 1: enabled)
Temperature data-ready on INT2 pad. Default value: 0
(0: disabled; 1: enabled)
Gyroscope data-ready on INT2 pad. Default value: 0
(0: disabled; 1: enabled)
Accelerometer data-ready on INT2 pad. Default value: 0
(0: disabled; 1: enabled)
WHO_AM_I (0Fh)
Who_AM_I register (r). This register is a read-only register. Its value is fixed at 6Ah.
0 1 1
Table 48. WHO_AM_I register
0 1 0 1 0
DS12171 - Rev 3 page 47/116
ISM330DLC
CTRL1_XL (10h)
10.13
CTRL1_XL (10h)
Linear acceleration sensor control register 1 (r/w).
ODR_XL3 ODR_XL2 ODR_XL1
Table 49. CTRL1_XL register
ODR_XL0 FS_XL1 FS_XL0 LPF1_BW_SEL BW0_XL
Table 50. CTRL1_XL register description
ODR_XL [3:0] Output data rate and power mode selection. Default value: 0000 (see
).
FS_XL [1:0]
Accelerometer full-scale selection. Default value: 00
(00: ±2 g ; 01: ±16 g ; 10: ±4 g ; 11: ±8 g )
LPF1_BW_SEL Accelerometer digital LPF (LPF1) bandwidth selection. For bandwidth selection refer to
BW0_XL
Accelerometer analog chain bandwidth selection (only for accelerometer ODR ≥ 1.67 kHz).
(0: BW @ 1.5 kHz;
1: BW @ 400 Hz)
Table 51. Accelerometer ODR register setting
ODR_XL3 ODR_XL2 ODR_XL1 ODR_XL0
0
0
0
0
1
1
1
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
0
1
1
0
0
1
1
0
0
1 x
0
1
1
0
1
0
1
0
1
0
1
0 x
ODR selection [Hz] when
XL_HM_MODE = 1
Power-down
1.6 Hz (low power only)
12.5 Hz (low power)
26 Hz (low power)
52 Hz (low power)
104 Hz (normal mode)
208 Hz (normal mode)
416 Hz (high performance)
833 Hz (high performance)
1.66 kHz (high performance)
3.33 kHz (high performance)
6.66 kHz (high performance)
Not allowed
ODR selection [Hz] when
XL_HM_MODE = 0
Power-down
12.5 Hz (high performance)
12.5 Hz (high performance)
26 Hz (high performance)
52 Hz (high performance)
104 Hz (high performance)
208 Hz (high performance)
416 Hz (high performance)
833 Hz (high performance)
1.66 kHz (high performance)
3.33 kHz (high performance)
6.66 kHz (high performance)
Not allowed
DS12171 - Rev 3 page 48/116
ISM330DLC
CTRL2_G (11h)
10.14
CTRL2_G (11h)
Angular rate sensor control register 2 (r/w).
Table 52. CTRL2_G register
ODR_G3 ODR_G2 ODR_G1 ODR_G0
1. This bit must be set to ‘0’ for the correct operation of the device.
FS_G1 FS_G0
ODR_G [3:0]
FS_G [1:0]
FS_125
Table 53. CTRL2_G register description
Gyroscope output data rate selection. Default value: 0000
(Refer to
Gyroscope full-scale selection. Default value: 00
(00: ±250 dps; 01: ±500 dps; 10: ±1000 dps; 11: ±2000 dps)
Gyroscope full-scale at ±125 dps. Default value: 0
(0: disabled; 1: enabled)
FS_125
ODR_G3
0
1
1
1
1
0
0
0
0
0
0
0
ODR_G2
1
0
0
0
0
0
0
1
0
0
1
1
1
0
0
1
1
1
1
0
0
0
0
1
ODR_G1
1
0
1
0
1
0
1
0
0
1
1
0
Table 54. Gyroscope ODR configuration setting
ODR_G0
ODR [Hz] when
G_HM_MODE = 1
Power down
12.5 Hz (low power)
26 Hz (low power)
52 Hz (low power)
104 Hz (normal mode)
208 Hz (normal mode)
416 Hz (high performance)
833 Hz (high performance)
1.66 kHz (high performance)
3.33 kHz (high performance
6.66 kHz (high performance
Not available
ODR [Hz] when
G_HM_MODE = 0
Power down
12.5 Hz (high performance)
26 Hz (high performance)
52 Hz (high performance)
104 Hz (high performance)
208 Hz (high performance)
416 Hz (high performance)
833 Hz (high performance)
1.66 kHz (high performance)
3.33 kHz (high performance)
6.66 kHz (high performance)
Not available
0
DS12171 - Rev 3 page 49/116
ISM330DLC
CTRL3_C (12h)
10.15
CTRL3_C (12h)
Control register 3 (r/w).
BOOT BDU H_LACTIVE
Table 55. CTRL3_C register
PP_OD SIM IF_INC BLE SW_RESET
Table 56. CTRL3_C register description
BOOT
BDU
Reboots memory content. Default value: 0
(0: normal mode; 1: reboot memory content)
Block Data Update. Default value: 0
(0: continuous update;
1: output registers not updated until MSB and LSB have been read)
H_LACTIVE
Interrupt activation level. Default value: 0
(0: interrupt output pads active high; 1: interrupt output pads active low)
PP_OD
SIM
Push-pull/open-drain selection on INT1 and INT2 pads. Default value: 0
(0: push-pull mode; 1: open-drain mode)
SPI Serial Interface Mode selection. Default value: 0
(0: 4-wire interface; 1: 3-wire interface)
IF_INC
Register address automatically incremented during a multiple byte access with a serial interface (I²C or SPI).
Default value: 1
(0: disabled; 1: enabled)
BLE
Big/Little Endian Data selection. Default value 0
(0: data LSB @ lower address; 1: data MSB @ lower address)
SW_RESET
Software reset. Default value: 0
(0: normal mode; 1: reset device)
This bit is automatically cleared.
DS12171 - Rev 3 page 50/116
ISM330DLC
CTRL4_C (13h)
10.16
10.17
CTRL4_C (13h)
Control register 4 (r/w).
Table 57. CTRL4_C register
DEN_XL_EN SLEEP INT2_on_INT1
DEN_DRDY
_INT1
DRDY_MASK
1. This bit must be set to '0' for the correct operation of the device.
I2C_disable LPF1_SEL_G 0
Table 58. CTRL4_C register description
DEN_XL_EN
SLEEP
INT2_on_INT1
Extend DEN functionality to accelerometer sensor. Default value: 0
(0: disabled; 1: enabled)
Gyroscope sleep mode enable. Default value: 0
(0: disabled; 1: enabled)
All interrupt signals available on INT1 pad enable. Default value: 0
(0: interrupt signals divided between INT1 and INT2 pads;
1: all interrupt signals in logic or on INT1 pad)
DEN_DRDY_INT1
DEN DRDY signal on INT1 pad. Default value: 0
(0: disabled; 1: enabled)
DRDY_MASK
Configuration 1 data available enable bit. Default value: 0
(0: DA timer disabled; 1: DA timer enabled)
I2C_disable
LPF1_SEL_G
Disable I²C interface. Default value: 0
(0: both I²C and SPI enabled; 1: I²C disabled, SPI only)
Enable gyroscope digital LPF1 if auxiliary SPI is disabled; the bandwidth can be selected through FTYPE
[1:0] in
(0: disabled; 1: enabled)
CTRL5_C (14h)
Control register 5 (r/w).
ROUNDING2 ROUNDING1 ROUNDING0
Table 59. CTRL5_C register
DEN_LH ST1_G ST0_G ST1_XL ST0_XL
Table 60. CTRL5_C register description
ROUNDING[2:0]
Circular burst-mode (rounding) read from output registers through the primary interface. Default value: 000
(000: no rounding; others: refer to
)
DEN_LH
ST_G [1:0]
ST_XL [1:0]
DEN active level configuration. Default value: 0
(0: active low; 1: active high)
Angular rate sensor self-test enable. Default value: 00
(00: self-test disabled; others: refer to
)
Linear acceleration sensor self-test enable. Default value: 00
(00: self-test disabled; others: refer to
)
DS12171 - Rev 3 page 51/116
DS12171 - Rev 3
ISM330DLC
CTRL5_C (14h)
Table 61. Output registers rounding pattern
ROUNDING[2:0]
000 No rounding
001
010
011
100
101
110
111
Accelerometer only
Gyroscope only
Gyroscope + accelerometer
Registers from
Accelerometer + registers from
Rounding pattern
only
Gyroscope + accelerometer + registers from
and registers from
Gyroscope + accelerometer + registers from
ST1_G
0
0
1
1
Table 62. Angular rate sensor self-test mode selection
ST0_G
0
1
0
1
Normal mode
Positive sign self-test
Not allowed
Negative sign self-test
Self-test mode
ST1_XL
0
0
1
1
Table 63. Linear acceleration sensor self-test mode selection
ST0_XL
0
1
0
1
Normal mode
Positive sign self-test
Negative sign self-test
Not allowed
Self-test mode page 52/116
ISM330DLC
CTRL6_C (15h)
10.18
CTRL6_C (15h)
Angular rate sensor control register 6 (r/w).
Table 64. CTRL6_C register
TRIG_EN LVL1_EN LVL2_EN XL_HM_MODE USR_OFF_W
1. This bit must be set to ‘0’ for the correct operation of the device.
0
FTYPE_1
Table 65. CTRL6_C register description
TRIG_EN
LVL1_EN
DEN data edge-sensitive trigger enable. Refer to
DEN data level-sensitive trigger enable. Refer to
.
.
LVL2_EN DEN level-sensitive latched enable. Refer to
.
XL_HM_MODE
High-performance operating mode disable for accelerometer. Default value: 0
(0: high-performance operating mode enabled;
1: high-performance operating mode disabled)
USR_OFF_W
FTYPE[1:0]
Weight of XL user offset bits of registers X_OFS_USR (73h) ,
,
(0: 2 -10 g /LSB;
1: 2 -6 g /LSB)
Gyroscope low-pass filter (LPF1) bandwidth selection.
Table 67 shows the selectable bandwidth values (available if auxiliary SPI is disabled).
FTYPE_0
TRIG_EN, LVL1_EN, LVL2_EN
100
010
011
110
Table 66. Trigger mode selection
Trigger mode
Edge-sensitive trigger mode is selected
Level-sensitive trigger mode is selected
Level-sensitive latched mode is selected
Level-sensitive FIFO enable mode is selected
FTYPE[1:0]
00
01
10
11
BW
ODR = 800 Hz
Phase delay
245 Hz
195 Hz
155 Hz
293 Hz
1. Phase delay @ 20 Hz
14°
17°
19°
13°
Table 67. Gyroscope LPF1 bandwidth selection
BW
ODR = 1.6 kHz
Phase delay
315 Hz
224 Hz
10°
12°
168 Hz
505 Hz
15°
8°
BW
ODR = 3.3 kHz
Phase delay
343 Hz
234 Hz
8°
10°
172 Hz
925 Hz
12°
6°
BW
ODR = 6.6 kHz
351 Hz
237 Hz
7°
9°
173 Hz
937 Hz
11°
5°
DS12171 - Rev 3 page 53/116
ISM330DLC
CTRL7_G (16h)
10.19
CTRL7_G (16h)
Angular rate sensor control register 7 (r/w).
Table 68. CTRL7_G register
G_HM_MODE HP_EN_G HPM1_G HPM0_G
1. This bit must be set to ‘0’ for the correct operation of the device.
0
ROUNDING
_STATUS
0
0
Table 69. CTRL7_G register description
G_HM_MODE
HP_EN_G
High-performance operating mode disable for gyroscope. Default: 0
(0: high-performance operating mode enabled;
1: high-performance operating mode disabled)
Gyroscope digital high-pass filter enable. The filter is enabled only if the gyro is in HP mode. Default value: 0
(0: HPF disabled; 1: HPF enabled)
HPM_G[1:0]
Gyroscope digital HP filter cutoff selection. Default: 00
(00: 16 mHz;
01: 65 mHz;
10: 260 mHz;
11; 1.04 Hz)
Source register rounding function on WAKE_UP_SRC (1Bh)
,
STATUS_REG (1Eh), and FUNC_SRC1 (53h) registers in the primary interface.
ROUNDING_STATUS
Default value: 0
(0: rounding disabled; 1: rounding enabled)
DS12171 - Rev 3 page 54/116
ISM330DLC
CTRL8_XL (17h)
10.20
CTRL8_XL (17h)
Linear acceleration sensor control register 8 (r/w).
Table 70. CTRL8_XL register
LPF2_XL_EN HPCF_XL1 HPCF_XL0 HP_REF_MODE
INPUT_
COMPOSITE
1. This bit must be set to ‘0’ for the correct operation of the device.
HP_SLOPE_XL_
EN
LOW_PASS_ON
_6D
Table 71. CTRL8_XL register description
LPF2_XL_EN
HPCF_XL[1:0]
HP_REF_MODE
INPUT_COMPOSITE
HP_SLOPE_XL_EN
LOW_PASS_ON_6D
Accelerometer low-pass filter LPF2 selection. Refer to Figure 9
.
Accelerometer LPF2 and high-pass filter configuration and cutoff setting. Refer to
.
Enable HP filter reference mode. Default value: 0 (1)
(0: disabled; 1: enabled)
Composite filter input selection. Default: 0
(0: ODR/2 low pass filtered sent to composite filter (default)
1: ODR/4 low pass filtered sent to composite filter)
Accelerometer slope filter / high-pass filter selection. Refer to
LPF2 on 6D function selection. Refer to
1. When enabled, the first output data has to be discarded.
.
.
Table 72. Accelerometer bandwidth selection
HP_SLOPE_
XL_EN
0
(low-pass path)
1
(high-pass path)
LPF2_XL_EN
0
1
-
LPF1_BW_SEL
0
1
-
-
HPCF_XL[1:0]
11
00
01
10
11
-
-
00
01
10
INPUT_
COMPOSITE
-
-
1 (low noise)
0 (low latency)
0
Bandwidth
ODR/2
ODR/4
ODR/50
ODR/100
ODR/9
ODR/400
ODR/4
ODR/100
ODR/9
ODR/400
1. The bandwidth column is related to LPF1 if LPF2_XL_EN = 0 or to LPF2 if LPF2_XL_EN = 1.
2. The bandwidth column is related to the slope filter if HPCF_XL[1:0] = 00 or to the HP filter if HPCF_XL[1:0] = 01/10/11.
DS12171 - Rev 3 page 55/116
ISM330DLC
CTRL9_XL (18h)
10.21
10.22
CTRL9_XL (18h)
Linear acceleration sensor control register 9 (r/w).
Table 73. CTRL9_XL register
DEN_X DEN_Y DEN_Z DEN_XL_G
1. This bit must be set to ‘0’ for the correct operation of the device.
0
SOFT_EN 0
0
Table 74. CTRL9_XL register description
DEN_X
DEN_Y
DEN_Z
DEN_XL_G
SOFT_EN
DEN value stored in LSB of X-axis. Default value: 1
(0: DEN not stored in X-axis LSB; 1: DEN stored in X-axis LSB)
DEN value stored in LSB of Y-axis. Default value: 1
(0: DEN not stored in Y-axis LSB; 1: DEN stored in Y-axis LSB)
DEN value stored in LSB of Z-axis. Default value: 1
(0: DEN not stored in Z-axis LSB; 1: DEN stored in Z-axis LSB)
DEN stamping sensor selection. Default value: 0
(0: DEN pin info stamped in the gyroscope axis selected by bits [7:5];
1: DEN pin info stamped in the accelerometer axis selected by bits [7:5])
Enable soft-iron correction algorithm for magnetometer. Default value: 0 (1)
(0: soft-iron correction algorithm disabled;
1: soft-iron correction algorithm enabled)
1. This bit is effective if the IRON_EN bit of MASTER_CONFIG (1Ah) and FUNC_EN bit of
CTRL10_C (19h)
Control register 10 (r/w).
Table 75. CTRL10_C register
0
0
TIMER_EN 0
1. This bit must be set to ‘0’ for the correct operation of the device.
TILT_EN FUNC_EN 0
0
Table 76. CTRL10_C register description
TIMER_EN
Enable timestamp count. The count is saved in
TIMESTAMP0_REG (40h) , TIMESTAMP1_REG (41h)
and
. Default: 0
(0: timestamp count disabled; 1: timestamp count enabled)
TILT_EN Enable tilt calculation.
FUNC_EN
Enable embedded functionalities (tilt, sensor hub and ironing). Default value: 0
(0: disable functionalities of embedded functions and accelerometer filters;
1: enable functionalities of embedded functions and accelerometer filters)
1. This is effective if the FUNC_EN bit is set to '1'.
DS12171 - Rev 3 page 56/116
ISM330DLC
MASTER_CONFIG (1Ah)
10.23
MASTER_CONFIG (1Ah)
Master configuration register (r/w).
DRDY_ON_INT1
DATA_VALID
_SEL_FIFO
0
Table 77. MASTER_CONFIG register
START_CONFIG PULL_UP_EN
PASS_
THROUGH
_MODE
1. This bit must be set to ‘0’ for the correct operation of the device.
IRON_EN
Table 78. MASTER_CONFIG register description
DRDY_ON_INT1
DATA_VALID_SEL_FIFO
START_CONFIG
PULL_UP_EN
PASS_THROUGH_MODE
IRON_EN
MASTER_ON
Manage the master DRDY signal on INT1 pad. Default: 0
(0: disable master DRDY on INT1; 1: enable master DRDY on INT1)
Selection of FIFO data-valid signal. Default value: 0
(0: data-valid signal used to write data in FIFO is the XL/Gyro data-ready;
1: data-valid signal used to write data in FIFO is the sensor hub data-ready)
Sensor hub trigger signal selection. Default value: 0
(0: sensor hub signal is the XL/Gyro data-ready;
1: sensor hub signal external from INT2 pad.)
Auxiliary I²C pull-up. Default value: 0
(0: internal pull-up on auxiliary I²C line disabled;
1: internal pull-up on auxiliary I²C line enabled)
I²C interface pass-through. Default value: 0
(0: pass-through disabled; 1: pass-through enabled)
Enable hard-iron correction algorithm for magnetometer. Default value: 0
(0: hard-iron correction algorithm disabled;
1: hard-iron correction algorithm enabled)
Sensor hub I²C master enable (1)
. Default: 0
(0: master I²C of sensor hub disabled; 1: master I²C of sensor hub enabled)
1. This is effective if the FUNC_EN bit is set to '1'.
MASTER_ON
DS12171 - Rev 3 page 57/116
ISM330DLC
WAKE_UP_SRC (1Bh)
10.24
WAKE_UP_SRC (1Bh)
Wake-up interrupt source register (r).
0 0 FF_IA
Table 79. WAKE_UP_SRC register
SLEEP_
STATE_IA
WU_IA X_WU Y_WU
FF_IA
SLEEP_STATE_IA
WU_IA
X_WU
Y_WU
Z_WU
Table 80. WAKE_UP_SRC register description
Free-fall event detection status. Default: 0
(0: free-fall event not detected; 1: free-fall event detected)
Sleep event status. Default value: 0
(0: sleep event not detected; 1: sleep event detected)
Wakeup event detection status. Default value: 0
(0: wakeup event not detected; 1: wakeup event detected.)
Wakeup event detection status on X-axis. Default value: 0
(0: wakeup event on X-axis not detected; 1: wakeup event on X-axis detected)
Wakeup event detection status on Y-axis. Default value: 0
(0: wakeup event on Y-axis not detected; 1: wakeup event on Y-axis detected)
Wakeup event detection status on Z-axis. Default value: 0
(0: wakeup event on Z-axis not detected; 1: wakeup event on Z-axis detected)
Z_WU
DS12171 - Rev 3 page 58/116
ISM330DLC
TAP_SRC (1Ch)
10.25
TAP_SRC (1Ch)
Tap source register (r).
0 TAP_IA
Table 81. TAP_SRC register
SINGLE_TAP DOUBLE_TAP TAP_SIGN X_TAP
TAP_IA
SINGLE_TAP
DOUBLE_TAP
TAP_SIGN
X_TAP
Y_TAP
Z_TAP
Table 82. TAP_SRC register description
Tap event detection status. Default: 0
(0: tap event not detected; 1: tap event detected)
Single-tap event status. Default value: 0
(0: single tap event not detected; 1: single tap event detected)
Double-tap event detection status. Default value: 0
(0: double-tap event not detected; 1: double-tap event detected.)
Sign of acceleration detected by tap event. Default: 0
(0: positive sign of acceleration detected by tap event;
1: negative sign of acceleration detected by tap event)
Tap event detection status on X-axis. Default value: 0
(0: tap event on X-axis not detected; 1: tap event on X-axis detected)
Tap event detection status on Y-axis. Default value: 0
(0: tap event on Y-axis not detected; 1: tap event on Y-axis detected)
Tap event detection status on Z-axis. Default value: 0
(0: tap event on Z-axis not detected; 1: tap event on Z-axis detected)
Y_TAP Z_TAP
DS12171 - Rev 3 page 59/116
ISM330DLC
D6D_SRC (1Dh)
10.26
D6D_SRC (1Dh)
6D orientation source register (r)
DEN_DRDY D6D_IA ZH
Table 83. D6D_SRC register
ZL YH YL XH XL
10.27
Table 84. D6D_SRC register description
DEN_DRDY
DEN data-ready signal. It is set high when data output is related to the data coming from a DEN active
D6D_IA
ZH
Interrupt active for change position portrait, landscape, face-up, face-down. Default value: 0
(0: change position not detected; 1: change position detected)
Z-axis high event (over threshold). Default value: 0
(0: event not detected; 1: event (over threshold) detected)
ZL
YH
YL
XH
XL
Z-axis low event (under threshold). Default value: 0
(0: event not detected; 1: event (under threshold) detected)
Y-axis high event (over threshold). Default value: 0
(0: event not detected; 1: event (over-threshold) detected)
Y-axis low event (under threshold). Default value: 0
(0: event not detected; 1: event (under threshold) detected)
X-axis high event (over threshold). Default value: 0
(0: event not detected; 1: event (over threshold) detected)
X-axis low event (under threshold). Default value: 0
(0: event not detected; 1: event (under threshold) detected)
1. The DEN data-ready signal can be latched or pulsed depending on the value of the dataready_pulsed bit of the
DRDY_PULSE_CFG (0Bh) register.
STATUS_REG/STATUS_SPIAux (1Eh)
The STATUS_REG register is read by the primary interface SPI/I²C (r).
0 0 0
Table 85. STATUS_REG register
0 0 TDA GDA XLDA
TDA
GDA
XLDA
Table 86. STATUS_REG register description
Temperature new data available. Default: 0
(0: no set of data is available at temperature sensor output;
1: a new set of data is available at temperature sensor output)
Gyroscope new data available. Default value: 0
(0: no set of data available at gyroscope output;
1: a new set of data is available at gyroscope output)
Accelerometer new data available. Default value: 0
(0: no set of data available at accelerometer output;
1: a new set of data is available at accelerometer output)
DS12171 - Rev 3 page 60/116
ISM330DLC
OUT_TEMP_L (20h), OUT_TEMP_H (21h)
The STATUS_SPIAux register is read by the auxiliary SPI.
0 0 0
Table 87. STATUS_SPIAux register
0 0
GYRO_
SETTLING
GDA XLDA
10.28
GYRO_SETTLING
GDA
XLDA
Table 88. STATUS_SPIAux description
High when the gyroscope output is in the settling phase
Gyroscope data available (reset when one of the high parts of the output data is read)
Accelerometer data available (reset when one of the high parts of the output data is read)
OUT_TEMP_L (20h), OUT_TEMP_H (21h)
Temperature data output register (r). L and H registers together express a 16-bit word in two’s complement.
Temp7 Temp6 Temp5
Table 89. OUT_TEMP_L register
Temp4 Temp3 Temp2 Temp1 Temp0
Temp15 Temp14 Temp13
Table 90. OUT_TEMP_H register
Temp12 Temp11 Temp10 Temp9 Temp8
10.29
Temp[15:0]
Table 91. OUT_TEMP register description
Temperature sensor output data
The value is expressed as two’s complement sign extended on the MSB.
OUTX_L_G (22h)
Angular rate sensor pitch axis (X) angular rate output register (r). The value is expressed as a 16-bit word in two’s complement.
If this register is read by the primary interface, data are according to the full scale and ODR settings (
) of gyro general-purpose interface.
If this register is read by the auxiliary interface, data are according to the full scale and ODR (6.66 kHz) settings of the OIS gyro.
D7 D6 D5
Table 92. OUTX_L_G register
D4 D3 D2 D1 D0
D[7:0]
Table 93. OUTX_L_G register description
Pitch axis (X) angular rate value (LSbyte)
D[15:0] expressed in two’s complement and its value depends on the interface used:
SPI1/I²C: Gyro GP chain pitch axis output
SPI2: Gyro OIS chain pitch axis output
DS12171 - Rev 3 page 61/116
ISM330DLC
OUTX_H_G (23h)
10.30
OUTX_H_G (23h)
Angular rate sensor pitch axis (X) angular rate output register (r). The value is expressed as a 16-bit word in two’s complement.
If this register is read by the primary interface, data are according to the full scale and ODR settings (
) of the gyro general-purpose interface.
If this register is read by the auxiliary interface, data are according to the full scale and ODR (6.66 kHz) settings of the OIS gyro.
D15 D14 D13
Table 94. OUTX_H_G register
D12 D11 D10 D9 D8
10.31
D[15:8]
Table 95. OUTX_H_G register description
Pitch axis (X) angular rate value (MSbyte)
D[15:0] expressed in two’s complement and its value depends on the interface used:
SPI1/I²C: Gyro GP chain pitch axis output
SPI2: Gyro OIS chain pitch axis output
OUTY_L_G (24h)
Angular rate sensor roll axis (Y) angular rate output register (r). The value is expressed as a 16-bit word in two’s complement.
If this register is read by the primary interface, data are according to the full scale and ODR settings (
) of the gyro general-purpose interface.
If this register is read by the auxiliary interface, data are according to the full scale and ODR (6.66 kHz) settings of the OIS gyro.
D7 D6 D5
Table 96. OUTY_L_G register
D4 D3 D2 D1 D0
D[7:0]
Table 97. OUTY_L_G register description
Roll axis (Y) angular rate value (LSbyte)
D[15:0] expressed in two’s complement and its value depends on the interface used:
SPI1/I²C: Gyro GP chain roll axis output
SPI2: Gyro OIS chain roll axis output
DS12171 - Rev 3 page 62/116
ISM330DLC
OUTY_H_G (25h)
10.32
OUTY_H_G (25h)
Angular rate sensor roll axis (Y) angular rate output register (r). The value is expressed as a 16-bit word in two’s complement.
If this register is read by the primary interface, data are according to the full scale and ODR settings (
) of the gyro general-purpose interface.
If this register is read by the auxiliary interface, data are according to the full scale and ODR (6.66 kHz) settings of the OIS gyro.
D15 D14 D13
Table 98. OUTY_H_G register
D12 D11 D10 D9 D8
10.33
D[15:8]
Table 99. OUTY_H_G register description
Roll axis (Y) angular rate value (MSbyte)
D[15:0] expressed in two’s complement and its value depends on the interface used:
SPI1/I²C: Gyro GP chain roll axis output
SPI2: Gyro OIS chain roll axis output
OUTZ_L_G (26h)
Angular rate sensor yaw axis (Z) angular rate output register (r). The value is expressed as a 16-bit word in two’s complement.
If this register is read by the primary interface, data are according to the full scale and ODR settings (
) of the gyro general-purpose interface.
If this register is read by the auxiliary interface, data are according to the full scale and ODR (6.66 kHz) settings of the OIS gyro.
D7 D6 D5
Table 100. OUTZ_L_G register
D4 D3 D2 D1 D0
D[7:0]
Table 101. OUTZ_L_G register description
Yaw axis (Z) angular rate value (LSbyte)
D[15:0] expressed in two’s complement and its value depends on the interface used:
SPI1/I²C: Gyro GP chain yaw axis output
SPI2: Gyro OIS chain yaw axis output
DS12171 - Rev 3 page 63/116
ISM330DLC
OUTZ_H_G (27h)
10.34
OUTZ_H_G (27h)
Angular rate sensor Yaw axis (Z) angular rate output register (r). The value is expressed as a 16-bit word in two’s complement.
If this register is read by the primary interface, data are according to the full scale and ODR settings (
) of the gyro general-purpose interface.
If this register is read by the auxiliary interface, data are according to the full scale and ODR (6.66 kHz) settings of the OIS gyro.
D15 D14 D13
Table 102. OUTZ_H_G register
D12 D11 D10 D9 D8
10.35
D[15:8]
Table 103. OUTZ_H_G register description
Yaw axis (Z) angular rate value (MSbyte)
D[15:0] expressed in two’s complement and its value depends on the interface used:
SPI1/I²C: Gyro GP chain yaw axis output
SPI2: Gyro OIS chain yaw axis output
OUTX_L_XL (28h)
Linear acceleration sensor X-axis output register (r). The value is expressed as a 16-bit word in two’s complement.
Accelerometer data can be read also from AUX SPI @6.6 kHz.
D7 D6 D5
Table 104. OUTX_L_XL register
D4 D3 D2 D1 D0
10.36
D[7:0]
Table 105. OUTX_L_XL register description
X-axis linear acceleration value (LSbyte)
OUTX_H_XL (29h)
Linear acceleration sensor X-axis output register (r). The value is expressed as a 16-bit word in two’s complement.
Accelerometer data can be read also from AUX SPI @6.6 kHz.
D15 D14 D13
Table 106. OUTX_H_XL register
D12 D11 D10 D9 D8
D[15:8]
Table 107. OUTX_H_XL register description
X-axis linear acceleration value (MSbyte)
DS12171 - Rev 3 page 64/116
ISM330DLC
OUTY_L_XL (2Ah)
10.37
OUTY_L_XL (2Ah)
Linear acceleration sensor Y-axis output register (r). The value is expressed as a 16-bit word in two’s complement.
Accelerometer data can be read also from AUX SPI @6.6 kHz.
D7 D6 D5
Table 108. OUTY_L_XL register
D4 D3 D2 D1 D0
10.38
D[7:0]
Table 109. OUTY_L_XL register description
Y-axis linear acceleration value (LSbyte)
OUTY_H_XL (2Bh)
Linear acceleration sensor Y-axis output register (r). The value is expressed as a 16-bit word in two’s complement.
Accelerometer data can be read also from AUX SPI @6.6 kHz.
D15 D14 D13
Table 110. OUTY_H_XL register
D12 D11 D10 D9 D8
10.39
D[15:8]
Table 111. OUTY_H_XL register description
Y-axis linear acceleration value (MSbyte)
OUTZ_L_XL (2Ch)
Linear acceleration sensor Z-axis output register (r). The value is expressed as a 16-bit word in two’s complement.
Accelerometer data can be read also from AUX SPI @6.6 kHz.
D7 D6 D5
Table 112. OUTZ_L_XL register
D4 D3 D2 D1 D0
D[7:0]
Table 113. OUTZ_L_XL register description
Z-axis linear acceleration value (LSbyte)
DS12171 - Rev 3 page 65/116
ISM330DLC
OUTZ_H_XL (2Dh)
10.40
OUTZ_H_XL (2Dh)
Linear acceleration sensor Z-axis output register (r). The value is expressed as a 16-bit word in two’s complement.
Accelerometer data can be read also from AUX SPI @6.6 kHz.
D15 D14 D13
Table 114. OUTZ_H_XL register
D12 D11 D10 D9 D8
10.41
D[15:8]
Table 115. OUTZ_H_XL register description
Z-axis linear acceleration value (MSbyte)
SENSORHUB1_REG (2Eh)
First byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
SHub1_7 SHub1_6
Table 116. SENSORHUB1_REG register
SHub1_5 SHub1_4 SHub1_3 SHub1_2 SHub1_1 SHub1_0
10.42
SHub1_[7:0]
Table 117. SENSORHUB1_REG register description
First byte associated to external sensors
SENSORHUB2_REG (2Fh)
Second byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operations configurations (for external sensors from x = 0 to x = 3).
SHub2_7 SHub2_6
Table 118. SENSORHUB2_REG register
SHub2_5 SHub2_4 SHub2_3 SHub2_2 SHub2_1 SHub2_0
10.43
SHub2_[7:0]
Table 119. SENSORHUB2_REG register description
Second byte associated to external sensors
SENSORHUB3_REG (30h)
Third byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operations configurations (for external sensors from x = 0 to x = 3).
SHub3_7 SHub3_6
Table 120. SENSORHUB3_REG register
SHub3_5 SHub3_4 SHub3_3 SHub3_2 SHub3_1 SHub3_0
SHub3_[7:0]
Table 121. SENSORHUB3_REG register description
Third byte associated to external sensors
DS12171 - Rev 3 page 66/116
ISM330DLC
SENSORHUB4_REG (31h)
10.44
SENSORHUB4_REG (31h)
Fourth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
SHub4_7 SHub4_6
Table 122. SENSORHUB4_REG register
SHub4_5 SHub4_4 SHub4_3 SHub4_2 SHub4_1 SHub4_0
10.45
SHub4_[7:0]
Table 123. SENSORHUB4_REG register description
Fourth byte associated to external sensors
SENSORHUB5_REG (32h)
Fifth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
SHub5_7 SHub5_6
Table 124. SENSORHUB5_REG register
SHub5_5 SHub5_4 SHub5_3 SHub5_2 SHub5_1 SHub5_0
10.46
SHub5_[7:0]
Table 125. SENSORHUB5_REG register description
Fifth byte associated to external sensors
SENSORHUB6_REG (33h)
Sixth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
SHub6_7 SHub6_6
Table 126. SENSORHUB6_REG register
SHub6_5 SHub6_4 SHub6_3 SHub6_2 SHub6_1 SHub6_0
10.47
SHub6_[7:0]
Table 127. SENSORHUB6_REG register description
Sixth byte associated to external sensors
SENSORHUB7_REG (34h)
Seventh byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
SHub7_7 SHub7_6
Table 128. SENSORHUB7_REG register
SHub7_5 SHub7_4 SHub7_3 SHub7_2 SHub7_1 SHub7_0
SHub7_[7:0]
Table 129. SENSORHUB7_REG register description
Seventh byte associated to external sensors
DS12171 - Rev 3 page 67/116
ISM330DLC
SENSORHUB8_REG (35h)
10.48
SENSORHUB8_REG (35h)
Eighth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
SHub8_7 SHub8_6
Table 130. SENSORHUB8_REG register
SHub8_5 SHub8_4 SHub8_3 SHub8_2 SHub8_1 SHub8_0
10.49
SHub8_[7:0]
Table 131. SENSORHUB8_REG register description
Eighth byte associated to external sensors
SENSORHUB9_REG (36h)
Ninth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
SHub9_7 SHub9_6
Table 132. SENSORHUB9_REG register
SHub9_5 SHub9_4 SHub9_3 SHub9_2 SHub9_1 SHub9_0
10.50
SHub9_[7:0]
Table 133. SENSORHUB9_REG register description
Ninth byte associated to external sensors
SENSORHUB10_REG (37h)
Tenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
SHub10_7 SHub10_6
Table 134. SENSORHUB10_REG register
SHub10_5 SHub10_4 SHub10_3 SHub10_2 SHub10_1 SHub10_0
10.51
SHub10_[7:0]
Table 135. SENSORHUB10_REG register description
Tenth byte associated to external sensors
SENSORHUB11_REG (38h)
Eleventh byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
SHub11_7 SHub11_6
Table 136. SENSORHUB11_REG register
SHub11_5 SHub11_4 SHub11_3 SHub11_2 SHub11_1 SHub11_0
SHub11_[7:0]
Table 137. SENSORHUB11_REG register description
Eleventh byte associated to external sensors
DS12171 - Rev 3 page 68/116
ISM330DLC
SENSORHUB12_REG (39h)
10.52
SENSORHUB12_REG (39h)
Twelfth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
SHub12_7 SHub12_6
Table 138. SENSORHUB12_REG register
SHub12_5 SHub12_4 SHub12_3 SHub12_2 SHub12_1 SHub12_0
10.53
SHub12[7:0]
Table 139. SENSORHUB12_REG register description
Twelfth byte associated to external sensors
FIFO_STATUS1 (3Ah)
FIFO status control register (r). For a proper read of the register, it is recommended to set the BDU bit in
to 1.
DIFF_FIFO_7 DIFF_FIFO_6
Table 140. FIFO_STATUS1 register
DIFF_FIFO_5 DIFF_FIFO_4 DIFF_FIFO_3 DIFF_FIFO_2 DIFF_FIFO_1 DIFF_FIFO_0
10.54
DIFF_FIFO_[7:0]
Table 141. FIFO_STATUS1 register description
Number of unread words (16-bit axes) stored in FIFO.
FIFO_STATUS2 (3Bh)
FIFO status control register (r). For a proper read of the register, it is recommended to set the BDU bit in
to 1.
WaterM OVER_RUN
Table 142. FIFO_STATUS2 register
FIFO_FULL_
SMART
FIFO_EMPTY 0 DIFF_FIFO_10 DIFF_FIFO_9 DIFF_FIFO_8
Table 143. FIFO_STATUS2 register
WaterM
OVER_RUN
FIFO_FULL_SMART
FIFO_EMPTY
DIFF_FIFO_[10:8]
FIFO watermark status. The watermark is set through bits FTH_[7:0] in FIFO_CTRL1 (06h)
. Default value: 0
(0: FIFO filling is lower than watermark level
1: FIFO filling is equal to or higher than the watermark level)
FIFO overrun status. Default value: 0
(0: FIFO is not completely filled; 1: FIFO is completely filled)
Smart FIFO full status. Default value: 0
(0: FIFO is not full; 1: FIFO will be full at the next ODR)
FIFO empty bit. Default value: 0
(0: FIFO contains data; 1: FIFO is empty)
Number of unread words (16-bit axes) stored in FIFO.
1. FIFO watermark level is set in FTH_[10:0] in FIFO_CTRL1 (06h) and FIFO_CTRL2 (07h)
2. For a complete number of unread samples, consider DIFF_FIFO [7:0] in
DS12171 - Rev 3 page 69/116
ISM330DLC
FIFO_STATUS3 (3Ch)
10.55
FIFO_STATUS3 (3Ch)
FIFO status control register (r). For a proper read of the register, it is recommended to set the BDU bit in
to 1.
FIFO_
PATTERN_7
FIFO_
PATTERN_6
Table 144. FIFO_STATUS3 register
FIFO_
PATTERN_5
FIFO_
PATTERN_4
FIFO_
PATTERN_3
FIFO_
PATTERN_2
FIFO_
PATTERN_1
FIFO_
PATTERN_0
10.56
FIFO_PATTERN_[7:0]
Table 145. FIFO_STATUS3 register description
Word of recursive pattern read at the next read.
FIFO_STATUS4 (3Dh)
FIFO status control register (r). For a proper read of the register, it is recommended to set the BDU bit in
to 1.
0 0 0
Table 146. FIFO_STATUS4 register
0 0 0
FIFO_
PATTERN_9
FIFO_
PATTERN_8
10.57
FIFO_PATTERN_[9:8]
Table 147. FIFO_STATUS4 register description
Word of recursive pattern read at the next read.
FIFO_DATA_OUT_L (3Eh)
to 1.
DATA_OUT_
FIFO_L_7
DATA_OUT_
FIFO_L_6
Table 148. FIFO_DATA_OUT_L register
DATA_OUT_
FIFO_L_5
DATA_OUT_
FIFO_L_4
DATA_OUT_
FIFO_L_3
DATA_OUT_
FIFO_L_2
DATA_OUT_
FIFO_L_1
DATA_OUT_
FIFO_L_0
DATA_OUT_FIFO_L_[7:0]
Table 149. FIFO_DATA_OUT_L register description
FIFO data output (first byte)
DS12171 - Rev 3 page 70/116
ISM330DLC
FIFO_DATA_OUT_H (3Fh)
10.58
FIFO_DATA_OUT_H (3Fh)
to 1.
DATA_OUT_
FIFO_H_7
DATA_OUT_
FIFO_H_6
Table 150. FIFO_DATA_OUT_H register
DATA_OUT_
FIFO_H_5
DATA_OUT_
FIFO_H_4
DATA_OUT_
FIFO_H_3
DATA_OUT_
FIFO_H_2
DATA_OUT_
FIFO_H_1
DATA_OUT_
FIFO_H_0
10.59
DATA_OUT_FIFO_H_[7:0]
Table 151. FIFO_DATA_OUT_H register description
FIFO data output (second byte)
TIMESTAMP0_REG (40h)
Timestamp first (least significant) byte data output register (r). The value is expressed as a 24-bit word and the bit resolution is defined by setting the value in
TIME
STAMP0_7
TIME
STAMP0_6
Table 152. TIMESTAMP0_REG register
TIME
STAMP0_5
TIME
STAMP0_4
TIME
STAMP0_3
TIME
STAMP0_2
TIME
STAMP0_1
TIME
STAMP0_0
10.60
TIMESTAMP0_[7:0]
Table 153. TIMESTAMP0_REG register description
TIMESTAMP first byte data output
TIMESTAMP1_REG (41h)
Timestamp second byte data output register (r). The value is expressed as a 24-bit word and the bit resolution is defined by setting value in
.
TIME
STAMP1_7
TIME
STAMP1_6
Table 154. TIMESTAMP1_REG register
TIME
STAMP1_5
TIME
STAMP1_4
TIME
STAMP1_3
TIME
STAMP1_2
TIME
STAMP1_1
TIME
STAMP1_0
TIMESTAMP1_[7:0]
Table 155. TIMESTAMP1_REG register description
TIMESTAMP second byte data output
DS12171 - Rev 3 page 71/116
ISM330DLC
TIMESTAMP2_REG (42h)
10.61
TIMESTAMP2_REG (42h)
Timestamp third (most significant) byte data output register (r/w). The value is expressed as a 24-bit word and the bit resolution is defined by setting the value in
WAKE_UP_DUR (5Ch) . To reset the timer, the AAh value has to be
stored in this register.
TIME
STAMP2_7
TIME
STAMP2_6
Table 156. TIMESTAMP2_REG register
TIME
STAMP2_5
TIME
STAMP2_4
TIME
STAMP2_3
TIME
STAMP2_2
TIME
STAMP2_1
TIME
STAMP2_0
10.62
TIMESTAMP2_[7:0]
Table 157. TIMESTAMP2_REG register description
TIMESTAMP third byte data output
SENSORHUB13_REG (4Dh)
Thirteenth byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
SHub13_7 SHub13_6
Table 158. SENSORHUB13_REG register
SHub13_5 SHub13_4 SHub13_3 SHub13_2 SHub13_1 SHub13_0
10.63
SHub13_[7:0]
Table 159. SENSORHUB13_REG register description
Thirteenth byte associated to external sensors
SENSORHUB14_REG (4Eh)
Fourteenth byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
SHub14_7 SHub14_6
Table 160. SENSORHUB14_REG register
SHub14_5 SHub14_4 SHub14_3 SHub14_2 SHub14_1 SHub14_0
10.64
SHub14_[7:0]
Table 161. SENSORHUB14_REG register description
Fourteenth byte associated to external sensors
SENSORHUB15_REG (4Fh)
Fifteenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
SHub15_7 SHub15_6
Table 162. SENSORHUB15_REG register
SHub15_5 SHub15_4 SHub15_3 SHub15_2 SHub15_1 SHub15_0
SHub15_[7:0]
Table 163. SENSORHUB15_REG register description
Fifteenth byte associated to external sensors
DS12171 - Rev 3 page 72/116
ISM330DLC
SENSORHUB16_REG (50h)
10.65
SENSORHUB16_REG (50h)
Sixteenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
SHub16_7 SHub16_6
Table 164. SENSORHUB16_REG register
SHub16_5 SHub16_4 SHub16_3 SHub16_2 SHub16_1 SHub16_0
10.66
SHub16_[7:0]
Table 165. SENSORHUB16_REG register description
Sixteenth byte associated to external sensors
SENSORHUB17_REG (51h)
Seventeenth byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
SHub17_7 SHub17_6
Table 166. SENSORHUB17_REG register
SHub17_5 SHub17_4 SHub17_3 SHub17_2 SHub17_1 SHub17_0
10.67
SHub17_[7:0]
Table 167. SENSORHUB17_REG register description
Seventeenth byte associated to external sensors
SENSORHUB18_REG (52h)
Eighteenth byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
SHub18_7 SHub18_6
Table 168. SENSORHUB18_REG register
SHub18_5 SHub18_4 SHub18_3 SHub18_2 SHub18_1 SHub18_0
SHub18_[7:0]
Table 169. SENSORHUB18_REG register description
Eighteenth byte associated to external sensors
DS12171 - Rev 3 page 73/116
ISM330DLC
FUNC_SRC1 (53h)
10.68
FUNC_SRC1 (53h)
Tilt, hard/soft-iron and sensor hub interrupt source register (r).
0 0 TILT_IA
Table 170. FUNC_SRC1 register
0 0 HI_FAIL SI_END_OP
SENSOR
HUB_END_OP
10.69
TILT_IA
HI_FAIL
SI_END_OP
SENSORHUB_END_OP
Table 171. FUNC_SRC1 register description
Tilt event detection status. Default value: 0
(0: tilt event not detected; 1: tilt event detected)
Fail in hard/soft-ironing algorithm.
Hard/soft-iron calculation status. Default value: 0
(0: Hard/soft-iron calculation not concluded; 1: Hard/soft-iron calculation concluded)
Sensor hub communication status. Default value: 0
(0: sensor hub communication not concluded; 1: sensor hub communication concluded)
FUNC_SRC2 (54h)
Slave communication register (r).
0 SLAVE3_NACK
Table 172. FUNC_SRC2 register
SLAVE2_NACK SLAVE1_NACK SLAVE0_NACK 0 0 0
SLAVE3_NACK
SLAVE2_NACK
SLAVE1_NACK
SLAVE0_NACK
Table 173. FUNC_SRC2 register description
This bit is set to 1 if Not Acknowledge occurs on slave 3 communication. Default value: 0
This bit is set to 1 if Not Acknowledge occurs on slave 2 communication. Default value: 0
This bit is set to 1 if Not Acknowledge occurs on slave 1 communication. Default value: 0
This bit is set to 1 if Not Acknowledge occurs on slave 0 communication. Default value: 0
DS12171 - Rev 3 page 74/116
ISM330DLC
TAP_CFG (58h)
10.70
TAP_CFG (58h)
Enables interrupt and inactivity functions, configuration of filtering, and tap recognition functions (r/w).
INTERRUPTS_
ENABLE
INACT_EN1 INACT_EN0
Table 174. TAP_CFG register
SLOPE_FDS TAP_X_EN TAP_Y_EN TAP_Z_EN LIR
10.71
Table 175. TAP_CFG register description
INTERRUPTS_ENABLE
Enable basic interrupts (6D/4D, free-fall, wake-up, tap, inactivity). Default value: 0
(0: interrupt disabled; 1: interrupt enabled)
INACT_EN[1:0]
Enable inactivity function. Default value: 00
(00: disabled
01: sets accelerometer ODR to 12.5 Hz (low-power mode), gyro does not change;
10: sets accelerometer ODR to 12.5 Hz (low-power mode), gyro to sleep mode;
11: sets accelerometer ODR to 12.5 Hz (low-power mode), gyro to power-down mode)
SLOPE_FDS
TAP_X_EN
HPF or SLOPE filter selection on wake-up and activity/inactivity functions. Refer to
Figure 9. Accelerometer composite filter (for Modes 1/2 and Mode 3*) . Default value: 0
0: SLOPE filter applied; 1: HPF applied)
Enable X direction in tap recognition. Default value: 0
(0: X direction disabled; 1: X direction enabled)
TAP_Y_EN
TAP_Z_EN
LIR
Enable Y direction in tap recognition. Default value: 0
(0: Y direction disabled; 1: Y direction enabled)
Enable Z direction in tap recognition. Default value: 0
(0: Z direction disabled; 1: Z direction enabled)
Latched Interrupt. Default value: 0
(0: interrupt request not latched; 1: interrupt request latched)
TAP_THS_6D (59h)
Portrait/landscape position and tap function threshold register (r/w).
D4D_EN
Table 176. TAP_THS_6D register
SIXD_THS1 SIXD_THS0 TAP_THS4 TAP_THS3 TAP_THS2 TAP_THS1 TAP_THS0
D4D_EN
SIXD_THS[1:0]
TAP_THS[4:0]
Table 177. TAP_THS_6D register description
4D orientation detection enable. Z-axis position detection is disabled.
Default value: 0
(0: enabled; 1: disabled)
Threshold for 4D/6D function. Default value: 00
For details, refer to
Table 178. Threshold for D4D/D6D function
.
Threshold for tap recognition. Default value: 00000
1 LSb corresponds to FS_XL/2 5
DS12171 - Rev 3 page 75/116
ISM330DLC
INT_DUR2 (5Ah)
10.72
SIXD_THS[1:0]
00
01
10
11
Table 178. Threshold for D4D/D6D function
Threshold value
80 degrees
70 degrees
60 degrees
50 degrees
INT_DUR2 (5Ah)
Tap recognition function setting register (r/w).
DUR3 DUR2 DUR1
Table 179. INT_DUR2 register
DUR0 QUIET1 QUIET0 SHOCK1
SINGLE_DOUBLE_TAP
WK_THS[5:0]
SHOCK0
10.73
Table 180. INT_DUR2 register description
DUR[3:0]
QUIET[1:0]
Duration of maximum time gap for double tap recognition. Default: 0000
When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to
16*ODR_XL time. If the DUR[3:0] bits are set to a different value, 1LSB corresponds to 32*ODR_XL time.
Expected quiet time after a tap detection. Default value: 00
Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different value, 1LSB corresponds to 4*ODR_XL time.
SHOCK[1:0]
Maximum duration of overthreshold event. Default value: 00
Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event.
The default value of these bits is 00b which corresponds to 4*ODR_XL time. If the SHOCK[1:0] bits are set to a different value, 1LSB corresponds to 8*ODR_XL time.
WAKE_UP_THS (5Bh)
Single and double-tap function threshold register (r/w).
SINGLE_
DOUBLE_TAP
0
Table 181. WAKE_UP_THS register
WK_THS5 WK_THS4 WK_THS3 WK_THS2 WK_THS1 WK_THS0
Table 182. WAKE_UP_THS register description
Single/double-tap event enable. Default: 0
(0: only single-tap event enabled;
1: both single and double-tap events enabled)
Threshold for wakeup. Default value: 000000
1 LSb corresponds to FS_XL/2 6
DS12171 - Rev 3 page 76/116
ISM330DLC
WAKE_UP_DUR (5Ch)
10.74
WAKE_UP_DUR (5Ch)
Free-fall, wakeup, timestamp and sleep mode functions duration setting register (r/w).
FF_DUR5 WAKE_DUR1
Table 183. WAKE_UP_DUR register
WAKE_DUR0 TIMER_HR SLEEP_DUR3 SLEEP_DUR2 SLEEP_DUR1 SLEEP_DUR0
10.75
Table 184. WAKE_UP_DUR register description
FF_DUR5
WAKE_DUR[1:0]
TIMER_HR
SLEEP_DUR[3:0]
Free fall duration event. Default: 0
For the complete configuration of the free-fall duration, refer to FF_DUR[4:0] in FREE_FALL (5Dh)
configuration.
1 LSB = 1 ODR_time
Wake up duration event. Default: 00
1LSB = 1 ODR_time
Timestamp register resolution setting
. Default value: 0
(0: 1LSB = 6.4 ms; 1: 1LSB = 25 µs)
Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR)
1 LSB = 512 ODR
1. Configuration of this bit affects the
TIMESTAMP0_REG (40h) , TIMESTAMP1_REG (41h) , and
registers.
FREE_FALL (5Dh)
Free-fall function duration setting register (r/w).
FF_DUR4 FF_DUR3 FF_DUR2
Table 185. FREE_FALL register
FF_DUR1 FF_DUR0 FF_THS2 FF_THS1 FF_THS0
FF_DUR[4:0]
FF_THS[2:0]
Table 186. FREE_FALL register description
Free-fall duration event. Default: 0
For the complete configuration of the free fall duration, refer to FF_DUR5 in
configuration.
Free fall threshold setting. Default: 000
For details refer to
FF_THS[2:0]
000
001
010
011
100
101
110
111
Table 187. Threshold for free-fall function
Threshold value
156 m g
219 m g
250 m g
312 m g
344 m g
406 m g
469 m g
500 m g
DS12171 - Rev 3 page 77/116
ISM330DLC
MD1_CFG (5Eh)
10.76
MD1_CFG (5Eh)
Functions routing on INT1 register (r/w).
INT1_INACT_
STATE
INT1_
SINGLE_TAP
INT1_WU
Table 188. MD1_CFG register
INT1_FF
INT1_
DOUBLE_TAP
INT1_6D INT1_TILT INT1_ TIMER
INT1_INACT_STATE
INT1_SINGLE_TAP
INT1_WU
INT1_FF
INT1_DOUBLE_TAP
INT1_6D
INT1_TILT
INT1 _TIMER
Table 189. MD1_CFG register description
Routing on INT1 of inactivity mode. Default: 0
(0: routing on INT1 of inactivity disabled; 1: routing on INT1 of inactivity enabled)
Single-tap recognition routing on INT1. Default: 0
(0: routing of single-tap event on INT1 disabled;
1: routing of single-tap event on INT1 enabled)
Routing of wakeup event on INT1. Default value: 0
(0: routing of wakeup event on INT1 disabled;
1: routing of wakeup event on INT1 enabled)
Routing of free-fall event on INT1. Default value: 0
(0: routing of free-fall event on INT1 disabled;
1: routing of free-fall event on INT1 enabled)
Routing of tap event on INT1. Default value: 0
(0: routing of double-tap event on INT1 disabled;
1: routing of double-tap event on INT1 enabled)
Routing of 6D event on INT1. Default value: 0
(0: routing of 6D event on INT1 disabled; 1: routing of 6D event on INT1 enabled)
Routing of tilt event on INT1. Default value: 0
(0: routing of tilt event on INT1 disabled; 1: routing of tilt event on INT1 enabled)
Routing of end counter event of timer on INT1. Default value: 0
(0: routing of end counter event of timer on INT1 disabled;
1: routing of end counter event of timer event on INT1 enabled)
DS12171 - Rev 3 page 78/116
ISM330DLC
MD2_CFG (5Fh)
10.77
MD2_CFG (5Fh)
Functions routing on INT2 register (r/w).
INT2_INACT_
STATE
INT2_
SINGLE_TAP
Table 190. MD2_CFG register
INT2_WU INT2_FF
INT2_
DOUBLE_TAP
INT2_6D INT2_TILT INT2_IRON
10.78
INT2_INACT_STATE
INT2_SINGLE_TAP
INT2_WU
INT2_FF
INT2_DOUBLE_TAP
INT2_6D
INT2_TILT
INT2_IRON
Table 191. MD2_CFG register description
Routing on INT2 of inactivity mode. Default: 0
(0: routing on INT2 of inactivity disabled; 1: routing on INT2 of inactivity enabled)
Single-tap recognition routing on INT2. Default: 0
(0: routing of single-tap event on INT2 disabled;
1: routing of single-tap event on INT2 enabled)
Routing of wakeup event on INT2. Default value: 0
(0: routing of wakeup event on INT2 disabled;
1: routing of wake-up event on INT2 enabled)
Routing of free-fall event on INT2. Default value: 0
(0: routing of free-fall event on INT2 disabled;
1: routing of free-fall event on INT2 enabled)
Routing of tap event on INT2. Default value: 0
(0: routing of double-tap event on INT2 disabled;
1: routing of double-tap event on INT2 enabled)
Routing of 6D event on INT2. Default value: 0
(0: routing of 6D event on INT2 disabled; 1: routing of 6D event on INT2 enabled)
Routing of tilt event on INT2. Default value: 0
(0: routing of tilt event on INT2 disabled; 1: routing of tilt event on INT2 enabled)
Routing of soft-iron/hard-iron algorithm end event on INT2. Default value: 0
(0: routing of soft-iron/hard-iron algorithm end event on INT2 disabled;
1: routing of soft-iron/hard-iron algorithm end event on INT2 enabled)
MASTER_CMD_CODE (60h)
Table 192. MASTER_CMD_CODE register
MASTER_
CMD_CODE7
MASTER_
CMD_CODE6
MASTER_
CMD_CODE5
MASTER_
CMD_CODE4
MASTER_
CMD_CODE3
MASTER_
CMD_CODE2
MASTER_
CMD_CODE1
MASTER_
CMD_CODE0
MASTER_CMD_CODE[7:0]
Table 193. MASTER_CMD_CODE register description
Master command code used for stamping for sensor sync. Default value: 0
DS12171 - Rev 3 page 79/116
ISM330DLC
SENS_SYNC_SPI_ERROR_CODE (61h)
10.79
SENS_SYNC_SPI_ERROR_CODE (61h)
ERROR_
CODE7
ERROR_
CODE6
Table 194. SENS_SYNC_SPI_ERROR_CODE register
ERROR_
CODE5
ERROR_
CODE4
ERROR_
CODE3
ERROR_
CODE2
ERROR_
CODE1
ERROR_
CODE0
10.80
ERROR_CODE[7:0]
Table 195. SENS_SYNC_SPI_ERROR_CODE register description
Error code used for sensor synchronization. Default value: 0
OUT_MAG_RAW_X_L (66h)
External magnetometer raw data (r).
D7 D6
Table 196. OUT_MAG_RAW_X_L register
D5 D4 D3 D2 D1
10.81
D[7:0]
Table 197. OUT_MAG_RAW_X_L register description
X-axis external magnetometer value (LSbyte)
OUT_MAG_RAW_X_H (67h)
External magnetometer raw data (r).
D15 D14
Table 198. OUT_MAG_RAW_X_H register
D13 D12 D11 D10 D9
D0
D8
10.82
D[15:8]
Table 199. OUT_MAG_RAW_X_H register description
X-axis external magnetometer value (MSbyte)
OUT_MAG_RAW_Y_L (68h)
External magnetometer raw data (r).
D7 D6
Table 200. OUT_MAG_RAW_Y_L register
D5 D4 D3 D2 D1
D[7:0]
Table 201. OUT_MAG_RAW_Y_L register description
Y-axis external magnetometer value (LSbyte)
D0
DS12171 - Rev 3 page 80/116
ISM330DLC
OUT_MAG_RAW_Y_H (69h)
10.83
OUT_MAG_RAW_Y_H (69h)
External magnetometer raw data (r).
D15 D14
Table 202. OUT_MAG_RAW_Y_H register
D13 D12 D11 D10
10.84
D[15:8]
Table 203. OUT_MAG_RAW_Y_H register description
Y-axis external magnetometer value (MSbyte)
OUT_MAG_RAW_Z_L (6Ah)
External magnetometer raw data (r).
D7 D6
Table 204. OUT_MAG_RAW_Z_L register
D5 D4 D3 D2 D1
D9 D8
D0
10.85
D[7:0]
Table 205. OUT_MAG_RAW_Z_L register description
Z-axis external magnetometer value (LSbyte)
OUT_MAG_RAW_Z_H (6Bh)
External magnetometer raw data (r).
D15 D14
Table 206. OUT_MAG_RAW_Z_H register
D13 D12 D11 D10 D9 D8
10.86
D[15:8]
Table 207. OUT_MAG_RAW_Z_H register description
Z-axis external magnetometer value (MSbyte)
INT_OIS (6Fh)
OIS interrupt configuration register. Primary interface for read-only (r); only Aux SPI can write to this register (r/w).
INT2_
DRDY_OIS
LVL2_OIS -
Table 208. INT_OIS register
-
Table 209. INT_OIS register description
INT2_DRDY_OIS Enables the OIS chain DRDY on the INT2 pad. This setting has priority over all other INT2 settings.
LVL2_OIS Enables level-sensitive latched mode on the OIS chain. Default value: 0
DS12171 - Rev 3 page 81/116
ISM330DLC
CTRL1_OIS (70h)
10.87
CTRL1_OIS (70h)
OIS configuration register. Primary interface for read-only (r); only Aux SPI can write to this register (r/w).
Table 210. CTRL1_OIS register
BLE_OIS LVL1_OIS SIM_OIS MODE4_EN FS1_G_OIS FS0_G_OIS FS_125_OIS OIS_EN_SPI2
Table 211. CTRL1_OIS register description
BLE_OIS
LVL1_OIS
SIM_OIS
MODE4_EN
Big/Little Endian data selection. Default value: 0
(0: output LSbyte at lower register address;
1: output LSbyte at higher register address)
Enables level-sensitive trigger mode on OIS chain. Default value: 0
SPI2 3- or 4-wire mode. Default value: 0
(0: 4-wire SPI2; 1: 3-wire SPI2)
Enables accelerometer OIS chain if OIS_EN_SPI2 = 1. Default value: 0
(0: disable; 1: enable)
Gyroscope OIS chain full-scale selection.
(00: ±250 dps;
FS[1:0]_G_OIS 01: ±500 dps;
10: ±1000 dps;
11: ±2000 dps)
FS_125_OIS
OIS_EN_SPI2
Selects gyroscope OIS chain full scale ±125 dps
(0: FS selected through bits FS[1:0]_G_OIS; 1 = ±125 dps)
Enables OIS chain data processing for gyro in Mode 3 and Mode 4 (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
When the OIS chain is enabled, the OIS outputs are available through the SPI2 in registers
STATUS_REG/STATUS_SPIAux (1Eh) , and LPF1 is dedicated to this
chain.
register
.
DEN mode on the OIS path is active in the gyroscope only.
LVL1_OIS, LVL2_OIS
10
11
Table 212. DEN mode selection
DEN mode
Level-sensitive trigger mode is selected
Level-sensitive latched mode is selected
DS12171 - Rev 3 page 82/116
ISM330DLC
CTRL2_OIS (71h)
10.88
CTRL2_OIS (71h)
OIS configuration register. Primary interface for read-only (r); only Aux SPI can write to this register (r/w).
Table 213. CTRL2_OIS register
0
0
HPM1_OIS HPM0_OIS
1. This bit must be set to '0' for the correct operation of the device.
0
FTYPE_1_OIS FTYPE_0_OIS HP_EN_OIS
Table 214. CTRL2_OIS register description
HPM[1:0]_OIS
Gyroscope's OIS chain digital high-pass filter cutoff selection. Default value: 00
(00: 16 mHz;
01: 65 mHz;
10: 260 mHz;
11: 1.04 Hz)
FTYPE_[1:0]_OIS
Gyroscope's digital LPF1 filter bandwidth selection
shows cutoff and phase values obtained with all configurations
HP_EN_OIS
Enables gyroscope's OIS chain HPF. This filter is available on the OIS chain only if HP_EN_G in
is set to '0'.
1. HP_EN_OIS is active to select HPF on the auxiliary SPI chain only if HPF is not already used in the primary interface.
Table 215. Gyroscope OIS chain LPF1 bandwidth selection
ODR = 6.6 kHz
FTYPE_[1:0]_OIS
00
01
10
11
BW
351 Hz
237 Hz
173 Hz
937 Hz
Phase delay @ 20 Hz
7°
9°
11°
5°
10.89
Sampling data with frequency equal or higher to 3.3 kHz is recommended.
If data is down-sampled @ 1 kHz, it is recommended to use a cutoff @ 173 Hz.
If data is down-sampled @ 2 kHz, it is recommended to use a cutoff @ 237 Hz.
CTRL3_OIS (72h)
OIS configuration register. Primary interface for read-only (r); only Aux SPI can write to this register (r/w).
DEN_LH_OIS FS1_XL_OIS FS0_XL_OIS
Table 216. CTRL3_OIS register
FILTER_XL_
CONF_OIS_1
FILTER_XL_
CONF_OIS_0
ST1_OIS ST0_OIS
ST_OIS_
CLAMPDIS
DS12171 - Rev 3 page 83/116
DS12171 - Rev 3
ISM330DLC
CTRL3_OIS (72h)
DEN_LH_OIS
FS[1:0]_XL_OIS
FILTER_XL_CONF_OIS
[1:0]
ST[1:0]_OIS
ST_OIS_CLAMPDIS
Table 217. CTRL3_OIS register description
Polarity of DEN signal on OIS chain
(0: DEN pin is active-low;
1: DEN pin is active-high)
Accelerometer OIS channel full-scale selection. Default value: 00
(00: ±2 g ;
01: ±16 g ;
10: ±4 g ;
11: ±8 g )
These two bits act only when the accelerometer GP chain is in power-down, otherwise the accelerometer FS value is selected only from the GP side (but it is readable also from the OIS side).
Accelerometer OIS channel bandwidth selection (see Table 215
)
Gyroscope OIS chain self-test selection
Table 219 lists the output variation when the self-test is enabled and ST_OIS_CLAMPDIS = '1'.
Default value: 00
(00: Normal mode;
01: Positive sign self-test;
10: Normal mode;
11: Negative sign self-test)
Gyro OIS chain clamp disable
(0: All gyro OIS chain outputs = 8000h during self-test applied from primary interface;
1: OIS chain self-test outputs as shown in
Table 219. Self-test nominal output variation
if self-test applied from primary or auxiliary interfaces)
FILTER_XL_
CONF_OIS [1:0]
00
01
10
11
1. Phase delay @ 20 Hz
Table 218. Accelerometer OIS channel bandwidth selection
BW
ODR_GP = 0
ODR GP ≥ 1600 Hz
140 Hz
68.2 Hz
636 Hz
295 Hz
9.39°
17.6°
2.96°
5.12°
BW
128 Hz
66.5 Hz
329 Hz
222 Hz
ODR GP ≤ 800 Hz
Phase delay
11.5°
19.7°
5.08°
7.23°
Full scale
±2000
±1000
±500
±250
±125
Table 219. Self-test nominal output variation
Output variation [dps]
400
200
100
50
25 page 84/116
ISM330DLC
X_OFS_USR (73h)
10.90
X_OFS_USR (73h)
Accelerometer X-axis user offset correction (r/w). The offset value set in the X_OFS_USR offset register is internally added to the acceleration value measured on the X-axis.
X_OFS_
USR_7
X_OFS_
USR_6
X_OFS_
USR_5
Table 220. X_OFS_USR register
X_OFS_
USR_4
X_OFS_
USR_3
X_OFS_
USR_2
X_OFS_
USR_1
X_OFS_
USR_0
10.91
Table 221. X_OFS_USR register description
X_OFS_USR_[7:0]
Accelerometer X-axis user offset correction expressed in two’s complement, weight depends on the
CTRL6_C(4) bit. The value must be in the range [-127 127].
Y_OFS_USR (74h)
Accelerometer Y-axis user offset correction (r/w). The offset value set in the Y_OFS_USR offset register is internally added to the acceleration value measured on the Y-axis.
Y_OFS_
USR_7
Y_OFS_
USR_6
Y_OFS_
USR_5
Table 222. Y_OFS_USR register
Y_OFS_
USR_4
Y_OFS_
USR_3
Y_OFS_
USR_2
Y_OFS_
USR_1
Y_OFS_
USR_0
10.92
Table 223. Y_OFS_USR register description
Y_OFS_USR_[7:0]
Accelerometer Y-axis user offset correction expressed in two’s complement, weight depends on the
CTRL6_C(4) bit. The value must be in the range [-127 127].
Z_OFS_USR (75h)
Accelerometer Z-axis user offset correction (r/w). The offset value set in the Z_OFS_USR offset register is internally subtracted from the acceleration value measured on the Z-axis.
Z_OFS_
USR_7
Z_OFS_
USR_6
Z_OFS_
USR_5
Table 224. Z_OFS_USR register
Z_OFS_
USR_4
Z_OFS_
USR_3
Z_OFS_
USR_2
Z_OFS_
USR_1
Z_OFS_
USR_0
Table 225. Z_OFS_USR register description
Z_OFS_USR_[7:0]
Accelerometer Z-axis user offset correction expressed in two’s complement, weight depends on the
CTRL6_C(4) bit. The value must be in the range [-127 127].
DS12171 - Rev 3 page 85/116
11
Note:
ISM330DLC
Embedded functions register mapping
Embedded functions register mapping
Name
MAG_SI_XY
MAG_SI_XZ
MAG_SI_YX
MAG_SI_YY
MAG_SI_YZ
MAG_SI_ZX
MAG_SI_ZY
MAG_SI_ZZ
MAG_OFFX_L
MAG_OFFX_H
MAG_OFFY_L
MAG_OFFY_H
MAG_OFFZ_L
MAG_OFFZ_H
SLV0_ADD
SLV0_SUBADD
SLAVE0_CONFIG
SLV1_ADD
SLV1_SUBADD
SLAVE1_CONFIG
SLV2_ADD
SLV2_SUBADD
SLAVE2_CONFIG
SLV3_ADD
SLV3_SUBADD
SLAVE3_CONFIG
DATAWRITE_SRC_
MODE_SUB_SLV0
RESERVED
MAG_SI_XX
The tables given below provide a list of registers related to the embedded functions available in the device and the corresponding addresses.
The embedded functions registers are accessible when FUNC_CFG_EN is set to ‘1’ in
.
All modifications of the content of the embedded functions registers have to be performed with the device in power-down mode.
r/w r/w r/w r/w r/w r/w r/w
r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w
Table 226. Register address map embedded functions
Type
0A
0B
0C
0D
07
08
09
Hex
Register address
Binary
02
03
04
05
06
00000010
00000011
00000100
00000101
00000110
00000111
00001000
00001001
00001010
00001011
00001100
00001101
Default
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00001110 0E
2A
2B
2C
27
28
29
0F-15
24
25
26
30
31
32
2D
2E
2F
00100100
00100101
00100110
00100111
00101000
00101001
00101010
00101011
00101100
00101101
00101110
00101111
00110000
00110001
00110010
00000000
-
00001000
00000000
00000000
00000000
00001000
00000000
00000000
00000000
00001000
00000000
00000000
00000000
00000000
00000000
00000000
Comment
Reserved
DS12171 - Rev 3 page 86/116
ISM330DLC
Embedded functions register mapping
Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up.
DS12171 - Rev 3 page 87/116
ISM330DLC
Embedded functions registers description
12
Note:
12.1
12.2
Embedded functions registers description
All modifications of the content of the embedded functions registers have to be performed with the device in power-down mode.
SLV0_ADD (02h)
I²C slave address of the first external sensor (Sensor1) register (r/w).
Table 227. SLV0_ADD register
Slave0_add6 Slave0_add5 Slave0_add4 Slave0_add3 Slave0_add2 Slave0_add1 Slave0_add0 rw_0
Slave0_add[6:0] rw_0
Table 228. SLV0_ADD register description
I²C slave address of Sensor1 that can be read by sensor hub.
Default value: 0000000
Read/write operation on Sensor1. Default value: 0
(0: write operation; 1: read operation)
SLV0_SUBADD (03h)
Address of register on the first external sensor (Sensor1) register (r/w).
Table 229. SLV0_SUBADD register
Slave0_reg7 Slave0_reg6 Slave0_reg5 Slave0_reg4 Slave0_reg3 Slave0_reg2 Slave0_reg1 Slave0_reg0
Table 230. SLV0_SUBADD register description
Slave0_reg[7:0]
Address of register on Sensor1 that has to be read/write according to the rw_0 bit value in
.
Default value: 00000000
DS12171 - Rev 3 page 88/116
ISM330DLC
SLAVE0_CONFIG (04h)
12.3
12.4
SLAVE0_CONFIG (04h)
First external sensor (Sensor1) configuration and sensor hub settings register (r/w).
Slave0_rate1 Slave0_rate0
Table 231. SLAVE0_CONFIG register
Aux_sens_on1 Aux_sens_on0 Src_mode Slave0_numop2 Slave0_numop1 Slave0_numop0
Table 232. SLAVE0_CONFIG register description
Slave0_rate[1:0]
Aux_sens_on[1:0]
Decimation of read operation on Sensor1 starting from the sensor hub trigger. Default value: 00
(00: no decimation;
01: update every 2 samples;
10: update every 4 samples;
11: update every 8 samples.)
Number of external sensors to be read by sensor hub. Default value: 00
(00: one sensor;
01: two sensors;
10: three sensors;
11: four sensors.)
Src_mode
Source mode conditioned read. Default value: 0 (1)
(0: source mode read disabled; 1: source mode read enabled)
Slave0_numop[2:0] Number of read operations on Sensor1.
1. Read conditioned by the content of the register at address specified in the
DATAWRITE_SRC_MODE_SUB_SLV0 (0Eh)
register. If the content is non-zero, the operation continues with the reading of the address specified in the
register, else the operation is interrupted.
SLV1_ADD (05h)
I²C slave address of the second external sensor (Sensor2) register (r/w).
Table 233. SLV1_ADD register
Slave1_add6 Slave1_add5 Slave1_add4 Slave1_add3 Slave1_add2 Slave1_add1 Slave1_add0 r_1
Slave1_add[6:0] r_1
Table 234. SLV1_ADD register description
I²C slave address of Sensor2 that can be read by sensor hub.
Default value: 0000000
Read operation on Sensor2 enable. Default value: 0
(0: read operation disabled; 1: read operation enabled)
DS12171 - Rev 3 page 89/116
ISM330DLC
SLV1_SUBADD (06h)
12.5
12.6
SLV1_SUBADD (06h)
Address of register on the second external sensor (Sensor2) register (r/w).
Table 235. SLV1_SUBADD register
Slave1_reg7 Slave1_reg6 Slave1_reg5 Slave1_reg4 Slave1_reg3 Slave1_reg2 Slave1_reg1 Slave1_reg0
Table 236. SLV1_SUBADD register description
Slave1_reg[7:0]
Address of register on Sensor2 that has to be read according to the r_1 bit value in SLV1_ADD (05h)
.
Default value: 00000000
SLAVE1_CONFIG (07h)
Second external sensor (Sensor2) configuration register (r/w).
Table 237. SLAVE1_CONFIG register
Slave1_rate1 Slave1_rate0 write_once
1. This bit must be set to ‘0’ for the correct operation of the device.
Slave1_numop2 Slave1_numop1 Slave1_numop0
Table 238. SLAVE1_CONFIG register description
Slave1_rate[1:0] write_once
Decimation of read operation on Sensor2 starting from the sensor hub trigger. Default value: 00
(00: no decimation;
01: update every 2 samples;
10: update every 4 samples;
11: update every 8 samples.)
Slave 0 write operation is performed only at the first sensor hub cycle.
Default value: 0
(0: write operation for each sensor hub cycle;
1: write operation only for the first sensor hub cycle)
Slave1_numop[2:0] Number of read operations on Sensor2.
1. This is effective if the Aux_sens_on[1:0] field in
is set to a value other than 00.
DS12171 - Rev 3 page 90/116
ISM330DLC
SLV2_ADD (08h)
12.7
12.8
12.9
SLV2_ADD (08h)
I²C slave address of the third external sensor (Sensor3) register (r/w).
Table 239. SLV2_ADD register
Slave2_add6 Slave2_add5 Slave2_add4 Slave2_add3 Slave2_add2 Slave2_add1 Slave2_add0 r_2
Slave2_add[6:0] r_2
Table 240. SLV2_ADD register description
I²C slave address of Sensor3 that can be read by sensor hub.
Default value: 0000000
Read operation on Sensor3 enable. Default value: 0
(0: read operation disabled; 1: read operation enabled)
SLV2_SUBADD (09h)
Address of register on the third external sensor (Sensor3) register (r/w).
Table 241. SLV2_SUBADD register
Slave2_reg7 Slave2_reg6 Slave2_reg5 Slave2_reg4 Slave2_reg3 Slave2_reg2 Slave2_reg1 Slave2_reg0
Table 242. SLV2_SUBADD register description
Slave2_reg[7:0]
Address of register on Sensor3 that has to be read according to the r_2 bit value in SLV2_ADD (08h)
.
Default value: 00000000
SLAVE2_CONFIG (0Ah)
Third external sensor (Sensor3) configuration register (r/w).
Table 243. SLAVE2_CONFIG register
Slave2_rate1 Slave2_rate0 0
1. This bit must be set to ‘0’ for the correct operation of the device.
Slave2_numop2 Slave2_numop1 Slave2_numop0
Table 244. SLAVE2_CONFIG register description
Slave2_rate[1:0]
Decimation of read operation on Sensor3 starting from the sensor hub trigger. Default value: 00
(00: no decimation;
01: update every 2 samples;
10: update every 4 samples;
11: update every 8 samples.)
Slave2_numop[2:0] Number of read operations on Sensor3.
DS12171 - Rev 3 page 91/116
ISM330DLC
SLV3_ADD (0Bh)
12.10
SLV3_ADD (0Bh)
I²C slave address of the fourth external sensor (Sensor4) register (r/w).
Slave3_add6 Slave3_add5 Slave3_add4
Table 245. SLV3_ADD register
Slave3_add3 Slave3_add2 Slave3_add1 Slave3_add0 r_3
12.11
Slave3_add[6:0] r_3
Table 246. SLV3_ADD register description
I²C slave address of Sensor4 that can be read by the sensor hub.
Default value: 0000000
Read operation on Sensor4 enable. Default value: 0
(0: read operation disabled; 1: read operation enabled)
SLV3_SUBADD (0Ch)
Address of register on the fourth external sensor (Sensor4) register (r/w).
Table 247. SLV3_SUBADD register
Slave3_reg7 Slave3_reg6 Slave3_reg5 Slave3_reg4 Slave3_reg3 Slave3_reg2 Slave3_reg1 Slave3_reg0
12.12
Table 248. SLV3_SUBADD register description
Slave3_reg[7:0]
Address of register on Sensor4 that has to be read according to the r_3 bit value in SLV3_ADD (0Bh)
.
Default value: 00000000
SLAVE3_CONFIG (0Dh)
Fourth external sensor (Sensor4) configuration register (r/w).
Table 249. SLAVE3_CONFIG register
Slave3_rate1 Slave3_rate0 0
1. This bit must be set to ‘0’ for the correct operation of the device.
Slave3_numop2 Slave3_numop1 Slave3_numop0
Table 250. SLAVE3_CONFIG register description
Slave3_rate[1:0]
Decimation of read operation on Sensor4 starting from the sensor hub trigger. Default value: 00
(00: no decimation;
01: update every 2 samples;
10: update every 4 samples;
11: update every 8 samples.)
Slave3_numop[2:0] Number of read operations on Sensor4.
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DATAWRITE_SRC_MODE_SUB_SLV0 (0Eh)
12.13
DATAWRITE_SRC_MODE_SUB_SLV0 (0Eh)
Data to be written into the slave device register (r/w).
Table 251. DATAWRITE_SRC_MODE_SUB_SLV0 register
Slave_dataw7 Slave_dataw6 Slave_dataw5 Slave_dataw4 Slave_dataw3 Slave_dataw2 Slave_dataw1 Slave_dataw0
12.14
Table 252. DATAWRITE_SRC_MODE_SUB_SLV0 register description
Slave_dataw[7:0]
Data to be written into the slave device according to the rw_0 bit in SLV0_ADD (02h)
register or address to be read in source mode.
Default value: 00000000
MAG_SI_XX (24h)
Soft-iron matrix correction register (r/w).
Table 253. MAG_SI_XX register
MAG_SI_XX_7 MAG_SI_XX_6 MAG_SI_XX_5 MAG_SI_XX_4 MAG_SI_XX_3 MAG_SI_XX_2 MAG_SI_XX_1 MAG_SI_XX_0
12.15
Table 254. MAG_SI_XX register description
MAG_SI_XX_[7:0] Soft-iron correction row1 col1 coefficient
1. Value is expressed in sign-module format.
. Default value: 00001000
MAG_SI_XY (25h)
Soft-iron matrix correction register (r/w).
Table 255. MAG_SI_XY register
MAG_SI_XY_7 MAG_SI_XY_6 MAG_SI_XY_5 MAG_SI_XY_4 MAG_SI_XY_3 MAG_SI_XY_2 MAG_SI_XY_1 MAG_SI_XY_0
12.16
Table 256. MAG_SI_XY register description
MAG_SI_XY_[7:0] Soft-iron correction row1 col2 coefficient
. Default value: 00000000
1. Value is expressed in sign-module format.
MAG_SI_XZ (26h)
Soft-iron matrix correction register (r/w).
Table 257. MAG_SI_XZ register
MAG_SI_XZ_7 MAG_SI_XZ_6 MAG_SI_XZ_5 MAG_SI_XZ_4 MAG_SI_XZ_3 MAG_SI_XZ_2 MAG_SI_XZ_1 MAG_SI_XZ_0
Table 258. MAG_SI_XZ register description
MAG_SI_XZ_[7:0]
Soft-iron correction row1 col3 coefficient (1)
. Default value: 00000000
1. Value is expressed in sign-module format.
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MAG_SI_YX (27h)
12.17
MAG_SI_YX (27h)
Soft-iron matrix correction register (r/w).
Table 259. MAG_SI_YX register
MAG_SI_YX_7 MAG_SI_YX_6 MAG_SI_YX_5 MAG_SI_YX_4 MAG_SI_YX_3 MAG_SI_YX_2 MAG_SI_YX_1 MAG_SI_YX_0
12.18
Table 260. MAG_SI_YX register description
MAG_SI_YX_[7:0] Soft-iron correction row2 col1 coefficient
. Default value: 00000000
1. Value is expressed in sign-module format.
MAG_SI_YY (28h)
Soft-iron matrix correction register (r/w).
Table 261. MAG_SI_YY register
MAG_SI_YY_7 MAG_SI_YY_6 MAG_SI_YY_5 MAG_SI_YY_4 MAG_SI_YY_3 MAG_SI_YY_2 MAG_SI_YY_1 MAG_SI_YY_0
12.19
Table 262. MAG_SI_YY register description
MAG_SI_YY_[7:0] Soft-iron correction row2 col2 coefficient
. Default value: 00001000
1. Value is expressed in sign-module format.
MAG_SI_YZ (29h)
Soft-iron matrix correction register (r/w).
Table 263. MAG_SI_YZ register
MAG_SI_YZ_7 MAG_SI_YZ_6 MAG_SI_YZ_5 MAG_SI_YZ_4 MAG_SI_YZ_3 MAG_SI_YZ_2 MAG_SI_YZ_1 MAG_SI_YZ_0
12.20
Table 264. MAG_SI_YZ register description
MAG_SI_YZ_[7:0]
Soft-iron correction row2 col3 coefficient
1. Value is expressed in sign-module format.
. Default value: 00000000
MAG_SI_ZX (2Ah)
Soft-iron matrix correction register (r/w).
Table 265. MAG_SI_ZX register
MAG_SI_ZX_7 MAG_SI_ZX_6 MAG_SI_ZX_5 MAG_SI_ZX_4 MAG_SI_ZX_3 MAG_SI_ZX_2 MAG_SI_ZX_1 MAG_SI_ZX_0
Table 266. MAG_SI_ZX register description
MAG_SI_ZX_[7:0]
Soft-iron correction row3 col1 coefficient (1)
. Default value: 00000000
1. Value is expressed in sign-module format.
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MAG_SI_ZY (2Bh)
12.21
MAG_SI_ZY (2Bh)
Soft-iron matrix correction register (r/w).
Table 267. MAG_SI_ZY register
MAG_SI_ZY_7 MAG_SI_ZY_6 MAG_SI_ZY_5 MAG_SI_ZY_4 MAG_SI_ZY_3 MAG_SI_ZY_2 MAG_SI_ZY_1 MAG_SI_ZY_0
12.22
Table 268. MAG_SI_ZY register description
MAG_SI_ZY_[7:0]
Soft-iron correction row3 col2 coefficient (1)
. Default value: 00000000
1. Value is expressed in sign-module format.
MAG_SI_ZZ (2Ch)
Soft-iron matrix correction register (r/w).
Table 269. MAG_SI_ZZ register
MAG_SI_ZZ_7 MAG_SI_ZZ_6 MAG_SI_ZZ_5 MAG_SI_ZZ_4 MAG_SI_ZZ_3 MAG_SI_ZZ_2 MAG_SI_ZZ_1 MAG_SI_ZZ_0
12.23
Table 270. MAG_SI_ZZ register description
MAG_SI_ZZ_[7:0]
Soft-iron correction row3 col3 coefficient (1) . Default value: 00001000
1. Value is expressed in sign-module format.
MAG_OFFX_L (2Dh)
Offset for X-axis hard-iron compensation register (r/w). The value is expressed as a 16-bit word in two’s complement.
Table 271. MAG_OFFX_L register
MAG_OFFX_L_7 MAG_OFFX_L_6 MAG_OFFX_L_5 MAG_OFFX_L_4 MAG_OFFX_L_3 MAG_OFFX_L_2 MAG_OFFX_L_1 MAG_OFFX_L_0
12.24
MAG_OFFX_L_[7:0]
Table 272. MAG_OFFX_L register description
Offset for X-axis hard-iron compensation. Default value: 00000000
MAG_OFFX_H (2Eh)
Offset for X-axis hard-iron compensation register (r/w).The value is expressed as a 16-bit word in two’s complement.
Table 273. MAG_OFFX_H register
MAG_OFFX_H_7 MAG_OFFX_H_6 MAG_OFFX_H_5 MAG_OFFX_H_4 MAG_OFFX_H_3 MAG_OFFX_H_2 MAG_OFFX_H_1 MAG_OFFX_H_0
MAG_OFFX_H_[7:0]
Table 274. MAG_OFFX_H register description
Offset for X-axis hard-iron compensation. Default value: 00000000
DS12171 - Rev 3 page 95/116
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MAG_OFFY_L (2Fh)
12.25
MAG_OFFY_L (2Fh)
Offset for Y-axis hard-iron compensation register (r/w). The value is expressed as a 16-bit word in two’s complement.
Table 275. MAG_OFFY_L register
MAG_OFFY_L_7 MAG_OFFY_L_6 MAG_OFFY_L_5 MAG_OFFY_L_4 MAG_OFFY_L_3 MAG_OFFY_L_2 MAG_OFFY_L_1 MAG_OFFY_L_0
12.26
MAG_OFFY_L_[7:0]
Table 276. MAG_OFFY_L register description
Offset for Y-axis hard-iron compensation. Default value: 00000000
MAG_OFFY_H (30h)
Offset for Y-axis hard-iron compensation register (r/w). The value is expressed as a 16-bit word in two’s complement.
Table 277. MAG_OFFY_H register
MAG_OFFY_H_7 MAG_OFFY_H_6 MAG_OFFY_H_5 MAG_OFFY_H_4 MAG_OFFY_H_3 MAG_OFFY_H_2 MAG_OFFY_H_1 MAG_OFFY_H_0
12.27
MAG_OFFY_H_[7:0]
Table 278. MAG_OFFY_H register description
Offset for Y-axis hard-iron compensation. Default value: 00000000
MAG_OFFZ_L (31h)
Offset for Z-axis hard-iron compensation register (r/w). The value is expressed as a 16-bit word in two’s complement.
Table 279. MAG_OFFZ_L register
MAG_OFFZ_L_7 MAG_OFFZ_L_6 MAG_OFFZ_L_5 MAG_OFFZ_L_4 MAG_OFFZ_L_3 MAG_OFFZ_L_2 MAG_OFFZ_L_1 MAG_OFFZ_L_0
12.28
MAG_OFFZ_L_[7:0]
Table 280. MAG_OFFZ_L register description
Offset for Z-axis hard-iron compensation. Default value: 00000000
MAG_OFFZ_H (32h)
Offset for Z-axis hard-iron compensation register (r/w). The value is expressed as a 16-bit word in two’s complement.
Table 281. MAG_OFFZ_H register
MAG_OFFZ_H_7 MAG_OFFZ_H_6 MAG_OFFZ_H_5 MAG_OFFZ_H_4 MAG_OFFZ_H_3 MAG_OFFZ_H_2 MAG_OFFZ_H_1 MAG_OFFZ_H_0
MAG_OFFZ_H_[7:0]
Table 282. MAG_OFFZ_H register description
Offset for Z-axis hard-iron compensation. Default value: 00000000
DS12171 - Rev 3 page 96/116
13
Soldering information
The LGA package is compliant with the ECOPACK ® , RoHS and "Green" standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020.
Land pattern and soldering recommendations are available at www.st.com/mems.
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Soldering information
DS12171 - Rev 3 page 97/116
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Package information
14
14.1
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
. ECOPACK ® is an ST trademark.
LGA-14L package information
Figure 23. LGA-14L 2.5 x 3.0 x 0.86 mm package outline and mechanical data
Pin1 indicator
W H 0.5
Pin1 indicator
4x (0.1)
TOP VIEW
14x 0.25±0.05
1
BOTTOM VIEW
14x 0.475±0.05
ITEM
L e n g t
W i d t h h [
[ L ]
W ]
H e i g h t [ H ]
Dimensions are in millimeter unless otherwise specified
General tolerance is +/-0.1mm unless otherwise specified
OUTER DIMENSIONS
DIMENSION [mm]
2 .
3 .
0 .
5
0
8
0
0
6
TOLERANCE [mm]
±
±
M
0
0
A
.
.
1
1
X
DM00249496_1
DS12171 - Rev 3 page 98/116
14.2
LGA-14 packing information
Figure 24. Carrier tape information for LGA-14 package
ISM330DLC
LGA-14 packing information
Figure 25. LGA-14 package orientation in carrier tape
DS12171 - Rev 3 page 99/116
DS12171 - Rev 3
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LGA-14 packing information
A
Figure 26. Reel information for carrier tape of LGA-14 package
T
40mm min.
Access hole at slot location
B
C
D N
Full radius
G measured at hub
Tape slot in core for tape start
2.5mm min. width
Table 283. Reel dimensions for carrier tape of LGA-14 package
Reel dimensions (mm)
A (max)
B (min)
C
D (min)
N (min)
G
T (max)
330
1.5
13 ±0.25
20.2
60
12.4 +2/-0
18.4
page 100/116
Revision history
Date
15-Jun-2017
24-Nov-2017
13-Nov-2018
Revision
1
2
3
Table 284. Document revision history
Changes
Initial release
Updated Table 3: Mechanical characteristics
Updated footnote 1 of Table 41: FIFO ODR selection
Added product label indicating ST's 10-year longevity commitment
Added sensor resonant frequency to
Table 2. Mechanical characteristics
Updated bit 7 in Section 10.5 FIFO_CTRL2 (07h)
Updated bit 0 in Section 10.76 MD1_CFG (5Eh)
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Contents
Contents
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Contents
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Contents
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Contents
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Contents
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Contents
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Contents
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List of tables
List of tables
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List of tables
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List of tables
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List of tables
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List of tables
DS12171 - Rev 3 page 113/116
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List of tables
DS12171 - Rev 3 page 114/116
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List of figures
List of figures
DS12171 - Rev 3 page 115/116
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IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
DS12171 - Rev 3 page 116/116
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Key features
±2/±4/±8/±16 g full-scale acceleration range
±125/±250/±500/±1000/±2000 dps angular rate range
0.75 mA in high-performance, combo mode
Up to 4 kbyte of FIFO with dynamic allocation of significant data
Configurable signal processing path with low latency and low noise for control loop stability
Sensor hub feature for collecting data from up to 4 external sensors
Frequently asked questions
-40 °C to +85 °C
SPI & I²C serial interface with main processor data synchronization. Auxiliary SPI serial interface for independent, low-noise low-latency data output for gyroscope and accelerometer.
Plastic, land grid array (LGA) package (2.5 x 3.0 x 0.83 mm)
Yes, tilt detection, free-fall, wakeup, 6D/4D orientation, click and double-click supported
