STMicroelectronics STM32H750XB Datasheet

STM32H750VB STM32H750ZB
STM32H750IB STM32H750XB
32-bit Arm® Cortex®-M7 480MHz MCUs, 128 Kbyte Flash,
1 Mbyte RAM, 46 com. and analog interfaces, crypto
Datasheet - production data
Features
Includes ST state-of-the-art patented
technology
Core
• 32-bit Arm® Cortex®-M7 core with doubleprecision FPU and L1 cache: 16 Kbytes of data
and 16 Kbytes of instruction cache; frequency
up to 480 MHz, MPU, 1027 DMIPS/
2.14 DMIPS/MHz (Dhrystone 2.1), and DSP
instructions
Memories
• 128 Kbytes of Flash memory
• 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc.
64 Kbytes of ITCM RAM + 128 Kbytes of
DTCM RAM for time critical routines),
864 Kbytes of user SRAM, and 4 Kbytes of
SRAM in Backup domain
• Dual mode Quad-SPI memory interface
running up to 133 MHz
• Flexible external memory controller with up to
32-bit data bus:
– SRAM, PSRAM, NOR Flash memory
clocked up to 133 MHz in synchronous
mode
– SDRAM/LPSDR SDRAM
– 8/16-bit NAND Flash memories
• CRC calculation unit
• ROP, PC-ROP, active tamper, secure firmware
upgrade support, Secure access mode
General-purpose input/outputs
• Up to 168 I/O ports with interrupt capability
This is information on a product in full production.
TFBGA240+25
(14x14 mm)
UFBGA176+25
(10x10 mm)
Reset and power management
• 3 separate power domains which can be
independently clock-gated or switched off:
– D1: high-performance capabilities
– D2: communication peripherals and timers
– D3: reset/clock control/power management
• 1.62 to 3.6 V application supply and I/Os
• POR, PDR, PVD and BOR
• Dedicated USB power embedding a 3.3 V
internal regulator to supply the internal PHYs
• Embedded regulator (LDO) with configurable
scalable output to supply the digital circuitry
• Voltage scaling in Run and Stop mode (6
configurable ranges)
• Backup regulator (~0.9 V)
• Voltage reference for analog peripheral/VREF+
• Low-power modes: Sleep, Stop, Standby and
VBAT supporting battery charging
Low-power consumption
Security
February 2021
LQFP100
(14 x 14 mm)
LQFP144
(20 x 20 mm)
LQFP176
(24 x 24 mm)
• VBAT battery operating mode with charging
capability
• CPU and domain power state monitoring pins
• 2.95 µA in Standby mode (Backup SRAM OFF,
RTC/LSE ON)
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Clock management
• 2× operational amplifiers (7.3 MHz bandwidth)
• Internal oscillators: 64 MHz HSI, 48 MHz
HSI48, 4 MHz CSI, 32 kHz LSI
• 1× digital filters for sigma delta modulator
(DFSDM) with 8 channels/4 filters
• External oscillators: 4-48 MHz HSE,
32.768 kHz LSE
Graphics
• 3× PLLs (1 for the system clock, 2 for kernel
clocks) with Fractional mode
• LCD-TFT controller up to XGA resolution
Interconnect matrix
• Hardware JPEG Codec
•
3 bus matrices (1 AXI and 2 AHB)
•
Bridges (5× AHB2-APB, 2× AXI2-AHB)
• Chrom-ART graphical hardware Accelerator
(DMA2D) to reduce CPU load
Up to 22 timers and watchdogs
• 1× high-resolution timer (2.1 ns max
resolution)
4 DMA controllers to unload the CPU
• 1× high-speed master direct memory access
controller (MDMA) with linked list support
• 2× dual-port DMAs with FIFO
• 2× 32-bit timers with up to 4 IC/OC/PWM or
pulse counter and quadrature (incremental)
encoder input (up to 240 MHz)
• 1× basic DMA with request router capabilities
• 2× 16-bit advanced motor control timers (up to
240 MHz)
Up to 35 communication peripherals
• 10× 16-bit general-purpose timers (up to
240 MHz)
• 4× I2Cs FM+ interfaces (SMBus/PMBus)
• 4× USARTs/4x UARTs (ISO7816 interface,
LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART
• 5× 16-bit low-power timers (up to 240 MHz)
• 6× SPIs, 3 with muxed duplex I2S audio class
accuracy via internal audio PLL or external
clock, 1x I2S in LP domain (up to 150 MHz)
• 1× SysTick timer
• 4x SAIs (serial audio interface)
• 2× watchdogs (independent and window)
• RTC with sub-second accuracy and hardware
calendar
• SPDIFRX interface
Cryptographic acceleration
• SWPMI single-wire protocol master I/F
• AES 128, 192, 256, TDES,
• MDIO Slave interface
• HASH (MD5, SHA-1, SHA-2), HMAC
• 2× SD/SDIO/MMC interfaces (up to 125 MHz)
• True random number generators
• 2× CAN controllers: 2 with CAN FD, 1 with
time-triggered CAN (TT-CAN)
Debug mode
• 2× USB OTG interfaces (1FS, 1HS/FS) crystalless solution with LPM and BCD
• Ethernet MAC interface with DMA controller
• HDMI-CEC
• 8- to 14-bit camera interface (up to 80 MHz)
• SWD & JTAG interfaces
• 4-Kbyte Embedded Trace Buffer
96-bit unique ID
All packages are ECOPACK2 compliant
11 analog peripherals
• 3× ADCs with 16-bit max. resolution (up to 36
channels, up to 3.6 MSPS)
• 1× temperature sensor
• 2× 12-bit D/A converters (1 MHz)
• 2× ultra-low-power comparators
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Contents
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1
Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2
Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.1
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.2
Secure access mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.3
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.5
Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5.1
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.6
Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.7
Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.7.1
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.7.2
System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.8
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.9
Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.10
DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.11
Chrom-ART Accelerator (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.12
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 32
3.13
Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 32
3.14
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 32
3.15
Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.16
Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.17
Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.18
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.19
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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3.20
Digital-to-analog converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.21
Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.22
Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.23
Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 36
3.24
Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.25
LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.26
JPEG Codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.27
True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.28
Cryptographic acceleration (CRYP and HASH) . . . . . . . . . . . . . . . . . . . . 39
3.29
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.29.1
High-resolution timer (HRTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.29.2
Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.29.3
General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.29.4
Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.29.5
Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . 43
3.29.6
Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.29.7
Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.29.8
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.30
Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 44
3.31
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.32
Universal synchronous/asynchronous receiver transmitter (USART) . . . 45
3.33
Low-power universal asynchronous receiver transmitter (LPUART) . . . . 46
3.34
Serial peripheral interfaces (SPI)/integrated interchip
sound interfaces (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.35
Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.36
SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.37
Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 48
3.38
Management Data Input/Output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . 49
3.39
SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . . . 49
3.40
Controller area network (FDCAN1, FDCAN2) . . . . . . . . . . . . . . . . . . . . . 49
3.41
Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 50
3.42
Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . . 50
3.43
High-definition multimedia interface (HDMI)
- consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.44
Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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4
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6
Electrical characteristics (rev Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.3.2
VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.3.3
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 99
6.3.4
Embedded reset and power control block characteristics . . . . . . . . . . 100
6.3.5
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.3.6
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.3.7
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.3.8
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.3.9
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.3.10
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.3.11
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.3.12
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.3.13
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 127
6.3.14
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.3.15
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.16
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.3.17
FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.3.18
Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.3.19
Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
6.3.20
16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
6.3.21
DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
6.3.22
Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 168
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Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.3.24
Temperature and VBAT monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
6.3.25
Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
6.3.26
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
6.3.27
Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 173
6.3.28
Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 176
6.3.29
Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 178
6.3.30
LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 179
6.3.31
Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.3.32
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.3.33
JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Electrical characteristics (rev V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
7.1
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6.3.23
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
7.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
7.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
7.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
7.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
7.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
7.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
7.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 201
7.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
7.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
7.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
7.3.2
VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
7.3.3
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 205
7.3.4
Embedded reset and power control block characteristics . . . . . . . . . . 206
7.3.5
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
7.3.6
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
7.3.7
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 220
7.3.8
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 221
7.3.9
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 225
7.3.10
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
7.3.11
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
7.3.12
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
7.3.13
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 233
7.3.14
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
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7.3.15
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
7.3.16
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
7.3.17
FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
7.3.18
Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
7.3.19
Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
7.3.20
16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
7.3.21
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
7.3.22
Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 280
7.3.23
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
7.3.24
Temperature and VBAT monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
7.3.25
Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
7.3.26
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
7.3.27
Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 284
7.3.28
Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 286
7.3.29
Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 289
7.3.30
LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 290
7.3.31
Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
7.3.32
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
8.1
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
8.2
LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
8.3
LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
8.4
UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
8.5
TFBGA240+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
8.6
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
8.6.1
Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
9
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
DS12556 Rev 6
7/336
7
List of tables
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
8/336
STM32H750xB features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
System vs domain low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
STM32H750xB pin/ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Port A alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Port B alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Port C alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Port D alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Port E alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Port F alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Port G alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Port H alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Port I alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Port J alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Port K alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
VCAP operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 99
Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Typical and maximum current consumption in Run mode, code with data processing
running from ITCM, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache ON, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache OFF, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Typical consumption in Run mode and corresponding performance
versus code position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Typical current consumption batch acquisition mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 105
Typical and maximum current consumption in Stop mode, regulator ON. . . . . . . . . . . . . 106
Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . 106
Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 107
Peripheral current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Peripheral current consumption in Stop, Standby and VBAT mode . . . . . . . . . . . . . . . . . 114
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4-48 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
List of tables
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
PLL characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
PLL characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8 . . . . . . . . 131
Output voltage characteristics for PC13, PC14, PC15 and PI8 . . . . . . . . . . . . . . . . . . . . 132
Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 139
Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 139
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 140
Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 141
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 142
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 144
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 149
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 153
SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
QUADSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Dynamics characteristics: Delay Block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
DS12556 Rev 6
9/336
12
List of tables
Table 97.
Table 98.
Table 99.
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
Table 127.
Table 128.
Table 129.
Table 130.
Table 131.
Table 132.
Table 133.
Table 134.
Table 135.
Table 136.
Table 137.
Table 138.
Table 139.
Table 140.
Table 141.
Table 142.
10/336
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
DFSDM measured timing - 1.62-3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Dynamic characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V . . . . . . . . . . . . . 190
Dynamic characteristics: eMMC characteristics, VDD = 1.71 to 1.9 V . . . . . . . . . . . . . . . 191
USB OTG_FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 194
Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 195
Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 196
Dynamics JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Dynamics SWD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Supply voltage and maximum frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 204
VCAP operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 205
Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Typical and maximum current consumption in Run mode, code with data processing
running from ITCM, LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache ON,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache OFF,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Typical and maximum current consumption batch acquisition mode,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Typical and maximum current consumption in Stop, LDO regulator ON . . . . . . . . . . . . . 211
Typical and maximum current consumption in Sleep mode, LDO regulator . . . . . . . . . . 212
Typical and maximum current consumption in Standby . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 213
Peripheral current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
4-48 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 143.
Table 144.
Table 145.
Table 146.
Table 147.
Table 148.
Table 149.
Table 150.
Table 151.
Table 152.
Table 153.
Table 154.
Table 155.
Table 156.
Table 157.
Table 158.
Table 159.
Table 160.
Table 161.
Table 162.
Table 163.
Table 164.
Table 165.
Table 166.
Table 167.
Table 168.
Table 169.
Table 170.
Table 171.
Table 172.
Table 173.
Table 174.
Table 175.
Table 176.
Table 177.
Table 178.
Table 179.
Table 180.
Table 181.
Table 182.
Table 183.
Table 184.
Table 185.
Table 186.
Table 187.
Table 188.
Table 189.
Table 190.
Table 191.
Table 192.
Table 193.
Table 194.
List of tables
CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
PLL characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
PLL characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8 . . . . . . . . 237
Output voltage characteristics for PC13, PC14, PC15 and PI8 . . . . . . . . . . . . . . . . . . . . 238
Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 244
Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 244
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 246
Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 246
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 248
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 249
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 255
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 260
SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
LPSDR SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
QUADSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Delay Block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Minimum sampling time vs RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
DS12556 Rev 6
11/336
12
List of tables
Table 195.
Table 196.
Table 197.
Table 198.
Table 199.
Table 200.
Table 201.
Table 202.
Table 203.
Table 204.
Table 205.
Table 206.
Table 207.
Table 208.
Table 209.
Table 210.
Table 211.
Table 212.
Table 213.
Table 214.
Table 215.
Table 216.
Table 217.
Table 218.
Table 219.
Table 220.
Table 221.
Table 222.
Table 223.
12/336
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
DFSDM measured timing - 1.62-3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Dynamics characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V . . . . . . . . . . . . 303
Dynamics characteristics: eMMC characteristics VDD = 1.71V to 1.9V . . . . . . . . . . . . . . 304
Dynamics characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Dynamics characteristics: Ethernet MAC signals for SMI . . . . . . . . . . . . . . . . . . . . . . . . 307
Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 308
Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 308
Dynamics JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Dynamics SWD characteristics: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
LQPF100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
LQFP144 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
LQFP176 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
UFBGA176+25 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 324
TFBG240+25 ball package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
TFBGA240+25 recommended PCB design rules (0.8 mm pitch) . . . . . . . . . . . . . . . . . . . 328
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
STM32H750xB block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power-up/power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
STM32H750xB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
UFBGA176+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
TFBGA240+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 138
Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 140
Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 141
Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 143
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 149
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 152
NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 153
SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
ADC accuracy characteristics (example for 12-bit resolution) . . . . . . . . . . . . . . . . . . . . . 162
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 164
Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 164
12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
DS12556 Rev 6
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15
List of figures
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
Figure 86.
Figure 87.
Figure 88.
Figure 89.
Figure 90.
Figure 91.
Figure 92.
Figure 93.
Figure 94.
Figure 95.
Figure 96.
Figure 97.
Figure 98.
Figure 99.
Figure 100.
14/336
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 243
Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 245
Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 247
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 254
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 259
NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 260
SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
QUADSPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
ADC accuracy characteristics (example for 12-bit resolution) . . . . . . . . . . . . . . . . . . . . . 274
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 275
Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 275
12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
USART timing diagram in Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
USART timing diagram in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 101.
Figure 102.
Figure 103.
Figure 104.
Figure 105.
Figure 106.
Figure 107.
Figure 108.
Figure 109.
Figure 110.
Figure 111.
Figure 112.
Figure 113.
Figure 114.
Figure 115.
Figure 116.
Figure 117.
Figure 118.
Figure 119.
Figure 120.
Figure 121.
Figure 122.
Figure 123.
Figure 124.
Figure 125.
Figure 126.
Figure 127.
Figure 128.
Figure 129.
Figure 130.
List of figures
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
LQFP100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
LQFP144 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
LQFP144 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
LQFP176 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
LQFP176 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
LQFP176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
UFBGA176+25 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
UFBGA176+25 package recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
UFBGA176+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
TFBGA240+25 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
TFBGA240+25 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
TFBGA240+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
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Introduction
1
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Introduction
This document provides information on STM32H750xB microcontrollers, such as
description, functional overview, pin assignment and definition, electrical characteristics,
packaging, and ordering information.
This document should be read in conjunction with the STM32H750xB reference manual
(RM0433), available from the STMicroelectronics website www.st.com.
For information on the Arm®(a) Cortex®-M7 core, please refer to the Cortex®-M7 Technical
Reference Manual, available from the http://www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
2
Description
Description
STM32H750xB devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC
core operating at up to 480 MHz. The Cortex® -M7 core features a floating point unit (FPU)
which supports Arm® double-precision (IEEE 754 compliant) and single-precision dataprocessing instructions and data types. STM32H750xB devices support a full set of DSP
instructions and a memory protection unit (MPU) to enhance application security.
STM32H750xB devices incorporate high-speed embedded memories with a Flash memory
of 128 Kbytes, up to 1 Mbyte of RAM (including 192 Kbytes of TCM RAM, up to 864 Kbytes
of user SRAM and 4 Kbytes of backup SRAM), as well as an extensive range of enhanced
I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB bus matrix
and a multi layer AXI interconnect supporting internal and external memory access.
All the devices offer three ADCs, two DACs, two ultra-low power comparators, a low-power
RTC, a high-resolution timer, 12 general-purpose 16-bit timers, two PWM timers for motor
control, five low-power timers, a true random number generator (RNG), and a cryptographic
acceleration cell. The devices support four digital filters for external sigma-delta modulators
(DFSDM). They also feature standard and advanced communication interfaces.
•
Standard peripherals
–
•
Four I2Cs
–
Four USARTs, four UARTs and one LPUART
–
Six SPIs, three I2Ss in Half-duplex mode. To achieve audio class accuracy, the
I2S peripherals can be clocked by a dedicated internal audio PLL or by an external
clock to allow synchronization.
–
Four SAI serial audio interfaces
–
One SPDIFRX interface
–
One SWPMI (Single Wire Protocol Master Interface)
–
Management Data Input/Output (MDIO) slaves
–
Two SDMMC interfaces
–
A USB OTG full-speed and a USB OTG high-speed interface with full-speed
capability (with the ULPI)
–
One FDCAN plus one TT-FDCAN interface
–
An Ethernet interface
–
Chrom-ART Accelerator
–
HDMI-CEC
Advanced peripherals including
–
A flexible memory control (FMC) interface
–
A Quad-SPI Flash memory interface
–
A camera interface for CMOS sensors
–
An LCD-TFT display controller
–
A JPEG hardware compressor/decompressor
Refer to Table 1: STM32H750xB features and peripheral counts for the list of peripherals
available on each part number.
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52
Description
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
STM32H750xB devices operate in the –40 to +85 °C temperature range from a 1.62 to
3.6 V power supply. The supply voltage can drop down to 1.62 V by using an external power
supervisor (see Section 3.5.2: Power supply supervisor) and connecting the PDR_ON pin to
VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power
voltage detector enabled.
Dedicated supply inputs for USB (OTG_FS and OTG_HS) are available on all packages
except LQFP100 to allow a greater power supply choice.
A comprehensive set of power-saving modes allows the design of low-power applications.
STM32H750xB devices are offered in 3 packages ranging from 100 pins to 240 pins/balls.
The set of included peripherals changes with the device chosen.
These features make STM32H750xB microcontrollers suitable for a wide range of
applications:
•
Motor drive and application control
•
Medical equipment
•
Industrial applications: PLC, inverters, circuit breakers
•
Printers, and scanners
•
Alarm systems, video intercom, and HVAC
•
Home audio appliances
•
Mobile applications, Internet of Things
•
Wearable devices: smart watches.
Figure 1 shows the device block diagram.
Table 1. STM32H750xB features and peripheral counts
Peripherals
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Flash memory in Kbytes
128
SRAM in Kbytes
TCM RAM in
Kbytes
SRAM mapped onto AXI
bus
512
SRAM1 (D2 domain)
128
SRAM2 (D2 domain)
128
SRAM3 (D2 domain)
32
SRAM4 (D3 domain)
64
ITCM RAM (instruction)
64
DTCM RAM (data)
128
Backup SRAM (Kbytes)
4
FMC
Yes
General-purpose input/outputs
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82
114
140
Quad-SPI interface
Yes
Ethernet
Yes
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Description
Table 1. STM32H750xB features and peripheral counts (continued)
Peripherals
Timers
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
High-resolution
1
General-purpose
10
Advanced-control (PWM)
2
Basic
2
Low-power
5
Wakeup pins
Tamper pins
4
2
6
3
Random number generator
Yes
Cryptographic processor
Yes
SPI / I2S
6/3(1)
I2C
4
USART/UART/
LPUART
4/4
/1
SAI
4
SPDIFRX
4 inputs
SWPMI
Yes
MDIO
Yes
SDMMC
2
FDCAN/TT-FDCAN
1/1
USB OTG_FS
Yes
USB OTG_HS
Yes
Communication
interfaces
Ethernet and camera interface
Yes
LCD-TFT
Yes
JPEG Codec
Yes
Chrom-ART Accelerator (DMA2D)
Yes
16-bit ADCs
Number of Direct channels
Number of Fast channels
Number of Slow channels
3
2
3
11
2
9
17
2
9
21
12-bit DAC
Number of channels
Yes
2
Comparators
2
Operational amplifiers
2
DFSDM
Yes
Maximum CPU frequency
Operating voltage
4
9
23
480MHz
1.71 to 3.6 V(4)
DS12556 Rev 6
(2)(3)/400
MHz
1.62 to 3.6 V(5)
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52
Description
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 1. STM32H750xB features and peripheral counts (continued)
Peripherals
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Ambient temperatures: –40 up to +85 °C(6)
Operating temperatures
Package
Junction temperature: –40 to + 125 °C
LQFP100
LQFP144
LQFP176,
TFBGA240+25
UFBGA176+25
1. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio
mode.
2. The maximum CPU frequency of 480 MHz can be obtained on devices revision V.
3. The product junction temperature must be kept within the –40 to +105 °C temperature range.
4. Since the LQFP100 package does not feature the PDR_ON pin (tied internally to VDD), the minimum VDD value for this
package is 1.71 V.
5. VDD/VDDA can drop down to 1.62 V by using an external power supervisor (see Section 3.5.2: Power supply supervisor) and
connecting PDR_ON pin to VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power voltage
detector enabled.
6. The product junction temperature must be kept within the –40 to +125 °C temperature range.
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Description
Figure 1. STM32H750xB block diagram
MII / RMII
To APB1-2
peripherals
MDIO
as AF
AHB1
D-TCM
64KB
D-TCM
64KB
DMA1
AXIM
DMA/
FIFO
FIFO
D-Cache
16KB
512 KB AXI
SRAM
LCD-TFT
WWDG
FIFO
JPEG
FMC_signals
Quad-SPI
RNG
HASH
3DES/AES
SRAM1 SRAM2 SRAM3
128 KB 128 KB 32 KB
ADC1
32b
TIM6
16b
16b
TIM7
16b
16b
AHB/APB
SWPMI
FIFO
SDMMC1
32b
16b
Delay block
A P B 10 MHz
3
DAP
AHB4
SPI1/I2S1
TIM1/PWM
16b
16b
HSEM
CRC
ADC3
RX, TX as AF
UART7
RX, TX as AF
RX, TX as AF
SPI2/I2S2
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
SPI3/I2S3
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
SCL, SDA, SMBAL as AF
I2C2/SMBUS
I2C3/SMBUS
MDIOs
MDC, MDIO
TT-FDCAN1
FDCAN2
4 KB BKP
RAM
SPDIFRX1
LPTIM3
AHB/APB
VREF
I2C4
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
SPI6/I2S6
RX, TX, CK, CTS, RTS as AF
LPUART1
LPTIM2
LPTIM1
CEC as AF
DAC_OUT1, DAC_OUT2 as AF
16b
OPAMP1&2
@VDD33
VDD12 BBgen + POWER MNGT
PWRCTRL
RCC
Reset &
control
SAI4
LPTIM3_OUT as AF
TX, RX
TX, RX
IN[1:4] as AF
HDMI-CEC
COMP1&2
LPTIM4
SCL, SDA, SMBAL as AF
SCL, SDA, SMBAL as AF
USBCR
64 KB SRAM
GPIO PORTK
LPTIM5
RX, TX, SCK
CTS, RTS as AF
RX, TX as AF
DAC
GPIO PORTA.. J
RX, TX, SCK, CTS,
RTS as AF
UART5
I2C1/SMBUS
RAM
I/F
32-bit AHB BUS-MATRIX
AHB4 (200MHz)
smcard
irDA USART6
smcard
irDA USART1
TIM8/PWM
irDA
UART8
APB1 100 MHz (max)
10 KB SRAM
BDMA
AHB4
AHB4
DMA
Mux2
AHB4
SPI4
AHB4
TIM15
LPTIM4_OUT as AF
LPTIM2_IN1, LPTIM2_IN2 and
LPTIM2_OUT
APB2 100 MHz (max)
TIM17
TIM16
LPTIM5_OUT as AF
SCL, SDA, SMBAL as AF
FIFO FIFO FIFO
SPI5
Voltage
regulator
3.3 to 1.2V
LPTIM1_IN1, LPTIM1_IN2,
LPTIM1_OUT as AF
OPAMPx_VINM
OPAMPx_VINP
OPAMPx_VOUT as AF
VDDMMC33 = 1.8 to 3.6V
VDDUSB33 = 3.0 to 3.6 V
VDD = 1.8 to 3.6 V
VSS
VCAP
@VSW
SYSCFG
XTAL 32 kHz
LS
EXTI WKUP
IWDG
Temperature
sensor
@VDD
CSI
HSI48
HSI
LSI
HS RC
LS RC
RTC
Backup registers
LS
SD, SCK, FS, MCLK,
D[3;1], CK[2:1] as AF
COMPx_INP, COMPx_INM,
COMPx_OUT as AF
irDA
UART4
AHB4 (200MHz)
PK[7:0]
1 channel as AF
USART3
APB4
MHz
(max)
APB4
100100
MHz
(max)
PA..J[15:0]
1 channel as AF
smcard
AHB4
4 compl. chan. (TIM1_CH1[1:4]N),
4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF
4 compl. chan.(TIM8_CH1[1:4]N),
4 chan. (TIM8_CH1[1:4], ETR,
BKIN as AF
Up to 17 analog inputs
common to ADC1 and 2
2 channels as AF
TIM13
FIFO
RX, TX, SCK, CTS, RTS as AF
4 channels
TIM12
USART2
APB4 100 MHz (max)
RX, TX, SCK, CTS, RTS as AF
4 channels, ETR as AF
TIM5
Digital filter
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
4 channels, ETR as AF
TIM4
AHB/APB
SAI3
SAI1
MOSI, MISO, SCK, NSS as AF
4 channels, ETR as AF
TIM14
16b
DFSDM1
SD, SCK, FS, MCLK, D[3:1],
CK[2:1] as AF
2 compl. chan.(TIM15_CH1[1:2]N),
2 chan. (TIM_CH15[1:2], BKIN as AF
TIM2
TIM3
smcard
SAI2
1 compl. chan.(TIM17_CH1N),
1 chan. (TIM17_CH1, BKIN as AF
1 compl. chan.(TIM16_CH1N),
1 chan. (TIM16_CH1, BKIN as AF
16b
HRTIM1
SD, SCK, FS, MCLK, CK[2:1] as AF
MOSI, MISO, SCK, NSS as AF
AHB2 (200MHz)
DCMI
Up to 20 analog inputs
common to ADC1 & 2
ADC2
AHB/APB
CLK, CS,D[7:0]
AXI/AHB34 (200MHz)
AHB3
LCD_R[7:0], LCD_G[7:0],
LCD_B[7:0], LCD_HSYNC,
LCD_VSYNC, LCD_DE, LCD_CLK
FIFO
DMA
Mux1
FMC
64-bit AXI BUS-MATRIX
16 Streams
FIFO
CHROM-ART
(DMA2D)
HRTIM1_CH[A..E]x
HRTIM1_FLT[5:1],
HRTIM1_FLT[5:1]_in, SYSFLT
DFSDM1_CKOUT,
DFSDM1_DATAIN[0:7],
DFSDM1_CKIN[0:7]
SD, SCK, FS, MCLK, D/CK[4:1] as
AF
DMA/
FIFO
32-bit AHB BUS-MATRIX
I-Cache
16KB
AHBS
HSYNC, VSYNC, PIXCLK, D[13:0]
PHY
OTG_FS
128 KB
FLASH
ETM
MDMA
SDMMC_D[7:0],SDMMC_D[7:3,1]Dir
SDMMC_D0dir, SDMMC_D2dir
CMD, CMDdir, CK, Ckin,
CKio as AF
DMA/
FIFO
8 Stream 8 Stream
FIFOs
FIFOs
AXI/AHB12 (200MHz)
AHB2 (200MHz)
TRACECK
TRACED[3:0]
PHY
ETHER
SDMMC2 OTG_HS
MAC
AHBP
Arm CPU
Cortex-M7
480 MHz
JTAG/SW
AHB4 (200MHz)
JTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
DMA2
(200MHz)
AHB1 (200MHz)
I-TCM
64KB
DP, DM, STP,
SDMMC_
NXT,ULPI:CK DP, DM, ID,
D[7:0],
VBUS
, D[7:0], DIR,
CMD, CK as AF
ID, VBUS
AWU
OSC32_IN
OSC32_OUT
RTC_TS
RTC_TAMP[1:3]
RTC_OUT
RTC_REFIN
VBAT = 1.8 to 3.6 V
@VDD
XTAL OSC
4- 48 MHz
PLL1+PLL2+PLL3
OSC_IN
OSC_OUT
WDG_LS_D1
@VDD
POR
reset
Int
SUPPLY SUPERVISION
POR/PDR/BOR
PVD
VDDA, VSSA
NRESET
WKUP[5:0]
MSv50638V4
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52
Functional overview
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
3
Functional overview
3.1
Arm® Cortex®-M7 with FPU
The Arm® Cortex®-M7 with double-precision FPU processor is the latest generation of Arm
processors for embedded systems. It was developed to provide a low-cost platform that
meets the needs of MCU implementation, with a reduced pin count and optimized power
consumption, while delivering outstanding computational performance and low interrupt
latency.
The Cortex®-M7 processor is a highly efficient high-performance featuring:
•
Six-stage dual-issue pipeline
•
Dynamic branch prediction
•
Harvard architecture with L1 caches (16 Kbytes of I-cache and 16 Kbytes of D-cache)
•
64-bit AXI interface
•
64-bit ITCM interface
•
2x32-bit DTCM interfaces
The following memory interfaces are supported:
•
Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency
•
Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM
accesses
•
AXI Bus interface to optimize Burst transfers
•
Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
It also supports single and double precision FPU (floating point unit) speeds up software
development by using metalanguage development tools, while avoiding saturation.
Figure 1 shows the general block diagram of the STM32H750xB family.
Note:
Cortex®-M7 with FPU core is binary compatible with the Cortex®-M4 core.
3.2
Memory protection unit (MPU)
The memory protection unit (MPU) manages the CPU access rights and the attributes of the
system resources. It has to be programmed and enabled before use. Its main purposes are
to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by
a privileged task, but also to protect data processes or read-protect memory regions.
The MPU defines access rules for privileged accesses and user program accesses. It
allows defining up to 16 protected regions that can in turn be divided into up to 8
independent subregions, where region address, size, and attributes can be configured. The
protection area ranges from 32 bytes to 4 Gbytes of addressable memory.
When an unauthorized access is performed, a memory management exception is
generated.
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3.3
Memories
3.3.1
Embedded Flash memory
Functional overview
The STM32H750xB devices embed 128 Kbytes of Flash memory that can be used for
storing programs and data.
The Flash memory is organized as follows:
3.3.2
•
128 Kbytes of user Flash memory containing 128 Kbytes of System Flash memory
from which the device can boot
•
2 Kbytes (64 Flash words) of user option bytes for user configuration
Secure access mode
In addition to other typical memory protection mechanism (RDP, PCROP), STM32H750xB
devices introduce the Secure access mode, a new enhanced security feature. This mode
allows developing user-defined secure services by ensuring, on the one hand code and
data protection and on the other hand code safe execution.
Two types of secure services are available:
•
STMicroelectronics Root Secure Services:
These services are embedded in System memory. They provide a secure solution for
firmware and third-party modules installation. These services rely on cryptographic
algorithms based on a device unique private key.
•
User-defined secure services:
These services are embedded in user Flash memory. Examples of user secure
services are proprietary user firmware update solution, secure Flash integrity check or
any other sensitive applications that require a high level of protection.
The secure firmware is embedded in specific user Flash memory areas configured
through option bytes.
Secure services are executed just after a reset and preempt all other applications to
guarantee protected and safe execution. Once executed, the corresponding code and data
are no more accessible.
The above secure services are available only for Cortex®-M7 core operating in Secure
access mode. The other masters cannot access the option bytes involved in Secure access
mode settings or the Flash secured areas.
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Functional overview
3.3.3
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Embedded SRAM
All devices feature:
•
512 Kbytes of AXI-SRAM mapped onto AXI bus on D1 domain.
•
SRAM1 mapped on D2 domain: 128 Kbytes
•
SRAM2 mapped on D2 domain: 128 Kbytes
•
SRAM3 mapped on D2 domain: 32 Kbytes
•
SRAM4 mapped on D3 domain: 64 Kbytes
•
4 Kbytes of backup SRAM
The content of this area is protected against possible unwanted write accesses,
and is retained in Standby or VBAT mode.
•
RAM mapped to TCM interface (ITCM and DTCM):
Both ITCM and DTCM RAMs are 0 wait state memories. either They can be accessed
either from the CPU or the MDMA (even in Sleep mode) through a specific AHB slave
of the CPU(AHBP):
–
64 Kbytes of ITCM-RAM (instruction RAM)
This RAM is connected to ITCM 64-bit interface designed for execution of critical
real-times routines by the CPU.
–
128 Kbytes of DTCM-RAM (2x 64-Kbyte DTCM-RAMs on 2x32-bit DTCM ports)
The DTCM-RAM could be used for critical real-time data, such as interrupt service
routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for
load/store operations) thanks to the Cortex®-M7 dual issue capability.
The MDMA can be used to load code or data in ITCM or DTCM RAMs.
Error code correction (ECC)
Over the product lifetime, and/or due to external events such as radiations, invalid bits in
memories may occur. They can be detected and corrected by ECC. This is an expected
behavior that has to be managed at final-application software level in order to ensure data
integrity through ECC algorithms implementation.
SRAM data are protected by ECC:
•
7 ECC bits are added per 32-bit word.
•
8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM.
The ECC mechanism is based on the SECDED algorithm. It supports single-error correction
and double-error detection.
3.4
Boot modes
At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option
bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF
which includes:
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•
All Flash address space
•
All RAM address space: ITCM, DTCM RAMs and SRAMs
•
The System memory bootloader
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Functional overview
The boot loader is located in non-user System memory. It is used to reprogram the Flash
memory through a serial interface (USART, I2C, SPI, USB-DFU). Refer to STM32
microcontroller System memory Boot mode application note (AN2606) for details.
3.5
Power supply management
3.5.1
Power supply scheme
STM32H750xB power supply voltages are the following:
•
VDD = 1.62 to 3.6 V: external power supply for I/Os, provided externally through VDD
pins.
•
VDDLDO = 1.62 to 3.6 V: supply voltage for the internal regulator supplying VCORE
•
VDDA = 1.62 to 3.6 V: external analog power supplies for ADC, DAC, COMP and
OPAMP.
•
VDD33USB and VDD50USB:
VDD50USB can be supplied through the USB cable to generate the VDD33USB via the
USB internal regulator. This allows supporting a VDD supply different from 3.3 V.
The USB regulator can be bypassed to supply directly VDD33USB if VDD = 3.3 V.
•
VBAT = 1.2 to 3.6 V: power supply for the VSW domain when VDD is not present.
•
VCAP: VCORE supply voltage, which values depend on voltage scaling (1.0 V, 1.1 V,
1.2 V or 1.35 V). They are configured through VOS bits in PWR_D3CR register and
ODEN bit in the SYSCFG_PWRCR register. The VCORE domain is split into the
following power domains that can be independently switch off.
–
D1 domain containing some peripherals and the Cortex®-M7 core.
–
D2 domain containing a large part of the peripherals.
–
D3 domain containing some peripherals and the system control.
During power-up and power-down phases, the following power sequence requirements
must be respected (see Figure 2):
•
When VDD is below 1 V, other power supplies (VDDA, VDD33USB, VDD50USB) must
remain below VDD + 300 mV.
•
When VDD is above 1 V, all power supplies are independent.
During the power-down phase, VDD can temporarily become lower than other supplies only
if the energy provided to the microcontroller remains below 1 mJ. This allows external
decoupling capacitors to be discharged with different time constants during the power-down
transient phase.
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Functional overview
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 2. Power-up/power-down sequence
V
3.6
VDDX(1)
VDD
VBOR0
1
0.3
Power-on
Invalid supply area
Operating mode
VDDX < VDD + 300 mV
Power-down
time
VDDX independent from VDD
MSv47490V1
1. VDDx refers to any power supply among VDDA, VDD33USB, VDD50USB.
3.5.2
Power supply supervisor
The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry:
•
Power-on reset (POR)
The POR supervisor monitors VDD power supply and compares it to a fixed threshold.
The devices remain in Reset mode when VDD is below this threshold,
•
Power-down reset (PDR)
The PDR supervisor monitors VDD power supply. A reset is generated when VDD drops
below a fixed threshold.
The PDR supervisor can be enabled/disabled through PDR_ON pin.
•
Brownout reset (BOR)
The BOR supervisor monitors VDD power supply. Three BOR thresholds (from 2.1 to
2.7 V) can be configured through option bytes. A reset is generated when VDD drops
below this threshold.
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3.5.3
Functional overview
Voltage regulator
The same voltage regulator supplies the 3 power domains (D1, D2 and D3). D1 and D2 can
be independently switched off.
Voltage regulator output can be adjusted according to application needs through 6 power
supply levels:
•
•
Run mode (VOS0 to VOS3)
–
Scale 0: boosted performance (available only with LDO regulator)
–
Scale 1: high performance
–
Scale 2: medium performance and consumption
–
Scale 3: optimized performance and low-power consumption
Stop mode (SVOS3 to SVOS5)
–
Scale 3: peripheral with wakeup from Stop mode capabilities (UART, SPI, I2C,
LPTIM) are operational
–
Scale 4 and 5 where the peripheral with wakeup from Stop mode is disabled
The peripheral functionality is disabled but wakeup from Stop mode is possible
through GPIO or asynchronous interrupt.
3.6
Low-power strategy
There are several ways to reduce power consumption on STM32H750xB:
•
Decrease the dynamic power consumption by slowing down the system clocks even in
Run mode and by individually clock gating the peripherals that are not used.
•
Save power consumption when the CPU is idle, by selecting among the available lowpower mode according to the user application needs. This allows achieving the best
compromise between short startup time, low-power consumption, as well as available
wakeup sources.
The devices feature several low-power modes:
•
CSleep (CPU clock stopped)
•
CStop (CPU sub-system clock stopped)
•
DStop (Domain bus matrix clock stopped)
•
Stop (System clock stopped)
•
DStandby (Domain powered down)
•
Standby (System powered down)
CSleep and CStop low-power modes are entered by the MCU when executing the WFI
(Wait for Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of
the Cortex®-Mx core is set after returning from an interrupt service routine.
A domain can enter low-power mode (DStop or DStandby) when the processor, its
subsystem and the peripherals allocated in the domain enter low-power mode.
If part of the domain is not in low-power mode, the domain remains in the current mode.
Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared
and the power domains are in DStop or DStandby mode.
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Table 2. System vs domain low-power mode
D1 domain power
mode
System power mode
Run
3.7
D2 domain power
mode
D3 domain power
mode
DRun/DStop/DStandby DRun/DStop/DStandby
DRun
Stop
DStop/DStandby
DStop/DStandby
DStop
Standby
DStandby
DStandby
DStandby
Reset and clock controller (RCC)
The clock and reset controller is located in D3 domain. The RCC manages the generation of
all the clocks, as well as the clock gating and the control of the system and peripheral
resets. It provides a high flexibility in the choice of clock sources and allows to apply clock
ratios to improve the power consumption. In addition, on some communication peripherals
that are capable to work with two different clock domains (either a bus interface clock or a
kernel peripheral clock), the system frequency can be changed without modifying the
baudrate.
3.7.1
Clock management
The devices embed four internal oscillators, two oscillators with external crystal or
resonator, two internal oscillators with fast startup time and three PLLs.
The RCC receives the following clock source inputs:
•
•
Internal oscillators:
–
64 MHz HSI clock
–
48 MHz RC oscillator
–
4 MHz CSI clock
–
32 kHz LSI clock
External oscillators:
–
HSE clock: 4-50 MHz (generated from an external source) or 4-48 MHz(generated
from a crystal/ceramic resonator)
–
LSE clock: 32.768 kHz
The RCC provides three PLLs: one for system clock, two for kernel clocks.
The system starts on the HSI clock. The user application can then select the clock
configuration.
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3.7.2
Functional overview
System reset sources
Power-on reset initializes all registers while system reset reinitializes the system except for
the debug, part of the RCC and power controller status registers, as well as the backup
power domain.
A system reset is generated in the following cases:
•
3.8
Power-on reset (pwr_por_rst)
•
Brownout reset
•
Low level on NRST pin (external reset)
•
Window watchdog
•
Independent watchdog
•
Software reset
•
Low-power mode security reset
•
Exit from Standby
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
After reset, all GPIOs (except debug pins) are in Analog mode to reduce power
consumption (refer to GPIOs register reset values in the device reference manual).
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
3.9
Bus-interconnect matrix
The devices feature an AXI bus matrix, two AHB bus matrices and bus bridges that allow
interconnecting bus masters with bus slaves (see Figure 3).
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Functional overview
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Figure 3. STM32H750xB bus matrix
AHBS
CPU
ITCM
64 Kbyte
MDMA
DMA2D
DMA1_MEM
SDMMC1
LTDC
D1-to-D2 AHB
DMA2
DMA2_MEM
DMA1
Ethernet
SDMMC2 USBHS1
MAC
USBHS2
DMA2_PERIPH
DTCM
128 Kbyte
AHBP
AXIM
I$
D$
16KB 16KB
DMA1_PERIPH
Cortex-M7
APB3
SRAM1 128
Kbyte
AHB3
SRAM2 128
Kbyte
DS12556 Rev 6
AHB1
AHB2
AXI SRAM
512 Kbyte
APB1
QSPI
APB2
FMC
64-bit AXI bus matrix
D1 domain
32-bit AHB bus matrix
D2 domain
D2-to-D1 AHB
D2-to-D3 AHB
D1-to-D3 AHB
BDMA
32-bit AHB bus matrix
D3 domain
Legend
32-bit bus
AHB4
TCM AHB
AXI
APB
64-bit bus
Master interface
Bus multiplexer
Slave interface
APB4
SRAM4
64 Kbyte
Backup
SRAM
4 Kbyte
MSv50639V2
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
SRAM3
32 Kbyte
Flash
memory
128 Kbytes
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
3.10
Functional overview
DMA controllers
The devices feature four DMA instances to unload CPU activity:
•
A master direct memory access (MDMA)
The MDMA is a high-speed DMA controller, which is in charge of all types of memory
transfers (peripheral to memory, memory to memory, memory to peripheral), without
any CPU action. It features a master AXI interface and a dedicated AHB interface to
access Cortex®-M7 TCM memories.
The MDMA is located in D1 domain. It is able to interface with the other DMA
controllers located in D2 domain to extend the standard DMA capabilities, or can
manage peripheral DMA requests directly.
Each of the 16 channels can perform single block transfers, repeated block transfers
and linked list transfers.
•
Two dual-port DMAs (DMA1, DMA2) located in D2 domain, with FIFO and request
router capabilities.
•
One basic DMA (BDMA) located in D3 domain, with request router capabilities.
The DMA request router could be considered as an extension of the DMA controller. It
routes the DMA peripheral requests to the DMA controller itself. This allowing managing the
DMA requests with a high flexibility, maximizing the number of DMA requests that run
concurrently, as well as generating DMA requests from peripheral output trigger or DMA
event.
3.11
Chrom-ART Accelerator (DMA2D)
The Chrom-Art Accelerator (DMA2D) is a graphical accelerator which offers advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
•
Rectangle filling with a fixed color
•
Rectangle copy
•
Rectangle copy with pixel format conversion
•
Rectangle composition with blending and pixel format conversion
Various image format coding are supported, from indirect 4bpp color mode up to 32bpp
direct color. It embeds dedicated memory to store color lookup tables. The DMA2D also
supports block based YCbCr to handle JPEG decoder output.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
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Functional overview
3.12
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller which is able to manage 16
priority levels, and handle up to 150 maskable interrupt channels plus the 16 interrupt lines
of the Cortex®-M7 with FPU core.
•
Closely coupled NVIC gives low-latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Allows early processing of interrupts
•
Processing of late arriving, higher-priority interrupts
•
Support tail chaining
•
Processor context automatically saved on interrupt entry, and restored on interrupt exit
with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.13
Extended interrupt and event controller (EXTI)
The EXTI controller performs interrupt and event management. In addition, it can wake up
the processor, power domains and/or D3 domain from Stop mode.
The EXTI handles up to 89 independent event/interrupt lines split as 28 configurable events
and 61 direct events .
Configurable events have dedicated pending flags, active edge selection, and software
trigger capable.
Direct events provide interrupts or events from peripherals having a status flag.
3.14
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
programmable polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
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3.15
Functional overview
Flexible memory controller (FMC)
The FMC controller main features are the following:
•
Interface with static-memory mapped devices including:
–
3.16
Static random access memory (SRAM)
–
NOR Flash memory/OneNAND Flash memory
–
PSRAM (4 memory banks)
–
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
•
Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
•
8-,16-,32-bit data bus width
•
Independent Chip Select control for each memory bank
•
Independent configuration for each memory bank
•
Write FIFO
•
Read FIFO for SDRAM controller
•
The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is the
FMC kernel clock divided by 2.
Quad-SPI memory interface (QUADSPI)
All devices embed a Quad-SPI memory interface, which is a specialized communication
interface targeting Single, Dual or Quad-SPI Flash memories. It supports both single and
double datarate operations.
It can operate in any of the following modes:
•
Direct mode through registers
•
External Flash status register polling mode
•
Memory mapped mode.
Up to 256 Mbytes of external Flash memory can be mapped, and 8-, 16- and 32-bit data
accesses are supported as well as code execution.
The opcode and the frame format are fully programmable.
3.17
Analog-to-digital converters (ADCs)
The STM32H750xB devices embed three analog-to-digital converters, which resolution can
be configured to 16, 14, 12, 10 or 8 bits.
Each ADC shares up to 20 external channels, performing conversions in the Single-shot or
Scan mode. In Scan mode, automatic conversion is performed on a selected group of
analog inputs.
Additional logic functions embedded in the ADC interface allow:
•
Simultaneous sample and hold
•
Interleaved sample and hold
The ADC can be served by the DMA controller, thus allowing to automatically transfer ADC
converted values to a destination location without any software action.
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Functional overview
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
In addition, an analog watchdog feature can accurately monitor the converted voltage of
one, some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, HRTIM1 and LPTIM1 timer.
3.18
Temperature sensor
STM32H750xB devices embed a temperature sensor that generates a voltage (VTS) that
varies linearly with the temperature. This temperature sensor is internally connected to
ADC3_IN18. The conversion range is between 1.7 V and 3.6 V. It can measure the device
junction temperature ranging from − 40 up to +125 °C.
The temperature sensor have a good linearity, but it has to be calibrated to obtain a good
overall accuracy of the temperature measurement. As the temperature sensor offset varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only. To improve the accuracy of
the temperature sensor measurement, each device is individually factory-calibrated by ST.
The temperature sensor factory calibration data are stored by ST in the System memory
area, which is accessible in Read-only mode.
3.19
VBAT operation
The VBAT power domain contains the RTC, the backup registers and the backup SRAM.
To optimize battery duration, this power domain is supplied by VDD when available or by the
voltage applied on VBAT pin (when VDD supply is not present). VBAT power is switched
when the PDR detects that VDD dropped below the PDR level.
The voltage on the VBAT pin could be provided by an external battery, a supercapacitor or
directly by VDD, in which case, the VBAT mode is not functional.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
Note:
When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
When PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no
more available and VBAT pin should be connected to VDD.
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
3.20
Functional overview
Digital-to-analog converters (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
•
two DAC converters: one for each output channel
•
8-bit or 12-bit monotonic output
•
left or right data alignment in 12-bit mode
•
synchronized update capability
•
noise-wave generation
•
triangular-wave generation
•
dual DAC channel independent or simultaneous conversions
•
DMA capability for each channel including DMA underrun error detection
•
external triggers for conversion
•
input voltage reference VREF+ or internal VREFBUF reference.
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA streams.
3.21
Ultra-low-power comparators (COMP)
STM32H750xB devices embed two rail-to-rail comparators (COMP1 and COMP2). They
feature programmable reference voltage (internal or external), hysteresis and speed (low
speed for low-power) as well as selectable output polarity.
The reference voltage can be one of the following:
•
An external I/O
•
A DAC output channel
•
An internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers,
and be combined into a window comparator.
3.22
Operational amplifiers (OPAMP)
STM32H750xB devices embed two rail-to-rail operational amplifiers (OPAMP1 and
OPAMP2) with external or internal follower routing and PGA capability.
The operational amplifier main features are:
•
PGA with a non-inverting gain ranging of 2, 4, 8 or 16 or inverting gain ranging of -1, -3,
-7 or -15
•
One positive input connected to DAC
•
Output connected to internal ADC
•
Low input bias current down to 1 nA
•
Low input offset voltage down to 1.5 mV
•
Gain bandwidth up to 7.3 MHz
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52
Functional overview
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
The devices embeds two operational amplifiers (OPAMP1 and OPAMP2) with two inputs
and one output each. These three I/Os can be connected to the external pins, thus enabling
any type of external interconnections. The operational amplifiers can be configured
internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 16 or with
inverting gain ranging from -1 to -15.
3.23
Digital filter for sigma-delta modulators (DFSDM)
The devices embed one DFSDM with 4 digital filters modules and 8 external input serial
channels (transceivers) or alternately 8 internal parallel inputs support.
The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse
Density Modulation) microphones and perform PDM to PCM conversion and filtering in
hardware. DFSDM features optional parallel data stream inputs from internal ADC
peripherals or microcontroller memory (through DMA/CPU transfers into DFSDM).
DFSDM transceivers support several serial interface formats (to support various Σ∆
modulators). DFSDM digital filter modules perform digital processing according user
selected filter parameters with up to 24-bit final ADC resolution.
The DFSDM peripheral supports:
•
•
8 multiplexed input digital serial channels:
–
configurable SPI interface to connect various SD modulator(s)
–
configurable Manchester coded 1 wire interface support
–
PDM (Pulse Density Modulation) microphone input support
–
maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
–
clock output for SD modulator(s): 0..20 MHz
alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution):
–
•
–
Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
–
integrator: oversampling ratio (1..256)
•
up to 24-bit output data resolution, signed output data format
•
automatic data offset correction (offset stored in register by user)
•
continuous or single conversion
•
start-of-conversion triggered by:
•
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internal sources: ADC data or memory data streams (DMA)
4 digital filter modules with adjustable digital signal processing:
–
software trigger
–
internal timers
–
external events
–
start-of-conversion synchronously with first digital filter module (DFSDM0)
analog watchdog feature:
–
low value and high value data threshold registers
–
dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
–
input from final output data or from selected input digital serial channels
–
continuous monitoring independently from standard conversion
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
•
Functional overview
short circuit detector to detect saturated analog input values (bottom and top range):
–
up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream
–
monitoring continuously each input serial channel
•
break signal generation on analog watchdog event or on short circuit detector event
•
extremes detector:
–
storage of minimum and maximum values of final conversion data
–
refreshed by software
•
DMA capability to read the final conversion data
•
interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial
channel clock absence
•
“regular” or “injected” conversions:
–
“regular” conversions can be requested at any time or even in Continuous mode
without having any impact on the timing of “injected” conversions
–
“injected” conversions for precise timing and with high conversion priority
Table 3. DFSDM implementation
DFSDM features
3.24
DFSDM1
Number of filters
4
Number of input
transceivers/channels
8
Internal ADC parallel input
X
Number of external triggers
16
Regular channel information in
identification register
X
Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can achieve a data transfer rate up to 140 Mbyte/s using a 80 MHz pixel clock. It
features:
•
Programmable polarity for the input pixel clock and synchronization signals
•
Parallel data communication can be 8-, 10-, 12- or 14-bit
•
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
•
Supports Continuous mode or Snapshot (a single frame) mode
•
Capability to automatically crop the image
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52
Functional overview
3.25
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
LCD-TFT controller
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024x768) resolution with the following features:
3.26
•
2 display layers with dedicated FIFO (64x64-bit)
•
Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
•
Up to 8 input color formats selectable per layer
•
Flexible blending between two layers using alpha value (per pixel or constant)
•
Flexible programmable parameters for each layer
•
Color keying (transparency color)
•
Up to 4 programmable interrupt events
•
AXI master interface with burst of 16 words
JPEG Codec (JPEG)
The JPEG Codec can encode and decode a JPEG stream as defined in the ISO/IEC 109181 specification. It provides an fast and simple hardware compressor and decompressor of
JPEG images with full management of JPEG headers.
The JPEG codec main features are as follows:
3.27
•
8-bit/channel pixel depths
•
Single clock per pixel encoding and decoding
•
Support for JPEG header generation and parsing
•
Up to four programmable quantization tables
•
Fully programmable Huffman tables (two AC and two DC)
•
Fully programmable minimum coded unit (MCU)
•
Encode/decode support (non simultaneous)
•
Single clock Huffman coding and decoding
•
Two-channel interface: Pixel/Compress In, Pixel/Compressed Out
•
Support for single greyscale component
•
Ability to enable/disable header processing
•
Fully synchronous design
•
Configuration for High-speed decode mode
True random number generator (RNG)
The RNG is a true random number generator that provides full entropy outputs to the
application as 32-bit samples. It is composed of a live entropy source (analog) and an
internal conditioning component.
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
3.28
Functional overview
Cryptographic acceleration (CRYP and HASH)
The devices embed a cryptographic processor that supports the advanced cryptographic
algorithms usually required to ensure confidentiality, authentication, data integrity and nonrepudiation when exchanging messages with a peer:
•
•
Encryption/Decryption
–
DES/TDES (data encryption standard/triple data encryption standard): ECB
(electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64-,
128- or 192-bit key
–
AES (advanced encryption standard): ECB, CBC, GCM, CCM, and CTR (Counter
mode) chaining algorithms, 128, 192 or 256-bit key
Universal HASH
–
SHA-1 and SHA-2 (secure HASH algorithms)
–
MD5
–
HMAC
The cryptographic accelerator supports DMA request generation.
3.29
Timers and watchdogs
The devices include one high-resolution timer, two advanced-control timers, ten generalpurpose timers, two basic timers, five low-power timers, two watchdogs and a SysTick timer.
All timer counters can be frozen in Debug mode.
Table 4 compares the features of the advanced-control, general-purpose and basic timers.
Table 4. Timer feature comparison
Timer
type
Timer
Highresolution HRTIM1
timer
Advanced
-control
TIM1,
TIM8
DMA
Capture/
Counter Counter Prescaler
request
compare
resolution
type
factor
generation channels
16-bit
16-bit
Complementary
output
Max
interface
clock
(MHz)
Max
timer
clock
(MHz)
(1)
/1 /2 /4
(x2 x4 x8
x16 x32,
with DLL)
Yes
10
Yes
480
480
Any
Up,
integer
Down, between 1
Up/down
and
65536
Yes
4
Yes
120
240
Up
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52
Functional overview
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 4. Timer feature comparison (continued)
Timer
type
Timer
TIM2,
TIM5
TIM3,
TIM4
TIM12
DMA
Capture/
Counter Counter Prescaler
request
compare
resolution
type
factor
generation channels
TIM15
TIM16,
TIM17
Max
interface
clock
(MHz)
Max
timer
clock
(MHz)
32-bit
Yes
4
No
120
240
16-bit
Any
Up,
integer
Down, between 1
Up/down
and
65536
Yes
4
No
120
240
16-bit
Up
Any
integer
between 1
and
65536
No
2
No
120
240
Up
Any
integer
between 1
and
65536
No
1
No
120
240
Up
Any
integer
between 1
and
65536
Yes
2
1
120
240
Up
Any
integer
between 1
and
65536
Yes
1
1
120
240
Yes
0
No
120
240
No
0
No
120
240
16-bit
16-bit
16-bit
Basic
TIM6,
TIM7
16-bit
Up
Any
integer
between 1
and
65536
Lowpower
timer
LPTIM1,
LPTIM2,
LPTIM3,
LPTIM4,
LPTIM5
16-bit
Up
1, 2, 4, 8,
16, 32, 64,
128
1. The maximum timer clock is up to 480 MHz depending on TIMPRE bit in the RCC_CFGR register and D2PRE1/2 bits in
RCC_D2CFGR register.
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(1)
Any
Up,
integer
Down, between 1
Up/down
and
65536
General
purpose
TIM13,
TIM14
Complementary
output
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
3.29.1
Functional overview
High-resolution timer (HRTIM1)
The high-resolution timer (HRTIM1) allows generating digital signals with high-accuracy
timings, such as PWM or phase-shifted pulses.
It consists of 6 timers, 1 master and 5 slaves, totaling 10 high-resolution outputs, which can
be coupled by pairs for deadtime insertion. It also features 5 fault inputs for protection
purposes and 10 inputs to handle external events such as current limitation, zero voltage or
zero current switching.
The HRTIM1 timer is made of a digital kernel clocked at 480 MHz The high-resolution is
available on the 10 outputs in all operating modes: variable duty cycle, variable frequency,
and constant ON time.
The slave timers can be combined to control multiswitch complex converters or operate
independently to manage multiple independent converters.
The waveforms are defined by a combination of user-defined timings and external events
such as analog or digital feedbacks signals.
HRTIM1 timer includes options for blanking and filtering out spurious events or faults. It also
offers specific modes and features to offload the CPU: DMA requests, Burst mode
controller, Push-pull and Resonant mode.
It supports many topologies including LLC, Full bridge phase shifted, buck or boost
converters, either in voltage or current mode, as well as lighting application (fluorescent or
LED). It can also be used as a general purpose timer, for instance to achieve high-resolution
PWM-emulated DAC.
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52
Functional overview
3.29.2
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
•
Input capture
•
Output compare
•
PWM generation (Edge- or Center-aligned modes)
•
One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
3.29.3
General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32H750xB
devices (see Table 4 for differences).
•
TIM2, TIM3, TIM4, TIM5
The devices include 4 full-featured general-purpose timers: TIM2, TIM3, TIM4 and
TIM5. TIM2 and TIM5 are based on a 32-bit auto-reload up/downcounter and a 16-bit
prescaler while TIM3 and TIM4 are based on a 16-bit auto-reload up/downcounter and
a 16-bit prescaler. All timers feature 4 independent channels for input capture/output
compare, PWM or One-pulse mode output. This gives up to 16 input capture/output
compare/PWMs on the largest packages.
TIM2, TIM3, TIM4 and TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
•
TIM12, TIM13, TIM14, TIM15, TIM16, TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM13, TIM14, TIM16 and TIM17 feature one independent channel, whereas TIM12
and TIM15 have two independent channels for input capture/output compare, PWM or
One-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers or used as simple timebases.
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3.29.4
Functional overview
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
3.29.5
Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5)
The low-power timers have an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
3.29.6
•
16-bit up counter with 16-bit autoreload register
•
16-bit compare register
•
Configurable output: pulse, PWM
•
Continuous / One-shot mode
•
Selectable software / hardware input trigger
•
Selectable clock source:
•
Internal clock source: LSE, LSI, HSI or APB clock
•
External clock source over LPTIM input (working even with no internal clock source
running, used by the Pulse Counter Application)
•
Programmable digital glitch filter
•
Encoder mode
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
3.29.7
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
Debug mode.
3.29.8
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
•
A 24-bit downcounter
•
Autoreload capability
•
Maskable system interrupt generation when the counter reaches 0
•
Programmable clock source.
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52
Functional overview
3.30
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Real-time clock (RTC), backup SRAM and backup registers
The RTC is an independent BCD timer/counter. It supports the following features:
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
•
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
•
Two programmable alarms.
•
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
•
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
•
Three anti-tamper detection pins with programmable filter.
•
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
•
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby mode.
The RTC clock sources can be:
•
A 32.768 kHz external crystal (LSE)
•
An external resonator or oscillator (LSE)
•
The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
•
The high-speed external clock (HSE) divided by 32.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes.
All RTC events (Alarm, Wakeup Timer, Timestamp or Tamper) can generate an interrupt and
wakeup the device from the low-power modes.
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3.31
Functional overview
Inter-integrated circuit interface (I2C)
STM32H750xB devices embed four I2C interfaces.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
•
•
3.32
I2C-bus specification and user manual rev. 5 compatibility:
–
Slave and Master modes, multimaster capability
–
Standard-mode (Sm), with a bitrate up to 100 kbit/s
–
Fast-mode (Fm), with a bitrate up to 400 kbit/s
–
Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
–
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
–
Programmable setup and hold times
–
Optional clock stretching
System Management Bus (SMBus) specification rev 2.0 compatibility:
–
Hardware PEC (Packet Error Checking) generation and verification with ACK
control
–
Address resolution protocol (ARP) support
–
SMBus alert
•
Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility
•
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming.
•
Wakeup from Stop mode on address match
•
Programmable analog and digital noise filters
•
1-byte buffer with DMA capability
Universal synchronous/asynchronous receiver transmitter
(USART)
STM32H750xB devices have four embedded universal synchronous receiver transmitters
(USART1, USART2, USART3 and USART6) and four universal asynchronous receiver
transmitters (UART4, UART5, UART7 and UART8). Refer to Table 5 for a summary of
USARTx and UARTx features.
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire Half-duplex communication mode and
have LIN Master/Slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 Driver Enable. They are able to communicate at speeds of up to
12.5 Mbit/s.
USART1, USART2, USART3 and USART6 also provide Smartcard mode (ISO 7816
compliant) and SPI-like communication capability.
The USARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode
is enabled by software and is disabled by default.
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52
Functional overview
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
All USART have a clock domain independent from the CPU clock, allowing the USARTx to
wake up the MCU from Stop mode.The wakeup from Stop mode is programmable and can
be done on:
•
Start bit detection
•
Any received data frame
•
A specific programmed data frame
•
Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
All USART interfaces can be served by the DMA controller.
Table 5. USART features
USART modes/features(1)
USART1/2/3/6
UART4/5/7/8
Hardware flow control for modem
X
X
Continuous communication using DMA
X
X
Multiprocessor communication
X
X
Synchronous mode (Master/Slave)
X
-
Smartcard mode
X
-
Single-wire Half-duplex communication
X
X
IrDA SIR ENDEC block
X
X
LIN mode
X
X
Dual clock domain and wakeup from low power mode
X
X
Receiver timeout interrupt
X
X
Modbus communication
X
X
Auto baud rate detection
X
X
Driver Enable
X
X
USART data length
7, 8 and 9 bits
Tx/Rx FIFO
X
Tx/Rx FIFO size
X
16
1. X = supported.
3.33
Low-power universal asynchronous receiver transmitter
(LPUART)
The device embeds one Low-Power UART (LPUART1). The LPUART supports
asynchronous serial communication with minimum power consumption. It supports half
duplex single wire communication and modem operations (CTS/RTS). It allows
multiprocessor communication.
The LPUARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO
mode is enabled by software and is disabled by default.
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Functional overview
The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode. The wakeup from Stop mode are programmable and can be done
on:
•
Start bit detection
•
Any received data frame
•
A specific programmed data frame
•
Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to
9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame
while having an extremely low energy consumption. Higher speed clock can be used to
reach higher baudrates.
LPUART interface can be served by the DMA controller.
3.34
Serial peripheral interfaces (SPI)/integrated interchip
sound interfaces (I2S)
The devices feature up to six SPIs (SPI2S1, SPI2S2, SPI2S3, SPI4, SPI5 and SPI6) that
allow communicating up to 150 Mbits/s in Master and Slave modes, in Half-duplex, Fullduplex and Simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the
frame is configurable from 4 to 16 bits. All SPI interfaces support NSS pulse mode, TI mode,
Hardware CRC calculation and 8x 8-bit embedded Rx and Tx FIFOs with DMA capability.
Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They
can be operated in Master or Slave mode, in Simplex or Full-duplex communication mode,
and can be configured to operate with a 16-/32-bit resolution as an input or output channel.
Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of
the I2S interfaces is/are configured in Master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency. All I2S interfaces support 16x 8bit embedded Rx and Tx FIFOs with DMA capability.
3.35
Serial audio interfaces (SAI)
The devices embed 4 SAIs (SAI1, SAI2, SAI3 and SAI4) that allow designing many stereo
or mono audio protocols such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC’97. An
SPDIF output is available when the audio block is configured as a transmitter. To bring this
level of flexibility and reconfigurability, the SAI contains two independent audio sub-blocks.
Each block has it own clock generator and I/O line controller.
Audio sampling frequencies up to 192 kHz are supported.
In addition, up to 8 microphones can be supported thanks to an embedded PDM interface.
The SAI can work in master or slave configuration. The audio sub-blocks can be either
receiver or transmitter and can work synchronously or asynchronously (with respect to the
other one). The SAI can be connected with other SAIs to work synchronously.
DS12556 Rev 6
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52
Functional overview
3.36
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
SPDIFRX Receiver Interface (SPDIFRX)
The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958
and IEC-61937. These standards support simple stereo streams up to high sample rate,
and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up
to 5.1).
The main SPDIFRX features are the following:
•
Up to 4 inputs available
•
Automatic symbol rate detection
•
Maximum symbol rate: 12.288 MHz
•
Stereo stream from 32 to 192 kHz supported
•
Supports Audio IEC-60958 and IEC-61937, consumer applications
•
Parity bit management
•
Communication using DMA for audio samples
•
Communication using DMA for control and user channel information
•
Interrupt capabilities
The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and
decode the incoming data stream. The user can select the wanted SPDIF input, and when a
valid signal will be available, the SPDIFRX will re-sample the incoming signal, decode the
Manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the
CPU decoded data, and associated status flags.
The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF
sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms.
3.37
Single wire protocol master interface (SWPMI)
The Single wire protocol master interface (SWPMI) is the master interface corresponding to
the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The
main features are:
•
Full-duplex communication mode
•
automatic SWP bus state management (active, suspend, resume)
•
configurable bitrate up to 2 Mbit/s
•
automatic SOF, EOF and CRC handling
SWPMI can be served by the DMA controller.
48/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
3.38
Functional overview
Management Data Input/Output (MDIO) slaves
The devices embed an MDIO slave interface it includes the following features:
•
–
32 x 16-bit firmware read/write, MDIO read-only output data registers
–
32 x 16-bit firmware read-only, MDIO write-only input data registers
•
Configurable slave (port) address
•
Independently maskable interrupts/events:
•
3.39
32 MDIO Registers addresses, each of which is managed using separate input and
output data registers:
–
MDIO Register write
–
MDIO Register read
–
MDIO protocol error
Able to operate in and wake up from Stop mode
SD/SDIO/MMC card host interfaces (SDMMC)
Two SDMMC host interfaces are available. They support MultiMediaCard System
Specification Version 4.51 in three different databus modes: 1 bit (default), 4 bits and 8 bits.
Both interfaces support the SD memory card specifications version 4.1. and the SDIO card
specification version 4.0. in two different databus modes: 1 bit (default) and 4 bits.
Each SDMMC host interface supports only one SD/SDIO/MMC card at any one time and a
stack of MMC Version 4.51 or previous.
The SDMMC host interface embeds a dedicated DMA controller allowing high-speed
transfers between the interface and the SRAM.
3.40
Controller area network (FDCAN1, FDCAN2)
The controller area network (CAN) subsystem consists of two CAN modules, a shared
message RAM memory and a clock calibration unit.
Both CAN modules (FDCAN1 and FDCAN2) are compliant with ISO 11898-1 (CAN protocol
specification version 2.0 part A, B) and CAN FD protocol specification version 1.0.
FDCAN1 supports time triggered CAN (TT-FDCAN) specified in ISO 11898-4, including
event synchronized time-triggered communication, global system time, and clock drift
compensation. The FDCAN1 contains additional registers, specific to the time triggered
feature. The CAN FD option can be used together with event-triggered and time-triggered
CAN communication.
A 10-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers,
transmit event FIFOs, transmit buffers (and triggers for TT-FDCAN). This message RAM is
shared between the two FDCAN1 and FDCAN2 modules.
The common clock calibration unit is optional. It can be used to generate a calibrated clock
for both FDCAN1 and FDCAN2 from the HSI internal RC oscillator and the PLL, by
evaluating CAN messages received by the FDCAN1.
DS12556 Rev 6
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52
Functional overview
3.41
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Universal serial bus on-the-go high-speed (OTG_HS)
The devices embed two USB OTG high-speed (up to 480 Mbit/s) device/host/OTG
peripheral. OTG-HS1 supports both full-speed and high-speed operations, while OTG-HS2
supports only full-speed operations. They both integrate the transceivers for full-speed
operation (12 Mbit/s) and are able to operate from the internal HSI48 oscillator. OTG-HS1
features a UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s). When using
the USB OTG-HS1 in HS mode, an external PHY device connected to the ULPI is required.
The USB OTG HS peripherals are compliant with the USB 2.0 specification and with the
OTG 2.0 specification. They have software-configurable endpoint setting and supports
suspend/resume. The USB OTG controllers require a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The main features are:
•
Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing
•
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
•
9 bidirectional endpoints (including EP0)
•
16 host channels with periodic OUT support
•
Software configurable to OTG1.3 and OTG2.0 modes of operation
•
USB 2.0 LPM (Link Power Management) support
•
Battery Charging Specification Revision 1.2 support
•
Internal FS OTG PHY support
•
External HS or HS OTG operation supporting ULPI in SDR mode (OTG_HS1 only)
The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can
be clocked using the 60 MHz output.
3.42
•
Internal USB DMA
•
HNP/SNP/IP inside (no need for any external resistor)
•
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
Ethernet MAC interface with dedicated DMA controller (ETH)
The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
50/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Functional overview
The devices include the following features:
3.43
•
Supports 10 and 100 Mbit/s rates
•
Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors
•
Tagged MAC frame support (VLAN support)
•
Half-duplex (CSMA/CD) and full-duplex operation
•
MAC control sublayer (control frames) support
•
32-bit CRC generation and removal
•
Several address filtering modes for physical and multicast address (multicast and
group addresses)
•
32-bit status code for each transmitted or received frame
•
Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
•
Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
•
Triggers interrupt when system time becomes greater than target time
High-definition multimedia interface (HDMI)
- consumer electronics control (CEC)
The devices embed a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC
controller to wakeup the MCU from Stop mode on data reception.
3.44
Debug infrastructure
The devices offer a comprehensive set of debug and trace features to support software
development and system integration.
•
Breakpoint debugging
•
Code execution tracing
•
Software instrumentation
•
JTAG debug port
•
Serial-wire debug port
•
Trigger input and output
•
Serial-wire trace port
•
Trace port
•
Arm® CoreSight™ debug and trace components
The debug can be controlled via a JTAG/Serial-wire debug access port, using industry
standard debugging tools.
The trace port performs data capture for logging and analysis.
DS12556 Rev 6
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52
Memory mapping
4
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Memory mapping
Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.
52/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
5
Pin descriptions
Pin descriptions
PA14
PA15
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB3
PB4
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS
VDD
Figure 4. LQFP100 pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PE2 1
75 VDD
PE3 2
74 VSS
PE4 3
73 VCAP
PE5 4
72 PA13
PE6 5
71 PA12
VBAT 6
70 PA11
PC13 7
69 PA10
PC14-OSC32_IN 8
68 PA9
PC15-OSC32_OUT 9
67 PA8
VSS 10
66 PC9
VDD 11
65 PC8
PH0-OSC_IN 12
64 PC7
100-pins
PH1-OSC_OUT 13
63 PC6
NRST 14
62 PD15
PC0 15
61 PD14
PC1 16
60 PD13
PC2_C 17
59 PD12
PC3_C 18
58 PD11
VSSA 19
57 PD10
VREF+ 20
56 PD9
VDDA 21
55 PD8
PA0 22
54 PB15
PA1 23
53 PB14
PA2 24
52 PB13
PA3 25
51 PB12
VDD
VSS
VCAP
PB11
PB10
PE15
PE14
PE13
PE12
PE11
PE10
PE9
PE8
PE7
PB2
PB1
PB0
PC5
PA7
PC4
PA6
PA5
PA4
VDD
VSS
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MSv41918V4
1. The above figure shows the package top view.
DS12556 Rev 6
53/336
93
Pin descriptions
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71
144-pins
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
VDD
VSS
VCAP
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDD33USB
VSS
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP
VDD
PE2
PE3
PE4
PE5
PE6
VBAT
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PF0
PF1
PF2
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2_C
PC3_C
VDD
VSSA
VREF+
VDDA
PA0
PA1
PA2
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VDD
PDR_ON
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDD
VSS
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
VDD
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
Figure 5. LQFP144 pinout
MSv41917V4
1. The above figure shows the package top view.
54/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Pin descriptions
PE2
PE3
PE4
PE5
PE6
VBAT
PI8
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PI9
PI10
PI11
VSS
VDD
PF0
PF1
PF2
PF3
PF4
PF5
VSS
VDD
PF6
PF7
PF8
PF9
PF10
PH0-OSC_IN
PH1-OSC_OUT
NRST
PC0
PC1
PC2_C
PC3_C
VDD
VSSA
VREF+
VDDA
PA0
PA1
PA2
PH2
PH3
134
133
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
PINOUT UNDER DEVELOPMENT
169
170
171
172
173
174
175
176
PI7
PI6
PI5
PI4
VDD
PDR_ON
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDD
VSS
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
VDD
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
VDD
VSS
PI3
PI2
Figure 6. LQFP176 pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
176-pins
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
PI1
PI0
PH15
PH14
PH13
VDD
VSS
VCAP
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
VDD33USB
VSS
PG8
PG7
PG6
PG5
PG4
PG3
PG2
PD15
PD14
VDD
VSS
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
VDD
VSS
PH12
PH4
PH5
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP
VDD
PH6
PH7
PH8
PH9
PH10
PH11
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
MSv41916V5
1. The above figure shows the package top view.
DS12556 Rev 6
55/336
93
Pin descriptions
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 7. UFBGA176+25 ballout
1
2
3
5
6
10
11
A
PE3
PE2
PE1
PE0
PB8
PB5
PG14
PG13
PB4
PB3
PD7
B
PE4
PE5
PE6
PB9
PB7
PB6
PG15
PG12
PG11
PG10
C
VBAT
PI7
PI6
PI5
VDD
PDR_ON
VDD
VDD
VDD
D
PC13
PI8
PI9
PI4
VSS
BOOT0
VSS
VSS
VSS
PF0
PI10
PI11
VSS
VDD
PH2
VSS
VSS
VSS
VSS
E
F
PC14OSC32_
IN
PC15OSC32_
OUT
4
7
8
9
12
13
14
PC12
PA15
PA14
PA13
15
PD6
PD0
PC11
PC10
PA12
PG9
PD5
PD1
PI3
PI2
PA11
PD4
PD3
PD2
PH15
PI1
PA10
PH13
PH14
PI0
PA9
VSS
VSS
VCAP
PC9
PA8
G
PH0OSC_IN
VSS
VDD
PH3
VSS
VSS
VSS
VSS
VSS
VSS
VDD
PC8
PC7
H
PH1OSC_
OUT
PF2
PF1
PH4
VSS
VSS
VSS
VSS
VSS
VSS
VDD
33USB
PG8
PC6
J
NRST
PF3
PF4
PH5
VSS
VSS
VSS
VSS
VSS
VDD
VDD
PG7
PG6
K
PF7
PF6
PF5
VDD
VSS
VSS
VSS
VSS
VSS
PH12
PG5
PG4
PG3
L
PF10
PF9
PF8
VSS
PH11
PH10
PD15
PG2
M
VSSA
PC0
PC1
PC2_C
PC3_C
PB2
PG1
VSS
VSS
VCAP
PH6
PH8
PH9
PD14
PD13
N
VREF-
PA1
PA0
PA4
PC4
PF13
PG0
VDD
VDD
VDD
PE13
PH7
PD12
PD11
PD10
P
VREF+
PA2
PA6
PA5
PC5
PF12
PF15
PE8
PE9
PE11
PE14
PB12
PB13
PD9
PD8
R
VDDA
PA3
PA7
PB1
PB0
PF11
PF14
PE7
PE10
PE12
PE15
PB10
PB11
PB14
PB15
MSv41912V3
1. The above figure shows the package top view.
56/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Pin descriptions
Figure 8. TFBGA240+25 ballout
1
2
3
4
5
6
7
8
9
10
11
VCAP
PK5
PG10
PG9
PD5
12
13
14
15
16
17
PC10
PA15
PI1
PI0
VSS
A
VSS
PI6
PI5
PI4
PB5
VDD
LDO
B
VBAT
VSS
PI7
PE1
PB6
VSS
PB4
PK4
PG11
PJ15
PD6
PD3
PC11
PA14
PI2
PH15
PH14
PE2
PE0
PB7
PB3
PK6
PK3
PG12
VSS
PD7
PC12
VSS
PI3
PA13
VSS
VDD
LDO
PB9
PB8
PG15
PK7
PG14
PG13
PJ14
PJ12
PD2
PD0
PA10
PA9
PH13
VCAP
VDD
VDD
PJ13
VDD
PD1
PC8
PC9
PA8
PA12
PA11
PC6
PG8
PG7
VDD33
USB
PG5
PG6
VSS
VDD50
USB
C
D
PC15- PC14OSC32_ OSC32_
OUT
IN
PE5
PE4
PE3
E
NC
PI9
PC13
PI8
PE6
F
NC
VSS
PI10
PI11
VDD
G
PF2
NC
PF1
PF0
VDD
PI13
PI14
PDR_
ON
BOO
T0
PD4
PC7
VSS
VSS
VSS
VSS
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VDD
H
PI12
J
PH1PH0OSC_
OSC_IN
OUT
VSS
PF5
PF4
VSS
VSS
VSS
VSS
VSS
VDD
PK0
K
NRST
PF6
PF7
PF8
VDD
VSS
VSS
VSS
VSS
VSS
VDD
L
VDDA
PC0
PF10
PF9
VDD
VSS
VSS
VSS
VSS
VSS
M
VREF+
PC1
PC2
PC3
VDD
N
VREF-
PH2
PA2
PA1
PA0
PJ0
VDD
VDD
PE10
VDD
VDD
P
VSSA
PH3
PH4
PH5
PI15
PJ1
PF13
PF14
PE9
PE11
R
PC2_C
PC3_C
PA6
VSS
PA7
PB2
PF12
VSS
PF15
T
PA0_C
PA1_C
PA5
PC4
PB1
PJ2
PF11
PG0
U
VSS
PA3
PA4
PC5
PB0
PJ3
PJ4
PG1
PF3
VDD
PG4
PG3
PG2
PK2
PK1
VSS
VSS
PJ11
VSS
NC
NC
VDD
PJ10
VSS
NC
NC
VDD
PJ9
VSS
NC
NC
VDD
PJ8
PJ7
PJ6
VSS
NC
PB10
PB11
PH10
PH11
PD15
PD14
VDD
PE12
PE15
PJ5
PH9
PH12
PD11
PD12
PD13
PE8
PE13
PH6
VSS
PH8
PB12
PB15
PD10
PD9
PE7
PE14
VCAP
VDD
LDO
PH7
PB13
PB14
PD8
VSS
MSv41911V3
1. The above figure shows the package top view.
DS12556 Rev 6
57/336
93
Pin descriptions
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 6. Legend/abbreviations used in the pinout table
Name
Pin name
Pin type
Abbreviation
Unless otherwise specified in brackets below the pin name, the pin function during
and after reset is the same as the actual pin name
S
Supply pin
I
Input only pin
I/O
Input / output pin
ANA
Analog-only Input
FT
5 V tolerant I/O
TT
3.3 V tolerant I/O
B
Dedicated BOOT0 pin
RST
I/O structure
Notes
Pin functions
58/336
Definition
Bidirectional reset pin with embedded weak pull-up resistor
Option for TT and FT I/Os
_f
I2C FM+ option
_a
analog option (supplied by VDDA)
_u
USB option (supplied by VDD33USB)
_h
High-speed low-voltage I/O
Unless otherwise specified by a note, all I/Os are set as floating inputs during and
after reset.
Alternate
functions
Functions selected through GPIOx_AFR registers
Additional
functions
Functions directly selected/enabled through peripheral registers
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Pin descriptions
Table 7. STM32H750xB pin/ball definition
1
A2
1
C3
PE2
I/O
FT_h
-
2
2
A1
2
D3
PE3
I/O
FT_h
-
TRACED0, TIM15_BKIN,
SAI1_SD_B, SAI4_SD_B,
FMC_A19, EVENTOUT
-
-
TRACED1, SAI1_D2,
DFSDM1_DATIN3, TIM15_CH1N,
SPI4_NSS, SAI1_FS_A,
SAI4_FS_A, SAI4_D2, FMC_A20,
DCMI_D4, LCD_B0, EVENTOUT
-
-
TRACED2, SAI1_CK2,
DFSDM1_CKIN3, TIM15_CH1,
SPI4_MISO, SAI1_SCK_A,
SAI4_SCK_A, SAI4_CK2,
FMC_A21, DCMI_D6, LCD_G0,
EVENTOUT
-
-
3
4
3
4
B1
B2
LQFP176
1
TRACECLK, SAI1_CK1,
SPI4_SCK, SAI1_MCLK_A,
SAI4_MCLK_A,
QUADSPI_BK1_IO2, SAI4_CK1,
ETH_MII_TXD3, FMC_A23,
EVENTOUT
LQFP144
Alternate functions
LQFP100
Notes
I/O structure
Pin name
(function after
reset)
Pin type
TFBGA240 +25
UFBGA176+25
Pin/ball name
3
4
D2
D1
PE4
PE5
I/O
I/O
FT_h
FT_h
Additional
functions
-
5
5
B3
5
E5
PE6
I/O
FT_h
-
TRACED3, TIM1_BKIN2,
SAI1_D1, TIM15_CH2,
SPI4_MOSI, SAI1_SD_A,
SAI4_SD_A, SAI4_D1,
SAI2_MCLK_B,
TIM1_BKIN2_COMP12,
FMC_A22, DCMI_D7, LCD_G1,
EVENTOUT
-
-
H10
-
A1
VSS
S
-
-
-
-
-
-
-
-
-
VDD
S
-
-
-
-
6
6
C1
6
B1
VBAT
S
-
-
-
-
-
-
J6
-
B2
VSS
S
-
-
-
-
-
-
D2
7
E4
PI8
I/O
FT
-
EVENTOUT
RTC_
TAMP2/
WKUP3
7
7
D1
8
E3
PC13
I/O
FT
-
EVENTOUT
RTC_
TAMP1/
RTC_TS/
WKUP2
-
-
J7
-
B6
VSS
S
-
-
-
-
8
8
E1
9
C2
PC14OSC32_IN
(OSC32_IN)(1)
I/O
FT
-
EVENTOUT
OSC32_IN
DS12556 Rev 6
59/336
93
Pin descriptions
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 7. STM32H750xB pin/ball definition (continued)
LQFP100
LQFP144
UFBGA176+25
LQFP176
TFBGA240 +25
Pin type
I/O structure
Notes
Pin/ball name
Alternate functions
9
9
F1
10
C1
PC15OSC32_OUT
(OSC32_OUT)(1)
I/O
FT
-
EVENTOUT
OSC32_
OUT
-
-
D3
11
E2
PI9
I/O
FT_h
-
UART4_RX, FDCAN1_RX,
FMC_D30, LCD_VSYNC,
EVENTOUT
-
-
-
E3
12
F3
PI10
I/O
FT_h
-
FDCAN1_RXFD_MODE,
ETH_MII_RX_ER, FMC_D31,
LCD_HSYNC, EVENTOUT
-
-
E4
13
F4
PI11
I/O
FT
-
LCD_G6, OTG_HS_ULPI_DIR,
EVENTOUT
WKUP4
-
-
F2
14
A17
VSS
S
-
-
-
-
-
-
F3
15
E6
-
-
-
Pin name
(function after
reset)
Additional
functions
VDD
S
-
-
-
-
-
E1
(2)
NC
-
-
-
-
-
-
F1(3)
NC
-
-
-
-
-
(4)
NC
-
-
-
-
-
-
-
-
-
-
10
E2
16
G4
PF0
I/O
FT_f
-
I2C2_SDA, FMC_A0, EVENTOUT
-
-
11
H3
17
G3
PF1
I/O
FT_f
-
I2C2_SCL, FMC_A1, EVENTOUT
-
-
12
H2
18
G1
PF2
I/O
FT
-
I2C2_SMBA, FMC_A2,
EVENTOUT
-
-
-
-
-
H1
PI12
I/O
FT
-
LCD_HSYNC, EVENTOUT
-
-
-
-
-
H2
PI13
I/O
FT
-
LCD_VSYNC, EVENTOUT
-
-
-
-
-
H3
PI14
I/O
FT_h
-
LCD_CLK, EVENTOUT
-
-
13
J2
19
H4
PF3
I/O
FT_ha
-
FMC_A3, EVENTOUT
ADC3_
INP5
-
14
J3
20
J5
PF4
I/O
FT_ha
-
FMC_A4, EVENTOUT
ADC3_
INN5,
ADC3_
INP9
-
15
K3
21
J4
PF5
I/O
FT_ha
-
FMC_A5, EVENTOUT
ADC3_
INP4
10
16
G2
22
C10
VSS
S
-
-
-
-
11
17
G3
23
E9
VDD
S
-
-
-
-
-
18
K2
24
K2
PF6
I/O
FT_ha
-
TIM16_CH1, SPI5_NSS,
SAI1_SD_B, UART7_RX,
SAI4_SD_B, QUADSPI_BK1_IO3,
EVENTOUT
ADC3_
INN4,
ADC3_
INP8
60/336
G2
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Pin descriptions
Table 7. STM32H750xB pin/ball definition (continued)
19
25
K3
PF7
I/O
I/O structure
Pin type
TFBGA240 +25
LQFP176
UFBGA176+25
K1
Pin name
(function after
reset)
FT_ha
Notes
-
LQFP144
LQFP100
Pin/ball name
Alternate functions
Additional
functions
-
TIM17_CH1, SPI5_SCK,
SAI1_MCLK_B, UART7_TX,
SAI4_MCLK_B,
QUADSPI_BK1_IO2, EVENTOUT
ADC3_
INP3
ADC3_
INN3,
ADC3_
INP7
-
20
L3
26
K4
PF8
I/O
FT_ha
-
TIM16_CH1N, SPI5_MISO,
SAI1_SCK_B,
UART7_RTS/UART7_DE,
SAI4_SCK_B, TIM13_CH1,
QUADSPI_BK1_IO0, EVENTOUT
-
21
L2
27
L4
PF9
I/O
FT_ha
-
TIM17_CH1N, SPI5_MOSI,
SAI1_FS_B, UART7_CTS,
SAI4_FS_B, TIM14_CH1,
QUADSPI_BK1_IO1, EVENTOUT
ADC3_
INP2
ADC3_
INN2,
ADC3_
INP6
-
22
L1
28
L3
PF10
I/O
FT_ha
-
TIM16_BKIN, SAI1_D3,
QUADSPI_CLK, SAI4_D3,
DCMI_D11, LCD_DE, EVENTOUT
12
23
G1
29
J2
PH0-OSC_IN
(PH0)
I/O
FT
-
EVENTOUT
OSC_IN
13
24
H1
30
J1
PH1-OSC_OUT
(PH1)
I/O
FT
-
EVENTOUT
OSC_OUT
14
25
J1
31
K1
NRST
I/O
RST
-
-
-
-
DFSDM1_CKIN0,
DFSDM1_DATIN4, SAI2_FS_B,
OTG_HS_ULPI_STP,
FMC_SDNWE, LCD_R5,
EVENTOUT
ADC123_
INP10
-
TRACED0, SAI1_D1,
DFSDM1_DATIN0,
DFSDM1_CKIN4,
SPI2_MOSI/I2S2_SDO,
SAI1_SD_A, SAI4_SD_A,
SDMMC2_CK, SAI4_D1,
ETH_MDC, MDIOS_MDC,
EVENTOUT
ADC123_
INN10,
ADC123_
INP11,
RTC_
TAMP3/
WKUP5
15
16
-
26
27
-
M2
M3
-
17(6) 28(6) M4(6)
32
33
-
34(6)
L2
M2
(5)
M3
R1(5)
PC0
PC1
I/O
I/O
FT_a
FT_ha
PC2
I/O
FT_a
-
PC2_C
ANA
TT_a
-
DS12556 Rev 6
CDSLEEP, DFSDM1_CKIN1,
SPI2_MISO/I2S2_SDI,
DFSDM1_CKOUT,
OTG_HS_ULPI_DIR,
ETH_MII_TXD2, FMC_SDNE0,
EVENTOUT
ADC123_
INN11,
ADC123_
INP12
ADC3_
INN1,
ADC3_
INP0
61/336
93
Pin descriptions
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 7. STM32H750xB pin/ball definition (continued)
-
-
-
18(6) 29(6) M5(6)
-
M4
(5)
Notes
I/O structure
Pin name
(function after
reset)
Pin type
TFBGA240 +25
LQFP176
UFBGA176+25
LQFP144
LQFP100
Pin/ball name
PC3
I/O
FT_a
-
35(6)
R2(5)
PC3_C
ANA
TT_a
-
Alternate functions
CSLEEP, DFSDM1_DATIN1,
SPI2_MOSI/I2S2_SDO,
OTG_HS_ULPI_NXT,
ETH_MII_TX_CLK,
FMC_SDCKE0, EVENTOUT
Additional
functions
ADC12_
INN12,
ADC12_
INP13
ADC3_
INP1
-
30
G3
36
E11
VDD
S
-
-
-
-
J10
-
C13
VSS
S
-
-
-
-
19
31
M1
37
P1
VSSA
S
-
-
-
-
-
-
N1
-
N1
VREF-
S
-
-
-
-
20
32
P1
38
M1
VREF+
S
-
-
-
-
21
33
R1
39
L1
VDDA
S
-
-
-
-
22
34
N3
40
N5(5)
PA0
I/O
FT_a
-
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
TIM15_BKIN,
USART2_CTS/USART2_NSS,
UART4_TX, SDMMC2_CMD,
SAI2_SD_B, ETH_MII_CRS,
EVENTOUT
ADC1_
INP16,
WKUP0
-
-
-
-
23
35
N2
41
-
-
-
-
24
36
P2
42
(5)
PA0_C
ANA
TT_a
-
N4(5)
PA1
I/O
FT_ha
-
T2(5)
PA1_C
ANA
TT_a
-
T1
N3
PA2
I/O
FT_a
-
TIM2_CH2, TIM5_CH2,
LPTIM3_OUT, TIM15_CH1N,
USART2_RTS/USART2_DE,
UART4_RX, QUADSPI_BK1_IO3,
SAI2_MCLK_B,
ETH_MII_RX_CLK/ETH_RMII_RE
F_CLK, LCD_R2, EVENTOUT
ADC12_
INN1,
ADC12_
INP0
ADC1_
INN16,
ADC1_
INP17
ADC12_
INP1
-
TIM2_CH3, TIM5_CH3,
LPTIM4_OUT, TIM15_CH1,
USART2_TX, SAI2_SCK_B,
ETH_MDIO, MDIOS_MDIO,
LCD_R1, EVENTOUT
ADC12_
INP14,
WKUP1
ADC3_
INP13
-
-
F4
43
N2
PH2
I/O
FT_ha
-
LPTIM1_IN2,
QUADSPI_BK2_IO0,
SAI2_SCK_B, ETH_MII_CRS,
FMC_SDCKE0, LCD_R0,
EVENTOUT
-
-
-
-
F5
VDD
S
-
-
-
-
-
-
J8
-
C16
VSS
S
-
-
-
-
62/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Pin descriptions
Table 7. STM32H750xB pin/ball definition (continued)
-
G4
44
P2
PH3
I/O
FT_ha
-
-
-
H4
45
P3
PH4
I/O
FT_fa
-
I2C2_SCL, LCD_G5,
OTG_HS_ULPI_NXT, LCD_G4,
EVENTOUT
ADC3_
INN14,
ADC3_
INP15
-
I2C2_SDA, SPI5_NSS,
FMC_SDNWE, EVENTOUT
ADC3_
INN15,
ADC3_
INP16
ADC12_
INP15
-
-
J4
LQFP176
-
QUADSPI_BK2_IO1,
SAI2_MCLK_B, ETH_MII_COL,
FMC_SDNE0, LCD_R1,
EVENTOUT
LQFP144
Alternate functions
LQFP100
Notes
I/O structure
Pin name
(function after
reset)
Pin type
TFBGA240 +25
UFBGA176+25
Pin/ball name
46
P4
PH5
I/O
FT_fa
Additional
functions
ADC3_
INN13,
ADC3_
INP14
25
37
R2
47
U2
PA3
I/O
FT_ha
-
TIM2_CH4, TIM5_CH4,
LPTIM5_OUT, TIM15_CH2,
USART2_RX, LCD_B2,
OTG_HS_ULPI_D0,
ETH_MII_COL, LCD_B5,
EVENTOUT
26
38
K6
-
F2(4)
VSS
S
-
-
-
-
-
-
L4
48
-
VSS
S
-
-
-
-
27
39
K4
49
G5
VDD
S
-
-
-
-
-
D1PWREN, TIM5_ETR,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK, SPI6_NSS,
OTG_HS_SOF, DCMI_HSYNC,
LCD_VSYNC, EVENTOUT
ADC12_
INP18,
DAC1_
OUT1
-
D2PWREN,
TIM2_CH1/TIM2_ETR,
TIM8_CH1N, SPI1_SCK/I2S1_CK,
SPI6_SCK, OTG_HS_ULPI_CK,
LCD_R4, EVENTOUT
ADC12_
INN18,
ADC12_
INP19,
DAC1_
OUT2
-
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN,
SPI1_MISO/I2S1_SDI,
SPI6_MISO, TIM13_CH1,
TIM8_BKIN_COMP12,
MDIOS_MDC,
TIM1_BKIN_COMP12,
DCMI_PIXCLK, LCD_G2,
EVENTOUT
ADC12_
INP3
28
29
30
40
41
42
N4
P4
P3
50
51
52
U3
T3
R3
PA4
PA5
PA6
I/O
I/O
I/O
TT_a
TT_ha
FT_a
DS12556 Rev 6
63/336
93
Pin descriptions
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 7. STM32H750xB pin/ball definition (continued)
32
43
44
N5
53
54
R5
T4
PA7
PC4
I/O
I/O
I/O structure
Pin type
TFBGA240 +25
LQFP176
UFBGA176+25
R3
Pin name
(function after
reset)
TT_a
TT_a
Notes
31
LQFP144
LQFP100
Pin/ball name
Alternate functions
Additional
functions
-
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SDO,
SPI6_MOSI, TIM14_CH1,
ETH_MII_RX_DV/ETH_RMII_CRS
_DV, FMC_SDNWE, EVENTOUT
ADC12_
INN3,
ADC12_
INP7,
OPAMP1_
VINM
-
DFSDM1_CKIN2, I2S1_MCK,
SPDIFRX1_IN3,
ETH_MII_RXD0/ETH_RMII_RXD0
, FMC_SDNE0, EVENTOUT
ADC12_
INP4,
OPAMP1_
VOUT,
COMP1_
INM
ADC12_
INN4,
ADC12_
INP8,
OPAMP1_
VINM
33
45
P5
55
U4
PC5
I/O
TT_a
-
SAI1_D3, DFSDM1_DATIN2,
SPDIFRX1_IN4, SAI4_D3,
ETH_MII_RXD1/ETH_RMII_RXD1
, FMC_SDCKE0, COMP1_OUT,
EVENTOUT
-
-
-
-
G13
VDD
S
-
-
-
-
-
-
J9
-
R4
VSS
S
-
-
-
-
-
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N, DFSDM1_CKOUT,
UART4_CTS, LCD_R3,
OTG_HS_ULPI_D1,
ETH_MII_RXD2, LCD_G1,
EVENTOUT
ADC12_
INN5,
ADC12_
INP9,
OPAMP1_
VINP,
COMP1_
INP
-
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N, DFSDM1_DATIN1,
LCD_R6, OTG_HS_ULPI_D2,
ETH_MII_RXD3, LCD_G0,
EVENTOUT
ADC12_
INP5,
COMP1_
INM
COMP1_
INP
34
35
46
47
R5
R4
56
57
U5
T5
PB0
PB1
I/O
I/O
FT_a
TT_u
36
48
M6
58
R6
PB2
I/O
FT_ha
-
RTC_OUT, SAI1_D1,
DFSDM1_CKIN1, SAI1_SD_A,
SPI3_MOSI/I2S3_SDO,
SAI4_SD_A, QUADSPI_CLK,
SAI4_D1, EVENTOUT
-
-
-
-
P5
PI15
I/O
FT
-
LCD_G2, LCD_R0, EVENTOUT
-
-
-
-
-
N6
PJ0
I/O
FT
-
LCD_R7, LCD_R1, EVENTOUT
-
-
-
-
-
P6
PJ1
I/O
FT
-
LCD_R2, EVENTOUT
-
-
-
-
-
T6
PJ2
I/O
FT
-
LCD_R3, EVENTOUT
-
-
-
-
-
U6
PJ3
I/O
FT
-
LCD_R4, EVENTOUT
-
64/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Pin descriptions
Table 7. STM32H750xB pin/ball definition (continued)
LQFP100
LQFP144
UFBGA176+25
LQFP176
TFBGA240 +25
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Pin/ball name
Alternate functions
-
-
-
-
U7
PJ4
I/O
FT
-
LCD_R5, EVENTOUT
-
-
49
R6
59
T7
PF11
I/O
FT_a
-
SPI5_MOSI, SAI2_SD_B,
FMC_SDNRAS, DCMI_D12,
EVENTOUT
ADC1_
INP2
Additional
functions
-
50
P6
60
R7
PF12
I/O
FT_ha
-
FMC_A6, EVENTOUT
ADC1_
INN2,
ADC1_
INP6
-
51
M8
61
J3
VSS
S
-
-
-
-
-
52
N8
62
H5
VDD
S
-
-
-
-
-
53
N6
63
P7
PF13
I/O
FT_ha
-
DFSDM1_DATIN6, I2C4_SMBA,
FMC_A7, EVENTOUT
ADC2_
INP2
ADC2_
INN2,
ADC2_
INP6
-
54
R7
64
P8
PF14
I/O
FT_fha
-
DFSDM1_CKIN6, I2C4_SCL,
FMC_A8, EVENTOUT
-
55
P7
65
R9
PF15
I/O
FT_fh
-
I2C4_SDA, FMC_A9, EVENTOUT
-
-
56
N7
66
T8
PG0
I/O
FT_h
-
FMC_A10, EVENTOUT
-
-
-
F6
-
J16
VSS
S
-
-
-
-
-
-
-
-
H13
VDD
S
-
-
-
-
-
57
M7
67
U8
PG1
I/O
TT_h
-
FMC_A11, EVENTOUT
OPAMP2_
VINM
OPAMP2_
VOUT,
COMP2_
INM
37
58
R8
68
U9
PE7
I/O
TT_ha
-
TIM1_ETR, DFSDM1_DATIN2,
UART7_RX, QUADSPI_BK2_IO0,
FMC_D4/FMC_DA4, EVENTOUT
38
59
P8
69
T9
PE8
I/O
TT_ha
-
TIM1_CH1N, DFSDM1_CKIN2,
UART7_TX, QUADSPI_BK2_IO1,
FMC_D5/FMC_DA5,
COMP2_OUT, EVENTOUT
OPAMP2_
VINM
OPAMP2_
VINP,
COMP2_
INP
39
60
P9
70
P9
PE9
I/O
TT_ha
-
TIM1_CH1, DFSDM1_CKOUT,
UART7_RTS/UART7_DE,
QUADSPI_BK2_IO2,
FMC_D6/FMC_DA6, EVENTOUT
-
61
M9
71
J17
VSS
S
-
-
-
-
-
62
N9
72
J13
VDD
S
-
-
-
-
40
63
R9
73
N9
PE10
I/O
FT_ha
-
TIM1_CH2N, DFSDM1_DATIN4,
UART7_CTS,
QUADSPI_BK2_IO3,
FMC_D7/FMC_DA7, EVENTOUT
COMP2_
INM
DS12556 Rev 6
65/336
93
Pin descriptions
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 7. STM32H750xB pin/ball definition (continued)
42
64
65
R10
74
75
P10
R10
PE11
PE12
I/O
I/O
I/O structure
Pin type
TFBGA240 +25
LQFP176
UFBGA176+25
P10
Pin name
(function after
reset)
FT_ha
FT_h
Notes
41
LQFP144
LQFP100
Pin/ball name
Alternate functions
Additional
functions
-
TIM1_CH2, DFSDM1_CKIN4,
SPI4_NSS, SAI2_SD_B,
FMC_D8/FMC_DA8, LCD_G3,
EVENTOUT
COMP2_
INP
-
TIM1_CH3N, DFSDM1_DATIN5,
SPI4_SCK, SAI2_SCK_B,
FMC_D9/FMC_DA9,
COMP1_OUT, LCD_B4,
EVENTOUT
-
-
43
66
N11
76
T10
PE13
I/O
FT_h
-
TIM1_CH3, DFSDM1_CKIN5,
SPI4_MISO, SAI2_FS_B,
FMC_D10/FMC_DA10,
COMP2_OUT, LCD_DE,
EVENTOUT
-
-
F7
-
T12
VSS
S
-
-
-
-
-
-
-
-
K13
VDD
S
-
-
-
-
44
67
P11
77
U10
PE14
I/O
FT_h
-
TIM1_CH4, SPI4_MOSI,
SAI2_MCLK_B,
FMC_D11/FMC_DA11, LCD_CLK,
EVENTOUT
-
-
TIM1_BKIN,
FMC_D12/FMC_DA12,
TIM1_BKIN_COMP12/COMP_
TIM1_BKIN, LCD_R7, EVENTOUT
-
-
TIM2_CH3, HRTIM_SCOUT,
LPTIM2_IN1, I2C2_SCL,
SPI2_SCK/I2S2_CK,
DFSDM1_DATIN7, USART3_TX,
QUADSPI_BK1_NCS,
OTG_HS_ULPI_D3,
ETH_MII_RX_ER, LCD_G4,
EVENTOUT
-
-
45
46
68
69
R11
R12
78
79
R11
P11
PE15
PB10
I/O
I/O
FT_h
FT_f
47
70
R13
80
P12
PB11
I/O
FT_f
-
TIM2_CH4, HRTIM_SCIN,
LPTIM2_ETR, I2C2_SDA,
DFSDM1_CKIN7, USART3_RX,
OTG_HS_ULPI_D4,
ETH_MII_TX_EN/ETH_RMII_TX_
EN, LCD_G5, EVENTOUT
48
71
M10
81
U11
VCAP
S
-
-
-
-
49
-
K7
-
-
VSS
S
-
-
-
-
-
-
-
-
U12
VDDLDO
S
-
-
-
-
50
72
N10
82
L13
VDD
S
-
-
-
-
-
-
-
-
R12
PJ5
I/O
FT
-
LCD_R6, EVENTOUT
-
66/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Pin descriptions
Table 7. STM32H750xB pin/ball definition (continued)
-
M11
83
T11
PH6
I/O
FT
-
-
-
N12
84
U13
PH7
I/O
FT_fa
-
I2C3_SCL, SPI5_MISO,
ETH_MII_RXD3, FMC_SDCKE1,
DCMI_D9, EVENTOUT
-
-
-
M12
85
T13
PH8
I/O
FT_fha
-
TIM5_ETR, I2C3_SDA, FMC_D16,
DCMI_HSYNC, LCD_R2,
EVENTOUT
-
-
-
F8
-
-
VSS
S
-
-
-
-
-
-
-
-
M13
VDD
S
-
-
-
-
-
-
M13
86
R13
PH9
I/O
FT_h
-
TIM12_CH2, I2C3_SMBA,
FMC_D17, DCMI_D0, LCD_R3,
EVENTOUT
-
-
-
L13
87
P13
PH10
I/O
FT_h
-
TIM5_CH1, I2C4_SMBA,
FMC_D18, DCMI_D1, LCD_R4,
EVENTOUT
-
-
-
L12
88
P14
PH11
I/O
FT_fh
-
TIM5_CH2, I2C4_SCL, FMC_D19,
DCMI_D2, LCD_R5, EVENTOUT
-
-
-
K12
89
R14
PH12
I/O
FT_fh
-
TIM5_CH3, I2C4_SDA, FMC_D20,
DCMI_D3, LCD_R6, EVENTOUT
-
-
-
H12
90
N16
VSS
S
-
-
-
-
-
-
J12
91
P17
VDD
S
-
-
-
-
-
TIM1_BKIN, I2C2_SMBA,
SPI2_NSS/I2S2_WS,
DFSDM1_DATIN1, USART3_CK,
FDCAN2_RX, OTG_HS_ULPI_D5,
ETH_MII_TXD0/ETH_RMII_TXD0,
OTG_HS_ID,
TIM1_BKIN_COMP12,
UART5_RX, EVENTOUT
-
TIM1_CH1N, LPTIM2_OUT,
SPI2_SCK/I2S2_CK,
DFSDM1_CKIN1,
USART3_CTS/USART3_NSS,
FDCAN2_TX, OTG_HS_ULPI_D6,
ETH_MII_TXD1/ETH_RMII_TXD1,
UART5_TX, EVENTOUT
51
52
73
74
P12
P13
LQFP176
-
TIM12_CH1, I2C2_SMBA,
SPI5_SCK, ETH_MII_RXD2,
FMC_SDNE1, DCMI_D8,
EVENTOUT
LQFP144
Alternate functions
LQFP100
Notes
I/O structure
Pin name
(function after
reset)
Pin type
TFBGA240 +25
UFBGA176+25
Pin/ball name
92
93
T14
U14
PB12
PB13
I/O
I/O
FT_u
FT_u
DS12556 Rev 6
Additional
functions
-
OTG_HS_
VBUS
67/336
93
Pin descriptions
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 7. STM32H750xB pin/ball definition (continued)
75
94
U15
PB14
I/O
I/O structure
Pin type
TFBGA240 +25
LQFP176
UFBGA176+25
R14
Pin name
(function after
reset)
FT_u
Notes
53
LQFP144
LQFP100
Pin/ball name
Alternate functions
Additional
functions
-
TIM1_CH2N, TIM12_CH1,
TIM8_CH2N, USART1_TX,
SPI2_MISO/I2S2_SDI,
DFSDM1_DATIN2,
USART3_RTS/USART3_DE,
UART4_RTS/UART4_DE,
SDMMC2_D0, OTG_HS_DM,
EVENTOUT
-
-
54
76
R15
95
T15
PB15
I/O
FT_u
-
RTC_REFIN, TIM1_CH3N,
TIM12_CH2, TIM8_CH3N,
USART1_RX,
SPI2_MOSI/I2S2_SDO,
DFSDM1_CKIN2, UART4_CTS,
SDMMC2_D1, OTG_HS_DP,
EVENTOUT
55
77
P15
96
U16
PD8
I/O
FT_h
-
DFSDM1_CKIN3, SAI3_SCK_B,
USART3_TX, SPDIFRX1_IN2,
FMC_D13/FMC_DA13,
EVENTOUT
-
-
DFSDM1_DATIN3, SAI3_SD_B,
USART3_RX,
FDCAN2_RXFD_MODE,
FMC_D14/FMC_DA14,
EVENTOUT
-
-
56
78
P14
97
T17
PD9
I/O
FT_h
57
79
N15
98
T16
PD10
I/O
FT_h
-
DFSDM1_CKOUT, SAI3_FS_B,
USART3_CK,
FDCAN2_TXFD_MODE,
FMC_D15/FMC_DA15, LCD_B3,
EVENTOUT
-
-
-
-
N12
VDD
S
-
-
-
-
-
-
F9
-
U17
VSS
S
-
-
-
-
-
LPTIM2_IN2, I2C4_SMBA,
USART3_CTS/USART3_NSS,
QUADSPI_BK1_IO0, SAI2_SD_A,
FMC_A16, EVENTOUT
-
-
-
58
80
N14
99
R15
PD11
I/O
FT_h
59
81
N13
100
R16
PD12
I/O
FT_fh
-
LPTIM1_IN1, TIM4_CH1,
LPTIM2_IN1, I2C4_SCL,
USART3_RTS/USART3_DE,
QUADSPI_BK1_IO1, SAI2_FS_A,
FMC_A17, EVENTOUT
60
82
M15
101
R17
PD13
I/O
FT_fh
-
LPTIM1_OUT, TIM4_CH2,
I2C4_SDA, QUADSPI_BK1_IO3,
SAI2_SCK_A, FMC_A18,
EVENTOUT
68/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Pin descriptions
Table 7. STM32H750xB pin/ball definition (continued)
LQFP100
LQFP144
UFBGA176+25
LQFP176
TFBGA240 +25
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Pin/ball name
Alternate functions
-
83
K8
102
-
VSS
S
-
-
-
-
-
84
J13
103
N11
VDD
S
-
-
-
-
61
85
M14
104
P16
PD14
I/O
FT_h
-
TIM4_CH3, SAI3_MCLK_B,
UART8_CTS,
FMC_D0/FMC_DA0, EVENTOUT
-
62
86
L14
105
P15
PD15
I/O
FT_h
-
TIM4_CH4, SAI3_MCLK_A,
UART8_RTS/UART8_DE,
FMC_D1/FMC_DA1, EVENTOUT
-
-
-
-
-
N15
PJ6
I/O
FT
-
TIM8_CH2, LCD_R7, EVENTOUT
-
-
-
-
-
N14
PJ7
I/O
FT
-
TRGIN, TIM8_CH2N, LCD_G0,
EVENTOUT
-
-
-
-
-
N10
VDD
S
-
-
-
-
F10
-
R8
VSS
S
-
-
-
-
-
-
N13
PJ8
I/O
FT
-
TIM1_CH3N, TIM8_CH1,
UART8_TX, LCD_G1, EVENTOUT
-
-
-
-
-
M14
PJ9
I/O
FT
-
TIM1_CH3, TIM8_CH1N,
UART8_RX, LCD_G2,
EVENTOUT
-
-
-
-
-
L14
PJ10
I/O
FT
-
TIM1_CH2N, TIM8_CH2,
SPI5_MOSI, LCD_G3,
EVENTOUT
-
-
-
-
-
K14
PJ11
I/O
FT
-
TIM1_CH2, TIM8_CH2N,
SPI5_MISO, LCD_G4,
EVENTOUT
-
-
-
-
-
N8
VDD
S
-
-
G6
-
U1
-
-
-
VSS
S
-
-
-
-
-
N17
NC
-
-
-
-
-
-
M16(2)
NC
-
-
-
-
-
(2)
NC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(2)
-
-
-
Additional
functions
-
M17
K15
VSS
S
-
-
-
-
L16
(2)
NC
-
-
-
-
-
L17
(2)
NC
-
-
-
-
-
K16
(2)
NC
-
-
-
-
-
K17
(2)
NC
-
-
-
-
-
-
-
-
-
-
-
-
-
L15
VSS
S
-
-
-
-
-
-
-
-
J14
PK0
I/O
FT
-
TIM1_CH1N, TIM8_CH3,
SPI5_SCK, LCD_G5, EVENTOUT
-
DS12556 Rev 6
69/336
93
Pin descriptions
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 7. STM32H750xB pin/ball definition (continued)
LQFP100
LQFP144
UFBGA176+25
LQFP176
TFBGA240 +25
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Pin/ball name
Alternate functions
-
-
-
-
J15
PK1
I/O
FT
-
TIM1_CH1, TIM8_CH3N,
SPI5_NSS, LCD_G6, EVENTOUT
-
-
-
-
-
H17
PK2
I/O
FT
-
TIM1_BKIN, TIM8_BKIN,
TIM8_BKIN_COMP12,
TIM1_BKIN_COMP12, LCD_G7,
EVENTOUT
-
-
87
L15
106
H16
PG2
I/O
FT_h
-
TIM8_BKIN,
TIM8_BKIN_COMP12, FMC_A12,
EVENTOUT
-
-
88
K15
107
H15
PG3
I/O
FT_h
-
TIM8_BKIN2,
TIM8_BKIN2_COMP12,
FMC_A13, EVENTOUT
-
-
-
G7
-
-
VSS
S
-
-
-
-
-
-
-
-
N7
VDD
S
-
-
-
-
-
89
K14
108
H14
PG4
I/O
FT_h
-
TIM1_BKIN2,
TIM1_BKIN2_COMP12,
FMC_A14/FMC_BA0, EVENTOUT
-
-
90
K13
109
G14
PG5
I/O
FT_h
-
TIM1_ETR, FMC_A15/FMC_BA1,
EVENTOUT
-
-
91
J15
110
G15
PG6
I/O
FT_h
-
TIM17_BKIN, HRTIM_CHE1,
QUADSPI_BK1_NCS, FMC_NE3,
DCMI_D12, LCD_R7, EVENTOUT
-
-
92
J14
111
F16
PG7
I/O
FT_h
-
HRTIM_CHE2, SAI1_MCLK_A,
USART6_CK, FMC_INT,
DCMI_D13, LCD_CLK,
EVENTOUT
-
-
Additional
functions
-
93
H14
112
F15
PG8
I/O
FT_h
-
TIM8_ETR, SPI6_NSS,
USART6_RTS/USART6_DE,
SPDIFRX1_IN3, ETH_PPS_OUT,
FMC_SDCLK, LCD_G7,
EVENTOUT
-
94
G12
113
G16
VSS
S
-
-
-
-
-
-
-
-
G17
VDD50USB
S
-
-
-
-
-
95
H13
114
F17
VDD33USB
S
-
-
-
-
-
-
-
-
M5
VDD
S
-
-
-
-
70/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Pin descriptions
Table 7. STM32H750xB pin/ball definition (continued)
64
65
96
97
98
G15
G14
115
116
117
F14
F13
E13
PC6
PC7
PC8
I/O
I/O
I/O
I/O structure
Pin type
TFBGA240 +25
LQFP176
UFBGA176+25
H15
Pin name
(function after
reset)
FT_h
FT_h
FT_h
Notes
63
LQFP144
LQFP100
Pin/ball name
Alternate functions
Additional
functions
-
HRTIM_CHA1, TIM3_CH1,
TIM8_CH1, DFSDM1_CKIN3,
I2S2_MCK, USART6_TX,
SDMMC1_D0DIR, FMC_NWAIT,
SDMMC2_D6, SDMMC1_D6,
DCMI_D0, LCD_HSYNC,
EVENTOUT
SWPMI_IO
-
TRGIO, HRTIM_CHA2,
TIM3_CH2, TIM8_CH2,
DFSDM1_DATIN3, I2S3_MCK,
USART6_RX,
SDMMC1_D123DIR, FMC_NE1,
SDMMC2_D7, SWPMI_TX,
SDMMC1_D7, DCMI_D1,
LCD_G6, EVENTOUT
-
-
TRACED1, HRTIM_CHB1,
TIM3_CH3, TIM8_CH3,
USART6_CK,
UART5_RTS/UART5_DE,
FMC_NE2/FMC_NCE,
SWPMI_RX, SDMMC1_D0,
DCMI_D2, EVENTOUT
-
MCO2, TIM3_CH4, TIM8_CH4,
I2C3_SDA, I2S_CKIN,
UART5_CTS,
QUADSPI_BK1_IO0, LCD_G3,
SWPMI_SUSPEND,
SDMMC1_D1, DCMI_D3,
LCD_B2, EVENTOUT
-
66
99
F14
118
E14
PC9
I/O
FT_fh
-
-
-
G8
-
-
VSS
S
-
-
-
-
-
-
-
L5
VDD
S
-
-
-
67
68
100
101
F15
E15
119
120
E15
D15
PA8
PA9
I/O
I/O
FT_fha
FT_u
DS12556 Rev 6
-
MCO1, TIM1_CH1, HRTIM_CHB2,
TIM8_BKIN2, I2C3_SCL,
USART1_CK, OTG_FS_SOF,
UART7_RX,
TIM8_BKIN2_COMP12, LCD_B3,
LCD_R6, EVENTOUT
-
-
TIM1_CH2, HRTIM_CHC1,
LPUART1_TX, I2C3_SMBA,
SPI2_SCK/I2S2_CK,
USART1_TX,
FDCAN1_RXFD_MODE,
DCMI_D0, LCD_R5, EVENTOUT
OTG_FS_
VBUS
71/336
93
Pin descriptions
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 7. STM32H750xB pin/ball definition (continued)
70
102
103
C15
121
122
D14
E17
PA10
PA11
I/O
I/O
I/O structure
Pin type
TFBGA240 +25
LQFP176
UFBGA176+25
D15
Pin name
(function after
reset)
FT_u
FT_u
Notes
69
LQFP144
LQFP100
Pin/ball name
Alternate functions
Additional
functions
-
TIM1_CH3, HRTIM_CHC2,
LPUART1_RX, USART1_RX,
FDCAN1_TXFD_MODE,
OTG_FS_ID, MDIOS_MDIO,
LCD_B4, DCMI_D1, LCD_B1,
EVENTOUT
-
-
TIM1_CH4, HRTIM_CHD1,
LPUART1_CTS,
SPI2_NSS/I2S2_WS, UART4_RX,
USART1_CTS/USART1_NSS,
FDCAN1_RX, OTG_FS_DM,
LCD_R4, EVENTOUT
-
-
71
104
B15
123
E16
PA12
I/O
FT_u
-
TIM1_ETR, HRTIM_CHD2,
LPUART1_RTS/LPUART1_DE,
SPI2_SCK/I2S2_CK, UART4_TX,
USART1_RTS/USART1_DE,
SAI2_FS_B, FDCAN1_TX,
OTG_FS_DP, LCD_R5,
EVENTOUT
72
105
A15
124
C15
PA13
(JTMS/SWDIO)
I/O
FT
-
JTMS-SWDIO, EVENTOUT
-
73
106
F13
125
D17
VCAP
S
-
-
-
-
74
107
F12
126
-
VSS
S
-
-
-
-
-
-
-
-
C17
VDDLDO
-
-
-
-
75
108
G13
127
K5
VDD
S
-
-
-
-
-
-
E12
128
D16
PH13
I/O
FT_h
-
TIM8_CH1N, UART4_TX,
FDCAN1_TX, FMC_D21,
LCD_G2, EVENTOUT
-
-
-
E13
129
B17
PH14
I/O
FT_h
-
TIM8_CH2N, UART4_RX,
FDCAN1_RX, FMC_D22,
DCMI_D4, LCD_G3, EVENTOUT
-
-
-
D13
130
B16
PH15
I/O
FT_h
-
TIM8_CH3N,
FDCAN1_TXFD_MODE,
FMC_D23, DCMI_D11, LCD_G4,
EVENTOUT
-
-
-
-
-
E14
131
A16
PI0
I/O
FT_h
-
TIM5_CH4, SPI2_NSS/I2S2_WS,
FDCAN1_RXFD_MODE,
FMC_D24, DCMI_D13, LCD_G5,
EVENTOUT
-
-
G9
-
-
VSS
S
-
-
-
72/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Pin descriptions
Table 7. STM32H750xB pin/ball definition (continued)
-
D14
132
A15
PI1
I/O
FT_h
-
-
-
C14
133
B15
PI2
I/O
FT_h
-
TIM8_CH4, SPI2_MISO/I2S2_SDI,
FMC_D26, DCMI_D9, LCD_G7,
EVENTOUT
-
-
LQFP176
-
TIM8_BKIN2,
SPI2_SCK/I2S2_CK,
TIM8_BKIN2_COMP12,
FMC_D25, DCMI_D8, LCD_G6,
EVENTOUT
LQFP144
Alternate functions
LQFP100
Notes
I/O structure
Pin name
(function after
reset)
Pin type
TFBGA240 +25
UFBGA176+25
Pin/ball name
Additional
functions
-
-
-
C13
134
C14
PI3
I/O
FT_h
-
TIM8_ETR,
SPI2_MOSI/I2S2_SDO,
FMC_D27, DCMI_D10,
EVENTOUT
-
-
D9
135
-
VSS
S
-
-
-
-
-
-
C9
136
-
VDD
S
-
-
-
-
76
109
A14
137
B14
PA14
(JTCK/SWCLK)
I/O
FT
-
JTCK-SWCLK, EVENTOUT
-
-
JTDI, TIM2_CH1/TIM2_ETR,
HRTIM_FLT1, CEC,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS, SPI6_NSS,
UART4_RTS/UART4_DE,
UART7_TX, EVENTOUT
-
-
HRTIM_EEV1, DFSDM1_CKIN5,
SPI3_SCK/I2S3_CK,
USART3_TX, UART4_TX,
QUADSPI_BK1_IO1,
SDMMC1_D2, DCMI_D8,
LCD_R2, EVENTOUT
-
-
HRTIM_FLT2, DFSDM1_DATIN5,
SPI3_MISO/I2S3_SDI,
USART3_RX, UART4_RX,
QUADSPI_BK2_NCS,
SDMMC1_D3, DCMI_D4,
EVENTOUT
-
-
77
78
79
110
111
112
A13
B14
B13
138
139
140
A14
A13
B13
PA15
(JTDI)
PC10
PC11
I/O
I/O
I/O
FT
FT_ha
FT_h
80
113
A12
141
C12
PC12
I/O
FT_h
-
TRACED3, HRTIM_EEV2,
SPI3_MOSI/I2S3_SDO,
USART3_CK, UART5_TX,
SDMMC1_CK, DCMI_D9,
EVENTOUT
-
-
G10
-
-
VSS
S
-
-
-
-
81
114
B12
142
D13
PD0
I/O
FT_h
-
DFSDM1_CKIN6, SAI3_SCK_A,
UART4_RX, FDCAN1_RX,
FMC_D2/FMC_DA2, EVENTOUT
-
DS12556 Rev 6
73/336
93
Pin descriptions
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 7. STM32H750xB pin/ball definition (continued)
LQFP100
LQFP144
UFBGA176+25
LQFP176
TFBGA240 +25
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Pin/ball name
Alternate functions
82
115
C12
143
E12
PD1
I/O
FT_h
-
DFSDM1_DATIN6, SAI3_SD_A,
UART4_TX, FDCAN1_TX,
FMC_D3/FMC_DA3, EVENTOUT
-
83
116
D12
144
D12
PD2
I/O
FT_h
-
TRACED2, TIM3_ETR,
UART5_RX, SDMMC1_CMD,
DCMI_D11, EVENTOUT
-
-
DFSDM1_CKOUT,
SPI2_SCK/I2S2_CK,
USART2_CTS/USART2_NSS,
FMC_CLK, DCMI_D5, LCD_G7,
EVENTOUT
-
-
84
117
D11
145
B12
PD3
I/O
FT_h
Additional
functions
85
118
D10
146
A12
PD4
I/O
FT_h
-
HRTIM_FLT3, SAI3_FS_A,
USART2_RTS/USART2_DE,
FDCAN1_RXFD_MODE,
FMC_NOE, EVENTOUT
86
119
C11
147
A11
PD5
I/O
FT_h
-
HRTIM_EEV3, USART2_TX,
FDCAN1_TXFD_MODE,
FMC_NWE, EVENTOUT
-
-
120
D8
148
-
VSS
S
-
-
-
-
-
121
C8
149
-
VDD
S
-
-
-
-
-
SAI1_D1, DFSDM1_CKIN4,
DFSDM1_DATIN1,
SPI3_MOSI/I2S3_SDO,
SAI1_SD_A, USART2_RX,
SAI4_SD_A,
FDCAN2_RXFD_MODE,
SAI4_D1, SDMMC2_CK,
FMC_NWAIT, DCMI_D10,
LCD_B2, EVENTOUT
-
-
87
122
B11
150
B11
PD6
I/O
FT_h
88
123
A11
151
C11
PD7
I/O
FT_h
-
DFSDM1_DATIN4,
SPI1_MOSI/I2S1_SDO,
DFSDM1_CKIN1, USART2_CK,
SPDIFRX1_IN1, SDMMC2_CMD,
FMC_NE1, EVENTOUT
-
-
-
-
D11
PJ12
I/O
FT
-
TRGOUT, LCD_G3, LCD_B0,
EVENTOUT
-
-
-
-
-
E10
PJ13
I/O
FT
-
LCD_B4, LCD_B1, EVENTOUT
-
-
-
-
-
D10
PJ14
I/O
FT
-
LCD_B2, EVENTOUT
-
-
-
-
-
B10
PJ15
I/O
FT
-
LCD_B3, EVENTOUT
-
-
-
H6
-
-
VSS
S
-
-
-
-
-
-
-
-
-
VDD
S
-
-
-
-
74/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Pin descriptions
Table 7. STM32H750xB pin/ball definition (continued)
-
-
-
-
124
125
126
127
128
B10
B9
B8
A8
152
153
154
155
156
A10
A9
B9
C9
D9
PG9
PG10
PG11
PG12
PG13
I/O
I/O
I/O
I/O
I/O
I/O structure
Pin type
TFBGA240 +25
LQFP176
UFBGA176+25
C10
Pin name
(function after
reset)
FT_h
FT_h
FT_h
FT_h
FT_h
Notes
-
LQFP144
LQFP100
Pin/ball name
Alternate functions
Additional
functions
-
SPI1_MISO/I2S1_SDI,
USART6_RX, SPDIFRX1_IN4,
QUADSPI_BK2_IO2, SAI2_FS_B,
FMC_NE2/FMC_NCE,
DCMI_VSYNC, EVENTOUT
-
-
HRTIM_FLT5,
SPI1_NSS/I2S1_WS, LCD_G3,
SAI2_SD_B, FMC_NE3,
DCMI_D2, LCD_B2, EVENTOUT
-
-
LPTIM1_IN2, HRTIM_EEV4,
SPI1_SCK/I2S1_CK,
SPDIFRX1_IN1, SDMMC2_D2,
ETH_MII_TX_EN/ETH_RMII_TX_
EN, DCMI_D3, LCD_B3,
EVENTOUT
-
-
LPTIM1_IN1, HRTIM_EEV5,
SPI6_MISO,
USART6_RTS/USART6_DE,
SPDIFRX1_IN2, LCD_B4,
ETH_MII_TXD1/ETH_RMII_TXD1,
FMC_NE4, LCD_B1, EVENTOUT
-
-
TRACED0, LPTIM1_OUT,
HRTIM_EEV10, SPI6_SCK,
USART6_CTS/USART6_NSS,
ETH_MII_TXD0/ETH_RMII_TXD0,
FMC_A24, LCD_R0, EVENTOUT
-
-
-
129
A7
157
D8
PG14
I/O
FT_h
-
TRACED1, LPTIM1_ETR,
SPI6_MOSI, USART6_TX,
QUADSPI_BK2_IO3,
ETH_MII_TXD1/ETH_RMII_TXD1,
FMC_A25, LCD_B0, EVENTOUT
-
130
D7
158
-
VSS
S
-
-
-
-
-
131
C7
159
-
VDD
S
-
-
-
-
-
-
-
-
C8
PK3
I/O
FT
-
LCD_B4, EVENTOUT
-
-
-
-
-
B8
PK4
I/O
FT
-
LCD_B5, EVENTOUT
-
-
-
-
-
A8
PK5
I/O
FT
-
LCD_B6, EVENTOUT
-
-
-
-
-
C7
PK6
I/O
FT
-
LCD_B7, EVENTOUT
-
-
-
-
-
D7
PK7
I/O
FT
-
LCD_DE, EVENTOUT
-
-
-
H7
-
-
VSS
S
-
-
-
-
-
132
B7
160
D6
PG15
I/O
FT_h
-
USART6_CTS/USART6_NSS,
FMC_SDNCAS, DCMI_D13,
EVENTOUT
-
DS12556 Rev 6
75/336
93
Pin descriptions
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 7. STM32H750xB pin/ball definition (continued)
90
133
134
A9
161
162
C6
B7
PB3
(JTDO/TRACES
WO)
PB4(NJTRST)
I/O
I/O
I/O structure
Pin type
TFBGA240 +25
LQFP176
UFBGA176+25
A10
Pin name
(function after
reset)
FT
FT
Notes
89
LQFP144
LQFP100
Pin/ball name
Alternate functions
Additional
functions
-
JTDO/TRACESWO, TIM2_CH2,
HRTIM_FLT4,
SPI1_SCK/I2S1_CK,
SPI3_SCK/I2S3_CK, SPI6_SCK,
SDMMC2_D2, CRS_SYNC,
UART7_RX, EVENTOUT
-
-
NJTRST, TIM16_BKIN,
TIM3_CH1, HRTIM_EEV6,
SPI1_MISO/I2S1_SDI,
SPI3_MISO/I2S3_SDI,
SPI2_NSS/I2S2_WS, SPI6_MISO,
SDMMC2_D3, UART7_TX,
EVENTOUT
-
-
91
135
A6
163
A5
PB5
I/O
FT
-
TIM17_BKIN, TIM3_CH2,
HRTIM_EEV7, I2C1_SMBA,
SPI1_MOSI/I2S1_SDO,
I2C4_SMBA,
SPI3_MOSI/I2S3_SDO,
SPI6_MOSI, FDCAN2_RX,
OTG_HS_ULPI_D7,
ETH_PPS_OUT, FMC_SDCKE1,
DCMI_D10, UART5_RX,
EVENTOUT
-
-
H8
-
-
VSS
S
-
-
-
-
-
TIM16_CH1N, TIM4_CH1,
HRTIM_EEV8, I2C1_SCL, CEC,
I2C4_SCL, USART1_TX,
LPUART1_TX, FDCAN2_TX,
QUADSPI_BK1_NCS,
DFSDM1_DATIN5, FMC_SDNE1,
DCMI_D5, UART5_TX,
EVENTOUT
-
PVD_IN
VPP
92
136
B6
164
B5
PB6
I/O
FT_f
93
137
B5
165
C5
PB7
I/O
FT_fa
-
TIM17_CH1N, TIM4_CH2,
HRTIM_EEV9, I2C1_SDA,
I2C4_SDA, USART1_RX,
LPUART1_RX,
FDCAN2_TXFD_MODE,
DFSDM1_CKIN5, FMC_NL,
DCMI_VSYNC, EVENTOUT
94
138
D6
166
E8
BOOT0
I
B
-
-
76/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Pin descriptions
Table 7. STM32H750xB pin/ball definition (continued)
96
97
139
140
141
B4
A4
167
168
169
D5
D4
C4
PB8
PB9
PE0
I/O
I/O
I/O
I/O structure
Pin type
TFBGA240 +25
LQFP176
UFBGA176+25
A5
Pin name
(function after
reset)
FT_fh
FT_fh
FT_h
Notes
95
LQFP144
LQFP100
Pin/ball name
Alternate functions
Additional
functions
-
TIM16_CH1, TIM4_CH3,
DFSDM1_CKIN7, I2C1_SCL,
I2C4_SCL, SDMMC1_CKIN,
UART4_RX, FDCAN1_RX,
SDMMC2_D4, ETH_MII_TXD3,
SDMMC1_D4, DCMI_D6,
LCD_B6, EVENTOUT
-
-
TIM17_CH1, TIM4_CH4,
DFSDM1_DATIN7, I2C1_SDA,
SPI2_NSS/I2S2_WS, I2C4_SDA,
SDMMC1_CDIR, UART4_TX,
FDCAN1_TX, SDMMC2_D5,
I2C4_SMBA, SDMMC1_D5,
DCMI_D7, LCD_B7, EVENTOUT
-
-
LPTIM1_ETR, TIM4_ETR,
HRTIM_SCIN, LPTIM2_ETR,
UART8_RX,
FDCAN1_RXFD_MODE,
SAI2_MCLK_A, FMC_NBL0,
DCMI_D2, EVENTOUT
-
-
98
142
A3
170
B4
PE1
I/O
FT_h
-
LPTIM1_IN2, HRTIM_SCOUT,
UART8_TX,
FDCAN1_TXFD_MODE,
FMC_NBL1, DCMI_D3,
EVENTOUT
-
-
-
-
A7
VCAP
S
-
-
-
-
99
-
D5
-
-
VSS
S
-
-
-
-
-
143
C6
171
E7
PDR_ON
I
FT
-
-
-
-
-
-
-
A6
VDDLDO
S
-
-
-
-
100
144
C5
172
-
VDD
S
-
-
-
-
-
-
D4
173
A4
PI4
I/O
FT_h
-
TIM8_BKIN, SAI2_MCLK_A,
TIM8_BKIN_COMP12,
FMC_NBL2, DCMI_D5, LCD_B4,
EVENTOUT
-
-
-
C4
174
A3
PI5
I/O
FT_h
-
TIM8_CH1, SAI2_SCK_A,
FMC_NBL3, DCMI_VSYNC,
LCD_B5, EVENTOUT
-
-
-
C3
175
A2
PI6
I/O
FT_h
-
TIM8_CH2, SAI2_SD_A,
FMC_D28, DCMI_D6, LCD_B6,
EVENTOUT
-
-
-
C2
176
B3
PI7
I/O
FT_h
-
TIM8_CH3, SAI2_FS_A,
FMC_D29, DCMI_D7, LCD_B7,
EVENTOUT
-
DS12556 Rev 6
77/336
93
Pin descriptions
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 7. STM32H750xB pin/ball definition (continued)
LQFP100
LQFP144
UFBGA176+25
LQFP176
TFBGA240 +25
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Pin/ball name
Alternate functions
-
-
H9
-
-
VSS
S
-
-
-
-
-
-
K9
-
-
VSS
S
-
-
-
-
-
-
K10
-
M15
VSS
S
-
-
-
-
Additional
functions
1. When this pin/ball was previously configured as an oscillator, the oscillator function is kept during and after a reset. This is
valid for all resets except for power-on reset.
2. This ball should remain floating.
3. This ball should not remain floating. It can be connected to VSS or VDD. It is reserved for future use.
4. This ball should be connected to VSS.
5. Pxy_C and Pxy pins/balls are two separate pads (analog switch open). The analog switch is configured through a SYSCFG
register. Refer to the product reference manual for a detailed description of the switch configuration bits.
6. There is a direct path between Pxy_C and Pxy pins/balls, through an analog switch. Pxy alternate functions are available on
Pxy_C when the analog switch is closed. The analog switch is configured through a SYSCFG register. Refer to the product
reference manual for a detailed description of the switch configuration bits.
78/336
DS12556 Rev 6
AF0
AF1
AF2
AF3
AF4
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD
SYS
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1/
3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
PA0
-
TIM2_CH1/
TIM2_ETR
TIM5_CH1
TIM8_ETR
TIM15_BKIN
-
-
USART2_
CTS/
USART2_
NSS
UART4_TX
SDMMC2_
CMD
SAI2_SD_B
ETH_MII_
CRS
-
-
-
EVENTOUT
PA1
-
TIM2_CH2
TIM5_CH2
LPTIM3_
OUT
TIM15_
CH1N
-
-
USART2_
RTS/
USART2_
DE
UART4_RX
QUADSPI_
BK1_IO3
SAI2_MCLK
_B
ETH_MII_
RX_CLK/
ETH_RMII_
REF_CLK
-
-
LCD_R2
EVENTOUT
PA2
-
TIM2_CH3
TIM5_CH3
LPTIM4_
OUT
TIM15_CH1
-
-
USART2_
TX
SAI2_SCK_
B
-
-
ETH_MDIO
MDIOS_
MDIO
-
LCD_R1
EVENTOUT
PA3
-
TIM2_CH4
TIM5_CH4
LPTIM5_
OUT
TIM15_CH2
-
-
USART2_
RX
-
LCD_B2
OTG_HS_
ULPI_D0
ETH_MII_
COL
-
-
LCD_B5
EVENTOUT
PA4
D1
PWREN
-
TIM5_ETR
-
-
SPI1_NSS/
I2S1_WS
SPI3_NSS/
I2S3_WS
USART2_
CK
SPI6_NSS
-
-
-
OTG_HS_
SOF
DCMI_
HSYNC
LCD_
VSYNC
EVENTOUT
PA5
D2
PWREN
TIM2_CH1/
TIM2_ETR
-
TIM8_
CH1N
-
SPI1_SCK
/I2S1_CK
-
-
SPI6_SCK
-
OTG_HS_
ULPI_CK
-
-
-
LCD_R4
EVENTOUT
PA6
-
TIM1_BKIN
TIM3_CH1
TIM8_BKIN
-
SPI1_MISO
/I2S1_SDI
-
-
SPI6_MISO
TIM13_
CH1
TIM8_BKIN
_COMP12
MDIOS_
MDC
TIM1_BKIN
_COMP12
DCMI_PIX
CLK
LCD_G2
EVENTOUT
PA7
-
TIM1_CH1N
TIM3_CH2
TIM8_CH1
N
-
SPI1_MOSI
/I2S1_SDO
-
-
SPI6_MOSI
TIM14_
CH1
-
ETH_MII_
RX_DV/
ETH_RMII_
CRS_DV
FMC_SDN
WE
-
-
EVENTOUT
PA8
MCO1
TIM1_CH1
HRTIM_CH
B2
TIM8_BKIN
2
I2C3_SCL
-
-
USART1_
CK
-
-
OTG_FS_
SOF
UART7_RX
TIM8_BKIN
2_COMP12
LCD_B3
LCD_R6
EVENTOUT
PA9
-
TIM1_CH2
HRTIM_CH
C1
LPUART1_
TX
I2C3_SMBA
SPI2_SCK/
I2S2_CK
-
USART1_
TX
-
FDCAN1_
RXFD_
MODE
-
-
-
DCMI_D0
LCD_R5
EVENTOUT
PA10
-
TIM1_CH3
HRTIM_CH
C2
LPUART1_
RX
-
-
-
USART1_
RX
-
FDCAN1_
TXFD_
MODE
OTG_FS_ID
MDIOS_
MDIO
LCD_B4
DCMI_D1
LCD_B1
EVENTOUT
PA11
-
TIM1_CH4
HRTIM_CH
D1
LPUART1_
CTS
-
SPI2_NSS
/I2S2_WS
UART4_RX
USART1_
CTS/
USART1_
NSS
-
FDCAN1_
RX
OTG_FS_
DM
-
-
-
LCD_R4
EVENTOUT
PA12
-
TIM1_ETR
HRTIM_CH
D2
LPUART1_
RTS/
LPUART1_
DE
-
SPI2_SCK/
I2S2_CK
UART4_TX
USART1_
RTS/
USART1_
DE
SAI2_FS_B
FDCAN1_
TX
OTG_FS_
DP
-
-
-
LCD_R5
EVENTOUT
Port
Port A
DS12556 Rev 6
79/336
Pin descriptions
SYS
LPUART/
TIM8/
LPTIM2/3/4/
5/HRTIM1/
DFSDM1
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 8. Port A alternate functions
AF2
AF3
AF4
SYS
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4/
5/HRTIM1/
DFSDM1
PA13
JTMSSWDIO
-
-
PA14
JTCKSWCLK
-
PA15
JTDI
TIM2_CH1/
TIM2_ETR
Port A
Port
AF1
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1/
3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD
SYS
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
HRTIM_
FLT1
-
CEC
SPI1_NSS/
I2S1_WS
SPI3_NSS/
I2S3_WS
SPI6_NSS
UART4_
RTS/
UART4_
DE
-
-
UART7_TX
-
-
-
EVENTOUT
Port B
DS12556 Rev 6
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SPI1/2/3/4/5/
6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/3
/6/UART7/S
DMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD
/COMP
UART5/
LCD
SYS
PB0
-
TIM1_CH2N
TIM3_CH3
TIM8_
CH2N
-
-
DFSDM1_
CKOUT
-
UART4_
CTS
LCD_R3
OTG_HS_
ULPI_D1
ETH_MII_
RXD2
-
-
LCD_G1
EVENTOUT
PB1
-
TIM1_CH3N
TIM3_CH4
TIM8_
CH3N
-
-
DFSDM1_
DATIN1
-
-
LCD_R6
OTG_HS_
ULPI_D2
ETH_MII_
RXD3
-
-
LCD_G0
EVENTOUT
PB2
RTC_OUT
-
SAI1_D1
-
DFSDM1_
CKIN1
-
SAI1_SD_A
SPI3_
MOSI/I2S3_
SDO
SAI4_SD_
A
QUADSPI_
CLK
SAI4_D1
-
-
-
-
EVENTOUT
PB3
JTDO/TRA
CESWO
TIM2_CH2
HRTIM_
FLT4
-
-
SPI1_SCK/
I2S1_CK
SPI3_SCK/
I2S3_CK
-
SPI6_SCK
SDMMC2_
D2
CRS_SYNC
UART7_RX
-
-
-
EVENTOUT
PB4
NJTRST
TIM16_
BKIN
TIM3_CH1
HRTIM_
EEV6
-
SPI1_MISO/
I2S1_SDI
SPI3_MISO/
I2S3_SDI
SPI2_NSS/I
2S2_WS
SPI6_
MISO
SDMMC2_
D3
-
UART7_TX
-
-
-
EVENTOUT
PB5
-
TIM17_
BKIN
TIM3_CH2
HRTIM_
EEV7
I2C1_SMBA
SPI1_MOSI/
I2S1_SDO
I2C4_SMBA
SPI3_MOSI/
I2S3_SDO
SPI6_
MOSI
FDCAN2_
RX
OTG_HS_
ULPI_D7
ETH_PPS_
OUT
FMC_
SDCKE1
DCMI_
D10
UART5_
RX
EVENTOUT
PB6
-
TIM16_
CH1N
TIM4_CH1
HRTIM_
EEV8
I2C1_SCL
CEC
I2C4_SCL
USART1_
TX
LPUART1_
TX
FDCAN2_
TX
QUADSPI_
BK1_NCS
DFSDM1_
DATIN5
FMC_
SDNE1
DCMI_D5
UART5_
TX
EVENTOUT
PB7
-
TIM17_
CH1N
TIM4_CH2
HRTIM_
EEV9
I2C1_SDA
-
I2C4_SDA
USART1_
RX
LPUART1_
RX
FDCAN2_
TXFD_
MODE
-
DFSDM1_
CKIN5
FMC_NL
DCMI_
VSYNC
-
EVENTOUT
Port
AF1
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 9. Port B alternate functions
AF0
Pin descriptions
80/336
Table 8. Port A alternate functions (continued)
AF0
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SPI1/2/3/4/5/
6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/3
/6/UART7/S
DMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD
/COMP
UART5/
LCD
SYS
PB8
-
TIM16_CH1
TIM4_CH3
DFSDM1_
CKIN7
I2C1_SCL
-
I2C4_SCL
SDMMC1_
CKIN
UART4_RX
FDCAN1_
RX
SDMMC2_
D4
ETH_MII_
TXD3
SDMMC1_
D4
DCMI_D6
LCD_B6
EVENTOUT
PB9
-
TIM17_CH1
TIM4_CH4
DFSDM1_
DATIN7
I2C1_SDA
SPI2_NSS/
I2S2_WS
I2C4_SDA
SDMMC1_
CDIR
UART4_TX
FDCAN1_
TX
SDMMC2_
D5
I2C4_
SMBA
SDMMC1_
D5
DCMI_D7
LCD_B7
EVENTOUT
PB10
-
TIM2_CH3
HRTIM_
SCOUT
LPTIM2_IN
1
I2C2_SCL
SPI2_SCK/
I2S2_CK
DFSDM1_
DATIN7
USART3_
TX
-
QUADSPI_
BK1_NCS
OTG_HS_
ULPI_D3
ETH_MII_
RX_ER
-
-
LCD_G4
EVENTOUT
PB11
-
TIM2_CH4
HRTIM_
SCIN
LPTIM2_
ETR
I2C2_SDA
-
DFSDM1_
CKIN7
USART3_
RX
-
-
OTG_HS_
ULPI_D4
ETH_MII_
TX_EN/
ETH_RMII_
TX_EN
-
-
LCD_G5
EVENTOUT
PB12
-
TIM1_BKIN
-
-
I2C2_SMBA
SPI2_NSS/
I2S2_WS
DFSDM1_
DATIN1
USART3_
CK
-
FDCAN2_
RX
OTG_HS_
ULPI_D5
ETH_MII_
TXD0/ETH_
RMII_TXD0
OTG_HS_
ID
TIM1_
BKIN_
COMP12
UART5_
RX
EVENTOUT
PB13
-
TIM1_CH1N
-
LPTIM2_
OUT
-
SPI2_SCK/
I2S2_CK
DFSDM1_
CKIN1
USART3_
CTS/
USART3_
NSS
-
FDCAN2_
TX
OTG_HS_
ULPI_D6
ETH_MII_
TXD1/ETH_
RMII_TXD1
-
-
UART5_
TX
EVENTOUT
PB14
-
TIM1_CH2N
TIM12_
CH1
TIM8_
CH2N
USART1_TX
SPI2_MISO/
I2S2_SDI
DFSDM1_
DATIN2
USART3_
RTS/
USART3_
DE
UART4_
RTS/
UART4_
DE
SDMMC2_
D0
-
-
OTG_HS_
DM
-
-
EVENTOUT
PB15
RTC_
REFIN
TIM1_CH3N
TIM12_
CH2
TIM8_
CH3N
USART1_RX
SPI2_MOSI/
I2S2_SDO
DFSDM1_
CKIN2
-
UART4_
CTS
SDMMC2_
D1
-
-
OTG_HS_
DP
-
-
EVENTOUT
DS12556 Rev 6
Port B
Port
AF1
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 9. Port B alternate functions (continued)
AF0
Pin descriptions
81/336
AF0
AF2
AF3
AF4
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD
SYS
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
PC0
-
-
-
DFSDM1_
CKIN0
-
-
DFSDM1_
DATIN4
-
SAI2_FS_B
-
OTG_HS_
ULPI_STP
-
FMC_
SDNWE
-
LCD_R5
EVENTOUT
PC1
TRACED0
-
SAI1_D1
DFSDM1_
DATIN0
DFSDM1_
CKIN4
SPI2_
MOSI/I2S2
_SDO
SAI1_SD_A
-
SAI4_SD_
A
SDMMC2_
CK
SAI4_D1
ETH_MDC
MDIOS_
MDC
-
-
EVENTOUT
PC2
CDSLEEP
-
-
DFSDM1_
CKIN1
-
SPI2_
MISO/I2S2
_SDI
DFSDM1_
CKOUT
-
-
-
OTG_HS_
ULPI_DIR
ETH_MII_
TXD2
FMC_SDNE
0
-
-
EVENTOUT
PC3
CSLEEP
-
-
DFSDM1_
DATIN1
-
SPI2_
MOSI/I2S2
_SDO
-
-
-
-
OTG_HS_
ULPI_NXT
ETH_MII_
TX_CLK
FMC_SDCK
E0
-
-
EVENTOUT
PC4
-
-
-
DFSDM1_
CKIN2
-
I2S1_
MCK
-
-
-
SPDIFRX1
_IN3
-
ETH_MII_
RXD0/ETH_
RMII_RXD0
FMC_SDNE
0
-
-
EVENTOUT
PC5
-
-
SAI1_D3
DFSDM1_
DATIN2
-
-
-
-
SPDIFRX1
_IN4
SAI4_D3
ETH_MII_
RXD1/ETH_
RMII_RXD1
FMC_SDCK
E0
COMP1_
OUT
-
EVENTOUT
PC6
-
HRTIM_CH
A1
TIM3_CH1
TIM8_CH1
DFSDM1_
CKIN3
I2S2_
MCK
-
USART6_
TX
SDMMC1_
D0DIR
FMC_
NWAIT
SDMMC2_
D6
-
SDMMC1_
D6
DCMI_D0
LCD_
HSYNC
EVENTOUT
PC7
TRGIO
HRTIM_CH
A2
TIM3_CH2
TIM8_CH2
DFSDM1_
DATIN3
-
I2S3_MCK
USART6_
RX
SDMMC1_
D123DIR
FMC_NE1
SDMMC2_
D7
SWPMI_TX
SDMMC1_
D7
DCMI_D1
LCD_G6
EVENTOUT
PC8
TRACED1
HRTIM_CH
B1
TIM3_CH3
TIM8_CH3
-
-
-
USART6_
CK
UART5_
RTS/
UART5_
DE
FMC_NE2/
FMC_NCE
-
SWPMI_RX
SDMMC1_
D0
DCMI_D2
-
EVENTOUT
PC9
MCO2
-
TIM3_CH4
TIM8_CH4
I2C3_SDA
I2S_CKIN
-
-
UART5_
CTS
QUADSPI_
BK1_IO0
LCD_G3
SWPMI_
SUSPEND
SDMMC1_
D1
DCMI_D3
LCD_B2
EVENTOUT
PC10
-
-
HRTIM_
EEV1
DFSDM1_
CKIN5
-
-
SPI3_SCK/
I2S3_CK
USART3_
TX
UART4_TX
QUADSPI_
BK1_IO1
-
-
SDMMC1_
D2
DCMI_D8
LCD_R2
EVENTOUT
PC11
-
-
HRTIM_
FLT2
DFSDM1_
DATIN5
-
-
SPI3_MISO/
I2S3_SDI
USART3_
RX
UART4_RX
QUADSPI_
BK2_NCS
-
-
SDMMC1_
D3
DCMI_D4
-
EVENTOUT
PC12
TRACED3
-
HRTIM_
EEV2
-
-
-
SPI3_MOSI/
I2S3_SDO
USART3_
CK
UART5_TX
-
-
-
SDMMC1_
CK
DCMI_D9
-
EVENTOUT
PC13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
SYS
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
Port
Port C
AF1
Pin descriptions
82/336
Table 10. Port C alternate functions
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD
SYS
PC14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
PC15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
AF0
AF1
AF2
AF3
AF4
SYS
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
PD0
-
-
-
PD1
-
-
PD2
TRACED2
PD3
Port C
Port
AF1
Table 11. Port D alternate functions
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD
SYS
DFSDM1_
CKIN6
-
-
SAI3_SCK_
A
-
UART4_RX
FDCAN1_
RX
-
-
FMC_D2/
FMC_DA2
-
-
EVENTOUT
-
DFSDM1_
DATIN6
-
-
SAI3_SD_A
-
UART4_TX
FDCAN1_
TX
-
-
FMC_D3/
FMC_DA3
-
-
EVENTOUT
-
TIM3_ETR
-
-
-
-
-
UART5_RX
-
-
-
SDMMC1_
CMD
DCMI_D11
-
EVENTOUT
-
-
-
DFSDM1_
CKOUT
-
SPI2_SCK/
I2S2_CK
-
USART2_
CTS/
USART2_
NSS
-
-
-
-
FMC_CLK
DCMI_D5
LCD_G7
EVENTOUT
PD4
-
-
HRTIM_
FLT3
-
-
-
SAI3_FS_A
USART2_
RTS/
USART2_
DE
-
FDCAN1_R
XFD_MODE
-
-
FMC_NOE
-
-
EVENTOUT
PD5
-
-
HRTIM_
EEV3
-
-
-
-
USART2_
TX
-
FDCAN1_T
XFD_MODE
-
-
FMC_NWE
-
-
EVENTOUT
PD6
-
-
SAI1_D1
DFSDM1_
CKIN4
DFSDM1_
DATIN1
SPI3_
MOSI/I2S3
_SDO
SAI1_SD_A
USART2_
RX
SAI4_SD_
A
FDCAN2_R
XFD_MODE
SAI4_D1
SDMMC2_
CK
FMC_
NWAIT
DCMI_D10
LCD_B2
EVENTOUT
PD7
-
-
-
DFSDM1_
DATIN4
-
SPI1_
MOSI/I2S1
_SDO
DFSDM1_
CKIN1
USART2_
CK
-
SPDIFRX1_
IN1
-
SDMMC2_
CMD
FMC_NE1
-
-
EVENTOUT
Pin descriptions
AF6
Port
Port D
DS12556 Rev 6
83/336
AF5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 10. Port C alternate functions (continued)
AF0
AF2
AF3
AF4
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD
SYS
PD8
-
-
-
DFSDM1_
CKIN3
-
-
SAI3_SCK_
B
USART3_
TX
-
SPDIFRX1_
IN2
-
-
FMC_D13/
FMC_DA13
-
-
EVENTOUT
PD9
-
-
-
DFSDM1_
DATIN3
-
-
SAI3_SD_B
USART3_
RX
-
FDCAN2_R
XFD_MODE
-
-
FMC_D14/
FMC_DA14
-
-
EVENTOUT
PD10
-
-
-
DFSDM1_
CKOUT
-
-
SAI3_FS_B
USART3_
CK
-
FDCAN2_T
XFD_MODE
-
-
FMC_D15/
FMC_DA15
-
LCD_B3
EVENTOUT
PD11
-
-
-
LPTIM2_
IN2
I2C4_SMBA
-
-
USART3_
CTS/
USART3_N
SS
-
QUADSPI_
BK1_IO0
SAI2_SD_A
-
FMC_A16
-
-
EVENTOUT
PD12
-
LPTIM1_IN1
TIM4_CH1
LPTIM2_
IN1
I2C4_SCL
-
-
USART3_
RTS/
USART3_
DE
-
QUADSPI_
BK1_IO1
SAI2_FS_A
-
FMC_A17
-
-
EVENTOUT
PD13
-
LPTIM1_
OUT
TIM4_CH2
-
I2C4_SDA
-
-
-
QUADSPI_
BK1_IO3
SAI2_SCK_
A
-
FMC_A18
-
-
EVENTOUT
PD14
-
-
TIM4_CH3
-
-
-
SAI3_MCLK
_B
-
UART8_
CTS
-
-
-
FMC_D0/
FMC_DA0
-
-
EVENTOUT
PD15
-
-
TIM4_CH4
-
-
-
SAI3_MCLK
_A
-
UART8_
RTS/
UART8_
DE
-
-
-
FMC_D1/
FMC_DA1
-
-
EVENTOUT
Port D
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
AF5
Port
AF1
Pin descriptions
84/336
Table 11. Port D alternate functions (continued)
AF0
AF0
AF2
AF3
AF4
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD
SYS
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
PE0
-
LPTIM1_
ETR
TIM4_ETR
HRTIM_
SCIN
LPTIM2_
ETR
-
-
-
UART8_RX
FDCAN1_
RXFD_
MODE
SAI2_
MCLK_A
-
FMC_NBL0
DCMI_D2
-
EVENTOUT
PE1
-
LPTIM1_IN2
-
HRTIM_
SCOUT
-
-
-
-
UART8_TX
FDCAN1_
TXFD_
MODE
-
-
FMC_NBL1
DCMI_D3
-
EVENTOUT
PE2
TRACE
CLK
-
SAI1_CK1
-
-
SPI4_SCK
SAI1_MCLK
_A
-
SAI4_
MCLK_A
QUADSPI_
BK1_IO2
SAI4_CK1
ETH_MII_
TXD3
FMC_A23
-
-
EVENTOUT
PE3
TRACED0
-
-
-
TIM15_BKIN
-
SAI1_SD_B
-
SAI4_SD_
B
-
-
-
FMC_A19
-
-
EVENTOUT
PE4
TRACED1
-
SAI1_D2
DFSDM1_
DATIN3
TIM15_CH1
N
SPI4_NSS
SAI1_FS_A
-
SAI4_FS_A
-
SAI4_D2
-
FMC_A20
DCMI_D4
LCD_B0
EVENTOUT
PE5
TRACED2
-
SAI1_CK2
DFSDM1_
CKIN3
TIM15_CH1
SPI4_
MISO
SAI1_SCK_
A
-
SAI4_SCK
_A
-
SAI4_CK2
-
FMC_A21
DCMI_D6
LCD_G0
EVENTOUT
PE6
TRACED3
TIM1_
BKIN2
SAI1_D1
-
TIM15_CH2
SPI4_
MOSI
SAI1_SD_A
-
SAI4_SD_
A
SAI4_D1
SAI2_
MCLK_B
TIM1_BKIN
2_COMP12
FMC_A22
DCMI_D7
LCD_G1
EVENTOUT
PE7
-
TIM1_ETR
-
DFSDM1_
DATIN2
-
-
-
UART7_RX
-
-
QUADSPI_
BK2_IO0
-
FMC_D4/
FMC_DA4
-
-
EVENTOUT
PE8
-
TIM1_CH1N
-
DFSDM1_
CKIN2
-
-
-
UART7_TX
-
-
QUADSPI_
BK2_IO1
-
FMC_D5/
FMC_DA5
COMP2_
OUT
-
EVENTOUT
PE9
-
TIM1_CH1
-
DFSDM1_
CKOUT
-
-
-
UART7_
RTS/
UART7_
DE
-
-
QUADSPI_
BK2_IO2
-
FMC_D6/
FMC_DA6
-
-
EVENTOUT
PE10
-
TIM1_CH2N
-
DFSDM1_
DATIN4
-
-
-
UART7_
CTS
-
-
QUADSPI_
BK2_IO3
-
FMC_D7/
FMC_DA7
-
-
EVENTOUT
PE11
-
TIM1_CH2
-
DFSDM1_
CKIN4
-
SPI4_NSS
-
-
-
-
SAI2_SD_B
-
FMC_D8/
FMC_DA8
-
LCD_G3
EVENTOUT
PE12
-
TIM1_CH3N
-
DFSDM1_
DATIN5
-
SPI4_SCK
-
-
-
-
SAI2_SCK_
B
-
FMC_D9/
FMC_DA9
COMP1_
OUT
LCD_B4
EVENTOUT
PE13
-
TIM1_CH3
-
DFSDM1_
CKIN5
-
SPI4_
MISO
-
-
-
-
SAI2_FS_B
-
FMC_D10/
FMC_DA10
COMP2_
OUT
LCD_DE
EVENTOUT
DS12556 Rev 6
85/336
Pin descriptions
SYS
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
Port
Port E
AF1
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 12. Port E alternate functions
AF2
AF3
AF4
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
PE14
-
TIM1_CH4
-
PE15
-
TIM1_BKIN
-
Port E
Port
AF1
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD
SYS
-
-
SPI4_
MOSI
-
-
-
-
SAI2_
MCLK_B
-
FMC_D11/
FMC_DA11
-
LCD_CLK
EVENTOUT
-
-
-
-
-
-
-
-
FMC_D12/
FMC_DA12
TIM1_BKIN
_COMP12/
COMP_
TIM1_BKIN
LCD_R7
EVENTOUT
Pin descriptions
86/336
Table 12. Port E alternate functions (continued)
AF0
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
DS12556 Rev 6
AF0
AF2
AF3
AF4
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD
SYS
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
PF0
-
-
-
-
I2C2_SDA
-
-
-
-
-
-
-
FMC_A0
-
-
EVENTOUT
PF1
-
-
-
-
I2C2_SCL
-
-
-
-
-
-
-
FMC_A1
-
-
EVENTOUT
PF2
-
-
-
-
I2C2_SMBA
-
-
-
-
-
-
-
FMC_A2
-
-
EVENTOUT
PF3
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A3
-
-
EVENTOUT
PF4
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A4
-
-
EVENTOUT
PF5
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A5
-
-
EVENTOUT
PF6
-
TIM16_CH1
-
-
-
SPI5_NSS
SAI1_SD_B
UART7_RX
SAI4_SD_
B
QUADSPI_
BK1_IO3
-
-
-
-
-
EVENTOUT
PF7
-
TIM17_CH1
-
-
-
SPI5_SCK
SAI1_MCLK
_B
UART7_TX
SAI4_
MCLK_B
QUADSPI_
BK1_IO2
-
-
-
-
-
EVENTOUT
PF8
-
TIM16_
CH1N
-
-
-
SPI5_
MISO
SAI1_SCK_
B
UART7_
RTS/
UART7_
DE
SAI4_SCK
_B
TIM13_
CH1
QUADSPI_
BK1_IO0
-
-
-
-
EVENTOUT
PF9
-
TIM17_
CH1N
-
-
-
SPI5_
MOSI
SAI1_FS_B
UART7_
CTS
SAI4_FS_B
TIM14_CH
1
QUADSPI_
BK1_IO1
-
-
-
-
EVENTOUT
PF10
-
TIM16_
BKIN
SAI1_D3
-
-
-
-
-
-
QUADSPI_
CLK
SAI4_D3
-
-
DCMI_D11
LCD_DE
EVENTOUT
PF11
-
-
-
-
-
SPI5_
MOSI
-
-
-
-
SAI2_SD_B
-
FMC_
SDNRAS
DCMI_D12
-
EVENTOUT
PF12
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A6
-
-
EVENTOUT
PF13
-
-
-
DFSDM1_
DATIN6
I2C4_SMBA
-
-
-
-
-
-
-
FMC_A7
-
-
EVENTOUT
PF14
-
-
-
DFSDM1_
CKIN6
I2C4_SCL
-
-
-
-
-
-
-
FMC_A8
-
-
EVENTOUT
PF15
-
-
-
-
I2C4_SDA
-
-
-
-
-
-
-
FMC_A9
-
-
EVENTOUT
DS12556 Rev 6
87/336
Pin descriptions
SYS
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
Port
Port F
AF1
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 13. Port F alternate functions
AF0
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/4/TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/UART7
/SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD
/COMP
UART5/
LCD
SYS
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
-
-
-
-
-
-
-
-
FMC_A10
-
-
EVENT
-OUT
-
-
-
-
-
-
-
-
-
FMC_A11
-
-
EVENT
-OUT
-
TIM8_BKIN
-
-
-
-
-
-
-
TIM8_BKIN_
COMP12
FMC_A12
-
-
EVENT
-OUT
-
-
TIM8_
BKIN2
-
-
-
-
-
-
-
TIM8_BKIN2
_COMP12
FMC_A13
-
-
EVENT
-OUT
-
TIM1_
BKIN2
-
-
-
-
-
-
-
-
-
TIM1_BKIN2
_COMP12
FMC_A14/
FMC_BA0
-
-
EVENT
-OUT
PG5
-
TIM1_ETR
-
-
-
-
-
-
-
-
-
-
FMC_A15/
FMC_BA1
-
-
EVENT
-OUT
PG6
-
TIM17_
BKIN
HRTIM_
CHE1
-
-
-
-
-
-
-
QUADSPI_
BK1_NCS
-
FMC_NE3
DCMI_
D12
LCD_
R7
EVENT
-OUT
PG7
-
-
HRTIM_
CHE2
-
-
-
SAI1_
MCLK_A
USART6_
CK
-
-
-
-
FMC_INT
DCMI_
D13
LCD_
CLK
EVENT
-OUT
PG8
-
-
-
TIM8_ETR
-
SPI6_NSS
-
USART6_
RTS/
USART6_
DE
SPDIFRX1
_IN3
-
-
ETH_PPS_
OUT
FMC_
SDCLK
-
LCD_
G7
EVENT
-OUT
PG9
-
-
-
-
-
SPI1_
MISO/I2S1
_SDI
-
USART6_
RX
SPDIFRX1
_IN4
QUADSPI_
BK2_IO2
SAI2_FS_B
-
FMC_NE2/
FMC_NCE
DCMI_
VSYNC
-
EVENT
-OUT
PG10
-
-
HRTIM_
FLT5
-
-
SPI1_NSS/
I2S1_WS
-
-
-
LCD_G3
SAI2_SD_B
-
FMC_NE3
DCMI_D2
LCD_
B2
EVENT
-OUT
PG11
-
LPTIM1_IN2
HRTIM_
EEV4
-
-
SPI1_SCK/
I2S1_CK
-
-
SPDIFRX1
_IN1
-
SDMMC2_D2
ETH_MII_
TX_EN/
ETH_RMII_
TX_EN
-
DCMI_D3
LCD_
B3
EVENT
-OUT
PG12
-
LPTIM1_IN1
HRTIM_
EEV5
-
-
SPI6_
MISO
USART6_
RTS/
USART6_
DE
SPDIFRX1
_IN2
LCD_B4
-
ETH_MII_
TXD1/ETH_
RMII_TXD1
FMC_NE4
-
LCD_
B1
EVENT
-OUT
PG13
TRACED0
LPTIM1_
OUT
HRTIM_
EEV10
-
-
SPI6_SCK
USART6_
CTS/
USART6_
NSS
-
-
-
ETH_MII_
TXD0/ETH_
RMII_TXD0
FMC_A24
-
LCD_
R0
EVENT
-OUT
SYS
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
PG0
-
-
-
-
PG1
-
-
-
PG2
-
-
PG3
-
PG4
DS12556 Rev 6
-
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
Port
Port G
AF1
Pin descriptions
88/336
Table 14. Port G alternate functions
AF2
AF3
AF4
SYS
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
PG14
TRACED1
LPTIM1_
ETR
-
PG15
-
-
-
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SAI2/4/TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/UART7
/SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/
DCMI/LCD
/COMP
UART5/
LCD
SYS
-
-
SPI6_
MOSI
-
USART6_
TX
QUADSPI_
BK2_IO3
-
ETH_MII_
TXD1/ETH_
RMII_TXD1
FMC_A25
-
LCD_
B0
EVENT
-OUT
-
-
-
-
USART6_
CTS/
USART6_
NSS
-
-
-
FMC_
SDNCAS
DCMI_
D13
-
EVENT
-OUT
Port G
Port
AF1
-
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 14. Port G alternate functions (continued)
AF0
Pin descriptions
89/336
AF0
AF2
AF3
AF4
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD
SYS
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
PH0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
PH1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
PH2
-
LPTIM1_IN2
-
-
-
-
-
-
-
QUADSPI_
BK2_IO0
SAI2_SCK_
B
ETH_MII_
CRS
FMC_
SDCKE0
-
LCD_R0
EVENTOUT
PH3
-
-
-
-
-
-
-
-
-
QUADSPI_
BK2_IO1
SAI2_
MCLK_B
ETH_MII_
COL
FMC_
SDNE0
-
LCD_R1
EVENTOUT
PH4
-
-
-
-
I2C2_SCL
-
-
-
-
LCD_G5
OTG_HS_
ULPI_NXT
-
-
-
LCD_G4
EVENTOUT
PH5
-
-
-
-
I2C2_SDA
SPI5_NSS
-
-
-
-
-
-
FMC_
SDNWE
-
-
EVENTOUT
PH6
-
-
TIM12_
CH1
-
I2C2_SMBA
SPI5_SCK
-
-
-
-
-
ETH_MII_
RXD2
FMC_
SDNE1
DCMI_D8
-
EVENTOUT
PH7
-
-
-
-
I2C3_SCL
SPI5_
MISO
-
-
-
-
-
ETH_MII_
RXD3
FMC_
SDCKE1
DCMI_D9
-
EVENTOUT
PH8
-
-
TIM5_ETR
-
I2C3_SDA
-
-
-
-
-
-
-
FMC_D16
DCMI_
HSYNC
LCD_R2
EVENTOUT
PH9
-
-
TIM12_
CH2
-
I2C3_SMBA
-
-
-
-
-
-
-
FMC_D17
DCMI_D0
LCD_R3
EVENTOUT
PH10
-
-
TIM5_CH1
-
I2C4_SMBA
-
-
-
-
-
-
-
FMC_D18
DCMI_D1
LCD_R4
EVENTOUT
PH11
-
-
TIM5_CH2
-
I2C4_SCL
-
-
-
-
-
-
-
FMC_D19
DCMI_D2
LCD_R5
EVENTOUT
PH12
-
-
TIM5_CH3
-
I2C4_SDA
-
-
-
-
-
-
-
FMC_D20
DCMI_D3
LCD_R6
EVENTOUT
PH13
-
-
-
TIM8_
CH1N
-
-
-
-
UART4_TX
FDCAN1_
TX
-
-
FMC_D21
-
LCD_G2
EVENTOUT
PH14
-
-
-
TIM8_
CH2N
-
-
-
-
UART4_RX
FDCAN1_
RX
-
-
FMC_D22
DCMI_D4
LCD_G3
EVENTOUT
PH15
-
-
-
TIM8_
CH3N
-
-
-
-
-
FDCAN1_
TXFD_
MODE
-
-
FMC_D23
DCMI_D11
LCD_G4
EVENTOUT
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
SYS
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
Port
Port H
AF1
Pin descriptions
90/336
Table 15. Port H alternate functions
AF0
AF2
AF3
AF4
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD
SYS
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
PI0
-
-
TIM5_CH4
-
-
SPI2_NSS/
I2S2_WS
-
-
-
FDCAN1_
RXFD_
MODE
-
-
FMC_D24
DCMI_D13
LCD_G5
EVENTOUT
PI1
-
-
-
TIM8_
BKIN2
-
SPI2_SCK/
I2S2_CK
-
-
-
-
-
TIM8_BKIN
2_COMP12
FMC_D25
DCMI_D8
LCD_G6
EVENTOUT
PI2
-
-
-
TIM8_CH4
-
SPI2_
MISO/I2S2
_SDI
-
-
-
-
-
-
FMC_D26
DCMI_D9
LCD_G7
EVENTOUT
PI3
-
-
-
TIM8_ETR
-
SPI2_
MOSI/I2S2
_SDO
-
-
-
-
-
-
FMC_D27
DCMI_D10
-
EVENTOUT
PI4
-
-
-
TIM8_BKIN
-
-
-
-
-
-
SAI2_
MCLK_A
TIM8_BKIN
_COMP12
FMC_NBL2
DCMI_D5
LCD_B4
EVENTOUT
PI5
-
-
-
TIM8_CH1
-
-
-
-
-
-
SAI2_SCK_
A
-
FMC_NBL3
DCMI_
VSYNC
LCD_B5
EVENTOUT
PI6
-
-
-
TIM8_CH2
-
-
-
-
-
-
SAI2_SD_A
-
FMC_D28
DCMI_D6
LCD_B6
EVENTOUT
PI7
-
-
-
TIM8_CH3
-
-
-
-
-
-
SAI2_FS_A
-
FMC_D29
DCMI_D7
LCD_B7
EVENTOUT
PI8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENTOUT
PI9
-
-
-
-
-
-
-
-
UART4_RX
FDCAN1_
RX
-
-
FMC_D30
-
LCD_
VSYNC
EVENTOUT
PI10
-
-
-
-
-
-
-
-
-
FDCAN1_
RXFD_
MODE
-
ETH_MII_
RX_ER
FMC_D31
-
LCD_
HSYNC
EVENTOUT
PI11
-
-
-
-
-
-
-
-
-
LCD_G6
OTG_HS_
ULPI_DIR
-
-
-
-
EVENTOUT
PI12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_
HSYNC
EVENTOUT
PI13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_
VSYNC
EVENTOUT
PI14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_CLK
EVENTOUT
PI15
-
-
-
-
-
-
-
-
-
LCD_G2
-
-
-
-
LCD_R0
EVENTOUT
DS12556 Rev 6
91/336
Pin descriptions
SYS
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
Port
Port I
AF1
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 16. Port I alternate functions
AF0
AF2
AF3
AF4
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD
SYS
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
TIM1/2/16/
17/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
PJ0
-
-
-
-
-
-
-
-
-
LCD_R7
-
-
-
-
LCD_R1
EVENTOUT
PJ1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R2
EVENTOUT
PJ2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R3
EVENTOUT
PJ3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R4
EVENTOUT
PJ4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R5
EVENTOUT
PJ5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R6
EVENTOUT
PJ6
-
-
-
TIM8_CH2
-
-
-
-
-
-
-
-
-
-
LCD_R7
EVENTOUT
PJ7
TRGIN
-
-
TIM8_
CH2N
-
-
-
-
-
-
-
-
-
-
LCD_G0
EVENTOUT
PJ8
-
TIM1_CH3N
-
TIM8_CH1
-
-
-
-
UART8_TX
-
-
-
-
-
LCD_G1
EVENTOUT
PJ9
-
TIM1_CH3
-
TIM8_
CH1N
-
-
-
-
UART8_RX
-
-
-
-
-
LCD_G2
EVENTOUT
PJ10
-
TIM1_CH2N
-
TIM8_CH2
-
SPI5_
MOSI
-
-
-
-
-
-
-
-
LCD_G3
EVENTOUT
PJ11
-
TIM1_CH2
-
TIM8_
CH2N
-
SPI5_
MISO
-
-
-
-
-
-
-
-
LCD_G4
EVENTOUT
PJ12
TRGOUT
-
-
-
-
-
-
-
-
LCD_G3
-
-
-
-
LCD_B0
EVENTOUT
PJ13
-
-
-
-
-
-
-
-
-
LCD_B4
-
-
-
-
LCD_B1
EVENTOUT
PJ14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B2
EVENTOUT
PJ15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B3
EVENTOUT
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
SYS
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
Port
Port J
AF1
Pin descriptions
92/336
Table 17. Port J alternate functions
AF0
AF2
AF3
AF4
I2C1/2/3/4/
USART1/
TIM15/
LPTIM2/
DFSDM1/
CEC
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
SAI2/4/
TIM8/
QUADSPI/
SDMMC2/
OTG1_HS/
OTG2_FS/
LCD
I2C4/
UART7/
SWPMI1/
TIM1/8/
DFSDM1/
SDMMC2/
MDIOS/
ETH
TIM1/8/FMC
/SDMMC1/
MDIOS/
OTG1_FS/
LCD
TIM1/DCMI
/LCD/
COMP
UART5/
LCD
SYS
SPI1/2/3/4/
5/6/CEC
SPI2/3/SAI1
/3/I2C4/
UART4/
DFSDM1
SPI2/3/6/
USART1/2/
3/6/UART7/
SDMMC1
SPI6/SAI2/
4/UART4/5/
8/LPUART/
SDMMC1/
SPDIFRX1
SAI4/
FDCAN1/2/
TIM13/14/
QUADSPI/
FMC/
SDMMC2/
LCD/
SPDIFRX1
SYS
TIM1/2/16/1
7/LPTIM1/
HRTIM1
SAI1/TIM3/
4/5/12/
HRTIM1
LPUART/
TIM8/
LPTIM2/3/4
/5/HRTIM1/
DFSDM1
PK0
-
TIM1_CH1N
-
TIM8_CH3
-
SPI5_SCK
-
-
-
-
-
-
-
-
LCD_G5
EVENTOUT
PK1
-
TIM1_CH1
-
TIM8_
CH3N
-
SPI5_NSS
-
-
-
-
-
-
-
-
LCD_G6
EVENTOUT
PK2
-
TIM1_BKIN
-
TIM8_BKIN
-
-
-
-
-
-
TIM8_BKIN
_COMP12
TIM1_BKIN
_COMP12
-
-
LCD_G7
EVENTOUT
PK3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B4
EVENTOUT
PK4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B5
EVENTOUT
PK5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B6
EVENTOUT
PK6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B7
EVENTOUT
PK7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_DE
EVENTOUT
Port
Port K
AF1
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 18. Port K alternate functions
Pin descriptions
93/336
Electrical characteristics (rev Y)
6
6.1
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of junction temperature, supply voltage and frequencies by tests in production on
100% of the devices with an junction temperature at TJ = 25 °C and TJ = TJmax (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean±3σ).
6.1.2
Typical values
Unless otherwise specified, typical data are based on TJ = 25 °C, VDD = 3.3 V (for the
1.7 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
6.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 9.
6.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 10.
Figure 9. Pin loading conditions
Figure 10. Pin input voltage
MCU pin
MCU pin
C = 50 pF
VIN
MS19011V2
94/336
DS12556 Rev 6
MS19010V2
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
6.1.6
Electrical characteristics (rev Y)
Power supply scheme
Figure 11. Power supply scheme
VDD50USB
100 nF
100 nF
VDD33USB
1μF
VDD33USB
USB
IOs
USB
regulator
Level shifter
Power
switch
VSS
IOs
N(1) x 100 nF
+ 1 x 4.7 μF
VDD
D3 domain
(System
logic,
EXTI,
IO
logic Peripherals,
RAM)
D2 domain
(peripherals,
RAM)
D1 domain
(CPU, peripherals,
RAM)
VDD domain
VBAT
charging
HSI, LSI,
CSI, HSI48,
HSE, PLLs
Backup domain
Backup VBKP
regulator
VSW
VBAT
Power switch
Power switch
LSE, RTC,
Wakeup logic,
backup
IO
registers,
logic
Reset
BKUP
IOs
VREF
100 nF + 1 x 1 μF
100 nF + 1 x 1 μF
VDDA
VDDA
Flash
VSS
VDD
VBAT
1.2 to 3.6V
VSS
Core domain (VCORE)
Voltage
regulator
VDDLDO
4.7μF
2 x 2.2μF
VDDLDO
VCAP
Power
switch
VSS
VDD50USB
VSS
Analog domain
REF_BUF
VREF+
ADC, DAC
VREF+
VREF-
VREF-
Backup
RAM
VSS
OPAMP,
Comparator
VSSA
MSv46116V5
1. N corresponds to the number of VDD pins available on the package.
2. A tolerance of +/- 20% is acceptable on decoupling capacitors.
Caution:
Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure good operation of the
DS12556 Rev 6
95/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
6.1.7
Current consumption measurement
Figure 12. Current consumption measurement scheme
IDD_VBAT
VBAT
IDD
VDD
VDDA
ai14126
6.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 19: Voltage characteristics,
Table 20: Current characteristics, and Table 21: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and the functional operation
of the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are
available on demand.
Table 19. Voltage characteristics (1)
Symbols
VDDX - VSS
VIN(2)
Ratings
Min
Max
Unit
−0.3
4.0
V
Input voltage on FT_xxx pins
VSS−0.3
Min(VDD, VDDA,
VDD33USB, VBAT)
+4.0(3)(4)
V
Input voltage on TT_xx pins
VSS-0.3
4.0
V
Input voltage on BOOT0 pin
VSS
9.0
V
VSS-0.3
4.0
V
-
50
mV
-
50
mV
External main supply voltage (including VDD,
VDDLDO, VDDA, VDD33USB, VBAT)
Input voltage on any other pins
|∆VDDX|
Variations between different VDDX power pins
of the same domain
|VSSx-VSS| Variations between all the different ground pins
1. All main power (VDD, VDDA, VDD33USB, VBAT) and ground (VSS, VSSA) pins must always be connected to
the external power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 57 for the maximum allowed injected current
values.
96/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
3. This formula has to be applied on power supplies related to the IO structure described by the pin definition
table.
4. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled.
Table 20. Current characteristics
Symbols
Ratings
Max
ΣIVDD
Total current into sum of all VDD power lines (source)(1)
620
ΣIVSS
(sink)(1)
620
Total current out of sum of all VSS ground lines
IVDD
Maximum current into each VDD power pin
(source)(1)
100
IVSS
Maximum current out of each VSS ground pin (sink)(1)
100
Output current sunk by any I/O and control pin
IIO
ΣI(PIN)
IINJ(PIN)
(3)(4)
ΣIINJ(PIN)
Total output current sunk by sum of all I/Os and control
Unit
20
pins(2)
140
Total output current sourced by sum of all I/Os and control pins(2)
140
Injected current on FT_xxx, TT_xx, RST and B pins except PA4,
PA5
−5/+0
Injected current on PA4, PA5
−0/0
Total injected current (sum of all I/Os and control pins)(5)
±25
mA
1. All main power (VDD, VDDA, VDD33USB) and ground (VSS, VSSA) pins must always be connected to the
external power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
QFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer also to Table 19: Voltage characteristics for the maximum allowed input voltage
values.
5. When several inputs are submitted to a current injection, the maximum ∑IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
Table 21. Thermal characteristics
Symbol
TSTG
TJ
Ratings
Storage temperature range
Maximum junction temperature
DS12556 Rev 6
Value
− 65 to +150
125
Unit
°C
97/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
6.3
Operating conditions
6.3.1
General operating conditions
Table 22. General operating conditions
Symbol
Parameter
Operating conditions
Min
Max
(1)
3.6
VDD
Standard operating voltage
-
VDDLDO
Supply voltage for the internal regulator
VDDLDO ≤ VDD
1.62(1)
3.6
USB used
3.0
3.6
USB not used
0
3.6
ADC or COMP used
1.62
DAC used
1.8
OPAMP used
2.0
VREFBUF used
1.8
ADC, DAC, OPAMP,
COMP, VREFBUF not
used
0
TT_xx I/O
−0.3
VDD+0.3
BOOT0
0
9
All I/O except BOOT0
and TT_xx
−0.3
Min(VDD, VDDA,
VDD33USB) +3.6V
< 5.5V(2)(3)
–40
85
–40
105
–40
125
VDD33USB Standard operating voltage, USB domain
VDDA
VIN
Analog operating voltage
1.62
I/O Input voltage
TA
Ambient temperature for Maximum power dissipation
the suffix 6 version
Low-power dissipation(4)
TJ
Junction temperature
range
Suffix 6 version
3.6
Unit
V
°C
°C
1. When RESET is released functionality is guaranteed down to VBOR0 min
2. This formula has to be applied on power supplies related to the IO structure described by the pin definition table.
3. For operation with voltage higher than Min (VDD, VDDA, VDD33USB) +0.3V, the internal Pull-up and Pull-Down resistors must
be disabled.
4. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 8.6:
Thermal characteristics).
98/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
6.3.2
Electrical characteristics (rev Y)
VCAP external capacitor
Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to
the VCAP pin. CEXT is specified in Table 23. Two external capacitors can be connected to
VCAP pins.
Figure 13. External capacitor CEXT
C
ESR
R Leak
MS19044V2
1. Legend: ESR is the equivalent series resistance.
Table 23. VCAP operating conditions(1)
Symbol
Parameter
Conditions
CEXT
Capacitance of external capacitor
2.2 µF(2)
ESR
ESR of external capacitor
< 100 mΩ
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
2. This value corresponds to CEXT typical value. A variation of +/-20% is tolerated.
6.3.3
Operating conditions at power-up / power-down
Subject to general operating conditions for TA.
Table 24. Operating conditions at power-up / power-down (regulator ON)
Symbol
tVDD
tVDDA
tVDDUSB
Parameter
Min
Max
VDD rise time rate
0
∞
VDD fall time rate
10
∞
VDDA rise time rate
0
∞
VDDA fall time rate
10
∞
VDDUSB rise time rate
0
∞
VDDUSB fall time rate
10
∞
DS12556 Rev 6
Unit
µs/V
99/336
311
Electrical characteristics (rev Y)
6.3.4
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Embedded reset and power control block characteristics
The parameters given in Table 25 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 22: General operating
conditions.
Table 25. Reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tRSTTEMPO(1)
Reset temporization
after BOR0 released
-
-
377
-
µs
VBOR0
Brown-out reset threshold 0
Rising edge(1)
1.62
1.67
1.71
Falling edge
1.58
1.62
1.68
VBOR1
Brown-out reset threshold 1
2.04
2.10
2.15
1.95
2.00
2.06
VBOR2
Brown-out reset threshold 2
2.34
2.41
2.47
2.25
2.31
2.37
VBOR3
Brown-out reset threshold 3
2.63
2.70
2.78
2.54
2.61
2.68
VPVD0
Programmable Voltage
Detector threshold 0
Rising edge
1.90
1.96
2.01
1.81
1.86
1.91
VPVD1
Programmable Voltage
Detector threshold 1
Rising edge
2.05
2.10
2.16
1.96
2.01
2.06
VPVD2
Programmable Voltage
Detector threshold 2
Rising edge
2.19
2.26
2.32
2.10
2.15
2.21
VPVD3
Programmable Voltage
Detector threshold 3
Rising edge
2.35
2.41
2.47
2.25
2.31
2.37
VPVD4
Programmable Voltage
Detector threshold 4
Rising edge
2.49
2.56
2.62
2.39
2.45
2.51
VPVD5
Programmable Voltage
Detector threshold 5
Rising edge
2.64
2.71
2.78
2.55
2.61
2.68
VPVD6
Programmable Voltage
Detector threshold 6
Rising edge
2.78
2.86
2.94
2.69
2.76
2.83
Vhyst_BOR_PVD
Hysteresis voltage of BOR
(unless BOR0) and PVD
Hysteresis in Run mode
-
100
-
mV
IDD_BOR_PVD(1)
BOR(2) (unless BOR0) and
PVD consumption from VDD
-
-
0.630
µA
100/336
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Falling edge
Falling edge
Falling edge
Falling edge
Falling edge
Falling edge
Falling edge in Run mode
DS12556 Rev 6
V
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 25. Reset and power control block characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
VAVM_0
Analog voltage detector for
VDDA threshold 0
Rising edge
1.66
1.71
1.76
1.56
1.61
1.66
VAVM_1
Analog voltage detector for
VDDA threshold 1
Rising edge
2.06
2.12
2.19
1.96
2.02
2.08
VAVM_2
Analog voltage detector for
VDDA threshold 2
Rising edge
2.42
2.50
2.58
2.35
2.42
2.49
VAVM_3
Analog voltage detector for
VDDA threshold 3
Rising edge
2.74
2.83
2.91
2.64
2.72
2.80
Vhyst_VDDA
Hysteresis of VDDA voltage
detector
-
-
100
-
mV
IDD_PVM
PVM consumption from
VDD(1)
-
-
-
0.25
µA
IDD_VDDA
Voltage detector
consumption on VDDA(1)
-
-
2.5
µA
Falling edge
Falling edge
Falling edge
Falling edge
Resistor bridge
Unit
V
1. Guaranteed by design.
2. BOR0 is enabled in all modes and its consumption is therefore included in the supply current characteristics tables (refer to
Section 6.3.6: Supply current characteristics).
6.3.5
Embedded reference voltage
The parameters given in Table 26 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 22: General operating
conditions.
Table 26. Embedded reference voltage
Symbol
VREFINT
tS_vrefint(1)(2)
tS_vbat(1)(2)
Irefbuf(2)
ΔVREFINT(2)
Tcoeff(2)
VDDcoeff(2)
Parameter
Conditions
Min
Typ
Max
Unit
-40°C < TJ < 105°C,
VDD = 3.3 V
1.180
1.216
1.255
V
ADC sampling time when
reading the internal reference
voltage
-
4.3
-
-
VBAT sampling time when
reading the internal VBAT
reference voltage
-
9
-
-
VDDA=3.3 V
9
13.5
23
µA
-40°C < TJ < 105°C
-
5
15
mV
Average temperature
coefficient
-
20
70
ppm/°C
3.0V < VDD < 3.6V
-
10
1370
ppm/V
Internal reference voltages
Reference Buffer
consumption for ADC
Internal reference voltage
spread over the temperature
range
Average temperature
coefficient
Average Voltage coefficient
µs
DS12556 Rev 6
101/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 26. Embedded reference voltage (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
VREFINT_DIV1 1/4 reference voltage
-
-
25
-
VREFINT_DIV2 1/2 reference voltage
-
-
50
-
VREFINT_DIV3 3/4 reference voltage
-
-
75
-
1.
The shortest sampling time for the application can be determined by multiple iterations.
2.
Guaranteed by design.
Unit
%
VREFINT
Table 27. Internal reference voltage calibration values
Symbol
Parameter
Raw data acquired at temperature of 30 °C, VDDA = 3.3 V
VREFIN_CAL
6.3.6
Memory address
1FF1E860 - 1FF1E861
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 12: Current consumption
measurement scheme.
All the run-mode current consumption measurements given in this section are performed
with a CoreMark code.
Typical and maximum current consumption
The MCU is placed under the following conditions:
•
All I/O pins are in analog input mode.
•
All peripherals are disabled except when explicitly mentioned.
•
The Flash memory access time is adjusted with the minimum wait states number,
depending on the fACLK frequency (refer to the table “Number of wait states according to
CPU clock (frcc_c_ck) frequency and VCORE range” available in the reference manual).
•
When the peripherals are enabled, the AHB clock frequency is the CPU frequency
divided by 2 and the APB clock frequency is AHB clock frequency divided by 2.
The parameters given in Table 28 to Table 36 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 22: General
operating conditions.
102/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 28. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM, regulator ON(1)
Symbol
Parameter
Conditions
VOS1
VOS2
All
peripherals
disabled
IDD
Supply
current in Run
mode
VOS3
VOS1
All
peripherals
VOS2
enabled
VOS3
Max(2)
frcc_c_ck
(MHz)
Typ
TJ =
25°C
TJ =
85°C
TJ =
105°C
TJ =
125°C
400
71
110
210
290
540
300
56
-
-
-
-
300
50
72
170
230
370
216
37
58
150
210
380
200
35.5
-
-
-
-
200
33
50
130
190
300
180
30
47
130
180
290
168
28
45
130
180
290
144
25
41
120
180
290
60
13
28
110
160
280
25
10
24
99
160
270
400
165
220(3)
400
500(3)
840
300
130
-
-
-
-
300
120
170
300
390
570
200
83
-
-
-
-
200
78
110
220
300
470
unit
mA
1. Data are in DTCM for best computation performance, cache has no influence on consumption in this case.
2. Guaranteed by characterization results unless otherwise specified.
3. Guaranteed by test in production.
DS12556 Rev 6
103/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 29. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache ON, regulator ON
Symbol
Parameter
Conditions
VOS1
VOS2
All
peripherals
disabled
IDD
Supply
current in Run
mode
VOS3
VOS1
All
peripherals
VOS2
enabled
VOS3
Max(1)
frcc_c_ck
(MHz)
Typ
TJ =
25°C
TJ =
85°C
TJ =
105°C
TJ =
125°C
400
105
160
310
420
750
300
55
-
-
-
-
300
50
72
160
230
370
216
38
-
-
-
-
200
36
-
-
-
-
200
33
50
130
190
300
180
30
-
-
-
-
168
29
-
-
-
-
144
26
-
-
-
-
60
14
-
-
-
-
25
14
-
-
-
-
400
160
220
400
500
750
300
130
-
-
-
-
300
120
160
300
390
560
200
81
-
-
-
-
200
77
110
220
300
460
unit
mA
1. Guaranteed by characterization results unless otherwise specified.
Table 30. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache OFF, regulator ON
Symbol
IDD
Parameter
Supply
current in Run
mode
Conditions
Max(1)
frcc_c_ck
(MHz)
Typ
TJ =
25°C
TJ =
85°C
TJ =
105°C
TJ =
125°C
VOS1
All
peripherals VOS2
disabled
VOS3
400
73
110
220
290
540
300
52
75
170
230
370
200
34
52
130
190
300
VOS1
400
135
190
360
470
730
300
100
150
270
370
550
200
70
100
210
300
460
All
peripherals VOS2
enabled
VOS3
1. Guaranteed by characterization results.
104/336
DS12556 Rev 6
unit
mA
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 31. Typical consumption in Run mode and corresponding performance
versus code position
Symbol
Parameter
Conditions
All
peripherals
disabled,
cache ON
Supply current
in Run mode
IDD
Code
frcc_c_ck
(MHz)
CoreMark
Typ
ITCM
400
2012
71
35
FLASH
A
400
2012
105
52
AXI
SRAM
400
2012
105
52
SRAM1
400
2012
105
52
SRAM4
400
2012
105
ITCM
400
2012
71
FLASH
A
400
593
70.5
119
AXI
SRAM
400
344
70.5
205
SRAM1
400
472
74.5
158
SRAM4
400
432
72
167
Peripheral
All
peripherals
disabled
cache OFF
Unit
IDD/
CoreMark
52
mA
Unit
µA/
CoreMark
35
Table 32. Typical current consumption batch acquisition mode
Symbol
Parameter
IDD
Supply current in
batch acquisition
mode
Conditions
D1Standby,
D2Standby,
D3Run
VOS3
D1Stop, D2Stop,
D3Run
VOS3
frcc_ahb_ck(AHB4)
(MHz)
Typ
64
6.5
unit
mA
64
12
Table 33. Typical and maximum current consumption in Sleep mode, regulator ON
Symbol
Parameter
Conditions
VOS1
IDD(Sleep)
Supply
current in
Sleep mode
All
peripherals
VOS2
disabled
VOS3
Max(1)
frcc_c_ck
(MHz)
Typ
TJ =
25°C
TJ =
85°C
TJ =
105°C
TJ =
125°C
400
31.0
64
220
330
660
300
24.5
57
210
330
650
300
22.0
48
180
270
500
200
17.0
42
170
270
490
200
15.5
37
150
230
400
unit
mA
1. Guaranteed by characterization results.
DS12556 Rev 6
105/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 34. Typical and maximum current consumption in Stop mode, regulator ON
Max(1)
Symbol
Parameter
Flash
memory in
low-power
mode, no
IWDG
D1Stop,
D2Stop,
D3Stop
IDD(Stop)
Conditions
Flash
memory ON,
no IWDG
D1Stop,
D2Standby,
D3Stop
Flash
memory
OFF, no
IWDG
Flash
memory ON,
no IWDG
D1Standby,
D2Stop,
D3Stop
Flash OFF,
no IWDG
D1Standby,
D2Standby,
D3Stop
Typ
TJ =
25°C
TJ =
85°C
TJ =
105°C
TJ =
125°C
SVOS5
1.4
7.2(2)
49
75(2)
140
SVOS4
1.95
11
66
110
200
SVOS3
2.85
16(2)
91
150(2)
240
SVOS5
1.65
7.2
49
75
140
SVOS4
2.2
11
66
110
180
SVOS3
3.15
16
91
150
300
SVOS5
0.99
5.1
35
60
97
SVOS4
1.4
7.5
47
79
130
SVOS3
2.05
12
64
110
170
SVOS5
1.25
5.5
35
61
98
SVOS4
1.65
7.8
47
80
130
SVOS3
2.3
12
65
110
170
SVOS5
0.57
3
21
36
57
SVOS4
0.805
4.5
27
47
74
SVOS3
1.2
6.7
37
63
99
8
13(2)
20
(2)
SVOS5
0.17
1.1
SVOS4
0.245
1.5
11
17
26
SVOS3
0.405
2.4(2)
15
23(2)
35
unit
mA
1. Guaranteed by characterization results.
2. Guaranteed by test in production.
Table 35. Typical and maximum current consumption in Standby mode
Typ(3)
Conditions
Symbol
IDD
(Standby)
Parameter
Supply
current in
Standby
mode
Backup
SRAM
RTC
1.62 V
& LSE
Max (3 V)(1)
2.4 V
3V
3.3 V
TJ =
25°C
TJ =
85°C
TJ =
TJ =
105°C 125°C
OFF
OFF
1.8
1.9
1.95
2.05
4(2)
18(3)
40(2)
90(3)
ON
OFF
3.4
3.4
3.5
3.7
8.2(3)
47(3)
83(3)
141(3)
OFF
ON
2.4
3.5
3.86
4.12
-
-
-
-
ON
ON
3.95
5.1
5.46
5.97
-
-
-
-
1. The maximum current consumption values are given for PDR OFF (internal reset OFF). When the PDR is OFF (internal
reset OFF), the current consumption is reduced by 1.2 µA compared to PDR ON.
2. Guaranteed by test in production.
3. Guaranteed by characterization results.
106/336
DS12556 Rev 6
Unit
µA
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 36. Typical and maximum current consumption in VBAT mode
Typ(1)
Conditions
Symbol
IDD
(VBAT)
Parameter
Supply
current in
standby
mode
Backup
SRAM
RTC &
LSE
1.2 V
OFF
OFF
0.024
ON
OFF
1.4
1.6
1.8
OFF
ON
0.24
0.45
ON
ON
1.97
2.37
Max (3 V)
TJ =
25°C
TJ =
85°C
0.035 0.062 0.096 0.5(1)
4.1(1)
10(1)
24(1)
1.8
4.4(1)
22(1)
48(1)
87(1)
0.62
0.73
-
-
-
-
2.57
2.77
-
-
-
-
2V
3V
3.4 V
TJ =
TJ =
105°C 125°C
Unit
µA
1. Guaranteed by characterization results.
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate a current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 58: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
An additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid a current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 37: Peripheral current
consumption in Run mode), the I/Os used by an application also contribute to the current
consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to
supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external)
connected to the pin:
I SW = V DDx × f SW × C L
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDx is the MCU supply voltage
fSW is the I/O switching frequency
CL is the total capacitance seen by the I/O pin: C = CINT+ CEXT
DS12556 Rev 6
107/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
On-chip peripheral current consumption
The MCU is placed under the following conditions:
•
At startup, all I/O pins are in analog input configuration.
•
All peripherals are disabled unless otherwise mentioned.
•
The I/O compensation cell is enabled.
•
frcc_c_ck is the CPU clock. fPCLK = frcc_c_ck/4, and fHCLK = frcc_c_ck/2.
The given value is calculated by measuring the difference of current consumption
•
108/336
–
with all peripherals clocked off
–
with only one peripheral clocked on
–
frcc_c_ck = 400 MHz (Scale 1), frcc_c_ck = 300 MHz (Scale 2),
frcc_c_ck = 200 MHz (Scale 3)
The ambient operating temperature is 25 °C and VDD=3.3 V.
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 37. Peripheral current consumption in Run mode
IDD(Typ)
Peripheral
AHB3
Unit
VOS1
VOS2
VOS3
MDMA
8.3
7.6
7
DMA2D
21
20
18
JPEG
24
23
21
FLASH
9.9
9
8.3
FMC registers
0.9
0.9
0.8
FMC kernel
6.1
5.5
5.3
QUADSPI
registers
1.5
1.4
1.3
QUADSPI kernel
0.9
0.8
0.7
SDMMC1
registers
8
7.2
6.8
SDMMC1 kernel
2.4
2
1.8
DTCM1
5.7
5
4.5
DTCM2
5.5
4.8
4.3
ITCM
3.2
2.9
2.6
D1SRAM1
7.6
6.8
6.1
AHB3 bridge
7.5
6.8
6.3
DMA1
1.1
1
1
DMA2
1.7
1.4
1.1
ADC1/2 registers
3.9
3.2
3.1
ADC1/2 kernel
0.9
0.8
0.7
ART accelerator
5.5
4.5
4.2
16
14
13
USB1 OTG
registers
15
14
13
USB1 OTG kernel
-
8.5
8.5
USB1 ULPI
0.3
0.3
0.1
USB2 OTG
registers
15
13
12
USB2 OTG kernel
-
8.6
8.6
USB2 ULPI
16
16
16
AHB1 Bridge
10
9.6
8.6
µA/MHz
ETH1MAC
ETH1TX
ETH1RX
AHB1
DS12556 Rev 6
109/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 37. Peripheral current consumption in Run mode (continued)
IDD(Typ)
Peripheral
AHB2
AHB4
APB3
110/336
Unit
VOS1
VOS2
VOS3
DCMI
1.7
1.7
1.7
CRYP
0.1
0.1
0.1
HASH
0.1
0.1
0.1
RNG registers
1.8
1.4
1.2
RNG kernel
-
9.6
9.6
SDMMC2
registers
13
12
11
SDMMC2 kernel
2.7
2.5
2.4
D2SRAM1
3.3
3.1
2.8
D2SRAM2
2.9
2.7
2.5
D2SRAM3
1.9
1.8
1.7
AHB2 bridge
0.1
0.1
0.1
GPIOA
1.1
1
0.9
GPIOB
1
0.9
0.9
GPIOC
1.4
1.3
1.3
GPIOD
1.1
1
0.9
GPIOE
1
0.9
0.8
GPIOF
0.9
0.8
0.8
GPIOG
0.9
0.7
0.7
GPIOH
1
0.9
0.9
GPIOI
0.9
0.9
0.8
GPIOJ
0.9
0.8
0.8
GPIOK
0.9
0.8
0.7
CRC
0.5
0.4
0.4
BDMA
6.2
5.8
5.5
ADC3 registers
1.8
1.7
1.7
ADC3 kernel
0.1
0.1
0.1
Backup SRAM
1.9
1.8
1.8
Bridge AHB4
0.1
0.1
0.1
LCD-TFT
12
11
10
WWDG1
0.5
0.4
0.3
APB3 bridge
0.5
0.2
0.1
DS12556 Rev 6
µA/MHz
µA/MHz
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 37. Peripheral current consumption in Run mode (continued)
IDD(Typ)
Peripheral
APB1
Unit
VOS1
VOS2
VOS3
TIM2
3.5
3.2
2.9
TIM3
3.4
3.1
2.7
TIM4
2.7
2.5
1.9
TIM5
3.2
2.9
2.5
TIM6
1
0.8
0.7
TIM7
1
0.9
0.7
TIM12
1.7
1.5
1.2
TIM13
1.5
1.3
1
TIM14
1.4
1.3
0.9
LPTIM1 registers
0.7
0.6
0.5
LPTIM1 kernel
2.3
2.1
1.9
WWDG2
0.6
0.4
0.4
SPI2 registers
1.8
1.5
1.2
SPI2 kernel
0.6
0.5
0.5
SPI3 registers
1.5
1.3
1.1
SPI3 kernel
0.6
0.5
0.5
SPDIFRX1
registers
0.6
0.5
0.3
SPDIFRX1 kernel
2.9
2.4
2.4
USART2 registers
1.4
1.3
1
USART2 kernel
4.7
4.1
4
USART3 registers
1.4
1.3
1
USART3 kernel
4.2
3.8
3.5
UART4 registers
1.5
1.1
1
UART4 kernel
3.7
3.6
3.2
DS12556 Rev 6
µA/MHz
111/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 37. Peripheral current consumption in Run mode (continued)
IDD(Typ)
Peripheral
APB1
(continued)
112/336
Unit
VOS1
VOS2
VOS3
UART5 registers
1.4
1.4
1
UART5 kernel
3.6
3.2
3.1
I2C1 registers
0.8
0.8
0.6
I2C1 kernel
2
1.8
1.7
I2C2 registers
0.7
0.7
0.4
I2C2 kernel
1.9
1.7
1.6
I2C3 registers
0.9
0.7
0.6
I2C3 kernel
2.1
1.9
1.9
HDMI-CEC
registers
0.5
0.3
0.3
DAC1/2
1.4
1.1
0.9
USART7 registers
1.9
1.8
1.3
USART7 kernel
4
3.5
3.3
USART8 registers
1.6
1.5
1.2
USART8 kernel
4
3.6
3.3
CRS
3.4
3.1
2.9
SWPMI registers
2.3
2
2
SWPMI kernel
0.1
0.1
0.1
OPAMP
0.5
0.4
0.4
MDIO
2.7
2.4
2.3
FDCAN registers
16
15
14
FDCAN kernel
7.8
7.6
7.1
Bridge APB1
0.1
0.1
0.1
DS12556 Rev 6
µA/MHz
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 37. Peripheral current consumption in Run mode (continued)
IDD(Typ)
Peripheral
APB2
Unit
VOS1
VOS2
VOS3
TIM1
5.1
4.8
4.3
TIM8
5.4
4.9
4.6
USART1 registers
2.7
2.6
2.5
USART1 kernel
0.1
0.1
0.1
USART6 registers
2.6
2.5
2.5
USART6 kernel
0.1
0.1
0.1
SPI1 registers
1.8
1.6
1.6
SPI1 kernel
1
0.8
0.6
SPI4 registers
1.6
1.5
1.5
SPI4 kernel
0.5
0.4
0.4
TIM15
3.1
2.8
2.7
TIM16
2.4
2.1
2.1
TIM17
2.2
2
1.9
SPI5 registers
1.8
1.7
1.7
SPI5 kernel
0.6
0.5
0.3
SAI1 registers
1.5
1.4
1.4
SAI1 kernel
2
1.7
1.5
SAI2 registers
1.5
1.5
1.3
SAI2 kernel
2.2
1.9
1.8
SAI3 registers
1.8
1.6
1.6
SAI3 kernel
2.5
2.3
2.1
DFSDM1 registers
6
5.4
5.2
DFSDM1 kernel
0.9
0.8
0.7
HRTIM
40
37
35
Bridge APB2
0.1
0.1
0.1
DS12556 Rev 6
µA/MHz
113/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 37. Peripheral current consumption in Run mode (continued)
IDD(Typ)
Peripheral
APB4
Unit
VOS1
VOS2
VOS3
SYSCFG
1
0.7
0.7
LPUART1
registers
1.1
1.1
1.1
LPUART1 kernel
2.6
2.4
2.1
SPI6 registers
1.6
1.5
1.4
SPI6 kernel
0.2
0.2
0.2
I2C4 registers
0.1
0.1
0.1
I2C4 kernel
2.4
2.1
2
LPTIM2 registers
0.5
0.5
0.5
LPTIM2 kernel
2.3
2.1
1.8
LPTIM3 registers
0.5
0.5
0.5
LPTIM3 kernel
2
2.1
1.5
LPTIM4 registers
0.5
0.5
0.5
LPTIM4 kernel
2
2
1.9
LPTIM5 registers
0.5
0.5
0.5
LPTIM5 kernel
2
1.8
1.5
COMP1/2
0.7
0.5
0.5
VREFBUF
0.6
0.4
0.4
RTC
1.2
1.1
1.1
SAI4 registers
1.6
1.5
1.4
SAI4 kernel
1.3
1.3
1.2
Bridge APB4
0.1
0.1
0.1
µA/MHz
Table 38. Peripheral current consumption in Stop, Standby and VBAT mode
Symbol
IDD
114/336
Typ
Parameter
Conditions
RTC+LSE low drive
-
2.32
RTC+LSE mediumlow drive
-
2.4
RTC+LSE mediumhigh drive
-
2.7
RTC+LSE High drive
-
3
DS12556 Rev 6
3V
Unit
µA
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
6.3.7
Electrical characteristics (rev Y)
Wakeup time from low-power modes
The wakeup times given in Table 39 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
•
For Stop or Sleep modes: the wakeup event is WFE.
•
WKUP (PC1) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and VDD=3.3 V.
Table 39. Low-power mode wakeup timings
Symbol
Parameter
Conditions
Typ(1)
Max(1)
Unit
tWUSLEEP(2)
Wakeup from Sleep
-
9
10
CPU
clock
cycles
VOS3, HSI, Flash memory in normal mode
4.4
5.6
VOS3, HSI, Flash memory in low-power
mode
12
15
VOS4, HSI, Flash memory in normal mode
15
20
VOS4, HSI, Flash memory in low-power
mode
23
28
VOS5, HSI, Flash memory in normal mode
30
71
VOS5, HSI, Flash memory in low-power
mode
38
47
VOS3, CSI, Flash memory in normal mode
27
37
VOS3, CSI, Flash memory in low power
mode
36
50
VOS4, CSI, Flash memory in normal mode
38
48
VOS4, CSI, Flash memory in low-power
mode
47
61
VOS5, CSI, Flash memory in normal mode
52
64
VOS5, CSI, Flash memory in low-power
mode
62
77
VOS3, HSI, Flash memory in normal mode
2.6
3.4
VOS3, CSI, Flash memory in normal mode
26
36
-
390
500
tWUSTOP(2)
Wakeup from Stop
tWUSTOP2(2)
Wakeup from Stop,
clock kept running
tWUSTDBY(2)
Wakeup from Standby
mode
µs
1. Guaranteed by characterization results.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction.
DS12556 Rev 6
115/336
311
Electrical characteristics (rev Y)
6.3.8
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O.
The external clock signal has to respect the Table 58: I/O static characteristics. However,
the recommended clock input waveform is shown in Figure 14.
Table 40. High-speed external user clock characteristics(1)
Symbol
Parameter
Min
Typ
Max
Unit
fHSE_ext
User external clock source frequency
4
25
50
MHz
0.7VDD
-
VDD
VSS
-
0.3VSS
7
-
-
VSW
OSC_IN amplitude
(VHSEH − VHSEL)
VDC
OSC_IN input voltage
tW(HSE)
OSC_IN high or low time
V
ns
1. Guaranteed by design.
Figure 14. High-speed external clock source AC timing diagram
VHSEH
90 %
10 %
VHSEL
tr(HSE)
tf(HSE)
tW(HSE) t
tW(HSE)
THSE
External
clock source
fHSE_ext
OSC_IN
IL
STM32
ai17528b
116/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 58: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 15.
Table 41. Low-speed external user clock characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
kHz
fLSE_ext
User external clock source frequency
-
-
32.768
1000
VLSEH
OSC32_IN input pin high level voltage
-
0.7 VDDIOx
-
VDDIOx
VLSEL
OSC32_IN input pin low level voltage
-
VSS
-
0.3 VDDIOx
-
250
-
-
tw(LSEH)
OSC32_IN high or low time
tw(LSEL)
V
ns
1. Guaranteed by design.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 15. Low-speed external clock source AC timing diagram
VLSEH
90%
VLSEL
10%
tr(LSE)
tf(LSE)
tW(LSE)
OSC32_IN
IL
tW(LSE) t
TLSE
External
clock source
fLSE_ext
STM32
ai17529b
DS12556 Rev 6
117/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 42. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 42. 4-48 MHz HSE oscillator characteristics(1)
Symbol
Parameter
Operating
conditions(2)
Min
Typ
Max
Unit
F
Oscillator frequency
-
4
-
48
MHz
RF
Feedback resistor
-
-
200
-
kΩ
-
-
4
VDD=3 V, Rm=30 Ω
CL=10pF@4MHz
-
0.35
-
VDD=3 V, Rm=30 Ω
CL=10 pF at 8 MHz
-
0.40
-
VDD=3 V, Rm=30 Ω
CL=10 pF at 16 MHz
-
0.45
-
VDD=3 V, Rm=30 Ω
CL=10 pF at 32 MHz
-
0.65
-
VDD=3 V, Rm=30 Ω
CL=10 pF at 48 MHz
-
0.95
-
Maximum critical crystal gm
Startup
-
-
1.5
mA/V
Start-up time
VDD is stabilized
-
2
-
ms
During startup
IDD(HSE)
Gmcritmax
tSU
HSE current consumption
(4)
(3)
mA
1. Guaranteed by design.
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typical), designed for high-frequency applications, and selected to
match the requirements of the crystal or resonator (see Figure 16). CL1 and CL2 are usually
the same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. The PCB and MCU pin capacitance must be included
(10 pF can be used as a rough estimate of the combined pin and board capacitance) when
sizing CL1 and CL2.
Note:
118/336
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Figure 16. Typical application with an 8 MHz crystal
Resonator with
integrated capacitors
CL1
8 MHz
resonator
CL2
fHSE
OSC_IN
REXT(1)
RF
Bias
controlled
gain
OSC_OU T
STM32
ai17530b
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 43. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 43. Low-speed external user clock characteristics(1)
Symbol
Parameter
Operating conditions(2)
Min
Typ
Max
Unit
F
Oscillator frequency
-
-
32.768
-
kHz
LSEDRV[1:0] = 00,
Low drive capability
-
290
-
LSEDRV[1:0] = 01,
Medium Low drive capability
-
390
-
LSEDRV[1:0] = 10,
Medium high drive capability
-
550
-
LSEDRV[1:0] = 11,
High drive capability
-
900
-
LSEDRV[1:0] = 00,
Low drive capability
-
-
0.5
LSEDRV[1:0] = 01,
Medium Low drive capability
-
-
0.75
LSEDRV[1:0] = 10,
Medium high drive capability
-
-
1.7
LSEDRV[1:0] = 11,
High drive capability
-
-
2.7
VDD is stabilized
-
2
-
IDD
Gmcritmax
tSU(3)
LSE current
consumption
Maximum critical crystal
gm
Startup time
nA
µA/V
s
1. Guaranteed by design.
DS12556 Rev 6
119/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers.
3. tSU is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768k Hz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 17. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors
CL1
fHSE
OSC32_IN
32.768 kHz
resonator
RF
Bias
controlled
gain
OSC32_OUT
STM32
CL2
ai17531c
1. An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.
6.3.9
Internal clock source characteristics
The parameters given in Table 44 and Table 47 are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 22: General
operating conditions.
48 MHz high-speed internal RC oscillator (HSI48)
Table 44. HSI48 oscillator characteristics
Symbol
fHSI48
TRIM
(2)
Parameter
HSI48 frequency
Conditions
Min
Typ
Max
Unit
VDD=3.3 V, TJ=30 °C
47.5(1)
48
48.5(1)
MHz
-
-
0.17
-
%
± 32 steps
-
±5.45
-
%
-
45
-
55
%
%
USER trimming step
USER TRIM
COVERAGE(3)
USER TRIMMING Coverage
DuCy(HSI48)(2)
Duty Cycle
ACCHSI48_REL(3)
Accuracy of the HSI48 oscillator over
temperature (factory calibrated)
VDD=1.62 to 3.6 V,
TJ=-40 to 125 °C
–4.5
-
3.5
∆VDD(HSI48)(3)
HSI48 oscillator frequency drift with
VDD(4)
VDD=3 to 3.6 V
-
0.025
0.05
VDD=1.62 V to 3.6 V
-
0.05
0.1
%
tsu(HSI48)(2)
HSI48 oscillator start-up time
-
-
2.1
3.5
µs
IDD(HSI48)(2)
HSI48 oscillator power consumption
-
-
350
400
µA
NT jitter
Next transition jitter
Accumulated jitter on 28 cycles(5)
-
-
± 0.15
-
ns
PT jitter
Paired transition jitter
Accumulated jitter on 56 cycles(5)
-
-
± 0.25
-
ns
120/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
1. Guaranteed by test in production.
2. Guaranteed by design.
3. Guaranteed by characterization.
4. These values are obtained by using the formula:
(Freq(3.6V) - Freq(3.0V)) / Freq(3.0V) or (Freq(3.6V) - Freq(1.62V)) / Freq(1.62V).
5. Jitter measurements are performed without clock source activated in parallel.
64 MHz high-speed internal RC oscillator (HSI)
Table 45. HSI oscillator characteristics(1)
Symbol
Parameter
fHSI
HSI frequency
TRIM
HSI user trimming step
DuCy(HSI)
Duty Cycle
ΔVDD (HSI)
HSI oscillator frequency drift over
VDD (reference is 3.3 V)
ΔTEMP (HSI)
HSI oscillator frequency drift over
temperature (reference is 64 MHz)
tsu(HSI)
HSI oscillator start-up time
tstab(HSI)
HSI oscillator stabilization time
IDD(HSI)
HSI oscillator power consumption
Conditions
Min
Typ
Max
Unit
VDD=3.3 V, TJ=30 °C
63.7(2)
64
64.3(2)
MHz
Trimming is not a multiple
of 32
-
0.24
0.32
Trimming is 128, 256 and
384
−5.2
−1.8
-
Trimming is 64, 192, 320
and 448
−1.4
−0.8
-
Other trimming are a
multiple of 32 (not
including multiple of 64
and 128)
−0.6
−0.25
-
-
45
-
55
%
VDD=1.62 to 3.6 V
−0.12
-
0.03
%
TJ=-20 to 105 °C
−1(3)
-
1(3)
%
TJ=−40 to TJmax °C
−2(3)
-
1(3)
-
-
1.4
2
µs
at 1% of target frequency
-
4
8
µs
-
-
300
400
µA
%
1. Guaranteed by design unless otherwise specified.
2. Guaranteed by test in production.
3. Guaranteed by characterization.
4 MHz low-power internal RC oscillator (CSI)
Table 46. CSI oscillator characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fCSI
CSI frequency
VDD=3.3 V, TJ=30 °C
3.96(2)
4
4.04(2)
MHz
TRIM
Trimming step
-
-
0.35
-
%
Duty Cycle
-
45
-
55
%
DuCy(CSI)
DS12556 Rev 6
121/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 46. CSI oscillator characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
(3)
Max
TJ = 0 to 85 °C
-
−3.7
TJ = −40 to 125 °C
-
−11(3)
7.5(3)
VDD = 1.62 to 3.6 V
-
−0.06
0.06
%
CSI oscillator startup time
-
-
1
2
µs
tstab(CSI)
CSI oscillator stabilization time
(to reach ±3% of fCSI)
-
-
4
8
cycle
IDD(CSI)
CSI oscillator power consumption
-
-
23
30
µA
Min
Typ
Max
Unit
VDD = 3.3 V, TJ = 25 °C
31.4
32
32.6
TJ = –40 to 105 °C, VDD =
1.62 to 3.6 V
29.76
-
33.60
∆TEMP (CSI)
CSI oscillator frequency drift over
temperature
DVDD (CSI)
CSI oscillator frequency drift over
VDD
tsu(CSI)
4.5
Unit
(3)
%
1. Guaranteed by design.
2. Guaranteed by test in production.
3. Guaranteed by characterization.
Low-speed internal (LSI) RC oscillator
Table 47. LSI oscillator characteristics
Symbol
fLSI(1)
Parameter
Conditions
LSI frequency
tsu(LSI)(2)
LSI oscillator startup time
-
-
80
130
tstab(LSI)(2)
LSI oscillator stabilization
time (5% of final value)
-
-
120
170
IDD(LSI)(2)
LSI oscillator power
consumption
-
-
130
280
kHz
µs
nA
1. Guaranteed by characterization results.
2. Guaranteed by design.
6.3.10
PLL characteristics
The parameters given in Table 48 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 22: General operating conditions.
Table 48. PLL characteristics (wide VCO frequency range)(1)
Symbol
fPLL_IN
122/336
Parameter
Conditions
Min
Typ
Max
Unit
PLL input clock
-
2
-
16
MHz
PLL input clock duty cycle
-
10
-
90
%
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 48. PLL characteristics (wide VCO frequency range)(1) (continued)
Symbol
fPLL_P_OUT
fPLL_Q_OUT
fVCO_OUT
tLOCK
Parameter
PLL multiplier output clock P
PLL multiplier output clock Q/R
PLL lock time
Jitter
Long term jitter
Typ
Max
Unit
(2)
1.5
-
VOS2
1.5
-
300
VOS3
1.5
-
200
VOS1
1.5
-
400(2)
VOS2
1.5
-
300
VOS3
1.5
-
200
-
192
-
836
400
(3)
150(3)
Normal mode
-
50
Sigma-delta mode
(CKIN ≥ 8 MHz)
-
58(3)
166(3)
VCO = 192 MHz
-
134
-
VCO = 200 MHz
-
134
-
VCO = 400 MHz
-
76
-
VCO = 800 MHz
-
39
-
Normal mode
-
±0.7
-
Sigma-delta mode
(CKIN = 16 MHz)
-
±0.8
-
VDDA
-
440
1150
VCORE
-
530
-
VDDA
-
180
500
VCORE
-
200
-
VCO freq =
420 MHz
PLL power consumption on VDD
Min
VOS1
PLL VCO output
Cycle-to-cycle jitter(4)
IDD(PLL)(3)
Conditions
VCO freq =
150 MHz
MHz
µs
±ps
%
µA
1. Guaranteed by design unless otherwise specified.
2. This value must be limited to the maximum frequency due to the product limitation (400 MHz for VOS1, 300 MHz for VOS2,
200 MHz for VOS3).
3. Guaranteed by characterization results.
4. Integer mode only.
Table 49. PLL characteristics (medium VCO frequency range)(1)
Symbol
fPLL_IN
fPLL_OUT
fVCO_OUT
tLOCK
Parameter
Conditions
Min
Typ
Max
Unit
PLL input clock
-
1
-
2
MHz
PLL input clock duty cycle
-
10
-
90
%
VOS1
1.17
-
210
VOS2
1.17
-
210
VOS3
1.17
-
200
-
150
-
420
MHz
Normal mode
-
60(2)
100(2)
µs
Sigma-delta mode
forbidden
-
-
µs
PLL multiplier output clock P, Q,
R
PLL VCO output
PLL lock time
DS12556 Rev 6
MHz
123/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 49. PLL characteristics (medium VCO frequency range)(1) (continued)
Symbol
Parameter
Cycle-to-cycle jitter(3)
Jitter
-
fPLL_OUT =
50 MHz
Period jitter
Long term jitter
I(PLL)(2)
Conditions
Normal mode
VCO freq =
420MHz
PLL power consumption on VDD
VCO freq =
150MHz
Min
Typ
Max
VCO =
150 MHz
-
145
-
VCO =
300 MHz
-
91
-
VCO =
400 MHz
-
64
-
VCO =
420 MHz
-
63
-
VCO =
150 MHz
-
55
-
VCO =
400 MHz
-
30
-
VCO =
150 MHz
-
-
-
VCO =
300 MHz
-
-
-
VCO =
400 MHz
-
+/-0.3
-
VDD
-
440
1150
VCORE
-
530
-
VDD
-
180
500
VCORE
-
200
-
Unit
+/ps
+/ps
%
µA
1. Guaranteed by design unless otherwise specified.
2. Guaranteed by characterization results.
3. Integer mode only.
6.3.11
Memory characteristics
Flash memory
The characteristics are given at TJ = –40 to 125 °C unless otherwise specified.
The devices are shipped to customers with the Flash memory erased.
Table 50. Flash memory characteristics
Symbol
IDD
124/336
Parameter
Supply current
Conditions
Min
Typ
Max
Write / Erase 8-bit mode
-
6.5
-
Write / Erase 16-bit mode
-
11.5
-
Write / Erase 32-bit mode
-
20
-
Write / Erase 64-bit mode
-
35
-
DS12556 Rev 6
Unit
mA
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 51. Flash memory programming
Symbol
tprog
tERASE128KB
tME
Min(1)
Typ
Max(1)
Program/erase parallelism x 8
-
290
580(2)
Program/erase parallelism x 16
-
180
360
Program/erase parallelism x 32
-
130
260
Program/erase parallelism x 64
-
100
200
Program/erase parallelism x 8
-
2
4
Program/erase parallelism x 16
-
1.8
3.6
Program/erase parallelism x 32
-
1.1
2.2
Program/erase parallelism x 8
-
13
26
Program/erase parallelism x 16
-
8
16
Program/erase parallelism x 32
-
6
12
Program/erase parallelism x 64
-
5
10
1.62
-
3.6
1.8
-
3.6
Parameter
Word (266 bits) programming
time
Sector (128 KB) erase time
Mass erase time
Conditions
Unit
µs
s
Program parallelism x 8
Vprog
Programming voltage
Program parallelism x 16
Program parallelism x 32
Program parallelism x 64
V
1. Guaranteed by characterization results.
2. The maximum programming time is measured after 10K erase operations.
Table 52. Flash memory endurance and data retention
Value
Symbol
NEND
tRET
Parameter
Conditions
Min(1)
Endurance
TJ = –40 to +125 °C (6 suffix versions)
10
Data retention
1 kcycle at TA = 85 °C
30
10 kcycles at TA = 55 °C
20
Unit
kcycles
Years
1. Guaranteed by characterization results.
DS12556 Rev 6
125/336
311
Electrical characteristics (rev Y)
6.3.12
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 53. They are based on the EMS levels and classes
defined in application note AN1709.
Table 53. EMS characteristics
Symbol
VFESD
VFTB
Parameter
Conditions
Level/
Class
Voltage limits to be applied on any I/O pin to induce
VDD = 3.3 V, TA = +25 °C,
a functional disturbance
UFBGA240, frcc_c_ck =
Fast transient voltage burst limits to be applied
400 MHz, conforms to
through 100 pF on VDD and VSS pins to induce a
IEC 61000-4-2
functional disturbance
3B
4B
As a consequence, it is recommended to add a serial resistor (1 kΏ) located as close as
possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm
on PCB).
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
126/336
•
Corrupted program counter
•
Unexpected reset
•
Critical Data corruption (control registers...)
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.
Table 54. EMI characteristics
Symbol Parameter
Conditions
Monitored
frequency band
Max vs.
[fHSE/fCPU]
Unit
8/400 MHz
SEMI
6.3.13
VDD = 3.6 V, TA = 25 °C, UFBGA240 package,
Peak level
conforming to IEC61967-2
0.1 to 30 MHz
6
30 to 130 MHz
5
130 MHz to 1 GHz
13
1 GHz to 2 GHz
7
EMI Level
2.5
dBµV
-
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each
sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC
JS-001 and ANSI/ESDA/JEDEC JS-002 standards.
Table 55. ESD absolute maximum ratings
Conditions
Packages
Class
Maximum
value(1)
Electrostatic discharge
VESD(HBM) voltage (human body
model)
TA = +25 °C conforming to
ANSI/ESDA/JEDEC JS001
All
1C
1000
Electrostatic discharge
VESD(CDM) voltage (charge device
model)
TA = +25 °C conforming to
ANSI/ESDA/JEDEC JS002
All
Symbol
Ratings
Unit
V
C1
250
1. Guaranteed by characterization results.
DS12556 Rev 6
127/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
•
A supply overvoltage is applied to each power supply pin
•
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with JESD78 IC latchup standard.
Table 56. Electrical sensitivities
Symbol
LU
6.3.14
Parameter
Static latchup class
Conditions
Class
TA = +25 °C conforming to JESD78
II level A
I/O current injection characteristics
As a general rule, a current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3.3 V-capable I/O pins) should be avoided during the normal
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when an abnormal injection accidentally happens, susceptibility
tests are performed on a sample basis during the device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency
deviation).
The following tables are the compilation of the SIC1/SIC2 and functional ESD results.
Negative induced A negative induced leakage current is caused by negative injection and
positive induced leakage current by positive injection.
Table 57. I/O current injection susceptibility(1)
Functional susceptibility
Symbol
IINJ
Description
Negative
injection
Positive
injection
PA7, PC5, PG1, PB14, PJ7, PA11, PA12, PA13, PA14, PA15,
PJ12, PB4
5
0
PA2, PH2, PH3, PE8, PA6, PA7, PC4, PE7, PE10, PE11
0
NA
PA0, PA_C, PA1, PA1_C, PC2, PC2_C, PC3, PC3_C, PA4,
PA5, PH4, PH5, BOOT0
0
0
All other I/Os
5
NA
1. Guaranteed by characterization.
128/336
DS12556 Rev 6
Unit
mA
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
6.3.15
Electrical characteristics (rev Y)
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 58: I/O static characteristics are
derived from tests performed under the conditions summarized in Table 22: General
operating conditions. All I/Os are CMOS and TTL compliant (except for BOOT0).
For information on GPIO configuration, refer to the application note AN4899 “STM32 GPIO
configuration for hardware settings and low-power consumption” available from the ST
website www.st.com.
Table 58. I/O static characteristics
Symbol
Parameter
Condition
Min
Typ
Max
-
-
0.3VDD(1)
-
-
0.4VDD−
0.1(2)
BOOT0 I/O input low level voltage
-
-
0.19VDD+
0.1(2)
I/O input high level voltage except
BOOT0
0.7VDD(1)
-
-
0.47VDD+
0.25(2)
-
-
0.17VDD+
0.6(2)
-
-
-
250
-
-
200
-
-
-
+/-250
Max(VDDXXX) < VIN ≤ 5.5 V
(5)(6)(9)
-
-
1500
0< VIN ≤ Max(VDDXXX)(9)
-
-
+/- 350
Max(VDDXXX) < VIN ≤ 5.5 V
(5)(6)(9)
-
-
5000(7)
0< VIN ≤ Max(VDDXXX) (9)
-
-
+/-250
0< VIN ≤ VDDIOX
-
-
15
I/O input low level voltage except
BOOT0
VIL
VIH
I/O input low level voltage except
BOOT0
I/O input high level voltage except
BOOT0(3)
1.62 V<VDDIOx<3.6 V
1.62 V<VDDIOx<3.6 V
BOOT0 I/O input high level
voltage(3)
VHYS(2)
TT_xx, FT_xxx and NRST I/O
input hysteresis
1.62 V< VDDIOx <3.6 V
BOOT0 I/O input hysteresis
0< VIN ≤
FT_xx Input leakage
Ileak(4)
current(2)
FT_u IO
TT_xx Input leakage current
VPP (BOOT0 alternate function)
RPU
Weak pull-up equivalent
resistor(8)
RPD
Weak pull-down equivalent
resistor(8)
CIO
I/O pin capacitance
Max(VDDXXX)(9)
VDDIOX < VIN ≤ 9 V
VIN=VSS
Unit
V
V
mV
nA
35
30
40
50
kΩ
VIN=VDD
(9)
-
30
40
50
-
5
-
pF
1. Compliant with CMOS requirement.
2. Guaranteed by design.
DS12556 Rev 6
129/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
3. VDDIOx represents VDDIO1, VDDIO2 or VDDIO3. VDDIOx= VDD.
4. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following
formula: ITotal_Ileak_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max).
5. All FT_xx IO except FT_lu, FT_u and PC3.
6. VIN must be less than Max(VDDXXX) + 3.6 V.
7. To sustain a voltage higher than MIN(VDD, VDDA, VDD33USB) +0.3 V, the internal pull-up and pull-down resistors must be
disabled.
8. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
9. Max(VDDXXX) is the maximum value of all the I/O supplies.
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 18.
Figure 18. VIL/VIH for all I/Os except BOOT0
3
2.5
2
S req
Voltage
CMO
TLL requirement: VIHmin = 2 V
0.7V D
in=
t: V IHm
en
uirem
D
+0.25
=0.47VDD
on VIHmin
ulati
d on sim
1.5
Base
-0.1
=0.4VDD
tion VILmax
la
u
im
on s
=0.3VDD
Based
max
ment: VIL
require
CMOS
TLL requirement: VILmin = 0.8 V
1
0.5
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
MSv46121V3
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2. In particular:
130/336
•
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 20).
•
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
ΣIVSS (see Table 20).
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Output voltage levels
Unless otherwise specified, the parameters given in Table 59 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 22: General operating conditions. All I/Os are CMOS and TTL compliant.
Table 59. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8(1)
Symbol
Parameter
Conditions(3)
Min
Max
Output low level voltage
CMOS
IIO=8 mA
2.7 V≤ VDD ≤3.6 V
-
0.4
Output high level voltage
CMOS port(2)
IIO=-8 mA
2.7 V≤ VDD ≤3.6 V
VDD−0.4
-
Output low level voltage
TTL port(2)
IIO=8 mA
2.7 V≤ VDD ≤3.6 V
-
0.4
Output high level voltage
TTL port(2)
IIO=-8 mA
2.7 V≤ VDD ≤3.6 V
2.4
-
VOL(3)
Output low level voltage
IIO=20 mA
2.7 V≤ VDD ≤3.6 V
-
1.3
VOH(3)
Output high level voltage
IIO=-20 mA
2.7 V≤ VDD ≤3.6 V
VDD−1.3
-
VOL(3)
Output low level voltage
IIO=4 mA
1.62 V≤ VDD ≤3.6 V
-
0.4
VOH (3)
Output high level voltage
IIO=-4 mA
1.62 V≤VDD<3.6 V
VDD−-0.4
-
IIO= 20 mA
2.3 V≤ VDD≤3.6 V
-
0.4
IIO= 10 mA
1.62 V≤ VDD ≤3.6 V
-
0.4
Unit
port(2)
VOL
VOH
VOL(3)
VOH
(3)
VOLFM+(3)
Output low level voltage for an FTf
I/O pin in FM+ mode
V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 19:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 60. Output voltage characteristics for PC13, PC14, PC15 and PI8(1)
Conditions(3)
Min
Max
Output low level voltage
CMOS port(2)
IIO=3 mA
2.7 V≤ VDD ≤3.6 V
-
0.4
Output high level voltage
CMOS port(2)
IIO=-3 mA
2.7 V≤ VDD ≤3.6 V
VDD−0.4
-
Output low level voltage
TTL port(2)
IIO=3 mA
2.7 V≤ VDD ≤3.6 V
-
0.4
Output high level voltage
TTL port(2)
IIO=-3 mA
2.7 V≤ VDD ≤3.6 V
2.4
-
VOL(3)
Output low level voltage
IIO=1.5 mA
1.62 V≤ VDD ≤3.6 V
-
0.4
VOH(3)
Output high level voltage
IIO=-1.5 mA
1.62 V≤ VDD ≤3.6 V
VDD−0.4
-
Symbol
VOL
VOH
VOL(3)
VOH
(3)
Parameter
Unit
V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 19:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Output buffer timing characteristics (HSLV option disabled)
The HSLV bit of SYSCFG_CCCSR register can be used to optimize the I/O speed when the
product voltage is below 2.5 V.
Table 61. Output timing characteristics (HSLV OFF)(1)(2)
Speed
Symbol
Fmax(3)
Parameter
Maximum frequency
00
tr/tf(4)
Fmax(3)
Output high to low level
fall time and output low
to high level rise time
Maximum frequency
01
tr/tf(4)
Output high to low level
fall time and output low
to high level rise time
conditions
Min
Max
C=50 pF, 2.7 V≤ VDD≤3.6 V
-
12
C=50 pF, 1.62 V≤VDD≤2.7 V
-
3
C=30 pF, 2.7 V≤VDD≤3.6 V
-
12
C=30 pF, 1.62 V≤VDD≤2.7 V
-
3
C=10 pF, 2.7 V≤VDD≤3.6 V
-
16
C=10 pF, 1.62 V≤VDD≤2.7 V
-
4
C=50 pF, 2.7 V≤ VDD≤3.6 V
-
16.6
C=50 pF, 1.62 V≤VDD≤2.7 V
-
33.3
C=30 pF, 2.7 V≤VDD≤3.6 V
-
13.3
C=30 pF, 1.62 V≤VDD≤2.7 V
-
25
C=10 pF, 2.7 V≤VDD≤3.6 V
-
10
C=10 pF, 1.62 V≤VDD≤2.7 V
-
20
C=50 pF, 2.7 V≤ VDD≤3.6 V
-
60
C=50 pF, 1.62 V≤VDD≤2.7 V
-
15
C=30 pF, 2.7 V≤VDD≤3.6 V
-
80
C=30 pF, 1.62 V≤VDD≤2.7 V
-
15
C=10 pF, 2.7 V≤VDD≤3.6 V
-
110
C=10 pF, 1.62 V≤VDD≤2.7 V
-
20
C=50 pF, 2.7 V≤ VDD≤3.6 V
-
5.2
C=50 pF, 1.62 V≤VDD≤2.7 V
-
10
C=30 pF, 2.7 V≤VDD≤3.6 V
-
4.2
C=30 pF, 1.62 V≤VDD≤2.7 V
-
7.5
C=10 pF, 2.7 V≤VDD≤3.6 V
-
2.8
C=10 pF, 1.62 V≤VDD≤2.7 V
-
5.2
DS12556 Rev 6
Unit
MHz
ns
MHz
ns
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Table 61. Output timing characteristics (HSLV OFF)(1)(2) (continued)
Speed
Symbol
Parameter
conditions
Min
Max
C=50 pF, 2.7 V≤VDD≤3.6 V
-
85
C=50 pF, 1.62 V≤VDD≤2.7 V(5)
-
35
-
110
C=30 pF, 1.62 V≤VDD≤2.7 V
-
40
C=10 pF, 2.7 V≤VDD≤3.6 V(5)
-
166
C=10 pF, 1.62 V≤VDD≤2.7 V(5)
-
100
-
3.8
(5)
(5)
Fmax(3)
Maximum frequency
10
C=30 pF, 2.7 V≤VDD≤3.6 V
(5)
(5)
C=50 pF, 2.7 V≤VDD≤3.6 V
(5)
C=50 pF, 1.62 V≤VDD≤2.7 V
tr/tf(4)
Output high to low level
fall time and output low
to high level rise time
-
6.9
V(5)
-
2.8
C=30 pF, 1.62 V≤VDD≤2.7 V(5)
-
5.2
C=10 pF, 2.7 V≤VDD≤3.6 V(5)
-
1.8
V(5)
-
3.3
V(5)
-
100
C=50 pF, 1.62 V≤VDD≤2.7 V(5)
-
50
V(5)
-
133
V(5)
-
66
C=10 pF, 2.7 V≤VDD≤3.6 V(5)
-
220
C=10 pF, 1.62 V≤VDD≤2.7 V(5)
-
85
V(5)
-
3.3
V(5)
-
6.6
V(5)
-
2.4
C=30 pF, 1.62 V≤VDD≤2.7 V(5)
-
4.5
C=10 pF, 2.7 V≤VDD≤3.6 V(5)
-
1.5
V(5)
-
2.7
C=30 pF, 2.7 V≤VDD≤3.6
C=10 pF, 1.62 V≤VDD≤2.7
C=50 pF, 2.7 V≤VDD≤3.6
Fmax(3)
Maximum frequency
11
C=30 pF, 2.7 V≤VDD≤3.6
C=30 pF, 1.62 V≤VDD≤2.7
C=50 pF, 2.7 V≤VDD≤3.6
C=50 pF, 1.62 V≤VDD≤2.7
tr/tf(4)
Output high to low level
fall time and output low
to high level rise time
C=30 pF, 2.7 V≤VDD≤3.6
C=10 pF, 1.62 V≤VDD≤2.7
Unit
MHz
ns
MHz
ns
1. Guaranteed by design.
2. The frequency of the GPIOs that can be supplied in VBAT mode (PC13, PC14, PC15 and PI8) is limited to 2 MHz
3. The maximum frequency is defined with the following conditions:
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45%<Duty cycle<55%
4. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
5. Compensation system enabled.
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Output buffer timing characteristics (HSLV option enabled)
Table 62. Output timing characteristics (HSLV ON)(1)
Speed
Symbol
Fmax
(2)
Parameter
Maximum frequency
00
tr/tf(3)
Fmax
(2)
Output high to low level
fall time and output low
to high level rise time
Maximum frequency
01
tr/tf(3)
Fmax
(2)
Output high to low level
fall time and output low
to high level rise time
Maximum frequency
10
tr/tf(3)
Fmax
(2)
Output high to low level
fall time and output low
to high level rise time
Maximum frequency
11
tr/tf(3)
Output high to low level
fall time and output low
to high level rise time
conditions
Min
Max
C=50 pF, 1.62 V≤VDD≤2.7 V
-
10
C=30 pF, 1.62 V≤VDD≤2.7 V
-
10
C=10 pF, 1.62 V≤VDD≤2.7 V
-
10
C=50 pF, 1.62 V≤VDD≤2.7 V
-
11
C=30 pF, 1.62 V≤VDD≤2.7 V
-
9
C=10 pF, 1.62 V≤VDD≤2.7 V
-
6.6
C=50 pF, 1.62 V≤VDD≤2.7 V
-
50
C=30 pF, 1.62 V≤VDD≤2.7 V
-
58
C=10 pF, 1.62 V≤VDD≤2.7 V
-
66
C=50 pF, 1.62 V≤VDD≤2.7 V
-
6.6
C=30 pF, 1.62 V≤VDD≤2.7 V
-
4.8
C=10 pF, 1.62 V≤VDD≤2.7 V
-
3
C=50 pF, 1.62 V≤VDD≤2.7 V(4)
-
55
C=30 pF, 1.62 V≤VDD≤2.7
V(4)
-
80
C=10 pF, 1.62 V≤VDD≤2.7
V(4)
-
133
C=50 pF, 1.62 V≤VDD≤2.7
V(4)
-
5.8
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
-
4
C=10 pF, 1.62 V≤VDD≤2.7
V(4)
-
2.4
C=50 pF, 1.62 V≤VDD≤2.7
V(4)
-
60
C=30 pF, 1.62 V≤VDD≤2.7
V(4)
-
90
C=10 pF, 1.62 V≤VDD≤2.7 V(4)
-
175
C=50 pF, 1.62 V≤VDD≤2.7
V(4)
-
5.3
C=30 pF, 1.62 V≤VDD≤2.7
V(4)
-
3.6
(4)
-
1.9
C=10 pF, 1.62 V≤VDD≤2.7 V
Unit
MHz
ns
MHz
ns
MHz
ns
MHz
ns
1. Guaranteed by design.
2. The maximum frequency is defined with the following conditions:
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45%<Duty cycle<55%
3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
4. Compensation system enabled.
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Electrical characteristics (rev Y)
6.3.16
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 58: I/O static characteristics).
Unless otherwise specified, the parameters given in Table 63 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 22: General operating conditions.
Table 63. NRST pin characteristics
Symbol
RPU(2)
Parameter
Conditions
Min
Typ
Max
Unit
VIN = VSS
30
40
50
㏀
1.71 V < VDD < 3.6 V
-
-
50
1.71 V < VDD < 3.6 V
300
-
-
1.62 V < VDD < 3.6 V
1000
-
-
Weak pull-up equivalent
resistor(1)
VF(NRST)(2) NRST Input filtered pulse
VNF(NRST)(2) NRST Input not filtered pulse
ns
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
2. Guaranteed by design.
Figure 19. Recommended NRST pin protection
VDD
External
reset circuit (1)
NRST (2)
RPU
Internal Reset
Filter
0.1 μF
STM32
ai14132d
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 58. Otherwise the reset is not taken into account by the device.
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6.3.17
Electrical characteristics (rev Y)
FMC characteristics
Unless otherwise specified, the parameters given in Table 64 to Table 77 for the FMC
interface are derived from tests performed under the ambient temperature, frcc_c_ck
frequency and VDD supply voltage conditions summarized in Table 22: General operating
conditions, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output
characteristics.
Asynchronous waveforms and timings
Figure 20 through Figure 23 represent asynchronous waveforms and Table 64 through
Table 71 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
•
AddressSetupTime = 0x1
•
AddressHoldTime = 0x1
•
DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)
•
BusTurnAroundDuration = 0x0
•
Capcitive load CL = 30 pF
In all timing tables, the TKERCK is the fmc_ker_ck clock period.
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 20. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
tw(NE)
FMC_NE
tv(NOE_NE)
t w(NOE)
t h(NE_NOE)
FMC_NOE
FMC_NWE
tv(A_NE)
FMC_A[25:0]
t h(A_NOE)
Address
tv(BL_NE)
t h(BL_NOE)
FMC_NBL[1:0]
t h(Data_NE)
t su(Data_NOE)
th(Data_NOE)
t su(Data_NE)
Data
FMC_D[15:0]
t v(NADV_NE)
tw(NADV)
FMC_NADV
(1)
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32753V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
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DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 64. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)
Symbol
Parameter
Min
Max
2Tfmc_ker_ck − 1
2 Tfmc_ker_ck +1
0
0.5
2Tfmc_ker_ck − 1
2Tfmc_ker_ck + 1
tw(NE)
FMC_NE low time
tv(NOE_NE)
FMC_NEx low to FMC_NOE low
tw(NOE)
FMC_NOE low time
th(NE_NOE)
FMC_NOE high to FMC_NE high hold time
0
-
tv(A_NE)
FMC_NEx low to FMC_A valid
-
0.5
th(A_NOE)
Address hold time after FMC_NOE high
0
-
tv(BL_NE)
FMC_NEx low to FMC_BL valid
-
0.5
th(BL_NOE)
FMC_BL hold time after FMC_NOE high
0
-
tsu(Data_NE)
Data to FMC_NEx high setup time
11
-
tsu(Data_NOE)
Data to FMC_NOEx high setup time
11
-
th(Data_NOE)
Data hold time after FMC_NOE high
0
-
th(Data_NE)
Data hold time after FMC_NEx high
0
-
tv(NADV_NE)
FMC_NEx low to FMC_NADV low
-
0
tw(NADV)
FMC_NADV low time
-
Tfmc_ker_ck + 1
Unit
ns
1. Guaranteed by characterization results.
Table 65. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings(1)(2)
Symbol
Min
Max
FMC_NE low time
7Tfmc_ker_ck +1
7Tfmc_ker_ck +1
FMC_NWE low time
5Tfmc_ker_ck −1
5Tfmc_ker_ck +1
FMC_NWAIT low time
Tfmc_ker_ck −0.5
tsu(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx high
4Tfmc_ker_ck +11
-
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT invalid
3Tfmc_ker_ck+11.5
-
tw(NE)
tw(NOE)
tw(NWAIT)
Parameter
Unit
ns
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
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Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 21. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
tw(NE)
FMC_NEx
FMC_NOE
tv(NWE_NE)
t h(NE_NWE)
tw(NWE)
FMC_NWE
tv(A_NE)
FMC_A[25:0]
th(A_NWE)
Address
tv(BL_NE)
FMC_NBL[1:0]
th(BL_NWE)
NBL
tv(Data_NE)
th(Data_NWE)
Data
FMC_D[15:0]
t v(NADV_NE)
tw(NADV)
FMC_NADV (1)
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32754V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
Table 66. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)
Symbol
tw(NE)
tv(NWE_NE)
tw(NWE)
th(NE_NWE)
tv(A_NE)
Parameter
FMC_NE low time
FMC_NEx low to FMC_NWE low
Min
Max
3Tfmc_ker_ck − 1
3Tfmc_ker_ck
Tfmc_ker_ck
Tfmc_ker_ck + 1
Tfmc_ker_ck − 0.5 Tfmc_ker_ck + 0.5
FMC_NWE low time
FMC_NWE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
th(A_NWE)
Address hold time after FMC_NWE high
tv(BL_NE)
FMC_NEx low to FMC_BL valid
Tfmc_ker_ck
-
-
2
Tfmc_ker_ck − 0.5
-
-
0.5
Tfmc_ker_ck − 0.5
-
th(BL_NWE)
FMC_BL hold time after FMC_NWE high
tv(Data_NE)
Data to FMC_NEx low to Data valid
-
Tfmc_ker_ck + 2.5
th(Data_NWE)
Data hold time after FMC_NWE high
Tfmc_ker_ck+0.5
-
tv(NADV_NE)
FMC_NEx low to FMC_NADV low
-
0
FMC_NADV low time
-
Tfmc_ker_ck + 1
tw(NADV)
1. Guaranteed by characterization results.
140/336
Unit
DS12556 Rev 6
ns
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 67. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings(1)(2)
Symbol
Min
Max
8Tfmc_ker_ck − 1
8Tfmc_ker_ck + 1
FMC_NWE low time
6Tfmc_ker_ck − 1.5
6Tfmc_ker_ck + 0.5
tsu(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx high
5Tfmc_ker_ck + 13
-
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT invalid
4Tfmc_ker_ck+ 13
-
tw(NE)
tw(NWE)
Parameter
FMC_NE low time
Unit
ns
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
Figure 22. Asynchronous multiplexed PSRAM/NOR read waveforms
tw(NE)
FMC_ NE
tv(NOE_NE)
t h(NE_NOE)
FMC_NOE
t w(NOE)
FMC_NWE
th(A_NOE)
tv(A_NE)
FMC_ A[25:16]
Address
tv(BL_NE)
th(BL_NOE)
FMC_ NBL[1:0]
NBL
th(Data_NE)
tsu(Data_NE)
t v(A_NE)
FMC_ AD[15:0]
tsu(Data_NOE)
th(Data_NOE)
Data
Address
th(AD_NADV)
t v(NADV_NE)
tw(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32755V1
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Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 68. Asynchronous multiplexed PSRAM/NOR read timings(1)
Symbol
Parameter
Min
Max
3Tfmc_ker_ck − 1
3Tfmc_ker_ck + 1
2Tfmc_ker_ck
2Tfmc_ker_ck + 0.5
Tfmc_ker_ck − 1
Tfmc_ker_ck + 1
FMC_NOE high to FMC_NE high hold time
0
-
FMC_NEx low to FMC_A valid
-
0.5
FMC_NEx low to FMC_NADV low
0
0.5
FMC_NADV low time
Tfmc_ker_ck − 0.5
Tfmc_ker_ck+1
th(AD_NADV)
FMC_AD(address) valid hold time after
FMC_NADV high
Tfmc_ker_ck + 0.5
-
th(A_NOE)
Address hold time after FMC_NOE high
Tfmc_ker_ck − 0.5
-
th(BL_NOE)
FMC_BL time after FMC_NOE high
0
-
FMC_NEx low to FMC_BL valid
-
0.5
tw(NE)
FMC_NE low time
tv(NOE_NE)
FMC_NEx low to FMC_NOE low
FMC_NOE low time
ttw(NOE)
th(NE_NOE)
tv(A_NE)
tv(NADV_NE)
tw(NADV)
tv(BL_NE)
tsu(Data_NE)
Data to FMC_NEx high setup time
Tfmc_ker_ck − 2
-
tsu(Data_NOE)
Data to FMC_NOE high setup time
Tfmc_ker_ck − 2
-
th(Data_NE)
Data hold time after FMC_NEx high
0
-
th(Data_NOE)
Data hold time after FMC_NOE high
0
-
Unit
ns
1. Guaranteed by characterization results.
Table 69. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)
Symbol
tw(NE)
tw(NOE)
Parameter
FMC_NE low time
FMC_NWE low time
tsu(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx high
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT
invalid
1. Guaranteed by characterization results.
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DS12556 Rev 6
Min
Max
8Tfmc_ker_ck − 1
8Tfmc_ker_ck
5Tfmc_ker_ck − 1.5
5Tfmc_ker_ck + 0.5
5Tfmc_ker_ck + 3
-
4Tfmc_ker_ck
-
Unit
ns
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Figure 23. Asynchronous multiplexed PSRAM/NOR write waveforms
tw(NE)
FMC_ NEx
FMC_NOE
tv(NWE_NE)
t h(NE_NWE)
tw(NWE)
FMC_NWE
th(A_NWE)
tv(A_NE)
FMC_ A[25:16]
Address
tv(BL_NE)
th(BL_NWE)
FMC_ NBL[1:0]
NBL
t v(A_NE)
t v(Data_NADV)
Data
Address
FMC_ AD[15:0]
th(Data_NWE)
th(AD_NADV)
t v(NADV_NE)
tw(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32756V1
Table 70. Asynchronous multiplexed PSRAM/NOR write timings(1)
Symbol
tw(NE)
tv(NWE_NE)
tw(NWE)
th(NE_NWE)
tv(A_NE)
tv(NADV_NE)
tw(NADV)
Parameter
Min
Max
Unit
FMC_NE low time
4Tfmc_ker_c − 1
4Tfmc_ker_ck
FMC_NEx low to FMC_NWE low
Tfmc_ker_c − 1
Tfmc_ker_ck + 0.5
FMC_NWE low time
2Tfmc_ker_ck− 0.5 2Tfmc_ker_ck+ 0.5
FMC_NWE high to FMC_NE high hold time
Tfmc_ker_ck − 0.5
-
FMC_NEx low to FMC_A valid
-
0
FMC_NEx low to FMC_NADV low
0
0.5
Tfmc_ker_ck
Tfmc_ker_ck+ 1
Tfmc_ker_ck+0.5
-
FMC_NADV low time
th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high
ns
th(A_NWE)
Address hold time after FMC_NWE high
Tfmc_ker_ck+0.5
-
th(BL_NWE)
FMC_BL hold time after FMC_NWE high
Tfmc_ker_ck − 0.5
-
-
0.5
-
Tfmc_ker_ck + 2
Tfmc_ker_ck+0.5
-
tv(BL_NE)
FMC_NEx low to FMC_BL valid
tv(Data_NADV) FMC_NADV high to Data valid
th(Data_NWE) Data hold time after FMC_NWE high
1. Guaranteed by characterization results.
DS12556 Rev 6
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Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 71. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)
Symbol
Parameter
FMC_NE low time
tw(NE)
tw(NWE)
FMC_NWE low time
tsu(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx high
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT invalid
Min
Max
9Tfmc_ker_ck – 1
9Tfmc_ker_ck
7Tfmc_ker_ck – 0.5
7Tfmc_ker_ck + 0.5
6Tfmc_ker_ck + 3
-
4Tfmc_ker_ck
-
Unit
ns
1. Guaranteed by characterization results.
Synchronous waveforms and timings
Figure 24 through Figure 27 represent synchronous waveforms and Table 72 through
Table 75 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
•
BurstAccessMode = FMC_BurstAccessMode_Enable
•
MemoryType = FMC_MemoryType_CRAM
•
WriteBurst = FMC_WriteBurst_Enable
•
CLKDivision = 1
•
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
In all the timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following
FMC_CLK maximum values:
144/336
•
For 2.7 V<VDD<3.6 V, FMC_CLK =100 MHz at 20 pF
•
For 1.8 V<VDD<1.9 V, FMC_CLK =100 MHz at 20 pF
•
For 1.62 V<VDD<1.8 V, FMC_CLK =100 MHz at 15 pF
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Figure 24. Synchronous multiplexed NOR/PSRAM read timings
BUSTURN = 0
tw(CLK)
tw(CLK)
FMC_CLK
Data latency = 0
td(CLKL-NExL)
FMC_NEx
t d(CLKL-NADVL)
td(CLKH-NExH)
td(CLKL-NADVH)
FMC_NADV
td(CLKL-AV)
td(CLKH-AIV)
FMC_A[25:16]
td(CLKL-NOEL)
td(CLKH-NOEH)
FMC_NOE
t d(CLKL-ADV)
FMC_AD[15:0]
td(CLKL-ADIV)
tsu(ADV-CLKH)
AD[15:0]
th(CLKH-ADV)
tsu(ADV-CLKH)
D1
tsu(NWAITV-CLKH)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tsu(NWAITV-CLKH)
tsu(NWAITV-CLKH)
th(CLKH-ADV)
D2
th(CLKH-NWAITV)
th(CLKH-NWAITV)
th(CLKH-NWAITV)
MS32757V1
DS12556 Rev 6
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Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 72. Synchronous multiplexed NOR/PSRAM read timings(1)
Symbol
tw(CLK)
Parameter
FMC_CLK period
td(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2)
td(CLKH_NExH)
FMC_CLK high to FMC_NEx high (x= 0…2)
td(CLKL-NADVL)
FMC_CLK low to FMC_NADV low
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x=16…25)
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid (x=16…25)
td(CLKL-NOEL)
FMC_CLK low to FMC_NOE low
td(CLKH-NOEH)
FMC_CLK high to FMC_NOE high
Min
Max
2Tfmc_ker_ck − 1
-
-
1
Tfmc_ker_ck + 0.5
-
-
1.
0
-
-
2.5
Tfmc_ker_ck
-
-
1.5
Tfmc_ker_ck − 0.5
-
td(CLKL-ADV)
FMC_CLK low to FMC_AD[15:0] valid
-
3
td(CLKL-ADIV)
FMC_CLK low to FMC_AD[15:0] invalid
0
-
tsu(ADV-CLKH)
FMC_A/D[15:0] valid data before FMC_CLK high
3
-
th(CLKH-ADV)
FMC_A/D[15:0] valid data after FMC_CLK high
0
-
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
3
-
th(CLKH-NWAIT)
1
-
FMC_NWAIT valid after FMC_CLK high
1. Guaranteed by characterization results.
146/336
DS12556 Rev 6
Unit
ns
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Figure 25. Synchronous multiplexed PSRAM write timings
BUSTURN = 0
tw(CLK)
tw(CLK)
FMC_CLK
Data latency = 0
td(CLKL-NExL)
td(CLKH-NExH)
FMC_NEx
td(CLKL-NADVL)
td(CLKL-NADVH)
FMC_NADV
td(CLKH-AIV)
td(CLKL-AV)
FMC_A[25:16]
td(CLKH-NWEH)
td(CLKL-NWEL)
FMC_NWE
td(CLKL-ADIV)
td(CLKL-ADV)
FMC_AD[15:0]
td(CLKL-Data)
td(CLKL-Data)
AD[15:0]
D1
D2
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
td(CLKH-NBLH)
FMC_NBL
MS32758V1
DS12556 Rev 6
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Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 73. Synchronous multiplexed PSRAM write timings(1)
Symbol
tw(CLK)
Parameter
FMC_CLK period
Min
Max
2Tfmc_ker_ck − 1
-
-
1
Tfmc_ker_ck + 0.5
-
td(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2)
td(CLKH-NExH)
FMC_CLK high to FMC_NEx high (x= 0…2)
td(CLKL-NADVL)
FMC_CLK low to FMC_NADV low
-
1.5
td(CLKL-NADVH)
FMC_CLK low to FMC_NADV high
0
-
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x=16…25)
-
2
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid (x=16…25)
Tfmc_ker_ck
-
-
1.5
Tfmc_ker_ck + 0.5
-
td(CLKL-NWEL)
FMC_CLK low to FMC_NWE low
t(CLKH-NWEH)
FMC_CLK high to FMC_NWE high
td(CLKL-ADV)
FMC_CLK low to FMC_AD[15:0] valid
-
2.5
td(CLKL-ADIV)
FMC_CLK low to FMC_AD[15:0] invalid
0
-
td(CLKL-DATA)
FMC_A/D[15:0] valid data after FMC_CLK low
-
2.5
td(CLKL-NBLL)
FMC_CLK low to FMC_NBL low
-
2
td(CLKH-NBLH)
FMC_CLK high to FMC_NBL high
Tfmc_ker_ck + 0.5
-
tsu(NWAIT-CLKH)
FMC_NWAIT valid before FMC_CLK high
2
-
th(CLKH-NWAIT)
FMC_NWAIT valid after FMC_CLK high
2
-
1. Guaranteed by characterization results.
148/336
DS12556 Rev 6
Unit
ns
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Figure 26. Synchronous non-multiplexed NOR/PSRAM read timings
tw(CLK)
tw(CLK)
FMC_CLK
td(CLKL-NExL)
td(CLKH-NExH)
Data latency = 0
FMC_NEx
td(CLKL-NADVL)
td(CLKL-NADVH)
FMC_NADV
td(CLKH-AIV)
td(CLKL-AV)
FMC_A[25:0]
td(CLKL-NOEL)
td(CLKH-NOEH)
FMC_NOE
tsu(DV-CLKH)
th(CLKH-DV)
tsu(DV-CLKH)
D1
FMC_D[15:0]
D2
tsu(NWAITV-CLKH)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
th(CLKH-NWAITV)
tsu(NWAITV-CLKH)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tsu(NWAITV-CLKH)
th(CLKH-DV)
t h(CLKH-NWAITV)
th(CLKH-NWAITV)
MS32759V1
Table 74. Synchronous non-multiplexed NOR/PSRAM read timings(1)
Symbol
tw(CLK)
t(CLKL-NExL)
Parameter
FMC_CLK period
FMC_CLK low to FMC_NEx low (x=0..2)
Min
Max
2Tfmc_ker_ck − 1
-
-
2
Tfmc_ker_ck + 0.5
-
td(CLKH-NExH)
FMC_CLK high to FMC_NEx high (x= 0…2)
td(CLKL-NADVL)
FMC_CLK low to FMC_NADV low
-
0.5
td(CLKL-NADVH)
FMC_CLK low to FMC_NADV high
0
-
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x=16…25)
-
2
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid (x=16…25)
Tfmc_ker_ck
-
-
1.5
Tfmc_ker_ck + 0.5
-
td(CLKL-NOEL)
FMC_CLK low to FMC_NOE low
td(CLKH-NOEH)
FMC_CLK high to FMC_NOE high
tsu(DV-CLKH)
FMC_D[15:0] valid data before FMC_CLK high
3
-
th(CLKH-DV)
FMC_D[15:0] valid data after FMC_CLK high
0
-
3
-
1
-
tSU(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
th(CLKH-NWAIT)
FMC_NWAIT valid after FMC_CLK high
Unit
ns
1. Guaranteed by characterization results.
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Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 27. Synchronous non-multiplexed PSRAM write timings
tw(CLK)
tw(CLK)
FMC_CLK
td(CLKL-NExL)
td(CLKH-NExH)
Data latency = 0
FMC_NEx
td(CLKL-NADVL)
td(CLKL-NADVH)
FMC_NADV
td(CLKH-AIV)
td(CLKL-AV)
FMC_A[25:0]
td(CLKL-NWEL)
td(CLKH-NWEH)
FMC_NWE
td(CLKL-Data)
FMC_D[15:0]
td(CLKL-Data)
D1
D2
FMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
tsu(NWAITV-CLKH)
td(CLKH-NBLH)
th(CLKH-NWAITV)
FMC_NBL
MS32760V1
Table 75. Synchronous non-multiplexed PSRAM write timings(1)
Symbol
t(CLK)
Parameter
FMC_CLK period
td(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2)
t(CLKH-NExH)
FMC_CLK high to FMC_NEx high (x= 0…2)
Min
Max
2Tfmc_ker_ck − 1
-
-
2
Tfmc_ker_ck + 0.5
-
td(CLKL-NADVL)
FMC_CLK low to FMC_NADV low
-
0.5
td(CLKL-NADVH)
FMC_CLK low to FMC_NADV high
0
-
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x=16…25)
-
2
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid (x=16…25)
Tfmc_ker_ck
-
-
1.5
Tfmc_ker_ck + 1
-
td(CLKL-NWEL)
FMC_CLK low to FMC_NWE low
td(CLKH-NWEH)
FMC_CLK high to FMC_NWE high
td(CLKL-Data)
FMC_D[15:0] valid data after FMC_CLK low
-
3.5
td(CLKL-NBLL)
FMC_CLK low to FMC_NBL low
-
2
td(CLKH-NBLH)
FMC_CLK high to FMC_NBL high
Tfmc_ker_ck + 1
-
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
2
-
th(CLKH-NWAIT)
2
-
FMC_NWAIT valid after FMC_CLK high
1. Guaranteed by characterization results.
150/336
DS12556 Rev 6
Unit
ns
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
NAND controller waveforms and timings
Figure 28 through Figure 31 represent synchronous waveforms, and Table 76 and Table 77
provide the corresponding timings. The results shown in this table are obtained with the
following FMC configuration:
•
COM.FMC_SetupTime = 0x01
•
COM.FMC_WaitSetupTime = 0x03
•
COM.FMC_HoldSetupTime = 0x02
•
COM.FMC_HiZSetupTime = 0x01
•
ATT.FMC_SetupTime = 0x01
•
ATT.FMC_WaitSetupTime = 0x03
•
ATT.FMC_HoldSetupTime = 0x02
•
ATT.FMC_HiZSetupTime = 0x01
•
Bank = FMC_Bank_NAND
•
MemoryDataWidth = FMC_MemoryDataWidth_16b
•
ECC = FMC_ECC_Enable
•
ECCPageSize = FMC_ECCPageSize_512Bytes
•
TCLRSetupTime = 0
•
TARSetupTime = 0
•
CL = 30 pF
In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period.
Figure 28. NAND controller waveforms for read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NWE
td(ALE-NOE)
th(NOE-ALE)
FMC_NOE (NRE)
tsu(D-NOE)
th(NOE-D)
FMC_D[15:0]
MS32767V1
DS12556 Rev 6
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Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 29. NAND controller waveforms for write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
th(NWE-ALE)
td(ALE-NWE)
FMC_NWE
FMC_NOE (NRE)
th(NWE-D)
tv(NWE-D)
FMC_D[15:0]
MS32768V1
Figure 30. NAND controller waveforms for common memory read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
th(NOE-ALE)
td(ALE-NOE)
FMC_NWE
tw(NOE)
FMC_NOE
tsu(D-NOE)
th(NOE-D)
FMC_D[15:0]
MS32769V1
152/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Figure 31. NAND controller waveforms for common memory write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE)
tw(NWE)
th(NOE-ALE)
FMC_NWE
FMC_N OE
td(D-NWE)
tv(NWE-D)
th(NWE-D)
FMC_D[15:0]
MS32770V1
Table 76. Switching characteristics for NAND Flash read cycles(1)
Symbol
tw(N0E)
Parameter
FMC_NOE low width
Min
Max
4Tfmc_ker_ck –0.5
4Tfmc_ker_ck + 0.5
tsu(D-NOE)
FMC_D[15-0] valid data before FMC_NOE high
8
-
th(NOE-D)
FMC_D[15-0] valid data after FMC_NOE high
0
-
td(ALE-NOE)
FMC_ALE valid before FMC_NOE low
-
3Tfmc_ker_ck + 1
th(NOE-ALE)
FMC_NWE high to FMC_ALE invalid
4Tfmc_ker_ck − 2
-
Unit
ns
1. Guaranteed by characterization results.
Table 77. Switching characteristics for NAND Flash write cycles(1)
Symbol
tw(NWE)
Parameter
FMC_NWE low width
tv(NWE-D)
FMC_NWE low to FMC_D[15-0] valid
th(NWE-D)
FMC_NWE high to FMC_D[15-0] invalid
td(D-NWE)
FMC_D[15-0] valid before FMC_NWE high
td(ALE-NWE)
FMC_ALE valid before FMC_NWE low
th(NWE-ALE)
FMC_NWE high to FMC_ALE invalid
Min
Max
4Tfmc_ker_ck − 0.5
4Tfmc_ker_ck + 0.5
0
-
2Tfmc_ker_ck − 0.5
-
5Tfmc_ker_ck − 1
-
-
3Tfmc_ker_ck + 0.5
2Tfmc_ker_ck − 1
-
Unit
ns
1. Guaranteed by characterization results.
DS12556 Rev 6
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Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
SDRAM waveforms and timings
In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following
FMC_SDCLK maximum values:
•
For 1.8 V<VDD<3.6V: FMC_CLK =100 MHz at 20 pF
•
For 1.62 V<DD<1.8 V, FMC_CLK =100 MHz at 15 pF
Figure 32. SDRAM read access waveforms (CL = 1)
FMC_SDCLK
td(SDCLKL_AddC)
th(SDCLKL_AddR)
td(SDCLKL_AddR)
FMC_A[12:0]
Row n
Col2
Col1
Coli
Coln
th(SDCLKL_AddC)
th(SDCLKL_SNDE)
td(SDCLKL_SNDE)
FMC_SDNE[1:0]
th(SDCLKL_NRAS)
td(SDCLKL_NRAS)
FMC_SDNRAS
th(SDCLKL_NCAS)
td(SDCLKL_NCAS)
FMC_SDNCAS
FMC_SDNWE
tsu(SDCLKH_Data)
th(SDCLKH_Data)
Data1
FMC_D[31:0]
Data2
Datai
Datan
MS32751V2
Table 78. SDRAM read timings(1)
Symbol
Parameter
Min
Max
tw(SDCLK)
FMC_SDCLK period
2Tfmc_ker_ck − 1
2Tfmc_ker_ck + 0.5
tsu(SDCLKH _Data)
Data input setup time
3
-
th(SDCLKH_Data)
Data input hold time
0
-
td(SDCLKL_Add)
Address valid time
-
1.5
td(SDCLKL- SDNE)
Chip select valid time
-
1.5
th(SDCLKL_SDNE)
Chip select hold time
0.5
-
td(SDCLKL_SDNRAS)
SDNRAS valid time
-
1
th(SDCLKL_SDNRAS)
SDNRAS hold time
0.5
-
td(SDCLKL_SDNCAS)
SDNCAS valid time
-
0.5
th(SDCLKL_SDNCAS)
SDNCAS hold time
0
-
1. Guaranteed by characterization results.
154/336
DS12556 Rev 6
Unit
ns
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 79. LPSDR SDRAM read timings(1)
Symbol
Parameter
Min
Max
tW(SDCLK)
FMC_SDCLK period
2Tfmc_ker_ck − 1
2Tfmc_ker_ck + 0.5
tsu(SDCLKH_Data)
Data input setup time
3
-
th(SDCLKH_Data)
Data input hold time
0.5
-
td(SDCLKL_Add)
Address valid time
-
2.5
td(SDCLKL_SDNE)
Chip select valid time
-
2.5
th(SDCLKL_SDNE)
Chip select hold time
0
-
td(SDCLKL_SDNRAS
SDNRAS valid time
-
0.5
th(SDCLKL_SDNRAS)
SDNRAS hold time
0
-
td(SDCLKL_SDNCAS)
SDNCAS valid time
-
1.5
th(SDCLKL_SDNCAS)
SDNCAS hold time
0
-
Unit
ns
1. Guaranteed by characterization results.
Figure 33. SDRAM write access waveforms
FMC_SDCLK
td(SDCLKL_AddC)
th(SDCLKL_AddR)
td(SDCLKL_AddR)
FMC_A[12:0]
Row n
Col2
Col1
Coli
Coln
th(SDCLKL_AddC)
th(SDCLKL_SNDE)
td(SDCLKL_SNDE)
FMC_SDNE[1:0]
td(SDCLKL_NRAS)
th(SDCLKL_NRAS)
FMC_SDNRAS
td(SDCLKL_NCAS)
th(SDCLKL_NCAS)
td(SDCLKL_NWE)
th(SDCLKL_NWE)
FMC_SDNCAS
FMC_SDNWE
td(SDCLKL_Data)
FMC_D[31:0]
Data1
Data2
Datai
Datan
th(SDCLKL_Data)
td(SDCLKL_NBL)
FMC_NBL[3:0]
MS32752V2
DS12556 Rev 6
155/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 80. SDRAM write timings(1)
Symbol
Parameter
Min
Max
tw(SDCLK)
FMC_SDCLK period
2Tfmc_ker_ck − 1
2Tfmc_ker_ck + 0.5
td(SDCLKL _Data)
Data output valid time
-
3
th(SDCLKL _Data)
Data output hold time
0
-
td(SDCLKL_Add)
Address valid time
-
1.5
td(SDCLKL_SDNWE)
SDNWE valid time
-
1.5
th(SDCLKL_SDNWE)
SDNWE hold time
0.5
-
td(SDCLKL_ SDNE)
Chip select valid time
-
1.5
th(SDCLKL-_SDNE)
Chip select hold time
0.5
-
td(SDCLKL_SDNRAS)
SDNRAS valid time
-
1
th(SDCLKL_SDNRAS)
SDNRAS hold time
0.5
-
td(SDCLKL_SDNCAS)
SDNCAS valid time
-
1
td(SDCLKL_SDNCAS)
SDNCAS hold time
0.5
-
Unit
ns
1. Guaranteed by characterization results.
Table 81. LPSDR SDRAM write timings(1)
Symbol
Parameter
Min
Max
tw(SDCLK)
FMC_SDCLK period
2Tfmc_ker_ck − 1
2Tfmc_ker_ck + 0.5
td(SDCLKL _Data)
Data output valid time
-
2.5
th(SDCLKL _Data)
Data output hold time
0
-
td(SDCLKL_Add)
Address valid time
-
2.5
td(SDCLKL-SDNWE)
SDNWE valid time
-
2.5
th(SDCLKL-SDNWE)
SDNWE hold time
0
-
td(SDCLKL- SDNE)
Chip select valid time
-
3
th(SDCLKL- SDNE)
Chip select hold time
0
-
td(SDCLKL-SDNRAS)
SDNRAS valid time
-
1.5
th(SDCLKL-SDNRAS)
SDNRAS hold time
0
-
td(SDCLKL-SDNCAS)
SDNCAS valid time
-
1.5
td(SDCLKL-SDNCAS)
SDNCAS hold time
0
-
1. Guaranteed by characterization results.
156/336
DS12556 Rev 6
Unit
ns
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
6.3.18
Electrical characteristics (rev Y)
Quad-SPI interface characteristics
Unless otherwise specified, the parameters given in Table 82 and Table 83 for QUADSPI
are derived from tests performed under the ambient temperature, frcc_c_ck frequency and
VDD supply voltage conditions summarized in Table 22: General operating conditions, with
the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Measurement points are done at CMOS levels: 0.5VDD
•
I/O compensation cell enabled
•
HSLV activated when VDD≤2.7 V
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics.
Table 82. QUADSPI characteristics in SDR mode(1)
Symbol
Fck1/TCK
tw(CKH)
tw(CKL)
ts(IN)
Parameter
QUADSPI clock frequency
QUADSPI clock high and low
time
Data input setup time
Conditions
Min
Typ
Max
2.7 V ≤ VDD<3.6 V
CL=20 pF
-
-
133
1.62 V<VDD<3.6 V
CL=15 pF
-
-
100
TCK/2–0.5
-
TCK/2
TCK/2
-
TCK/2 + 0.5
2
-
-
2.7 V ≤ VDD < 3.6 V
MHz
1.62 V ≤ VDD < 3.6 V
2.7 V ≤ VDD < 3.6 V
Unit
2.5
1
-
-
th(IN)
Data input hold time
tv(OUT)
Data output valid time
-
-
1.5
2
th(OUT)
Data output hold time
-
0.5
-
-
1.62 V ≤ VDD < 3.6 V
1.5
-
ns
-
1. Guaranteed by characterization results.
DS12556 Rev 6
157/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 83. QUADSPI characteristics in DDR mode(1)
Symbol
Fck1/t(CK)
tw(CKH)
tw(CKL)
Parameter
QUADSPI clock
frequency
Data input setup time
thr(IN), thf(IN)
Data input hold time
thr(OUT),
thf(OUT)
Min
Typ
Max
2.7 V<VDD<3.6 V
CL=20 pF
-
-
100
1.62 V<VDD<3.6 V
CL=15 pF
-
-
100
TCK/2 –0.5
-
TCK/2
TCK/2
-
TCK/2+0.5
3
-
-
QUADSPI clock high and
low time
tsr(IN), tsf(IN)
tvr(OUT),
tvf(OUT)
Conditions
Data output valid time
Data output hold time
Unit
MHz
2.7 V ≤ VDD < 3.6 V
1.62 V ≤ VDD < 3.6 V
2.7 V ≤ VDD < 3.6 V
1
-
1
1.62 V ≤ VDD < 3.6 V
-
-
-
1.5
-
-
DHHC=0
-
3.5
4
DHHC=1
Pres=1, 2...
-
TCK/4+3.5
TCK/4+4
DHHC=0
3
-
-
DHHC=1
Pres=1, 2...
TCK/4+3
-
-
ns
1. Guaranteed by characterization results.
Figure 34. Quad-SPI timing diagram - SDR mode
tr(CK)
t(CK)
tw(CKH)
tw(CKL)
tf(CK)
Clock
tv(OUT)
th(OUT)
Data output
D1
D0
ts(IN)
Data input
D0
D2
th(IN)
D1
D2
MSv36878V1
Figure 35. Quad-SPI timing diagram - DDR mode
tr(CLK)
t(CLK)
tw(CLKH)
tw(CLKL)
tf(CLK)
Clock
tvf(OUT)
Data output
thr(OUT)
IO0
tvr(OUT)
IO1
IO2
thf(OUT)
IO3
tsf(IN) thf(IN)
Data input
IO0
IO1
IO4
IO5
tsr(IN) thr(IN)
IO2
IO3
IO4
IO5
MSv36879V3
158/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
6.3.19
Electrical characteristics (rev Y)
Delay block (DLYB) characteristics
Unless otherwise specified, the parameters given in Table 85 for the delay block are derived
from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply
voltage summarized in Table 22: General operating conditions.
Table 84. Dynamics characteristics: Delay Block characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
tinit
Initial delay
-
1400
2200
2400
t∆
Unit Delay
-
35
40
45
Unit
ps
1. Guaranteed by characterization results.
6.3.20
16-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 85 are derived from tests
performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 22: General operating conditions.
Table 85. ADC characteristics(1)
Symbol
Parameter
VDDA
Analog power supply
VREF+
Positive reference voltage
VREF-
Negative reference voltage
fADC
ADC clock frequency
Sampling rate for Fast
channels, BOOST = 1,
fADC = 36 MHz(2)
Conditions
Min
Typ
Max
-
1.62
-
3.6
VDDA ≥ 2 V
2
-
VDDA
VDDA< 2 V
VDDA
-
VSSA
BOOST = 1
-
-
36
BOOST = 0
-
-
20
16-bit resolution
-
-
3.60(2)
14-bit resolution
-
-
4.00(2)
12-bit resolution
-
-
4.50(2)
10-bit resolution
-
-
5.00(2)
2 V ≤ VDDA ≤ 3.3 V
fS
16-bit resolution
-
-
2.00(2)
14-bit resolution
-
-
2.20(2)
12-bit resolution
-
-
2.50(2)
-
2.80(2)
10-bit resolution
-
16-bit resolution
-
-
1.00
14-bit resolution
-
-
1.00
12-bit resolution
-
-
1.00
10-bit resolution
-
-
1.00
8-bit resolution
DS12556 Rev 6
MHz
MSPS
3.30(2)
8-bit resolution
Sampling rate for Slow
channels, BOOST = 0,
fADC = 10 MHz
V
6.00(2)
8-bit resolution
Sampling rate for Fast
channels, BOOST = 0,
fADC = 20 MHz
Unit
1.00
159/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 85. ADC characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fADC = 36 MHz
-
-
3.6
MHz
16-bit resolution
-
-
10
1/fADC
0
-
VREF+
fTRIG
External trigger frequency
VAIN(3)
Conversion voltage range
-
VCMIV
Common mode input
voltage
-
RAIN
External input impedance
-
-
-
50
㏀
CADC
Internal sample and hold
capacitor
-
-
4
-
pF
ADC LDO startup time
-
-
5
10
µs
tADCREG_
STUP
V
VREF/2−
/2+
VREF/2 REF
10%
10%
tSTAB
ADC power-up time
LDO already started
1
tCAL
Offset and linearity
calibration time
-
165,010
-
1,280
tOFF_CAL Offset calibration time
tLATR
tLATRINJ
tS
tCONV
Trigger conversion latency
for regular and injected
channels without aborting
the conversion
Trigger conversion latency
for regular and injected
channels when a regular
conversion is aborted
Sampling time
Total conversion time
(including sampling time)
1.5
2
2.5
CKMODE = 01
-
-
2
CKMODE = 10
2.25
CKMODE = 11
2.125
CKMODE = 00
2.5
3
3.5
CKMODE = 01
-
-
3
CKMODE = 10
-
-
3.25
CKMODE = 11
-
-
3.125
-
1.5
-
810.5
tS + 0.5 + N/2
(9 to 648 cycles in 14-bit
mode)
1. Guaranteed by design.
2. These values are obtained using the following formula: fS = fADC/ tCONV ,
where fADC = 36 MHz and tCONV = 1,5 cycle sampling time + tSAR sampling time.
Refer to the product reference manual for the value of tSAR depending on resolution.
3. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA.
160/336
conversion
cycle
CKMODE = 00
N-bit resolution
DS12556 Rev 6
V
1/fADC
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 86. ADC accuracy(1)(2)(3)
Symbol
Parameter
ET
Total
unadjusted
error
ED
EL
ENOB(5)
SINAD(5)
SNR(5)
THD(5)
Differential
linearity
error
Integral
linearity
error
Effective
number of
bits
(2 MSPS)
Signal-tonoise and
distortion
ratio
(2 MSPS)
Signal-tonoise ratio
(2 MSPS)
Total
harmonic
distortion
Conditions(4)
Single
ended
Differential
Single
ended
Differential
Single
ended
Differential
Single
ended
Differential
Single
ended
Differential
Single
ended
Differential
Single
ended
Differential
Min
Typ
Max
BOOST = 1
-
±6
-
BOOST = 0
-
±8
-
BOOST = 1
-
±10
-
BOOST = 0
-
±16
-
BOOST = 1
-
2
-
BOOST = 0
-
1
-
BOOST = 1
-
8
-
BOOST = 0
-
2
-
BOOST = 1
-
±6
-
BOOST = 0
-
±4
-
BOOST = 1
-
±6
-
BOOST = 0
-
±4
-
BOOST = 1
-
11.6
-
BOOST = 0
-
12
-
BOOST = 1
-
13.3
-
BOOST = 0
-
13.5
-
BOOST = 1
-
71.6
-
BOOST = 0
-
74
-
BOOST = 1
-
81.83
-
BOOST = 0
-
83
-
BOOST = 1
-
72
-
BOOST = 0
-
74
-
BOOST = 1
-
82
-
BOOST = 0
-
83
-
BOOST = 1
-
−78
-
BOOST = 0
-
−80
-
BOOST = 1
-
−90
-
BOOST = 0
-
−95
-
Unit
±LSB
bits
dB
1. Guaranteed by characterization for BGA packages, the values for LQFP packages might differ.
2. ADC DC accuracy values are measured after internal calibration.
3. The above table gives the ADC performance in 16-bit mode.
4. ADC clock frequency ≤ 36 MHz, 2 V ≤ VDDA ≤3.3 V, 1.6 V ≤ VREF ≤ VDDA, BOOSTEN (for I/O) = 1.
5. ENOB, SINAD, SNR and THD are specified for VDDA = VREF = 3.3 V.
Note:
ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
DS12556 Rev 6
161/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in
Section 6.3.14 does not affect the ADC accuracy.
Figure 36. ADC accuracy characteristics (example for 12-bit resolution)
[1LSB IDEAL =
V REF+
4096
(or
V DDA
4096
depending on package)]
EG
4095
4094
4093
(2)
ET
(3)
7
(1)
6
5
EO
4
EL
3
ED
2
1L SBIDEAL
1
0
1
2
3
456
V SSA
7
4093 4094 4095 4096
VDDA
ai14395c
1. Example of an actual transfer curve.
2. Ideal transfer curve.
3. End point correlation line.
4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
162/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Figure 37. Typical connection diagram using the ADC
STM32
VDD
RAIN(1) AINx
VAIN
Cparasitic
Sample and hold ADC
converter
VT
0.6 V
RADC(1)
VT
0.6 V
IL±1 μA
12-bit
converter
C ADC(1)
ai17534b
1. Refer to Table 85 for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
fADC should be reduced.
DS12556 Rev 6
163/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 38 or Figure 39,
depending on whether VREF+ is connected to VDDA or not. The 100 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 38. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32
VREF+(1)
1 μF // 100 nF
VDDA
1 μF // 100 nF
VSSA/VREF+(1)
MSv50648V1
1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176+25 and
TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA.
Figure 39. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32
VREF+/VDDA(1)
1 μF // 100 nF
VREF-/VSSA(1)
MSv50649V1
1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176+25 and
TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA.
164/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
6.3.21
Electrical characteristics (rev Y)
DAC electrical characteristics
Table 87. DAC characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
VDDA
Analog supply voltage
-
1.8
3.3
3.6
VREF+
Positive reference voltage
-
1.80
-
VDDA
VREF-
Negative reference
voltage
-
-
VSSA
-
connected to
VSSA
5
-
-
connected to
VDDA
25
-
-
10.3
13
16
VDD = 2.7 V
-
-
1.6
VDD = 2.0 V
-
-
2.6
VDD = 2.7 V
-
-
17.8
RL
Resistive Load
DAC output
buffer ON
RO(2)
Output Impedance
RBON
Output impedance sample
and hold mode, output
buffer ON
DAC output
buffer ON
Output impedance sample
and hold mode, output
buffer OFF
DAC output
buffer OFF
RBOFF
DAC output buffer OFF
Unit
V
㏀
㏀
㏀
VDD = 2.0 V
-
-
18.7
DAC output buffer OFF
-
-
50
pF
Sample and Hold mode
-
0.1
1
µF
DAC output buffer ON
0.2
-
VREF+
−0.2
V
DAC output buffer OFF
0
-
VREF+
Settling time (full scale: for
a 12-bit code transition
between the lowest and
the highest input codes
Normal mode, DAC output buffer
tSETTLING
when DAC_OUT reaches
OFF, ±1LSB CL=10 pF
the final value of ±0.5LSB,
±1LSB, ±2LSB, ±4LSB,
±8LSB)
-
1.7(2)
2(2)
µs
Wakeup time from off
state (setting the Enx bit in Normal mode, DAC output buffer
the DAC Control register)
ON, CL ≤ 50 pF, RL = 5 ㏀
until the ±1LSB final value
-
5
7.5
µs
VREF+ = 3.6 V
-
850
-
VREF+ = 1.8 V
-
425
-
CL(2)
CSH
(2)
VDAC_OUT
tWAKEUP(3)
Voffset(2)
Capacitive Load
Voltage on DAC_OUT
output
Middle code offset for 1
trim code step
DS12556 Rev 6
µV
165/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 87. DAC characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
No load, middle
code (0x800)
-
360
-
No load, worst
code (0xF1C)
-
490
-
No load,
middle/worst
code (0x800)
-
20
-
-
360*TON/
(TON+TOFF)
-
No load, middle
code (0x800)
-
170
-
No load, worst
code (0xF1C)
-
170
-
No load,
middle/worst
code (0x800)
-
160
-
Sample and Hold mode, Buffer
ON, CSH=100 nF (worst code)
-
170*TON/
(TON+TOFF)
-
Sample and Hold mode, Buffer
OFF, CSH=100 nF (worst code)
-
160*TON/
(TON+TOFF)
-
DAC output
buffer ON
DAC quiescent
IDDA(DAC)
consumption from VDDA
DAC output
buffer OFF
Sample and Hold mode,
CSH=100 nF
DAC output
buffer ON
IDDV(DAC)
DAC consumption from
VREF+
DAC output
buffer OFF
Unit
µA
1. Guaranteed by characterization results.
2. Guaranteed by design.
3. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).
Table 88. DAC accuracy(1)
Symbol
Parameter
Conditions
Min
Typ
Max
DNL
Differential non
linearity(2)
DAC output buffer ON
-
±2
-
DAC output buffer OFF
-
±2
-
DAC output buffer ON, CL ≤ 50 pF,
RL ≥ 5 ㏀
-
±4
-
DAC output buffer OFF,
CL ≤ 50 pF, no RL
-
±4
-
VREF+ = 3.6 V
-
-
±12
VREF+ = 1.8 V
-
-
±25
-
-
±8
INL
Offset
Integral non linearity
(3)
Offset error at code
0x800 (3)
DAC output
buffer ON,
CL ≤ 50 pF,
RL ≥ 5 ㏀
DAC output buffer OFF,
CL ≤ 50 pF, no RL
166/336
DS12556 Rev 6
Unit
LSB
LSB
LSB
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 88. DAC accuracy(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Offset1
Offset error at code
0x001(4)
DAC output buffer OFF,
CL ≤ 50 pF, no RL
-
-
±5
LSB
-
-
±5
OffsetCal
Offset error at code
0x800 after factory
calibration
Gain
Gain error(5)
DAC output
buffer ON,
CL ≤ 50 pF,
RL ≥ 5 ㏀
VREF+ = 3.6 V
LSB
VREF+ = 1.8 V
-
-
±7
DAC output buffer ON,CL ≤ 50 pF,
RL ≥ 5 ㏀
-
-
±1
DAC output buffer OFF,
CL ≤ 50 pF, no RL
-
-
±1
%
TUE
Total unadjusted error
DAC output buffer OFF,
CL ≤ 50 pF, no RL
-
-
±12
LSB
SNR
Signal-to-noise ratio(6)
DAC output buffer ON,CL ≤ 50 pF,
RL ≥ 5 ㏀ , 1 kHz, BW = 500 KHz
-
67.8
-
dB
SINAD
Signal-to-noise and
distortion ratio(6)
DAC output buffer ON, CL ≤ 50 pF,
RL ≥ 5 ㏀ , 1 kHz
-
67.5
-
dB
ENOB
Effective number of
bits
DAC output buffer ON,
CL ≤ 50 pF, RL ≥ 5 ㏀ , 1 kHz
-
10.9
-
bits
1. Guaranteed by characterization.
2. Difference between two consecutive codes minus 1 LSB.
3. Difference between the value measured at Code i and the value measured at Code i on a line drawn between Code 0 and
last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF
when the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON.
6. Signal is -0.5dBFS with Fsampling=1 MHz.
DS12556 Rev 6
167/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 40. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
RL
DAC_OUTx
12-bit
digital to
analog
converter
CL
ai17157V3
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
6.3.22
Voltage reference buffer characteristics
Table 89. VREFBUF characteristics(1)
Symbol
Parameter
Conditions
Normal mode
VDDA
Analog supply voltage
Degraded mode
Normal mode
VREFBUF
_OUT
Voltage Reference
Buffer Output
Min
Typ
Max
VSCALE = 000
2.8
3.3
3.6
VSCALE = 001
2.4
-
3.6
VSCALE = 010
2.1
-
3.6
VSCALE = 011
1.8
-
3.6
VSCALE = 000
1.62
-
2.80
VSCALE = 001
1.62
-
2.40
VSCALE = 010
1.62
-
2.10
VSCALE = 011
1.62
-
1.80
VSCALE = 000
-
2.5
-
VSCALE = 001
-
2.048
-
VSCALE = 010
-
1.8
-
VSCALE = 011
-
1.5
-
VSCALE = 000
VDDA−
150 mV
-
VDDA
VSCALE = 001
VDDA−
150 mV
-
VDDA
VSCALE = 010
VDDA−
150 mV
-
VDDA
VSCALE = 011
VDDA−
150 mV
-
VDDA
(2)
Degraded mode
Unit
V
TRIM
Trim step resolution
-
-
-
±0.05
±0.2
%
CL
Load capacitor
-
-
0.5
1
1.50
uF
168/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 89. VREFBUF characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
esr
Equivalent Serial
Resistor of CL
-
-
-
-
2
Ω
Iload
Static load current
-
-
-
-
4
mA
Iline_reg
Line regulation
2.8 V ≤ VDDA ≤ 3.6 V
Iload = 500 µA
-
200
-
Iload = 4 mA
-
100
-
Iload_reg
Load regulation
500 µA ≤ ILOAD ≤ 4 mA
Normal Mode
-
50
-
ppm/
mA
-
-
-
Tcoeff
xVREFINT
+ 75
ppm/
°C
DC
-
-
60
-
100KHz
-
-
40
-
CL=0.5 µF
-
-
300
-
CL=1 µF
-
-
500
-
CL=1.5 µF
-
-
650
-
-
8
-
Tcoeff
Temperature coefficient −40 °C < TJ < +125 °C
PSRR
Power supply rejection
tSTART
IINRUSH
IDDA(VRE
FBUF)
Start-up time
Control of maximum
DC current drive on
VREFBUF_OUT during
startup phase(3)
-
VREFBUF
consumption from
VDDA
ppm/V
dB
µs
mA
ILOAD = 0 µA
-
-
15
25
ILOAD = 500 µA
-
-
16
30
ILOAD = 4 mA
-
-
32
50
µA
1. Guaranteed by design.
2.
In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (VDDA−drop voltage).
3. To properly control VREFBUF IINRUSH current during the startup phase and the change of scaling, VDDA voltage should be in
the range of 1.8 V-3.6 V, 2.1 V-3.6 V, 2.4 V-3.6 V and 2.8 V-3.6 V for VSCALE = 011, 010, 001 and 000, respectively.
6.3.23
Temperature sensor characteristics
Table 90. Temperature sensor characteristics
Symbol
Parameter
TL(1)
(2)
Avg_Slope
V30(3)
Typ
Max
Unit
VSENSE linearity with temperature
-
-
3
°C
Average slope
-
2
-
mV/°C
V
Voltage at 30°C ± 5 °C
-
0.62
-
(1)
Startup time in Run mode (buffer startup)
-
-
25.2
(1)
ADC sampling time when reading the temperature
9
-
-
Sensor consumption
-
0.18 0.31
Sensor buffer consumption
-
3.8
tstart_run
tS_temp
Min
Isens(1)
Isensbuf(1)
6.5
µs
µA
1. Guaranteed by design.
DS12556 Rev 6
169/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
2. Guaranteed by characterization.
3. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1
byte.
Table 91. Temperature sensor calibration values
Symbol
6.3.24
Parameter
Memory address
TS_CAL1
Temperature sensor raw data acquired value at
30 °C, VDDA=3.3 V
0x1FF1 E820 -0x1FF1 E821
TS_CAL2
Temperature sensor raw data acquired value at
110 °C, VDDA=3.3 V
0x1FF1 E840 - 0x1FF1 E841
Temperature and VBAT monitoring
Table 92. VBAT monitoring characteristics
Symbol
Parameter
Min
Typ
Max
Unit
R
Resistor bridge for VBAT
-
26
-
KΩ
Q
Ratio on VBAT measurement
-
4
-
-
–10
-
+10
%
µs
(1)
Error on Q
Er
tS_vbat(1)
ADC sampling time when reading VBAT input
9
-
-
VBAThigh
High supply monitoring
-
3.55
-
VBATlow
Low supply monitoring
-
1.36
-
V
1. Guaranteed by design.
Table 93. VBAT charging characteristics
Symbol
RBC
Parameter
Battery charging resistor
Condition
Min
Typ
Max
VBRS in PWR_CR3= 0
-
5
-
1.5
-
VBRS in PWR_CR3= 1
Unit
KΩ
Table 94. Temperature monitoring characteristics
Symbol
170/336
Parameter
Min
Typ
Max
TEMPhigh
High temperature monitoring
-
117
-
TEMPlow
Low temperature monitoring
-
–25
-
DS12556 Rev 6
Unit
°C
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
6.3.25
Electrical characteristics (rev Y)
Voltage booster for analog switch
Table 95. Voltage booster for analog switch characteristics(1)
Symbol
VDD
Parameter
Condition
Min
Typ Max Unit
-
1.62
2-6
3.6
V
-
-
-
50
µs
1.62 V ≤ VDD ≤ 2.7 V
-
-
125
2.7 V < VDD < 3.6 V
-
-
250
Supply voltage
tSU(BOOST) Booster startup time
IDD(BOOST) Booster consumption
µA
1. Guaranteed by characterization results.
DS12556 Rev 6
171/336
311
Electrical characteristics (rev Y)
6.3.26
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Comparator characteristics
Table 96. COMP characteristics(1)
Symbol
Conditions
Min
Typ
Max
Analog supply voltage
-
1.62
3.3
3.6
Comparator input voltage
range
-
0
-
VDDA
VBG(2)
Scaler input voltage
-
Refer to VREFINT
VSC
Scaler offset voltage
-
-
±5
±10
BRG_EN=0 (bridge disable)
-
0.2
0.3
BRG_EN=1 (bridge enable)
-
0.8
1
-
-
140
250
High-speed mode
-
2
5
Medium mode
-
5
20
Ultra-low-power mode
-
15
80
High-speed mode
-
50
80
Medium mode
-
0.5
1.2
Ultra-low-power mode
-
2.5
7
High-speed mode
-
50
120
Medium mode
-
0.5
1.2
Ultra-low-power mode
-
2.5
7
Full common mode range
-
±5
±20
No hysteresis
-
0
-
Low hysteresis
-
10
-
Medium hysteresis
-
20
-
High hysteresis
-
30
-
Static
-
400
600
With 50 kHz
±100 mV overdrive
square signal
-
800
-
Static
-
5
7
-
6
-
Static
-
70
100
With 50 kHz
±100 mV overdrive
square signal
-
75
-
VDDA
VIN
IDDA(SCALER)
Parameter
Scaler static consumption
from VDDA
tSTART_SCALER Scaler startup time
tSTART
Comparator startup time to
reach propagation delay
specification
Propagation delay for
200 mV step with 100 mV
overdrive
tD
Voffset
Vhys
Propagation delay for step
> 200 mV with 100 mV
overdrive only on positive
inputs
Comparator offset error
Comparator hysteresis
Ultra-lowpower mode
IDDA(COMP)
Comparator consumption
from VDDA
Medium mode With 50 kHz
±100 mV overdrive
square signal
High-speed
mode
1. Guaranteed by design, unless otherwise specified.
2. Refer to Table 26: Embedded reference voltage.
172/336
DS12556 Rev 6
Unit
V
mV
µA
µs
µs
ns
µs
ns
µs
mV
mV
nA
µA
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
6.3.27
Electrical characteristics (rev Y)
Operational amplifier characteristics
Table 97. OPAMP characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
Analog supply voltage
Range
-
2
3.3
3.6
CMIR
Common Mode Input
Range
-
0
-
VDDA
25°C, no load on output
-
-
±1.5
All voltages and
temperature, no load
-
-
±2.5
-
-
±3.0
-
Offset trim step at low
TRIMOFFSETP
common input voltage
TRIMLPOFFSETP (0.1*V
DDA)
-
-
1.1
1.5
TRIMOFFSETN Offset trim step at high
common input voltage
TRIMLPOFFSETN (0.9*V
DDA)
-
-
1.1
1.5
Drive current
-
-
-
500
Drive current in PGA mode
-
-
-
270
CLOAD
Capacitive load
-
-
-
50
pF
CMRR
Common mode rejection
ratio
-
-
80
-
dB
PSRR
Power supply rejection
ratio
CLOAD ≤ 50pf /
RLOAD ≥ 4 kΩ(2) at 1 kHz,
Vcom=VDDA/2
50
66
-
dB
GBW
Gain bandwidth for high
supply range
-
4
7.3
12.3
MHz
SR
Slew rate (from 10% and
90% of output voltage)
Normal mode
-
3
-
High-speed mode
-
30
-
AO
Open loop gain
-
59
90
129
dB
φm
Phase margin
-
-
55
-
°
GM
Gain margin
-
-
12
-
dB
VIOFFSET
ΔVIOFFSET
ILOAD
ILOAD_PGA
Input offset voltage
Input offset voltage drift
V
mV
μV/°C
mV
DS12556 Rev 6
μA
V/µs
173/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 97. OPAMP characteristics(1) (continued)
Symbol
VOHSAT
VOLSAT
tWAKEUP
Parameter
Conditions
Min
Typ
Max
High saturation voltage
Iload=max or RLOAD=min(2),
Input at VDDA
VDDA
−100 mV
-
-
Low saturation voltage
Iload=max or RLOAD=min(2),
Input at 0 V
-
-
100
Normal
mode
CLOAD ≤ 50pf,
RLOAD ≥ 4 kΩ(2),
follower
configuration
-
0.8
3.2
High
speed
CLOAD ≤ 50pf,
RLOAD ≥ 4 kΩ(2),
follower
configuration
-
0.9
2.8
-
-
2
-
-
-
-
4
-
-
-
-
8
-
-
-
-
16
-
-
-
-
−1
-
-
-
-
−3
-
-
-
-
−7
-
-
-
-
−15
-
-
PGA Gain=2
-
10/10
-
PGA Gain=4
-
30/10
-
PGA Gain=8
-
70/10
-
PGA Gain=16
-
150/10
-
PGA Gain=-1
-
10/10
-
PGA Gain=-3
-
30/10
-
PGA Gain=-7
-
70/10
-
PGA Gain=-15
-
150/10
-
-
−15
-
15
Gain=2
-
GBW/2
-
Gain=4
-
GBW/4
-
Gain=8
-
GBW/8
-
Gain=16
-
GBW/16
-
Wake up time from OFF
state
Non inverting gain value
PGA gain
Inverting gain value
R2/R1 internal resistance
values in non-inverting
PGA mode(3)
Rnetwork
R2/R1 internal resistance
values in inverting PGA
mode(3)
Delta R
PGA BW
174/336
Resistance variation (R1 or
R2)
PGA bandwidth for
different non inverting gain
DS12556 Rev 6
Unit
mV
µs
kΩ/
kΩ
%
MHz
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 97. OPAMP characteristics(1) (continued)
Symbol
en
IDDA(OPAMP)
Parameter
Voltage noise density
OPAMP consumption from
VDDA
Conditions
at
1 KHz
at
10 KHz
Normal
mode
Highspeed
mode
output loaded
with 4 kΩ
no Load,
quiescent mode,
follower
Min
Typ
Max
-
140
-
-
55
-
-
570
1000
Unit
nV/√
Hz
µA
-
610
1200
1. Guaranteed by design, unless otherwise specified.
2. RLOAD is the resistive load connected to VSSA or to VDDA.
3. R2 is the internal resistance between the OPAMP output and th OPAMP inverting input. R1 is the internal resistance
between the OPAMP inverting input and ground. PGA gain = 1 + R2/R1.
DS12556 Rev 6
175/336
311
Electrical characteristics (rev Y)
6.3.28
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Digital filter for Sigma-Delta Modulators (DFSDM) characteristics
Unless otherwise specified, the parameters given in Table 98 for DFSDM are derived from
tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
summarized in Table 22: General operating conditions, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load C = 30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (DFSDMx_CKINx, DFSDMx_DATINx, DFSDMx_CKOUT for
DFSDMx).
Table 98. DFSDM measured timing - 1.62-3.6 V(1)
Symbol
Parameter
Conditions
Min
Typ
Max
fDFSDMCLK
DFSDM clock
1.62 V < VDD < 3.6 V
-
-
250
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 V < VDD < 3.6 V
-
-
20
(fDFSDMCLK/4)
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
2.7 < VDD < 3.6 V
-
-
20
(fDFSDMCLK/4)
SPI mode (SITP[1:0]=0,1),
Internal clock mode
(SPICKSEL[1:0]≠0),
1.62 < VDD < 3.6 V
-
-
20
(fDFSDMCLK/4)
SPI mode (SITP[1:0]=0,1),
Internal clock mode
(SPICKSEL[1:0]≠0),
2.7 < VDD < 3.6 V
-
-
20
(fDFSDMCLK/4)
1.62 < VDD < 3.6 V
-
-
20
45
50
55
fCKIN
(1/TCKIN)
fCKOUT
DuCyCKOUT
176/336
Input clock
frequency
Output clock
frequency
Output clock
frequency duty 1.62 < VDD < 3.6 V
cycle
Even division,
CKOUTDIV[7:0]
= 1, 3, 5...
Odd division,
CKOUTDIV[7:0]
= 2, 4, 6...
Unit
MHz
%
(((n/2+1)/(n+1))* (((n/2+1)/(n+1)) (((n/2+1)/(n+1))*
100)–5
*100)
100)+5
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 98. DFSDM measured timing - 1.62-3.6 V(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
twh(CKIN)
twl(CKIN)
Input clock
high and low
time
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
TCKIN/2 - 0.5
TCKIN/2
-
tsu
Data input
setup time
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
4
-
-
Unit
ns
th
Data input
hold time
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
0.5
-
-
TManchester
Manchester
data period
(recovered
clock period)
Manchester mode (SITP[1:0]=2,3),
Internal clock mode
(SPICKSEL[1:0]≠0),
1.62 < VDD < 3.6 V
(CKOUTDIV+1)
* TDFSDMCLK
-
(2*CKOUTDIV)
* TDFSDMCLK
1. Guaranteed by characterization results.
DS12556 Rev 6
177/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
DFSDM_CKINy
DFSDM_DATINy
DFSDM_CKOUT
(SPICKSEL=0)
tsu
th
twl
twh
tr
tf
tr
tf
SITP = 00
tsu
th
SITP = 01
SPICKSEL=3
SPICKSEL=2
SPICKSEL=1
tsu
DFSDM_DATINy
SPI timing : SPICKSEL = 1, 2, 3
SPI timing : SPICKSEL = 0
Figure 41. Channel transceiver timing diagrams
th
twl
twh
SITP = 0
tsu
th
SITP = 1
DFSDM_DATINy
Manchester timing
SITP = 2
SITP = 3
recovered clock
recovered data
0
0
1
1
0
MS30766V2
178/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
6.3.29
Electrical characteristics (rev Y)
Camera interface (DCMI) timing specifications
Unless otherwise specified, the parameters given in Table 99 for DCMI are derived from
tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply
voltage summarized in Table 22: General operating conditions, with the following
configuration:
•
DCMI_PIXCLK polarity: falling
•
DCMI_VSYNC and DCMI_HSYNC polarity: high
•
Data formats: 14 bits
•
Capacitive load C=30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
Table 99. DCMI characteristics(1)
Symbol
Min
Max
Unit
-
0.4
-
-
80
MHz
Pixel clock input duty cycle
30
70
%
tsu(DATA)
Data input setup time
1
-
th(DATA)
Data input hold time
1
-
-
Parameter
Frequency ratio DCMI_PIXCLK/frcc_c_ck
DCMI_PIXCLK Pixel clock input
DPixel
tsu(HSYNC)
tsu(VSYNC)
DCMI_HSYNC/DCMI_VSYNC input setup time
1.5
-
th(HSYNC)
th(VSYNC)
DCMI_HSYNC/DCMI_VSYNC input hold time
1
-
ns
1. Guaranteed by characterization results.
Figure 42. DCMI timing diagram
1/DCMI_PIXCLK
DCMI_PIXCLK
tsu(HSYNC)
th(HSYNC)
DCMI_HSYNC
tsu(VSYNC)
th(HSYNC)
DCMI_VSYNC
tsu(DATA) th(DATA)
DATA[0:13]
MS32414V2
DS12556 Rev 6
179/336
311
Electrical characteristics (rev Y)
6.3.30
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
LCD-TFT controller (LTDC) characteristics
Unless otherwise specified, the parameters given in Table 100 for LCD-TFT are derived
from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply
voltage summarized in Table 22: General operating conditions, with the following
configuration:
•
LCD_CLK polarity: high
•
LCD_DE polarity: low
•
LCD_VSYNC and LCD_HSYNC polarity: high
•
Pixel formats: 24 bits
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Capacitive load C=30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
•
I/O compensation cell enabled
Table 100. LTDC characteristics (1)
Symbol
fCLK
Parameter
LTDC clock output frequency
Conditions
Min
Max
2.7 V < VDD < 3.6 V,
20 pF
-
150
2.7 V < VDD < 3.6 V
-
133
1.62 V < VDD < 3.6 V
-
90
-
45
55
DCLK
LTDC clock output duty cycle
tw(CLKH),
tw(CLKL)
Clock High time, low time
tv(DATA)
Data output valid time
-
0.5
th(DATA)
Data output hold time
0
-
tv(HSYNC),
tv(VSYNC),
tv(DE)
HSYNC/VSYNC/DE output valid
time
-
0.5
th(HSYNC),
th(VSYNC),
th(DE)
HSYNC/VSYNC/DE output hold
time
0.5
-
MHz
%
tw(CLK)/2−0.5 tw(CLK)/2+0.5
ns
1. Guaranteed by characterization results.
180/336
Unit
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Figure 43. LCD-TFT horizontal timing diagram
tCLK
LCD_CLK
LCD_VSYNC
tv(HSYNC)
tv(HSYNC)
LCD_HSYNC
th(DE)
tv(DE)
LCD_DE
tv(DATA)
LCD_R[0:7]
LCD_G[0:7]
LCD_B[0:7]
Pixel Pixel
1
2
Pixel
N
th(DATA)
HSYNC Horizontal
width back porch
Active width
Horizontal
back porch
One line
MS32749V1
Figure 44. LCD-TFT vertical timing diagram
tCLK
LCD_CLK
tv(VSYNC)
tv(VSYNC)
LCD_VSYNC
LCD_R[0:7]
LCD_G[0:7]
LCD_B[0:7]
M lines data
VSYNC Vertical
width back porch
Active width
Vertical
back porch
One frame
MS32750V1
DS12556 Rev 6
181/336
311
Electrical characteristics (rev Y)
6.3.31
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Timer characteristics
The parameters given in Table 101 are guaranteed by design.
Refer to Section 6.3.15: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 101. TIMx characteristics(1)(2)
Symbol
tres(TIM)
fEXT
ResTIM
tMAX_COUNT
Conditions(3)
Min
Max
Unit
AHB/APBx prescaler=1
or 2 or 4, fTIMxCLK =
200 MHz
1
-
tTIMxCLK
AHB/APBx
prescaler>4, fTIMxCLK =
100 MHz
1
-
tTIMxCLK
Timer external clock
frequency on CH1 to CH4 f
TIMxCLK = 200 MHz
0
fTIMxCLK/2
MHz
Timer resolution
-
16/32
bit
-
65536 ×
65536
tTIMxCLK
Parameter
Timer resolution time
Maximum possible count
with 32-bit counter
-
1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers.
2. Guaranteed by design.
3. The maximum timer frequency on APB1 or APB2 is up to 200 MHz, by setting the TIMPRE bit in the
RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x
Frcc_pclkx_d2.
182/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
6.3.32
Electrical characteristics (rev Y)
Communications interfaces
I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual revision 03 for:
•
Standard-mode (Sm): with a bit rate up to 100 kbit/s
•
Fast-mode (Fm): with a bit rate up to 400 kbit/s.
•
Fast-mode Plus (Fm+): with a bit rate up to 1Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0433 reference manual) and when the i2c_ker_ck frequency is
greater than the minimum shown in the table below:
Table 102. Minimum i2c_ker_ck frequency in all I2C modes
Symbol
Parameter
Condition
Min
Standard-mode
Fast-mode
f(I2CCLK)
I2CCLK
frequency
Fast-mode Plus
Unit
2
Analog filter ON
DNF=0
8
Analog filter OFF
DNF=1
9
Analog filter ON
DNF=0
17
Analog filter OFF
DNF=1
16
MHz
The SDA and SCL I/O requirements are met with the following restrictions:
•
The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain,
the PMOS connected between the I/O pin and VDD is disabled, but still present.
•
The 20 mA output drive requirement in Fast-mode Plus is not supported. This limits the
maximum load Cload supported in Fm+, which is given by these formulas:
tr(SDA/SCL)=0.8473xRpxCload
Rp(min)= (VDD-VOL(max))/IOL(max)
Where Rp is the I2C lines pull-up. Refer to Section 6.3.15: I/O port characteristics for
the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to Table 103 for the analog filter
characteristics:
Table 103. I2C analog filter characteristics(1)
Symbol
Parameter
Min
Max
Unit
tAF
Maximum pulse width of spikes that
are suppressed by the analog filter
50(2)
260(3)
ns
1. Guaranteed by design.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered.
DS12556 Rev 6
183/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 104 for the SPI interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 22: General operating conditions, with the
following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Capacitive load C = 30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
•
I/O compensation cell enabled
•
HSLV activated when VDD ≤ 2.7 V
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 104. SPI dynamic characteristics(1)
Symbol
fSCK
1/tc(SCK)
Parameter
SPI clock frequency
tsu(NSS)
NSS setup time
th(NSS)
NSS hold time
tw(SCKH),
tw(SCKL)
SCK high and low time
184/336
Conditions
Min
Typ
Max
Master mode
1.62 V≤VDD≤3.6 V
90
Master mode
2.7 V≤VDD≤3.6 V
SPI1,2,3
133
Master mode
2.7 V≤VDD≤3.6 V
SPI4,5,6
100
Slave receiver mode
1.62 V≤VDD≤3.6 V
SPI1,2,3
-
-
150
Slave receiver mode
1.62 V≤VDD≤3.6 V
SPI4,5,6
100
Slave mode transmitter/full
duplex
2.7 V≤VDD≤3.6 V
31
Slave mode transmitter/full
duplex
1.62 V≤VDD≤3.6 V
25
Slave mode
Master mode
DS12556 Rev 6
2
-
-
1
-
-
TPLCK - 2
TPLCK
TPLCK + 2
Unit
MHz
ns
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 104. SPI dynamic characteristics(1) (continued)
Symbol
Min
Typ
Max
Master mode
2
-
-
Slave mode
2
-
-
Master mode
1
-
-
Slave mode
1
-
-
ta(SO)
Data output access time Slave mode
9
13
27
tdis(SO)
Data output disable time Slave mode
0
1
5
Slave mode, 2.7 V≤VDD≤3.6 V
-
11.5
16
Slave mode 1.62 V≤VDD≤3.6 V
-
13
20
Master mode
-
1
3
Slave mode, 1.62 V≤VDD≤3.6 V
9
-
-
Master mode
0
-
-
tsu(MI)
tsu(SI)
Parameter
Data input setup time
th(MI)
Data input hold time
th(SI)
tv(SO)
Conditions
Data output valid time
tv(MO)
th(SO)
th(MO)
Data output hold time
Unit
ns
1. Guaranteed by characterization results.
Figure 45. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
SCK input
tsu(NSS)
th(NSS)
tw(SCKH)
tr(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
tw(SCKL)
MISO output
tv(SO)
First bit OUT
th(SO)
Next bits OUT
tf(SCK)
tdis(SO)
Last bit OUT
th(SI)
tsu(SI)
MOSI input
First bit IN
Next bits IN
Last bit IN
MSv41658V1
DS12556 Rev 6
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Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 46. SPI timing diagram - slave mode and CPHA = 1(1)
NSS input
tc(SCK)
tsu(NSS)
tw(SCKH)
ta(SO)
tw(SCKL)
tf(SCK)
th(NSS)
SCK input
CPHA=1
CPOL=0
CPHA=1
CPOL=1
MISO output
tv(SO)
th(SO)
First bit OUT
tsu(SI)
tr(SCK)
Next bits OUT
tdis(SO)
Last bit OUT
th(SI)
First bit IN
MOSI input
Next bits IN
Last bit IN
MSv41659V1
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
Figure 47. SPI timing diagram - master mode(1)
High
NSS input
SCK Output
CPHA= 0
CPOL=0
SCK Output
tc(SCK)
CPHA=1
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=1
tsu(MI)
MISO
INP UT
tw(SCKH)
tw(SCKL)
MSB IN
tr(SCK)
tf(SCK)
BIT6 IN
LSB IN
th(MI)
MOSI
OUTPUT
MSB OUT
tv(MO)
B I T1 OUT
LSB OUT
th(MO)
ai14136c
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
186/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
I2S interface characteristics
Unless otherwise specified, the parameters given in Table 105 for the I2S interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 22: General operating conditions, with the
following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load C = 30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
•
I/O compensation cell enabled
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (CK, SD, WS).
Table 105. I2S dynamic characteristics(1)
Symbol
Parameter
Conditions
Min
Max
Unit
fMCK
I2S Main clock output
-
256x8K
256FS
MHz
fCK
I2S clock frequency
Master data
-
64FS
Slave data
-
64FS
tv(WS)
WS valid time
Master mode
-
3.5
th(WS)
WS hold time
Master mode
0
-
tsu(WS)
WS setup time
Slave mode
1
-
th(WS)
WS hold time
Slave mode
1
-
Master receiver
1
-
Slave receiver
1
-
Master receiver
4
-
Slave receiver
2
-
Slave transmitter (after enable edge)
-
20
Master transmitter (after enable edge)
-
3
Slave transmitter (after enable edge)
9
-
Master transmitter (after enable edge)
0
-
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
tv(SD_ST)
tv(SD_MT)
th(SD_ST)
th(SD_MT)
Data input setup time
Data input hold time
Data output valid time
Data output hold time
MHz
ns
1. Guaranteed by characterization results.
DS12556 Rev 6
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Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 48. I2S slave timing diagram (Philips protocol)(1)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 49. I2S master timing diagram (Philips protocol)(1)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
188/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
SAI characteristics
Unless otherwise specified, the parameters given in Table 106 for SAI are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 22: General operating conditions, with the following
configuration:
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load C=30 pF
•
Measurement points are performed at CMOS levels: 0.5VDD
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (SCK,SD,WS).
Table 106. SAI characteristics(1)
Symbol
Parameter
Conditions
Min
Max
Unit
fMCK
SAI Main clock output
-
256 x 8K
256xFs
MHz
Master data: 32 bits
-
128xFs(3)
Slave data: 32 bits
-
128xFs
Master mode
2.7≤VDD≤3.6V
-
15
Master mode
1.71≤VDD≤3.6V
-
20
Slave mode
7
-
Master mode
1
-
Slave mode
1
-
Master receiver
0.5
-
Slave receiver
1
-
Master receiver
3.5
-
Slave receiver
2
-
Slave transmitter (after enable edge)
2.7≤VDD≤3.6V
-
17
Slave transmitter (after enable edge)
1.62≤VDD≤3.6V
-
20
Slave transmitter (after enable edge)
7
-
Master transmitter (after enable edge)
2.7≤VDD≤3.6V
-
17
Master transmitter (after enable edge)
1.62≤VDD≤3.6V
-
20
Master transmitter (after enable edge)
7.55
-
FCK
SAI clock frequency(2)
tv(FS)
FS valid time
tsu(FS)
FS setup time
th(FS)
FS hold time
tsu(SD_A_MR)
tsu(SD_B_SR)
th(SD_A_MR)
th(SD_B_SR)
tv(SD_B_ST)
th(SD_B_ST)
tv(SD_A_MT)
th(SD_A_MT)
Data input setup time
Data input hold time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
MHz
ns
ns
1. Guaranteed by characterization results.
2. APB clock frequency must be at least twice SAI clock frequency.
3. With FS=192 kHz.
DS12556 Rev 6
189/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 50. SAI master timing waveforms
1/fSCK
SAI_SCK_X
th(FS)
SAI_FS_X
(output)
tv(FS)
tv(SD_MT)
SAI_SD_X
(transmit)
th(SD_MT)
Slot n
tsu(SD_MR)
Slot n+2
th(SD_MR)
SAI_SD_X
(receive)
Slot n
MS32771V1
Figure 51. SAI slave timing waveforms
1/fSCK
SAI_SCK_X
tw(CKH_X)
SAI_FS_X
(input)
tw(CKL_X)
th(FS)
tsu(FS)
tv(SD_ST)
SAI_SD_X
(transmit)
th(SD_ST)
Slot n
tsu(SD_SR)
SAI_SD_X
(receive)
Slot n+2
th(SD_SR)
Slot n
MS32772V1
MDIO characteristics
Table 107. MDIO Slave timing parameters
Symbol
Min
Typ
Max
Unit
Management data clock
-
-
40
MHz
td(MDIO)
Management data input/output output valid time
7
8
20
tsu(MDIO)
Management data input/output setup time
4
-
-
th(MDIO)
Management data input/output hold time
1
-
-
FsDC
Parameter
ns
The MDIO controller is mapped on APB2 domain. The frequency of the APB bus should at
least 1.5 times the MDC frequency: FPCLK2 ≥ 1.5 * FMDC.
190/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Figure 52. MDIO Slave timing diagram
tMDC)
td(MDIO)
tsu(MDIO)
th(MDIO)
MSv40460V1
SD/SDIO MMC card host interface (SDMMC) characteristics
Unless otherwise specified, the parameters given in Table 108 for the SDIO/MMC interface
are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDD
supply voltage conditions summarized in Table 22: General operating conditions, with the
following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Capacitive load C = 30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
•
I/O compensation cell enabled
•
HSLV activated when VDD ≤ 2.7 V
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output
characteristics.
Table 108. Dynamic characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V(1)(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
Clock frequency in data transfer mode
-
0
-
125
MHz
tW(CKL)
Clock low time
9.5
10.5
-
tW(CKH)
Clock high time
8.5
9.5
-
3
-
-
0.5
-
-
3
-
-
-
3.5
5
2
-
-
fPP =50 MHz
ns
CMD, D inputs (referenced to CK) in MMC and SD HS/SDR/DDR mode
tISU
Input setup time HS
tIH
Input hold time HS
tIDW(3)
Input valid window (variable window)
fPP ≥ 50 MHz
ns
CMD, D outputs (referenced to CK) in MMC and SD HS/SDR/DDR mode
tOV
Output valid time HS
tOH
Output hold time HS
fPP ≥ 50 MHz
DS12556 Rev 6
ns
191/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 108. Dynamic characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V(1)(2)
Symbol
Parameter
Conditions
Min
Typ
Max
3
-
-
0.5
-
-
-
1
2
0
-
-
Unit
CMD, D inputs (referenced to CK) in SD default mode
tISUD
Input setup time SD
tIHD
Input hold time SD
fPP =25 MHz
ns
CMD, D outputs (referenced to CK) in SD default mode
tOVD
Output valid default time SD
tOHD
Output hold default time SD
fPP =25 MHz
ns
1. Guaranteed by characterization results.
2. Above 100 MHz, CL = 20 pF.
3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.
Table 109. Dynamic characteristics: eMMC characteristics, VDD = 1.71 to 1.9 V(1)(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
Clock frequency in data transfer mode
-
0
-
120
MHz
tW(CKL)
Clock low time
9.5
10.5
-
tW(CKH)
Clock high time
8.5
9.5
-
2.5
-
-
1
-
-
3.5
-
-
-
5
7
3
-
-
fPP =50 MHz
ns
CMD, D inputs (referenced to CK) in eMMC mode
tISU
Input setup time HS
tIH
Input hold time HS
tIDW(3)
Input valid window (variable window)
fPP ≥ 50 MHz
ns
CMD, D outputs (referenced to CK) in eMMC mode
tOV
Output valid time HS
tOH
Output hold time HS
fPP ≥ 50 MHz
1. Guaranteed by characterization results.
2. CL = 20 pF.
3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.
192/336
DS12556 Rev 6
ns
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Figure 53. SDIO high-speed mode
Figure 54. SD default mode
CK
tOVD
tOHD
D, CMD
(output)
ai14888
Figure 55. DDR mode
CAN (controller area network) interface
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (FDCANx_TX and FDCANx_RX).
DS12556 Rev 6
193/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
USB OTG_FS characteristics
The USB interface is fully compliant with the USB specification version 2.0 and is USB-IF
certified (for Full-speed device operation).
Table 110. USB OTG_FS electrical characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
USB transceiver operating
voltage
-
3.0(1)
-
3.6
V
RPUI
Embedded USB_DP pull-up
value during idle
-
900
1250
1600
RPUR
Embedded USB_DP pull-up
value during reception
-
1400
2300
3200
ZDRV
Output driver impedance(2)
Driver high
and low
28
36
44
VDD33USB
Ω
1. The USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are
degraded in the 2.7 to 3.0 V voltage range.
2. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching
impedance is already included in the embedded driver.
USB OTG_HS characteristics
Unless otherwise specified, the parameters given in Table 111 for ULPI are derived from
tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage
conditions summarized in Table 22: General operating conditions, with the following
configuration:
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Capacitive load C = 20 pF
•
Measurement points are done at CMOS levels: 0.5VDD.
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output
characteristics.
Table 111. Dynamic characteristics: USB ULPI(1)
Symbol
Parameter
Conditions
Min
Typ
Max
tSC
Control in (ULPI_DIR, ULPI_NXT) setup time
-
0.5
-
-
tHC
Control in (ULPI_DIR, ULPI_NXT) hold time
-
6.5
-
-
tSD
Data in setup time
-
2.5
-
-
tHD
Data in hold time
-
0
-
-
2.7 V < VDD < 3.6 V,
CL = 20 pF
-
6.5
8.5
-
-
1.7 V < VDD < 3.6 V,
CL = 15 pF
-
6.5
13
tDC/tDD
Data/control output delay
1. Guaranteed by characterization results.
194/336
DS12556 Rev 6
Unit
ns
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Figure 56. ULPI timing diagram
Clock
Control In
(ULPI_DIR,
ULPI_NXT)
tSC
tHC
tSD
tHD
data In
(8-bit)
tDC
tDC
Control out
(ULPI_STP)
tDD
data out
(8-bit)
ai17361c
Ethernet characteristics
Unless otherwise specified, the parameters given in Table 112, Table 113 and Table 114 for
SMI, RMII and MII are derived from tests performed under the ambient temperature,
frcc_c_ck frequency summarized in Table 22: General operating conditions, with the following
configuration:
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load C = 20 pF
•
Measurement points are done at CMOS levels: 0.5VDD.
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output
characteristics.
Table 112 gives the list of Ethernet MAC signals for the SMI and Figure 57 shows the
corresponding timing diagram.
Table 112. Dynamics characteristics: Ethernet MAC signals for SMI(1)
Symbol
tMDC
Parameter
Min
Typ
Max
MDC cycle time(2.5 MHz)
400
400
403
Td(MDIO)
Write data valid time
1
1.5
3
tsu(MDIO)
Read data setup time
8
-
-
th(MDIO)
Read data hold time
0
-
-
Unit
ns
1. Guaranteed by characterization results.
DS12556 Rev 6
195/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 57. Ethernet SMI timing diagram
tMDC
ETH_MDC
td(MDIO)
ETH_MDIO(O)
tsu(MDIO)
th(MDIO)
ETH_MDIO(I)
MS31384V1
Table 113 gives the list of Ethernet MAC signals for the RMII and Figure 58 shows the
corresponding timing diagram.
Table 113. Dynamics characteristics: Ethernet MAC signals for RMII(1)
Symbol
Parameter
Min
Typ
Max
tsu(RXD)
Receive data setup time
2
-
-
tih(RXD)
Receive data hold time
3
-
-
tsu(CRS)
Carrier sense setup time
2.5
-
-
tih(CRS)
Carrier sense hold time
2
-
-
td(TXEN)
Transmit enable valid delay time
4
4.5
7
td(TXD)
Transmit data valid delay time
7
7.5
11.5
Unit
ns
1. Guaranteed by characterization results.
Figure 58. Ethernet RMII timing diagram
RMII_REF_CLK
td(TXEN)
td(TXD)
RMII_TX_EN
RMII_TXD[1:0]
tsu(RXD)
tsu(CRS)
tih(RXD)
tih(CRS)
RMII_RXD[1:0]
RMII_CRS_DV
ai15667b
Table 114 gives the list of Ethernet MAC signals for MII and Figure 59 shows the
corresponding timing diagram.
196/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Table 114. Dynamics characteristics: Ethernet MAC signals for MII(1)
Symbol
Parameter
Min
Typ
Max
tsu(RXD)
Receive data setup time
2
-
-
tih(RXD)
Receive data hold time
3
-
-
tsu(DV)
Data valid setup time
1.5
-
-
tih(DV)
Data valid hold time
1
-
-
tsu(ER)
Error setup time
1.5
-
-
tih(ER)
Error hold time
0.5
-
-
td(TXEN)
Transmit enable valid delay time
4.5
6.5
11
td(TXD)
Transmit data valid delay time
7
7.5
15
Unit
ns
1. Guaranteed by characterization results.
Figure 59. Ethernet MII timing diagram
MII_RX_CLK
tsu(RXD)
tsu(ER)
tsu(DV)
tih(RXD)
tih(ER)
tih(DV)
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
MII_TX_CLK
td(TXEN)
td(TXD)
MII_TX_EN
MII_TXD[3:0]
ai15668b
6.3.33
JTAG/SWD interface characteristics
Unless otherwise specified, the parameters given in Table 115 and Table 116 for JTAG/SWD
are derived from tests performed under the ambient temperature, frcc_c_ck frequency and
VDD supply voltage summarized in Table 22: General operating conditions, with the
following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 0x10
•
Capacitive load C=30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output
characteristics.
DS12556 Rev 6
197/336
311
Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 115. Dynamics JTAG characteristics(1)
Symbol
Parameter
Fpp
1/tc(TCK)
TCK clock
frequency
Conditions
Min
Typ
Max
2.7 V <VDD< 3.6 V
-
-
37
MHz
1.62 V <VDD< 3.6 V
-
-
27.5
tisu(TMS)
TMS input
setup time
-
2
-
-
tih(TMS)
TMS input
hold time
-
1
-
-
tisu(TDI)
TDI input
setup time
-
1.5
-
-
tih(TDI)
TDI input
hold time
-
1
-
-
TDO output
valid time
2.7 V <VDD< 3.6 V
-
8
13.5
tov (TDO)
1.62 V <VDD< 3.6 V
-
8
18
-
7
-
-
toh(TDO)
Unit
TDO output
hold time
ns
1. Guaranteed by characterization results.
Table 116. Dynamics SWD characteristics(1)
Symbol
Parameter
Fpp
Conditions
Min
Typ
Max
2.7 V <VDD< 3.6 V
-
-
71
1.62 V <VDD< 3.6 V
-
-
55.5
1/tc(SWCLK)
SWCLK
clock
frequency
tisu(SWDIO)
SWDIO input
setup time
-
2.5
-
-
tih(SWDIO)
SWDIO input
hold time
-
1
-
-
2.7 V <VDD< 3.6 V
-
8.5
14
tov (SWDIO)
SWDIO
output valid
time
1.62 V <VDD< 3.6 V
-
8.5
18
-
8
-
-
toh(SWDIO)
MHz
SWDIO
output hold
time
1. Guaranteed by characterization results.
198/336
Unit
DS12556 Rev 6
ns
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
Figure 60. JTAG timing diagram
tc(TCK)
TCK
tsu(TMS/TDI)
th(TMS/TDI)
tw(TCKL) tw(TCKH)
TDI/TMS
tov(TDO)
toh(TDO)
TDO
MSv40458V1
Figure 61. SWD timing diagram
tc(SWCLK)
SWCLK
tsu(SWDIO)
th(SWDIO)
twSWCLKL) tw(SWCLKH)
SWDIO
(receive)
tov(SWDIO)
toh(SWDIO)
SWDIO
(transmit)
MSv40459V1
DS12556 Rev 6
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311
Electrical characteristics (rev V)
7
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
7.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
7.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of junction temperature, supply voltage and frequencies by tests in production on
100% of the devices with an junction temperature at TJ = 25 °C and TJ = TJmax (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean±3σ).
7.1.2
Typical values
Unless otherwise specified, typical data are based on TJ = 25 °C, VDD = 3.3 V (for the
1.7 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
7.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
7.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 62.
7.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 63.
Figure 62. Pin loading conditions
Figure 63. Pin input voltage
MCU pin
MCU pin
C = 50 pF
VIN
MS19011V2
200/336
DS12556 Rev 6
MS19010V2
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
7.1.6
Electrical characteristics (rev V)
Power supply scheme
Figure 64. Power supply scheme
VDD50USB
100 nF
100 nF
VDD33USB
1μF
VDD33USB
USB
IOs
USB
regulator
Level shifter
Power
switch
VSS
IOs
N(1) x 100 nF
+ 1 x 4.7 μF
VDD
D3 domain
(System
logic,
EXTI,
IO
logic Peripherals,
RAM)
D2 domain
(peripherals,
RAM)
D1 domain
(CPU, peripherals,
RAM)
VDD domain
VBAT
charging
HSI, LSI,
CSI, HSI48,
HSE, PLLs
Backup domain
Backup VBKP
regulator
VSW
VBAT
Power switch
Power switch
LSE, RTC,
Wakeup logic,
backup
IO
registers,
logic
Reset
BKUP
IOs
VREF
100 nF + 1 x 1 μF
100 nF + 1 x 1 μF
VDDA
VDDA
Flash
VSS
VDD
VBAT
1.2 to 3.6V
VSS
Core domain (VCORE)
Voltage
regulator
VDDLDO
4.7μF
2 x 2.2μF
VDDLDO
VCAP
Power
switch
VSS
VDD50USB
VSS
Analog domain
REF_BUF
VREF+
ADC, DAC
VREF+
VREF-
VREF-
Backup
RAM
VSS
OPAMP,
Comparator
VSSA
MSv46116V5
1. N corresponds to the number of VDD pins available on the package.
2. A tolerance of +/- 20% is acceptable on decoupling capacitors.
Caution:
Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure good operation of the
DS12556 Rev 6
201/336
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
7.1.7
Current consumption measurement
Figure 65. Current consumption measurement scheme
IDD_VBAT
VBAT
IDD
VDD
VDDA
ai14126
7.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 117: Voltage characteristics,
Table 118: Current characteristics, and Table 119: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and the functional operation
of the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are
available on demand.
Table 117. Voltage characteristics (1)
Symbols
VDDX - VSS
VIN(2)
Ratings
Min
Max
Unit
−0.3
4.0
V
Input voltage on FT_xxx pins
VSS−0.3
Min(VDD, VDDA,
VDD33USB, VBAT)
+4.0(3)(4)
V
Input voltage on TT_xx pins
VSS-0.3
4.0
V
Input voltage on BOOT0 pin
VSS
9.0
V
VSS-0.3
4.0
V
-
50
mV
-
50
mV
External main supply voltage (including VDD,
VDDLDO, VDDA, VDD33USB, VBAT)
Input voltage on any other pins
|∆VDDX|
Variations between different VDDX power pins
of the same domain
|VSSx-VSS| Variations between all the different ground pins
1. All main power (VDD, VDDA, VDD33USB, VBAT) and ground (VSS, VSSA) pins must always be connected to
the external power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 154: I/O current injection susceptibility for the
maximum allowed injected current values.
202/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
3. This formula has to be applied on power supplies related to the IO structure described by the pin definition
table.
4. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled.
Table 118. Current characteristics
Symbols
Ratings
Max
ΣIVDD
Total current into sum of all VDD power lines (source)(1)
620
ΣIVSS
(sink)(1)
620
Total current out of sum of all VSS ground lines
IVDD
Maximum current into each VDD power pin
(source)(1)
100
IVSS
Maximum current out of each VSS ground pin (sink)(1)
100
Output current sunk by any I/O and control pin
IIO
Total output current sunk by sum of all I/Os and control
ΣI(PIN)
IINJ(PIN)
(3)(4)
ΣIINJ(PIN)
Unit
20
pins(2)
mA
140
Total output current sourced by sum of all I/Os and control pins(2)
140
Injected current on FT_xxx, TT_xx, RST and B pins except PA4,
PA5
−5/+0
Injected current on PA4, PA5
−0/0
Total injected current (sum of all I/Os and control pins)(5)
±25
1. All main power (VDD, VDDA, VDD33USB) and ground (VSS, VSSA) pins must always be connected to the
external power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
QFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer also to Table 117: Voltage characteristics for the maximum allowed input voltage
values.
5. When several inputs are submitted to a current injection, the maximum ∑IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
Table 119. Thermal characteristics
Symbol
TSTG
TJ
Ratings
Storage temperature range
Maximum junction temperature
DS12556 Rev 6
Value
− 65 to +150
125
Unit
°C
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
7.3
Operating conditions
7.3.1
General operating conditions
Table 120. General operating conditions
Symbol
Parameter
VDD
Standard operating voltage
VDDLDO
Supply voltage for the internal
regulator
VDD33USB
Standard operating voltage, USB
domain
VDDA
Analog operating voltage
Operating
conditions
Min
Typ
Max
Unit
-
1.62(1)
-
3.6
V
VDDLDO ≤ VDD
1.62(1)
-
3.6
3.0
-
3.6
0
-
3.6
ADC or COMP used
1.62
-
DAC used
1.8
-
OPAMP used
2.0
-
VREFBUF used
1.8
-
0
-
−0.3
-
VDD+0.3
0
-
9
USB used
USB not used
ADC, DAC, OPAMP,
COMP, VREFBUF not
used
TT_xx I/O
BOOT0
VIN
I/O Input voltage
Internal regulator ON (LDO)
VCORE
V
All I/O except BOOT0
and TT_xx
−0.3
-
Min(VDD, VDDA,
VDD33USB)
+3.6V <
5.5V(2)(3)
VOS3 (max frequency
200 MHz)
0.95
1.0
1.26
VOS2 (max frequency
300 MHz)
1.05
1.10
1.26
VOS1 (max frequency
400 MHz)
1.15
1.20
1.26
VOS0(4) (max
frequency 480 MHz(5))
1.26
1.35
1.40
VOS3 (max frequency
200 MHz)
0.98
1.03
1.26
1.08
1.13
1.26
1.17
1.23
1.26
1.37
1.38
1.40
VOS2 (max frequency
Regulator OFF: external VCORE
300 MHz)
voltage must be supplied from external
VOS1 (max frequency
regulator on two VCAP pins
400 MHz)
VOS0 (max frequency
480 MHz(5))
204/336
3.6
DS12556 Rev 6
V
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 120. General operating conditions (continued)
Symbol
fCPU
Operating
conditions
Parameter
Arm® Cortex®-M7 clock frequency
fHCLK
AHB clock frequency
fPCLK
APB clock frequency
Min
Typ
Max
VOS3
-
-
200
VOS2
-
-
300
VOS1
-
-
400
VOS0
-
-
480(5)
VOS3
-
-
100
VOS2
-
-
150
VOS1
-
-
200
VOS0
-
-
240(5)
VOS3
-
-
50(6)
VOS2
-
-
75
VOS1
-
-
100
VOS0
-
-
120(5)
–40
85
–40
105
–40
125
TA
Ambient temperature for the suffix 6
version
Maximum power dissipation
TJ
Junction temperature range
Suffix 6 version
Low-power dissipation
(7)
Unit
MHz
°C
°C
1. When RESET is released functionality is guaranteed down to VBOR0 min
2. This formula has to be applied on power supplies related to the IO structure described by the pin definition table.
3. For operation with voltage higher than Min (VDD, VDDA, VDD33USB) +0.3V, the internal Pull-up and Pull-Down resistors must
be disabled.
4. VOS0 is available only when the LDO regulator is ON.
5. TJmax = 105 °C.
6. Maximum APB clock frequency when at least one peripheral is enabled.
7. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 8.6:
Thermal characteristics).
Table 121. Supply voltage and maximum frequency configuration
Power scale
VCORE source
Max TJ (°C)
Max frequency (MHz)
Min VDDLDO (V)
VOS0
LDO
105
480
1.7
VOS1
LDO
125
400
1.62
VOS2
LDO
125
300
1.62
VOS3
LDO
125
200
1.62
SVOS4
LDO
105
N/A
1.62
SVOS5
LDO
105
N/A
1.62
DS12556 Rev 6
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311
Electrical characteristics (rev V)
7.3.2
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
VCAP external capacitor
Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to
the VCAP pin. CEXT is specified in Table 122. Two external capacitors can be connected to
VCAP pins.
Figure 66. External capacitor CEXT
C
ESR
R Leak
MS19044V2
1. Legend: ESR is the equivalent series resistance.
Table 122. VCAP operating conditions(1)
Symbol
Parameter
Conditions
CEXT
Capacitance of external capacitor
2.2 µF(2)
ESR
ESR of external capacitor
< 100 mΩ
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
2. This value corresponds to CEXT typical value. A variation of +/-20% is tolerated.
7.3.3
Operating conditions at power-up / power-down
Subject to general operating conditions for TA.
Table 123. Operating conditions at power-up / power-down (regulator ON)
Symbol
tVDD
tVDDA
tVDDUSB
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Parameter
Min
Max
VDD rise time rate
0
∞
VDD fall time rate
10
∞
VDDA rise time rate
0
∞
VDDA fall time rate
10
∞
VDDUSB rise time rate
0
∞
VDDUSB fall time rate
10
∞
DS12556 Rev 6
Unit
µs/V
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
7.3.4
Electrical characteristics (rev V)
Embedded reset and power control block characteristics
The parameters given in Table 124 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 120: General
operating conditions.
Table 124. Reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tRSTTEMPO(1)
Reset temporization
after BOR0 released
-
-
377
-
µs
VBOR0
Brown-out reset threshold 0
Rising edge(1)
1.62
1.67
1.71
Falling edge
1.58
1.62
1.68
VBOR1
Brown-out reset threshold 1
2.04
2.10
2.15
1.95
2.00
2.06
VBOR2
Brown-out reset threshold 2
2.34
2.41
2.47
2.25
2.31
2.37
VBOR3
Brown-out reset threshold 3
2.63
2.70
2.78
2.54
2.61
2.68
VPVD0
Programmable Voltage
Detector threshold 0
Rising edge
1.90
1.96
2.01
1.81
1.86
1.91
VPVD1
Programmable Voltage
Detector threshold 1
Rising edge
2.05
2.10
2.16
1.96
2.01
2.06
VPVD2
Programmable Voltage
Detector threshold 2
Rising edge
2.19
2.26
2.32
2.10
2.15
2.21
VPVD3
Programmable Voltage
Detector threshold 3
Rising edge
2.35
2.41
2.47
2.25
2.31
2.37
VPVD4
Programmable Voltage
Detector threshold 4
Rising edge
2.49
2.56
2.62
2.39
2.45
2.51
VPVD5
Programmable Voltage
Detector threshold 5
Rising edge
2.64
2.71
2.78
2.55
2.61
2.68
VPVD6
Programmable Voltage
Detector threshold 6
Rising edge
2.78
2.86
2.94
2.69
2.76
2.83
Vhyst_BOR_PVD
Hysteresis voltage of BOR
(unless BOR0) and PVD
Hysteresis in Run mode
-
100
-
mV
IDD_BOR_PVD(1)
BOR(2) (unless BOR0) and
PVD consumption from VDD
-
-
0.630
µA
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Falling edge
Falling edge
Falling edge
Falling edge
Falling edge
Falling edge
Falling edge in Run mode
DS12556 Rev 6
V
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 124. Reset and power control block characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
VAVM_0
Analog voltage detector for
VDDA threshold 0
Rising edge
1.66
1.71
1.76
1.56
1.61
1.66
VAVM_1
Analog voltage detector for
VDDA threshold 1
Rising edge
2.06
2.12
2.19
1.96
2.02
2.08
VAVM_2
Analog voltage detector for
VDDA threshold 2
Rising edge
2.42
2.50
2.58
2.35
2.42
2.49
VAVM_3
Analog voltage detector for
VDDA threshold 3
Rising edge
2.74
2.83
2.91
2.64
2.72
2.80
Vhyst_VDDA
Hysteresis of VDDA voltage
detector
-
-
100
-
mV
IDD_PVM
PVM consumption from
VDD(1)
-
-
-
0.25
µA
IDD_VDDA
Voltage detector
consumption on VDDA(1)
-
-
2.5
µA
Falling edge
Falling edge
Falling edge
Falling edge
Resistor bridge
Unit
V
1. Guaranteed by design.
2. BOR0 is enabled in all modes and its consumption is therefore included in the supply current characteristics tables (refer to
Section 7.3.6: Supply current characteristics).
7.3.5
Embedded reference voltage
The parameters given in Table 125 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 120: General
operating conditions.
Table 125. Embedded reference voltage
Symbol
VREFINT
tS_vrefint(1)(2)
tS_vbat(1)(2)
Irefbuf(2)
ΔVREFINT(2)
Tcoeff(2)
VDDcoeff(2)
208/336
Parameter
Conditions
Min
Typ
Max
Unit
-40°C < TJ < 125 °C,
VDD = 3.3 V
1.180
1.216
1.255
V
ADC sampling time when
reading the internal reference
voltage
-
4.3
-
-
VBAT sampling time when
reading the internal VBAT
reference voltage
-
9
-
-
VDDA=3.3 V
9
13.5
23
µA
Internal reference voltage
spread over the temperature
range
-40°C < TJ < 125 °C
-
5
15
mV
Average temperature
coefficient
Average temperature
coefficient
-
20
70
ppm/°C
3.0V < VDD < 3.6V
-
10
1370
ppm/V
Internal reference voltages
Reference Buffer
consumption for ADC
Average Voltage coefficient
µs
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 125. Embedded reference voltage (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
VREFINT_DIV1 1/4 reference voltage
-
-
25
-
VREFINT_DIV2 1/2 reference voltage
-
-
50
-
VREFINT_DIV3 3/4 reference voltage
-
-
75
-
1.
The shortest sampling time for the application can be determined by multiple iterations.
2.
Guaranteed by design.
Unit
%
VREFINT
Table 126. Internal reference voltage calibration values
Symbol
Parameter
Raw data acquired at temperature of 30 °C, VDDA = 3.3 V
VREFIN_CAL
7.3.6
Memory address
1FF1E860 - 1FF1E861
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 65: Current consumption
measurement scheme.
All the run-mode current consumption measurements given in this section are performed
with a CoreMark code.
Typical and maximum current consumption
The MCU is placed under the following conditions:
•
All I/O pins are in analog input mode.
•
All peripherals are disabled except when explicitly mentioned.
•
The Flash memory access time is adjusted with the minimum wait states number,
depending on the fACLK frequency (refer to the table “Number of wait states according to
CPU clock (frcc_c_ck) frequency and VCORE range” available in the reference manual).
•
When the peripherals are enabled, the AHB clock frequency is the CPU frequency
divided by 2 and the APB clock frequency is AHB clock frequency divided by 2.
The parameters given in the below tables are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 120: General operating
conditions.
DS12556 Rev 6
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311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 127. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM, LDO regulator ON(1)
Max(2)
Symbol
Parameter
Conditions
VOS0
VOS1
All
peripherals
disabled
IDD
Supply
current in
Run mode
VOS2
VOS3
VOS0
All
peripherals
enabled
VOS1
VOS2
VOS3
fHCLK
(MHz)
Typ
480
Tj=25
°C
Tj=85
°C
Tj=105
°C
Tj=125
°C
148
226
307
390
-
400
125
-
-
-
-
400
110
168
230
296
384
300
84
-
-
-
-
300
76
114
170
224
297
216
56
88
152
205
278
200
53
-
-
-
-
200
47
71
121
164
223
180
43
64
116
159
218
168
40
63
115
158
217
144
35
55
109
153
212
60
16
36
92
135
194
25
12
24
83
126
185
480
226
348
439
550
-
400
190
-
-
-
-
400
167
256
327
416
536
300
135
-
-
-
-
300
122
183
248
320
419
200
85
-
-
-
-
200
76
116
174
233
313
1. Data are in DTCM for best computation performance, the cache has no influence on consumption in this case.
2. Guaranteed by characterization results, unless otherwise specified.
210/336
DS12556 Rev 6
Unit
mA
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 128. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache ON,
LDO regulator ON
Max(1)
Symbol
Parameter
Conditions
VOS0
All
peripherals
disabled
VOS1
VOS2
IDD
Supply
current in
Run mode
VOS3
VOS0
All
peripherals
enabled
VOS1
VOS2
VOS3
fHCLK
(MHz)
Typ
480
Tj=25
°C
Tj=85
°C
Tj=105
°C
Tj=125
°C
110
222
304
388
-
400
91
-
-
-
-
400
80
162
228
294
381
300
61.5
-
-
-
-
300
55
111
168
222
294
200
38.5
-
-
-
-
200
34.5
69
120
163
222
480
220
342
436
546
-
400
195
-
-
-
-
400
175
264
336
424
544
300
135
-
-
-
-
300
120
180
246
318
418
200
83
-
-
-
-
200
75
114
173
232
312
Unit
mA
1. Guaranteed by characterization results, unless otherwise specified.
Table 129. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache OFF,
LDO regulator ON
Max(1)
Symbol
Parameter
Typ
VOS0
480
87
157
VOS1
400
73
VOS2
300
VOS3
Conditions
All
peripherals
disabled
IDD
fHCLK
(MHz)
Supply
current in
Run mode
All
peripherals
enabled
Tj=105
°C
Tj=125
°C
259
342
453
123
201
267
355
52
85
150
204
277
200
34
54
109
152
212
VOS0
480
168
276
390
504
658
VOS1
400
135
224
308
397
519
VOS2
300
100
154
228
301
401
VOS3
200
70
103
167
226
307
Tj=25°C Tj=85°C
Unit
mA
1. Guaranteed by characterization results, unless otherwise specified.
DS12556 Rev 6
211/336
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 130. Typical and maximum current consumption batch acquisition mode,
LDO regulator ON
Max(1)
Symbol
Parameter
Supply
current in
batch
acquisition
mode
IDD
Conditions
D1
Standby,
D2
Standby,
D3 Run
VOS3
D1 Stop,
D2 Stop,
D3 Run
VOS3
fHCLK
(MHz)
Typ
64
2.7
4.7
8
1.1
-
Tj=105
°C
Tj=125
°C
12.9
19.0
27.5
-
-
-
Tj=25°C Tj=85°C
Unit
mA
64
5.4
18.4
83.7
132.6
202.4
8
3.8
-
-
-
-
1. Guaranteed by characterization results, unless otherwise specified.
Table 131. Typical and maximum current consumption in Stop, LDO regulator ON
Max(1)
Symbol
Parameter
D1 Stop,
D2 Stop,
D3 Stop
IDD (Stop)
D1 Stop,
D2 Standby,
D3 Stop
D1 Standby,
D2 Stop,
D3 Stop
D1 Standby,
D2 Standby,
D3 Stop
Conditions
Typ
Tj=25°C
Tj=85°C
Tj=105
°C
Tj=125
°C
Flash
memory
OFF, no
IWDG
SVOS5
1.27
6.3
42.5
72.0
-
SVOS4
1.96
9.4
57.4
94.6
-
SVOS3
2.78
13.8
75.9
121.3
183.8
Flash
memory
ON, no
IWDG
SVOS5
1.27
6.3
42.5
72.0
-
SVOS4
2.25
9.8
57.9
95.2
-
SVOS3
3.07
14.1
76.4
122.0
184.8
Flash
memory
OFF, no
IWDG
SVOS5
0.91
4.6
30.4
51.2
-
SVOS4
1.42
6.8
41.1
67.3
-
SVOS3
2.02
10.0
54.4
86.6
130.0
Flash
memory
ON, no
IWDG
SVOS5
0.91
4.6
30.4
51.2
-
SVOS4
1.70
7.2
41.5
67.9
-
SVOS3
2.31
10.3
54.9
87.1
130.8
SVOS5
0.49
2.4
16.5
28.0
-
SVOS4
0.76
3.6
22.2
36.6
-
SVOS3
1.10
5.3
29.3
46.9
71.2
SVOS5
0.15
0.7
4.3
7.3
-
SVOS4
0.22
1.0
5.8
9.6
-
SVOS3
0.35
1.5
7.8
12.3
18.6
Flash
memory
OFF, no
IWDG
1. Guaranteed by characterization results, unless otherwise specified.
212/336
DS12556 Rev 6
Unit
mA
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 132. Typical and maximum current consumption in Sleep mode, LDO regulator (1)
Max(2)
Symbol
Parameter
Conditions
fHCLK
(MHz)
Typ
480
VOS0
All
peripherals
disabled
VOS1
VOS2
IDD (Sleep)
Supply
current in
Sleep mode
VOS3
VOS0
All
peripherals
enabled
VOS1
VOS2
VOS3
Tj=25
°C
Tj=85
°C
Tj=105
°C
50.7
96.3
253.4
366.1
400
43.4
87.8
245.5
357.9
400
35.3
66.5
181.3
265.8
379.6
300
27.9
-
-
-
-
300
24.6
47.3
139.1
207.3
300.4
200
18.8
-
-
-
-
200
16.5
33.6
106.4
160.9
236.1
480
136.0
194.7
348.5
464.4
400
115.0
169.0
325.9
441.7
400
97.7
138.2
251.3
338.4
456.4
300
74.9
-
-
-
-
300
67.3
95.8
187.6
257.9
354.1
200
52.8
-
-
-
-
200
47.1
69.3
141.4
197.7
275.1
Unit
Tj=125
°C
mA
1. The parameters given in the above table for the SMPS regulator are derived by extrapolation from the LDO consumption
and typical SMPS efficiency factors
.
2. Guaranteed by characterization results, unless otherwise specified.
Table 133. Typical and maximum current consumption in Standby
Max(1)
Typ
Conditions
3V
Symbol
IDD
(Standby)
Parameter
Supply
current in
Standby
mode
Unit
Backup
SRAM
RTC
and
LSE
OFF
OFF
1,92
1,95
2,06
2,16
4
18
40
90
ON
OFF
3,33
3,44
3,6
3,79
8.2
47
83
141
OFF
ON
2,43
2,57
2,77
2,95
-
-
-
-
ON
ON
3,82
4,05
4,31
4,55
-
-
-
-
1.62 V 2.4 V
3V
3.3 V
Tj=25 Tj=85 Tj=105 Tj=125
°C
°C
°C
°C
µA
1. Guaranteed by characterization results, unless otherwise specified.
DS12556 Rev 6
213/336
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 134. Typical and maximum current consumption in VBAT mode
Conditions
Symbol
IDD
(VBAT)
Parameter
Supply
current in
VBAT mode
Max(1)
Typ
3V
Backup
SRAM
RTC
and
LSE
1.2 V
2V
3V
3.4 V
OFF
OFF
0,02
0,02
0,03
0,05
0,5
4,1
10
24
ON
OFF
1,33
1,45
1,58
1,7
4,4
22
48
87
OFF
ON
0,46
0,57
0,75
0,87
-
-
-
-
ON
ON
1,77
2
2,3
2,5
-
-
-
-
Unit
Tj=25 Tj=85 Tj=105
°C
°C
°C
Tj=125
°C
µA
1. Guaranteed by characterization results, unless otherwise specified.
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate a current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 155: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
An additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
214/336
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid a current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 135: Peripheral current
consumption in Run mode), the I/Os used by an application also contribute to the current
consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to
supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external)
connected to the pin:
I SW = V DDx × f SW × C L
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDx is the MCU supply voltage
fSW is the I/O switching frequency
CL is the total capacitance seen by the I/O pin: C = CINT+ CEXT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
On-chip peripheral current consumption
The MCU is placed under the following conditions:
•
At startup, all I/O pins are in analog input configuration.
•
All peripherals are disabled unless otherwise mentioned.
•
The I/O compensation cell is enabled.
•
frcc_c_ck is the CPU clock. fPCLK = frcc_c_ck/4, and fHCLK = frcc_c_ck/2.
The given value is calculated by measuring the difference of current consumption
•
–
with all peripherals clocked off
–
with only one peripheral clocked on
–
frcc_c_ck = 480 MHz (Scale 0), frcc_c_ck = 400 MHz (Scale 1), frcc_c_ck = 300 MHz
(Scale 2), frcc_c_ck = 200 MHz (Scale 3)
The ambient operating temperature is 25 °C and VDD=3.3 V.
DS12556 Rev 6
215/336
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 135. Peripheral current consumption in Run mode
Bus
AHB3
AHB1
216/336
Peripheral
VOS0
VOS1
VOS2
VOS3
MDMA
4.6
3.8
3.4
3.2
DMA2D
2.9
2.4
2.1
1.9
JPGDEC
4.1
3.7
3.4
3.1
FLASH
17.0
15.0
14.0
12.0
FMC registers
0.9
1.1
0.9
0.8
FMC kernel
7.0
6.1
5.6
5.0
QUADSPI registers
1.5
1.5
1.4
1.3
QSPI kernel
1.0
0.9
0.8
0.7
SDMMC1 registers
8.2
7.2
6.7
6.0
SDMMC1 kernel
1.3
1.2
0.9
0.9
DTCM1
7.9
6.8
6.0
5.3
DTCM2
8.3
7.2
6.4
5.7
ITCM
7.0
6.3
5.6
5.1
D1SRAM1
13.0
11.0
9.9
8.7
AHB3 bridge
35.0
32.0
29.0
26.0
Total AHB3
120
106
96
86
DMA1
54.0
48.0
41.0
37.0
DMA2
55.0
49.0
42.0
37.0
ADC12 registers
4.5
4.1
3.7
3.3
ADC12 kernel
1.0
0.7
0.4
0.6
ART accelerator
4.1
3.7
3.2
2.9
ETH1MAC
17.0
15.0
14.0
12.0
ETH1TX
0.1
0.1
0.1
0.1
ETH1RX
0.1
0.1
0.1
0.1
USB1 OTG registers
23.0
21.0
19.0
17.0
USB1 OTG kernel
8.2
0.5
8.3
8.2
USB1 ULPI
0.1
0.1
0.1
0.1
USB2 OTG registers
21.0
19.0
17.0
15.0
USB2 OTG kernel
8.5
0.4
8.6
8.3
USB2 ULPI
23.0
19.0
20.0
19.0
AHB1 bridge
0.1
0.1
0.1
0.1
Total AHB1
220
181
178
161
DS12556 Rev 6
Unit
µA/MHz
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 135. Peripheral current consumption in Run mode (continued)
Bus
AHB2
AHB4
APB3
Peripheral
VOS0
VOS1
VOS2
VOS3
DCMI
2.1
1.9
1.8
1.6
CRYPT
0.1
0.1
0.1
0.1
HASH
0.1
0.1
0.1
0.1
RNG registers
1.7
2.0
1.3
1.2
RNG kernel
11.0
0.1
9.7
9.4
SDMMC2 registers
47.0
41.0
37.0
34.0
SDMMC2 kernel
1.7
1.2
1.1
1.0
D2SRAM1
5.7
4.9
4.4
3.9
D2SRAM2
5.2
4.5
4.0
3.5
D2SRAM3
4.1
3.6
3.2
2.8
AHB2 bridge
0.1
0.1
0.1
0.1
Total AHB2
79
60
63
58
GPIOA
1.5
1.3
1.3
1.1
GPIOB
1.2
1.0
1.0
0.9
GPIOC
0.8
0.7
0.7
0.6
GPIOD
1.1
1.0
1.0
0.9
GPIOE
0.7
0.7
0.7
0.6
GPIOF
0.8
0.8
0.7
0.6
GPIOG
0.9
0.8
0.8
0.7
GPIOH
1.1
1.0
1.0
0.9
GPIOI
0.9
0.9
0.8
0.7
GPIOJ
0.8
0.8
0.7
0.7
GPIOK
0.7
0.8
0.7
0.6
CRC
0.4
0.5
0.4
0.3
BDMA
6.6
5.9
5.3
4.8
ADC3 registers
1.7
1.5
1.2
1.2
ADC3 kernel
0.4
0.3
0.5
0.2
BKPRAM
2.3
1.9
1.7
1.5
AHB4 bridge
0.1
0.1
0.1
0.1
Total AHB4
22
20
19
16
WWDG1
0.7
0.5
0.5
0.2
LCD-TFT
81.0
36.0
33.0
30.0
APB3 bridge
0.3
0.2
0.1
0.1
Total APB3
87
41
38
34
DS12556 Rev 6
Unit
µA/MHz
µA/MHz
217/336
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 135. Peripheral current consumption in Run mode (continued)
Bus
APB1
218/336
Peripheral
VOS0
VOS1
VOS2
VOS3
TIM2
7.7
3.6
3.3
3.0
TIM3
6.7
3.2
3.0
2.7
TIM4
6.3
3.1
2.8
2.5
TIM5
7.4
3.5
3.2
2.8
TIM6
1.4
0.7
0.8
0.6
TIM7
1.4
0.7
0.7
0.6
TIM12
3.2
1.5
1.5
1.3
TIM13
2.3
1.1
1.1
0.9
TIM14
2.1
1.1
1.1
0.9
LPTIM1 registers
0.7
0.5
0.8
0.7
LPTIM1 kernel
2.4
2.3
1.9
1.7
WWDG2
0.6
0.5
0.5
0.4
SPI2 registers
2.0
1.8
1.7
1.4
SPI2 kernel
0.8
0.6
0.5
0.6
SPI3 registers
1.8
1.6
1.6
1.3
SPI3 kernel
0.7
0.9
0.7
0.7
SPDIFRX1 registers
0.5
0.7
0.7
0.6
SPDIFRX1 kernel
3.5
2.8
2.4
2.2
USART2 registers
1.9
1.7
1.4
1.3
USART2 kernel
4.3
3.9
3.6
3.2
USART3 registers
1.9
1.7
1.4
1.3
USART3 kernel
4.4
3.9
3.5
3.2
UART4 registers
1.7
1.5
1.4
1.4
UART4 kernel
3.9
3.4
3.1
2.8
UART5 registers
1.6
1.4
1.4
1.3
UART5 kernel
3.8
3.4
3.0
2.7
I2C1 registers
1.1
0.8
0.9
0.8
I2C1 kernel
2.5
2.3
2.0
1.9
I2C2 registers
1.0
0.8
0.9
0.8
DS12556 Rev 6
Unit
µA/MHz
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 135. Peripheral current consumption in Run mode (continued)
Bus
APB1
(continued)
APB2
Peripheral
VOS0
VOS1
VOS2
VOS3
I2C2 kernel
2.3
2.2
1.9
1.7
I2C3 registers
0.8
1.0
0.8
0.8
I2C3 kernel
2.4
1.9
1.8
1.6
HDMI-CEC registers
0.7
0.5
0.6
0.5
HDMI-CEC kernel
0.1
0.1
3.2
0.1
DAC12
3.6
1.3
1.2
1.0
USART7 registers
1.8
1.8
1.6
1.4
USART7 kernel
4.0
3.3
3.0
2.8
USART8 registers
2.0
1.6
1.6
1.4
USART8 kernel
3.9
3.4
3.1
2.8
CRS
6.4
5.5
5.0
4.5
SWPMI registers
2.7
2.4
2.3
1.9
SWPMI kernel
0.1
0.1
0.1
0.1
OPAMP
0.2
0.3
0.3
0.2
MDIO
3.3
2.9
2.6
2.3
FDCAN registers
19.0
17.0
15.0
13.0
FDCAN kernel
9.1
7.9
6.9
6.4
APB1 bridge
0.1
0.1
0.1
0.1
Total APB1
142
108
102
88
TIM1
11.0
5.0
4.5
4.0
TIM8
10.0
4.7
4.3
3.8
USART1 registers
3.6
2.5
2.7
2.9
USART1 kernel
0.1
0.1
0.1
0.1
USART6 registers
4.5
3.0
3.1
3.4
USART6 kernel
0.1
0.1
0.1
0.1
SPI1 registers
2.0
1.7
1.6
1.4
SPI1 kernel
0.9
0.8
0.7
0.6
SPI4 registers
2.1
1.7
1.6
1.5
SPI4 kernel
0.6
0.5
0.5
0.3
TIM15
5.5
2.5
2.3
2.1
TIM16
4.1
2.0
1.8
1.7
TIM17
4.1
1.9
1.8
1.6
SPI5 registers
2.0
1.8
1.6
1.3
SPI5 kernel
0.5
0.4
0.4
0.5
SAI1 registers
1.3
1.1
1.1
1.0
DS12556 Rev 6
Unit
µA/MHz
219/336
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 135. Peripheral current consumption in Run mode (continued)
Bus
APB2
(continued)
APB4
220/336
Peripheral
VOS0
VOS1
VOS2
VOS3
SAI1 kernel
1.4
1.1
1.0
0.8
SAI2 registers
1.5
1.3
1.2
1.0
SAI2 kernel
1.1
1.0
0.9
0.9
SAI3 registers
1.6
1.3
1.1
1.0
SAI3 kernel
1.1
1.2
1.1
0.9
DFSDM1 registers
6.5
5.8
5.2
4.7
DFSDM1 kernel
0.3
0.2
0.2
0.4
HRTIM
84.0
39.0
35.0
32.0
APB2 bridge
0.2
0.1
0.1
0.2
Total APB2
150
81
74
68
SYSCFG
0.9
1.0
0.7
0.8
LPUART1 registers
1.1
1.3
1.0
0.8
LPUART1 kernel
2.9
2.2
2.2
2.1
SPI6 registers
1.8
1.6
1.4
1.3
SPI6 kernel
0.4
0.4
0.5
0.3
I2C4 registers
0.9
0.7
0.7
0.4
I2C4 kernel
2.2
2.1
1.9
1.8
LPTIM2 registers
0.8
0.6
0.7
0.5
LPTIM2 kernel
2.3
2.1
1.8
1.4
LPTIM3 registers
0.7
0.7
0.7
0.4
LPTIM3 kernel
2.1
1.7
1.6
1.5
LPTIM4 registers
0.8
0.4
0.6
0.4
LPTIM4 kernel
2.2
2.0
1.7
1.5
LPTIM5 registers
0.5
0.4
0.6
0.4
LPTIM5 kernel
2.0
1.8
1.5
1.2
COMP12
0.6
0.4
0.5
0.2
VREF
0.4
0.2
0.2
0.1
RTC
1.1
0.9
1.0
0.6
SAI4 registers
1.7
1.4
1.3
1.0
SAI4 kernel
2.0
2.0
1.8
1.6
APB4 bridge
0.1
0.1
0.1
0.1
Total APB4
28
24.4
22.4
18.9
DS12556 Rev 6
Unit
µA/MHz
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
7.3.7
Electrical characteristics (rev V)
Wakeup time from low-power modes
The wakeup times given in Table 136 are measured starting from the wakeup event trigger
up to the first instruction executed by the CPU:
•
For Stop or Sleep modes: the wakeup event is WFE.
•
WKUP (PC1) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and VDD=3.3 V.
Table 136. Low-power mode wakeup timings
Symbol
Parameter
Conditions
Typ(1)
Max(1)
Unit
tWUSLEEP(2)
Wakeup from Sleep
-
9
10
CPU
clock
cycles
VOS3, HSI, Flash memory in normal mode
4.4
5.6
VOS3, HSI, Flash memory in low-power
mode
12
15
VOS4, HSI, Flash memory in normal mode
15
20
VOS4, HSI, Flash memory in low-power
mode
23
28
VOS5, HSI, Flash memory in normal mode
39
71
VOS5, HSI, Flash memory in low-power
mode
39
47
VOS3, CSI, Flash memory in normal mode
30
37
VOS3, CSI, Flash memory in low power
mode
36
50
VOS4, CSI, Flash memory in normal mode
38
48
VOS4, CSI, Flash memory in low-power
mode
47
61
VOS5, CSI, Flash memory in normal mode
68
75
VOS5, CSI, Flash memory in low-power
mode
68
77
VOS3, HSI, Flash memory in normal mode
2.6
3.4
VOS3, CSI, Flash memory in normal mode
26
36
-
390
500
tWUSTOP
(2)
tWUSTOP_
KERON
(2)
tWUSTDBY(2)
Wakeup from Stop
Wakeup from Stop,
clock kept running
Wakeup from Standby
mode
µs
1. Guaranteed by characterization results.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction.
DS12556 Rev 6
221/336
311
Electrical characteristics (rev V)
7.3.8
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O.
The external clock signal has to respect the Table 155: I/O static characteristics. However,
the recommended clock input waveform is shown in Figure 67.
Table 137. High-speed external user clock characteristics(1)
Symbol
Parameter
Min
Typ
Max
Unit
fHSE_ext
User external clock source frequency
4
25
50
MHz
0.7VDD
-
VDD
VSS
-
0.3VSS
7
-
-
VSW
OSC_IN amplitude
(VHSEH − VHSEL)
VDC
OSC_IN input voltage
tW(HSE)
OSC_IN high or low time
V
ns
1. Guaranteed by design.
Figure 67. High-speed external clock source AC timing diagram
VHSEH
90 %
10 %
VHSEL
tr(HSE)
tf(HSE)
tW(HSE) t
tW(HSE)
THSE
External
clock source
fHSE_ext
OSC_IN
IL
STM32
ai17528b
222/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 155: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 68.
Table 138. Low-speed external user clock characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
kHz
fLSE_ext
User external clock source frequency
-
-
32.768
1000
VLSEH
OSC32_IN input pin high level voltage
-
0.7 VDDIOx
-
VDDIOx
VLSEL
OSC32_IN input pin low level voltage
-
VSS
-
0.3 VDDIOx
-
250
-
-
tw(LSEH)
OSC32_IN high or low time
tw(LSEL)
V
ns
1. Guaranteed by design.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 68. Low-speed external clock source AC timing diagram
VLSEH
90%
VLSEL
10%
tr(LSE)
tf(LSE)
tW(LSE)
OSC32_IN
IL
tW(LSE) t
TLSE
External
clock source
fLSE_ext
STM32
ai17529b
DS12556 Rev 6
223/336
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 139. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 139. 4-48 MHz HSE oscillator characteristics(1)
Symbol
Parameter
Operating
conditions(2)
Min
Typ
Max
Unit
F
Oscillator frequency
-
4
-
48
MHz
RF
Feedback resistor
-
-
200
-
kΩ
During startup(3)
-
-
4
VDD=3 V, Rm=30 Ω
CL=10pF@4MHz
-
0.35
-
VDD=3 V, Rm=30 Ω
CL=10 pF at 8 MHz
-
0.40
-
VDD=3 V, Rm=30 Ω
CL=10 pF at 16 MHz
-
0.45
-
VDD=3 V, Rm=30 Ω
CL=10 pF at 32 MHz
-
0.65
-
VDD=3 V, Rm=30 Ω
CL=10 pF at 48 MHz
-
0.95
-
IDD(HSE)
HSE current consumption
mA
Gmcritmax
Maximum critical crystal gm
Startup
-
-
1.5
mA/V
tSU(4)
Start-up time
VDD is stabilized
-
2
-
ms
1. Guaranteed by design.
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typical), designed for high-frequency applications, and selected to
match the requirements of the crystal or resonator (see Figure 69). CL1 and CL2 are usually
the same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. The PCB and MCU pin capacitance must be included
(10 pF can be used as a rough estimate of the combined pin and board capacitance) when
sizing CL1 and CL2.
Note:
224/336
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Figure 69. Typical application with an 8 MHz crystal
Resonator with
integrated capacitors
CL1
8 MHz
resonator
CL2
fHSE
OSC_IN
REXT(1)
RF
Bias
controlled
gain
OSC_OU T
STM32
ai17530b
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 140. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 140. Low-speed external user clock characteristics(1)
Symbol
Parameter
Operating conditions(2)
Min
Typ
Max
Unit
F
Oscillator frequency
-
-
32.768
-
kHz
LSEDRV[1:0] = 00,
Low drive capability
-
290
-
LSEDRV[1:0] = 01,
Medium Low drive capability
-
390
-
LSEDRV[1:0] = 10,
Medium high drive capability
-
550
-
LSEDRV[1:0] = 11,
High drive capability
-
900
-
LSEDRV[1:0] = 00,
Low drive capability
-
-
0.5
LSEDRV[1:0] = 01,
Medium Low drive capability
-
-
0.75
LSEDRV[1:0] = 10,
Medium high drive capability
-
-
1.7
LSEDRV[1:0] = 11,
High drive capability
-
-
2.7
VDD is stabilized
-
2
-
IDD
Gmcritmax
tSU(3)
LSE current
consumption
Maximum critical crystal
gm
Startup time
nA
µA/V
s
1. Guaranteed by design.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers.
3. tSU is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768k Hz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
DS12556 Rev 6
225/336
311
Electrical characteristics (rev V)
Note:
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 70. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors
CL1
fHSE
OSC32_IN
32.768 kHz
resonator
RF
Bias
controlled
gain
OSC32_OUT
STM32
CL2
ai17531c
1. An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.
7.3.9
Internal clock source characteristics
The parameters given in Table 141 to Table 144 are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 120: General
operating conditions.
48 MHz high-speed internal RC oscillator (HSI48)
Table 141. HSI48 oscillator characteristics
Symbol
fHSI48
TRIM(2)
Parameter
Conditions
Min
Typ
Max
Unit
VDD=3.3 V,
TJ=30 °C
47.5(1)
48
48.5(1)
MHz
-
-
0.175
-
%
± 32 steps
±4.79
±5.60
-
%
-
45
-
55
%
TJ=-40 to 125 °C
–4.5
-
3.5
%
VDD=3 to 3.6 V
-
0.025
0.05
VDD=1.62 V to 3.6 V
-
0.05
0.1
HSI48 frequency
USER trimming step
USER TRIM
COVERAGE(3)
USER TRIMMING Coverage
DuCy(HSI48)(2)
Duty Cycle
ACCHSI48_REL(3)(4)
Accuracy of the HSI48 oscillator over
temperature (factory calibrated)
∆VDD(HSI48)(3)
HSI48 oscillator frequency drift with
VDD(5)
tsu(HSI48)(2)
HSI48 oscillator start-up time
-
-
2.1
4.0
µs
IDD(HSI48)(2)
HSI48 oscillator power consumption
-
-
350
400
µA
NT jitter
Next transition jitter
Accumulated jitter on 28 cycles(6)
-
-
± 0.15
-
ns
PT jitter
Paired transition jitter
Accumulated jitter on 56 cycles(6)
-
-
± 0.25
-
ns
1. Guaranteed by test in production.
2. Guaranteed by design.
3. Guaranteed by characterization.
4.
%
∆fHSI = ACCHSI48_REL + ∆VDD.
226/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
5. These values are obtained by using the formula: (Freq(3.6V) - Freq(3.0V)) / Freq(3.0V) or (Freq(3.6V) - Freq(1.62V)) /
Freq(1.62V).
6. Jitter measurements are performed without clock source activated in parallel.
64 MHz high-speed internal RC oscillator (HSI)
Table 142. HSI oscillator characteristics(1)
Symbol
Parameter
HSI frequency
fHSI
TRIM
HSI user trimming step
DuCy(HSI)
Duty Cycle
ΔVDD (HSI)
HSI oscillator frequency drift over
VDD (reference is 3.3 V)
ΔTEMP (HSI)
HSI oscillator frequency drift over
temperature (reference is 64 MHz)
tsu(HSI)
HSI oscillator start-up time
tstab(HSI)
HSI oscillator stabilization time
IDD(HSI)
HSI oscillator power consumption
Conditions
Min
Typ
Max
Unit
VDD=3.3 V, TJ=30 °C
63.7(2)
64
64.3(2)
MHz
Trimming is not a multiple
of 32
-
0.24
0.32
Trimming is 128, 256 and
384
−5.2
−1.8
-
Trimming is 64, 192, 320
and 448
−1.4
−0.8
-
Other trimming are a
multiple of 32 (not
including multiple of 64
and 128)
−0.6
−0.25
-
-
45
-
55
%
VDD=1.62 to 3.6 V
−0.12
-
0.03
%
TJ=-20 to 105 °C
−1(3)
-
1(3)
TJ=−40 to TJmax °C
−2(3)
-
1(3)
-
-
1.4
2
µs
at 1% of target frequency
-
4
8
µs
-
-
300
400
µA
%
%
1. Guaranteed by design unless otherwise specified.
2. Guaranteed by test in production.
3. Guaranteed by characterization.
4 MHz low-power internal RC oscillator (CSI)
Table 143. CSI oscillator characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fCSI
CSI frequency
VDD=3.3 V, TJ=30 °C
3.96(2)
4
4.04(2)
MHz
TRIM
Trimming step
-
-
0.35
-
%
Duty Cycle
-
45
-
55
%
TJ = 0 to 85 °C
-
−3.7(3)
4.5(3)
TJ = −40 to 125 °C
-
−11(3)
7.5(3)
VDD = 1.62 to 3.6 V
-
−0.06
0.06
DuCy(CSI)
∆TEMP (CSI)
CSI oscillator frequency drift over
temperature
DVDD (CSI)
CSI oscillator frequency drift over
VDD
DS12556 Rev 6
%
%
227/336
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 143. CSI oscillator characteristics(1) (continued)
Symbol
Conditions
Min
Typ
Max
Unit
CSI oscillator startup time
-
-
1
2
µs
tstab(CSI)
CSI oscillator stabilization time
(to reach ±3% of fCSI)
-
-
-
4
cycle
IDD(CSI)
CSI oscillator power consumption
-
-
23
30
µA
Typ
Max
Unit
32
32.6(1)
TJ = –40 to 110 °C, VDD = 1.62 to
29.76(2)
3.6 V
-
33.6(2)
TJ = –40 to 125 °C, VDD = 1.62 to
3.6 V
29.4
-
33.6
-
-
80
130
tsu(CSI)
Parameter
1. Guaranteed by design.
2. Guaranteed by test in production.
3. Guaranteed by characterization.
Low-speed internal (LSI) RC oscillator
Table 144. LSI oscillator characteristics
Symbol
Parameter
Conditions
VDD = 3.3 V, TJ = 25 °C
31.4(1)
fLSI
LSI frequency
tsu(LSI)(3)
LSI oscillator
startup time
tstab(LSI)(3)
LSI oscillator
stabilization
time (5% of
final value)
-
-
120
170
IDD(LSI)(3)
LSI oscillator
power
consumption
-
-
130
280
kHz
µs
1. Guaranteed by test in production.
2. Guaranteed by characterization results.
3. Guaranteed by design.
228/336
Min
DS12556 Rev 6
nA
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
7.3.10
Electrical characteristics (rev V)
PLL characteristics
The parameters given in Table 145 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 120: General operating conditions.
Table 145. PLL characteristics (wide VCO frequency range)(1)
Symbol
fPLL_IN
fPLL_P_OUT
fVCO_OUT
tLOCK
Parameter
Conditions
Min
Typ
Max
Unit
PLL input clock
-
2
-
16
MHz
PLL input clock duty cycle
-
10
-
90
%
PLL multiplier output clock P
Cycle-to-cycle jitter(4)
1.5
-
480
VOS1
1.5
-
400(2)
VOS2
1.5
-
300(2)
VOS3
1.5
-
200(2)
-
192
-
960
Long term jitter
150(3)
-
50
Sigma-delta mode
(CKIN ≥ 8 MHz)
-
58(3)
166(3)
VCO =
192 MHz
-
134
-
VCO =
200 MHz
-
134
-
VCO =
400 MHz
-
76
-
VCO =
800 MHz
-
39
-
VCO =
800 MHz
-
±0.7
-
Sigma-delta
VCO =
mode (CKIN =
800 MHz
16 MHz)
-
±0.8
-
VDDA
-
590
1500
VCORE
-
720
-
VDDA
-
180
600
VCORE
-
280
-
-
VCO freq =
836 MHz
PLL power consumption on VDD
(3)
Normal mode
Normal mode
Jitter
IDD(PLL)(3)
VOS0
PLL VCO output
PLL lock time
(2)
VCO freq =
192 MHz
MHz
µs
±ps
%
µA
1. Guaranteed by design unless otherwise specified.
2. This value must be limited to the maximum frequency due to the product limitation (480 MHz for VOS0, 400 MHz for VOS1,
300 MHz for VOS2, 200 MHz for VOS3).
3. Guaranteed by characterization results.
4. Integer mode only.
DS12556 Rev 6
229/336
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 146. PLL characteristics (medium VCO frequency range)(1)
Symbol
fPLL_IN
fPLL_OUT
fVCO_OUT
tLOCK
Parameter
Conditions
Min
Typ
Max
Unit
PLL input clock
-
1
-
2
MHz
PLL input clock duty cycle
-
10
-
90
%
VOS1
1.17
-
210
VOS2
1.17
-
210
VOS3
1.17
-
200
-
150
-
420
-
60(2)
100(2)
PLL multiplier output clock P, Q,
R
PLL VCO output
Normal mode
PLL lock time
Cycle-to-cycle
Sigma-delta mode
jitter(3)
-
Jitter
Period jitter
Long term jitter
I(PLL)(2)
fPLL_OUT =
50 MHz
Normal mode
VCO freq =
420MHz
PLL power consumption on VDD
VCO freq =
150MHz
1. Guaranteed by design unless otherwise specified.
2. Guaranteed by characterization results.
3. Integer mode only.
230/336
DS12556 Rev 6
forbidden
VCO =
150 MHz
-
145
-
VCO =
300 MHz
-
91
-
VCO =
400 MHz
-
64
-
VCO =
420 MHz
-
63
-
VCO =
150 MHz
-
55
-
VCO =
400 MHz
-
30
-
VCO =
400 MHz
-
±0.3
-
VDD
-
440
1150
VCORE
-
530
-
VDD
-
180
500
VCORE
-
200
-
MHz
µs
±ps
±-ps
%
µA
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
7.3.11
Electrical characteristics (rev V)
Memory characteristics
Flash memory
The characteristics are given at TJ = –40 to 125 °C unless otherwise specified.
The devices are shipped to customers with the Flash memory erased.
Table 147. Flash memory characteristics
Symbol
IDD
Parameter
Supply current
Conditions
Min
Typ
Max
Write / Erase 8-bit mode
-
6.5
-
Write / Erase 16-bit mode
-
11.5
-
Write / Erase 32-bit mode
-
20
-
Write / Erase 64-bit mode
-
35
-
Min(1)
Typ
Max(1)
Unit
mA
Table 148. Flash memory programming
Symbol
tprog
tERASE128KB
tME
Parameter
Word (266 bits) programming
time
Sector (128 KB) erase time
Mass erase time
Conditions
Program/erase parallelism x 8
-
290
580(2)
Program/erase parallelism x 16
-
180
360
Program/erase parallelism x 32
-
130
260
Program/erase parallelism x 64
-
100
200
Program/erase parallelism x 8
-
2
4
Program/erase parallelism x 16
-
1.8
3.6
Program/erase parallelism x 32
-
1.1
2.2
Program/erase parallelism x 8
-
13
26
Program/erase parallelism x 16
-
8
16
Program/erase parallelism x 32
-
6
12
Program/erase parallelism x 64
-
5
10
1.62
-
3.6
1.8
-
3.6
Unit
µs
s
Program parallelism x 8
Vprog
Programming voltage
Program parallelism x 16
Program parallelism x 32
Program parallelism x 64
V
1. Guaranteed by characterization results.
2. The maximum programming time is measured after 10K erase operations.
DS12556 Rev 6
231/336
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 149. Flash memory endurance and data retention
Value
Symbol
NEND
tRET
Parameter
Conditions
Unit
Min(1)
Endurance
TJ = –40 to +125 °C (6 suffix versions)
10
Data retention
1 kcycle at TA = 85 °C
30
10 kcycles at TA = 55 °C
20
kcycles
Years
1. Guaranteed by characterization results.
7.3.12
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 150. They are based on the EMS levels and classes
defined in application note AN1709.
Table 150. EMS characteristics
Symbol
VFESD
VFTB
Parameter
Conditions
Voltage limits to be applied on any I/O pin to induce
VDD = 3.3 V, TA = +25 °C,
a functional disturbance
UFBGA240, frcc_c_ck =
Fast transient voltage burst limits to be applied
400 MHz, conforms to
through 100 pF on VDD and VSS pins to induce a
IEC 61000-4-2
functional disturbance
Level/
Class
3B
5A
As a consequence, it is recommended to add a serial resistor (1 kΏ) located as close as
possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm
on PCB).
232/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
Corrupted program counter
•
Unexpected reset
•
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.
Table 151. EMI characteristics
Symbol Parameter
Conditions
Monitored
frequency band
Max vs.
[fHSE/fCPU]
Unit
8/400 MHz
SEMI
VDD = 3.6 V, TA = 25 °C, UFBGA240 package,
Peak level
conforming to IEC61967-2
DS12556 Rev 6
0.1 to 30 MHz
11
30 to 130 MHz
6
130 MHz to 1 GHz
12
1 GHz to 2 GHz
7
EMI Level
2.5
dBµV
-
233/336
311
Electrical characteristics (rev V)
7.3.13
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each
sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC
JS-001 and ANSI/ESDA/JEDEC JS-002 standards.
Table 152. ESD absolute maximum ratings
Conditions
Packages
Class
Maximum
value(1)
Electrostatic discharge
VESD(HBM) voltage (human body
model)
TA = +25 °C conforming to
ANSI/ESDA/JEDEC JS001
All
1C
1000
Electrostatic discharge
VESD(CDM) voltage (charge device
model)
TA = +25 °C conforming to
ANSI/ESDA/JEDEC JS002
All
Symbol
Ratings
V
C1
250
1. Guaranteed by characterization results.
Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
•
A supply overvoltage is applied to each power supply pin
•
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with JESD78 IC latchup standard.
Table 153. Electrical sensitivities
Symbol
LU
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Parameter
Static latchup class
Conditions
TA = +25 °C conforming to JESD78
DS12556 Rev 6
Unit
Class
II level A
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
7.3.14
Electrical characteristics (rev V)
I/O current injection characteristics
As a general rule, a current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3.3 V-capable I/O pins) should be avoided during the normal
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when an abnormal injection accidentally happens, susceptibility
tests are performed on a sample basis during the device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency
deviation).
The following tables are the compilation of the SIC1/SIC2 and functional ESD results.
Negative induced A negative induced leakage current is caused by negative injection and
positive induced leakage current by positive injection.
Table 154. I/O current injection susceptibility(1)
Functional susceptibility
Symbol
IINJ
Description
Negative
injection
Positive
injection
PA7, PC5, PG1, PB14, PJ7, PA11, PA12, PA13, PA14, PA15,
PJ12, PB4
5
0
PA2, PH2, PH3, PE8, PA6, PA7, PC4, PE7, PE10, PE11
0
NA
PA0, PA_C, PA1, PA1_C, PC2, PC2_C, PC3, PC3_C, PA4,
PA5, PH4, PH5, BOOT0
0
0
All other I/Os
5
NA
Unit
mA
1. Guaranteed by characterization.
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Electrical characteristics (rev V)
7.3.15
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 155: I/O static characteristics are
derived from tests performed under the conditions summarized in Table 120: General
operating conditions. All I/Os are CMOS and TTL compliant (except for BOOT0).
For information on GPIO configuration, refer to the application note AN4899 “STM32 GPIO
configuration for hardware settings and low-power consumption” available from the ST
website www.st.com.
Table 155. I/O static characteristics
Symbol
Parameter
Condition
Min
Typ
Max
-
-
0.3VDD(1)
-
-
0.4VDD−0.
1(2)
BOOT0 I/O input low level voltage
-
-
0.19VDD+
0.1(2)
I/O input high level voltage except
BOOT0
0.7VDD(1)
-
-
0.47VDD+0.
25(2)
-
-
0.17VDD+0.
6(2)
-
-
-
250
-
-
200
-
-
-
+/-250
Max(VDDXXX) < VIN ≤ 5.5 V
(5)(6)(9)
-
-
1500
0< VIN ≤ Max(VDDXXX)(9)
-
-
+/- 350
Max(VDDXXX) < VIN ≤ 5.5 V
(5)(6)(9)
-
-
5000(7)
0< VIN ≤ Max(VDDXXX) (9)
-
-
+/-250
0< VIN ≤ VDDIOX
-
-
15
I/O input low level voltage except
BOOT0
VIL
VIH
I/O input low level voltage except
BOOT0
I/O input high level voltage except
BOOT0(3)
1.62 V<VDDIOx<3.6 V
1.62 V<VDDIOx<3.6 V
BOOT0 I/O input high level
voltage(3)
VHYS(2)
TT_xx, FT_xxx and NRST I/O
input hysteresis
1.62 V< VDDIOx <3.6 V
BOOT0 I/O input hysteresis
0< VIN ≤
FT_xx Input leakage
Ileak(4)
current(2)
FT_u IO
TT_xx Input leakage current
VPP (BOOT0 alternate function)
RPU
Weak pull-up equivalent
resistor(8)
RPD
Weak pull-down equivalent
resistor(8)
CIO
I/O pin capacitance
Max(VDDXXX)(9)
VDDIOX < VIN ≤ 9 V
VIN=VSS
V
V
mV
nA
35
30
40
50
kΩ
VIN=VDD
(9)
-
1. Compliant with CMOS requirements.
2. Guaranteed by design.
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Unit
DS12556 Rev 6
30
40
50
-
5
-
pF
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
3. VDDIOx represents VDDIO1, VDDIO2 or VDDIO3. VDDIOx= VDD.
4. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following
formula: ITotal_Ileak_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max).
5. All FT_xx IO except FT_lu, FT_u and PC3.
6. VIN must be less than Max(VDDXXX) + 3.6 V.
7. To sustain a voltage higher than MIN(VDD, VDDA, VDD33USB) +0.3 V, the internal pull-up and pull-down resistors must be
disabled.
8. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
9. Max(VDDXXX) is the maximum value of all the I/O supplies.
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 71.
Figure 71. VIL/VIH for all I/Os except BOOT0
3
2.5
2
S req
Voltage
CMO
TLL requirement: VIHmin = 2 V
0.7V D
in=
t: V IHm
en
uirem
D
+0.25
=0.47VDD
on VIHmin
ulati
d on sim
1.5
Base
-0.1
=0.4VDD
tion VILmax
la
u
im
on s
=0.3VDD
Based
max
ment: VIL
require
CMOS
TLL requirement: VILmin = 0.8 V
1
0.5
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
MSv46121V3
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 7.2. In particular:
•
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 118).
•
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
ΣIVSS (see Table 118).
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Output voltage levels
Unless otherwise specified, the parameters given in Table 156: Output voltage
characteristics for all I/Os except PC13, PC14, PC15 and PI8 and Table 157: Output voltage
characteristics for PC13, PC14, PC15 and PI8 are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 120: General
operating conditions. All I/Os are CMOS and TTL compliant.
Table 156. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8(1)
Symbol
Parameter
Conditions(3)
Min
Max
Output low level voltage
CMOS
IIO=8 mA
2.7 V≤ VDD ≤3.6 V
-
0.4
Output high level voltage
CMOS port(2)
IIO=-8 mA
2.7 V≤ VDD ≤3.6 V
VDD−0.4
-
Output low level voltage
TTL port(2)
IIO=8 mA
2.7 V≤ VDD ≤3.6 V
-
0.4
Output high level voltage
TTL port(2)
IIO=-8 mA
2.7 V≤ VDD ≤3.6 V
2.4
-
VOL(3)
Output low level voltage
IIO=20 mA
2.7 V≤ VDD ≤3.6 V
-
1.3
VOH(3)
Output high level voltage
IIO=-20 mA
2.7 V≤ VDD ≤3.6 V
VDD−1.3
-
VOL(3)
Output low level voltage
IIO=4 mA
1.62 V≤ VDD ≤3.6 V
-
0.4
VOH (3)
Output high level voltage
IIO=-4 mA
1.62 V≤VDD<3.6 V
VDD−-0.4
-
IIO= 20 mA
2.3 V≤ VDD≤3.6 V
-
0.4
IIO= 10 mA
1.62 V≤ VDD ≤3.6 V
-
0.4
Unit
port(2)
VOL
VOH
VOL(3)
VOH
(3)
VOLFM+(3)
Output low level voltage for an FTf
I/O pin in FM+ mode
V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 117:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 157. Output voltage characteristics for PC13, PC14, PC15 and PI8(1)
Conditions(3)
Min
Max
Output low level voltage
CMOS port(2)
IIO=3 mA
2.7 V≤ VDD ≤3.6 V
-
0.4
Output high level voltage
CMOS port(2)
IIO=-3 mA
2.7 V≤ VDD ≤3.6 V
VDD−0.4
-
Output low level voltage
TTL port(2)
IIO=3 mA
2.7 V≤ VDD ≤3.6 V
-
0.4
Output high level voltage
TTL port(2)
IIO=-3 mA
2.7 V≤ VDD ≤3.6 V
2.4
-
VOL(2)
Output low level voltage
IIO=1.5 mA
1.62 V≤ VDD ≤3.6 V
-
0.4
VOH(2)
Output high level voltage
IIO=-1.5 mA
1.62 V≤ VDD ≤3.6 V
VDD−0.4
-
Symbol
VOL
VOH
VOL(3)
VOH
(2)
Parameter
Unit
V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 117:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Output buffer timing characteristics (HSLV option disabled)
The HSLV bit of SYSCFG_CCCSR register can be used to optimize the I/O speed when the
product voltage is below 2.7 V.
Table 158. Output timing characteristics (HSLV OFF)(1)(2)
Speed
Symbol
Fmax(3)
Parameter
Maximum frequency
00
tr/tf(4)
Fmax(3)
Output high to low level
fall time and output low
to high level rise time
Maximum frequency
01
tr/tf(4)
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Output high to low level
fall time and output low
to high level rise time
conditions
Min
Max
C=50 pF, 2.7 V≤ VDD≤3.6 V
-
12
C=50 pF, 1.62 V≤VDD≤2.7 V
-
3
C=30 pF, 2.7 V≤VDD≤3.6 V
-
12
C=30 pF, 1.62 V≤VDD≤2.7 V
-
3
C=10 pF, 2.7 V≤VDD≤3.6 V
-
16
C=10 pF, 1.62 V≤VDD≤2.7 V
-
4
C=50 pF, 2.7 V≤ VDD≤3.6 V
-
16.6
C=50 pF, 1.62 V≤VDD≤2.7 V
-
33.3
C=30 pF, 2.7 V≤VDD≤3.6 V
-
13.3
C=30 pF, 1.62 V≤VDD≤2.7 V
-
25
C=10 pF, 2.7 V≤VDD≤3.6 V
-
10
C=10 pF, 1.62 V≤VDD≤2.7 V
-
20
C=50 pF, 2.7 V≤ VDD≤3.6 V
-
60
C=50 pF, 1.62 V≤VDD≤2.7 V
-
15
C=30 pF, 2.7 V≤VDD≤3.6 V
-
80
C=30 pF, 1.62 V≤VDD≤2.7 V
-
15
C=10 pF, 2.7 V≤VDD≤3.6 V
-
110
C=10 pF, 1.62 V≤VDD≤2.7 V
-
20
C=50 pF, 2.7 V≤ VDD≤3.6 V
-
5.2
C=50 pF, 1.62 V≤VDD≤2.7 V
-
10
C=30 pF, 2.7 V≤VDD≤3.6 V
-
4.2
C=30 pF, 1.62 V≤VDD≤2.7 V
-
7.5
C=10 pF, 2.7 V≤VDD≤3.6 V
-
2.8
C=10 pF, 1.62 V≤VDD≤2.7 V
-
5.2
DS12556 Rev 6
Unit
MHz
ns
MHz
ns
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 158. Output timing characteristics (HSLV OFF)(1)(2) (continued)
Speed
Symbol
Parameter
conditions
Min
Max
C=50 pF, 2.7 V≤VDD≤3.6 V
-
85
C=50 pF, 1.62 V≤VDD≤2.7 V(5)
-
35
-
110
C=30 pF, 1.62 V≤VDD≤2.7 V
-
40
C=10 pF, 2.7 V≤VDD≤3.6 V(5)
-
166
C=10 pF, 1.62 V≤VDD≤2.7 V(5)
-
100
-
3.8
(5)
(5)
Fmax(3)
Maximum frequency
10
C=30 pF, 2.7 V≤VDD≤3.6 V
(5)
(5)
C=50 pF, 2.7 V≤VDD≤3.6 V
(5)
C=50 pF, 1.62 V≤VDD≤2.7 V
tr/tf(4)
Output high to low level
fall time and output low
to high level rise time
-
6.9
V(5)
-
2.8
C=30 pF, 1.62 V≤VDD≤2.7 V(5)
-
5.2
C=10 pF, 2.7 V≤VDD≤3.6 V(5)
-
1.8
Vv
-
3.3
Vv
-
100
C=30 pF, 2.7 V≤VDD≤3.6
C=10 pF, 1.62 V≤VDD≤2.7
C=50 pF, 2.7 V≤VDD≤3.6
C=50 pF, 1.62 V≤VDD≤2.7 V(5)
Fmax(3)
Maximum frequency
11
-
50
C=30 pF, 2.7 V≤VDD≤3.6
Vv
-
133
C=30 pF, 1.62 V≤VDD≤2.7
V(5)
-
66
C=10 pF, 2.7 V≤VDD≤3.6 V(5)
-
220
C=10 pF, 1.62 V≤VDD≤2.7 V(5)
-
85
V(5)
-
3.3
V(5)
-
6.6
V(5)
-
2.4
C=30 pF, 1.62 V≤VDD≤2.7 V(5)
-
4.5
C=10 pF, 2.7 V≤VDD≤3.6 V(5)
-
1.5
V(5)
-
2.7
C=50 pF, 2.7 V≤VDD≤3.6
C=50 pF, 1.62 V≤VDD≤2.7
tr/tf(4)
Output high to low level
fall time and output low
to high level rise time
C=30 pF, 2.7 V≤VDD≤3.6
C=10 pF, 1.62 V≤VDD≤2.7
Unit
MHz
ns
MHz
ns
1. Guaranteed by design.
2. The frequency of the GPIOs that can be supplied in VBAT mode (PC13, PC14, PC15 and PI8) is limited to 2 MHz
3. The maximum frequency is defined with the following conditions:
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45%<Duty cycle<55%
4. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
5. Compensation system enabled.
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Output buffer timing characteristics (HSLV option enabled)
Table 159. Output timing characteristics (HSLV ON)(1)
Speed
Symbol
Fmax
(2)
Parameter
Maximum frequency
00
tr/tf(3)
Fmax
(2)
Output high to low level
fall time and output low
to high level rise time
Maximum frequency
01
tr/tf(3)
Fmax
(2)
Output high to low level
fall time and output low
to high level rise time
Maximum frequency
10
tr/tf(3)
Fmax
(2)
Output high to low level
fall time and output low
to high level rise time
Maximum frequency
11
tr/tf(3)
Output high to low level
fall time and output low
to high level rise time
conditions
Min
Max
C=50 pF, 1.62 V≤VDD≤2.7 V
-
10
C=30 pF, 1.62 V≤VDD≤2.7 V
-
10
C=10 pF, 1.62 V≤VDD≤2.7 V
-
10
C=50 pF, 1.62 V≤VDD≤2.7 V
-
11
C=30 pF, 1.62 V≤VDD≤2.7 V
-
9
C=10 pF, 1.62 V≤VDD≤2.7 V
-
6.6
C=50 pF, 1.62 V≤VDD≤2.7 V
-
50
C=30 pF, 1.62 V≤VDD≤2.7 V
-
58
C=10 pF, 1.62 V≤VDD≤2.7 V
-
66
C=50 pF, 1.62 V≤VDD≤2.7 V
-
6.6
C=30 pF, 1.62 V≤VDD≤2.7 V
-
4.8
C=10 pF, 1.62 V≤VDD≤2.7 V
-
3
C=50 pF, 1.62 V≤VDD≤2.7 V(4)
-
55
C=30 pF, 1.62 V≤VDD≤2.7
V(4)
-
80
C=10 pF, 1.62 V≤VDD≤2.7
V(4)
-
133
C=50 pF, 1.62 V≤VDD≤2.7
V(4)
-
5.8
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
-
4
C=10 pF, 1.62 V≤VDD≤2.7
V(4)
-
2.4
C=50 pF, 1.62 V≤VDD≤2.7
V(4)
-
60
C=30 pF, 1.62 V≤VDD≤2.7
V(4)
-
90
C=10 pF, 1.62 V≤VDD≤2.7 V(4)
-
175
C=50 pF, 1.62 V≤VDD≤2.7
V(4)
-
5.3
C=30 pF, 1.62 V≤VDD≤2.7
V(4)
-
3.6
(4)
-
1.9
C=10 pF, 1.62 V≤VDD≤2.7 V
Unit
MHz
ns
MHz
ns
MHz
ns
MHz
ns
1. Guaranteed by design.
2. The maximum frequency is defined with the following conditions:
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45%<Duty cycle<55%
3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
4. Compensation system enabled.
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
7.3.16
Electrical characteristics (rev V)
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 155: I/O static characteristics).
Unless otherwise specified, the parameters given in Table 160 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 120: General operating conditions.
Table 160. NRST pin characteristics
Symbol
RPU(2)
Parameter
Conditions
Min
Typ
Max
Unit
VIN = VSS
30
40
50
㏀
1.71 V < VDD < 3.6 V
-
-
50
1.71 V < VDD < 3.6 V
300
-
-
1.62 V < VDD < 3.6 V
1000
-
-
Weak pull-up equivalent
resistor(1)
VF(NRST)(2) NRST Input filtered pulse
VNF(NRST)(2) NRST Input not filtered pulse
ns
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
2. Guaranteed by design.
Figure 72. Recommended NRST pin protection
VDD
External
reset circuit (1)
RPU
NRST (2)
Internal Reset
Filter
0.1 μF
STM32
ai14132d
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 155. Otherwise the reset is not taken into account by the device.
7.3.17
FMC characteristics
Unless otherwise specified, the parameters given in Table 161 to Table 174 for the FMC
interface are derived from tests performed under the ambient temperature, fHCLK frequency
and VDD supply voltage conditions summarized in Table 120: General operating conditions,
with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Measurement points are done at CMOS levels: 0.5VDD
•
IO Compensation cell activated.
•
HSLV activated when VDD ≤ 2.7 V
•
VOS level set to VOS1.
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Electrical characteristics (rev V)
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Refer to Section 7.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics.
Asynchronous waveforms and timings
Figure 73 through Figure 75 represent asynchronous waveforms and Table 161 through
Table 168 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
•
AddressSetupTime = 0x1
•
AddressHoldTime = 0x1
•
DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)
•
BusTurnAroundDuration = 0x0
•
Capacitive load CL = 30 pF
In all timing tables, the TKERCK is the fmc_ker_ck clock period.
Figure 73. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
tw(NE)
FMC_NE
tv(NOE_NE)
t w(NOE)
t h(NE_NOE)
FMC_NOE
FMC_NWE
tv(A_NE)
FMC_A[25:0]
t h(A_NOE)
Address
tv(BL_NE)
t h(BL_NOE)
FMC_NBL[1:0]
t h(Data_NE)
t su(Data_NOE)
th(Data_NOE)
t su(Data_NE)
Data
FMC_D[15:0]
t v(NADV_NE)
tw(NADV)
FMC_NADV
(1)
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32753V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
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Electrical characteristics (rev V)
Table 161. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)
Symbol
Parameter
Min
tw(NE)
FMC_NE low time
3Tfmc_ker_ck–1
tv(NOE_NE)
FMC_NEx low to FMC_NOE low
0
0.5
tw(NOE)
FMC_NOE low time
2Tfmc_ker_ck –1
2Tfmc_ker_ck+1
th(NE_NOE)
FMC_NOE high to FMC_NE high
hold time
0
-
tv(A_NE)
FMC_NEx low to FMC_A valid
-
0.5
th(A_NOE)
Address hold time after
FMC_NOE high
0
-
tsu(Data_NE)
Data to FMC_NEx high setup
time
11
-
tsu(Data_NOE)
Data to FMC_NOEx high setup
time
11
-
th(Data_NOE)
Data hold time after FMC_NOE
high
0
-
th(Data_NE)
Data hold time after FMC_NEx
high
0
-
-
0
-
Tfmc_ker_ck+1
tv(NADV_NE) FMC_NEx low to FMC_NADV low
tw(NADV)
FMC_NADV low time
Max
Unit
3Tfmc_ker_ck+1
ns
1. Guaranteed by characterization results.
Table 162. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT
timings(1)(2)
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
7Tfmc_ker_ck+1
7Tfmc_ker_ck+1
tw(NOE)
FMC_NOE low time
5Tfmc_ker_ck–1
5Tfmc_ker_ck +1
tw(NWAIT)
FMC_NWAIT low time
Tfmc_ker_ck– 0.5
tsu(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx
high
4Tfmc_ker_ck +11
-
th(NE_NWAIT)
FMC_NEx hold time after
FMC_NWAIT invalid
3Tfmc_ker_ck+11.5
-
ns
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
DS12556 Rev 6
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311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 74. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
tw(NE)
FMC_NEx
FMC_NOE
tv(NWE_NE)
t h(NE_NWE)
tw(NWE)
FMC_NWE
tv(A_NE)
FMC_A[25:0]
th(A_NWE)
Address
tv(BL_NE)
FMC_NBL[1:0]
th(BL_NWE)
NBL
tv(Data_NE)
th(Data_NWE)
Data
FMC_D[15:0]
t v(NADV_NE)
FMC_NADV (1)
tw(NADV)
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32754V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
246/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 163. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)
Symbol
Parameter
Min
Max
tw(NE)
FMC_NE low time
3Tfmc_ker_ck –1
3Tfmc_ker_ck
tv(NWE_NE)
FMC_NEx low to FMC_NWE low
Tfmc_ker_ck
Tfmc_ker_ck+1
tw(NWE)
FMC_NWE low time
Tfmc_ker_ck –0.5
Tfmc_ker_ck+0.5
th(NE_NWE)
FMC_NWE high to FMC_NE high
hold time
Tfmc_ker_ck
-
tv(A_NE)
FMC_NEx low to FMC_A valid
-
2
th(A_NWE)
Address hold time after FMC_NWE
high
Tfmc_ker_ck –0.5
-
tv(BL_NE)
FMC_NEx low to FMC_BL valid
-
0.5
th(BL_NWE)
FMC_BL hold time after FMC_NWE
high
Tfmc_ker_ck –0.5
-
tv(Data_NE)
Data to FMC_NEx low to Data valid
-
Tfmc_ker_ck+ 2.5
th(Data_NWE)
Data hold time after FMC_NWE high
Tfmc_ker_ck+0.5
-
tv(NADV_NE)
FMC_NEx low to FMC_NADV low
-
0
tw(NADV)
FMC_NADV low time
-
Tfmc_ker_ck+ 1
Unit
ns
1. Guaranteed by characterization results.
Table 164. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT
timings(1)(2)
Symbol
Parameter
Min
Max
tw(NE)
FMC_NE low time
8Tfmc_ker_ck –1
8Tfmc_ker_ck+1
tw(NWE)
FMC_NWE low time
6Tfmc_ker_ck –1.5
6Tfmc_ker_ck+0.5
tsu(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx
high
5Tfmc_ker_ck+13
-
th(NE_NWAIT)
FMC_NEx hold time after
FMC_NWAIT invalid
4Tfmc_ker_ck+13
-
Unit
ns
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
DS12556 Rev 6
247/336
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 75. Asynchronous multiplexed PSRAM/NOR read waveforms
tw(NE)
FMC_ NE
tv(NOE_NE)
t h(NE_NOE)
FMC_NOE
t w(NOE)
FMC_NWE
th(A_NOE)
tv(A_NE)
FMC_ A[25:16]
Address
tv(BL_NE)
th(BL_NOE)
FMC_ NBL[1:0]
NBL
th(Data_NE)
tsu(Data_NE)
t v(A_NE)
FMC_ AD[15:0]
tsu(Data_NOE)
th(Data_NOE)
Data
Address
th(AD_NADV)
t v(NADV_NE)
tw(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32755V1
248/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 165. Asynchronous multiplexed PSRAM/NOR read timings(1)
Symbol
Parameter
Min
Max
tw(NE)
FMC_NE low time
4Tfmc_ker_ck –1
4Tfmc_ker_ck +1
tv(NOE_NE)
FMC_NEx low to FMC_NOE low
2Tfmc_ker_ck
2Tfmc_ker_ck
+0.5
ttw(NOE)
FMC_NOE low time
Tfmc_ker_ck –1
th(NE_NOE)
FMC_NOE high to FMC_NE high hold
time
0
-
tv(A_NE)
FMC_NEx low to FMC_A valid
-
0.5
tv(NADV_NE)
FMC_NEx low to FMC_NADV low
0
0.5
tw(NADV)
FMC_NADV low time
Tfmc_ker_ck –0.5
Tfmc_ker_ck +1
th(AD_NADV)
FMC_AD(address) valid hold time
after FMC_NADV high)
Tfmc_ker_ck +0.5
-
th(A_NOE)
Address hold time after FMC_NOE
high
Tfmc_ker_ck –0.5
-
tsu(Data_NE)
Data to FMC_NEx high setup time
11
-
tsu(Data_NOE)
Data to FMC_NOE high setup time
11
-
th(Data_NE)
Data hold time after FMC_NEx high
0
-
th(Data_NOE)
Data hold time after FMC_NOE high
0
-
Unit
Tfmc_ker_ck +1
ns
1. Guaranteed by characterization results.
Table 166. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)(2)
Symbol
Parameter
Min
Max
Unit
tw(NE)
FMC_NE low time
8Tfmc_ker_ck –1
8Tfmc_ker_ck
tw(NOE)
FMC_NWE low time
5Tfmc_ker_ck –1.5
5Tfmc_ker_ck +0.5
tsu(NWAIT_NE)
FMC_NWAIT valid before
FMC_NEx high
4Tfmc_ker_ck +11
-
th(NE_NWAIT)
FMC_NEx hold time after
FMC_NWAIT invalid
3Tfmc_ker_ck +11.5
-
ns
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
DS12556 Rev 6
249/336
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 167. Asynchronous multiplexed PSRAM/NOR write timings(1)
Symbol
Parameter
Min
Max
tw(NE)
FMC_NE low time
4Tfmc_ker_ck –1
4Tfmc_ker_ck
tv(NWE_NE)
FMC_NEx low to FMC_NWE low
Tfmc_ker_ck –1
Tfmc_ker_ck +0.5
tw(NWE)
FMC_NWE low time
2Tfmc_ker_ck –0.5
2Tfmc_ker_ck +0.5
th(NE_NWE)
FMC_NWE high to FMC_NE high hold
time
Tfmc_ker_ck –0.5
-
tv(A_NE)
FMC_NEx low to FMC_A valid
-
0
tv(NADV_NE)
FMC_NEx low to FMC_NADV low
0
0.5
tw(NADV)
FMC_NADV low time
Tfmc_ker_ck
Tfmc_ker_ck + 1
th(AD_NADV)
FMC_AD(adress) valid hold time after
FMC_NADV high)
Tfmc_ker_ck +0.5
-
th(A_NWE)
Address hold time after FMC_NWE
high
Tfmc_ker_ck +0.5
-
th(BL_NWE)
FMC_BL hold time after FMC_NWE
high
Tfmc_ker_ck – 0.5
-
tv(BL_NE)
FMC_NEx low to FMC_BL valid
-
0.5
tv(Data_NADV)
FMC_NADV high to Data valid
-
Tfmc_ker_ck +2
th(Data_NWE)
Data hold time after FMC_NWE high
Tfmc_ker_ck +0.5
-
Unit
ns
1. Guaranteed by characterization results.
Table 168. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2)
Symbol
Parameter
Min
Max
tw(NE)
FMC_NE low time
9Tfmc_ker_ck –1
9Tfmc_ker_ck
tw(NWE)
FMC_NWE low time
7Tfmc_ker_ck –0.5
7Tfmc_ker_ck +0.5
tsu(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx
high
5Tfmc_ker_ck +11
-
th(NE_NWAIT)
FMC_NEx hold time after
FMC_NWAIT invalid
4Tfmc_ker_ck +11.5
-
Unit
1. Guaranteed by characterization results.
2. NWAIT pulse width is equal to 1 AHB cycle.
Synchronous waveforms and timings
Figure 76 through Figure 79 represent synchronous waveforms and Table 169 through
Table 172 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
250/336
•
BurstAccessMode = FMC_BurstAccessMode_Enable
•
MemoryType = FMC_MemoryType_CRAM
•
WriteBurst = FMC_WriteBurst_Enable
•
CLKDivision = 1
•
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
DS12556 Rev 6
ns
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
In all the timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following
FMC_CLK maximum values:
•
For 2.7 V<VDD<3.6 V, FMC_CLK = 125 MHz at 20 pF
•
For 1.8 V<VDD<1.9 V, FMC_CLK = 100 MHz at 20 pF
•
For 1.62 V<VDD<1.8 V, FMC_CLK = 100 MHz at 15 pF
Figure 76. Synchronous multiplexed NOR/PSRAM read timings
BUSTURN = 0
tw(CLK)
tw(CLK)
FMC_CLK
Data latency = 0
td(CLKL-NExL)
FMC_NEx
t d(CLKL-NADVL)
td(CLKH-NExH)
td(CLKL-NADVH)
FMC_NADV
td(CLKL-AV)
td(CLKH-AIV)
FMC_A[25:16]
td(CLKL-NOEL)
td(CLKH-NOEH)
FMC_NOE
t d(CLKL-ADV)
FMC_AD[15:0]
td(CLKL-ADIV)
tsu(ADV-CLKH)
AD[15:0]
th(CLKH-ADV)
tsu(ADV-CLKH)
D1
tsu(NWAITV-CLKH)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tsu(NWAITV-CLKH)
tsu(NWAITV-CLKH)
th(CLKH-ADV)
D2
th(CLKH-NWAITV)
th(CLKH-NWAITV)
th(CLKH-NWAITV)
MS32757V1
DS12556 Rev 6
251/336
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 169. Synchronous multiplexed NOR/PSRAM read timings(1)
Symbol
Parameter
Min
Max
tw(CLK)
FMC_CLK period
2Tfmc_ker_ck –1
-
td(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2)
-
1
td(CLKH_NExH)
FMC_CLK high to FMC_NEx high (x= 0…2)
Tfmc_ker_ck+0.5
-
td(CLKL-NADVL)
FMC_CLK low to FMC_NADV low
-
1
td(CLKL-NADVH)
FMC_CLK low to FMC_NADV high
0
-
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x=16…25)
-
2.5
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid
(x=16…25)
Tfmc_ker_ck
-
td(CLKL-NOEL)
FMC_CLK low to FMC_NOE low
-
1.5
td(CLKH-NOEH)
FMC_CLK high to FMC_NOE high
Tfmc_ker_ck –0.5
-
td(CLKL-ADV)
FMC_CLK low to FMC_AD[15:0] valid
-
3
td(CLKL-ADIV)
FMC_CLK low to FMC_AD[15:0] invalid
0
-
tsu(ADV-CLKH)
FMC_A/D[15:0] valid data before FMC_CLK
high
3
-
th(CLKH-ADV)
FMC_A/D[15:0] valid data after FMC_CLK
high
0
-
tsu(NWAIT-CLKH)
FMC_NWAIT valid before FMC_CLK high
3
-
th(CLKH-NWAIT)
FMC_NWAIT valid after FMC_CLK high
1
-
1. Guaranteed by characterization results.
252/336
DS12556 Rev 6
Unit
ns
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Figure 77. Synchronous multiplexed PSRAM write timings
BUSTURN = 0
tw(CLK)
tw(CLK)
FMC_CLK
Data latency = 0
td(CLKL-NExL)
td(CLKH-NExH)
FMC_NEx
td(CLKL-NADVL)
td(CLKL-NADVH)
FMC_NADV
td(CLKH-AIV)
td(CLKL-AV)
FMC_A[25:16]
td(CLKH-NWEH)
td(CLKL-NWEL)
FMC_NWE
td(CLKL-ADIV)
td(CLKL-ADV)
FMC_AD[15:0]
td(CLKL-Data)
td(CLKL-Data)
AD[15:0]
D1
D2
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
td(CLKH-NBLH)
FMC_NBL
MS32758V1
DS12556 Rev 6
253/336
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 170. Synchronous multiplexed PSRAM write timings(1)
Symbol
Parameter
Min
Max
tw(CLK)
FMC_CLK period, VDD = 2.7 to 3.6 V
2Tfmc_ker_ck –1
1
-
td(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x =0..2)
-
1
td(CLKH-NExH)
FMC_CLK high to FMC_NEx high
(x = 0…2)
Tfmc_ker_ck +0.5
-
td(CLKL-NADVL)
FMC_CLK low to FMC_NADV low
-
1.5
td(CLKL-NADVH)
FMC_CLK low to FMC_NADV high
0
-
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid
(x =16…25)
-
2
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid
(x =16…25)
Tfmc_ker_ck
-
td(CLKL-NWEL)
FMC_CLK low to FMC_NWE low
-
1.5
t(CLKH-NWEH)
FMC_CLK high to FMC_NWE high
Tfmc_ker_ck +0.5
-
td(CLKL-ADV)
FMC_CLK low to to FMC_AD[15:0] valid
-
2.5
td(CLKL-ADIV)
FMC_CLK low to FMC_AD[15:0] invalid
0
-
td(CLKL-DATA)
FMC_A/D[15:0] valid data after FMC_CLK
low
-
2.5
td(CLKL-NBLL)
FMC_CLK low to FMC_NBL low
-
2
td(CLKH-NBLH)
FMC_CLK high to FMC_NBL high
Tfmc_ker_ck +0.5
-
tsu(NWAIT-CLKH)
FMC_NWAIT valid before FMC_CLK high
2
-
th(CLKH-NWAIT)
FMC_NWAIT valid after FMC_CLK high
2
-
1. Guaranteed by characterization results.
254/336
DS12556 Rev 6
Unit
Ns
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Figure 78. Synchronous non-multiplexed NOR/PSRAM read timings
tw(CLK)
tw(CLK)
FMC_CLK
td(CLKL-NExL)
td(CLKH-NExH)
Data latency = 0
FMC_NEx
td(CLKL-NADVL)
td(CLKL-NADVH)
FMC_NADV
td(CLKH-AIV)
td(CLKL-AV)
FMC_A[25:0]
td(CLKL-NOEL)
td(CLKH-NOEH)
FMC_NOE
tsu(DV-CLKH)
th(CLKH-DV)
tsu(DV-CLKH)
D1
FMC_D[15:0]
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tsu(NWAITV-CLKH)
tsu(NWAITV-CLKH)
tsu(NWAITV-CLKH)
th(CLKH-DV)
D2
th(CLKH-NWAITV)
t h(CLKH-NWAITV)
th(CLKH-NWAITV)
MS32759V1
DS12556 Rev 6
255/336
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 171. Synchronous non-multiplexed NOR/PSRAM read timings(1)
Symbol
Parameter
Min
Max
tw(CLK)
FMC_CLK period
2Tfmc_ker_ck –1
-
t(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2)
-
1
td(CLKH-NExH)
FMC_CLK high to FMC_NEx high
(x= 0…2)
2Tfmc_ker_ck+0.5
-
td(CLKL-NADVL)
FMC_CLK low to FMC_NADV low
-
0.5
td(CLKL-NADVH)
FMC_CLK low to FMC_NADV high
0
-
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid
(x=16…25)
-
2
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid
(x=16…25)
2Tfmc_ker_ck
-
td(CLKL-NOEL)
FMC_CLK low to FMC_NOE low
-
1.5
td(CLKH-NOEH)
FMC_CLK high to FMC_NOE high
2Tfmc_ker_ck-0.5
-
tsu(DV-CLKH)
FMC_D[15:0] valid data before FMC_CLK
high
3
-
th(CLKH-DV)
FMC_D[15:0] valid data after FMC_CLK
high
0
-
tsu(NWAIT-CLKH)
FMC_NWAIT valid before FMC_CLK high
3
-
th(CLKH-NWAIT)
FMC_NWAIT valid after FMC_CLK high
1
-
1. Guaranteed by characterization results.
256/336
DS12556 Rev 6
Unit
ns
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Figure 79. Synchronous non-multiplexed PSRAM write timings
tw(CLK)
tw(CLK)
FMC_CLK
td(CLKL-NExL)
td(CLKH-NExH)
Data latency = 0
FMC_NEx
td(CLKL-NADVL)
td(CLKL-NADVH)
FMC_NADV
td(CLKH-AIV)
td(CLKL-AV)
FMC_A[25:0]
td(CLKL-NWEL)
td(CLKH-NWEH)
FMC_NWE
td(CLKL-Data)
FMC_D[15:0]
td(CLKL-Data)
D1
D2
FMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
tsu(NWAITV-CLKH)
td(CLKH-NBLH)
th(CLKH-NWAITV)
FMC_NBL
MS32760V1
DS12556 Rev 6
257/336
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 172. Synchronous non-multiplexed PSRAM write timings(1)
Symbol
Parameter
Min
Max
t(CLK)
FMC_CLK period
2Tfmc_ker_ck –1
-
td(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2)
-
2
t(CLKH-NExH)
FMC_CLK high to FMC_NEx high
(x= 0…2)
Tfmc_ker_ck+0.5
-
td(CLKL-NADVL)
FMC_CLK low to FMC_NADV low
-
0.5
td(CLKL-NADVH)
FMC_CLK low to FMC_NADV high
0
-
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid
(x=16…25)
-
2.
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid
(x=16…25)
Tfmc_ker_ck
-
td(CLKL-NWEL)
FMC_CLK low to FMC_NWE low
-
1.5
td(CLKH-NWEH)
FMC_CLK high to FMC_NWE high
Tfmc_ker_ck+1
-
td(CLKL-Data)
FMC_D[15:0] valid data after FMC_CLK
low
-
3.5
td(CLKL-NBLL)
FMC_CLK low to FMC_NBL low
-
2
td(CLKH-NBLH)
FMC_CLK high to FMC_NBL high
Tfmc_ker_ck+1
-
tsu(NWAIT-CLKH)
FMC_NWAIT valid before FMC_CLK high
2
-
th(CLKH-NWAIT)
FMC_NWAIT valid after FMC_CLK high
2
-
1. Guaranteed by characterization results.
258/336
DS12556 Rev 6
Unit
ns
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
NAND controller waveforms and timings
Figure 80 through Figure 83 represent synchronous waveforms, and Table 173 and
Table 174 provide the corresponding timings. The results shown in this table are obtained
with the following FMC configuration:
•
COM.FMC_SetupTime = 0x01
•
COM.FMC_WaitSetupTime = 0x03
•
COM.FMC_HoldSetupTime = 0x02
•
COM.FMC_HiZSetupTime = 0x01
•
ATT.FMC_SetupTime = 0x01
•
ATT.FMC_WaitSetupTime = 0x03
•
ATT.FMC_HoldSetupTime = 0x02
•
ATT.FMC_HiZSetupTime = 0x01
•
Bank = FMC_Bank_NAND
•
MemoryDataWidth = FMC_MemoryDataWidth_16b
•
ECC = FMC_ECC_Enable
•
ECCPageSize = FMC_ECCPageSize_512Bytes
•
TCLRSetupTime = 0
•
TARSetupTime = 0
•
Capacitive load CL = 30 pF
In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period.
Figure 80. NAND controller waveforms for read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NWE
td(ALE-NOE)
th(NOE-ALE)
FMC_NOE (NRE)
tsu(D-NOE)
th(NOE-D)
FMC_D[15:0]
MS32767V1
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 81. NAND controller waveforms for write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
th(NWE-ALE)
td(ALE-NWE)
FMC_NWE
FMC_NOE (NRE)
th(NWE-D)
tv(NWE-D)
FMC_D[15:0]
MS32768V1
Figure 82. NAND controller waveforms for common memory read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
th(NOE-ALE)
td(ALE-NOE)
FMC_NWE
tw(NOE)
FMC_NOE
tsu(D-NOE)
th(NOE-D)
FMC_D[15:0]
MS32769V1
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Figure 83. NAND controller waveforms for common memory write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE)
tw(NWE)
th(NOE-ALE)
FMC_NWE
FMC_N OE
td(D-NWE)
tv(NWE-D)
th(NWE-D)
FMC_D[15:0]
MS32770V1
Table 173. Switching characteristics for NAND Flash read cycles(1)
Symbol
Parameter
Min
Max
tw(N0E)
FMC_NOE low width
4Tfmc_ker_ck – 0.5
4Tfmc_ker_ck+0.5
tsu(D-NOE)
FMC_D[15-0] valid data before
FMC_NOE high
8
-
th(NOE-D)
FMC_D[15-0] valid data after
FMC_NOE high
0
-
-
3Tfmc_ker_ck +1
4Tfmc_ker_ck –2
-
td(ALE-NOE) FMC_ALE valid before FMC_NOE low
th(NOE-ALE)
FMC_NWE high to FMC_ALE invalid
Unit
ns
1. Guaranteed by characterization results.
Table 174. Switching characteristics for NAND Flash write cycles(1)
Symbol
Parameter
Min
Max
tw(NWE)
FMC_NWE low width
4Tfmc_ker_ck – 0.5
4Tfmc_ker_ck +0.5
tv(NWE-D)
FMC_NWE low to FMC_D[15-0]
valid
0
-
th(NWE-D)
FMC_NWE high to FMC_D[15-0]
invalid
2Tfmc_ker_ck – 0.5
-
td(D-NWE)
FMC_D[15-0] valid before
FMC_NWE high
5Tfmc_ker_ck – 1
-
td(ALE-NWE)
FMC_ALE valid before FMC_NWE
low
-
3Tfmc_ker_ck +0.5
th(NWE-ALE)
FMC_NWE high to FMC_ALE
invalid
2Tfmc_ker_ck – 1
-
Unit
ns
1. Guaranteed by characterization results.
DS12556 Rev 6
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
SDRAM waveforms and timings
In all timing tables, the TKERCK is the fmc_ker_ck clock period, with the following
FMC_SDCLK maximum values:
•
For 2.7 V<VDD<3.6 V: FMC_CLK =110 MHz at 20 pF
•
For 1.8 V<VDD<1.9 V: FMC_CLK =100 MHz at 20 pF
•
For 1.62 V<DD<1.8 V, FMC_CLK =100 MHz at 15 pF
Figure 84. SDRAM read access waveforms (CL = 1)
FMC_SDCLK
td(SDCLKL_AddC)
th(SDCLKL_AddR)
td(SDCLKL_AddR)
FMC_A[12:0]
Row n
Col2
Col1
Coli
Coln
th(SDCLKL_AddC)
th(SDCLKL_SNDE)
td(SDCLKL_SNDE)
FMC_SDNE[1:0]
td(SDCLKL_NRAS)
th(SDCLKL_NRAS)
FMC_SDNRAS
th(SDCLKL_NCAS)
td(SDCLKL_NCAS)
FMC_SDNCAS
FMC_SDNWE
tsu(SDCLKH_Data)
FMC_D[31:0]
th(SDCLKH_Data)
Data1
Data2
Datai
Datan
MS32751V2
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DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 175. SDRAM read timings(1)
Symbol
Parameter
Min
Max
tw(SDCLK)
FMC_SDCLK period
2Tfmc_ker_ck – 1
2Tfmc_ker_ck
+0.5
tsu(SDCLKH _Data)
Data input setup time
3
-
th(SDCLKH_Data)
Data input hold time
0
-
td(SDCLKL_Add)
Address valid time
-
1.5
td(SDCLKL- SDNE)
Chip select valid time
-
1.5
th(SDCLKL_SDNE)
Chip select hold time
0.5
-
td(SDCLKL_SDNRAS)
SDNRAS valid time
-
1
th(SDCLKL_SDNRAS)
SDNRAS hold time
0.5
-
td(SDCLKL_SDNCAS)
SDNCAS valid time
-
0.5
th(SDCLKL_SDNCAS)
SDNCAS hold time
0
-
Unit
ns
1. Guaranteed by characterization results.
Table 176. LPSDR SDRAM read timings(1)
Symbol
Parameter
Min
Max
Unit
tW(SDCLK)
FMC_SDCLK period
2Tfmc_ker_ck – 1
2Tfmc_ker_ck+0.5
tsu(SDCLKH_Data)
Data input setup time
3
-
th(SDCLKH_Data)
Data input hold time
0.5
-
td(SDCLKL_Add)
Address valid time
-
2.5
td(SDCLKL_SDNE)
Chip select valid time
-
2.5
th(SDCLKL_SDNE)
Chip select hold time
0
-
td(SDCLKL_SDNRAS
SDNRAS valid time
-
0.5
th(SDCLKL_SDNRAS)
SDNRAS hold time
0
-
td(SDCLKL_SDNCAS)
SDNCAS valid time
-
1.5
th(SDCLKL_SDNCAS)
SDNCAS hold time
0
-
ns
1. Guaranteed by characterization results.
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 85. SDRAM write access waveforms
FMC_SDCLK
td(SDCLKL_AddC)
th(SDCLKL_AddR)
td(SDCLKL_AddR)
FMC_A[12:0]
Row n
Col2
Col1
Coli
Coln
th(SDCLKL_AddC)
th(SDCLKL_SNDE)
td(SDCLKL_SNDE)
FMC_SDNE[1:0]
th(SDCLKL_NRAS)
td(SDCLKL_NRAS)
FMC_SDNRAS
td(SDCLKL_NCAS)
th(SDCLKL_NCAS)
td(SDCLKL_NWE)
th(SDCLKL_NWE)
FMC_SDNCAS
FMC_SDNWE
td(SDCLKL_Data)
Data1
FMC_D[31:0]
Data2
Datai
Datan
th(SDCLKL_Data)
td(SDCLKL_NBL)
FMC_NBL[3:0]
MS32752V2
Table 177. SDRAM Write timings(1)
Symbol
Parameter
tw(SDCLK)
FMC_SDCLK period
td(SDCLKL _Data)
Data output valid time
-
1
th(SDCLKL _Data)
Data output hold time
0
-
td(SDCLKL_Add)
Address valid time
-
1.5
td(SDCLKL_SDNWE)
SDNWE valid time
-
1.5
th(SDCLKL_SDNWE)
SDNWE hold time
0.5
-
td(SDCLKL_ SDNE)
Chip select valid time
-
1.5
th(SDCLKL-_SDNE)
Chip select hold time
0.5
-
td(SDCLKL_SDNRAS)
SDNRAS valid time
-
1
th(SDCLKL_SDNRAS)
SDNRAS hold time
0.5
-
td(SDCLKL_SDNCAS)
SDNCAS valid time
-
1
td(SDCLKL_SDNCAS)
SDNCAS hold time
0.5
-
1. Guaranteed by characterization results.
264/336
DS12556 Rev 6
Min
Max
Unit
2Tfmc_ker_ck – 1 2Tfmc_ker_ck+0.5
ns
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 178. LPSDR SDRAM Write timings(1)
Symbol
Parameter
Min
Max
tw(SDCLK)
FMC_SDCLK period
td(SDCLKL _Data)
Data output valid time
-
2.5
th(SDCLKL _Data)
Data output hold time
0
-
td(SDCLKL_Add)
Address valid time
-
2.5
td(SDCLKL-SDNWE)
SDNWE valid time
-
2.5
th(SDCLKL-SDNWE)
SDNWE hold time
0
-
td(SDCLKL- SDNE)
Chip select valid time
-
3
th(SDCLKL- SDNE)
Chip select hold time
0
-
td(SDCLKL-SDNRAS)
SDNRAS valid time
-
1.5
th(SDCLKL-SDNRAS)
SDNRAS hold time
0
-
td(SDCLKL-SDNCAS)
SDNCAS valid time
-
1.5
td(SDCLKL-SDNCAS)
SDNCAS hold time
0
-
Unit
2Tfmc_ker_ck – 1 2Tfmc_ker_ck+0.5
ns
1. Guaranteed by characterization results.
7.3.18
Quad-SPI interface characteristics
Unless otherwise specified, the parameters given in Table 179 and Table 180 for QUADSPI
are derived from tests performed under the ambient temperature, fAHB frequency and VDD
supply voltage conditions summarized in Table 120: General operating conditions, with the
following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Measurement points are done at CMOS levels: 0.5VDD
•
IO Compensation cell activated.
•
HSLV activated when VDD ≤ 2.7 V
•
VOS level set to VOS1
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics.
The following table summarizes the parameters measured in SDR mode.
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 179. QUADSPI characteristics in SDR mode(1)
Symbol
Fck11/TCK
tw(CKH)
Parameter
QUADSPI clock
frequency
Conditions
Min
Typ
Max
2.7<VDD<3.6 V
CL = 20 pF
-
-
133
1.62<VDD<3.6 V
CL = 15 pF
-
-
100
TCK/2–0.5
-
TCK/2
TCK/2
-
TCK/2+0.5
(n/2)*TCK/(n+1)-0.5
-
(n/2)*TCK/ (n+1)
(n/2+1)*TCK/(n+1)
-
(n/2+1)*TCK/
(n+1)+0.5
2.7<VDD<3.6 V
2
-
-
1.62<VDD<3.6 V
2
-
-
2.7<VDD<3.6 V
1
-
-
1.62<VDD<3.6 V
2.5
-
-
MHz
QUADSPI clock high
and low time Even
division
PRESCALER[7:0] =
n = 0,1,3,5...
tw(CKL)
QUADSPI clock high
and low time Odd
division
PRESCALER[7:0] =
n = 2,4,6,8...
ts(IN)
Data input setup time
th(IN)
Data input hold time
tv(OUT)
Data output valid time
-
-
1
2
th(OUT)
Data output hold time
-
0
-
-
tw(CKL)
tw(CKH)
1. Guaranteed by characterization results.
The following table summarizes the parameters measured in DDR mode.
266/336
Unit
DS12556 Rev 6
ns
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 180. QUADSPI characteristics in DDR mode(1)
Symbol
Fck11/TCK
tw(CKH)
tw(CKL)
tw(CKH)
tw(CKL)
Parameter
QUADSPI clock frequency
QUADSPI clock high and
low time Even division
QUADSPI clock high and
low time Odd division
tsr(IN), tsf(IN)
Data input setup time
thr(IN),thf(IN)
Data input hold time
tvr(OUT),
tvf(OUT)
thr(OUT),
thf(OUT)
Data output valid time
Data output hold time
Conditions
Min
Typ
Max
2.7<VDD<3.6 V
CL = 20 pF
-
-
100
1.62<VDD<3.6 V
CL = 15 pF
-
-
100
TCK/2–0.5
-
TCK/2
TCK/2
-
TCK/2+0.5
(n/2)*TCK/
(n+1)-0.5
-
(n/2)*TCK/
(n+1)
(n/2+1)*TCK/
(n+1)
-
(n/2+1)*TCK /
(n+1)+0.5
2.7<VDD<3.6 V
2.5
-
-
1.62<VDD<3.6 V
1.5
2.7<VDD<3.6 V
1
-
-
1.62<VDD<3.6 V
2.5
DHHC=0
-
5
6
DHHC=1
PRESCALER[7:0] =
1,2…
-
TCK/4+1
TCK/4+2
DHHC=0
3
-
-
DHHC=1
PRESCALER[7:0]=1
,2…
TCK/4
-
-
PRESCALER[7:0] =
n = 0,1,3,5...
PRESCALER[7:0] =
n = 2,4,6,8...
Unit
MHz
ns
1. Guaranteed by characterization results.
Figure 86. QUADSPI timing diagram - SDR mode
tr(CK)
t(CK)
tw(CKH)
tw(CKL)
tf(CK)
Clock
tv(OUT)
Data output
th(OUT)
D1
D0
ts(IN)
Data input
D0
D2
th(IN)
D1
D2
MSv36878V1
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 87. Quad-SPI timing diagram - DDR mode
tr(CLK)
t(CLK)
tw(CLKH)
tw(CLKL)
tf(CLK)
Clock
tvf(OUT)
Data output
thr(OUT)
tvr(OUT)
IO0
IO1
IO2
thf(OUT)
IO3
IO4
tsf(IN) thf(IN)
Data input
IO0
IO1
IO5
tsr(IN) thr(IN)
IO2
IO4
IO3
IO5
MSv36879V3
7.3.19
Delay block (DLYB) characteristics
Unless otherwise specified, the parameters given in Table 181 for Delay Block are derived
from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply
voltage summarized in Table 120: General operating conditions, with the following
configuration:
Table 181. Delay Block characteristics
7.3.20
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tinit
Initial delay
-
1400
2200
2400
ps
t∆
Unit Delay
-
35
40
45
-
16-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 182 are derived from tests
performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 120: General operating conditions.
Table 182. ADC characteristics(1)(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
Analog supply
voltage for ADC
ON
-
1.62
-
3.6
V
VREF+
Positive reference
voltage
-
1.62
-
VDDA
V
VREF-
Negative
reference voltage
-
fADC
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ADC clock
frequency
1.62 V ≤ VDDA ≤ 3.6 V
DS12556 Rev 6
V
VSSA
BOOST = 11
0.12
-
50
BOOST = 10
0.12
-
25
BOOST = 01
0.12
-
12.5
BOOST = 00
-
-
6.25
MHz
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 182. ADC characteristics(1)(2) (continued)
Symbol
Parameter
Conditions
Resolution = 16 bits,
VDDA >2.5 V
Sampling rate for
Direct channels(4)
-
-
3.60
Resolution = 16 bits
fADC=37 MHz
SMP = 2.5
-
-
3.35
Resolution = 14 bits
fADC = 50 MHz
SMP = 2.5
-
-
5.00
fADC = 50 MHz
SMP = 2.5
-
-
5.50
Resolution = 12 bits
TJ = 125 °C
fADC = 50 MHz
SMP = 1.5
-
-
7.10
fADC = 50 MHz
SMP = 1.5
-
-
8.30
fADC=32 MHz
SMP = 2.5
-
-
2.90
Resolution = 16 bits
fADC=31 MHz
SMP = 2.5
-
-
2.80
Resolution = 14 bits
fADC = 33 MHz
SMP = 2.5
-
-
3.30
fADC = 39 MHz
SMP = 2.5
-
-
4.30
fADC = 48 MHz
SMP = 2.5
-
-
6.00
fADC = 50 MHz
SMP = 2.5
-
-
7.10
-
-
-
-
-
-
-
-
-
-
Resolution = 16 bits,
VDDA >2.5 V
Resolution = 12 bits
Resolution = 10 bits
TJ = 90 °C
TJ = 125 °C
Resolution = 8 bits
Resolution = 16 bits
TJ = 90 °C
resolution = 14 bits
Sampling rate for
Slow channels
Max
SMP = 1.5
TJ = 90 °C
Resolution = 8 bits
Sampling rate for
Fast channels
Typ
fADC=36 MHz
Resolution = 10 bits
fs(3)
Min
resolution = 12 bits
resolution = 10 bits
TJ = 125 °C
fADC = 10 MHz
SMP = 1.5
resolution = 8 bits
Unit
MSps
1.00
tTRIG
External trigger
period
Resolution = 16 bits
-
-
10
1/
fADC
VAIN(5)
Conversion
voltage range
-
0
-
VREF+
V
VCMIV
Common mode
input voltage
-
VREF/2
− 10%
VREF/
2
VREF/2
+ 10%
V
RAIN(6)
External input
impedance
Resolution = 16 bits, TJ = 125 °C
-
-
-
-
170
Resolution = 14 bits, TJ = 125 °C
-
-
-
-
435
Resolution = 12 bits, TJ =125 °C
-
-
-
-
1150
Resolution = 10 bits, TJ = 125 °C
-
-
-
-
5650
Resolution = 8 bits, TJ = 125 °C
-
-
-
-
26500
Ω
CADC
Internal sample
and hold
capacitor
-
-
4
-
pF
tADCVREG
_STUP
ADC LDO startup
time
-
-
5
10
us
tSTAB
ADC Power-up
time
LDO already started
1
-
-
conver
sion
cycle
tCAL
Offset and
linearity
calibration time
-
165010
-
-
1/fADC
tOFF_
Offset calibration
time
-
1280
-
-
1/fADC
CAL
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 182. ADC characteristics(1)(2) (continued)
Symbol
Parameter
tLATR
Trigger
conversion
latency regular
and injected
channels without
conversion abort
tLATRINJ
Trigger
conversion
latency regular
injected channels
aborting a regular
conversion
Conditions
Min
Typ
Max
CKMODE = 00
1.5
2
2.5
CKMODE = 01
-
-
2.5
CKMODE = 10
-
-
2.5
CKMODE = 11
-
-
2.25
CKMODE = 00
2.5
3
3.5
CKMODE = 01
-
-
3.5
CKMODE = 10
-
-
3.5
CKMODE = 11
-
-
3.25
Unit
1/fADC
1/fADC
tS
Sampling time
-
1.5
-
810.5
1/fADC
tCONV
Total conversion
time (including
sampling time)
Resolution = N bits
ts + 0.5
+ N/2
-
-
1/fADC
270/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 182. ADC characteristics(1)(2) (continued)
Symbol
Parameter
IDDA_SE(
ADC)
IDD
(ADC)
Min
Typ
Max
Resolution = 16 bits, fADC=25 MHz
-
-
-
1440
-
Resolution = 14 bits, fADC=30 MHz
-
-
-
1350
-
Resolution = 12 bits, fADC=40 MHz
-
-
-
990
-
ADC consumption
on VDDA
BOOST=10,
Differential mode
fADC=25 MHz
Resolution = 16 bits
-
-
-
1080
-
Resolution = 14 bits
-
-
-
810
-
Resolution = 12 bits
-
-
-
585
-
ADC consumption
on VDDA
BOOST=01,
Differential mode
fADC=12.5 MHz
Resolution = 16 bits
-
-
-
630
-
Resolution = 14 bits
-
-
-
432
-
Resolution = 12 bits
-
-
-
315
-
ADC consumption
on VDDA
BOOST=00,
Differential mode
fADC=6.25 MHz
Resolution = 16 bits
-
-
-
360
-
Resolution = 14 bits
-
-
-
270
-
Resolution = 12 bits
-
-
-
225
-
ADC consumption
on VDDA
BOOST=11,
Single-ended
mode
Resolution = 16 bits, fADC=25 MHz
-
-
-
720
-
Resolution = 14 bits, fADC=30 MHz
-
-
-
675
-
Resolution = 12 bits, fADC=40 MHz
-
-
-
495
-
ADC consumption
on VDDA
BOOST=10,
Singl-ended mode
fADC=25 MHz
Resolution = 16 bits
-
-
-
540
-
Resolution = 14 bits
-
-
-
405
-
Resolution = 12 bits
-
-
-
292.5
-
ADC consumption
on VDDA
BOOST=01,
Single-ended
mode
fADC=12.5 MHz
Resolution = 16 bits
-
-
-
315
-
Resolution = 14 bits
-
-
-
216
-
Resolution = 12 bits
-
-
-
157.5
-
ADC consumption
on VDDA
BOOST=00,
Single-ended
mode
fADC=6.25 MHz
Resolution = 16 bits
-
-
-
180
-
Resolution = 14 bits
-
-
-
135
-
Resolution = 12 bits
-
-
-
112.5
-
fADC=50 MHz
-
-
-
400
-
fADC=25 MHz
-
-
-
220
-
ADC consumption
on VDDA,
BOOST=11,
Differential mode
IDDA_D
(ADC)
Conditions
ADC consumption
on VDD
Unit
µA
fADC=12.5 MHz
-
-
-
180
-
fADC=6.25 MHz
-
-
-
120
-
fADC=3.125 MHz
-
-
-
80
-
1. Guaranteed by design.
2. The voltage booster on ADC switches must be used for VDDA < 2.4 V (embedded I/O switches).
3. These values are valid for UFBGA176+25 and one ADC. Refer to Getting started with the STM32H7 Series MCU 16-bit ADC
(AN5354) for values of other packages and multiple ADCs operation.
4. Direct channels are connected to analog I/Os (PA0_C, PA1_C, PC2_C and PC3_C) to optimize ADC performance.
5. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA.
6. The tolerance is 10 LSBs for 16-bit resolution, 4 LSBs for 14-bit resolution, and 2 LSBs for 12-bit, 10-bit and 8-bit resolutions.
DS12556 Rev 6
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311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 183. Minimum sampling time vs RAIN(1)(2)
Minimum sampling time (s)
Resolution
RAIN (Ω)
Direct
channels(3)
16 bits
47
7.37E-08
1.14E-07
1.72E-07
47
6.29E-08
9.74E-08
1.55E-07
68
6.84E-08
1.02E-07
1.58E-07
100
7.80E-08
1.12E-07
1.62E-07
150
9.86E-08
1.32E-07
1.80E-07
220
1.32E-07
1.61E-07
2.01E-07
47
5.32E-08
8.00E-08
1.29E-07
68
5.74E-08
8.50E-08
1.32E-07
100
6.58E-08
9.31E-08
1.40E-07
150
8.37E-08
1.10E-07
1.51E-07
220
1.11E-07
1.34E-07
1.73E-07
330
1.56E-07
1.78E-07
2.14E-07
470
2.16E-07
2.39E-07
2.68E-07
680
3.01E-07
3.29E-07
3.54E-07
47
4.34E-08
6.51E-08
1.08E-07
68
4.68E-08
6.89E-08
1.11E-07
100
5.35E-08
7.55E-08
1.16E-07
150
6.68E-08
8.77E-08
1.26E-07
220
8.80E-08
1.08E-07
1.40E-07
330
1.24E-07
1.43E-07
1.71E-07
470
1.69E-07
1.89E-07
2.13E-07
680
2.38E-07
2.60E-07
2.80E-07
1000
3.45E-07
3.66E-07
3.84E-07
1500
5.15E-07
5.35E-07
5.48E-07
2200
7.42E-07
7.75E-07
7.78E-07
3300
1.10E-06
1.14E-06
1.14E-06
14 bits
12 bits
10 bits
272/336
DS12556 Rev 6
Fast channels(4) Slow channels(5)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 183. Minimum sampling time vs RAIN(1)(2) (continued)
Minimum sampling time (s)
Resolution
8 bits
RAIN (Ω)
Direct
channels(3)
47
3.32E-08
5.10E-08
8.61E-08
68
3.59E-08
5.35E-08
8.83E-08
100
4.10E-08
5.83E-08
9.22E-08
150
5.06E-08
6.76E-08
9.95E-08
220
6.61E-08
8.22E-08
1.11E-07
330
9.17E-08
1.08E-07
1.32E-07
470
1.24E-07
1.40E-07
1.63E-07
680
1.74E-07
1.91E-07
2.12E-07
1000
2.53E-07
2.70E-07
2.85E-07
1500
3.73E-07
3.93E-07
4.05E-07
2200
5.39E-07
5.67E-07
5.75E-07
3300
8.02E-07
8.36E-07
8.38E-07
4700
1.13E-06
1.18E-06
1.18E-06
6800
1.62E-06
1.69E-06
1.68E-06
10000
2.36E-06
2.47E-06
2.45E-06
15000
3.50E-06
3.69E-06
3.65E-06
Fast channels(4) Slow channels(5)
1. Guaranteed by design.
2. Data valid at up to 125 °C, with a 47 pF PCB capacitor, and VDDA=1.6 V.
3. Direct channels are connected to analog I/Os (PA0_C, PA1_C, PC2_C and PC3_C) to optimize ADC performance.
4. Fast channels correspond to PF3, PF5, PF7, PF9, PA6, PC4, PB1, PF11 and PF13.
5. Slow channels correspond to all ADC inputs except for the Direct and Fast channels.
DS12556 Rev 6
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 184. ADC accuracy(1)(2)
Symbol
Parameter
Conditions(3)
Direct
channel
ET
Total undadjusted error
Fast channel
Slow
channel
Min
Typ
Max
Single ended
-
+10/–20
-
Differential
-
±15
-
Single ended
-
+10/–20
-
Differential
-
±15
-
Single ended
-
±10
-
±10
-
Differential
EO
Offset error
-
-
±10
-
EG
Gain error
-
-
±15
-
Single ended
-
+3/–1
-
Differential
-
+4.5/–1
-
Single ended
-
±11
-
Differential
-
±7
-
Single ended
-
±13
-
Differential
-
±7
-
Single ended
-
±10
-
Differential
-
±6
-
Single ended
-
12.2
-
Differential
-
13.2
-
Single ended
-
75.2
-
Differential
-
81.2
-
Single ended
-
77.0
-
Differential
-
81.0
-
Single ended
-
87
-
Differential
-
90
-
ED
Differential linearity error
Direct
channel
EL
Integral linearity error
Fast channel
Slow
channel
ENOB
Effective number of bits
SINAD
Signal-to-noise and
distortion ratio
SNR
Signal-to-noise ratio
THD
Total harmonic distortion
Unit
LSB
Bits
dB
1. Data guaranteed by characterization for BGA packages. The values for LQFP packages might differ.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC clock frequency = 25 MHz, ADC resolution = 16 bits, VDDA=VREF+=3.3 V and BOOST=11.
Note:
ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in
Section 7.3.14 does not affect the ADC accuracy.
274/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Figure 88. ADC accuracy characteristics (example for 12-bit resolution)
[1LSB IDEAL =
V REF+
4096
(or
V DDA
4096
depending on package)]
EG
4095
4094
4093
(2)
ET
(3)
7
(1)
6
5
EO
4
EL
3
ED
2
1L SBIDEAL
1
0
1
2
3
456
7
V SSA
4093 4094 4095 4096
VDDA
ai14395c
1. Example of an actual transfer curve.
2. Ideal transfer curve.
3. End point correlation line.
4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
Figure 89. Typical connection diagram using the ADC
STM32
VDD
RAIN(1) AINx
VAIN
Cparasitic
Sample and hold ADC
converter
VT
0.6 V
RADC(1)
VT
0.6 V
IL±1 μA
12-bit
converter
C ADC(1)
ai17534b
1. Refer to Table 182 for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
fADC should be reduced.
DS12556 Rev 6
275/336
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 90 or Figure 91,
depending on whether VREF+ is connected to VDDA or not. The 100 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 90. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32
VREF+(1)
1 μF // 100 nF
VDDA
1 μF // 100 nF
VSSA/VREF+(1)
MSv50648V1
1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176+25 and
TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA.
Figure 91. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32
VREF+/VDDA(1)
1 μF // 100 nF
VREF-/VSSA(1)
MSv50649V1
1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176+25 and
TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA.
276/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
7.3.21
Electrical characteristics (rev V)
DAC characteristics
Table 185. DAC characteristics(1)(2)
Symbol
Parameter
Conditions
Min
Typ
Max
VDDA
Analog supply voltage
-
1.8
3.3
3.6
VREF+
Positive reference voltage
-
1.80
-
VDDA
VREF-
Negative reference
voltage
-
-
VSSA
-
connected
to VSSA
5
-
-
connected
to VDDA
25
-
-
10.3
13
16
VDD =
2.7 V
-
-
1.6
VDD =
2.0 V
-
-
2.6
VDD =
2.7 V
-
-
17.8
VDD =
2.0 V
-
-
18.7
DAC output buffer OFF
-
-
50
pF
Sample and Hold mode
-
0.1
1
µF
DAC output buffer ON
0.2
-
VDDA
−0.2
V
DAC output buffer OFF
0
-
VREF+
±0.5 LSB
-
2.05
-
±1 LSB
-
1.97
-
±2 LSB
-
1.67
-
±4 LSB
-
1.66
-
±8 LSB
-
1.65
-
-
1.7
2
-
5
7.5
RL
Resistive Load
DAC output buffer
ON
RO
Output Impedance
RBON
Output impedance
sample and hold mode,
output buffer ON
DAC output buffer
ON
Output impedance
sample and hold mode,
output buffer OFF
DAC output buffer
OFF
RBOFF
CL
CSH
VDAC_OUT
Capacitive Load
Voltage on DAC_OUT
output
Settling time (full scale:
for a 12-bit code transition
between the lowest and
the highest input codes
tSETTLING
when DAC_OUT reaches
the final value of ±0.5LSB,
±1LSB, ±2LSB, ±4LSB,
±8LSB)
DAC output buffer OFF
Normal mode, DAC
output buffer ON,
CL ≤ 50 pF,
RL ≥ 5 ㏀
Normal mode, DAC output buffer
OFF, ±1LSB CL=10 pF
Wakeup time from off
Normal mode, DAC output buffer
state (setting the ENx bit
ON, CL ≤ 50 pF, RL = 5 ㏀
tWAKEUP(3)
in the DAC Control
Normal mode, DAC output buffer
register) until the final
OFF, CL ≤ 10 pF
value of ±1LSB is reached
PSRR
DC VDDA supply rejection
ratio
Normal mode, DAC output buffer
ON, CL ≤ 50 pF, RL = 5 ㏀
DS12556 Rev 6
Unit
V
kΩ
kΩ
kΩ
µs
µs
-
2
5
−80
−28
dB
277/336
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 185. DAC characteristics(1)(2) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
MODE<2:0>_V12=100/101
(BUFFER ON)
-
0.7
2.6
tSAMP
Sampling time in Sample
and Hold mode
CL=100 nF
(code transition between
the lowest input code and
the highest input code
when DAC_OUT reaches
the ±1LSB final value)
MODE<2:0>_V12=110
(BUFFER OFF)
-
11.5
18.7
MODE<2:0>_V12=111
(INTERNAL BUFFER OFF)
-
0.3
0.6
µs
ms
CIint
Internal sample and hold
capacitor
-
1.8
2.2
2.6
pF
tTRIM
Middle code offset trim
time
Minimum time to verify the each
code
50
-
-
µs
Voffset
Middle code offset for 1
trim code step
VREF+ = 3.6 V
-
850
-
VREF+ = 1.8 V
-
425
-
No load,
middle
code
(0x800)
-
360
-
No load,
worst code
(0xF1C)
-
490
-
No load,
middle/wor
st code
(0x800)
-
20
-
-
360*TON/
(TON+TOFF)
-
No load,
middle
code
(0x800)
-
170
-
No load,
worst code
(0xF1C)
-
170
-
No load,
middle/wor
st code
(0x800)
-
160
-
Sample and Hold mode, Buffer
ON, CSH=100 nF (worst code)
-
170*TON/
(TON+TOFF)
-
Sample and Hold mode, Buffer
OFF, CSH=100 nF (worst code)
-
160*TON/
(TON+TOFF)
-
DAC output buffer
ON
IDDA(DAC)
DAC quiescent
consumption from VDDA
DAC output buffer
OFF
Sample and Hold mode,
CSH=100 nF
DAC output buffer
ON
IDDV(DAC)
DAC consumption from
VREF+
DAC output buffer
OFF
1. Guaranteed by design unless otherwise specified.
278/336
DS12556 Rev 6
(4)
(4)
(4)
µV
µA
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
2. TBD stands for “to be defined”.
3. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).
4. TON is the refresh phase duration, while TOFF is the hold phase duration. Refer to the product reference manual for more
details.
Table 186. DAC accuracy(1)
Symbol
Parameter
Conditions
Min
Typ
Max
DNL
Differential non
linearity(2)
DAC output buffer ON
−2
-
2
DAC output buffer OFF
−2
-
2
-
Monotonicity
10 bits
-
-
-
DAC output buffer ON, CL ≤ 50 pF,
RL ≥ 5 ㏀
−4
-
4
DAC output buffer OFF,
CL ≤ 50 pF, no RL
−4
-
4
VREF+ = 3.6 V
-
-
±15
VREF+ = 1.8 V
-
-
±30
DAC output buffer OFF,
CL ≤ 50 pF, no RL
-
-
±8
DAC output buffer OFF,
CL ≤ 50 pF, no RL
-
-
±5
VREF+ = 3.6 V
-
-
±6
VREF+ = 1.8 V
-
-
±7
DAC output buffer ON,CL ≤ 50 pF,
RL ≥ 5 ㏀
-
-
±1
DAC output buffer OFF,
CL ≤ 50 pF, no RL
-
-
±1
DAC output buffer ON,CL ≤ 50 pF,
RL ≥ 5 ㏀ , 1 kHz, BW = 500 KHz
-
67.8
-
DAC output buffer OFF,
CL ≤ 50 pF, no RL,1 kHz, BW =
500 KHz
-
67.8
-
DAC output buffer ON, CL ≤ 50 pF,
RL ≥ 5 ㏀ , 1 kHz
-
−78.6
-
DAC output buffer OFF,
CL ≤ 50 pF, no RL, 1 kHz
-
−78.6
-
DAC output buffer ON, CL ≤ 50 pF,
RL ≥ 5 ㏀ , 1 kHz
-
67.5
-
DAC output buffer OFF,
CL ≤ 50 pF, no RL, 1 kHz
-
67.5
-
INL
Offset
Integral non
linearity(3)
Offset error at code
0x800 (3)
Offset1
Offset error at code
0x001(4)
OffsetCal
Offset error at code
0x800 after factory
calibration
Gain
SNR
THD
SINAD
Gain error(5)
Signal-to-noise ratio(6)
Total harmonic
distortion(6)
Signal-to-noise and
distortion ratio(6)
DAC output
buffer ON,
CL ≤ 50 pF,
RL ≥ 5 ㏀
DAC output
buffer ON,
CL ≤ 50 pF,
RL ≥ 5 ㏀
DS12556 Rev 6
Unit
LSB
-
LSB
LSB
LSB
LSB
%
dB
dB
dB
279/336
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 186. DAC accuracy(1) (continued)
Symbol
ENOB
Parameter
Effective number of
bits
Conditions
Min
Typ
Max
DAC output buffer ON,
CL ≤ 50 pF, RL ≥ 5 ㏀ , 1 kHz
-
10.9
-
DAC output buffer OFF,
CL ≤ 50 pF, no RL, 1 kHz
-
Unit
bits
10.9
-
1. Guaranteed by characterization.
2. Difference between two consecutive codes minus 1 LSB.
3. Difference between the value measured at Code i and the value measured at Code i on a line drawn between Code 0 and
last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF
when the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON.
6. Signal is −0.5dBFS with Fsampling=1 MHz.
Figure 92. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
RL
DAC_OUTx
12-bit
digital to
analog
converter
CL
ai17157V3
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
280/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
7.3.22
Electrical characteristics (rev V)
Voltage reference buffer characteristics
Table 187. VREFBUF characteristics(1)
Symbol
Parameter
Conditions
Normal mode
VDDA
Analog supply voltage
Degraded mode
Normal mode
VREFBUF
_OUT
Voltage Reference
Buffer Output, at 30 °C,
Iload= 100 µA
Degraded
Min
Typ
Max
VSCALE = 000
2.8
3.3
3.6
VSCALE = 001
2.4
-
3.6
VSCALE = 010
2.1
-
3.6
VSCALE = 011
1.8
-
3.6
VSCALE = 000
1.62
-
2.80
VSCALE = 001
1.62
-
2.40
VSCALE = 010
1.62
-
2.10
VSCALE = 011
1.62
-
1.80
VSCALE = 000
2.498
2.5
2.5035
VSCALE = 001
2.046
2.049
2.052
VSCALE = 010
1.801
1.804
1.806
VSCALE = 011
1.4995
1.5015
1.504
VSCALE = 000
VDDA−
150 mV
-
VDDA
VSCALE = 001
VDDA−
150 mV
-
VDDA
VSCALE = 010
VDDA−
150 mV
-
VDDA
VSCALE = 011
VDDA−
150 mV
-
VDDA
mode(2)
Unit
V
TRIM
Trim step resolution
-
-
-
±0.05
±0.1
%
CL
Load capacitor
-
-
0.5
1
1.50
uF
esr
Equivalent Serial
Resistor of CL
-
-
-
-
2
Ω
Iload
Static load current
-
-
-
-
4
mA
Iline_reg
Line regulation
2.8 V ≤ VDDA ≤ 3.6 V
Iload = 500 µA
-
200
-
Iload = 4 mA
-
100
-
Iload_reg
Load regulation
500 µA ≤ ILOAD ≤ 4 mA
Normal Mode
-
50
-
ppm/
mA
Tcoeff
Temperature coefficient
-
-
Tcoeff
VREFINT
+ 100
ppm/
°C
PSRR
Power supply rejection
−40 °C < TJ < +125 °C
DC
-
-
60
-
100KHz
-
-
40
-
DS12556 Rev 6
ppm/V
dB
281/336
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 187. VREFBUF characteristics(1) (continued)
Symbol
tSTART
IINRUSH
IDDA(VRE
FBUF)
Parameter
Conditions
Start-up time
Typ
Max
CL=0.5 µF
-
-
300
-
CL=1 µF
-
-
500
-
CL=1.5 µF
-
-
650
-
-
8
-
Control of maximum
DC current drive on
VREFBUF_OUT during
startup phase(3)
-
VREFBUF
consumption from
VDDA
Min
Unit
µs
mA
ILOAD = 0 µA
-
-
15
25
ILOAD = 500 µA
-
-
16
30
ILOAD = 4 mA
-
-
32
50
µA
1. Guaranteed by design.
2.
In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (VDDA−drop voltage).
3. To properly control VREFBUF IINRUSH current during the startup phase and the change of scaling, VDDA voltage should be in
the range of 1.8 V-3.6 V, 2.1 V-3.6 V, 2.4 V-3.6 V and 2.8 V-3.6 V for VSCALE = 011, 010, 001 and 000, respectively.
7.3.23
Temperature sensor characteristics
Table 188. Temperature sensor characteristics
Symbol
Parameter
TL(1)
(2)
Avg_Slope
V30(3)
tstart_run
tS_temp
(1)
Isens(1)
Isensbuf(1)
Min
Typ
Max
Unit
VSENSE linearity with temperature
-
-
3
°C
Average slope
-
2
-
mV/°C
Voltage at 30°C ± 5 °C
-
0.62
-
V
Startup time in Run mode (buffer startup)
-
-
25.2
ADC sampling time when reading the temperature
9
-
-
Sensor consumption
-
0.18 0.31
Sensor buffer consumption
-
3.8
6.5
µs
µA
1. Guaranteed by design.
2. Guaranteed by characterization.
3. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1
byte.
Table 189. Temperature sensor calibration values
Symbol
282/336
Parameter
Memory address
TS_CAL1
Temperature sensor raw data acquired value at
30 °C, VDDA=3.3 V
0x1FF1 E820 -0x1FF1 E821
TS_CAL2
Temperature sensor raw data acquired value at
130 °C, VDDA=3.3 V
0x1FF1 E840 - 0x1FF1 E841
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
7.3.24
Electrical characteristics (rev V)
Temperature and VBAT monitoring
Table 190. VBAT monitoring characteristics
Symbol
Parameter
Min
Typ
Max
Unit
R
Resistor bridge for VBAT
-
26
-
KΩ
Q
Ratio on VBAT measurement
-
4
-
-
–10
-
+10
%
µs
(1)
Error on Q
Er
tS_vbat(1)
ADC sampling time when reading VBAT input
9
-
-
VBAThigh
High supply monitoring
-
3.55
-
VBATlow
Low supply monitoring
-
1.36
-
V
1. Guaranteed by design.
Table 191. VBAT charging characteristics
Symbol
RBC
Parameter
Battery charging resistor
Condition
Min
Typ
Max
VBRS in PWR_CR3= 0
-
5
-
1.5
-
VBRS in PWR_CR3= 1
Unit
KΩ
Table 192. Temperature monitoring characteristics
Symbol
7.3.25
Parameter
Min
Typ
Max
TEMPhigh
High temperature monitoring
-
117
-
TEMPlow
Low temperature monitoring
-
–25
-
Unit
°C
Voltage booster for analog switch
Table 193. Voltage booster for analog switch characteristics(1)
Symbol
VDD
Parameter
Condition
Min
Typ Max Unit
-
1.62
2.6
3.6
V
-
-
-
50
µs
1.62 V ≤ VDD ≤ 2.7 V
-
-
125
2.7 V < VDD < 3.6 V
-
-
250
Supply voltage
tSU(BOOST) Booster startup time
IDD(BOOST) Booster consumption
µA
1. Guaranteed by characterization results.
DS12556 Rev 6
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311
Electrical characteristics (rev V)
7.3.26
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Comparator characteristics
Table 194. COMP characteristics(1)
Symbol
Conditions
Min
Typ
Max
Analog supply voltage
-
1.62
3.3
3.6
VIN
Comparator input voltage
range
-
0
-
VDDA
V
VBG
Scaler input voltage
-
VSC
Scaler offset voltage
-
-
±5
±10
mV
BRG_EN=0 (bridge disable)
-
0.2
0.3
BRG_EN=1 (bridge enable)
-
0.8
1
-
-
140
250
High-speed mode
-
2
5
Medium mode
-
5
20
Ultra-low-power mode
-
15
80
High-speed mode
-
50
80
Medium mode
-
0.5
1.2
Ultra-low-power mode
-
2.5
7
High-speed mode
-
50
120
Medium mode
-
0.5
1.2
Ultra-low-power mode
-
2.5
7
Full common mode range
-
±5
±20
No hysteresis
-
0
-
Low hysteresis
5
10
22
Medium hysteresis
8
20
37
High hysteresis
16
30
52
Static
-
400
600
With 50 kHz
±100 mV overdrive
square signal
-
800
-
Static
-
5
7
-
6
-
Static
-
70
100
With 50 kHz
±100 mV overdrive
square signal
-
75
-
VDDA
IDDA(SCALER)
Parameter
Scaler static consumption
from VDDA
tSTART_SCALER Scaler startup time
tSTART
Comparator startup time to
reach propagation delay
specification
Propagation delay for
200 mV step with 100 mV
overdrive
tD(3)
Voffset
Vhys
Propagation delay for step
> 200 mV with 100 mV
overdrive only on positive
inputs
Comparator offset error
Comparator hysteresis
Ultra-lowpower mode
IDDA(COMP)
Comparator consumption
from VDDA
Medium mode With 50 kHz
±100 mV overdrive
square signal
High-speed
mode
1. Guaranteed by design, unless otherwise specified.
2. Refer to Table 125: Embedded reference voltage.
284/336
DS12556 Rev 6
Unit
(2)
µA
µs
µs
ns
µs
ns
µs
mV
mV
nA
µA
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
3. Guaranteed by characterization results.
7.3.27
Operational amplifier characteristics
Table 195. Operational amplifier characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
VDDA
Analog supply voltage
Range
-
2
3.3
3.6
CMIR
Common Mode Input
Range
-
0
-
VDDA
25°C, no load on output
-
-
±1.5
Unit
V
VIOFFSET
Input offset voltage
All voltages and
temperature, no load
-
-
±2.5
ΔVIOFFSET
Input offset voltage drift
-
-
±3.0
-
TRIMOFFSETP
TRIMLPOFFSETP
Offset trim step at low
common input voltage
(0.1*VDDA)
-
-
1.1
1.5
TRIMOFFSETN
TRIMLPOFFSETN
Offset trim step at high
common input voltage
(0.9*VDDA)
-
-
1.1
1.5
ILOAD
Drive current
-
-
-
500
ILOAD_PGA
Drive current in PGA mode
-
-
-
270
CLOAD
Capacitive load
-
-
-
50
pF
CMRR
Common mode rejection
ratio
-
-
80
-
dB
PSRR
Power supply rejection
ratio
CLOAD ≤ 50pf /
RLOAD ≥ 4 kΩ(1) at 1 kHz,
Vcom=VDDA/2
50
66
-
dB
GBW
Gain bandwidth for high
supply range
200 mV ≤ Output dynamic
range ≤ VDDA - 200 mV
4
7.3
12.3
MHz
SR
Slew rate (from 10% and
90% of output voltage)
Normal mode
-
3
-
High-speed mode
-
30
-
AO
Open loop gain
200 mV ≤ Output dynamic
range ≤ VDDA - 200 mV
59
90
129
dB
φm
Phase margin
-
-
55
-
°
GM
Gain margin
-
-
12
-
dB
VOHSAT
High saturation voltage
Iload=max or RLOAD=min,
Input at VDDA
VDDA
−100 mV
-
-
Low saturation voltage
Iload=max or RLOAD=min,
Input at 0 V
-
-
VOLSAT
mV
μV/°C
mV
DS12556 Rev 6
μA
V/µs
mV
100
285/336
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 195. Operational amplifier characteristics (continued)
Symbol
tWAKEUP
Parameter
Wake up time from OFF
state
Non inverting gain error
value
PGA gain
Inverting gain error value
External non-inverting gain
error value
R2/R1 internal resistance
values in non-inverting
PGA mode(2)
Rnetwork
R2/R1 internal resistance
values in inverting PGA
mode(2)
Delta R
286/336
Resistance variation (R1
or R2)
Conditions
Min
Typ
Max
0.8
3.2
Normal
mode
CLOAD ≤ 50pf,
RLOAD ≥ 4 kΩ,
follower
configuration
-
High
speed
mode
CLOAD ≤ 50pf,
RLOAD ≥ 4 kΩ,
follower
configuration
-
0.9
2.8
PGA gain = 2
−1
-
1
PGA gain = 4
−2
-
2
PGA gain = 8
−2.5
-
2.5
PGA gain = 16
−3
-
3
PGA gain = 2
−1
-
1
PGA gain = 4
−1
-
1
PGA gain = 8
−2
-
2
PGA gain = 16
−3
-
3
PGA gain = 2
−1
-
1
PGA gain = 4
−3
-
3
PGA gain = 8
−3.5
-
3.5
PGA gain = 16
−4
-
4
PGA Gain=2
-
10/10
-
PGA Gain=4
-
30/10
-
PGA Gain=8
-
70/10
-
PGA Gain=16
-
150/10
-
PGA Gain = -1
-
10/10
-
PGA Gain = -3
-
30/10
-
PGA Gain = -7
-
70/10
-
PGA Gain = -15
-
150/10
-
-
−15
-
15
DS12556 Rev 6
Unit
µs
%
kΩ/
kΩ
%
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 195. Operational amplifier characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Gain=2
-
GBW/2
-
Gain=4
-
GBW/4
-
Gain=8
-
GBW/8
-
Gain=16
-
GBW/16
-
Gain = -1
-
5.00
-
Gain = -3
-
3.00
-
Gain = -7
-
1.50
-
Gain = -15
-
0.80
-
-
140
-
-
55
-
-
570
1000
-
610
1200
PGA bandwidth for
different non inverting gain
PGA BW
PGA bandwidth for
different inverting gain
en
Voltage noise density
IDDA(OPAMP)
OPAMP consumption from
VDDA
at
1 KHz
at
10 KHz
Normal
mode
Highspeed
mode
output loaded
with 4 kΩ
no Load,
quiescent mode,
follower
Unit
MHz
MHz
nV/√
Hz
µA
1. RLOAD is the resistive load connected to VSSA or to VDDA.
2. R2 is the internal resistance between the OPAMP output and th OPAMP inverting input. R1 is the internal resistance
between the OPAMP inverting input and ground. PGA gain = 1 + R2/R1.
7.3.28
Digital filter for Sigma-Delta Modulators (DFSDM) characteristics
Unless otherwise specified, the parameters given in Table 196 for DFSDM are derived from
tests performed under the ambient temperature, fPCLKx frequency and supply voltage
conditions summarized in Table 120: General operating conditions.
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load CL = 30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
•
VOS level set to VOS1
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (DìFSDM_CKINx, DFSDM_DATINx, DFSDM_CKOUT for DFSDM).
DS12556 Rev 6
287/336
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 196. DFSDM measured timing - 1.62-3.6 V
Symbol
Parameter
Conditions
Min
Typ
Max
fDFSDMCLK
DFSDM
clock
1.62 < VDD < 3.6 V
-
-
250
SPI mode (SITP[1:0]=0,1),
External clock mode (SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
-
-
20
SPI mode (SITP[1:0]=0,1),
External clock mode (SPICKSEL[1:0]=0),
2.7 < VDD < 3.6 V
-
-
20
SPI mode (SITP[1:0]=0,1),
Internal clock mode (SPICKSEL[1:0]¹0),
1.62 < VDD < 3.6 V
-
-
20
SPI mode (SITP[1:0]=0,1),
Internal clock mode (SPICKSEL[1:0]¹0),
2.7 < VDD < 3.6 V
-
-
20
1.62 < VDD < 3.6 V
-
-
20
45
50
55
fCKIN
(1/TCKIN)
fCKOUT
DuCyCK
OUT
Input clock
frequency
Output clock
frequency
Output clock
frequency
duty cycle
1.62 < VDD < 3.6 V
MHz
Even division,
CKOUTDIV[7:0] =
1, 3, 5...
Odd division,
CKOUTDIV[7:0] =
2, 4, 6...
%
(((n/2+1)/(n+1)) (((n/2+1)/(n+1)) (((n/2+1)/(n+1))
*100)–5
*100)
*100)+5
twh(CKIN)
twl(CKIN)
Input clock
high and low
time
SPI mode (SITP[1:0]=0,1),
External clock mode (SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
TCKIN/2-0.5
TCKIN/2
-
tsu
Data input
setup time
SPI mode (SITP[1:0]=0,1),
External clock mode (SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
1.5
-
-
th
Data input
hold time
SPI mode (SITP[1:0]=0,1),
External clock mode (SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
0.5
-
-
TManchester
Manchester
data period
(recovered
clock period)
Manchester mode (SITP[1:0]=2,3),
Internal clock mode (SPICKSEL[1:0]¹0),
1.62 < VDD < 3.6 V
(CKOUTDIV+1)
* TDFSDMCLK
-
(2*CKOUTDIV)
* TDFSDMCLK
288/336
Unit
ns
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
DFSDM_CKINy
DFSDM_DATINy
DFSDM_CKOUT
(SPICKSEL=0)
tsu
th
twl
twh
tr
tf
tr
tf
SITP = 00
tsu
th
SITP = 01
SPICKSEL=3
SPICKSEL=2
SPICKSEL=1
tsu
DFSDM_DATINy
SPI timing : SPICKSEL = 1, 2, 3
SPI timing : SPICKSEL = 0
Figure 93. Channel transceiver timing diagrams
th
twl
twh
SITP = 0
tsu
th
SITP = 1
DFSDM_DATINy
Manchester timing
SITP = 2
SITP = 3
recovered clock
recovered data
0
0
1
1
0
MS30766V2
DS12556 Rev 6
289/336
311
Electrical characteristics (rev V)
7.3.29
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Camera interface (DCMI) timing specifications
Unless otherwise specified, the parameters given in Table 197 for DCMI are derived from
tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage
summarized in Table 120: General operating conditions, with the following configuration:
•
DCMI_PIXCLK polarity: falling
•
DCMI_VSYNC and DCMI_HSYNC polarity: high
•
Data formats: 14 bits
•
Capacitive load CL=30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
•
VOS level set to VOS1
Table 197. DCMI characteristics(1)
Symbol
Parameter
Min
Max
Unit
-
Frequency ratio DCMI_PIXCLK/fHCLK
-
0.4
-
DCMI_PIXCLK
Pixel Clock input
-
80
MHz
Dpixel
Pixel Clock input duty cycle
30
70
%
tsu(DATA)
Data input setup time
3
-
th(DATA)
Data hold time
1
-
tsu(HSYNC),
tsu(VSYNC)
DCMI_HSYNC/ DCMI_VSYNC input setup time
2
-
ns
th(HSYNC),
th(VSYNC)
DCMI_HSYNC/ DCMI_VSYNC input hold time
1
-
-
-
1. Guaranteed by characterization results.
Figure 94. DCMI timing diagram
1/DCMI_PIXCLK
DCMI_PIXCLK
tsu(HSYNC)
th(HSYNC)
DCMI_HSYNC
tsu(VSYNC)
th(HSYNC)
DCMI_VSYNC
tsu(DATA) th(DATA)
DATA[0:13]
MS32414V2
290/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
7.3.30
Electrical characteristics (rev V)
LCD-TFT controller (LTDC) characteristics
Unless otherwise specified, the parameters given in Table 198 for LCD-TFT are derived
from tests performed under the ambient temperature, fHCLK frequency and VDD supply
voltage summarized in Table 120: General operating conditions, with the following
configuration:
•
LCD_CLK polarity: high
•
LCD_DE polarity: low
•
LCD_VSYNC and LCD_HSYNC polarity: high
•
Pixel formats: 24 bits
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Capacitive load CL=30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
•
IO Compensation cell activated.
•
HSLV activated when VDD ≤ 2.7 V
•
VOS level set to VOS1
Table 198. LTDC characteristics(1)
Symbol
fCLK
Parameter
Min
2.7<VDD<3.6 V
20pF
LTDC clock
output
frequency
2.7<VDD<3.6 V
Max
150
-
1.62<VDD<3.6 V
133
LTDC clock output duty cycle
45
55
tw(CLKH),
tw(CLKL)
Clock High time, low time
tw(CLK)//2-0.5
tw(CLK)//2+0.5
th(DATA)
tv(DATA)
tv(HSYNC),
tv(VSYNC),
tv(DE)
th(HSYNC),
th(VSYNC),
th(DE)
2.7<VDD<3.6 V
Data output valid time
1.62<VDD<3.6 V
Data output hold time
HSYNC/VSYNC/DE output
valid time
-
0.5
%
-
5
0
-
2.7<VDD<3.6 V
-
0.5
1.62<VDD<3.6 V
-
5
0
-
HSYNC/VSYNC/DE output hold time
MHz
90
DCLK
tv(DATA)
Unit
1. Guaranteed by characterization results.
DS12556 Rev 6
291/336
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 95. LCD-TFT horizontal timing diagram
tCLK
LCD_CLK
LCD_VSYNC
tv(HSYNC)
tv(HSYNC)
LCD_HSYNC
th(DE)
tv(DE)
LCD_DE
tv(DATA)
LCD_R[0:7]
LCD_G[0:7]
LCD_B[0:7]
Pixel Pixel
1
2
Pixel
N
th(DATA)
HSYNC Horizontal
width back porch
Active width
Horizontal
back porch
One line
MS32749V1
Figure 96. LCD-TFT vertical timing diagram
tCLK
LCD_CLK
tv(VSYNC)
tv(VSYNC)
LCD_VSYNC
LCD_R[0:7]
LCD_G[0:7]
LCD_B[0:7]
M lines data
VSYNC Vertical
width back porch
Active width
Vertical
back porch
One frame
MS32750V1
292/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
7.3.31
Electrical characteristics (rev V)
Timer characteristics
The parameters given in Table 199 are guaranteed by design.
Refer to Section 7.3.15: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 199. TIMx characteristics(1)(2)
Symbol
tres(TIM)
fEXT
ResTIM
tMAX_COUNT
Conditions(3)
Min
Max
Unit
AHB/APBx prescaler=1
or 2 or 4, fTIMxCLK =
240 MHz
1
-
tTIMxCLK
AHB/APBx
prescaler>4, fTIMxCLK =
120 MHz
1
-
tTIMxCLK
Timer external clock
frequency on CH1 to CH4 f
TIMxCLK = 240 MHz
0
fTIMxCLK/2
MHz
Timer resolution
-
16/32
bit
-
65536 ×
65536
tTIMxCLK
Parameter
Timer resolution time
Maximum possible count
with 32-bit counter
-
1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers.
2. Guaranteed by design.
3. The maximum timer frequency on APB1 or APB2 is up to 240 MHz, by setting the TIMPRE bit in the
RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x
Frcc_pclkx_d2.
7.3.32
Communication interfaces
I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual revision 03 for:
•
Standard-mode (Sm): with a bit rate up to 100 kbit/s
•
Fast-mode (Fm): with a bit rate up to 400 kbit/s
•
Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0399 reference manual) and when the i2c_ker_ck frequency is
greater than the minimum shown in the table below:
DS12556 Rev 6
293/336
311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 200. Minimum i2c_ker_ck frequency in all I2C modes
Symbol
Parameter
Condition
Standard-mode
Fast-mode
f(I2CCLK)
I2CCLK
frequency
Fast-mode Plus
Min
-
2
Analog Filtre ON
DNF=0
8
Analog Filtre OFF
DNF=1
9
Analog Filtre ON
DNF=0
17
Analog Filtre OFF
DNF=1
16
Unit
MHz
-
The SDA and SCL I/O requirements are met with the following restrictions:
•
The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain,
the PMOS connected between the I/O pin and VDDIOx is disabled, but still present.
•
The 20 mA output drive requirement in Fast-mode Plus is not supported. This limits the
maximum load CLoad supported in Fm+, which is given by these formulas:
tr(SDA/SCL)=0.8473xRPxCLoad
RP(min)= (VDD-VOL(max))/IOL(max)
Where RP is the I2C lines pull-up. Refer to Section 7.3.15: I/O port characteristics for
the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics:
Table 201. I2C analog filter characteristics(1)
Symbol
Parameter
Min
Max
Unit
tAF
Maximum pulse width of spikes
that are suppressed by analog
filter
50(2)
80(3)
ns
1. Guaranteed by characterization results.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered.
USART interface characteristics
Unless otherwise specified, the parameters given in Table 202 for USART are derived from
tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 120: General operating conditions, with the following
configuration:
294/336
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load CL = 30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
•
IO Compensation cell activated.
•
VOS level set to VOS1
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, CK, TX, RX for USART).
Table 202. USART characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
fCK
USART clock frequency
-
-
tsu(NSS)
NSS setup time
Slave mode
tker+1
-
-
th(NSS)
NSS hold time
Slave mode
2
-
-
tw(SCKH),
tw(SCKL)
CK high and low time
Master mode
1/fCK/2-2
1/fCK/2
1/fCK/2+2
tsu(RX)
Data input setup time
Master mode
tker+6
-
-
Slave mode
1.5
-
-
th(RX)
Data input hold time
Master mode
0
-
-
Slave mode
1.5
-
-
Slave mode
-
12
20
Master mode
-
0.5
1
Slave mode
9
-
-
Master mode
0
-
-
tv(TX)
Data output valid time
th(TX)
Data output hold time
Master mode
Slave mode
Max
12.5
25
Unit
MHz
-
ns
1. Guaranteed by characterization results.
Figure 97. USART timing diagram in Master mode
High
NSS input
SCK Output
CPHA=0
CPOL=0
CPHA=0
CPOL=1
SCK Output
tc(SCK)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tsu(RX)
RX
INPUT
tw(SCKH)
tw(SCKL)
MSB IN
tr(SCK)/tf(SCK)
BIT6 IN
LSB IN
th(RX)
TX
OUTPUT
MSB OUT
tv(TX)
BIT1 OUT
LSB OUT
th(TX)
MSv65386V1
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
DS12556 Rev 6
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 98. USART timing diagram in Slave mode
NSS
input
tc(SCK)
SCK input
tsu(NSS)
th(NSS)
tw(SCKH)
tr(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(TX)
tw(SCKL)
tv(TX)
First bit OUT
TX output
th(TX)
Next bits OUT
tf(SCK)
tdis(TX)
Last bit OUT
th(RX)
tsu(RX)
RX input
First bit IN
Next bits IN
Last bit IN
MSv65387V1
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 203 for SPI are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 120: General operating conditions, with the following
configuration:
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Capacitive load CL = 30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
•
IO Compensation cell activated.
•
HSLV activated when VDD ≤ 2.7 V
•
VOS level set to VOS1
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
296/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 203. SPI dynamic characteristics(1)
Symbol
fSCK
Parameter
SPI clock frequency
Conditions
Min
Typ
Max
Master mode
1.62<VDD<3.6 V
SPI1, 2, 3
80
Master mode
2.7<VDD<3.6 V
SPI1, 2, 3
100
Master mode
1.62<VDD<3.6 V
SPI4, 5, 6
-
-
50
Slave receiver mode
1.62<VDD<3.6 V
100
Slave mode transmitter/full duplex
2.7<VDD<3.6 V
31
Slave mode transmitter/full duplex
1.62 <VDD<3.6 V
29
tsu(NSS)
NSS setup time
Slave mode
2
-
-
th(NSS)
NSS hold time
Slave mode
1
-
-
tw(SCKH),
tw(SCKL)
SCK high and low time
Master mode
TPCLK-2
TPCLK
TPCLK+2
Master mode
2
-
-
Slave mode
1
-
-
Master mode
3
-
-
Slave mode
2
-
-
tsu(MI)
tsu(SI)
th(MI)
th(SI)
Data input setup time
Data input hold time
ta(SO)
Data output access time
Slave mode
9
13
27
tdis(SO)
Data output disable time
Slave mode
0
1
5
Slave mode
2.7<VDD<3.6 V
-
12.5
16
Slave mode
1.62<VDD<3.6 V
-
12.5
17
tv(MO)
Master mode
-
1
3
th(SO)
Slave mode
1.62<VDD<3.6 V
10
-
-
Master mode
0
-
-
tv(SO)
Data output valid time
Data output hold time
th(MO)
Unit
MHz
-
ns
1. Guaranteed by characterization results.
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 99. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
SCK input
tsu(NSS)
th(NSS)
tw(SCKH)
tr(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
tw(SCKL)
MISO output
tv(SO)
th(SO)
First bit OUT
tf(SCK)
Next bits OUT
tdis(SO)
Last bit OUT
th(SI)
tsu(SI)
MOSI input
First bit IN
Next bits IN
Last bit IN
MSv41658V1
Figure 100. SPI timing diagram - slave mode and CPHA = 1(1)
NSS input
tc(SCK)
tsu(NSS)
tw(SCKH)
ta(SO)
tw(SCKL)
tf(SCK)
th(NSS)
SCK input
CPHA=1
CPOL=0
CPHA=1
CPOL=1
MISO output
tv(SO)
First bit OUT
tsu(SI)
MOSI input
th(SO)
Next bits OUT
tr(SCK)
tdis(SO)
Last bit OUT
th(SI)
First bit IN
Next bits IN
Last bit IN
MSv41659V1
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
298/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Figure 101. SPI timing diagram - master mode(1)
High
NSS input
SCK Output
CPHA= 0
CPOL=0
SCK Output
tc(SCK)
CPHA=1
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=1
tsu(MI)
MISO
INP UT
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
BIT6 IN
MSB IN
LSB IN
th(MI)
MOSI
OUTPUT
B I T1 OUT
MSB OUT
tv(MO)
LSB OUT
th(MO)
ai14136c
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
I2S Interface characteristics
Unless otherwise specified, the parameters given in Table 204 for I2S are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 120: General operating conditions, with the following
configuration:
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load CL = 30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
•
IO Compensation cell activated.
•
HSLV activated when VDD ≤ 2.7 V
•
VOS level set to VOS1
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (CK,SD,WS).
DS12556 Rev 6
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 204. I2S dynamic characteristics(1)
Symbol
Parameter
Min
Max
Unit
fMCK
I2S main clock output
256x8K
256FS
MHz
fCK
I2S clock frequency
Master data
-
64FS
Slave data
-
64FS
tv(WS)
WS valid time
Master mode
-
3
th(WS)
WS hold time
Master mode
0
-
tsu(WS)
WS setup time
Slave mode
1
-
th(WS)
WS hold time
Slave mode
1
-
Master receiver
1
-
Slave receiver
1
-
Master receiver
4
-
Slave receiver
2
-
Slave transmitter (after enable
edge)
-
17
tv(SD_MT)
Master transmitter (after
enable edge)
-
3
th(SD_ST)
Slave transmitter (after enable
edge)
9
-
Master transmitter (after
enable edge)
0
-
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
Conditions
Data input setup time
Data input hold time
tv(SD_ST)
Data output valid time
Data output hold time
th(SD_MT)
-
MHz
1. Guaranteed by characterization results.
Figure 102. I2S slave timing diagram (Philips protocol)(1)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Figure 103. I2S master timing diagram (Philips protocol)(1)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
SAI characteristics
Unless otherwise specified, the parameters given in Table 205 for SAI are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 120: General operating conditions, with the following
configuration:
•
Output speed is set to OSPEEDRy[1:0] = 10
•
•
Capacitive load CL = 30 pF
IO Compensation cell activated.
•
Measurement points are done at CMOS levels: 0.5VDD
•
VOS level set to VOS1.
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output
alternate function characteristics (SCK,SD,WS).
Table 205. SAI characteristics(1)
Symbol
Parameter
Conditions
Min
Max
fMCK
SAI Main clock output
-
256x8K
256xFS
fCK
SAI clock
frequency(2)
Master Data: 32 bits
-
128xFS(3) MHz
Slave Data: 32 bits
-
128xFS(3)
DS12556 Rev 6
Unit
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 205. SAI characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Max
Master mode
2.7≤VDD≤3.6
-
13
Master mode
1.62≤VDD≤3.6
-
20
FS hold time
Master mode
8
-
FS setup time
Slave mode
1
-
FS hold time
Slave mode
1
-
Master receiver
0.5
-
Slave receiver
1
-
Master receiver
3.5
-
Slave receiver
2
-
Slave transmitter (after enable
edge)
2.7≤VDD≤3.6
-
14
Slave transmitter (after enable
edge)
1.62≤VDD≤3.6
-
20
Slave transmitter (after enable
edge)
9
-
Master transmitter (after enable
edge)
2.7≤VDD≤3.6
-
12
Master transmitter (after enable
edge)
1.62≤VDD≤3.6
-
19
Master transmitter (after enable
edge)
7.5
-
tv(FS)
FS valid time
tsu(FS)
th(FS)
tsu(SD_A_MR)
tsu(SD_B_SR)
th(SD_A_MR)
th(SD_B_SR)
tv(SD_B_ST)
th(SD_B_ST)
tv(SD_A_MT)
th(SD_A_MT)
Data input setup time
Data input hold time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
1. Guaranteed by characterization results.
2. APB clock frequency must be at least twice SAI clock frequency.
3. With FS=192 kHz.
302/336
DS12556 Rev 6
Unit
ns
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Figure 104. SAI master timing waveforms
1/fSCK
SAI_SCK_X
th(FS)
SAI_FS_X
(output)
tv(FS)
tv(SD_MT)
SAI_SD_X
(transmit)
th(SD_MT)
Slot n
tsu(SD_MR)
Slot n+2
th(SD_MR)
SAI_SD_X
(receive)
Slot n
MS32771V1
Figure 105. SAI slave timing waveforms
1/fSCK
SAI_SCK_X
tw(CKH_X)
SAI_FS_X
(input)
tw(CKL_X)
th(FS)
tsu(FS)
tv(SD_ST)
SAI_SD_X
(transmit)
th(SD_ST)
Slot n
tsu(SD_SR)
SAI_SD_X
(receive)
Slot n+2
th(SD_SR)
Slot n
MS32772V1
MDIO characteristics
Table 206. MDIO Slave timing parameters
Symbol
Parameter
Min
Typ
Max
Unit
FMDC
Management Data Clock
-
-
30
MHz
td(MDIO)
Management Data Iput/output output valid time
8
10
19
tsu(MDIO)
Management Data Iput/output setup time
1
-
-
th(MDIO)
Management Data Iput/output hold time
1
-
-
DS12556 Rev 6
ns
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 106. MDIO Slave timing diagram
tMDC)
td(MDIO)
tsu(MDIO)
th(MDIO)
MSv40460V1
SD/SDIO MMC card host interface (SDMMC) characteristics
Unless otherwise specified, the parameters given in Table 207 and Table 208 for SDIO are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage summarized in Table 120: General operating conditions, with the following
configuration:
•
Output speed is set to OSPEEDRy[1:0] = 0x11
•
Capacitive load CL=30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
•
IO Compensation cell activated.
•
HSLV activated when VDD ≤ 2.7 V
•
VOS level set to VOS1
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output
characteristics.
Table 207. Dynamics characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V(1)(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
Clock frequency in data transfer mode
-
0
-
133
MHz
-
SDIO_CK/fPCLK2 frequency ratio
-
-
-
8/3
-
tW(CKL)
Clock low time
fPP =52MHz
8.5
9.5
-
tW(CKH)
Clock high time
fPP =52MHz
8.5
9.5
-
ns
CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(3)/DDR(3) mode
tISU
Input setup time HS
-
2.5
-
-
tIH
Input hold time HS
-
0.5
-
-
tIDW(4)
Input valid window (variable window)
-
3
-
-
ns
-
CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR/DDR(3) mode
tOV
Output valid time HS
-
-
3.5
5
tOH
Output hold time HS
-
2
-
-
304/336
DS12556 Rev 6
ns
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 207. Dynamics characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V(1)(2) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CMD, D inputs (referenced to CK) in SD default mode
tISUD
Input setup time SD
-
2.5
-
tIHD
Input hold time SD
-
0.5
-
ns
CMD, D outputs (referenced to CK) in SD default mode
tOVD
Output valid default time SD
-
-
0.5
2
tOHD
Output hold default time SD
-
0
-
-
ns
1. Guaranteed by characterization results.
2. Above 100 MHz, CL = 20 pF.
3. An external voltage converter is required to support SD 1.8 V.
4. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.
Table 208. Dynamics characteristics: eMMC characteristics VDD = 1.71V to 1.9V(1)(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
Clock frequency in data transfer
mode
-
0
-
120
MHz
-
SDIO_CK/fPCLK2 frequency ratio
-
-
-
8/3
-
tW(CKL)
Clock low time
fPP =52 MHz
8.5
9.5
-
tW(CKH)
Clock high time
fPP =52 MHz
8.5
9.5
-
ns
CMD, D inputs (referenced to CK) in eMMC mode
tISU
Input setup time HS
-
2
-
-
tIH
Input hold time HS
-
1.5
-
-
tIDW(3)
Input valid window (variable
window)
-
3.5
-
-
ns
CMD, D outputs (referenced to CK) in eMMC mode
tOVD
Output valid time HS
-
-
5
7
tOHD
Output hold time HS
-
3
-
-
ns
1. Guaranteed by characterization results.
2. CL = 20 pF.
3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.
DS12556 Rev 6
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 107. SDIO high-speed mode
Figure 108. SD default mode
CK
tOVD
tOHD
D, CMD
(output)
ai14888
Figure 109. DDR mode
tr(CLK)
t(CLK)
tw(CLKH)
tw(CLKL)
tf(CLK)
Clock
tvf(OUT)
Data output
thr(OUT)
IO0
tvr(OUT)
IO1
IO2
thf(OUT)
IO3
tsf(IN) thf(IN)
Data input
IO0
IO1
IO4
IO5
tsr(IN) thr(IN)
IO2
IO3
IO4
IO5
MSv36879V3
306/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
USB OTG_HS characteristics
Unless otherwise specified, the parameters given in Table 209 for ULPI are derived from
tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
summarized in Table 120: General operating conditions, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Capacitive load CL=20 pF
•
Measurement points are done at CMOS levels: 0.5VDD
•
IO Compensation cell activated.
•
VOS level set to VOS1
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output
characteristics.
Table 209. Dynamics characteristics: USB ULPI(1)
Symbol
Parameter
Condition
Min
Typ
Max
tSC
Control in (ULPI_DIR , ULPI_NXT) setup
time
-
2.5
-
-
tHC
Control in (ULPI_DIR, ULPI_NXT) hold
time
-
2
-
-
tSD
Data in setup time
-
2.5
-
-
tHD
Data in hold time
-
0
-
-
2.7<VDD<3.6 V
CL=20 pF
-
9
9.5
1.71<VDD<3.6 V
CL=15 pF
-
9
14
tDC/tDD
Control/Datal output delay
Unit
ns
1. Guaranteed by characterization results.
Figure 110. ULPI timing diagram
Clock
Control In
(ULPI_DIR,
ULPI_NXT)
tSC
tHC
tSD
tHD
data In
(8-bit)
tDC
Control out
(ULPI_STP)
tDC
tDD
data out
(8-bit)
ai17361c
DS12556 Rev 6
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Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Ethernet interface characteristics
Unless otherwise specified, the parameters given in Table 210, Table 211 and Table 212 for
SMI, RMII and MII are derived from tests performed under the ambient temperature,
frcc_c_ck frequency and VDD supply voltage conditions summarized in Table 120: General
operating conditions, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load CL=20 pF
•
Measurement points are done at CMOS levels: 0.5VDD
•
IO Compensation cell activated.
•
HSLV activated when VDD ≤ 2.7 V
•
VOS level set to VOS1
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output
characteristics:
Table 210. Dynamics characteristics: Ethernet MAC signals for SMI (1)
Symbol
Parameter
Min
Typ
Max
tMDC
MDC cycle time( 2.5 MHz)
400
400
403
Td(MDIO)
Write data valid time
0.5
1.5
4
tsu(MDIO)
Read data setup time
12.5
-
-
th(MDIO)
Read data hold time
0
-
-
Unit
ns
1. Guaranteed by characterization results.
Figure 111. Ethernet SMI timing diagram
tMDC
ETH_MDC
td(MDIO)
ETH_MDIO(O)
tsu(MDIO)
th(MDIO)
ETH_MDIO(I)
MS31384V1
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DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 211. Dynamics characteristics: Ethernet MAC signals for RMII (1)
Symbol
Parameter
Min
Typ
Max
tsu(RXD)
Receive data setup time
2
-
-
tih(RXD)
Receive data hold time
2
-
-
tsu(CRS)
Carrier sense setup time
1.5
-
-
tih(CRS)
Carrier sense hold time
1.5
-
-
td(TXEN)
Transmit enable valid delay time
7
8
9.5
td(TXD)
Transmit data valid delay time
8
9
11
Unit
ns
1. Guaranteed by characterization results.
Figure 112. Ethernet RMII timing diagram
RMII_REF_CLK
td(TXEN)
td(TXD)
RMII_TX_EN
RMII_TXD[1:0]
tih(RXD)
tih(CRS)
tsu(RXD)
tsu(CRS)
RMII_RXD[1:0]
RMII_CRS_DV
ai15667b
Table 212. Dynamics characteristics: Ethernet MAC signals for MII (1)
Symbol
Parameter
Min
Typ
Max
tsu(RXD)
Receive data setup time
2
-
-
tih(RXD)
Receive data hold time
2
-
-
tsu(DV)
Data valid setup time
1.5
-
-
tih(DV)
Data valid hold time
1.5
-
-
tsu(ER)
Error setup time
1.5
-
-
tih(ER)
Error hold time
0.5
-
-
td(TXEN)
Transmit enable valid delay time
9
10
11
td(TXD)
Transmit data valid delay time
8.5
9.5
12.5
Unit
ns
1. Guaranteed by characterization results.
DS12556 Rev 6
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311
Electrical characteristics (rev V)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Figure 113. Ethernet MII timing diagram
MII_RX_CLK
tsu(RXD)
tsu(ER)
tsu(DV)
tih(RXD)
tih(ER)
tih(DV)
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
MII_TX_CLK
td(TXEN)
td(TXD)
MII_TX_EN
MII_TXD[3:0]
ai15668b
JTAG/SWD interface characteristics
Unless otherwise specified, the parameters given in Table 213 and Table 214 for
JTAG/SWD are derived from tests performed under the ambient temperature, frcc_c_ck
frequency and VDD supply voltage summarized in Table 120: General operating conditions,
with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 0x10
•
Capacitive load CL=30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
•
VOS level set to VOS1
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output
characteristics:
Table 213. Dynamics JTAG characteristics
Symbol
Fpp
1/tc(TCK)
310/336
Parameter
TCK clock frequency
Conditions
Min
Typ
Max
2.7V <VDD< 3.6 V
-
-
37
1.62 <VDD< 3.6 V
-
-
27.5
Unit
MHz
tisu(TMS)
TMS input setup time
-
2.5
-
-
tih(TMS)
TMS input hold time
-
1
-
-
tisu(TDI)
TDI input setup time
-
1.5
-
-
-
tih(TDI)
TDI input hold time
-
1
-
-
-
tov(TDO)
TDO output valid time
2.7V <VDD< 3.6 V
-
8
13.5
-
1.62 <VDD< 3.6 V
-
8
18
-
toh(TDO)
TDO output hold time
-
7
-
-
-
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev V)
Table 214. Dynamics SWD characteristics:
Symbol
Fpp
1/tc(SWCLK)
Parameter
SWCLK clock frequency
Conditions
Min
Typ
Max
2.7V <VDD< 3.6 V
-
-
71
1.62 <VDD< 3.6 V
-
-
52.5
tisu(SWDIO)
SWDIO input setup time
-
2.5
-
-
tih(SWDIO)
SWDIO input hold time
-
1
-
-
2.7V <VDD< 3.6 V
-
8.5
14
-
8.5
19
8
-
-
tov(SWDIO)
SWDIO output valid time
1.62 <VDD< 3.6 V
toh(SWDIO)
SWDIO output hold time
-
Unit
MHz
ns
Figure 114. JTAG timing diagram
tc(TCK)
TCK
tsu(TMS/TDI)
th(TMS/TDI)
tw(TCKL) tw(TCKH)
TDI/TMS
tov(TDO)
toh(TDO)
TDO
MSv40458V1
Figure 115. SWD timing diagram
tc(SWCLK)
SWCLK
tsu(SWDIO)
th(SWDIO)
twSWCLKL) tw(SWCLKH)
SWDIO
(receive)
tov(SWDIO)
toh(SWDIO)
SWDIO
(transmit)
MSv40459V1
DS12556 Rev 6
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8
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at www.st.com. ECOPACK
is an ST trademark.
LQFP100 package information
LQFP100 is a 100-pin, 14 x 14 mm low-profile quad flat package.
Figure 116. LQFP100 package outline
0.25 mm
c
A1
A
SEATING PLANE
C
A2
GAUGE PLANE
D
L
D1
A1
K
ccc C
L1
D3
51
75
76
50
100
26
PIN 1
1
IDENTIFICATION
E
E3
E1
b
8.1
25
e
1L_ME_V5
1. Drawing is not to scale.
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Package information
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 215. LQPF100 package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
15.800
16.000
16.200
0.6220
0.6299
0.6378
D1
13.800
14.000
14.200
0.5433
0.5512
0.5591
D3
-
12.000
-
-
0.4724
-
E
15.800
16.000
16.200
0.6220
0.6299
0.6378
E1
13.800
14.000
14.200
0.5433
0.5512
0.5591
E3
-
12.000
-
-
0.4724
-
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0.0°
3.5°
7.0°
0.0°
3.5°
7.0°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
312/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Package information
Figure 117. LQFP100 recommended footprint
75
76
51
50
0.5
0.3
16.7 14.3
100
26
1.2
1
25
12.3
16.7
ai14906c
1. Dimensions are expressed in millimeters.
DS12556 Rev 6
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331
Package information
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Device marking for LQFP100
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 118. LQFP100 marking example (package top view)
Product identification(1)
STM32H750
VBT6
R
Revision code
Date code
Y WW
Pin 1
indentifier
MSv62430V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
314/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
LQFP144 package information
LQFP144 is a 144-pin, 20 x 20 mm low-profile quad flat package.
Figure 119. LQFP144 package outline
SEATING
PLANE
c
A1
A2
C
A
0.25 mm
GAUGE PLANE
D
L
D1
K
A1
ccc C
L1
D3
108
73
109
72
E
37
144
PIN 1
E1
E3
b
8.2
Package information
1
36
IDENTIFICATION
e
1A_ME_V4
1. Drawing is not to scale.
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331
Package information
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 216. LQFP144 package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
21.800
22.000
22.200
0.8583
0.8661
0.8740
D1
19.800
20.000
20.200
0.7795
0.7874
0.7953
D3
-
17.500
-
-
0.6890
-
E
21.800
22.000
22.200
0.8583
0.8661
0.8740
E1
19.800
20.000
20.200
0.7795
0.7874
0.7953
E3
-
17.500
-
-
0.6890
-
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0°
3.5°
7°
0°
3.5°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
316/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Package information
Figure 120. LQFP144 package recommended footprint
108
109
73
1.35
72
0.35
0.5
19.9
17.85
22.6
144
37
1
36
19.9
22.6
ai14905e
1. Dimensions are expressed in millimeters.
DS12556 Rev 6
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331
Package information
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Device marking for LQFP144
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 121. LQFP144 marking example (package top view)
Revision code
R
Product identification(1)
STM32H750ZBT6
Date code
Y WW
Pin 1 identifier
MSv63961V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
318/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
8.3
Package information
LQFP176 package information
LQFP176 is a 176-pin, 24 x 24 mm low profile quad flat package.
Figure 122. LQFP176 package outline
c
A1
A2
A
C Seating plane
0.25 mm
gauge plane
k
A1
L
HD
PIN 1
IDENTIFICATION
L1
D
ZE
E
HE
e
ZD
b
1T_ME_V2
1. Drawing is not to scale.
Table 217. LQFP176 package mechanical data
Dimensions
Ref.
Inches(1)
Millimeters
Min.
Typ.
Max.
Min.
Typ.
Max.
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
-
1.450
0.0531
-
0.0571
b
0.170
-
0.270
0.0067
-
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
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Package information
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 217. LQFP176 package mechanical data (continued)
Dimensions
Ref.
Inches(1)
Millimeters
Min.
Typ.
Max.
Min.
Typ.
Max.
D
23.900
-
24.100
0.9409
-
0.9488
HD
25.900
-
26.100
1.0197
-
1.0276
ZD
-
1.250
-
-
0.0492
-
E
23.900
-
24.100
0.9409
-
0.9488
HE
25.900
-
26.100
1.0197
-
1.0276
ZE
-
1.250
-
-
0.0492
-
e
-
0.500
-
-
0.0197
-
L(2)
0.450
-
0.750
0.0177
-
0.0295
L1
-
1.000
-
-
0.0394
-
k
0°
-
7°
0°
-
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. L dimension is measured at gauge plane at 0.25 mm above the seating plane.
320/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Package information
Figure 123. LQFP176 package recommended footprint
1.2
1
176
133
132
0.5
21.8
26.7
0.3
44
45
89
88
1.2
21.8
26.7
1T_FP_V1
1. Dimensions are expressed in millimeters.
DS12556 Rev 6
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331
Package information
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Device marking for LQFP176
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 124. LQFP176 marking example (package top view)
Product identification(1)
STM32H750IBT6
Y WW
Revision code
Date code
R
Pin 1identifier
MSv63962V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
322/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
8.4
Package information
UFBGA176+25 package information
UFBGA176+25 is a 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array
package.
Figure 125. UFBGA176+25 package outline
C
Seating plane
A4
ddd C
A3
A2
A1
b
e
A
A1 ball
identifier
E1
A1 ball
index
area
A
E
Z
A
Z
D1
D
e
B
R
15
1
BOTTOM VIEW
Øb (176 + 25 balls)
TOP VIEW
Ø eee M C A B
Ø fff M C
A0E7_ME_V8
1. Drawing is not to scale.
Table 218. UFBGA176+25 package mechanical data
inches(1)
millimeters
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
A
-
-
0.600
-
-
0.0236
A1
-
-
0.110
-
-
0.0043
A2
-
0.130
-
-
0.0051
-
A3
-
0.450
-
-
0.0177
-
A4
-
0.320
-
-
0.0126
-
b
0.240
0.290
0.340
0.0094
0.0114
0.0134
D
9.850
10.000
10.150
0.3878
0.3937
0.3996
D1
-
9.100
-
-
0.3583
-
E
9.850
10.000
10.150
0.3878
0.3937
0.3996
E1
-
9.100
-
-
0.3583
-
e
-
0.650
-
-
0.0256
-
Z
-
0.450
-
-
0.0177
-
ddd
-
-
0.080
-
-
0.0031
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Package information
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 218. UFBGA176+25 package mechanical data (continued)
inches(1)
millimeters
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
eee
-
-
0.150
-
-
0.0059
fff
-
-
0.050
-
-
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 126. UFBGA176+25 package recommended footprint
Dpad
Dsm
A0E7_FP_V1
Table 219. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA)
Dimension
324/336
Recommended values
Pitch
0.65 mm
Dpad
0.300 mm
Dsm
0.400 mm typ. (depends on the soldermask
registration tolerance)
Stencil opening
0.300 mm
Stencil thickness
Between 0.100 mm and 0.125 mm
Pad trace width
0.100 mm
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Package information
Device marking for UFBGA176+25
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 127. UFBGA176+25 marking example (package top view)
Revision code
R
Product identification(1)
STM32H750
IBK6
Date code
Y WW
Ball A1
identifier
MSv62431V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
DS12556 Rev 6
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331
Package information
8.5
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
TFBGA240+25 package information
TFBGA240+25 is a 265 ball, 14x14 mm, 0.8 mm pitch, fine pitch ball grid array
package.
ddd C
Figure 128. TFBGA240+25 package outline
A1
A
C
A2
SEATING
PLANE
A1 ball identifier
D1
D
e
E1
E
G
A
e
U
1
17
F
BOTTOM VIEW
b (240 + 25 balls)
TOP VIEW
A07U_ME_V2
1. Dimensions are expressed in millimeters.
326/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Package information
Table 220. TFBG240+25 ball package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.100
-
-
0.0433
A1
0.150
-
-
0.0059
-
-
A2
-
0.760
-
-
0.0299
-
b
0.350
0.400
0.450
0.0138
0.0157
0.0177
D
13.850
14.000
14.150
0.5453
0.5512
0.5571
D1
-
12.800
-
-
0.5039
-
E
13.850
14.000
14.150
0.5453
0.5512
0.5571
E1
-
12.800
-
-
0.5039
-
e
-
0.800
-
-
0.0315
-
F
-
0.600
-
-
0.0236
-
G
-
0.600
-
-
0.0236
-
ddd
-
-
0.100
-
-
0.0039
eee
-
-
0.150
-
-
0.0059
fff
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 129. TFBGA240+25 package recommended footprint
Dpad
Dsm
A07U_FP_V2
1. Dimensions are expressed in millimeters.
DS12556 Rev 6
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Package information
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 221. TFBGA240+25 recommended PCB design rules (0.8 mm pitch)
Dimension
Recommended values
Pitch
0.8 mm
Dpad
0.225 mm
Dsm
0.290 mm typ. (depends on the soldermask
registration tolerance)
Stencil opening
0.250 mm
Stencil thickness
0.100 mm
Device marking for TFBGA240+25
The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 130. TFBGA240+25 marking example (package top view)
Product
identification(1)
STM32H750
Revision code
XBH6
R
Date code
Ball
A1identifier
Y
WW
MSv62432V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
328/336
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
8.6
Package information
Thermal characteristics
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max × ΘJA)
Where:
•
TA max is the maximum ambient temperature in °C,
•
ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
•
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
•
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 222. Thermal characteristics
Symbol
ΘJA
ΘJB
Definition
Thermal resistance
junction-ambient
Thermal resistance
junction-board
Parameter
Value
Thermal resistance junction-ambient
LQFP100 - 14 x 14 mm /0.5 mm pitch
45.0
Thermal resistance junction-ambient
LQFP144 - 20 x 20 mm /0.5 mm pitch
43.7
Thermal resistance junction-ambient
LQFP176 - 24 x 24 mm /0.5 mm pitch
43.0
Thermal resistance junction-ambient
UFBGA176+25 - 10 x 10 mm /0.65 mm pitch
37.4
Thermal resistance junction-ambient
TFBGA240+25 - 14 x 14 mm / 0.8 mm pitch
36.6
Thermal resistance junction-ambient
LQFP100 - 14 x 14 mm /0.5 mm pitch
36.3
Thermal resistance junction-ambient
LQFP144 - 20 x 20 mm /0.5 mm pitch
38.3
Thermal resistance junction-ambient
LQFP176 - 24 x 24 mm /0.5 mm pitch
43.0
Thermal resistance junction-ambient
UFBGA176+25 - 10 x 10 mm /0.65 mm pitch
19.3
Thermal resistance junction-ambient
TFBGA240+25 - 14 x 14 mm / 0.8 mm pitch
24.3
DS12556 Rev 6
Unit
°C/W
°C/W
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Package information
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 222. Thermal characteristics
Symbol
ΘJC
8.6.1
330/336
Definition
Thermal resistance
junction-case
Parameter
Value
Thermal resistance junction-ambient
LQFP100 - 14 x 14 mm /0.5 mm pitch
11.5
Thermal resistance junction-ambient
LQFP144 - 20 x 20 mm /0.5 mm pitch
11.3
Thermal resistance junction-ambient
LQFP176 - 24 x 24 mm /0.5 mm pitch
11.2
Thermal resistance junction-ambient
UFBGA176+25 - 10 x 10 mm /0.65 mm pitch
23.9
Thermal resistance junction-ambient
TFBGA240+25 - 14 x 14 mm / 0.8 mm pitch
7.4
Unit
°C/W
Reference documents
•
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
•
For information on thermal management, refer to application note “Thermal
management guidelines for STM32 32-bit Arm Cortex MCUs applications” (AN5036)
available from www.st.com.
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
9
Ordering information
Ordering information
Example:
STM32 H
750
X
B
T
6
TR(1)
Device family
STM32 = Arm-based 32-bit microcontroller
Product type
H = High performance
Device subfamily
750 = STM32H750 value line with cryptographic
accelerator
Pin count
V = 100 pins
Z = 144 pins
I = 176 pins/balls
X = 240 balls
Flash memory size
B = 128 Kbytes
Package
T = LQFP ECOPACK2
K = UFBGA pitch 0.65 mm ECOPACK2
H = TFBGA ECOPACK2
Temperature range
6 = –40 to 85 °C
Packing
TR = tape and reel
No character = tray or tube
1. The tape and reel packing is not available on all packages.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
DS12556 Rev 6
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331
Revision history
10
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Revision history
Table 223. Document revision history
Date
Revision
21-May2018
1
Initial release.
2
Changed datasheet status to “production data”.
Added description of power-up and power-down phases in Section 3.5.1: Power supply
scheme.
Updated Table 44: HSI48 oscillator characteristics, Table 45: HSI oscillator
characteristics and Table 46: CSI oscillator characteristics.
Renamed Table 48 into “PLL characteristics (wide VCO frequency range)” and updated
note 2.. Added Table 49: PLL characteristics (medium VCO frequency range). Updated
tS_vbat in Table 92: VBAT monitoring characteristics.
Updated Table 97: OPAMP characteristics.
29-Jun-2018
05-Apr-2019
3
Changes
Changed maximum Arm Core-M7 frequency to 480 MHz.
Features:
– Changed operational amplifier bandwidth to 7.3 MHz
– Updated high-resolution timer to 2.1 ns
– Updated low-power consumption feature
Updated voltage scaling in Section 3.5.1: Power supply scheme. Added VOS0 in
Section 3.5.3: Voltage regulator.
Updated HSE clock in Section 3.7.1: Clock management.
Removed ETH_TX_ER from Table 7: STM32H750xB pin/ball definition.
Updated Section 6: Electrical characteristics (rev Y):
– Added note related to decoupling capacitor tolerance below Figure 11: Power supply
scheme.
– Added note 2. related to CEXT in Table 23: VCAP operating conditions.
– Updated note 2 below Figure 19: Recommended NRST pin protection.
– Updated fHSI48 in Table 44: HSI48 oscillator characteristics.
– Updated tstab in Table 45: HSI oscillator characteristics.
– Removed note 2 in Table 49: PLL characteristics (medium VCO frequency range).
– Added Table 60: Output voltage characteristics for PC13, PC14, PC15 and PI8.
– Added note related to PC13, PC14, PC15 an PI8 limited frequency in Table 61:
Output timing characteristics (HSLV OFF).
– Updated Tcoeff in Table 89: VREFBUF characteristics.
– Table 85: ADC characteristics: updated fS and added note related to fS formula;
updated tCAL.
– Renamed Section 6.3.24 into Temperature and VBAT monitoring and content
updated.
– Updated fDFSDMCLK in Table 98: DFSDM measured timing - 1.62-3.6 V.
Added Section 7: Electrical characteristics (rev V).
Updated paragraph introducing all package marking schematics to add the new
sentence “The printed markings may differ depending on the supply chain”. Updated
Table 222: Thermal characteristics. Added note related to ECOPACK®2 compliance in
Section 9: Ordering information.
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Revision history
Table 223. Document revision history
Date
24-Apr-2019
22-Nov2019
Revision
Changes
4
Updated Figure 1: STM32H750xB block diagram
Updated Table 7: STM32H750xB pin/ball definition.
Updated Table 8 to Table 18 (alternate functions).
Updated Table 37: Peripheral current consumption in Run mode.
Updated Table 135: Peripheral current consumption in Run mode.
Updated Table 182: ADC characteristics.
Updated Table 183: Minimum sampling time vs RAIN.
Updated Table 184: ADC accuracy.
Added device marking examples for all packages in Section 8: Package information
5
Added LQFP144 package together with STM32H750ZB part number, and LQFP176
package.
In Table 1: STM32H750xB features and peripheral counts, split number of ADC
channels into Direct, Fast and Slow channels; and added number of wakeup and
tamper pins.
Moved LSI from Backup to VDD domain in Figure 11 and Figure 64.
Updated capacitor value for 1.62 V<DD<1.8 V and FMC_CLK =100 MHz in Section :
SDRAM waveforms and timings.
Updated Section 6.2 and Section 7.2 introduction to device mission profile.
Power dissipation (PD) removed from Tables General operating conditions since this
parameter is redundant with ΘJA thermal resistance.
Updated maximum frequency for condition “All peripherals disabled and VOS2”
Table 128: Typical and maximum current consumption in Run mode, code with data
processing running from Flash memory, cache ON, LDO regulator ON
Updated condition related to frcc_c_ck in Section : On-chip peripheral current
consumption.
Updated Table 179: QUADSPI characteristics in SDR mode, Figure 35: Quad-SPI
timing diagram - DDR mode and Figure 87: Quad-SPI timing diagram - DDR mode.
Updated fDFSDMCLK maximum value in Table 98: DFSDM measured timing - 1.62-3.6 V
and Table 196: DFSDM measured timing - 1.62-3.6 V.
Updated notes 4. and 5. in Table 183: Minimum sampling time vs RAIN.
Updated Figure 128: TFBGA240+25 package outline.
Added note related to the availability of tape and reel packing in Section 9: Ordering
information.
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Revision history
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Table 223. Document revision history
Date
Revision
Changes
Added indication that patents apply to the devices in Features.
Added connection between SDMMC2 and D2-to-D3 AHB bus in Figure 3:
STM32H750xB bus matrix. Updated Section 3.27: True random number generator
(RNG).
Added Full-duplex mode in Section 3.34: Serial peripheral interfaces (SPI)/integrated
interchip sound interfaces (I2S).
Updated J1 and F2 signals in Figure 8: TFBGA240+25 ballout.
05-Feb2021
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6
Section 6: Electrical characteristics (rev Y):
– Added a 1 μF capacitor between VDD33USB and ground in Figure 11: Power supply
scheme.
– Table 51: Flash memory programming: removed reference to single bank
configuration in title and added tERASE128KB typical and maximum values.
– Added reference to AN4899 in Section 6.3.15: I/O port characteristics. Updated notes
in Table 62: Output timing characteristics (HSLV ON).
– Updated tsu(DV-CLKH)/th(DV-CLKH) and tsu(NWAIT-CLKH)/th(NWAIT-CLKH) in Table 72:
Synchronous multiplexed NOR/PSRAM read timings. Changed t(NWAIT-CLKH) to
tsu(NWAIT-CLKH) and updated tsu(DV-CLKH)/th(DV-CLKH) and tsu(NWAIT-CLKH)/th(NWAIT-CLKH)
in Table 74: Synchronous non-multiplexed NOR/PSRAM read timings. Updated
tsu(SDCLKH _Data) and th(SDCLKH _Data) in Table 78: SDRAM read timings and Table 79:
LPSDR SDRAM read timings.
– Updated ts(IN) and th(IN) in Table 82: QUADSPI characteristics in SDR mode and
tsr(IN)/tsf(IN) and thr(IN)/thf(IN) in Table 83: QUADSPI characteristics in DDR mode.
– Updated maximum sampling time (tS) value in Table 85: ADC characteristics.
Specified that Figure 36: ADC accuracy characteristics (example for 12-bit resolution)
is an example for 12-bit resolution.
– Updated tsu(MI) and th(MI) minimum values in Table 104: SPI dynamic characteristics.
– Updated tISU, tIH, tISUDand tIHD in Table 108: Dynamic characteristics: SD / MMC
characteristics, VDD = 2.7 to 3.6 V. Updated tISU, tIH in Table 109: Dynamic
characteristics: eMMC characteristics, VDD = 1.71 to 1.9 V.
– Updated DuCyCKOUT in Table 98: DFSDM measured timing - 1.62-3.6 V.
DS12556 Rev 6
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Revision history
Table 223. Document revision history
Date
05-Feb2021
Revision
Changes
Section 7: Electrical characteristics (rev V):
– Added a 1 μF capacitor between VDD33USB and ground in Figure 64: Power supply
scheme.
– Replaced Min VDD by Min VDDLDO in Table 121: Supply voltage and maximum
frequency configuration.
– Table 148: Flash memory programming: removed reference to single bank
configuration in title and added tERASE128KB typical and maximum values.
– Added reference to AN4899 in Section 7.3.15: I/O port characteristics. Changed
capacitance value for speed 10 and tr/tf, and speed for 11 and tr/tf/Fmax Table 159:
Output timing characteristics (HSLV ON).
– Updated tsu(DV-CLKH)/th(DV-CLKH) and tsu(NWAIT-CLKH)/th(NWAIT-CLKH) in Table 169:
Synchronous multiplexed NOR/PSRAM read timings. Changed t(NWAIT-CLKH) to
tsu(NWAIT-CLKH) and updated tsu(DV-CLKH)/th(DV-CLKH) and tsu(NWAIT-CLKH)/th(NWAIT-CLKH)
in Table 171: Synchronous non-multiplexed NOR/PSRAM read timings. Updated
tsu(SDCLKH _Data) and th(SDCLKH _Data) in Table 175: SDRAM read timings and
6
Table 176: LPSDR SDRAM read timings.
(continued)
– Updated ts(IN) and th(IN) in Table 179: QUADSPI characteristics in SDR mode and
tsr(IN)/tsf(IN) and thr(IN)/thf(IN) in Table 180: QUADSPI characteristics in DDR mode.
– Added reference to AN5354 application note in note of Table 182: ADC
characteristics. Specified that Figure 36: ADC accuracy characteristics (example for
12-bit resolution) is an example for 12-bit resolution.
– Changed temperature condition to 130 °C for TS_CAL2 in Table 189: Temperature
sensor calibration values.
– Updated DuCyCKOUT in Table 196: DFSDM measured timing - 1.62-3.6 V.
– Updated Figure 97: USART timing diagram in Master mode and Figure 98: USART
timing diagram in Slave mode.
– Updated tsu(MI) and th(MI) in Table 203: SPI dynamic characteristics.
– Updated tISU, tIH, tISUDand tIHD in Table 207: Dynamics characteristics: SD / MMC
characteristics, VDD = 2.7 to 3.6 V. Updated tISU, tIH in Table 208: Dynamics
characteristics: eMMC characteristics VDD = 1.71V to 1.9V.
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