STMicroelectronics STM32H7B0VB Datasheet

STM32H7B0xB

Datasheet

32-bit Arm

®

Cortex

®

-M7 280 MHz MCUs, 128-Kbyte Flash memory, 1.4-Mbyte

RAM, 46 com. and analog interfaces, SMPS, crypto

FBGA

LQFP64

(10 x 10 mm)

LQFP100

(14 x 14 mm)

LQFP144

(20x20 mm)

LQFP176

(24 x 24 mm)

UFBGA169

(7 x 7 mm)

UFBGA176+25

(10x10 mm)

Product summary

STM32H7B0xB

STM32H7B0AB ,

STM32H7B0IB ,

STM32H7B0RB ,

STM32H7B0ZB ,

STM32H7B0VB

Features

Includes ST state-of-the-art patented technology

Core

• 32-bit Arm ® Cortex ® -M7 core with double-precision FPU and L1 cache:

16 Kbytes of data and 16 Kbytes of instruction cache allowing to fill one cache line in a single access from the 128-bit embedded Flash memory; frequency up to 280 MHz, MPU, 599 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions

Memories

• 128 Kbytes of Flash memory plus 1 Kbyte of OTP memory

• ~1.4 Mbytes of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM +

128 Kbytes of DTCM RAM for time critical routines), 1.18 Mbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain

• 2x Octo-SPI memory interfaces with on-the-fly decryption, I/O multiplexing and support for serial PSRAM/NOR, Hyper RAM/Flash frame formats, running up to

140 MHz in SRD mode and up to 110 MHz in DTR mode

• Flexible external memory controller with up to 32-bit data bus:

– SRAM, PSRAM, NOR Flash memory clocked up to 125 MHz in

Synchronous mode

– SDRAM/LPSDR SDRAM

– 8/16-bit NAND Flash memories

• CRC calculation unit

Security

• ROP, PC-ROP, active tamper, secure firmware upgrade support, Secure access mode

General-purpose input/outputs

• Up to 138 I/O ports with interrupt capability

– Fast I/Os capable of up to 133 MHz

– Up to 164 5-V-tolerant I/Os

Low-power consumption

• Stop: down to 32 µA with full RAM retention

• Standby: 2.8 µA (Backup SRAM OFF, RTC/LSE ON, PDR OFF)

• V

BAT

: 0.8 µA (RTC and LSE ON)

Clock management

• Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI

• External oscillators: 4-50 MHz HSE, 32.768 kHz LSE

• 3× PLLs (1 for the system clock, 2 for kernel clocks) with fractional mode

DS13196 - Rev 6 - May 2021

For further information contact your local STMicroelectronics sales office.

www.st.com

DS13196 - Rev 6

STM32H7B0xB

Reset and power management

• 2 separate power domains, which can be independently clock gated to maximize power efficiency:

– CPU domain (CD) for Arm ® Cortex ® core and its peripherals, which can be independently switched in Retention mode

– Smart run domain (SRD) for reset and clock control, power management and some peripherals

• 1.62 to 3.6 V application supply and I/Os

• POR, PDR, PVD and BOR

• Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs

• Dedicated SDMMC power supply

• High power efficiency SMPS step-down converter regulator to directly supply

V

CORE

or an external circuitry

• Embedded regulator (LDO) with configurable scalable output to supply the digital circuitry

• Voltage scaling in Run and Stop mode

• Backup regulator (~0.9 V)

• Low-power modes: Sleep, Stop and Standby

• V

BAT

battery operating mode with charging capability

• CPU and domain power state monitoring pins

Interconnect matrix

• 3 bus matrices (1 AXI and 2 AHB)

• Bridges (5× AHB2APB, 3× AXI2AHB)

5 DMA controllers to unload the CPU

• 1× high-speed general-purpose master direct memory access controller

(MDMA)

• 2× dual-port DMAs with FIFO and request router capabilities

• 1× basic DMA with request router capabilities

• 1x basic DMA dedicated to DFSDM

Up to 35 communication peripherals

• 4× I2C FM+ interfaces (SMBus/PMBus)

• 5× USART/5x UARTs (ISO7816 interface, LIN, IrDA, modem control) and 1x

LPUART

• 6× SPIs, including 4 with muxed full-duplex I2S audio class accuracy via internal audio PLL or external clock and 1 x SPI/I2S in LP domain (up to 125 MHz)

• 2x SAIs (serial audio interface)

• SPDIFRX interface

• SWPMI single-wire protocol master interface

• MDIO Slave interface

• 2× SD/SDIO/MMC interfaces (up to 133 MHz)

• 2× CAN controllers: 2 with CAN FD, 1 with time-triggered CAN (TT-CAN)

• 1× USB OTG interfaces (1HS/FS)

• HDMI-CEC

• 8- to 14-bit camera interface up to 80 MHz

• 8-/16-bit parallel synchronous data input/output slave interface (PSSI) page 2/199

DS13196 - Rev 6

STM32H7B0xB

11 analog peripherals

• 2× ADCs with 16-bit max. resolution (up to 24 channels, up to 3.6 MSPS)

• 1× analog and 1x digital temperature sensors

• 1× 12-bit single-channel DAC (in SRD domain) + 1× 12-bit dual-channel DAC

• 2× ultra-low-power comparators

• 2× operational amplifiers (8 MHz bandwidth)

• 2× digital filters for sigma delta modulator (DFSDM), 1x with 8 channels/8 filters and 1x in SRD domain with 2 channels/1 filter

Graphics

• LCD-TFT controller up to XGA resolution

• Chrom-ART graphical hardware Accelerator (DMA2D) to reduce CPU load

• Hardware JPEG Codec

• Chrom-GRC

™

(GFXMMU)

Up to 19 timers and 2 watchdogs

• 2× 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature

(incremental) encoder input (up to 280 MHz)

• 2× 16-bit advanced motor control timers (up to 280 MHz)

• 10× 16-bit general-purpose timers (up to 280 MHz)

• 3× 16-bit low-power timers (up to 280 MHz)

• 2× watchdogs (independent and window)

• 1× SysTick timer

• RTC with sub-second accuracy and hardware calendar

Cryptographic acceleration

• AES chaining modes: ECB,CBC,CTR,GCM,CCM for 128, 192 or 256

• HASH (MD5, SHA-1, SHA-2), HMAC

• 2x OTFDEC AES-128 in CTR mode for Octo-SPI memory encryption/decryption

• 1x 32-bit, NIST SP 800-90B compliant, true random generator

Debug mode

• SWD and JTAG interfaces

• 4 KB Embedded Trace Buffer

96-bit unique ID

All packages are ECOPACK2 compliant page 3/199

1

Note:

STM32H7B0xB

Introduction

Introduction

This datasheet provides the ordering information and mechanical device characteristics of the STM32H7B0xB microcontrollers.

This document should be read in conjunction with the STM32H7B0xB reference manual (RM0455). The reference manual is available from the STMicroelectronics website .

For information on the device errata with respect to the datasheet and reference manual, refer to the

STM32H7B0xB errata sheet (ES0478), available on the STMicroelectronics website .

For information on the Arm ® Cortex from the www.arm.com website

® -M7 core, refer to the Cortex ® -M7 Technical Reference Manual, available

Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS13196 - Rev 6 page 4/199

2

STM32H7B0xB

Description

Description

STM32H7B0xB devices are based on the high-performance Arm ® Cortex ® -M7 32-bit RISC core operating at up to 280 MHz. The Cortex ® -M7 core features a floating point unit (FPU) which supports Arm ® double-precision

(IEEE 754 compliant) and single-precision data-processing instructions and data types. STM32H7B0xB devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security.

STM32H7B0xB devices incorporate high-speed embedded memories with a Flash memory of 128 Kbytes, around

1.4 Mbyte of RAM (including 192 Kbytes of TCM RAM, 1.18 Mbytes of user SRAM and 4 Kbytes of backup

SRAM), as well as an extensive range of enhanced I/Os and peripherals connected to four APB buses, three AHB buses, a 32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memory access.

All the devices offer two ADCs, two DACs (one dual and one single DAC), two ultra-low power comparators, a low-power RTC, 12 general-purpose 16-bit timers, two PWM timers for motor control, three low-power timers, a true random number generator (RNG), and a cryptographic acceleration cell and a HASH processor. The devices support nine digital filters for external sigma delta modulators (DFSDM). They also feature standard and advanced communication interfaces.

• Standard peripherals

– Four I2Cs

– Five USARTs, five UARTs and one LPUART

– Six SPIs, four I2Ss in full-duplex mode. To achieve audio class accuracy, the I 2 S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization.

– Two SAI serial audio interfaces, out of which one with PDM

– One SPDIFRX interface

– One single wire protocol master interface (SWPMI)

– One 16-bit parallel synchronous slave interface (PSSI) sharing the same interface as the digital camera)

– Management Data Input/Output (MDIO) slaves

– Two SDMMC interfaces (one can be supplied from a supply voltage separate from that of all other I/Os)

– A USB OTG high-speed with full-speed capability (with the ULPI)

– One FDCAN plus one TT-CAN interface

– Chrom-ART Accelerator

– HDMI-CEC

• Advanced peripherals including

– A flexible memory control (FMC) interface

– Two octo-SPI memory interface with on-the-fly decryption (OTFDEC)

– A digital camera interface for CMOS sensors (DCMI)

– A graphic memory management unit (GFXMMU)

– An LCD-TFT display controller (LTDC)

– A JPEG hardware compressor/decompressor

Refer to

Table 1. STM32H7B0xB features and peripheral counts for the list of peripherals available on each part

number.

STM32H7B0xB devices operate in the –40 to +85 °C ambient temperature range from a 1.62 to 3.6 V power supply. The supply voltage can drop down to 1.62 V by using an external power supervisor (see

Section 3.5.2 Power supply supervisor ) and connecting the PDR_ON pin to V

SS

. Otherwise the supply voltage must stay above 1.71 V with the embedded power voltage detector enabled.

The USB OTG_HS/FS interfaces can be supplied either by the integrated USB regulator or through a separate supply input.

A dedicated supply input is available for one of the SDMMC interface for package with more than 100 pins. It allows running from a different voltage level than all other I/Os.

A comprehensive set of power-saving mode allows the design of low-power applications.

The CPU and domain states can be directly monitored on some GPIOs configured as alternate functions.

STM32H7B0xB devices are offers in several packages ranging from 64 pins to 225 pins/balls. The set of included peripherals changes with the device chosen.

DS13196 - Rev 6 page 5/199

STM32H7B0xB

Description

•

•

•

•

•

These features make the STM32H7B0xB microcontrollers suitable for a wide range of applications:

•

•

•

Motor drive and application control

Medical equipment

Industrial applications: PLC, inverters, circuit breakers

Printers, and scanners

Alarm systems, video intercom, and HVAC

Home audio appliances

Mobile applications, Internet of Things

Wearable devices: smart watches.

Figure 1. STM32H7B0xB block diagram shows the general block diagram of the device family.

DS13196 - Rev 6 page 6/199

Peripherals

Flash memory (Kbytes)

SRAM in Kbytes

SRAM on AXI

SRAM on AHB (CD domain)

SRAM on AHB (SRD domain)

TCM RAM in Kbytes

ITCM RAM (instruction)

DTCM RAM (data)

Backup SRAM (Kbytes)

FMC

Interface

NOR Flash memory/RAM controller

Multiplexed I/O NOR Flash memory

16-bit NAND Flash memory

SDRAM controller

Octo-SPI interfaces

(3)

General-purpose

Advanced-control (PWM)

Timers

Basic

Low-power

Window watchdog / independent watchdog

Real-time Clock (RTC)

Passive

Tamper pins

(5)

Active

Random number generator

Cryptographic accelerator

Hash processor (HASH)

Table 1. STM32H7B0xB features and peripheral counts

SMPS (1)

x

(2)

x x

x (2)

2

(4)

2

1 x x

2

3

2

10

2

2

3

1/1

1

1

1

1 x x

64

128

4

1

128

1024

128

32 x

(2)

x

(2)

2 (4)

no-SMPS

x

(2)

x

(2)

1 Octo-SPI

-

-

-

1 Quad-SPI

2

1

SMPS (1)

no-SMPS

Peripherals

On-the-fly decryption

Communi-cation interfaces for external Octo-SPI memory

SPI/I2S

(6)

I2C

USART/UART

/LPUART

SAI/PDM

SPDIFRX

SWPMI

MDIOS

SDMMC

FDCAN/TT-CAN

USB OTG_HS ULPI, OTG_FS

PHY

Digital camera interface/PSSI (10)

LCD-TFT display controller

JPEG Codec

Chrom-ART Accelerator (DMA2D)

Graphic memory management unit (GFXMMU)

HDMI CEC

DFSDM

Number of filters for DFSDM1/DFSDM2

ADCs

8 to 16 bits

Number of channels

DACs

12 bits

Number of channels

Comparators

Operational amplifier

GPIOs

1

24

128

2

6/4

5/5

/1

2/1

4 inputs

2

8/1

2

2

1

24

121

2

6/4

4

5/5

/1

2/1

4 inputs

1

1

2

1/1

1

1/1

1

1

1

1

1

2

8/1

2

20

(11)

2

3 (1 single channel + 1 dual-channel interfaces)

2

2

138 112

1

(8)

2

5/4

5 (2) /5

/1

2 (2) /1

80

2 (7)

16 (11)

2 (2)

4/4

3

4 (2) /3 (2)

/1

1 (2)

/-

1/1

1

(2)

(9)

1/1

7/1

1

1

49

SMPS (1)

no-SMPS

Peripherals

Wakeup pins

Maximum CPU frequency (MHz)

SMPS step-down converter

USB internal regulator

USB separate supply pad

VDDMMC separate supply pad

VREF+ separate pad and internal buffer

Operating voltage

Operating temperatures

4

1

1

1

6 4

280

-

-

1

1

-

-

1

1.62 to 3.6 V (12)

1

UFBGA169

Ambient temperature range: −40 to 85 °C

Junction temperature range: −40 to 130 °C (13)

LQFP176 LQFP144

USART, I2C, SPI,

USB-DFU, FDCAN

USART, I2C, SPI,

USB-DFU, FDCAN

LQFP100

USART, I2C, SPI, USB-DFU

Packages

Bootloader

UFBGA176+25

USART, I2C, SPI, USB-

DFU, FDCAN

1. The devices with SMPS correspond to commercial code STM32H7B0xIxxQ.

2. For limitations on peripheral features depending on packages, check the available pins/balls in Table 7. STM32H7B0xB pin/ball definition

.

3. To maximize the performance, the I/O high-speed at low-voltage feature (HSLV) must be activated when V

DD

< 2.7 V. This feature is not available on all I/Os (see

Table 87. OCTOSPI characteristics in SDR mode , and

Table 88. OCTOSPI characteristics in DTR mode (with DQS)/Octal and

Hyperbus

).

4. The I/O high-speed at low-voltage feature (HSLV) at V

DD

< 2.7 V is not available for OCTOSPIM_P2.

5. A tamper pin can be configured either as passive or active (not both).

6. SPI1, SPI2, SPI3 and SPI6 interfaces give the flexibility to work in an exclusive way in either SPI mode or I2S audio mode.

7. Dedicated I/O supply pad (VDDMMC) or external level shifter are not supported.

8. The ULPI interface is supported. PC2 and PC3 are available on PC2_C and PC3_C, respectively, by closing the internal analog switch (see

Table 7. STM32H7B0xB pin/ball definition ).

9. The ULPI interface is not supported.

10. DCMI and PSSI cannot be used simultaneously since they share the same circuitry.

11. For limitations on fast pads or channels depending on packages, check to the available pins/balls in

Table 7. STM32H7B0xB pin/ball definition .

12. V

DD

/V

DDA

can drop down to 1.62 V by using an external power supervisor (see Section 3.5.2 Power supply supervisor ) and connecting PDR_ON

pin to V

SS

. Otherwise the supply voltage must stay above 1.71 V with the embedded power voltage detector enabled.

13. The junction temperature is limited to 105 °C in VOS0 voltage range.

-

LQFP64

STM32H7B0xB

Figure 1. STM32H7B0xB block diagram

SDMMC_D[7:0],SDMMC_D[7:3,1]Dir

SDMMC_D0dir, SDMMC_D2dir

CMD, CMDdir, CK, Ckin,

CKio as AF

HSYNC, VSYNC, PIXCLK, D[13:0]

PDCK, DE, RDY, D[15:0]

DFSDM_CKOUT,

DFSDM_DATAIN[7:0],

DFSDM_CKIN[7:0]

SD, SCK, FS, MCLK, PDM_D[3:1],

PDM_CK[2:1] as AF

SD, SCK, FS, MCLK, AF

MOSI, MISO, SCK, NSS /

SDO, SDI, CK, WS, MCK, as AF

MOSI, MISO, SCK, NSS as AF

MOSI, MISO, SCK, NSS as AF

RX, TX, SCK, CTS, RTS as AF

RX, TX, SCK, CTS, RTS as AF

RX, TX as AF

RX, TX, SCK, CTS, RTS as AF

2 compl. chan.(TIM15_CH1[1:2]N),

2 chan. (TIM_CH15[1:2], BKIN as AF

1 compl. chan.(TIM16_CH1N),

1 chan. (TIM16_CH1, BKIN as AF

1 compl. chan.(TIM17_CH1N),

1 chan. (TIM17_CH1, BKIN as AF

4 compl. chan. (TIM1_CH1[1:4]N),

4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF

4 compl. chan. (TIM1_CH1[1:4]N),

4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF

PA..I[15:0]

JTRST, JTDI,

JTCK/SWCLK

JTDO/SWD, JTDO

TRACECK

TRACED[3:0]

LCD_R[7:0], LCD_G[7:0],

LCD_B[7:0], LCD_HSYNC,

LCD_VSYNC, LCD_DE, LCD_CLK

DFSDM_CKOUT,

DFSDM_DATAIN[1:0],

DFSDM_CKIN[1:0]

COMPx_INP, COMPx_INM,

COMPx_OUT as AF

DAC2_OUT1 as AF

LPTIM2_OUT as AF

LPTIM3_OUT as AF

SCL, SDA, SMBAL as AF

MOSI, MISO, SCK, NSS /

SDO, SDI, CK, WS, MCK, as AF

RX, TX, CK, CTS, RTS as AF

VREF+

To APB1-2 peripherals

DP, DM, ID,

VBUS

SDMMC_

D[7:0],

CMD, CK as AF

D-TCM

64KB

D-TCM

64KB

CPU_AHBP

AHB1

DMA1 DMA2

AHB2

I-TCM

64KB

D-Cache

16KB

AHBS

AXI/AHB12 (280 MHz)

8 Stream

FIFOs

8 Stream

FIFOs

PHY

OTG_FS SDMMC2 BDMA1 8ch for DFSDM

JTAG/SW

ETM

ARM CPU

Cortex-M7

280 MHz

I-Cache

16KB

MDMA

CHROM-ART

(DMA2D)

LCD-TFT

AHBP

AXIM

16 Streams

FIFO

FIFO

FIFO

128 KB

FLASH

256 KB

AXI_SRAM1

384 KB

AXI_SRAM2

384 KB

AXI_SRAM3

FMC

FMC_signals

OCTOSPI1_signals

DMA/

FIFO

32-bit AHB BUS-MATRIX

DMA

Mux1

CRC

RNG

HSEM

HASH

3DES/AES

DB-SDMMC2

FIFO

AHB_SRAM1

64 KB

AHB_SRAM2

64 KB

AHB/APB

ADC1

ADC2

Analog Temp Sensor

32b

TIM2

TIM3

Up to 20 analog inputs

Some inputs are common to ADC1&2

Up to 20 analog inputs

4 channels, ETR as AF

WWDG

AHB/APB

JPEG

AHB3 (280 MHz)

SDMMC1 FIFO

OCTOSPI2_signals

DB-SDMMC1

DB-OCTOSPI1

DB-OCTOSPI2

AXI/AHB34 (280 MHz) AHB3

16b

16b

32b

16b

TIM4

TIM5

TIM12

4 channels, ETR as AF

4 channels, ETR as AF

4 channels

2 channels as AF

DCMI

PSSI

DFSDM1 8ftrs

SAI1/PDM

SAI2

SPI/I2S1

SPI4

SPI5 smcard irDA

USART1 smcard irDA

USART6

UART9 irDA

TIM15

16b

TIM16

16b

TIM17

16b

TIM1/PWM

16b

TIM8/PWM

16b

GPIO PORTA.. I

COMP1&2

DAC2

LPTIM2

16b

LPTIM3

16b

I2C4

SPI6/I2S6

LPUART1

VREF

Vref internal

AHB2 280 MHz (max)

16b

16b

TIM13

TIM14

1 channel as AF

1 channel as AF

AHB/APB AHB1 280 MHz (max) irDA

RX, TX, SCK, CTS,

RTS as AF

RX, TX, SCK

CTS, RTS as AF irDA

DMA

Mux2

BDMA2 DAP

32-bit AHB BUS-MATRIX

32 KB

SRD_SRAM

4 KB

TIM6

TIM7

SWPMI

BKP_SRAM

16b

16b

RAM

I/F

UART4

UART5

UART7

UART8

SPI2/I2S2

SPI3/I2S3

I2C1/SMBUS

I2C2/SMBUS

I2C3/SMBUS

MDIOS

TT-FDCAN1

FDCAN2

CRS

SPIF-RX1

HDMI-CEC

DAC1

DAC

DAC

LPTIM1

16b

RX, TX as AF

RX, TX as AF

RX, TX as AF

RX, TX as AF

MOSI, MISO, SCK, NSS /

SDO, SDI, CK, WS, MCK, as AF

MOSI, MISO, SCK, NSS /

SDO, SDI, CK, WS, MCK, as AF

SCL, SDA, SMBAL as AF

SCL, SDA, SMBAL as AF

SCL, SDA, SMBAL as AF

MDC, MDIO

TX, RX

TX, RX

SYNC

SPDIFRX[3:0] as AF

HDMI_CEC as AF

AHB4 280 MHz (max) DAC1_OUT1 as AF

DAC1_OUT2 as AF

LPTIM1_IN1, LPTIM1_IN2,

LPTIM2_OUT as AF

OPAMP1&2

OPAMPx_VINM

OPAMPx_VINP

Digital Temp Sensor

IWDG

Tamper monitor

RCC

Reset &

Clock

Control

AHB/

APB

VDD12

@VDD33

BBgen + POWER MNGT

Voltage regulator

3.3 to 1.2V

Temp

Monitor

SMPS

Step-down converter

USB regulator

Vbat charging

OPAMPx_VOUT as AF

VDD

VDDMMC

VSS

VCAP, VDDLDO

VDDSMPS, VSSSMPS

VLXSMPS, VFBSMPS

VDD50USB

VDD33USB

APB4 140 MHz (max) VBAT

SYSCFG

EXTI WKUP

CSI

HSI

@VDD

CSI RC 4MHz

PLL1+PLL2+PLL3

HSI RC 64MHz

@VSW

VDD

LSE XTAL 32 kHz

Backup registers

AWU

RTC

@VDD

HSE XTAL OSC

4 - 48MHz

WDG_LS_D1

OSC32_IN

OSC32_OUT

RTC_TS

RTC_TAMP[1:3]

RTC_OUT

RTC_REFIN

OSC_IN

OSC_OUT

HSI48 HSI48 RC 48MHz

MCO1

MCO2

LSI LSI RC 32kHz reset

Int

@VDD

SUPPLY SUPERVISION

POR/PDR/BOR

PVD

NRESET

WKUP[6:1]

DS13196 - Rev 6 page 10/199

3

3.1

Note:

3.2

3.3

3.3.1

STM32H7B0xB

Functional overview

Functional overview

Arm

®

Cortex

®

-M7 with FPU

The Arm ® Cortex ® -M7 with double-precision FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and optimized power consumption, while delivering outstanding computational performance and low interrupt latency.

The Cortex ® -M7 processor is a highly efficient high-performance featuring:

•

•

•

•

•

Six-stage dual-issue pipeline

Dynamic branch prediction

Harvard architecture with L1 caches (16 Kbytes of I-cache and 16 Kbytes of D-cache)

64-bit AXI4 interface

64-bit ITCM interface

• 2x32-bit DTCM interfaces

The following memory interfaces are supported:

•

•

•

•

Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency

Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM accesses

AXI Bus interface to optimize Burst transfers

Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals.

The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution.

It also supports single and double precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation.

Refer to

Figure 1. STM32H7B0xB block diagram

for the general block diagram of the STM32H7B0xB family.

Cortex ® -M7 with FPU core is binary compatible with the Cortex ® -M4 core.

Memory protection unit (MPU)

The memory protection unit (MPU) manages the CPU access rights and the attributes of the system resources.

It has to be programmed and enabled before use. Its main purposes are to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by a privileged task, but also to protect data processes or read-protect memory regions.

The MPU defines access rules for privileged accesses and user program accesses. It allows defining up to 16 protected regions that can in turn be divided into up to 8 independent subregions, where region address, size, and attributes can be configured. The protection area ranges from 32 bytes to 4 Gbytes of addressable memory.

When an unauthorized access is performed, a memory management exception is generated.

Memories

Embedded Flash memory

The STM32H7B0xB devices embed up to 128 Kbytes of Flash memory that can be used for storing programs and data.

The Flash memory is organized as 137-bit Flash words memory that can be used for storing both code and data constants. Each word consists of:

•

•

•

•

One Flash word (4 words, 16 bytes or 128 bits)

9 ECC bits.

The Flash memory is organized as follows:

• 128 Kbytes of user Flash memory, containing 16 user sectors of 8 Kbytes each

128 Kbytes of System Flash memory from which the device can boot.

1 Kbyte of OTP (one-time programmable) memory containing option bytes for user configuration.

DS13196 - Rev 6 page 11/199

3.3.2

3.3.3

3.4

STM32H7B0xB

Boot modes

Secure access mode

In addition to other typical memory protection mechanism (RDP, PCROP), STM32H7B0xB devices embed the

Secure access mode, an enhanced security feature. This mode allows developing user-defined secure services by ensuring, on the one hand code and data protection and on the other hand code safe execution.

Two types of secure services are available:

• STMicroelectronics Root Secure Services:

These services are embedded in System memory. They provide a secure solution for firmware and third-party modules installation. These services rely on cryptographic algorithms based on a device unique private key.

• User-defined secure services:

These services are embedded in user Flash memory. Examples of user secure services are proprietary user firmware update solution, secure Flash integrity check or any other sensitive applications that require a high level of protection.

The secure firmware is embedded in specific user Flash memory areas configured through option bytes.

Secure services are executed just after a reset and preempt all other applications to guarantee protected and safe execution. Once executed, the corresponding code and data are no more accessible.

The above secure services are available only for Cortex ® -M7 core operating in Secure access mode. The other masters cannot access the option bytes involved in Secure access mode settings or the Flash secured areas.

Embedded SRAM

All devices feature:

• 1 Mbyte of AXI-SRAM mapped onto AXI bus matrix in CPU domain (CD) split into:

– AXI-SRAM1: 256 Kbytes

– AXI-SRAM2: 384 Kbytes

•

– AXI-SRAM3: 384 Kbytes

128 Kbytes of AHB-RAM mapped onto AHB bus matrix in CPU domain (CD) split into:

– AHB-SRAM1: 64 Kbytes

– AHB-SRAM2: 64 Kbytes

32 Kbytes of SRD-SRAM mapped in Smart Run Domain (SRD) •

• 4 Kbytes of backup SRAM

The content of this area is protected against possible unwanted write accesses, and is retained in Standby or

V

BAT

mode.

• RAM mapped to TCM interface (ITCM and DTCM):

Both ITCM and DTCM RAMs are 0 wait state memories that are accessible from the CPU or the MDMA (even in

Sleep mode) through a specific AHB slave of the CPU(AHBP).

• 64 Kbytes of ITCM-RAM (instruction RAM)

This RAM is connected to ITCM 64-bit interface designed for execution of critical real-times routines by the CPU.

• 128 Kbytes of DTCM-RAM (2x 64 Kbyte DTCM-RAMs on 2x32-bit DTCM ports)

The DTCM-RAM could be used for critical real-time data, such as interrupt service routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for load/store operations) thanks to the Cortex ® -M7 dual issue capability.

Boot modes

•

•

At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF which includes:

All Flash address space

All RAM address space: ITCM, DTCM RAMs and SRAMs

• The system memory bootloader

The boot loader is located in non-user System memory. It is used to reprogram the Flash memory through a serial interface (USART, I2C, SPI, USB-DFU, FDCAN). Refer to STM32 microcontroller system memory boot mode application note (AN2606) for details.

DS13196 - Rev 6 page 12/199

3.5

3.5.1

Note:

STM32H7B0xB

Power supply management

Power supply management

Power supply scheme

•

•

•

•

V

DD

= 1.62 to 3.6 V: external power supply for I/Os, provided externally through V

DD

pins.

V

DDLDO

= 1.62 to 3.6 V: supply voltage for the internal regulator supplying V

CORE

V

DDA

= 1.62 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL.

V

DD33USB and V

DD50USB

:

V

DD50USB can be supplied through the USB cable to generate the V

DD33USB

via the USB internal regulator. This allows supporting a V

DD

supply different from 3.3 V.

The USB regulator can be bypassed to supply directly V

DD33USB

if V

DD

= 3.3 V.

•

•

•

V

DDMMC

= 1.62 to 3.6 V external power supply for independent I/Os. V

DDMMC

can be higher than V

DD

.

VDDMMC pin should be tied to VDD when it is not used.

V

BAT

= 1.2 to 3.6 V: power supply for the V

SW

domain when V

DD

is not present.

V

CAP

: V

CORE

supply, which value depends on voltage scaling (0.74 V, 0.9 V, 1.0 V, 1.1 V, 1.2 V or 1.3 V). It is configured through VOS bits in PWR_CR3 register. The V

CORE domain (CD) and the Smart Run Domain (SRD).

domain is split into two domains the CPU

•

•

•

– CD domain containing most of the peripherals and the Arm ® Cortex ® -M7 core

– SRD domain containing some peripherals and the system control.

V

DDSMPS

= 1.62 to 3.6 V: step-down converter power supply

V

LXSMPS

= V

CORE

or 1.8 to 2.5 V: external regulated step-down converter output

V

FBSMPS

= V

CORE

or 1.8 to 2.5 V: external step-down converter feedback voltage sense input

For I/O speed optimization at low V

DD

supply, refer to Section 3.8 General-purpose input/outputs (GPIOs) .

The features available on the device depend on the package (refer to Table 1. STM32H7B0xB features and peripheral counts

).

During power-up and power-down phases, the following power sequence requirements must be respected (see

Figure 2. Power-up/power-down sequence

):

•

•

When V

DD

is below 1 V, other power supplies (V

DDA

, V

DD33USB

and V

DD50USB

) must remain below V

DD

+

300 mV.

When V

DD

is above 1 V, all power supplies are independent (except for V

DDSMPS

, which must remain at the same level as V

DD

).

During the power-down phase, V

DD

can temporarily become lower than other supplies only if the energy provided to the microcontroller remains below 1 mJ. This allows external decoupling capacitors to be discharged with different time constants during the power-down transient phase.

DS13196 - Rev 6 page 13/199

STM32H7B0xB

Power supply management

Figure 2. Power-up/power-down sequence

V

3.6

V

DDX

(1)

V

DD

3.5.2

V

POR

V

PDR

1

0.3

Power-on

Invalid supply area

Operating mode

V

DDX

< V

DD

+ 300 mV

Power-down

V

DDX

independent from V

DD time

1.

V

DDx

refers to any power supply among V

DDA

, V

DD33USB

and V

DD50USB

.

2.

V

DD

and V

DDSMPS

must be wired together into order to follow the same voltage sequence.

•

•

•

•

•

•

•

Power supply supervisor

The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a

Brownout reset (BOR) circuitry:

Power-on reset (POR)

The POR supervisor monitors V

DD

power supply and compares it to a fixed threshold. The devices remain in reset mode when V

DD

is below this threshold,

Power-down reset (PDR)

The PDR supervisor monitors V

DD

power supply. A reset is generated when V threshold.

DD drops below a fixed

The PDR supervisor can be enabled/disabled through PDR_ON pin.

Brownout reset (BOR)

The BOR supervisor monitors V

DD

power supply. Three BOR thresholds (from 2.1 to 2.7 V) can be configured through option bytes. A reset is generated when V

DD

drops below this threshold.

Programmable voltage detector (PVD)

The PVD monitors the V

DD

power supply by comparing it with a threshold selected from a set of predefined values.

It can also monitor the voltage level of the PVD_IN pin by comparing it with an internal V

REFINT

voltage reference level.

Analog voltage detector (AVD)

The AVD monitors the V

DDA values.

power supply by comparing it with a threshold selected from a set of predefined

V

BAT

threshold

The V

BAT

battery voltage level can be monitored by comparing it with two thresholds levels.

Temperature threshold

A dedicated temperature sensor monitors the junction temperature and compare it with two threshold levels.

DS13196 - Rev 6 page 14/199

3.5.3

3.5.4

3.6

STM32H7B0xB

Low-power modes

•

•

Voltage regulator

The same voltage regulator supplies the two power domains (CD and SRD). The CD domain can be independently switched off.

Voltage regulator output can be adjusted according to application needs through six power supply levels:

Run mode (VOS0 to VOS3)

– Scale 0 and scale 1: high performance

– Scale 2: medium performance and consumption

– Scale 3: optimized performance and low-power consumption

Stop mode (SVOS3 to SVOS5)

– Scale 3: peripheral with wakeup from stop mode capabilities (UART, SPI, I2C, LPTIM) are operational

– Scale 4 and 5 where the peripheral with wakeup from Stop mode is disabled

The peripheral functionality is disabled but wakeup from Stop mode is possible through GPIO or asynchronous interrupt.

•

•

SMPS step-down converter

The built-in SMPS step-down converter is a highly power-efficient DC/DC non-linear switching regulator that provides lower power consumption than a conventional voltage regulator (LDO).

The step-down converter can be used to:

Directly supply the V

CORE

domain

– the SMPS step-down converter operating modes follow the device system operating modes (Run,

Stop, Standby).

– the SMPS step-down converter output voltage are set according to the selected VOS and SVOS bits

(voltage scaling)

Provide intermediate voltage level to supply the internal voltage regulator (LDO)

•

– The SMPS step-down converter operating modes follow the device system operating modes (Run,

Stop, Standby).

– The SMPS step-down converter output equals 1.8 V or 2.5 V according to the selected step-down level

Provide an external supply

– The SMPS step-down converter is forced to external operating mode

– The SMPS step-down converter output equals 1.8 V or 2.5 V according to the selected step-down level

The 1.8 V or 2.5 V SMPS step-down converter output voltage imposes a minimum V

DDSMPS

supply of 2.5 V or

3.3 V, respectively. It defines indirectly the minimum V

DD

supply and I/O level.

Low-power modes

There are several ways to reduce power consumption on STM32H7B0xB:

•

•

Decrease dynamic power consumption by slowing down the system clocks even in Run mode and individually clock gating the peripherals that are not used.

Save power consumption when the CPU is idle, by selecting among the available low-power mode according to the user application needs. This allows achieving the best compromise between short startup time, low-power consumption, as well as available wakeup sources.

The devices feature several low-power modes:

•

•

•

System Run with CSleep (CPU clock stopped)

Autonomous with CD domain in DStop (CPU and CPU Domain bus matrix clocks stopped)

Autonomous with CD domain in DStop2 (CPU and CPU Domain bus matrix clocks stopped, CPU domain in retention mode)

•

•

•

System Stop (SRD domain clocks stopped) and CD domain in DStop (CPU and CPU Domain bus matrix clocks stopped)

System Stop (SRD domain clocks stopped) and CD domain in DStop2 (CPU and CPU Domain bus matrix clocks stopped, CPU domain in retention mode)

Standby (System, CD and SRD domains powered down)

DS13196 - Rev 6 page 15/199

3.7

3.7.1

STM32H7B0xB

Reset and clock controller (RCC)

CSleep and CStop low-power modes are entered by the MCU when executing the WFI (Wait for Interrupt) or WFE

(Wait for Event) instructions, or when the SLEEPONEXIT bit of the Cortex ® -M7 core is set after returning from an interrupt service routine.

The CPU domain can enter low-power mode (DStop or DStop2) when the processor, its subsystem and the peripherals allocated in the domain enter low-power mode.

If part of the domain is not in low-power mode, the domain remains in the current mode.

Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared and the power domains are in DStop or DStop2 mode.

System power mode

Run

Stop

Standby

Table 2. System vs domain low-power mode

CD domain power mode

DRun/DStop/DStop2

DStop/DStop2

Standby

Some GPIO pins can be used to monitor CPU and domain power states:

SRD domain power mode

DRun

DStop

Standby

Table 3. Overview of low-power mode monitoring pins

Power state monitoring pins

PWR_CSLEEP

PWR_CSTOP

PWR_NDSTOP2

Description

CPU clock OFF

CPU domain in low-power mode

CPU domain retention mode selection

Reset and clock controller (RCC)

The clock and reset controller is located in the SRD domain. The RCC manages the generation of all the clocks, as well as the clock gating and the control of the system and peripheral resets. It provides a high flexibility in the choice of clock sources and allows to apply clock ratios to improve the power consumption. In addition, on some communication peripherals that are capable to work with two different clock domains (either a bus interface clock or a kernel peripheral clock), the system frequency can be changed without modifying the baud rate.

Clock management

The devices embed four internal oscillators, two oscillators with external crystal or resonator, two internal oscillators with fast startup time and three PLLs.

The RCC receives the following clock source inputs:

•

•

Internal oscillators:

– 64 MHz HSI clock (1% accuracy)

– 48 MHz RC oscillator

– 4 MHz CSI clock

– 32 kHz LSI clock

External oscillators:

– 4-50 MHz HSE clock

– 32.768 kHz LSE clock

The RCC provides three PLLs: one for system clock, two for kernel clocks.

The system starts on the HSI clock. The user application can then select the clock configuration.

A high precision can be achieved for the 48 MHz clock by using the embedded clock recovery system (CRS). It uses the USB SOF signal, the LSE or an external signal (SYNC) to fine tune the oscillator frequency on-the- fly.

DS13196 - Rev 6 page 16/199

3.7.2

3.8

STM32H7B0xB

General-purpose input/outputs (GPIOs)

•

•

•

•

•

•

•

•

System reset sources

Power-on reset initializes all registers while system reset reinitializes the system except for the debug, part of the

RCC and power controller status registers, as well as the backup power domain.

A system reset is generated in the following cases:

Power-on reset (pwr_por_rst)

Brownout reset

Low level on NRST pin (external reset)

Window watchdog

Independent watchdog

Software reset

Low-power mode security reset

Exit from Standby

General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission.

After reset, all GPIOs are in Analog mode to reduce power consumption.

The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers.

To maximize the performance, the I/O high-speed feature, HSLV, must be activated at low device supply voltage.

This is needed to achieve the performance required for peripherals such as the SDMMC, FMC and OCTOSPI.

The GPIOs are divided into four groups which can be optimized separately (refer to the description of HSLVx bits of SYSCFG_CCCSR register in RM0455).

The I/O high-speed feature must be used only when V

DD

is lower than 2.7 V, and both the HSLV user option bits

(VDDIO_HSLV and VDDMMC_HSLV) and HSLVx bits must be set to enable it (refer to RM0455 for details).

DS13196 - Rev 6 page 17/199

3.9

Bus-interconnect matrix

The devices feature an AXI bus matrix, two AHB bus matrices and bus bridges that allow interconnecting bus masters with bus slaves (see

Figure 3. STM32H7B0xB bus matrix

).

Figure 3. STM32H7B0xB bus matrix

AHBS

CPU

Cortex-M7

I$

16KB

D$

16KB

ITCM

64 Kbytes

DTCM

128 Kbytes

DMA1 DMA2 SDMMC2 USBHS1 BDMA1

SDMMC1 MDMA DMA2D LTDC

AXI to AHB

GFX-MMU

AHB3

APB3

Flash memory

128 Kbytes

FMC

OTFDEC1 OCTOSPI1

OTFDEC2 OCTOSPI2

AXI SRAM1

256 Kbytes

AXI SRAM2

384 Kbytes

AXI SRAM3

384 Kbytes

32-bit AHB bus matrix

CD domain

AHB SRAM1

64 Kbytes

AHB SRAM2 64

Kbytes

AHB1

AHB2

APB1

APB2

64-bit AXI bus matrix

CD domain

Legend

32-bit bus

64-bit bus

Bus multiplexer

TCM

AXI

AHB

APB

Master interface

Slave interface

CD-to-SRD AHB

BDMA2

32-bit AHB bus matrix

SRD domain

AHB4

SRD SRAM

32 Kbytes

Backup

SRAM

4 Kbytes

APB4

3.10

3.11

3.12

3.13

STM32H7B0xB

DMA controllers

DMA controllers

The devices feature five DMA instances to unload CPU activity:

• A master direct memory access (MDMA)

The MDMA is a high-speed DMA controller, which is in charge of all types of memory transfers (peripheral to memory, memory to memory, memory to peripheral), without any CPU action. It features a master AXI interface and a dedicated AHB interface to access Cortex ® -M7 TCM memories.

The MDMA is located in the CD domain. It is able to interface with the other DMA controllers located in this domain to extend the standard DMA capabilities, or can manage peripheral DMA requests directly.

Each of the 16 channels can perform single block transfers, repeated block transfers and linked list transfers.

•

•

Two dual-port DMAs (DMA1, DMA2) located in the CD domain and connected to the AHB matrix, with FIFO and request router capabilities.

One basic DMA (BDMA1) located in the CD domain and connected to the AHB matrix. This DMA is

dedicated to the DFSDM (see Section 3.26 Digital filter for sigma-delta modulators (DFSDM) )

One basic DMA (BDMA2) located in the SRD domain, with request router capabilities.

•

The DMA request router could be considered as an extension of the DMA controller. It routes the DMA peripheral requests to the DMA controller itself. This allowing managing the DMA requests with a high flexibility, maximizing the number of DMA requests that run concurrently, as well as generating DMA requests from peripheral output trigger or DMA event.

Chrom-ART Accelerator (DMA2D)

•

•

The Chrom-Art Accelerator (DMA2D) is a graphical accelerator which offers advanced bit blitting, row data copy and pixel format conversion. It supports the following functions:

Rectangle filling with a fixed color

Rectangle copy

•

•

Rectangle copy with pixel format conversion

Rectangle composition with blending and pixel format conversion

Various image format coding are supported, from indirect 4bpp color mode up to 32bpp direct color. It embeds dedicated memory to store color lookup tables. The DMA2D also supports block based YCbCr to handle JPEG decoder output.

An interrupt can be generated when an operation is complete or at a programmed watermark.

All the operations are fully automatized and are running independently from the CPU or the DMAs.

Chrom-GRC™ (GFXMMU)

The Chrom-GRC ™ is a graphical oriented memory management unit aimed at:

• Optimizing memory usage according to the display shape

•

•

Manage cache linear accesses to the frame buffer

Prefetch data

The display shape is programmable to store only the visible image pixels.

A virtual memory space is provided which is seen by all system masters and can be physically mapped to any system memory.

An interrupt can be generated in case of buffer overflow or memory transfer error.

Nested vectored interrupt controller (NVIC)

•

•

•

•

•

The devices embed a nested vectored interrupt controller which is able to manage 16 priority levels, and handle up to 150 maskable interrupt channels plus the 16 interrupt lines of the Cortex ® -M7 with FPU core.

Closely coupled NVIC gives low-latency interrupt processing

Interrupt entry vector table address passed directly to the core

Allows early processing of interrupts

Processing of late arriving, higher-priority interrupts

Support tail chaining

DS13196 - Rev 6 page 19/199

3.14

3.15

3.16

3.17

STM32H7B0xB

Extended interrupt and event controller (EXTI)

•

•

Processor context automatically saved

Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimum interrupt latency.

Extended interrupt and event controller (EXTI)

The EXTI controller performs interrupt and event management. In addition, it can wake up the processor, power domains and/or SRD domain from Stop mode.

The EXTI handles up to 89 independent event/interrupt lines split into 28 configurable events and 61 direct events.

Configurable events have dedicated pending flags, active edge selection, and software trigger capable.

Direct events provide interrupts or events from peripherals having a status flag.

Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a programmable polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The

CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location.

Flexible memory controller (FMC)

•

•

•

•

•

•

•

The FMC controller main features are the following:

• Interface with static-memory mapped devices including:

– Static random access memory (SRAM)

– NOR Flash memory/OneNAND Flash memory

– PSRAM (4 memory banks)

– NAND Flash memory with ECC hardware to check up to 8 Kbytes of data

Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories

8-,16-,32-bit data bus width

Independent Chip Select control for each memory bank

Independent configuration for each memory bank

Write FIFO

Read FIFO for SDRAM controller

The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is the FMC kernel clock divided by 2.

Octo-SPI memory interface (OCTOSPI)

The OCTOSPI is a specialized communication interface targeting single, dual, quad or octal SPI memories.

The STM32H7B0xB embeds two separate Octo-SPI interfaces.

Each OCTOSPI instance supports single/dual/quad/octal SPI formats.

Multiplex of single/dual/quad/octal SPI over the same bus can be achieved using the integrated I/O manager.

The OCTOSPI can operate in any of the three following modes:

•

•

•

Indirect mode: all the operations are performed using the OCTOSPI registers

Status-polling mode: the external memory status register is periodically read and an interrupt can be generated in case of flag setting

Memory-mapped mode: the external memory is memory mapped and it is seen by the system as if it was an internal memory supporting both read and write operations.

The OCTOSPI support two frame formats supported by most external serial memories such as serial PSRAMs, serial NOR Flash memories, Hyper RAMs and Hyper Flash memories:

•

•

The classical frame format with the command, address, alternate byte, dummy cycles and data phase

The HyperBus ™ frame format.

DS13196 - Rev 6 page 20/199

3.18

3.19

3.20

3.21

Note:

3.22

STM32H7B0xB

Analog-to-digital converters (ADCs)

Multichip package (MCP) combining any of the above mentioned memory types can also be supported.

Analog-to-digital converters (ADCs)

•

•

The STM32H7B0xB devices embed two analog-to-digital converters, whose resolution can be configured to 16,

14, 12, 10 or 8 bits. Each ADC shares up to 24 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

Simultaneous sample and hold

Interleaved sample and hold

The ADC can be served by the DMA controller, thus allowing to automatically transfer ADC converted values to a destination location without any software action.

In addition, an analog watchdog feature can accurately monitor the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM6,

TIM8, TIM15, and LPTIM1 timers.

Analog temperature sensor

The STM32H7B0xB embeds an analog temperature sensor that generates a voltage (V

TS

) that varies linearly with the temperature. This temperature sensor is internally connected to ADC2_IN18. The conversion range is between 1.7 V and 3.6 V. It can measure the device junction temperature ranging from −40 to +125 °C.

The temperature sensor have a good linearity, but it has to be calibrated to obtain a good overall accuracy of the temperature measurement. As the temperature sensor offset varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the System memory area, which is accessible in read-only mode.

Digital temperature sensor (DTS)

The STM32H7B0xB embeds a sensor that converts the temperature into a square wave which frequency is proportional to the temperature. The PCLK or the LSE clock can be used as reference clock for the measurements. A formula given in the product reference manual (RM0455) allows to calculate the temperature according to the measured frequency stored in the DTS_DR register.

V

BAT

operation

The V

BAT

power domain contains the RTC, the backup registers and the backup SRAM.

To optimize battery duration, this power domain is supplied by V

DD

when available or by the voltage applied on

VBAT pin (when V

DD

supply is not present). V

BAT

power is switched when the PDR detects that V

DD

dropped below the PDR level.

The voltage on the VBAT pin could be provided by an external battery, a supercapacitor or directly by V

DD which case, the V

DD

mode is not functional.

, in

V

BAT

operation is activated when V

DD

is not present.

The VBAT pin supplies the RTC, the backup registers and the backup SRAM.

The devices embed an internal V

BAT

battery charging circuitry that can be activated when V

DD

is present.

When the microcontroller is supplied from V

BAT

, external interrupts and RTC alarm/events do not exit it from

V

BAT

operation.

When PDR_ON pin is connected to V

SS

(Internal Reset OFF), the V

BAT

functionality is no more available and

V

BAT

pin should be connected to VDD.

Digital-to-analog converters (DAC)

The devices features one dual-channel DAC (DAC1), located in the CD domain, plus one single-channel DAC

(DAC2), located in the SRD domain.

DS13196 - Rev 6 page 21/199

3.23

3.24

3.25

STM32H7B0xB

Voltage reference buffer (VREFBUF)

The three 12-bit buffered DAC channels can be used to convert three digital signals into three analog voltage signal outputs.

The following feature are supported:

•

•

•

•

•

• three DAC converters: one for each output channel

8-bit or 12-bit monotonic output left or right data alignment in 12-bit mode synchronized update capability noise-wave generation triangular-wave generation

•

•

•

•

Triple DAC channel independent or simultaneous conversions

DMA capability for each channel including DMA underrun error detection external triggers for conversion input voltage reference V

REF+ or internal VREFBUF reference.

The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams.

Voltage reference buffer (VREFBUF)

The built-in voltage reference buffer can be used as voltage reference for ADCs and DACs, as well as voltage reference for external components through the VREF+ pin.

Five different voltages are supported (refer to the reference manual for details).

Ultra-low-power comparators (COMP)

The STM32H7B0xB devices embed two rail-to-rail comparators (COMP1 and COMP2). They feature programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) as well as selectable output polarity.

The reference voltage can be one of the following:

• An external I/O

•

•

•

•

A DAC output channel

An internal reference voltage or submultiple (1/4, 1/2, 3/4)

The analog temperature sensor

The V

BAT

/4 supply.

All comparators can wake up from Stop mode, generate interrupts and breaks for the timers, and be combined into a window comparator.

Operational amplifiers (OPAMP)

•

•

•

The STM32H7B0xB devices embed two rail-to-rail operational amplifiers (OPAMP1 and OPAMP2) with external or internal follower routing and PGA capability, and two inputs and one output each. These three I/Os can be connected to the external pins, thus enabling any type of external interconnections. The operational amplifiers can be configured internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 16 or with inverting gain ranging from -1 to -15.

The operational amplifier main features are:

PGA with a non-inverting gain ranging of 2, 4, 8 or 16 or inverting gain ranging of -1, -3, -7 or -15

Up to two positive inputs connected to DAC

Output connected to internal ADC

•

•

•

Low input bias current down to 1 nA

Low input offset voltage down to 1.5 mV

Gain bandwidth up to 8 MHz

The devices embed two operational amplifiers (OPMAP1 and OPAMP2) with two inputs and one output each.

These three I/Os can be connected to the external pins, thus enabling any type of external interconnections. The operational amplifiers can be configured internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 16 or with inverting gain ranging from -1 to -15.

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3.26

STM32H7B0xB

Digital filter for sigma-delta modulators (DFSDM)

Digital filter for sigma-delta modulators (DFSDM)

•

•

•

•

•

•

•

•

The device embeds two DFSDM interfaces:

• DSFDM1

It is located in the CD domain and features eight external digital serial interfaces (channels) and eight digital filters, or alternately eight internal parallel inputs.

• DSFDM2

It is located in the SRD domain. DFSDM2 is a lite version including two external digital serial interfaces

(channels) and one digital filters.

The DFSDM peripherals interface the external Σ∆ modulators to microcontroller and then perform digital filtering of the received data streams (which represent analog value on Σ∆ modulators inputs). DFSDMs can also interface

PDM (Pulse Density Modulation) microphones and perform PDM to PCM conversion and filtering in hardware.

The DFSDMs feature optional parallel data stream inputs from internal ADC peripherals or microcontroller memory (through DMA/CPU transfers into DFSDM).

DFSDM transceivers support several serial interface formats (to support various Σ∆ modulators). DFSDM digital filter modules perform digital processing according user selected filter parameters with up to 24-bit final ADC resolution.

The DFSDM peripherals support:

• Multiplexed input digital serial channels:

– configurable SPI interface to connect various SD modulator(s)

•

– configurable Manchester coded 1 wire interface support

– PDM (Pulse Density Modulation) microphone input support

– maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)

– clock output for SD modulator(s): 0..20 MHz

Alternative inputs from eight internal digital parallel channels (up to 16 bit input resolution):

•

•

•

– internal sources: ADC data or memory data streams (DMA)

Digital filter modules with adjustable digital signal processing:

– Sinc x filter: filter order/type (1..5), oversampling ratio (up to 1..1024)

– integrator: oversampling ratio (1..256)

Up to 24-bit output data resolution, signed output data format

Automatic data offset correction (offset stored in register by user)

Continuous or single conversion

Start-of-conversion triggered by:

– software trigger

– internal timers

– external events

– start-of-conversion synchronously with first digital filter module (DFSDM0)

Analog watchdog feature:

– low value and high value data threshold registers

– dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)

– input from final output data or from selected input digital serial channels

– continuous monitoring independently from standard conversion

Short circuit detector to detect saturated analog input values (bottom and top range):

– up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream

– monitoring continuously each input serial channel

Break signal generation on analog watchdog event or on short circuit detector event

Extremes detector:

– storage of minimum and maximum values of final conversion data

– refreshed by software

DMA capability to read the final conversion data

Interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial channel clock absence

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3.27

3.28

3.29

3.30

STM32H7B0xB

Digital camera interface (DCMI)

• “Regular” or “injected” conversions:

– “regular” conversions can be requested at any time or even in continuous mode without having any impact on the timing of “injected” conversions

– “injected” conversions for precise timing and with high conversion priority

Digital camera interface (DCMI)

•

•

•

•

•

The devices embed a camera interface that can connect with camera modules and CMOS sensors through an

8-bit to 14-bit parallel interface, to receive video data. The camera interface can achieve a data transfer rate up to

140 Mbyte/s using a 80 MHz pixel clock. It features:

Programmable polarity for the input pixel clock and synchronization signals

Parallel data communication can be 8-, 10-, 12- or 14-bit

Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB

565 progressive video or compressed data (like JPEG)

Supports continuous mode or snapshot (a single frame) mode

Capability to automatically crop the image

Parallel synchronous slave interface (PSSI)

The PSSI is a generic synchronous 8-/16-bit parallel data input/output slave interface. It allows the transmitter to send a data valid signal to indicate when the data is valid, and the receiver to output a flow control signal to indicate when it is ready to sample the data.

The PSSI main features are:

•

•

•

•

Slave mode operation

8- or 16-bit parallel data input or output

8-word (32-byte) FIFO

Data enable (DE) alternate function input and Ready (RDY) alternate function output.

When enabled, these signals can either allow the transmitter to indicate when the data is valid or the receiver to indicate when it is ready to sample the data, or both.

The PSSI shares most of the circuitry with the digital camera interface (DCMI). It thus cannot be used simultaneously with the DCMI.

LCD-TFT display controller (LTDC)

•

•

•

•

•

•

•

•

The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals to interface directly to a broad range of LCD and TFT panels up to XGA (1024x768) resolution with the following features:

2 display layers with dedicated FIFO (64x32-bit)

Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer

Up to 8 input color formats selectable per layer

Flexible blending between two layers using alpha value (per pixel or constant)

Flexible programmable parameters for each layer

Color keying (transparency color)

Up to 4 programmable interrupt events

AXI master interface with burst of 16 words

JPEG codec (JPEG)

•

•

•

The JPEG codec can encode and decode a JPEG stream as defined in the

ISO/IEC10918-1 specification. It provides an fast and simple hardware compressor and decompressor of JPEG images with full management of JPEG headers.

The JPEG codec main features are as follows:

8-bit/channel pixel depths

Single clock per pixel encoding and decoding

Support for JPEG header generation and parsing

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3.31

3.32

3.33

STM32H7B0xB

True random number generator (RNG)

•

•

•

•

•

•

•

•

•

•

•

•

Up to four programmable quantization tables

Fully programmable Huffman tables (two AC and two DC)

Fully programmable minimum coded unit (MCU)

Encode/decode support (non simultaneous)

Single clock Huffman coding and decoding

Two-channel interface: Pixel/Compress In, Pixel/Compressed Out

Stallable design

Support for single greyscale component

Ability to enable/disable header processing

Internal register interface

Fully synchronous design

Configuration for high-speed decode mode

True random number generator (RNG)

All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. The

RNG is a true random number generator that provides full entropy outputs to the application as 32-bit samples. It is composed of a live entropy source (analog) and an internal conditioning component.

Cryptographic acceleration (CRYP and HASH)

The devices embed a cryptographic processor that supports the advanced cryptographic algorithms usually required to ensure confidentiality, authentication, data integrity and non-repudiation when exchanging messages with a peer:

•

•

Encryption/Decryption

– DES/TDES (data encryption standard/triple data encryption standard): ECB (electronic codebook) and

CBC (cipher block chaining) chaining algorithms, 64-, 128- or 192-bit key

– AES (advanced encryption standard): ECB, CBC, GCM, CCM, and CTR (counter mode) chaining algorithms, 128, 192 or 256-bit key

Universal HASH

– SHA-1 and SHA-2 (secure HASH algorithms)

– MD5

– HMAC

The cryptographic accelerator supports DMA request generation.

On-the-fly decryption engine (OTFDEC)

The embedded OTFDEC decrypts in real-time the encrypted content stored in the external Octo-SPI memories used in Memory-mapped mode.

The OTFDEC uses the AES-128 algorithm in counter mode (CTR).

Code execution on external Octo-SPI memories can be protected against fault injection thanks to

STMicroelectronics enhanced encryption mode (refer to RM0455 for details).

The OTFDEC main features are as follow:

• On-the-fly 128-bit decryption during STM32 Octo-SPI read operations (single or multiple).

– AES-CTR algorithm with keystream FIFO (depth= 4)

•

•

– Support for any read size

Up to four independent encrypted regions

– Region definition granularity: 4096 bytes

– Region configuration write locking mechanism

– Two optional decryption modes: execute-only and execute-never

128-bit key for each region, two-byte firmware version, and eight-byte application-defined nonce

DS13196 - Rev 6 page 25/199

STM32H7B0xB

Timers and watchdogs

3.34

•

•

•

Encryption keys confidentiality and integrity protection

– Write only registers with software locking mechanism

– Availability of 8-bit CRC as public key information

Support for STM32 Octo-SPI prefetching mechanism.

Encryption mode

Timers and watchdogs

The devices include two advanced-control timers, ten general-purpose timers, two basic timers, three low-power timers, two watchdogs and a SysTick timer.

All timer counters can be frozen in Debug mode.

Table 4. Timer feature comparison

compares the features of the advanced-control, general-purpose and basic timers.

Table 4. Timer feature comparison

Timer type Timer

Counter resolution

Counter type

Prescaler factor

DMA request generation

Capture/ compare channels

Complementary output

Max interface clock

(MHz)

Advancedcontrol

General purpose

Basic

TIM1,

TIM8

TIM2,

TIM5

TIM3,

TIM4

TIM12

TIM13,

TIM14

TIM15

TIM16,

TIM17

TIM6,

TIM7

16-bit

32-bit

16-bit

16-bit

16-bit

16-bit

16-bit

16-bit

Up, Down,

Up/down

Up, Down,

Up/down

Up, Down,

Up/down

Up

Up

Up

Up

Up

Any integer between 1 and

65536

Any integer between 1 and

65536

Any integer between 1 and

65536

Any integer between 1 and

65536

Any integer between 1 and

65536

Any integer between 1 and

65536

Any integer between 1 and

65536

Any integer between 1 and

65536

Yes

Yes

Yes

No

No

Yes

Yes

Yes

4

4

4

2

1

2

1

0

Low-power timer

LPTIM1,

LPTIM2,

LPTIM3

16-bit Up

1, 2, 4, 8, 16, 32,

64, 128

No 0

1. The maximum timer clock is up to 280 MHz depending on TIMPRE bit in the RCC_CFGR register and

CDPRE1/2 bits in RCC_CDCFGR register.

Yes

No

No

No

No

1

1

No

No

140

140

140

140

140

140

140

140

140

Max timer clock

(MHz)

(1)

280

280

280

280

280

280

280

280

280

3.34.1

•

Advanced-control timers (TIM1, TIM8)

The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for:

Input capture

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3.34.2

3.34.3

3.34.4

STM32H7B0xB

Timers and watchdogs

•

•

•

Output compare

PWM generation (edge- or center-aligned modes)

One-pulse mode output

If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-100%).

The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining.

The advanced-control timers support independent DMA request generation.

•

•

General-purpose timers (TIMx)

There are ten synchronizable general-purpose timers embedded in the STM32H7B0xB devices (see

Table 4. Timer feature comparison

for differences).

TIM2, TIM3, TIM4 and TIM5

The devices include 4 full-featured general-purpose timers: TIM2, TIM3, TIM4 and TIM5. TIM2 and TIM5 are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler while TIM3 and TIM4 are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. All timers feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages.

TIM2, TIM3, TIM4 and TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers (TIM1, TIM8) via the Timer Link feature for synchronization or event chaining.

Any of these general-purpose timers can be used to generate PWM outputs.

TIM2, TIM3, TIM4 and TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors.

TIM12, TIM13, TIM14, TIM15, TIM16 and TIM17

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM13, TIM14, TIM16 and

TIM17 feature one independent channel, whereas TIM12 and TIM15 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2,

TIM3, TIM4 and TIM5 full-featured general-purpose timers or used as simple time bases.

Basic timers (TIM6 and TIM7)

These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic

16-bit time base.

TIM6 and TIM7 support independent DMA request generation.

•

•

•

•

•

•

•

•

•

•

Low-power timers (LPTIM1, LPTIM2, LPTIM3)

The low-power timers feature an independent clock and are running also in Stop mode if they are clocked by LSE,

LSI or an external clock. The low-power timers are able to wakeup the devices from Stop mode.

The low-power timers support the following features:

16-bit up counter with 16-bit autoreload register

16-bit compare register

Configurable output: pulse, PWM

Continuous / one-shot mode

Selectable software / hardware input trigger

Selectable clock source:

Internal clock source: LSE, LSI, HSI or APB clock

External clock source over LPTIM input (working even with no internal clock source running, used by the

Pulse Counter Application)

Programmable digital glitch filter

Encoder mode

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3.34.5

3.34.6

3.34.7

3.35

3.36

STM32H7B0xB

Real-time clock (RTC)

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes.

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

•

•

•

•

SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features:

A 24-bit downcounter

Autoreload capability

Maskable system interrupt generation when the counter reaches 0

Programmable clock source.

Real-time clock (RTC)

•

•

•

•

•

The RTC is an independent BCD timer/counter. It supports the following features:

•

•

•

Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD

(binary-coded decimal) format.

Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.

Two programmable alarms.

On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock.

Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision.

Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy.

Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to V

BAT

mode.

17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period.

•

•

•

•

The RTC is supplied through a switch that takes power either from the V

DD

supply when present or from the V

BAT pin.

The RTC clock sources can be:

A 32.768 kHz external crystal (LSE)

An external resonator or oscillator (LSE)

The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)

The high-speed external clock (HSE) divided by 32.

The RTC is functional in V

BAT

mode and in all low-power modes when it is clocked by the LSE. When clocked by the LSI, the RTC is not functional in V

BAT

mode, but is functional in all low-power modes.

All RTC events (Alarm, Wakeup Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device from the low-power modes.

Tamper and backup registers (TAMP)

The TAMP main features are the following:

• 32 backup registers:

– The backup registers (TAMP_BKPxR) are implemented in the RTC domain that remains powered-on by V

BAT

when the V

DD

power is switched off.

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3.38

STM32H7B0xB

Inter-integrated circuit interface (I2C)

•

•

•

•

•

Three external tamper detection events

– Each external event can be configured to be active or passive

– External passive tampers with configurable filter and internal pull-up

Seven internal tamper events

Any tamper detection can generate an RTC timestamp event

Any tamper detection can erase the RTC backup registers, the backup SRAM and the memory regions protected by the on-the-fly decryption engine (OTFDEC)

Monotonic counter

Inter-integrated circuit interface (I

2

C)

•

•

•

•

•

The STM32H7B0xB embed four I 2 C interfaces.

The I 2 C bus interface handles communications between the microcontroller and the serial I 2 C bus. It controls all

I 2 C bus-specific sequencing, protocol, arbitration and timing.

The I2C peripheral supports:

•

•

I 2 C-bus specification and user manual rev. 5 compatibility:

– Slave and master modes, multimaster capability

– Standard-mode (Sm), with a bit rate up to 100 kbit/s

– Fast-mode (Fm), with a bit rate up to 400 kbit/s

– Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s and 20 mA output drive I/Os

– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

– Programmable setup and hold times

– Optional clock stretching

System management bus (SMBus) specification rev 2.0 compatibility:

– Hardware PEC (packet error checking) generation and verification with ACK control

– Address resolution protocol (ARP) support

– SMBus alert

Power system management protocol (PMBus ™ ) specification rev 1.1 compatibility

Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming.

Wakeup from Stop mode on address match

Programmable analog and digital noise filters

1-byte buffer with DMA capability

Universal synchronous/asynchronous receiver transmitter (USART)

•

•

•

•

The STM32H7B0xB devices have five embedded universal synchronous receiver transmitters (USART1,

USART2, USART3, USART6 and USART10) and five universal asynchronous receiver transmitters (UART4,

UART5, UART7, UART8 and UART9). Refer to the table below for a summary of USARTx and UARTx features.

These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. They provide hardware management of the CTS and RTS signals, and RS485 Driver Enable. They are able to communicate at speeds of up to 10Mbit/s.

USART1, USART2, USART3, USART6 and USART10 also provide Smartcard mode (ISO 7816 compliant) and

SPI-like communication capability.

The USARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode is enabled by software and is disabled by default.

All USART have a clock domain independent from the CPU clock, allowing the USARTx to wake up the MCU from Stop mode.The wakeup from Stop mode are programmable and can be done on:

Start bit detection

Any received data frame

A specific programmed data frame

Specific TXFIFO/RXFIFO status when FIFO mode is enabled.

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3.39

3.40

STM32H7B0xB

Low-power universal asynchronous receiver transmitter (LPUART)

All USART interfaces can be served by the DMA controller.

Table 5. USART features

X = supported.

USART modes/features

Hardware flow control for modem

Continuous communication using DMA

Multiprocessor communication

Synchronous mode (Master/Slave)

Smartcard mode

Single-wire Half-duplex communication

IrDA SIR ENDEC block

LIN mode

Dual clock domain and wakeup from low power mode

Receiver timeout interrupt

Modbus communication

Auto baud rate detection

Driver Enable

USART data length

Tx/Rx FIFO

Tx/Rx FIFO size

USART1/2/3/6/10

X

X

X

X

X

X

X

X

X

X

X

X

X

7, 8 and 9 bits

UART4/5/7/8/9

X

X

X

-

-

X

X

X

X

X

X

X

X

X X

16

Low-power universal asynchronous receiver transmitter (LPUART)

The device embeds one Low-power UART (LPUART1). The LPUART supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication.

The LPUART embeds a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode is enabled by software and is disabled by default.

The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode.

The wakeup from Stop mode are programmable and can be done on:

•

•

•

•

Start bit detection

Any received data frame

A specific programmed data frame

Specific TXFIFO/RXFIFO status when FIFO mode is enabled.

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption.

Higher speed clock can be used to reach higher baud rates.

LPUART interface can be served by the DMA controller.

Serial peripheral interfaces (SPI)/integrated interchip sound interfaces (I2S)

The devices feature up to six SPIs (SPI1/I2S1, SPI2/I2S2, SPI3/I2S3, SPI6/I2S6 and SPI4, SPI5) that allow communicating up to 125 Mbits/s in master and slave modes, in half-duplex, full-duplex and simplex modes. The

3-bit prescaler gives 8 master mode frequencies and the frame is configurable from 4 to 32 bits for SPI1/I2S1,

SPI2/I2S2, SPI3/I2S3, from 4 to 16 bits for the others. All SPI interfaces support NSS pulse mode, TI mode,

Hardware CRC calculation, and 16x 8-bit embedded Rx and Tx FIFOs (SPI1/I2S1, SPI2/I2S2, SPI3/I2S3) or 8x

8-bit embedded Rx and Tx FIFOs (SPI4, SPI5, SPI6/I2S6), all with DMA capability. .

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3.42

3.43

3.44

STM32H7B0xB

Serial audio interfaces (SAI)

Four standard I 2 S interfaces (multiplexed with SPI1, SPI2, SPI3, SPI6) are available. They can be operated in master or slave mode, in simplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported.

When one or all I 2 S interfaces is/are configured in master mode, the master clock can be output to the external

DAC/codec at 256 times the sampling frequency. All I 2 S interfaces support 16x 8-bit embedded Rx and Tx FIFOs with DMA capability.

Serial audio interfaces (SAI)

The devices embed two SAIs (SAI1, SAI2) that allow designing many stereo or mono audio protocols such as

I2S, LSB or MSB-justified, PCM/DSP, TDM or AC’97. An SPDIF output is available when the audio block is configured as a transmitter. To bring this level of flexibility and reconfigurability, the SAI contains two independent audio sub-blocks. Each block has it own clock generator and I/O line controller.

Audio sampling frequencies up to 192 kHz are supported.

One of the SAI supports up to 8 microphones thanks to an embedded PDM interface.

The SAI can work in master or slave configuration. The audio sub-blocks can be either receiver or transmitter and can work synchronously or asynchronously (with respect to the other one). The SAI can be connected with other

SAIs to work synchronously.

SPDIFRX receiver interface (SPDIFRX)

•

•

•

•

•

•

•

•

The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958 and IEC-61937. These standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up to 5.1).

The main SPDIFRX features are the following:

Up to 4 inputs available

Automatic symbol rate detection

Maximum symbol rate: 12.288 MHz

Stereo stream from 32 to 192 kHz supported

Supports Audio IEC-60958 and IEC-61937, consumer applications

Parity bit management

Communication using DMA for audio samples

Communication using DMA for control and user channel information

• Interrupt capabilities

The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and decode the incoming data stream. The user can select the wanted SPDIF input, and when a valid signal will be available, the SPDIFRX will re-sample the incoming signal, decode the Manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the CPU decoded data, and associated status flags.

The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms.

Single wire protocol master interface (SWPMI)

•

•

•

•

The single wire protocol master interface (SWPMI) is the master interface corresponding to the contactless frontend (CLF) defined in the ETSI TS 102 613 technical specification. The main features are: full-duplex communication mode automatic SWP bus state management (active, suspend, resume) configurable bit rate up to 2 Mbit/s automatic SOF, EOF and CRC handling

SWPMI can be served by the DMA controller.

Management data input/output (MDIO) slaves

The devices embed an MDIO slave interface it includes the following features:

DS13196 - Rev 6 page 31/199

3.45

3.46

3.47

STM32H7B0xB

SD/SDIO/MMC card host interfaces (SDMMC)

•

•

•

•

32 MDIO register addresses, each of which is managed using separate input and output data registers:

– 32 x 16-bit firmware read/write, MDIO read-only output data registers

– 32 x 16-bit firmware read-only, MDIO write-only input data registers

Configurable slave (port) address

Independently maskable interrupts/events:

– MDIO register write

– MDIO register read

– MDIO protocol error

Able to operate in and wake up from STOP mode

SD/SDIO/MMC card host interfaces (SDMMC)

Two SDMMC host interfaces are available. They support MultiMediaCard System Specification version 4.51 in three different databus modes: 1 bit (default), 4 bits and 8 bits.

One of the SDMMC interface can be supplied through a separate V

DDMMC at a different voltage level than all other I/Os.

supply. If required, it can thus operate

Both interfaces support the SD memory card specifications version 4.1. and the SDIO card specification version

4.0. in two different databus modes: 1 bit (default) and 4 bits.

Each SDMMC host interface supports only one SD/SDIO/MMC card at any one time and a stack of MMC Version

4.51 or previous.

The SDMMC host interface embeds a dedicated DMA controller allowing high-speed transfers between the interface and the SRAM.

Controller area network (FDCAN1, FDCAN2)

The controller area network (CAN) subsystem consists of two CAN modules, a shared message RAM memory and a clock calibration unit.

Both CAN modules (FDCAN1 and FDCAN2) are compliant with ISO 11898-1 (CAN protocol specification version

2.0 part A, B) and CAN FD protocol specification version 1.0.

FDCAN1 supports time triggered CAN (TTCAN) specified in ISO 11898-4, including event synchronized time-triggered communication, global system time, and clock drift compensation. FDCAN1 contains additional registers, specific to the time triggered feature. The CAN FD option can be used together with event-triggered and time-triggered CAN communication.

A 10 Kbyte message RAM memory implements filters, receive FIFOs, receive buffers, transmit event FIFOs, transmit buffers (and triggers for TTCAN). This message RAM is shared between the two FDCAN1 and FDCAN2 modules.

The common clock calibration unit is optional. It can be used to generate a calibrated clock for both FDCAN1 and

FDCAN2 from the HSI internal RC oscillator and the PLL, by evaluating CAN messages received by the FDCAN1.

Universal serial bus on-the-go high-speed (OTG_HS)

The devices embed an USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral that supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 Mbit/s) and a

UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s). When using the USB OTG_HS interface in

HS mode, an external PHY device connected to the ULPI is required.

The USB OTG_HS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification.

It features software-configurable endpoint setting and supports suspend/resume. The USB OTG_HS controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator.

DS13196 - Rev 6 page 32/199

3.48

3.49

STM32H7B0xB

High-definition multimedia interface (HDMI) - consumer electronics control (CEC)

•

•

•

The main features are:

•

•

•

Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing

Supports the session request protocol (SRP) and host negotiation protocol (HNP)

8 bidirectional endpoints

•

•

•

•

•

16 host channels with periodic OUT support

Software configurable to OTG1.3 and OTG2.0 modes of operation

USB 2.0 LPM (Link Power Management) support

Battery Charging Specification Revision 1.2 support

Internal FS OTG PHY support

• External HS or HS OTG operation supporting ULPI in SDR mode

The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the

60 MHz output.

Internal USB DMA

HNP/SNP/IP inside (no need for any external resistor)

For OTG/Host modes, a power switch is needed in case bus-powered devices are connected

High-definition multimedia interface (HDMI) - consumer electronics control

(CEC)

The device embeds a HDMI-CEC controller that provides hardware support for the consumer electronics control

(CEC) protocol (supplement 1 to the HDMI standard).

This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC controller to wake up the MCU from Stop mode on data reception.

Debug infrastructure

•

•

•

•

•

•

The devices offer a comprehensive set of debug and trace features to support software development and system integration.

• Breakpoint debugging

Code execution tracing

Software instrumentation

JTAG debug port

Serial-wire debug port

Trigger input and output

Serial-wire trace port

•

•

Trace port

Arm ® CoreSight ™ debug and trace components

The debug can be controlled via a JTAG/Serial-wire debug access port, using industry standard debugging tools.

The trace port performs data capture for logging and analysis.

DS13196 - Rev 6 page 33/199

4

STM32H7B0xB

Memory mapping

Memory mapping

Refer to the product line reference manual (RM0455) for details on the memory mapping as well as the boundary addresses for all peripherals.

DS13196 - Rev 6 page 34/199

5

Pin descriptions

Figure 4. LQFP64 (STM32H7B0xB without SMPS) pinout

STM32H7B0xB

Pin descriptions

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA

VDDA

PA0

PA1

PA2

8

9

10

11

5

6

7

12

13

14

15

16

1

2

3

4

LQFP64

VDD

VSS

VCAP

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC7

PC6

PB15

PB14

PB13

PB12

41

40

39

38

44

43

42

37

36

35

34

33

48

47

46

45

1.

The above figure shows the package top view.

DS13196 - Rev 6 page 35/199

DS13196 - Rev 6

Figure 5. LQFP100 (STM32H7B0xB without SMPS) pinout

STM32H7B0xB

Pin descriptions

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

PE2

PE3

PE4

PE5

PE6

VBAT

PC13

PC14-OSC32_ON

PC15-OSC32_OUT

VSS 10

VDD 11

PH0-OSC_IN 12

PH1-OSC_OUT 13

NRST 14

7

8

5

6

9

1

2

3

4

PC0 15

PC1 16

PC2_C 17

PC3_C 18

VSSA 19

VREF+ 20

VDDA 21

PA0 22

PA1 23

PA2 24

PA3 25

LQFP100

57

56

55

54

53

60

59

58

52

51

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

63

62

61

66

65

64

71

70

69

68

67

75

74

73

72

VDD

VSS

VCAP

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

PD15

PD14

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

1.

The above figure shows the package top view.

page 36/199

DS13196 - Rev 6

PE2

PE3

PE4

PE5

PE6

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PF0

PF1

PF2

PF10

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2_C

PC3_C

VDD

VSSA

VREF+

VDDA

PA0

PA1

PA2

PF3

PF4

PF5

VSS

VDD

PF6

PF7

PF8

PF9

31

32

33

34

27

28

29

30

35

36

21

22

23

24

25

26

13

14

15

16

17

18

19

20

7

8

9

10

11

12

5

6

1

2

3

4

Figure 6. LQFP144 (STM32H7B0xB without SMPS) pinout

STM32H7B0xB

Pin descriptions

LQPF144

VDD

VSS

VCAP

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

VDD33USB

VSS

PG8

PG7

PG6

PG5

PG4

PG3

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

PG2

PD15

PD14

VDD

VSS

PD13

PD12

103

102

101

100

99

108

107

106

105

104

93

92

91

90

89

88

98

97

96

95

94

76

75

74

73

80

79

78

77

84

83

82

81

87

86

85

1.

The above figure shows the package top view.

page 37/199

Figure 7. LQFP176 (STM32H7B0xB without SMPS) pinout

STM32H7B0xB

Pin descriptions

37

38

39

40

41

42

43

44

31

32

33

34

35

36

25

26

27

28

29

30

20

21

22

23

24

9

10

11

12

13

14

15

16

17

18

19

6

7

8

1

2

3

4

5

PC14-OSC32_IN

PC15-OSC32_OUT

PI9

PI10

PI11

VSS

VDD

PF0

PF1

PF2

PF3

PF4

PF5

PE2

PE3

PE4

PE5

PE6

VBAT

PI8

PC13

VSS

VDD

PF6

PF7

PF8

PF9

PF10

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2_C

PC3_C

VDD

VSSA

VREF+

VDDA

PA0

PA1

PA2

PH2

PH3

LQFP176

1.

The above figure shows the package top view.

PI1

PI0

PH15

PH14

PH13

VSS

PG8

PG7

PG6

PG5

PG4

PG3

PG2

VDD

VSS

VCAP

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

VDD33USB

PD15

PD14

VDD

VSS

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

VDD

VSS

PH12

122

121

120

119

118

117

116

115

114

127

126

125

124

123

132

131

130

129

128

113

112

111

110

109

108

107

106

98

97

96

95

94

93

92

91

90

89

105

104

103

102

101

100

99

DS13196 - Rev 6 page 38/199

DS13196 - Rev 6

STM32H7B0xB

Pin descriptions

Figure 8. UFBGA169 (STM32H7B0xB with SMPS) ballout

K

L

H

J

M

N

F

G

D

E

A

B

C

1

PE4

PC15-

OSC32_

OUT

PC14-

OSC32_IN

VDD

VLXSMPS VSSSMPS VBAT

VDDSMPS VFBSMPS

VDD

PH0-

OSC_IN

VSS

PH1-

OSC_OUT

PC0 PC1

PC3_C

VDDA

VDD

PA2

2

PE2

PE3

PE6

VSS

PC2_C

VREF+

VSS

PH2

3

VDD

VSS

PE5

PC13

PF0

PF4

PF10

VSSA

PA0_C

PA1_C

PH3

PA3

4

VCAP

PF2

PF6

PF8

PC3

PA1

PA5

VDDLDO

PDR_ON

PE1

PF1

VSS

VDD

5

PB6

6

VDDMMC

PF5

PF9

PC2

PA0

PA6

PB1

PB8

PB9

PE0

PF3

PB0

PC5

PF7

NRST

PA4

PA7

PC4

PB2

PB4

PB5

PB7

BOOT0

PF11

PF12

7

VDD

VSS

PG14

PG13

PG15

PB3

PF13

PF14

PF15

PG0

PG1

VSS

VDD

8

PG10

PG4

PE7

PE8

PE9

PE13

PE12

PG11

PG9

PD7

PG12

PE10

PE11

9

PD5

PC6

PG6

PG2

PE14

PH10

PB10

PD6

PD4

PD3

PD2

PB11

PE15

10

VDD

11

PC12

12

PC10

13

PH14

PC7

PG7

PG3

PD11

PH12

PH11

VSS

PD1

PD0

PA10

VDDLDO

VCAP

PC11

PA15

PA14

VSS

PH13

VDD

PA13

PA9

VDDLDO VCAP

PA8

PC8

PA12

PA11 PC9

PG8 VDD50USB VDD33USB

PG5

PD13

PD9

PB13

VSS

VDD

VSS

PD15

PD10

VSS

PD8

PB12

VDD

PD14

PD12

VDD

PB15

PB14

1.

The above figure shows the package top view.

page 39/199

STM32H7B0xB

Pin descriptions

P

R

M

N

1

VSS

Figure 9. UFBGA176+25 (STM32H7B0xB with SMPS) ballout

2 3 4

PB8 VDDLDO VCAP

5

PB6

6

PB3

7

PG11 A

G

H

B

C

D

E

PC13 VSS PE2

PC15-

OSC32_

OUT

PC14-

OSC32_IN

PE5

VSS VBAT PE6

PE1 BOOT0

PDR_ON

VDD

MMC

PB5

VSS

VDD

F

PE4 PE3 PB9

VLX

SMPS

VDD

SMPS

PF6

VSS

SMPS

VFB

SMPS

PF4

PF1

PF2

PF5

PE0

PF0

VDD

PF3

PB7 PB4

VSS

VSS

VSS

PG13

PG14

PG15

VSS

VSS

VSS

8

PG9

PD7

PG10

PG12

VSS

VSS

VSS

9

PD3

PD5

PD4

PD6

VSS

VSS

VSS

10

PD1

PD2

PD0

VSS

VSS

VSS

VSS

11

PA15

PC12

PC11

VDD

12 13 14

PA14 VDDLDO VCAP

PH14 PA13 PA8

15

VSS

PA12

PC10 PH13 PA10 PA11

PH15

VDD

PA9 PC8

VSS

PG8

VDD33

USB

PG7

PG6

PG4

VDD

PC9

PG3

PC6

PD14

PC7

VDD50

USB

PG5

PG2

PD13

J

K

L

PH0-

OSC_IN

PH1-

OSC_

OUT

NRST

PF8

VSS

PF7

PF10

PF9

VDD

PC0 PC1 VREF−

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

PD15 PD11

VSS PD9

VSS

PB15

PD12

PB14

VDD PD10 PD8 PB13

PC2 PC3 VREF+

PC2_C PC3_C VSSA

VDDA

PH2

VDD VSS

PA3 PA7

PC5

PF11

PA0

VSS

PA1 PA1_C PH4

PA2 PA0_C PH3

PA4

PH5

PA5

PC4

PB2

PA6

PB1

PE8

PG0

PB0

VDD VSS

PG1 PF15

PE7 PB11

PE10 PF14

PH7

PF13

PE14 PH11

PB10 PH8

PH9 PB12

PH10 PH12

PF12

PE9

PE12 PE13 PE15 PH6

PE11 VCAP VDDLDO VSS

1.

The above figure shows the package top view.

2.

The devices with SMPS correspond to commercial code STM32H7B0IIK6Q.

Name

Pin name

Pin type

Table 6. Legend/abbreviations used in the pinout table

I/O structure

Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

S

I

Supply pin

Input only pin

I/O

ANA

FT

TT

B

RST

_f

Input / output pin

Analog-only Input

5 V tolerant I/O

3.3 V tolerant I/O

Dedicated BOOT0 pin

Bidirectional reset pin with embedded weak pull-up resistor

Option for TT and FT I/Os

I2C FM+ option

DS13196 - Rev 6 page 40/199

STM32H7B0xB

Pin descriptions

Name

I/O structure

Abbreviation

_a

_u

_h0

_h1

_h2

(1)

(1)

(1)

Definition analog option (supplied by V

DDA

)

USB option (supplied by

V

DD33

USB)

High-speed low voltage (mainly

SDMMC2 on V

DDMMC

power rail)

High-speed low voltage (mainly for OCTOSPI)

High-speed low voltage (mainly for FMC)

Notes

_h3 (1)

High-speed low voltage

_s

Secondary supply (supplied by

V

DDMMC

) (2)

Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset.

Functions selected through GPIOx_AFR registers

Functions directly selected/enabled through peripheral registers

Pin functions

Alternate functions

Additional functions

1. Refer to SYSCFG_CCCSR register in the device reference manual for how to set a group of I/Os in

High-speed low-voltage mode. Depending on the chosen I/Os (for example OCTOSPI), it can belong to several groups of I/Os and several HSLVx bits need to be set (refer to Table Pin/ball definition). Take care that the VDDIO_HSLV and/or VDDMMC_HSLV option bits must also be set.

2. Refer to the table Features and peripheral counts for the list of packages featuring a V

DDMMC supply pad.

separate

Table 7. STM32H7B0xB pin/ball definition

Pin/ball name (1) (2)

Pin name

(function after reset)

Pin type

I/O structure

Alternate functions Additional functions

A2

B2

A1

C3

B2

B1

-

-

-

C3 D3 -

1

2

3

4

1

2

3

4

1

2

3

4

C2

B3

A3

E3

E3

A1

-

E2

-

-

-

1

5

-

-

6

5

6

-

-

5

-

-

6

PE2

PE3

PE4

PE5

PE6

VSS

VDD

VBAT

I/O

S

S

S

I/O

I/O

I/O

I/O

-

-

-

FT_h2

FT_h2

FT_h2

FT_h2

FT_h2

TRACECLK, SAI1_CK1, SPI4_SCK,

SAI1_MCLK_A, OCTOSPIM_P1_IO2,

USART10_RX, FMC_A23, EVENTOUT

TRACED0, TIM15_BKIN, SAI1_SD_B,

USART10_TX, FMC_A19, EVENTOUT

TRACED1, SAI1_D2, DFSDM1_DATIN3,

TIM15_CH1N, SPI4_NSS, SAI1_FS_A,

FMC_A20, DCMI_D4/PSSI_D4,

LCD_B0, EVENTOUT

TRACED2, SAI1_CK2,

DFSDM1_CKIN3, TIM15_CH1,

SPI4_MISO, SAI1_SCK_A, FMC_A21,

DCMI_D6/PSSI_D6, LCD_G0,

EVENTOUT

TRACED3, TIM1_BKIN2, SAI1_D1,

TIM15_CH2, SPI4_MOSI, SAI1_SD_A,

SAI2_MCK_B, TIM1_BKIN2_COMP12,

FMC_A22, DCMI_D7/PSSI_D7,

LCD_G1, EVENTOUT

-

-

-

-

-

-

-

-

-

-

-

DS13196 - Rev 6 page 41/199

STM32H7B0xB

Pin descriptions

Pin/ball name (1) (2)

Pin name

(function after reset)

Pin type

I/O structure

Alternate functions Additional functions

D2

-

A15

-

-

-

-

-

-

7

VSS

PI8

7

-

8

9

-

-

-

-

10

11

-

-

-

-

-

-

-

-

-

-

-

-

-

D3

-

C1

B1

C1

C2

D2

D1

2

-

3

4

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

H2

H3

E1

E4

H1

G3

H4

-

D10

D11

F2

F1

G1

G2

F4

F3

J3

-

-

G3

F5

B7

A7

G4

F4

E5

-

-

D1

E2

E1

F1

F2

F3

E4

F6

7

8

-

9

-

-

14

15

16

17

18

12

13

-

-

-

-

-

-

-

10

11

19

8 PC13 I/O

12

20

21

22

23

24

18

19

13

-

-

14

15

-

-

16

17

-

9

10

11

VSS

PC14-OSC32_IN

(OSC32_IN)

PC15-

OSC32_OUT

(OSC32_OUT)

PI9

S

I/O

I/O

I/O

PI10

PF2

PF3

PF4

PF5

VSS

VDD

PF6

PI11

VSS

VDD

VSSSMPS

VLXSMPS

VDDSMPS

VFBSMPS

PF0

PF1

I/O

I/O

I/O

I/O

I/O

S

S

I/O

I/O

S

S

S

S

S

S

I/O

I/O

25 PF7 I/O

S

I/O

-

FT

FT

-

FT

-

EVENTOUT

EVENTOUT

-

EVENTOUT

FT_h2

FT_h2

FT_h2

FT_h2

-

-

FT_h1

FT

-

-

-

-

-

-

FT_f

FT_f

FT

FT_h2

FT_h2

FT_h1

EVENTOUT

OCTOSPIM_P2_IO0, UART4_RX,

FDCAN1_RX, FMC_D30, LCD_VSYNC,

EVENTOUT

OCTOSPIM_P2_IO1, FMC_D31,

PSSI_D14, LCD_HSYNC, EVENTOUT

OCTOSPIM_P2_IO2, LCD_G6,

OTG_HS_ULPI_DIR, PSSI_D15,

EVENTOUT

-

-

-

-

-

-

I2C2_SDA, OCTOSPIM_P2_IO0,

FMC_A0, EVENTOUT

I2C2_SCL, OCTOSPIM_P2_IO1,

FMC_A1, EVENTOUT

I2C2_SMBA, OCTOSPIM_P2_IO2,

FMC_A2, EVENTOUT

OCTOSPIM_P2_IO3, FMC_A3,

EVENTOUT

OCTOSPIM_P2_CLK, FMC_A4,

EVENTOUT

OCTOSPIM_P2_NCLK, FMC_A5,

EVENTOUT

-

-

TIM16_CH1, SPI5_NSS, SAI1_SD_B,

UART7_Rx, OCTOSPIM_P1_IO3,

EVENTOUT

TIM17_CH1, SPI5_SCK,

SAI1_MCLK_B, UART7_Tx,

OCTOSPIM_P1_IO2, EVENTOUT

-

TAMP_IN2/

TAMP_OUT3,

RTC_OUT2, WKUP4

TAMP_IN1/

TAMP_OUT2/

TAMP_OUT3,

RTC_OUT1/RTC_TS,

WKUP3

-

OSC32_IN

OSC32_OUT

-

-

-

-

-

-

-

-

-

-

WKUP5

-

-

-

-

-

-

-

-

DS13196 - Rev 6 page 42/199

STM32H7B0xB

Pin descriptions

Pin/ball name (1) (2)

Pin name

(function after reset)

Pin type

I/O structure

Alternate functions Additional functions

H4

G5

H3

H1

H2

G6

J1

J2

H5

(3)

K2

(3)

J4

(3)

K1 (3)

G1

G2

J3

-

L2

L1

J5

K3

(3)

(3)

J2

J4

K3

J1

K1

L1

L2

L3

M1

N1

(3)

M2

(3)

(3)

P1

(3)

R3 (3)

-

5

6

7

8

10

11

14

-

-

-

-

9

-

-

16

-

17 (4) 28 (4)

-

N2 (3)

E12

F6

N3

L4

M3

M4

-

-

-

13

-

-

12

18 (4)

-

-

19

-

20

21

-

12

13

14

15

22

-

20

21

22

23

24

25

26

27

29

34

-

-

(4)

30

-

31

-

32

33

26

27

34

35

(4)

(4)

36

-

37

-

38

39

PF8

PF9

28

29

30

31

32

PF10

PH0-

OSC_IN(PH0)

PH1-OSC_OUT

(PH1)

NRST

PC0

I/O

I/O

I/O

I/O

I/O

33

-

-

40

-

PC1

PC2

PC2_C

PC3

PC3_C

VDD

VSS

VSSA

VREF-

VREF+

VDDA

PA0

PA0_C

I/O

I/O

I/O

I/O

ANA

I/O

ANA

S

S

S

S

S

S

I/O

ANA

FT_h1

FT_h1

FT_h1

FT

FT

RST

FT_a

FT_ah0

FT_a

TT_a

FT_a

TT_a

FT_a

TT_a

TIM16_CH1N, SPI5_MISO,

SAI1_SCK_B, UART7_RTS,

TIM13_CH1, OCTOSPIM_P1_IO0,

EVENTOUT

TIM17_CH1N, SPI5_MOSI,

SAI1_FS_B, UART7_CTS, TIM14_CH1,

OCTOSPIM_P1_IO1, EVENTOUT

TIM16_BKIN, SAI1_D3, PSSI_D15,

OCTOSPIM_P1_CLK, DCMI_D11/

PSSI_D11, LCD_DE, EVENTOUT

EVENTOUT

-

-

-

OSC_IN

EVENTOUT OSC_OUT

-

DFSDM1_CKIN0, DFSDM1_DATIN4,

SAI2_FS_B, FMC_A25,

OTG_HS_ULPI_STP, LCD_G2,

FMC_SDNWE, LCD_R5, EVENTOUT

TRACED0, SAI1_D1,

DFSDM1_DATIN0, DFSDM1_CKIN4,

SPI2_MOSI/I2S2_SDO, SAI1_SD_A,

SDMMC2_CK, OCTOSPIM_P1_IO4,

MDIOS_MDC, LCD_G5, EVENTOUT

PWR_CSTOP, DFSDM1_CKIN1,

SPI2_MISO/I2S2_SDI,

DFSDM1_CKOUT, OCTOSPIM_P1_IO2,

OTG_HS_ULPI_DIR,

OCTOSPIM_P1_IO5, FMC_SDNE0,

EVENTOUT

-

ADC12_INP10

ADC12_INP11,

ADC12_INN10,

TAMP_IN3, WKUP6

ADC12_INP12,

ADC12_INN11

-

ADC2_INP0,

ADC2_INN1

PWR_CSLEEP, DFSDM1_DATIN1,

SPI2_MOSI/I2S2_SDO,

OCTOSPIM_P1_IO0,

OTG_HS_ULPI_NXT,

OCTOSPIM_P1_IO6, FMC_SDCKE0,

EVENTOUT

-

-

-

-

-

-

-

TIM2_CH1/TIM2_ETR, TIM5_CH1,

TIM8_ETR, TIM15_BKIN,

SPI6_NSS/I2S6_WS, USART2_CTS/

USART2_NSS, UART4_TX,

SDMMC2_CMD, SAI2_SD_B,

EVENTOUT

ADC12_INP13,

ADC12_INN12

ADC2_INP1

-

-

-

-

-

-

ADC1_INP16,

WKUP1

-

ADC1_INP0,

ADC1_INN1

DS13196 - Rev 6 page 43/199

STM32H7B0xB

Pin descriptions

Pin/ball name (1) (2)

Pin name

(function after reset)

Pin type

I/O structure

Alternate functions Additional functions

-

-

N2

M1

M2

M3

K4 (3)

P2

(3)

15 23

L3

(3)

N1

P3

(3)

R2

-

16

-

24

35

-

36

41

-

42

N4

G4

F7

R4

P4

R5 -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

45

46

43

-

-

44

N3

M4

N4

H6

N5 17 25

F8

H12

P5

18

19

20

26

27

28

37

38

39

40

47

48

49

50

L4 P6 21 29 41 51

K5 R7 22 30 42 52

J6 N6 23 31 43 53

K6 R6 24 32 44 54

N5 M7 25 33 45 55

PA1

PA1_C

PA2

PH2

VDD

VSS

PH3

PH4

PH5

PA3

VSS

VDD

PA4

PA5

PA6

PA7

PC4

PC5

S

S

I/O

I/O

I/O

I/O

S

S

I/O

I/O

ANA

I/O

I/O

I/O

I/O

I/O

I/O

I/O

FT_ah1

TT_a

FT_a

FT_h2

-

-

FT_ah2

FT_fa

FT_fa

FT_ah1

-

-

TT_a

TT_ah0

TT_ah1

FT_ah1

FT_a

FT_ah1

TIM2_CH2, TIM5_CH2, LPTIM3_OUT,

TIM15_CH1N, USART2_RTS,

UART4_RX, OCTOSPIM_P1_IO3,

SAI2_MCK_B, OCTOSPIM_P1_DQS,

LCD_R2, EVENTOUT

-

TIM2_CH3, TIM5_CH3, TIM15_CH1,

DFSDM2_CKIN1, USART2_TX,

SAI2_SCK_B, MDIOS_MDIO, LCD_R1,

EVENTOUT

LPTIM1_IN2, OCTOSPIM_P1_IO4,

SAI2_SCK_B, FMC_SDCKE0, LCD_R0,

EVENTOUT

-

-

OCTOSPIM_P1_IO5, SAI2_MCK_B,

FMC_SDNE0, LCD_R1, EVENTOUT

I2C2_SCL, LCD_G5,

OTG_HS_ULPI_NXT, PSSI_D14,

LCD_G4, EVENTOUT

I2C2_SDA, SPI5_NSS, FMC_SDNWE,

EVENTOUT

TIM2_CH4, TIM5_CH4,

OCTOSPIM_P1_CLK, TIM15_CH2,

I2S6_MCK, USART2_RX, LCD_B2,

OTG_HS_ULPI_D0, LCD_B5,

EVENTOUT

-

-

TIM5_ETR, SPI1_NSS/I2S1_WS,

SPI3_NSS/I2S3_WS, USART2_CK,

SPI6_NSS/I2S6_WS, DCMI_HSYNC/

PSSI_DE, LCD_VSYNC, EVENTOUT

PWR_NDSTOP2, TIM2_CH1/

TIM2_ETR, TIM8_CH1N, SPI1_SCK/

I2S1_CK, SPI6_SCK/I2S6_CK,

OTG_HS_ULPI_CK, PSSI_D14,

LCD_R4, EVENTOUT

TIM1_BKIN, TIM3_CH1,

TIM8_BKIN, SPI1_MISO/I2S1_SDI,

OCTOSPIM_P1_IO3, SPI6_MISO/

I2S6_SDI, TIM13_CH1,

TIM8_BKIN_COMP12, MDIOS_MDC,

TIM1_BKIN_COMP12, DCMI_PIXCLK/

PSSI_PDCK, LCD_G2, EVENTOUT

TIM1_CH1N, TIM3_CH2, TIM8_CH1N,

DFSDM2_DATIN1, SPI1_MOSI/

I2S1_SDO, SPI6_MOSI/I2S6_SDO,

TIM14_CH1, OCTOSPIM_P1_IO2,

FMC_SDNWE, LCD_VSYNC,

EVENTOUT

DFSDM1_CKIN2, I2S1_MCK,

SPDIFRX1_IN2, FMC_SDNE0,

LCD_R7, EVENTOUT

SAI1_D3, DFSDM1_DATIN2, PSSI_D15,

SPDIFRX1_IN3, OCTOSPIM_P1_DQS,

FMC_SDCKE0, COMP1_OUT, LCD_DE,

EVENTOUT

ADC1_INP17,

ADC1_INN16

ADC1_INP1

ADC1_INP14,

WKUP2

-

-

-

-

-

-

-

-

ADC1_INP15

ADC1_INP18,

DAC1_OUT1

ADC1_INP19,

ADC1_INN18,

DAC1_OUT2

ADC12_INP3,

DAC2_OUT1

ADC12_INP7,

ADC12_INN3,

OPAMP1_VINM

ADC12_INP4,

OPAMP1_VOUT,

COMP1_INM

ADC12_INP8,

ADC12_INN4,

OPAMP1_VINM

DS13196 - Rev 6 page 44/199

STM32H7B0xB

Pin descriptions

Pin/ball name (1) (2)

Pin name

(function after reset)

Pin type

I/O structure

Alternate functions Additional functions

N7

M7

K4

F9

-

-

-

-

-

-

-

M5 R8 26 34 46 56

L5 M8 27 35 47 57

L6 P7 28 36 48 58

N7

R10

N10

P8

F12

M5

N9

P11

F10

L12

N11

P9

M6

H7

J7

K7

-

-

L7

N6

-

-

G7

G8

-

-

-

-

-

-

-

-

-

-

-

-

49

54

55

56

-

-

57

50

51

52

53

58

-

-

-

-

-

-

-

-

-

-

-

37

59

64

65

66

-

-

67

60

61

62

63

68

H8 N8 38 59 69

J8

M11

N11

M8

R11

G6

M9

R9

-

-

-

-

39

-

-

40

60

61

62

63

70

71

72

73

VDD

VSS

PB0

PB1

PB2

PF11

PF14

PF15

PG0

VSS

VDD

PG1

PF12

VSS

VDD

PF13

PE7

PE8

PE9

VSS

VDD

PE10

S

S

I/O

I/O

I/O

I/O

S

S

I/O

I/O

S

S

I/O

I/O

I/O

I/O

I/O

I/O

I/O

S

S

I/O

-

-

FT_ah0

FT_ah0

FT_ah1

FT_ah1

FT_ah2

-

-

FT_ah2

FT_fah2

FT_fh2

FT_h2

-

-

FT_h2

FT_ah2

FT_ah2

FT_ah2

-

-

FT_ah2

-

-

TIM1_CH2N, TIM3_CH3,

TIM8_CH2N, DFSDM2_CKOUT,

DFSDM1_CKOUT, UART4_CTS,

LCD_R3, OTG_HS_ULPI_D1,

OCTOSPIM_P1_IO1, LCD_G1,

EVENTOUT

TIM1_CH3N, TIM3_CH4,

TIM8_CH3N, DFSDM1_DATIN1,

LCD_R6, OTG_HS_ULPI_D2,

OCTOSPIM_P1_IO0, LCD_G0,

EVENTOUT

RTC_OUT2, SAI1_D1,

DFSDM1_CKIN1, SAI1_SD_A,

SPI3_MOSI/I2S3_SDO,

OCTOSPIM_P1_CLK,

OCTOSPIM_P1_DQS, EVENTOUT

SPI5_MOSI, OCTOSPIM_P1_NCLK,

SAI2_SD_B, FMC_SDNRAS,

DCMI_D12/PSSI_D12, EVENTOUT

OCTOSPIM_P2_DQS, FMC_A6,

EVENTOUT

-

-

DFSDM1_DATIN6, I2C4_SMBA,

FMC_A7, EVENTOUT

DFSDM1_CKIN6, I2C4_SCL, FMC_A8,

EVENTOUT

I2C4_SDA, FMC_A9, EVENTOUT

OCTOSPIM_P2_IO4, UART9_RX,

FMC_A10, EVENTOUT

-

-

OCTOSPIM_P2_IO5, UART9_TX,

FMC_A11, EVENTOUT

TIM1_ETR, DFSDM1_DATIN2,

UART7_Rx, OCTOSPIM_P1_IO4,

FMC_D4/FMC_DA4, EVENTOUT

TIM1_CH1N, DFSDM1_CKIN2,

UART7_Tx, OCTOSPIM_P1_IO5,

FMC_D5/FMC_DA5, COMP2_OUT,

EVENTOUT

TIM1_CH1, DFSDM1_CKOUT,

UART7_RTS, OCTOSPIM_P1_IO6,

FMC_D6/FMC_DA6, EVENTOUT

-

-

TIM1_CH2N, DFSDM1_DATIN4,

UART7_CTS, OCTOSPIM_P1_IO7,

FMC_D7/FMC_DA7, EVENTOUT

-

-

ADC12_INP9,

ADC12_INN5,

OPAMP1_VINP,

COMP1_INP

ADC12_INP5,

COMP1_INM

COMP1_INP

ADC1_INP2

ADC1_INP6,

ADC1_INN2

-

-

ADC2_INP2

ADC2_INP6,

ADC2_INN2

-

-

-

-

OPAMP2_VINM

OPAMP2_VOUT,

COMP2_INM

OPAMP2_VINM

OPAMP2_VINP,

COMP2_INP

-

-

COMP2_INM

DS13196 - Rev 6 page 45/199

STM32H7B0xB

Pin descriptions

Pin/ball name (1) (2)

Pin name

(function after reset)

Pin type

I/O structure

Alternate functions Additional functions

N8 R12 41 64 74

L8 P12 42 65 75

K8 P13 43 66 76

J9

N9

M12 -

P14 -

44

45

67

68

77

78

L9 N12 29 46 69 79

-

K9

M9

N10

-

M10

-

-

-

-

-

30

31

-

32

-

-

-

P10

R13

M10

R14

-

P15

M11

N13

47

48

49

-

50

-

-

-

M14 -

N14 -

-

L10

K10

L12

L13

M13

N15

G10

-

-

-

-

-

-

-

-

-

-

70

71

-

-

72

-

-

-

-

-

-

-

86

87

80

81

-

-

82

83

84

85

88

89

90

91

PE13

PE14

PE15

PE11

PE12

PB10

PB11

VCAP

VSS

VDDLDO

VDD

PH6

PH7

PH8

PH9

PH10

PH11

PH12

VSS

VDD

I/O

I/O

I/O

I/O

I/O

S

S

S

S

I/O

I/O

I/O

I/O

I/O

S

S

I/O

I/O

I/O

I/O

-

-

-

-

FT

FT_ah2

FT_h2

FT_h2

FT_h2

FT_h2

FT_f

FT_f

FT_f

FT_fh2

FT_h2

FT_h2

FT_fh2

FT_fh2

-

-

TIM1_CH2, DFSDM1_CKIN4,

SPI4_NSS, SAI2_SD_B,

OCTOSPIM_P1_NCS, FMC_D8/

FMC_DA8, LCD_G3, EVENTOUT

TIM1_CH3N, DFSDM1_DATIN5,

SPI4_SCK, SAI2_SCK_B, FMC_D9/

FMC_DA9, COMP1_OUT, LCD_B4,

EVENTOUT

TIM1_CH3, DFSDM1_CKIN5,

SPI4_MISO, SAI2_FS_B, FMC_D10/

FMC_DA10, COMP2_OUT, LCD_DE,

EVENTOUT

TIM1_CH4, SPI4_MOSI, SAI2_MCK_B,

FMC_D11/FMC_DA11, LCD_CLK,

EVENTOUT

TIM1_BKIN, USART10_CK, FMC_D12/

FMC_DA12, TIM1_BKIN_COMP12,

LCD_R7, EVENTOUT

TIM2_CH3, LPTIM2_IN1, I2C2_SCL,

SPI2_SCK/I2S2_CK, DFSDM1_DATIN7,

USART3_TX, OCTOSPIM_P1_NCS,

OTG_HS_ULPI_D3, LCD_G4,

EVENTOUT

TIM2_CH4, LPTIM2_ETR, I2C2_SDA,

DFSDM1_CKIN7, USART3_RX,

OTG_HS_ULPI_D4, LCD_G5,

EVENTOUT

-

-

-

-

TIM12_CH1, I2C2_SMBA, SPI5_SCK,

FMC_SDNE1, DCMI_D8/PSSI_D8,

EVENTOUT

I2C3_SCL, SPI5_MISO, FMC_SDCKE1,

DCMI_D9/PSSI_D9, EVENTOUT

TIM5_ETR, I2C3_SDA, FMC_D16,

DCMI_HSYNC/PSSI_DE, LCD_R2,

EVENTOUT

TIM12_CH2, I2C3_SMBA, FMC_D17,

DCMI_D0/PSSI_D0, LCD_R3,

EVENTOUT

TIM5_CH1, I2C4_SMBA, FMC_D18,

DCMI_D1/PSSI_D1, LCD_R4,

EVENTOUT

TIM5_CH2, I2C4_SCL, FMC_D19,

DCMI_D2/PSSI_D2, LCD_R5,

EVENTOUT

TIM5_CH3, I2C4_SDA, FMC_D20,

DCMI_D3/PSSI_D3, LCD_R6,

EVENTOUT

-

-

COMP2_INP

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

DS13196 - Rev 6 page 46/199

STM32H7B0xB

Pin descriptions

Pin/ball name (1) (2)

Pin name

(function after reset)

Pin type

I/O structure

Alternate functions Additional functions

N12

L11

N13

M13

K13 J15 59 81 100

J11

J12

-

-

H9

H12

H13

J13

M12

K11

K12

-

J10

M15

L15 34

K15

K14

H15

R1

-

H14

J12

D6

G7

G15

L14

K13

L13

H6

J13

33

35

36

-

-

-

-

-

-

-

-

-

-

-

-

-

51

52

53

54

57

-

58

55

56

60

62

-

-

-

-

-

61

73

74

75

76

79

-

80

77

78

92

93

94

95

101

105

-

-

106

102

103

104

82

86

-

-

87

83

84

85

98

-

99

96

97

PB12

PB13

PB14

PD13

VSS

VDD

PD14

PD15

VSS

VSS

PG2

PB15

PD8

PD9

PD10

VSS

PD11

PD12

I/O

I/O

S

S

I/O

S

S

I/O

I/O

S

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

-

-

FT_h2

FT_h2

-

-

FT_h2

FT_h1

FT_h0

FT_h0

FT_h0

FT_h2

FT_h2

FT_h2

-

FT_h2

FT_fh2

FT_fh2

TIM1_BKIN, OCTOSPIM_P1_NCLK,

I2C2_SMBA, SPI2_NSS/

I2S2_WS, DFSDM1_DATIN1,

USART3_CK, FDCAN2_RX,

OTG_HS_ULPI_D5, DFSDM2_DATIN1,

TIM1_BKIN_COMP12, UART5_RX,

EVENTOUT

TIM1_CH1N, LPTIM2_OUT,

DFSDM2_CKIN1, SPI2_SCK/I2S2_CK,

DFSDM1_CKIN1, USART3_CTS/

USART3_NSS, FDCAN2_TX,

OTG_HS_ULPI_D6, SDMMC1_D0,

DCMI_D2/PSSI_D2, UART5_TX,

EVENTOUT

TIM1_CH2N, TIM12_CH1, TIM8_CH2N,

USART1_TX, SPI2_MISO/I2S2_SDI,

DFSDM1_DATIN2, USART3_RTS,

UART4_RTS, SDMMC2_D0, LCD_CLK,

EVENTOUT

RTC_REFIN, TIM1_CH3N, TIM12_CH2,

TIM8_CH3N, USART1_RX, SPI2_MOSI/

I2S2_SDO, DFSDM1_CKIN2,

UART4_CTS, SDMMC2_D1, LCD_G7,

EVENTOUT

DFSDM1_CKIN3, USART3_TX,

SPDIFRX1_IN1, FMC_D13/FMC_DA13,

EVENTOUT

DFSDM1_DATIN3, USART3_RX,

FMC_D14/FMC_DA14, EVENTOUT

DFSDM1_CKOUT, DFSDM2_CKOUT,

USART3_CK, FMC_D15/FMC_DA15,

LCD_B3, EVENTOUT

-

LPTIM2_IN2, I2C4_SMBA,

USART3_CTS/USART3_NSS,

OCTOSPIM_P1_IO0, SAI2_SD_A,

FMC_A16/FMC_CLE, EVENTOUT

LPTIM1_IN1, TIM4_CH1, LPTIM2_IN1,

I2C4_SCL, USART3_RTS,

OCTOSPIM_P1_IO1, SAI2_FS_A,

FMC_A17/FMC_ALE, DCMI_D12/

PSSI_D12, EVENTOUT

LPTIM1_OUT, TIM4_CH2, I2C4_SDA,

OCTOSPIM_P1_IO3, SAI2_SCK_A,

UART9_RTS, FMC_A18, DCMI_D13/

PSSI_D13, EVENTOUT

-

-

TIM4_CH3, UART8_CTS, UART9_RX,

FMC_D0/FMC_DA0, EVENTOUT

TIM4_CH4, UART8_RTS, UART9_TX,

FMC_D1/FMC_DA1, EVENTOUT

-

-

TIM8_BKIN, TIM8_BKIN_COMP12,

FMC_A12, EVENTOUT

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

DS13196 - Rev 6 page 47/199

STM32H7B0xB

Pin descriptions

Pin/ball name (1) (2)

Pin name

(function after reset)

Pin type

I/O structure

Alternate functions Additional functions

H10

C12

C13

F8

H11

G9

G10

G11

-

G12

G13

F9

F10

F12

F11

-

H13

H10

-

G14

F15

F14

G13

G12

J6

E15

F13

E14 37

D15

D14

E13

J7

38

-

-

-

-

-

-

-

-

-

-

-

-

39

-

-

-

-

-

-

-

-

-

-

-

-

63

64

65

66

-

E12 B14 40 67

E11 D13 41 68

88

-

-

89

90

91

92

93

94

-

95

112

113

-

114

PG8

VSS

VDD50USB

VDD33USB

96

97

98

99

-

115

116

117

118

-

100 119

101

107

-

-

108

109

110

111

120

PG3

VSS

VDD

PG4

PG5

PG6

PG7

PC6

PC7

PC8

PC9

VSS

PA8

PA9

I/O

S

S

I/O

I/O

I/O

S

I/O

I/O

I/O

S

S

S

I/O

I/O

I/O

I/O

I/O

FT_h2

-

-

FT_h2

FT_h2

FT_h2

FT_h2

FT_h2

-

-

-

FT_h0

FT_h0

FT_h0

FT_fh0

-

FT_fh0

FT_u

TIM8_BKIN2, TIM8_BKIN2_COMP12,

FMC_A13, EVENTOUT

-

-

TIM1_BKIN2, TIM1_BKIN2_COMP12,

FMC_A14/FMC_BA0, EVENTOUT

TIM1_ETR, FMC_A15/FMC_BA1,

EVENTOUT

TIM17_BKIN, OCTOSPIM_P1_NCS,

FMC_NE3, DCMI_D12/PSSI_D12,

LCD_R7, EVENTOUT

SAI1_MCLK_A, USART6_CK,

OCTOSPIM_P2_DQS, FMC_INT,

DCMI_D13/PSSI_D13, LCD_CLK,

EVENTOUT

TIM8_ETR, SPI6_NSS/I2S6_WS,

USART6_RTS, SPDIFRX1_IN2,

FMC_SDCLK, LCD_G7, EVENTOUT

-

-

-

TIM3_CH1, TIM8_CH1,

DFSDM1_CKIN3, I2S2_MCK,

USART6_TX, SDMMC1_D0DIR,

FMC_NWAIT, SDMMC2_D6,

SDMMC1_D6, DCMI_D0/PSSI_D0,

LCD_HSYNC, EVENTOUT

TRGIO, TIM3_CH2, TIM8_CH2,

DFSDM1_DATIN3, I2S3_MCK,

USART6_RX, SDMMC1_D123DIR,

FMC_NE1, SDMMC2_D7, SWPMI_TX,

SDMMC1_D7, DCMI_D1/PSSI_D1,

LCD_G6, EVENTOUT

TRACED1, TIM3_CH3, TIM8_CH3,

USART6_CK, UART5_RTS, FMC_NE2/

FMC_NCE, FMC_INT, SWPMI_RX,

SDMMC1_D0, DCMI_D2/PSSI_D2,

EVENTOUT

MCO2, TIM3_CH4, TIM8_CH4,

I2C3_SDA, I2S_CKIN, UART5_CTS,

OCTOSPIM_P1_IO0, LCD_G3,

SWPMI_SUSPEND, SDMMC1_D1,

DCMI_D3/PSSI_D3, LCD_B2,

EVENTOUT

-

MCO1, TIM1_CH1, TIM8_BKIN2,

I2C3_SCL, USART1_CK,

OTG_HS_SOF, UART7_RX,

TIM8_BKIN2_COMP12, LCD_B3,

LCD_R6, EVENTOUT

TIM1_CH2, LPUART1_TX, I2C3_SMBA,

SPI2_SCK/I2S2_CK, USART1_TX,

DCMI_D0/PSSI_D0, LCD_R5,

EVENTOUT

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

SWPMI_IO

OTG_HS_VBUS

DS13196 - Rev 6 page 48/199

STM32H7B0xB

Pin descriptions

Pin/ball name (1) (2)

Pin name

(function after reset)

Pin type

I/O structure

Alternate functions Additional functions

E10

F13

A12

C14

C15

C12

42

43

51

69

70

78

102

103

111

121

122

139

PA10

PA11

E13 B15 44 71 104 123

D11

D13

B10

D12

A10

B13

A13

-

-

-

-

-

-

45

46

47

-

48

-

-

-

-

B13

A14

M6

A13

-

C13

B12

D12

-

J9

-

-

-

72

73

74

-

75

-

-

-

-

124

125

126

-

127

128

129

130

131

-

132

-

-

105

106

107

-

108

-

-

-

-

PA12

PA13(JTMS/

SWDIO)

VCAP

VSS

VDDLDO

VDD

PH13

PH14

PH15

PI0

VSS

PI1

I/O

I/O

I/O

I/O

S

S

S

S

I/O

I/O

S

I/O

-

-

-

-

B12

-

J10

-

A12

-

-

-

49

-

-

-

76

133

-

-

-

109

134

135

136

137

C11 A11 50 77 110 138

PI2

PI3

VSS

VDD

PA14(JTCK/

SWCLK)

PA15(JTDI)

I/O

I/O

S

S

I/O

I/O

PC10

I/O

I/O

I/O

FT_u

FT_u

FT_u

FT

-

-

-

-

FT_h2

FT_h2

FT_h2

FT_h2

-

FT_h2

FT_h2

FT_h2

-

-

FT

FT

FT_h0

TIM1_CH3, LPUART1_RX,

USART1_RX, OTG_HS_ID,

MDIOS_MDIO, LCD_B4, DCMI_D1/

PSSI_D1, LCD_B1, EVENTOUT

TIM1_CH4, LPUART1_CTS, SPI2_NSS/

I2S2_WS, UART4_RX, USART1_CTS/

USART1_NSS, FDCAN1_RX, LCD_R4,

EVENTOUT

TIM1_ETR, LPUART1_RTS, SPI2_SCK/

I2S2_CK, UART4_TX, USART1_RTS,

SAI2_FS_B, FDCAN1_TX, LCD_R5,

EVENTOUT

JTMS/SWDIO, EVENTOUT

-

-

-

-

TIM8_CH1N, UART4_TX, FDCAN1_TX,

FMC_D21, LCD_G2, EVENTOUT

TIM8_CH2N, UART4_RX, FDCAN1_RX,

FMC_D22, DCMI_D4/PSSI_D4,

LCD_G3, EVENTOUT

TIM8_CH3N, FMC_D23, DCMI_D11/

PSSI_D11, LCD_G4, EVENTOUT

TIM5_CH4, SPI2_NSS/I2S2_WS,

FMC_D24, DCMI_D13/PSSI_D13,

LCD_G5, EVENTOUT

-

TIM8_BKIN2, SPI2_SCK/I2S2_CK,

TIM8_BKIN2_COMP12, FMC_D25,

DCMI_D8/PSSI_D8, LCD_G6,

EVENTOUT

TIM8_CH4, SPI2_MISO/I2S2_SDI,

FMC_D26, DCMI_D9/PSSI_D9,

LCD_G7, EVENTOUT

TIM8_ETR, SPI2_MOSI/I2S2_SDO,

FMC_D27, DCMI_D10/PSSI_D10,

EVENTOUT

-

-

JTCK/SWCLK, EVENTOUT

JTDI, TIM2_CH1/TIM2_ETR,

HDMI_CEC, SPI1_NSS/I2S1_WS,

SPI3_NSS/I2S3_WS, SPI6_NSS/

I2S6_WS, UART4_RTS, LCD_R3,

UART7_TX, LCD_B6, EVENTOUT

DFSDM1_CKIN5, DFSDM2_CKIN0,

SPI3_SCK/I2S3_CK, USART3_TX,

UART4_TX, OCTOSPIM_P1_IO1,

LCD_B1, SWPMI_RX, SDMMC1_D2,

DCMI_D8/PSSI_D8, LCD_R2,

EVENTOUT

-

-

-

-

OTG_HS_DM

OTG_HS_DP

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

DS13196 - Rev 6 page 49/199

STM32H7B0xB

Pin descriptions

Pin/ball name (1) (2)

Pin name

(function after reset)

Pin type

I/O structure

Alternate functions Additional functions

B11

A11

-

D10

C10

E9

D9

C9

A9

-

-

B9

A8

B8

C11 52 79

B11

J14

C10

A10

B10 54 83 116 144

A9

C9

B9

K2

-

D9

C8

A7

53

-

-

-

-

-

-

-

-

-

-

-

80

-

81

82

-

-

112 140

113 141

-

114

115

125

126

-

142

143

84 117 145

85

86

-

-

118

119

120

121

146

147

148

149

87 122 150

153

154

PC11

PC12

VSS

PD0

PD1

PD2

PD3

PD4

PD5

VSS

VDDMMC

PD6

D8

-

A6

C8

B8

K6

D5

A8

-

-

-

-

88 123 151

-

-

-

-

-

-

124 152

PD7

VSS

VDDMMC

PG9

PG10

PG11

I/O

S

S

I/O

I/O

S

I/O

I/O

I/O

I/O

I/O

S

S

I/O

I/O

I/O

I/O

I/O

FT_h0

FT_h0

-

FT_h2

FT_h2

FT_h0

FT_h2

FT_h1

FT_h1

-

-

FT_sh3

FT_sh3

-

-

FT_sh3

FT_sh3

FT_sh3

DFSDM1_DATIN5, DFSDM2_DATIN0,

SPI3_MISO/I2S3_SDI, USART3_RX,

UART4_RX, OCTOSPIM_P1_NCS,

SDMMC1_D3, DCMI_D4/PSSI_D4,

LCD_B4, EVENTOUT

TRACED3, TIM15_CH1,

DFSDM2_CKOUT, SPI6_SCK/I2S6_CK,

SPI3_MOSI/I2S3_SDO, USART3_CK,

UART5_TX, SDMMC1_CK, DCMI_D9/

PSSI_D9, LCD_R6, EVENTOUT

-

DFSDM1_CKIN6, UART4_RX,

FDCAN1_RX, UART9_CTS, FMC_D2/

FMC_DA2, LCD_B1, EVENTOUT

DFSDM1_DATIN6, UART4_TX,

FDCAN1_TX, FMC_D3/FMC_DA3,

EVENTOUT

TRACED2, TIM3_ETR, TIM15_BKIN,

UART5_RX, LCD_B7, SDMMC1_CMD,

DCMI_D11/PSSI_D11, LCD_B2,

EVENTOUT

DFSDM1_CKOUT, SPI2_SCK/

I2S2_CK, USART2_CTS/USART2_NSS,

FMC_CLK, DCMI_D5/PSSI_D5,

LCD_G7, EVENTOUT

USART2_RTS, OCTOSPIM_P1_IO4,

FMC_NOE, EVENTOUT

USART2_TX, OCTOSPIM_P1_IO5,

FMC_NWE, EVENTOUT

-

-

SAI1_D1, DFSDM1_CKIN4,

DFSDM1_DATIN1, SPI3_MOSI/

I2S3_SDO, SAI1_SD_A, USART2_RX,

OCTOSPIM_P1_IO6, SDMMC2_CK,

FMC_NWAIT, DCMI_D10/PSSI_D10,

LCD_B2, EVENTOUT

DFSDM1_DATIN4, SPI1_MOSI/

I2S1_SDO, DFSDM1_CKIN1,

USART2_CK, SPDIFRX1_IN0,

OCTOSPIM_P1_IO7, SDMMC2_CMD,

FMC_NE1, EVENTOUT

-

-

SPI1_MISO/I2S1_SDI, USART6_RX,

SPDIFRX1_IN3, OCTOSPIM_P1_IO6,

SAI2_FS_B, SDMMC2_D0, FMC_NE2/

FMC_NCE, DCMI_VSYNC/PSSI_RDY,

EVENTOUT

OCTOSPIM_P2_IO6, SPI1_NSS/

I2S1_WS, LCD_G3, SAI2_SD_B,

SDMMC2_D1, FMC_NE3, DCMI_D2/

PSSI_D2, LCD_B2, EVENTOUT

LPTIM1_IN2, SPI1_SCK/I2S1_CK,

SPDIFRX1_IN0, OCTOSPIM_P2_IO7,

SDMMC2_D2, USART10_RX,

DCMI_D3/PSSI_D3, LCD_B3,

EVENTOUT

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

DS13196 - Rev 6 page 50/199

STM32H7B0xB

Pin descriptions

Pin/ball name (1) (2)

Pin name

(function after reset)

Pin type

I/O structure

Alternate functions Additional functions

D6

E6

C7

-

-

-

E7

E8

D7

F7

B6

C6

A5

B5

D8

B7

C7

K7

-

K8

D7

A6

B6 56

C6

A5

B5

C5

A2

-

-

-

-

-

-

-

55

57

58

59

60

61

-

-

-

-

-

-

-

89

91

92

93

94

95

127

128

129

130

131

-

132

133 161

135

136

137

138

139

155

156

157

158

159

-

160

163

164

165

166

167

PG12

PG13

PG14

VSS

VDD

VSS

PG15

PB3(JTDO/

TRACESWO)

90 134 162 PB4(NJTRST)

PB5

PB6

PB7

BOOT0

PB8

S

S

S

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I

I/O

FT_sh3

FT_sh3

FT_sh3

-

-

-

FT_h1

FT_h0

FT_h0

FT_h0

FT_f

FT_fa

B

FT_fsh3

LPTIM1_IN1, OCTOSPIM_P2_NCS,

SPI6_MISO/I2S6_SDI, USART6_RTS,

SPDIFRX1_IN1, LCD_B4,

SDMMC2_D3, USART10_TX,

FMC_NE4, LCD_B1, EVENTOUT

TRACED0, LPTIM1_OUT,

SPI6_SCK/I2S6_CK, USART6_CTS/

USART6_NSS, SDMMC2_D6,

USART10_CTS/USART10_NSS,

FMC_A24, LCD_R0, EVENTOUT

TRACED1, LPTIM1_ETR,

SPI6_MOSI/I2S6_SDO, USART6_TX,

OCTOSPIM_P1_IO7, SDMMC2_D7,

USART10_RTS, FMC_A25, LCD_B0,

EVENTOUT

-

-

-

USART6_CTS/USART6_NSS,

OCTOSPIM_P2_DQS, USART10_CK,

FMC_SDNCAS, DCMI_D13/PSSI_D13,

EVENTOUT

JTDO/TRACESWO, TIM2_CH2,

SPI1_SCK/I2S1_CK, SPI3_SCK/

I2S3_CK, SPI6_SCK/I2S6_CK,

SDMMC2_D2, CRS_SYNC, UART7_RX,

EVENTOUT

NJTRST, TIM16_BKIN, TIM3_CH1,

SPI1_MISO/I2S1_SDI, SPI3_MISO/

I2S3_SDI, SPI2_NSS/I2S2_WS,

SPI6_MISO/I2S6_SDI, SDMMC2_D3,

UART7_TX, EVENTOUT

TIM17_BKIN, TIM3_CH2, I2C1_SMBA,

SPI1_MOSI/I2S1_SDO, I2C4_SMBA,

SPI3_MOSI/I2S3_SDO, SPI6_MOSI/

I2S6_SDO, FDCAN2_RX,

OTG_HS_ULPI_D7, LCD_B5,

FMC_SDCKE1, DCMI_D10/PSSI_D10,

UART5_RX, EVENTOUT

TIM16_CH1N, TIM4_CH1,

I2C1_SCL, HDMI_CEC, I2C4_SCL,

USART1_TX, LPUART1_TX,

FDCAN2_TX, OCTOSPIM_P1_NCS,

DFSDM1_DATIN5, FMC_SDNE1,

DCMI_D5/PSSI_D5, UART5_TX,

EVENTOUT

TIM17_CH1N, TIM4_CH2,

I2C1_SDA, I2C4_SDA, USART1_RX,

LPUART1_RX, DFSDM1_CKIN5,

FMC_NL, DCMI_VSYNC/PSSI_RDY,

EVENTOUT

-

TIM16_CH1, TIM4_CH3,

DFSDM1_CKIN7, I2C1_SCL,

I2C4_SCL, SDMMC1_CKIN,

UART4_RX, FDCAN1_RX,

SDMMC2_D4, SDMMC1_D4, DCMI_D6/

PSSI_D6, LCD_B6, EVENTOUT

-

-

-

-

-

-

PVD_IN

VPP

-

-

-

-

-

-

DS13196 - Rev 6 page 51/199

STM32H7B0xB

Pin descriptions

Pin/ball name (1) (2)

Pin name

(function after reset)

Pin type

I/O structure

Alternate functions Additional functions

C5

D5

D4

A4

-

C4

B4

-

-

-

-

-

B3

B4

C4

A4

K10

D4

A3

-

-

-

-

-

62

-

-

-

-

-

63

64

-

-

-

-

96

97

98

-

-

-

99

100

-

-

-

-

140

141

142

143

-

-

-

144

-

-

-

-

168

169

170

171

-

-

-

172

173

174

175

176

PB9

PE0

PE1

VCAP

VSS

PDR_ON

VDDLDO

VDD

PI4

PI5

PI6

PI7

I/O

I/O

I/O

S

S

S

S

S

I/O

I/O

I/O

I/O

FT_fsh3

FT_h2

FT_h2

-

-

-

-

-

FT_h2

FT_h2

FT_h2

FT_h2

-

-

-

-

-

-

-

-

-

H8

H9

J8

K9

R15

K12

G8

G9

H7

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

S

S

S

S

S

S

S

S

S

-

-

-

-

-

-

-

-

-

1. The devices with SMPS correspond to commercial code STM32H7B0xIxxQ.

2. A non-connected I/O in a given package is configured as an output tied to V

SS

. Any analog peripheral connected to such a pad (such as OPAMP, VREF+) must be disabled.

3. Pxy_C and Pxy pins/balls are two separate pads (analog switch open). The analog switch is configured through a SYSCFG register. Refer to the product reference manual for a detailed description of the switch configuration bits.

4. There is a direct path between Pxy_C and Pxy pins/balls, through an analog switch. Pxy alternate functions are available on Pxy_C when the analog switch is closed. The analog switch is configured through a SYSCFG register. Refer to the product reference manual for a detailed description of the switch configuration bits.

TIM17_CH1, TIM4_CH4,

DFSDM1_DATIN7, I2C1_SDA,

SPI2_NSS/I2S2_WS, I2C4_SDA,

SDMMC1_CDIR, UART4_TX,

FDCAN1_TX, SDMMC2_D5,

I2C4_SMBA, SDMMC1_D5, DCMI_D7/

PSSI_D7, LCD_B7, EVENTOUT

LPTIM1_ETR, TIM4_ETR,

LPTIM2_ETR, UART8_RX,

SAI2_MCK_A, FMC_NBL0, DCMI_D2/

PSSI_D2, LCD_R0, EVENTOUT

LPTIM1_IN2, UART8_TX, FMC_NBL1,

DCMI_D3/PSSI_D3, LCD_R6,

EVENTOUT

-

-

-

-

-

TIM8_BKIN, SAI2_MCK_A,

TIM8_BKIN_COMP12, FMC_NBL2,

DCMI_D5/PSSI_D5, LCD_B4,

EVENTOUT

TIM8_CH1, SAI2_SCK_A, FMC_NBL3,

DCMI_VSYNC/PSSI_RDY, LCD_B5,

EVENTOUT

TIM8_CH2, SAI2_SD_A, FMC_D28,

DCMI_D6/PSSI_D6, LCD_B6,

EVENTOUT

TIM8_CH3, SAI2_FS_A, FMC_D29,

DCMI_D7/PSSI_D7, LCD_B7,

EVENTOUT

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

DS13196 - Rev 6 page 52/199

Table 8. Port A alternate functions

Port

PA0

PA1

PA2

PA3

PA4

PA6

AF0

SYS

-

-

-

-

-

-

PA5 PWR_NDSTOP2

AF1

LPTIM1/

TIM1/2/16/17

PDM_SAI1/

TIM3/4/5/12/15

DFSDM1/

LPTIM2/3/

LPUART1/

OCTOSPIM_P1/2/

TIM8

TIM2_CH1/

TIM2_ETR

TIM2_CH2

TIM2_CH3

TIM2_CH4

-

TIM2_CH1/

TIM2_ETR

TIM1_BKIN

AF2

TIM5_CH1

TIM5_CH2

TIM5_CH3

TIM5_CH4

TIM5_ETR

-

TIM3_CH1

AF3

TIM8_ETR

LPTIM3_OUT

-

OCTOSPIM_

P1_CLK

-

TIM8_CH1N

TIM8_BKIN

AF4

CEC/DCMI/

PSSI/

DFSDM1/2/

I2C1/2/3/4/

LPTIM2/

TIM15/

USART1

TIM15_BKIN

TIM15_CH1N

TIM15_CH1

TIM15_CH2

-

-

-

AF5 AF6 AF7 AF8

CEC/SPI1/

I2S1/SPI2/

I2S2/SPI3/

I2S3/

SPI4/5/

SPI6/I2S6

DFSDM1/2/

I2C4/

OCTOSPIM_P1/

SAI1/SPI3/I2S3/

UART4

SDMMC1/

SPI2/I2S2/

SPI3/I2S3/

SPI6/I2S6/

UART7/

USART1/2/3/6

LPUART1/

SAI2/

SDMMC1/

SPDIFRX1/

SPI6/I2S6/

UART4/5/8

AF9 AF10

FDCAN1/2/FMC/

LCD/

OCTOSPIM_P1/2/

SDMMC2/

SPDIFRX1/

TIM13/14

CRS/FMC/LCD/

OCTOSPIM_P1/

OTG1_FS/OTG1_HS/

SAI2/SDMMC2/TIM8

AF11

DFSDM1/2/

I2C4/LCD/

MDIOS/

OCTOSPIM_P1/

SDMMC2/

SWPMI1/

TIM1/8/

UART7/9/

USART10

SPI6_NSS/

I2S6_WS

-

-

I2S6_MCK

SPI1_NSS/

I2S1_WS

SPI1_SCK/

I2S1_CK

SPI1_MISO/

I2S1_SDI

-

-

DFSDM2_

CKIN1

-

SPI3_NSS/

I2S3_WS

-

OCTOSPIM_

P1_IO3

USART2_

CTS/

USART2_

NSS

USART2_

RTS

USART2_

TX

USART2_

RX

USART2_

CK

-

-

UART4_TX

UART4_RX

SAI2_SCK_B

-

SPI6_NSS/

I2S6_WS

SPI6_SCK/

I2S6_CK

SPI6_MISO/

I2S6_SDI

SDMMC2_CMD

OCTOSPIM_

P1_IO3

-

LCD_B2

-

-

TIM13_CH1

SAI2_SD_B

SAI2_MCK_B

-

OTG_HS_

ULPI_D0

-

OTG_HS_

ULPI_CK

TIM8_BKIN_COMP12

-

OCTOSPIM_

P1_DQS

-

-

-

-

MDIOS_MDC

AF12

FMC/LCD/

MDIOS/

SDMMC1/

TIM1/8

-

-

MDIOS_MDIO

-

-

-

TIM1_BKIN_

COMP12

AF13

COMP/DCMI/

PSSI/LCD/

TIM1

-

-

-

-

DCMI_HSYNC/

PSSI_DE

PSSI_D14

DCMI_PIXCLK/

PSSI_PDCK

AF14

LCD/UART5

-

LCD_R2

LCD_R1

LCD_B5

LCD_

VSYNC

LCD_R4

LCD_G2

PA7 TIM1_CH1N TIM3_CH2 TIM8_CH1N

DFSDM2_

DATIN1

SPI1_MOSI/

I2S1_SDO

-

SPI6_MOSI/

I2S6_SDO

TIM14_CH1 OCTOSPIM_P1_IO2 FMC_SDNWE LCD_VSYNC

AF15

SYS

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

PA8

PA9

PA10

PA11

PA12

MCO1

-

-

-

-

TIM1_CH1

TIM1_CH2

TIM1_CH3

TIM1_CH4

TIM1_ETR -

-

-

-

TIM8_BKIN2

LPUART1_TX

LPUART1_RX

LPUART1_CTS

LPUART1_RTS

I2C3_SCL

I2C3_SMBA

-

-

-

SPI2_SCK/

I2S2_CK

-

-

SPI2_NSS/

I2S2_WS

SPI2_SCK/

I2S2_CK

-

-

-

UART4_RX

UART4_TX

USART1_

CK

USART1_

TX

USART1_

RX

USART1_

CTS/

USART1_NSS

USART1_

RTS

-

-

-

-

SAI2_FS_B

-

-

-

FDCAN1_

RX

FDCAN1_

TX

OTG_HS_

SOF

-

OTG_HS_

ID

-

-

UART7_RX

-

MDIOS_MDIO

-

-

TIM8_BKIN2_

COMP12

-

LCD_B4

-

-

LCD_B3

DCMI_D0/

PSSI_D0

DCMI_D1/

PSSI_D1

-

-

LCD_R6

LCD_R5

LCD_B1

LCD_R4

LCD_R5

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

PA13

PA14

JTMS/

SWDIO

JTCK/

SWCLK

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

EVENTOUT

EVENTOUT

PA15 JTDI

TIM2_CH1/

TIM2_ETR

HDMI_CEC

SPI1_NSS/

I2S1_WS

SPI3_NSS/

I2S3_WS

SPI6_NSS/

I2S6_WS

UART4_

RTS

LCD_R3 UART7_TX LCD_B6 EVENTOUT

Table 9. Port B alternate functions

Port

PB0

PB1

PB2

PB3

JTDO/

TRACESWO

PB4

PB5

PB6

AF0

SYS

-

-

-

-

RTC_OUT2

NJTRST

AF1

LPTIM1/

TIM1/2/16/17

TIM1_CH2N

TIM1_CH3N

-

TIM2_CH2

TIM16_BKIN

TIM17_BKIN

TIM16_CH1N

AF2

PDM_SAI1/

TIM3/4/5/12/15

DFSDM1/

LPTIM2/3/

LPUART1/

OCTOSPIM_P1/2/

TIM8

TIM3_CH3

TIM3_CH4

SAI1_D1

-

TIM3_CH1

TIM3_CH2

TIM4_CH1

AF3

TIM8_CH2N

TIM8_CH3N

-

-

-

-

-

AF4

CEC/DCMI/PSSI/

DFSDM1/2/

I2C1/2/3/4/

LPTIM2/TIM15/

USART1

DFSDM2_CKOUT

-

DFSDM1_CKIN1

-

-

I2C1_SMBA

I2C1_SCL

AF5

CEC/SPI1/

I2S1/SPI2/

I2S2/SPI3/

I2S3/

SPI4/5/

SPI6/I2S6

-

-

-

SPI1_SCK/

I2S1_CK

SPI1_MISO/

I2S1_SDI

SPI1_MOSI/

I2S1_SDO

HDMI_CEC

AF6

DFSDM1/2/I2C4/

OCTOSPIM_P1/

SAI1/SPI3/I2S3/

UART4

DFSDM1_CKOUT

DFSDM1_DATIN1

SAI1_SD_A

SPI3_SCK/

I2S3_CK

SPI3_MISO/

I2S3_SDI

I2C4_SMBA

I2C4_SCL

AF7

SDMMC1/SPI2/

I2S2/SPI3/I2S3/

SPI6/I2S6/

UART7/

USART1/2/3/6

-

-

SPI3_MOSI/

I2S3_SDO

-

SPI2_NSS/

I2S2_WS

SPI3_MOSI/

I2S3_SDO

USART1_TX

AF8

LPUART1/

SAI2/

SDMMC1/

SPDIFRX1/

SPI6/I2S6/

UART4/5/8

UART4_CTS

-

-

AF9 AF10

FDCAN1/2/FMC/LC

D/OCTOSPIM_P1/2/

SDMMC2/

SPDIFRX1/TIM13/14

CRS/FMC/LCD/

OCTOSPIM_P1/

OTG1_FS/

OTG1_HS/

SAI2/SDMMC2/

TIM8

LCD_R3

LCD_R6

OCTOSPIM_P1_CLK

OTG_HS_

ULPI_D1

OTG_HS_

ULPI_D2

OCTOSPIM_

P1_DQS

AF11

DFSDM1/2/

I2C4/LCD/MDIOS/

OCTOSPIM_P1/

SDMMC2/SWPMI1/

TIM1/8/UART7/9/

USART10

OCTOSPIM_P1_IO1

OCTOSPIM_

P1_IO0

-

SPI6_SCK/

I2S6_CK

SPI6_MISO/

I2S6_SDI

SPI6_MOSI/

I2S6_SDO

LPUART1_TX

SDMMC2_D2

SDMMC2_D3

FDCAN2_RX

FDCAN2_TX

CRS_SYNC

-

OTG_HS_

ULPI_D7

OCTOSPIM_

P1_NCS

UART7_RX

UART7_TX

LCD_B5

DFSDM1_DATIN5

AF12

FMC/LCD/

MDIOS/

SDMMC1/

TIM1/8

-

-

-

-

-

FMC_SDCKE1

FMC_SDNE1

PB7 TIM17_CH1N TIM4_CH2 I2C1_SDA I2C4_SDA USART1_RX LPUART1_RX DFSDM1_CKIN5 FMC_NL

PB8 TIM16_CH1 TIM4_CH3 DFSDM1_CKIN7 I2C1_SCL FDCAN1_RX SDMMC2_D4 SDMMC1_D4

AF13

COMP/DCMI/

PSSI/LCD/TIM1

-

-

-

-

-

DCMI_D10/

PSSI_D10

DCMI_VSYNC/

PSSI_RDY

DCMI_D6/PSSI_D6

AF14

LCD/

UART5

LCD_G1

LCD_G0

-

-

-

UART5_RX

AF15

SYS

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

DCMI_D5/PSSI_D5 UART5_TX EVENTOUT

-

LCD_B6

EVENTOUT

EVENTOUT

PB9

PB10

PB11

PB12

PB13

PB14

PB15

-

-

-

-

-

-

RTC_REFIN

TIM17_CH1

TIM2_CH3

TIM2_CH4

TIM1_BKIN

TIM1_CH1N

TIM1_CH2N

TIM1_CH3N

TIM4_CH4

-

-

-

-

TIM12_CH1

TIM12_CH2

DFSDM1_DATIN7

LPTIM2_IN1

LPTIM2_ETR

OCTOSPIM_

P1_NCLK

LPTIM2_OUT

TIM8_CH2N

TIM8_CH3N

I2C1_SDA

I2C2_SCL

I2C2_SDA

I2C2_SMBA

-

SPI2_NSS/

I2S2_WS

SPI2_SCK/

I2S2_CK

I2C4_SCL

I2C4_SDA

DFSDM1_DATIN7

SDMMC1_CKIN

SDMMC1_CDIR

USART3_TX

UART4_RX

UART4_TX

-

DFSDM1_CKIN7

SPI2_NSS/

I2S2_WS

DFSDM1_DATIN1

USART3_RX

USART3_CK

DFSDM2_CKIN1

USART1_TX

USART1_RX

SPI2_SCK/

I2S2_CK

SPI2_MOSI/

I2S2_SDO

DFSDM1_CKIN1

SPI2_MISO/

I2S2_SDI

DFSDM1_DATIN2

DFSDM1_CKIN2

USART3_CTS/

USART3_NSS

USART3_RTS

-

-

-

-

UART4_RTS

UART4_CTS

FDCAN1_TX

OCTOSPIM_

P1_NCS

-

FDCAN2_RX

FDCAN2_TX

SDMMC2_D0

SDMMC2_D1

SDMMC2_D5

OTG_HS_

ULPI_D3

OTG_HS_

ULPI_D4

OTG_HS_

ULPI_D5

OTG_HS_

ULPI_D6

-

-

I2C4_SMBA

-

-

DFSDM2_DATIN1

-

-

-

SDMMC1_D5

-

-

-

SDMMC1_D0

-

-

DCMI_D7/PSSI_D7

-

-

TIM1_BKIN_COMP12

DCMI_D2/PSSI_D2

-

-

LCD_B7

LCD_G4

LCD_G5

UART5_RX

UART5_TX

LCD_CLK

LCD_G7

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

Table 10. Port C alternate functions

PC12

PC13

PC14

PC15

AF0

TRACED3

-

-

-

AF1

-

-

-

-

AF2

TIM15_CH1

-

-

-

AF3

-

-

-

-

AF4

DFSDM2_CKOUT

-

-

-

AF5

SPI6_SCK/

I2S6_CK

-

-

-

AF6

SPI3_MOSI/

I2S3_SDO

-

-

-

AF7

USART3_CK

-

-

-

AF8

UART5_TX

-

-

-

AF9

-

-

-

-

AF10

-

-

-

-

AF11

-

-

-

-

AF12

SDMMC1_CK

-

-

-

AF13

DCMI_D9/

PSSI_D9

-

-

-

AF14 AF15

Port

PC0

PC1

PC2

PC3 PWR_CSLEEP

PC4

PC5

PC6

PC7

PC8

PC9

PC10

PC11

SYS

-

-

-

TRACED0

PWR_CSTOP

-

-

-

TRGIO

TRACED1

MCO2

LPTIM1/

TIM1/2/16/17

-

-

-

-

-

-

-

-

-

-

-

-

PDM_SAI1/

TIM3/4/5/12/15

-

-

-

SAI1_D1

-

-

-

SAI1_D3

TIM3_CH1

TIM3_CH2

TIM3_CH3

TIM3_CH4

DFSDM1/

LPTIM2/3/

LPUART1/

OCTOSPIM_P1/2/

TIM8

DFSDM1_CKIN0

DFSDM1_DATIN0

DFSDM1_CKIN1

DFSDM1_DATIN1

DFSDM1_CKIN2

DFSDM1_DATIN2

TIM8_CH1

TIM8_CH2

TIM8_CH3

TIM8_CH4

DFSDM1_CKIN5

CEC/DCMI/PSSI/

DFSDM1/2/

I2C1/2/3/4/

LPTIM2/TIM15/

USART1

-

DFSDM1_CKIN4

-

-

-

PSSI_D15

DFSDM1_CKIN3

DFSDM1_DATIN3

-

I2C3_SDA

DFSDM2_CKIN0

DFSDM1_DATIN5 DFSDM2_DATIN0

CEC/SPI1/

I2S1/SPI2/

I2S2/SPI3/

I2S3/

SPI4/5/

SPI6/I2S6

-

SPI2_MOSI/

I2S2_SDO

SPI2_MISO/

I2S2_SDI

SPI2_MOSI/

I2S2_SDO

I2S1_MCK

-

I2S2_MCK

I2S_CKIN

-

-

-

-

DFSDM1/2/I2C4/

OCTOSPIM_P1/

SAI1/SPI3/I2S3/

UART4

DFSDM1_DATIN4

SAI1_SD_A

DFSDM1_CKOUT

I2S3_MCK

-

-

-

-

-

-

SPI3_SCK/

I2S3_CK

SPI3_MISO/

I2S3_SDI

SDMMC1/

SPI2/I2S2/

SPI3/I2S3/

SPI6/I2S6/

UART7/

USART1/2/3/6

-

-

-

-

-

-

USART6_TX

USART6_RX

USART6_CK

-

USART3_TX

USART3_RX

LPUART1/

SAI2/SDMMC1/

SPDIFRX1/SPI6/

I2S6/UART4/5/8

SAI2_FS_B

-

-

-

-

-

SDMMC1_D0DIR

SDMMC1_D123DIR

UART5_RTS

UART5_CTS

UART4_TX

UART4_RX

FDCAN1/2/FMC/LCD

/OCTOSPIM_P1/2/

SDMMC2/

SPDIFRX1/TIM13/14

FMC_A25

CRS/FMC/LCD/

OCTOSPIM_P1/

OTG1_FS/

OTG1_HS/

SAI2/SDMMC2/

TIM8

DFSDM1/2/

I2C4/LCD/

MDIOS/

OCTOSPIM_P1/

SDMMC2/

SWPMI1/

TIM1/8/

UART7/9/

USART10

OTG_HS_

ULPI_STP

LCD_G2

SDMMC2_CK

OCTOSPIM_P1_IO2

OCTOSPIM_P1_IO0

SPDIFRX1_IN2

SPDIFRX1_IN3

OCTOSPIM_

P1_IO4

OTG_HS_

ULPI_DIR

OTG_HS_

ULPI_NXT

-

OCTOSPIM_

P1_DQS

OCTOSPIM_

P1_IO5

OCTOSPIM_

P1_IO6

-

-

-

FMC/LCD/

MDIOS/

SDMMC1/

TIM1/8

FMC_SDNWE

MDIOS_MDC

FMC_SDNE0

FMC_SDCKE0

FMC_SDNE0

COMP/DCMI/

PSSI/LCD/

TIM1

-

-

-

-

-

FMC_SDCKE0 COMP1_OUT

FMC_NWAIT

FMC_NE1

FMC_NE2/

FMC_NCE

OCTOSPIM_P1_IO0

OCTOSPIM_P1_IO1

OCTOSPIM_P1_NCS

SDMMC2_D6

SDMMC2_D7

FMC_INT

LCD_G3

LCD_B1

-

-

SWPMI_TX

SWPMI_RX

SWPMI_

SUSPEND

SWPMI_RX

-

SDMMC1_D6

SDMMC1_D7

SDMMC1_D0

SDMMC1_D1

SDMMC1_D2

SDMMC1_D3

DCMI_D0/

PSSI_D0

DCMI_D1/

PSSI_D1

DCMI_D2/

PSSI_D2

DCMI_D3/

PSSI_D3

DCMI_D8/

PSSI_D8

DCMI_D4/

PSSI_D4

LCD/UART5

LCD_R5

LCD_G5

-

-

LCD_R7

LCD_DE

LCD_HSYNC

LCD_G6

-

LCD_B2

LCD_R2

LCD_B4

SYS

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

LCD_R6

-

-

-

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

Table 11. Port D alternate functions

Port

PD0

PD1

PD2 TRACED2

PD3

PD4

PD5

PD6

PD7

PD8

PD9

PD10

PD11

PD12

PD13

AF0

SYS

-

-

-

-

-

-

-

-

-

-

-

-

-

AF1

-

-

-

-

-

-

-

-

AF2

-

-

TIM3_ETR

-

-

-

SAI1_D1

-

AF3

LPTIM1/

TIM1/2/16/17

PDM_SAI1/

TIM3/4/5/12/15

DFSDM1/

LPTIM2/3/

LPUART1/

OCTOSPIM_P1/2/

TIM8

CEC/DCMI/PSSI/

DFSDM1/2/

I2C1/2/3/4/

LPTIM2/TIM15/

USART1

CEC/SPI1/

I2S1/SPI2/

I2S2/SPI3/

I2S3/

SPI4/5/

SPI6/I2S6

DFSDM1/2/I2C4/

OCTOSPIM_P1/

SAI1/SPI3/I2S3/

UART4

SDMMC1/

SPI2/I2S2/

SPI3/I2S3/

SPI6/I2S6/

UART7/

USART1/2/3/6

LPUART1/

SAI2/

SDMMC1/

SPDIFRX1/

SPI6/I2S6/

UART4/5/8

FDCAN1/2/FMC/LC

D/OCTOSPIM_P1/2/

SDMMC2/

SPDIFRX1/

TIM13/14

DFSDM1_CKIN6

DFSDM1_DATIN6

-

DFSDM1_CKOUT

-

-

DFSDM1_CKIN4 DFSDM1_DATIN1

SPI3_MOSI/

I2S3_SDO

DFSDM1_DATIN4

AF4

TIM15_BKIN

-

-

-

-

-

-

AF5

-

-

-

SPI2_SCK/

I2S2_CK

-

-

AF6

-

-

-

-

-

-

SAI1_SD_A

SPI1_MOSI/

I2S1_SDO

DFSDM1_CKIN1

AF7

-

-

-

USART2_CTS/

USART2_NSS

USART2_RTS

USART2_TX

USART2_RX

USART2_CK

AF8

UART4_RX

UART4_TX

UART5_RX

-

-

-

-

-

AF9

FDCAN1_RX

FDCAN1_TX

LCD_B7

-

-

-

-

SPDIFRX1_IN0

AF10

CRS/FMC/LCD/

OCTOSPIM_P1/

OTG1_FS/

OTG1_HS/SAI2/

SDMMC2/TIM8

AF11

DFSDM1/2/

I2C4/LCD/

MDIOS/

OCTOSPIM_P1/

SDMMC2/

SWPMI1/

TIM1/8/

UART7/9/

USART10

AF12

FMC/LCD/

MDIOS/

SDMMC1/

TIM1/8

AF13

COMP/

DCMI/

PSSI/LCD/

TIM1

-

-

-

-

OCTOSPIM_P1_IO4

OCTOSPIM_P1_IO5

UART9_CTS

-

-

-

-

-

OCTOSPIM_P1_IO6 SDMMC2_CK

FMC_D2/

FMC_DA2

FMC_D3/

FMC_DA3

SDMMC1_CMD

DCMI_D11/

PSSI_D11

FMC_CLK

DCMI_D5/

PSSI_D5

FMC_NOE

FMC_NWE

FMC_NWAIT

-

-

-

-

DCMI_D10/

PSSI_D10

AF14

LCDUART5

LCD_B1

-

LCD_B2

LCD_G7

-

-

LCD_B2

AF15

SYS

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

OCTOSPIM_P1_IO7 SDMMC2_CMD FMC_NE1 EVENTOUT

-

-

-

-

LPTIM1_IN1

LPTIM1_OUT

-

-

-

-

TIM4_CH1

TIM4_CH2

DFSDM1_CKIN3

DFSDM1_DATIN3

DFSDM1_CKOUT

LPTIM2_IN2

LPTIM2_IN1

-

-

-

DFSDM2_CKOUT

I2C4_SMBA

I2C4_SCL

I2C4_SDA -

-

-

-

-

-

-

-

-

-

-

USART3_TX

USART3_RX

USART3_CK

USART3_CTS/

USART3_NSS

USART3_RTS

-

-

-

-

-

SPDIFRX1_IN1

-

-

OCTOSPIM_P1_IO0

OCTOSPIM_P1_IO1

OCTOSPIM_P1_IO3

-

-

-

SAI2_SD_A

SAI2_FS_A

SAI2_SCK_A

-

-

-

-

-

UART9_RTS

FMC_D13/

FMC_DA13

FMC_D14/

FMC_DA14

FMC_D15/

FMC_DA15

FMC_A16/

FMC_CLE

FMC_A17/

FMC_ALE

FMC_A18

-

-

-

-

DCMI_D12/

PSSI_D12

DCMI_D13/

PSSI_D13

LCD_B3

-

-

-

-

-

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

PD14

PD15 -

-

-

TIM4_CH3

TIM4_CH4 -

-

-

-

-

-

-

-

-

UART8_CTS

UART8_RTS -

-

-

UART9_RX

UART9_TX

FMC_D0/

FMC_DA0

FMC_D1/

FMC_DA1

-

-

-

EVENTOUT

EVENTOUT

Table 12. Port E alternate functions

Port

PE0

PE1

PE2

PE3

PE4

PE5

AF0

SYS

-

-

TRACECLK

TRACED0

TRACED1

TRACED2

PE6 TRACED3

PE7

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15 -

-

-

-

-

-

-

-

-

AF1 AF2 AF3

LPTIM1/

TIM1/2/16/17

PDM_SAI1/

TIM3/4/5/12/15

DFSDM1/

LPTIM2/3/

LPUART1/

OCTOSPIM_P1/2/

TIM8

AF4

CEC/DCMI/

PSSI/

DFSDM1/2/

I2C1/2/3/4/

LPTIM2/

TIM15/

USART1

AF5 AF6 AF7 AF8 AF9

CEC/SPI1/

I2S1/SPI2/

I2S2/SPI3/

I2S3/

SPI4/5/

SPI6/I2S6

DFSDM1/2/

I2C4/

OCTOSPIM_P1/

SAI1/SPI3/I2S3/

UART4

SDMMC1/

SPI2/I2S2/

SPI3/I2S3/

SPI6/I2S6/

UART7/

USART1/2/3/6

LPUART1/

SAI2/

SDMMC1/

SPDIFRX1/

SPI6/I2S6/

UART4/5/8

FDCAN1/2/FMC/LC

D/OCTOSPIM_P1/2/

SDMMC2/

SPDIFRX1/

TIM13/14

LPTIM1_ETR

LPTIM1_IN2

-

-

-

-

TIM1_BKIN2

TIM1_ETR

TIM1_CH1N

TIM1_CH1

TIM1_CH2N

TIM1_CH2

TIM1_CH3N

TIM1_CH3

TIM1_CH4

TIM1_BKIN

TIM4_ETR

-

SAI1_CK1

-

SAI1_D2

SAI1_CK2

SAI1_D1

-

-

-

-

-

-

-

-

-

-

-

-

-

DFSDM1_DATIN3

DFSDM1_CKIN3

-

DFSDM1_DATIN2

DFSDM1_CKIN2

DFSDM1_CKOUT

DFSDM1_DATIN4

DFSDM1_CKIN4

DFSDM1_DATIN5

DFSDM1_CKIN5

LPTIM2_ETR

-

-

TIM15_BKIN

TIM15_CH1N

TIM15_CH1

TIM15_CH2

-

-

-

-

-

-

-

-

-

-

-

SPI4_SCK

-

SPI4_NSS

SPI4_MISO

SPI4_MOSI

-

-

-

-

SPI4_NSS

SPI4_SCK

SPI4_MISO

SPI4_MOSI

-

-

-

SAI1_MCLK_A

SAI1_SD_B

SAI1_FS_A

SAI1_SCK_A

SAI1_SD_A

-

-

-

-

-

-

-

-

-

AF10

CRS/FMC/LCD/

OCTOSPIM_P1/

OTG1_FS/

OTG1_HS/SAI2/

SDMMC2/TIM8

AF11

DFSDM1/2/

I2C4/LCD/MDIOS/

OCTOSPIM_P1/

SDMMC2/SWPMI1/

TIM1/8/UART7/9/

USART10

AF12

FMC/LCD/

MDIOS/

SDMMC1/

TIM1/8

AF13

COMP/DCMI/

PSSI/LCD/TIM1

AF14

LCD/

UART5

AF15

SYS

-

-

-

-

-

-

-

-

-

-

-

-

UART7_RX

UART7_TX

UART7_RTS

UART7_CTS

UART8_Rx

UART8_Tx

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

OCTOSPIM_P1_IO2

-

SAI2_MCK_A

-

-

-

-

-

-

SAI2_MCK_B

OCTOSPIM_P1_IO4

OCTOSPIM_P1_IO5

OCTOSPIM_P1_IO6

OCTOSPIM_P1_IO7

SAI2_SD_B

SAI2_SCK_B

SAI2_FS_B

SAI2_MCK_B

-

-

USART10_RX

USART10_TX

-

-

TIM1_BKIN2_

COMP12

-

-

-

-

OCTOSPIM_P1_NCS

-

-

-

USART10_CK

FMC_NBL0

FMC_NBL1

FMC_A23

FMC_A19

FMC_A20

FMC_A21

FMC_A22

DCMI_D2/

PSSI_D2

DCMI_D3/

PSSI_D3

-

-

DCMI_D4/

PSSI_D4

DCMI_D6/

PSSI_D6

DCMI_D7/

PSSI_D7

LCD_R0

LCD_R6

-

-

LCD_B0

LCD_G0

LCD_G1

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

FMC_D4/

FMC_DA4

FMC_D5/

FMC_DA5

FMC_D6/

FMC_DA6

FMC_D7/

FMC_DA7

FMC_D8/

FMC_DA8

FMC_D9/

FMC_DA9

-

COMP2_OUT

-

-

-

-

-

-

-

LCD_G3

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

COMP1_

OUT

LCD_B4 EVENTOUT

FMC_D10/

FMC_DA10

FMC_D11/

FMC_DA11

COMP2_OUT

-

LCD_DE

LCD_CLK

FMC_D12/

FMC_DA12

TIM1_BKIN_COMP12 LCD_R7

EVENTOUT

EVENTOUT

EVENTOUT

Table 13. Port F alternate functions

Port

PF0

PF1

PF2

PF3

PF4

PF5

PF6

PF7

PF8

PF9

PF10

PF11

PF12

PF13

PF14

PF15

AF0 AF1

SYS

LPTIM1/

TIM1/2/16/17

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

TIM16_CH1

TIM17_CH1

TIM16_CH1N

TIM17_CH1N

TIM16_BKIN

-

-

-

-

-

-

-

-

-

-

-

AF2

PDM_SAI1/

TIM3/4/5/12/15

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

SAI1_D3

AF3

DFSDM1/

LPTIM2/3/

LPUART1/

OCTOSPIM_P1/2/

TIM8

-

-

-

-

-

-

-

-

-

-

-

-

-

DFSDM1_DATIN6

DFSDM1_CKIN6

-

AF4

CEC/DCMI/

PSSI/

DFSDM1/2/

I2C1/2/3/4/

LPTIM2/

TIM15/

USART1

I2C2_SDA

I2C2_SCL

I2C2_SMBA

-

-

-

-

-

-

-

AF5 AF6 AF7

CEC/SPI1/

I2S1/SPI2/

I2S2/SPI3/

I2S3/SPI4/5/

SPI6/I2S6

DFSDM1/2/I2C4/

OCTOSPIM_P1/

SAI1/SPI3/I2S3/

UART4

SDMMC1/SPI2/

I2S2/SPI3/

I2S3/SPI6/

I2S6/UART7/

USART1/2/3/6

LPUART1/

SAI2/

SDMMC1/

SPDIFRX1/

SPI6/I2S6/

UART4/5/8

-

-

-

-

-

-

SPI5_NSS

SPI5_SCK

SPI5_MISO

SPI5_MOSI

-

-

-

-

-

-

SAI1_SD_B

SAI1_MCLK_B

SAI1_SCK_B

SAI1_FS_B

-

-

-

-

-

-

UART7_Rx

UART7_Tx

UART7_RTS

UART7_CTS

AF8

-

-

-

-

-

-

-

-

-

-

AF9

FDCAN1/2/FMC/LCD/

OCTOSPIM_P1/2/

SDMMC2/SPDIFRX1/

TIM13/14

CRS/FMC/LCD/

OCTOSPIM_P1/

OTG1_FS/OTG1_HS/

SAI2/SDMMC2/TIM8

OCTOSPIM_P2_IO0

OCTOSPIM_P2_IO1

OCTOSPIM_P2_IO2

OCTOSPIM_P2_IO3

OCTOSPIM_P2_CLK

OCTOSPIM_

P2_NCLK

-

-

TIM13_CH1

TIM14_CH1

AF10

-

-

-

-

-

-

OCTOSPIM_P1_IO3

OCTOSPIM_P1_IO2

OCTOSPIM_P1_IO0

OCTOSPIM_P1_IO1

AF11

DFSDM1/2/

I2C4/LCD/

MDIOS/

OCTOSPIM_P1/

SDMMC2/

SWPMI1/TIM1/8/

UART7/9/

USART10

-

-

-

-

-

-

-

-

-

-

PSSI_D15

-

-

SPI5_MOSI -

-

-

-

-

OCTOSPIM_P1_CLK -

SAI2_SD_B -

-

AF12

FMC/LCD/

MDIOS/

SDMMC1/

TIM1/8

FMC_A0

FMC_A1

FMC_A2

FMC_A3

FMC_A4

FMC_A5

AF13

COMP/

DCMI/

PSSI/LCD/

TIM1

-

-

-

-

-

-

AF14

LCD/

UART5

-

-

-

-

-

-

AF15

SYS

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

-

-

-

-

-

FMC_SDNRAS

-

-

-

-

DCMI_D11/

PSSI_D11

DCMI_D12/

PSSI_D12

-

-

-

-

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

LCD_DE EVENTOUT

EVENTOUT

-

I2C4_SMBA

I2C4_SCL

I2C4_SDA

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

OCTOSPIM_

P1_NCLK

OCTOSPIM_

P2_DQS

-

-

-

-

-

-

-

-

-

-

FMC_A6

FMC_A7

FMC_A8

FMC_A9

-

-

-

-

-

-

-

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

Table 14. Port G alternate functions

AF6 AF7 AF8 AF9

Port

PG0

PG1

PG2

PG3

PG4

PG5

PG6

PG7

PG8

PG9

PG10

PG11

PG12

PG13

PG14

PG15

AF0

SYS

-

-

-

-

-

-

-

-

-

-

-

-

-

TRACED0

TRACED1

-

AF1 AF2 AF3 AF4 AF5

LPTIM1/

TIM1/2/16/17

PDM_SAI1/

TIM3/4/5/12/15

DFSDM1/LPTIM2/3/

LPUART1/

OCTOSPIM_P1/2/

TIM8

CEC/DCMI/

PSSI/

DFSDM1/2/

I2C1/2/3/4/

LPTIM2/

TIM15/

USART1

CEC/SPI1/

I2S1/SPI2/

I2S2/SPI3/

I2S3/

SPI4/5/

SPI6/I2S6

DFSDM1/2/

I2C4/

OCTOSPIM_P1/

SAI1/SPI3/I2S3/

UART4

SDMMC1/

SPI2/I2S2/

SPI3/I2S3/

SPI6/I2S6/

UART7/

USART1/2/3/6

LPUART1/

SAI2/

SDMMC1/

SPDIFRX1/

SPI6/I2S6/

UART4/5/8

FDCAN1/2/FMC/LCD

/OCTOSPIM_P1/2/

SDMMC2/SPDIFRX1/

TIM13/14

-

-

-

-

TIM1_BKIN2

TIM1_ETR

TIM17_BKIN

-

-

-

-

LPTIM1_IN2

LPTIM1_IN1

LPTIM1_OUT

LPTIM1_ETR

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

TIM8_BKIN

TIM8_BKIN2

-

-

-

-

TIM8_ETR

-

OCTOSPIM_P2_IO6

-

OCTOSPIM_P2_NCS

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

OCTOSPIM_P2_IO4

OCTOSPIM_P2_IO5

-

-

-

-

-

-

SPI6_NSS/

I2S6_WS

SPI1_MISO/

I2S1_SDI

SPI1_NSS/

I2S1_WS

SPI1_SCK/

I2S1_CK

SPI6_MISO/

I2S6_SDI

SPI6_SCK/

I2S6_CK

SPI6_MOSI/

I2S6_SDO

-

SAI1_MCLK_A USART6_CK

-

-

-

-

-

-

-

USART6_RTS

USART6_RX

-

-

USART6_RTS

USART6_CTS/

USART6_NSS

USART6_TX

USART6_CTS/

USART6_NSS

-

SPDIFRX1_IN2

SPDIFRX1_IN3

-

SPDIFRX1_IN0

SPDIFRX1_IN1

-

-

-

OCTOSPIM_P2_DQS

-

OCTOSPIM_P1_IO6

LCD_G3

OCTOSPIM_P2_IO7

LCD_B4

-

OCTOSPIM_P1_IO7

OCTOSPIM_P2_DQS

AF10

CRS/FMC/LCD/

OCTOSPIM_P1/

OTG1_FS/

OTG1_HS/SAI2/

SDMMC2/TIM8

-

-

-

-

-

-

AF11

DFSDM1/2/

I2C4/LCD/

MDIOS/

OCTOSPIM_P1/

SDMMC2/

SWPMI1/

TIM1/8/

UART7/9/

USART10

UART9_RX

UART9_TX

TIM8_BKIN_

COMP12

TIM8_BKIN2_

COMP12

TIM1_BKIN2_

COMP12

-

AF12

FMC/LCD/

MDIOS/

SDMMC1/

TIM1/8

FMC_A10

FMC_A11

FMC_A12

FMC_A13

FMC_A14/

FMC_BA0

FMC_A15/

FMC_BA1

OCTOSPIM_P1_NCS

-

-

-

-

-

AF13

COMP/DCMI/

PSSI/LCD/

TIM1

-

-

-

-

-

AF14

LCD/

UART5

-

-

-

-

-

AF15

SYS

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

FMC_NE3

FMC_INT

FMC_SDCLK

EVENTOUT

DCMI_D12/

PSSI_D12

DCMI_D13/

PSSI_D13

LCD_R7 EVENTOUT

LCD_CLK EVENTOUT

LCD_G7 EVENTOUT

SAI2_FS_B

SAI2_SD_B

SDMMC2_D2

SDMMC2_D3

SDMMC2_D6

SDMMC2_D7

-

SDMMC2_D0

SDMMC2_D1

USART10_RX

USART10_TX

USART10_CTS/

USART10_NSS

USART10_RTS

-

FMC_NE2/

FMC_NCE

FMC_NE3

-

DCMI_VSYNC/

PSSI_RDY

DCMI_D2/

PSSI_D2

DCMI_D3/

PSSI_D3

-

LCD_B2 EVENTOUT

LCD_B3

EVENTOUT

EVENTOUT

LCD_B1 EVENTOUT

-

-

-

-

-

DCMI_D13/

PSSI_D13

LCD_R0

LCD_B0

-

EVENTOUT

EVENTOUT

EVENTOUT

Table 15. Port H alternate functions

Port

PH0

PH1

PH2

PH3

PH4

PH5

PH6

PH7

PH8

PH9

PH10

PH11

PH12

PH13

PH14

PH15

AF0

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

AF1

SYS

LPTIM1/

TIM1/2/16/17

-

-

LPTIM1_IN2

-

-

-

-

-

-

-

-

-

-

-

-

-

AF2

PDM_SAI1/

TIM3/4/5/12/15

DFSDM1/

LPTIM2/3/

LPUART1/

OCTOSPIM_P1/2/

TIM8

-

-

-

-

-

-

TIM12_CH1

-

TIM5_ETR

TIM12_CH2

TIM5_CH1

TIM5_CH2

TIM5_CH3

-

-

-

AF3

-

-

-

-

-

-

-

-

-

-

-

-

-

TIM8_CH1N

TIM8_CH2N

TIM8_CH3N

AF4

CEC/DCMI/

PSSI/

DFSDM1/2/

I2C1/2/3/4/

LPTIM2/

TIM15/

USART1

-

-

-

-

I2C2_SCL

I2C2_SDA

I2C2_SMBA

I2C3_SCL

I2C3_SDA

I2C3_SMBA

I2C4_SMBA

I2C4_SCL

I2C4_SDA

-

-

-

AF5 AF6 AF7 AF8 AF9 AF10

CEC/SPI1/

I2S1/SPI2/

I2S2/SPI3/

I2S3/SPI4/5/

SPI6/I2S6

DFSDM1/2/I2C4/

OCTOSPIM_P1/

SAI1/SPI3/I2S3/

UART4

SDMMC1/SPI2/

I2S2/SPI3/I2S3/

SPI6/I2S6/

UART7/

USART1/2/3/6

LPUART1/

SAI2/

SDMMC1/

SPDIFRX1/

SPI6/I2S6/

UART4/5/8

FDCAN1/2/FMC/LCD

/OCTOSPIM_P1/2/

SDMMC2/SPDIFRX1/

TIM13/14

CRS/FMC/LCD/

OCTOSPIM_P1/

OTG1_FS/

OTG1_HS/SAI2/

SDMMC2/TIM8

-

-

-

-

-

SPI5_NSS -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

OCTOSPIM_P1_IO4

OCTOSPIM_P1_IO5

LCD_G5

-

-

-

SAI2_SCK_B

SAI2_MCK_B

OTG_HS_

ULPI_NXT

-

AF11

DFSDM1/2/

I2C4/LCD/

MDIOS/

OCTOSPIM_P1/

SDMMC2/

SWPMI1/TIM1/8/

UART7/9/

USART10

-

-

-

-

AF12

FMC/LCD/

MDIOS/

SDMMC1/

TIM1/8

-

-

FMC_SDCKE0

FMC_SDNE0

-

-

FMC_SDNWE

AF13

COMP/DCMI/

PSSI/LCD/TIM1

LCD/

UART5

-

-

-

-

PSSI_D14

AF14

-

-

LCD_R0

LCD_R1

LCD_G4

AF15

SYS

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

SPI5_SCK

SPI5_MISO

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

UART4_TX

UART4_RX

-

-

-

-

-

-

-

-

FDCAN1_TX

FDCAN1_RX

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

FMC_SDNE1

FMC_SDCKE1

FMC_D16

FMC_D17

FMC_D18

FMC_D19

FMC_D20

FMC_D21

FMC_D22

FMC_D23

-

DCMI_D8/

PSSI_D8

DCMI_D9/

PSSI_D9

DCMI_HSYNC/

PSSI_DE

DCMI_D0/

PSSI_D0

DCMI_D1/

PSSI_D1

DCMI_D2/

PSSI_D2

DCMI_D3/

PSSI_D3

-

DCMI_D4/

PSSI_D4

DCMI_D11/

PSSI_D11

-

-

-

LCD_R2

LCD_R3

LCD_R4

LCD_R5

LCD_R6

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

LCD_G2 EVENTOUT

LCD_G3 EVENTOUT

LCD_G4 EVENTOUT

Table 16. Port I alternate functions

Port

PI0

PI1

PI2

PI3

PI4

PI5

PI6

PI7

PI8

PI9

PI10

AF0

-

-

-

-

-

-

-

-

-

-

-

AF1

-

-

-

-

-

-

-

-

-

-

-

AF2

TIM5_CH4

-

-

-

-

-

-

-

-

-

-

AF3

SYS

LPTIM1/

TIM1/2/16/17

PDM_SAI1/

TIM3/4/5/12/15

DFSDM1/LPTIM2/3/

LPUART1/

OCTOSPIM_P1/2/

TIM8

-

TIM8_BKIN2

TIM8_CH4

TIM8_ETR

TIM8_BKIN

TIM8_CH1

TIM8_CH2

TIM8_CH3

-

OCTOSPIM_P2_IO0

OCTOSPIM_P2_IO1

AF4

CEC/DCMI/

PSSI/

DFSDM1/2/

I2C1/2/3/4/

LPTIM2/

TIM15/

USART1

AF5

CEC/SPI1/

I2S1/SPI2/

I2S2/SPI3/

I2S3/SPI4/5/

SPI6/I2S6

-

-

-

SPI2_NSS/

I2S2_WS

SPI2_SCK/

I2S2_CK

SPI2_MISO/

I2S2_SDI

AF6 AF7 AF8

DFSDM1/2/I2C4/

OCTOSPIM_P1/

SAI1/SPI3/I2S3/

UART4

SDMMC1/SPI2/

I2S2/SPI3/

I2S3/SPI6/

I2S6/UART7/

USART1/2/3/6

LPUART1/

SAI2/

SDMMC1/

SPDIFRX1/

SPI6/I2S6/

UART4/5/8

FDCAN1/2/FMC/L

CD/

OCTOSPIM_P1/2/

SDMMC2/

SPDIFRX1/

TIM13/14

-

-

-

-

-

-

-

-

-

AF9

-

-

-

-

-

-

-

-

-

-

-

SPI2_MOSI/

I2S2_SDO

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

UART4_RX

-

-

-

-

-

-

-

FDCAN1_RX

-

AF10

CRS/FMC/LCD/

OCTOSPIM_P1/

OTG1_FS/

OTG1_HS/SAI2/

SDMMC2/TIM8

DFSDM1/2/I2C4/LCD/

MDIOS/OCTOSPIM_P1/

SDMMC2/SWPMI1/

TIM1/8/UART7/9/

USART10

FMC/LCD/

MDIOS/

SDMMC1/

TIM1/8

-

-

-

-

SAI2_MCK_A

SAI2_SCK_A

SAI2_SD_A

SAI2_FS_A

-

-

-

AF11

-

TIM8_BKIN2_COMP12

-

-

TIM8_BKIN_COMP12

-

-

-

-

-

-

AF12

FMC_D30

FMC_D31

AF13

COMP/DCMI/

PSSI/LCD/TIM1

FMC_D24

FMC_D25

FMC_D26

FMC_D27

FMC_NBL2

FMC_NBL3

FMC_D28

FMC_D29

-

DCMI_D13/

PSSI_D13

DCMI_D8/

PSSI_D8

DCMI_D9/

PSSI_D9

DCMI_D10/

PSSI_D10

DCMI_D5/

PSSI_D5

DCMI_VSYNC/

PSSI_

RDY

DCMI_D6/

PSSI_D6

DCMI_D7/

PSSI_D7

-

-

PSSI_D14

AF14

LCD/

UART5

AF15

SYS

LCD_G5 EVENTOUT

LCD_G6 EVENTOUT

LCD_G7 EVENTOUT

-

LCD_B4

LCD_B5

LCD_B6

LCD_B7

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

-

LCD_

VSYNC

LCD_

HSYNC

EVENTOUT

EVENTOUT

EVENTOUT

PI11 OCTOSPIM_P2_IO2 LCD_G6

OTG_HS_

ULPI_DIR

PSSI_D15 EVENTOUT

6

6.1

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

STM32H7B0xB

Electrical characteristics

Electrical characteristics

Parameter conditions

Unless otherwise specified, all voltages are referenced to V

SS

.

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of junction temperature, supply voltage and frequencies by tests in production on 100% of the devices with an junction temperature at T

J

= 25 °C and T

J

= T

Jmax

(given by the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3σ).

Typical values

Unless otherwise specified, typical data are based on T

J

= 25 °C, V

DD

= 3.3 V (for the 1.62 V ≤ V

DD

≤ 3.6 V voltage range). They are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2σ).

Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

Loading capacitor

The loading conditions used for pin parameter measurement are shown in

Figure 10. Pin loading conditions .

Pin input voltage

The input voltage measurement on a pin of the device is described in

Figure 11. Pin input voltage .

Figure 10. Pin loading conditions

C = 50 pF

MCU pin

Figure 11. Pin input voltage

MCU pin

VIN

DS13196 - Rev 6 page 62/199

STM32H7B0xB

Parameter conditions

6.1.6

Power supply scheme

Figure 12. Power supply scheme

V

DDSMPS VDDSMPS

10 μF

4.7 μF

4.7

μ F

4.7 μF

SMPS enabled

2.2 μF

2.2 μH

LDO enabled

VLXSMPS

SMPS disabled

100 pF or 200 pF

VFBSMPS

VSSSMPS

VCAP1/2

100 nF (1)

VCAP3

LDO disabled

VDDLDO

Two different possible use cases

V

DD

100nF

PDR_ON

V

DD

SMPS

Switched Mode

Power Supply step down converter

LDO

Voltage regulator

V

DDMMC

1 μF

100 nF

VDDMMC

100 nF

Two different possible use cases

100 nF (1)

VDD

VDD

4.7 μF

100 nF (1)

VSS

Two different possible use cases

Battery

1 μF

VBAT

100 nF

V

DDMMC

IOs

V

DD

IOs

POR/PDR

V

DD domain

Power switch

BKUP

IOs

V

V

DDA

REF+

5V

4.7 μF

3.3V

1 μF

1 μF 100 nF

Two different possible use cases

VDD50USB

VDD33USB

47W

1 μF

1 μF 1 μF 100 nF

Three different possible use cases

VDDA

100 nF

VREF+

VREF-

VSSA

USB regulator

USB FS

IOs

Analog domain

Core domain

Backup domain

Defines different use case options

Define power domaines

DS13196 - Rev 6 page 63/199

STM32H7B0xB

Absolute maximum ratings

Note:

Caution:

6.1.7

1.

100 nF filtering capacitor on each package pin.

2.

A tolerance of +/- 20% is acceptable on decoupling capacitors.

Refer to Getting started with STM32H7A3/7B3 and STM32H7B0 hardware development(AN5307) for more details.

Each power supply pair (V

DD

/V

SS

, V

DDA

/V

SSA

...) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device.

Current consumption measurement

Figure 13. Current consumption measurement scheme

LDO ON

I

DD

_V

BAT

V

BAT

SMPS ON

I

DD

_V

BAT

V

BAT

I

DD

V

DDMMC

V

DD

V

DDLDO

V

DDA

I

DD

V

DDMMC

V

DD

V

DDSMPS

V

DDA

6.2

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 17. Voltage characteristics ,

Table 18. Current characteristics

, and

Table 19. Thermal characteristics may cause permanent damage to the device. These are

stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand.

Table 17. Voltage characteristics

All main power (V

DD

, V

DDA

, V

DD33USB

, V

DDMMC external power supply, in the permitted range.

, V

DDSMPS

, V

BAT

) and ground (V

SS

, V

SSA

) pins must always be connected to the

Symbols Ratings Min Max Unit

V

DDX

− V

SS

External main supply voltage (including V

DD

V

DDA

, V

DD33USB

, V

DDMMC,

V

BAT

, V

REF+

)

, V

DDLDO

, V

DDSMPS

,

−0.3

4.0

V

V

IN

(1)

Input voltage on FT_xxx pins

Input voltage on TT_xx pins

V

SS

−0.3

Min(V

DD

, V

DDA

,

V

DD33USB

, V

DDMMC

,

V

BAT

) +4.0

(2)(3)

4.0

V

V

Input voltage on BOOT0 pin

Input voltage on any other pins

V

SS

−0.3

V

SS

V

SS

−0.3

9.0

4.0

V

V

|ΔV

DDX

| Variations between different V

DDX

power pins of the same domain 50 mV

DS13196 - Rev 6 page 64/199

DS13196 - Rev 6

STM32H7B0xB

Absolute maximum ratings

Symbols Ratings

|V

SSx

−V

SS

| Variations between all the different ground pins

Min

-

Max

50

1. V

IN

maximum value must always be respected. Refer to

Table 62. I/O current injection susceptibility

for the maximum allowed injected current values.

2. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.

3. This formula has to be applied on power supplies related to the I/O structure described by the pin definition table.

Unit mV

Table 18. Current characteristics

Symbols

ΣIV

DD

ΣIV

SS

IV

DD

IV

SS

I

IO

Ratings

Total current into sum of all V

DD

power lines (source)

(1)

Total current out of sum of all V

SS

ground lines (sink) (1)

Maximum current into each V

DD

power pin (source) (1)

Maximum current out of each V

SS

ground pin (sink)

(1)

Output current sunk by any I/O and control pin

Max

620

620

100

100

Unit

20 mA

I

ΣI

(PIN)

INJ(PIN)

(3)(4)

Total output current sunk by sum of all I/Os and control pins (2)

Total output current sourced by sum of all I/Os and control pins (2)

Injected current on FT_xxx, TT_xx, RST and B pins except PA4, PA5

Injected current on PA4, PA5

Total injected current (sum of all I/Os and control pins) (5)

140

140

−5/+0

−0/0

ΣI

INJ(PIN)

±25

1. All main power (V

DD

, V

DDA

, V

DDSMPS

, V

DDLDO

, V

DD33USB

, V

DDMMC

) and ground (V connected to the external power supplies, in the permitted range.

SS

, V

SSA

) pins must always be

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.

3. A positive injection is induced by V

IN

>V

DD

while a negative injection is induced by V

IN

<V

SS

. I

INJ(PIN)

must never be

exceeded. Refer also to Table 17. Voltage characteristics for the maximum allowed input voltage values.

4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

5. When several inputs are submitted to a current injection, the maximum ∑I

INJ(PIN)

is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 19. Thermal characteristics

Symbol

T

STG

T

J

Storage temperature range

Ratings

Maximum junction temperature

1. The junction temperature is limited to 105 °C in the VOS0 voltage range.

Value

−65 to +150

130 (1)

Unit

°C page 65/199

6.3

6.3.1

STM32H7B0xB

Operating conditions

Operating conditions

General operating conditions

Symbol

V

DD

V

DDLDO

V

DDSMPS

V

DDMMC

V

DD33USB

V

DDA

V

BAT

Table 20. General operating conditions

Parameter

Standard operating voltage

Supply voltage for the internal regulator

Operating conditions Min Typ

-

VDDLDO ≤ VDD

1.62

(1)

1.62

(1)

-

-

1.2

(2)

-

Supply voltage for the internal SMPS Step-down converter

VDDSMPS = VDD 1.62

(1)

-

Standard operating voltage for independent MMC

I/Os

Standard operating voltage, USB domain

Analog operating voltage

Backup operating voltage

Indenpent MMC I/Os used

Independent MMC I/Os not used V

DDMMC

=

V

DD

USB used

1.62

3.0

0

(1)

1.62

(1)

USB not used

ADC or COMP used

DAC used

1.62

1.8

OPAMP used

VREFBUF used

ADC, DAC, OPAMP,

COMP, VREFBUF not used

-

2.0

1.8

0

1.2

TT_xx I/O

BOOT0

−0.3

0

-

-

-

-

-

-

-

-

-

-

-

-

V

IN

V

CORE

I/O Input voltage

Internal regulator ON (LDO or SMPS)

(4)

Regulator OFF: external V

CORE

voltage must be supplied from external regulator on VCAP pins

Max

3.6

3.6

3.6

3.6

3.6

3.6

3.6

3.6

3.6

All I/O except BOOT0 and TT_xx

−0.3

-

VOS3 (max frequency

88 MHz)

VOS2 (max frequency

160 MHz)

VOS1 (max frequency

225 MHz)

VOS0 (max frequency

280 MHz)

VOS3 (max frquency

88 MHz)

VOS2 (max frequency

160 MHz)

VOS1 (max frequency

225 MHz)

0.95

1.0

1.05

1.10

1.15

1.20

1.25

1.30

0.97

1.0

1.07

1.10

1.17

1.20

3.6

V

DD

+0.3

9

Min(V

DD

,

V

DDA

,

V

DD33USB

,

V

DDMMC

)

+3.6 V <

5.5 V (3)

1.05

1.15

1.25

1.35

1.05

1.15

1.25

Unit

V

DS13196 - Rev 6 page 66/199

DS13196 - Rev 6

STM32H7B0xB

Operating conditions f

DFSDM2_Aclk f

DFSDM2_Clk f fdcan_ker_ck f cec_ker_ck f

I2C_ker_ck f lptim_ker_ck f rcc_tim_ker_ck f rcc_tim_ker_ck f rng_clk f sai_a_ker_ck f sai_b_ker_ck f sai_a_ker_ck

Symbol

(1)(2)

f

CPU f

ACLK f

HCLK f

PCLK f

TraceCK

/ f

JTCK f ltdc_ker_ck f fmc_ker_ck f octospi_ker_clk f sdmmc_ker_ck f

DFSDM1_Aclk f

DFSDM1_Clk

Symbol

V

CORE

T

A

Parameter

Regulator OFF: external V

CORE

voltage must be supplied from external regulator on VCAP pins

Ambient temperature for the suffix 6 version

Operating conditions Min Typ

VOS0 (max frequency

280 MHz)

1.27

1.30

Maximum power dissipation

Low-power dissipation

(5)

VOS0

VOS3, VOS2, VOS1

–40

–40

–40

–40

-

-

-

-

Max

1.33

85

105

Unit

V

°C

T

J

Junction temperature range

105

130

°C

1. When a reset occurs, the functionality is guaranteed down to V

PDRmax

or to the specified V

DDmin

when the PDR is

OFF. The PDR can only be switched OFF though the PDR_ON pin that is not available in all packages (refer to

Table 7. STM32H7B0xB pin/ball definition

)

2. Only for power-up sequence when the SMPS step-down converter is configured to supply the LDO.

3. This formula has to be applied on power supplies related to the I/O structures described by the pin definition table.

4. At startup, the external V

CORE

voltage must remain higher or equal to 1.10 V before disabling the internal regulator (LDO).

5. In low-power dissipation state, T

A

can be extended to this range as long as T

Section 7.7 Thermal characteristics

).

J

does not exceed T

Jmax

(see

Table 21. Maximum allowed clock frequencies

Parameter

CPU

AXI

AHB

APB

Trace / JTAG

LTDC

FMC

OCTOSPI1/2

SDMMC1/2

DFSDM1

DFSDM2

FDCAN

HDMI_CEC

I2C[1:4]

LPTIM[1:3]

TIM[2:7],TIM[12:14]

PWM1,PWM8,TIM[15:17]

RNG

40

140

280

280

280

140

140

VOS0

280

280

280

140

140

140

140

66

140

140

280

280

140

35

112.5

225

225

225

112.5

112.5

VOS1

225

225

225

112.5

112.5

112.5

112.5

66

112.5

112.5

225

225

112.5

SAI1 150 150

40

80

160

160

160

80

80

VOS2

160

160

160

80

66

80

80

80

80

80

160

160

80

80

SAI2 150 150 80

88

88

44

44

20

44

88

VOS3

88

88

88

44

44

44

44

44

44

44

88

88

44

80

80

Unit

MHz page 67/199

DS13196 - Rev 6

STM32H7B0xB

Operating conditions

Symbol

(1)(2)

f sai_b_ker_ck f spdifrx_ker_ck f spi_ker_ck f lpuart_ker_ck f usart_ker_ck f uart_ker_ck f adp_clk f ulpi_ck f adc_ker_ck f dac_pclk f rtc_ker_ck

Parameter

SAI2

SPDIFRX1

SPI[1:6]

LPUART1

USART1/2/3/6/10

UART4/5/7/8/9

USBOTG

USB1ULPI

ADC1/2

DAC1/2

RTC

VOS0

150

280

280

140

280

280

48

66

50

140

1

VOS1

150

225

225

112.5

225

225

48

66

50

112.5

1

VOS2

80

160

160

80

160

160

48

66

50

80

1

VOS3

80

88

88

44

88

88

48

66

50

44

1

Unit

MHz

1. Guaranteed by design.

2. The maximum kernel clock frequencies can be limited by the maximum peripheral clock frequency (refer each peripheral electrical characteristics).

Power scale

VOS0

VOS1

VOS2

VOS3

SVOS4

SVOS5

Table 22. Supply voltage and maximum frequency configuration

V

CORE

source

LDO/SMPS

LDO/SMPS

LDO/SMPS

LDO/SMPS

LDO/SMPS

LDO/SMPS

Max T

J

(°C)

105

130

130

130

130

130

Max frequency (MHz)

280

225

160

88

N/A

N/A

Min V

DD

(V)

1.71

1.62

1.62

1.62

1.62

1.62

page 68/199

6.3.2

6.3.3

STM32H7B0xB

Operating conditions

VCAP external capacitor

Stabilization for the embedded LDO regulator is achieved by connecting an external capacitor C

EXT

to the VCAPx pin. C

EXT

is specified in

Table 23. VCAP operating conditions . Two external capacitors must be connected to

VCAP pins (refer to Getting started with STM32H7A3/7B3 and STM32H7B0 hardware development (AN5307).

Figure 14. External capacitor C

EXT

C

ESR

R

Leak

1.

Legend: ESR is the equivalent series resistance.

Table 23. VCAP operating conditions

When the internal LDO voltage regulator is switched OFF, the two 2.2 µF VCAP capacitors are not required. However all VCAPx package pins must be connected together and it is recommended to add a ceramic filtering capacitor of 100 nF as close as possible to each VCAPx pin.

Symbol Parameter Conditions

CEXT

ESR

External capacitor for LDO enabled

ESR of external capacitor

2.2 µF

(1)(2)

< 100 mΩ

1. This value corresponds to CEXT typical value. A variation of ±20% is tolerated.

2. If the VCAP3 pin is available (depending on the package), it must be connected to the other VCAP pins. No additional capacitor is required.

SMPS step-down converter

The devices embed a high power efficiency SMPS step-down converter requiring external components. Refer to Getting started with STM32H7A3/7B3 and STM32H7B0 hardware development (AN5307) for the required components and tradeoffs.

Table 24. Characteristics of SMPS step-down converter external components

Symbol Parameter

Capacitance of external capacitor on VDDSMPS

C

IN

ESR of external capacitor

C filt

Capacitance of external capacitor on VLXSMPS pin

Capacitance of external capacitor on VFBSMPS pin

C

OUT

L

-

ESR of external capacitor

Inductance of external Inductor on VLXSMPS pin

Serial DC resistor

I

SAT

I

RMS

DC current at which the inductance drops 30% from its value without current.

Average current for a 40 °C rise: rated current for which the temperature of the inductor is raised 40°C by DC current

Conditions

4.7 µF

100 mΩ

220 pF

10 µF

20 mΩ

2.2 µH

150 mΩ

1.7 A

1.4 A

DS13196 - Rev 6 page 69/199

DS13196 - Rev 6

STM32H7B0xB

Operating conditions

Table 25. SMPS step-down converter characteristics for external usage

V

Symbol

DDSMPS

(1)

Conditions

V

OUT

= 1.8 V

V

OUT

= 2.5 V

Min

2.3

3

V

OUT

(2)

I

OUT

=600 mA

I

OUT internal and external usage

External usage only (3)

-

T

RDS

ON

IDD

SMPS_Q

SMPS_START

Quiescent current

V

OUT

= 1.8 V

V

OUT

= 2.5 V

1. The switching frequency is 2.4 MHz±10%

2. Including line transient and load transient.

3. These characteristics are given for SMPSEXTHP bit is set in the PWR_CR3 register.

-

-

-

-

2.25

1.62

-

-

Typ

-

-

-

-

2.5

1.8

100

220

270

360

Max

3.6

3.6

2.75

1.98

600

600

120

-

405

540

Unit

The SMPS current consumption can be determined using the following formula based on the maximum LDO current consumption provided in

Section 6.3.7 Supply current characteristics :

I

DDSMPS where

= I

DDLDO

× V

CORE

÷ V

DD

× efficency

I

DDLDO

is the current in LDO configuration given in the following tables

V

CORE

is the digital core supply (V

CAP

)

Efficiency is defined in the following curves.

V

V mA mΩ

µA

µs page 70/199

DS13196 - Rev 6

STM32H7B0xB

Operating conditions

Figure 15. SMPS efficicency vs load current in Run, Sleep and Stop mode with SVOS3 MR mode,

T

J

= 30 °C

Efficiency (%)

100

90

80

70

60

50

40

30

1 10 100

VDDSMPS = 1.8V, VOS0

VDDSMPS = 3.3V, VOS0

VDDSMPS = 1.8V, VOS1

VDDSMPS = 3.3V, VOS1

VDDSMPS = 1.8V, VOS2

VDDSMPS = 3.3V, VOS2

VDDSMPS = 1.8V, VOS3

VDDSMPS = 3.3V, VOS3

1000

Current (mA)

Figure 16. SMPS efficiency vs load current in Run, Sleep and Stop mode with SVOS3 MR mode,

T

J

= 130 °C

Efficiency (%)

100

90

80

70

60

50

40

30

1 10 100

VDDSMPS = 1.8V, VOS0

VDDSMPS = 3.3V, VOS0

VDDSMPS = 1.8V, VOS0

VDDSMPS = 3.3V, VOS0

VDDSMPS = 1.8V, VOS1

VDDSMPS = 3.3V, VOS1

VDDSMPS = 1.8V, VOS2

VDDSMPS = 3.3V, VOS2

VDDSMPS = 1.8V, VOS3

VDDSMPS = 3.3V, VOS3

1000

Current (mA) page 71/199

DS13196 - Rev 6

STM32H7B0xB

Operating conditions

Figure 17. SMPS efficiency vs load current in Stop and DStop modes (SVOS3 LP mode, SVOS4, SVOS5),

T

J

= 30 °C

Efficiency (%)

100

40

30

20

10

0

0.01

90

80

70

60

50

0.1

1 10

VDDSMPS = 1.8V, SVOS5

VDDSMPS = 3.3V, SVOS5

VDDSMPS = 1.8V, SVOS4

VDDSMPS = 3.3V, SVOS4

VDDSMPS = 1.8V, SVOS3

VDDSMPS = 3.3V, SVOS3

100

Current (mA)

Figure 18. SMPS efficiency vs load current in Stop and DStop modes (SVOS3 LP mode, SVOS4, SVOS5),

T

J

= 130 °C

Efficiency (%)

100

90

60

50

40

30

20

80

70

10

0

0.01

0.1

1 10

VDDSMPS = 1.8V, SVOS5

VDDSMPS = 3.3V, SVOS5

VDDSMPS = 1.8V, SVOS4

VDDSMPS = 3.3V, SVOS4

VDDSMPS = 1.8V, SVOS3

VDDSMPS = 3.3V, SVOS3

100

Current (mA) page 72/199

6.3.4

STM32H7B0xB

Operating conditions

Figure 19. SMPS efficiency vs load current in Stop and DStop2 modes (SVOS3 LP mode, SVOS4, SVOS5),

T

J

= 30 °C

Efficiency (%)

100

40

30

20

10

0

0.01

90

80

70

60

50

0.1

1 10

VDDSMPS = 1.8V, SVOS5 in Stop2 mode

VDDSMPS = 3.3V, SVOS5 in Stop2 mode

VDDSMPS = 1.8V, SVOS4 in Stop2 mode

VDDSMPS = 3.3V, SVOS4 in Stop2 mode

VDDSMPS = 1.8V, SVOS3 in Stop2 mode

VDDSMPS = 3.3V, SVOS3 in Stop2 mode

100

Current (mA)

Figure 20. SMPS efficiency vs load current in Stop and DStop2 modes (SVOS3 LP mode, SVOS4, SVOS5),

T

J

= 130 °C

Efficiency (%)

100

60

50

40

30

20

10

0

0.01

90

80

70

0.1

1 10

VDDSMPS = 1.8V, SVOS5 in Stop2 mode

VDDSMPS = 3.3V, SVOS5 in Stop2 mode

VDDSMPS = 1.8V, SVOS4 in Stop2 mode

VDDSMPS = 3.3V, SVOS4 in Stop2 mode

VDDSMPS = 1.8V, SVOS3 in Stop2 mode

VDDSMPS = 3.3V, SVOS3 in Stop2 mode

100

Current (mA)

Operating conditions at power-up / power-down

Subject to general operating conditions for T

A

.

Operating conditions at power-up / power-down (regulator ON)

DS13196 - Rev 6 page 73/199

6.3.5

STM32H7B0xB

Operating conditions

Symbol t

VDD t

VDDA t

VDDUSB

VDDMMC

Table 26. Operating conditions at power-up / power-down (regulator ON)

V

DD

rise time rate

V

DD

fall time rate

V

DDA

rise time rate

V

DDA

fall time rate

V

DDUSB

rise time rate

V

DDUSB

fall time rate

V

DDMMC

rise time rate

V

DDMMC

fall time rate

Parameter

10

0

10

Min

0

10

0

0

10

∞

∞

∞

Max

∞

∞

∞

∞

∞

Unit

µs/V

Embedded reset and power control block characteristics

The parameters given in Table 27. Reset and power control block characteristics

are derived from tests performed under ambient temperature and V

DD

supply voltage conditions summarized in Table 20. General operating conditions .

Symbol t

RSTTEMPO

(1)

V

POR/PDR

V

BOR1

V

BOR2

V

BOR3

V

PVD0

V

PVD1

V

PVD2

V

PVD3

V

PVD4

V

PVD5

V

PVD6

V

POR/PDR

Table 27. Reset and power control block characteristics

Parameter

Reset temporization after POR released

Power-on/power-down reset threshold

Brown-out reset threshold 1

Brown-out reset threshold 2

Brown-out reset threshold 3

Programmable Voltage Detector threshold 0

Programmable Voltage Detector threshold 1

Programmable Voltage Detector threshold 2

Programmable Voltage Detector threshold 3

Programmable Voltage Detector threshold 4

Programmable Voltage Detector threshold 5

Programmable Voltage Detector threshold 6

Hysteresis for power-on/power-down reset

Conditions

-

Min

-

Typ

377

Max

550

Rising edge

(1)

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

1.62 1.67

1.71

1.58 1.62

1.68

2.04 2.10

2.15

1.95 2.00

2.06

2.34 2.41

2.47

2.25 2.31

2.37

2.63 2.70

2.78

2.54 2.61

2.68

1.90 1.96

2.01

1.81 1.86

1.91

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

2.05 2.10

2.16

1.96 2.01

2.06

2.19 2.26

2.32

2.10 2.15

2.21

2.35 2.41

2.47

Falling edge

Rising edge

Falling edge

2.25 2.31

2.37

2.49 2.56

2.62

2.39 2.45

2.51

Rising edge

Falling edge

2.64 2.71

2.78

2.55 2.61

2.68

Rising edge 2.78 2.86

2.94

Falling edge in Run mode 2.69 2.76

2.83

Hysteresis in Run mode 43 -

Unit

µs

V mV

DS13196 - Rev 6 page 74/199

6.3.6

STM32H7B0xB

Operating conditions

Symbol

V hyst_BOR_PVD

I

DD_BOR_PVD

(1)

I

DD_POR_PDR

V

AVM_0

V

AVM_1

V

AVM_2

Parameter

Hysteresis voltage of BOR

BOR and PVD consumption from V

DD

POR and PDR consumption from V

DD

Analog voltage detector for VDDA threshold 0

Analog voltage detector for VDDA threshold 1

Analog voltage detector for VDDA threshold 2

V

AVM_3

Analog voltage detector for VDDA threshold 3

V hyst_VDDA

I

DD_PVM

I

DD_VDDA

Hysteresis of VDDA voltage detector

PVM consumption from VDD

(1)

Voltage detector consumption on VDDA

1. Guaranteed by design.

(1)

Conditions

Hysteresis in Run mode

-

-

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

-

-

Resistor bridge

Min Typ Max Unit

100 mV

0.630

0.8

1.2

1.66 1.71

1.76

1.56 1.61

1.66

2.06 2.12

2.19

1.96 2.02

2.08

2.42 2.50

2.58

2.35 2.42

2.49

2.74 2.83

2.91

2.64 2.72

2.80

-

100

-

µA

V

mV

0.25

µA

2.5

µA

Embedded reference voltage

The parameters given in Table 28

are derived from tests performed under ambient temperature and V

DD

voltage conditions summarized in Table 20. General operating conditions

.

supply

Table 28. Embedded reference voltage

Symbol

V

REFINT

(1)

Parameter

Internal reference voltages

Conditions

−40 °C < T

J

< 130 °C t t

S_vrefint

(2)(3)

t

S_vbat

(3)

start_vrefint

(3)

ADC sampling time when reading the internal reference voltage

V

BAT

sampling time when reading the internal

V

BAT

reference voltage

Start time of reference voltage buffer when

ADC is enable

Reference Buffer consumption for ADC

-

-

-

Irefbuf (3)

V

DD

= 3.3 V

ΔVREFINT

(3)

Internal reference voltage spread over the temperature range

−40 °C < T

J

< 130 °C

T coeff

V

DDcoeff

V

REFINT_DIV1

V

REFINT_DIV2

V

REFINT_DIV3

Average temperature coefficient

Average Voltage coefficient

1/4 reference voltage

1/2 reference voltage

3/4 reference voltage

Average temperature coefficient

3.0 V < V

-

-

-

DD

< 3.6 V

1. Guaranteed by design and tested in production at 3.3 V

2. The shortest sampling time for the application can be determined by multiple iterations.

3. Guaranteed by design.

Min Typ Max

1.180 1.216 1.255

4.3

9

-

-

-

-

-

9

-

-

-

-

-

5

20

-

-

4.4

13.5

23

15

70

Unit

V

µs

µs

µA mV ppm/°C

10 1370 ppm/V

25 -

50 % V

REFINT

75 -

DS13196 - Rev 6 page 75/199

6.3.7

STM32H7B0xB

Operating conditions

Symbol

V

REFIN_CAL

Table 29. Internal reference voltage calibration values

Parameter

Raw data acquired at temperature of 30 °C,

VDDA

= 3.3 V

Memory address

08FFF810 - 08FFF812

Symbol

V

DD50USB

I

DD50USB

V

REGOUTV33V

I

OUT

T

WKUP

Table 30. USB regulator characteristics

Parameter

Supply voltage

Current consumption

Regulated output voltage

Output current load sinked by USB block

Wakeup time

Conditions

-

-

-

-

-

3

-

-

Min Typ

4 5

13.5

-

-

120

Max Unit

5,5 V

µA

3.6

20

170

V mA

µs

Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in

Figure 13. Current consumption measurement scheme .

All the run-mode current consumption measurements given in this section are performed with a CoreMark code.

Typical and maximum current consumption

The MCU is placed under the following conditions:

•

•

•

All I/O pins are in analog input mode.

All peripherals are disabled except when explicitly mentioned.

•

The Flash memory access time is adjusted with the minimum wait states number, depending on the f

ACLK frequency (refer to the table “Number of wait states according to CPU clock (f rcc_cpu_ck

) frequency and

V

CORE

range” available in the reference manual).

When the peripherals are enabled, the AHB clock frequency is the CPU frequency divided by 2 and the APB clock frequency is AHB clock frequency divided by 2.

The parameters given in the below tables are derived from tests performed under ambient temperature and supply voltage conditions summarized in

Table 20. General operating conditions

.

The maximum current consumptions provided in the following tables are given for LDO regulator ON. To obtain the maximum SMPS current consumption, the efficiency curves can be used with the maximum LDO current consumption as entry value (refer to

Section 6.3.3 SMPS step-down converter

).

DS13196 - Rev 6 page 76/199

STM32H7B0xB

Operating conditions

Table 31. Inrush current and inrush electric charge characteristics for LDO and SMPS

1.

The typical values are given for V

DDLDO

= V

DDSMPS

= 3.3 V and for typical decoupling capacitor values of C

EXT

and C

OUT

.

2.

The product consumption on V

DDCORE

is not taken into account in the inrush current and inrush electric charge.

Symbol Parameter Conditions Min Typ Max Unit

I

RUSH

Q

RUSH

Inrush current on voltage regulator power-on

(POR or wakeup from Standby)

Inrush current on voltage regulator power-on

(POR)

Inrush current on voltage regulator power-on

(wakeup from Standby)

Inrush current on voltage regulator power-on

(POR or wakeup from Standby)

Inrush current on voltage regulator power-on

(POR)

Inrush current on voltage regulator power-on

(wakeup from Standby) on V

DDLDO

(1)

on V

DDSMPS

(3)

SMPS supplies the V

DDCORE

SMPS supplies internal LDO V

OUT

=

1.8 V (5)

SMPS supplies internal LDO V

OUT

=

2.5 V (5)

on V

DDSMPS

(3)

SMPS supplies external circuit V

OUT

= 1.8 V

(5)

SMPS supplies external circuit V

OUT

= 2.5 V

(5)

on V

DDSMPS

(3)

SMPS supplies internal LDO V

OUT

=

1.8 V

SMPS supplies internal LDO V

OUT

=

2.5 V on V

DDLDO

(1)

on V

DDSMPS

(3)

SMPS supplies the V

DDCORE

SMPS supplies internal LDO V

OUT

=

1.8 V (5)

on V

DDSMPS

(3)

SMPS supplies internal LDO V

OUT

=

2.5 V (5)

SMPS supplies external circuit VOUT

= 1.8 V

(5)

SMPS supplies external circuit V

OUT

= 2.5 V

(5)

on V

DDSMPS

(3)

SMPS supplies internal LDO V

OUT

=

1.8 V

SMPS supplies internal LDO V

OUT

=

2.5 V

-

-

-

-

-

-

-

-

55

96 (2)

25

92 (4)

45

25

4.0

2.9

135

(4)

100

(4)

70 (4)

50 (4)

70 200

(4)

95 210

(4)

4.4

5.3

(2)

2.9

7 (2)

7.5

(2)

5.7

(2)

5.2

(2)

4 (2)

8.0

15 (2)

-

14.5 20.5

(2)

mA

μC

1. The inrush current and inrush electric charge on V

DDLDO

are not present in Bypass mode or when the

SMPS supplies V

DDCORE

.

2. The maximum value is given for the maximum decoupling capacitor C

EXT

.

3. The inrush current and inrush electric charge on V

DDSMPS

C

OUT

) is not present, that is if the SMPS is not used.

is not present if the external component (L or

4. The maximum value is given for the maximum decoupling capacitor C

OUT

and the minimum V

DDSMPS voltage.

5. The inrush current and inrush electric charge due to the transition from 1.2 V to the final V

OUT or 2.5 V) is not taken into account.

value (1.8 V

DS13196 - Rev 6 page 77/199

STM32H7B0xB

Operating conditions

Table 32. Typical and maximum current consumption in Run mode, code with data processing running from ITCM, regulator ON

Data are in DTCM for best computation performance. In this case, the cache has no influence on consumption.

Max

(1)(2)

Symbol Parameter Conditions f rcc_cpu_ck

(MHz)

Typ

LDO

Typ

SMPS

T

J

=

25 °C

T

J

=

85 °C

T

J

=

105 °C

T

J

=

130 °C unit

I

DD

Supply current in

Run mode

All peripherals disabled

All peripherals enabled

VOS0

VOS1

VOS2

VOS3

VOS0

VOS1

VOS2

VOS3

87

63

55

146

129

100

41

35

29

23

173

70

67

65

56

52

106

92

80

75

69

45

41

115

105

77

23

21

16

9

142

47

45

43

38

35

77

64

58

52

51.5

45.0

32.5

27.5

17.5

15.0

8.5

7.5

5.5

3.0

63.5

19.0

18.0

17.0

14.5

13.0

34.0

27.5

24.0

21.0

108.0

99.0

71.5

65.0

41.5

38.0

19.0

18.0

12.5

6.0

133.5

42

39

37.5

34.0

30.5

69.5

56.5

52.0

46.5

225

225

160

160

88

88

88

88

60

25

280

180

168

160

160

144

280

225

225

200 mA

168

147

118

102

77

66

55

46

41

34

196

88

85

83

70

67

128

114

98

93

214

185

156

132

108

91

85

71

66

59

242

125

122

120

101

97

173

159

136

130

1. Guaranteed by characterization results, unless otherwise specified.

2. The maximum values are given for LDO regulator ON. Refer to

Section 6.3.3 SMPS step-down converter

for the SMPS maximum current consumption.

DS13196 - Rev 6 page 78/199

STM32H7B0xB

Operating conditions

Table 33. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory, cache ON

Symbol

I

DD

Parameter

Supply current in

Run mode

Conditions

All peripherals disabled

All peripherals enabled

VOS0

VOS1

VOS2

VOS3

VOS0

VOS1

VOS2 f rcc_cpu_ck

(MHz)

25

280

225

225

160

160

88

88

160

144

88

88

60

280

225

225

200

180

168

160

Typ

LDO

(1)

6.0

132.5

107.5

99.0

71.5

65.0

41.5

38.0

34.0

30.5

19.0

17.5

12.5

69.0

56.0

51.5

46.5

42.0

39.0

37.5

Typ

SMPS

2.5

63.5

51.0

44.5

32.5

27.5

17.5

15.0

14.5

13.0

8.5

7.5

5.0

33.5

27.0

23.5

21.5

19.0

18.0

17.0

(1)

VOS3

1. Guaranteed by characterization results, unless otherwise specified.

2. The maximum values are given for LDO regulator ON. Refer to

Section 6.3.3 SMPS step-down converter

for the SMPS maximum current consumption.

9

142

115

105

77

69

45

41

38

35

23

21

16

58

52

47

45

43

T

J

=

25 °C

77

64

23

173

145

129

100

87

63

55

56

53

41

35

29

80

75

70

67

65

T

J

=

85 °C

106

92

Max (1)(2)

34

195

168

147

118

102

77

66

70

67

55

46

41

T

J

=

105 °C

128

114

98

92

88

85

83

59

241

213

185

155

101

97

85

71

66

132

108

91

T

J

=

130 °C

173

158

136

129

125

122

120 unit mA

Table 34. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory, cache OFF

Symbol

I

DD

Parameter

Supply current in

Run mode

Conditions

All peripherals disabled

All peripherals enabled

VOS0

VOS1

VOS2

VOS3

VOS0

VOS1 f rcc_cpu_ck

(MHz)

88

88

280

225

225

280

225

225

160

160

Typ

LDO

(1)

18.5

16.5

119.5

98.5

90.5

56.0

47.0

43.0

34.0

29.5

Typ

SMPS (1)

9.0

7.5

58.0

48.0

42.0

28.0

23.5

21.0

16.5

13.5

T

J

=

25 °C

23

19

127

105

96

63

54

49

39

34.

T

J

=

85 °C

Max

(1)(2)

T

J

=

105 °C

40

33

157

135

120

91

82

71

62

51

54

44

180

157

138

113

103

89

79

65

Unit mA

T

J

=

130 °C

84

69

225

203

176

157

148

126

116

96

DS13196 - Rev 6 page 79/199

STM32H7B0xB

Operating conditions

Symbol

I

DD

Parameter

Supply current in

Run mode

Conditions

All peripherals enabled

VOS1

VOS2 f rcc_cpu_ck

(MHz)

160

160

88

88

Typ

LDO

68.0

60.5

41.0

36.5

(1)

Typ

SMPS

32.0

26.5

18.0

15.0

(1)

VOS3

1. Guaranteed by characterization results, unless otherwise specified.

2. The maximum values are given for LDO regulator ON. Refer to

Section 6.3.3 SMPS step-down converter

for the SMPS maximum current consumption.

T

J

=

25 °C

73

64

45

39

T

J

=

85 °C

96

82

62

53

Max

(1)(2)

T

J

=

105 °C

114

97

77

64

T

J

=

130 °C

152

127

107

89

Unit mA

Table 35. Typical consumption in Run mode and corresponding performance versus code position

Symbol

I

DD

Parameter

Supply current in Run mode

Conditions

Peripheral

All peripherals disabled, cache ON

All peripherals disabled cache

OFF

Code

ITCM

FLASH

AXI

SRAM

AHB

SRAM

SRD

SRAM

ITCM

FLASH

AXI

SRAM

AHB

SRAM

SRD

SRAM f rcc_cpu_c k

(MHz)

Coremark

Typ

LDO

280

280

280

280

280

280

280

280

280

280

1414

1414

1414

1414

1414

1414

668

668

295

295

69.5

69.0

69.5

70.0

70.0

69.5

56.0

62.5

59.5

59.0

Typ

SMPS

33.8

33.4

33.6

33.7

33.7

33.8

28.0

30.2

28.8

28.5

Unit mA

LDO I

DD

/

Coremark

49.2

48.8

49.2

49.5

49.5

49.2

83.8

93.6

201.7

200.0

SMPS I

DD

Coremark

/

23.9

23.6

23.8

23.8

23.8

23.9

41.9

45.2

97.6

96.6

Unit

µA/

Coremark

Table 36. Typical current consumption in Autonomous mode

Symbol

I

DD

Parameter

Supply current in Autonomous mode

Conditions

(1)

Run, DStop mode

Run, DStop2 mode

VOS3

VOS3 f rcc_hclk4

1. System in Run mode, CPU domain is DStop or DStop2 mode with memories of the CPU domain shut-off enable or disable.

(AHB4) (MHz)

64

64

Typ Unit

2.98

2.64

mA

DS13196 - Rev 6 page 80/199

STM32H7B0xB

Operating conditions

Table 37. Typical current consumption in Sleep mode, regulator ON

I

Symbol

DD(Sleep)

Parameter

Supply current in

Sleep mode

Conditions

All peripherals disabled

VOS0

VOS1

VOS2 f rcc_cpu_ck

(MHz)

280

225

225

160

160

88

88

Typ

LDO

18.1

15.0

13.7

10.3

9.3

5.8

5.2

Typ

SMPS

13.0

10.6

9.3

6.8

5.8

3.6

3.0

VOS3

1. Guaranteed by characterization results.

2. The maximum values are given for LDO regulator ON. Refer to

Section 6.3.3 SMPS step-down converter

for the SMPS maximum current consumption.

T

J

=

25 °C

23

20

18

14

12

9

8

T

J

=

85 °C

Max

(1)(2)

T

J

=

105 °C

51

47

40

36

72

68

57

53

30

26

21

44

40

32

T

J

=

130 °C

115

112

93

90

74

70

57

Unit mA

Symbol Parameter

Table 38. Typical current consumption in System Stop mode

Conditions

Typ

LDO

Typ

SMPS

T

J

=

25 °C

T

J

=

85 °C

Max (1)(2)

T

J

=

105 °C

I

DD(Stop)

Stop, DStop

Stop, DStop2

Flash memory in low- power mode, memory shut-off disable

Flash memory in normal mode, memory shut-off disable

Flash memory in low- power mode, memory shut-off enable

Flash memory in normal mode, memory shut-off enable

Flash memory in low- power mode, memory shut-off disable

SVOS3

Main

(3)

SVOS5

SVOS3

Main

(3)

0.540

SVOS3 LP 0.495

SVOS4 0.370

0.245

0.560

SVOS3 LP 0.515

SVOS4

SVOS5

SVOS3

Main

(3)

0.390

0.245

0.530

SVOS3 LP 0.480

SVOS4 0.360

0.230

SVOS5

SVOS3

Main

(3)

0.550

SVOS3 LP 0.500

SVOS4 0.380

0.230

SVOS5

SVOS3

Main

(3)

0.161

SVOS3 LP 0.115

SVOS4 0.095

SVOS5 0.090

0.487

0.193

0.137

0.090

0.504

0.209

0.153

0.090

0.481

0.186

0.134

0.085

0.498

0.204

0.151

0.085

0.343

0.046

0.037

0.032

2.33

2.27

1.59

0.98

2.39

2.33

1.65

1.04

2.31

2.25

1.57

0.96

2.37

2.31

1.63

1.02

0.32

0.28

0.20

0.14

14.36

14.21

10.58

7.18

14.62

14.47

10.84

7.43

14.23

14.09

10.49

6.95

14.50

14.35

10.75

7.21

1.67

1.62

1.23

0.93

24.52

24.28

18.52

13.10

24.93

24.69

18.93

13.51

24.27

24.04

18.32

12.59

24.68

24.45

18.73

13.00

2.86

2.80

2.19

1.75

T

J

=

130 °C

Unit

46.29

45.94

35.90

26.61

47.01

46.65

36.62

27.32

45.71

45.36

35.41

25.26

46.43

46.07

36.13

25.97

5.58

5.50

4.43

3.80

mA

DS13196 - Rev 6 page 81/199

STM32H7B0xB

Operating conditions

Symbol Parameter Conditions

Typ

LDO

Typ

SMPS

T

J

=

25 °C

T

J

=

85 °C

Max (1)(2)

T

J

=

105 °C

I

DD(Stop)

Stop, DStop2

Flash memory in low -power mode, memory shut-off enable

SVOS3

Main

(3)

0.146

SVOS3 LP 0.100

SVOS4 0.085

SVOS5 0.075

0.337

0.040

0.033

0.028

0.30

0.26

0.19

0.12

1. Guaranteed by characterization results.

2. The maximum values are given for LDO regulator ON. Refer to

Section 6.3.3 SMPS step-down converter

for the SMPS maximum current consumption.

3. When the SMPS is ON, an additional consumption is observed. It is recommended to use LP SVOS3 to optimize power consumption.

1.55

1.51

1.15

0.80

2.63

2.58

2.01

1.46

T

J

=

130 °C

Unit

5.04

4.96

3.98

3.02

mA

Symbol Parameter

Table 39. Typical current consumption RAM shutoff in Stop mode

Conditions

Typ LDO

SVOS3 LP SVOS4 SVOS5

Unit

∆

IDD

(Stop) Stop, Dstop or Dstop2

AXISRAM1 shutoff power consumption (power consumption reduction when AXISRAM1 shutoff is enabled)

AXISRAM2 shutoff power consumption (power consumption reduction when AXISRAM2 shutoff is enabled)

AXISRAM13 shutoff power consumption (power consumption reduction when AXISRAM3 shutoff is enabled)

AHBSRAM1 shutoff power consumption (power consumption reduction when AHBSRAM1 shutoff is enabled)

AHBSRAM2 shutoff power consumption (power consumption reduction when AHBSRAM2 shutoff is enabled)

ITCM and ETM shutoff power consumption (power consumption reduction when ITCM and ETM shutoff is enabled)

GFXMMU and JPEG shutoff power consumption (power consumption reduction when GFXMMU and JPEG shutoff is enabled)

High-speed interface USB and FDCAN shutoff power consumption

(power consumption reduction when High-speed interface USB and

FDCAN shutoff is enabled)

SRDSRAM shutoff power consumption (power consumption reduction when SRDSRAM shutoff is enabled)

3.00

4.40

4.40

0.90

0.90

1.00

0.20

0.20

0.30

1.80

2.70

2.70

0.50

0.50

0.60

0.10

0.10

0.30

3.00

4.40

4.40

0.70

0.70

0.90

0.10

0.10

0.40

µA

Table 40. Typical and maximum current consumption in Standby mode

Symbol

I

DD

(Standby)

Parameter

Supply current in

Standby mode,

IWDG OFF

Conditions

Backup

SRAM

OFF

ON

OFF

ON

RTC &

LSE (2)

OFF

OFF

ON

ON

1. Guaranteed by characterization results.

2. The LSE clock is in low-drive mode.

Typ

1.62

V

2.4

V (3)

3 V

(3)

3.3

V (3)

T

J

=

25 °C

1.97

2.76

3.02

3.30

4.0

2.78

3.69

4.02

4.40

5.4

2.46

3.37

3.73

4.07

5.0

3.27

4.30

4.73

5.17

6.4

T

Max (3.6V) (1)

J

=

85 °C

T

J

=

105 °C

T

J

=

130 °C

Unit

11.0

13.0

12.2

14.2

22.0

25.0

23.3

26.3

57.0

64.0

59.0

66.0

µA

DS13196 - Rev 6 page 82/199

STM32H7B0xB

Operating conditions

3. These values are given for PDR ON. When the PDR is OFF (internal reset OFF), the typical current consumption is reduced

(refer to Section 6.3.5 Embedded reset and power control block characteristics ).

Table 41. Typical and maximum current consumption in V

BAT

mode

Typ

I

Symbol

DD

(VBAT)

Parameter

Supply current in

V

BAT

mode

Conditions

Backup

SRAM

OFF

ON

OFF

ON

RTC &

LSE (2)

OFF

OFF

ON

ON

1. Guaranteed by characterization results.

2. The LSE clock is in low-drive mode.

1.2 V 2 V 3 V 3.3 V

0.01 0.02 0.03 0.07

0.85 0.93 1.05 1.14

0.50 0.63 0.74 0.84

1.34 1.54 1.76 1.91

T

J

=

25 °C

0.2

1.5

1.2

2.5

Max (3.6V) (1)

T

J

=

85 °C

T

J

=

105 °C

1.9

3.6

3.1

4.8

4.6

7.5

5.9

8.8

Caution:

T

J

=

130 °C

14

20.0

16

22.0

Unit

µA

I/O system current consumption

I/O static current consumption

All the I/Os used as inputs with pull-up generate a current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in

Table 63. I/O static characteristics .

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

An additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid a current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption (see Table 42. Peripheral current consumption in Run mode ), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches,

it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin:

I

SW

=V

DDx

× f sw

× C

L where

I

SW

is the current sunk by a switching I/O to charge/discharge the capacitive load

V

DDx

is the MCU supply voltage f

SW

is the I/O switching frequency

C

L

is the total capacitance seen by the I/O pin: C = C

INT

+ C

EXT

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

On-chip peripheral current consumption

The MCU is placed under the following conditions:

•

•

At startup, all I/O pins are in analog input configuration.

All peripherals are disabled unless otherwise mentioned.

•

•

The I/O compensation cell is enabled.

f rcc_cpu_ck

is the CPU clock. f

PCLK

= f rcc_cpu_ck

/4, and f

HCLK

= f rcc_cpu_ck

/2.

The given value is calculated by measuring the difference of current consumption

DS13196 - Rev 6 page 83/199

DS13196 - Rev 6

STM32H7B0xB

Operating conditions

•

•

•

• with all peripherals clocked off with only one peripheral clocked on f rcc_cpu_ck

= 280 MHz (Scale 0), f

= 88 MHz (Scale 3) rcc_cpu_ck

= 225 MHz (Scale 1), f rcc_cpu_ck

= 160 MHz (Scale 2), f rcc_cpu_ck

The ambient operating temperature is 25 °C and V

DD

=3.3 V.

AHB3

AHB1

AHB2

Table 42. Peripheral current consumption in Run mode

Peripheral

0.90

0.80

0.60

4.90

1.00

5.00

5.10

1.10

0.80

1.10

5.00

0.10

22.00

9.30

0.10

0.10

1.40

1.60

9.30

0.60

2.20

8.30

2.00

0.70

1.80

0.30

1.20

1.30

2.70

VOS1

6.40

I

DD

(Typ)

VOS2

5.90

2.80

4.40

19.00

1.30

2.50

4.00

17.00

1.20

8.40

0.50

2.00

7.60

1.80

0.70

1.60

0.30

1.10

1.20

2.40

0.80

0.80

0.50

4.50

0.90

4.60

4.60

1.00

0.70

1.00

4.60

0.10

20.00

9.10

0.10

0.10

1.30

1.50

0.90

0.90

0.60

5.40

1.10

5.30

5.40

1.10

0.70

1.10

5.30

0.10

24.00

9.50

0.10

0.10

1.50

1.80

10.00

0.50

2.30

8.90

2.20

VOS0

7.10

3.00

4.70

20.00

1.30

0.70

2.00

0.30

1.20

1.40

2.80

AXISRAM2

AXISRAM3

DTCM1

DTCM2

ITCM

AXISRAM1

Bridge

DMA1

DMA2

CRC

ADC12 registers

ADC12 kernel

USB1OTG registers

USB1OTG kernel

USB1ULPI

Bridge

CRYPT

HASH

MDMA

DMA2D

JPGDEC

FLITF

FMC registers

FMC kernel

OSPI1 registers

OSPI1 kernel

SDMMC1 registers

SDMMC1 kernel

OSPI2 registers

OSPI2 kernel

IOMNGR

OTFDEC1

OTFDEC2

GFXMMU

0.70

0.70

0.50

4.10

0.80

4.20

4.30

1.00

0.70

1.00

4.20

0.10

18.00

8.80

0.10

0.10

1.20

1.30

7.70

0.50

1.80

6.90

1.60

VOS3

5.40

2.30

3.60

15.00

1.10

0.60

1.50

0.30

1.10

1.20

2.30

Unit

µA/MHz page 84/199

DS13196 - Rev 6

AHB2

AHB4

APB3

APB1

Peripheral

GPIOK

BDMA2

SRDSRAM

BKPRAM

IWDG

Bridge

LTDC

WWDG1

Bridge

TIM2

TIM3

TIM4

TIM5

TIM6

TIM7

TIM12

TIM13

TIM14

LPTIM1 registers

LPTIM1 kernel

DCMI

HSEM

RNG registers

RNG kernel

SDMMC2 registers

SDMMC2 kernel

BDMA1

AHBSRAM1

AHBSRAM2

Bridge

GPIOA

GPIOB

GPIOC

GPIOD

GPIOE

GPIOF

GPIOG

GPIOH

GPIOI

GPIOJ

STM32H7B0xB

Operating conditions

1.70

1.80

1.80

1.80

1.80

1.80

1.80

1.80

1.80

1.60

0.70

0.60

8.40

1.80

VOS1

4.60

I

DD

(Typ)

VOS2

4.20

0.10

1.40

9.70

6.30

2.10

0.10

1.20

9.50

5.70

1.90

1.50

1.70

1.70

1.60

1.60

1.70

1.60

1.60

1.60

1.50

0.60

0.60

7.70

1.70

6.70

1.50

1.40

3.30

2.60

2.30

0.80

2.00

1.00

0.10

6.90

5.90

5.40

1.80

3.90

0.50

0.70

0.07

0.10

11.00

6.10

1.30

1.30

3.00

2.40

2.10

0.70

1.80

0.90

0.10

6.30

5.40

4.90

1.70

3.50

0.50

0.70

0.07

0.10

9.80

7.20

1.60

1.60

3.60

2.80

2.50

0.80

2.20

1.10

0.10

7.50

6.30

5.80

2.00

4.20

0.60

0.80

0.07

0.10

12.00

1.70

0.70

0.70

9.10

2.00

VOS0

5.00

0.10

1.50

10.00

6.80

2.30

1.80

2.00

2.00

1.90

1.90

2.00

1.90

1.90

1.90

5.60

1.20

1.20

2.80

2.10

1.90

0.60

1.70

0.90

0.10

6.20

4.90

4.50

1.50

3.20

0.50

0.60

0.07

0.10

8.90

1.30

0.60

0.50

7.00

1.50

VOS3

3.90

0.10

1.10

9.20

5.20

1.70

1.40

1.50

1.50

1.50

1.50

1.50

1.50

1.50

1.50

Unit

µA/MHz page 85/199

DS13196 - Rev 6

APB1

APB2

Peripheral

HDMICEC registers

HDMICEC kernel

DAC1

UART7 registers

UART7 kernel

UART8 registers

UART8 kernel

Bridge

CRS

SWP registers

SWP kernel

OPAMP

MDIO

FDCAN registers

FDCAN kernel

Bridge

TIM1

TIM8

USART1 registers

USART1 kernel

SPI2 registers

SPI2 kernel

SPI3 registers

SPI3 kernel

SPDIFRX1 registers

SPDIFRX1 kernel

USART2 registers

USART2 kernel

USART3 registers

USART3 kernel

UART4 registers

UART4 kernel

UART5 registers

UART5 kernel

I2C1 registers

I2C1 kernel

I2C2 registers

I2C2 kernel

I2C3 registers

I2C3 kernel

STM32H7B0xB

Operating conditions

3.40

1.70

3.50

0.80

2.00

0.80

1.90

0.80

2.00

1.80

4.30

1.80

4.20

1.60

VOS1

2.00

I

DD

(Typ)

VOS2

1.80

0.80

2.40

0.80

0.50

2.70

0.80

2.30

0.70

0.50

2.50

3.10

1.50

3.20

0.80

1.80

0.70

1.80

0.70

1.80

1.70

3.90

1.70

3.80

1.50

2.90

16.00

4.80

0.10

9.10

8.80

0.10

0.10

0.30

0.40

2.10

0.10

3.80

0.50

0.10

1.30

1.70

3.50

2.00

3.50

2.60

15.00

3.50

0.10

8.30

8.00

0.10

0.10

0.20

0.40

2.00

0.10

3.50

0.40

0.10

1.20

1.50

3.20

1.80

3.20

3.10

17.00

5.60

0.10

9.80

9.50

0.10

0.10

0.30

0.50

2.30

0.10

4.20

0.50

0.10

1.40

1.80

3.80

2.10

3.80

2.00

4.60

2.00

4.50

1.70

VOS0

2.20

0.90

2.70

0.90

0.60

2.90

3.70

1.80

3.80

0.90

2.10

0.90

2.10

0.90

2.20

2.40

14.00

1.10

0.10

7.60

7.30

0.10

0.10

0.10

0.40

1.80

0.10

3.20

0.40

0.10

1.10

1.40

2.90

1.70

2.90

1.50

3.60

1.50

3.40

1.30

VOS3

1.70

0.70

2.00

0.70

0.40

2.20

2.80

1.40

2.90

0.70

1.70

0.70

1.60

0.70

1.70

Unit

µA/MHz page 86/199

DS13196 - Rev 6

APB2

APB4

Peripheral

DFSDM1 kernel

Bridge

SYSCFG

LPUART1 registers

LPUART1 kernel

SPI6 registers

SPI6 kernel

I2C4 registers

I2C4 kernel

LPTIM2 registers

LPTIM2 kernel

LPTIM3 registers

LPTIM3 kernel

DAC2

COMP12

VREF

RTCAPB

TMPSENS

DFSDM2 registers

DFSDM2 kernel

USART6 registers

USART6 kernel

USART10 registers

USART10 kernel

UART9 registers

UART9 kernel

SPI1 registers

SPI1 kernel

SPI4 registers

SPI4 kernel

TIM15

TIM16

TIM17

SPI5 registers

SPI5 kernel

SAI1 registers

SAI1 kernel

SAI2 registers

SAI2 kernel

DFSDM1 registers

STM32H7B0xB

Operating conditions

3.90

4.00

1.90

0.50

1.60

1.30

2.10

1.10

9.60

1.90

0.80

1.90

0.50

4.90

VOS1

4.00

I

DD

(Typ)

VOS2

4.50

0.10

4.10

0.10

3.60

0.10

0.10

4.60

0.10

4.00

0.10

3.50

3.60

1.70

0.40

1.50

1.20

1.90

1.00

8.80

1.80

0.70

1.70

0.40

4.40

1.40

0.70

0.30

0.30

1.70

2.10

1.50

0.10

0.70

1.70

0.60

1.70

0.50

0.10

0.40

0.30

1.00

2.10

1.50

0.50

1.30

0.60

0.30

0.20

1.60

2.00

1.40

0.10

0.60

1.60

0.50

1.60

0.50

0.10

0.40

0.30

0.90

1.90

1.40

0.50

1.50

0.80

0.40

0.30

1.90

2.30

1.70

0.10

0.80

1.90

0.60

1.90

0.60

0.10

0.50

0.40

1.10

2.30

1.70

0.60

2.10

0.90

2.10

0.50

5.30

VOS0

3.80

0.10

4.00

0.10

3.50

0.10

4.20

4.30

2.00

0.50

1.80

1.40

2.30

1.20

10.00

1.20

0.50

0.30

0.20

1.40

1.80

1.30

0.10

0.60

1.40

0.50

1.40

0.40

0.10

0.30

0.30

0.80

1.70

1.30

0.40

1.60

0.70

1.50

0.40

4.00

VOS3

6.30

0.10

6.40

0.10

5.50

0.10

3.20

3.30

1.50

0.40

1.30

1.00

1.70

0.90

8.00

Unit

µA/MHz page 87/199

STM32H7B0xB

Operating conditions

APB4

Peripheral

Bridge

VOS0

0.10

VOS1

0.10

I

DD

(Typ)

VOS2

0.10

VOS3

0.10

Unit

µA/MHz

6.3.8

Symbol

I

DD

Table 43. Peripheral current consumption in Stop, Standby and V

BAT

mode

Parameter

RTC+LSE low drive

RTC+LSE medium- low drive

RTC+LSE medium- high drive

RTC+LSE High drive

Backup SRAM

Conditions

-

-

-

-

-

Typ Max (3.6 V)

3.3 V T

J

= 25 °C T

J

= 85 °C T

J

= 105 °C T

J

= 130 °C

0.77

0.87

1.0

1.1

1.2

1.3

1.3

1.4

2.0

2.1

1.03

1.38

1.10

1.3

1.6

1.4

1.5

1.8

2.0

1.6

1.9

3.2

2.3

2.6

7.0

Unit

µA

Wakeup time from low-power modes

The wakeup times given in Table 44. Low-power mode wakeup timings

are measured starting from the wakeup event trigger up to the first instruction executed by the CPU:

•

•

For Stop or Sleep modes: the wakeup event is WFE.

WKUP (PC1) pin is used to wakeup from Standby, Stop and Sleep modes.

All timings are derived from tests performed under ambient temperature and V

DD

=3.3 V.

Symbol t

WUSLEEP

(3)

t

WUDSTOP

(3)

t

WUDSTOP2

(3)

Parameter

Wakeup from Sleep

Table 44. Low-power mode wakeup timings

Conditions

Wakeup from DStop

Wakeup from DStop2, clock kept running

Typ

(1)

Max

(1)(2)

5.00

SVOS3 Main, HSI, Flash memory in normal mode 4.2

SVOS3 Main, HSI, Flash memory in low-power mode 8.3

SVOS3 LP, HSI, Flash memory in normal mode 5.0

SVOS3 LP, HSI, Flash memory in low-power mode

SVOS4, HSI, Flash memory in normal mode

9.0

15.7

SVOS4, HSI, Flash memory in low-power mode

SVOS5, HSI, Flash memory in normal mode

SVOS5, HSI, Flash memory in low-power mode

19.7

35.0

35.0

SVOS3 Main, CSI, Flash memory in normal mode 42.5

SVOS3 Main, CSI, Flash memory in low power mode 48.0

SVOS3 LP, CSI, Flash memory in normal mode 43.3

SVOS3 LP, CSI, Flash memory in low power mode 48.8

SVOS4, CSI, Flash memory in normal mode 54.0

SVOS4, CSI, Flash memory in low-power mode

SVOS5, CSI, Flash memory in normal mode

59.5

74.8

SVOS5, CSI, Flash memory in low-power mode

SVOS3 LP, HSI, Flash memory in low-power mode

SVOS4, HSI, Flash memory in low-power mode

SVOS5, HSI, Flash memory in low-power mode

74.8

9.7

20.4

35.7

5.00

53

59

65

72

90

90

13

26

44

25

43

43

52

58

6

11

7

12

19

Unit

CPU clock cycles

µs

DS13196 - Rev 6 page 88/199

STM32H7B0xB

Operating conditions t

Symbol

WUDSTOP2

(3)

Parameter

Wakeup from DStop2, clock kept running

Conditions

SVOS3 LP, CSI, Flash memory in low-power mode

SVOS4, CSI, Flash memory in low-power mode

SVOS5, CSI, Flash memory in low-power mode

Typ

(1)

51.3

62.0

77.3

t

WUSTDBY

(3)

Wakeup from Standby mode -

1. Guaranteed by characterization results.

2. Measures done at −40 °C in the worst conditions.

3. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction.

257

Max

(1)(2)

62

75

93

330

6.3.9

Unit

µs

External clock source characteristics

High-speed external user clock generated from an external source

In bypass mode, the HSE oscillator is switched off and the input pin is a standard I/O.

The external clock signal has to respect

Table 45. High-speed external user clock characteristics in addition to

Table 63. I/O static characteristics . The external clock can be low-swing (analog) or digital. In case of a low-swing

analog input clock, the clock squarer must be activated (refer to RM0455).

Table 45. High-speed external user clock characteristics t f

Symbol

HSE_ext

V

V

W(HSEH)

HSEH

HSEL

/t

W(HSEL)

(2)

Parameter

User external clock source frequency

Digital OSC_IN input highlevel voltage

Digital OSC_IN input low-level voltage

Digital OSC_IN input high or low time

Conditions

External digital/analog clock

External digital clock

External digital clock

Min

V

4

0.7 V

7

(1)

SS

DD

Typ

25

-

-

-

(1)

Max

V

50

(1)

DD

0.3 V

-

DD

Unit

MHz

V ns t

V lswHSE

(V

HSEH

−V

HSEL

DuCy r(HSE)

/t

HSE f(HSE)

)

(3)

Analog low-swing OSC_IN peak-to-peak amplitude

0.2

External analog lowswing clock

Analog low-swing OSC_IN duty cycle

45

Analog low-swing OSC_IN rise and fall times

External analog lowswing clock, 10% to 90%

0.05 / f

HSE_ext

50

-

2/3 V

0.3 / f

55

DD

HSE_ext

V

% ns

1. Guaranteed by design.

2. The rise and fall times for a digital input signal are not specified. However the V

HSEH

and V

HSEL

conditions must be fulfilled.

3. The DC component of the signal must ensure that the signal peaks are located between V

DD

and V

SS

.

DS13196 - Rev 6 page 89/199

Figure 21. High-speed external clock source AC timing diagram

STM32H7B0xB

Operating conditions

VHSEH

VHSEL

90 %

10 % tr(HSE)

External clock source

THSE tf(HSE) fHSE_ext

OS C _IN tW(HSE)

IL

STM32 tW(HSE) t

Low-speed external user clock generated from an external source

In bypass mode, the LSE oscillator is switched off and the input pin is a standard I/O. The external clock

signal has to respect Table 46. Low-speed external user clock characteristics

in addition to Table 63. I/O static characteristics

. The external clock can be low-swing (analog) or digital. In case of a low-swing analog input clock, the clock squarer must be activated (refer to RM0455).

Table 46. Low-speed external user clock characteristics

Symbol f

LSE_ext

V

LSEH

V

LSEL t w(LSEH)

/ t w(LSEL)

V

V lsw_H lsw_L

V lswLSE

(V

LSEH

−V

LSEL

)

DuCy

LSE

Parameter

User external clock source frequency

Digital OSC32_IN input high-level voltage

OSC32_IN input low-level voltage

OSC32_IN high or low time

Analog low-swing OSC_IN high-level voltage

Analog low-swing OSC_IN low-level voltage

Analog low-swing OSC_IN peak-to-peak amplitude

Analog low-swing OSC_IN duty cycle

Conditions

External digital/analog clock

External digital clock

External digital clock

External analog low-swing clock t r(LSE)

/t f(LSE)

Analog low-swing OSC_IN rise and fall times

External analog low-swing clock,

10% to 90%

1. Guaranteed by design.

Min

(1) Typ (1) Max (1)

Unit

-

0.7 V

DD

V

SS

250

32.768

1000 kHz

-

-

V

DD

0.3 V

-

DD

V ns

0.6

1.225

0.35

0.8

V

0.2

0.875

45

-

50

100

55

200

% ns

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com.

DS13196 - Rev 6 page 90/199

Figure 22. Low-speed external clock source AC timing diagram

STM32H7B0xB

Operating conditions

VLSEH

VLSEL

90 %

10 % tr(LSE)

External clock source

T LSE tf(LSE) fLSE_ext

OSC32 _IN tW(LSE) tW(LSE) t

IL

STM32

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 50 MHz crystal/ceramic resonator oscillator.

All the information given in this paragraph are based on characterization results obtained with typical external

components specified in Table 47. 4-50 MHz HSE oscillator characteristics

. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Table 47. 4-50 MHz HSE oscillator characteristics

Symbol

F

R

F

Parameter

Oscillator frequency

Feedback resistor

Operating conditions

(1)

-

-

I

DD(HSE)

HSE current consumption

During startup

(3)

V

DD

=3 V, Rm=30 Ω

C

L

=10 pF at 4 MHz

V

DD

=3 V, Rm=30 Ω

C

L

=10 pF at 8 MHz

V

DD

=3 V, Rm=30 Ω

C

L

=10 pF at 16 MHz

V

DD

=3 V, Rm=30 Ω

C

L

=10 pF at 32 MHz

V

DD

=3 V, Rm=30 Ω

C

L

=10 pF at 48 MHz

Startup Gm critmax t

SU

(4)

Maximum critical crystal gm

Start-up time V

DD

is stabilized

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Guaranteed by design.

3. This consumption level occurs during the first 2/3 of the t

SU(HSE)

startup time.

Min

(2)

4

-

-

-

-

-

-

-

-

-

Typ (2)

-

200

-

0.35

Max

(2)

50

-

4

-

0.40

0.45

0.65

0.95

-

2

-

-

-

-

1.5

-

Unit

MHz kΩ mA mA/V ms

DS13196 - Rev 6 page 91/199

STM32H7B0xB

Operating conditions

4. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Note:

For C

L1

and C

L2

, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range

(typical), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see

Figure 23. Typical application with an 8 MHz crystal

). C

L1

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

L1

and C

L2

. The

PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing C

L1

and C

L2

.

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com.

Resonator with integrated capacitors

C L1

Figure 23. Typical application with an 8 MHz crystal

C L2

8 MHz resonator

R EXT (1)

OSC_ IN

OSC_ OU T

R F

Bias controlled gain fHS E

STM32

Symbol

F

I

DD

Gm critmax

1.

R

EXT

value depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator.

All the information given in this paragraph are based on characterization results obtained with typical external

components specified in Table 48. Low-speed external user clock characteristics

. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Table 48. Low-speed external user clock characteristics

Parameter

Oscillator frequency

LSE current consumption

Maximum critical crystal gm

Operating conditions

(1)

-

LSEDRV[1:0] = 00,

Low drive capability

LSEDRV[1:0] = 01,

Medium Low drive capability

LSEDRV[1:0] = 10,

Medium high drive capability

LSEDRV[1:0] = 11,

High drive capability

LSEDRV[1:0] = 00,

Low drive capability

LSEDRV[1:0] = 01,

Min

(2)

-

-

-

-

-

-

-

Typ

(2)

32.768

290

390

550

900

-

-

Max

(2)

-

-

Unit kHz

-

-

-

0.5

0.75

nA

µA/V

DS13196 - Rev 6 page 92/199

STM32H7B0xB

Operating conditions

Symbol

Gm critmax

Parameter

Maximum critical crystal gm

Operating conditions

(1)

Medium Low drive capability

LSEDRV[1:0] = 10,

Medium high drive capability

LSEDRV[1:0] = 11,

High drive capability

Min

-

-

(2)

t

SU

(3)

Startup time VDD is stabilized -

1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers.

2. Guaranteed by design.

3. t

SU

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768k Hz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Note:

Typ

(2)

-

-

2

Max

(2)

1.7

2.7

-

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com.

Unit

µA/V s

Figure 24. Typical application with a 32.768 kHz crystal

Resonator with integrated capacitors C

L1 f

HSE

32.768 kHz resonator

OSC32_IN

OSC32_OUT

R

F

Bias controlled gain

STM32

C

L2

6.3.10

1.

An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.

Internal clock source characteristics

The parameters given in Table 49. HSI48 oscillator characteristics

to Table 52. LSI oscillator characteristics

are derived from tests performed under ambient temperature and V

DD

supply voltage conditions summarized in

Table 20. General operating conditions .

48 MHz high-speed internal RC oscillator (HSI48)

Symbol f

HSI48

TRIM

(2)

USER TRIM COVERAGE

(3)

DuCy(HSI48)

(2)

ACCHSI48_REL

(3)

ΔV

DD

(HSI48)

(2)

Table 49. HSI48 oscillator characteristics

Parameter

HSI48 frequency

User trimming step

User trimming coverage

Duty cycle

Accuracy of the HSI48 oscillator over temperature

(reference is 30 °C)

Conditions Min Typ Max Unit

V

DD

= 3.3 V, T

J

= 30 °C 47.5

(1)

48

48.5

(1)

MHz

0.175 0.250

%

± 32 steps

-

±4,70

45

±5.6

-

-

55

%

%

T

J

= −40 to 130 °C −4.5

4 %

HSI48 oscillator frequency drift with V

DD

(reference is

3.3 V)

V

DD

= 3 to 3.6 V

V

DD

= 1.62 to 3.6 V -

0.025

0.05

0.05

0.1

%

DS13196 - Rev 6 page 93/199

STM32H7B0xB

Operating conditions

Symbol t su

(HSI48)

(2)

I

DD

(HSI48) (2)

N

T

jitter (2)

P

T

jitter (2)

Parameter

HSI48 oscillator startup time

HSI48 oscillator power consumption

Next transition jitter accumulated jitter on 28 cycles

Paired transition jitter Accumulated jitter on 56 cycles

(6)

Conditions

-

-

-

-

1. Calibrated during manufacturing tests.

2. Guaranteed by design.

3. Guaranteed by characterization results.

4. Δf

HSI

= ACCHSI48_REL + ΔV

DD

5. These values are obtained by using the formula: (Freq(3.6 V) − Freq(3.0 V)) / Freq(3.0 V) or (Freq(3.6 V) −

Freq(1.62 V)) / Freq(1.62 V).

6. Jitter measurements are performed without clock sources activated in parallel.

64 MHz high-speed internal RC oscillator (HSI)

-

-

Min Typ Max Unit

2.1

4.0

µs

350 400 µA

± 0.15

± 0.25

-

ns ns

Symbol f

HSI

TRIM

HSI frequency

Parameter

HSI user trimming step

Table 50. HSI oscillator characteristics

Conditions

V

DD

=3.3 V, T

J

=30 °C

Trimming is not a multiple of 32 (3)

Trimming is 128, 256 and 384 (3)

Trimming is 64, 192, 320 and 448 (3)

Other trimming are a multiple of 32 (not including multiple of 64 and 128)

(3)

DuCy(HSI) Duty Cycle

Δ

VDD (HSI)

HSI oscillator frequency drift over V

DD

(reference is 3.3 V)

V

DD

=1.62 to 3.6 V

Δ

TEMP (HSI)

HSI oscillator frequency drift over temperature

(reference is 64 MHz) t su

(HSI) HSI oscillator start-up time t stab

(HSI) HSI oscillator stabilization time

T

J

=-20 to 105 °C

T

J

=−40 to T

J max °C

at 1 % of target frequency at 5 % of target frequency

I

DD

(HSI) HSI oscillator power consumption

1. Guaranteed by design, unless otherwise specified.

2. Calibrated during manufacturing tests.

3. Trimming value of HSICAL[8:0] (refer to RM0455).

4. Guaranteed by characterization results.

4 MHz low-power internal RC oscillator (CSI)

Min

(1) Typ (1) Max (1)

Unit

63.7

(2)

-

64

64.3

0.24

(2)

0.32

MHz

−5.2

−1.8

−1.4

−0.8

-

-

%

−0.6

−0.25

45 -

−0.12

-

-

55 %

0.03

%

−1 (4)

−2 (4)

-

-

-

-

-

-

1

(4)

1

(4)

2

%

1.4

µs

4

-

8

4

µs

300 400 µA

Symbol f

CSI

TRIM

Parameter

CSI frequency

Table 51. CSI oscillator characteristics

CSI user trimming step

Conditions

V

DD

= 3.3 V, T

J

= 30 °C

Trimming is not a multiple of 16

Trimming is a multiple of 32

Min

(1) Typ (1) Max (1)

Unit

3.96

(2)

4

4.04

(2)

0.40

0.75

−4,75 −2,75 0.75

MHz

-

-

DS13196 - Rev 6 page 94/199

STM32H7B0xB

Operating conditions

Symbol

TRIM

DuCy(CSI)

Parameter

CSI user trimming step

Duty Cycle

∆

TEMP

(CSI) CSI oscillator frequency drift over temperature

∆V

DD

(CSI) t su

(CSI)

CSI oscillator frequency drift over V

CSI oscillator startup time

DD t stab

(CSI)

CSI oscillator stabilization time (to reach ± 3 % of f

CSI

)

CSI oscillator power consumption I

DD

(CSI)

1. Guaranteed by design, unless otherwise specified.

2. Calibrated during manufacturing tests.

3. Guaranteed by characterization results.

Low-speed internal (LSI) RC oscillator

Conditions

Other trimming are a multiple of 16 (not including multiple of 32)

-

T

J

= 0 to 85 °C

T

J

= −40 to 130 °C

V

DD

= 1.62 to 3.6 V

-

-

-

Min

(1) Typ (1) Max (1)

Unit

−0,43

45

−3.7

(3)

−11 (3)

−0.06

-

0.00

-

-

-

-

1

0.75

55

4,5 (3)

7,5 (3)

0.06

2

%

%

%

%

µs

-

-

23

4

30 cycle

µA

6.3.11

Table 52. LSI oscillator characteristics

Symbol f

LSI

Parameter

LSI frequency t su

(LSI)

(3)

t stab

(LSI) (3)

LSI oscillator startup time

LSI oscillator stabilization time (5% of final value)

I

DD

(LSI)

(3)

LSI oscillator power consumption

1. Calibrated during manufacturing tests.

2. Guaranteed by characterization results.

3. Guaranteed by design.

Conditions Min Typ Max Unit

V

DD

= 3.3 V, T

J

= 25 °C

31,4 (1) 32 32,6 (1)

T

J

= –40 to 110 °C, V

DD

= 1.62 to 3.6 V 29,76

(2)

-

33,6 (2)

T

J

= –40 to 130 °C, V

DD

= 1.62 to 3.6 V 29,4 (2)

-

33,6 (2)

kHz

80 130

µs

120 170

130 280 nA

PLL characteristics

The parameters given in Table 53. PLL characteristics (wide VCO frequency range) are derived from tests

performed under temperature and V

DD

supply voltage conditions summarized in

Table 20. General operating conditions .

Table 53. PLL characteristics (wide VCO frequency range) f

PLL_P_OUT

PLL multiplier output clock P, Q, R f

Symbol f

PLL_IN

VCO_OUT

Parameter

PLL input clock

PLL input clock duty cycle

PLL VCO output

-

-

VOS0

VOS1

VOS2

-

VOS3

Conditions

Min (1) Typ (1)

Max

(1)

Unit

2

10

1

1

1

1

128 -

-

-

-

-

-

-

16

90

280

(2)

225

(2)

160

(2)

88

(2)

560

(3)

MHz

%

MHz

DS13196 - Rev 6 page 95/199

STM32H7B0xB

Operating conditions

Symbol Parameter Conditions

I t

LOCK

Jitter

DD(PLL)

PLL lock time

Cycle-to-cycle jitter

Long term jitter

PLL power consumption

Normal mode

Sigma-delta mode (f

PLL_IN

≥ 8 MHz) f

VCO_OUT

= 128 MHz f

VCO_OUT

= 200 MHz f

VCO_OUT

= 400 MHz f

VCO_OUT

= 560 MHz

Normal mode (f

PLL_IN

= 2 MHz), f

VCO_OUT

= 560 MHz

Normal mode (f

PLL_IN

= 16 MHz), f

VCO_OUT

= 560 MHz f f

Sigma-delta mode (f

PLL_IN

= 2 MHz), f

VCO_OUT

= 560 MHz

Sigma-delta mode (f

PLL_IN

= 16 MHz), f

VCO_OUT

= 560 MHz

VCO_OUT

VCO_OUT

= 560 MHz

= 128 MHz

V

DD

V

CORE

V

DD

V

CORE

1. Guaranteed by design, unless otherwise specified.

2. This value must be limited to the maximum frequency due to the product limitation.

3. Guaranteed by characterization results.

-

-

-

-

-

-

-

-

-

Min (1) Typ (1)

Max

(1)

Unit

45 100

(3)

µs

60 120

(3)

60 -

-

-

50

20

15

±0.2

±0.8

-

-

-

-

-

±ps

%

±0.2

±0.8

330

-

-

420

630

155

170

-

230

-

µA

Symbol f

PLL_IN f

PLL_OUT t

LOCK

Jitter

I

DD(PLL)

Parameter

PLL input clock

PLL input clock duty cycle

PLL multiplier output clock P, Q, R f

VCO_OUT

PLL VCO output

PLL lock time

Cycle-to-cycle jitter

Period jitter

Long term jitter

Table 54. PLL characteristics (medium VCO frequency range)

PLL power consumption on V

DD

Conditions

-

-

VOS0

VOS1

VOS2

VOS3

-

Normal mode

Sigma-delta mode f

VCO_OUT

= 150 MHz f

VCO_OUT

= 200 MHz f

VCO_OUT

= 400 MHz -

-

f f f

VCO_OUT

= 420 MHz f

VCO_OUT

= 150 MHz

f

PLL_OUT

= 50 MHz f

VCO_OUT

= 400 MHz

Normal mode, f

VCO_OUT

= 400 MHz

VCO_OUT

VCO_OUT

= 420 MHz

= 150 MHz

V

DD

V

CORE

V

DD

-

-

-

-

-

-

-

Min

(1)

Typ

(1) Max (1)

Unit

1

10

1.17

1.17

-

-

-

-

2

90

210

210

MHz

%

1.17

1.17

150

-

-

-

45

-

forbidden

60

160 (2)

88 (2)

420

80

-

(3)

MHz

µs

-

40

18

-

-

±ps

15

75

25

-

-

-

±-ps

±0.2

275

450

160

-

360

-

240

%

µA

DS13196 - Rev 6 page 96/199

STM32H7B0xB

Operating conditions

Symbol

I

DD(PLL)

Parameter

PLL power consumption on V

DD f

VCO_OUT

Conditions

= 150 MHz

1. Guaranteed by design, unless otherwise specified.

2. This value must be limited to the maximum frequency due to the product limitation.

3. Guaranteed by characterization results.

6.3.12

V

CORE

Memory characteristics

Flash memory

The characteristics are given at T

J

= –40 to 130 °C unless otherwise specified.

The devices are shipped to customers with the Flash memory erased.

Symbol

I

DD

Parameter

Supply current

Table 55. Flash memory characteristics

Conditions

Word program

Sector erase

Mass erase

Min

-

-

-

Min

(1)

Typ

(1) Max (1)

Unit

165 µA

Typ

2.5

1.8

2.0

Max

4

3

3

Unit mA

Symbol t prog

Parameter

Word program time

Table 56. Flash memory programming

-

Conditions

128 bits (user area)

16 bits (OTP area) t

ERASE8KB t

ME

V prog

Sector erase time (8 Kbytes)

Bank mass erase time

Programming voltage

1. Guaranteed by characterization results.

Symbol Parameter

N t

END

RET

-

Endurance

Data retention

1. Guaranteed by characterization results.

Table 57. Flash memory endurance and data retention

Conditions

T

J

= –40 to +130 °C

1 kcycle at T

A

= 85 °C

10 kcycles at T

A

= 55 °C

Min

-

-

-

-

1.62

Typ

-

-

-

-

-

Value

Min (1)

10

30

20

Max

(1)

20

20

2.2

10

3.6

kcycles

Unit

Years

Unit

µs ms

V

DS13196 - Rev 6 page 97/199

6.3.13

STM32H7B0xB

Operating conditions

EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

•

•

Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

FTB : A burst of fast transient voltage (positive and negative) is applied to V

DD

and V

SS

through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Table 58. EMS characteristics

. They are based on the EMS levels and classes defined in application note AN1709.

Table 58. EMS characteristics

Symbol Parameter Conditions

V

FESD

V

FTB

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on V

DD

and V

SS

pins to induce a functional disturbance

V

DD

= 3.3 V, T

A

= +25 °C, LQFP144, f

216 MHz, conforms to IEC 61000-4-2 rcc_cpu_ck

=

Level/

Class

3B

5A

As a consequence, it is recommended to add a serial resistor (1 kΏ) located as close as possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm on PCB).

Designing hardened software to avoid noise problems

•

•

•

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

Corrupted program counter

Unexpected reset

Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values.

When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring

(see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading.

DS13196 - Rev 6 page 98/199

STM32H7B0xB

Operating conditions

Table 59. EMI characteristics

Symbol Parameter Conditions

S

EMI

Peak level

V

DD

= 3.6 V, T

A

= 25 °C, LQFP144 package, conforming to

IEC61967-2

6.3.14

Monitored frequency band

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1 GHz

1 GHz to 2 GHz

EMI Level

Max vs. [f

HSE f

CPU

]

/

8/216 MHz

12

17

15

14

3.5

Unit dBµV

-

Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC JS-001 and ANSI/ESDA/JEDEC JS-002 standards.

Table 60. ESD absolute maximum ratings

Symbol Ratings Conditions Packages Class

V

V

ESD(HBM)

ESD(CDM)

Electrostatic discharge voltage

(human body model)

Electrostatic discharge voltage

(charge device model)

T

JEDEC JS-001

T

A

A

= +25 °C conforming to ANSI/ESDA/

= +25 °C conforming to ANSI/ESDA/

JEDEC JS-002

Packages with

SMPS

Packages without

SMPS

1C

2

All LQFP packages C1

All BGA packages C2a

1. Guaranteed by characterization results.

2. The electrostatic discharge is 2000 V for all pins, except V

FBSMPS passes at 1600 V.

, for which the test fails at 2000 V and

Maximum value

1000

(2)

Unit

2000

250

500

V

Static latchup

Two complementary static tests are required on six parts to assess the latchup performance:

•

•

A supply overvoltage is applied to each power supply pin

A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with JESD78 IC latchup standard.

Symbol

LU

Parameter

Static latchup class

Table 61. Electrical sensitivities

Conditions

T

J

= +130 °C, conforming to JESD78

Class

II level A

DS13196 - Rev 6 page 99/199

STM32H7B0xB

Operating conditions

6.3.15

I/O current injection characteristics

As a general rule, a current injection to the I/O pins, due to external voltage below V

SS

or above V

DD

(for standard, 3.3 V-capable I/O pins) should be avoided during the normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when an abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during the device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency deviation).

The following tables are the compilation of the SIC1/SIC2 and functional ESD results.

Negative induced A negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection.

Symbol

I

INJ

Table 62. I/O current injection susceptibility

Description

Functional susceptibility

Negative injection Positive injection

Unit

0 NA PF2, PI12

PG1, PE9, PB0, PA7, PC4, PC5, PE7, PE8, PA4, PA5, PA6, PF2, PI12, PC2_C,

PC3_C, PA0_C, PA1_C, BOOT0

All other I/Os

0

5

0

NA mA

6.3.16

Note:

I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in

Table 63. I/O static characteristics are derived from tests

performed under the conditions summarized in

Table 20. General operating conditions

. All I/Os are CMOS and

TTL compliant (except for BOOT0).

For information on GPIO configuration, refer to the application note AN4899 “STM32 GPIO configuration for hardware settings and low-power consumption” available from the ST website www.st.com

.

Table 63. I/O static characteristics

Symbol

V

V

V

IL

IH

HYS

(2)

Parameter

I/O input low-level voltage except BOOT0

I/O input low-level voltage except BOOT0

BOOT0 I/O input low level voltage

I/O input high level voltage except BOOT0

I/O input high level voltage except BOOT0

BOOT0 I/O input high level voltage

TT_xx, FT_xxx and NRST I/O input hysteresis

BOOT0 I/O input hysteresis

Condition

1.62 V < V

DDIOx

< 3.6 V

1.62 V < V

DDIOx

< 3.6 V

1.62 V < V

DDIOx

< 3.6 V

I leak

FT_xx input leakage current (2)

0 < V

IN

≤ Max(V

DDxxx

) (5)

Max(V

DDxxx

) < V

IN

≤ 5.5 V (3)(4)(5)

Min Typ Max

-

-

-

0.7V

DD

(1)

0.47V

DD

+0.25

(2)

0.17V

DD

+0.6

(2)

-

-

-

-

250

200

-

-

0.3V

DD

(1)

0.4V

DD

−0.1

(2)

0.19V

DD

+0.1

(2)

-

-

-

-

-

Unit

V

V mV

-

-

-

±250

1500 nA

DS13196 - Rev 6 page 100/199

STM32H7B0xB

Operating conditions

Symbol

I leak

RPU

RPD

CIO

Parameter

FT_u I/O

TT_xx input leakage current

VPP (BOOT0 alternate function)

Weak pull-up equivalent resistor (7)

Weak pull-down equivalent resistor

(7)

I/O pin capacitance

Condition

0 < V

IN

≤ Max(V

DDxxx

) (5)

Max(V

DDxxx

) < V

IN

≤ 5.5 V

(3)(4) (8) (5)

0 < V

IN

≤ Max(V

DDxxx

) (5)

0 < V

IN

≤ V

DDIOx

V

DDIOx

< V

IN

≤ 9 V

V

IN

= V

SS

V

IN

= V

DD

(5)

-

Min

-

-

-

-

-

30

30

-

1. Compliant with CMOS requirements.

2. Guaranteed by design.

3. All FT_xx IO except FT_lu and FT_u.

4. V

IN

must be less than Max(V

DDxxx

) + 3.6 V.

5. Max(V

DDxxx

) is the maximum value of all the I/O supplies.

6. To sustain a voltage higher than MIN(V

DD

, V

DDA

, V

DD33USB

) +0.3 V, the internal pull-up and pull-down resistors must be disabled.

7. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/

NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10%).

-

40

40

5

-

-

Typ

-

-

Max

±350

5000

(6)

±250

15

35

50

50

-

Unit nA uA kΩ pF

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements for FT I/Os is shown in

Figure 25. V

IL

/V

IH

for all I/Os except BOOT0

.

Figure 25. V

IL

/V

IH

for all I/Os except BOOT0

DS13196 - Rev 6

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA

(with a relaxed V

OL

/V

OH

).

page 101/199

DS13196 - Rev 6

STM32H7B0xB

Operating conditions

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 6.2 Absolute maximum ratings . In particular:

•

•

The sum of the currents sourced by all the I/Os on V

DD, plus the maximum Run consumption of the MCU sourced on V

DD, cannot exceed the absolute maximum rating ΣI

VDD

(see Table 18. Current characteristics ).

The sum of the currents sunk by all the I/Os on V

SS on V

SS

plus the maximum Run consumption of the MCU sunk

cannot exceed the absolute maximum rating ΣI

VSS

(see

Table 18. Current characteristics

).

Output voltage levels

Unless otherwise specified, the parameters given in

Table 64. Output voltage characteristics for all I/Os except

PC13, PC14, PC15 and PI8 and Table 65. Output voltage characteristics for PC13, PC14, PC15 and PI8 are

derived from tests performed under ambient temperature and V

DD

supply voltage conditions summarized in

Table 20. General operating conditions . All I/Os are CMOS and TTL compliant.

Table 64. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8

The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 17. Voltage characteristics , and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the

absolute maximum ratings ΣIIO.

Symbol Parameter Conditions

(1)

Min Max Unit

V

V

V

V

V

V

V

V

OL

OH

OL

(1)

OH

(1)

OL

(1)

OH

(1)

OL

(1)

V

OH

(1)

OLFM+

(1)

Output low level voltage

Output high level voltage

Output low level voltage

Output high level voltage

Output low level voltage

Output high level voltage

Output low level voltage

Output high level voltage

Output low level voltage for an FTf I/O pin in FM+ mode

CMOS port

(2)

I

IO

=8 mA

2.7 V≤ V

DD

≤3.6 V

CMOS port

(2)

I

IO

= −8 mA

2.7 V≤ V

DD

≤3.6 V

V

DD

-

−0.4

0.4

-

TTL port (2)

I

IO

=8 mA

2.7 V≤ V

DD

≤3.6 V

TTL port (2)

I

IO

=-8 mA

2.7 V≤ V

DD

≤3.6 V

I

IO

=20 mA

2.7 V≤ V

DD

≤3.6 V

I

IO

=−20 mA

2.7 V≤ V

DD

≤3.6 V

I

IO

= 4 mA

1.62 V≤ V

DD

≤3.6 V

V

2.4

DD

-

-

-

−1.3

0.4

-

-

1.3

0.4

I

IO

= −4 mA 1.62 V≤V

DD

<3.6 V V

DD

−0.4

-

I

IO

= 20 mA

2.3 V≤ V

DD

≤3.6 V

0.4

I

IO

= 10 mA

1.62 V≤ V

DD

≤3.6 V

0.4

1. Guaranteed by design.

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

V

Table 65. Output voltage characteristics for PC13, PC14, PC15 and PI8

The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 17. Voltage characteristics , and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the

absolute maximum ratings ΣIIO.

page 102/199

DS13196 - Rev 6

STM32H7B0xB

Operating conditions

V

V

Symbol

OL

OH

V

OL

(1)

V

OH

(1)

V

OL

(1)

V

OH

(1)

V

OL

(1)

V

OH

(1)

Parameter

Output low level voltage

Output high level voltage

Output low level voltage

Output high level voltage

Output low level voltage

Output high level voltage

Output low level voltage I

I

I

TTL port

TTL port

IO

IO

IO

(2)

(2)

I

IO

I

IO

Conditions

=−8 mA, 2.7 V ≤ V

DD

=20 mA, 2.7 V ≤ V

DD

= −20 mA, 2.7 V ≤ V

DD

= 4 mA, 1.62 V ≤ V

DD

(1)

= 8 mA, 2.7 V≤ V

≤ 3.6 V

DD

≤ 3.6 V

≤ 3.6 V

V

OLFM+

(1)

Output high level voltage

Output low level voltage for an FT_f I/O pin in FM+ mode

I

IO

= −4 mA, 1.62 V ≤ V

DD

< 3.6 V

I

IO

= 20 mA, 2.3 V ≤ V

DD

≤ 3.6 V

I

IO

= 10 mA, 1.62 V ≤ V

DD

≤ 3.6 V

1. Guaranteed by design.

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

≤ 3.6 V

≤ 3.6 V

-

-

-

-

-

2.4

Min

VDD−1.3 -

VDD−0.4 -

-

Max Unit

CMOS port (2)

I

IO

=8 mA, 2.7 V≤ VDD ≤ 3.6 V -

CMOS port (2)

I

IO

= −8 mA, 2.7 V≤ V

DD

≤ 3.6 V

0.4

V

DD

−0.4 -

0.4

1.3

0.4

0.4

0.4

V

Output buffer timing characteristics (HSLV option disabled)

The HSLV bit of SYSCFG_CCCSR register can be used to optimize the I/O speed when the product voltage is below 2.7 V.

Speed Symbol

00

01

F max

(2)

t r

/t f

(3)

F max

(2)

t r

/t f

(3)

Table 66. Output timing characteristics (HSLV OFF)

Parameter

Maximum frequency

Output high to low level fall time and output low to high level rise time

Maximum frequency

Output high to low level fall time and output low to high level rise time conditions

C=50 pF, 2.7 V≤ V

DD

≤3.6 V

C=50 pF, 1.62 V≤V

DD

≤2.7 V

C=30 pF, 2.7 V≤V

DD

≤3.6 V

C=30 pF, 1.62 V≤V

DD

≤2.7 V

C=10 pF, 2.7 V≤V

DD

≤3.6 V

C=10 pF, 1.62 V≤V

DD

≤2.7 V

C=50 pF, 2.7 V≤ V

DD

≤3.6 V

C=50 pF, 1.62 V≤V

DD

≤2.7 V

C=30 pF, 2.7 V≤V

DD

≤3.6 V

C=30 pF, 1.62 V≤V

DD

≤2.7 V

C=10 pF, 2.7 V≤V

DD

≤3.6 V

C=10 pF, 1.62 V≤V

DD

≤2.7 V

C=50 pF, 2.7 V≤ V

DD

≤3.6 V

C=50 pF, 1.62 V≤V

DD

≤2.7 V

C=30 pF, 2.7 V≤V

DD

≤3.6 V

C=30 pF, 1.62 V≤V

DD

≤2.7 V

C=10 pF, 2.7 V≤V

DD

≤3.6 V

C=10 pF, 1.62 V≤V

DD

≤2.7 V

C=50 pF, 2.7 V≤ V

DD

≤3.6 V

C=50 pF, 1.62 V≤V

DD

≤2.7 V

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Min (1) Max (1)

Unit

12

-

3

12

MHz

-

3

16

4

16.6

33.3

13.3

25

10

20

60

15

80 ns

MHz

15

110

20

5.2

10 ns page 103/199

DS13196 - Rev 6

STM32H7B0xB

Operating conditions

Speed Symbol

01

10

11

(5)

F

F t t t r r r

/t max

(2)

/t max

(2)

/t f f f

(3)

(3)

(3)

Parameter

Output high to low level fall time and output low to high level rise time

Maximum frequency

Output high to low level fall time and output low to high level rise time

Maximum frequency

Output high to low level fall time and output low to high level rise time conditions

C=30 pF, 2.7 V≤V

DD

≤3.6 V

C=30 pF, 1.62 V≤V

DD

≤2.7 V

C=10 pF, 2.7 V≤V

DD

≤3.6 V

C=10 pF, 1.62 V≤V

DD

≤2.7 V

C=50 pF, 2.7 V≤V

DD

≤3.6 V (4)

C=50 pF, 1.62 V≤V

DD

≤2.7 V

(4)

C=30 pF, 2.7 V≤V

DD

≤3.6 V (4)

C=30 pF, 1.62 V≤V

DD

≤2.7 V

(4)

C=10 pF, 2.7 V≤V

DD

≤3.6 V (4)

C=10 pF, 1.62 V≤V

DD

≤2.7 V

(4)

C=50 pF, 2.7 V≤V

DD

≤3.6 V (4)

C=50 pF, 1.62 V≤V

DD

≤2.7 V

(4)

C=30 pF, 2.7 V≤V

DD

≤3.6 V (4)

C=30 pF, 1.62 V≤V

DD

≤2.7 V

(4)

C=10 pF, 2.7 V≤V

DD

≤3.6 V (4)

C=10 pF, 1.62 V≤V

DD

≤2.7 V

(4)

C=50 pF, 2.7 V≤V

DD

≤3.6 V (4)

C=50 pF, 1.62 V≤V

DD

≤2.7 V

(4)

C=30 pF, 2.7 V≤V

DD

≤3.6 V (4)

C=30 pF, 1.62 V≤V

DD

≤2.7 V

(4)

C=10 pF, 2.7 V≤V

DD

≤3.6 V (4)

C=10 pF, 1.62 V≤V

DD

≤2.7 V

(4)

C=50 pF, 2.7 V≤V

DD

≤3.6 V (4)

C=50 pF, 1.62 V≤V

DD

≤2.7 V

(4)

C=30 pF, 2.7 V≤V

DD

≤3.6 V (4)

C=30 pF, 1.62 V≤V

DD

≤2.7 V

(4)

C=10 pF, 2.7 V≤V

DD

≤3.6 V (4)

C=10 pF, 1.62 V≤V

DD

≤2.7 V

(4)

Min

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

(1) Max

4.2

7.5

2.8

5.2

85

35

110

40

166

100

3.8

6.9

2.8

5.2

1.8

3.3

100

50

133

66

220

85

3.3

6.6

2.4

4.5

1.5

2.7

(1)

Unit ns

MHz ns

MHz ns

1. Guaranteed by design.

2. The maximum frequency is defined with the following conditions: (t r

+t f

) ≤ 2/3 T, skew ≤ 1/20 T, 45%<Duty cycle<55%

3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.

4. Compensation system enabled.

5. Reserved for output clock only.

Output buffer timing characteristics (HSLV option enabled)

Speed Symbol

00 F max

(2)

Table 67. Output timing characteristics (HSLV ON)

Parameter

Maximum frequency conditions

C=50 pF, 1.62 V≤VDD≤2.7 V

Min (1) Max (1)

Unit

10

MHz page 104/199

6.3.17

STM32H7B0xB

Operating conditions

Speed Symbol

00

01

10

11

(5)

F

F

F

F t t t t max

(2)

r r r

/t

/t

/t f

(3)

max

(2)

r

/t f

(3)

max

(2)

f

(3)

max

(2)

f

(3)

Parameter

Maximum frequency

Output high to low level fall time and output low to high level rise time

Maximum frequency

Output high to low level fall time and output low to high level rise time

Maximum frequency

Output high to low level fall time and output low to high level rise time

Maximum frequency

Output high to low level fall time and output low to high level rise time conditions

C=30 pF, 1.62 V≤VDD≤2.7 V

C=10 pF, 1.62 V≤VDD≤2.7 V

C=50 pF, 1.62 V≤VDD≤2.7 V

C=30 pF, 1.62 V≤VDD≤2.7 V

C=10 pF, 1.62 V≤VDD≤2.7 V

C=50 pF, 1.62 V≤VDD≤2.7 V

C=30 pF, 1.62 V≤VDD≤2.7 V

C=10 pF, 1.62 V≤VDD≤2.7 V

C=50 pF, 1.62 V≤VDD≤2.7 V

C=30 pF, 1.62 V≤VDD≤2.7 V

C=10 pF, 1.62 V≤VDD≤2.7 V

C=50 pF, 1.62 V≤VDD≤2.7 V

(4)

C=30 pF, 1.62 V≤VDD≤2.7 V

(4)

C=10 pF, 1.62 V≤VDD≤2.7 V

(4)

C=50 pF, 1.62 V≤VDD≤2.7 V

(4)

C=30 pF, 1.62 V≤VDD≤2.7 V

(4)

C=10 pF, 1.62 V≤VDD≤2.7 V

(4)

C=50 pF, 1.62 V≤VDD≤2.7 V

(4)

C=30 pF, 1.62 V≤VDD≤2.7 V

(4)

C=10 pF, 1.62 V≤VDD≤2.7 V

(4)

C=50 pF, 1.62 V≤VDD≤2.7 V

(4)

C=30 pF, 1.62 V≤VDD≤2.7 V

(4)

C=10 pF, 1.62 V≤VDD≤2.7 V

(4)

Min (1) Max (1)

Unit

-

-

-

-

-

-

-

-

-

-

-

-

MHz ns

MHz ns

6.6

4.8

3

55

50

58

66

10

10

11

9

6.6

-

-

-

-

-

-

-

-

-

-

-

80

133

5.8

4

2.4

60

90

175

5.3

3.6

1.9

MHz ns

MHz ns

1. Guaranteed by design.

2. The maximum frequency is defined with the following conditions: (t r

+t f

) ≤ 2/3 T, skew ≤ 1/20 T, 45%<Duty cycle<55%

3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.

4. Compensation system enabled.

5. Reserved for output clock only.

NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

PU

(see

Table 63. I/O static characteristics ).

Unless otherwise specified, the parameters given in

Table 68. NRST pin characteristics

are derived from tests performed under the ambient temperature and V

DD

supply voltage conditions summarized in

Table 20. General operating conditions .

Symbol

R

PU

(1)

V

F(NRST)

(1)

V

NF(NRST)

(1)

Table 68. NRST pin characteristics

Parameter

Weak pull-up equivalent resistor (2)

NRST Input filtered pulse

NRST Input not filtered pulse

Conditions

V

IN

= V

SS

1.71 V < V

DD

< 3.6 V

1.71 V < V

DD

< 3.6 V

1.62 V < V

DD

< 3.6 V

Min

30

-

350

1000

Typ Max Unit

40 50 ㏀

-

-

-

50

-

ns

DS13196 - Rev 6 page 105/199

STM32H7B0xB

Operating conditions

1. Guaranteed by design.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10%).

Figure 26. Recommended NRST pin protection

External reset circuit (1)

NRST (2)

VDD

R PU

0.1 µF

Filter

Internal Reset

STM32

6.3.18

Note:

1.

The reset network protects the device against parasitic resets.

2.

The user must ensure that the level on the NRST pin can go below the V

IL(NRST)

max level specified in

Table 63. I/O static characteristics . Otherwise the reset is not taken into account by the device.

•

•

•

•

•

FMC characteristics

Unless otherwise specified, the parameters given in the below tables for the FMC interface are derived from tests performed under the ambient temperature, f

HCLK

frequency and V

DD

supply voltage conditions summarized in

Table 20. General operating conditions , with the following configuration:

Output speed is set to OSPEEDRy[1:0] = 11

Measurement points are done at CMOS levels: 0.5V

DD

IO Compensation cell activated.

HSLV activated when V

DD

≤ 2.7 V

VOS level set to VOS0.

At VOS1, the performance in some FMC modes can be degraded by up to 5 % compared to VOS0. This is indicated by a footnote when applicable.

Refer to

Section 6.3.16 I/O port characteristics

for more details on the input/output alternate function characteristics.

Asynchronous waveforms and timings

Figure 27 through

Figure 29

represent asynchronous waveforms and

Table 69 through

Table 76

provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration:

•

•

•

•

•

AddressSetupTime = 0x1

AddressHoldTime = 0x1

DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)

BusTurnAroundDuration = 0x0

Capacitive load C

L

= 30 pF

In all timing tables, T fmc_ker_ck

is the kernel clock period.

DS13196 - Rev 6 page 106/199

DS13196 - Rev 6

STM32H7B0xB

Operating conditions

Figure 27. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms t w(NE)

FMC_NE t v(NOE_NE) t w(NOE) t h(NE_NOE)

FMC_NOE

FMC_NWE

FMC_A[25:0]

t

v(A_NE)

t

v(BL_NE)

Address t h(A_NOE) t h(BL_NOE)

FMC_NBL[1:0] t h(Data_NE) t h(Data_NOE)

FMC_D[15:0] t su(Data_NOE) t su(Data_NE)

Data t v(NADV_NE) t w(NADV)

FMC_NADV (1)

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE)

1.

Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

Symbol t w(NE) t v(NOE_NE) t w(NOE) t h(NE_NOE) t v(A_NE) t h(A_NOE) t su(Data_NE) t su(Data_NOE) t h(Data_NOE)

Table 69. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings

Parameter

FMC_NE low time

FMC_NEx low to FMC_NOE low

FMC_NOE low time

FMC_NOE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

Address hold time after FMC_NOE high

Data to FMC_NEx high setup time

Data to FMC_NOEx high setup time

Data hold time after FMC_NOE high

Min (1)

3T fmc_ker_ck

− 1

0

2T fmc_ker_ck

− 1

0

-

0

13

11

0

Max

(1)

3T fmc_ker_ck

+1

0.5

2T fmc_ker_ck

+ 1

-

0.5

-

-

-

-

Unit ns page 107/199

DS13196 - Rev 6

STM32H7B0xB

Operating conditions

Symbol t h(Data_NE) t v(NADV_NE) t w(NADV)

Parameter

Data hold time after FMC_NEx high

FMC_NEx low to FMC_NADV low

FMC_NADV low time

1. Guaranteed by characterization results.

Min (1)

0

-

-

Max

(1)

-

0

T fmc_ker_ck

+ 1

Unit ns

Table 70. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings

NWAIT pulse width is equal to 1 AHB cycle.

Symbol Parameter

Min (1) Max (1)

t w(NE) t w(NOE) t w(NWAIT) t su(NWAIT_NE) t h(NE_NWAIT)

FMC_NE low time

FMC_NWE low time

FMC_NWAIT low time

FMC_NWAIT valid before FMC_NEx high

FMC_NEx hold time after FMC_NWAIT invalid

7T fmc_ker_ck +1

5T fmc_ker_ck −1

T fmc_ker_ck −1

−0.5

4T fmc_ker_ck

+9

3T fmc_ker_ck

+12

7T fmc_ker_ck +1

5T fmc_ker_ck

+1

-

-

-

1. Guaranteed by characterization results.

Unit ns

Figure 28. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE)

FMC_NEx

FMC_NOE

FMC_NWE

FMC_A[25:0]

FMC_NBL[1:0]

FMC_D[15:0]

FMC_NADV(1) tv(NWE_NE) tw(NWE) tv(A_NE) tv(BL_NE) tv(Data_NE) tv(NADV_NE) tw(NADV) th(A_NWE)

Address th(BL_NWE)

NBL th(Data_NWE)

Data th(NE_NWE)

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) page 108/199

DS13196 - Rev 6

STM32H7B0xB

Operating conditions

1.

Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

Table 71. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings

Symbol t w(NE) t v(NWE_NE) t w(NWE) t h(NE_NWE) t v(A_NE) t h(A_NWE) t v(BL_NE) t h(BL_NWE) t v(Data_NE) t h(Data_NWE) t v(NADV_NE) t w(NADV)

Parameter

FMC_NE low time

FMC_NEx low to FMC_NWE low

FMC_NWE low time

FMC_NWE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

Address hold time after FMC_NWE high

FMC_NEx low to FMC_BL valid

FMC_BL hold time after FMC_NWE high

Data to FMC_NEx low to Data valid

Data hold time after FMC_NWE high

FMC_NEx low to FMC_NADV low

FMC_NADV low time

1. Guaranteed by characterization results.

Min (1)

3T fmc_ker_ck − 1

T fmc_ker_ck

− 1

T fmc_ker_ck

− 0.5

T fmc_ker_ck

-

T fmc_ker_ck

+ 0.5

-

T fmc_ker_ck

− 0.5

-

T fmc_ker_ck+1

-

-

Max (1)

3T fmc_ker_ck + 1

T fmc_ker_ck

T fmc_ker_ck

+ 0.5

-

2

-

0.5

-

T fmc_ker_ck

+ 3

-

0

T fmc_ker_ck

+ 1

Unit ns

Table 72. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings

NWAIT pulse width is equal to 1 AHB cycle.

Symbol Parameter

Min (1) Max (1)

t w(NE) t w(NWE) t su(NWAIT_NE) t h(NE_NWAIT)

FMC_NE low time

FMC_NWE low time

FMC_NWAIT valid before FMC_NEx high

FMC_NEx hold time after FMC_NWAIT invalid

8T fmc_ker_ck − 1

6T fmc_ker_ck − 1

5T fmc_ker_ck

+ 13

4T fmc_ker_ck

+ 12

8T fmc_ker_ck + 1

6T fmc_ker_ck + 1

-

-

1. Guaranteed by characterization results.

Unit ns page 109/199

DS13196 - Rev 6

STM32H7B0xB

Operating conditions

Figure 29. Asynchronous multiplexed PSRAM/NOR read waveforms tw(NE)

FMC_NE tv(NOE_NE) th(NE_NOE)

FMC_NOE tw(NOE)

FMC_NWE tv(A_NE) th(A_NOE)

FMC_A[25:16]

Address tv(BL_NE) th(BL_NOE)

FMC_NBL[1:0] NBL

FMC_AD[15:0] tv(NADV_NE) tv(A_NE)

Address th(AD_NADV) tw(NADV) tsu(Data_NE) tsu(Data_NOE)

Data th(Data_NE) th(Data_NOE)

FMC_NADV

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE)

Symbol t w(NE) t v(NOE_NE) t w(NOE) t h(NE_NOE) t v(A_NE) t v(NADV_NE) t w(NADV) t h(AD_NADV) t h(A_NOE) t su(Data_NE) t su(Data_NOE)

Table 73. Asynchronous multiplexed PSRAM/NOR read timings

Parameter

FMC_NE low time

FMC_NEx low to FMC_NOE low

FMC_NOE low time

FMC_NOE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

FMC_NEx low to FMC_NADV low

FMC_NADV low time

FMC_AD(address) valid hold time after FMC_NADV high

Address hold time after FMC_NOE high

Data to FMC_NEx high setup time

Data to FMC_NOE high setup time

Min (1)

4T fmc_ker_ck − 1

2T fmc_ker_ck

T fmc_ker_ck

− 1

0

-

0

T fmc_ker_ck

− 0.5

T fmc_ker_ck

+ 0.5

T fmc_ker_ck

− 0.5

13

11

Max

(1)

4T fmc_ker_ck + 1

2T fmc_ker_ck + 0.5

T fmc_ker_ck

+ 1

-

0.5

0.5

T fmc_ker_ck

+1

-

-

-

-

Unit ns page 110/199

DS13196 - Rev 6

STM32H7B0xB

Operating conditions

Symbol t h(Data_NE) t h(Data_NOE)

1. Guaranteed by characterization results.

Parameter

Data hold time after FMC_NEx high

Data hold time after FMC_NOE high

Min (1)

0

0

Max

(1)

-

-

Unit ns

Table 74. Asynchronous multiplexed PSRAM/NOR read - NWAIT timings

Symbol t w(NE) t w(NOE) t su(NWAIT_NE) t h(NE_NWAIT)

Parameter

FMC_NE low time

FMC_NWE low time

FMC_NWAIT valid before FMC_NEx high

FMC_NEx hold time after FMC_NWAIT invalid

1. Guaranteed by characterization results.

Min (1)

8T fmc_ker_ck

− 1

5T fmc_ker_ck

− 1

4T fmc_ker_ck

+ 9

4T fmc_ker_ck

+ 12

Max (1)

8T fmc_ker_ck

+ 1

5T fmc_ker_ck

+ 1

-

-

Unit ns

Table 75. Asynchronous multiplexed PSRAM/NOR write timings

Symbol t w(NE) t v(NWE_NE) t w(NWE) t h(NE_NWE) t v(A_NE) t v(NADV_NE) t w(NADV) t h(AD_NADV) t h(A_NWE) t h(BL_NWE) t v(BL_NE) t v(Data_NADV) t h(Data_NWE)

Parameter

FMC_NE low time

FMC_NEx low to FMC_NWE low

FMC_NWE low time

FMC_NWE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

FMC_NEx low to FMC_NADV low

FMC_NADV low time

FMC_AD(address) valid hold time after FMC_NADV high

Address hold time after FMC_NWE high

FMC_BL hold time after FMC_NWE high

FMC_NEx low to FMC_BL valid

FMC_NADV high to Data valid

Data hold time after FMC_NWE high

1. Guaranteed by characterization results.

Min (1)

Max

(1)

4T fmc_ker_ck

− 1

Tfmc_ker_c − 1

4T fmc_ker_ck

T fmc_ker_ck

+ 0.5

2T fmc_ker_ck

− 0.5

2T fmc_ker_ck

+ 0.5

T fmc_ker_ck

− 0.5

-

0

0

T fmc_ker_ck

T fmc_ker_ck

+ 0.5

T fmc_ker_ck

+ 0.5

T fmc_ker_ck

− 0.5

-

-

T fmc_ker_ck

+0.5

0.5

T fmc_ker_ck

+ 1

-

-

-

0.5

T fmc_ker_ck

-

+ 2

Unit ns

Table 76. Asynchronous multiplexed PSRAM/NOR write - NWAIT timings

Symbol t w(NE) t w(NWE) t su(NWAIT_NE) t h(NE_NWAIT)

Parameter

FMC_NE low time

FMC_NWE low time

FMC_NWAIT valid before FMC_NEx high

FMC_NEx hold time after FMC_NWAIT invalid

1. Guaranteed by characterization results.

Min (1)

9T fmc_ker_ck

− 1

7T fmc_ker_ck

− 0.5

5T fmc_ker_ck

+ 9

4T fmc_ker_ck

+ 12

Max

(1)

9T fmc_ker_ck

7T fmc_ker_ck

+ 0.5

-

-

Synchronous waveforms and timings

Figure 30

through Figure 33

represent synchronous waveforms and Table 77

through

Table 80 provide the

corresponding timings. The results shown in these tables are obtained with the following FMC configuration:

Unit ns page 111/199

DS13196 - Rev 6

STM32H7B0xB

Operating conditions

•

•

•

•

BurstAccessMode = FMC_BurstAccessMode_Enable

MemoryType = FMC_MemoryType_CRAM

WriteBurst = FMC_WriteBurst_Enable

CLKDivision = 1

• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM

In all timing tables, T fmc_ker_ck

is the kernel clock period, with the following FMC_CLK maximum values:

•

•

•

For 2.7 V < V

DD

< 3.6 V, FMC_CLK = 125 MHz at 20 pF

For 1.8 V < V

DD

< 1.9 V, FMC_CLK = 100 MHz at 20 pF

For 1.62 V < V

DD

<1.8 V, FMC_CLK = 100 MHz at 15 pF

Figure 30. Synchronous multiplexed NOR/PSRAM read timings tw(CLK) tw(CLK) BUSTURN = 0

FMC_CLK td(CLKL-NExL)

Data latency = 0 td(CLKH-NExH)

FMC_NEx td(CLKL-NADVL)

FMC_NADV td(CLKL-NADVH) td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16] td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE td(CLKL-ADV)

FMC_AD[15:0]

FMC_NWAIT

(WAITCFG = 1b,

WAITPOL + 0b)

FMC_NWAIT

(WAITCFG = 0b,

WAITPOL + 0b) td(CLKL-ADIV)

AD[15:0] tsu(ADV-CLKH) tsu(NWAITV-CLKH)

D1 th(CLKH-ADV) tsu(ADV-CLKH) tsu(NWAITV-CLKH)

D2 th(CLKH-NWAITV) th(CLKH-ADV) th(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV)

Symbol t w(CLK) t d(CLKL-NExL) t d(CLKH_NExH)

Table 77. Synchronous multiplexed NOR/PSRAM read timings

Parameter

FMC_CLK period

FMC_CLK low to FMC_NEx low (x=0..2)

FMC_CLK high to FMC_NEx high (x= 0…2)

Min

(1)

2T fmc_ker_ck

–0.5

-

T fmc_ker_ck

+1.5

Max (1)(2)

-

2

-

Unit ns page 112/199

Symbol t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NOEL) t d(CLKH-NOEH) t d(CLKL-ADV) t d(CLKL-ADIV) t su(ADV-CLKH) t h(CLKH-ADV) t su(NWAIT-CLKH) t h(CLKH-NWAIT)

Parameter

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

FMC_CLK low to FMC_NOE low

FMC_CLK high to FMC_NOE high

FMC_CLK low to FMC_AD[15:0] valid

FMC_CLK low to FMC_AD[15:0] invalid

FMC_A/D[15:0] valid data before FMC_CLK high

FMC_A/D[15:0] valid data after FMC_CLK high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

1. Guaranteed by characterization results.

2. At VOS1, these values are degraded by up to 5 %.

STM32H7B0xB

Operating conditions

Min

(1)

-

0

-

T fmc_ker_ck

+1.5

-

T fmc_ker_ck

+1.5

-

0

3

0.5

3

1

-

-

-

-

-

1.5

-

3

Max (1)(2)

Unit

1

-

2.0

ns

DS13196 - Rev 6 page 113/199

DS13196 - Rev 6

STM32H7B0xB

Operating conditions

FMC_CLK

Figure 31. Synchronous multiplexed PSRAM write timings tw(CLK) tw(CLK) BUSTURN = 0 td(CLKL-NExL)

Data latency = 0 td(CLKH-NExH)

FMC_NEx td(CLKL-NADVL)

FMC_NADV td(CLKL-NADVH) td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16] td(CLKL-NWEL) td(CLKH-NWEH)

FMC_NWE td(CLKL-ADV)

FMC_AD[15:0]

FMC_NWAIT

(WAITCFG = 0b,

WAITPOL + 0b) td(CLKL-ADIV)

AD[15:0] td(CLKL-Data) td(CLKL-Data)

D1 D2 tsu(NWAITV-CLKH) th(CLKH-NWAITV) td(CLKH-NBLH)

FMC_NBL

Symbol t w(CLK) t d(CLKL-NExL) t d(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NWEL) t

(CLKH-NWEH)

Table 78. Synchronous multiplexed PSRAM write timings

Parameter

FMC_CLK period

FMC_CLK low to FMC_NEx low (x =0..2)

FMC_CLK high to FMC_NEx high

(x = 0…2)

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid

(x =16…25)

FMC_CLK high to FMC_Ax invalid

(x =16…25)

FMC_CLK low to FMC_NWE low

FMC_CLK high to FMC_NWE high

Min

(1)

2T fmc_ker_ck

–1

-

T fmc_ker_ck

+1.5

-

0

-

T fmc_ker_ck

+1.5

-

T fmc_ker_ck

+1

Max (1)(2)

-

2

Unit

-

1.5

-

2 ns

-

1.5

page 114/199

DS13196 - Rev 6

STM32H7B0xB

Operating conditions

Symbol t d(CLKL-ADV) t d(CLKL-ADIV) t d(CLKL-DATA) t d(CLKL-NBLL) t d(CLKH-NBLH) t su(NWAIT-CLKH) t h(CLKH-NWAIT)

Parameter

FMC_CLK low to to FMC_AD[15:0] valid

FMC_CLK low to FMC_AD[15:0] invalid

FMC_A/D[15:0] valid data after FMC_CLK low

FMC_CLK low to FMC_NBL low

FMC_CLK high to FMC_NBL high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

1. Guaranteed by characterization results.

2. At VOS1, these values are degraded by up to 5 %.

Min

(1)

-

0

-

-

T fmc_ker_ck

+0.5

2

2

Figure 32. Synchronous non-multiplexed NOR/PSRAM read timings tw(CLK)

FMC_CLK td(CLKL-NExL)

FMC_NEx td(CLKL-NADVL) tw(CLK)

Data latency = 0 td(CLKL-NADVH) td(CLKH-NExH)

FMC_NADV td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0] td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE tsu(DV-CLKH)

FMC_D[15:0] tsu(NWAITV-CLKH)

D1 th(CLKH-DV) tsu(DV-CLKH)

D2 th(CLKH-NWAITV) th(CLKH-DV)

FMC_NWAIT

(WAITCFG = 1b,

WAITPOL + 0b)

FMC_NWAIT

(WAITCFG = 0b,

WAITPOL + 0b) tsu(NWAITV-CLKH) tsu(NWAITV-CLKH) t h(CLKH-NWAITV) th(CLKH-NWAITV)

Max (1)(2)

Unit

2.5

-

3

2 ns

-

-

-

Symbol t w(CLK) t

(CLKL-NExL)

Table 79. Synchronous non-multiplexed NOR/PSRAM read timings

Parameter

FMC_CLK period

FMC_CLK low to FMC_NEx low (x=0..2)

Min (1)

2T fmc_ker_ck

–0.5

-

Max (1)(2)

-

2

Unit ns page 115/199

DS13196 - Rev 6

STM32H7B0xB

Operating conditions t

Symbol d(CLKH-NExH)

Parameter

FMC_CLK high to FMC_NEx high

(x= 0…2)

FMC_CLK low to FMC_NADV low t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NOEL) t d(CLKH-NOEH) t su(DV-CLKH) t h(CLKH-DV) t

(NWAIT-CLKH) t h(CLKH-NWAIT)

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

FMC_CLK low to FMC_NOE low

FMC_CLK high to FMC_NOE high

FMC_D[15:0] valid data before FMC_CLK high

FMC_D[15:0] valid data after FMC_CLK high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

1. Guaranteed by characterization results.

2. At VOS1, these values are degraded by up to 5 %.

Min (1)

T fmc_ker_ck

+1.5

-

0

-

T fmc_ker_ck

+1.5

-

T fmc_ker_ck

+1

3

0.5

3

1

FMC_CLK tw(CLK) td(CLKL-NExL)

FMC_NEx td(CLKL-NADVL)

FMC_NADV

Figure 33. Synchronous non-multiplexed PSRAM write timings tw(CLK)

Data latency = 0 td(CLKL-NADVH) td(CLKH-NExH) td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0] td(CLKL-NWEL) td(CLKH-NWEH)

FMC_NWE

FMC_D[15:0] td(CLKL-Data)

D1 td(CLKL-Data)

D2

Max (1)(2)

Unit

-

1.5

-

2

-

1.5

-

-

-

-

ns

FMC_NWAIT

(WAITCFG = 0b,

WAITPOL + 0b)

FMC_NBL tsu(NWAITV-CLKH) td(CLKH-NBLH) th(CLKH-NWAITV) page 116/199

DS13196 - Rev 6

STM32H7B0xB

Operating conditions

Table 80. Synchronous non-multiplexed PSRAM write timings

Symbol t

(CLK) t d(CLKL-NExL) t

(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NWEL) t d(CLKH-NWEH) t d(CLKL-Data) t d(CLKL-NBLL) t d(CLKH-NBLH) t su(NWAIT-CLKH) t h(CLKH-NWAIT)

FMC_CLK period

Parameter

FMC_CLK low to FMC_NEx low (x=0..2)

FMC_CLK high to FMC_NEx high (x= 0…2)

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

FMC_CLK low to FMC_NWE low

FMC_CLK high to FMC_NWE high

FMC_D[15:0] valid data after FMC_CLK low

FMC_CLK low to FMC_NBL low

FMC_CLK high to FMC_NBL high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

1. Guaranteed by characterization results.

2. At VOS1, these values are degraded by up to 5 %.

-

0

-

Min

(1)

2T fmc_ker_ck

− 0.5

T fmc_ker_ck

+ 1.5

-

-

T fmc_ker_ck

+ 1.5

-

-

T fmc_ker_ck

+ 1

T fmc_ker_ck

+ 0.5

2

2

NAND controller waveforms and timings

Figure 34

through Figure 37 represent synchronous waveforms, and Table 81

and Table 82

provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration:

•

•

•

•

•

•

•

•

•

•

•

•

COM.FMC_SetupTime = 0x01

COM.FMC_WaitSetupTime = 0x03

COM.FMC_HoldSetupTime = 0x02

COM.FMC_HiZSetupTime = 0x01

ATT.FMC_SetupTime = 0x01

ATT.FMC_WaitSetupTime = 0x03

ATT.FMC_HoldSetupTime = 0x02

ATT.FMC_HiZSetupTime = 0x01

Bank = FMC_Bank_NAND

MemoryDataWidth = FMC_MemoryDataWidth_16b

ECC = FMC_ECC_Enable

ECCPageSize = FMC_ECCPageSize_512Bytes

•

•

•

TCLRSetupTime = 0

TARSetupTime = 0

Capacitive load C

L

= 30 pF

In all timing tables, T fmc_ker_ck

is the kernel clock period.

-

3

2

-

-

-

-

1.5

-

-

1.5

2

-

2

Max

(1)(2)

Unit ns page 117/199

DS13196 - Rev 6

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16)

FMC_NWE

FMC_NOE (NRE)

FMC_D[15:0]

Figure 34. NAND controller waveforms for read access

STM32H7B0xB

Operating conditions td(ALE-NOE) tsu(D-NOE) th(NOE-D) th(NOE-ALE)

Figure 35. NAND controller waveforms for write access

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16)

FMC_NWE

FMC_NOE (NRE)

FMC_D[15:0] tv(NWE-D) td(ALE-NWE) th(NWE-D) th(NWE-ALE) page 118/199

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16)

FMC_NWE

FMC_NOE

STM32H7B0xB

Operating conditions

Figure 36. NAND controller waveforms for common memory read access td(ALE-NOE) tw(NOE) tsu(D-NOE) th(NOE-D) th(NOE-ALE)

FMC_D[15:0]

Figure 37. NAND controller waveforms for common memory write access

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16) td(ALE-NOE)

FMC_NWE

FMC_NOE tw(NWE) th(NOE-ALE) td(D-NWE) tv(NWE-D) th(NWE-D)

FMC_D[15:0]

DS13196 - Rev 6

Table 81. Switching characteristics for NAND Flash memory read cycles

Symbol t w(N0E) t su(D-NOE) t h(NOE-D) t d(ALE-NOE) t h(NOE-ALE)

Parameter

FMC_NOE low width

FMC_D[15-0] valid data before FMC_NOE high

FMC_D[15-0] valid data after FMC_NOE high

FMC_ALE valid before FMC_NOE low

FMC_NWE high to FMC_ALE invalid

1. Guaranteed by characterization results.

Min

(1)

4T fmc_ker_ck

– 0.5

8

0

-

4T fmc_ker_ck

–1

Max

(1)

4T fmc_ker_ck

+0.5

-

-

3T fmc_ker_ck

+0.5

-

Unit ns page 119/199

DS13196 - Rev 6

STM32H7B0xB

Operating conditions

Table 82. Switching characteristics for NAND Flash write cycles

Symbol t w(NWE) t v(NWE-D) t h(NWE-D) t d(D-NWE) t d(ALE-NWE) t h(NWE-ALE)

Parameter

FMC_NWE low width

FMC_NWE low to FMC_D[15-0] valid

FMC_NWE high to FMC_D[15-0] invalid

FMC_D[15-0] valid before FMC_NWE high

FMC_ALE valid before FMC_NWE low

FMC_NWE high to FMC_ALE invalid

1. Guaranteed by characterization results.

Min

(1)

4T fmc_ker_ck

– 0.5

0

2T fmc_ker_ck

+ 1.5

5T fmc_ker_ck

– 2

-

2T fmc_ker_ck

+ 0.5

Max

(1)

4T fmc_ker_ck

+0.5

-

-

-

3T fmc_ker_ck

+0.5

-

SDRAM waveforms and timings

In all timing tables, T fmc_ker_ck

is the kernel clock period, with the following FMC_SDCLK maximum values:

•

•

•

For 2.7 V < V

DD

<3.6 V: FMC_CLK =110 MHz at 20 pF

For 1.8 V < V

DD

<1.9 V: FMC_CLK =100 MHz at 20 pF

For 1.62 V <

DD

<1.8 V, FMC_CLK =100 MHz at 15 pF

Unit ns

Figure 38. SDRAM read access waveforms (CL = 1)

FMC_SDCLK td(SDCLKL_AddR)

FMC_A[12:0] Row n td(SDCLKL_AddC) th(SDCLKL_AddR)

Col1 Col2 Coli th(SDCLKL_AddC) td(SDCLKL_SNDE)

Coln th(SDCLKL_SNDE)

FMC_SDNE[1:0] td(SDCLKL_NRAS)

FMC_SDNRAS th(SDCLKL_NRAS) td(SDCLKL_NCAS) th(SDCLKL_NCAS)

FMC_SDNCAS

FMC_SDNWE

FMC_D[31:0] tsu(SDCLKH_Data)

Data1 th(SDCLKH_Data)

Data2 Datai Datan page 120/199

DS13196 - Rev 6

STM32H7B0xB

Operating conditions

Symbol t w(SDCLK) t su(SDCLKH _Data) t h(SDCLKH_Data) t d(SDCLKL_Add) t d(SDCLKL- SDNE) t h(SDCLKL_SDNE) t d(SDCLKL_SDNRAS) t h(SDCLKL_SDNRAS) t d(SDCLKL_SDNCAS) t h(SDCLKL_SDNCAS)

Parameter

FMC_SDCLK period

Data input setup time

Data input hold time

Address valid time

Chip select valid time

Chip select hold time

SDNRAS valid time

SDNRAS hold time

SDNCAS valid time

SDNCAS hold time

1. Guaranteed by characterization results.

2. At VOS1, these values are degraded by up to 5 %.

Table 83. SDRAM read timings

Min

(1)

2T fmc_ker_ck

– 1

3

0

-

-

0.5

-

0.5

-

0

Table 84. LPSDRAM read timings

Symbol t

W(SDCLK) t su(SDCLKH_Data) t h(SDCLKH_Data) t d(SDCLKL_Add) t d(SDCLKL_SDNE) t h(SDCLKL_SDNE) t d(SDCLKL_SDNRAS t h(SDCLKL_SDNRAS) t d(SDCLKL_SDNCAS) t h(SDCLKL_SDNCAS)

Parameter

FMC_SDCLK period

Data input setup time

Data input hold time

Address valid time

Chip select valid time

Chip select hold time

SDNRAS valid time

SDNRAS hold time

SDNCAS valid time

SDNCAS hold time

1. Guaranteed by characterization results.

2. At VOS1, these values are degraded by up to 5 %.

Min (1)

2T fmc_ker_ck

– 1

3

0.5

-

-

0

-

0

-

0

Max (1)(2)

2T fmc_ker_ck

+0.5

-

-

1.5

2

-

2

-

0.5

-

Unit ns

Max

(1)(2)

2T fmc_ker_ck

+0.5

-

-

3.5

2.5

-

1

-

1.5

-

Unit ns page 121/199

DS13196 - Rev 6

STM32H7B0xB

Operating conditions

Figure 39. SDRAM write access waveforms

FMC_SDCLK td(SDCLKL_AddR)

FMC_A[12:0]

FMC_SDNE[1:0] td(SDCLKL_NRAS)

FMC_SDNRAS

FMC_SDNCAS

FMC_SDNWE td(SDCLKL_Data)

FMC_D[31:0] td(SDCLKL_NBL)

FMC_NBL[3:0]

Row n td(SDCLKL_AddC) th(SDCLKL_AddR)

Col1 Col2 Coli th(SDCLKL_AddC) td(SDCLKL_SNDE)

Coln th(SDCLKL_SNDE) th(SDCLKL_NRAS) td(SDCLKL_NCAS) td(SDCLKL_NWE)

Data1 Data2 Datai th(SDCLKL_Data)

Datan th(SDCLKL_NCAS) th(SDCLKL_NWE)

Table 85. SDRAM Write timings

Symbol t w(SDCLK) t d(SDCLKL _Data

) t h(SDCLKL _Data) t d(SDCLKL_Add) t d(SDCLKL_SDNWE) t h(SDCLKL_SDNWE) t d(SDCLKL_ SDNE) t h(SDCLKL-_SDNE) t d(SDCLKL_SDNRAS) t h(SDCLKL_SDNRAS) t d(SDCLKL_SDNCAS) t d(SDCLKL_SDNCAS)

Parameter

FMC_SDCLK period

Data output valid time

Data output hold time

Address valid time

SDNWE valid time

SDNWE hold time

Chip select valid time

Chip select hold time

SDNRAS valid time

SDNRAS hold time

SDNCAS valid time

SDNCAS hold time

1. Guaranteed by characterization results.

Min

(1)

2T fmc_ker_ck

– 1

-

0

-

-

0.5

-

0.5

-

0.5

-

0.5

Max (1)(2)

2T fmc_ker_ck

+0.5

2.5

-

2

2.5

-

2

-

1.5

-

1.5

-

Unit ns page 122/199

6.3.19

Note:

STM32H7B0xB

Operating conditions

2. At VOS1, these values are degraded by up to 5 %.

Table 86. LPSDR SDRAM Write timings

Symbol t w(SDCLK) t d(SDCLKL _Data

) t h(SDCLKL _Data) t d(SDCLKL_Add) t d(SDCLKL-SDNWE) t h(SDCLKL-SDNWE) t d(SDCLKL- SDNE) t h(SDCLKL- SDNE) t d(SDCLKL-SDNRAS) t h(SDCLKL-SDNRAS) t d(SDCLKL-SDNCAS) t d(SDCLKL-SDNCAS)

Parameter

FMC_SDCLK period

Data output valid time

Data output hold time

Address valid time

SDNWE valid time

SDNWE hold time

Chip select valid time

Chip select hold time

SDNRAS valid time

SDNRAS hold time

SDNCAS valid time

SDNCAS hold time

1. Guaranteed by characterization results.

2. At VOS1, these values are degraded by up to 5 %.

Min

(1)

2T fmc_ker_ck

– 1

-

0

-

0

-

0

-

0

-

0

-

Max

(1)(2)

2T fmc_ker_ck

+0.5

2.5

-

2.5

-

2

-

2

-

3

-

3

•

•

•

•

•

Octo-SPI interface characteristics

Unless otherwise specified, the parameters given in

Table 87. OCTOSPI characteristics in SDR mode

and

Table 88. OCTOSPI characteristics in DTR mode (with DQS)/Octal and Hyperbus for the OCTOSPI interface

are derived from tests performed under the ambient temperature, f

HCLK

frequency and V

DD

supply voltage

summarized in Table 20. General operating conditions , with the following configuration:

Output speed is set to OSPEEDRy[1:0] = 11

Measurement points are done at CMOS levels: 0.5V

DD

I/O compensation cell activated.

HSLV activated when V

DD

≤ 2.7 V

VOS level set to VOS0

At VOS1, the performance can be degraded by up to 5 % compared to VOS0. This is indicated by a footnote when applicable.

Refer to

Section 6.3.16 I/O port characteristics

for more details on the input/output alternate function characteristics.

Unit ns

Delay block bypassed.

Symbol Parameter

F

(CLK)

OCTOSPI clock frequency t w(CLKH) t w(CLKL)

OCTOSPI clock high and low time

Table 87. OCTOSPI characteristics in SDR mode

Conditions

1.62 V < V

DD

< 3.6 V, VOS0,

C

LOAD

= 15 pF

1.62 V < V

DD

< 3.6 V, VOS0,

C

LOAD

= 20 pF

2.7 V < V

DD

< 3.6 V, VOS0,

C

LOAD

= 20 pF

PRESCALER[7:0] = n = 0,1,3,5

Min

(1)(2)

-

-

t

(CLK)

/2 t

(CLK)

/2−1

Typ (1)(2)

-

Max (1)(2)(3)

90

Unit

-

-

-

80

140 t

(CLK)

/2+1 t

(CLK)

/2

MHz ns

DS13196 - Rev 6 page 123/199

DS13196 - Rev 6

STM32H7B0xB

Operating conditions

Symbol Parameter Conditions Min

(1)(2)

t t w(CLKH) w(CLKL)

OCTOSPI clock high and low time

PRESCALER[7:0] = n = 2,4,6,8

(n/2)*t

(CLK)

/

(n+1)

(n/2+1)*t

(CLK)

/

(n+1) −1 t t s(IN)

(4) h(IN) (4)

t v(OUT) t h(OUT)

Data input setup time

Data input hold time

Data output valid time

Data output hold time

2.7 V < V

DD

< 3.6 V

1.62 V < V

DD

< 3.6 V

2.7 V < V

DD

< 3.6 V

1.62 V < V

DD

< 3.6 V

-

-

2

2

4.5

5

-

0

1. All values apply to Octal and Quad-SPI mode.

2. Guaranteed by characterization results.

3. At VOS1, these values are degraded by up to 5 %.

4. Using PC2, PC3 PI11, PF0 or PF1 I/O in the data bus adds 3.5 ns to this timing value.

-

-

-

-

1

-

Typ (1)(2)

-

-

Max (1)(2)(3)

(n/2)*t

(CLK)

/

(n+1)+1

(n/2+1)*t

(CLK)

/

(n+1)

-

-

-

-

1.5

(4)

-

Unit ns t r(CLK)

Figure 40. OctoSPI timing diagram - SDR mode t

(CLK) t w(CLKH) t w(CLKL) t f(CLK)

Clock

Data output t v(OUT)

D0 t h(OUT)

D2

Data input

D0 t s(IN)

D1 t h(IN)

D1 D2

Symbol

F

(CLK)

(3)(4)

t w(CLKH) t w(CLKL) t w(CLKH) t w(CLKL) t v(CLK) t h(CLK)

Table 88. OCTOSPI characteristics in DTR mode (with DQS)/Octal and Hyperbus

Parameter

OCTOSPI clock frequency

Conditions

1.71 V < V

C

DD

< 3.6 V, VOS0,

LOAD

= 15 pF

2.7 V < V

DD

< 3.6 V, VOS0,

C

LOAD

= 20 pF

1.62 V < V

C

DD

< 2.5 V, VOS0,

LOAD

= 20 pF

Min

(1)

-

-

-

Typ (1)

-

-

-

Max (1)(2)

120

(5)

100

100/45

(6)

OCTOSPI clock high and low time

OCTOSPI clock high and low time

Clock valid time

Clock hold time

PRESCALER[7:0] = n = 0,1,3,5

PRESCALER[7:0] = n = 2,4,6,8

-

t

(CLK)

/2 t

(CLK)

/2−1

(n/2)*t

(CLK)

/

(n+1)

(n/2+1)*t

(CLK)

/

(n+1)−1

t

(CLK)

/2−0.5

t

(CLK)

/2

-

-

-

-

-

t

(CLK)

/2+1 t

(CLK)

/2

(n/2)*t

(CLK)

/

(n+1)+1

(n/2+1)*t

(CLK)

/

(n+1) t

(CLK)

+1

-

Unit

MHz ns page 124/199

DS13196 - Rev 6

STM32H7B0xB

Operating conditions t

Symbol t t t w(CS) t v(DQ) v(DS) h(DS) v(RWDS)

Parameter

Chip select high time

Data input vallid time

Data strobe input valid time

Data strobe input hold time

Data strobe output valid time

Conditions

-

-

-

-

-

Min

0

0

0

-

(1)

3 x t

(CLK)

Typ

-

-

-

-

-

(1)

t t sr(DQ) t sf(DQ)

(7)

t hr(DQ) t t hf(DQ)

(7)

vr(OUT) vf(OUT)

Data input setup time

Data input hold time

Data output valid time

-

Rising edge

Falling edge

DHQC = 0

DHQC = 1, PRESCALER[7:0]=1,2...

−1

3

3.5

-

t t hr(OUT) hf(OUT)

Data output hold time

DHQC = 0

DHQC = 1, PRESCALER[7:0]=1,2...

4.5

t

(CLK)

/4

1. Guaranteed by characterization results, unless otherwise specified.

2. At VOS1, these values are degraded by up to 5 %.

3. The maximum frequency values are given for a maximum RWDS to DQ skew ≤ ±1.0 ns.

4. DHQC must be set to reach the mentioned frequency.

5. Guaranteed by design.

6. Using PC2, PC3, PI11, PF0 or PF1 I/Os limits the maximum clock frequency.

7. Delay block bypassed.

8. Using PC2, PC3, PI11, PF0 or PF1 I/O in the data bus adds 3.5 ns to this timing value.

-

-

-

5.5

t

(CLK)

/4+

1

-

-

Max

3 x t

-

-

-

-

-

(1)(2)

(CLK)

-

-

7

(8)

t

(CLK)

/4+2

(8)

-

-

Unit ns t r(CLK)

Figure 41. OctoSPI timing diagram - DTR mode t

(CLK) t w(CLKH) t w(CLKL) t f(CLK)

Clock

Data output

Data input t vf(OUT) t hr(OUT)

D0

D0

D1 t sf(IN) t hf(IN)

D1

D2 t vr(OUT) t hf(OUT)

D2

D3

D3

D4 t sr(IN) t hr(IN)

D4

D5

D5 page 125/199

STM32H7B0xB

Operating conditions

NCLK

CLK t r(CLK) t f(NCLK)

Figure 42. OctoSPI Hyperbus clock t

(CLK) t

(NCLK) t w(CLKH) t w(CLKL) t w(NCLKL) t w(NCLKH) t f(CLK) t r(NCLK)

V

OD(CLK)

6.3.20

Figure 43. OctoSPI Hyperbus read t w(CS)

NCS t v(CLK) t h(CLK)

CLK, NCLK t v(RWDS) t v(DS) t h(DS)

RWDS

DQ[7:0] t v(OUT) t h(OUT)

47:40 39:32 31:24 23:16 15:8 7:0

Latency count

Command address

Host drives DQ[7:0] and the memory drives RWDS.

t v(DQ) t s(DQ) t h(DQ)

Dn

A

Dn

B

Dn+1

A

Dn+1

B

Memory drives DQ[7:0] and RWDS.

Figure 44. OctoSPI Hyperbus write t w(CS)

NCS

Read write recovery t v(CLK)

Access latency t h(CLK)

CLK, NCLK

RWDS

DQ[7:0] t v(RWDS) High = 2x latency count

Low = 1x latency count

Latency count t v(OUT) t h(OUT)

47:40 39:32 31:24 23:16 15:8 7:0

Command address

Host drives DQ[7:0] and the memory drives RWDS.

t v(OUT) t h(OUT) t v(OUT) t h(OUT)

Dn

A

Dn

B

Dn+1

A

Dn+1

B

Host drives DQ[7:0] and RWDS.

Delay block (DLYB) characteristics

Unless otherwise specified, the parameters given in

Table 89. Delay Block characteristics for Delay Block are

derived from tests performed under the ambient temperature, f rcc_cpu_ck

frequency and VDD supply voltage

summarized in Table 20. General operating conditions , with the following configuration:

DS13196 - Rev 6 page 126/199

STM32H7B0xB

Operating conditions

6.3.21

Symbol t init t

∆

Parameter

Initial delay

Unit Delay

Table 89. Delay Block characteristics

Conditions

-

-

Min

1400

40

Typ

1700

47

Max

2700

59

Unit ps

16-bit ADC characteristics

Unless otherwise specified, the parameters given in

Table 90. ADC characteristics

are derived from tests performed under the ambient temperature, f

PCLK2 frequency and V

DDA

supply voltage conditions summarized

in Table 20. General operating conditions

.

Symbol

V

DDA

V

REF+

(2)

V

REF-

(2)

f

ADC f

S

(3)

Table 90. ADC characteristics

Parameter

Analog power supply for ADC ON

Conditions

-

Positive reference voltage

V

DDA

≥ 2 V

V

DDA

< 2 V

Negative reference voltage

-

ADC clock frequency

Sampling rate for

Direct channels

Sampling rate for Fast channels

1,62 V ≤V

DDA

≤ 3.6 V

BOOST =

11

BOOST =

10

BOOST =

01

BOOST =

00

Resolution = 16 bits,

V

DDA

> 2.5 V

Resolution = 16 bits

Resolution = 14 bits

Resolution = 12 bits

Resolution = 10 bits

Resolution = 8 bits

Resolution = 16 bits, V

DDA

>2.5V

Resolution = 16 bits

Resolution = 14 bits

Resolution = 12 bits

Resolution = 10 bits

T

T

J

J

=

90 °C

=

125 °C

T

J

= 90 °C

TJ =

125°C f

ADC

= 36 MHz SMP = 1.5

f

ADC

= 37 MHz SMP = 2.5

f

ADC

= 50 MHz SMP = 2.5

f f f f f f f f

ADC

ADC

ADC

ADC

ADC

ADC

ADC

ADC

=50 MHz

=50 MHz

=50 MHz

=32 MHz

=31 MHz

=33 MHz

=39 MHz

=48 MHz

SMP = 2.5

SMP=1.5

SMP=1.5

SMP=2.5

SMP=2.5

SMP=2.5

SMP=2.5

SMP=2.5

Min

(1) Typ (1) Max (1)

1.62

1.62

-

-

V

DDA

V

SSA

3.6

V

DDA

0.12

0.12

0.12

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

50

25

12.5

6.25

3.60

3.35

5.00

5.50

7.10

8.30

2.90

2.80

3.30

4.30

6.00

Unit

V

MHz

MSPS

DS13196 - Rev 6 page 127/199

STM32H7B0xB

Operating conditions

I t

V f

S

(3)

TRIG

AIN

(4)

CMIV

AIN

(5)

C

ADC t

ADCVREG_

STUP t

STAB

ADC LDO startup time t t

Symbol

V

R t

CAL

OFF_CAL t

LATR

LATRINJ t t

S

CONV

DDA_D(ADC)

Parameter

Sampling rate for Fast channels

Sampling rate for

Slow channels,

BOOST = 00, f

ADC

10 MHz

=

External trigger period

Conversion voltage range

Common mode input voltage

Resolution = 8 bits

Resolution = 16 bits

Resolution = 14 bits

Resolution = 12 bits

Resolution = 10 bits

Resolution = 8 bits

TJ =

125°C

T

J

= 90 °C

T

J

Conditions

=

125 °C f f

ADC

ADC

=50 MHz SMP=2.5

=10 MHz SMP=1.5

Resolution = 16 bits

-

-

External input impedance

Resolution = 16 bits, T

J

= 125 °C

Resolution = 14 bits, T

J

= 125 °C

Resolution = 12 bits, TJ

J

= 125 °C

Resolution = 10 bits, T

J

= 125 °C

Resolution = 8 bits, T

J

= 125 °C

Internal sample and hold capacitor

-

Min

-

-

-

-

-

-

-

-

(1) Typ

-

-

-

-

-

-

-

4

(1) Max

7.10

1.00

10

-

(1)

0 V

REF+

V

REF

/2

− 10%

-

-

-

-

-

V

REF

/

2

-

-

-

-

-

V

REF

/2

+ 10%

170

435

1150

5650

26500

ADC power-up time

Offset and linearity calibration time

Offset calibration time

Trigger conversion latency for regular and injected channels without aborting the conversion

Trigger conversion latency for regular and injected channels when a regular conversion is aborted

Sampling time

Total conversion time

(including sampling time)

ADC consumption on

V

DDA

, BOOST=11,

Differential mode

-

LDO already started

-

-

CKMODE = 00

CKMODE = 01

CKMODE = 10

CKMODE = 11

CKMODE = 00

CKMODE = 01

CKMODE = 10

CKMODE = 11

-

N-bits resolution

Resolution = 16 bits, f

Resolution = 14 bits, f

Resolution = 12 bits, f

ADC

ADC

ADC

=25 MHz

=30 MHz

=40 MHz

-

1

1.5

tS +

0.5 +

N/2

-

1.5

-

-

-

2.5

-

-

-

-

-

5

-

165010

10

1280

2

-

-

-

3

-

-

-

-

2.5

2.5

2.5

2.25

3.5

3.5

3.5

3.25

810.5

-

1440

1350

990

-

-

-

-

-

Unit

MSPS

1/f

ADC

V

µs conversion cycle

1/f

V

Ω pF

ADC

µA

DS13196 - Rev 6 page 128/199

STM32H7B0xB

Operating conditions

I

I

Symbol

DDA_D(ADC)

DDA_SE(ADC)

I

DD(ADC)

Single-ended mode

ADC consumption on

V

Parameter

ADC consumption on

V

DDA

, BOOST=10,

Differential mode f

ADC

=25 MHz

ADC consumption on

V

DDA

, BOOST=01,

Differential mode f

ADC

=12.5 MHz

ADC consumption on

V

DDA

, BOOST=00,

Differential mode f

ADC

=6.25 MHz

ADC consumption on

V

DDA

, BOOST=11,

Single-ended mode

ADC consumption on

V

DDA f

ADC

DDA

, BOOST=10,

=25 MHz

, BOOST=01,

Single-ended mode f

ADC

=12.5 MHz

ADC consumption on

V

DDA

, BOOST=00,

Single-ended mode f

ADC

=6.25 MHz

ADC consumption on

V

DD

Conditions

Resolution = 16 bits

Resolution = 14 bits

Resolution = 12 bits

Resolution = 16 bits

Resolution = 14 bits

Resolution = 12 bits

Resolution = 16 bits

Resolution = 14 bits

Resolution = 12 bits

Resolution = 16 bits, f

ADC

=25 MHz

Resolution = 14 bits, f

ADC

=30 MHz

Resolution = 12 bits, f

ADC

=40 MHz

Resolution = 16 bits

Resolution = 14 bits

Resolution = 12 bits

Resolution = 16 bits

Resolution = 14 bits

Resolution = 12 bits

Resolution = 16 bits

Resolution = 14 bits

Resolution = 12 bits f

ADC

=50 MHz f

ADC

=25 MHz f

ADC

=12.5 MHz f

ADC

=6.25 MHz f

ADC

=3.125 MHz

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

1. Guaranteed by design.

2. Depending on the package, V

REF+

can be internally connected to V

DDA

and V

REF-

to V

SSA

.

3. These values are valid UFBGA176+25 and one ADC. The values for other packages and multiple ADCs might be different

4. The voltage booster on ADC switches must be used for V

DDA

< 2.4 V (embedded I/O switches).

5. The tolerance is 10 LSBs for 16-bit resolution, 4 LSBs for 14-bit resolution, and 2 LSBs for 12-bit, 10-bit and

8-bit resolutions.

Min

(1) Typ (1) Max (1)

-

-

-

-

-

-

-

-

-

-

1080

810

585

630

432

315

360

270

225

720 -

-

-

-

-

-

-

-

-

-

675

495

540

405

292.5

315

216

157.5

180

135

112.5

400

220

180

120

80

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Table 91. Minimum sampling time vs R

AIN

Data valid up to 130 °C, with a 47 pF PCB capacitor and V

DDA

=1.6 V.

Minimum sampling time (s)

Resolution RAIN (Ω)

Direct channels (1)(2)

Fast channels

(1)(3)

16 bits

14 bits

47

47

68

100

7.37E-08

6.29E-08

6.84E-08

7.80E-08

1.14E-07

9.74E-08

1.02E-07

1.12E-07

Unit

µA

µA

Slow channels

(1)(4)

1.72E-07

1.55E-07

1.58E-07

1.62E-07

DS13196 - Rev 6 page 129/199

STM32H7B0xB

Operating conditions

Resolution RAIN (Ω)

14 bits

12 bits

10 bits

8 bits

680

1000

1500

2200

3300

100

150

220

330

470

330

470

680

47

68

150

220

47

68

100

150

220

330

470

680

1000

1500

2200

3300

4700

6800

10000

15000

47

68

100

150

220

Direct channels (1)(2)

9.86E-08

1.32E-07

5.32E-08

5.74E-08

6.58E-08

8.37E-08

1.11E-07

1.56E-07

2.16E-07

3.01E-07

4.34E-08

4.68E-08

5.35E-08

6.68E-08

8.80E-08

1.24E-07

1.69E-07

2.38E-07

3.45E-07

5.15E-07

7.42E-07

1.10E-06

3.32E-08

3.59E-08

4.10E-08

5.06E-08

6.61E-08

9.17E-08

1.24E-07

1.74E-07

2.53E-07

3.73E-07

5.39E-07

8.02E-07

1.13E-06

1.62E-06

2.36E-06

3.50E-06

1. Guaranteed by design.

2. Direct channels are connected to analog I/Os (PA0_C, PA1_C, PC2_C and PC3_C) to optimize ADC performance.

2.60E-07

3.66E-07

5.35E-07

7.75E-07

1.14E-06

5.10E-08

5.35E-08

5.83E-08

6.76E-08

8.22E-08

1.08E-07

1.40E-07

1.91E-07

2.70E-07

3.93E-07

5.67E-07

8.36E-07

1.18E-06

1.69E-06

2.47E-06

3.69E-06

Minimum sampling time (s)

Fast channels

(1)(3)

1.32E-07

1.61E-07

8.00E-08

8.50E-08

9.31E-08

1.10E-07

1.34E-07

1.78E-07

2.39E-07

3.29E-07

6.51E-08

6.89E-08

7.55E-08

8.77E-08

1.08E-07

1.43E-07

1.89E-07

2.80E-07

3.84E-07

5.48E-07

7.78E-07

1.14E-06

8.61E-08

8.83E-08

9.22E-08

9.95E-08

1.11E-07

1.32E-07

1.63E-07

2.12E-07

2.85E-07

4.05E-07

5.75E-07

8.38E-07

1.18E-06

1.68E-06

2.45E-06

3.65E-06

Slow channels

(1)(4)

1.80E-07

2.01E-07

1.29E-07

1.32E-07

1.40E-07

1.51E-07

1.73E-07

2.14E-07

2.68E-07

3.54E-07

1.08E-07

1.11E-07

1.16E-07

1.26E-07

1.40E-07

1.71E-07

2.13E-07

DS13196 - Rev 6 page 130/199

STM32H7B0xB

Operating conditions

3. Fast channels correspond for ADCx_INPx to PA6, PB1, PC4, PF11, PF13 and for ADCx_INNx to PA7, PB0,

PC5, PF12, PF14

4. Slow channels correspond to all ADC inputs except for the Direct and Fast channels.

Figure 45. ADC conversion timing diagram

CLK

Mux Sampling (1)

1/2 SMP

15 14 13 12 11 10 9 8 7 6

Number of CLK clock cycles = ADC resolution / 2

5

Total conversion time: 0.5 +Tsamp + N/2

4 3 2 1 0

1. The sampling time defines the minimum sampling clock cycles (SMP) to be programmed in the ADC (refer to the product reference manual for details).

Table 92. ADC accuracy

Data guaranteed by characterization for BGA packages. The values for LQFP packages might differ. ADC DC accuracy values are measured after internal calibration.

Symbol Parameter

Conditions (1)

Min Typ Max Unit

ET

EO

EG

ED

EL

ENOB

SINAD

SNR

THD

Total undadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error

Effective number of bits

Signal-to-noise and distortion ratio

Signal-to-noise ratio

Total harmonic distortion

Direct channel

Fast channel

Slow channel

Single ended

Differential

Single ended

Differential

Single ended

Differential

-

-

Single ended

Differential

Direct channel

Fast channel

Slow channel

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

Differential

Single ended

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

LSB

Bits dB

±15

+3/–1

+4.5/–1

±11

±7

±13

±7

±10

±6

+10/–20

±15

+10/–20

±15

±10

±10

±10

12.2

13.2

75.2

81.2

77.0

81.0

87

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

DS13196 - Rev 6 page 131/199

STM32H7B0xB

Operating conditions

Symbol

THD

Parameter

Total harmonic distortion

Conditions (1)

Differential

1. ADC clock frequency = 25 MHz, ADC resolution = 16 bits, V

DDA

=V

REF+

=3.3 V and BOOST=11.

Note:

Min

-

Typ

90

Max Unit

dB

ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input.

It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

Any positive injection current within the limits specified for I

INJ(PIN)

and ΣI

INJ(PIN)

injection characteristics

does not affect the ADC accuracy.

in

Section 6.3.15 I/O current

Output code

2 n -1

2 n -2

2 n -3

5

4

3

2

1

7

6

0

V

SSA

E

O

Figure 46. ADC accuracy characteristics

[1LSB =

V

REF+

2 n

V

DDA

(or )]

2 n

E

G

E

T

E

L

E

D

1 LSB ideal

(2)

(3)

(1)

(1) Example of an actual transfer curve

(2) Ideal transfer curve

(3) End-point correlation line n = ADC resolution

E

T

= total unadjusted error: maximum deviation between the actual and ideal transfer curves

E

O

= offset error: maximum deviation between the first actual transition and the first ideal one

E

G

= gain error: deviation between the last ideal transition and the last actual one

E

D

= differential linearity error: maximum deviation between actual steps and the ideal one

E

L

= integral linearity error: maximum deviation between any actual transition and the end point correlation line

V

REF+

(V

DDA

)

1.

Example of an actual transfer curve.

2.

Ideal transfer curve.

3.

End point correlation line.

4.

E

T

= Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.

5.

EO = Offset Error: deviation between the first actual transition and the first ideal one.

6.

EG = Gain Error: deviation between the last ideal transition and the last actual one.

7.

ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.

8.

EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.

DS13196 - Rev 6 page 132/199

DS13196 - Rev 6

STM32H7B0xB

Operating conditions

Figure 47. Typical connection diagram using the ADC

V

AIN

R

AIN

(1)

C

AINx parasitic

V

DD

V

T

0.6 V

V

T

0.6 V

I

L

± 250 nA

Sample and hold ADC converter

R

ADC

(1)

ADC converter

STM32

C

ADC

(1)

1.

Refer to Table 90. ADC characteristics for the values of R

AIN

, R

ADC

and C

ADC

.

2.

C parasitic

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high C parasitic

value downgrades conversion accuracy. To remedy this, f

ADC

should be reduced.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 48. Power supply and reference decoupling

(V

REF+ not connected to V

depending on whether V

DDA

REF+

)

or

Figure 49. Power supply and reference decoupling (V

REF+

is connected to V

DDA

connected to V

or not. The 100 nF capacitors should be ceramic (good

DDA

) ,

quality). They should be placed them as close as possible to the chip.

Figure 48. Power supply and reference decoupling (V

REF+ not connected to V

DDA

)

STM32

V

REF+

(1)

1 µF // 100 nF

1 µF // 100 nF

V

DDA

V

SSA

/V

REF-

(1) page 133/199

STM32H7B0xB

Operating conditions

1.

V

REF+

input is not available on all package (refer to Table 1. STM32H7B0xB features and peripheral counts

) whereas V

REF– is available only on UFBGA176+25, TFBGA225 with SMPS and TFBGA216. When V

REF- is not available, it is internally connected to V

SSA

.

Figure 49. Power supply and reference decoupling (V

REF+ connected to V

DDA

)

STM32

V

REF+

/V

DDA

(1)

1 µF // 100 nF

V

REF-

/V

SSA

(1)

6.3.22

1.

V

REF+

input is not available on all package (refer to Table 1. STM32H7B0xB features and peripheral counts

) whereas V

REF– is available only on UFBGA176+25, TFBGA225 with SMPS and TFBGA216. When V

REF- is not available, it is internally connected to V

SSA

.

DAC characteristics

Symbol

V

DDA

V

REF+

V

REF-

R

L

R

O

R

BON

R

BOFF

C

L

C

SH

Parameter

Analog supply voltage

Positive reference voltage

Negative reference voltage

Resistive Load

Output Impedance

Output impedance sample and hold mode, output buffer ON

Output impedance sample and hold mode, output buffer OFF

Capacitive Load

Table 93. DAC characteristics

Conditions

-

-

-

DAC output buffer ON connected to V

SSA connected to V

DDA

DAC output buffer OFF

DAC output buffer ON

DAC output buffer OFF

V

DD

= 2.7 V

V

DD

= 2.0 V

V

DD

= 2.7 V

V

DD

= 2.0 V

DAC output buffer OFF

Sample and Hold mode

10.3

-

-

-

-

-

-

Min

(1)

1.8

1.80

-

5

25 -

13

-

-

-

Typ (1)

3.3

-

V

SSA

-

-

-

0.1

Max

(1)

3.6

V

DDA

-

-

-

16

1.6

2.6

17.8

18.7

50

1

Unit

V kΩ kΩ kΩ pF

µF

DS13196 - Rev 6 page 134/199

STM32H7B0xB

Operating conditions

Symbol Parameter Conditions Min

(1) Typ (1)

DAC output buffer ON

V

DAC_OUT

Voltage on DAC_OUT output t

I

SETTLING

Settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes when

DAC_OUT reaches the final value of ±0.5LSB, ±1LSB, ±2LSB, ±4LSB,

C

L

±8LSB) t

WAKEUP

(2)

Wakeup time from off state (setting the

ENx bit in the DAC Control register) until the final value of ±1LSB is reached

PSRR t

V

I

SAMP leak

C

Iint t

TRIM offset

DDA(DAC)

DC V

DDA

supply rejection ratio

Sampling time in Sample and Hold mode

=100 nF

(code transition between the lowest input code and the highest input code when DAC_OUT reaches the ±1LSB final value)

Output leakage current

Internal sample and hold capacitor

Middle code offset trim time

Middle code offset for 1 trim code step

DAC quiescent consumption from V

DDA

DAC output buffer OFF

C

Normal mode, DAC

L output buffer ON,

≤ 50 pF, R

L

≥ 5 kΩ

±0.5 LSB

±1 LSB

±2 LSB

±4 LSB

±8 LSB

Normal mode, DAC output buffer OFF, ±1LSB

C

L

=10 pF

Normal mode, DAC output buffer ON,

C

L

≤ 50 pF, R

L

= 5 kΩ

Normal mode, DAC output buffer OFF,

C

L

≤ 10 pF

Normal mode, DAC output buffer ON,

C

L

≤ 50 pF, R

L

= 5 kΩ

MODE<2:0>_V12=100/101

(BUFFER ON)

MODE<2:0>_V12=110

(BUFFER OFF)

MODE<2:0>_V12=111

(INTERNAL BUFFER OFF)

-

-

Minimum time to verify the each code

V

REF+

= 3.6 V

V

REF+

= 1.8 V

DAC output buffer ON

DAC output buffer OFF

No load, middle code

(0x800)

No load, worst code

(0xF1C)

No load, middle/worst code (0x800)

0.2

-

-

-

-

-

-

-

-

-

-

-

1.8

50

-

-

0

-

-

-

-

-

Sample and Hold mode, C

SH

=100 nF

I

DDV(DAC)

DAC consumption from V

REF+

1. Guaranteed by design, unless otherwise specified.

DAC output buffer ON

DAC output buffer OFF

No load, middle code

(0x800)

No load, worst code

(0xF1C)

No load, middle/worst code (0x800)

Sample and Hold mode, Buffer ON, C

SH

=100 nF

(worst code)

Sample and Hold mode, Buffer OFF,

C

SH

=100 nF (worst code)

-

-

-

-

-

-

-

-

2.05

1.97

1.67

1.66

1.65

1.7

5

2

−80

0.7

11.5

0.3

-

2.2

-

850

425

360

490

20

360*T

ON

/

(T

ON

+T

OFF

)

(4)

170

170

160

170*T

ON

/

(T

ON

+T

OFF

)

(4)

160*T

ON

/

(T

ON

+T

OFF

)

(4)

(3)

Max

(1)

Unit

V

DDA

−0.2

V

REF+

-

-

-

-

-

V

µs

2

7.5

5

−28

2.6

18.7

0.6

2.6

-

-

-

-

-

-

-

-

-

-

-

-

µs dB ms

µs nA pF

µs

µV

µA

DS13196 - Rev 6 page 135/199

STM32H7B0xB

Operating conditions

2. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).

3. Refer to Table 63. I/O static characteristics .

4. T

ON

is the refresh phase duration, while T manual for more details.

OFF

is the hold phase duration. Refer to the product reference

Table 94. DAC accuracy

Symbol Parameter Conditions

DNL

INL

Offset

Offset1

OffsetCal

Gain

TUE

Differential non linearity

Integral non linearity

Offset error at code 0x800 after factory calibration

Gain error (5)

(3)

Total undajusted error

(2)

Offset error at code 0x800

Offset error at code 0x001

(3)

(4)

DAC output buffer ON

DAC output buffer OFF

DAC output buffer ON, C

L

≤ 50 pF, R

L

≥ 5 kΩ

DAC output buffer OFF, C

L

≤ 50 pF, no R

L

DAC output buffer ON, C

DAC output buffer ON, C

L

L

≤ 50 pF, R

≤ 50 pF, R

L

L

≥ 5 kΩ

≥ 5 kΩ

V

REF+

= 3.6 V

V

REF+

= 1.8 V

DAC output buffer OFF, C

L

≤ 50 pF, no R

L

DAC output buffer OFF, C

L

≤ 50 pF, no R

L

-

V

REF+

= 3.6 V

VR

EF+

= 1.8 V

DAC output buffer ON,C

L

≤ 50 pF, R

L

≥ 5 kΩ

DAC output buffer OFF, C

L

≤ 50 pF, no R

L

DAC output buffer ON,C

L

≤ 50 pF, R

L

≥ 5 kΩ

DAC output buffer OFF, C

L

≤ 50 pF, no R

L

TUECal

Total undajusted error after calibration

DAC output buffer ON C

L

≤ 50pF, R

L

≥ 5kΩ

SNR

THD

Signal-to-noise ratio

(6)

Total harmonic distorsion

(6)

SINAD Signal-to-noise and distorsion ratio

(6)

ENOB Effective number of bits

DAC output buffer ON C

L

≤ 50pF, R

L

≥ 5kΩ 1 kHz, BW 500KHz

DAC output buffer OFF C

L

≤ 50pF, no R

L

1kHz, BW 500KHz

DAC output buffer ON C

L

≤ 50pF, R

L

≥ 5kΩ, 1 kHz

DAC output buffer OFF C

L

≤ 50pF, no R

L

, 1 kHz

DAC output buffer ON C

L

≤ 50pF, R

L

≥ 5kΩ, 1 kHz

DAC output buffer OFF C

L

≤ 50pF, no R

L

, 1 kHz

DAC output buffer ON C

L

≤ 50pF, R

L

≥ 5kΩ, 1 kHz

DAC output buffer OFF C

L

≤ 50pF, no R

L

, 1 kHz

1. Guaranteed by design, unless otherwise specified.

2. Difference between two consecutive codes minus 1 LSB.

3. Difference between the value measured at Code i and the value measured at Code i on a line drawn between Code 0 and last Code 4095.

4. Difference between the value measured at Code (0x001) and the ideal value.

5. Difference between the ideal slope of the transfer function and the measured slope computed from code

0x000 and 0xFFF when the buffer is OFF, and from code giving 0.2 V and (V

REF+

− 0.2 V) when the buffer is ON.

6. Signal is −0.5dBFS with Fsampling = 1 MHz.

Min (1) Typ (1) Max (1)

Unit

−2

−2

−4

−4

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

67.8

67.8

−78,6

−78,6

67.5

67.5

10.9

10.9

2

2

4

4

±12

±25

±8

±1

±1

-

-

-

-

LSB

LSB

LSB

±5 LSB

±5

±7

±30

±12

±23

-

-

-

-

LSB

%

LSB

LSB dB dB dB dB

DS13196 - Rev 6 page 136/199

STM32H7B0xB

Operating conditions

Figure 50. 12-bit buffered /non-buffered DAC

Buffered/Non-buffered DAC

Buffer(1)

12-bit digital to analog converter

DAC_OUTx

R L

C L

6.3.23

1.

The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.

Voltage reference buffer characteristics

Symbol

V

DDA

TRIM

C

L esr

Parameter

Analog supply voltage

V

REFBUF_OUT

Voltage Reference Buffer

Output

Trim step resolution

Load capacitor

Equivalent Serial Resistor of

C

L

Table 95. VREFBUF characteristics

-

-

Conditions

Normal mode

Degraded mode

Normal mode at 30°C,

I

LOAD

=100 µA

Degraded mode

(2)

(2)

VSCALE = 000

VSCALE = 001

VSCALE = 010

VSCALE = 011

VSCALE = 000

VSCALE = 001

VSCALE = 010

VSCALE = 011

VSCALE = 000

VSCALE = 001

VSCALE = 010

VSCALE = 011

VSCALE = 000

VSCALE = 001

VSCALE = 010

VSCALE = 011

-

-

Min (1)

2.8

2.4

2.1

1.8

1.62

1.62

1.62

1.62

2.496

(3)

2,0460

1,8010

1,4995

VDDA− 150 mV

VDDA− 150 mV

VDDA− 150 mV

VDDA− 150 mV

-

0.5

Typ (1)

-

-

3.3

-

-

-

-

-

2.5000

2.0490

1.8040

1.5015

-

-

-

-

±0.05

1

-

Max

(1)

3.6

3.6

3.6

3.6

2.80

2.40

2.10

1.80

2.504

(3)

2,0520

1,8060

1,5040

VDDA

VDDA

VDDA

VDDA

±0.1

1.50

2

Unit

V

% uF

Ω

DS13196 - Rev 6 page 137/199

STM32H7B0xB

Operating conditions

I

Symbol

I

I

LOAD line_reg

LOAD_reg

T coeff

Parameter

Static load current

Line regulation

Load regulation

Temperature coefficient

2.8 V ≤ V

500 µA ≤ I

−40 °C < T

-

DDA

J

Conditions

≤ 3.6 V

LOAD

≤ 4 mA

< +130 °C

-

I

LOAD

= 500 µA

I

LOAD

= 4 mA

Normal Mode

-

Min

-

-

-

-

-

(1)

t

PSRR

START

Power supply rejection

Startup time

DC

100KHz

C

L

=0.5 µF

C

L

=1 µF

C

L

=1.5 µF

-

-

-

-

-

-

-

-

-

-

60

40

300

500

650

I

INRUSH

Control of maximum

DC current drive on

V

REFBUF_OUT

during startup

phase (4)

8

I

DDA(VREFBUF)

V

REFBUF

consumption from

V

DDA

I

LOAD

= 0 µA

I

LOAD

= 500 µA

I

LOAD

= 4 mA

-

-

-

-

-

-

1. Guaranteed by design, unless otherwise specified.

2. In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (V

DDA

−drop voltage).

3. Guaranteed by tests in production.

4. To properly control VREFBUF I

INRUSH

current during the startup phase and the change of scaling, VDDA voltage should be in the range of 1.8 V-3.6 V, 2.1 V-3.6 V, 2.4 V-3.6 V and 2.8 V-3.6 V for VSCALE = 011,

010, 001 and 000, respectively.

15

16

32

Typ (1)

-

200

100

50

-

Max

(1)

4

-

-

-

Tcoeff

VREFINT +

100

-

-

-

-

-

Unit mA ppm/V ppm/ mA ppm/ °C dB

µs

-

25

30

50 mA

µA

6.3.24

Analog temperature sensor characteristics

Table 96. Analog temperature sensor characteristics

Symbol

T

L

(1)

Avg_Slope

(2)

Parameter

V

SENSE

linearity with temperature (from V

SENSOR

voltage)

V

SENSE

linearity with temperature (from ADC counter)

Average slope (from V

SENSOR

voltage)

Average slope (from ADC counter)

Voltage at 30°C ± 5 °C

Min

-

-

-

-

V

30

(3)

t start_run

(1)

t

S_temp

(1)

I sens

(1)

I sensbuf

(1)

Startup time in Run mode (buffer startup)

ADC sampling time when reading the temperature

Sensor consumption

Sensor buffer consumption -

-

-

-

9

1. Guaranteed by design.

2. Guaranteed by characterization results.

3. Measured at V

DDA

= 3.3 V ± 10 mV. The V

30

ADC conversion result is stored in the TS_CAL1 byte.

Typ

-

-

2

2

0.62

-

-

0.18

3.8

Max

3

3

-

-

-

25.2

-

0.31

6.5

Unit

°C mV/°C

V

µs

µA

DS13196 - Rev 6 page 138/199

6.3.25

6.3.26

STM32H7B0xB

Operating conditions

Table 97. Analog temperature sensor calibration values

Symbol Parameter

TS_CAL1 Temperature sensor raw data acquired value at 30 °C, V

DDA

=3.3 V

TS_CAL2 Temperature sensor raw data acquired value at 130 °C, V

DDA

=3.3 V

Memory address

0x08FF F814 - 0x08FF F816

0x08FF F818 - 0x08FF F81A

Digital temperature sensor characteristics

Table 98. Digital temperature sensor characteristics

Symbol f

DTS

(2)

T

LC

(2)

Parameter

Output Clock frequency

Temperature linearity coefficient

Conditions

-

VOS2

Min (1)

500

1660

T

TOTAL_ERROR

T

VDD_CORE

(2)

Temperature offset measurement, all VOS

Additional error due to supply variation t

TRIM t

WAKE_UP

I

DDCORE_DTS

Calibration time

Wake-up time from off state until DTS ready bit is set

DTS consumption on V

CORE

1. Guaranteed by design, unless otherwise specified.

2. Guaranteed by characterization results.

T

J

=−40 °C to 30 °C −13

T

J

=30 °C to 130 °C −7

VOS2 0

VOS0, VOS1, VOS3 −1

-

-

-

8.5

Typ

-

-

-

-

4

2

0

1

°C

°C

2 ms

67 116.00

μs

30

(1)

750

2100

Max (1)

1150

2750

70.0

Unit kHz

Hz/°C

μA

Temperature and V

BAT

monitoring

Table 99. V

BAT

monitoring characteristics

Symbol Parameter

R

Q

Er (1)

t

S_vbat

(1)

V

BAThigh

V

BATlow

Resistor bridge for V

BAT

Ratio on V

BAT

measurement

Error on Q

ADC sampling time when reading V

High supply monitoring

Low supply monitoring

1. Guaranteed by design.

BAT input

Min

-

-

–10

9

-

-

Typ

26

4

-

-

3.55

1.36

Max

-

-

+10

-

-

-

Unit

KΩ

-

%

µs

V

Symbol

R

BC

Parameter

Table 100. V

BAT

charging characteristics

Battery charging resistor

Condition

VBRS in PWR_CR3= 0

VBRS in PWR_CR3= 1

Min

-

-

Typ

5

1.5

Max

-

-

Unit

KΩ

DS13196 - Rev 6 page 139/199

STM32H7B0xB

Operating conditions

6.3.27

Table 101. Temperature monitoring characteristics

Symbol

TEMP high

TEMP low

Parameter

High temperature monitoring

Low temperature monitoring

1. Guaranteed by design.

Min

(1)

-

-

Typ (1)

117

– 25

Voltage booster for analog switch

Max (1)

-

-

Unit

°C

Symbol

V

DD t

SU(BOOST)

I

DD(BOOST)

Table 102. Voltage booster for analog switch characteristics

Parameter

Supply voltage

Booster startup time

Booster consumption

Condition

-

-

1.62 V ≤ V

DD

≤ 2.7 V

2.7 V < V

DD

< 3.6 V

Min

(1)

1.62

-

-

-

Typ (1)

2.6

-

-

-

1. Guaranteed by characterization results.

Comparator characteristics

Max (1)

3.6

50

125

250

Unit

V

µs

µA

6.3.28

Symbol

V

DDA

V

IN

V

BG

(2)

V

SC

Parameter

Analog supply voltage

Comparator input voltage range

Scaler input voltage

Scaler offset voltage

I

DDA(SCALER)

Scaler static consumption from V

DDA t

START_SCALER

Scaler startup time t

START t

D

(3)

V offset

V hys

Propagation delay for 200 mV step with

100 mV overdrive

Propagation delay for step > 200 mV with

100 mV overdrive only on positive inputs

Comparator offset error

Comparator hysteresis

Table 103. COMP characteristics

Comparator startup time to reach propagation delay specification

Conditions

-

-

-

-

BRG_EN=0 (bridge disable)

BRG_EN=1 (bridge enable)

-

High-speed mode

Medium mode

Ultra-low-power mode

High-speed mode

Medium mode

Ultra-low-power mode

High-speed mode

Medium mode

Ultra-low-power mode

Full common mode range

No hysteresis

Low hysteresis

Medium hysteresis

High hysteresis

-

-

-

-

-

-

-

-

-

-

-

-

-

-

8

16

-

4

Min (1) Typ (1) Max (1)

Unit

1.62

0

3.3

-

3.6

V

DDA

V

-

±5

0

10

20

30

0.5

2.5

50

0.5

2.5

2

5

15

50

±5 ±10 mV

0.2

0.8

0.3

1

µA

140 250 µs

5

20

80

80

µs ns

0.9

7

µs

120 ns

1.2

7

µs

±20 mV

-

22

37

52 mV

DS13196 - Rev 6 page 140/199

STM32H7B0xB

Operating conditions

Symbol

I

DDA

(COMP)

Parameter

Comparator consumption from V

DDA

1. Guaranteed by design, unless otherwise specified.

2. Refer to Section 6.3.6 Embedded reference voltage

.

3. Guaranteed by characterization results.

6.3.29

Operational amplifier characteristics

Conditions

Static

Ultra-low-power mode

With 50 kHz ±100 mV overdrive square signal

Medium mode

High-speed mode

Static

With 50 kHz ±100 mV overdrive square signal

Static

With 50 kHz ±100 mV overdrive square signal

Min (1) Typ (1) Max (1)

Unit

400 600 nA

800 -

-

5

6

7

-

µA

-

70

75

100

-

Symbol

V

DDA

CMIR

VI

OFFSET

ΔVI

OFFSET

TRIMOFFSETP,

TRIMLPOFFSETP

TRIMOFFSETN,

TRIMLPOFFSETN

I

LOAD

I

LOAD_PGA

C

LOAD

CMRR

PSRR

GBW

SR

AO

φm

GM

V

OHSAT

Table 104. Operational amplifier characteristics

Parameter

Analog supply voltage Range

Common Mode Input Range

Input offset voltage

Conditions

-

-

25°C, no load on output

All voltages and temperature, no load

Input offset voltage drift

Offset trim step at low common input voltage

(0.1*V

DDA

)

Offset trim step at high common input voltage

(0.9*V

DDA

)

Drive current

Drive current in PGA mode

Capacitive load

Common mode rejection ratio

-

-

Power supply rejection ratio

Gain bandwidth for high supply range

Slew rate (from 10% and 90% of output voltage)

Open loop gain

Phase margin

Gain margin

High saturation voltage

-

-

-

-

C

LOAD

≤ 50pf / R

LOAD

≥ 4 kΩ

V com

=V

DDA

/2

(2) at 1 kHz,

200 mV ≤ Output dynamic range ≤ V

DDA

-

200 mV

Normal mode

High-speed mode

200 mV ≤ Output dynamic range ≤ V

DDA

-

200 mV

-

-

I load

=max or R

LOAD

=min,

Input at V

DDA

-

-

4

-

-

59

-

-

V

DDA

−100 mV

Min (1)

2

0

-

-

-

-

-

-

-

50

Typ (1)

3.3

-

-

-

±3.0

Max (1)

3.6

V

DDA

±1.5

±2.5

-

Unit

V mV

μV/°C

1.1

1.1

7.3

3

24

90

55

12

-

-

-

-

80

66

1.5

1.5

500

270

50

-

mV

12.3

MHz

-

-

129

V/µs dB

-

° dB

mV

μA pF dB dB

DS13196 - Rev 6 page 141/199

STM32H7B0xB

Operating conditions t

Symbol

V

R

OLSAT

WAKEUP

PGA gain network

Parameter

Low saturation voltage

Wake up time from OFF state

Non inverting gain error value

Inverting gain error value

External non-inverting gain error value

R2/R1 internal resistance values in non-inverting PGA mode

(3)

R2/R1 internal resistance values in inverting PGA mode

(3)

Conditions

I load

=max or R

LOAD

=min, Input at 0 V

Normal mode

C

LOAD

≤ 50pf, R

LOAD

≥ 4 kΩ, follower configuration

High speed mode

C

LOAD

≤ 50pf, R

LOAD

≥ 4 kΩ, follower configuration

PGA gain = 2

PGA gain = 4

PGA gain = 8

PGA gain = 16

PGA gain = 2

PGA gain = 4

PGA gain = 8

PGA gain = 16

PGA gain = 2

PGA gain = 4

PGA gain = 8

PGA gain = 16

PGA Gain=2

PGA Gain=4

PGA Gain=8

PGA Gain=16

PGA Gain = -1

PGA Gain = -3

PGA Gain = -7

PGA Gain = -15

Delta R

Resistance variation (R1 or

R2)

-

PGA BW

PGA bandwidth for different non inverting gain

PGA bandwidth for different inverting gain

I en

DDA(OPAMP)

Voltage noise density

OPAMP consumption from

V

DDA at 1 KHz at 10 KHz

Normal mode

High-speed mode

1. Guaranteed by design, unless otherwise specified.

2. R

LOAD

is the resistive load connected to VSSA or to VDDA.

Gain=2

Gain=4

Gain=8

Gain=16

Gain = -1

Gain = -3

Gain = -7

Gain = -15 output loaded with 4 kΩ no Load, quiescent mode, follower

Min (1)

-

-

Typ (1) Max (1)

Unit

100 mV

0.8

3.2

µs

0.9

2.8

10/10

30/10

70/10

150/10

10/10

30/10

70/10

150/10

-

-

-

-

-

-

-

-

-

-

-

-

-

% kΩ/ kΩ

%

GBW/2

GBW/4

GBW/8

GBW/16

5.00

3.00

1.50

0.80

140

55

570

610

-

-

1000

-

-

-

-

-

-

-

-

MHz

MHz nV/√Hz

µA

1200

-

-

-

-

-

-

-

-

1

3

2

3

3.5

4

2.5

3

1

1

1

2

15

-

−15

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

−2

−3

−1

−3

−3.5

−4

−1

−2

−2.5

−3

−1

−1

DS13196 - Rev 6 page 142/199

STM32H7B0xB

Operating conditions

3. R2 is the internal resistance between the OPAMP output and th OPAMP inverting input. R1 is the internal resistance between the OPAMP inverting input and ground. PGA gain = 1 + R2/R1.

6.3.30

Digital filter for Sigma-Delta Modulators (DFSDM) characteristics

Unless otherwise specified, the parameters given in

Table 105. DFSDM measured timing 1.62-3.6 V for DFSDM

are derived from tests performed under the ambient temperature, f

PCLKx

frequency and supply voltage conditions

summarized in Table 20. General operating conditions and

Table 21. Maximum allowed clock frequencies

.

•

•

•

Output speed is set to OSPEEDRy[1:0] = 10

Capacitive load C

L

= 30 pF

Measurement points are done at CMOS levels: 0.5V

DD

VOS level set to VOS0 •

Refer to

Section 6.3.16 I/O port characteristics

for more details on the input/output alternate function characteristics (DìFSDM_CKINx, DFSDM_DATINx, DFSDM_CKOUT for DFSDM).

Symbol f

DFSDMCLK f

CKIN

(1/

T

CKIN

) f

CKOUT

DuCyCKOUT t wh(CKIN) t wl(CKIN) t su t h

T

Manchester

Parameter

DFSDM clock

Input clock frequency

Table 105. DFSDM measured timing 1.62-3.6 V

Conditions

1.62 V < V

DD

< 3.6 V

SPI mode (SITP[1:0]=0,1), External clock mode

(SPICKSEL[1:0]=0),

SPI mode (SITP[1:0]=0,1), Internal clock mode

(SPICKSEL[1:0]≠0)

Min

-

-

-

Output clock frequency

1.62 < V

DD

< 3.6 V -

Output clock frequency duty cycle

1.62 < V

DD

< 3.6 V

Typ

-

-

-

-

Max f

SYSCLK

20 (f

DFSDMCLK

/4)

20 (f

DFSDMCLK

/4)

20

Even division,CKOUTDIV[7:0]

= n, 1, 3, 5, ...

Odd division,CKOUTDIV[7:0]

= n, 2, 4, 6, ...

45 50 55

(((n/

2+1)/(n−1))*100)−5

(((n/2+1)/

(n−1))*100)

(((n/

2+1)/(n−1))*100)+5

Input clock high and low time

Data input setup time

Data input hold time

Manchester data period

(recovered clock period)

SPI mode

(SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

1.62 < V

DD

< 3.6 V

SPI mode

(SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

1.62 < V

DD

< 3.6 V

SPI mode

(SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

1.62 < V

DD

< 3.6 V

Manchester mode

(SITP[1:0]=2,3),

Internal clock mode

(SPICKSEL[1:0]¹0),

1.62 < V

DD

< 3.6 V

-

-

-

T

CKIN

/2 - 0.5

4

0.5

(CKOUTDIV[7:0]+1) x T

DFSDMCLK

T

CKIN

/2

-

-

-

-

-

-

(2*CKOUTDIV[7:0]) x T

DFSDMCLK

Unit

MHz

% ns

DS13196 - Rev 6 page 143/199

STM32H7B0xB

Operating conditions

SPICKSEL=3

SPICKSEL=2

SPICKSEL=1

SITP = 0

SITP = 1

Figure 51. Channel transceiver timing diagrams

(SPICKSEL=0)

SITP = 00

SITP = 01 t su t h t wl t wh t su t h t r t f t su t h t wl t wh t su t h t r t f

SITP = 2

SITP = 3

6.3.31

recovered clock recovered data

0 0 1 1 0

•

Camera interface (DCMI) timing specifications

Unless otherwise specified, the parameters given in

Table 106. DCMI characteristics for DCMI are derived

from tests performed under the ambient temperature, f

HCLK

frequency and VDD supply voltage summarized in

Table 20. General operating conditions and

Table 21. Maximum allowed clock frequencies , with the following

configuration:

DCMI_PIXCLK polarity: falling

DS13196 - Rev 6 page 144/199

STM32H7B0xB

Operating conditions

Symbol

-

DCMI_PIXCLK

D pixel t su(

DATA) t h

(DATA) tsu(HSYNC), tsu(VSYNC) th(HSYNC), th(VSYNC)

1. Guaranteed by design.

•

•

•

•

•

•

DCMI_VSYNC and DCMI_HSYNC polarity: high

Data formats: 14 bits

Capacitive load C

L

=30 pF

Measurement points are done at CMOS levels: 0.5V

DD

Output speed is set to OSPEEDRy[1:0] = 11

VOS level set to VOS0

Table 106. DCMI characteristics

Parameter

Frequency ratio DCMI_PIXCLK/f

HCLK

Pixel Clock input

Pixel Clock input duty cycle

Data input setup time

Data hold time

DCMI_HSYNC/ DCMI_VSYNC input setup time

DCMI_HSYNC/ DCMI_VSYNC input hold time

Figure 52. DCMI timing diagram

1/DCMI_PIXCLK

DCMI_PIXCLK t su(HSYNC) t h(HSYNC)

DCMI_HSYNC t su(VSYNC) t h(HSYNC)

DCMI_VSYNC t su(DATA) t h(DATA)

Min

(1)

-

-

30

2.5

1

3

1

DATA[0:13]

Max

(1)

0.4

80

70

-

-

-

-

Unit

-

MHz

%

ns

-

DS13196 - Rev 6 page 145/199

6.3.32

Note:

STM32H7B0xB

Operating conditions

•

•

•

•

•

•

•

PSSI interface characteristics

Unless otherwise specified, the parameters given in

Table 107 and 108

for PSSI are derived from tests performed under the ambient temperature, f

HCLK

frequency and V

DD

supply voltage summarized in Table 20. General operating conditions and

Table 21. Maximum allowed clock frequencies

, with the following configuration:

PSSI_PDCK polarity: falling

PSSI_RDY and PSSI_DE polarity: low

Bus width : 16 lines

DATA width : 32 bits

Capacitive load C=30 pF

Measurement points are done at CMOS levels: 0.5V

DD

Output speed is set to OSPEEDRy[1:0] = 11

At VOS1, the performance in Transmit mode can be degraded by up to 5 % compared to VOS0. This is indicated by a footnote when applicable.

Table 107. PSSI transmit characteristics

Guaranteed by characterization results.

Symbol

-

Parameter

Frequency ratio PSSI_PDCK/f

HCLK

PSSI clock input PSSI_PDCK

D pixel t dv(DATA) t dh(DATA) t dv((DE) t dh(DE) t su(RDY) t h(RDY)

PSSI clock input duty cycle

Data output valid time

Data output hold time

DE output valid time

DE output hold time

RDY input setup time

RDY input hold time

1. At VOS1, these values are degraded by up to 5 %.

5

-

6

3

0

Min

30

-

-

-

Max (1)

0.4

50

70

10

-

14

-

-

-

Unit

-

MHz

% ns

Guaranteed by characterization results.

Symbol

-

PSSI_PDCK

D pixel t su(DATA) t h(DATA) t su((DE) t h(DE) t ov(RDY) t oh(RDY)

Table 108. PSSI receive characteristics

Parameter

Frequency ratio PSSI_PDCK/f

HCLK

PSSI clock input

PSSI clock input duty cycle

Data input setup time

Data input hold time

DE input setup time

DE input hold time

RDY output valid time

RDY output hold time

2

1

3

Min

-

-

30

1

-

4.5

-

-

-

Max

0.4

100

70

-

10

-

DS13196 - Rev 6 page 146/199

DS13196 - Rev 6

STM32H7B0xB

Operating conditions

CKPOL = 0

CKPOL = 1

PSSI D[15:0]

(output)

DEPOL = 0

DEPOL = 1

RDYPOL = 0 t su(RDY)

RDYPOL = 1

Figure 53. PSSI timing diagram in Transmit mode t c(PDCK) t w(PDCKH) t w(PDCKL) t f(PDCK) t r(PDCK) t ov(DATA)

Invalid data OUT t ov(DE) t oh(DATA)

Valid data OUT t oh(DE)

Invalid data OUT t h(RDY)

MSv65388V1

Figure 54. PSSI timing diagram in Receive mode t c(PDCK) t w(PDCKH) t w(PDCKL) t f(PDCK) t r(PDCK)

CKPOL = 0

CKPOL = 1

PSSI D[15:0]

(input) t su(DATA)

Invalid data IN t su(DE) t hDATA)

Valid data IN t h(DE)

Invalid data IN

DEPOL = 0

DEPOL = 1 t ov(RDY)

RDYPOL = 0

RDYPOL = 1 t oh(RDY)

MSv65389V1 page 147/199

STM32H7B0xB

Operating conditions

6.3.33

Note:

•

•

•

•

•

•

•

•

•

•

LCD-TFT controller (LTDC) characteristics

Unless otherwise specified, the parameters given in

Table 109 for LCD-TFT are derived from tests performed

under the ambient temperature, f

HCLK

frequency and VDD supply voltage summarized in Table 20. General operating conditions and

Table 21. Maximum allowed clock frequencies

, with the following configuration:

LCD_CLK polarity: high

LCD_DE polarity: low

LCD_VSYNC and LCD_HSYNC polarity: high

Pixel formats: 24 bits

Output speed is set to OSPEEDRy[1:0] = 11

Capacitive load C

L

=30 pF

Measurement points are done at CMOS levels: 0.5VDD

IO Compensation cell activated.

HSLV activated when V

DD

≤ 2.7 V

VOS level set to VOS 0

At VOS1, the performance can be degraded by up to 5 % compared to VOS0. This is indicated by a footnote when applicable.

Symbol f

CLK

D

CLK t w(CLKH)

, t w(CLKL) t v(DATA) t h(DATA) t v(HSYNC)

, t v(VSYNC)

, t v(DE)

Table 109. LTDC characteristics

Parameter

LTDC clock output frequency

LTDC clock output duty cycle

Clock High time, low time

Data output valid time

Data output hold time

HSYNC/VSYNC/DE output valid time t h(HSYNC)

, t h(VSYNC)

, t h(DE)

HSYNC/VSYNC/DE output hold time

1. At VOS1, these values are degraded by up to 5 %.

Conditions

2.7 V < V

DD

< 3.6 V, 20 pF

2.7 V < V

DD

< 3.6 V

1.62 V < V

DD

< 3.6 V

-

-

2.7 V < V

DD

< 3.6 V

1.62 V < V

DD

< 3.6 V

-

2.7 V < V

DD

< 3.6 V

1.62 V < V

DD

< 3.6 V

-

Min

-

-

-

Max (1)

140

133

66.5

45 55 t w(CLK)

/2−0.5

t w(CLK)

/2+0.5

-

3.0

7.5

0

-

-

0

-

3.0

7.5

-

Unit

MHz

% ns

DS13196 - Rev 6 page 148/199

Figure 55. LCD-TFT horizontal timing diagram tCLK

LCD_CLK

LCD_VSYNC tv(HSYNC)

LCD_HSYNC tv(HSYNC) tv(DE) th(DE)

LCD_DE

LCD_R[0:7]

LCD_G[0:7]

LCD_B[0:7]

HSYNC width tv(DATA)

Pixel

1

Pixel

2

Horizontal back porch th(DATA)

Active width

One line

Pixel

N

Horizontal back porch

STM32H7B0xB

Operating conditions

6.3.34

Figure 56. LCD-TFT vertical timing diagram tCLK

LCD_CLK tv(VSYNC)

LCD_VSYNC

LCD_R[0:7]

LCD_G[0:7]

LCD_B[0:7]

M lines data tv(VSYNC)

VSYNC width

Vertical back porch

Active width

One frame

Vertical back porch

Timer characteristics

The parameters given in Table 110. TIMx characteristics

are guaranteed by design.

Refer to

Section 6.3.16 I/O port characteristics

for details on the input/output alternate function characteristics

(output compare, input capture, external clock, PWM output).

DS13196 - Rev 6 page 149/199

6.3.35

6.3.36

6.3.36.1

Note:

STM32H7B0xB

Operating conditions

Table 110. TIMx characteristics

Symbol t res(TIM)

Parameter

Timer resolution time

Conditions

(1)

AHB/APBx prescaler=1 or 2 or 4, f

TIMxCLK

= 280 MHz

AHB/APBx prescaler>4, f

TIMxCLK

=

140 MHz

Min

1

1

(2) Max

-

-

(2)

t t

Unit

TIMxCLK

TIMxCLK f

EXT

Timer external clock frequency on

CH1 to CH4

Res

TIM

Timer resolution t

MAX_COUNT

Maximum possible count with 32bit counter

f

TIMxCLK

= 280 MHz

0

-

f

TIMxCLK

16/32

/2

65536 × 65536 t

MHz bit

TIMxCLK

1. The maximum timer frequency on APB1 or APB2 is up to 280 MHz, by setting the TIMPRE bit in the RCC_CFGR register. If

APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x F rcc_pclkx_d2

.

2. Guaranteed by design.

Low-power timer characteristics

Symbol t res(TIM) f

LPTIMxCLK f

EXT

Res

TIM t

MAX_COUNT

Table 111. LPTIMx characteristics

Parameter

Timer resolution time

Timer kernel clock

Timer external clock frequency on Input1 and Input2

Timer resolution

Maximum possible count

Min

1

0

0

-

-

Max

-

100 f

LPTIM xCLK/2

16

65536

Communication interfaces

I 2 C interface characteristics

The I 2 C interface meets the timings requirements of the I2C-bus specification and user manual revision 03 for:

•

•

•

Standard-mode (Sm): with a bit rate up to 100 kbit/s

Fast-mode (Fm): with a bit rate up to 400 kbit/s

Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.

The parameters given in Table 112 and

Table 113

are obtained with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 00

At VOS1, the performance can be degraded by up to 5 % compared to VOS0. This is indicated by a footnote when applicable.

The I 2 C timings requirements are guaranteed by design when the I 2 C peripheral is properly configured (refer to

RM0455 reference manual) and when the i2c_ker_ck frequency is greater than the minimum shown in the table below:

Unit t

TIMxCLK

MHz bit t

TIMxCLK

Symbol f

I2CCLK

Table 112. Minimum i2c_ker_ck frequency in all I 2 C modes

Parameter

I2CCLK frequency

Standard-mode

Fast-mode

Fast-mode Plus

Condition

-

Analog Filtre ON, DNF=0

Analog Filtre OFF, DNF=1

Analog Filtre ON, DNF=0

Min

2

9

9

19

Unit

MHz

DS13196 - Rev 6 page 150/199

STM32H7B0xB

Operating conditions

6.3.36.2

Note:

Symbol f

CK

Symbol f

I2CCLK

Parameter

I2CCLK frequency Fast-mode Plus

Condition

Analog Filtre OFF, DNF=1

Min

16

Unit

-

The SDA and SCL I/O requirements are met with the following restrictions:

•

•

The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and V

DDIOx

is disabled, but still present.

The 20 mA output drive requirement in Fast-mode Plus is not supported. This limits the maximum load C

Load supported in Fm+, which is given by these formulas: t r(SDA/SCL)

=0.8473xR

P xC

Load

R

P(min)

= (V

DD

-V

OL(max)

)/I

OL(max)

Where R

P

is the I2C lines pull-up. Refer to Section 6.3.16 I/O port characteristics for the I

2 C I/Os characteristics.

All I 2 C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics:

Table 113. I 2 C analog filter characteristics

Symbol t

AF

Parameter

Maximum pulse width of spikes that are suppressed by analog filter

1. Guaranteed by design.

2. Spikes whose width is lower than t

AF(min) are filtered.

3. Spikes whose width is higer than t

AF(max)

are not filtered.

Min (1)

Max

(1)

Unit

50

(2) 260 (3)

ns

•

•

•

•

•

USART interface characteristics

Unless otherwise specified, the parameters given in

Table 114 for USART are derived from tests performed under

the ambient temperature, f

PCLKx frequency and V

DD

supply voltage conditions summarized in

Table 20. General operating conditions and

Table 21. Maximum allowed clock frequencies

, with the following configuration:

Output speed is set to OSPEEDRy[1:0] = 11

Capacitive load C

L

= 30 pF

Measurement points are done at CMOS levels: 0.5V

DD

IO Compensation cell activated.

VOS level set to VOS0

At VOS1, the performance can be degraded by up to 5 % compared to VOS0. This is indicated by a footnote when applicable.

Refer to

Section 6.3.16 I/O port characteristics

for more details on the input/output alternate function characteristics (NSS, CK, TX, RX for USART).

Parameter

USART clock frequency t su(NSS) t h(NSS) t w(SCKH)

, t w(SCKL) t su(MI)

NSS setup time

NSS hold time

CK high and low time

Data input setup time

Table 114. USART characteristics

Conditions

Master mode

Slave receiver mode

Slave mode transmitter mode, 2.7 V < V

DD

< 3.6 V

Slave mode transmitter mode, 1.62 V < V

DD

< 3.6 V

Slave mode

Slave mode

Master mode

Master mode t

Min ker

-

2

+2

Typ

-

-

-

Max

(1)

35

93.0

29.0

22.0

-

-

Unit

MHz

-

1/f ck

/2−2 1/f ck

/2 1/f ck

/2+2

17 ns

DS13196 - Rev 6 page 151/199

STM32H7B0xB

Operating conditions

Symbol t su(SI) t h(MI) t h(SI) t v(SO) t v(SO) t v(MO) t h(SO) t h(MO)

Parameter

Data input setup time

Data input hold time

Data output valid time

Data output hold time

Slave mode

Master mode

Slave mode transmitter mode, 1.62 V < V

Slave mode transmitter mode, 2.7 V < V

1. At VOS1, these values are degraded by up to 5 %.

Conditions

Slave mode

Master mode

Slave mode

Master mode

DD

DD

< 3.6 V

< 3.6 V

NSS input

High

Figure 57. USART timing diagram in Master mode t c(SCK)

CPHA=0

CPOL=0

CPHA=0

CPOL=1

1.5

-

-

-

Min

1

0

12

1

Typ

-

-

-

15.5

15.5

1.5

-

-

Max

(1)

-

-

-

22

17

2

-

-

Unit ns

CPHA=1

CPOL=0

CPHA=1

CPOL=1

RX

INPUT

TX

OUTPUT t su(RX) t w(SCKH) t w(SCKL)

MSB IN t h(RX)

MSB OUT t v(TX)

BIT6 IN

BIT1 OUT t h(TX) t r(SCK)

/t f(SCK)

LSB IN

LSB OUT

MSv65386V1

1.

Measurement points are done at 0.5V

DD

and with external C

L

= 30 pF.

DS13196 - Rev 6 page 152/199

STM32H7B0xB

Operating conditions

Figure 58. USART timing diagram in Slave mode

6.3.36.3

Note:

NSS input t w(SCKH) t c(SCK)

CPHA=0

CPOL=0

CPHA=0

CPOL=1 t a(TX)

TX output t su(NSS) t w(SCKL)

First bit OUT t h(RX) t v(TX) t su(RX)

RX input First bit IN t h(TX)

Next bits OUT

Next bits IN t t r(SCK) f(SCK) t h(NSS)

Last bit OUT

Last bit IN t dis(TX)

MSv65387V1

•

•

•

•

SPI interface characteristics

Unless otherwise specified, the parameters given in

Table 115 for SPI are derived from tests performed under

the ambient temperature, f

PCLKx

frequency and V

DD

supply voltage conditions summarized in Table 20. General operating conditions and

Table 21. Maximum allowed clock frequencies

, with the following configuration:

Output speed is set to OSPEEDRy[1:0] = 11

•

•

Capacitive load C

L

= 30 pF

Measurement points are done at CMOS levels: 0.5V

DD

IO Compensation cell activated.

HSLV activated when V

DD

≤ 2.7 V

VOS level set to VOS0

At VOS1, the performance can be degraded by up to 5 % compared to VOS0. This is indicated by a footnote when applicable.

Refer to

Section 6.3.16 I/O port characteristics

for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI).

Symbol f

SCK t su(NSS) t h(NSS) t su(MI)

Parameter

SPI clock frequency

NSS setup time

NSS hold time

Data input setup time

Table 115. SPI dynamic characteristics

Conditions

Master mode 2.7 < V

DD

< 3.6 V, SPI1, 2, 3

Master mode, 2.7 < V

DD

<3.6 V, SPI4, 5, 6

Master mode, 1.62 < V

DD

< 3.6 V, SPI4, 5, 6

Slave receiver mode, 1.62 < V

DD

< 3.6 V

Slave mode transmitter/full duplex, 2.7 < V

DD

< 3.6 V

Slave mode transmitter/full duplex, 1.62 <V

DD

< 3.6 V

Slave mode

Slave mode

Master mode

Min (1)

Typ

(1)

-

2

1

3 -

-

-

-

Max

(1)(2)

Unit

125/100

(3)

100

75/38 (3)

100

45/31 (3)

29/18 (3)

-

-

-

MHz ns ns

DS13196 - Rev 6 page 153/199

STM32H7B0xB

Operating conditions

Symbol t su(SI) t h(MI) t h(SI) t a(SO) t dis(SO)

Parameter

Data input setup time

Data input hold time

Data output access time

Slave mode

Master mode

Slave mode

Slave mode

Conditions t t v(SO) v(MO) t h(SO) t h(MO)

Data output disable time Slave mode

Data output valid time

Data output hold time

Slave mode, 2.7 < V

DD

< 3.6 V

Slave mode, 1.62 < V

DD

< 3.6 V

Master mode, 2.7 < V

DD

< 3.6 V

Master mode, 1.62 < V

DD

< 3.6 V

Slave mode, 1.62 < V

DD

< 3.6 V

Master mode

1. Guaranteed by characterization results.

2. At VOS1, these values are degraded by up to 5 %.

3. Using PC3_C / PC2_C (not available on all packages).

Figure 59. SPI timing diagram - slave mode and CPHA = 0

7

0

-

-

0

-

-

Min (1)

Typ

(1)

2

3

-

-

1

9

-

13

1

9/15 (3)

9/15 (3)

1/5

(3)

1/5

(3)

-

-

Max

(1)(2)

Unit

-

-

-

27

5

11/16

(3)

17/27 (3)

1.5/7 (3)

2/13

(3)

-

ns

NSS input t w(SCKH) t c(SCK)

CPHA=0

CPOL=0

CPHA=0

CPOL=1 t a(SO)

MISO output t su(NSS) t w(SCKL)

First bit OUT t h(SI) t v(SO) t su(SI)

MOSI input First bit IN t h(SO)

Next bits OUT

Next bits IN t r(SCK) t h(NSS) t f(SCK)

Last bit OUT t dis(SO)

Last bit IN

DS13196 - Rev 6 page 154/199

STM32H7B0xB

Operating conditions

MOSI input

Figure 60. SPI timing diagram - slave mode and CPHA = 1 (1)

NSS input

CPHA=1

CPOL=0

CPHA=1

CPOL=1 t su(NSS) t a(SO)

MISO output t w(SCKH) t c(SCK) t w(SCKL) t v(SO) t su(SI)

First bit OUT t h(SI)

First bit IN t h(SO)

Next bits OUT

Next bits IN t f(SCK) t h(NSS) t r(SCK) t dis(SO)

Last bit OUT

Last bit IN

1.

Measurement points are done at 0.5V

DD

and with external C

L

= 30 pF.

Figure 61. SPI timing diagram - master mode (1)

NSS input

High tc(SCK)

CPHA=0

CPOL=0

CPHA=0

CPOL=1

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO

INPUT

MOSI

OUTPUT tsu(MI) tw(SCKH) tw(SCKL)

MSB IN th(MI)

MSB OUT tv(MO)

BIT6 IN

BIT1 OUT th(MO) tr(SCK) tf(SCK)

LSB IN

LSB OUT

6.3.36.4

1.

Measurement points are done at 0.5V

DD

and with external C

L

= 30 pF.

I 2 S Interface characteristics

Unless otherwise specified, the parameters given in

Table 116 for I

2 S are derived from tests performed under the ambient temperature, f

PCLKx

frequency and V

DD

supply voltage conditions summarized in Table 20. General operating conditions and

Table 21. Maximum allowed clock frequencies

, with the following configuration:

DS13196 - Rev 6 page 155/199

Note:

STM32H7B0xB

Operating conditions

•

•

•

•

•

•

Output speed is set to OSPEEDRy[1:0] = 10

Capacitive load C

L

= 30 pF

Measurement points are done at CMOS levels: 0.5V

DD

IO Compensation cell activated.

HSLV activated when VDD ≤ 2.7 V

VOS level set to VOS0

At VOS1, the performance can be degraded by up to 5 % compared to VOS0. This is indicated by a footnote when applicable.

Refer to

Section 6.3.16 I/O port characteristics

for more details on the input/output alternate function characteristics (CK,SD,WS).

Table 116. I 2 S dynamic characteristics

Symbol f

MCK

Parameter

I 2 S main clock output -

Conditions f

CK

I 2 S clock frequency

Master TX

Master RX

Slave TX

Slave RX t v(WS) t h(WS) t su(WS) t h(WS) t su(SD_MR) t su(SD_SR) t h(SD_MR) t h(SD_SR) t v(SD_ST) t v(SD_MT) t h(SD_ST) t h(SD_MT)

WS valid time

WS hold time

WS setup time

WS hold time

Data input setup time

Data input hold time

Data output valid time

Data output hold time

Master mode

Master mode

Slave mode

Slave mode

Master receiver

Slave receiver

Master receiver

Slave receiver

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

1. Guaranteed by characterization results.

2. At VOS1, these values are degraded by up to 5 %.

3. Using PC3_C / PC2_C (not available on all packages).

2

1

2

2

4.5

Min

(1)

-

-

-

-

-

-

0

1

-

-

7

0

-

-

-

-

-

-

16/27 (3)

4/15 (3)

-

-

Max

(1)(2)

50

50/33 (3)

40

31/18.5

(3)

50

5.5

-

Unit

MHz

MHz ns

DS13196 - Rev 6 page 156/199

Figure 62. I 2 S slave timing diagram (Philips protocol) (1)

STM32H7B0xB

Operating conditions

1.

LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

Figure 63. I 2 S master timing diagram (Philips protocol) (1)

DS13196 - Rev 6

1.

LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

page 157/199

6.3.36.5

Note:

STM32H7B0xB

Operating conditions

•

•

•

•

•

SAI characteristics

Unless otherwise specified, the parameters given in

Table 117 for SAI are derived from tests performed under

the ambient temperature, f

PCLKx

frequency and VDD supply voltage conditions summarized in Table 20. General operating conditions and

Table 21. Maximum allowed clock frequencies

, with the following configuration:

Output speed is set to OSPEEDRy[1:0] = 10

Capacitive load C

L

= 30 pF

IO Compensation cell activated.

Measurement points are done at CMOS levels: 0.5VDD

VOS level set to VOS0

At VOS1, the performance can be degraded by up to 5 % compared to VOS0. This is indicated by a footnote when applicable.

Refer to

Section 6.3.16 I/O port characteristics

for more details on the input/output alternate function characteristics (SCK,SD,WS).

Table 117. SAI characteristics

Symbol f

MCK

Parameter

SAI Main clock output

Conditions

t f

CK v(FS)

SAI clock frequency

F

S

valid time

Master transmitter, 2.7 ≤ V

DD

≤ 3.6 V

Master transmitter, 1.62 ≤ V

DD

≤ 3.6 V

Master receiver, 1.6 ≤ V

DD

≤ 3.6 V

Slave transmitter, 2.7 ≤ VDD ≤ 3.6 V

Slave transmitter, 1.62 ≤ VDD ≤ 3.6 V

Slave receiver, 1.62 ≤ V

DD

≤ 3.6 V

Master mode,2.7 ≤ V

DD

≤ 3.6 V

Master mode, 1.62 ≤ V

DD

≤ 3.6 V

Slave mode t su(FS) t h(FS)

F

S

setup time

F

S

hold time

F

S

hold time

Master mode t su(SD_A_MR) t su(SD_B_SR) t h(SD_A_MR) t h(SD_B_SR) t v(SD_B_ST) t h(SD_B_ST) t v(SD_A_MT)

Data input setup time

Data output hold time

Data output valid time

Slave mode

Master receiver

Slave receiver

Master receiver

Data input hold time

Data output valid time

Slave receiver

Slave transmitter (after enable edge), 2.7 ≤ V

DD

≤ 3.6 V

Slave transmitter (after enable edge), 1.62 ≤ V

DD

≤ 3.6 V

Slave transmitter (after enable edge)

Master transmitter (after enable edge), 2.7 ≤ V

DD

≤ 3.6 V

Master transmitter (after enable edge), 1.62 ≤ V

DD

≤ 3.6 V

Master transmitter (after enable edge) t h(SD_A_MT)

Data output hold time

1. Guaranteed by characterization results.

2. At VOS1, these values are degraded by up to 5 %.

3. APB clock frequency must be at least twice SAI clock frequency.

2

0.5

1

5.5

3

-

-

8

-

-

7.5

Min

(1)

-

Max

(1)(2)

50

Unit

-

-

-

-

-

-

-

-

8

1

34

27

27

37

30

50

14.5

18.5

-

-

MHz

-

-

-

-

-

13.5

16.5

14

18

-

ns

DS13196 - Rev 6 page 158/199

STM32H7B0xB

Operating conditions

SAI_SCK_X

SAI_FS_X(output) tv(FS)

SAI_SD_X(transmit)

SAI_SD_X(receive)

1/fSCK

Figure 64. SAI master timing waveforms th(FS) tsu(SD_MR) tv(SD_MT)

Slot n th(SD_MR)

Slot n

Slot n+2 th(SD_MT)

SAI_SCK_X tw(CKH_X)

SAI_FS_X(input)

SAI_SD_X(transmit) tsu(FS)

SAI_SD_X(receive)

1/fSCK

Figure 65. SAI slave timing waveforms tw(CKL_X) tsu(SD_SR) tv(SD_ST)

Slot n

Slot n th(SD_SR)

Slot n+2 th(FS) th(SD_ST)

6.3.36.6

Note:

•

•

•

•

MDIO characteristics

Unless otherwise specified, the parameters given in

Table 118 are derived from tests performed under the

ambient temperature, f

HCLK

frequency and V

conditions , with the following configuration:

DD

supply voltage summarized in Table 20. General operating

•

Output speed is set to OSPEEDRy[1:0] = 10

Measurement points are done at CMOS levels: 0.5V

I/O compensation cell activated.

HSLV activated when V

DD

≤ 2.7 V

VOS level set to VOS0

DD

At VOS1, the performance can be degraded by up to 5 % compared to VOS0. This is indicated by a footnote when applicable.

DS13196 - Rev 6 page 159/199

STM32H7B0xB

Operating conditions

Table 118. MDIO Slave timing parameters

Symbol

F

MDC t d(MDIO) t su(MDIO) t h(MDIO)

Parameter

Management Data Clock

Management Data Iput/output output valid time

Management Data Iput/output setup time

Management Data Iput/output hold time

1. At VOS1, these values are degraded by up to 5 %.

Min

-

9

2.5

1

Typ

-

11

-

-

Max

(1)

30

21

-

-

Unit

MHz ns

Figure 66. MDIO Slave timing diagram t

MDC) t d(MDIO) t su(MDIO) t h(MDIO)

6.3.36.7

Note:

•

•

•

•

•

•

SD/SDIO MMC card host interface (SDMMC) characteristics

Unless otherwise specified, the parameters given in

Table 119 and

Table 120

for SDIO are derived from tests performed under the ambient temperature, f

PCLKx

frequency and V

DD

supply voltage summarized in

Table 20. General operating conditions and

Table 21. Maximum allowed clock frequencies , with the following

configuration:

Output speed is set to OSPEEDRy[1:0] = 11

Capacitive load C

L

=30 pF

Measurement points are done at CMOS levels: 0.5V

DD

IO Compensation cell activated.

HSLV activated when V

DD

≤ 2.7 V

VOS level set to VOS0

At VOS1, the performance can be degraded by up to 5 % compared to VOS0. This is indicated by a footnote when applicable.

Refer to

Section 6.3.16 I/O port characteristics

for more details on the input/output characteristics.

Table 119. Dynamics characteristics: SDMMC characteristics, V

DD

=2.7 to 3.6 V

Above 100 MHz, C

L

= 20 pF.

Symbol Parameter Conditions

Min (1)

Typ

(1)

f

PP

t

W(CKL) t

W(CKH)

Clock frequency in data transfer mode

SDIO_CK/f

PCLK2

frequency ratio

Clock low time

Clock high time

-

f

PP

=52 MHz f

PP

=52 MHz

0

-

8.5

8.5

-

-

9.5

9.5

Max (1)(2)

133

8/3

-

-

Unit

MHz

ns

DS13196 - Rev 6 page 160/199

STM32H7B0xB

Operating conditions

Symbol Parameter Conditions

CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR/DDR mode t

ISU t

IH

Input setup time HS

Input hold time HS -

t

IDW

(3)

Input valid window (variable window) -

CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR/DDR mode t

OV t

OH

Output valid time HS

Output hold time HS

CMD, D inputs (referenced to CK) in SD default mode t

ISUD

Input setup time SD t

IHD

Input hold time SD

CMD, D outputs (referenced to CK) in SD default mode t

OVD t

OHD

Output valid default time SD

Output hold default time SD -

-

-

-

-

-

Min

2.5

0.5

3.0

-

5

2.5

0.5

-

0

(1)

1. Guaranteed by characterization results.

2. At VOS1, these values are degraded by up to 5 %.

3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.

Typ

(1)

6

1

-

-

-

-

-

-

-

Max (1)(2)

-

-

-

6.5

-

1.5

-

-

-

Unit ns

ns ns ns

Table 120. Dynamics characteristics: eMMC characteristics VDD=1.71V to 1.9V

Above 100 MHz, C

L

= 20 pF.

Symbol Parameter Conditions Min

(1) Typ (1)

Ma

(1)(2)

f

PP

Clock frequency in data transfer mode t

W(CKL) t

W(CKH)

Clock low time

Clock high time

CMD, D inputs (referenced to CK) in eMMC mode t

ISU t

IH

Input setup time HS

Input hold time HS t

IDW

(3)

Input valid window (variable window)

CMD, D outputs (referenced to CK) in eMMC mode t

OVD t

OHD

Output valid time HS

Output hold time HS

f

PP

=52 MHz f

PP

=52 MHz

-

-

-

-

-

0

8.5

8.5

2.5

0.5

3.5

-

5.5

-

9.5

9.5

-

-

-

-

6

1. Guaranteed by characterization results.

2. At VOS1, these values are degraded by up to 5 %.

3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.

85

-

-

-

-

-

-

6.5

Unit

MHz ns ns ns

DS13196 - Rev 6 page 161/199

Figure 67. SDIO high-speed mode

STM32H7B0xB

Operating conditions

CK

D, CMD(output)

Figure 68. SD default mode tOVD tOHD t r(CLK)

Figure 69. DDR mode t

(CLK) t w(CLKH) t w(CLKL) t f(CLK)

Clock

Data output

Data input t vf(OUT) t hr(OUT)

IO0

IO0

IO1 t sf(IN) t hf(IN)

IO1

IO2 t vr(OUT) t hf(OUT)

IO2

IO3

IO3

IO4 t sr(IN) t hr(IN)

IO5

IO4 IO5

6.3.36.8

USB OTG_FS characteristics

Unless otherwise specified, the parameters given in

Table 121. Dynamics characteristics: USB OTG_FS

for ULPI are derived from tests performed under the ambient temperature, f

PCLKx

frequency and V

DD

supply voltage

summarized in Table 20. General operating conditions and

Table 21. Maximum allowed clock frequencies

, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11

DS13196 - Rev 6 page 162/199

6.3.36.9

Note:

STM32H7B0xB

Operating conditions

•

•

•

•

Capacitive load C

L

=20 pF

Measurement points are done at CMOS levels: 0.5V

DD

IO Compensation cell activated.

VOS level set to VOS0

Refer to

Section 6.3.16 I/O port characteristics

for more details on the input/output characteristics.

Table 121. Dynamics characteristics: USB OTG_FS

Symbol

V

DD33USB

R

PUI

R

PUR

Z

DRV

Parameter

USB transceiver operating voltage

Embedded USB_DP pull-up value during idle

Embedded USB_DP pull-up value during reception

Output driver impedance

(2)

Condition

-

-

-

Driver high and low

Min

3.0

(1)

900

1400

28

Typ

-

1250

2300

36

Max

3.6

1600

3200

44

Unit

V

Ω

1. The USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics that are degraded in the 2.7 to

3.0 V voltage range.

2. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching impedance is already included in the embedded driver.

•

•

•

•

USB OTG_HS characteristics

Unless otherwise specified, the parameters given in

Table 122 for ULPI are derived from tests performed under

the ambient temperature, f

PCLKx

frequency and V

DD

supply voltage summarized in

Table 20. General operating conditions and

Table 21. Maximum allowed clock frequencies

, with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 11

Capacitive load C

L

=20 pF

Measurement points are done at CMOS levels: 0.5V

DD

IO Compensation cell activated.

VOS level set to VOS0

At VOS1, the performance can be degraded by up to 5 % compared to VOS0. This is indicated by a footnote when applicable.

Refer to

Section 6.3.16 I/O port characteristics

for more details on the input/output characteristics.

Table 122. Dynamics characteristics: USB ULPI

Symbol Parameter Condition

Min (1) Typ (1)

Max

(1)(2)(3)

Unit t t

SC t

HC t

SD t

HD

DC

/t

DD

Control in (ULPI_DIR , ULPI_NXT) setup time

Control in (ULPI_DIR, ULPI_NXT) hold time

Data in setup time

Data in hold time

Control/Datal output delay

-

-

-

-

2.7 < V

DD

< 3.6 V, C

L

=20 pF

1.71 < V

DD

< 3.6 V, C

L

=15 pF

3.5

2

3

0

-

-

1. Guaranteed by characterization results.

2. At VOS1, these values are degraded by up to 5 %.

3. For external ULPI transceivers operating at 1.8 V, check carefully the timing values for compatibility.

-

-

7

9

-

-

-

-

-

8.5

13 ns

DS13196 - Rev 6 page 163/199

STM32H7B0xB

Operating conditions

Figure 70. ULPI timing diagram

Clock

Control In

(ULPI_DIR,ULPI_NXT) tSC tSD data In

(8-bit)

Control out

(ULPI_STP) data out

(8-bit) tHC tHD tDD tDC tDC

6.3.36.10

Note:

•

•

JTAG/SWD interface characteristics

Unless otherwise specified, the parameters given in

Table 123 and Table 124

for JTAG/SWD are derived from tests performed under the ambient temperature, f rcc_cpu_ck

frequency and V

DD

supply voltage summarized in

Table 20. General operating conditions and

Table 21. Maximum allowed clock frequencies , with the following

configuration:

•

•

Output speed is set to OSPEEDRy[1:0] = 10

Capacitive load C

L

=30 pF

Measurement points are done at CMOS levels: 0.5V

DD

VOS level set to VOS0

At VOS1, the performance can be degraded by up to 5 % compared to VOS0. This is indicated by a footnote when applicable.

Refer to

Section 6.3.16 I/O port characteristics

for more details on the input/output characteristics:

Symbol

F pp

1/t c(TCK) t isu(TMS) t ih(TMS) t isu(TDI) t ih(TDI) t ov(TDO)

Table 123. Dynamics JTAG characteristics

Parameter

T

CK

clock frequency

TMS input setup time

TMS input hold time

TDI input setup time

TDI input hold time

TDO output valid time t oh(TDO)

TDO output hold time

1. At VOS1, these values are degraded by up to 5 %.

Conditions

2.7 V <V

DD

< 3.6 V

1.62 V <V

DD

< 3.6 V

-

-

-

-

2.7 V <V

DD

< 3.6 V

1.62 V <V

DD

< 3.6 V

-

Min

-

-

1

1

-

-

1.5

1

7

Typ

-

-

-

-

8

8

-

-

-

Max

(1)

35

27.5

-

-

14

18

-

-

-

Symbol

F pp

Unit

MHz ns

Table 124. Dynamics SWD characteristics

Parameter

SWCLK clock frequency

Conditions

2.7V <V

DD

< 3.6 V

Min

-

Typ

-

Max

(1)

76

Unit

MHz

DS13196 - Rev 6 page 164/199

DS13196 - Rev 6

Symbol

1/t c(SWCLK) t isu(SWDIO) t ih(SWDIO)

Parameter

SWCLK clock frequency

SWDIO input setup time

SWDIO input hold time t ov(SWDIO)

SWDIO output valid time t oh(SWDIO)

SWDIO output hold

1. At VOS1, these values are degraded by up to 5 %.

Conditions

1.62 <V

DD

< 3.6 V

-

-

2.7V <V

DD

< 3.6 V

1.62 <V

DD

< 3.6 V

-

Figure 71. JTAG timing diagram t c(TCK)

TCK t su(TMS/TDI) t h(TMS/TDI) t w(TCKL) t w(TCKH)

TDI/TMS t ov(TDO)

TDO

STM32H7B0xB

Operating conditions

1

-

-

8

Min

-

2

-

8.5

8.5

-

Typ

-

-

Max

(1)

55.5

-

-

13

18

-

Unit

MHz ns t oh(TDO)

Figure 72. SWD timing diagram t c(SWCLK)

SWCLK

SWDIO

(receive)

SWDIO

(transmit) t su(SWDIO) t h(SWDIO) t ov(SWDIO) t wSWCLKL) t w(SWCLKH) t oh(SWDIO) page 165/199

7

STM32H7B0xB

Package information

Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com

. ECOPACK is an ST trademark.

DS13196 - Rev 6 page 166/199

STM32H7B0xB

LQFP64 package information

7.1

LQFP64 package information

This is a 64-pins, 10 x 10 mm, low-profile quad flat package.

Figure 73. LQFP64 - Outline

SEATING PLANE

C b

49 ccc C

D

D1

D3

48 33

32

L1

L

0.25 mm

GAUGE PLANE

K

64

PIN 1

IDENTIFICATION

1

1.

Drawing is not to scale.

e

16

17

DS13196 - Rev 6 page 167/199

STM32H7B0xB

LQFP64 package information

Table 125. LQFP64 pin - Mechanical data

Symbol

D

D1 b c

D3

E

A

A1

A2 e

K

L

E1

E3

L1 ccc

Min

-

0.050

1.350

0.170

0.090

-

-

-

-

-

-

-

0°

0.450

-

millimeters

Typ

-

-

1.400

0.220

-

12.000

10.000

7.500

12.000

10.000

7.500

0.500

3.5°

0.600

1.000

-

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Max

1.600

0.150

1.450

0.270

0.200

-

-

-

-

-

-

-

7°

0.750

-

0.080

Min

-

0.0020

0.0531

0.0067

0.0035

-

-

-

-

-

-

-

0°

0.0177

-

-

Figure 74. LQFP64 - Recommended footprint

inches (1)

Typ

-

-

0.0551

0.0087

-

0.4724

0.3937

0.2953

0.4724

0.3937

0.2953

0.0197

3.5°

0.0236

0.0394

-

Max

0.0630

0.0059

0.0571

0.0106

0.0079

-

-

-

-

-

-

-

7°

0.0295

-

0.0031

48

0.5

33

32

0.3

49

12.7

10.3

64

1

10.3

7.8

12.7

16

17

1.2

7.1.1

1.

Dimensions are expressed in millimeters.

Device marking for LQFP64

The following figure gives an example of topside marking versus pin 1 position identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.

DS13196 - Rev 6 page 168/199

DS13196 - Rev 6

Figure 75. LQFP64 marking example (package top view)

STM32H7B0xB

LQFP64 package information

Product identification (1)

STM32H7B0

RBT6

Date code

Y WW

Revision code

Pin 1 indentifier

R

1.

Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

page 169/199

7.2

LQFP100 package information

This LQFP is a 100 pins, 14 x 14 mm, low-profile quad flat package.

Figure 76. LQFP100 - Outline

SEATING PLANE

C ccc C

D

D1

D3

76

75 51

50

0.25 mm

GAUGE PLANE

L1

L K

STM32H7B0xB

LQFP100 package information

DS13196 - Rev 6

100

PIN 1

IDENTIFICATION

1 e

25

26

1.

Drawing is not to scale

Table 126. LQFP100 - Mechanical data

Symbol

D1

D3

E

E1

E3 e

L

L1 k ccc

A

A1

A2 b c

D

Min

-

0.050

1.350

0.170

0.090

15.800

13.800

-

15.800

13.800

-

-

0.450

-

0.0°

millimeters

Typ

-

-

1.400

0.220

-

16.000

14.000

12.000

16.000

14.000

12.000

0.500

0.600

1.000

3.5°

-

16.200

14.200

-

-

0.750

-

7.0°

0.080

Max

1.600

0.150

1.450

0.270

0.200

16.200

14.200

-

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.6220

0.5433

-

-

0.0177

-

0.0°

-

Min

-

0.0020

0.0531

0.0067

0.0035

0.6220

0.5433

-

0.6299

0.5512

0.4724

0.0197

0.0236

0.0394

3.5°

-

inches (1)

Typ

-

-

0.0551

0.0087

-

0.6299

0.5512

0.4724

0.6378

0.5591

-

-

0.0295

-

7.0°

0.0031

Max

0.0630

0.0059

0.0571

0.0106

0.0079

0.6378

0.5591

page 170/199

Figure 77. LQFP100 - Recommended footprint

75 51

76 50

0.5

0.3

16.7

14.3

STM32H7B0xB

LQFP100 package information

100

1

12.3

16.7

25

26

1.2

1.

Dimensions are expressed in millimeters.

DS13196 - Rev 6 page 171/199

7.2.1

STM32H7B0xB

LQFP100 package information

Device marking for LQFP100

The following figure gives an example of topside marking versus pin 1 position identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.

Figure 78. LQFP100 marking example (package top view)

Product identification (1)

ES32H7B0VBT6

Revision code

Date code

Y WW

Pin 1 indentifier

1.

Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

DS13196 - Rev 6 page 172/199

STM32H7B0xB

LQFP144 package information

7.3

LQFP144 package information

LQFP144 is a 144-pin, 20 x 20 mm low-profile quad flat package.

Figure 79. LQFP144 - Outline

SEATING

PLANE

C

A A2

A1 ccc C c

A1

D

D1

D3 b

109

108 73

72

0.25 mm

GAUGE PLANE

L1

L

K

E3 E1 E

144

PIN 1

IDENTIFICATION

1

1.

Drawing is not to scale e

36

37

DS13196 - Rev 6 page 173/199

DS13196 - Rev 6

STM32H7B0xB

LQFP144 package information

Table 127. LQFP144 - Mechanical data

Symbol

D

D1 b c

D3

E

A

A1

A2

E1

E3 e

L

L1 k ccc

Min

-

0.050

1.350

0.170

0.090

21.800

19.800

-

21.800

19.800

-

-

0.450

-

0°

millimeters

Typ

-

-

1.400

0.220

-

22.000

20.000

17.500

22.000

20.000

17.500

0.500

0.600

1.000

3.5°

-

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Max

1.600

0.150

1.450

0.270

0.200

22.200

20.200

-

22.200

20.200

-

-

0.750

-

7°

0.080

Min

-

0.0020

0.0531

0.0067

0.0035

0.8583

0.7795

-

0.8583

0.7795

-

-

0.0177

-

0°

-

Figure 80. LQFP144 - Recommended footprint

108 73

1.35

109 0.35

72

inches (1)

Typ

-

-

0.0551

0.0087

-

0.8661

0.7874

0.689

0.8661

0.7874

0.689

0.0197

0.0236

0.0394

3.5°

-

Max

0.0630

0.0059

0.0571

0.0106

0.0079

0.8740

0.7953

-

0.8740

0.7953

-

-

0.0295

-

7°

0.0031

0.5

19.9

17.85

22.6

144

1

1.

Dimensions are expressed in millimeters.

19.9

22.6

37

36 page 174/199

7.3.1

STM32H7B0xB

LQFP144 package information

Device marking for LQFP144

The following figure gives an example of topside marking versus pin 1 position identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.

Figure 81. LQFP144 marking example (package top view)

Product identification (1)

STM32H7B0ZBT6

Date code

Y WW

Pin 1 indentifier

Revision code

1.

Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

DS13196 - Rev 6 page 175/199

7.4

LQFP176 package information

This LQFP is a 176-pin, 24 x 24 mm, 0.5 mm pitch, low profile quad flat package.

C Seating plane

Figure 82. LQFP176 - Outline

0.25 mm gauge plane

STM32H7B0xB

LQFP176 package information k

A1

HD

D

L1

L

PIN 1

IDENTIFICATION

ZE

E

HE e

ZD b

1.

Drawing is not to scale.

DS13196 - Rev 6 page 176/199

STM32H7B0xB

LQFP176 package information

Table 128. LQFP176 - Mechanical data

Symbol b c

D

HD

ZD

E

A

A1

A2

HE

ZE e

L

(2)

L1 k ccc

Min

-

0.050

1.350

0.170

0.090

23.900

25.900

-

23.900

25.900

-

-

0.450

-

0°

millimeters

Typ

-

-

-

-

1.250

-

-

1.250

0.500

-

1.000

-

-

-

-

-

1. Values in inches are converted from mm and rounded to four decimal digits.

2. L dimension is measured at gauge plane at 0.25 mm above the seating plane.

Max

26.100

-

-

0.750

-

7°

0.080

1.600

0.150

1.450

0.270

0.200

24.100

26.100

-

24.100

Min

1.0197

-

-

0.0177

-

0°

-

-

0.0020

0.0531

0.0067

0.0035

0.9409

1.0197

-

0.9409

Figure 83. LQFP176 - Recommended footprint

inches (1)

Typ

-

0.0492

0.0197

-

0.0394

-

-

-

-

-

-

-

-

-

0.0492

-

Max

1.0276

-

-

0.0295

-

7°

0.0031

0.0630

0.0059

0.0571

0.0106

0.0079

0.9488

1.0276

-

0.9488

1.2

1

176

0.5

133

132

0.3

44

45

Note: Dimensions are expressed in millimeters.

DS13196 - Rev 6

21.8

26.7

88

89

1.2

page 177/199

7.4.1

STM32H7B0xB

LQFP176 package information

Device marking for LQFP176

The following figure gives an example of topside marking versus pin 1 position identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.

Figure 84. LQFP176 marking example (package top view)

Product identification (1)

STM32H7B0IBT6

Revision code

Date code

Y WW

Pin 1 indentifier

1.

Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

DS13196 - Rev 6 page 178/199

7.5

STM32H7B0xB

UFBGA169 package information

UFBGA169 package information

This UFBGA is a 169 balls, 7 x 7 mm, 0.50 mm pitch, ultra thin profile fine pitch ball grid array package

Figure 85. UFBGA169 - Outline

Z Seating plane

A2

A4

A3 e b

SIDE VIEW

E1

F

A

A1

A1 ball identifier ddd Z

A1 ball index area

X

E

A

F

D1 D e

Y

N

13

BOTTOM VIEW

1

Øb (169 balls)

Ø

Ø eee fff

M

M

Z

Z

X Y

TOP VIEW

1.

Drawing is not to scale.

2.

– The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized markings, or other feature of package body or integral heat slug.

– A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional.

DS13196 - Rev 6 page 179/199

DS13196 - Rev 6

STM32H7B0xB

UFBGA169 package information

Table 129. UFBGA169 - Mechanical data

Symbol e

F ddd

eee (4) fff (5)

D

D1

E

E1

A

(2)

A1

A2

A4

b (3)

Min.

-

-

-

-

0.230

6.850

-

6.850

-

-

-

-

-

millimeters

Typ.

-

-

0.130

0.320

0.280

7.000

6.000

7.000

6.000

0.500

0.500

-

-

-

Max.

0.600

0.110

-

-

0.330

7.150

-

7.150

-

-

-

0.080

0.015

0.050

Min.

-

-

-

-

0.0091

0.2697

-

0.2697

-

-

-

-

-

inches

Typ.

-

0.0051

0.0126

0.0110

0.2756

0.2362

0.2756

0.2362

0.0197

0.0197

-

-

-

-

(1)

Max.

0.0236

1. Values in inches are converted from mm and rounded to four decimal digits.

2. •

•

Ultra Thin profile: 0.50 < A ≤ 0.65 mm / Fine pitch: e < 1.00 mm pitch.

The total profile height (dim A) is measured from the seating plane to the top of the component

•

• The maximum total package height is calculated by the following methodology:

A Max = A1 Typ + A2 Typ + A4 Typ + √ (A1²+A2²+A4² tolerance values)

3. The typical balls diameters before mounting is 0.20 mm.

4. The tolerance of position that controls the location of the pattern of balls with respect to datum A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datum A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.

5. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained entirely in the respective zone eee above The axis of each ball must lie simultaneously in both tolerance zones.

0.0043

-

-

0.0130

0.2815

-

0.2815

-

-

-

0.0031

0.0059

0.0020

Figure 86. UFBGA169 - Recommended footprint

Dpad

Dsm

page 180/199

7.5.1

STM32H7B0xB

UFBGA169 package information

Table 130. UFBGA169 - recommended PCB design rules (0.5 mm pitch BGA)

Dimension

Pitch

Dpad

Dsm

Solder paste

Recommended values

0.5 mm

0.27 mm

0.35 mm typ. (depends on the soldermask registration tolerance)

0.27 mm aperture diameter

Device marking for UFBGA169

The following figure gives an example of topside marking versus pin 1 position identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.

Figure 87. UFBGA169 marking example (package top view)

Ball 1 indentifier

Product identification (1)

STM32H

7B0ABI6Q

Date code

Y WW Revision code

1.

Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

DS13196 - Rev 6 page 181/199

7.6

STM32H7B0xB

UFBGA(176+25) package information

UFBGA(176+25) package information

This UFBGA is a 176+25 balls, 10 x 10 mm, 0.65 mm pitch, ultra thin profile fine pitch ball grid array package.

Figure 88. UFBGA(176+25) - Outline

C

Seating plane

A4

A2 A3

A e b

E1

F ddd C

A1

A

A1 ball identifier

A1 ball index area

A

F

E

D1 e

R

15

BOTTOM VIEW

1

Øb (176 + 25 balls)

Ø

Ø eee fff

M

M

C

C

A B

B

D

TOP VIEW

1.

Drawing is not to scale.

2.

The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized markings, or other feature of package body or integral heat slug. A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional.

DS13196 - Rev 6 page 182/199

DS13196 - Rev 6

STM32H7B0xB

UFBGA(176+25) package information

Table 131. UFBGA(176+25) - Mechanical data

Symbol b

D

D1

E

E1

A (2)

A1

A2

A3

A4 e

F ddd eee

(3)

fff

(4)

Min.

-

0.050

-

-

-

0.240

9.850

-

9.850

-

-

-

-

-

millimeters

Typ.

-

0.080

0.450

0.130

0.320

0.290

10.000

9.100

10.000

9.100

0.650

0.450

-

-

-

Max.

0.600

0.110

-

-

-

0.340

10.150

-

10.150

-

-

-

0.080

0.015

0.050

Min.

-

0.0020

-

-

-

0.0094

0.3878

-

0.3878

-

-

-

-

-

inches

Typ.

-

0.0031

0.0177

0.0051

0.0126

0.0114

0.03937

0.3583

0.03937

0.3583

0.0256

0.0177

-

-

-

(1)

Max.

0.0236

0.0043

-

-

-

0.0134

0.3996

-

0.3996

-

-

-

0.0031

0.0059

0.0020

1. Values in inches are converted from mm and rounded to four decimal digits.

2. Ultra thin profile: 0.50 < A Max \u0001 0.65mm / Fine pitch: e < 1.00mm. The total profile height (Dim.A) is measured from the seating plane “C” to the top of the component.

3. The tolerance of position that controls the location of the pattern of balls with respect to datum A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datum A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.

4. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained entirely in the respective zone eee above The axis of each ball must lie simultaneously in both tolerance zones.

Figure 89. UFBGA(176+25) - Recommended footprint

Dpad

Dsm

page 183/199

7.6.1

STM32H7B0xB

Thermal characteristics

Table 132. UFBGA(176+25) - Recommended PCB design rules (0.65 mm pitch BGA)

Dimension

Pitch

Dpad

Dsm

Stencil opening

Stencil thickness

Pad trace width

Recommended values

0.65 mm

0.300 mm

0.400 mm typ. (depends on the soldermask registration tolerance)

0.300 mm aperture diameter

Between 0.100 mm and 0.125 mm

0.100 mm

Device marking for UFBGA176+25

The following figure gives an example of topside marking versus pin 1 position identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.

Figure 90. UFBGA176+25 marking example (package top view)

Product identification (1)

STM32H7B0

IBK6Q

Ball 1 indentifier

Date code

Y WW

Revision code

7.7

1.

Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

Thermal characteristics

The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation:

T

J max = T

A max + (P

D max × Θ

JA

)

DS13196 - Rev 6 page 184/199

7.7.1

STM32H7B0xB

Thermal characteristics

Where:

•

•

•

•

T

A max is the maximum ambient temperature in °C,

Θ

JA

is the package junction-to-ambient thermal resistance, in °C/W,

P

D max is the sum of P

INT max and P

I/O max (P

D max = P

INT max + P

I/O max),

P

INT max is the product of I

DD

and V

DD

, expressed in Watts. This is the maximum chip internal power.

P

I/O max represents the maximum power dissipation on output pins where:

P

I/O max = Σ (V

OL

× I

OL

) + Σ((V

DD

– V

OH

) × I

OH

), taking into account the actual V

OL

/ I

OL

and V

OH

/ I

OH

of the I/Os at low and high level in the application.

Symbol

Θ

JA

Θ

JB

Θ

JC

Definition

Thermal resistance junction-ambiant

Thermal resistance junction-board

Thermal resistance junction-case

Table 133. Thermal characteristics

Parameter

Thermal resistance junction-ambient LQFP64 - 10 x 10 mm /0.5 mm pitch

Thermal resistance junction-ambient LQFP100 - 14 x 14 mm /0.5 mm pitch

Thermal resistance junction-ambient LQFP144 - 20 x 20 mm /0.5 mm pitch

Thermal resistance junction-ambient LQFP176 - 24 x 24 mm /0.5 mm pitch value unit

48.8

47.4

46

43.6

Thermal resistance junction-ambient UFBGA169 - 7 x 7 mm /0.5 mm pitch

41.4

Thermal resistance junction-ambient UFBGA176+25 - 10 x 10 mm /0.65

mm pitch

44.4

Thermal resistance junction-board LQFP64 - 10 x 10 mm /0.5 mm pitch 37.2

Thermal resistance junction-board LQFP100 - 14 x 14 mm /0.5 mm pitch

Thermal resistance junction-board LQFP144 - 20 x 20 mm /0.5 mm pitch

39.2

41.3

Thermal resistance junction-board LQFP176 - 24 x 24 mm /0.5 mm pitch

40.2

Thermal resistance junction-board UFBGA169 - 7 x 7 mm /0.5 mm pitch 15.3

Thermal resistance junction-board UFBGA176+25 - 10 x 10 mm /0.65

mm pitch

Thermal resistance junction-case LQFP64 - 10 x 10 mm /0.5 mm pitch

25

13

Thermal resistance junction-case LQFP100 - 14 x 14 mm /0.5 mm pitch 12.8

Thermal resistance junction-case LQFP144 - 20 x 20 mm /0.5 mm pitch 12.6

Thermal resistance junction-case LQFP176 - 24 x 24 mm /0.5 mm pitch 11.5

Thermal resistance junction-case UFBGA169 - 7 x 7 mm /0.5 mm pitch 19.9

Thermal resistance junction-case UFBGA176+25 - 10 x 10 mm /0.65

mm pitch

18.9

°C/W

°C/W

°C/W

•

•

Reference documents

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air).

Available from www.jedec.org.

For information on thermal management, refer to application note “Thermal management guidelines for

STM32 32-bit Arm Cortex MCUs applications” (AN5036) available from www.st.com

.

DS13196 - Rev 6 page 185/199

8

STM32H7B0xB

Ordering information

Ordering information

Example: STM32

Device family

STM32 = Arm-based 32-bit microcontroller

H 7B0

Product type

H = High performance

Device subfamily

7B0 = STM32H7B0 Value line with cryptographic accelerator

Z

Pin count

R = 64 pins

V = 100 pins/balls

Z = 144 pins

A = 169 balls

I = 176 or 176 + 25 pins/balls

Flash memory size

B = 128 Kbytes

Package

T = LQFP ECOPACK2

K = UFBGA 0.65 mm pitch ECOPACK2

I = UFBGA 0.5 mm pitch ECOPACK2

B T 6 Q TR

Temperature range

6 = Industrial temperature range, –40 to 85 °C

Option

Q = with SMPS

Blank = without SMPS

Packing

TR = tape and reel

No character = tray or tube

For a list of available options (such as speed and package) or for further information on any aspect of this device, contact your nearest ST sales office.

DS13196 - Rev 6 page 186/199

STM32H7B0xB

Revision history

Date

20-Dec-2019

27-Apr-2020

08-Jul-2020

Revision

1

2

3

Table 134. Document revision history

Changes

Initial release.

Updated Octo-SPI interface in

Table 1. STM32H7B0xB features and peripheral counts

.

Updated Figure 2. Power-up/power-down sequence in

Section 6.1.6 Power supply scheme .

Updated HSLV feature description in

Section 3.8 General-purpose input/outputs

(GPIOs) .

In Section 5 Pin descriptions : updated

Table 6. Legend/abbreviations used in the pinout table ; changed SPDIFRX into SPDIFRX1 and updated all SPDIFRX1

pin names.

Updated Table 17. Voltage characteristics to add V

REF+

in the list of external main supply voltage.

Removed clock frequencies from

Table 20. General operating conditions

and added new

Table 21. Maximum allowed clock frequencies .

Changed condition for t

RSTTEMPO

characteristics

.

in Table 27. Reset and power control block

Added I

DD50USB

in Table 30. USB regulator characteristics .

Updated Table 38. Typical current consumption in System Stop mode

, added

Table 39. Typical current consumption RAM shutoff in Stop mode

, and added

IWDG and changed SPDIFRX into SPDIFRX1 in Table 42. Peripheral current consumption in Run mode

.

Table 56. Flash memory programming : updated t

ME

description and unit.

In the whole

Section 6.3.18 FMC characteristics , replaced sentence "the

T

KERCK

is the fmc_ker_ck clock period" by "the T fmc_ker_ck

is the kernel clock period".

Section 6.3.19 Octo-SPI interface characteristics : added parameter

measurement conditions, updated

Table 87. OCTOSPI characteristics in SDR mode

and Table 88. OCTOSPI characteristics in DTR mode (with DQS)/Octal and Hyperbus

, updated

Figure 42. OctoSPI Hyperbus clock

,

Figure 43. OctoSPI

Hyperbus read and Figure 44. OctoSPI Hyperbus write .

Updated Figure 48. Power supply and reference decoupling (V

REF+ not connected to V

DDA

)

, note 1.

and note

1.

.

Section 6.3.30 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics

, Section 6.3.31 Camera interface (DCMI) timing

specificationsSection 6.3.33 LCD-TFT controller (LTDC) characteristics

,

Section 6.3.36.2 USART interface characteristics

, Section 6.3.36.3 SPI interface characteristics ,

Section 6.3.36.4 I2S Interface characteristics

,

Section 6.3.36.5 SAI characteristics ,

Section 6.3.36.7 SD/SDIO MMC card host interface (SDMMC) characteristics

,

Section 6.3.36.8 USB

OTG_FS characteristics ,

Section 6.3.36.9 USB OTG_HS characteristics ,

Section 6.3.36.10 JTAG/SWD interface characteristics : changed VOS level to

VOS0 in the parameter measurement conditions.

Updated note related to ULPI interface availability on packages that do not

feature PC2 and PC3 I/Os in Table 1. STM32H7B0xB features and peripheral counts

.

Updated Table 18. Current characteristics , Table 19. Thermal characteristics

and

Figure 13. Current consumption measurement scheme .

DS13196 - Rev 6 page 187/199

DS13196 - Rev 6

Date

16-Sep-2020

28-Sep-2020

04-May-2021

STM32H7B0xB

Revision

4

5

6

Changes

Updated Figure 12. Power supply scheme

. Added note to V

REFINT

in

Table 28. Embedded reference voltage .Added

Table 31. Inrush current and inrush electric charge characteristics for LDO and SMPS

. Updated

Table 44. Low-power mode wakeup timings ,

Table 32. Typical and maximum current consumption in Run mode, code with data processing running from ITCM, regulator ON

and Table 33. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory, cache ON

.

Updated Table 66. Output timing characteristics (HSLV OFF)

and

Table 67. Output timing characteristics (HSLV ON)

.

Updated Table 60. ESD absolute maximum ratings .

Added notes related to performance degradation at VOS1 in

Section 6.3.18 FMC characteristics ,

Section 6.3.19 Octo-

SPI interface characteristics ,

Section 6.3.32 PSSI interface characteristics

, Section 6.3.33 LCD-TFT controller (LTDC) characteristics

,

Section 6.3.36.2 USART interface characteristics

, Section 6.3.36.3 SPI interface characteristics ,

Section 6.3.36.4 I2S Interface characteristics

,

Section 6.3.36.5 SAI characteristics ,

Section 6.3.36.6 MDIO characteristics

, Section 6.3.36.7 SD/SDIO MMC card host interface

(SDMMC) characteristics

,

Section 6.3.36.9 USB OTG_HS characteristics

and Section 6.3.36.10 JTAG/SWD interface characteristics

. Updated F

(CLK) measurement conditions in

Table 87. OCTOSPI characteristics in SDR mode

and Table 88. OCTOSPI characteristics in DTR mode (with DQS)/Octal and

Hyperbus

.

Added

Figure 45. ADC conversion timing diagram .

Added

Section 6.3.32 PSSI interface characteristics

.

Updated Figure 57. USART timing diagram in Master mode

and

Figure 58. USART timing diagram in Slave mode

.

Added note related to ULPI transceivers operating at 1.8 V in

Table 122. Dynamics characteristics: USB ULPI .

Updated VDDMMC separate supply pad in

Section 2 Description .

In Section 3.31 True random number generator (RNG) , changed "random

number generator" in "true random number generator" and description updated.

Updated Figure 12. Power supply scheme

and

Section 6.3.2 VCAP external capacitor

.

Added V

BAT

in

Section 6.3.1 General operating conditions

.

Updated High-speed external user clock generated from an external source

and

Low-speed external user clock generated from an external source .

Added reference to application note AN4899 in

Section 6.3.16 I/O port characteristics

.

Updated DuCyCKOUT in Table 105. DFSDM measured timing 1.62-3.6 V

Updated Figure 88. UFBGA(176+25) - Outline

and

Table 131. UFBGA(176+25) -

Mechanical data

.

Updated V

HSEL

characteristics

.

maximum value in

Table 45. High-speed external user clock

Added indication that patents apply to the devices in

Section Features

.

Added reference to errata sheet in Section 1 Introduction .

Updated WKUP signals in Figure 1. STM32H7B0xB block diagram and in

Table 7. STM32H7B0xB pin/ball definition .

Updated Section 3.40 Serial peripheral interfaces (SPI)/integrated interchip sound interfaces (I2S)

.

Added note to TRIM parameter in Table 50. HSI oscillator characteristics .

Extended

Figure 46. ADC accuracy characteristics to both ADC resolutions and

updated Figure 47. Typical connection diagram using the ADC .

Replace 110 °C by 130 °C in Table 97. Analog temperature sensor calibration values

.

page 188/199

DS13196 - Rev 6

Date

STM32H7B0xB

Revision Changes

Updated t su(ADV-CLKH)

, t h(CLKH-ADV)

, t su(NWAIT-CLKH)

and t h(CLKH-NWAIT)

minimum

values in Table 9

. Updated t su(DV-CLKH)

, t h(CLKH-DV)

, t

(NWAIT-CLKH)

and t h(CLKH-

NWAIT)

minimum values in

Table 79. Synchronous non-multiplexed NOR/PSRAM read timings

. Updated t su(SDCLKH _Data)

and t h(SDCLKH _Data)

minimum values in

Table 83. SDRAM read timings . Updated t

su(SDCLKH_Data)

and t h(SDCLKH_Data)

minimum values in Table 84. LPSDRAM read timings

.

•

•

•

Section 6.3.19 Octo-SPI interface characteristics :

Updated t

S(IN)/

/t

H(IN)

conditions and minimum values in Table 87. OCTOSPI characteristics in SDR mode

and updated Figure 40. OctoSPI timing diagram - SDR mode

.

Updated Table 88. OCTOSPI characteristics in DTR mode (with DQS)/

Octal and Hyperbus and

Figure 41. OctoSPI timing diagram - DTR mode

.

Updated Figure 42. OctoSPI Hyperbus clock , Figure 43. OctoSPI Hyperbus read and Figure 44. OctoSPI Hyperbus write .

•

•

Table 115. SPI dynamic characteristics :

Changed t su(MI)

and t h(MI)

minimum values in Master mode.

Removed t w(SCKH)

, t w(SCKL)

.

•

•

Table 119. Dynamics characteristics: SDMMC characteristics, V

DD

=2.7 to 3.6 V

:

Modified t mode.

ISU

and t

IH

minimum values for CMD/ D inputs in High-speed

Modified t

ISUD

and t

IH

minimum values for CMD/ D inputs in Default mode.

•

•

Table 120. Dynamics characteristics: eMMC characteristics VDD=1.71V to 1.9V

:

Removed SDIO_CK/f

PCLK2

frequency ratio.

Modified t

ISU

and t

IH

minimum values in CMD, D inputs (referenced to CK) in eMMC mode.

•

•

•

Section 7.5 UFBGA169 package information :

Added note 2 below

Updated

Figure 85. UFBGA169 - Outline

Table 129. UFBGA169 - Mechanical data

Removed note related to non-solder mask below

Recommended footprint .

.

.

Figure 86. UFBGA169 -

•

•

Section 7.6 UFBGA(176+25) package information :

Added note 2 below

Updated

Figure 88. UFBGA(176+25) - Outline .

Figure 89. UFBGA(176+25) - Recommended footprint

.

page 189/199

STM32H7B0xB

Contents

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.1

Arm ® Cortex ® -M7 with FPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.2

Memory protection unit (MPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.3

Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.3.1

3.3.2

Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Secure access mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.3.3

Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.4

Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.5

Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.5.1

3.5.2

3.5.3

3.5.4

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Voltage regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

SMPS step-down converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.6

Low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.7

Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.7.1

3.7.2

Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.8

General-purpose input/outputs (GPIOs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.9

Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.10

DMA controllers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.11

Chrom-ART Accelerator (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.12

Chrom-GRC™ (GFXMMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.13

Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.14

Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.15

Cyclic redundancy check calculation unit (CRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.16

Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.17

Octo-SPI memory interface (OCTOSPI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.18

Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.19

Analog temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.20

Digital temperature sensor (DTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.21

V

BAT

operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.22

Digital-to-analog converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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3.23

Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.24

Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.25

Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.26

Digital filter for sigma-delta modulators (DFSDM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.27

Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.28

Parallel synchronous slave interface (PSSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.29

LCD-TFT display controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.30

JPEG codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.31

Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.32

Cryptographic acceleration (CRYPT and HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.33

On-the-fly decryption engine (OTFDEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.34

Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.34.1

Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.34.2

General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.34.3

Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.34.4

Low-power timers (LPTIM1, LPTIM2, LPTIM3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.34.5

Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.34.6

Window watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.34.7

SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.35

Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.36

Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.37

Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.38

Universal synchronous/asynchronous receiver transmitter (USART) . . . . . . . . . . . . . . . . . . . 29

3.39

Low-power universal asynchronous receiver transmitter (LPUART) . . . . . . . . . . . . . . . . . . . 30

3.40

Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . . . . . . . . . . . . . . . . 30

3.41

Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.42

SPDIFRX receiver interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.43

Single wire protocol master interface (SWPMI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.44

Management data input/output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.45

SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.46

Controller area network (FDCAN1, FDCAN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.47

Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.48

High-definition multimedia interface (HDMI) - consumer electronics control (CEC) . . . . . . . 33

3.49

Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

5 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

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Contents

6 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

6.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

6.1.6

6.1.7

Minimum and maximum values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.2

Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.3

Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

6.3.6

6.3.7

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

SMPS step-down converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Embedded reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 74

Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

6.3.8

6.3.9

Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

6.3.10

Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

6.3.11

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

6.3.12

Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

6.3.13

EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

6.3.14

Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

6.3.15

I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.3.16

I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.3.17

NRST pin characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

6.3.18

FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

6.3.19

Octo-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

6.3.20

Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

6.3.21

16-bit ADC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

6.3.22

DAC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

6.3.23

Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

6.3.24

Temperature sensor characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

6.3.25

Digital temperature sensor characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

6.3.26

Temperature and VBAT monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

6.3.27

Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

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Contents

6.3.28

Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

6.3.29

Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

6.3.30

Digital filter for Sigma-Delta Modulators (DFSDM) characteristics. . . . . . . . . . . . . . . . . . 143

6.3.31

Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

6.3.32

PSSI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

6.3.33

LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

6.3.34

Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

6.3.35

Low-power timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

6.3.36

Communication interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

7 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

7.1

LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

7.1.1

Device marking for LQFP64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

7.2

LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

7.2.1

LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

7.3

LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

7.3.1

LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

7.4

LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176

7.4.1

Device marking for LQFP176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

7.5

UFBGA169 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179

7.5.1

Device marking for UFBGA169 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

7.6

UFBGA(176+25) package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

7.6.1

Device marking for UFBGA176+25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

7.7

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

7.7.1

Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

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List of tables

List of tables

Table 1. STM32H7B0xB features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. System vs domain low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 3. Overview of low-power mode monitoring pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 5. USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 6. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 7. STM32H7B0xB pin/ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 8. Port A alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 9. Port B alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 10. Port C alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 11. Port D alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 12. Port E alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 13. Port F alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 14. Port G alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 15. Port H alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 16. Port I alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 17. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 18. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 19. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 20. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 21. Maximum allowed clock frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 22. Supply voltage and maximum frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 23. VCAP operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 24. Characteristics of SMPS step-down converter external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 25. SMPS step-down converter characteristics for external usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 26. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 27. Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 28. Embedded reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 29. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 30. USB regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 31. Inrush current and inrush electric charge characteristics for LDO and SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 32. Typical and maximum current consumption in Run mode, code with data processing running from ITCM, regulator

ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 33. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory, cache ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 34. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory, cache OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 35. Typical consumption in Run mode and corresponding performance versus code position . . . . . . . . . . . . . . . . . 80

Table 36. Typical current consumption in Autonomous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 37. Typical current consumption in Sleep mode, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 38. Typical current consumption in System Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 39. Typical current consumption RAM shutoff in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 40. Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 41. Typical and maximum current consumption in V

BAT

mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 42. Peripheral current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 43. Peripheral current consumption in Stop, Standby and V

BAT

mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 44. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 45. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 46. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 47. 4-50 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 48. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 49. HSI48 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 50. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

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List of tables

Table 51. CSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 52. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 53. PLL characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 54. PLL characteristics (medium VCO frequency range). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 55. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 56. Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 57. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 58. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 59. EMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 60. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 61. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 62. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 63. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 64. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8 . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 65. Output voltage characteristics for PC13, PC14, PC15 and PI8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 66. Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 67. Output timing characteristics (HSLV ON). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 68. NRST pin characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 69. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 70. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 71. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 72. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 73. Asynchronous multiplexed PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

Table 74. Asynchronous multiplexed PSRAM/NOR read - NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

Table 75. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

Table 76. Asynchronous multiplexed PSRAM/NOR write - NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

Table 77. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

Table 78. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

Table 79. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Table 80. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

Table 81. Switching characteristics for NAND Flash memory read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

Table 82. Switching characteristics for NAND Flash write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 83. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 84. LPSDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 85. SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 86. LPSDR SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 87. OCTOSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 88. OCTOSPI characteristics in DTR mode (with DQS)/Octal and Hyperbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 89. Delay Block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 90. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 91. Minimum sampling time vs R

AIN

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 92. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 93. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 94. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Table 95. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Table 96. Analog temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Table 97. Analog temperature sensor calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 98. Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 99. V

BAT

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 100. V

BAT

charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 101. Temperature monitoring characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 102. Voltage booster for analog switch characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 103. COMP characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 104. Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Table 105. DFSDM measured timing 1.62-3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

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List of tables

Table 106. DCMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Table 107. PSSI transmit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Table 108. PSSI receive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Table 109. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Table 110. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 111. LPTIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 112. Minimum i2c_ker_ck frequency in all I 2 C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 113. I 2 C analog filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 114. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 115. SPI dynamic characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 116. I 2 S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Table 117. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Table 118. MDIO Slave timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Table 119. Dynamics characteristics: SDMMC characteristics, V

DD

=2.7 to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Table 120. Dynamics characteristics: eMMC characteristics VDD=1.71V to 1.9V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Table 121. Dynamics characteristics: USB OTG_FS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 122. Dynamics characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 123. Dynamics JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 124. Dynamics SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 125. LQFP64 pin - Mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 126. LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 127. LQFP144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Table 128. LQFP176 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 129. UFBGA169 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Table 130. UFBGA169 - recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 131. UFBGA(176+25) - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table 132. UFBGA(176+25) - Recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Table 133. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Table 134. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

DS13196 - Rev 6 page 196/199

STM32H7B0xB

List of figures

List of figures

Figure 1. STM32H7B0xB block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 2. Power-up/power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 3. STM32H7B0xB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 4. LQFP64 (STM32H7B0xB without SMPS) pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 5. LQFP100 (STM32H7B0xB without SMPS) pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 6. LQFP144 (STM32H7B0xB without SMPS) pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 7. LQFP176 (STM32H7B0xB without SMPS) pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 8. UFBGA169 (STM32H7B0xB with SMPS) ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 9. UFBGA176+25 (STM32H7B0xB with SMPS) ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 10. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 12. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 13. Current consumption measurement scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 14. External capacitor C

EXT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 15. SMPS efficicency vs load current in Run, Sleep and Stop mode with SVOS3 MR mode, T

J

= 30 °C. . . . . . . . . 71

Figure 16. SMPS efficiency vs load current in Run, Sleep and Stop mode with SVOS3 MR mode, T

J

= 130 °C . . . . . . . . 71

Figure 17. SMPS efficiency vs load current in Stop and DStop modes (SVOS3 LP mode, SVOS4, SVOS5), T

J

= 30 °C . . 72

Figure 18. SMPS efficiency vs load current in Stop and DStop modes (SVOS3 LP mode, SVOS4, SVOS5), T

J

= 130 °C . 72

Figure 19. SMPS efficiency vs load current in Stop and DStop2 modes (SVOS3 LP mode, SVOS4, SVOS5), T

J

= 30 °C . 73

Figure 20. SMPS efficiency vs load current in Stop and DStop2 modes (SVOS3 LP mode, SVOS4, SVOS5), T

J

= 130 °C. 73

Figure 21. High-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 22. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 23. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 24. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 25. V

IL

/V

IH

for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 26. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 27. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 28. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 29. Asynchronous multiplexed PSRAM/NOR read waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

Figure 30. Synchronous multiplexed NOR/PSRAM read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

Figure 31. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

Figure 32. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Figure 33. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

Figure 34. NAND controller waveforms for read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

Figure 35. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

Figure 36. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

Figure 37. NAND controller waveforms for common memory write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

Figure 38. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 39. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 40. OctoSPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 41. OctoSPI timing diagram - DTR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure 42. OctoSPI Hyperbus clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 43. OctoSPI Hyperbus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 44. OctoSPI Hyperbus write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 45. ADC conversion timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 46. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 47. Typical connection diagram using the ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 48. Power supply and reference decoupling (V

REF+ not connected to V

DDA

). . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 49. Power supply and reference decoupling (V

REF+ connected to V

DDA

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure 50. 12-bit buffered /non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 51. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Figure 52. DCMI timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

DS13196 - Rev 6 page 197/199

STM32H7B0xB

List of figures

Figure 53. PSSI timing diagram in Transmit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Figure 54. PSSI timing diagram in Receive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Figure 55. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Figure 56. LCD-TFT vertical timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Figure 57. USART timing diagram in Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Figure 58. USART timing diagram in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Figure 59. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Figure 60. SPI timing diagram - slave mode and CPHA = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Figure 61. SPI timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Figure 62. I 2 S slave timing diagram (Philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Figure 63. I

2

S master timing diagram (Philips protocol)

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Figure 64. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Figure 65. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Figure 66. MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Figure 67. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Figure 68. SD default mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Figure 69. DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Figure 70. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Figure 71. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 72. SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 73. LQFP64 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 74. LQFP64 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Figure 75. LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Figure 76. LQFP100 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Figure 77. LQFP100 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 78. LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Figure 79. LQFP144 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 80. LQFP144 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 81. LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 82. LQFP176 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Figure 83. LQFP176 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Figure 84. LQFP176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Figure 85. UFBGA169 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Figure 86. UFBGA169 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Figure 87. UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Figure 88. UFBGA(176+25) - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Figure 89. UFBGA(176+25) - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Figure 90. UFBGA176+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

DS13196 - Rev 6 page 198/199

STM32H7B0xB

IMPORTANT NOTICE – PLEASE READ CAREFULLY

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DS13196 - Rev 6 page 199/199