This document provides electrical specifications, pin assignments, and package diagrams for the SPC564A80 series of microcontroller units (MCUs). For functional characteristics, refer to the SPC564A80 Microcontroller Reference Manual.

1.2 Description

The microcontroller’s e200z4 host processor core is built on Power Architecture technology and designed specifically for embedded applications. In addition to the Power Architecture technology, this core supports instructions for digital signal processing (DSP).

The SPC564A80 has two levels of memory hierarchy consisting of 8 KB of instruction cache, backed by 192 KB on-chip SRAM and 4 MB of internal flash memory. The

SPC564A80 includes an external bus interface, and also a calibration bus that is only accessible when using the calibration tools.

This document describes the features of the SPC564A80 and highlights important electrical and physical characteristics of the device.

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Table 2

summarizes the SPC564A80 and compares it to the SPC563M64.

Table 2.

DMA

DMA Nexus

Serial eSCI_A eSCI_B eSCI_C

CAN

CAN_A

CAN_B

CAN_C

SPI

SPC564A80, SPC563M64 and SPC564A70 comparison

Feature SPC564A80 SPC563M64

Process

Core

SIMD

VLE

Cache

Non-Maskable Interrupt (NMI)

MMU

MPU

Crossbar switch

Core performance

Windowing software watchdog

Core Nexus

SRAM

Flash

Flash fetch accelerator

External bus

Calibration bus

SPC564A70 e200z4

90 nm e200z3

Yes

Yes e200z4

8 KB instruction

24 entry

16 entry



0–150 MHz

Class 3+

192 KB

4 MB



256-bit

16-bit (incl 32-bit muxed)

64 ch.

NMI & Critical Interrupt

16 entry



0–80 MHz

8 KB instruction

24 entry

16 entry



0–150 MHz

Yes

Class 2+

94 KB

1.5 MB

Class 3+

128 KB

2 MB

16-bit

32 ch.

None

Yes (MSC Uplink)



128-bit

None

16-bit (incl 32-bit muxed)

64 ch.

Yes

64 buf

Yes (MSC Uplink)

64 buf

32 buf

Yes

64 buf

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Table 2.

SPC564A80, SPC563M64 and SPC564A70 comparison (continued)

Feature SPC564A80 SPC563M64

Micro Second Channel (MSC) bus downlink

DSPI_A

DSPI_B

DSPI_C

DSPI_D

FlexRay

System timers eMIOS eTPU

ADC

Code memory

Data memory

Interrupt controller

ADC_A

ADC_B

Temp sensor

Variable gain amp.

Decimation filter

Sensor diagnostics

CRC

FMPLL

VRC

Supplies

Low-power modes

Packages

Yes

24 ch.

486 ch.

40 ch.

Yes

(1)

5 V, 3.3 V

(2)

LQFP176

(4)

LBGA208

(4)

PBGA

Known Good Die (KGD)

496-pin CSP

(5)

Yes (with LVDS)

5 PIT channels

4 STM channels

1 Software Watchdog

16 ch.

32 ch. eTPU2

14 KB

3 KB

307 ch.

34 ch.

Yes

5 V, 3.3 V

(3)

Stop Mode

Slow Mode

LQFP100

LQFP144

LQFP176

LBGA208

496-pin CSP

(5)

199 interrupt vectors are reserved.

5 V single supply only for LQFP176.

5 V single supply only for LQFP144 and LQFP100.

Pinout compatible with STMicroelectronics’ SPC563M64 devices.

For ST calibration tool only.

SPC564A70

Yes

24 ch.

486 ch.

(1)

40 ch.

Yes

LBGA208

PBGAKnown Good

Die (KGD)

496-pin CSP

(5)

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Introduction

●

SPC564A80 feature list

●

150 MHz e200z4 Power Architecture core

– Variable length instruction encoding (VLE)

– Superscalar architecture with 2 execution units

– Up to 2 integer or floating point instructions per cycle

– Up to 4 multiply and accumulate operations per cycle

Memory organization

– 4 MB on-chip flash memory with ECC and Read While Write (RWW)

– 192 KB on-chip SRAM with standby functionality (32 KB) and ECC

– 8 KB instruction cache (with line locking), configurable as 2- or 4-way

– 14 + 3 KB eTPU code and data RAM

– 5



4 crossbar switch (XBAR)

– 24-entry MMU

– External Bus Interface (EBI) with slave and master port

Fail Safe Protection

– 16-entry Memory Protection Unit (MPU)

– CRC unit with 3 sub-modules

– Junction temperature sensor

Interrupts

– Configurable interrupt controller (with NMI)

– 64-channel DMA

Serial channels

– 3

 eSCI

– 3



DSPI (2 of which support downstream Micro Second Channel [MSC])

– 3



FlexCAN with 64 messages each

– 1



FlexRay module (V2.1) up to 10 Mbit/s with dual or single channel and 128 message objects and ECC

 eMIOS: 24 unified channels

 eTPU2 (second generation eTPU)

– 32 standard channels

– 1

 reaction module (6 channels with three outputs per channel)

2 enhanced queued analog-to-digital converters (eQADCs)

– Forty 12-bit input channels (multiplexed on 2 ADCs); expandable to 56 channels with external multiplexers

– 6 command queues

– Trigger and DMA support

– 688 ns minimum conversion time

On-chip CAN/SCI/FlexRay Bootstrap loader with Boot Assist Module (BAM)

Nexus

– Class 3+ for the e200z4 core

– Class 1 for the eTPU

JTAG (5-pin)

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Development Trigger Semaphore (DTS)

– Register of semaphores (32-bits) and an identification register

– Used as part of a triggered data acquisition protocol

– EVTO pin is used to communicate to the external tool

Clock generation

– On-chip 4–40 MHz main oscillator

– On-chip FMPLL (frequency-modulated phase-locked loop)

Up to 120 general purpose I/O lines

– Individually programmable as input, output or special function

– Programmable threshold (hysteresis)

Power reduction mode: slow, stop and stand-by modes

Flexible supply scheme

– 5 V single supply with external ballast

– Multiple external supply: 5 V, 3.3 V and 1.2 V

Packages

– LQFP176

– LBGA208

– PBGA324

– Known Good Die (KGD)

– 496-pin CSP (calibration tool only)

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1.5.2

●

SPC564A80 devices have a high performance e200z448n3 core processor:

Dual issue, 32-bit Power Architecture embedded category CPU

Variable Length Encoding Enhancements

8 KB instruction cache: 2- or 4- way set associative instruction cache

Thirty-two 64-bit general purpose registers (GPRs)

Memory management unit (MMU) with 24-entry fully-associative translation look-aside buffer (TLB)

Harvard Architecture: Separate instruction bus and load/store bus

Vectored interrupt support

Non-maskable interrupt input

Critical Interrupt input

New ‘Wait for Interrupt’ instruction, to be used with new low power modes

Reservation instructions for implementing read-modify-write accesses

Signal processing extension (SPE) APU

Single Precision Floating point (scalar and vector)

Nexus Class 3+ debug

Process ID manipulation for the MMU using an external tool

Crossbar Switch (XBAR)

The XBAR multiport crossbar switch supports simultaneous connections between five master ports and four slave ports. The crossbar supports a 32-bit address bus width and a

64-bit data bus width.

The crossbar allows three concurrent transactions to occur from the master ports to any slave port but each master must access a different slave. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher priority master completes its transactions. Requesting masters are treated with equal priority and are granted access to a slave port in round-robin fashion, based upon the ID of the last master to be granted access. The crossbar provides the following features:

● 5 master ports

– CPU instruction bus

– CPU data bus

– eDMA

– FlexRay

– External Bus Interface

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4 slave ports

– Flash

– Calibration and EBI bus

– SRAM

– Peripheral bridge

32-bit internal address, 64-bit internal data paths

1.5.3 eDMA

●

The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data movements via 64 programmable channels, with minimal intervention from the host processor. The hardware micro-architecture includes a

DMA engine which performs source and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation is utilized to minimize the overall block size. The eDMA module provides the following features:

All data movement via dual-address transfers: read from source, write to destination

Programmable source and destination addresses, transfer size, plus support for enhanced addressing modes

Transfer control descriptor organized to support two-deep, nested transfer operations

An inner data transfer loop defined by a “minor” byte transfer count

An outer data transfer loop defined by a “major” iteration count

Channel activation via one of three methods:

– Explicit software initiation

– Initiation via a channel-to-channel linking mechanism for continuous transfers

– Peripheral-paced hardware requests (one per channel)

Support for fixed-priority and round-robin channel arbitration

Channel completion reported via optional interrupt requests

One interrupt per channel, optionally asserted at completion of major iteration count

Error termination interrupts optionally enabled

Support for scatter/gather DMA processing

Ability to suspend channel transfers by a higher priority channel

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The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems.

For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable.

When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority ceiling protocol for coherent accesses. By

Doc ID 15399 Rev 9

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1.5.5

Introduction providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource cannot preempt each other.

The INTC provides the following features:

●

9-bit vector addresses

Unique vector for each interrupt request source

Hardware connection to processor or read from register

Each interrupt source can assigned a specific priority by software

Preemptive prioritized interrupt requests to processor

ISR at a higher priority preempts executing ISRs or tasks at lower priorities

Automatic pushing or popping of preempted priority to or from a LIFO

Ability to modify the ISR or task priority to implement the priority ceiling protocol for accessing shared resources

● Low latency—three clocks from receipt of interrupt request from peripheral to interrupt request to processor

This device also includes a non-maskable interrupt (NMI) pin that bypasses the INTC and multiplexing logic.

Memory protection unit (MPU)

The Memory Protection Unit (MPU) provides hardware access control for all memory references generated in a device. Using preprogrammed region descriptors, which define memory spaces and their associated access rights, the MPU concurrently monitors all system bus transactions and evaluates the appropriateness of each transfer. Memory references with sufficient access control rights are allowed to complete; references that are not mapped to any region descriptor or have insufficient rights are terminated with a protection error response.

The MPU has these major features:

● Support for 16 memory region descriptors, each 128 bits in size

– Specification of start and end addresses provide granularity for region sizes from

32 bytes to 4 GB

– MPU is invalid at reset, thus no access restrictions are enforced

– Two types of access control definitions: processor core bus master supports the traditional {read, write, execute} permissions with independent definitions for supervisor and user mode accesses; the remaining non-core bus masters (eDMA,

FlexRay, and EBI

) support {read, write} attributes

●

– Automatic hardware maintenance of the region descriptor valid bit removes issues associated with maintaining a coherent image of the descriptor

– Alternate memory view of the access control word for each descriptor provides an efficient mechanism to dynamically alter the access rights of a descriptor only

(a)

– For overlapping region descriptors, priority is given to permission granting over access denying as this approach provides more flexibility to system software

Support for two XBAR slave port connections (SRAM and PBRIDGE)

– For each connected XBAR slave port (SRAM and PBRIDGE), MPU hardware monitors every port access using the pre-programmed memory region descriptors

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– An access protection error is detected if a memory reference does not hit in any memory region or the reference is flagged as illegal in all memory regions where it does hit. In the event of an access error, the XBAR reference is terminated with an error response and the MPU inhibits the bus cycle being sent to the targeted slave device

– 64-bit error registers, one for each XBAR slave port, capture the last faulting address, attributes, and detail information

1.5.6 FMPLL

●

The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 40 MHz crystal oscillator or external clock generator. Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication factor, output clock divider ratio are all software configurable. The PLL has the following major features:

Input clock frequency from 4 MHz to 40 MHz

Reduced frequency divider (RFD) for reduced frequency operation without forcing the

PLL to relock

● Three modes of operation

– Bypass mode with PLL off

●

– Bypass mode with PLL running (default mode out of reset)

– PLL normal mode

Each of the three modes may be run with a crystal oscillator or an external clock reference

Programmable frequency modulation

– Modulation enabled/disabled through software

– Triangle wave modulation up to 100 kHz modulation frequency

– Programmable modulation depth (0% to 2% modulation depth)

– Programmable modulation frequency dependent on reference frequency

●

Lock detect circuitry reports when the PLL has achieved frequency lock and continuously monitors lock status to report loss of lock conditions

Clock Quality Module

– Detects the quality of the crystal clock and causes interrupt request or system reset if error is detected

– Detects the quality of the PLL output clock; if error detected, causes system reset or switches system clock to crystal clock and causes interrupt request

Programmable interrupt request or system reset on loss of lock

Self-clocked mode (SCM) operation

1.5.7 SIU

The SPC564A80 SIU controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and the system reset operation. The reset configuration block contains the external pin boot configuration logic.

The pad configuration block controls the static electrical characteristics of I/O pins. The

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GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU.

The reset controller performs reset monitoring of internal and external reset sources, and drives the RSTOUT pin. Communication between the SIU and the e200z4 CPU core is via the crossbar switch. The SIU provides the following features:

● System configuration

– MCU reset configuration via external pins

●

– Pad configuration control for each pad

– Pad configuration control for virtual I/O via DSPI serialization

System reset monitoring and generation

– Power-on reset support

●

– Reset status register provides last reset source to software

– Glitch detection on reset input

– Software controlled reset assertion

External interrupt

– Rising or falling edge event detection

– Programmable digital filter for glitch rejection

– Critical Interrupt request

– Non-Maskable Interrupt request

●

GPIO

– Centralized control of I/O and bus pins

– Virtual GPIO via DSPI serialization (requires external deserialization device)

– Dedicated input and output registers for setting each GPIO and Virtual GPIO pin

Internal multiplexing

– Allows serial and parallel chaining of DSPIs

– Allows flexible selection of eQADC trigger inputs

– Allows selection of interrupt requests between external pins and DSPI

The SPC564A80 provides up to 4 MB of programmable, non-volatile, flash memory. The non-volatile memory (NVM) can be used to store instructions or data, or both. The flash module includes a Fetch Accelerator that optimizes the performance of the flash array to match the CPU architecture. The flash module interfaces the system bus to a dedicated flash memory array controller. For CPU ‘loads’, DMA transfers and CPU instruction fetch, it supports a 64-bit data bus width at the system bus port, and 128- and 256-bit read data interfaces to flash memory. The module contains a prefetch controller which prefetches sequential lines of data from the flash array into the buffers. Prefetch buffer hits allow no-wait responses.

The flash memory provides the following features:

● Supports a 64-bit data bus for instruction fetch, CPU loads and DMA access. Byte, halfword, word and doubleword reads are supported. Only aligned word and doubleword writes are supported.

● Fetch Accelerator

– Architected to optimize the performance of the flash

– Configurable read buffering and line prefetch support

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– Four-entry 256-bit wide line read buffer

– Prefetch controller

Hardware and software configurable read and write access protections on a per-master basis

Interface to the flash array controller pipelined with a depth of one, allowing overlapped accesses to proceed in parallel for interleaved or pipelined flash array designs

Configurable access timing usable in a wide range of system frequencies

Multiple-mapping support and mapping-based block access timing (0-31 additional cycles) usable for emulation of other memory types

Software programmable block program/erase restriction control

Erase of selected block(s)

Read page size of 128 bits (four words)

ECC with single-bit correction, double-bit detection

Program page size of 128 bits (four words) to accelerate programming

ECC single-bit error corrections are visible to software

Minimum program size is two consecutive 32-bit words, aligned on a 0-modulo-8 byte address, due to ECC

Embedded hardware program and erase algorithm

Erase suspend, program suspend and erase-suspended program

Shadow information stored in non-volatile shadow block

Independent program/erase of the shadow block

1.5.9 BAM

●

The BAM (Boot Assist Module) is a block of read-only memory that is programmed once by

ST and is identical for all SPC564A80 MCUs. The BAM program is executed every time the

MCU is powered-on or reset in normal mode. The BAM supports different modes of booting.

They are:

Booting from internal flash memory

●

Serial boot loading (A program is downloaded into RAM via eSCI or the FlexCAN and then executed)

Booting from external memory on external bus

●

The BAM also reads the reset configuration half word (RCHW) from internal flash memory and configures the SPC564A80 hardware accordingly. The BAM provides the following features:

●

Sets up MMU to cover all resources and mapping of all physical addresses to logical addresses with minimum address translation

Sets up MMU to allow user boot code to execute as either Power Architecture embedded category (default) or as VLE code

Location and detection of user boot code

Automatic switch to serial boot mode if internal flash is blank or invalid

Supports user programmable 64-bit password protection for serial boot mode

Supports serial bootloading via FlexCAN bus and eSCI using standard protocol

Supports serial bootloading via FlexCAN bus and eSCI with auto baud rate sensing

Supports serial bootloading of either Power Architecture code (default) or VLE code

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●

Supports booting from calibration bus interface

Supports censorship protection for internal flash memory

Provides an option to enable the core watchdog timer

Provides an option to disable the system watchdog timer

1.5.10 eMIOS

The eMIOS timer module provides the capability to generate or measure events in hardware.

The eMIOS module features include:

●

Twenty-four 24-bit wide channels

3 channels’ internal timebases can be shared between channels

1 Timebase from eTPU2 can be imported and used by the channels

Global enable feature for all eMIOS and eTPU timebases

Dedicated pin for each channel (not available on all package types)

●

Each channel (0–23) supports the following functions:

General-purpose input/output (GPIO)

Single-action input capture (SAIC)

Single-action output compare (SAOC)

Output pulse-width modulation buffered (OPWMB)

Input period measurement (IPM)

Input pulse-width measurement (IPWM)

Double-action output compare (DAOC)

Modulus counter buffered (MCB)

Output pulse width and frequency modulation buffered (OPWFMB)

1.5.11 eTPU2

The eTPU2 is an enhanced co-processor designed for timing control. Operating in parallel with the host CPU, the eTPU2 processes instructions and real-time input events, performs output waveform generation, and accesses shared data without host intervention.

Consequently, for each timer event, the host CPU setup and service times are minimized or eliminated. A powerful timer subsystem is formed by combining the eTPU2 with its own instruction and data RAM. High-level assembler/compiler and documentation allows customers to develop their own functions on the eTPU2.

SPC564A80 devices feature the second generation of the eTPU, called eTPU2.

Enhancements of the eTPU2 over the standard eTPU include:

● The Timer Counter (TCR1), channel logic and digital filters (both channel and the external timer clock input [TCRCLK]) now have an option to run at full system clock speed or system clock / 2.

●

Channels support unordered transitions: transition 2 can now be detected before transition 1. Related to this enhancement, the transition detection latches (TDL1 and

TDL2) can now be independently negated by microcode.

A new User Programmable Channel Mode has been added: the blocking, enabling, service request and capture characteristics of this channel mode can be programmed via microcode.

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Microinstructions now provide an option to issue Interrupt and Data Transfer requests selected by channel. They can also be requested simultaneously at the same instruction.

Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the entry point.

Channel digital filters can be bypassed.

●

The eTPU2 includes these distinctive features:

● 32 channels; each channel associated with one input and one output signal

– Enhanced input digital filters on the input pins for improved noise immunity

– Identical, orthogonal channels: each channel can perform any time function. Each time function can be assigned to more than one channel at a given time, so each signal can have any functionality.

– Each channel has an event mechanism which supports single and double action functionality in various combinations. It includes two 24-bit capture registers, two

24-bit match registers, 24-bit greater-equal and equal-only comparators.

●

– Input and output signal states visible from the host

2 independent 24-bit time bases for channel synchronization:

– First time base clocked by system clock with programmable prescale division from

2 to 512 (in steps of 2), or by output of second time base prescaler

– Second time base counter can work as a continuous angle counter, enabling angle based applications to match angle instead of time

– Both time bases can be exported to the eMIOS timer module

– Both time bases visible from the host

Event-triggered microengine:

– Fixed-length instruction execution in two-system-clock microcycle

– 14 KB of code memory (SCM)

– 3 KB of parameter (data) RAM (SPRAM)

– Parallel execution of data memory, ALU, channel control and flow control subinstructions in selected combinations

– 32-bit microengine registers and 24-bit wide ALU, with 1 microcycle addition and subtraction, absolute value, bitwise logical operations on 24-bit, 16-bit, or byte operands, single-bit manipulation, shift operations, sign extension and conditional execution

– Additional 24-bit Multiply/MAC/Divide unit which supports all signed/unsigned

Multiply/MAC combinations, and unsigned 24-bit divide. The MAC/Divide unit works in parallel with the regular microcode commands.

● Resource sharing features support channel use of common channel registers, memory and microengine time:

– Hardware scheduler works as a “task management” unit, dispatching event service routines by predefined, host-configured priority

– Automatic channel context switch when a “task switch” occurs, that is, one function thread ends and another begins to service a request from other channel: channelspecific registers, flags and parameter base address are automatically loaded for the next serviced channel

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– SPRAM shared between host CPU and eTPU2, supporting communication either between channels and host or inter-channel

– Hardware implementation of four semaphores support coherent parameter sharing between both eTPU engines

– Dual-parameter coherency hardware support allows atomic access to two parameters by host

Test and development support features:

– Nexus Class 1 debug, supporting single-step execution, arbitrary microinstruction execution, hardware breakpoints and watchpoints on several conditions

– Software breakpoints

– SCM continuous signature-check built-in self test (MISC - multiple input signature calculator), runs concurrently with eTPU2 normal operation

The reaction module provides the ability to modulate output signals to manage closed loop control without CPU assistance. It works in conjunction with the eQADC and eTPU2 to increase system performance by removing the CPU from the current control loop.

●

The reaction module has the following features:

Six reaction channels

Each channel output is a bus of three signals, providing ability to control 3 inputs.

Each channel can implement a peak and hold waveform, making it possible to implement up to six independent peak and hold control channels

Target applications include solenoid control for direct injection systems and valve control in automatic transmissions

1.5.13 eQADC

The enhanced queued analog to digital converter (eQADC) block provides accurate and fast conversions for a wide range of applications. The eQADC provides a parallel interface to two on-chip analog to digital converters (ADC), and a single master to single slave serial interface to an off-chip external device. Both on-chip ADCs have access to all the analog channels.

The eQADC prioritizes and transfers commands from six command conversion command

‘queues’ to the on-chip ADCs or to the external device. The block can also receive data from the on-chip ADCs or from an off-chip external device into the six result queues, in parallel, independently of the command queues. The six command queues are prioritized with

Queue_0 having the highest priority and Queue_5 the lowest. Queue_0 also has the added ability to bypass all buffering and queuing and abort a currently running conversion on either

ADC and start a Queue_0 conversion. This means that Queue_0 will always have a deterministic time from trigger to start of conversion, irrespective of what tasks the ADCs were performing when the trigger occurred. The eQADC supports software and external hardware triggers from other blocks to initiate transfers of commands from the queues to the on-chip ADCs or to the external device. It also monitors the fullness of command queues and result queues, and accordingly generates DMA or interrupt requests to control data movement between the queues and the system memory, which is external to the eQADC.

The ADCs also support features designed to allow the direct connection of high impedance acoustic sensors that might be used in a system for detecting engine knock. These features

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The eQADC also integrates a programmable decimation filter capable of taking in ADC conversion results at a high rate, passing them through a hardware low pass filter, then down-sampling the output of the filter and feeding the lower sample rate results to the result

FIFOs. This allows the ADCs to sample the sensor at a rate high enough to avoid aliasing of out-of-band noise; while providing a reduced sample rate output to minimize the amount

DSP processing bandwidth required to fully process the digitized waveform.

●

The eQADC provides the following features:

● Dual on-chip ADCs

– 2



12-bit ADC resolution

– Programmable resolution for increased conversion speed (12-bit, 10-bit, 8-bit)

12-bit conversion time: 938 ns (1 M sample/sec)

10-bit conversion time: 813 ns (1.2 M sample/second)

8-bit conversion time: 688 ns (1.4 M sample/second)

– Up to 10-bit accuracy at 500 KSample/s and 8-bit accuracy at 1 MSample/s

– Differential conversions

– Single-ended signal range from 0 to 5 V

– Variable gain amplifiers on differential inputs (



●

– Sample times of 2 (default), 8, 64 or 128 ADC clock cycles

– Provides time stamp information when requested

– Allows time stamp information relative to eTPU clock sources, such as an angle clock

– Parallel interface to eQADC CFIFOs and RFIFOs

– Supports both right-justified unsigned and signed formats for conversion results

40 single-ended input channels, expandable to 56 channels with external multiplexers

(supports four external 8-to-1 muxes)

8 channels can be used as 4 pairs of differential analog input channels

Differential channels include variable gain amplifier for improved dynamic range

Differential channels include programmable pull-up and pull-down resistors for biasing and sensor diagnostics (200 k



100 k



5 k



●

Additional internal channels for monitoring voltages (such as core voltage, I/O voltage,

LVI voltages, etc.) inside the device

An internal bandgap reference to allow absolute voltage measurements

Silicon die temperature sensor

– Provides temperature of silicon as an analog value

– Read using an internal ADC analog channel

– May be read with either ADC

2 Decimation Filters

– Programmable decimation factor (1 to 16)

– Selectable IIR or FIR filter

– Up to 4th order IIR or 8th order FIR

– Programmable coefficients

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●

– Saturated or non-saturated modes

– Programmable Rounding (Convergent; Two’s Complement; Truncated)

– Prefill mode to precondition the filter before the sample window opens

– Supports Multiple Cascading Decimation Filters to implement more complex filter designs

– Optional Absolute Integrators on the output of Decimation Filters

Full duplex synchronous serial interface to an external device

– Free-running clock for use by an external device

– Supports a 26-bit message length

Priority based queues

– Supports six queues with fixed priority. When commands of distinct queues are bound for the same ADC, the higher priority queue is always served first

– Queue_0 can bypass all prioritization, buffering and abort current conversions to start a Queue_0 conversion a deterministic time after the queue trigger

– Supports software and hardware trigger modes to arm a particular queue

– Generates interrupt when command coherency is not achieved

External hardware triggers

– Supports rising edge, falling edge, high level and low level triggers

– Supports configurable digital filter

1.5.14 DSPI

The deserial serial peripheral interface (DSPI) block provides a synchronous serial interface for communication between the SPC564A80 MCU and external devices. The DSPI supports pin count reduction through serialization and deserialization of eTPU and eMIOS channels and memory-mapped registers. The channels and register content are transmitted using a

SPI-like protocol. This SPI-like protocol is completely configurable for baud rate, polarity and phase, frame length, chip select assertion, etc. Each bit in the frame may be configured to serialize either eTPU channels, eMIOS channels or GPIO signals. The DSPI can be configured to serialize data to an external device that implements the Microsecond Bus protocol. There are three identical DSPI blocks on the SPC564A80 MCU. The DSPI pins support 5 V logic levels or Low Voltage Differential Signalling (LVDS) to improve high speed operation.

DSPI module features include:

● Selectable LVDS pads working at 40 MHZ for SOUT and SCK pins for DSPI_B and

DSPI_C

● 3 sources of serialized data: eTPU_A, eMIOS output channels and memory-mapped register in the DSPI

●

4 destinations for deserialized data: eTPU_A and eMIOS input channels, SIU external

Interrupt input request, memory-mapped register in the DSPI

32-bit DSI and TSB modes require 32 PCR registers, 32 GPO and GPI registers in the

SIU to select either GPIO, eTPU or eMIOS bits for serialization

● The DSPI Module can generate and check parity in a serial frame

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Introduction SPC564A74L7, SPC564A80B4, SPC564A80L7

1.5.15 eSCI

●

Three enhanced serial communications interface (eSCI) modules provide asynchronous serial communications with peripheral devices and other MCUs, and include support to interface to Local Interconnect Network (LIN) slave devices. Each eSCI block provides the following features:

Full-duplex operation

Standard mark/space non-return-to-zero (NRZ) format

13-bit baud rate selection

Programmable 8-bit or 9-bit, data format

Programmable 12-bit or 13-bit data format for Timed Serial Bus (TSB) configuration to support the Microsecond bus standard

Automatic parity generation

LIN support

– Autonomous transmission of entire frames

– Configurable to support all revisions of the LIN standard

– Automatic parity bit generation

– Double stop bit after bit error

– 10- or 13-bit break support

Separately enabled transmitter and receiver

Programmable transmitter output parity

2 receiver wake-up methods:

– Idle line wake-up

– Address mark wake-up

Interrupt-driven operation with flags

Receiver framing error detection

Hardware parity checking

1/16 bit-time noise detection

DMA support for both transmit and receive data

– Global error bit stored with receive data in system RAM to allow post processing of errors

1.5.16 FlexCAN

The SPC564A80 MCU includes three controller area network (FlexCAN) blocks. The

FlexCAN module is a communication controller implementing the CAN protocol according to

Bosch Specification version 2.0B. The CAN protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. Each FlexCAN module contains 64 message buffers.

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●

The FlexCAN modules provide the following features:

● Full Implementation of the CAN protocol specification, Version 2.0B

– Standard data and remote frames

– Extended data and remote frames

– Zero to eight bytes data length

– Programmable bit rate up to 1 Mbit/s

Content-related addressing

64 message buffers of zero to eight bytes data length

Individual Rx Mask Register per message buffer

Each message buffer configurable as Rx or Tx, all supporting standard and extended messages

Includes 1088 bytes of embedded memory for message buffer storage

Includes 256-byte memory for storing individual Rx mask registers

Full featured Rx FIFO with storage capacity for six frames and internal pointer handling

Powerful Rx FIFO ID filtering, capable of matching incoming IDs against 8 extended, 16 standard or 32 partial (8 bits) IDs, with individual masking capability

Selectable backwards compatibility with previous FlexCAN versions

Programmable clock source to the CAN Protocol Interface, either system clock or oscillator clock

Listen only mode capability

Programmable loop-back mode supporting self-test operation

3 programmable Mask Registers

Programmable transmit-first scheme: lowest ID, lowest buffer number or highest priority

Time Stamp based on 16-bit free-running timer

Global network time, synchronized by a specific message

Maskable interrupts

Warning interrupts when the Rx and Tx Error Counters reach 96

Independent of the transmission medium (an external transceiver is assumed)

Multi-master concept

High immunity to EMI

Short latency time due to an arbitration scheme for high-priority messages

Low power mode, with programmable wake-up on bus activity

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Introduction SPC564A74L7, SPC564A80B4, SPC564A80L7

1.5.17 FlexRay

●

The SPC564A80 includes one dual-channel FlexRay module that implements the FlexRay

Communications System Protocol Specification, Version 2.1 Rev A. Features include:

Single channel support

FlexRay bus data rates of 10 Mbit/s, 8 Mbit/s, 5 Mbit/s, and 2.5 Mbit/s supported

128 message buffers, each configurable as:

– Receive message buffer

– Single buffered transmit message buffer

●

– Double buffered transmit message buffer (combines two single buffered message buffer)

2 independent receive FIFOs

●

– 1 receive FIFO per channel

– Up to 255 entries for each FIFO

ECC support

The system timers include two distinct types of system timer:

●

Periodic interrupts/triggers using the Periodic Interrupt Timer (PIT)

Operating system task monitors using the System Timer Module (STM)

Periodic interrupt timer (PIT)

The PIT provides five independent timer channels, capable of producing periodic interrupts and periodic triggers. The PIT has no external input or output pins and is intended to provide system ‘tick’ signals to the operating system, as well as periodic triggers for eQADC queues.

Of the five channels in the PIT, four are clocked by the system clock and one is clocked by the crystal clock. This one channel is also referred to as Real-Time Interrupt (RTI) and is used to wake up the device from low power stop mode.

The following features are implemented in the PIT:

●

5 independent timer channels

Each channel includes 32-bit wide down counter with automatic reload

4 channels clocked from system clock

1 channel clocked from crystal clock (wake-up timer)

●

Wake-up timer remains active when System STOP mode is entered; used to restart system clock after predefined time-out period

Each channel optionally able to generate an interrupt request or a trigger event (to trigger eQADC queues) when timer reaches zero

System timer module (STM)

The System Timer Module (STM) is designed to implement the software task monitor as defined by AUTOSAR

(b)

. It consists of a single 32-bit counter, clocked by the system clock,

26/157 b.

AUTOSAR: AUTomotive Open System ARchitecture (see www.autosar.org)

Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Introduction and four independent timer comparators. These comparators produce a CPU interrupt when the timer exceeds the programmed value.

The following features are implemented in the STM:

●

One 32-bit up counter with 8-bit prescaler

Four 32-bit compare channels

Independent interrupt source for each channel

Counter can be stopped in debug mode

1.5.19 Software watchdog timer (SWT)

The Software Watchdog Timer (SWT) is a second watchdog module to complement the standard Power Architecture watchdog integrated in the CPU core. The SWT is a 32-bit modulus counter, clocked by the system clock or the crystal clock, that can provide a system reset or interrupt request when the correct software key is not written within the required time window.

●

The following features are implemented:

32-bit modulus counter

Clocked by system clock or crystal clock

Optional programmable watchdog window mode

Can optionally cause system reset or interrupt request on timeout

Reset by writing a software key to memory mapped register

Enabled out of reset

Configuration is protected by a software key or a write-once register

The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The

CRC features:

● Support for CRC-16-CCITT (x25 protocol):

– X

+ X

+ 1

●

Support for CRC-32 (Ethernet protocol):

– X

+ X

+ X + 1

Zero wait states for each write/read operations to the CRC_CFG and CRC_INP registers at the maximum frequency

The ECSM provides a myriad of miscellaneous control functions regarding program-visible information about the platform configuration and revision levels, a reset status register, a software watchdog timer, wakeup control for exiting sleep modes, and information on platform memory errors reported by error-correcting codes and/or generic access error information for certain processor cores.

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Introduction SPC564A74L7, SPC564A80B4, SPC564A80L7

The Error Correction Status Module supports a number of miscellaneous control functions for the platform. The ECSM includes these features:

● Registers for capturing information on platform memory errors if error-correcting codes

(ECC) are implemented

● For test purposes, optional registers to specify the generation of double-bit memory errors are enabled on the SPC564A80.

The sources of the ECC errors are:

●

Flash

SRAM

Peripheral RAM (FlexRay, CAN, eTPU2 Parameter RAM)

The SPC564A80 device features an external bus interface that is available in PBGA324 and calibration packages.

The EBI supports operation at frequencies of system clock /1, /2 and /4, with a maximum frequency support of 80 MHz. Customers running the device at 120 MHz or 132 MHz will use the /2 divider, giving an EBI frequency of 60 MHz or 66 MHz. Customers running the device at 80 MHz will be able to use the /1 divider to have the EBI run at the full 80 MHz frequency.

Features include:

●

1.8 V to 3.3 V ± 10% I/O (1.6 V to 3.6 V)

Memory controller with support for various memory types

16-bit data bus, up to 22-bit address bus

Pin muxing included to support 32-bit muxed bus

Selectable drive strength

Configurable bus speed modes

Bus monitor

Configurable wait states

The Calibration EBI controls data transfer across the crossbar switch to/from memories or peripherals attached to the calibration tool connector in the calibration address space. The

Calibration EBI is only available in the calibration tool.

●

Features include:

1.8 V to 3.3 V ± 10% I/O (1.6 V to 3.6 V)

Memory controller supports various memory types

16-bit data bus, up to 22-bit address bus

Pin muxing supports 32-bit muxed bus

Selectable drive strength

Configurable bus speed modes

Bus monitor

Configurable wait states

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The power management controller contains circuitry to generate the internal 3.3 V supply and to control the regulation of 1.2 V supply with an external NPN ballast transistor. It also contains low voltage inhibit (LVI) and power-on reset (POR) circuits for the 1.2 V supply, the

3.3 V supply, the 3.3 V/5 V supply of the closest I/O segment (VDDEH1) and the 5 V supply of the regulators (VDDREG).

1.5.25 Nexus port controller

The NPC (Nexus Port Controller) block provides real-time Nexus Class3+ development support capabilities for the SPC564A80 Power Architecture-based MCU in compliance with the IEEE-ISTO 5001-2003 and 2010 standards. MDO port widths of 4 pins and 12 pins are available in all packages.

1.5.26 JTAG

●

The JTAGC (JTAG Controller) block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. Testing is performed via a boundary scan technique, as defined in the IEEE 1149.1-2001 standard. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block is compliant with the IEEE 1149.1-2001 standard and supports the following features:

IEEE 1149.1-2001 Test Access Port (TAP) interface 4 pins (TDI, TMS, TCK, and TDO)

A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:

– BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD, HIGHZ, CLAMP

● A 5-bit instruction register that supports the additional following public instructions:

– ACCESS_AUX_TAP_NPC

●

– ACCESS_AUX_TAP_ONCE

– ACCESS_AUX_TAP_eTPU

– ACCESS_CENSOR

3 test data registers to support JTAG Boundary Scan mode

●

– Bypass register

– Boundary scan register

– Device identification register

A TAP controller state machine that controls the operation of the data registers, instruction register and associated circuitry

● Censorship Inhibit Register

– 64-bit Censorship password register

– If the external tool writes a 64-bit password that matches the Serial Boot password stored in the internal flash shadow row, Censorship is disabled until the next system reset.

SPC564A80 devices include a system development feature, the Development Trigger

Semaphore (DTS) module, that enables software to signal an external tool by driving a persistent (affected only by reset or an external tool) signal on an external device pin. There

Doc ID 15399 Rev 9 29/157

Introduction SPC564A74L7, SPC564A80B4, SPC564A80L7 is a variety of ways this module can be used, including as a component of an external realtime data acquisition system

1.6 SPC564A80 series architecture

Figure 1 shows a top-level block diagram of the SPC564A80 series.

30/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7

Interrupt

Controller eDMA

64 Channel

Power Architecture TM e200z4

Nexus Class 3+

SPE

VLE

MMU

8 KB I-cache

JTAG

Nexus

IEEE-ISTO

5001-2003/2010

FlexRay

4 MB

Flash

M0 M1

Crossbar Switch

MPU

Analog PLL

192 KB

SRAM

RCOSC

XOSC

M6 M7

Voltage Regulator

Standby

Regulator with Switch

ECSM

Introduction

I/O Bridge eMIOS

Channel

3 KB Data eTPU2

RAM

14 KB Code

Channel

RAM

Nexus

Class 1

LEGEND

ADC

ADCi

– Analog to Digital Converter

– ADC interface

AMux – Analog Multiplexer

BAM – Boot Assist Module

CRC

DEC

DTS

DSPI

– Cyclic Redundancy Check unit

– Decimation Filter

– Development Trigger Semaphore

– Deserial/Serial Peripheral Interface

EBI – External Bus Interface

ECSM – Error Correction Status Module eDMA – Enhanced Direct Memory Access eMIOS – Enhanced Modular Input Output System eSCI – Enhanced Serial Communications Interface eTPU2 – Second gen. Enhanced Time Processing Unit

FlexCAN – Controller Area Network (FlexCAN)

FMPLL – Frequency-Modulated Phase Locked Loop

JTAG – IEEE 1149.1 test controller

MMU – Memory Management Unit

MPU

PMC

– Memory Protection Unit

– Power Management Controller

PIT – Periodic Interrupt Timer

RCOSC – low-speed RC oscillator

REACM – Reaction module

SIU – System Integration Unit

SPE – Signal Processing Extension

SRAM – Static RAM

STM

SWT

– System Timer Module

– Software Watchdog Timer

VGA

VLE

– Variable Gain Amplifier

– Variable Length (instruction) Encoding

XOSC – XTAL Oscillator

Figure 1.

SPC564A80 series block diagram

ADCi DEC x2

AMux

VGA

Doc ID 15399 Rev 9 31/157

Introduction SPC564A74L7, SPC564A80B4, SPC564A80L7

Table 3

summarizes the functions of the blocks present on the SPC564A80 series microcontrollers.

Table 3.

Boot assist module (BAM)

Calibration Bus interface

Controller area network (FlexCAN)

Crossbar switch (XBAR)

Cyclic redundancy check (CRC)

Deserial serial peripheral interface (DSPI) e200z4 core

SPC564A80 series block summary

Block

Enhanced direct memory access (eDMA)

Function

Block of read-only memory containing executable code that searches for user-supplied boot code and, if none is found, executes the BAM boot code resident in device ROM.

Transfers data across the crossbar switch to/from peripherals attached to the calibration tool connector.

Supports the standard CAN communications protocol.

Internal busmaster.

CRC checksum generator.

Provides a synchronous serial interface for communication with external devices.

Executes programs and interrupt handlers.

Performs complex data movements with minimal intervention from the core.

Enhanced modular input-output system

(eMIOS)

Enhanced queued analog-to-digital converter (eQADC)

Enhanced serial communication interface

(eSCI)

Provides the functionality to generate or measure events.

Enhanced time processor unit (eTPU2)

Error Correction Status Module (ECSM)

External bus interface (EBI)

Flash memory

FlexRay

Interrupt controller (INTC)

JTAG controller

Memory protection unit (MPU)

Nexus port controller (NPC)

Provides accurate and fast conversions for a wide range of applications.

Provides asynchronous serial communication capability with peripheral devices and other microcontroller units.

Second-generation co-processor processes real-time input events, performs output waveform generation, and accesses shared data without host intervention.

The Error Correction Status Module supports a number of miscellaneous control functions for the platform, and includes registers for capturing information on platform memory errors if errorcorrecting codes (ECC) are implemented

Enables expansion of internal bus to enable connection of external memory or peripherals.

Provides storage for program code, constants, and variables.

Provides high-speed distributed control for advanced automotive applications.

Provides priority-based preemptive scheduling of interrupt requests.

Provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode.

Provides hardware access control for all memory references generated.

Provides real-time development support capabilities in compliance with the IEEE-ISTO 5001-2003 standard.

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Table 3.

Reaction Module (REACM)

System Integration Unit (SIU)

Static random-access memory (SRAM)

System timers

SPC564A80 series block summary (continued)

Block

Temperature sensor

Function

Works in conjunction with the eQADC and eTPU2 to increase system performance by removing the CPU from the current control loop.

Controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and the system reset operation.

Provides storage for program code, constants, and variables.

Includes periodic interrupt timer with real-time interrupt; output compare timer and system watchdog timer.

Provides the temperature of the device as an analog value.

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Pinout and signal description

2

SPC564A74L7, SPC564A80B4, SPC564A80L7

Pinout and signal description

This section contains the pinouts for all production packages for the SPC564A80 family of devices.

Caution: Any pins labeled “NC” are to be left unconnected. Any connection to an external circuit or voltage may cause unpredictable device behavior or damage.

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SPC564A74L7, SPC564A80B4, SPC564A80L7 Pinout and signal description

AN[18]

AN[17]

AN[16]

AN[11] / ANZ

AN[9] / ANX

VDDA

VSSA

AN[39]

AN[8] / ANW

VDDREG

VRCCTL

VSTBY

VRC33

MCKO

VSS

MDO[0]

MDO[1]

MDO[2]

MDO[3]

(see signal details, pin 21)

(see signal details, pin 22)

(see signal details, pin 23)

(see signal details, pin 24)

(see signal details, pin 25)

(see signal details, pin 26)

(see signal details, pin 27)

(see signal details, pin 28)

VSS

(see signal details, pin 30)

VDDEH1A

(see signal details, pin 32)

VDD

(see signal details, pin 34)

(see signal details, pin 35)

(see signal details, pin 36)

(see signal details, pin 37)

(see signal details, pin 38)

(see signal details, pin 39)

(see signal details, pin 40)

VDDEH1B

(see signal details, pin 42)

VSS

NIC

176-Pin

LQFP signal details: pin 21: ETPUA31 / DSPI_C_ PCS[4] / ETPUA13_O / GPIO[145] pin 22: ETPUA30 / DSPI_C_ PCS[3] / ETPUA11_O / GPIO[144] pin 23: ETPUA29 / DSPI_C_PCS[2] / RCH5_C / GPIO[143] pin 24: ETPUA28 / DSPI_C_ PCS[1] / RCH5_B / GPIO[142] pin 25: ETPUA27 / IRQ[15] / DSPI_C_SOUT_LVDS+ / SOUTB / GPIO[141] pin 26: ETPUA26 / IRQ[14] / DSPI_C_ SOUT_LVDS- / GPIO[140] pin 27: ETPUA25 / IRQ[13] / DSPI_C_ SCK_LVDS+ / GPIO[139] pin 28: ETPUA24 / IRQ[12] / DSPI_C_ SCK_LVDS- / GPIO[138] pin 30: ETPUA23 / IRQ[11] / ETPUA21_O / FR_A_TX_EN / GPIO[137] pin 32: ETPUA22 / IRQ[10] / ETPUA17_O / GPIO[136] pin 34: ETPUA21 / IRQ[9] / RCH0_C / FR_A_RX / GPIO[135] pin 35: ETPUA20 / IRQ[8] / RCH0_B / FR_A_TX / GPIO[134] pin 36: ETPUA19 / DSPI_D_ PCS[4] / RCH5_A / GPIO[133] pin 37: ETPUA18 / DSPI_D_ PCS[3] / RCH4_A / GPIO[132] pin 38: ETPUA17 / DSPI_D_ PCS[2] / RCH3_A / GPIO[131] pin 39: ETPUA16 / DSPI_D_ PCS[1] / RCH2_A / GPIO[130] pin 40: ETPUA15 / DSPI_B_ PCS[5] / RCH1_A / GPIO[129] pin 42: ETPUA14 / DSPI_B_ PCS[4] / ETPUA9_O / RCH0_A / GPIO[128]

103

102

101

100

113

112

111

110

109

108

107

106

105

104

123

122

121

120

119

118

117

116

115

114

132

131

130

129

128

127

126

125

124

VDD

TMS

TDI

MDO5 / ETPUA4_O / GPIO[76]

TCK

VSS

MDO4 / ETPUA2_O / GPIO[75]

VDDEH7A

MDO11 / ETPUA29_O / GPIO[82]

TDO

GPIO[219]

JCOMP

EVTO

MSEO[0]

MSEO[1]

EVTI

VSS

DSPI_B_PCS[3] / DSPI_C_SIN / GPIO[108]

DSPI_B_SOUT / DSPI_C_PCS[5] / GPIO[104]

DSPI_B_SIN / DSPI_C_PCS[2] / GPIO[103]

DSPI_B_PCS[0] / DSPI_D_PCS[2] / GPIO[105]

VDDEH6B

DSPI_B_PCS[1] / DSPI_D_PCS[0] / GPIO[106]

VSS

DSPI_B_PCS[2] / DSPI_C_SOUT / GPIO[107]

DSPI_B_SCK / DSPI_C_PCS[1] / GPIO[102]

DSPI_B_PCS[4] / DSPI_C_SCK / GPIO[109]

DSPI_B_PCS[5] / DSPI_C_PCS[0] / GPIO[110]

VDD

RSTOUT

CAN_C_TX / DSPI_D_PCS3 / GPIO[87]

SCI_A_TX / EMIOS13 / GPIO[89]

SCI_A_RX / EMIOS15 / GPIO[90]

CAN_C_RX / DSPI_D_PCS4 / GPIO[88]

RESET

VSS

VDDEH6A

VSS

XTAL

EXTAL / EXTCLK

VDDPLL

VSS

CAN_B_RX / DSPI_C_PCS[4] / SCI_C_RX / GPIO[86]

Note: Pin 96 (VSS) should be tied low.

Figure 2.

176-pin LQFP pinout (top view)

Doc ID 15399 Rev 9 35/157

Figure 3.

208-pin LBGA package ballmap (viewed from above)

2 3 4 5 6 7 8 9 10

VSS

B VDD

C VSTBY

AN9

VSS

VDD

AN11

AN8

VSS

VDDA1

AN21

AN17

VSSA1

AN0

AN34

AN1

AN4

AN16

AN5

REFBYPC

AN3

VRH

AN22

AN7

VRL

AN25

AN23

AN27

AN28

AN32

11 12

VSSA0 AN12-SDS

VDDA0 AN13-SDO

AN33

MDO2

MDO3

AN14-SDI AN15-FCK

MDO0

MDO1

VSS

VRC33

VSS

MSEO0

VSS A

VDD B

TCK C

D VRC33 AN39 VDD

E ETPUA30 ETPUA31 AN37

VSS

VDD

AN18 AN2 AN6 AN24 AN30 AN31 AN35 VDDEH7 VSS

TMS

TDI

EVTO

EVTI

NC D

MSEO1 E

ETPUA28

ETPUA24

ETPUA23

ETPUA20

ETPUA16

ETPUA12

ETPUA29

ETPUA27

ETPUA22

ETPUA19

ETPUA15

ETPUA11

ETPUA26

ETPUA25

ETPUA17

ETPUA14

ETPUA7

ETPUA6

AN36

ETPUA21

ETPUA18

ETPUA13

VDDEH1AB

TCRCLKA

VSS

VDDEH6AB TDO MCKO

DSPI_B_

SOUT

GPIO99

DSPI_B_

PCS3

DSPI_B_

PCS4

DSPI_B_

PCS5

SCI_B_TX

SCI_A_TX

CAN_C_TX

SCI_A_R

CAN_C_

DSPI_B_

SIN

DSPI_B_

PCS2

GPIO98

RSTOUT

WKPCFG

JCOMP F

DSPI_B_

PCS0

DSPI_B_

PCS1

DSPI_B_

SCK

VDDREG K

RESET L

M ETPUA10 ETPUA9 ETPUA1

N ETPUA8 ETPUA4 ETPUA0

ETPUA3

VSS

ETPUA2

VSS

VDD

VSS

VDD

ETPUA5

VSS

VDD

GPIO206

EMIOS0

VDD

GPIO207

VRC33

EMIOS2

EMIOS6

EMIOS4

EMIOS1

EMIOS3 EMIOS9

GPIO219

MDO9_

ETPUA25_

SCI_B_RX

EMIOS10

EMIOS8

EMIOS11

EMIOS13

VDDEH4AB EMIOS12

MDO11_

ETPUA29_

EMIOS14

EMIOS15

MDO4_

ETPUA2_O

MDO10_

ETPUA27_

MDO5_

ETPUA4_O

MDO7_

ETPUA19_

MDO8_

ETPUA21_

VRC33

CAN_A_TX

EMIOS23 CAN_A_RX

MDO6_

ETPUA13_

CAN_B_TX

VSS

(1)

VDD

CAN_B_RX

VDDE5

8 9 10 11 12 13

PLLREF BOOTCFG1

VRCCTL

VSS

VDD

ENGCLK

VSS

VDD

VSS

EXTAL

XTAL

VDDPLL R

VSS

This pin (N13) should be tied low.

ETPUA24

ETPUA23

ETPUA20

ETPUA16

ETPUA12

ETPUA8

ETPUA4

VSS

VRC33

ETPUA30

ETPUA28

VDD

VSS

ETPUA31

ETPUA29

ETPUA27

ETPUA22

ETPUA19

ETPUA15

ETPUA11

ETPUA7

ETPUA3

VSTBY

VDD

VSS

ETPUA26

ETPUA25

ETPUA17

ETPUA14

ETPUA10

ETPUA6

ETPUA2

ETPUA0

ETPUA21

ETPUA18

ETPUA13

VDDEH1AB

ETPUA9

ETPUA5

ETPUA1

AN37

AN36

VDD

VSS

AN11

AN39

AN38

VDD

VDDA0

AN19

AN17

AN8

ANW

VSSA0

AN16

AN20

AN9

Figure 4.

324-pin PBGA package ballmap (northwest, viewed from above)

AN1

AN0

AN21

AN10

ANY

AN5

AN4

AN3

AN18

VRH

REFBYPC

AN7

AN2

VRL

AN23

AN22

AN6

VSS

BDIP

CS3

ADDR16

ADDR18

ADDR20

ADDR22

ADDR24

ADDR26

ADDR28

ADDR29

VSS

TCRCLKA

CS2

ADDR17

ADDR19

ADDR21

ADDR23

ADDR25

VDDE-EH

ADDR27

VSS

VDD

CS1

WE1

RD_WR

VDDE-EH

ADDR12

ADDR13

ADDR15

ADDR30

VSS

VDD

VDDE2

CS0

WE0

VRC33

ADDR14

ADDR31

VSS

VDD

VDDE2

DATA0

VDD

VDDE2

DATA1

DATA2

VDDE2

DATA8

VDDE2

DATA3

VRC33

DATA9

GPIO206

DATA4

Figure 5.

324-pin PBGA package ballmap (southwest, viewed from above)

VDDE2

DATA10

DATA5

DATA6

VDDE2

VSS

VDDE2

VSS

DATA11

GPIO207

DATA7

DATA12

DATA13

VDDE2

EMIOS0

VSS

VDDE2

DATA14

DATA15

EMIOS3

EMIOS1

AN27

AN26

AN25

AN24

VSS

AN28

AN31

AN30

AN29

VSS

AN35

AN32

AN33

AN34

NIC

(1),(2)

VSS

VSSA1

VDDA1

VDDEH7

AN12_

SDS

AN13_

SDO

AN14_

SDI

AN15_

FCK

MDO11_

ETPUA29_O

MDO9_

ETPUA25_O

MDO5_

ETPUA4_O

MDO6_

ETPUA13_O

MDO10_

ETPUA27_O

MDO7_

ETPUA19_O

MDO2

MDO3

MDO8_

ETPUA21_O

MDO4_

ETPUA2_O

MDO1

VSS

NIC

(1),(2)

NIC

(1),(2)

RDY

VDDEH6AB

DSPI_B_

SOUT

GPIO99

DSPI_B_

PCS5

VSS VSS VSS

Pins marked “NIC” have no internal connection.

Balls B22, C21, D20, E19, F19 and J14 are shorted together inside the package.

Figure 6.

324-pin PBGA package ballmap (northeast, viewed from above)

VDD

MDO0

VSS

NIC

(1),(2)

TMS

JCOMP

MCKO

GPIO203

DSPI_B_

PCS3

DSPI_B_

PCS4

DSPI_A_

SOUT

VRC33

VSS

NIC

(1),(2)

TCK

TDO

EVTI

MSEO0

GPIO204

DSPI_B_

PCS0

DSPI_B_

SCK

DSPI_A_

SIN

VSS

NIC

(1),(2)

VDD

TDI

NIC

(1)

EVTO

MSEO1

DSPI_B_

SIN

DSPI_B_

PCS1

DSPI_B_

PCS2

DSPI_A_

SCK

VSS

EMIOS2

EMIOS6

EMIOS5

EMIOS8

EMIOS10

EMIOS9

VDDEH4AB

EMIOS15

EMIOS13

EMIOS12

EMIOS17

EMIOS16

EMIOS4 EMIOS7 EMIOS11 EMIOS14

12 13 14

Pins marked “NIC” have no internal connection.

This pin (T21) should be tied low.

EMIOS21

EMIOS22

EMIOS19

EMIOS18

VDDE5

CAN_A_TX

EMIOS23

EMIOS20

SCI_C_TX

VDDE5

CAN_A_RX

CAN_B_TX

DSPI_A_

PCS1

DSPI_A_

PCS4

CAN_C_TX

WKPCFG

SCI_B_RX

VDDEH6AB

VDD

VSS

SCI_C_RX

VDDE5

CAN_B_RX

DSPI_A_

PCS0

SCI_A_TX

SCI_A_RX

CAN_C_RX

BOOTCFG1

PLLCFG1

VRCCTL

VDD

VSS

CLKOUT

VDDE5

GPIO98

DSPI_A_

PCS5

RSTOUT

SCI_B_TX

VSS

(2)

BOOTCFG0

PLLREF

NIC

(1)

VDD

VSS

ENGCLK

Figure 7.

324-pin PBGA package ballmap (southeast, viewed from above)

VDDREG

NIC

(1)

RSTCFG

RESET

VSS

EXTAL

XTAL

VDDPLL

VRC33

VDD

VSS

Table 4.

RESET

Name

GPIO[219]

RSTOUT

PLLREF

IRQ[4]

ETRIG2

GPIO[208]

PLLCFG1

(13)

IRQ[5]

DSPI_D_SOUT

GPIO[209]

RSTCFG

GPIO[210]

SPC564A80 signal properties

GPIO

Function

(1)

EMIOS14

(8)

GPIO[203]

EMIOS15

(8)

GPIO[204] eMIOS channel

GPIO eMIOS channel

GPIO

GPIO[206] ETRIG0 GPIO / eQADC Trigger Input

GPIO[207] ETRIG1 GPIO / eQADC Trigger Input

External Reset Input

External Reset Output

FMPLL Mode Selection

External Interrupt Request eQADC Trigger Input

GPIO

—

External interrupt request

DSPI D data output

GPIO

RSTCFG

GPIO

—

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

During Reset

(7)

After

Reset

—

001

010

100

000

—

010

100

000

203

204

I/O

206 I/O

(9)

207 I/O

(9)

219

(11)

I/O

GPIO

VDDEH7

Slow

VDDEH7

Slow

VDDEH7

Slow

(10)

VDDEH7

Slow

VDDEH7

MultiV

(12)

—

230

Reset / Configuration

VDDEH6

Slow

VDDEH6

Slow

208

209

210

—

I/O

VDDEH6

Slow

VDDEH6

Medium

VDDEH6

Slow

— / Up

RESET / Up

RSTOUT / Down

— / Up

— / Down

— / Up

—/ Up

— / Up

RESET / Up

RSTOUT / Down

PLLREF / Up

— / Up

—

176

—

143

144

122

102

—

Package pin #

208

L16

K15

—

M14

—

H20

H21

AA7

R22

P21

V21

U20

P22

324

—

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

BOOTCFG[0]

IRQ[2]

GPIO[211]

BOOTCFG[1]

IRQ[3]

ETRIG3

GPIO[212]

WKPCFG

NMI

DSPI_B_SOUT

GPIO[213]

CS[0]

ADDR[8]

GPIO[0]

CS[1]

ADDR9

GPIO[1]

CS[2]

ADDR10

WE[2]/BE[2]

CAL_WE[2]/BE[2]

GPIO[2]

CS[3]

ADDR11

WE[3]/BE[3]

CAL_WE[3]/BE[3]

GPIO[3]

Boot Config. Input

External Interrupt Request

GPIO

Boot Config. Input

External Interrupt Request eQADC Trigger Input

GPIO

Weak Pull Config. Input

Non-Maskable Interrupt

DSPI D data output

GPIO

External chip selects

External address bus

GPIO

External chip selects

External address bus

GPIO

External chip selects

External address bus

Write/byte enable

Cal. bus write/byte enable

GPIO

External chip selects

External address bus

Write/byte enable

Cal bus write/byte enable

GPIO

001

010

100

000

001

010

100

000

0001

0010

0100

1000

0000

0001

0010

0100

1000

0000

211

212

213

I/O

VDDEH6

Slow

VDDEH6

Slow

VDDEH6

Medium

External Bus Interface

I/O

VDDE2

Fast

VDDE2

Fast

VDDE2

Fast

VDDE2

Fast

— / Down

— / Up

BOOTCFG[0] /

Down

176

—

BOOTCFG[1] /

Down

WKPCFG / Up 86

— / Up

—

Package pin #

208

M15

L15

—

U21

T20

R19

324

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

ADDR12

GPIO[8]

ADDR13

WE[2]

GPIO[9]

ADDR14

WE[3]

GPIO[10]

ADDR15

GPIO[11]

ADDR16

FR_A_TX

DATA16

GPIO[12]

ADDR17

FR_A_TX_EN

DATA17

GPIO[13]

ADDR18

FR_A_RX

DATA18

GPIO[14]

ADDR19

FR_B_TX

DATA19

GPIO[15]

ADDR20

FR_B_TX_EN

DATA20

GPIO[16]

External address bus

GPIO

External address bus

Write/byte enable

GPIO

External address bus

Write/byte enables

GPIO

External address bus

GPIO

External address bus

Flexray TX data channel A

External data bus

GPIO

External address bus

FlexRay ch. A TX data enable

External data bus

GPIO

External address bus

Flexray RX data ch. A

External data bus

GPIO

External address bus

Flexray TX data ch. B

External data bus

GPIO

External address bus

Flexray TX data enable for ch. B

External data bus

GPIO

001

010

100

000

001

010

100

000

001

010

100

000

001

010

100

000

001

010

100

000

001

100

000

001

100

000

I/O

VDDE3

Fast

VDDE3

Fast

VDDE3

Fast

VDDE3

Fast

VDDE-EH

Medium

VDDE-EH

Medium

VDDE-EH

Medium

VDDE-EH

Medium

VDDE-EH

Medium

— / Up

176

Package pin #

208 324

— — T3

— — U3

— — U4

— — V3

— — P1

— — P2

— — R1

— — R2

— — T1

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

ADDR25

DATA25

GPIO[21]

ADDR26

DATA26

GPIO[22]

ADDR27

DATA27

GPIO[23]

ADDR28

DATA28

GPIO[24]

ADDR29

DATA29

GPIO[25]

ADDR21

FR_B_RX

DATA21

GPIO[17]

ADDR22

DATA22

GPIO[18]

ADDR23

DATA23

GPIO[19]

ADDR24

DATA24

GPIO[20]

External address bus

Flexray RX data channel B

External data bus

GPIO

External address bus

External data bus

GPIO

External address bus

External data bus

GPIO

External address bus

External data bus

GPIO

External address bus

External data bus

GPIO

External address bus

External data bus

GPIO

External address bus

External data bus

GPIO

External address bus

External data bus

GPIO

External address bus

External data bus

GPIO

001

100

000

001

100

000

001

100

000

001

100

000

001

100

000

001

100

000

001

100

000

001

010

100

000

001

100

000

I/O

VDDE-EH

Medium

VDDE-EH

Medium

VDDE-EH

Medium

VDDE-EH

Medium

VDDE-EH

Medium

VDDE-EH

Medium

VDDE-EH

Medium

VDDE-EH

Medium

VDDE-EH

Medium

— / Up

176

Package pin #

208 324

— — T2

— — U1

— — U2

— — V1

— — V2

— — W1

— — Y2

— — Y1

— — AA1

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

DATA2

ADDR18

GPIO[30]

DATA3

ADDR19

GPIO[31]

DATA4

ADDR20

GPIO[32]

DATA5

ADDR21

GPIO[33]

DATA6

ADDR22

GPIO[34]

ADDR30

ADDR6

(8)

DATA30

GPIO[26]

ADDR31

ADDR7

(8)

DATA31

GPIO[27]

DATA0

ADDR16

GPIO[28]

DATA1

ADDR17

GPIO[29]

External address bus

External data bus

GPIO

External address bus

External data bus

GPIO

External data bus

External address bus

GPIO

External data bus

External address bus

GPIO

External data bus

External address bus

GPIO

External data bus

External address bus

GPIO

External data bus

External address bus

GPIO

External data bus

External address bus

GPIO

External data bus

External address bus

GPIO

001

010

000

001

010

000

001

010

000

001

010

000

001

010

000

001

010

000

001

010

000

001

010

100

000

001

010

100

000

I/O

VDDE-EH

Medium

VDDE-EH

Medium

VDDE5

Fast

VDDE5

Fast

VDDE5

Fast

VDDE5

Fast

VDDE5

Fast

VDDE5

Fast

VDDE5

Fast

— / Up

176

Package pin #

208 324

— — W3

— — V4

— — AB4

— — AA5

— — AB5

— — AB6

— — AB7

— — AA8

— — AB8

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

DATA11

ADDR27

GPIO[39]

DATA12

ADDR28

GPIO[40]

DATA13

ADDR29

GPIO[41]

DATA14

ADDR30

GPIO[42]

DATA7

ADDR23

GPIO[35]

DATA8

ADDR24

GPIO[36]

DATA9

ADDR25

GPIO[37]

DATA10

ADDR26

GPIO[38]

DATA15

ADDR31

GPIO[43]

RD_WR

GPIO[62]

External data bus

External address bus

GPIO

External data bus

External address bus

GPIO

External data bus

External address bus

GPIO

External data bus

External address bus

GPIO

External data bus

External address bus

GPIO

External data bus

External address bus

GPIO

External data bus

External address bus

GPIO

External data bus

External address bus

GPIO

External data bus

External address bus

GPIO

External read/write

GPIO

001

010

000

001

010

000

001

010

000

001

010

000

001

010

000

001

010

000

001

010

000

001

010

000

001

010

000

I/O

VDDE5

Fast

VDDE5

Fast

VDDE5

Fast

VDDE5

Fast

VDDE5

Fast

VDDE5

Fast

VDDE5

Fast

VDDE5

Fast

VDDE5

Fast

VDDE2

Fast

— / Up

176

Package pin #

208 324

— — AA9

— — Y6

— — Y7

— — Y8

— — W9

— — W10

— — Y10

— — W11

— — Y11

— — P3

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

BDIP

GPIO[63]

WE[0]/BE[0]

GPIO[64]

WE[1]/BE[1]

GPIO[65]

GPIO[68]

ALE

GPIO[69]

(8)

GPIO[70]

CAL_CS0

CAL_CS2

CAL_ADDR[10]

CAL_WE[2]/BE[2]

CAL_CS3

CAL_ADDR[11]

CAL_WE[3]/BE[3]

CAL_ADDR[12]

CAL_WE[2]/BE[2]

CAL_ADDR[13]

CAL_WE[3]/BE[3]

External burst data in progress

GPIO

External write/byte enable

GPIO

External write/byte enable

GPIO

External output enable

GPIO

External transfer start

Address latch enable

GPIO[69]

External transfer acknowledge

External transfer start

GPIO

Calibration chip select

Calibration address bus

Calibration write/byte enable

Calibration chip select

Calibration address bus

Calibration write/byte enable

Calibration address bus

Calibration write/byte enable

Calibration address bus

Calibration write/byte enable

001

010

100

001

010

100

001

010

000

001

010

000

P 01

I/O

VDDE2

Fast

VDDE2

Fast

336

338

339

340

Calibration Bus

VDDE12

Fast

I/O

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE2

Fast

VDDE2

Fast

VDDE2

Fast

VDDE2

Fast

— / Up

— / —

176

Package pin #

208 324

—

AB9

— — T4

— — R4

— —

—

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

CAL_ADDR[14]

CAL_DATA[31]

CAL_ADDR[15]

CAL_ALE

CAL_ADDR[16]

CAL_DATA[16]

CAL_ADDR[17]

CAL_DATA[17]

CAL_ADDR[18]

CAL_DATA[18]

CAL_ADDR[19]

CAL_DATA[19]

CAL_ADDR[20]

CAL_DATA[20]

CAL_ADDR[21]

CAL_DATA[21]

CAL_ADDR[22]

CAL_DATA[22]

CAL_ADDR[23]

CAL_DATA[23]

CAL_ADDR[24]

CAL_DATA[24]

CAL_ADDR[25]

CAL_DATA[25]

CAL_ADDR[26]

CAL_DATA[26]

CAL_ADDR[27]

CAL_DATA[27]

Calibration address bus

Calibration data bus

Calibration address bus

Calibration address latch enable

Calibration address bus

Calibration data bus

Calibration address bus

Calibration data bus

Calibration address bus

Calibration data bus

Calibration address bus

Calibration data bus

Calibration address bus

Calibration data bus

Calibration address bus

Calibration data bus

Calibration address bus

Calibration data bus

Calibration address bus

Calibration data bus

Calibration address bus

Calibration data bus

Calibration address bus

Calibration data bus

Calibration address bus

Calibration data bus

Calibration address bus

Calibration data bus

340

345

I/O

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

— / —

176

Package pin #

208 324

—

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

CAL_ADDR[28]

CAL_DATA[28]

CAL_ADDR[29]

CAL_DATA[29]

CAL_ADDR[30]

CAL_DATA[30]

CAL_DATA[0]

CAL_DATA[1]

CAL_DATA[2]

CAL_DATA[3]

CAL_DATA[4]

CAL_DATA[5]

CAL_DATA[6]

CAL_DATA[7]

CAL_DATA[8]

CAL_DATA[9]

CAL_DATA[10]

Calibration address bus

Calibration data bus

Calibration address bus

Calibration data bus

Calibration address bus

Calibration data bus

345

341

I/O

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

— / Up

— / —

— / Up

176

Package pin #

208 324

—

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

CAL_DATA[11]

CAL_DATA[12]

CAL_DATA[13]

CAL_DATA[14]

CAL_DATA[15]

CAL_RD_WR

CAL_WE[0]/BE[0]

CAL_WE[1]/BE[1]

CAL_OE

CAL_TS

CAL_ALE

CAL_MDO[4]

CAL_MDO[5]

CAL_MDO[6]

CAL_MDO[7]

Calibration data bus

Calibration read/write enable

Calibration write/byte enable

Calibration output enable

Calibration transfer start

Address Latch Enable

Calibration Nexus Message Data

Out

Calibration Nexus Message Data

Out

Calibration Nexus Message Data

Out

Calibration Nexus Message Data

Out

341

342

343

—

I/O

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

— / Up

—

— / Up

— / —

CAL_MDO[4] / —

CAL_MDO[5] / —

CAL_MDO[6] / —

CAL_MDO[7] / —

176

—

Package pin #

208

—

324

—

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

CAL_MDO[8]

CAL_MDO[9]

CAL_MDO[10]

CAL_MDO[11]

EVTI

EVTO

MCKO

MDO0

(16)

MDO1

(16)

MDO2

(16)

MDO3

(16)

MDO4

(16)

ETPUA2_O

(8)

GPIO[75]

Calibration Nexus Message Data

Out

Calibration Nexus Message Data

Out

Calibration Nexus Message Data

Out

Calibration Nexus Message Data

Out

Nexus event in

Nexus event out

Nexus message clock out

Nexus message data out

Nexus message data out eTPU A channel (output only)

GPIO

—

231

227

219

(11

)

220

221

222

223

I/O

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

NEXUS

VDDEH7

MultiV

(12),(14)

VDDEH7

MultiV

(12),(14),

(15)

VRC33

Fast

VRC33

Fast

VRC33

Fast

VRC33

Fast

VRC33

Fast

VDDEH7

MultiV

(12),(14)

—

— / Up

—

CAL_MDO[8] / —

CAL_MDO[9] / —

176

—

CAL_MDO[10] / — —

CAL_MDO[11] / — —

EVTI / Up

EVTO / —

MCKO / —

MDO[0] / —

MDO[1] / —

MDO[2] / —

MDO[3] / —

— / —

116 E15

120 D15

Package pin #

208

F15

A14

B14

A13

B13

126 P10

—

F21

F22

G20

B20

C19

C18

D18

B19

324

—

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

MDO5

(16)

ETPUA4_O

(8)

GPIO[76]

MDO6

(16)

ETPUA13_O

(8)

GPIO[77]

MDO7

(16)

ETPUA19_O

(8)

GPIO[78]

MDO8

(16)

ETPUA21_O

(8)

GPIO[79]

MDO9

(16)

ETPUA25_O

(8)

GPIO[80]

MDO10

(16)

ETPUA27_O

(8)

GPIO[81]

MDO11

(16)

ETPUA29_O

(8)

GPIO[82]

MSEO[0]

(16)

MSEO[1]

(16)

RDY

Nexus message data out eTPU A channel (output only)

GPIO

Nexus message data out eTPU A channel (output only)

GPIO

Nexus message data out eTPU A channel (output only)

GPIO

Nexus message data out eTPU A channel (output only)

GPIO

Nexus message data out eTPU A channel (output only)

GPIO

Nexus message data out eTPU A channel (output only)

GPIO

Nexus message data out eTPU A channel (output only)

GPIO[82]

Nexus message start/end out

Nexus ready output

224

225

226

I/O

VDDEH7

MultiV

(12),(14)

VDDEH7

MultiV

VDDEH7

MultiV

(12),(14)

VDDEH7

MultiV

VDDEH7

MultiV

(12),(14)

VDDEH7

(12),(14)

VDDEH7

MultiV

(12),(14)

VDDEH7

MultiV

(12),(14)

VDDEH7

MultiV

(12),(14)

VDDEH7

MultiV

(12),(14)

JTAG

Status

(7)

During Reset

—

After

Reset

— / —

MSEO[0] / —

MSEO[1] / —

—

176 208

129 T10

135 T11

136 N11

137 P11

139 T7

134 R10

124 P9

118 C15

117 E16

—

Package pin #

—

C17

D17

B18

A19

B17

A18

A17

G21

G22

G19

324

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

TCK

TDI

TDO

TMS

JCOMP

CAN_A_TX

SCI_A_TX

GPIO[83]

CAN_A_RX

SCI_A_RX

GPIO[84]

CAN_B_TX

DSPI_C_PCS[3]

SCI_C_TX

GPIO[85]

CAN_B_RX

DSPI_C_PCS[4]

SCI_C_RX

GPIO[86]

CAN_C_TX

DSPI_D_PCS[3]

GPIO[87]

JTAG test clock input

JTAG test data input

JTAG test data output

JTAG test mode select input

JTAG TAP controller enable

FlexCAN A TX eSCI A TX

GPIO

FlexCAN A RX eSCI A RX

GPIO

FlexCAN B TX

DSPI C peripheral chip select eSCI C TX

GPIO

FlexCAN B RX

DSPI C peripheral chip select eSCI C RX

GPIO

FlexCAN C TX

DSPI D peripheral chip select

GPIO

001

010

100

000

001

010

100

000

—

232

228

—

I/O

VDDEH7

MultiV

(12)

VDDEH7

MultiV

(12)

VDDEH7

MultiV

(12)

VDDEH7

MultiV

(12)

VDDEH7

MultiV

(12)

FlexCAN

VDDEH6

Slow

VDDEH6

Slow

VDDEH6

Slow

VDDEH6

Slow

VDDEH6

Medium

TCK / Down

TDI / Up

TDO / Up

TMS / Up

JCOMP / Down

— / Up

TCK / Down

TDI / Up

TDO / Up

TMS / Up

JCOMP / Down

121 F16

— / Up

176

128 C16

130 E14

123 F14

131 D14

Package pin #

208

P12

R12

T12

R13

101 K13

D21

D22

E21

E20

F20

Y17

AA18

AB18

AB19

P19

324

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

CAN_C_RX

DSPI_D_PCS[4]

GPIO[88]

SCI_A_TX

EMIOS13

(8)

GPIO[89]

SCI_A_RX

EMIOS15

(8)

GPIO[90]

SCI_B_TX

DSPI_D_PCS[1]

GPIO[91]

SCI_B_RX

DSPI_D_PCS[5]

GPIO[92]

SCI_C_TX

GPIO[244]

SCI_C_RX

GPIO[245]

DSPI_A_SCK

(17)

DSPI_C_PCS[1]

GPIO[93]

DSPI_A_SIN

(17)

DSPI_C_PCS[2]

GPIO[94]

FlexCAN C RX

DSPI D peripheral chip select

GPIO eSCI A TX eMIOS channel

GPIO eSCI A RX eMIOS channel

GPIO eSCI B TX

DSPI D peripheral chip select

GPIO eSCI B RX

DSPI D peripheral chip select

GPIO eSCI C TX

GPIO eSCI C RX

GPIO

—

DSPI C peripheral chip select

GPIO

—

DSPI C peripheral chip select

GPIO

—

244

245

I/O

VDDEH6

Slow

—

I/O

—

I/O eSCI

I/O

VDDEH6

Medium

VDDEH6

Medium

VDDEH6

Medium

VDDEH6

Medium

DSPI

VDDEH6

Medium

VDDEH6

Medium

VDDEH7

Medium

VDDEH7

Medium

— / Up

176

Package pin #

208 324

98 L14 R20

100 J14 N20

99 K14 P20

87 L13 R21

84 M13 T19

—

— W18

— Y19

— — L22

— — L21

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

DSPI_A_SOUT

(17)

DSPI_C_PCS[5]

GPIO[95]

DSPI_A_PCS[0]

(17)

DSPI_D_PCS[2]

GPIO[96]

DSPI_A_PCS[1]

(17)

DSPI_B_PCS[2]

GPIO[97]

CS[2]

DSPI_D_SCK

GPIO[98]

CS[3]

DSPI_D_SIN

GPIO[99]

DSPI_A_PCS[4]

(17)

DSPI_D_SOUT

GPIO[100]

DSPI_A_PCS[5]

(17)

DSPI_B_PCS[3]

GPIO[101]

DSPI_B_SCK

DSPI_C_PCS[1]

GPIO[102]

DSPI_B_SIN

DSPI_C_PCS[2]

GPIO[103]

—

DSPI C peripheral chip select

GPIO

—

DSPI D peripheral chip select

GPIO

—

DSPI B peripheral chip select

GPIO

—

SPI clock pin for DSPI module

GPIO

—

DSPI D data input

GPIO

—

DSPI D data output

GPIO

—

DSPI B peripheral chip select

GPIO

SPI clock pin for DSPI module

DSPI C peripheral chip select

GPIO

DSPI B data input

DSPI C peripheral chip select

GPIO

—

100

101

102

103

—

I/O

—

I/O

—

I/O

—

I/O

—

I/O

VDDEH7

Medium

VDDEH7

Medium

VDDEH7

Medium

VDDEH7

Medium

VDDEH7

Medium

VDDEH7

Medium

VDDEH7

Medium

VDDEH6

Medium

VDDEH6

Medium

Status

(7)

During Reset

— / Up

After

Reset

— / Up

176

Package pin #

208 324

— — L20

— — M20

— — M19

141 J15 M21

142 H13 K19

— — N19

— — N21

106 J16 K21

112 G15 H22

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

DSPI_B_SOUT

DSPI_C_PCS[5]

GPIO[104]

DSPI_B_PCS[0]

DSPI_D_PCS[2]

GPIO[105]

DSPI_B_PCS[1]

DSPI_D_PCS[0]

GPIO[106]

DSPI_B_PCS[2]

DSPI_C_SOUT

GPIO[107]

DSPI_B_PCS[3]

DSPI_C_SIN

GPIO[108]

DSPI_B_PCS[4]

DSPI_C_SCK

GPIO[109]

DSPI_B_PCS[5]

DSPI_C_PCS[0]

GPIO[110]

AN0

(18)

DAN0+

AN1

(18)

DAN0-

AN2

(18)

DAN1+

DSPI B data output

DSPI C peripheral chip select

GPIO

DSPI B peripheral chip select

DSPI D peripheral chip select

GPIO

DSPI B peripheral chip select

DSPI D peripheral chip select

GPIO

DSPI B peripheral chip select

DSPI C data output

GPIO

DSPI B peripheral chip select

DSPI C data input

GPIO

DSPI B peripheral chip select

SPI clock pin for DSPI module

GPIO

DSPI B peripheral chip select

DSPI C peripheral chip select

GPIO

Single Ended Analog Input

Positive Terminal Diff. Input

Single Ended Analog Input

Negative Terminal Diff. Input

Single Ended Analog Input

Positive Terminal Diff. Input

—

104

105

106

107

108

109

110

—

I/O

VDDEH6

Medium

VDDEH6

Medium

VDDEH6

Medium

VDDEH6

Medium

VDDEH6

Medium

VDDEH6

Medium

VDDEH6

Medium

I eQADC

VDDA

Analog

VDDA

Analog

VDDA

Analog

— / Up

I / —

— / Up

AN[0] / —

AN[1] / —

AN[2] / —

176

Package pin #

208 324

113 G13

111 G16

109 H16

107 H15

114 G14

105 H14

104 J13

172 B5

171 A6

170 D6

J19

J21

J22

K22

J20

K20

L19

D10

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

AN3

(18)

DAN1-

AN4

(18)

DAN2+

AN5

(18)

DAN2-

AN6

(18)

DAN3+

AN7

(18)

DAN3-

AN8

ANW

AN9

ANX

AN10

ANY

AN11

ANZ

AN12 - SDS

MA0

ETPUA19_O

(8)

SDS

AN13 - SDO

MA1

ETPUA21_O

(8)

SDO

Single Ended Analog Input

Negative Terminal Diff. Input

Single Ended Analog Input

Positive Terminal Diff. Input

Single Ended Analog Input

Negative Terminal Diff. Input

Single Ended Analog Input

Positive Terminal Diff. Input

Single Ended Analog Input

Negative Terminal Diff. Input

Single-ended Analog Input

Multiplexed Analog Input

Single-ended Analog Input

External Multiplexed Analog Input

Single-ended Analog Input

Multiplexed Analog Input

Single-ended Analog Input

Multiplexed Analog Input

Single-ended Analog Input

MUX Address 0 eTPU A channel (output only) eQADC Serial Data Select

Single-ended Analog Input

MUX Address 1 eTPU A channel (output only) eQADC Serial Data Out

—

001

010

100

000

001

010

100

000

—

215

216

I/O

VDDA

Analog

VDDA

Analog

VDDA

Analog

VDDA

Analog

VDDA

Analog

VDDA

Analog

VDDA

Analog

VDDA

Analog

VDDA

Analog

VDDEH7

(19)

Medium

VDDEH7

(19)

Medium

During Reset

I / —

Status

(7)

After

Reset

AN[3] / —

AN[4] / —

AN[5] / —

AN[6] / —

AN[7] / —

AN[8] / —

AN[9] / —

AN[10] / —

AN[11] / —

AN[12] / —

AN[13] / —

169 C7

168 B6

167 A7

166 D7

165 C8

176

Package pin #

208 324

—

148 A12

147 B12

D11

C10

— D8

A16

B16

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

AN14 - SDI

MA2

ETPUA27_O

(8)

SDI

AN15 - FCK

FCK

ETPUA29_O

(8)

Single-ended Analog Input

MUX Address 2 eTPU A channel (output only) eQADC Serial Data In

Single-ended Analog Input eQADC Free Running Clock eTPU A channel (output only)

001

010

100

000

001

010

100

217

218

VDDEH7

(19)

Medium

VDDEH7

(19)

Medium

I / —

AN[14] / —

AN[15] / —

AN16

AN17

AN18

AN19

AN20

AN21

AN22

AN23

AN24

AN25

Single-ended Analog Input

—

— I

VDDA

Analog

VDDA

Analog

VDDA

Analog

VDDA

Analog

VDDA

Analog

VDDA

Analog

VDDA

Analog

VDDA

Analog

VDDA

Analog

VDDA

Analog

I / —

AN[16] / —

AN[17] / —

AN[18] / —

AN[19] / —

AN[20] / —

AN[21] / —

AN[22] / —

AN[23] / —

AN[24] / —

AN[25] / —

146 C12

145 C13

176

Package pin #

208 324

—

173 B4

161 B8

160 C9

159 D8

158 B9

C16

D16

— B6

— C7

C11

B11

D12

C12

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

AN26

AN27

AN28

AN29

AN30

AN31

AN32

AN33

AN34

AN35

AN36

AN37

AN38

AN39

Single-ended Analog Input

—

— I

VDDA

Analog

VDDA

Analog

VDDA

Analog

VDDA

Analog

VDDA

Analog

VDDA

Analog

VDDA

Analog

VDDA

Analog

VDDA

Analog

VDDA

Analog

VDDA

Analog

VDDA

Analog

VDDA

Analog

VDDA

Analog

I / —

AN[26] / —

AN[27] / —

AN[28] / —

AN[29] / —

AN[30] / —

AN[31] / —

AN[32] / —

AN[33] / —

AN[34] / —

AN[35] / —

AN[36] / —

AN[37] / —

AN[38] / —

AN[39] / —

176

Package pin #

208 324

—

157 A10

156 B10

—

155 D9

— B12

— D13

154 D10

153 C10

152 C11

151 C5

150 D11

174 F4

175 E3

— —

8 D2

A12

A13

C13

B13

B14

C14

D14

A14

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

VRH

VRL

REFBYBC

TCRCLKA

IRQ[7]

GPIO[113]

ETPUA0

ETPUA12_O

(8)

ETPUA19_O

(8)

GPIO[114]

ETPUA1

ETPUA13_O

(8)

GPIO[115]

ETPUA2

ETPUA14_O

(8)

GPIO[116]

ETPUA3

ETPUA15_O

(8)

GPIO[117]

ETPUA4

ETPUA16_O

(8)

FR_B_TX

GPIO[118]

Voltage Reference High

Voltage Reference Low

Reference Bypass Capacitor

Input eTPU A TCR clock

External interrupt request

GPIO eTPU A channel eTPU A channel (output only) eTPU A channel (output only)

GPIO eTPU A channel eTPU A channel (output only)

Flexray TX data channel B

GPIO

—

001

010

100

000

0001

0010

1000

0000

113

114

115

116

117

118

VDDA

—

VDDA

—

VDDA

Analog

I/O

I/O eTPU2

VDDEH4

Slow

VDDEH4

Slow

VDDEH4

Slow

VDDEH4

Slow

VDDEH4

Slow

VDDEH4

Slow

I / —

— / Up

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

VRH

VRL

REFBYPC

— / Up

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

176

163 A8

162 A9

164 B7

—

— / WKPCFG GPIO / WKPCFG 58

Package pin #

208

A10

A11

B10

324

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

ETPUA5

ETPUA17_O

(8)

DSPI_B_SCK_LVD

S-

FR_B_TX_EN

GPIO[119]

ETPUA6

ETPUA18_O

(8)

DSPI_B_SCK_LVD

S+

FR_B_RX

GPIO[120]

ETPUA7

ETPUA19_O

(8)

DSPI_B_SOUT_LV

DS-

ETPUA6_O

(8)

GPIO[121]

ETPUA8

ETPUA20_O

(8)

DSPI_B_SOUT_LV

DS+

GPIO[122]

ETPUA9

ETPUA21_O

(8)

RCH1_B

GPIO[123]

ETPUA10

ETPUA22_O

(8)

RCH1_C

GPIO[124] eTPU A channel eTPU A channel (output only)

LVDS negative DSPI clock

Flexray TX data enable for ch. B

GPIO eTPU A channel eTPU A channel (output only)

LVDS positive DSPI clock

Flexray RX data channel B

GPIO eTPU A channel eTPU A channel (output only)

LVDS negative DSPI data out eTPU A channel (output only)

GPIO eTPU A channel eTPU A channel (output only)

LVDS positive DSPI data out

GPIO eTPU A channel eTPU A channel (output only)

Reaction channel 1B

GPIO eTPU A channel eTPU A channel (output only)

Reaction channel 1C

GPIO

0001

0010

0100

1000

0000

119

0001

0010

0100

1000

0000

120

0001

0010

0100

1000

0000

121

001

010

100

000

001

010

100

000

001

010

100

000

122

123

124

I/O

VDDEH4

Slow +

LVDS

VDDEH4

Medium +

LVDS

VDDEH4

Slow +

LVDS

VDDEH4

Slow +

LVDS

VDDEH4

Slow

VDDEH1

Slow

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

176

Package pin #

208 324

54 M4

53 L3

52 K3

51 N1

50 M2

49 M1

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

ETPUA11

ETPUA23_O

(8)

RCH4_B

GPIO[125]

ETPUA12

DSPI_B_PCS[1]

RCH4_C

GPIO[126]

ETPUA13

DSPI_B_PCS[3]

GPIO[127]

ETPUA14

DSPI_B_PCS[4]

ETPUA9_O

(8)

RCH0_A

GPIO[128]

ETPUA15

DSPI_B_PCS[5]

RCH1_A

GPIO[129]

ETPUA16

DSPI_D_PCS[1]

RCH2_A

GPIO[130]

ETPUA17

DSPI_D_PCS[2]

RCH3_A

GPIO[131] eTPU A channel eTPU A channel (output only)

Reaction channel 4B

GPIO eTPU A channel

DSPI B peripheral chip select

Reaction channel 4C

GPIO eTPU A channel

DSPI B peripheral chip select

GPIO eTPU A channel

DSPI B peripheral chip select eTPU A channel (output only)

Reaction channel 0A

GPIO eTPU A channel

DSPI B peripheral chip select

Reaction channel 1A

GPIO eTPU A channel

DSPI D peripheral chip select

Reaction channel 2A

GPIO eTPU A channel

DSPI D peripheral chip select

Reaction channel 3A

GPIO

I/O

001

010

100

000

001

010

100

000

001

010

100

000

0001

0010

0100

1000

0000

001

010

100

000

001

010

100

000

125

126

127

128

129

130

131

VDDEH1

Slow

VDDEH1

Medium

VDDEH1

Medium

VDDEH1

Medium

VDDEH1

Medium

VDDEH1

Slow

VDDEH1

Slow

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

176

Package pin #

208 324

48 L2

47 L1

46 J4

42 J3

40 K2

39 K1

38 H3

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

ETPUA18

DSPI_D_PCS[3]

RCH4_A

GPIO[132]

ETPUA19

DSPI_D_PCS[4]

RCH5_A

GPIO[133]

ETPUA20

IRQ[8]

RCH0_B

FR_A_TX

GPIO[134]

ETPUA21

IRQ[9]

RCH0_C

FR_A_RX

GPIO[135]

ETPUA22

IRQ[10]

ETPUA17_O

(8)

GPIO[136]

ETPUA23

IRQ[11]

ETPUA21_O

(8)

FR_A_TX_EN

GPIO[137] eTPU A channel

DSPI D peripheral chip select

Reaction channel 4A

GPIO eTPU A channel

DSPI D peripheral chip select

Reaction channel 5A

GPIO eTPU A channel

External interrupt request

Reaction channel 0B

Flexray TX data channel A

GPIO eTPU A channel

External interrupt request

Reaction channel 0C

Flexray RX channel A

GPIO eTPU A channel

External interrupt request eTPU A channel (output only)

GPIO eTPU A channel

External interrupt request eTPU A channel (output only)

Flexray ch. A TX enable

GPIO

I/O

0001

0010

0100

1000

0000

0001

0010

0100

1000

0000

001

010

100

000

001

010

100

000

001

010

100

000

0001

0010

0100

1000

0000

132

133

134

135

136

137

VDDEH1

Slow

VDDEH1

Slow

VDDEH1

Slow

VDDEH1

Slow

VDDEH1

Slow

VDDEH1

Slow

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

176

Package pin #

208 324

37 H4

36 J2

35 J1

34 G4

32 H2

30 H1

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

ETPUA24

IRQ[12]

DSPI_C_SCK_LVD

S-

GPIO[138]

ETPUA25

IRQ[13]

DSPI_C_SCK_LVD

S+

GPIO[139]

ETPUA26

IRQ[14]

DSPI_C_SOUT_LV

DS-

GPIO[140]

ETPUA27

IRQ[15]

DSPI_C_SOUT_LV

DS+

DSPI_B_SOUT

GPIO[141]

ETPUA28

DSPI_C_PCS[1]

RCH5_B

GPIO[142]

ETPUA29

DSPI_C_PCS[2]

RCH5_C

GPIO[143] eTPU A channel

External interrupt request

LVDS negative DSPI clock

GPIO eTPU A channel

External interrupt request

LVDS positive DSPI clock

GPIO eTPU A channel

External interrupt request

LVDS negative DSPI data out

GPIO eTPU A channel

External interrupt request

LVDS positive DSPI data out

DSPI data out

GPIO eTPU A channel

DSPI C peripheral chip select

Reaction channel 5B

GPIO eTPU A channel

DSPI C peripheral chip select

Reaction channel 5C

GPIO

001

010

100

000

001

010

100

000

001

010

100

000

138

139

140

0001

0010

0100

1000

0000

141

001

010

100

000

001

010

100

000

142

143

I/O

VDDEH1

Slow +

LVDS

VDDEH1

Medium +

LVDS

VDDEH1

Slow +

LVDS

VDDEH1

Slow +

LVDS

VDDEH1

Medium

VDDEH1

Medium

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

176

Package pin #

208 324

28 G1

27 G3

26 F3

25 G2

24 F1

23 F2

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

ETPUA30

DSPI_C_PCS[3]

ETPUA11_O

(8)

GPIO[144]

ETPUA31

DSPI_C_PCS[4]

ETPUA13_O

(8)

GPIO[145]

EMIOS0

ETPUA0_O

(8)

ETPUA25_O

(8)

GPIO[179]

EMIOS1

ETPUA1_O

(8)

GPIO[180]

EMIOS2

ETPUA2_O

(8)

RCH2_B

GPIO[181]

EMIOS3

ETPUA3_O

(8)

GPIO[182]

EMIOS4

ETPUA4_O

(8)

RCH2_C

GPIO[183] eTPU A channel

DSPI C peripheral chip select eTPU A channel (output only)

GPIO eTPU A channel

DSPI C peripheral chip select eTPU A channel (output only)

GPIO eMIOS channel eTPU A channel (output only) eTPU A channel (output only)

GPIO eMIOS channel eTPU A channel (output only)

Reaction channel 2B

GPIO eMIOS channel eTPU A channel (output only)

Reaction channel 2C

GPIO

001

010

100

000

001

010

100

000

001

010

100

000

001

010

100

000

001

010

100

000

144

145

179

180

181

182

183

I/O

I/O eMIOS

VDDEH1

Medium

VDDEH1

Medium

VDDEH4

Slow

VDDEH4

Slow

VDDEH4

Slow

VDDEH4

Slow

VDDEH4

Slow

— /

WKPCFG

— /

WKPCFG

— / Up

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— / Up

— /

WKPCFG

— /

WKPCFG

176

Package pin #

208 324

22 E1

21 E2

63 T4

64 T5

65 N7

66 R6

67 R5

AB10

AB11

W12

AA11

AB12

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

EMIOS5

ETPUA5_O

(8)

GPIO[184]

EMIOS6

ETPUA6_O

(8)

GPIO[185]

EMIOS7

ETPUA7_O

(8)

GPIO[186]

EMIOS8

ETPUA8_O

(8)

SCI_B_TX

GPIO[187]

EMIOS9

ETPUA9_O

(8)

SCI_B_RX

GPIO[188]

EMIOS10

DSPI_D_PCS[3]

RCH3_B

GPIO[189]

EMIOS11

DSPI_D_PCS[4]

RCH3_C

GPIO[190]

EMIOS12

DSPI_C_SOUT

ETPUA27_O

(8)

GPIO[191] eMIOS channel eTPU A channel (output only)

GPIO eMIOS channel eTPU A channel (output only)

GPIO eMIOS channel eTPU A channel (output only) eSCI B TX

GPIO eMIOS channel eTPU A channel (output only) eSCI B RX

GPIO eMIOS channel

DSPI D peripheral chip select

Reaction channel 3B

GPIO eMIOS channel

DSPI D peripheral chip select

Reaction channel 3C

GPIO eMIOS channel

DSPI C data output eTPU A channel (output only)

GPIO

001

010

100

000

001

010

100

000

001

010

100

000

001

010

100

000

001

010

100

000

184

185

186

187

188

189

190

191

I/O

VDDEH4

Slow

VDDEH4

Slow

VDDEH4

Slow

VDDEH4

Slow

VDDEH4

Slow

VDDEH4

Medium

VDDEH4

Medium

VDDEH4

Medium

— /

WKPCFG

— / Down

— / Up

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— / Down

— / Up

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

176

Package pin #

208 324

—

68 P7

70 P8

71 R7

73 N8

75 R8

— AA12

— AB13

76 N10

Y12

W13

AA13

Y13

AB14

W15

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

EMIOS18

GPIO[197]

EMIOS19

GPIO[198]

EMIOS20

GPIO[199]

EMIOS21

GPIO[200]

EMIOS22

GPIO[201]

EMIOS23

GPIO[202]

EMIOS13

DSPI_D_SOUT

GPIO[192]

EMIOS14

IRQ[0]

ETPUA29_O

(8)

GPIO[193]

EMIOS15

IRQ[1]

GPIO[194]

EMIOS16

GPIO[195]

EMIOS17

GPIO[196] eMIOS channel

DSPI D data output

GPIO eMIOS channel

External interrupt request eTPU A channel (output only)

GPIO eMIOS channel

External interrupt request

GPIO eMIOS channel

GPIO

001

010

100

000

192

193

194

195

196

197

198

199

200

201

202

VDDEH4

Medium

VDDEH4

Slow

VDDEH4

Slow

VDDEH4

Slow

VDDEH4

Slow

VDDEH4

Slow

VDDEH4

Slow

VDDEH4

Slow

VDDEH4

Slow

VDDEH4

Slow

VDDEH4

Slow

Clock Synthesizer

I/O

— /

WKPCFG

— / Down

— / Up

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— / Down

— /

WKPCFG

— / Down

— / Up

— /

WKPCFG

— /

WKPCFG

— /

WKPCFG

— / Down

176

Package pin #

208 324

77 T8

78 R9

79 T9

AA14

AB15

Y14

—

AA15

Y15

AB16

AA16

—

AB17

W16

— —

80 R11

Y16

AA17

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

XTAL

EXTAL

EXTCLK

CLKOUT

ENGCLK

VDDREG

VRCCTL

VRC33

(20)

VDDA

VSSA

VDDA0

(21)

VSSA0

(22)

VDDA1

(21)

VSSA1

(22)

VDDPLL

VSTBY

Crystal oscillator output

Crystal oscillator input

External clock input

System clock output

Engineering clock output

Voltage Regulator Supply —

Voltage Regulator Control Output —

Internal regulator output

Input for external 3.3 V supply

—

— eQADC high reference voltage eQADC ground/low reference voltage eQADC high reference voltage eQADC ground/low reference voltage eQADC high reference voltage

—

— eQADC ground/low reference voltage

FMPLL Supply Voltage

Power Supply for Standby RAM

—

229

214

Power / Ground

5 V

—

3.3 V

5 V

VDDEH6

Analog

VDDEH6

Analog

VDDE5

Fast

VDDE5

Fast

—

— I

I —

5 V

—

5 V

—

1.2

0.9 V - 6 V

—

I / —

O / —

I/O / —

I / —

—

CLKOUT

ENGCLK

VDDREG

VRCCTL

VRC33

VDDA

VSSA

VDDA0

VSSA0

VDDA1

VSSA1

VDDPLL

VSTBY

176

Package pin #

208 324

P16

N16

V22

U22

—

— T14

— AA20

AB21

K16

N14

M22

V20

A15, D1,

N6, N12

A21, B1,

P4, W7, Y22

— — 6

— B11

—

— A11

— A4

C15

— A5

R16

A15, B15

W22

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

VDD

VDDE12

VDDE2

(23)

VDDE5

VDDE-EH

VDDEH1A

(25)

VDDEH1B

(25)

VDDEH1AB

(25)

Core supply for input or decoupling

External supply input for calibration bus interfaces

External supply input for EBI interfaces

—

External supply input for

ENGCLK, CLKOUT and EBI signals DATA[0:15]

—

External supply for EBI interfaces —

I/O Supply Input

—

I/O Supply Input

—

I/O Supply Input

—

I 1.2 V

1.8 V - 3.3 V

3.0 V - 5 V

3.3 V - 5.0 V

I / —

176

VDDEH1B

(25)

VDDEH1AB

(25)

—

Package pin #

VDD

VDDE12

VDDE2

(24)

VDDE5

VDDE-EH

VDDEH1A

(25)

—

33,

45,

62,

103,

132,

149,

176

B1, B16,

C2, D3,

E4, N5,

P4, P13,

R3, R14,

T2, T15

A2, A20, B3,

C4, C22, D5,

V19, W5,

W20, Y4, Y21,

AA3, AA22,

AB2

— —

—

M9, M10, N11,

P11, W6, W8,

Y5, AA4, AA6,

AA10, AB3

— T13

W17, Y18,

AA19, AB20

—

R3, W2

—

208

—

324

—

VDDEH4

(26)

I/O Supply Input

— — I 3.3 V - 5.0 V I / — VDDEH4

(26)

— — —

VDDEH4A

(26)

I/O Supply Input

— — I 3.3 V - 5.0 V I / — VDDEH4A

(26)

55 — —

VDDEH4B

(26)

I/O Supply Input

— — I 3.3 V - 5.0 V I / — VDDEH4B

(26)

74 — —

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

VDDEH4AB

(26)

I/O Supply Input

— — I 3.3 V - 5.0 V I / —

176

VDDEH4AB

(26)

—

Package pin #

208

W14

324

VDDEH6

(27)

I/O Supply Input

— — I 3.3 V - 5.0 V I / — VDDEH6

(27)

— — —

VDDEH6A

(27)

I/O Supply Input

— — I 3.3 V - 5.0 V I / — VDDEH6A

(27)

95 — —

VDDEH6B

(27)

I/O Supply Input

— — I 3.3 V - 5.0 V I / — VDDEH6B

(27)

110 — —

VDDEH6AB

(27)

I/O Supply Input

— — I 3.3 V - 5.0 V I / — VDDEH6AB

(27)

— F13 H19, U19

I/O Supply Input

VDDEH7 — — I 3.3 V - 5.0 V I / — VDDEH7 — D12 D15

I/O Supply Input

VDDEH7A — — I 3.3 V - 5.0 V I / — VDDEH7A 125 — —

Table 4.

Name

SPC564A80 signal properties (continued)

Function

(1)

(2)

PCR

Field

(3)

PCR

(4)

I/O

Type

Voltage

(5)

Pad Type

(6)

Status

(7)

During Reset

After

Reset

I/O Supply Input

VDDEH7B — — I 3.3 V - 5.0 V I / — VDDEH7B

176

Package pin #

208 324

138 — —

VSS Ground — — I — I / — VSS

15,

29,

43,

57,

72,

90,

94,

96,

108,

115,

127,

133,

140

A1, A16,

B2, B15,

C3, C14,

D4, D13,

G7, G8,

G9,

G10,

H7, H8,

H9, H10,

J7, J8,

J9, J10,

K7,

K8, K9,

K10,

M16,

N4, N13,

P3, P14,

R2, R15,

T1, T16

A1, A22, B2,

B21, C3, C20,

D4, D19, J9,

J10, J11, J12,

J13, K9, K10,

K11, K12,

K13, K14, L9,

L10, L11, L12,

L13, L14,

M11, M12,

M13, M14, N9,

N10, N12,

N13, N14, P9,

P10, P12,

P13, P14,

T21, T22,

W4,W19, Y3,

Y20, AA2,

AA21, AB1,

AB22

For each pin in the table, each line in the Function column is a separate function of the pin. For all I/O pins the selection of primary pin function or secondary function or

GPIO is done in the SIU except where explicitly noted. See the Signal details table for a description of each signal.

The P/A/G column indicates the position a signal occupies in the muxing order for a pin—Primary, Alternate 1, Alternate 2, Alternate 3, or GPIO. Signals are selected by setting the PA field value in the appropriate PCR register in the SIU module. The PA field values are as follows: P - 0b0001, A1 - 0b0010, A2 - 0b0100, A3 - 0b1000, or G -

0b0000. Depending on the register, the PA field size can vary in length. For PA fields having fewer than four bits, remove the appropriate number of leading zeroes from these values.

The Pad Configuration Register (PCR) PA field is used by software to select pin function.

Values in the PCR No. column refer to registers in the System Integration Unit (SIU). The actual register name is “SIU_PCR” suffixed by the PCR number. For example,

PCR[190] refers to the SIU register named SIU_PCR190.

The VDDE and VDDEH supply inputs are broken into segments. Each segment of slow I/O pins (VDDEH) may have a separate supply in the 3.3 V to 5.0 V range (-

10%/+5%). Each segment of fast I/O (VDDE) may have a separate supply in the 1.8 V to 3.3 V range (+/- 10%).

See Table 5

for details on pad types.

The Status During Reset pin is sampled after the internal POR is negated. Prior to exiting POR, the signal has a high impedance. Terminology is O - output, I - input, Up - weak pull up enabled, Down - weak pull down enabled, Low - output driven low, High - output driven high. A dash for the function in this column denotes that both the input and output buffer are turned off. The signal name to the left or right of the slash indicates the pin is enabled.

Output only.

When used as ETRIG, this pin must be configured as an input. For GPIO it can be configured either as an input or output.

10. Maximum frequency is 50 kHz.

11. The SIU_PCR219 register is unusual in that it controls pads for two separate device pins: GPIO[219] and MCKO. See the SPC564A80 Microcontroller Reference Manual

(SIU chapter) for details.

12. Multivoltage pads are automatically configured in low swing mode when a JTAG or Nexus function is selected, otherwise they are high swing.

13. On LQFP176 and LBGA208 packages, this pin is tied low internally.

14. Nexus multivoltage pads default to 5 V operation until the Nexus module is enabled.

15. EVTO should be clamped to 3.3 V to prevent possible damage to external tools that only support 3.3 V.

16. Do not connect pin directly to a power supply or ground.

17. This signal name is used to support legacy naming.

18. During and just after POR negates, internal pull resistors can be enabled, resulting in as much as 4 mA of current draw. The pull resistors are disabled when the system clock propagates through the device.

19. For pins AN12-AN15, if the analog features are used the VDDEH7 input pins should be tied to VDDA because that segment must meet the VDDA specification to support analog input function.

20. Do not use VRC33 to drive external circuits.

21. VDDA0 and VDDA1 are shorted together internally in BGA packages. In the QFP package the two pads are double bonded on one pin called VDDA.

22. VSSA0 and VSSA1 are shorted together internally in BGA packages. In the QFP package the two pads are double bonded on one pin called VSSA.

23. VDDE2 and VDDE3 are shorted together in all production packages.

24. VDDE2 and VDDE3 are shorted together in all production packages.

25. VDDEH1A, VDDEH1B, and VDDEH1AB are shorted together in all production packages. The separation of the signal names is present to support legacy naming, however they should be considered as the same signal in this document.

26. VDDEH4, VDDEH4A, VDDEH4B, and VDDEH4AB are shorted together in all production packages. The separation of the signal names is present to support legacy naming, however they should be considered as the same signal in this document.

27. VDDEH6, VDDEH6A, VDDEH6B, and VDDEH6AB are shorted together in all production packages. The separation of the signal names is present to support legacy naming, however they should be considered as the same signal in this document.

SPC564A74L7, SPC564A80B4, SPC564A80L7 Pinout and signal description

Table 5.

Pad types

Pad Type Name I/O Voltage Range

Slow

Medium

Fast

MultiV

(1),(2)

Analog

LVDS pad_ssr_hv pad_msr_hv pad_fc pad_multv_hv pad_ae_hv pad_lo_lv

3.0V - 5.5 V

3.0 V - 5.5 V

3.0 V - 3.6 V

3.0 V - 5.5 V (high swing mode)

3.0 V - 3.6 V (low swing mode)

0.0 - 5.5 V

—

Multivoltage pads are automatically configured in low swing mode when a JTAG or Nexus function is selected, otherwise they are high swing.

VDDEH7 supply cannot be below 4.5 V when in low-swing mode.

Table 6.

Signal details

Signal Module or Function

CLKOUT

ENGCLK

EXTAL

Clock Generation

Description

SPC564A80 clock output for the external/calibration bus interface

Clock for external ASIC devices

Input pin for an external crystal oscillator or an external clock source based on the value driven on the PLLREF pin at reset.

PLLREF is used to select whether the oscillator operates in xtal mode or external reference mode from reset. PLLREF=0 selects external reference mode. On the 324BGA package,

PLLREF is bonded to the ball used for PLLCFG[0] for compatibility with previous devices .

PLLREF

Clock Generation

Reset/Configuration

XTAL

DSPI_B_SCK_LVDS-

DSPI_B_SCK_LVDS+

DSPI_B_SOUT_LVDS-

DSPI_B_SOUT_LVDS+

Clock Generation

DSPI

For the 176-pin QFP and 208-ball BGA packages:

0: External reference clock is selected.

1: XTAL oscillator mode is selected

For the 324 ball BGA package:

If RSTCFG is 0:

0: External reference clock is selected.

1: XTAL oscillator mode is selected.

If RSTCFG is 1, XTAL oscillator mode is selected.

Crystal oscillator input

LVDS pair used for DSPI_B TSB mode transmission

Doc ID 15399 Rev 9 73/157

Pinout and signal description SPC564A74L7, SPC564A80B4, SPC564A80L7

Table 6.

Signal details (continued)

Signal Module or Function

DSPI_C_SCK_LVDS-

DSPI_C_SCK_LVDS+

DSPI_C_SOUT_LVDS-

DSPI_C_SOUT_LVDS+

PCS_B[0]

PCS_C[0]

PCS_D[0]

PCS_B[1:5]

PCS_C[1:5]

PCS_D[1:5]

SCK_B

SCK_C

SCK_D

SIN_B

SIN_C

SIN_D

SOUT_B

SOUT_C

SOUT_D

DSPI

DSPI_B - DSPI_D

Description

LVDS pair used for DSPI_C TSB mode transmission

Peripheral chip select when device is in master mode—slave select when used in slave mode

Peripheral chip select when device is in master mode—not used in slave mode

DSPI clock—output when device is in master mode; input when in slave mode

DSPI data in

DSPI data out

The ADDR[10:31] signals specify the physical address of the bus transaction.

ADDR[10:31]

ALE

BDIP

CS[0:3]

DATA[0:31]

EBI

The 26 address lines correspond to bits 3-31 of the EBI’s 32-bit internal address bus.

ADDR[15:31] can be used as Address and Data signals when configured appropriately for a multiplexed external bus. This allows 32-bit data operations, or 16-bit data operations without using DATA[0:15] signals.

The Address Latch Enable (ALE) signal is used to demultiplex the address from the data bus. It is asserted while the least significant 16 bits of the address are present in the multiplexed address/data bus.

BDIP is asserted to indicate that the master is requesting another data beat following the current one.

CSx is asserted by the master to indicate that this transaction is targeted for a particular memory bank on the Primary external bus.

The DATA[0:31] signals contain the data to be transferred for the current transaction.

OE is used to indicate when an external memory is permitted to drive back read data. External memories must have their data output buffers off when OE is negated. OE is only asserted for chip-select accesses.

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SPC564A74L7, SPC564A80B4, SPC564A80L7 Pinout and signal description

Table 6.

Signal details (continued)

Signal Module or Function

RD_WR

WE[2:3]

WE[0:3]/BE[0:3] eMIOS[0:23]

AN[0:39]

FCK

MA[0:2]

REFBYPC

SDI

SDO

SDS

VRH

VRL

SCI_A_RX

SCI_B_RX

SCI_C_RX

SCI_A_TX

SCI_B_TX

SCI_C_TX

ETPU_A[0:31]

EBI

EBI eMIOS eQADC eQADC eQADC eQADC eQADC eQADC eQADC eQADC eQADC eSCI_A - eSCI_C eSCI_A - eSCI_C eTPU

Description

RD_WR indicates whether the current transaction is a read access or a write access.

TA is asserted to indicate that the slave has received the data

(and completed the access) for a write cycle, or returned data for a read cycle. If the transaction is a burst read, TA is asserted for each one of the transaction beats. For write transactions, TA is only asserted once at access completion, even if more than one write data beat is transferred.

The Transfer Start signal (TS) is asserted by the SPC564A80 to indicate the start of a transfer.

Write enables are used to enable program operations to a particular memory. WE[2:3] are only asserted for write accesses

Write enables are used to enable program operations to a particular memory. These signals can also be used as byte enables for read and write operation by setting the WEBS bit in the appropriate EBI Base Register (EBI_BR n ). WE[0:3] are only asserted for write accesses. BE[0:3] are asserted for both read and write accesses eMIOS I/O channels

Single-ended analog inputs for analog-to-digital converter eQADC free running clock for eQADC SSI.

These three control bits are output to enable the selection for an external Analog Mux for expansion channels.

Bypass capacitor input

Serial data in

Serial data out

Serial data select

Voltage reference high input

Voltage reference low input eSCI receive eSCI transmit eTPU I/O channel

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Pinout and signal description

EVTO

MCKO

MDO[0:11]

(1)

MSEO[0:1]

(1)

RDY

Nexus

SPC564A74L7, SPC564A80B4, SPC564A80L7

Table 6.

Signal details (continued)

Signal Module or Function

RCH0_[A:C]

RCH1_[A:C]

RCH2_[A:C]

RCH3_[A:C]

RCH4_[A:C]

RCH5_[A:C]

TCRCLKA

CAN_A_TX

CAN_B_TX

CAN_C_TX

CAN_A_RX

CAN_B_RX

CAN_C_RX

FR_A_RX

FR_B_RX

FR_A_TX_EN

FR_B_TX_EN

FR_A_TX

FR_B_TX

JCOMP

TCK

TDI

TDO

TMS eTPU2

Reaction Module eTPU2

FlexCan_A -

FlexCAN_C

FlexCAN_A -

FlexCAN_C

FlexRay

JTAG

EVTI Nexus

Description eTPU2 reaction channels. Used to control external actuators, e.g., solenoid control for direct injection systems and valve control in automatic transmissions

Input clock for TCR time base

FlexCAN transmit

FlexCAN receive

FlexRay receive (Channels A, B)

FlexRay transmit enable (Channels A, B)

Flexray transmit (Channels A, B)

Enables the JTAG TAP controller.

Clock input for the on-chip test logic.

Serial test instruction and data input for the on-chip test logic.

Serial test data output for the on-chip test logic.

Controls test mode operations for the on-chip test logic.

EVTI is an input that is read on the negation of RESET to enable or disable the Nexus Debug port. After reset, the EVTI pin is used to initiate program synchronization messages or generate a breakpoint.

Output that provides timing to a development tool for a single watchpoint or breakpoint occurrence.

MCKO is a free running clock output to the development tools which is used for timing of the MDO and MSEO signals.

Trace message output to development tools. This pin also indicates the status of the crystal oscillator clock following a power-on reset, when MDO[0] is driven high until the crystal oscillator clock achieves stability and is then negated.

Output pin—Indicates the start or end of the variable length message on the MDO pins

Nexus Ready Output (RDY) is an output that indicates to the development tools the data is ready to be read from or written to the Nexus read/write access registers.

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Table 6.

Signal details (continued)

Signal Module or Function Description

Two BOOTCFG signals are implemented in SPC564A80

MCUs.

BOOTCFG[0:1]

WKPCFG

ETRIG[2:3]

GPIO[206] ETRIG0

(Input)

GPIO[207] ETRIG1

(Input)

The BAM program uses the BOOTCFG0 bit to determine where to read the reset configuration word, and whether to initiate a FlexCAN or eSCI boot.

The BOOTCFG1 pin is sampled during the assertion of the

RSTOUT signal, and the value is used to update the RSR and the BAM boot mode

SIU - Configuration

See the SPC564A80 Microcontroller Reference Manual for more information.

The following values are for BOOTCFG[0:1}:

00:Boot from internal flash memory

01:FlexCAN/eSCI boot

10:Boot from external memory using EBI

11:Reserved

Note: For the 176-pin QFP and 208-ball BGA packages

BOOTCFG[0] is always 0 since the EBI interface is not available.

The WKPCFG pin is applied at the assertion of the internal reset signal (assertion of RSTOUT), and is sampled 4 clock cycles before the negation of the RSTOUT pin.

The value is used to configure whether the eTPU and eMIOS pins are connected to internal weak pull up or weak pull down devices after reset. The value latched on the WKPCFG pin at reset is stored in the Reset Status Register (RSR), and is updated for all reset sources except the Debug Port Reset and

Software External Reset.

0:Weak pulldown applied to eTPU and eMIOS pins at reset

1:Weak pullup applied to eTPU and eMIOS pins at reset.

SIU - eQADC Triggers External signal eTRIGx triggers eQADC CFIFOx

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Pinout and signal description SPC564A74L7, SPC564A80B4, SPC564A80L7

Table 6.

Signal details (continued)

Signal Module or Function Description

The IRQ[0:15] pins connect to the SIU IRQ inputs. IMUX Select

IRQs.

IRQ[0:5]

IRQ[7:15]

SIU - External

Interrupts

See the SPC564A80 Microcontroller Reference Manual for more information.

NMI

SIU - External

Interrupts

Non-Maskable Interrupt

Configurable general purpose I/O pins. Each GPIO input and output is separately controlled by an 8-bit input (GPDI) or output (GPDO) register. Additionally, each GPIO pins is configured using a dedicated SIU_PCR register.

GPIO[0:3]

GPIO[8:43]

GPIO[62:65]

GPIO[68:70]

GPIO[75:145]

GPIO[179:204]

GPIO[208:213]

GPIO[219]

GPIO[244:245]

SIU - GPIO The GPIO pins are generally multiplexed with other I/O pin functions.

See The SPC564A80 Microcontroller Reference Manual for more information.

–

The RESET pin is an active low input. The RESET pin is asserted by an external device during a power-on or external reset. The internal reset signal asserts only if the RESET pin asserts for 10 clock cycles. Assertion of the RESET pin while the device is in reset causes the reset cycle to start over.

RESET SIU - Reset

The RESET pin has a glitch detector which detects spikes greater than two clock cycles in duration that fall below the switch point of the input buffer logic of the VDDEH input pins.

The switch point lies between the maximum VIL and minimum

VIH specifications for the VDDEH input pins.

Used to enable or disable the PLLREF and the BOOTCFG[0:1] configuration signals.

RSTCFG SIU - Reset

0:Get configuration information from BOOTCFG[0:1] and

PLLREF

1:Use default configuration of booting from internal flash with crystal clock source

RSTOUT SIU - Reset

For the 176-pin QFP and 208-ball BGA packages RSTCFG is always 0, so PLLREF and BOOTCFG signals are used.

The RSTOUT pin is an active low output that uses a push/pull configuration. The RSTOUT pin is driven to the low state by the

MCU for all internal and external reset sources. There is a delay between initiation of the reset and the assertion of the

RSTOUT pin.

Do not connect pin directly to a power supply or ground.

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Table 7.

Power/ground segmentation

Power Segment Voltage

VDDE2

VDDE3

VDDE5

VDDE12

VDDE-EH

VDDEH1

VDDEH4

VDDEH6

VDDEH7

VDDA

VRC33

(1)

1.8 V - 3.3 V

3.0 V - 5 V

3.3 V - 5.0 V

5 V

3.3 V

I/O Pins Powered by Segment

CS0, CS1, CS2, CS3,RD_WR, BDIP, WE0, WE1, OE, TS, TA

ADDR12, ADDR13, ADDR14, ADDR15

DATA0, DATA1, DATA2, DATA3, DATA4, DATA5, DATA6, DATA7,

DATA8, DATA9, DATA10, DATA11, DATA12, DATA13, DATA14,

DATA15, CLKOUT, ENGCLK

CAL_CS0, CAL_CS2, CAL_CS3 CAL_ADDR12, CAL_ADDR13,

CAL_ADDR14, CAL_ADDR15, CAL_ADDR16, CAL_ADDR17,

CAL_ADDR18, CAL_ADDR19, CAL_ADDR20, CAL_ADDR21,

CAL_ADDR22, CAL_ADDR23, CAL_ADDR24, CAL_ADDR25,

CAL_ADDR26, CAL_ADDR27, CAL_ADDR28, CAL_ADDR29,

CAL_ADDR30, CAL_DATA0, CAL_DATA1, CAL_DATA2,

CAL_DATA3, CAL_DATA4, CAL_DATA5, CAL_DATA6, CAL_DATA7,

CAL_DATA8, CAL_DATA9, CAL_DATA10, CAL_DATA11,

CAL_DATA12, CAL_DATA13, CAL_DATA14, CAL_DATA15,

CAL_RD_WR, CAL_WE0, CAL_WE1, CAL_OE, CAL_TS

ADDR16, ADDR17, ADDR18, ADDR19, ADDR20, ADDR21,

ADDR22, ADDR23, ADDR24, ADDR25, ADDR26, ADDR27,

ADDR28, ADDR29, ADDR30, ADDR31

ETPUA10, ETPUA11, ETPUA12, ETPUA13, ETPUA14, ETPUA15,

ETPUA16, ETPUA17, ETPUA18, ETPUA19, ETPUA20, ETPUA21,

ETPUA22, ETPUA23, ETPUA24, ETPUA25, ETPUA26, ETPUA27,

ETPUA28, ETPUA29, ETPUA30, ETPUA31

EMIOS0, EMIOS1, EMIOS2, EMIOS3, EMIOS4, EMIOS5, EMIOS6,

EMIOS7, EMIOS8, EMIOS9, EMIOS10, EMIOS11, EMIOS12,

EMIOS13, EMIOS14, EMIOS15, EMIOS16, EMIOS17, EMIOS18,

EMIOS19, EMIOS20, EMIOS21, EMIOS22, EMIOS23, TCRCLKA,

ETPUA0, ETPUA1, ETPUA2, ETPUA3, ETPUA4, ETPUA5,

ETPUA6, ETPUA7, ETPUA8, ETPUA9, ETPUA0

RESET, RSTOUT, PLLREF, PLLCFG1, RSTCFG, BOOTCFG0,

BOOTCFG1, WKPCFG, CAN_A_TX, CAN_A_RX, CAN_B_TX,

CAN_B_RX, CAN_C_TX, CAN_C_RX, SCI_A_TX, SCI_A_RX,

SCI_B_TX, SCI_C_RX, DSPI_B_SCK, DSPI_B_SIN,

DSPI_B_SOUT, DSPI_B_PCS[0], DSPI_B_PCS[1],

DSPI_B_PCS[2], DSPI_B_PCS[3], DSPI_B_PCS[4],

DSPI_B_PCS[5], SCI_B_RX, SCI_C_TX, EXTAL, XTAL

EMIOS14, EMIOS 15, GPIO98, GPIO99, GPIO203, GPIO204,

GPIO206, GPIO207, GPIO219, EVTI, EVTO, MDO4, MDO5,

MDO6, MDO7, MDO8, MDO9, MDO10, MDO11, MSEO0, MSEO1,

RDY, TCK, TDI, TDO, TMS, JCOMP, DSPI_A_SCK, DSPI_A_SIN,

DSPI_A_SOUT, DSPI_A_PCS[0], DSPI_A_PCS[1],

DSPI_A_PCS[4], DSPI_A_PCS[5], AN12-SDS, AN13-SDO, AN14-

SDI, AN15-FCK

AN0, AN1, AN2, AN3, AN4, AN5, AN6, AN7, AN8, AN9, AN10,

AN11, AN16, AN17, AN18, AN19, AN20, AN21, AN22, AN23,

AN24, AN25, AN26, AN27, AN28, AN29, AN30, AN31, AN32,

AN33, AN34, AN35, AN36, AN37, AN38, AN39, VRH, VRL,

REFBYBC

MCKO, MDO0, MDO1, MDO2, MDO3

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Pinout and signal description SPC564A74L7, SPC564A80B4, SPC564A80L7

Table 7.

Power/ground segmentation (continued)

Power Segment Voltage I/O Pins Powered by Segment

VDDREG

VRCCTL

VDDPLL

VSTBY

VSS

5 V

—

1.2 V

0.95–1.2 V

(unregulated mode)

2.0–5.5 V (regulated mode)

—

Do not use VRC33 to drive external circuits.

Other Power Segments

—

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SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics

This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the SPC564A80 series of MCUs.

The electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluation. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon these specifications will be met. Finalized specifications will be published after complete characterization and device qualifications have been completed.

In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol column.

In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol “SR” for System Requirement is included in the

Symbol column.

The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the classifications listed in

Table 8 are used and

the parameters are tagged accordingly in the tables where appropriate.

Table 8.

Parameter classifications

Classification tag

Tag description

Those parameters are guaranteed during production testing on each individual device.

Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations.

Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category.

Those parameters are derived mainly from simulations.

Note: The classification is shown in the column labeled “C” in the parameter tables where appropriate.

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Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7

Table 9.

Absolute maximum ratings

(1)

FLASH

STBY

DDPLL

SSPLL

Symbol

RC33

DDEH

DDREG

DDA

DDE

– V

SSA

– V

SSA

– V

MAXD

MAXA

Value

Parameter Conditions min max

SR 1.2 V core supply voltage

(2)

SR Flash core voltage

(3),(4)

SR SRAM standby voltage

(5)

SR Clock synthesizer voltage

Voltage regulator control input voltage

(4)

SR Analog supply voltage

(5)

Reference to V

SSA

SR I/O supply voltage

(4),(6)

SR I/O supply voltage

(5)

–0.3

1.32

3.6

1.32

3.6

SR DC input voltage

(7)

DDEH

DDE

powered I/O pads

DDA

powered I/O pads

Voltage regulator supply voltage

SR Analog reference high voltage Reference to VRL

SR V

differential voltage

SR V

REF

differential voltage

VRL to V

SSA

differential voltage

SSPLL

to V

differential voltage

Maximum DC digital input current

(11)

Maximum DC analog input current

(12)

Per pin, applies to all digital pins

Per pin, applies to all analog pins

–0.3

5.5

3.6

5.5

–1.0

(8)

–1.0

(10)

–1.0

DDEH

0.3 V

(9)

DDE

0.3 V

(10)

5.5

–0.3

–0.1

–0.3

–0.1

–3

—

5.5

0.1

5.5

0.3

0.1

Unit

V mA mA

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Table 9.

Absolute maximum ratings

(1)

(continued)

Value

Symbol Parameter Conditions Unit min max

Maximum operating temperature range - die junction temperature

–40.0

150.0

STG

SR Storage temperature range –55.0

150.0

SDR

Maximum solder temperature

(13)

SR Moisture sensitivity level

(14)

— 260.0

MSL — 3

Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device.

Allowed 2 V for 10 hours cumulative time, remaining time at 1.2 V +10%.

The V

FLASH

supply is connected to V devices only.

RC33

in the package substrate. This specification applies to calibration package

Allowed 5.3 V for 10 hours cumulative time, remaining time at 3.3 V +10%.

Allowed 5.9 V for 10 hours cumulative time, remaining time at 5 V +10%.

All functional non-supply I/O pins are clamped to V

SS and V

DDE

, or V

DDEH

AC signal overshoot and undershoot of up to 2.0 V of the input voltages is permitted for an accumulative duration of 60 hours over the complete lifetime of the device (injection current not limited for this duration).

Internal structures hold the voltage greater than –1.0 V if the injection current limit of 2 mA is met.

Internal structures hold the input voltage less than the maximum voltage on all pads powered by V

DDEH maximum injection current specification is met (2 mA for all pins) and V

DDEH

supplies, if the

is within the operating voltage specifications.

10. Internal structures hold the input voltage less than the maximum voltage on all pads powered by V maximum injection current specification is met (2 mA for all pins) and V

DDE

supplies, if the

is within the operating voltage specifications.

11. Total injection current for all pins (including both digital and analog) must not exceed 25 mA.

12. Total injection current for all analog input pins must not exceed 15 mA.

13. Solder profile per IPC/JEDEC J-STD-020D.

14. Moisture sensitivity per JEDEC test method A112.

Table 10.

Thermal characteristics for 176-pin QFP

(1)

Symbol



C Parameter

CC D Junction-to-Ambient, Natural Convection

(2)

CC D Junction-to-Ambient, Natural Convection

(2)

R 

JMA

R 

JMA

D Junction-to-Moving-Air, Ambient

(2)

D Junction-to-Moving-Air, Ambient

(2)

Conditions

Single layer board - 1s

Four layer board - 2s2p

200 ft./min., single layer board - 1s at 200 ft./min., four layer board - 2s2p

R 

CC D Junction-to-Board

(3)

Value

Unit

°C/W

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Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7

Table 10.

Thermal characteristics for 176-pin QFP

(1)

(continued)

Symbol C Parameter Conditions

R 

JCtop



CC D Junction-to-Case

(4)

CC D

Junction-to-Package Top, Natural

Convection

(5)

Value

Unit

°C/W

Thermal characteristics are targets based on simulation that are subject to change per device characterization.

Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets

JEDEC specification for this package.

Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package.

Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.

Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

Table 11.

Thermal characteristics for 208-pin LBGA

(1)

Symbol C Parameter Conditions Value Unit



CC D

Junction-to-Ambient, Natural

Convection

(2),(3)

CC D

Junction-to-Ambient, Natural

Convection

(2),(4)

One layer board - 1s

Four layer board - 2s2p

°C/W





JMA



D Junction-to-Moving-Air, Ambient

CC D Junction-to-board

(5)

CC D Junction-to-case

(6)

CC D

Junction-to-package top natural convection

(7)

(2),(4)

at 200 ft./min., one layer board at 200 ft./min., four layer board 2s2p

Four layer board - 2s2p

°C/W

Thermal characteristics are targets based on simulation that are subject to change per device characterization.

Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.

Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method

(MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.

Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

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Table 12.

Thermal characteristics for 324-pin PBGA

(1)

Symbol



C Parameter

CC D Junction-to-Ambient, Natural Convection

(2)

CC D Junction-to-Ambient, Natural Convection

(2)



JMA

D Junction-to-Moving-Air, Ambient

(2)

Conditions

Single layer board - 1s

Four layer board - 2s2p at 200 ft./min., single layer board at 200 ft./min., four layer board 2s2p



JCtop



CC D Junction-to-Board

(3)

CC D Junction-to-Case

(4)

CC D

Junction-to-Package Top, Natural

Convection

(5)

Value

Unit

°C/W

Thermal characteristics are targets based on simulation that are subject to change per device characterization.

Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets

JEDEC specification for this package.

Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package.

3.3.1 General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, T

, can be obtained from the equation:

Equation 1 T

= T

+ (R 

* P

) where:

= ambient temperature for the package ( o

R 

= junction-to-ambient thermal resistance ( o

C/W)

= power dissipation in the package (W)

●

The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance depends on the:

Construction of the application board (number of planes)

Effective size of the board which cools the component

Quality of the thermal and electrical connections to the planes

Power dissipated by adjacent components

Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced.

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Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7

●

As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. The value obtained on a board with the internal planes is usually within the normal range if the application board has:

One oz. (35 micron nominal thickness) internal planes

Components are well separated

Overall power dissipation on the board is less than 0.02 W/cm

The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device.

At a known board temperature, the junction temperature is estimated using the following equation:

Equation 2 T

= T

+ (R 

* P

) where:

= board temperature for the package perimeter ( o

R 

= junction-to-board thermal resistance ( o

C/W) per JESD51-8S

= power dissipation in the package (W)

When the heat loss from the package case to the air does not factor into the calculation, an acceptable value for the junction temperature is predictable. Ensure the application board is similar to the thermal test condition, with the component soldered to a board with internal planes.

The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal resistance:

Equation 3 R 

= R 

+ R 

CA where:

R 

= junction-to-ambient thermal resistance ( o

C/W)

R 

= junction-to-case thermal resistance ( o

C/W)

R 

= case to ambient thermal resistance ( o

C/W)

R 

is device related and is not affected by other factors. The thermal environment can be controlled to change the case-to-ambient thermal resistance, R 

. For example, change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where

90% of the heat flow is through the case to heat sink to ambient. For most packages, a better model is required.

A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit

86/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics board. This model can be used to generate simple estimations and for computational fluid dynamics (CFD) thermal models.

To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization parameter (



) to determine the junction temperature by measuring the temperature at the top center of the package case using the following equation:

Equation 4 T

= T

+ (



x P

) where:

= thermocouple temperature on top of the package ( o



= thermal characterization parameter ( o

C/W)

= power dissipation in the package (W)

The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire.

References:

Semiconductor Equipment and Materials International

3081 Zanker Road

San Jose, CA 95134

USA

(408) 943-6900

MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering

Documents at 800-854-7179 or 303-397-7956.

JEDEC specifications are available on the WEB at http://www.jedec.org.

● C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an

Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.

● G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled

Applications”, Electronic Packaging and Production, pp. 53-58, March 1998.

● B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal

Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San

Diego, 1999, pp. 212-220.

Doc ID 15399 Rev 9 87/157

Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7

3.4 EMI (electromagnetic interference) characteristics

Table 13.

EMI Testing Specifications

(1)

Symbol Parameter Conditions Clocks

Frequency

Range

Radiated emissions, electric field

RE_TEM

150 kHz – 50

MHz

DDREG

= 5.25 V;

= 25 °C

150 kHz – 30 MHz

RBW 9 kHz, Step

Size 5 kHz

16 MHz crystal

40 MHz bus

No PLL frequency modulation

50 – 150 MHz

150 – 500 MHz

500 – 1000 MHz

IEC Level

SAE Level

150 kHz– 50

MHz

30 MHz – 1 GHz -

RBW 120 kHz,

Step Size 80 kHz

16 MHz crystal

40 MHz bus

± 2% PLL frequency modulation

50 – 150 MHz

150 – 500 MHz

500 – 1000 MHz

IEC Level

SAE Level

EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03 and IEC 61967-2.

Level

(Max)

Unit dB



—

— dB



—

3.5 Electrostatic discharge (ESD) characteristics

Table 14.

ESD ratings

(1),(2)

Symbol Parameter Conditions Value Unit

—

SR ESD for Human Body Model (HBM)

HBM circuit description

—

2000

1500

100

— SR

ESD for field induced charge Model

(FDCM)

All pins

Corner pins

Positive pulses (HBM)

500

750

— SR Number of pulses per pin

—

— Negative pulses (HBM) 1

— SR Number of pulses — 1

All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.

Device failure is defined as: “If after exposure to ESD pulses, the device does not meet the device specification requirements, which includes the complete DC parametric and functional testing at room temperature and hot temperature.”

—

 pF

88/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics

3.6 Power management control (PMC) and power on reset (POR) electrical specifications

Table 15.

PMC Operating Conditions and External Regulators Supply Voltage

ID Name Parameter Min Typ

Jtemp SR — Junction temperature

Vddreg SR — PMC 5 V supply voltage V

DDREG

Vdd SR —

Core supply voltage 1.2 V V

when external regulator is used without disabling the internal regulator (PMC unit turned on, LVI monitor active)

(1)

—

Ivdd

SR —

Core supply voltage 1.2 V V

when external regulator is used with a disabled internal regulator (PMC unit turned-off, LVI monitor disabled)

SR —

Voltage regulator core supply maximum required DC output current

Vdd33 SR —

Regulated 3.3 V supply voltage when external regulator is used without disabling the internal regulator (PMC unit turned-on, internal 3.3V regulator enabled, LVI monitor active)

(3)

— SR —

Regulated 3.3 V supply voltage when external regulator is used with a disabled internal regulator

(PMC unit turned-off, LVI monitor disabled)

— SR —

Voltage regulator 3.3 V supply maximum required DC output current

–40

4.75

1.26

(2)

1.14

445

3.3

An internal regulator controller can be used to regulate core supply.

The minimum supply required for the part to exit reset and enter in normal run mode is 1.28 V.

An internal regulator can be used to regulate 3.3 V supply.

1.3

1.2

—

3.45

3.3

—

Max

150

5.25

1.32

—

3.6

—

Unit

°C

V mA

Table 16.

PMC Electrical Characteristics

ID Name Parameter

VBG

—

Min Typ

CC C

Nominal bandgap voltage reference

— 1.219

CC P

Untrimmed bandgap reference voltage

VBG - 7% VBG

CC P

Trimmed bandgap reference

VBG -10mV VBG voltage (5 V, 27 °C)

CC C

Bandgap reference temperature variation

CC C

Bandgap reference supply voltage variation

—

100

3000

Max

—

Unit

Vbg + 6% V

VBG +

10mV

—

V ppm/°C

— ppm/V

Notes

Doc ID 15399 Rev 9 89/157

Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7

Table 16.

PMC Electrical Characteristics (continued)

ID Name Parameter Min Typ Max Unit Notes

—

CC C

Variation of LVI for rising core supply at power-on reset

1.120

1.200

CC C

Variation of LVI for rising core supply after power-on reset

Lvi1p2 - 3% Lvi1p2

3c — CC C

Trimming step LVI core supply

3d Lvi1p2_h CC C LVI core supply hysteresis

4 Por1.2V_r CC C POR 1.2 V rising

— 20

—

Por1.2V_f

—

C POR 1.2 V rising variation

C POR 1.2 V falling

C POR 1.2 V falling variation

1.280

Lvi1p2 +

—

— 40 —

— 0.709

—

Por1.2V_r -

35%

Por1.2V_r

Por1.2V_r +

35%

— 0.638

—

Por1.2V_f -

35%

Por1.2V_f

Por1.2V_f +

35%

Vdd

—

CC C

Nominal V

core supply internal regulator target DC output voltage

(1)

CC P

Nominal V

core supply internal regulator target DC output voltage variation after power-on reset

—

CC P

Nominal V

core supply internal regulator target DC output voltage variation at power-on reset

Vdd - 6%

Vdd -

10%

(2)

—

Ivrcctl

CC C Trimming step Vdd

CC C

Voltage regulator controller for core supply maximum

DC output current

Lvi1p2 CC C

Nominal LVI for rising core supply

(3)

—

Vdd33 CC C

Nominal 3.3 V supply internal regulator DC output voltage

—

CC P

Nominal 3.3 V supply internal regulator DC output voltage variation at poweron reset

CC P

Nominal 3.3 V supply internal regulator DC output voltage variation power-on reset

—

Vdd33 -

8.5%

Vdd33 -

7.5%

1.28

Vdd

—

1.160

3.39

Vdd33

—

Vdd + 10%

Vdd + 3%

—

Vdd33 +

Vdd3 + 7% V

V mV mA

V mV mV

See note

With internal load up to Idd3p3

(4)

(5)

90/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics

Table 16.

PMC Electrical Characteristics (continued)

ID Name Parameter Min

— CC D

Voltage regulator 3.3 V output impedance at maximum DC load

Idd3p3 CC P

Voltage regulator 3.3 V maximum DC output current

(internal regulator enabled)

(6)

5e Vdd33 ILim CC C

Voltage regulator 3.3 V DC current limit

—

(7)

—

Typ

—

130

Max

—

Unit

 mA mA

Notes

6 Lvi3p3 CC C

Nominal LVI for rising 3.3 V supply

— 3.090

— V

The Lvi3p3 specs are also valid for the Vddeh

LVI

—

CC C

Variation of LVI for rising

3.3 V supply at power-on reset

Lvi3p3 - 6% Lvi3p3

CC C

Variation of LVI for rising

3.3 V supply after power-on Lvi3p3 - 3% Lvi3p3 reset

6c — CC C Trimming step LVI 3.3 V

6d Lvi3p3_h CC C LVI 3.3 V hysteresis

—

Lvi3p3 +

—

V mV mV

See note

(8)

7 Por3.3V_r CC C

Nominal POR for rising

3.3 V supply

— 2.07

—

7a — CC C

Variation of POR for rising

3.3 V supply

Por3.3V_r-

35%

Por3.3V_r

Por3.3V_r +

35%

7b Por3.3V_f

CC C

Nominal POR for falling

3.3 V supply

7c —

— 1.95

—

CC C

Variation of POR for falling

3.3 V supply

Por3.3V_f -

35%

Por3.3V_f

Por3.3V_f +

35%

Lvi5p0 CC C

Nominal LVI for rising 5 V

DDREG

supply

—

— 4.290

CC C

Variation of LVI for rising 5 V

DDREG

supply at power-on reset

Lvi5p0 - 6% Lvi5p0

— CC C

Variation of LVI for rising 5 V

DDRE

G supply power-on reset

Lvi5p0 - 3% Lvi5p0

8c — CC C Trimming step LVI 5 V

8d Lvi5p0_h CC C LVI 5 V hysteresis

—

Lvi5p0 +

—

V mV mV

The 3.3V

POR specs are also valid for the V

DDEH

POR

Doc ID 15399 Rev 9 91/157

Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7

Table 16.

PMC Electrical Characteristics (continued)

ID Name Parameter Min Typ Max Unit Notes

Por5V_r CC C

Nominal POR for rising 5 V

DDREG

supply

— CC C

Variation of POR for rising

5 V V

DDREG

supply

9b Por5V_f CC C

Nominal POR for falling 5 V

DDREG

supply

9c — CC C

Variation of POR for falling

5 V V

DDREG

supply

—

Por5V_r

- 35%

—

Por5V_f

- 35%

2.67

Por5V_r

2.47

Por5V_f

—

Por5V_r

+ 50%

—

Por5V_f

+ 50%

Using external ballast transistor.

Min range is extended to 10% since Lvi1p2 is reprogrammed from 1.2 V to 1.16 V after power-on reset.

LVI for falling supply is calculated as LVI rising – LVI hysteresis.

Lvi1p2 tracks DC target variation of internal Vdd regulator. Minimum and maximum Lvi1p2 correspond to minimum and maximum Vdd DC target respectively.

Minimum loading (<10 mA) for reading trim values from flash, powering internal RC oscillator, and IO consumption during

POR.

No external load is allowed, except for use as a reference for an external tool.

This value is valid only when the internal regulator is bypassed. When the internal regulator is enabled, the maximum external load allowed on the Nexus pads is 30 pF at 40 MHz.

Lvi3p3 tracks DC target variation of internal Vdd33 regulator. Minimum and maximum Lvi3p3 correspond to minimum and maximum Vdd33 DC target respectively.

In designs where the SPC564A80 microcontroller’s internal regulators are used, a ballast is required for generation of the 1.2 V internal supply. No ballast is required when an external

1.2 V supply is used.

92/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7

The resistor may or may not be required. This depends on the allowable power dissipation of the npn bypass transistor device. The resistor may be used to limit the in-rush current at power on.

Creg

DDREG

Electrical characteristics

The bypass transistor

MUST be operated out of saturation region.

Keep parasitic inductance under 20nH

RCCTL

MCU

Mandatory decoupling capacitor network

Ce Cd

VRCCTL capacitor and resistor is required

Figure 8.

Core voltage regulator controller external components preferred configuration

Table 17.

SPC564A80 External network specification

External Network

Parameter

Min Typ Max Comment

1.1



3*2.35



F+5



Equivalent ESR of Ce capacitors



4*50nF



0.252



Creg

Cc 5



Rc 1.1



2.2



3*4.7



F+10



4*100nF



0.280





2.97



3*6.35



F+13.5



50m



4*135nF



0.308



13.5



5.6



NJD2873 or BCP68 only

X7R,-50%/+35%

X7R, -50%/+35%

+/-10%

It depends on external Vreg.

X7R, -50%/+35%

May or may not be required. It depends on the allowable power dissipation of

T1.

Doc ID 15399 Rev 9 93/157

Electrical characteristics

3.6.2

SPC564A74L7, SPC564A80B4, SPC564A80L7

Recommended power transistors

The following NPN transistors are recommended for use with the on-chip voltage regulator controller: ON Semiconductor

BCP68T1 or NJD2873 as well as Philips Semiconductor

BCP68. The collector of the external transistor is preferably connected to the same voltage supply source as the output stage of the regulator.

Table 18.

Recommended operating characteristics

Symbol h

(



) DC current gain (Beta)

Parameter Value

60 – 550

Absolute minimum power dissipation

>1.0

(1.5 preferred)

CMaxDC

VCE

SAT

Minimum peak collector current

Collector-to-emitter saturation voltage

Base-to-emitter voltage

Adjust resistor at bipolar transistor collector for 3.3 V/5.0 V to avoid VCE < VCE

SAT

1.0

200 – 600

0.4 – 1.0

(1)

Unit

—

A mV

3.7 Power up/down sequencing

There is no power sequencing required among power sources during power up and power down, in order to operate within specification.

Although there are no power up/down sequencing requirements to prevent issues such as latch-up or excessive current spikes the state of the I/O pins during power up/down varies according to

Table 19

for all pins with fast pads, and

Table 20 for all pins with medium, slow,

and multi-voltage pads.

Table 19.

Power sequence pin states (fast pads)

DDE

LOW

DDE

RC33

LOW

RC33

LOW

Pad State

LOW

HIGH

HIGH IMPEDANCE

FUNCTIONAL

Table 20.

Power sequence pin states (medium, slow, and multi-voltage pads)

DDEH

LOW

DDEH

LOW

Pad State

LOW

HIGH IMPEDANCE

FUNCTIONAL

94/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7

3.8 DC electrical specifications

Table 21.

DC electrical specifications

Electrical characteristics

Symbol C Parameter Conditions

DDE-EH

DDE

DDEH

RC33

DDA

INDC

– V

SSA

SR — Core supply voltage

SR — I/O supply voltage

SR —

3.3 V regulated voltage

(1)

SR — Analog supply voltage

SR — Analog input voltage

SR — V

differential voltage

SR —

Analog reference low voltage

—

– V

SSA

SR — VRL differential voltage

SR —

Analog reference high voltage

—

– V

FLASH

(4)

DDF

STBY

SR — V

REF

differential voltage

SR —

Flash operating voltage

(3)

—

SR — Flash read voltage —

SRAM standby voltage

Unregulated mode

SR —

Keep-out Range: 1.2V–

Regulated mode

DDREG

DDPLL

SR —

Voltage regulator supply voltage

SR —

Clock synthesizer operating voltage

—

SSPLL

– V

SR —

SSPLL

to V

SS differential voltage

IL_S

—

Slow/medium I/O pad input low voltage

Hysteresis enabled

Hysteresis disabled min

1.14

1.62

3.0

4.75

(2)

SSA

-0.3

–100

SSA

–100

DDA

-0.1

4.75

1.14

3.0

0.95

2.0

4.75

1.14

–100

-0.3

—

Value typ

DDA

5.25

1.32

3.6

1.2

max

1.32

3.6

5.25

3.6

5.25

DDA

+0.3

100

SSA

+0.1

100

Unit

V mV

— 5.5

—

5.25

1.32

100 mV

0.35*V

DDEH

0.40*V

DDEH

Doc ID 15399 Rev 9 95/157

Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7

Table 21.

DC electrical specifications (continued)

Symbol

IL_F

IL_LS

IL_HS

IH_S

IH_F

IH_LS

IH_HS

OL_S

OL_F

OL_LS

C Parameter

Fast pad I/O input low voltage

Hysteresis enabled

Hysteresis disabled

Multi-voltage I/O pad input low voltage in

Low-swingmode

(5),(6),(7),(8)

Multi-voltage pad I/O input low voltage in high-swing-mode

Hysteresis enabled

Hysteresis disabled

Hysteresis enabled

Hysteresis disabled

Slow/medium pad I/O input high voltage

(9)

Hysteresis enabled

Hysteresis disabled

Fast I/O input high voltage

Multi-voltage pad I/O input high voltage in low-swingmode

(5),(6),(7),(8)

Hysteresis enabled

Hysteresis disabled

Hysteresis enabled

Hysteresis disabled

Multi-voltage I/O input high voltage in highswing-mode

Hysteresis enabled

Hysteresis disabled

CC P

Slow/medium pad I/O output low voltage

(9)

Fast I/O output low voltage

(9)

Multi-voltage pad I/O output low voltage in low-swing mode

(5),(6),(7),(8),(9)

Conditions min

-0.3

0.65 V

DDEH

0.55 V

DDEH

0.65 V

DDE

0.58 V

DDE

2.5

2.2

0.65 V

0.55 V

—

DDEH

Value typ

— max

0.35*V

DDE

Unit

— 0.40*V

DDE

— 0.8

— 1.1

—

0.35 V

DDEH

0.4 V

DDEH

+0.3

DDEH

+0.3

DDE

+0.3

DDE

+0.3

DDEH

+0.3

DDEH

+0.3

DDEH

+0.3

DDEH

+0.3

0.2*V

DDEH

0.2*V

DDE

— — 0.6

96/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics

Table 21.

DC electrical specifications (continued)

Symbol

OL_HS

OH_S

OH_F

OH_LS

OH_HS

HYS_S

HYS_F

HYS_LS

DDPLL

DDSTBY

C Parameter Conditions min

CC P

Multi-voltage pad I/O output low voltage in high-swing mode

(9)

Slow/medium pad I/O output high voltage

(9)

Fast pad I/O output high voltage

(9)

Multi-voltage pad I/O output high voltage in low-swing mode

(5),(6),(7),(8)

OH_LS

0.5 mA

—

0.8 V

DDEH

0.8 V

DDE

2.1

CC P

CC C

Multi-voltage pad I/O output high voltage in high-swing mode

(9)

Slow/medium/multivoltage I/O input hysteresis

CC C Fast I/O input hysteresis

CC C

—

Low-Swing-Mode Multi-

Voltage I/O Input

Hysteresis hysteresis enabled

CC P

at 1.32 V at

80 MHz

Operating current 1.2 V supplies

at 1.32V

at 120 MHz

DD at 1.32V

at 150 MHz

0.8 V

DDEH

0.1 * V

DDEH

0.1 * V

DDE

0.25

—

Operating current 0.95-

1.2 V

STBY

at 55 o

Operating current 2–

5.5 V

STBY

at 55 o

Operating current 0.95-

1.2 V

STBY

27 o

—

DDSTBY27

Operating current 2-

5.5 V

STBY

27 o

Value typ

—

3.1

—

35 max

0.2*V

DDEH

—

3.7

—

380

400

445

100

110

100

Unit

V v mA mA mA



Doc ID 15399 Rev 9 97/157

Electrical characteristics

Table 21.

DC electrical specifications (continued)

SPC564A74L7, SPC564A80B4, SPC564A80L7

Symbol C Parameter Conditions

DDSTBY150

DDSLOW

DDSTOP

DDREG

DD33

DDA

REF

DDH1

DDH4

DDH6

DDH7

DD7

DDH9

DD12

ACT_S

ACT_F

ACT_MV_PU

Operating current 0.95-

1.2 V

STBY

150 o

Operating current 2–

5.5 V

P V

low-power mode

P operating current at

1.32 V

STBY

150 o

Slow mode

(10)

Stop mode

(11)

CC C

Operating current 3.3 V supplies

RC33

(1)

(12)

DDA

Operating current 5.0 V

Analog reference supplies supply current

(transient)

Operating current

DDE

(14)

supplies

DDREG

DDEH1

DDEH4

DDEH6

DDEH7

DDE7

DDEH9

DDE12

Slow/medium I/O weak pull up/down current

(15)

3.0 V – 3.6 V

4.75 V – 5.5 V

D 1.62 V – 1.98 V

Fast I/O weak pull up/down current

(15)

2.25 V – 2.75 V

D 3.0 V – 3.6 V

C Multi-voltage pad weak pullup current

DDE

3.0–3.6 V

(5)

MultiV pad, high swing mode only

P 4.75 V – 5.25 V min

—

Value typ

790

760

—

— max

2000

191

190

30.0

1.0

(13)

See note

(14) mA

200

120

139

158

200

Unit



A mA mA mA



98/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7

Table 21.

DC electrical specifications (continued)

Symbol C Parameter Conditions min

ACT_MV_PD

INACT_D

INACT_A

IN_A

IN_M

PUPD200K

PUPD100K

C Multivoltage pad weak pulldown current

DDE

3.0–3.6 V

(5)

MultiV pad, high swing mode only

CC P

SR T

I/O input leakage current

(16)

DC injection current

(per pin)

Analog input current, channel off, AN[0:7]

(17)

Analog input current, channel off, all other analog pins

(17)

4.75 V – 5.25 V

—

DSC(PCR[8:9])

= 0b00

Load capacitance (fast

I/O)

(18)

DSC(PCR[8:9])

= 0b01

DSC(PCR[8:9])

= 0b10

DSC(PCR[8:9])

= 0b11

CC D

Input capacitance

(digital pins)

CC D

Input capacitance

(analog pins)

CC D

SR P

Input capacitance

(digital and analog pins

(19)

)

Weak Pull-Up/Down

Resistance

(20)

, 200 k



Option

Weak Pull-Up/Down

Resistance

(20)

, 100 k



Option

—

–2.5

–1.0

–250

–150

—

130

Electrical characteristics

Value typ max

Unit

—

280

140



A mA nA pF

200

2.5

1.0

250

150 k

 k

 pF pF pF

Doc ID 15399 Rev 9 99/157

Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7

Table 21.

DC electrical specifications (continued)

Value

Symbol C Parameter Conditions Unit min typ max

PUPD5K

SR C

Weak Pull-Up/Down

Resistance

(20)

5 k



Option

5 V ± 5% supply

1.4

— 7.5



PUPDMTCH

CC C

Pull-up/Down

Resistance matching ratios (100K/200K)

Pull-up and pull-down resistances both enabled and settings are equal.

–2.5

— 2.5

to T

) SR —

Operating temperature range - ambient

(packaged)

— –40.0

125.0



— SR —

Slew rate on power supply pins

— — 25 V/ms

These specifications apply when V

RC33

is supplied externally, after disabling the internal regulator (V

DDREG

= 0).

ADC is functional with 4 V



DDA



4.75 V but with derated accuracy. This means the ADC will continue to function at full speed with no undesirable behavior, but the accuracy will be degraded.

The V

DDF only.

supply is connected to V

in the package substrate. This specification applies to calibration package devices

FLASH

is only available in the calibration package.

Power supply for multi-voltage pads cannot be below 4.5 V when in low-swing mode.

The slew rate (SRC) setting must be 0b11 when in low-swing mode.

While in low-swing mode there are no restrictions in transitioning to high-swing mode.

Pin in low-swing mode can accept a 5 V input.

All V

values 100% tested with ± 2 mA load except where noted.

10. Bypass mode, system clock at 1 MHz (using system clock divider), PLL shut down, CPU running simple executive code,

4 x ADC conversion every 10 ms, 2 x PWM channels 1 kHz, all other modules stopped.

11. Bypass mode, system clock at 1 MHz (using system clock divider), CPU stopped, PIT running, all other modules stopped.

12. This current will be consumed for external regulation and internal regulation, when 3.3V regulator is switched off by shadow flash

13. If 1.2V and 3.3V internal regulators are on,then iddreg=70mA

If supply is external that is 3.3V internal regulator is off, then iddreg=15mA

14. Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a particular I/O segment, and the voltage of the I/O segment. See

Table 22

for values to calculate power dissipation for specific operation. The total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment.

15. Absolute value of current, measured at V

and V

16. Weak pull up/down inactive. Measured at V

DDE

= 3.6 V and V

DDEH

= 5.25 V. Applies to fast, slow, and medium pads.

17. Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8 to 12 o

C, in the ambient temperature range of 50 to 125 o

C. Applies to analog pads.

18. Applies to CLKOUT, external bus pins, and Nexus pins.

19. Applies to the FCK, SDI, SDO, and SDS pins.

20. This programmable option applies only to eQADC differential input channels and is used for biasing and sensor diagnostics.

100/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics

3.9 I/O pad current specifications

The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption is the sum of all output pin currents for a particular

segment. The output pin current can be calculated from Table 22

based on the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in

Table 22

Table 22.

I/O pad average I

DDE

specifications

(1)

Pad Type Symbol C

Period

(ns)

Load

(2)

(pF)

DDE

(V)

Drive/Slew

Rate Select

DDE

Avg

(mA)

(3)

DDE

RMS

(mA)

Slow

Medium

Fast

DRV_SSR_HV

DRV_MSR_HV

DRV_FC

CC D

MultiV

(High

Swing

Mode)

DRV_MULTV_HV

CC D

117

CC D 212

MultiV

(Low

Swing

Mode)

DRV_MULTV_HV

CC D 30

Numbers from simulations at best case process, 150 °C.

All loads are lumped.

Average current is for pad configured as output only.

200

425

130

650

840

317

200

5.5

3.6

1.98

5.5

1.98

5.5

22.7

12.1

8.3

4.44

12.5

2.5

0.5

1.5

5.3

1.1

7.3

5.42

2.84

6.1

2.3

5.8

3.4

—

68.3

41.1

27.7

14.3

—

18.6

12.6

6.4

—

Doc ID 15399 Rev 9 101/157

Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7

3.9.1 I/O pad V

RC33

current specifications

The power consumption of the V

RC33

supply is dependent on the usage of the pins on all I/O segments. The power consumption is the sum of all input and output pin V

RC33

currents for all I/O segments. The output pin V

RC33

current can be calculated from

Table 23 based on

the voltage, frequency, and load on all fast pad pins. The input pin V

RC33

current can be

calculated from Table 23 based on the voltage, frequency, and load on all medium-speed

pads. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in

Table 23 .

Table 23.

I/O pad V

RC33

average I

DDE

specifications

(1)

Pad Type Symbol C

Period

(ns)

Load

(2)

(pF)

Drive Select

DD33

Avg

(µA)

Slow

Medium I

DRV_SSR_HV

DRV_MSR_HV

CC D

100

200

800

100

500

200

MultiV

(3)

(High

Swing Mode)

DRV_MULTV_HV

CC D

500

117

200

0.01

33.4

CC D 212 200 00 33.4

MultiV

(4)

(Low

Swing Mode)

DRV_MULTV_HV

CC D 30 30 11 33.4

These are typical values that are estimated from simulation and not tested. Currents apply to output pins only.

All loads are lumped.

Average current is for pad configured as output only.

In low swing mode, multi-voltage pads must operate in highest slew rate setting.

0.8

0.04

0.06

0.009

2.75

0.11

0.02

DD33

RMS

(µA)

34.9

235.7

87.4

47.4

258

76.5

56.2

35.4

34.8

33.8

33.7

102/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics

Table 24.

RC33

pad average DC current

(1)

Pad

Type

Symbol C

Period

(ns)

Load

(2)

(pF)

RC33

(V)

DDE

(V)

Drive

Select

DD33

Avg

(µA)

Fast I

DRV_FC

CC D

3.6

1.98

2.35

1.75

1.41

1.06

1.75

CC D

3.6

1.98

1.32

1.14

0.95

These are typical values that are estimated from simulation and not tested. Currents apply to output pins only.

All loads are lumped.

DD33

RMS

(µA)

6.12

4.3

3.43

2.9

4.56

3.44

2.95

2.62

3.9.2 LVDS pad specifications

LVDS pads are implemented to support the MSC (Microsecond Channel) protocol which is an enhanced feature of the DSPI module. The LVDS pads are compliant with LVDS specifications and support data rates up to 50 MHz.

Table 25.

DSPI LVDS pad specification

# Characteristic Symbol C Condition

Min.

Value

Typ.

Value

Max.

Value

Unit

4 Data Frequency

5 Differential output voltage f

LVDSCLK

Data Rate

CC D —

Driver Specs

CC P

SRC=0b00 or 0b11

CC P SRC=0b01

CC P SRC=0b10

150

160

400

320

480

MHz mV

Common mode voltage

(LVDS), VOS

7 Rise/Fall time

Propagation delay (Low to

High)

Propagation delay (High to

Low)

PLH

PHL

CC P

CC D

—

1.06

1.2

1.39

V ns ns ns

Doc ID 15399 Rev 9 103/157

Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7

Table 25.

DSPI LVDS pad specification (continued)

# Characteristic

10 Delay (H/L), sync Mode

Delay, Z to Normal

(High/Low)

Diff Skew Itphla-tplhbI or

Itplhb-tphlaI

13 Trans. Line (differential Zo)

14 Temperature

Symbol C Condition t

PDSYNC

CC D

CC D —

SKEW

CC D —

Termination

CC D

—

Min.

Value

Typ.

Value

500

Max.

Value

Unit ns ns

–40

100

0.5

105

150 ns





Table 26.

PLLMRFM electrical specifications

DDPLL

= 1.08 V to 3.6 V, V

= V

SSPLL

= 0 V, T

= T

to T

)

Symbol C Parameter Conditions min

Value max f ref_crystal f ref_ext f t f f f pll_in vco sys sys

CYC f

LORL f

LORH f

SCM

PLL reference frequency range

(1)

Crystal reference

External reference

CC P

Phase detector input frequency range

(after pre-divider)

CC P VCO frequency range

CC C

On-chip PLL frequency

(2)

System frequency in bypass mode

System clock period

Loss of reference frequency window

(3)

CC P Self-clocked mode frequency

(4),(5)

(2)

—

Crystal reference

External reference

—

Lower limit

Upper limit

—

256

—

1.6

1.2

512

150

1 / f sys

3.7

72.25

Unit

MHz

MHz ns

MHz

104/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics

Table 26.

PLLMRFM electrical specifications

DDPLL

= 1.08 V to 3.6 V, V

= V

SSPLL

= 0 V, T

= T

to T

) (continued)

Value

Symbol C Parameter Conditions Unit min max

JITTER t cst

IHEXT

Peak-to-peak (clock edge to clock edge)

CLKOUT period jitter

(6),(7),(8),(9)

Long-term jitter

(avg. over 2 ms interval)

CC T Crystal start-up time

(10), (11)

EXTAL input high voltage f

SYS

maximum

Crystal

Mode

(12)

External

Reference

(12),

(13)

—

–5

–6

—

Vxtal

+ 0.4

RC33

/2 +

0.4

—

RC33

% f

CLKOUT ns ms

ILEXT

EXTAL input low voltage

Crystal

Mode

(13)

(12)

External

Reference

(12),

—

Vxtal -

0.4

RC33

/2 -

0.4

4 MHz

8 MHz

12 MHz

— CC T XTAL load capacitance

(10) pF

16 MHz

20 MHz

40 MHz 5 8 f f t lpll t dc

LCK

PLL lock time

(10), (14)

CC T Duty cycle of reference

Frequency LOCK range

Frequency un-LOCK range

—

–6

–18

200

 s

% f sys

% f sys f f

CC Modulation Depth

CC D Modulation frequency

(15)

Center spread

Down Spread

±0.25

–0.5

±4.0

–8.0

% f sys f

MOD

— — 100 kHz

Considering operation with PLL not bypassed.

All internal registers retain data at 0 Hz.

“Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked mode.

Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the f

LOR window.

Doc ID 15399 Rev 9 105/157

Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7

VCO

self clock range is 20–150 MHz. f

SCM

represents f

SYS

after PLL output divider (ERFD) of 2 through 16 in enhanced mode.

This value is determined by the crystal manufacturer and board design.

Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f

SYS

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via V

DDPLL percentage for a given interval.

and V

SSPLL

and variation in crystal oscillator frequency increase the C

JITTER

Proper PC board layout procedures must be followed to achieve specifications.

Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C

JITTER f

or f

(depending on whether center spread or down spread modulation is enabled).

and either

10. This value is determined by the crystal manufacturer and board design. For 4 MHz to 40 MHz crystals specified for this

PLL, load capacitors should not exceed these limits.

11. Proper PC board layout procedures must be followed to achieve specifications.

12. This parameter is guaranteed by design rather than 100% tested.

13. V

IHEXT

cannot exceed V

RC33

in external reference mode.

14. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR).

15. Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.

3.11 Temperature sensor electrical characteristics

Table 27.

Temperature sensor electrical characteristics

Symbol C Parameter Conditions min

Value typical

—

CC C

Temperature monitoring range

CC C Sensitivity

CC P Accuracy T

= –40 to 150 °C

–40

—

–10

—

6.3

—

Unit max

150

—

°C mV/°C

°C

3.12 eQADC electrical characteristics

Table 28.

eQADC conversion specifications (operating)

Value

Unit

Symbol C Parameter min max f

ADCLK

SR f

ADCLK

—

ADC clock (ADCLK) frequency

Conversion cycles

Stop mode recovery time

(1)

ADC clock (ADCLK) frequency

2+13

—

128+14

MHz

ADCLK cycles

 s mV

Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time that the ADC is ready to perform conversions.Delay from power up to full accuracy = 8 ms.

106/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics

Table 29.

eQADC single ended conversion specifications (operating)

Value

Symbol C Parameter Unit min max

OFFNC

OFFWC

GAINNC

GAINWC CC

INJ

TUE8

TUE16

Offset error without calibration

Offset error with calibration

Full scale gain error without calibration

Full scale gain error with calibration

Disruptive input injection current

(1), (2), (3), (4)

Incremental error due to injection current

(5),(6)

Total unadjusted error (TUE) at 8 MHz

Total unadjusted error at 16 MHz

–4

–160

–4

–3

–4

–8

160

(6)

Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs greater then V

and 0x0 for values less then V

. Other channels are not affected by non-disruptive conditions.

Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do not affect device reliability or cause permanent damage.

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values using V calculated values.

POSCLAMP

= V

DDA

+ 0.5 V and V

NEGCLAMP

= – 0.3 V, then use the larger of the

Condition applies to two adjacent pins at injection limits.

Performance expected with production silicon.

All channels have same 10 k



< Rs < 100 k



; Channel under test has Rs=10 k



; I

INJ

INJMAX

INJMIN

Counts

Counts mA

Counts

Table 30.

eQADC differential ended conversion specifications (operating)

Value

Symbol C Parameter min

GAINVGA1

(1)

–

Variable gain amplifier accuracy (gain=1)

(2)

8 MHz

ADC

–4

INL

16 MHz

ADC

–8

DNL

8 MHz

ADC

16 MHz

ADC

–3

(4)

(4) max

(4)

Unit

Counts

(3)

Counts

Doc ID 15399 Rev 9 107/157

Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7

Table 30.

eQADC differential ended conversion specifications (operating) (continued)

Value

Symbol

–

Parameter min

Variable gain amplifier accuracy (gain=2)

(2) max

GAINVGA2

(1)

GAINVGA4

(1)

DIFF max

DIFF max2

DIFF max4

DIFF cmv

–

Unit

INL

8 MHz

ADC

16 MHz

ADC

–5

–8

8 MHz

ADC

–3

DNL

16 MHz

ADC

–3

Variable gain amplifier accuracy (gain=4)

(2)

INL

8 MHz

ADC

16 MHz

ADC

–7

–8

Counts

DNL

8 MHz

ADC

16 MHz

ADC

–4

PREGAIN set to 1X setting

Maximum differential voltage

(DANx+ - DANx-) or (DANx- -

DANx+)

(5)

PREGAIN set to 2X setting

PREGAIN set to 4X setting

Differential input

Common mode voltage (DANx- +

DANx+)/2

(5)

—

(VRH - VRL)/2

(VRH - VRL)/4

(VRH - VRL)/8

+ V

)/2 - (V

+ V

)/2 +

Counts

Applies only to differential channels.

Variable gain is controlled by setting the PRE_GAIN bits in the ADC_ACR1-8 registers to select a gain factor of



2, or



4. Settings are for differential input only. Tested at



1 gain. Values for other settings are guaranteed by as indicated.

At V

– V

= 5.12 V, one LSB = 1.25 mV.

Guaranteed 10-bit mono tonicity.

Voltages between VRL and VRH will not cause damage to the pins. However, they may not be converted accurately if the differential voltage is above the maximum differential voltage. In addition, conversion errors may occur if the common mode voltage of the differential signal violates the Differential Input common mode voltage specification.

108/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics

3.13 Configuring SRAM wait states

Use the SWSC field in the ECSM_MUDCR register to specify an additional wait state for the device SRAM. By default, no wait state is added.

Table 31.

Cutoff frequency for additional SRAM wait state

(1)

SWSC Value

153

Max frequencies including 2% PLL FM.

Please see the device reference manual for details.

3.14 Platform flash controller electrical characteristics

Table 32.

APC, RWSC, WWSC settings vs. frequency of operation

(1),(2)

Max. Flash Operating

Frequency (MHz)

(3)

APC

(4)

RWSC

(4)

WWSC

20 MHz

61 MHz

90 MHz

123 MHz

0b000

0b001

0b010

0b011

0b000

0b001

0b010

0b011

0b11

153 MHz 0b100 0b100 0b11

APC, RWSC and WWSC are fields in the flash memory BIUCR register used to specify wait states for address pipelining and read/write accesses. Illegal combinations exist—all entries must be taken from the same row.

TBD: To Be Defined.

Max frequencies including 2% PLL FM.

APC must be equal to RWSC.

3.15 Flash memory electrical characteristics

Table 33.

Flash program and erase specifications

(1)

# Symbol C Parameter

Min.

Value

Typical

Value

Initial

Max

(2)

Max

(3)

Unit

T dwprogram pprogram

16kpperase

Double Word (64 bits) Program Time

Page Program Time

16 KB Block Pre-program and Erase

Time

—

300

—

160

(4)

500

 s

1000 5000 ms

Doc ID 15399 Rev 9 109/157

Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7

Table 33.

Flash program and erase specifications

(1)

(continued)

# Symbol C Parameter

Min.

Value

Typical

Value

Initial

Max

(2)

Max

(3)

Unit

64kpperase

128kpperase

64 KB Block Pre-program and Erase

Time

128 KB Block Pre-program and Erase

Time

—

800

1500

1800

3000

5000

7500 ms ms

7 T

256kpperase

256 KB Block Pre-program and Erase

Time

— 3000 5300 15000 ms

8 T psrt

SR — Program suspend request rate

(5)

100 — — —

 s

9 T esrt

SR — Erase suspend request rate

(6)

Typical program and erase times assume nominal supply values and operation at 25 pending device characterization.

C. All times are subject to change

Initial factory condition: < 100 program/erase cycles, 25 o

C, typical supply voltage, 80 MHz minimum system frequency.

The maximum erase time occurs after the specified number of program/erase cycles. This maximum value is characterized but not guaranteed.

Page size is 128 bits (4 words).

Time between program suspend resume and the next program suspend request.

Time between erase suspend resume and the next erase suspend request.

Table 34.

Flash module life

Value

Symbol C Parameter Conditions min typ

P/E

Number of program/erase cycles per block for 16 KB,

48 KB, and 64 Kbyte blocks over the operating temperature range (T

)

Number of program/erase cycles per block for

128 Kbyte and 256 Kbyte blocks over the operating temperature range (T

)

—

100,000

1,000

—

100,000

Data

Retention

CC C

Minimum data retention at



C average ambient temperature

(1)

Blocks with 0 – 1,000

P/E cycles

Blocks with 1,001 –

10,000 P/E cycles

—

Blocks with 10,001 –

100,000 P/E cycles

5 —

Ambient temperature averaged over duration of application, not to exceed product operating temperature range.

Unit

P/E cycles

P/E cycles years years years

110/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics

Table 35.

Pad AC specifications (5.0 V)

(1)

Name C

Output Delay

(ns)

(2),(3)

Low-to-High / Highto-Low

Rise/Fall Edge (ns)

(3),(4)

Drive Load

(pF)

SRC/DSC

Medium

Slow

(5),(6),(7)

(7),(10)

MultiV

(11)

(High Swing Mode)

Min Max Min

CC D

4.6/3.7

12/13

69/71

12/12

28/34

152/165

2.2/2.2

N/A

5.6/6

34/35

CC D 7.3/5.7

19/18 4.4/4.3

N/A

13/13 CC D 26/27 61/69

CC D 137/142 320/330

CC D 4.1/3.6

10.3/8.9

72/74

3.28/2.98

N/A

CC D 8.38/6.11

16/12.9

5.48/4.81

CC D 61.7/10.4

92.2/24.3

42.0/12.2

Max

7/7

15/15

74/74

14/14

34/34

164/164

8/8

11/11

63/63

MultiV

(Low Swing Mode)

Fast

(12) pad_i_hv

(13) pull_hv

CC D

2.31/2.34

0.5/0.5

7.62/6.33

1.9/1.9

6000

1.26/1.67

N/A

0.3/0.3

6.5/4.4

±1.5/1.5

5000/5000

0.5

(8)

N/A

These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at

= 1.14 V to 1.32 V, V

DDEH

= 4.5 V to 5.5 V, T

= T

to T

This parameter is supplied for reference and is not guaranteed by design and not tested.

Delay and rise/fall are measured to 20% or 80% of the respective signal.

This parameter is guaranteed by characterization before qualification rather than 100% tested.

In high swing mode, high/low swing pad Vol and Voh values are the same as those of the slew controlled output pads

Medium Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown.

Output delay is shown in Figure 9: Pad output delay . Add a maximum of one system clock to the output delay for delay with

respect to system clock.

Can be used on the tester.

This drive select value is not supported. If selected, it will be approximately equal to 11.

10. Slow Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown.

11. Selectable high/low swing IO pad with selectable slew in high swing mode only.

12. Fast pads are 3.3 V pads.

13. Stand alone input buffer. Also has weak pull-up/pull-down.

MSB,LSB

(8)

(9)

(8)

(9)

(8)

(9)

Doc ID 15399 Rev 9 111/157

Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7

Table 36.

Pad AC specifications (V

DDE

= 3.3 V)

(1)

Pad Type C

Output Delay

(ns)

(2),(3)

Low-to-High / Highto-Low

Rise/Fall Edge (ns)

(3),(4)

Drive Load

(pF)

SRC/DSC

Min Max Min Max MSB,LSB

Medium

(5),(6),(7)

CC D

CC D 113/109 270/285

CC D 9.2/6.9

CC D

5.8/4.4

16/13

14/16

27/27

83/86

30/23

18/17

46/49

37/45

69/82

200/210

27/28

81/87

2.7/2.1

11.2/8.6

N/A

6.5/6.7

15/13

38/38

53/46

5.5/4.1

21/16

N/A

15.4/15.4

32/26

80/82

106/95

10/10

34/34

19/19

43/43

86/86

120/120

20/20

63/63

200

(8)

(9)

Slow

(7),(10)

CC D

31/31

58/52

80/90

144/155

CC D 162/168 415/415

CC D 216/205 533/540

CC D 3.7/3.1

CC D 46/49

42/42

82/85

190/190

250/250

10/10

37/37

200

(8)

N/A 10

(9)

MultiV

(7),(11)

(High Swing Mode)

CC D

210

295

15/15

46/46

100/100

134/134

200

MultiV

(Low Swing Mode)

Not a valid operational mode

Fast pad_i_hv

(12) pull_hv

CC D

0.5/0.5

2.5/2.5

3/3

6000

0.4/0.4

1.2/1.2

±1.5/1.5

5000/5000

0.5

(8)

N/A

These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at

= 1.14 V to 1.32 V, V

DDE

= 3 V to 3.6 V, V

DDEH

= 3 V to 3.6 V, T

= T

to T

This parameter is supplied for reference and is not guaranteed by design and not tested.

Delay and rise/fall are measured to 20% or 80% of the respective signal.

112/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics

This parameter is guaranteed by characterization before qualification rather than 100% tested.

In high swing mode, high/low swing pad Vol and Voh values are the same as those of the slew controlled output pads

Medium Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown.

Output delay is shown in

Figure 9 . Add a maximum of one system clock to the output delay for delay with respect to system

clock.

Can be used on the tester.

This drive select value is not supported. If selected, it will be approximately equal to 11.

10. Slow Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown.

11. Selectable high/low swing IO pad with selectable slew in high swing mode only.

12. Stand alone input buffer. Also has weak pull-up/pull-down.

VDDE/2

Pad

Data Input

Rising

Edge

Output

Delay

Pad

Output

Figure 9.

Pad output delay

Falling

Edge

Output

Delay

Doc ID 15399 Rev 9 113/157

Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7

3.17.1 Reset and configuration pin timing

Table 37.

Reset and Configuration Pin Timing

(1)

# Characteristic Symbol

RESET Pulse Width

(2)

RESET Glitch Detect Pulse Width

PLLREF, BOOTCFG, WKPCFG Setup Time to RSTOUT Valid t

RPW t

GPW t

RCSU

4 PLLREF, BOOTCFG, WKPCFG Hold Time to RSTOUT Valid t

RCH

Reset timing specified at: V

DDEH

= 3.0 V to 5.25 V, V

= 1.14 V to 1.32 V, T

= T

to T

RESET pulse width is measured from 50% of the falling edge to 50% of the rising edge.

Min

Max

—

Unit t cyc t cyc t cyc t cyc

RESET 1

RSTOUT

BOOTCFG

WKPCFG

Figure 10.

Reset and Configuration Pin Timing

114/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics

3.17.2 IEEE 1149.1 interface timing

Table 38.

JTAG pin AC electrical characteristics

(1)

# Symbol C Characteristic

Min.

Value

Max.

Value

Unit

13 t t t

JCYC

JDC

TCKRISE t

TMSS, t

TDIS t

TMSH, t

TDIH t

TDOV t

TDOI t

TDOHZ t

JCMPPW t t t

JCMPS t

BSDV

BSDVZ

BSDHZ

CC D TCK Cycle Time

CC D TCK Clock Pulse Width

CC D

TCK Rise and Fall Times (40% -

70%)

CC D TMS, TDI Data Setup Time

CC D TMS, TDI Data Hold Time

TCK Low to TDO Data Valid

TCK Low to TDO Data Invalid

TCK Low to TDO High Impedance

CC D JCOMP Assertion Time

CC D JCOMP Setup Time to TCK Low

CC D TCK Falling Edge to Output Valid

TCK Falling Edge to Output Valid out of High Impedance

TCK Falling Edge to Output High

Impedance

100

—

100

—

(2)

—

50 ns ns ns ns ns ns ns ns ns ns ns ns ns

15 t t

BSDST

BSDHT

Boundary Scan Input Valid to TCK

Rising Edge

TCK Rising Edge to Boundary Scan

Input Invalid

(3)

—

— ns ns

JTAG timing specified at V

Swing mode, T

= T

= 1.14 V to 1.32 V, V

DDEH

to T

and C

= 4.5 V to 5.5 V with multi-voltage pads programmed to Low-

= 30 pF with DSC = 0b10, SRC = 0b11. These specifications apply to JTAG boundary scan only. See

Table 39

for functional specifications.

Pad delay is 8–10 ns. Remainder includes TCK pad delay, clock tree delay logic delay and TDO output pad delay.

For 20 MHz TCK.

Note: The Nexus/JTAG Read/Write Access Control/Status Register (RWCS) write (to begin a read access) or the write to the Read/Write Access Data Register (RWD) (to begin a write access) does not actually begin its action until 1 JTAG clock (TCK) after leaving the JTAG

Update-DR state. This prevents the access from being performed and therefore will not signal its completion via the READY (RDY) output unless the JTAG controller receives an additional TCK. In addition, EVTI is not latched into the device unless there are clock transitions on TCK.

The tool/debugger must provide at least one TCK clock for the EVTI signal to be recognized by the MCU. When using the RDY signal to indicate the end of a Nexus read/write access, ensure that TCK continues to run for at least 1 TCK after leaving the Update-DR state. This can be just a TCK with TMS low while in the Run-Test/Idle state or by continuing with the

Doc ID 15399 Rev 9 115/157

Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7 next Nexus/JTAG command. Expect the affect of EVTI and RDY to be delayed by edges of

TCK. Note: RDY is not available in all packages of all devices.

TCK

Figure 11.

JTAG test clock input timing

TCK

TMS, TDI

TDO

116/157

Figure 12.

JTAG test access port timing

Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7

TCK

JCOMP

Figure 13.

JTAG JCOMP timing

Electrical characteristics

Doc ID 15399 Rev 9 117/157

Electrical characteristics

TCK

SPC564A74L7, SPC564A80B4, SPC564A80L7

Output

Signals

Output

Signals

Input

Signals

Figure 14.

JTAG boundary scan timing

Table 39.

Nexus debug port timing

(1)

# Symbol C Characteristic

3 t

MCYC t

MDC t

MDOV

6 t

MSEOV t

EVTOV

7 t

EVTIPW

8 t

EVTOPW

CC D MCKO Cycle Time

CC D Absolute Minimum MCKO Cycle Time

CC D MCKO Duty Cycle

CC D MCKO Low to MDO Data Valid

(5)

CC D MCKO Low to MSEO Data Valid

(5)

CC D MCKO Low to EVTO Data Valid

(5)

CC D EVTI Pulse Width

CC D EVTO Pulse Width

Min. Value Max. Value

(2),(3)

(4)

—

- 0.1

0.35

- 0.1

4.0

0.35

—

Unit t

CYC ns

% t

MCYC t

TCYC t

MCYC

118/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics

Table 39.

Nexus debug port timing

(1)

(continued)

# Symbol C Characteristic

16 t

TCYC t

TDC t

NTDIS t

NTDIH t

NTMSS t

NTMSH

—

TCK Cycle Time

Absolute Minimum TCK Cycle Time

TCK Duty Cycle

TDI Data Setup Time

TDI Data Hold Time

CC D TMS Data Setup Time

CC D TMS Data Hold Time

TDO propagation delay from falling edge of TCK

TDO hold time with respect to TCK falling edge (minimum TDO propagation delay)

Min. Value Max. Value

(6),(7)

100

(8)

—

5.25

—

19.5

— t

Unit

CYC ns

% ns ns ns ns ns ns

All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified at V

= T

L to T

= 1.14 V to 1.32 V, V

DDEH

, and C

= 4.5 V to 5.5 V with multi-voltage pads programmed to Low-Swing mode,

= 30 pF with DSC = 0b10.

Achieving the absolute minimum MCKO cycle time may require setting the MCKO divider to more than its minimum setting

(NPC_PCR[MCKO_DIV] depending on the actual system frequency being used.

This is a functionally allowable feature. However, this may be limited by the maximum frequency specified by the Absolute minimum MCKO period specification.

This may require setting the MCO divider to more than its minimum setting (NPC_PCR[MCKO_DIV]) depending on the actual system frequency being used.

MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.

Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system frequency being used.

This is a functionally allowable feature. However, this may be limited by the maximum frequency specified by the Absolute minimum TCK period specification.

This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system frequency being used.

MCKO

MDO

MSEO

EVTO

Output Data Valid

Figure 15.

Nexus output timing

Doc ID 15399 Rev 9 119/157

Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7

TCK

EVTI

EVTO

9 7

Figure 16.

Nexus event trigger and test clock timings

TCK

TMS, TDI

TDO

Figure 17.

Nexus TDI, TMS, TDO timing

120/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics

Table 40.

Nexus debug port operating frequency

Package Nexus Width Nexus Routing

MDO[0:3]

Nexus Pin Usage

MDO[4:11] CAL_MDO[4:11]

Max. Operating

Frequency

LQFP176

BGA208

BGA324

CSP496

Reduced port mode

(1)

Route to MDO

(2)

Nexus Data Out

[0:3]

Full port mode

(4)

Route to MDO

(2)

Nexus Data Out

[0:3]

GPIO

Nexus Data Out

[4:11]

GPIO

Reduced port mode

(1)

Route to MDO

(2)

Nexus Data Out

[0:3]

Full port mode

(4)

Route to

CAL_MDO

(7)

Cal Nexus Data

Out [0:3]

GPIO

Route to MDO

(2)

Nexus Data Out

[0:3]

Nexus Data Out

[4:11]

GPIO

Cal Nexus Data

Out [4:11]

40 MHz

(5),(6)

40 MHz

(5),(6)

40 MHz

(3)

NPC_PCR[FPM] = 0

NPC_PCR[NEXCFG] = 0

The Nexus AUX port runs up to 40 MHz. Set NPC_PCR[MCKO_DIV] to divide-by-two if the system frequency is greater than 40 MHz.

NPC_PCR[FPM] = 1

Set the NPC_PCR[MCKO_DIV] to divide by two if the system frequency is between 40 MHz and 80 MHz inclusive. Set the

NPC_PCR[MCKO_DIV] to divide by four if the system frequency is greater than 80 MHz.

Pad restrictions limit the Maximum Operation Frequency in these configurations

NPC_PCR[NEXCFG] = 1

Doc ID 15399 Rev 9 121/157

Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7

3.17.4 External Bus Interface (EBI) and calibration bus interface timing

Table 41.

External Bus Interface maximum operating frequency

Port

Width

Multiplexed

Mode

ADDR[12:15]

Pin Usage

ADDR[16:31]

Pin Usage

DATA[0:15]

Pin Usage

16-bit Yes ADDR[12:15] GPIO

ADDR[16:31]

DATA[0:15]

DATA[0:15] 16-bit

32-bit

Yes

ADDR[12:15]

ADDR[16:31]

DATA[16:31]

DATA[0:15]

Set SIU_ECCR[EBDF] to divide by two or divide by four if the system frequency is greater than 66 MHz.

System Frequency must be



132 MHz and SIU_ECCR[EBDF] set to divide by four.

Pad restrictions limit the maximum operating frequency.

Max. Operating

Frequency

66 MHz

(1)

33 MHz

(2),(3)

33 MHz

(2),(3)

Table 42.

Calibration bus interface maximum operating frequency

Port

Width

Multiplexed

Mode

CAL_ADDR[12:15]

Pin Usage

CAL_ADDR[16:30]

Pin Usage

CAL_DATA[0:15]

Pin Usage

16-bit

32-bit

Yes

GPIO GPIO

CAL_ADDR[12:15] CAL_ADDR[16:30]

CAL_WE[2:3]

CAL_DATA[31]

CAL_ADDR[16:30]

CAL_DATA[16:30]

CAL_ADDR[12:30]

CAL_DATA[0:15]

CAL_ADDR[0:15]

CAL_DATA[0:15]

Set SIU_ECCR[EBDF] to divide by two or divide by four if the system frequency is greater than 66 MHz

Max. Operating

Frequency

66 MHz

(1)

66 MHz

(1)

66 MHz

(1)

Table 43.

External bus interface (EBI) and calibration bus operation timing

(1)

# Symbol C Characteristic

66 MHz (ext. bus)

(2)

Unit

Min Max

1 T

CC P CLKOUT Period 15.2

— ns

Notes

Signals are measured at 50%

DDE

2 t

CDC

3 t

CRT

4 t

CFT

CC D CLKOUT duty cycle

CC D CLKOUT rise time

CC D CLKOUT fall time

CLKOUT Posedge to Output Signal

Invalid or High Z(Hold Time)

45%

—

55%

(3)

C ns ns

5 t

COH

CC D

– ADDR[8:31]

– CS[0:3]

– DATA[0:31]

– OE

– RD_WR

– TS

– WE[0:3]/BE[0:3]

1.3

— ns

122/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics

Table 43.

External bus interface (EBI) and calibration bus operation timing

(1)

(continued)

# Symbol C Characteristic

66 MHz (ext. bus)

(2)

Min Max

Unit Notes

CLKOUT Posedge to Output Signal Valid

(Output Delay)

6 t

COV

CC D

ADDR[8:31]

CS[0:3]

DATA[0:31]

RD_WR

WE[0:3]/BE[0:3]

Input Signal Valid to CLKOUT Posedge

(Setup Time)

— 9 ns

7 t

CIS

6.0

— ns

CC D

DATA[0:31]

CLKOUT Posedge to Input Signal Invalid

(Hold Time)

8 t

CIH

1.0

— ns

9 t

APW

10 t

AAI

DATA[0:31]

CC D ALE Pulse Width

CC D

(4)

ALE Negated to Address Invalid

6.5

1.5

(5)

—

— ns ns

External Bus and Calibration bus timing specified at f

SYS

DDE

= 3 V to 3.6 V (unless stated otherwise), T

= T

= 150 MHz and 100 MHz, V

DD to T

, and C

= 1.14 V to 1.32 V,

= 30 pF with DSC = 0b10.

The external bus is limited to half the speed of the internal bus. The maximum external bus frequency is 66 MHz for 16-bit muxed mode and 33 MHz for non-muxed mode. For The EBI division factor should be set accordingly based on the internal frequency being used.

Refer to Fast Pad timing in Table 35

and Table 36

(different values for 1.8 V vs. 3.3 V).

Measured at 50% of ALE.

When CAL_TS pad is used for CAL_ALE function the hold time is 1 ns instead of 1.5 ns.

Voh_f

VDDE/2

Vol_f

CLKOUT

Figure 18.

CLKOUT timing

Doc ID 15399 Rev 9 123/157

Electrical characteristics

CLKOUT

OUTPUT

BUS

VDDE/2

OUTPUT

SIGNAL

VDDE/2

OUTPUT

SIGNAL

Figure 19.

Synchronous output timing

SPC564A74L7, SPC564A80B4, SPC564A80L7

VDDE/2

124/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7

CLKOUT

VDDE/2

INPUT

BUS

VDDE/2

INPUT

SIGNAL

VDDE/2

System Clock

CLKOUT

ALE

Figure 20.

Synchronous input timing

A/D

ADDR

9 10

DATA

Figure 21.

ALE signal timing

Doc ID 15399 Rev 9

Electrical characteristics

125/157

Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7

Table 44.

External interrupt timing

(1)

# Characteristic Symbol Min Max Unit

IRQ Pulse Width Low

IRQ Pulse Width High

3 IRQ Edge to Edge Time

(2) t

IPWL t

IPWH t

ICYC

—

— t cyc t cyc t cyc

IRQ timing specified at V

= 1.14 V to 1.32 V, V

DDEH

= 3.0 V to 5.5 V, V

DD33

and V

DDSYN

= 3.0 V to 3.6 V, T

= T

to T

Applies when IRQ pins are configured for rising edge or falling edge events, but not both.

IRQ

Figure 22.

External Interrupt Timing

Table 45.

eTPU timing

(1)

# Characteristic Symbol Min Max Unit

2 eTPU Input Channel Pulse Width eTPU Output Channel Pulse Width t

ICPW t

OCPW

(2)

—

— t t cyc cyc

eTPU timing specified at V

, and C

= 1.08 V to 1.32 V, V

= 200 pF with SRC = 0b00.

DDEH

= 3.0 V to 5.5 V, V

DD33 and V

DDSYN

= 3.0 V to 3.6 V, T

= T

This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).

126/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics

Table 46.

eMIOS timing

(1)

# Symbol C Characteristic

Min.

Value

Max.

Value

Unit

2 t

MIPW t

MOPW

D eMIOS Input Pulse Width eMIOS Output Pulse Width

—

— t t

CYC

eMIOS timing specified at f

SYS with SRC = 0b00.

= 80 MHz, V

= 1.14 V to 1.32 V, V

DDEH

= 4.5 V to 5.5 V, T

= T

to T

, and C

= 50 pF

DSPI channel frequency support for the SPC564A80 MCU is shown in Table 47 . Timing specifications are in Table 48 .

Table 47.

DSPI channel frequency support

System

Clock (MHz)

DSPI Use

Mode

Max. Usable

Frequency

(MHz)

150

LVDS

Non-LVDS

37.5

18.75

120

LVDS

Non-LVDS

LVDS

Non-LVDS

Notes

Use sysclock /4 divide ratio.

Use sysclock /8 divide ratio.

Use sysclock /3 divide ratio. Gives 33/66 duty cycle. Use DSPI configuration DBR=0b1 (double baud rate), BR=0b0000

(scaler value 2) and PBR=0b01 (prescaler value 3).

Use sysclock /6 divide ratio.

Use sysclock /2 divide ratio.

Use sysclock /4 divide ratio.

Table 48.

DSPI timing

(1),(2)

7 t

8 t t

SCK t

CSC t

ASC t

SDC

Symbol C Characteristic

CC D SCK Cycle Time

(3),(4),(5)

CC D PCS to SCK Delay

(6)

CC D After SCK Delay

(8)

CC D SCK Duty Cycle t

CC D

Slave Access Time

(SS active to SOUT driven) t

DIS

PCSC

PASC

CC D

Slave SOUT Disable Time

(SS inactive to SOUT High-Z or invalid)

CC D PCSx to PCSS time

CC D PCSS to PCSx time

Condition Min.

Max.

24.4 ns

(7)

(9)

2.9 ms

—

( ½ t

)–2 ( ½ t

)+2

—

(10)

(11)

—

— ns ns ns

Unit

— ns ns ns ns

Doc ID 15399 Rev 9 127/157

Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7

Table 48.

DSPI timing

(1),(2)

(continued)

# Symbol C Characteristic Condition Min.

Max.

Unit

10 t t

SUI

Master (MTFE = 0)

D Slave

Master (MTFE = 1, CPHA =

(12)

Data Setup Time for Inputs

DDEH

=4.5–5.5 V

DDEH

=3–3.6 V

DDEH

=4.5–5.5 V

Master (MTFE = 1, CPHA = 1)

DDEH

=3–3.6 V

Data Hold Time for Inputs

D Master (MTFE = 0)

D Slave

Master (MTFE = 1,

CPHA = 0)

(12)

D Master (MTFE = 1, CPHA = 1)

23.5

-4

—

— ns ns

-4 —

11 t

SUO

Master (MTFE = 0)

Slave

D Master (MTFE = 1, CPHA = 0)

Data Valid (after SCK edge)

DDEH

=4.5–5.5 V

DDEH

=3–3.6 V

DDEH

=4.5–5.5 V

DDEH

=3–3.6 V

—

6.3

21 ns

DDEH

=4.5–5.5 V

Master (MTFE = 1, CPHA = 1)

DDEH

=3–3.6 V

Data Hold Time for Outputs

Master (MTFE = 0)

DDEH

=4.5–5.5 V

DDEH

=3 –3.6 V

D Slave

D Master (MTFE = 1, CPHA = 0)

—

–5

–7.5

6.3

—

12 t

CC 5.5

—

Master (MTFE = 1, CPHA = 1)

DDEH

=4.5–5.5 V

DDEH

=3–3.6 V

–5

–7.5

—

All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on medium-speed pads. DSPI signals using slow pads have an additional delay based on the slew rate. DSPI timing is specified at V

DDEH

4.5 to 5.5 V, T

= T

L to T

, and C

= 50 pF with SRC = 0b11.

= 3 to 3.6 V and V

DDEH

Data is verified at f

SYS

= 102 MHz and 153 MHz (100 MHz and 150 MHz + 2% frequency modulation).

128/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics

The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated based on two SPC564A80 devices communicating over a DSPI link.

The actual minimum SCK cycle time is limited by pad performance.

For DSPI channels using LVDS output operation, up to 40 MHz SCK cycle time is supported. For non-LVDS output, maximum SCK frequency is 20 MHz. Appropriate clock division must be applied.

The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].

Timing met when pcssck = 3(01), and cssck =2 (0000).

The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].

Timing met when ASC = 2 (0000), and PASC = 3 (01).

10. Timing met when pcssck = 3.

11. Timing met when ASC = 3.

12. This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10.

2 3

PCSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

SIN

First Data

SOUT First Data

Data

Last Data

Note: Refer to

Table 48

for the numbers.

Figure 23.

DSPI classic SPI timing — master, CPHA = 0

Doc ID 15399 Rev 9 129/157

Electrical characteristics

PCSx

SPC564A74L7, SPC564A80B4, SPC564A80L7

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

SIN

SOUT

First Data Data

Data First Data

Note: Refer to

Table 48

for the numbers.

Last Data

Figure 24.

DSPI classic SPI timing — master, CPHA = 1

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

SOUT

SIN

First Data

Data

Last Data

Note: Refer to Table 48 for the numbers.

130/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7

Figure 25.

DSPI classic SPI timing — slave, CPHA = 0

Electrical characteristics

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

SOUT

SIN

First Data

Note: Refer to

Table 48

for the numbers.

Data

Last Data

Figure 26.

DSPI classic SPI timing — slave, CPHA = 1

PCSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

9 10

SIN

Data Last Data

SOUT

First Data

First Data Data

Last Data

Note: Refer to Table 48 for the numbers.

Doc ID 15399 Rev 9 131/157

Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7

Figure 27.

DSPI modified transfer format timing — master, CPHA = 0

PCSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

SIN

SOUT

First Data

Data

Note: Refer to Table 48 for the numbers.

Last Data

Figure 28.

DSPI modified transfer format timing — master, CPHA = 1

132/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

SOUT

First Data

Data

11 12

Last Data

Last Data SIN

Note: Refer to

Table 48

for the numbers.

Electrical characteristics

Figure 29.

DSPI modified transfer format timing — slave, CPHA =0

Doc ID 15399 Rev 9 133/157

Electrical characteristics

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

SOUT First Data

First Data SIN

Note: Refer to

Table 48 for the numbers.

Data

SPC564A74L7, SPC564A80B4, SPC564A80L7

Last Data

Figure 30.

DSPI modified transfer format timing — slave, CPHA =1

PCSS

PCSx

Note: Refer to Table 48 for the numbers.

Figure 31.

DSPI PCS strobe (PCSS) timing

134/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Electrical characteristics

3.17.9 eQADC SSI timing

Table 49.

eQADC SSI timing characteristics (pads at 3.3 V or at 5.0 V)

(1)

CLOAD = 25 pF on all outputs. Pad drive strength set to maximum.

# Symbol C Rating Min

3 t

FCKHT t t f

FCK

FCKLT

CC D FCK Frequency

(2), (3)

1/17

CC D FCK Period (t

FCK

= 1/ f

FCK

) 2

CC D Clock (FCK) High Time t

SYS_CLK



6.5

CC D Clock (FCK) Low Time t

SYS_CLK



6.5

-7.5

4 t

SDS_LL

CC D SDS Lead/Lag Time

5 t

SDO_LL

CC D SDO Lead/Lag Time -7.5

7 t t

DVFE

EQ _ SU

Data Valid from FCK Falling

Edge (t

FCKLT+ t

SDO_LL

) eQADC Data Setup Time

(Inputs)

Typ Max



9* t

SYS_CLK



6.5

8* t

SYS_CLK



6.5

7.5

Unit f

SYS_CLK t

SYS_CLK ns ns ns ns ns ns

8 t

EQ_HO

CC D eQADC Data Hold Time (Inputs) 1 ns

SS timing specified at f

SYS

SRC = 0b00.

= 80 MHz, V

= 1.14 V to 1.32 V, V

DDEH

= 4.5 V to 5.5 V, T

= T

to T

, and C

= 50 pF with

Maximum operating frequency is highly dependent on track delays, master pad delays, and slave pad delays.

FCK duty is not 50% when it is generated through the division of the system clock by an odd number.

FCK

SDS

4 4

SDO

External Device Data Sample at

FCK Falling Edge

SDI eQADC Data Sample at

FCK Rising Edge

Figure 32.

eQADC SSI timing

5 6

1st (MSB) 2nd

25th

26th

1st (MSB) 2nd 25th 26th

Doc ID 15399 Rev 9 135/157

Electrical characteristics SPC564A74L7, SPC564A80B4, SPC564A80L7

3.17.10 FlexCAN system clock source

Table 50.

FlexCAN engine system clock divider threshold

# Symbol Characteristic

1 F

CAN_TH

FlexCAN engine system clock threshold

Value

100

Unit

MHz

Table 51.

FlexCAN engine system clock divider

System Frequency Required SIU_SYSDIV[CAN_SRC] Value

<= F

CAN_TH

> F

CAN_TH

(1),(2)

(2),(3)

Divides system clock source for FlexCAN engine by 1.

System clock is only selected for FlexCAN when CAN_CR[CLK_SRC] = 1.

Divides system clock source for FlexCAN engine by 2.

136/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Packages

4 Packages

4.1 ECOPACK



In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

ECOPACK

is an ST trademark.

Doc ID 15399 Rev 9 137/157

Packages

4.2 Package mechanical data

4.2.1 LQFP176

SPC564A74L7, SPC564A80B4, SPC564A80L7

138/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Packages

Figure 33.

LQFP176 package mechanical drawing

Doc ID 15399 Rev 9 139/157

Packages SPC564A74L7, SPC564A80B4, SPC564A80L7

Table 52.

LQFP176 package mechanical data

DATABOOK MILLIMETERS

(1)

REF.

TYP MIN MAX TYP MIN MAX

E e

A2 b

(2)

ZE ccc

ANGLE

0.500

1.000

1.250

0.050

1.350

0.170

1.600

0.150

1.450

0.270

0.090

0.200

23.900

24.100

23.900

24.100

25.900

0.450

0 o

26.100

0.750

0.080

7 o

Controlling Dimension: MILLIMETER

L dimension is measured at gauge plane at 0.25 above the seating plane.

TYP

0.020

0.039

0.049

INCHES

MIN

0.002

0.053

0.007

0.004

0.941

1.020

0.018

MAX

0.063

0.057

0.011

0.008

0.949

1.028

0.030

0.003

7 o

140/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7

4.2.2 BGA208

Seating plane

Packages

D1 e F

1 3

2 4

7 9 11 13 15

8 10 12 14 16

A1 corner index area

(See note 1) b (208 balls) eee M fff M

C A B

Bottom view

The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug.

A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional.

Table 53.

LBGA208 mechanical data mm

Symbol

Min Typ

(2)

A1 0.30

A4 b

(3)

0.50

1.085

0.30

0.60

Max

1.70

0.80

0.70

Min

0.0118

0.0197

inches

(1)

Typ

0.0427

0.0118

0.0236

Max

0.0669

0.0315

0.0276

Doc ID 15399 Rev 9 141/157

Packages SPC564A74L7, SPC564A80B4, SPC564A80L7

Table 53.

LBGA208 mechanical data (continued) mm

Symbol

Min Typ Max inches

(1)

Min Typ Max

E1 e

16.80

17.00

15.00

17.00

15.00

1.00

17.20

0.6614

0.6693

0.5906

0.6693

0.5906

0.0394

0.6772

F ddd eee

(4) fff

(5)

1.00

0.20

0.25

0.0394

0.0079

0.0098

0.10

0.0039

Values in inches are converted from mm and rounded to 4 decimal digits.

LBGA stands for L ow profile B all G rid A rray.

—Low profile: The total profile height (Dim A) is measured from the seating plane to the top of the component

—The maximum total package height is calculated by the following methodology:

A2 Typ+A1 Typ +



(A1

+A3

+A4

tolerance values)

— Low profile: 1.20mm < A < 1.70mm

The typical ball diameter before mounting is 0.60mm.

The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.

For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.

The tolerance of position that controls the location of the balls within the matrix with respect to each other.

For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.

Each tolerance zone fff in the array is contained entirely in the respective zone eee above.

The axis of each ball must lie simultaneously in both tolerance zones.

4.2.3 PBGA324

142/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Packages

Figure 34.

PBGA324 package mechanical drawing

Doc ID 15399 Rev 9 143/157

Packages SPC564A74L7, SPC564A80B4, SPC564A80L7

Table 54.

PBGA324 package mechanical data mm inches

Symbol

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

(1),(2),(3)

A2 b

0.270

1.720

1.320

0.6000

23.00

21.00

23.000

1.620

0.350

1.720

0.400

1.320

0.600

1.820

0.450

0.550

22.80

22.800

0.650

23.200

0.550

22.900

23.000

21.000

23.000

0.650

23.100

E1 e f ddd

0.950

0.875

21.000

1.000

1.050

1.125

0.200

0.950

0.875

21.000

1.000

1.050

1.125

0.200

Max mounted height is 1.77mm.Based on 0.35mm ball pad diameter. Solder paste is 0.15mm thickness and 0.35mm diameter.

PBGA stands for Plastic Ball Grid Array.

The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1corner. Exact shape of each corner is optional.

144/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Ordering information

Table 55 shows the orderable part numbers for the SPC564A80 series.

Table 55.

Order codes

Order code Flash/SRAM Package

SPC564A74L7CFA

SPC564A74B2CFA

SPC564A74B4CFA

SPC564A80L7CFC

SPC564A80B2CFC

SPC564A80B4CFC

SPC564A80L7CFB

SPC564A80B2CFB

SPC564A80B4CFB

SPC564A80L7CFA

SPC564A80B2CFA

SPC564A80B4CFA

SPC564A80H1EFA

3 MB/160 KB

4 MB/192 KB

176LQFP

208LBGA

324PBGA

LQFP176

LBGA208

PBGA324

LQFP176

LBGA208

PBGA324

LQFP176

LBGA208

PBGA324

KGD

Speed

(MHz)

120

150

Doc ID 15399 Rev 9 145/157

Ordering information SPC564A74L7, SPC564A80B4, SPC564A80L7

Figure 35.

Product code structure

Example code:

SPC56

Product identifier

4 A

Core Family

Memory

Package

Temperature

Custom vers.

Max Freq.

Conditioning

Y = Tray

R = Tape and Reel

A = 150 MHz

B = 120 MHz

C = 80 MHz

F = Optional Flexray controller

B = –40 to 105 °C

C = –40 to 125 °C

B2 = LBGA208

B4 = PBGA324

L7 = LQFP176

H1 = Known Good Die

80 = 4 MB

74 = 3 MB

A = SPC564A80 family

4 = e200z4

SPC56 = Power Architecture in 90 nm

146/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7

6 Document revision history

Document revision history

Table 56.

Revision history

Date Revision

23-Feb-2009

09-Dec-2009

Changes

Initial release

Maximum device speed is 145 MHz (was 150 MHz)

16-entry Memory Protection Unit (MPU). Was incorrectly listed as 8-entry.

288-ball BGA package deleted

Feature details section added

Changes to signal summary table:

– Added ANY function to AN[10]

– Added ANW function to AN[8]

Changes to 208 ball BGA ballmap:

– A12 is AN12-SDS (was AN12)

– A15 is VRC33 (was VDD33)

– B12 is AN13-SDO (was AN13)

– C12 is AN14SDI (was AN14)

– C13 is AN15-FCK (was AN15)

– D1 is VRC33 (was VDD33)

– F13 is VDDEH6AB (was VDDEH6)

– H13 is GPIO99 (was PCSA3)

– J15 is GPIO98 (was PCSA2)

– K4 is now VDDEH1AB (was VDDEH1)

– N6 is now VRC33 (was VDD33)

– N9 is VDDEH4AB (was VDDEH4)

– N12 is now VRC33 (was VDD33)

– P6 is now NC

– T13 is VDDE5 (was NC)

Changes to 324 ball BGA ballmap:

– A6 is VDDA (was VDDA1)

– A7 is VSSA (was VSSA1)

– A15 is VSSA (was VSSA0)

– A16 is AN12_SDS (was AN12)

– A17 is MDO11_ETPUA29O (was MDO11)

– A18 is MDO10_ETPUA27O (was MDO10)

– A19 is MDO8_ETPUA21O (was MDO8)

– A21 is VRC33 (was VDD33)

– B1 is VRC33 (was VDD33)

– B15 is VSSA (was VSSA0)

– B16 is AN13_SDO (was AN13)

– B17 is MDO9_ETPUA25O (was MDO9)

– B18 is MDO7_ETPUA19O (was MDO7)

– B19 is MDO4_ETPUA2O (was MDO4)

– B22 is NIC (was VDDE7)

Doc ID 15399 Rev 9 147/157

Document revision history SPC564A74L7, SPC564A80B4, SPC564A80L7

Table 56.

Revision history (continued)

Date

09-Dec-2009

Revision

Changes

– C4 is VDD (was VDDEH1A)

– C15 is VDDA (was VDDA0)

– C16 is AN14_SDI (was AN14)

– C17 is MDO5_ETPUA4O (was MDO5)

– C21 is NIC1 (was VDDE7)

– D15 is VDDEH7 (was VDDEH9)

– D16 is AN15_FCK (was AN15)

– D17 is MDO6_ETPUA13O (was MDO6)

– D20 is NIC (was VDDE7)

– E19 is NIC (was VDDE7)

– E22 is NIC (was NC)

– F19 is NIC (was VDDE7)

– H4 is VDDEH1AB (was VDDEH1A)

– H19 is VDDEH6AB (was VDDEH10)

– J14 is NIC (was VDDE7)

– K19 is GPIO99 (was PCSA3)

– M9 is VDDE2 (was VDD2)

– M21 is GPIO98 (was PCSA2)

– M22 is VDDREG (was NC)

– N22 is NIC (was NC)

– P2 is ADDR17 (was ADD17)

– P4 is VRC33 (was VDD33)

– R3 is VDDE-EH (was VDDE2)

– T21 is VSS (was VRCVSS)

– T22 is VSS (was VSSPLL)

– U19 is VDDEH6AB (was VDDEH6A)

– W2 is VDDE-EH (was VDDE2)

– W7 is VRC33 (was VDD33)

– W14 is VDDEH4AB (was VDDEH4B)

– W21 is NIC (was VRC33)

– Y22 is VRC33 (was VDD33)

– AB22 is VSS (was VSSPLL)

Recommended operating characteristics for power transistor updated

Pad current specifications updated

LVDS pad specifications updated. SRC does not apply to common mode voltage.

Temperature sensor electrical characteristics added eQADC electrical characteristics updated with VGA gain specs

Pad AC specifications updated

Definition for RDY signal added to signal details

STBY

maximum is 5.5 V (was listed incorrectly as 6.0 V)

MAXA

maximum is 5 mA (was TBD)

Analog differential input functions added to AN0–AN7 in signal summary

148/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Document revision history

Table 56.

Revision history (continued)

Date

02-Apr-2010

Revision

Changes

Internal release.

Changes to Signal Properties table (changes apply to Revision 2 and later devices:

EBI changes:

– WE_BE[2] (A2) and CAL_WE_BE[2] (A3) signals added to CS[2] (PCR 2)

– WE_BE[3] (A2) and CAL_WE_BE[3] (A3) signals added to CS[3] (PCR 3)

Calibration bus changes:

– CAL_WE[2]/BE[2] (A2) signal added to CAL_CS[2] (PCR 338)

– CAL_WE[3]/BE[3] (A2) signal added to CAL_CS[3] (PCR 339)

– CAL_ALE (A1) added to CAL_ADDR[15] (PCR 340) eQADC changes:

– AN[8] and AN[38] pins swapped. AN[8] Is now on pins 9 (176-pin), B3 (208-ball) and

D6 (324-ball). AN[8] was on C5 (324-ball) on previous devices. AN[38] Is now on C5

(324-ball). AN[38] was on pins 9 (176-pin), B3 (208-ball) and D6 (324-ball) on previous devices.

– ANZ function added to AN11 pin

Reaction channels added to eTPU2:

– RCH0_A (A3) added to ETPU_A[14] (PCR 128)

– RCH0_B (A2) added to ETPU_A[20] (PCR 134)

– RCH0_C (A2) added to ETPU_A[21] (PCR 135)

– RCH1_A (A2) added to ETPU_A[15] (PCR 129)

– RCH1_B (A2) added to ETPU_A[9] (PCR 123)

– RCH1_C (A2) added to ETPU_A[10] (PCR 124)

– RCH2_A (A2) added to ETPU_A[16] (PCR 130)

– RCH3_A (A2) added to ETPU_A[17] (PCR 131

– RCH4_A (A2) added to ETPU_A[18] (PCR 132))

– RCH4_B (A2) added to ETPU_A[11] (PCR 125)

– RCH4_C (A2) added to ETPU_A[12] (PCR 126)

– RCH5_A (A2) added to ETPU_A[19] (PCR 133)

– RCH5_B (A2) added to ETPU_A[28] (PCR 142)

– RCH5_C (A2) added to ETPU_A[29] (PCR 143)

Reaction channels added to eMIOS:

– RCH2_B (A2) added to EMIOS[2] (PCR 181)

– RCH2_C (A2) added to EMIOS[4] (PCR 183)

– RCH3_B (A2) added to EMIOS[10] (PCR 189)

– RCH3_C (A2) added to EMIOS[11] (PCR 190)

Pad changes:

– ETPUA16 (PCR 130) has Medium (was Slow) pad

– ETPUA17 (PCR 131) has Medium (was Slow) pad

– ETPUA18 (PCR 132) has Medium (was Slow) pad

– ETPUA19 (PCR 133) has Medium (was Slow) pad

– ETPUA25 (PCR 139) has Slow+LVDS (was Medium+LVDS) pads

Doc ID 15399 Rev 9 149/157

Document revision history SPC564A74L7, SPC564A80B4, SPC564A80L7

Table 56.

Revision history (continued)

Date

02-Apr-2010

(cont)

Revision

(cont)

Changes

Signal Details table updated:

– Added eTPU2 reaction channels

– Changed IRQ[0:15] to two ranges, excluding IRQ6, which does not exist on this device

– Changed TCR_A to TCRCLKA (TCR_A is the pin name, not the signal name)

– Changed WE_BE[0:1] to WE_BE[0:3] (2 new signals added to Rev. 2). Also changed notation from “WE_BE[n]” to “WE[n]/BE[n]” to be consistent.

Changes to Power/ground segmentation table:

– ADDR[20:21] removed from VDDE2 segment; they are in VDDE-EH

– CAL_CS1 removed from VDDE12 segment (there is no CAL_CS1 on this device)

– CAL_EVTO and CAL_MCKO removed from VDDE12 segment. Those pins do not exist

– VDDE-VDDEH renamed to VDDE-EH

– EMIOS24 removed from VDDEH segment. That pin does not exist.

– ETPUA[0:9] added to VDDEH4 segment

– Renamed TCR_A in VDDEH4 segment to TCRCLKA.

– EXTAL and XTAL added to VDDEH6 segment

– AN15-FCK added to VDDEH7 segment

– GPIO98, GPIO99, GPIO206, GPIO207 and GPIO219 added to VDDEH7 segment.

– MSEO1 added to VDDEH7 segment

– Power segment VDDEH1A renamed to VDDEH1

Changes to 176-pin package pinout:

– Changed pin 9 from AN38 to AN8.

– Added note that pin 96 (VSS) should be tied low.

Changes to 208-ball package ballmap:

– Changed ball B3 from AN38 to AN8.

– Added note that ball N13 (VSS) should be tied low.

324-ball package ballmap updated for Rev. 2 silicon

– Renamed VDDA (A6) to VDDA0

– Renamed VSSA (A7) to VSSA0

– AN8 was on ball C5; it is now on D6

– AN38 was on ball D6; it is now on C5

– Renamed VSSA (A15) to VSSA1

– Renamed VDDA (C15) to VDDA1

– Rename VSSA (B15) to VSSA1

BGA288 package is no longer offered

Changes to features list:

– Correction: there are 6 reaction channels (was noted as 5)

– Development Trigger Semaphore (DTS) added to features list and feature details

– FlexRay module now has 128 message buffers (was 64) and ECC support

Added note after JTAG pin AC electrical characteristics table detailing JTAG EVTI and

RDY signal clocking with TCK. This affects debuggers.

150/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Document revision history

Table 56.

Revision history (continued)

Date

02-Apr-2010

(cont)

01-Oct-2010

Revision

(cont)

Changes

Added information to AC timings section:

– New section added: Reset and configuration pin timing

– New section added: External interrupt timing (IRQ pin)

– New section added: eTPU timing

– Added Nexus debug port operating frequency table to Nexus timings section

– Added external bus interface maximum operating frequency table and calibration bus interface maximum operation frequency table

– Added FlexCAN system clock source section

Changes to Power management control (PMC) and power on reset (POR) electrical specifications:

– Max value for parameter 2 (vddreg) is 5.25 V (was 5.5 V)

Updated “Core voltage regulator controller external components preferred configuration” diagram.

Changes to DC electrical specifications table:

– Slew rate on power supply pins (system requirement) changed to 25 V/ms (was

50 V/ms)

Throughout the document the maximum frequency is now 150 MHz (was 145 MHz)

Changes to DC electrical specifications:

– Parameter classifications added

– V

DDREG

max value changed to 5.25 V (was 5.5 V)

– V

OH_LS

min value changed to 2.0 V (was 2.7 V) with a load current of 0.5 mA

– V

OL_LS

max value changed to 0.6 V (was 0.2*V

DDEH

) with load current of 2 mA

– V

INDC

min value changed to V

SSA

-0.3 (was V

SSA

-1.0)

– V

INDC

max value changed to V

DDA

+0.3 (was V

DDA

+1.0)

Added new section: Configuring SRAM wait states

– VRCCTL external circuit updated.

Updates to Nexus timings:

– t

MDOV

max value changed to 0.35 (was 0.2)

– t

MSEOV

max value changed to 0.35 (was 0.2)

– t

EVTOV

max value changed to 0.35 (was 0.2)

Updates to DC electrical specifications:

– V

STBY

min value changed to 0.95 V (was 0.9 V)

– V

STBY

has two ranges—for regulated mode and unregulated mode

Correction to PLLMRFM electrical specifications:

– V

DDPLL

range is from 1.08 V to 3.6 V (was 3.0 V to 3.6 V.

Updates to pad AC specifications:

– Specs with drive load = 200 pF deleted. DSC (drive strength control) values range from 10 – 50 pF.

– I/O pad average I

DDE

specifications updated (fast pad specs only)

– I/O pad V

RC33

average I

DDE

specifications (fast pad specs only)

Updates to Reset and configuration pin timings:

– Footnote added: RESET pulse width is measured from 50% of the falling edge to

50% of the rising edge.

– Timings are specified at V

= 1.14 V to 1.32 V (was 1.08 V to 1.32 V).

Doc ID 15399 Rev 9 151/157

Document revision history SPC564A74L7, SPC564A80B4, SPC564A80L7

Table 56.

Revision history (continued)

Date

01-Oct-2010

(cont)

10-Feb-2011

Revision

(cont)

Changes

Updates to EBI timings:

– Note added to t

AAI

: When CAL_TS is used as CAL_ALE the hold time is 1 ns instead of 1.5 ns.

– Correction: maximum calibration bus interface operating frequency is 66 MHz for all port configurations.

– VDDE range in footnote 1 corrected to read, “External Bus and Calibration bus timing specified at f

SYS

= 150 MHz and 100 MHz, VDD = 1.14 V to 1.32 V,

VDDE = 3 V to 3.6 V (unless stated otherwise)” (VDDE range was 1.62 V to 3.6 V)

Correction to IEEE 1149.1 timings:

– SRC value in footnote 1 corrected to read, “JTAG timing specified at VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.5 V with multi-voltage pads programmed to Low-

Swing mode, TA = TL to TH, and CL = 30 pF with DSC = 0b10, SRC = 0b11.” (SRC value was 0b00)

Correction to External interrupt timing (IRQ pin) timings:

– Timings are specified at V

= 1.14 V to 1.32 V (was 1.08 V to 1.32 V).

Update to DSPI timings:

– Some of the timing parameters can vary depending on the value of V

DDE

. For these parameters, ranges are now defined for two ranges of V

DDE

Change in signal name notation for DSPI, CAN and SCI signals:

– DSPI:

PCS_x[n] is now DSPI_x_PCS[n]

SOUT_x is now DSPI_x_SOUT

SIN_x is now DSPI_x_SIN

SCK_x is now DSPI_x_SCK

– CAN:

CNTXx is now CAN_x_TX

CNRXx is now CAN_x_RX

– SCI:

RXDx is now SCI_x_RX

TXDx is now SCI_x_TX

Updates to DC electrical specifications:

– Slew rate on power supply pins specification changed to 25 V/ms (was 50 V/ms)

OH_LS min spec changed to 2.0 V at 0.5 mA (was 2.7 V at 0.5 mA)

Updated I/O pad current specifications

Updated I/O pad V

RC33

current specifications

Corrections to Nexus timing:

– Maximum Nexus debug port operating frequency is 40 MHz in all configurations

– To route Nexus to MDO, clear NPC_PCR[NEXCFG] (formerly this was documented as NPC_PCR[CAL]

– To route Nexus to CAL_MDO, set NPC_PCR[NEXCFG]=1 (formerly this was documented as NPC_PCR[CAL]

– Minor editorial updates.

– Re-organized the first few subsections of the “Overview” section.

– Added ECSM to the block diagram.

– Added information on the REACM, SIU, and ECS modules to the “Block summary” section.

152/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Document revision history

Table 56.

Revision history (continued)

Date

10-Feb-2011

(cont)

Revision

(cont)

Changes

– Added DATA[0:15] to V

DDE5

in the “signal properties” table.

– Updated VSTBY parameters in the “Power/ground segmentation” table.

– Updated the parameter symbols and classifications throughout the document.

– Updated footnote instances in the “Absolute maximum ratings“ table.

– Removed I

MAXA

footnote in the “Absolute Maximum Ratings” table.

– Updated the format of the “EMI (electromagnetic interference) characteristics” table.

– Removed the footnote on V

DDREG

in the “Power management control (PMC) and power on reset (POR) electrical specifications“ table.

– Updated values for Vbg, Idd3p3, Por3.3V_r, Por3.3V_f, Por5V_r, and Por5V_f in the

“PMC electrical characteristics” table.

– Updated “Bandgap reference supply voltage variation” in the “PMC Electrical

Characteristics” table.

– Removed the “VRC electrical specifications” table as it contained redundant information.

– Updated VCE

SAT

and V

BE in the “Recommended power transistors” operating characteristics” table.

– Updated V IH_LS in the “DC electrical specifications” table.

– Updated the V

OH_LS

min value in the “DC electrical specifications” table.

– Updated I

DDSTBY

and I

DDSTBY150

in the “DC electrical specifications” table.

– Updated the I

DDA

REF

DDREG

max value in the “DC electrical specifications” table.

– Updated I

ACT_F

, I

ACT_MV_PU

, I

ACT_MV_PD the “DC electrical specifications” table.

, R

PUPD5K

, R

PUPDMTCH

, and footnotes in

– Updated Medium pad type I

DD33

values in the “I/O pad V

RC33

average I

DDE specifications” table.

– Updated values for V

in the “DSPI LVDS pad specification“ table.

– Removed the footnotes from the “DSPI LVDS pad specifications“ table.

– Removed the redundant “XTAL Load Capacitance” parameter instance from the

“PLLMRFM electrical specifications” table.

– Updated footnotes in the “PLLMRFM electrical specifications” table.

– Updated values for OFFNC and GAINNC in the “eQADC conversion specifications

(operating)“ table.

– Added DIFF max

, DIFF max2

, DIFF max4

, and DIFF conversion specifications (operating)” table.

cmv

parameters to the “eQADC

– Added the maximum operating frequency values in the “Cutoff frequency for additional SRAM wait state” table.

– Updated multiple entries in the “APC, RWSC, WWSC settings vs. frequency of operation” table.

– Removed footnote in the “APC, RWSC, WWSC settings vs. frequency of operation” table.

– Updated the Typical values for T dwprogram

,, T pprogram

, and T

16kpperase

, and updated the Initial Max values for T

128kpperase

and T

256kpperase

in the “Flash program and erase specifications” table.

– Changed the voltage in the “Pad AC specifications” table title from 4.5 V to 5.0 V.

– Added the maximum LH/HL output delay values for pad type MultiV in the “Pad AC specifications (V

DDE

= 3.3 V)“ table.

Doc ID 15399 Rev 9 153/157

Document revision history SPC564A74L7, SPC564A80B4, SPC564A80L7

Table 56.

Revision history (continued)

Date Revision

03-Feb-2012 6

Changes

– Minor editorial changes.

– In

Section 1.4: SPC564A80 feature list , moved “24 unified channels” after “1 x

eMIOS”.

– In

Table 4 updated the following rows:

DSPI_D_SCK /GPIO [98] -Changed “-” to CS[2]

DSPI_D_SIN /GPIO[99] -Changed “-” to CS[3].

– In

Table 12

Column “Value” added conditional text.

– In

Table 21

made the following changes:

-For the value “VOL_S” parameter changed from “Slow/ medium/multi-voltage pad

I/O output low voltage” to “Slow/medium pad I/O output low voltage”.

-Added a new row for “IDDSTBY27”.

-For row “IDDSTBY(operating current 0.95 -1.2V)” added max value “100” and changed typ value from “125” to “35”.

-For row “I

DDSTBY

(operating current 2 - 5.5V)” added max value “110” and changed typ value from “135” to “45”.

-For symbol “I

DDSTBY 150

(operating current 0.95 -1.2V)” added max value “2000”, changed typ value from “1050” to “790”,C cell changed from “T” to “P” and for symbol “I

DDSTBY

(operating current 2 - 5.5V)” added max value “2000”, changed typ value from “1050” to “760”, C cell changed from “T” to “P”.

-Removed note 9 and note 10 (Characterization based capability) from symbol

“V

OL_HS

”

– Splitted

Table 28: eQADC conversion specifications (operating) into

Table 29: eQADC single ended conversion specifications (operating) and Table 30: eQADC differential ended conversion specifications (operating)

– In

Table 30: eQADC differential ended conversion specifications (operating) made

the following changes:

-Added the note of DIFF cmv

on all of the DIFF specs.

-Min value changed from (VRH-VRL)/2-5% to (VRH+VRL)/2-5 % and max value changed from (VRH-VRL)/2+5% to (VRH+VRL)/2+5%for DIFFcmv.

– In

Table 31: Cutoff frequency for additional SRAM wait state made the following

changes:

-Added note “Max frequencies including 2% PLL FM”.

-Max operating frequency changed from “96” to “98” and “150” to “153”.

– In

Section 3.13: Configuring SRAM wait states

, changed text from “SPC564A80 4M

Microcontroller Reference Manual “ to “device reference manual”.

– In

Table 32: APC, RWSC, WWSC settings vs. frequency of operation

- Added note for “Max Flash Operating Frequency(MHz).

- Changed values from 30, 60,120, 150 to 20,61,123, 153 respectively in Max Flash

Operating Frequency (MHz).

– In

Table 33: Flash program and erase specifications , added two parameter “T

psrt

” and “T esrt

”.

– In

Table 41: External Bus Interface maximum operating frequency

, replacedthe <= symbol in notes with



– Added note “Refer to table DSPI timing for the numbers” in all the figures under

Section 3.17.8: DSPI timing .

154/157 Doc ID 15399 Rev 9

SPC564A74L7, SPC564A80B4, SPC564A80L7 Document revision history

Table 56.

Revision history (continued)

Date

03-Feb-2012

(cont)

07-Mar-2012

21-Mar-2012

Revision

(cont)

Changes

– Added

Table 17: SPC564A80 External network specification

– Updated

Figure 8: Core voltage regulator controller external components preferred configuration .

– Changed External Network Parameter Ce min value to “3*2.35 F+5 F” from



Table 17: SPC564A80 External network specification .

– Changed Trans. Line (differential Zo) unit to



from W in Table 25: DSPI LVDS pad specification

– Update table footnotes in

Table 21: DC electrical specifications

– Minor editorial changes.

– In

Section 1.4, “SPC564A80 feature list

, moved “24 unified channels” after “1 x eMIOS”.

– In

Table 4,“SPC564A80 signal properties”

/Column “Name” updated the following rows:

DSPI_D_SCK /GPIO [98] -Changed “-” to CS[2]

DSPI_D_SIN /GPIO[99] -Changed “-” to CS[3].

– In

Table 12,“Thermal characteristics for 324-pin PBGA” / Column “Value” added

conditional text.

– In

Table 21,“DC electrical specifications”

made the following changes:

-For the value “V

OL_S

” parameter changed from “Slow/ medium/multi-voltage pad

I/O output low voltage” to “Slow/medium pad I/O output low voltage”.

-Added a new row for “I

DDSTBY27

”.

-For row “I

DDSTBY

(operating current 0.95 -1.2V)” added max value “100” and changed typ value from “125” to “35”.

-For row “I

DDSTBY

(operating current 2 - 5.5V)” added max value “110” and changed typ value from “135” to “45”.

-For symbol “I

DDSTBY 150

(operating current 0.95 -1.2V)” added max value “2000”, changed typ value from “1050” to “790”,C cell changed from “T” to “P” and for symbol “I

DDSTBY

(operating current 2 - 5.5V)” added max value “2000”, changed typ value from “1050” to “760”, C cell changed from “T” to “P”.

-Removed note 9 and note 10 (Characterization based capability) from symbol

“V

OL_HS

”

– Splitted

Table 28,“eQADC conversion specifications (operating)”

into

Table 29,“eQADC single ended conversion specifications (operating)” and

Table 30,“eQADC differential ended conversion specifications (operating)”

– In

Table 30 ,“eQADC differential ended conversion specifications (operating)” made

the following changes:

-Added the note of DIFF cmv

on all of the DIFF specs.

-Min value changed from (VRH-VRL)/2-5% to (VRH+VRL)/2-5 % and max value changed from (VRH-VRL)/2+5 % to (VRH+VRL)/2+5 %for DIFFcmv.

– In

Table 31 ,“Cutoff frequency for additional SRAM wait state” made the following

changes:

-Added note “Max frequencies including 2% PLL FM”.

-Max operating frequency changed from “96” to “98” and “150” to “153”.

– In Section 3.13, “Configuring SRAM wait states , changed text from “SPC564A80 4M

Microcontroller Reference Manual “ to “device reference manual”.

Doc ID 15399 Rev 9 155/157

Document revision history SPC564A74L7, SPC564A80B4, SPC564A80L7

Table 56.

Revision history (continued)

Date

21-Mar-2012

Revision

(cont.)

Changes

– In

Table 32,“APC, RWSC, WWSC settings vs. frequency of operation

”

- Added note for “Max Flash Operating Frequency(MHz).

- Changed values from 30, 60,120, 150 to 20,61,123, 153 respectively in Max Flash

Operating Frequency (MHz).

– In

Table 33

,“Flash program and erase specifications”

dded two parameter “T psrt

” and “T esrt

”.

– In

Table 41,“External Bus Interface maximum operating frequency” , replacedthe <=

symbol in notes with



– Added note “Refer to table DSPI timing for the numbers” in all the figures under

Section 3.17.8, “DSPI timing

In Table 55 , changed LBGA208 to MAPBGA and changed all packages to 123XXXX

format.

– Added

Table 17,“SPC564A80 External network specification” .

– Updated

Figure 8

18-Sep-2013 9



Table 17,“SPC564A80 External network specification”

Changed Trans. Line (differential Zo) unit to



from W in Table 25,“DSPI LVDS pad specification” .

– Updated Disclaimer.

156/157 Doc ID 15399 Rev 9

SPC564A74B4, SPC564A74L7, SPC564A80B4, SPC564A80L7

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Doc ID 15399 Rev 9 157/157

32-bit MCU family built on the embedded Power Architecture

®

Features

Contents

List of tables

List of figures

1 Introduction

1.2 Description

1.4

SPC564A80 feature list

Periodic interrupt timer (PIT)

System timer module (STM)

1.6 SPC564A80 series architecture

LEGEND

2

Pinout and signal description

3.4 EMI (electromagnetic interference) characteristics

3.5 Electrostatic discharge (ESD) characteristics

3.6 Power management control (PMC) and power on reset (POR) electrical specifications

MCU

3.7 Power up/down sequencing

3.8 DC electrical specifications

3.9 I/O pad current specifications

3.11 Temperature sensor electrical characteristics

3.12 eQADC electrical characteristics

3.13 Configuring SRAM wait states

3.14 Platform flash controller electrical characteristics

3.15 Flash memory electrical characteristics

4 Packages

4.1 ECOPACK

4.2 Package mechanical data

6 Document revision history

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